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soc/intel/skl/graphics: Implement panel setup

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Logs from Linux' i915 suggest that not even the FSP/GOP takes proper
care of this. The sequence is mostly the same as on older platforms,
with a slightly different configuration of the backlight PWM.

We light the panel up with 50% PWM duty cycle. This often results in
an already rather high perceived brightness, but shouldn't be too
blinding.

Change-Id: I762a77c8df023a4c14af502af5edfeeb961da1ae
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30246
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This commit is contained in:
Nico Huber
2018-12-16 02:39:28 +01:00
parent 5d2e1d8023
commit 1a65017a50
2 changed files with 76 additions and 0 deletions
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12
src/soc/intel/skylake/chip.h
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@@ -48,6 +48,18 @@ struct soc_intel_skylake_config {
/* Common struct containing soc config data required by common code */
struct soc_intel_common_config common_soc_config;
/* IGD panel configuration */
unsigned int gpu_pp_up_delay_ms;
unsigned int gpu_pp_down_delay_ms;
unsigned int gpu_pp_cycle_delay_ms;
unsigned int gpu_pp_backlight_on_delay_ms;
unsigned int gpu_pp_backlight_off_delay_ms;
unsigned int gpu_pch_backlight_pwm_hz;
enum {
GPU_BACKLIGHT_POLARITY_HIGH = 0,
GPU_BACKLIGHT_POLARITY_LOW,
} gpu_pch_backlight_polarity;
/*
* Interrupt Routing configuration
* If bit7 is 1, the interrupt is disabled.