Add support for the Intel Eagle Heights development board.
Signed-off-by: Thomas Jourdan <thomas.jourdan@gmail.com> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4392 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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committed by
Myles Watson
parent
6c96517a13
commit
1a692d8176
@@ -57,3 +57,7 @@
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#define DEVPRES1_D0F1 (1 << 5)
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#define DEVPRES1_D8F0 (1 << 1)
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#define MSCFG 0XF6
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/* DRC */
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#define DRC_NOECC_MODE (0 << 20)
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#define DRC_72BIT_ECC (1 << 20)
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@@ -963,8 +963,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
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{{ 0x00000120, 0x00000000, 0x00000032, 0x00000010}},
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/* FSB 167 */
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{{ 0x00154320, 0x00000000, 0x00065432, 0x00010000}},
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/* N/A */
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{{ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff}},
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/* FSB 200 DIMM 400 */
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{{ 0x00000001, 0x00000000, 0x00000001, 0x00000000}},
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};
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static const u32 dqs_data[] = {
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@@ -1220,5 +1220,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
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pci_write_config16(ctrl->f0, MCHSCRB, data16);
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/* The memory is now setup, use it */
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#if CONFIG_USE_DCACHE_RAM == 0
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cache_lbmem(MTRR_TYPE_WRBACK);
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#endif
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}
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20
src/northbridge/intel/i3100/reset_test.c
Normal file
20
src/northbridge/intel/i3100/reset_test.c
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@@ -0,0 +1,20 @@
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/* Convert to C by yhlu */
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#define MCH_DRC 0x7c
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#define DRC_DONE (1 << 29)
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/* If I have already booted once skip a bunch of initialization */
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/* To see if I have already booted I check to see if memory
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* has been enabled.
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*/
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static int bios_reset_detected(void)
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{
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uint32_t dword;
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dword = pci_read_config32(PCI_DEV(0, 0, 0), MCH_DRC);
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if( (dword & DRC_DONE) != 0 ) {
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return 1;
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}
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return 0;
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}
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