Add support for the Intel Eagle Heights development board.

Signed-off-by: Thomas Jourdan <thomas.jourdan@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4392 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Thomas Jourdan
2009-07-01 17:01:17 +00:00
committed by Myles Watson
parent 6c96517a13
commit 1a692d8176
31 changed files with 3926 additions and 36 deletions

View File

@@ -57,3 +57,7 @@
#define DEVPRES1_D0F1 (1 << 5)
#define DEVPRES1_D8F0 (1 << 1)
#define MSCFG 0XF6
/* DRC */
#define DRC_NOECC_MODE (0 << 20)
#define DRC_72BIT_ECC (1 << 20)

View File

@@ -963,8 +963,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
{{ 0x00000120, 0x00000000, 0x00000032, 0x00000010}},
/* FSB 167 */
{{ 0x00154320, 0x00000000, 0x00065432, 0x00010000}},
/* N/A */
{{ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff}},
/* FSB 200 DIMM 400 */
{{ 0x00000001, 0x00000000, 0x00000001, 0x00000000}},
};
static const u32 dqs_data[] = {
@@ -1220,5 +1220,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
pci_write_config16(ctrl->f0, MCHSCRB, data16);
/* The memory is now setup, use it */
#if CONFIG_USE_DCACHE_RAM == 0
cache_lbmem(MTRR_TYPE_WRBACK);
#endif
}

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@@ -0,0 +1,20 @@
/* Convert to C by yhlu */
#define MCH_DRC 0x7c
#define DRC_DONE (1 << 29)
/* If I have already booted once skip a bunch of initialization */
/* To see if I have already booted I check to see if memory
* has been enabled.
*/
static int bios_reset_detected(void)
{
uint32_t dword;
dword = pci_read_config32(PCI_DEV(0, 0, 0), MCH_DRC);
if( (dword & DRC_DONE) != 0 ) {
return 1;
}
return 0;
}