Add support for the Intel Eagle Heights development board.
Signed-off-by: Thomas Jourdan <thomas.jourdan@gmail.com> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4392 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Thomas Jourdan
committed by
Myles Watson
Myles Watson
parent
6c96517a13
commit
1a692d8176
@@ -26,3 +26,4 @@ driver i3100_ehci.o
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driver i3100_smbus.o
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driver i3100_pci.o
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object i3100_reset.o
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object i3100_pciexp_portb.o
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35
src/southbridge/intel/i3100/cmos_failover.c
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35
src/southbridge/intel/i3100/cmos_failover.c
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@@ -0,0 +1,35 @@
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/*
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* This file is part of the coreboot project.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include "i3100.h"
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#define RTC_FAILED (1 <<2)
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#define GEN_PMCON_3 0xa4
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static void check_cmos_failed(void)
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{
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u8 byte;
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byte = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3);
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if (byte & RTC_FAILED) {
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// clear bit 1 and bit 2
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byte = cmos_read(RTC_BOOT_BYTE);
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byte &= 0x0c;
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byte |= CONFIG_MAX_REBOOT_CNT << 4;
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cmos_write(byte, RTC_BOOT_BYTE);
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}
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}
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@@ -35,12 +35,18 @@
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#define GPIO_BAR 0x48
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#define RCBA 0xf0
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#define SERIRQ_CNTL 0x64
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#define GEN_PMCON_1 0xA0
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#define GEN_PMCON_2 0xA2
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#define GEN_PMCON_3 0xA4
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#define NMI_OFF 0
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#define MAINBOARD_POWER_OFF 0
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#define MAINBOARD_POWER_ON 1
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#ifndef MAINBOARD_POWER_ON_AFTER_FAIL
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#define MAINBOARD_POWER_ON_AFTER_FAIL MAINBOARD_POWER_ON
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#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
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#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON
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#endif
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#define ALL (0xff << 24)
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@@ -93,11 +99,10 @@ static void setup_ioapic(device_t dev)
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}
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/* Put the APIC in virtual wire mode */
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l[0] = 0x10;
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l[0] = 0x12;
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l[4] = ENABLED | TRIGGER_EDGE | POLARITY_HIGH | PHYSICAL_DEST | ExtINT;
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}
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#define SERIRQ_CNTL 0x64
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static void i3100_enable_serial_irqs(device_t dev)
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{
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/* set packet length and toggle silent mode bit */
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@@ -257,6 +262,68 @@ static void i3100_pirq_init(device_t dev)
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}
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}
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static void i3100_power_options(device_t dev) {
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u8 reg8;
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u16 reg16;
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int pwr_on = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
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int nmi_option;
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/* Which state do we want to goto after g3 (power restored)?
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* 0 == S0 Full On
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* 1 == S5 Soft Off
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*/
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get_option(&pwr_on, "power_on_after_fail");
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reg8 = pci_read_config8(dev, GEN_PMCON_3);
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reg8 &= 0xfe;
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if (pwr_on) {
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reg8 &= ~1;
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} else {
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reg8 |= 1;
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}
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/* avoid #S4 assertions */
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reg8 |= (3 << 4);
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/* minimum asssertion is 1 to 2 RTCCLK */
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reg8 &= ~(1 << 3);
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pci_write_config8(dev, GEN_PMCON_3, reg8);
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printk_info("set power %s after power fail\n", pwr_on ? "on" : "off");
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/* Set up NMI on errors. */
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reg8 = inb(0x61);
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/* Higher Nibble must be 0 */
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reg8 &= 0x0f;
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/* IOCHK# NMI Enable */
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reg8 &= ~(1 << 3);
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/* PCI SERR# Enable */
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// reg8 &= ~(1 << 2);
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/* PCI SERR# Disable for now */
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reg8 |= (1 << 2);
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outb(reg8, 0x61);
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reg8 = inb(0x70);
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nmi_option = NMI_OFF;
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get_option(&nmi_option, "nmi");
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if (nmi_option) {
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/* Set NMI. */
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printk_info ("NMI sources enabled.\n");
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reg8 &= ~(1 << 7);
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} else {
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/* Can't mask NMI from PCI-E and NMI_NOW */
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printk_info ("NMI sources disabled.\n");
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reg8 |= ( 1 << 7);
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}
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outb(reg8, 0x70);
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// Enable CPU_SLP# and Intel Speedstep, set SMI# rate down
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reg16 = pci_read_config16(dev, GEN_PMCON_1);
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reg16 &= ~((3 << 0) | (1 << 10));
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reg16 |= (1 << 3) | (1 << 5);
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/* CLKRUN_EN */
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// reg16 |= (1 << 2);
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pci_write_config16(dev, GEN_PMCON_1, reg16);
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// Set the board's GPI routing.
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// i82801gx_gpi_routing(dev);
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}
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static void i3100_gpio_init(device_t dev)
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{
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@@ -296,9 +363,6 @@ static void i3100_gpio_init(device_t dev)
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static void lpc_init(struct device *dev)
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{
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u8 byte;
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int pwr_on = MAINBOARD_POWER_ON_AFTER_FAIL;
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setup_ioapic(dev);
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/* Decode 0xffc00000 - 0xffffffff to fwh idsel 0 */
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@@ -306,18 +370,12 @@ static void lpc_init(struct device *dev)
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i3100_enable_serial_irqs(dev);
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get_option(&pwr_on, "power_on_after_fail");
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byte = pci_read_config8(dev, 0xa4);
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byte &= 0xfe;
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if (!pwr_on) {
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byte |= 1;
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}
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pci_write_config8(dev, 0xa4, byte);
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printk_info("set power %s after power fail\n", pwr_on ? "on" : "off");
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/* Set up the PIRQ */
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i3100_pirq_init(dev);
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/* Setup power options */
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i3100_power_options(dev);
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/* Set the state of the gpio lines */
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i3100_gpio_init(dev);
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94
src/southbridge/intel/i3100/i3100_pciexp_portb.c
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94
src/southbridge/intel/i3100/i3100_pciexp_portb.c
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@@ -0,0 +1,94 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2008 Arastra, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*
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*/
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/* This code is based on src/northbridge/intel/e7520/pciexp_porta.c */
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#include <console/console.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <device/pci_ops.h>
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#include <device/pciexp.h>
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#include <arch/io.h>
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#include "chip.h"
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#include <part/hard_reset.h>
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#define PCIE_LCTL 0x50
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#define PCIE_LSTS 0x52
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typedef struct northbridge_intel_i3100_config config_t;
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static void pcie_init(struct device *dev)
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{
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}
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static unsigned int pcie_scan_bridge(struct device *dev, unsigned int max)
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{
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u16 val;
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u16 ctl;
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int flag = 0;
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do {
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val = pci_read_config16(dev, PCIE_LSTS);
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printk_debug("pcie portb link status: %02x\n", val);
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if ((val & (1<<10)) && (!flag)) { /* training error */
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ctl = pci_read_config16(dev, PCIE_LCTL);
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pci_write_config16(dev, PCIE_LCTL, (ctl | (1<<5)));
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val = pci_read_config16(dev, PCIE_LSTS);
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printk_debug("pcie portb reset link status: %02x\n", val);
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flag=1;
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hard_reset();
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}
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} while (val & (3<<10));
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return pciexp_scan_bridge(dev, max);
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}
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static struct device_operations pcie_ops = {
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.read_resources = pci_bus_read_resources,
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.set_resources = pci_dev_set_resources,
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.enable_resources = pci_bus_enable_resources,
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.init = pcie_init,
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.scan_bus = pcie_scan_bridge,
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.reset_bus = pci_bus_reset,
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.ops_pci = 0,
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};
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static struct pci_driver pci_driver_0 __pci_driver = {
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.ops = &pcie_ops,
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.vendor = PCI_VENDOR_ID_INTEL,
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.device = PCI_DEVICE_ID_INTEL_3100_PCIE_PB0,
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};
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static struct pci_driver pci_driver_1 __pci_driver = {
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.ops = &pcie_ops,
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.vendor = PCI_VENDOR_ID_INTEL,
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.device = PCI_DEVICE_ID_INTEL_3100_PCIE_PB1,
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};
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static struct pci_driver pci_driver_2 __pci_driver = {
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.ops = &pcie_ops,
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.vendor = PCI_VENDOR_ID_INTEL,
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.device = PCI_DEVICE_ID_INTEL_3100_PCIE_PB2,
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};
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static struct pci_driver pci_driver_3 __pci_driver = {
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.ops = &pcie_ops,
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.vendor = PCI_VENDOR_ID_INTEL,
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.device = PCI_DEVICE_ID_INTEL_3100_PCIE_PB3,
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};
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@@ -27,32 +27,76 @@
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#include <device/pci_ops.h>
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#include "i3100.h"
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#define SATA_CMD 0x04
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#define SATA_PI 0x09
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#define SATA_PTIM 0x40
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#define SATA_STIM 0x42
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#define SATA_D1TIM 0x44
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#define SATA_SYNCC 0x48
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#define SATA_SYNCTIM 0x4A
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#define SATA_IIOC 0x54
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#define SATA_MAP 0x90
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#define SATA_PCS 0x91
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#define SATA_ACR0 0xA8
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#define SATA_ACR1 0xAC
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#define SATA_ATC 0xC0
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#define SATA_ATS 0xC4
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#define SATA_SP 0xD0
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typedef struct southbridge_intel_i3100_config config_t;
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static void sata_init(struct device *dev)
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{
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u8 ahci;
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/* Get the chip configuration */
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ahci = (pci_read_config8(dev, SATA_MAP) >> 6) & 0x03;
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/* Enable SATA devices */
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printk_info("SATA init (%s mode)\n", ahci ? "AHCI" : "Legacy");
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printk_debug("SATA init\n");
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/* SATA configuration */
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pci_write_config8(dev, 0x04, 0x07);
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pci_write_config8(dev, 0x09, 0x8f);
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if(ahci) {
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/* AHCI mode */
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pci_write_config8(dev, SATA_MAP, (1 << 6) | (0 << 0));
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/* Set timings */
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pci_write_config16(dev, 0x40, 0x0a307);
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pci_write_config16(dev, 0x42, 0x0a307);
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/* Enable ports */
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pci_write_config8(dev, SATA_PCS, 0x03);
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pci_write_config8(dev, SATA_PCS + 1, 0x0F);
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/* Sync DMA */
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pci_write_config16(dev, 0x48, 0x000f);
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pci_write_config16(dev, 0x4a, 0x1111);
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/* Setup timings */
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pci_write_config16(dev, SATA_PTIM, 0x8000);
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pci_write_config16(dev, SATA_STIM, 0x8000);
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/* Fast ATA */
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pci_write_config16(dev, 0x54, 0x1000);
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/* Select IDE mode */
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pci_write_config8(dev, 0x90, 0x00);
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/* Enable ports 0-3 */
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pci_write_config8(dev, 0x92, 0x0f);
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/* Synchronous DMA */
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pci_write_config8(dev, SATA_SYNCC, 0);
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pci_write_config16(dev, SATA_SYNCTIM, 0);
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/* IDE I/O configuration */
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pci_write_config32(dev, SATA_IIOC, 0);
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} else {
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/* SATA configuration */
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pci_write_config8(dev, SATA_CMD, 0x07);
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pci_write_config8(dev, SATA_PI, 0x8f);
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/* Set timings */
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pci_write_config16(dev, SATA_PTIM, 0x0a307);
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pci_write_config16(dev, SATA_STIM, 0x0a307);
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/* Sync DMA */
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pci_write_config8(dev, SATA_SYNCC, 0x0f);
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pci_write_config16(dev, SATA_SYNCTIM, 0x1111);
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/* Fast ATA */
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pci_write_config16(dev, SATA_IIOC, 0x1000);
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/* Select IDE mode */
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pci_write_config8(dev, SATA_MAP, 0x00);
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/* Enable ports 0-3 */
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pci_write_config8(dev, SATA_PCS + 1, 0x0f);
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}
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printk_debug("SATA Enabled\n");
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}
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Block a user