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nb/intel/haswell/gma: Support boards that have DDI E connected

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On an ASRock H81M-HDS neither libgfxinit, nor Linux, is able to
initialise the display when lanes are not configured to be shared
between DDI A and DDI E.

Intel's reference manual [1] states that the decision to share lanes
between DDI A and DDI E is "based on board configuration". Hence, add a
new field to the devicetree that boards can set. All existing Haswell
boards have this unset, thus taking a value of 0, so there is no change
to existing behaviour.

[1]: Intel Open Source Graphics Programmer's Reference Manual (PRM)
     Volume 2c: Command Reference: Registers (Haswell)
     https://01.org/linuxgraphics/documentation/hardware-specification-prms/2013-intel-core-processor-family

Change-Id: I6f7832293215d2b53e31b0a5c985e6098eb72f1b
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/29385
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Tristan Corrick
2018-10-31 02:27:29 +13:00
committed by Nico Huber
parent fdf907e440
commit 1a73eb08e7
2 changed files with 6 additions and 1 deletions
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2
src/northbridge/intel/haswell/chip.h
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@@ -40,6 +40,8 @@ struct northbridge_intel_haswell_config {
u32 gpu_cpu_backlight; /* CPU Backlight PWM value */
u32 gpu_pch_backlight; /* PCH Backlight PWM value */
bool gpu_ddi_e_connected;
struct i915_gpu_controller_info gfx;
};

5
src/northbridge/intel/haswell/gma.c
View File

@@ -368,7 +368,10 @@ static void gma_setup_panel(struct device *dev)
bit 4: DDI A supports 4 lanes and DDI E is not used
bit 7: DDI buffer is idle
*/
gtt_write(DDI_BUF_CTL_A, DDI_BUF_IS_IDLE | DDI_A_4_LANES | DDI_INIT_DISPLAY_DETECTED);
reg32 = DDI_BUF_IS_IDLE | DDI_INIT_DISPLAY_DETECTED;
if (!conf->gpu_ddi_e_connected)
reg32 |= DDI_A_4_LANES;
gtt_write(DDI_BUF_CTL_A, reg32);
/* Set FDI registers - is this required? */
gtt_write(_FDI_RXA_MISC, 0x00200090);