From 1a832d0c0678bef87e5f98cdee359cb305bcde8c Mon Sep 17 00:00:00 2001
From: Harsha B R <harsha.b.r@intel.com>
Date: Sat, 4 Feb 2023 18:27:39 +0530
Subject: [PATCH] mb/intel/mtlrvp: Enable ACPI support for Type-C ports

This patch adds ACPI support for Type-C ports.

BUG=b:224325352
BRANCH=None
Test=Able to build and boot MTLRVP. Verify SSDT for the corresponding
entry,
\_SB.PCI0.PMC.MUX.CON0 under Device (CON0)
\_SB.PCI0.PMC.MUX.CON1 under Device (CON1)
\_SB.PCI0.PMC.MUX.CON2 under Device (CON2)
\_SB.PCI0.PMC.MUX.CON3 under Device (CON3)

Signed-off-by: Harsha B R <harsha.b.r@intel.com>
Change-Id: I8e5957ca7a6c542a64d79b2ceefbed79ead15811
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72789
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Usha P <usha.p@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
---
 src/mainboard/intel/mtlrvp/Kconfig            |  1 +
 src/mainboard/intel/mtlrvp/dsdt.asl           |  1 +
 .../variants/mtlrvp_p_ext_ec/overridetree.cb  | 30 +++++++++++++++++++
 3 files changed, 32 insertions(+)

diff --git a/src/mainboard/intel/mtlrvp/Kconfig b/src/mainboard/intel/mtlrvp/Kconfig
index 945aa2e51c..3468ac9651 100644
--- a/src/mainboard/intel/mtlrvp/Kconfig
+++ b/src/mainboard/intel/mtlrvp/Kconfig
@@ -13,6 +13,7 @@ config BOARD_INTEL_MTLRVP_P
 
 config BOARD_INTEL_MTLRVP_P_EXT_EC
 	select BOARD_INTEL_MTLRVP_COMMON
+	select DRIVERS_INTEL_PMC
 
 if BOARD_INTEL_MTLRVP_COMMON
 
diff --git a/src/mainboard/intel/mtlrvp/dsdt.asl b/src/mainboard/intel/mtlrvp/dsdt.asl
index d253617dcb..a367bbbb69 100644
--- a/src/mainboard/intel/mtlrvp/dsdt.asl
+++ b/src/mainboard/intel/mtlrvp/dsdt.asl
@@ -22,6 +22,7 @@ DefinitionBlock(
 		{
 			#include <soc/intel/common/block/acpi/acpi/northbridge.asl>
 			#include <soc/intel/meteorlake/acpi/southbridge.asl>
+			#include <soc/intel/meteorlake/acpi/tcss.asl>
 		}
 	}
 
diff --git a/src/mainboard/intel/mtlrvp/variants/mtlrvp_p_ext_ec/overridetree.cb b/src/mainboard/intel/mtlrvp/variants/mtlrvp_p_ext_ec/overridetree.cb
index b08d7cabe4..f51f18b564 100644
--- a/src/mainboard/intel/mtlrvp/variants/mtlrvp_p_ext_ec/overridetree.cb
+++ b/src/mainboard/intel/mtlrvp/variants/mtlrvp_p_ext_ec/overridetree.cb
@@ -3,8 +3,38 @@ chip soc/intel/meteorlake
 	device domain 0 on
 		device ref soc_espi on
 			chip ec/google/chromeec
+				use conn0 as mux_conn[0]
+				use conn1 as mux_conn[1]
+				use conn2 as mux_conn[2]
+				use conn3 as mux_conn[3]
 				device pnp 0c09.0 on end
 			end
 		end
+		device ref pmc hidden
+			chip drivers/intel/pmc_mux
+				device generic 0 on
+					chip drivers/intel/pmc_mux/conn
+						use usb2_port1 as usb2_port
+						use tcss_usb3_port1 as usb3_port
+						device generic 0 alias conn0 on end
+					end
+					chip drivers/intel/pmc_mux/conn
+						use usb2_port2 as usb2_port
+						use tcss_usb3_port2 as usb3_port
+						device generic 1 alias conn1 on end
+					end
+					chip drivers/intel/pmc_mux/conn
+						use usb2_port3 as usb2_port
+						use tcss_usb3_port3 as usb3_port
+						device generic 2 alias conn2 on end
+					end
+					chip drivers/intel/pmc_mux/conn
+						use usb2_port4 as usb2_port
+						use tcss_usb3_port4 as usb3_port
+						device generic 3 alias conn3 on end
+					end
+				end
+			end
+		end
 	end
 end