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AGESA: Trace execution with AGESA_EVENTLOG()

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Change-Id: I5601ed92ca808603b0a9edad118ca54aa168aceb
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7604
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
This commit is contained in:
Kyösti Mälkki
2014-10-21 14:19:04 +03:00
parent b139b5efcc
commit 1aa35c6f6c
39 changed files with 247 additions and 300 deletions
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6
src/cpu/amd/agesa/agesawrapper_s3.c
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@@ -59,7 +59,7 @@ AGESA_STATUS agesawrapper_amdinitresume(void)
status = AmdInitResume((AMD_RESUME_PARAMS *) AmdParamStruct.NewStructPtr); status = AmdInitResume((AMD_RESUME_PARAMS *) AmdParamStruct.NewStructPtr);
AGESA_EVENTLOG_(status, AmdParamStruct.StdHeader.HeapStatus); AGESA_EVENTLOG(status, &AmdParamStruct.StdHeader);
AmdReleaseStruct(&AmdParamStruct); AmdReleaseStruct(&AmdParamStruct);
return status; return status;
@@ -93,7 +93,7 @@ AGESA_STATUS agesawrapper_amds3laterestore(void)
(void **)&AmdS3LateParamsPtr->S3DataBlock.VolatileStorage); (void **)&AmdS3LateParamsPtr->S3DataBlock.VolatileStorage);
status = AmdS3LateRestore(AmdS3LateParamsPtr); status = AmdS3LateRestore(AmdS3LateParamsPtr);
AGESA_EVENTLOG_(status, AmdInterfaceParams.StdHeader.HeapStatus); AGESA_EVENTLOG(status, &AmdInterfaceParams.StdHeader);
ASSERT(status == AGESA_SUCCESS); ASSERT(status == AGESA_SUCCESS);
return status; return status;
@@ -122,7 +122,7 @@ AGESA_STATUS agesawrapper_amdS3Save(void)
AmdS3SaveParamsPtr->StdHeader = AmdInterfaceParams.StdHeader; AmdS3SaveParamsPtr->StdHeader = AmdInterfaceParams.StdHeader;
status = AmdS3Save(AmdS3SaveParamsPtr); status = AmdS3Save(AmdS3SaveParamsPtr);
AGESA_EVENTLOG_(status, AmdInterfaceParams.StdHeader.HeapStatus); AGESA_EVENTLOG(status, &AmdInterfaceParams.StdHeader);
ASSERT(status == AGESA_SUCCESS); ASSERT(status == AGESA_SUCCESS);
S3DataType = S3DataTypeNonVolatile; S3DataType = S3DataTypeNonVolatile;

5
src/cpu/amd/agesa/amd_late_init.c
View File

@@ -21,7 +21,6 @@
#include <bootstate.h> #include <bootstate.h>
#include <northbridge/amd/agesa/agesawrapper.h> #include <northbridge/amd/agesa/agesawrapper.h>
#include <northbridge/amd/agesa/agesawrapper_call.h>
#if CONFIG_AMD_SB_CIMX #if CONFIG_AMD_SB_CIMX
#include <sb_cimx.h> #include <sb_cimx.h>
@@ -32,7 +31,7 @@ static void agesawrapper_post_device(void *unused)
if (acpi_is_wakeup_s3()) if (acpi_is_wakeup_s3())
return; return;
AGESAWRAPPER(amdinitlate); agesawrapper_amdinitlate();
#if CONFIG_AMD_SB_CIMX #if CONFIG_AMD_SB_CIMX
sb_Late_Post(); sb_Late_Post();
@@ -40,7 +39,7 @@ static void agesawrapper_post_device(void *unused)
if (!acpi_s3_resume_allowed()) if (!acpi_s3_resume_allowed())
return; return;
AGESAWRAPPER(amdS3Save); agesawrapper_amdS3Save();
} }
BOOT_STATE_INIT_ENTRIES(agesa_bscb) = { BOOT_STATE_INIT_ENTRIES(agesa_bscb) = {

11
src/mainboard/amd/dinar/romstage.c
View File

@@ -30,7 +30,6 @@
#include <console/loglevel.h> #include <console/loglevel.h>
#include <cpu/amd/car.h> #include <cpu/amd/car.h>
#include <northbridge/amd/agesa/agesawrapper.h> #include <northbridge/amd/agesa/agesawrapper.h>
#include <northbridge/amd/agesa/agesawrapper_call.h>
#include "cpu/x86/bist.h" #include "cpu/x86/bist.h"
#include <superio/smsc/sch4037/sch4037.h> #include <superio/smsc/sch4037/sch4037.h>
#include <superio/smsc/sio1036/sio1036.h> #include <superio/smsc/sio1036/sio1036.h>
@@ -64,7 +63,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
} }
post_code(0x32); post_code(0x32);
AGESAWRAPPER(amdinitmmio); agesawrapper_amdinitmmio();
/* Halt if there was a built in self test failure */ /* Halt if there was a built in self test failure */
post_code(0x33); post_code(0x33);
@@ -81,10 +80,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
} }
post_code(0x35); post_code(0x35);
AGESAWRAPPER(amdinitreset); agesawrapper_amdinitreset();
post_code(0x36); post_code(0x36);
AGESAWRAPPER(amdinitearly); agesawrapper_amdinitearly();
post_code(0x37); post_code(0x37);
nb_Poweron_Init(); nb_Poweron_Init();
@@ -93,10 +92,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x39); post_code(0x39);
AGESAWRAPPER(amdinitpost); agesawrapper_amdinitpost();
post_code(0x40); post_code(0x40);
AGESAWRAPPER(amdinitenv); agesawrapper_amdinitenv();
post_code(0x43); post_code(0x43);

11
src/mainboard/amd/inagua/romstage.c
View File

@@ -32,7 +32,6 @@
#include <cpu/x86/mtrr.h> #include <cpu/x86/mtrr.h>
#include <cpu/amd/car.h> #include <cpu/amd/car.h>
#include <northbridge/amd/agesa/agesawrapper.h> #include <northbridge/amd/agesa/agesawrapper.h>
#include <northbridge/amd/agesa/agesawrapper_call.h>
#include "cpu/x86/bist.h" #include "cpu/x86/bist.h"
#include <superio/smsc/kbc1100/kbc1100.h> #include <superio/smsc/kbc1100/kbc1100.h>
#include "cpu/x86/lapic.h" #include "cpu/x86/lapic.h"
@@ -75,19 +74,19 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
post_code(0x35); post_code(0x35);
AGESAWRAPPER(amdinitmmio); agesawrapper_amdinitmmio();
post_code(0x37); post_code(0x37);
AGESAWRAPPER(amdinitreset); agesawrapper_amdinitreset();
post_code(0x39); post_code(0x39);
AGESAWRAPPER(amdinitearly); agesawrapper_amdinitearly();
post_code(0x40); post_code(0x40);
AGESAWRAPPER(amdinitpost); agesawrapper_amdinitpost();
post_code(0x41); post_code(0x41);
AGESAWRAPPER(amdinitenv); agesawrapper_amdinitenv();
post_code(0x50); post_code(0x50);
copy_and_run(); copy_and_run();

15
src/mainboard/amd/olivehill/romstage.c
View File

@@ -31,7 +31,6 @@
#include <console/loglevel.h> #include <console/loglevel.h>
#include <cpu/amd/car.h> #include <cpu/amd/car.h>
#include <northbridge/amd/agesa/agesawrapper.h> #include <northbridge/amd/agesa/agesawrapper.h>
#include <northbridge/amd/agesa/agesawrapper_call.h>
#include "cpu/x86/bist.h" #include "cpu/x86/bist.h"
#include "cpu/x86/lapic.h" #include "cpu/x86/lapic.h"
#include "southbridge/amd/agesa/hudson/hudson.h" #include "southbridge/amd/agesa/hudson/hudson.h"
@@ -51,7 +50,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
outb(0xD2, 0xcd6); outb(0xD2, 0xcd6);
outb(0x00, 0xcd7); outb(0x00, 0xcd7);
AGESAWRAPPER_PRE_CONSOLE(amdinitmmio); agesawrapper_amdinitmmio();
/* Set LPC decode enables. */ /* Set LPC decode enables. */
pci_devfn_t dev = PCI_DEV(0, 0x14, 3); pci_devfn_t dev = PCI_DEV(0, 0x14, 3);
@@ -81,29 +80,29 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
val = inb(0xcd6); val = inb(0xcd6);
post_code(0x37); post_code(0x37);
AGESAWRAPPER(amdinitreset); agesawrapper_amdinitreset();
post_code(0x38); post_code(0x38);
printk(BIOS_DEBUG, "Got past yangtze_early_setup\n"); printk(BIOS_DEBUG, "Got past yangtze_early_setup\n");
post_code(0x39); post_code(0x39);
AGESAWRAPPER(amdinitearly); agesawrapper_amdinitearly();
int s3resume = acpi_is_wakeup_early() && acpi_s3_resume_allowed(); int s3resume = acpi_is_wakeup_early() && acpi_s3_resume_allowed();
if (!s3resume) { if (!s3resume) {
post_code(0x40); post_code(0x40);
AGESAWRAPPER(amdinitpost); agesawrapper_amdinitpost();
post_code(0x41); post_code(0x41);
AGESAWRAPPER(amdinitenv); agesawrapper_amdinitenv();
/* TODO: Disable cache is not ok. */ /* TODO: Disable cache is not ok. */
disable_cache_as_ram(); disable_cache_as_ram();
} else { /* S3 detect */ } else { /* S3 detect */
printk(BIOS_INFO, "S3 detected\n"); printk(BIOS_INFO, "S3 detected\n");
post_code(0x60); post_code(0x60);
AGESAWRAPPER(amdinitresume); agesawrapper_amdinitresume();
agesawrapper_amdinitcpuio(); agesawrapper_amdinitcpuio();
AGESAWRAPPER(amds3laterestore); agesawrapper_amds3laterestore();
post_code(0x61); post_code(0x61);
prepare_for_resume(); prepare_for_resume();

15
src/mainboard/amd/parmer/romstage.c
View File

@@ -31,7 +31,6 @@
#include <console/loglevel.h> #include <console/loglevel.h>
#include <cpu/amd/car.h> #include <cpu/amd/car.h>
#include <northbridge/amd/agesa/agesawrapper.h> #include <northbridge/amd/agesa/agesawrapper.h>
#include <northbridge/amd/agesa/agesawrapper_call.h>
#include "cpu/x86/bist.h" #include "cpu/x86/bist.h"
#include "cpu/x86/lapic.h" #include "cpu/x86/lapic.h"
#include "southbridge/amd/agesa/hudson/hudson.h" #include "southbridge/amd/agesa/hudson/hudson.h"
@@ -43,7 +42,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{ {
u32 val; u32 val;
AGESAWRAPPER_PRE_CONSOLE(amdinitmmio); agesawrapper_amdinitmmio();
/* Set LPC decode enables. */ /* Set LPC decode enables. */
pci_devfn_t dev = PCI_DEV(0, 0x14, 3); pci_devfn_t dev = PCI_DEV(0, 0x14, 3);
@@ -68,25 +67,25 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
post_code(0x37); post_code(0x37);
AGESAWRAPPER(amdinitreset); agesawrapper_amdinitreset();
post_code(0x39); post_code(0x39);
AGESAWRAPPER(amdinitearly); agesawrapper_amdinitearly();
int s3resume = acpi_is_wakeup_early() && acpi_s3_resume_allowed(); int s3resume = acpi_is_wakeup_early() && acpi_s3_resume_allowed();
if (!s3resume) { if (!s3resume) {
post_code(0x40); post_code(0x40);
AGESAWRAPPER(amdinitpost); agesawrapper_amdinitpost();
post_code(0x41); post_code(0x41);
AGESAWRAPPER(amdinitenv); agesawrapper_amdinitenv();
disable_cache_as_ram(); disable_cache_as_ram();
} else { /* S3 detect */ } else { /* S3 detect */
printk(BIOS_INFO, "S3 detected\n"); printk(BIOS_INFO, "S3 detected\n");
post_code(0x60); post_code(0x60);
AGESAWRAPPER(amdinitresume); agesawrapper_amdinitresume();
agesawrapper_amdinitcpuio(); agesawrapper_amdinitcpuio();
AGESAWRAPPER(amds3laterestore); agesawrapper_amds3laterestore();
post_code(0x61); post_code(0x61);
prepare_for_resume(); prepare_for_resume();

15
src/mainboard/amd/persimmon/romstage.c
View File

@@ -32,7 +32,6 @@
#include <cpu/x86/mtrr.h> #include <cpu/x86/mtrr.h>
#include <cpu/amd/car.h> #include <cpu/amd/car.h>
#include <northbridge/amd/agesa/agesawrapper.h> #include <northbridge/amd/agesa/agesawrapper.h>
#include <northbridge/amd/agesa/agesawrapper_call.h>
#include "cpu/x86/bist.h" #include "cpu/x86/bist.h"
#include <superio/fintek/common/fintek.h> #include <superio/fintek/common/fintek.h>
#include <superio/fintek/f81865f/f81865f.h> #include <superio/fintek/f81865f/f81865f.h>
@@ -80,29 +79,29 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
post_code(0x35); post_code(0x35);
AGESAWRAPPER(amdinitmmio); agesawrapper_amdinitmmio();
post_code(0x37); post_code(0x37);
AGESAWRAPPER(amdinitreset); agesawrapper_amdinitreset();
post_code(0x39); post_code(0x39);
AGESAWRAPPER(amdinitearly); agesawrapper_amdinitearly();
int s3resume = acpi_is_wakeup_early() && acpi_s3_resume_allowed(); int s3resume = acpi_is_wakeup_early() && acpi_s3_resume_allowed();
if (!s3resume) { if (!s3resume) {
post_code(0x40); post_code(0x40);
AGESAWRAPPER(amdinitpost); agesawrapper_amdinitpost();
post_code(0x42); post_code(0x42);
AGESAWRAPPER(amdinitenv); agesawrapper_amdinitenv();
} else { /* S3 detect */ } else { /* S3 detect */
printk(BIOS_INFO, "S3 detected\n"); printk(BIOS_INFO, "S3 detected\n");
post_code(0x60); post_code(0x60);
AGESAWRAPPER(amdinitresume); agesawrapper_amdinitresume();
AGESAWRAPPER(amds3laterestore); agesawrapper_amds3laterestore();
post_code(0x61); post_code(0x61);
prepare_for_resume(); prepare_for_resume();

11
src/mainboard/amd/south_station/romstage.c
View File

@@ -32,7 +32,6 @@
#include <cpu/x86/mtrr.h> #include <cpu/x86/mtrr.h>
#include <cpu/amd/car.h> #include <cpu/amd/car.h>
#include <northbridge/amd/agesa/agesawrapper.h> #include <northbridge/amd/agesa/agesawrapper.h>
#include <northbridge/amd/agesa/agesawrapper_call.h>
#include "cpu/x86/bist.h" #include "cpu/x86/bist.h"
#include <superio/fintek/common/fintek.h> #include <superio/fintek/common/fintek.h>
#include <superio/fintek/f81865f/f81865f.h> #include <superio/fintek/f81865f/f81865f.h>
@@ -75,19 +74,19 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
post_code(0x35); post_code(0x35);
AGESAWRAPPER(amdinitmmio); agesawrapper_amdinitmmio();
post_code(0x37); post_code(0x37);
AGESAWRAPPER(amdinitreset); agesawrapper_amdinitreset();
post_code(0x39); post_code(0x39);
AGESAWRAPPER(amdinitearly); agesawrapper_amdinitearly();
post_code(0x40); post_code(0x40);
AGESAWRAPPER(amdinitpost); agesawrapper_amdinitpost();
post_code(0x41); post_code(0x41);
AGESAWRAPPER(amdinitenv); agesawrapper_amdinitenv();
post_code(0x50); post_code(0x50);
copy_and_run(); copy_and_run();

15
src/mainboard/amd/thatcher/romstage.c
View File

@@ -31,7 +31,6 @@
#include <console/loglevel.h> #include <console/loglevel.h>
#include <cpu/amd/car.h> #include <cpu/amd/car.h>
#include <northbridge/amd/agesa/agesawrapper.h> #include <northbridge/amd/agesa/agesawrapper.h>
#include <northbridge/amd/agesa/agesawrapper_call.h>
#include "cpu/x86/bist.h" #include "cpu/x86/bist.h"
#include "cpu/x86/lapic.h" #include "cpu/x86/lapic.h"
#include "southbridge/amd/agesa/hudson/hudson.h" #include "southbridge/amd/agesa/hudson/hudson.h"
@@ -48,7 +47,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
u8 byte; u8 byte;
pci_devfn_t dev; pci_devfn_t dev;
AGESAWRAPPER_PRE_CONSOLE(amdinitmmio); agesawrapper_amdinitmmio();
/* Set LPC decode enables. */ /* Set LPC decode enables. */
dev = PCI_DEV(0, 0x14, 3); dev = PCI_DEV(0, 0x14, 3);
@@ -82,25 +81,25 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
post_code(0x37); post_code(0x37);
AGESAWRAPPER(amdinitreset); agesawrapper_amdinitreset();
post_code(0x39); post_code(0x39);
AGESAWRAPPER(amdinitearly); agesawrapper_amdinitearly();
int s3resume = acpi_is_wakeup_early() && acpi_s3_resume_allowed(); int s3resume = acpi_is_wakeup_early() && acpi_s3_resume_allowed();
if (!s3resume) { if (!s3resume) {
post_code(0x40); post_code(0x40);
AGESAWRAPPER(amdinitpost); agesawrapper_amdinitpost();
post_code(0x41); post_code(0x41);
AGESAWRAPPER(amdinitenv); agesawrapper_amdinitenv();
disable_cache_as_ram(); disable_cache_as_ram();
} else { /* S3 detect */ } else { /* S3 detect */
printk(BIOS_INFO, "S3 detected\n"); printk(BIOS_INFO, "S3 detected\n");
post_code(0x60); post_code(0x60);
AGESAWRAPPER(amdinitresume); agesawrapper_amdinitresume();
agesawrapper_amdinitcpuio(); agesawrapper_amdinitcpuio();
AGESAWRAPPER(amds3laterestore); agesawrapper_amds3laterestore();
post_code(0x61); post_code(0x61);
prepare_for_resume(); prepare_for_resume();

11
src/mainboard/amd/torpedo/romstage.c
View File

@@ -29,7 +29,6 @@
#include <console/loglevel.h> #include <console/loglevel.h>
#include <cpu/amd/car.h> #include <cpu/amd/car.h>
#include <northbridge/amd/agesa/agesawrapper.h> #include <northbridge/amd/agesa/agesawrapper.h>
#include <northbridge/amd/agesa/agesawrapper_call.h>
#include "cpu/x86/bist.h" #include "cpu/x86/bist.h"
#include <superio/smsc/kbc1100/kbc1100.h> #include <superio/smsc/kbc1100/kbc1100.h>
#include "cpu/x86/lapic.h" #include "cpu/x86/lapic.h"
@@ -45,7 +44,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
u32 val; u32 val;
post_code(0x35); post_code(0x35);
AGESAWRAPPER_PRE_CONSOLE(amdinitmmio); agesawrapper_amdinitmmio();
if (!cpu_init_detectedx && boot_cpu()) { if (!cpu_init_detectedx && boot_cpu()) {
post_code(0x30); post_code(0x30);
@@ -72,13 +71,13 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
post_code(0x36); post_code(0x36);
AGESAWRAPPER(amdinitreset); agesawrapper_amdinitreset();
post_code(0x37); post_code(0x37);
AGESAWRAPPER(amdinitearly); agesawrapper_amdinitearly();
post_code(0x38); post_code(0x38);
AGESAWRAPPER(amdinitpost); agesawrapper_amdinitpost();
post_code(0x39); post_code(0x39);
printk(BIOS_DEBUG, "sb_before_pci_init "); printk(BIOS_DEBUG, "sb_before_pci_init ");
@@ -86,7 +85,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
printk(BIOS_DEBUG, "passed.\n"); printk(BIOS_DEBUG, "passed.\n");
post_code(0x40); post_code(0x40);
AGESAWRAPPER(amdinitenv); agesawrapper_amdinitenv();
post_code(0x43); post_code(0x43);
copy_and_run(); copy_and_run();

11
src/mainboard/amd/union_station/romstage.c
View File

@@ -32,7 +32,6 @@
#include <cpu/x86/mtrr.h> #include <cpu/x86/mtrr.h>
#include <cpu/amd/car.h> #include <cpu/amd/car.h>
#include <northbridge/amd/agesa/agesawrapper.h> #include <northbridge/amd/agesa/agesawrapper.h>
#include <northbridge/amd/agesa/agesawrapper_call.h>
#include "cpu/x86/bist.h" #include "cpu/x86/bist.h"
#include "cpu/x86/lapic.h" #include "cpu/x86/lapic.h"
#include <sb_cimx.h> #include <sb_cimx.h>
@@ -69,19 +68,19 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
post_code(0x35); post_code(0x35);
AGESAWRAPPER(amdinitmmio); agesawrapper_amdinitmmio();
post_code(0x37); post_code(0x37);
AGESAWRAPPER(amdinitreset); agesawrapper_amdinitreset();
post_code(0x39); post_code(0x39);
AGESAWRAPPER(amdinitearly); agesawrapper_amdinitearly();
post_code(0x40); post_code(0x40);
AGESAWRAPPER(amdinitpost); agesawrapper_amdinitpost();
post_code(0x41); post_code(0x41);
AGESAWRAPPER(amdinitenv); agesawrapper_amdinitenv();
post_code(0x50); post_code(0x50);
copy_and_run(); copy_and_run();

11
src/mainboard/asrock/e350m1/romstage.c
View File

@@ -31,7 +31,6 @@
#include <cpu/x86/mtrr.h> #include <cpu/x86/mtrr.h>
#include <cpu/amd/car.h> #include <cpu/amd/car.h>
#include <northbridge/amd/agesa/agesawrapper.h> #include <northbridge/amd/agesa/agesawrapper.h>
#include <northbridge/amd/agesa/agesawrapper_call.h>
#include "cpu/x86/bist.h" #include "cpu/x86/bist.h"
#include <superio/nuvoton/common/nuvoton.h> #include <superio/nuvoton/common/nuvoton.h>
#include <superio/nuvoton/nct5572d/nct5572d.h> #include <superio/nuvoton/nct5572d/nct5572d.h>
@@ -75,19 +74,19 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
post_code(0x35); post_code(0x35);
AGESAWRAPPER(amdinitmmio); agesawrapper_amdinitmmio();
post_code(0x37); post_code(0x37);
AGESAWRAPPER(amdinitreset); agesawrapper_amdinitreset();
post_code(0x39); post_code(0x39);
AGESAWRAPPER(amdinitearly); agesawrapper_amdinitearly();
post_code(0x40); post_code(0x40);
AGESAWRAPPER(amdinitpost); agesawrapper_amdinitpost();
post_code(0x41); post_code(0x41);
AGESAWRAPPER(amdinitenv); agesawrapper_amdinitenv();
post_code(0x50); post_code(0x50);
copy_and_run(); copy_and_run();

15
src/mainboard/asrock/imb-a180/romstage.c
View File

@@ -31,7 +31,6 @@
#include <console/loglevel.h> #include <console/loglevel.h>
#include <cpu/amd/car.h> #include <cpu/amd/car.h>
#include <northbridge/amd/agesa/agesawrapper.h> #include <northbridge/amd/agesa/agesawrapper.h>
#include <northbridge/amd/agesa/agesawrapper_call.h>
#include "cpu/x86/bist.h" #include "cpu/x86/bist.h"
#include "cpu/x86/lapic.h" #include "cpu/x86/lapic.h"
#include "southbridge/amd/agesa/hudson/hudson.h" #include "southbridge/amd/agesa/hudson/hudson.h"
@@ -56,7 +55,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
//outb(0xD2, 0xcd6); //outb(0xD2, 0xcd6);
//outb(0x00, 0xcd7); //outb(0x00, 0xcd7);
AGESAWRAPPER_PRE_CONSOLE(amdinitmmio); agesawrapper_amdinitmmio();
/* Set LPC decode enables. */ /* Set LPC decode enables. */
pci_devfn_t dev = PCI_DEV(0, 0x14, 3); pci_devfn_t dev = PCI_DEV(0, 0x14, 3);
@@ -105,29 +104,29 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
val = inb(0xcd6); val = inb(0xcd6);
post_code(0x37); post_code(0x37);
AGESAWRAPPER(amdinitreset); agesawrapper_amdinitreset();
post_code(0x38); post_code(0x38);
printk(BIOS_DEBUG, "Got past yangtze_early_setup\n"); printk(BIOS_DEBUG, "Got past yangtze_early_setup\n");
post_code(0x39); post_code(0x39);
AGESAWRAPPER(amdinitearly); agesawrapper_amdinitearly();
int s3resume = acpi_is_wakeup_early() && acpi_s3_resume_allowed(); int s3resume = acpi_is_wakeup_early() && acpi_s3_resume_allowed();
if (!s3resume) { if (!s3resume) {
post_code(0x40); post_code(0x40);
AGESAWRAPPER(amdinitpost); agesawrapper_amdinitpost();
post_code(0x41); post_code(0x41);
AGESAWRAPPER(amdinitenv); agesawrapper_amdinitenv();
/* TODO: Disable cache is not ok. */ /* TODO: Disable cache is not ok. */
disable_cache_as_ram(); disable_cache_as_ram();
} else { /* S3 detect */ } else { /* S3 detect */
printk(BIOS_INFO, "S3 detected\n"); printk(BIOS_INFO, "S3 detected\n");
post_code(0x60); post_code(0x60);
AGESAWRAPPER(amdinitresume); agesawrapper_amdinitresume();
agesawrapper_amdinitcpuio(); agesawrapper_amdinitcpuio();
AGESAWRAPPER(amds3laterestore); agesawrapper_amds3laterestore();
post_code(0x61); post_code(0x61);
prepare_for_resume(); prepare_for_resume();

15
src/mainboard/asus/f2a85-m/romstage.c
View File

@@ -19,7 +19,6 @@
*/ */
#include <northbridge/amd/agesa/agesawrapper.h> #include <northbridge/amd/agesa/agesawrapper.h>
#include <northbridge/amd/agesa/agesawrapper_call.h>
#include <arch/acpi.h> #include <arch/acpi.h>
#include <arch/cpu.h> #include <arch/cpu.h>
@@ -76,7 +75,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
hudson_lpc_port80(); hudson_lpc_port80();
#endif #endif
AGESAWRAPPER_PRE_CONSOLE(amdinitmmio); agesawrapper_amdinitmmio();
if (!cpu_init_detectedx && boot_cpu()) { if (!cpu_init_detectedx && boot_cpu()) {
@@ -128,24 +127,24 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
post_code(0x37); post_code(0x37);
AGESAWRAPPER(amdinitreset); agesawrapper_amdinitreset();
post_code(0x39); post_code(0x39);
AGESAWRAPPER(amdinitearly); agesawrapper_amdinitearly();
int s3resume = acpi_is_wakeup_early() && acpi_s3_resume_allowed(); int s3resume = acpi_is_wakeup_early() && acpi_s3_resume_allowed();
if (!s3resume) { if (!s3resume) {
post_code(0x40); post_code(0x40);
AGESAWRAPPER(amdinitpost); agesawrapper_amdinitpost();
post_code(0x41); post_code(0x41);
AGESAWRAPPER(amdinitenv); agesawrapper_amdinitenv();
disable_cache_as_ram(); disable_cache_as_ram();
} else { /* S3 detect */ } else { /* S3 detect */
printk(BIOS_INFO, "S3 detected\n"); printk(BIOS_INFO, "S3 detected\n");
post_code(0x60); post_code(0x60);
AGESAWRAPPER(amdinitresume); agesawrapper_amdinitresume();
agesawrapper_amdinitcpuio(); agesawrapper_amdinitcpuio();
AGESAWRAPPER(amds3laterestore); agesawrapper_amds3laterestore();
post_code(0x61); post_code(0x61);
prepare_for_resume(); prepare_for_resume();

15
src/mainboard/gizmosphere/gizmo/romstage.c
View File

@@ -33,7 +33,6 @@
#include <cpu/x86/mtrr.h> #include <cpu/x86/mtrr.h>
#include <cpu/amd/car.h> #include <cpu/amd/car.h>
#include <northbridge/amd/agesa/agesawrapper.h> #include <northbridge/amd/agesa/agesawrapper.h>
#include <northbridge/amd/agesa/agesawrapper_call.h>
#include "cpu/x86/bist.h" #include "cpu/x86/bist.h"
#include <cpu/x86/cache.h> #include <cpu/x86/cache.h>
#include <sb_cimx.h> #include <sb_cimx.h>
@@ -88,29 +87,29 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
post_code(0x35); post_code(0x35);
AGESAWRAPPER(amdinitmmio); agesawrapper_amdinitmmio();
post_code(0x37); post_code(0x37);
AGESAWRAPPER(amdinitreset); agesawrapper_amdinitreset();
post_code(0x39); post_code(0x39);
AGESAWRAPPER(amdinitearly); agesawrapper_amdinitearly();
int s3resume = acpi_is_wakeup_early() && acpi_s3_resume_allowed(); int s3resume = acpi_is_wakeup_early() && acpi_s3_resume_allowed();
if (!s3resume) { if (!s3resume) {
post_code(0x40); post_code(0x40);
AGESAWRAPPER(amdinitpost); agesawrapper_amdinitpost();
post_code(0x42); post_code(0x42);
AGESAWRAPPER(amdinitenv); agesawrapper_amdinitenv();
} else { /* S3 detect */ } else { /* S3 detect */
printk(BIOS_INFO, "S3 detected\n"); printk(BIOS_INFO, "S3 detected\n");
post_code(0x60); post_code(0x60);
AGESAWRAPPER(amdinitresume); agesawrapper_amdinitresume();
AGESAWRAPPER(amds3laterestore); agesawrapper_amds3laterestore();
post_code(0x61); post_code(0x61);
prepare_for_resume(); prepare_for_resume();

15
src/mainboard/hp/pavilion_m6_1035dx/romstage.c
View File

@@ -18,7 +18,6 @@
*/ */
#include <northbridge/amd/agesa/agesawrapper.h> #include <northbridge/amd/agesa/agesawrapper.h>
#include <northbridge/amd/agesa/agesawrapper_call.h>
#include <arch/acpi.h> #include <arch/acpi.h>
#include <arch/cpu.h> #include <arch/cpu.h>
@@ -39,7 +38,7 @@
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{ {
u32 val; u32 val;
AGESAWRAPPER_PRE_CONSOLE(amdinitmmio); agesawrapper_amdinitmmio();
/* Set LPC decode enables. */ /* Set LPC decode enables. */
pci_devfn_t dev = PCI_DEV(0, 0x14, 3); pci_devfn_t dev = PCI_DEV(0, 0x14, 3);
@@ -64,25 +63,25 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
post_code(0x37); post_code(0x37);
AGESAWRAPPER(amdinitreset); agesawrapper_amdinitreset();
post_code(0x39); post_code(0x39);
AGESAWRAPPER(amdinitearly); agesawrapper_amdinitearly();
int s3resume = acpi_is_wakeup_early() && acpi_s3_resume_allowed(); int s3resume = acpi_is_wakeup_early() && acpi_s3_resume_allowed();
if (!s3resume) { if (!s3resume) {
post_code(0x40); post_code(0x40);
AGESAWRAPPER(amdinitpost); agesawrapper_amdinitpost();
post_code(0x41); post_code(0x41);
AGESAWRAPPER(amdinitenv); agesawrapper_amdinitenv();
disable_cache_as_ram(); disable_cache_as_ram();
} else { /* S3 detect */ } else { /* S3 detect */
printk(BIOS_INFO, "S3 detected\n"); printk(BIOS_INFO, "S3 detected\n");
post_code(0x60); post_code(0x60);
AGESAWRAPPER(amdinitresume); agesawrapper_amdinitresume();
agesawrapper_amdinitcpuio(); agesawrapper_amdinitcpuio();
AGESAWRAPPER(amds3laterestore); agesawrapper_amds3laterestore();
post_code(0x61); post_code(0x61);
prepare_for_resume(); prepare_for_resume();

15
src/mainboard/jetway/nf81-t56n-lf/romstage.c
View File

@@ -19,7 +19,6 @@
*/ */
#include <northbridge/amd/agesa/agesawrapper.h> #include <northbridge/amd/agesa/agesawrapper.h>
#include <northbridge/amd/agesa/agesawrapper_call.h>
#include <arch/acpi.h> #include <arch/acpi.h>
#include <arch/cpu.h> #include <arch/cpu.h>
@@ -96,29 +95,29 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
post_code(0x35); post_code(0x35);
AGESAWRAPPER(amdinitmmio); agesawrapper_amdinitmmio();
post_code(0x37); post_code(0x37);
AGESAWRAPPER(amdinitreset); agesawrapper_amdinitreset();
post_code(0x39); post_code(0x39);
AGESAWRAPPER(amdinitearly); agesawrapper_amdinitearly();
int s3resume = acpi_is_wakeup_early() && acpi_s3_resume_allowed(); int s3resume = acpi_is_wakeup_early() && acpi_s3_resume_allowed();
if (!s3resume) { if (!s3resume) {
post_code(0x40); post_code(0x40);
AGESAWRAPPER(amdinitpost); agesawrapper_amdinitpost();
post_code(0x42); post_code(0x42);
AGESAWRAPPER(amdinitenv); agesawrapper_amdinitenv();
} else { /* S3 detect */ } else { /* S3 detect */
printk(BIOS_INFO, "S3 detected\n"); printk(BIOS_INFO, "S3 detected\n");
post_code(0x60); post_code(0x60);
AGESAWRAPPER(amdinitresume); agesawrapper_amdinitresume();
AGESAWRAPPER(amds3laterestore); agesawrapper_amds3laterestore();
post_code(0x61); post_code(0x61);
prepare_for_resume(); prepare_for_resume();

15
src/mainboard/lenovo/g505s/romstage.c
View File

@@ -18,7 +18,6 @@
*/ */
#include <northbridge/amd/agesa/agesawrapper.h> #include <northbridge/amd/agesa/agesawrapper.h>
#include <northbridge/amd/agesa/agesawrapper_call.h>
#include <arch/acpi.h> #include <arch/acpi.h>
#include <arch/cpu.h> #include <arch/cpu.h>
@@ -39,7 +38,7 @@
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{ {
u32 val; u32 val;
AGESAWRAPPER_PRE_CONSOLE(amdinitmmio); agesawrapper_amdinitmmio();
/* Set LPC decode enables. */ /* Set LPC decode enables. */
pci_devfn_t dev = PCI_DEV(0, 0x14, 3); pci_devfn_t dev = PCI_DEV(0, 0x14, 3);
@@ -64,25 +63,25 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
post_code(0x37); post_code(0x37);
AGESAWRAPPER(amdinitreset); agesawrapper_amdinitreset();
post_code(0x39); post_code(0x39);
AGESAWRAPPER(amdinitearly); agesawrapper_amdinitearly();
int s3resume = acpi_is_wakeup_early() && acpi_s3_resume_allowed(); int s3resume = acpi_is_wakeup_early() && acpi_s3_resume_allowed();
if (!s3resume) { if (!s3resume) {
post_code(0x40); post_code(0x40);
AGESAWRAPPER(amdinitpost); agesawrapper_amdinitpost();
post_code(0x41); post_code(0x41);
AGESAWRAPPER(amdinitenv); agesawrapper_amdinitenv();
disable_cache_as_ram(); disable_cache_as_ram();
} else { /* S3 detect */ } else { /* S3 detect */
printk(BIOS_INFO, "S3 detected\n"); printk(BIOS_INFO, "S3 detected\n");
post_code(0x60); post_code(0x60);
AGESAWRAPPER(amdinitresume); agesawrapper_amdinitresume();
agesawrapper_amdinitcpuio(); agesawrapper_amdinitcpuio();
AGESAWRAPPER(amds3laterestore); agesawrapper_amds3laterestore();
post_code(0x61); post_code(0x61);
prepare_for_resume(); prepare_for_resume();

15
src/mainboard/lippert/frontrunner-af/romstage.c
View File

@@ -32,7 +32,6 @@
#include <cpu/x86/mtrr.h> #include <cpu/x86/mtrr.h>
#include <cpu/amd/car.h> #include <cpu/amd/car.h>
#include <northbridge/amd/agesa/agesawrapper.h> #include <northbridge/amd/agesa/agesawrapper.h>
#include <northbridge/amd/agesa/agesawrapper_call.h>
#include "cpu/x86/bist.h" #include "cpu/x86/bist.h"
#include <superio/smsc/smscsuperio/smscsuperio.h> #include <superio/smsc/smscsuperio/smscsuperio.h>
#include "cpu/x86/lapic.h" #include "cpu/x86/lapic.h"
@@ -79,33 +78,33 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
post_code(0x35); post_code(0x35);
AGESAWRAPPER(amdinitmmio); agesawrapper_amdinitmmio();
post_code(0x37); post_code(0x37);
AGESAWRAPPER(amdinitreset); agesawrapper_amdinitreset();
post_code(0x39); post_code(0x39);
AGESAWRAPPER(amdinitearly); agesawrapper_amdinitearly();
int s3resume = acpi_is_wakeup_early() && acpi_s3_resume_allowed(); int s3resume = acpi_is_wakeup_early() && acpi_s3_resume_allowed();
if (!s3resume) { if (!s3resume) {
post_code(0x40); post_code(0x40);
/* Reboots with outb(3,0x92), outb(4,0xcf9) or triple-fault all /* Reboots with outb(3,0x92), outb(4,0xcf9) or triple-fault all
* hang, looks like DRAM re-init goes wrong, don't know why. */ * hang, looks like DRAM re-init goes wrong, don't know why. */
val = AGESAWRAPPER(amdinitpost); val = agesawrapper_amdinitpost();
if (val == 7) /* fatal, amdinitenv below is going to hang */ if (val == 7) /* fatal, amdinitenv below is going to hang */
outb(0x06, 0x0cf9); /* reset system harder instead */ outb(0x06, 0x0cf9); /* reset system harder instead */
post_code(0x42); post_code(0x42);
AGESAWRAPPER(amdinitenv); agesawrapper_amdinitenv();
} else { /* S3 detect */ } else { /* S3 detect */
printk(BIOS_INFO, "S3 detected\n"); printk(BIOS_INFO, "S3 detected\n");
post_code(0x60); post_code(0x60);
AGESAWRAPPER(amdinitresume); agesawrapper_amdinitresume();
AGESAWRAPPER(amds3laterestore); agesawrapper_amds3laterestore();
post_code(0x61); post_code(0x61);
prepare_for_resume(); prepare_for_resume();

15
src/mainboard/lippert/toucan-af/romstage.c
View File

@@ -32,7 +32,6 @@
#include <cpu/x86/mtrr.h> #include <cpu/x86/mtrr.h>
#include <cpu/amd/car.h> #include <cpu/amd/car.h>
#include <northbridge/amd/agesa/agesawrapper.h> #include <northbridge/amd/agesa/agesawrapper.h>
#include <northbridge/amd/agesa/agesawrapper_call.h>
#include "cpu/x86/bist.h" #include "cpu/x86/bist.h"
#include <superio/winbond/common/winbond.h> #include <superio/winbond/common/winbond.h>
#include <superio/winbond/w83627dhg/w83627dhg.h> #include <superio/winbond/w83627dhg/w83627dhg.h>
@@ -80,33 +79,33 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
post_code(0x35); post_code(0x35);
AGESAWRAPPER(amdinitmmio); agesawrapper_amdinitmmio();
post_code(0x37); post_code(0x37);
AGESAWRAPPER(amdinitreset); agesawrapper_amdinitreset();
post_code(0x39); post_code(0x39);
AGESAWRAPPER(amdinitearly); agesawrapper_amdinitearly();
int s3resume = acpi_is_wakeup_early() && acpi_s3_resume_allowed(); int s3resume = acpi_is_wakeup_early() && acpi_s3_resume_allowed();
if (!s3resume) { if (!s3resume) {
post_code(0x40); post_code(0x40);
/* Reboots with outb(3,0x92), outb(4,0xcf9) or triple-fault all /* Reboots with outb(3,0x92), outb(4,0xcf9) or triple-fault all
* hang, looks like DRAM re-init goes wrong, don't know why. */ * hang, looks like DRAM re-init goes wrong, don't know why. */
val = AGESAWRAPPER(amdinitpost); val = agesawrapper_amdinitpost();
if (val == 7) /* fatal, amdinitenv below is going to hang */ if (val == 7) /* fatal, amdinitenv below is going to hang */
outb(0x06, 0x0cf9); /* reset system harder instead */ outb(0x06, 0x0cf9); /* reset system harder instead */
post_code(0x42); post_code(0x42);
AGESAWRAPPER(amdinitenv); agesawrapper_amdinitenv();
} else { /* S3 detect */ } else { /* S3 detect */
printk(BIOS_INFO, "S3 detected\n"); printk(BIOS_INFO, "S3 detected\n");
post_code(0x60); post_code(0x60);
AGESAWRAPPER(amdinitresume); agesawrapper_amdinitresume();
AGESAWRAPPER(amds3laterestore); agesawrapper_amds3laterestore();
post_code(0x61); post_code(0x61);
prepare_for_resume(); prepare_for_resume();

11
src/mainboard/supermicro/h8qgi/romstage.c
View File

@@ -28,7 +28,6 @@
#include "cpu/x86/lapic.h" #include "cpu/x86/lapic.h"
#include <cpu/amd/car.h> #include <cpu/amd/car.h>
#include <northbridge/amd/agesa/agesawrapper.h> #include <northbridge/amd/agesa/agesawrapper.h>
#include <northbridge/amd/agesa/agesawrapper_call.h>
#include "northbridge/amd/agesa/family10/reset_test.h" #include "northbridge/amd/agesa/family10/reset_test.h"
#include <nb_cimx.h> #include <nb_cimx.h>
#include <sb_cimx.h> #include <sb_cimx.h>
@@ -46,7 +45,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
u32 val; u32 val;
post_code(0x30); post_code(0x30);
AGESAWRAPPER_PRE_CONSOLE(amdinitmmio); agesawrapper_amdinitmmio();
post_code(0x31); post_code(0x31);
/* Halt if there was a built in self test failure */ /* Halt if there was a built in self test failure */
@@ -66,7 +65,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
post_code(0x37); post_code(0x37);
AGESAWRAPPER(amdinitreset); agesawrapper_amdinitreset();
if (!cpu_init_detectedx && boot_cpu()) { if (!cpu_init_detectedx && boot_cpu()) {
post_code(0x38); post_code(0x38);
@@ -81,7 +80,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
sb_Poweron_Init(); sb_Poweron_Init();
} }
post_code(0x3B); post_code(0x3B);
AGESAWRAPPER(amdinitearly); agesawrapper_amdinitearly();
post_code(0x3C); post_code(0x3C);
/* W83627DHG pin89,90 function select is RSTOUT3#, RSTOUT2# by default. /* W83627DHG pin89,90 function select is RSTOUT3#, RSTOUT2# by default.
@@ -101,10 +100,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
} }
post_code(0x40); post_code(0x40);
AGESAWRAPPER(amdinitpost); agesawrapper_amdinitpost();
post_code(0x41); post_code(0x41);
AGESAWRAPPER(amdinitenv); agesawrapper_amdinitenv();
post_code(0x42); post_code(0x42);
post_code(0x50); post_code(0x50);

11
src/mainboard/supermicro/h8scm/romstage.c
View File

@@ -28,7 +28,6 @@
#include "cpu/x86/lapic.h" #include "cpu/x86/lapic.h"
#include <cpu/amd/car.h> #include <cpu/amd/car.h>
#include <northbridge/amd/agesa/agesawrapper.h> #include <northbridge/amd/agesa/agesawrapper.h>
#include <northbridge/amd/agesa/agesawrapper_call.h>
#include "northbridge/amd/agesa/family10/reset_test.h" #include "northbridge/amd/agesa/family10/reset_test.h"
#include <nb_cimx.h> #include <nb_cimx.h>
#include <sb_cimx.h> #include <sb_cimx.h>
@@ -45,7 +44,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
u32 val; u32 val;
post_code(0x30); post_code(0x30);
AGESAWRAPPER_PRE_CONSOLE(amdinitmmio); agesawrapper_amdinitmmio();
post_code(0x31); post_code(0x31);
/* Halt if there was a built in self test failure */ /* Halt if there was a built in self test failure */
@@ -65,7 +64,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
post_code(0x37); post_code(0x37);
AGESAWRAPPER(amdinitreset); agesawrapper_amdinitreset();
if (!cpu_init_detectedx && boot_cpu()) { if (!cpu_init_detectedx && boot_cpu()) {
post_code(0x38); post_code(0x38);
@@ -80,7 +79,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
sb_Poweron_Init(); sb_Poweron_Init();
} }
post_code(0x3B); post_code(0x3B);
AGESAWRAPPER(amdinitearly); agesawrapper_amdinitearly();
post_code(0x3C); post_code(0x3C);
nb_Ht_Init(); nb_Ht_Init();
@@ -95,10 +94,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
} }
post_code(0x40); post_code(0x40);
AGESAWRAPPER(amdinitpost); agesawrapper_amdinitpost();
post_code(0x41); post_code(0x41);
AGESAWRAPPER(amdinitenv); agesawrapper_amdinitenv();
post_code(0x42); post_code(0x42);
post_code(0x50); post_code(0x50);

11
src/mainboard/tyan/s8226/romstage.c
View File

@@ -28,7 +28,6 @@
#include "cpu/x86/lapic.h" #include "cpu/x86/lapic.h"
#include <cpu/amd/car.h> #include <cpu/amd/car.h>
#include <northbridge/amd/agesa/agesawrapper.h> #include <northbridge/amd/agesa/agesawrapper.h>
#include <northbridge/amd/agesa/agesawrapper_call.h>
#include "northbridge/amd/agesa/family10/reset_test.h" #include "northbridge/amd/agesa/family10/reset_test.h"
#include <nb_cimx.h> #include <nb_cimx.h>
#include <sb_cimx.h> #include <sb_cimx.h>
@@ -44,7 +43,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
u32 val; u32 val;
post_code(0x30); post_code(0x30);
AGESAWRAPPER_PRE_CONSOLE(amdinitmmio); agesawrapper_amdinitmmio();
post_code(0x31); post_code(0x31);
/* For serial port. */ /* For serial port. */
@@ -69,7 +68,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
post_code(0x37); post_code(0x37);
AGESAWRAPPER(amdinitreset); agesawrapper_amdinitreset();
if (!cpu_init_detectedx && boot_cpu()) { if (!cpu_init_detectedx && boot_cpu()) {
post_code(0x38); post_code(0x38);
@@ -84,7 +83,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
sb_Poweron_Init(); sb_Poweron_Init();
} }
post_code(0x3B); post_code(0x3B);
AGESAWRAPPER(amdinitearly); agesawrapper_amdinitearly();
post_code(0x3C); post_code(0x3C);
/* W83627DHG pin89,90 function select is RSTOUT3#, RSTOUT2# by default. /* W83627DHG pin89,90 function select is RSTOUT3#, RSTOUT2# by default.
@@ -104,10 +103,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
} }
post_code(0x40); post_code(0x40);
AGESAWRAPPER(amdinitpost); agesawrapper_amdinitpost();
post_code(0x41); post_code(0x41);
AGESAWRAPPER(amdinitenv); agesawrapper_amdinitenv();
post_code(0x42); post_code(0x42);
post_code(0x50); post_code(0x50);

5
src/northbridge/amd/agesa/agesawrapper.h
View File

@@ -23,7 +23,6 @@
#include <stdint.h> #include <stdint.h>
#include "Porting.h" #include "Porting.h"
#include "AGESA.h" #include "AGESA.h"
#include <northbridge/amd/agesa/agesawrapper_call.h>
/* Define AMD Ontario APPU SSID/SVID */ /* Define AMD Ontario APPU SSID/SVID */
#define AMD_APU_SVID 0x1022 #define AMD_APU_SVID 0x1022
@@ -48,7 +47,9 @@ AGESA_STATUS agesawrapper_amdinitlate(void);
AGESA_STATUS agesawrapper_amdinitpost(void); AGESA_STATUS agesawrapper_amdinitpost(void);
AGESA_STATUS agesawrapper_amdinitmid(void); AGESA_STATUS agesawrapper_amdinitmid(void);
AGESA_STATUS agesawrapper_amdreadeventlog(UINT8 HeapStatus); void agesawrapper_trace(AGESA_STATUS ret, AMD_CONFIG_PARAMS *StdHeader, const char *func);
#define AGESA_EVENTLOG(status, stdheader) \
agesawrapper_trace(status, stdheader, __func__)
AGESA_STATUS agesawrapper_amdinitcpuio(void); AGESA_STATUS agesawrapper_amdinitcpuio(void);
AGESA_STATUS agesawrapper_amdinitmmio(void); AGESA_STATUS agesawrapper_amdinitmmio(void);

73
src/northbridge/amd/agesa/agesawrapper_call.h
View File

@@ -1,73 +0,0 @@
/*
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#ifndef _AGESAWRAPPER_CALL_H_
#define _AGESAWRAPPER_CALL_H_
#include <stdint.h>
#include <console/console.h>
#include "AGESA.h"
/*
* Possible AGESA_STATUS values:
*
* 0x0 = AGESA_SUCCESS
* 0x1 = AGESA_UNSUPPORTED
* 0x2 = AGESA_BOUNDS_CHK
* 0x3 = AGESA_ALERT
* 0x4 = AGESA_WARNING
* 0x5 = AGESA_ERROR
* 0x6 = AGESA_CRITICAL
* 0x7 = AGESA_FATAL
*/
static const char * decodeAGESA_STATUS(AGESA_STATUS sret)
{
const char* statusStrings[] = { "AGESA_SUCCESS", "AGESA_UNSUPPORTED",
"AGESA_BOUNDS_CHK", "AGESA_ALERT",
"AGESA_WARNING", "AGESA_ERROR",
"AGESA_CRITICAL", "AGESA_FATAL"
};
if (sret > 7) return "unknown"; /* Non-AGESA error code */
return statusStrings[sret];
}
static inline u32 do_agesawrapper(AGESA_STATUS (*func)(void), const char *name)
{
AGESA_STATUS ret;
printk(BIOS_DEBUG, "agesawrapper_%s() entry\n", name);
ret = func();
printk(BIOS_DEBUG, "agesawrapper_%s() returned %s\n",
name, decodeAGESA_STATUS(ret));
return (u32)ret;
}
#define AGESAWRAPPER(func) do_agesawrapper(agesawrapper_ ## func, #func)
#define AGESAWRAPPER_PRE_CONSOLE(func) agesawrapper_ ## func()
#if CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY12 || CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY14
/* TODO: These families do not pass valid HeapStatus. */
#define AGESA_EVENTLOG(status) \
if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(0)
#define AGESA_EVENTLOG_(x,y) AGESA_EVENTLOG(x)
#else
#define AGESA_EVENTLOG(status, heapstatus) \
if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(heapstatus)
#define AGESA_EVENTLOG_(x,y) AGESA_EVENTLOG(x,y)
#endif
#endif

73
src/northbridge/amd/agesa/eventlog.c
View File

@@ -1,9 +1,53 @@
/*
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <console/console.h> #include <console/console.h>
#include <stdint.h>
#include <string.h>
#include <northbridge/amd/agesa/agesawrapper.h> #include <northbridge/amd/agesa/agesawrapper.h>
#include <northbridge/amd/agesa/BiosCallOuts.h> #include <northbridge/amd/agesa/BiosCallOuts.h>
#include "amdlib.h" #include "amdlib.h"
#include "AGESA.h"
#include "AMD.h"
/*
* Possible AGESA_STATUS values:
*
* 0x0 = AGESA_SUCCESS
* 0x1 = AGESA_UNSUPPORTED
* 0x2 = AGESA_BOUNDS_CHK
* 0x3 = AGESA_ALERT
* 0x4 = AGESA_WARNING
* 0x5 = AGESA_ERROR
* 0x6 = AGESA_CRITICAL
* 0x7 = AGESA_FATAL
*/
static const char * decodeAGESA_STATUS(AGESA_STATUS sret)
{
const char* statusStrings[] = { "AGESA_SUCCESS", "AGESA_UNSUPPORTED",
"AGESA_BOUNDS_CHK", "AGESA_ALERT",
"AGESA_WARNING", "AGESA_ERROR",
"AGESA_CRITICAL", "AGESA_FATAL"
};
if (sret > 7) return "unknown"; /* Non-AGESA error code */
return statusStrings[sret];
}
#if 0 #if 0
@@ -42,6 +86,7 @@ static void agesa_alert(EVENT_PARAMS *event)
switch (event->EventInfo) { switch (event->EventInfo) {
case MEM_ALERT_USER_TMG_MODE_OVERRULED: case MEM_ALERT_USER_TMG_MODE_OVERRULED:
printk(BIOS_DEBUG, "Socket %x Dct %x Channel %x " printk(BIOS_DEBUG, "Socket %x Dct %x Channel %x "
"TIMING_MODE_SPECIFIC is requested but can not be applied to current configurations.\n", "TIMING_MODE_SPECIFIC is requested but can not be applied to current configurations.\n",
(unsigned int)event->DataParam1, (unsigned int)event->DataParam1,
(unsigned int)event->DataParam2, (unsigned int)event->DataParam2,
@@ -664,25 +709,19 @@ static void interpret_agesa_eventlog(EVENT_PARAMS *event)
} }
#endif #endif
/** static void amd_readeventlog(AMD_CONFIG_PARAMS *StdHeader)
* @param HeapStatus -the current HeapStatus
*/
AGESA_STATUS agesawrapper_amdreadeventlog(UINT8 HeapStatus)
{ {
AGESA_STATUS Status;
EVENT_PARAMS AmdEventParams; EVENT_PARAMS AmdEventParams;
LibAmdMemFill(&AmdEventParams, memset(&AmdEventParams, 0, sizeof(EVENT_PARAMS));
0,
sizeof(EVENT_PARAMS),
&(AmdEventParams.StdHeader));
AmdEventParams.StdHeader.AltImageBasePtr = 0; AmdEventParams.StdHeader.AltImageBasePtr = 0;
AmdEventParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; AmdEventParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
AmdEventParams.StdHeader.Func = 0; AmdEventParams.StdHeader.Func = 0;
AmdEventParams.StdHeader.ImageBasePtr = 0; AmdEventParams.StdHeader.ImageBasePtr = 0;
AmdEventParams.StdHeader.HeapStatus = HeapStatus; AmdEventParams.StdHeader.HeapStatus = StdHeader->HeapStatus;
Status = AmdReadEventLog(&AmdEventParams);
AmdReadEventLog(&AmdEventParams);
while (AmdEventParams.EventClass != 0) { while (AmdEventParams.EventClass != 0) {
printk(BIOS_DEBUG,"\nEventLog: EventClass = %x, EventInfo = %x.\n", printk(BIOS_DEBUG,"\nEventLog: EventClass = %x, EventInfo = %x.\n",
(unsigned int)AmdEventParams.EventClass, (unsigned int)AmdEventParams.EventClass,
@@ -693,8 +732,14 @@ AGESA_STATUS agesawrapper_amdreadeventlog(UINT8 HeapStatus)
printk(BIOS_DEBUG," Param3 = %x, Param4 = %x.\n", printk(BIOS_DEBUG," Param3 = %x, Param4 = %x.\n",
(unsigned int)AmdEventParams.DataParam3, (unsigned int)AmdEventParams.DataParam3,
(unsigned int)AmdEventParams.DataParam4); (unsigned int)AmdEventParams.DataParam4);
Status = AmdReadEventLog(&AmdEventParams); AmdReadEventLog(&AmdEventParams);
} }
}
return Status;
void agesawrapper_trace(AGESA_STATUS ret, AMD_CONFIG_PARAMS *StdHeader, const char *func)
{
printk(BIOS_DEBUG, "%s() returned %s\n", func, decodeAGESA_STATUS(ret));
if (ret != AGESA_SUCCESS)
amd_readeventlog(StdHeader);
} }

2
src/northbridge/amd/agesa/family10/northbridge.c
View File

@@ -832,7 +832,7 @@ static void amdfam10_domain_enable_resources(device_t dev)
{ {
/* Must be called after PCI enumeration and resource allocation */ /* Must be called after PCI enumeration and resource allocation */
printk(BIOS_DEBUG, "\nFam10 - %s: AmdInitMid.\n", __func__); printk(BIOS_DEBUG, "\nFam10 - %s: AmdInitMid.\n", __func__);
AGESAWRAPPER(amdinitmid); agesawrapper_amdinitmid();
printk(BIOS_DEBUG, " ader - leaving %s.\n", __func__); printk(BIOS_DEBUG, " ader - leaving %s.\n", __func__);
} }

14
src/northbridge/amd/agesa/family12/agesawrapper.c
View File

@@ -247,7 +247,7 @@ AGESA_STATUS agesawrapper_amdinitreset(VOID)
AmdResetParams.HtConfig.Depth = 0; AmdResetParams.HtConfig.Depth = 0;
status = AmdInitReset((AMD_RESET_PARAMS *) AmdParamStruct.NewStructPtr); status = AmdInitReset((AMD_RESET_PARAMS *) AmdParamStruct.NewStructPtr);
AGESA_EVENTLOG(status); AGESA_EVENTLOG(status, &AmdParamStruct.StdHeader);
AmdReleaseStruct(&AmdParamStruct); AmdReleaseStruct(&AmdParamStruct);
return status; return status;
} }
@@ -273,7 +273,7 @@ AGESA_STATUS agesawrapper_amdinitearly(VOID)
OemCustomizeInitEarly(AmdEarlyParamsPtr); OemCustomizeInitEarly(AmdEarlyParamsPtr);
status = AmdInitEarly((AMD_EARLY_PARAMS *) AmdParamStruct.NewStructPtr); status = AmdInitEarly((AMD_EARLY_PARAMS *) AmdParamStruct.NewStructPtr);
AGESA_EVENTLOG(status); AGESA_EVENTLOG(status, &AmdParamStruct.StdHeader);
AmdReleaseStruct(&AmdParamStruct); AmdReleaseStruct(&AmdParamStruct);
return status; return status;
@@ -296,7 +296,7 @@ AGESA_STATUS agesawrapper_amdinitpost(VOID)
AmdCreateStruct(&AmdParamStruct); AmdCreateStruct(&AmdParamStruct);
status = AmdInitPost((AMD_POST_PARAMS *) AmdParamStruct.NewStructPtr); status = AmdInitPost((AMD_POST_PARAMS *) AmdParamStruct.NewStructPtr);
AGESA_EVENTLOG(status); AGESA_EVENTLOG(status, &AmdParamStruct.StdHeader);
AmdReleaseStruct(&AmdParamStruct); AmdReleaseStruct(&AmdParamStruct);
/* Initialize heap space */ /* Initialize heap space */
@@ -321,7 +321,7 @@ AGESA_STATUS agesawrapper_amdinitenv(VOID)
AmdParamStruct.StdHeader.ImageBasePtr = 0; AmdParamStruct.StdHeader.ImageBasePtr = 0;
AmdCreateStruct(&AmdParamStruct); AmdCreateStruct(&AmdParamStruct);
status = AmdInitEnv((AMD_ENV_PARAMS *) AmdParamStruct.NewStructPtr); status = AmdInitEnv((AMD_ENV_PARAMS *) AmdParamStruct.NewStructPtr);
AGESA_EVENTLOG(status); AGESA_EVENTLOG(status, &AmdParamStruct.StdHeader);
AmdReleaseStruct(&AmdParamStruct); AmdReleaseStruct(&AmdParamStruct);
return status; return status;
@@ -370,7 +370,7 @@ AGESA_STATUS agesawrapper_amdinitmid(VOID)
AmdCreateStruct(&AmdParamStruct); AmdCreateStruct(&AmdParamStruct);
status = AmdInitMid((AMD_MID_PARAMS *) AmdParamStruct.NewStructPtr); status = AmdInitMid((AMD_MID_PARAMS *) AmdParamStruct.NewStructPtr);
AGESA_EVENTLOG(status); AGESA_EVENTLOG(status, &AmdParamStruct.StdHeader);
AmdReleaseStruct(&AmdParamStruct); AmdReleaseStruct(&AmdParamStruct);
return status; return status;
@@ -389,7 +389,7 @@ AGESA_STATUS agesawrapper_amdinitlate(VOID)
AmdLateParams.StdHeader.ImageBasePtr = 0; AmdLateParams.StdHeader.ImageBasePtr = 0;
status = AmdInitLate(&AmdLateParams); status = AmdInitLate(&AmdLateParams);
AGESA_EVENTLOG(status); AGESA_EVENTLOG(status, &AmdLateParams.StdHeader);
ASSERT(status == AGESA_SUCCESS); ASSERT(status == AGESA_SUCCESS);
DmiTable = AmdLateParams.DmiTable; DmiTable = AmdLateParams.DmiTable;
@@ -417,7 +417,7 @@ AGESA_STATUS agesawrapper_amdlaterunaptask(UINT32 Func, UINT32 Data, VOID * Conf
ApExeParams.StdHeader.ImageBasePtr = 0; ApExeParams.StdHeader.ImageBasePtr = 0;
status = AmdLateRunApTask(&ApExeParams); status = AmdLateRunApTask(&ApExeParams);
AGESA_EVENTLOG(status); AGESA_EVENTLOG(status, &ApExeParams.StdHeader);
ASSERT(status == AGESA_SUCCESS); ASSERT(status == AGESA_SUCCESS);
return status; return status;

3
src/northbridge/amd/agesa/family12/northbridge.c
View File

@@ -37,7 +37,6 @@
#include "sb_cimx.h" #include "sb_cimx.h"
#include <northbridge/amd/agesa/agesawrapper.h> #include <northbridge/amd/agesa/agesawrapper.h>
#include <northbridge/amd/agesa/agesawrapper_call.h>
//#define FX_DEVS NODE_NUMS //#define FX_DEVS NODE_NUMS
#define FX_DEVS 1 #define FX_DEVS 1
@@ -777,7 +776,7 @@ static void domain_enable_resources(device_t dev)
/* Enable MMIO on AMD CPU Address Map Controller */ /* Enable MMIO on AMD CPU Address Map Controller */
agesawrapper_amdinitcpuio(); agesawrapper_amdinitcpuio();
AGESAWRAPPER(amdinitmid); agesawrapper_amdinitmid();
printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s - End.\n",__func__); printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s - End.\n",__func__);
} }

16
src/northbridge/amd/agesa/family14/agesawrapper.c
View File

@@ -157,7 +157,7 @@ AGESA_STATUS agesawrapper_amdinitreset(VOID)
AmdResetParams.HtConfig.Depth = 0; AmdResetParams.HtConfig.Depth = 0;
status = AmdInitReset((AMD_RESET_PARAMS *) AmdParamStruct.NewStructPtr); status = AmdInitReset((AMD_RESET_PARAMS *) AmdParamStruct.NewStructPtr);
AGESA_EVENTLOG(status); AGESA_EVENTLOG(status, &AmdParamStruct.StdHeader);
AmdReleaseStruct(&AmdParamStruct); AmdReleaseStruct(&AmdParamStruct);
return status; return status;
} }
@@ -182,7 +182,7 @@ AGESA_STATUS agesawrapper_amdinitearly(VOID)
OemCustomizeInitEarly(AmdEarlyParamsPtr); OemCustomizeInitEarly(AmdEarlyParamsPtr);
status = AmdInitEarly((AMD_EARLY_PARAMS *) AmdParamStruct.NewStructPtr); status = AmdInitEarly((AMD_EARLY_PARAMS *) AmdParamStruct.NewStructPtr);
AGESA_EVENTLOG(status); AGESA_EVENTLOG(status, &AmdParamStruct.StdHeader);
AmdReleaseStruct(&AmdParamStruct); AmdReleaseStruct(&AmdParamStruct);
return status; return status;
@@ -204,7 +204,7 @@ AGESA_STATUS agesawrapper_amdinitpost(VOID)
AmdCreateStruct(&AmdParamStruct); AmdCreateStruct(&AmdParamStruct);
status = AmdInitPost((AMD_POST_PARAMS *) AmdParamStruct.NewStructPtr); status = AmdInitPost((AMD_POST_PARAMS *) AmdParamStruct.NewStructPtr);
AGESA_EVENTLOG(status); AGESA_EVENTLOG(status, &AmdParamStruct.StdHeader);
AmdReleaseStruct(&AmdParamStruct); AmdReleaseStruct(&AmdParamStruct);
/* Initialize heap space */ /* Initialize heap space */
@@ -229,8 +229,10 @@ AGESA_STATUS agesawrapper_amdinitenv(VOID)
AmdParamStruct.StdHeader.Func = 0; AmdParamStruct.StdHeader.Func = 0;
AmdParamStruct.StdHeader.ImageBasePtr = 0; AmdParamStruct.StdHeader.ImageBasePtr = 0;
AmdCreateStruct(&AmdParamStruct); AmdCreateStruct(&AmdParamStruct);
status = AmdInitEnv((AMD_ENV_PARAMS *) AmdParamStruct.NewStructPtr); status = AmdInitEnv((AMD_ENV_PARAMS *) AmdParamStruct.NewStructPtr);
AGESA_EVENTLOG(status); AGESA_EVENTLOG(status, &AmdParamStruct.StdHeader);
/* Initialize Subordinate Bus Number and Secondary Bus Number /* Initialize Subordinate Bus Number and Secondary Bus Number
* In platform BIOS this address is allocated by PCI enumeration code * In platform BIOS this address is allocated by PCI enumeration code
Modify D1F0x18 Modify D1F0x18
@@ -347,7 +349,7 @@ AGESA_STATUS agesawrapper_amdinitmid(VOID)
AmdCreateStruct(&AmdParamStruct); AmdCreateStruct(&AmdParamStruct);
status = AmdInitMid((AMD_MID_PARAMS *) AmdParamStruct.NewStructPtr); status = AmdInitMid((AMD_MID_PARAMS *) AmdParamStruct.NewStructPtr);
AGESA_EVENTLOG(status); AGESA_EVENTLOG(status, &AmdParamStruct.StdHeader);
AmdReleaseStruct(&AmdParamStruct); AmdReleaseStruct(&AmdParamStruct);
return status; return status;
@@ -375,7 +377,7 @@ AGESA_STATUS agesawrapper_amdinitlate(VOID)
(u32) AmdLateParamsPtr); (u32) AmdLateParamsPtr);
status = AmdInitLate(AmdLateParamsPtr); status = AmdInitLate(AmdLateParamsPtr);
AGESA_EVENTLOG(status); AGESA_EVENTLOG(status, &AmdParamStruct.StdHeader);
ASSERT(status == AGESA_SUCCESS); ASSERT(status == AGESA_SUCCESS);
DmiTable = AmdLateParamsPtr->DmiTable; DmiTable = AmdLateParamsPtr->DmiTable;
@@ -414,7 +416,7 @@ AGESA_STATUS agesawrapper_amdlaterunaptask(UINT32 Func, UINT32 Data, VOID * Conf
ApExeParams.RelatedDataBlock = ConfigPtr; ApExeParams.RelatedDataBlock = ConfigPtr;
status = AmdLateRunApTask(&ApExeParams); status = AmdLateRunApTask(&ApExeParams);
AGESA_EVENTLOG(status); AGESA_EVENTLOG(status, &ApExeParams.StdHeader);
ASSERT(status == AGESA_SUCCESS); ASSERT(status == AGESA_SUCCESS);
return status; return status;

3
src/northbridge/amd/agesa/family14/northbridge.c
View File

@@ -36,7 +36,6 @@
#include <cpu/amd/mtrr.h> #include <cpu/amd/mtrr.h>
#include <northbridge/amd/agesa/agesawrapper.h> #include <northbridge/amd/agesa/agesawrapper.h>
#include <northbridge/amd/agesa/agesawrapper_call.h>
#if CONFIG_AMD_SB_CIMX #if CONFIG_AMD_SB_CIMX
#include <sb_cimx.h> #include <sb_cimx.h>
#endif #endif
@@ -775,7 +774,7 @@ static void domain_enable_resources(device_t dev)
/* Enable MMIO on AMD CPU Address Map Controller */ /* Enable MMIO on AMD CPU Address Map Controller */
agesawrapper_amdinitcpuio(); agesawrapper_amdinitcpuio();
AGESAWRAPPER(amdinitmid); agesawrapper_amdinitmid();
} }
printk(BIOS_DEBUG, " ader - leaving domain_enable_resources.\n"); printk(BIOS_DEBUG, " ader - leaving domain_enable_resources.\n");

14
src/northbridge/amd/agesa/family15/agesawrapper.c
View File

@@ -210,7 +210,7 @@ AGESA_STATUS agesawrapper_amdinitreset(void)
#if (defined AGESA_ENTRY_INIT_RESET) && (AGESA_ENTRY_INIT_RESET == TRUE) #if (defined AGESA_ENTRY_INIT_RESET) && (AGESA_ENTRY_INIT_RESET == TRUE)
status = AmdInitReset((AMD_RESET_PARAMS *) AmdParamStruct.NewStructPtr); status = AmdInitReset((AMD_RESET_PARAMS *) AmdParamStruct.NewStructPtr);
#endif #endif
AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); AGESA_EVENTLOG(status, &AmdParamStruct.StdHeader);
AmdReleaseStruct(&AmdParamStruct); AmdReleaseStruct(&AmdParamStruct);
return status; return status;
@@ -243,7 +243,7 @@ AGESA_STATUS agesawrapper_amdinitearly(void)
OemCustomizeInitEarly(AmdEarlyParamsPtr); OemCustomizeInitEarly(AmdEarlyParamsPtr);
status = AmdInitEarly(AmdEarlyParamsPtr); status = AmdInitEarly(AmdEarlyParamsPtr);
AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); AGESA_EVENTLOG(status, &AmdParamStruct.StdHeader);
GetCpuServicesOfCurrentCore((CONST CPU_SPECIFIC_SERVICES **) & FamilySpecificServices, GetCpuServicesOfCurrentCore((CONST CPU_SPECIFIC_SERVICES **) & FamilySpecificServices,
&AmdParamStruct.StdHeader); &AmdParamStruct.StdHeader);
@@ -281,7 +281,7 @@ AGESA_STATUS agesawrapper_amdinitpost(void)
OemCustomizeInitPost(PostParams); OemCustomizeInitPost(PostParams);
status = AmdInitPost(PostParams); status = AmdInitPost(PostParams);
AGESA_EVENTLOG(status, PostParams->StdHeader.HeapStatus); AGESA_EVENTLOG(status, &PostParams->StdHeader);
AmdReleaseStruct(&AmdParamStruct); AmdReleaseStruct(&AmdParamStruct);
@@ -317,7 +317,7 @@ AGESA_STATUS agesawrapper_amdinitenv(void)
} }
EnvParams = (AMD_ENV_PARAMS *) AmdParamStruct.NewStructPtr; EnvParams = (AMD_ENV_PARAMS *) AmdParamStruct.NewStructPtr;
status = AmdInitEnv(EnvParams); status = AmdInitEnv(EnvParams);
AGESA_EVENTLOG(status, EnvParams->StdHeader.HeapStatus); AGESA_EVENTLOG(status, &EnvParams->StdHeader);
AmdReleaseStruct(&AmdParamStruct); AmdReleaseStruct(&AmdParamStruct);
return status; return status;
@@ -369,7 +369,7 @@ AGESA_STATUS agesawrapper_amdinitmid(void)
return status; return status;
} }
status = AmdInitMid((AMD_MID_PARAMS *) AmdParamStruct.NewStructPtr); status = AmdInitMid((AMD_MID_PARAMS *) AmdParamStruct.NewStructPtr);
AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); AGESA_EVENTLOG(status, &AmdParamStruct.StdHeader);
AmdReleaseStruct(&AmdParamStruct); AmdReleaseStruct(&AmdParamStruct);
return status; return status;
@@ -396,7 +396,7 @@ AGESA_STATUS agesawrapper_amdinitlate(void)
printk(BIOS_DEBUG, "agesawrapper_amdinitlate: AmdLateParamsPtr = %X\n", (u32) AmdLateParamsPtr); printk(BIOS_DEBUG, "agesawrapper_amdinitlate: AmdLateParamsPtr = %X\n", (u32) AmdLateParamsPtr);
status = AmdInitLate(AmdLateParamsPtr); status = AmdInitLate(AmdLateParamsPtr);
AGESA_EVENTLOG(status, AmdLateParamsPtr->StdHeader.HeapStatus); AGESA_EVENTLOG(status, &AmdLateParamsPtr->StdHeader);
ASSERT(status == AGESA_SUCCESS); ASSERT(status == AGESA_SUCCESS);
DmiTable = AmdLateParamsPtr->DmiTable; DmiTable = AmdLateParamsPtr->DmiTable;
@@ -438,7 +438,7 @@ AGESA_STATUS agesawrapper_amdlaterunaptask(UINT32 Func, UINT32 Data, VOID * Conf
printk(BIOS_DEBUG, "AmdLateRunApTask on Core: %x\n", (uint32_t) Data); printk(BIOS_DEBUG, "AmdLateRunApTask on Core: %x\n", (uint32_t) Data);
status = AmdLateRunApTask((AP_EXE_PARAMS *) ConfigPtr); status = AmdLateRunApTask((AP_EXE_PARAMS *) ConfigPtr);
AGESA_EVENTLOG(status, AmdLateParams.StdHeader.HeapStatus); AGESA_EVENTLOG(status, &AmdLateParams.StdHeader);
ASSERT((status == AGESA_SUCCESS) || (status == AGESA_UNSUPPORTED)); ASSERT((status == AGESA_SUCCESS) || (status == AGESA_UNSUPPORTED));
return status; return status;

3
src/northbridge/amd/agesa/family15/northbridge.c
View File

@@ -42,7 +42,6 @@
#include <cpu/amd/amdfam15.h> #include <cpu/amd/amdfam15.h>
#include <cpuRegisters.h> #include <cpuRegisters.h>
#include <northbridge/amd/agesa/agesawrapper.h> #include <northbridge/amd/agesa/agesawrapper.h>
#include <northbridge/amd/agesa/agesawrapper_call.h>
#include "sb_cimx.h" #include "sb_cimx.h"
#define MAX_NODE_NUMS (MAX_NODES * MAX_DIES) #define MAX_NODE_NUMS (MAX_NODES * MAX_DIES)
@@ -710,7 +709,7 @@ static void domain_enable_resources(device_t dev)
/* Enable MMIO on AMD CPU Address Map Controller */ /* Enable MMIO on AMD CPU Address Map Controller */
agesawrapper_amdinitcpuio(); agesawrapper_amdinitcpuio();
AGESAWRAPPER(amdinitmid); agesawrapper_amdinitmid();
printk(BIOS_DEBUG, " Fam15 - leaving %s.\n", __func__); printk(BIOS_DEBUG, " Fam15 - leaving %s.\n", __func__);
} }

12
src/northbridge/amd/agesa/family15rl/agesawrapper.c
View File

@@ -147,7 +147,7 @@ AGESA_STATUS agesawrapper_amdinitreset(void)
AmdResetParams.HtConfig.Depth = 0; AmdResetParams.HtConfig.Depth = 0;
status = AmdInitReset((AMD_RESET_PARAMS *) AmdParamStruct.NewStructPtr); status = AmdInitReset((AMD_RESET_PARAMS *) AmdParamStruct.NewStructPtr);
AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); AGESA_EVENTLOG(status, &AmdParamStruct.StdHeader);
AmdReleaseStruct(&AmdParamStruct); AmdReleaseStruct(&AmdParamStruct);
return status; return status;
} }
@@ -172,7 +172,7 @@ AGESA_STATUS agesawrapper_amdinitearly(void)
OemCustomizeInitEarly(AmdEarlyParamsPtr); OemCustomizeInitEarly(AmdEarlyParamsPtr);
status = AmdInitEarly((AMD_EARLY_PARAMS *) AmdParamStruct.NewStructPtr); status = AmdInitEarly((AMD_EARLY_PARAMS *) AmdParamStruct.NewStructPtr);
AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); AGESA_EVENTLOG(status, &AmdParamStruct.StdHeader);
AmdReleaseStruct(&AmdParamStruct); AmdReleaseStruct(&AmdParamStruct);
return status; return status;
@@ -196,7 +196,7 @@ AGESA_STATUS agesawrapper_amdinitpost(void)
AmdCreateStruct(&AmdParamStruct); AmdCreateStruct(&AmdParamStruct);
PostParams = (AMD_POST_PARAMS *) AmdParamStruct.NewStructPtr; PostParams = (AMD_POST_PARAMS *) AmdParamStruct.NewStructPtr;
status = AmdInitPost(PostParams); status = AmdInitPost(PostParams);
AGESA_EVENTLOG(status, PostParams->StdHeader.HeapStatus); AGESA_EVENTLOG(status, &PostParams->StdHeader);
AmdReleaseStruct(&AmdParamStruct); AmdReleaseStruct(&AmdParamStruct);
/* Initialize heap space */ /* Initialize heap space */
EmptyHeap(); EmptyHeap();
@@ -222,7 +222,7 @@ AGESA_STATUS agesawrapper_amdinitenv(void)
EnvParam = (AMD_ENV_PARAMS *) AmdParamStruct.NewStructPtr; EnvParam = (AMD_ENV_PARAMS *) AmdParamStruct.NewStructPtr;
status = AmdInitEnv(EnvParam); status = AmdInitEnv(EnvParam);
AGESA_EVENTLOG(status, EnvParam->StdHeader.HeapStatus); AGESA_EVENTLOG(status, &EnvParam->StdHeader);
/* Initialize Subordinate Bus Number and Secondary Bus Number /* Initialize Subordinate Bus Number and Secondary Bus Number
* In platform BIOS this address is allocated by PCI enumeration code * In platform BIOS this address is allocated by PCI enumeration code
Modify D1F0x18 Modify D1F0x18
@@ -273,7 +273,7 @@ AGESA_STATUS agesawrapper_amdinitmid(void)
((AMD_MID_PARAMS *) AmdParamStruct.NewStructPtr)->GnbMidConfiguration.iGpuVgaMode = 0; /* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */ ((AMD_MID_PARAMS *) AmdParamStruct.NewStructPtr)->GnbMidConfiguration.iGpuVgaMode = 0; /* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */
status = AmdInitMid((AMD_MID_PARAMS *) AmdParamStruct.NewStructPtr); status = AmdInitMid((AMD_MID_PARAMS *) AmdParamStruct.NewStructPtr);
AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); AGESA_EVENTLOG(status, &AmdParamStruct.StdHeader);
AmdReleaseStruct(&AmdParamStruct); AmdReleaseStruct(&AmdParamStruct);
return status; return status;
@@ -299,7 +299,7 @@ AGESA_STATUS agesawrapper_amdinitlate(void)
AmdCreateStruct(&AmdParamStruct); AmdCreateStruct(&AmdParamStruct);
AmdLateParams = (AMD_LATE_PARAMS *) AmdParamStruct.NewStructPtr; AmdLateParams = (AMD_LATE_PARAMS *) AmdParamStruct.NewStructPtr;
status = AmdInitLate(AmdLateParams); status = AmdInitLate(AmdLateParams);
AGESA_EVENTLOG(status, AmdLateParams->StdHeader.HeapStatus); AGESA_EVENTLOG(status, &AmdLateParams->StdHeader);
ASSERT(status == AGESA_SUCCESS); ASSERT(status == AGESA_SUCCESS);
DmiTable = AmdLateParams->DmiTable; DmiTable = AmdLateParams->DmiTable;

5
src/northbridge/amd/agesa/family15rl/northbridge.c
View File

@@ -43,7 +43,6 @@
#include <cpu/amd/amdfam15.h> #include <cpu/amd/amdfam15.h>
#include <cpuRegisters.h> #include <cpuRegisters.h>
#include <northbridge/amd/agesa/agesawrapper.h> #include <northbridge/amd/agesa/agesawrapper.h>
#include <northbridge/amd/agesa/agesawrapper_call.h>
#define MAX_NODE_NUMS (MAX_NODES * MAX_DIES) #define MAX_NODE_NUMS (MAX_NODES * MAX_DIES)
@@ -697,14 +696,14 @@ static void domain_read_resources(struct device *dev)
static void domain_enable_resources(struct device *dev) static void domain_enable_resources(struct device *dev)
{ {
if (acpi_is_wakeup_s3()) if (acpi_is_wakeup_s3())
AGESAWRAPPER(fchs3laterestore); agesawrapper_fchs3laterestore();
/* Must be called after PCI enumeration and resource allocation */ /* Must be called after PCI enumeration and resource allocation */
if (!acpi_is_wakeup_s3()) { if (!acpi_is_wakeup_s3()) {
/* Enable MMIO on AMD CPU Address Map Controller */ /* Enable MMIO on AMD CPU Address Map Controller */
agesawrapper_amdinitcpuio(); agesawrapper_amdinitcpuio();
AGESAWRAPPER(amdinitmid); agesawrapper_amdinitmid();
} }
printk(BIOS_DEBUG, " ader - leaving %s.\n", __func__); printk(BIOS_DEBUG, " ader - leaving %s.\n", __func__);
} }

12
src/northbridge/amd/agesa/family15tn/agesawrapper.c
View File

@@ -147,7 +147,7 @@ AGESA_STATUS agesawrapper_amdinitreset(void)
AmdResetParams.HtConfig.Depth = 0; AmdResetParams.HtConfig.Depth = 0;
status = AmdInitReset((AMD_RESET_PARAMS *) AmdParamStruct.NewStructPtr); status = AmdInitReset((AMD_RESET_PARAMS *) AmdParamStruct.NewStructPtr);
AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); AGESA_EVENTLOG(status, &AmdParamStruct.StdHeader);
AmdReleaseStruct(&AmdParamStruct); AmdReleaseStruct(&AmdParamStruct);
return status; return status;
} }
@@ -172,7 +172,7 @@ AGESA_STATUS agesawrapper_amdinitearly(void)
OemCustomizeInitEarly(AmdEarlyParamsPtr); OemCustomizeInitEarly(AmdEarlyParamsPtr);
status = AmdInitEarly((AMD_EARLY_PARAMS *) AmdParamStruct.NewStructPtr); status = AmdInitEarly((AMD_EARLY_PARAMS *) AmdParamStruct.NewStructPtr);
AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); AGESA_EVENTLOG(status, &AmdParamStruct.StdHeader);
AmdReleaseStruct(&AmdParamStruct); AmdReleaseStruct(&AmdParamStruct);
return status; return status;
@@ -196,7 +196,7 @@ AGESA_STATUS agesawrapper_amdinitpost(void)
AmdCreateStruct(&AmdParamStruct); AmdCreateStruct(&AmdParamStruct);
PostParams = (AMD_POST_PARAMS *) AmdParamStruct.NewStructPtr; PostParams = (AMD_POST_PARAMS *) AmdParamStruct.NewStructPtr;
status = AmdInitPost(PostParams); status = AmdInitPost(PostParams);
AGESA_EVENTLOG(status, PostParams->StdHeader.HeapStatus); AGESA_EVENTLOG(status, &PostParams->StdHeader);
AmdReleaseStruct(&AmdParamStruct); AmdReleaseStruct(&AmdParamStruct);
/* Initialize heap space */ /* Initialize heap space */
EmptyHeap(); EmptyHeap();
@@ -222,7 +222,7 @@ AGESA_STATUS agesawrapper_amdinitenv(void)
EnvParam = (AMD_ENV_PARAMS *) AmdParamStruct.NewStructPtr; EnvParam = (AMD_ENV_PARAMS *) AmdParamStruct.NewStructPtr;
status = AmdInitEnv(EnvParam); status = AmdInitEnv(EnvParam);
AGESA_EVENTLOG(status, EnvParam->StdHeader.HeapStatus); AGESA_EVENTLOG(status, &EnvParam->StdHeader);
/* Initialize Subordinate Bus Number and Secondary Bus Number /* Initialize Subordinate Bus Number and Secondary Bus Number
* In platform BIOS this address is allocated by PCI enumeration code * In platform BIOS this address is allocated by PCI enumeration code
Modify D1F0x18 Modify D1F0x18
@@ -273,7 +273,7 @@ AGESA_STATUS agesawrapper_amdinitmid(void)
((AMD_MID_PARAMS *) AmdParamStruct.NewStructPtr)->GnbMidConfiguration.iGpuVgaMode = 0; /* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */ ((AMD_MID_PARAMS *) AmdParamStruct.NewStructPtr)->GnbMidConfiguration.iGpuVgaMode = 0; /* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */
status = AmdInitMid((AMD_MID_PARAMS *) AmdParamStruct.NewStructPtr); status = AmdInitMid((AMD_MID_PARAMS *) AmdParamStruct.NewStructPtr);
AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); AGESA_EVENTLOG(status, &AmdParamStruct.StdHeader);
AmdReleaseStruct(&AmdParamStruct); AmdReleaseStruct(&AmdParamStruct);
return status; return status;
@@ -299,7 +299,7 @@ AGESA_STATUS agesawrapper_amdinitlate(void)
AmdCreateStruct(&AmdParamStruct); AmdCreateStruct(&AmdParamStruct);
AmdLateParams = (AMD_LATE_PARAMS *) AmdParamStruct.NewStructPtr; AmdLateParams = (AMD_LATE_PARAMS *) AmdParamStruct.NewStructPtr;
status = AmdInitLate(AmdLateParams); status = AmdInitLate(AmdLateParams);
AGESA_EVENTLOG(status, AmdLateParams->StdHeader.HeapStatus); AGESA_EVENTLOG(status, &AmdLateParams->StdHeader);
ASSERT(status == AGESA_SUCCESS); ASSERT(status == AGESA_SUCCESS);
DmiTable = AmdLateParams->DmiTable; DmiTable = AmdLateParams->DmiTable;

5
src/northbridge/amd/agesa/family15tn/northbridge.c
View File

@@ -42,7 +42,6 @@
#include <cpu/amd/amdfam15.h> #include <cpu/amd/amdfam15.h>
#include <cpuRegisters.h> #include <cpuRegisters.h>
#include <northbridge/amd/agesa/agesawrapper.h> #include <northbridge/amd/agesa/agesawrapper.h>
#include <northbridge/amd/agesa/agesawrapper_call.h>
#define MAX_NODE_NUMS (MAX_NODES * MAX_DIES) #define MAX_NODE_NUMS (MAX_NODES * MAX_DIES)
@@ -695,14 +694,14 @@ static void domain_read_resources(device_t dev)
static void domain_enable_resources(device_t dev) static void domain_enable_resources(device_t dev)
{ {
if (acpi_is_wakeup_s3()) if (acpi_is_wakeup_s3())
AGESAWRAPPER(fchs3laterestore); agesawrapper_fchs3laterestore();
/* Must be called after PCI enumeration and resource allocation */ /* Must be called after PCI enumeration and resource allocation */
if (!acpi_is_wakeup_s3()) { if (!acpi_is_wakeup_s3()) {
/* Enable MMIO on AMD CPU Address Map Controller */ /* Enable MMIO on AMD CPU Address Map Controller */
agesawrapper_amdinitcpuio(); agesawrapper_amdinitcpuio();
AGESAWRAPPER(amdinitmid); agesawrapper_amdinitmid();
} }
printk(BIOS_DEBUG, " ader - leaving %s.\n", __func__); printk(BIOS_DEBUG, " ader - leaving %s.\n", __func__);
} }

12
src/northbridge/amd/agesa/family16kb/agesawrapper.c
View File

@@ -147,7 +147,7 @@ AGESA_STATUS agesawrapper_amdinitreset(void)
AmdResetParams.HtConfig.Depth = 0; AmdResetParams.HtConfig.Depth = 0;
status = AmdInitReset((AMD_RESET_PARAMS *) AmdParamStruct.NewStructPtr); status = AmdInitReset((AMD_RESET_PARAMS *) AmdParamStruct.NewStructPtr);
AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); AGESA_EVENTLOG(status, &AmdParamStruct.StdHeader);
AmdReleaseStruct(&AmdParamStruct); AmdReleaseStruct(&AmdParamStruct);
return status; return status;
} }
@@ -172,7 +172,7 @@ AGESA_STATUS agesawrapper_amdinitearly(void)
OemCustomizeInitEarly(AmdEarlyParamsPtr); OemCustomizeInitEarly(AmdEarlyParamsPtr);
status = AmdInitEarly((AMD_EARLY_PARAMS *) AmdParamStruct.NewStructPtr); status = AmdInitEarly((AMD_EARLY_PARAMS *) AmdParamStruct.NewStructPtr);
AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); AGESA_EVENTLOG(status, &AmdParamStruct.StdHeader);
AmdReleaseStruct(&AmdParamStruct); AmdReleaseStruct(&AmdParamStruct);
return status; return status;
@@ -196,7 +196,7 @@ AGESA_STATUS agesawrapper_amdinitpost(void)
AmdCreateStruct(&AmdParamStruct); AmdCreateStruct(&AmdParamStruct);
PostParams = (AMD_POST_PARAMS *) AmdParamStruct.NewStructPtr; PostParams = (AMD_POST_PARAMS *) AmdParamStruct.NewStructPtr;
status = AmdInitPost(PostParams); status = AmdInitPost(PostParams);
AGESA_EVENTLOG(status, PostParams->StdHeader.HeapStatus); AGESA_EVENTLOG(status, &PostParams->StdHeader);
AmdReleaseStruct(&AmdParamStruct); AmdReleaseStruct(&AmdParamStruct);
/* Initialize heap space */ /* Initialize heap space */
EmptyHeap(); EmptyHeap();
@@ -222,7 +222,7 @@ AGESA_STATUS agesawrapper_amdinitenv(void)
EnvParam = (AMD_ENV_PARAMS *) AmdParamStruct.NewStructPtr; EnvParam = (AMD_ENV_PARAMS *) AmdParamStruct.NewStructPtr;
status = AmdInitEnv(EnvParam); status = AmdInitEnv(EnvParam);
AGESA_EVENTLOG(status, EnvParam->StdHeader.HeapStatus); AGESA_EVENTLOG(status, &EnvParam->StdHeader);
/* Initialize Subordinate Bus Number and Secondary Bus Number /* Initialize Subordinate Bus Number and Secondary Bus Number
* In platform BIOS this address is allocated by PCI enumeration code * In platform BIOS this address is allocated by PCI enumeration code
Modify D1F0x18 Modify D1F0x18
@@ -273,7 +273,7 @@ AGESA_STATUS agesawrapper_amdinitmid(void)
((AMD_MID_PARAMS *) AmdParamStruct.NewStructPtr)->GnbMidConfiguration.iGpuVgaMode = 0; /* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */ ((AMD_MID_PARAMS *) AmdParamStruct.NewStructPtr)->GnbMidConfiguration.iGpuVgaMode = 0; /* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */
status = AmdInitMid((AMD_MID_PARAMS *) AmdParamStruct.NewStructPtr); status = AmdInitMid((AMD_MID_PARAMS *) AmdParamStruct.NewStructPtr);
AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); AGESA_EVENTLOG(status, &AmdParamStruct.StdHeader);
AmdReleaseStruct(&AmdParamStruct); AmdReleaseStruct(&AmdParamStruct);
return status; return status;
@@ -299,7 +299,7 @@ AGESA_STATUS agesawrapper_amdinitlate(void)
AmdCreateStruct(&AmdParamStruct); AmdCreateStruct(&AmdParamStruct);
AmdLateParams = (AMD_LATE_PARAMS *) AmdParamStruct.NewStructPtr; AmdLateParams = (AMD_LATE_PARAMS *) AmdParamStruct.NewStructPtr;
status = AmdInitLate(AmdLateParams); status = AmdInitLate(AmdLateParams);
AGESA_EVENTLOG(status, AmdLateParams->StdHeader.HeapStatus); AGESA_EVENTLOG(status, &AmdLateParams->StdHeader);
ASSERT(status == AGESA_SUCCESS); ASSERT(status == AGESA_SUCCESS);
DmiTable = AmdLateParams->DmiTable; DmiTable = AmdLateParams->DmiTable;

5
src/northbridge/amd/agesa/family16kb/northbridge.c
View File

@@ -42,7 +42,6 @@
#include <cpu/amd/amdfam16.h> #include <cpu/amd/amdfam16.h>
#include <cpuRegisters.h> #include <cpuRegisters.h>
#include <northbridge/amd/agesa/agesawrapper.h> #include <northbridge/amd/agesa/agesawrapper.h>
#include <northbridge/amd/agesa/agesawrapper_call.h>
#define MAX_NODE_NUMS (MAX_NODES * MAX_DIES) #define MAX_NODE_NUMS (MAX_NODES * MAX_DIES)
@@ -737,14 +736,14 @@ static void domain_read_resources(device_t dev)
static void domain_enable_resources(device_t dev) static void domain_enable_resources(device_t dev)
{ {
if (acpi_is_wakeup_s3()) if (acpi_is_wakeup_s3())
AGESAWRAPPER(fchs3laterestore); agesawrapper_fchs3laterestore();
/* Must be called after PCI enumeration and resource allocation */ /* Must be called after PCI enumeration and resource allocation */
if (!acpi_is_wakeup_s3()) { if (!acpi_is_wakeup_s3()) {
/* Enable MMIO on AMD CPU Address Map Controller */ /* Enable MMIO on AMD CPU Address Map Controller */
agesawrapper_amdinitcpuio(); agesawrapper_amdinitcpuio();
AGESAWRAPPER(amdinitmid); agesawrapper_amdinitmid();
} }
printk(BIOS_DEBUG, " ader - leaving domain_enable_resources.\n"); printk(BIOS_DEBUG, " ader - leaving domain_enable_resources.\n");
} }