cpu/intel/slot_1: Init L2 cache on SECC(2) CPUs.

Bring from coreboot v1 support for initializing L2 cache on Slot 1
Pentium II/III CPUs, code names Klamath, Deschutes and Katmai.

Build tested on ASUS P2B-LS and P3B-F. Boot tested on P2B-LS with
Pentium III 600MHz, Katmai core.

Also add missing include of model_68x in slot_1, to address a
similar problem fixed for model_6bx by r5945.

Also change Deschutes CPU init sequence to match Katmai.

Change-Id: I502e8481d1a20f0a2504685e7be16b57f59c8257
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: http://review.coreboot.org/122
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

src/cpu/intel/model_67x/model_67x_init.c

@@ -26,6 +26,7 @@
 #include <cpu/intel/microcode.h>
 #include <cpu/x86/cache.h>
 #include <cpu/x86/msr.h>
+#include <cpu/intel/l2_cache.h>
 
 static const uint32_t microcode_updates[] = {
 	/* Include microcode updates here. */
@@ -46,6 +47,9 @@ static void model_67x_init(device_t cpu)
 	/* Update the microcode */
 	intel_update_microcode(microcode_updates);
 
+	/* Initialize L2 cache */
+	p6_configure_l2_cache();
+
 	/* Turn on caching if we haven't already */
 	x86_enable_cache();