lynxpoint: Add helper functions for reading PM and GPIO base

These base addresses are used in several places and it
is helpful to have one location that is reading it.

Change-Id: Ibf589247f37771f06c18e3e58f92aaf3f0d11271
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/2812
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

src/cpu/intel/haswell/acpi.c

@@ -33,6 +33,8 @@
 #include "haswell.h"
 #include "chip.h"
 
+#include <southbridge/intel/lynxpoint/pch.h>
+
 static int get_cores_per_package(void)
 {
 	struct cpuinfo_x86 c;
@@ -322,7 +324,7 @@ static int generate_P_state_entries(int core, int cores_per_package)
 void generate_cpu_entries(void)
 {
 	int len_pr;
-	int coreID, cpuID, pcontrol_blk = PMB0_BASE, plen = 6;
+	int coreID, cpuID, pcontrol_blk = get_pmbase(), plen = 6;
 	int totalcores = dev_count_cpu();
 	int cores_per_package = get_cores_per_package();
 	int numcpus = totalcores/cores_per_package;

src/cpu/intel/haswell/haswell_init.c

@@ -267,7 +267,7 @@ static void configure_c_states(void)
 
 	msr = rdmsr(MSR_PMG_IO_CAPTURE_BASE);
 	msr.lo &= ~0x7ffff;
-	msr.lo |= (PMB0_BASE + 4);	// LVL_2 base address
+	msr.lo |= (get_pmbase() + 4);	// LVL_2 base address
 	msr.lo |= (2 << 16);		// CST Range: C7 is max C-state
 	wrmsr(MSR_PMG_IO_CAPTURE_BASE, msr);