diff --git a/src/vendorcode/intel/Kconfig b/src/vendorcode/intel/Kconfig
index b821286737..4eb359b507 100644
--- a/src/vendorcode/intel/Kconfig
+++ b/src/vendorcode/intel/Kconfig
@@ -19,6 +19,10 @@ config UDK_202111_BINDING
def_bool n
select UDK_BASE
+config UDK_202302_BINDING
+ def_bool n
+ select UDK_BASE
+
if UDK_BASE
config UDK_2013_VERSION
int
@@ -36,8 +40,13 @@ config UDK_202111_VERSION
int
default 202111
+config UDK_202302_VERSION
+ int
+ default 202302
+
config UDK_VERSION
int
+ default UDK_202302_VERSION if UDK_202302_BINDING
default UDK_202111_VERSION if UDK_202111_BINDING
default UDK_202005_VERSION if UDK_202005_BINDING
default UDK_2017_VERSION if UDK_2017_BINDING
diff --git a/src/vendorcode/intel/Makefile.inc b/src/vendorcode/intel/Makefile.inc
index 078c8113af..67c7210190 100644
--- a/src/vendorcode/intel/Makefile.inc
+++ b/src/vendorcode/intel/Makefile.inc
@@ -26,4 +26,10 @@ CPPFLAGS_x86_32 += -I$(src)/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Inclu
CPPFLAGS_x86_64 += -I$(src)/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/X64
CPPFLAGS_common += -I$(src)/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include
CPPFLAGS_common += -I$(src)/vendorcode/intel/edk2/edk2-stable202111/IntelFsp2Pkg/Include
+else ifeq ($(CONFIG_UDK_202302_BINDING),y)
+CPPFLAGS_x86_32 += -I$(src)/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Ia32
+CPPFLAGS_x86_64 += -I$(src)/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/X64
+CPPFLAGS_common += -I$(src)/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include
+CPPFLAGS_common += -I$(src)/vendorcode/intel/edk2/edk2-stable202302/IntelFsp2Pkg/Include
+CPPFLAGS_common += -I$(src)/vendorcode/intel/edk2/edk2-stable202302/UefiCpuPkg/Include/
endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/IntelFsp2Pkg/Include/FspEas.h b/src/vendorcode/intel/edk2/edk2-stable202302/IntelFsp2Pkg/Include/FspEas.h
new file mode 100644
index 0000000000..d92682906d
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/IntelFsp2Pkg/Include/FspEas.h
@@ -0,0 +1,18 @@
+/** @file
+ Intel FSP definition from Intel Firmware Support Package External
+ Architecture Specification v2.0.
+
+ Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _FSP_EAS_H_
+#define _FSP_EAS_H_
+
+#include
+#include
+#include
+#include
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/IntelFsp2Pkg/Include/FspEas/FspApi.h b/src/vendorcode/intel/edk2/edk2-stable202302/IntelFsp2Pkg/Include/FspEas/FspApi.h
new file mode 100644
index 0000000000..388fcedc10
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/IntelFsp2Pkg/Include/FspEas/FspApi.h
@@ -0,0 +1,761 @@
+/** @file
+ Intel FSP API definition from Intel Firmware Support Package External
+ Architecture Specification v2.0 and above.
+
+ Copyright (c) 2014 - 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _FSP_API_H_
+#define _FSP_API_H_
+
+#include
+#include
+
+///
+/// FSP Reset Status code
+/// These are defined in FSP EAS v2.4 section 13.2.2 - OEM Status Code
+/// @{
+
+#define ENCODE_RESET_REQUEST(ResetType) \
+ ((EFI_STATUS)((MAX_BIT >> 1) | (ResetType)))
+#define FSP_STATUS_RESET_REQUIRED_COLD ENCODE_RESET_REQUEST(1)
+#define FSP_STATUS_RESET_REQUIRED_WARM ENCODE_RESET_REQUEST(2)
+#define FSP_STATUS_RESET_REQUIRED_3 ENCODE_RESET_REQUEST(3)
+#define FSP_STATUS_RESET_REQUIRED_4 ENCODE_RESET_REQUEST(4)
+#define FSP_STATUS_RESET_REQUIRED_5 ENCODE_RESET_REQUEST(5)
+#define FSP_STATUS_RESET_REQUIRED_6 ENCODE_RESET_REQUEST(6)
+#define FSP_STATUS_RESET_REQUIRED_7 ENCODE_RESET_REQUEST(7)
+#define FSP_STATUS_RESET_REQUIRED_8 ENCODE_RESET_REQUEST(8)
+#define FSP_STATUS_VARIABLE_REQUEST ENCODE_RESET_REQUEST(10)
+/// @}
+
+///
+/// FSP Event related definition.
+///
+#define FSP_EVENT_CODE 0xF5000000
+#define FSP_POST_CODE (FSP_EVENT_CODE | 0x00F80000)
+
+/*
+ FSP may optionally include the capability of generating events messages to aid in the debugging of firmware issues.
+ These events fall under three catagories: Error, Progress, and Debug. The event reporting mechanism follows the
+ status code services described in section 6 and 7 of the PI Specification v1.7 Volume 3.
+
+ @param[in] Type Indicates the type of event being reported.
+ See MdePkg/Include/Pi/PiStatusCode.h for the definition of EFI_STATUS_CODE_TYPE.
+ @param[in] Value Describes the current status of a hardware or software entity.
+ This includes information about the class and subclass that is used to classify the entity as well as an operation.
+ For progress events, the operation is the current activity. For error events, it is the exception.
+ For debug events, it is not defined at this time.
+ See MdePkg/Include/Pi/PiStatusCode.h for the definition of EFI_STATUS_CODE_VALUE.
+ @param[in] Instance The enumeration of a hardware or software entity within the system.
+ A system may contain multiple entities that match a class/subclass pairing. The instance differentiates between them.
+ An instance of 0 indicates that instance information is unavailable, not meaningful, or not relevant.
+ Valid instance numbers start with 1.
+ @param[in] *CallerId This parameter can be used to identify the sub-module within the FSP generating the event.
+ This parameter may be NULL.
+ @param[in] *Data This optional parameter may be used to pass additional data. The contents can have event-specific data.
+ For example, the FSP provides a EFI_STATUS_CODE_STRING_DATA instance to this parameter when sending debug messages.
+ This parameter is NULL when no additional data is provided.
+
+ @retval EFI_SUCCESS The event was handled successfully.
+ @retval EFI_INVALID_PARAMETER Input parameters are invalid.
+ @retval EFI_DEVICE_ERROR The event handler failed.
+*/
+typedef
+EFI_STATUS
+(EFIAPI *FSP_EVENT_HANDLER)(
+ IN EFI_STATUS_CODE_TYPE Type,
+ IN EFI_STATUS_CODE_VALUE Value,
+ IN UINT32 Instance,
+ IN OPTIONAL EFI_GUID *CallerId,
+ IN OPTIONAL EFI_STATUS_CODE_DATA *Data
+ );
+
+/*
+ Handler for FSP-T debug log messages, provided by the bootloader.
+
+ @param[in] DebugMessage A pointer to the debug message to be written to the log.
+ @param[in] MessageLength Number of bytes to written to the debug log.
+
+ @retval UINT32 The return value indicates the number of bytes actually written to
+ the debug log. If the return value is less than MessageLength,
+ an error occurred.
+*/
+typedef
+UINT32
+(EFIAPI *FSP_DEBUG_HANDLER)(
+ IN CHAR8 *DebugMessage,
+ IN UINT32 MessageLength
+ );
+
+#pragma pack(1)
+///
+/// FSP_UPD_HEADER Configuration.
+///
+typedef struct {
+ ///
+ /// UPD Region Signature. This signature will be
+ /// "XXXXXX_T" for FSP-T
+ /// "XXXXXX_M" for FSP-M
+ /// "XXXXXX_S" for FSP-S
+ /// "XXXXXX_I" for FSP-I
+ /// Where XXXXXX is an unique signature
+ ///
+ UINT64 Signature;
+ ///
+ /// Revision of the Data structure.
+ /// For FSP spec 2.0/2.1, this value is 1 and only FSPM_UPD having ARCH_UPD.
+ /// For FSP spec 2.2 and above, this value is 2 and ARCH_UPD present in all UPD structures.
+ ///
+ UINT8 Revision;
+ UINT8 Reserved[23];
+} FSP_UPD_HEADER;
+
+///
+/// FSPT_ARCH_UPD Configuration.
+///
+typedef struct {
+ ///
+ /// Revision of the structure is 1 for this version of the specification.
+ ///
+ UINT8 Revision;
+ UINT8 Reserved[3];
+ ///
+ /// Length of the structure in bytes. The current value for this field is 32.
+ ///
+ UINT32 Length;
+ ///
+ /// FspDebugHandler Optional debug handler for the bootloader to receive debug messages
+ /// occurring during FSP execution.
+ ///
+ FSP_DEBUG_HANDLER FspDebugHandler;
+ UINT8 Reserved1[20];
+} FSPT_ARCH_UPD;
+
+///
+/// FSPT_ARCH2_UPD Configuration for FSP 2.4 and above.
+///
+typedef struct {
+ ///
+ /// Revision of the structure is 2 for this version of the specification.
+ ///
+ UINT8 Revision;
+ UINT8 Reserved[3];
+ ///
+ /// Length of the structure in bytes. The current value for this field is 32.
+ ///
+ UINT32 Length;
+ ///
+ /// FspDebugHandler Optional debug handler for the bootloader to receive debug messages
+ /// occurring during FSP execution.
+ ///
+ EFI_PHYSICAL_ADDRESS FspDebugHandler;
+ UINT8 Reserved1[16];
+} FSPT_ARCH2_UPD;
+
+#if CONFIG(PLATFORM_USES_FSP2_X86_32)
+
+///
+/// FSPM_ARCH_UPD Configuration.
+///
+typedef struct {
+ ///
+ /// Revision of the structure. For FSP v2.0 value is 1.
+ ///
+ UINT8 Revision;
+ UINT8 Reserved[3];
+ ///
+ /// Pointer to the non-volatile storage (NVS) data buffer.
+ /// If it is NULL it indicates the NVS data is not available.
+ ///
+ /// Note: This ought to be VOID*, but that won't allow calling this binary on x86_64.
+ ///
+ UINT32 NvsBufferPtr;
+ ///
+ /// Pointer to the temporary stack base address to be
+ /// consumed inside FspMemoryInit() API.
+ ///
+ /// Note: This ought to be VOID*, but that won't allow calling this binary on x86_64.
+ ///
+ UINT32 StackBase;
+ ///
+ /// Temporary stack size to be consumed inside
+ /// FspMemoryInit() API.
+ ///
+ UINT32 StackSize;
+ ///
+ /// Size of memory to be reserved by FSP below "top
+ /// of low usable memory" for bootloader usage.
+ ///
+ UINT32 BootLoaderTolumSize;
+ ///
+ /// Current boot mode.
+ ///
+ UINT32 BootMode;
+ ///
+ /// Optional event handler for the bootloader to be informed of events occurring during FSP execution.
+ /// This value is only valid if Revision is >= 2.
+ ///
+ /// Note: This ought to be FSP_EVENT_HANDLER*, but that won't allow calling this binary on x86_64.
+ ///
+ UINT32 FspEventHandler;
+ UINT8 Reserved1[4];
+} FSPM_ARCH_UPD;
+
+#endif
+
+///
+/// FSPM_ARCH2_UPD Configuration for FSP 2.4 and above.
+///
+typedef struct {
+ ///
+ /// Revision of the structure is 3 for this version of the specification.
+ ///
+ UINT8 Revision;
+ UINT8 Reserved[3];
+ ///
+ /// Length of the structure in bytes. The current value for this field is 64.
+ ///
+ UINT32 Length;
+ ///
+ /// Pointer to the non-volatile storage (NVS) data buffer.
+ /// If it is NULL it indicates the NVS data is not available.
+ /// This value is deprecated starting with v2.4 of the FSP specification,
+ /// and will be removed in an upcoming version of the FSP specification.
+ ///
+ EFI_PHYSICAL_ADDRESS NvsBufferPtr;
+ ///
+ /// Pointer to the temporary stack base address to be
+ /// consumed inside FspMemoryInit() API.
+ ///
+ EFI_PHYSICAL_ADDRESS StackBase;
+ ///
+ /// Temporary stack size to be consumed inside
+ /// FspMemoryInit() API.
+ ///
+ UINT64 StackSize;
+ ///
+ /// Size of memory to be reserved by FSP below "top
+ /// of low usable memory" for bootloader usage.
+ ///
+ UINT32 BootLoaderTolumSize;
+ ///
+ /// Current boot mode.
+ ///
+ UINT32 BootMode;
+ ///
+ /// Optional event handler for the bootloader to be informed of events occurring during FSP execution.
+ /// This value is only valid if Revision is >= 2.
+ ///
+ EFI_PHYSICAL_ADDRESS FspEventHandler;
+ UINT8 Reserved1[16];
+} FSPM_ARCH2_UPD;
+
+///
+/// FSPS_ARCH_UPD Configuration.
+///
+typedef struct {
+ ///
+ /// Revision of the structure is 1 for this version of the specification.
+ ///
+ UINT8 Revision;
+ UINT8 Reserved[3];
+ ///
+ /// Length of the structure in bytes. The current value for this field is 32.
+ ///
+ UINT32 Length;
+ ///
+ /// FspEventHandler Optional event handler for the bootloader to be informed of events
+ /// occurring during FSP execution.
+ ///
+ FSP_EVENT_HANDLER FspEventHandler;
+ ///
+ /// A FSP binary may optionally implement multi-phase silicon initialization,
+ /// This is only supported if the FspMultiPhaseSiInitEntryOffset field in FSP_INFO_HEADER
+ /// is non-zero.
+ /// To enable multi-phase silicon initialization, the bootloader must set
+ /// EnableMultiPhaseSiliconInit to a non-zero value.
+ ///
+ UINT8 EnableMultiPhaseSiliconInit;
+ UINT8 Reserved1[19];
+} FSPS_ARCH_UPD;
+
+///
+/// FSPS_ARCH2_UPD Configuration for FSP 2.4 and above.
+///
+typedef struct {
+ ///
+ /// Revision of the structure is 2 for this version of the specification.
+ ///
+ UINT8 Revision;
+ UINT8 Reserved[3];
+ ///
+ /// Length of the structure in bytes. The current value for this field is 32.
+ ///
+ UINT32 Length;
+ ///
+ /// FspEventHandler Optional event handler for the bootloader to be informed of events
+ /// occurring during FSP execution.
+ ///
+ EFI_PHYSICAL_ADDRESS FspEventHandler;
+ UINT8 Reserved1[16];
+} FSPS_ARCH2_UPD;
+
+///
+/// FSPI_ARCH_UPD Configuration.
+///
+typedef struct {
+ ///
+ /// Revision of the structure is 1 for this version of the specification.
+ ///
+ UINT8 Revision;
+ UINT8 Reserved[3];
+ ///
+ /// Length of the structure in bytes. The current value for this field is 64.
+ ///
+ UINT32 Length;
+ ///
+ /// The physical memory-mapped base address of the bootloader SMM firmware volume (FV).
+ ///
+ EFI_PHYSICAL_ADDRESS BootloaderSmmFvBaseAddress;
+ ///
+ /// The length in bytes of the bootloader SMM firmware volume (FV).
+ ///
+ UINT64 BootloaderSmmFvLength;
+ ///
+ /// The physical memory-mapped base address of the bootloader SMM FV context data.
+ /// This data is provided to bootloader SMM drivers through a HOB by the FSP MM Foundation.
+ ///
+ EFI_PHYSICAL_ADDRESS BootloaderSmmFvContextData;
+ ///
+ /// The length in bytes of the bootloader SMM FV context data.
+ /// This data is provided to bootloader SMM drivers through a HOB by the FSP MM Foundation.
+ ///
+ UINT16 BootloaderSmmFvContextDataLength;
+ UINT8 Reserved1[30];
+} FSPI_ARCH_UPD;
+
+///
+/// FSPT_UPD_COMMON Configuration.
+///
+typedef struct {
+ ///
+ /// FSP_UPD_HEADER Configuration.
+ ///
+ FSP_UPD_HEADER FspUpdHeader;
+} FSPT_UPD_COMMON;
+
+///
+/// FSPT_UPD_COMMON Configuration for FSP spec. 2.2 and above.
+///
+typedef struct {
+ ///
+ /// FSP_UPD_HEADER Configuration.
+ ///
+ FSP_UPD_HEADER FspUpdHeader;
+
+ ///
+ /// FSPT_ARCH_UPD Configuration.
+ ///
+ FSPT_ARCH_UPD FsptArchUpd;
+} FSPT_UPD_COMMON_FSP22;
+
+///
+/// FSPT_UPD_COMMON Configuration for FSP spec. 2.4 and above.
+///
+typedef struct {
+ ///
+ /// FSP_UPD_HEADER Configuration.
+ ///
+ FSP_UPD_HEADER FspUpdHeader;
+
+ ///
+ /// FSPT_ARCH2_UPD Configuration.
+ ///
+ FSPT_ARCH2_UPD FsptArchUpd;
+} FSPT_UPD_COMMON_FSP24;
+
+///
+/// FSPM_UPD_COMMON Configuration.
+///
+typedef struct {
+ ///
+ /// FSP_UPD_HEADER Configuration.
+ ///
+ FSP_UPD_HEADER FspUpdHeader;
+ ///
+ /// FSPM_ARCH_UPD Configuration.
+ ///
+ FSPM_ARCH_UPD FspmArchUpd;
+} FSPM_UPD_COMMON;
+
+///
+/// FSPM_UPD_COMMON Configuration for FSP spec. 2.4 and above.
+///
+typedef struct {
+ ///
+ /// FSP_UPD_HEADER Configuration.
+ ///
+ FSP_UPD_HEADER FspUpdHeader;
+ ///
+ /// FSPM_ARCH2_UPD Configuration.
+ ///
+ FSPM_ARCH2_UPD FspmArchUpd;
+} FSPM_UPD_COMMON_FSP24;
+
+///
+/// FSPS_UPD_COMMON Configuration.
+///
+typedef struct {
+ ///
+ /// FSP_UPD_HEADER Configuration.
+ ///
+ FSP_UPD_HEADER FspUpdHeader;
+} FSPS_UPD_COMMON;
+
+///
+/// FSPS_UPD_COMMON Configuration for FSP spec. 2.2 and above.
+///
+typedef struct {
+ ///
+ /// FSP_UPD_HEADER Configuration.
+ ///
+ FSP_UPD_HEADER FspUpdHeader;
+
+ ///
+ /// FSPS_ARCH_UPD Configuration.
+ ///
+ FSPS_ARCH_UPD FspsArchUpd;
+} FSPS_UPD_COMMON_FSP22;
+
+///
+/// FSPS_UPD_COMMON Configuration for FSP spec. 2.4 and above.
+///
+typedef struct {
+ ///
+ /// FSP_UPD_HEADER Configuration.
+ ///
+ FSP_UPD_HEADER FspUpdHeader;
+
+ ///
+ /// FSPS_ARCH2_UPD Configuration.
+ ///
+ FSPS_ARCH2_UPD FspsArchUpd;
+} FSPS_UPD_COMMON_FSP24;
+
+///
+/// FSPI_UPD_COMMON Configuration.
+///
+typedef struct {
+ ///
+ /// FSP_UPD_HEADER Configuration.
+ ///
+ FSP_UPD_HEADER FspUpdHeader;
+
+ ///
+ /// FSPI_ARCH_UPD Configuration.
+ ///
+ FSPI_ARCH_UPD FspiArchUpd;
+} FSPI_UPD_COMMON;
+
+///
+/// Enumeration of FSP_INIT_PHASE for NOTIFY_PHASE.
+///
+typedef enum {
+ ///
+ /// This stage is notified when the bootloader completes the
+ /// PCI enumeration and the resource allocation for the
+ /// PCI devices is complete.
+ ///
+ EnumInitPhaseAfterPciEnumeration = 0x20,
+ ///
+ /// This stage is notified just before the bootloader hand-off
+ /// to the OS loader.
+ ///
+ EnumInitPhaseReadyToBoot = 0x40,
+ ///
+ /// This stage is notified just before the firmware/Preboot
+ /// environment transfers management of all system resources
+ /// to the OS or next level execution environment.
+ ///
+ EnumInitPhaseEndOfFirmware = 0xF0
+} FSP_INIT_PHASE;
+
+///
+/// Definition of NOTIFY_PHASE_PARAMS.
+///
+typedef struct {
+ ///
+ /// Notification phase used for NotifyPhase API
+ ///
+ FSP_INIT_PHASE Phase;
+} NOTIFY_PHASE_PARAMS;
+
+///
+/// Action definition for FspMultiPhaseSiInit API
+///
+typedef enum {
+ EnumMultiPhaseGetNumberOfPhases = 0x0,
+ EnumMultiPhaseExecutePhase = 0x1,
+ EnumMultiPhaseGetVariableRequestInfo = 0x2,
+ EnumMultiPhaseCompleteVariableRequest = 0x3
+} FSP_MULTI_PHASE_ACTION;
+
+typedef enum {
+ EnumFspVariableRequestGetVariable = 0x0,
+ EnumFspVariableRequestGetNextVariableName = 0x1,
+ EnumFspVariableRequestSetVariable = 0x2,
+ EnumFspVariableRequestQueryVariableInfo = 0x3
+} FSP_VARIABLE_REQUEST_TYPE;
+
+#pragma pack(16)
+typedef struct {
+ IN FSP_VARIABLE_REQUEST_TYPE VariableRequest;
+ IN OUT CHAR16 *VariableName;
+ IN OUT UINT64 *VariableNameSize;
+ IN OUT EFI_GUID *VariableGuid;
+ IN OUT UINT32 *Attributes;
+ IN OUT UINT64 *DataSize;
+ IN OUT VOID *Data;
+ OUT UINT64 *MaximumVariableStorageSize;
+ OUT UINT64 *RemainingVariableStorageSize;
+ OUT UINT64 *MaximumVariableSize;
+} FSP_MULTI_PHASE_VARIABLE_REQUEST_INFO_PARAMS;
+
+typedef struct {
+ EFI_STATUS VariableRequestStatus;
+} FSP_MULTI_PHASE_COMPLETE_VARIABLE_REQUEST_PARAMS;
+#pragma pack()
+
+///
+/// Data structure returned by FSP when bootloader calling
+/// FspMultiPhaseSiInit API with action 0 (EnumMultiPhaseGetNumberOfPhases)
+///
+typedef struct {
+ UINT32 NumberOfPhases;
+ UINT32 PhasesExecuted;
+} FSP_MULTI_PHASE_GET_NUMBER_OF_PHASES_PARAMS;
+
+///
+/// FspMultiPhaseSiInit function parameter.
+///
+/// For action 0 (EnumMultiPhaseGetNumberOfPhases):
+/// - PhaseIndex must be 0.
+/// - MultiPhaseParamPtr should point to an instance of FSP_MULTI_PHASE_GET_NUMBER_OF_PHASES_PARAMS.
+///
+/// For action 1 (EnumMultiPhaseExecutePhase):
+/// - PhaseIndex will be the phase that will be executed by FSP.
+/// - MultiPhaseParamPtr shall be NULL.
+///
+typedef struct {
+ IN FSP_MULTI_PHASE_ACTION MultiPhaseAction;
+ IN UINT32 PhaseIndex;
+ IN OUT VOID *MultiPhaseParamPtr;
+} FSP_MULTI_PHASE_PARAMS;
+
+#pragma pack()
+
+/**
+ This FSP API is called soon after coming out of reset and before memory and stack is
+ available. This FSP API will load the microcode update, enable code caching for the
+ region specified by the boot loader and also setup a temporary stack to be used until
+ main memory is initialized.
+
+ A hardcoded stack can be set up with the following values, and the "esp" register
+ initialized to point to this hardcoded stack.
+ 1. The return address where the FSP will return control after setting up a temporary
+ stack.
+ 2. A pointer to the input parameter structure
+
+ However, since the stack is in ROM and not writeable, this FSP API cannot be called
+ using the "call" instruction, but needs to be jumped to.
+
+ @param[in] FsptUpdDataPtr Pointer to the FSPT_UPD data structure.
+
+ @retval EFI_SUCCESS Temporary RAM was initialized successfully.
+ @retval EFI_INVALID_PARAMETER Input parameters are invalid.
+ @retval EFI_UNSUPPORTED The FSP calling conditions were not met.
+ @retval EFI_DEVICE_ERROR Temp RAM initialization failed.
+
+ If this function is successful, the FSP initializes the ECX and EDX registers to point to
+ a temporary but writeable memory range available to the boot loader and returns with
+ FSP_SUCCESS in register EAX. Register ECX points to the start of this temporary
+ memory range and EDX points to the end of the range. Boot loader is free to use the
+ whole range described. Typically the boot loader can reload the ESP register to point
+ to the end of this returned range so that it can be used as a standard stack.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *FSP_TEMP_RAM_INIT)(
+ IN VOID *FsptUpdDataPtr
+ );
+
+/**
+ This FSP API is used to notify the FSP about the different phases in the boot process.
+ This allows the FSP to take appropriate actions as needed during different initialization
+ phases. The phases will be platform dependent and will be documented with the FSP
+ release. The current FSP supports two notify phases:
+ Post PCI enumeration
+ Ready To Boot
+
+ @param[in] NotifyPhaseParamPtr Address pointer to the NOTIFY_PHASE_PRAMS
+
+ @retval EFI_SUCCESS The notification was handled successfully.
+ @retval EFI_UNSUPPORTED The notification was not called in the proper order.
+ @retval EFI_INVALID_PARAMETER The notification code is invalid.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *FSP_NOTIFY_PHASE)(
+ IN NOTIFY_PHASE_PARAMS *NotifyPhaseParamPtr
+ );
+
+/**
+ This FSP API is called after TempRamInit and initializes the memory.
+ This FSP API accepts a pointer to a data structure that will be platform dependent
+ and defined for each FSP binary. This will be documented in Integration guide with
+ each FSP release.
+ After FspMemInit completes its execution, it passes the pointer to the HobList and
+ returns to the boot loader from where it was called. BootLoader is responsible to
+ migrate its stack and data to Memory.
+ FspMemoryInit, TempRamExit and FspSiliconInit APIs provide an alternate method to
+ complete the silicon initialization and provides bootloader an opportunity to get
+ control after system memory is available and before the temporary RAM is torn down.
+
+ @param[in] FspmUpdDataPtr Pointer to the FSPM_UPD data structure.
+ @param[out] HobListPtr Pointer to receive the address of the HOB list.
+
+ @retval EFI_SUCCESS FSP execution environment was initialized successfully.
+ @retval EFI_INVALID_PARAMETER Input parameters are invalid.
+ @retval EFI_UNSUPPORTED The FSP calling conditions were not met.
+ @retval EFI_DEVICE_ERROR FSP initialization failed.
+ @retval EFI_OUT_OF_RESOURCES Stack range requested by FSP is not met.
+ @retval FSP_STATUS_RESET_REQUIREDx A reset is required. These status codes will not be returned during S3.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *FSP_MEMORY_INIT)(
+ IN VOID *FspmUpdDataPtr,
+ OUT VOID **HobListPtr
+ );
+
+/**
+ This FSP API is called after FspMemoryInit API. This FSP API tears down the temporary
+ memory setup by TempRamInit API. This FSP API accepts a pointer to a data structure
+ that will be platform dependent and defined for each FSP binary. This will be
+ documented in Integration Guide.
+ FspMemoryInit, TempRamExit and FspSiliconInit APIs provide an alternate method to
+ complete the silicon initialization and provides bootloader an opportunity to get
+ control after system memory is available and before the temporary RAM is torn down.
+
+ @param[in] TempRamExitParamPtr Pointer to the Temp Ram Exit parameters structure.
+ This structure is normally defined in the Integration Guide.
+ And if it is not defined in the Integration Guide, pass NULL.
+
+ @retval EFI_SUCCESS FSP execution environment was initialized successfully.
+ @retval EFI_INVALID_PARAMETER Input parameters are invalid.
+ @retval EFI_UNSUPPORTED The FSP calling conditions were not met.
+ @retval EFI_DEVICE_ERROR FSP initialization failed.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *FSP_TEMP_RAM_EXIT)(
+ IN VOID *TempRamExitParamPtr
+ );
+
+/**
+ This FSP API is called after TempRamExit API.
+ FspMemoryInit, TempRamExit and FspSiliconInit APIs provide an alternate method to complete the
+ silicon initialization.
+
+ @param[in] FspsUpdDataPtr Pointer to the FSPS_UPD data structure.
+ If NULL, FSP will use the default parameters.
+
+ @retval EFI_SUCCESS FSP execution environment was initialized successfully.
+ @retval EFI_INVALID_PARAMETER Input parameters are invalid.
+ @retval EFI_UNSUPPORTED The FSP calling conditions were not met.
+ @retval EFI_DEVICE_ERROR FSP initialization failed.
+ @retval FSP_STATUS_RESET_REQUIREDx A reset is required. These status codes will not be returned during S3.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *FSP_SILICON_INIT)(
+ IN VOID *FspsUpdDataPtr
+ );
+
+/**
+ This FSP API is expected to be called after FspSiliconInit but before FspNotifyPhase.
+ This FSP API provides multi-phase silicon initialization; which brings greater modularity
+ beyond the existing FspSiliconInit() API. Increased modularity is achieved by adding an
+ extra API to FSP-S. This allows the bootloader to add board specific initialization steps
+ throughout the SiliconInit flow as needed.
+
+ @param[in,out] FSP_MULTI_PHASE_PARAMS For action - EnumMultiPhaseGetNumberOfPhases:
+ FSP_MULTI_PHASE_PARAMS->MultiPhaseParamPtr will contain
+ how many phases supported by FSP.
+ For action - EnumMultiPhaseExecutePhase:
+ FSP_MULTI_PHASE_PARAMS->MultiPhaseParamPtr shall be NULL.
+ @retval EFI_SUCCESS FSP execution environment was initialized successfully.
+ @retval EFI_INVALID_PARAMETER Input parameters are invalid.
+ @retval EFI_UNSUPPORTED The FSP calling conditions were not met.
+ @retval EFI_DEVICE_ERROR FSP initialization failed.
+ @retval FSP_STATUS_RESET_REQUIREDx A reset is required. These status codes will not be returned during S3.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *FSP_MULTI_PHASE_SI_INIT)(
+ IN FSP_MULTI_PHASE_PARAMS *MultiPhaseSiInitParamPtr
+ );
+
+/**
+ This FSP API initializes SMM and provide any OS runtime silicon services,
+ including Reliability, Availability, and Serviceability (RAS) features implemented by the CPU.
+
+ @param[in] FspiUpdDataPtr Pointer to the FSPI_UPD data structure.
+ If NULL, FSP will use the default parameters.
+
+ @retval EFI_SUCCESS FSP execution environment was initialized successfully.
+ @retval EFI_INVALID_PARAMETER Input parameters are invalid.
+ @retval EFI_UNSUPPORTED The FSP calling conditions were not met.
+ @retval EFI_DEVICE_ERROR FSP initialization failed.
+ @retval FSP_STATUS_RESET_REQUIREDx A reset is required. These status codes will not be returned during S3.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *FSP_SMM_INIT)(
+ IN VOID *FspiUpdDataPtr
+ );
+
+/**
+ This FSP API provides multi-phase memory and silicon initialization, which brings greater modularity to the existing
+ FspMemoryInit() and FspSiliconInit() API. Increased modularity is achieved by adding an extra API to FSP-M and FSP-S.
+ This allows the bootloader to add board specific initialization steps throughout the MemoryInit and SiliconInit flows as needed.
+ The FspMemoryInit() API is always called before FspMultiPhaseMemInit(); it is the first phase of memory initialization. Similarly,
+ the FspSiliconInit() API is always called before FspMultiPhaseSiInit(); it is the first phase of silicon initialization.
+ After the first phase, subsequent phases are invoked by calling the FspMultiPhaseMem/SiInit() API.
+ The FspMultiPhaseMemInit() API may only be called after the FspMemoryInit() API and before the FspSiliconInit() API;
+ or in the case that FSP-T is being used, before the TempRamExit() API. The FspMultiPhaseSiInit() API may only be called after
+ the FspSiliconInit() API and before NotifyPhase() API; or in the case that FSP-I is being used, before the FspSmmInit() API.
+ The multi-phase APIs may not be called at any other time.
+
+ @param[in,out] FSP_MULTI_PHASE_PARAMS For action - EnumMultiPhaseGetNumberOfPhases:
+ FSP_MULTI_PHASE_PARAMS->MultiPhaseParamPtr will contain
+ how many phases supported by FSP.
+ For action - EnumMultiPhaseExecutePhase:
+ FSP_MULTI_PHASE_PARAMS->MultiPhaseParamPtr shall be NULL.
+ @retval EFI_SUCCESS FSP execution environment was initialized successfully.
+ @retval EFI_INVALID_PARAMETER Input parameters are invalid.
+ @retval EFI_UNSUPPORTED The FSP calling conditions were not met.
+ @retval EFI_DEVICE_ERROR FSP initialization failed.
+ @retval FSP_STATUS_RESET_REQUIRED_* A reset is required. These status codes will not be returned during S3.
+ @retval FSP_STATUS_VARIABLE_REQUEST A variable request has been made by FSP that needs boot loader handling.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *FSP_MULTI_PHASE_INIT)(
+ IN FSP_MULTI_PHASE_PARAMS *MultiPhaseInitParamPtr
+ );
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/IntelFsp2Pkg/Include/FspGlobalData.h b/src/vendorcode/intel/edk2/edk2-stable202302/IntelFsp2Pkg/Include/FspGlobalData.h
new file mode 100644
index 0000000000..1bcec00ef1
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/IntelFsp2Pkg/Include/FspGlobalData.h
@@ -0,0 +1,104 @@
+/** @file
+
+ Copyright (c) 2014 - 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _FSP_GLOBAL_DATA_H_
+#define _FSP_GLOBAL_DATA_H_
+
+#include
+
+#define FSP_IN_API_MODE 0
+#define FSP_IN_DISPATCH_MODE 1
+#define FSP_GLOBAL_DATA_VERSION 0x3
+
+#pragma pack(1)
+
+typedef enum {
+ TempRamInitApiIndex,
+ FspInitApiIndex,
+ NotifyPhaseApiIndex,
+ FspMemoryInitApiIndex,
+ TempRamExitApiIndex,
+ FspSiliconInitApiIndex,
+ FspMultiPhaseSiInitApiIndex,
+ FspSmmInitApiIndex,
+ FspMultiPhaseMemInitApiIndex,
+ FspApiIndexMax
+} FSP_API_INDEX;
+
+typedef struct {
+ VOID *DataPtr;
+ UINTN MicrocodeRegionBase;
+ UINTN MicrocodeRegionSize;
+ UINTN CodeRegionBase;
+ UINTN CodeRegionSize;
+ UINTN Reserved;
+} FSP_PLAT_DATA;
+
+#define FSP_GLOBAL_DATA_SIGNATURE SIGNATURE_32 ('F', 'S', 'P', 'D')
+#define FSP_PERFORMANCE_DATA_SIGNATURE SIGNATURE_32 ('P', 'E', 'R', 'F')
+#define FSP_PERFORMANCE_DATA_TIMER_MASK 0xFFFFFFFFFFFFFF
+
+typedef struct {
+ UINT32 Signature;
+ UINT8 Version;
+ UINT8 Reserved1[3];
+ ///
+ /// Offset 0x08
+ ///
+ UINTN CoreStack;
+ VOID *SmmInitUpdPtr;
+ ///
+ /// IA32: Offset 0x10; X64: Offset 0x18
+ ///
+ UINT32 StatusCode;
+ UINT8 ApiIdx;
+ ///
+ /// 0: FSP in API mode; 1: FSP in DISPATCH mode
+ ///
+ UINT8 FspMode;
+ UINT8 OnSeparateStack;
+ UINT8 Reserved2;
+ UINT32 NumberOfPhases;
+ UINT32 PhasesExecuted;
+ UINT32 Reserved3[8];
+ ///
+ /// IA32: Offset 0x40; X64: Offset 0x48
+ /// Start of UINTN and pointer section
+ /// All UINTN and pointer members are put in this section
+ /// for maintaining natural alignment for both IA32 and X64 builds.
+ ///
+ FSP_PLAT_DATA PlatformData;
+ VOID *TempRamInitUpdPtr;
+ VOID *MemoryInitUpdPtr;
+ VOID *SiliconInitUpdPtr;
+ ///
+ /// IA32: Offset 0x64; X64: Offset 0x90
+ /// To store function parameters pointer
+ /// so it can be retrieved after stack switched.
+ ///
+ VOID *FunctionParameterPtr;
+ FSP_INFO_HEADER *FspInfoHeader;
+ VOID *UpdDataPtr;
+ VOID *FspHobListPtr;
+ VOID *VariableRequestParameterPtr;
+ ///
+ /// End of UINTN and pointer section
+ /// At this point, next field offset must be either *0h or *8h to
+ /// meet natural alignment requirement.
+ ///
+ UINT8 Reserved4[16];
+ UINT32 PerfSig;
+ UINT16 PerfLen;
+ UINT16 Reserved5;
+ UINT32 PerfIdx;
+ UINT32 Reserved6;
+ UINT64 PerfData[32];
+} FSP_GLOBAL_DATA;
+
+#pragma pack()
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/IntelFsp2Pkg/Include/FspMeasurePointId.h b/src/vendorcode/intel/edk2/edk2-stable202302/IntelFsp2Pkg/Include/FspMeasurePointId.h
new file mode 100644
index 0000000000..8e15f1d922
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/IntelFsp2Pkg/Include/FspMeasurePointId.h
@@ -0,0 +1,56 @@
+/** @file
+
+ Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _FSP_MEASURE_POINT_ID_H_
+#define _FSP_MEASURE_POINT_ID_H_
+
+//
+// 0xD0 - 0xEF are reserved for FSP common measure point
+//
+#define FSP_PERF_ID_MRC_INIT_ENTRY 0xD0
+#define FSP_PERF_ID_MRC_INIT_EXIT (FSP_PERF_ID_MRC_INIT_ENTRY + 1)
+
+#define FSP_PERF_ID_SYSTEM_AGENT_INIT_ENTRY 0xD8
+#define FSP_PERF_ID_SYSTEM_AGENT_INIT_EXIT (FSP_PERF_ID_SYSTEM_AGENT_INIT_ENTRY + 1)
+
+#define FSP_PERF_ID_PCH_INIT_ENTRY 0xDA
+#define FSP_PERF_ID_PCH_INIT_EXIT (FSP_PERF_ID_PCH_INIT_ENTRY + 1)
+
+#define FSP_PERF_ID_CPU_INIT_ENTRY 0xE0
+#define FSP_PERF_ID_CPU_INIT_EXIT (FSP_PERF_ID_CPU_INIT_ENTRY + 1)
+
+#define FSP_PERF_ID_GFX_INIT_ENTRY 0xE8
+#define FSP_PERF_ID_GFX_INIT_EXIT (FSP_PERF_ID_GFX_INIT_ENTRY + 1)
+
+#define FSP_PERF_ID_ME_INIT_ENTRY 0xEA
+#define FSP_PERF_ID_ME_INIT_EXIT (FSP_PERF_ID_ME_INIT_ENTRY + 1)
+
+//
+// 0xF0 - 0xFF are reserved for FSP API
+//
+#define FSP_PERF_ID_API_TEMP_RAM_INIT_ENTRY 0xF0
+#define FSP_PERF_ID_API_TEMP_RAM_INIT_EXIT (FSP_PERF_ID_API_TEMP_RAM_INIT_ENTRY + 1)
+
+#define FSP_PERF_ID_API_FSP_MEMORY_INIT_ENTRY 0xF2
+#define FSP_PERF_ID_API_FSP_MEMORY_INIT_EXIT (FSP_PERF_ID_API_FSP_MEMORY_INIT_ENTRY + 1)
+
+#define FSP_PERF_ID_API_TEMP_RAM_EXIT_ENTRY 0xF4
+#define FSP_PERF_ID_API_TEMP_RAM_EXIT_EXIT (FSP_PERF_ID_API_TEMP_RAM_EXIT_ENTRY + 1)
+
+#define FSP_PERF_ID_API_FSP_SILICON_INIT_ENTRY 0xF6
+#define FSP_PERF_ID_API_FSP_SILICON_INIT_EXIT (FSP_PERF_ID_API_FSP_SILICON_INIT_ENTRY + 1)
+
+#define FSP_PERF_ID_API_NOTIFY_POST_PCI_ENTRY 0xF8
+#define FSP_PERF_ID_API_NOTIFY_POST_PCI_EXIT (FSP_PERF_ID_API_NOTIFY_POST_PCI_ENTRY + 1)
+
+#define FSP_PERF_ID_API_NOTIFY_READY_TO_BOOT_ENTRY 0xFA
+#define FSP_PERF_ID_API_NOTIFY_READY_TO_BOOT_EXIT (FSP_PERF_ID_API_NOTIFY_READY_TO_BOOT_ENTRY + 1)
+
+#define FSP_PERF_ID_API_NOTIFY_END_OF_FIRMWARE_ENTRY 0xFC
+#define FSP_PERF_ID_API_NOTIFY_END_OF_FIRMWARE_EXIT (FSP_PERF_ID_API_NOTIFY_END_OF_FIRMWARE_ENTRY + 1)
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/IntelFsp2Pkg/Include/FspStatusCode.h b/src/vendorcode/intel/edk2/edk2-stable202302/IntelFsp2Pkg/Include/FspStatusCode.h
new file mode 100644
index 0000000000..91d282ebfd
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/IntelFsp2Pkg/Include/FspStatusCode.h
@@ -0,0 +1,40 @@
+/** @file
+ Intel FSP status code definition
+
+ Copyright (c) 2016, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _FSP_STATUS_CODE_H_
+#define _FSP_STATUS_CODE_H_
+
+//
+// FSP API - 4 BITS
+//
+#define FSP_STATUS_CODE_TEMP_RAM_INIT 0xF000
+#define FSP_STATUS_CODE_MEMORY_INIT 0xD000
+#define FSP_STATUS_CODE_TEMP_RAM_EXIT 0xB000
+#define FSP_STATUS_CODE_SILICON_INIT 0x9000
+#define FSP_STATUS_CODE_POST_PCIE_ENUM_NOTIFICATION 0x6000
+#define FSP_STATUS_CODE_READY_TO_BOOT_NOTIFICATION 0x4000
+#define FSP_STATUS_CODE_END_OF_FIRMWARE_NOTIFICATION 0x2000
+
+//
+// MODULE - 4 BITS
+//
+#define FSP_STATUS_CODE_GFX_PEIM 0x0700
+#define FSP_STATUS_CODE_COMMON_CODE 0x0800
+#define FSP_STATUS_CODE_SILICON_COMMON_CODE 0x0900
+#define FSP_STATUS_CODE_SYSTEM_AGENT 0x0A00
+#define FSP_STATUS_CODE_PCH 0x0B00
+#define FSP_STATUS_CODE_CPU 0x0C00
+#define FSP_STATUS_CODE_MRC 0x0D00
+#define FSP_STATUS_CODE_ME_BIOS 0x0E00
+//
+// Individual Codes - 1 BYTE
+//
+#define FSP_STATUS_CODE_API_ENTRY 0x0000
+#define FSP_STATUS_CODE_API_EXIT 0x007F
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/IntelFsp2Pkg/Include/Guid/FspHeaderFile.h b/src/vendorcode/intel/edk2/edk2-stable202302/IntelFsp2Pkg/Include/Guid/FspHeaderFile.h
new file mode 100644
index 0000000000..9ea1b2f054
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/IntelFsp2Pkg/Include/Guid/FspHeaderFile.h
@@ -0,0 +1,272 @@
+/** @file
+ Intel FSP Header File definition from Intel Firmware Support Package External
+ Architecture Specification v2.0 and above.
+
+ Copyright (c) 2014 - 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include
+
+#ifndef __FSP_HEADER_FILE_H__
+#define __FSP_HEADER_FILE_H__
+
+#define FSP_HEADER_REVISION_3 3
+
+#define FSPE_HEADER_REVISION_1 1
+#define FSPP_HEADER_REVISION_1 1
+
+///
+/// Fixed FSP header offset in the FSP image
+///
+#define FSP_INFO_HEADER_OFF 0x94
+
+#define OFFSET_IN_FSP_INFO_HEADER(x) (UINT32)&((FSP_INFO_HEADER *)(UINTN)0)->x
+
+#define FSP_INFO_HEADER_SIGNATURE SIGNATURE_32 ('F', 'S', 'P', 'H')
+
+#define IMAGE_ATTRIBUTE_GRAPHICS_SUPPORT BIT0
+#define IMAGE_ATTRIBUTE_DISPATCH_MODE_SUPPORT BIT1
+#define IMAGE_ATTRIBUTE_64BIT_MODE_SUPPORT BIT2
+#define FSP_IA32 0
+#define FSP_X64 1
+
+ #pragma pack(1)
+
+///
+/// FSP Information Header as described in FSP v2.0 Spec section 5.1.1.
+///
+typedef struct {
+ ///
+ /// Byte 0x00: Signature ('FSPH') for the FSP Information Header.
+ ///
+ UINT32 Signature;
+ ///
+ /// Byte 0x04: Length of the FSP Information Header.
+ ///
+ UINT32 HeaderLength;
+ ///
+ /// Byte 0x08: Reserved.
+ ///
+ UINT8 Reserved1[2];
+ ///
+ /// Byte 0x0A: Indicates compliance with a revision of this specification in the BCD format.
+ /// For revision v2.4 the value will be 0x24.
+ ///
+ UINT8 SpecVersion;
+ ///
+ /// Byte 0x0B: Revision of the FSP Information Header.
+ /// The Current value for this field is 0x7.
+ ///
+ UINT8 HeaderRevision;
+ ///
+ /// Byte 0x0C: Revision of the FSP binary.
+ /// Major.Minor.Revision.Build
+ /// If FSP HeaderRevision is <= 5, the ImageRevision can be decoded as follows:
+ /// 7 : 0 - Build Number
+ /// 15 : 8 - Revision
+ /// 23 : 16 - Minor Version
+ /// 31 : 24 - Major Version
+ /// If FSP HeaderRevision is >= 6, ImageRevision specifies the low-order bytes of the build number and revision
+ /// while ExtendedImageRevision specifies the high-order bytes of the build number and revision.
+ /// 7 : 0 - Low Byte of Build Number
+ /// 15 : 8 - Low Byte of Revision
+ /// 23 : 16 - Minor Version
+ /// 31 : 24 - Major Version
+ ///
+ UINT32 ImageRevision;
+ ///
+ /// Byte 0x10: Signature string that will help match the FSP Binary to a supported HW configuration.
+ ///
+ CHAR8 ImageId[8];
+ ///
+ /// Byte 0x18: Size of the entire FSP binary.
+ ///
+ UINT32 ImageSize;
+ ///
+ /// Byte 0x1C: FSP binary preferred base address.
+ ///
+ UINT32 ImageBase;
+ ///
+ /// Byte 0x20: Attribute for the FSP binary.
+ /// Bit 0: Graphics Support - Set to 1 when FSP supports enabling Graphics Display.
+ /// Bit 1: Dispatch Mode Support - Set to 1 when FSP supports the optional Dispatch Mode API defined in Section 7.2 and 9. This bit is only valid if FSP HeaderRevision is >= 4.
+ /// Bit 2: 64-bit mode support - Set to 1 to indicate FSP supports 64-bit long mode interfaces. Set to 0 to indicate FSP supports 32-bit mode interfaces. This bit is only valid if FSP HeaderRevision is >= 7.
+ /// Bit 3: FSP Variable Services Support - Set to 1 to indicate FSP utilizes the FSP Variable Services defined in Section 9.6 to store non-volatile data. This bit is only valid if FSP HeaderRevision is >= 7.
+ /// Bits 15:4 - Reserved
+ ///
+ UINT16 ImageAttribute;
+ ///
+ /// Byte 0x22: Attributes of the FSP Component.
+ /// Bit 0 - Build Type
+ /// 0 - Debug Build
+ /// 1 - Release Build
+ /// Bit 1 - Release Type
+ /// 0 - Test Release
+ /// 1 - Official Release
+ /// Bit 11:2 - Reserved
+ /// Bits 15:12 - Component Type
+ /// 0000 - Reserved
+ /// 0001 - FSP-T
+ /// 0010 - FSP-M
+ /// 0011 - FSP-S
+ /// 0100 - FSP-I (FSP SMM)
+ /// 0101 to 0111 - Reserved
+ /// 1000 - FSP-O
+ /// 1001 to 1111 - Reserved
+ ///
+ UINT16 ComponentAttribute;
+ ///
+ /// Byte 0x24: Offset of the FSP configuration region.
+ ///
+ UINT32 CfgRegionOffset;
+ ///
+ /// Byte 0x28: Size of the FSP configuration region.
+ ///
+ UINT32 CfgRegionSize;
+ ///
+ /// Byte 0x2C: Reserved2.
+ ///
+ UINT32 Reserved2;
+ ///
+ /// Byte 0x30: The offset for the API to setup a temporary stack till the memory is initialized.
+ ///
+ UINT32 TempRamInitEntryOffset;
+ ///
+ /// Byte 0x34: Reserved3.
+ ///
+ UINT32 Reserved3;
+ ///
+ /// Byte 0x38: The offset for the API to inform the FSP about the different stages in the boot process.
+ ///
+ UINT32 NotifyPhaseEntryOffset;
+ ///
+ /// Byte 0x3C: The offset for the API to initialize the memory.
+ ///
+ UINT32 FspMemoryInitEntryOffset;
+ ///
+ /// Byte 0x40: The offset for the API to tear down temporary RAM.
+ ///
+ UINT32 TempRamExitEntryOffset;
+ ///
+ /// Byte 0x44: The offset for the API to initialize the CPU and chipset.
+ ///
+ UINT32 FspSiliconInitEntryOffset;
+ ///
+ /// Byte 0x48: Offset for the API for the optional Multi-Phase processor and chipset initialization.
+ /// This value is only valid if FSP HeaderRevision is >= 5.
+ /// If the value is set to 0x00000000, then this API is not available in this component.
+ ///
+ UINT32 FspMultiPhaseSiInitEntryOffset;
+ ///
+ /// Byte 0x4C: Extended revision of the FSP binary.
+ /// This value is only valid if FSP HeaderRevision is >= 6.
+ /// ExtendedImageRevision specifies the high-order byte of the revision and build number in the FSP binary revision.
+ /// 7 : 0 - High Byte of Build Number
+ /// 15 : 8 - High Byte of Revision
+ /// The FSP binary build number can be decoded as follows:
+ /// Build Number = (ExtendedImageRevision[7:0] << 8) | ImageRevision[7:0]
+ /// Revision = (ExtendedImageRevision[15:8] << 8) | ImageRevision[15:8]
+ /// Minor Version = ImageRevision[23:16]
+ /// Major Version = ImageRevision[31:24]
+ ///
+ UINT16 ExtendedImageRevision;
+ ///
+ /// Byte 0x4E: Reserved4.
+ ///
+ UINT16 Reserved4;
+ ///
+ /// Byte 0x50: Offset for the API for the Multi-Phase memory initialization.
+ ///
+ UINT32 FspMultiPhaseMemInitEntryOffset;
+ ///
+ /// Byte 0x54: Offset for the API to initialize SMM.
+ ///
+ UINT32 FspSmmInitEntryOffset;
+} FSP_INFO_HEADER;
+
+///
+/// Signature of the FSP Extended Header
+///
+#define FSP_INFO_EXTENDED_HEADER_SIGNATURE SIGNATURE_32 ('F', 'S', 'P', 'E')
+
+///
+/// FSP Information Extended Header as described in FSP v2.0 Spec section 5.1.2.
+///
+typedef struct {
+ ///
+ /// Byte 0x00: Signature ('FSPE') for the FSP Extended Information Header.
+ ///
+ UINT32 Signature;
+ ///
+ /// Byte 0x04: Length of the table in bytes, including all additional FSP producer defined data.
+ ///
+ UINT32 Length;
+ ///
+ /// Byte 0x08: FSP producer defined revision of the table.
+ ///
+ UINT8 Revision;
+ ///
+ /// Byte 0x09: Reserved for future use.
+ ///
+ UINT8 Reserved;
+ ///
+ /// Byte 0x0A: FSP producer identification string
+ ///
+ CHAR8 FspProducerId[6];
+ ///
+ /// Byte 0x10: FSP producer implementation revision number. Larger numbers are assumed to be newer revisions.
+ ///
+ UINT32 FspProducerRevision;
+ ///
+ /// Byte 0x14: Size of the FSP producer defined data (n) in bytes.
+ ///
+ UINT32 FspProducerDataSize;
+ ///
+ /// Byte 0x18: FSP producer defined data of size (n) defined by FspProducerDataSize.
+ ///
+} FSP_INFO_EXTENDED_HEADER;
+
+//
+// A generic table search algorithm for additional tables can be implemented with a
+// signature search algorithm until a terminator signature 'FSPP' is found.
+//
+#define FSP_FSPP_SIGNATURE SIGNATURE_32 ('F', 'S', 'P', 'P')
+#define FSP_PATCH_TABLE_SIGNATURE FSP_FSPP_SIGNATURE
+
+///
+/// FSP Patch Table as described in FSP v2.0 Spec section 5.1.5.
+///
+typedef struct {
+ ///
+ /// Byte 0x00: FSP Patch Table Signature "FSPP".
+ ///
+ UINT32 Signature;
+ ///
+ /// Byte 0x04: Size including the PatchData.
+ ///
+ UINT16 HeaderLength;
+ ///
+ /// Byte 0x06: Revision is set to 0x01.
+ ///
+ UINT8 HeaderRevision;
+ ///
+ /// Byte 0x07: Reserved for future use.
+ ///
+ UINT8 Reserved;
+ ///
+ /// Byte 0x08: Number of entries to Patch.
+ ///
+ UINT32 PatchEntryNum;
+ ///
+ /// Byte 0x0C: Patch Data.
+ ///
+ // UINT32 PatchData[];
+} FSP_PATCH_TABLE;
+
+ #pragma pack()
+
+extern EFI_GUID gFspHeaderFileGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/IntelFsp2Pkg/Include/Guid/FspNonVolatileStorageHob2.h b/src/vendorcode/intel/edk2/edk2-stable202302/IntelFsp2Pkg/Include/Guid/FspNonVolatileStorageHob2.h
new file mode 100644
index 0000000000..279bdccd80
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/IntelFsp2Pkg/Include/Guid/FspNonVolatileStorageHob2.h
@@ -0,0 +1,24 @@
+/** @file
+ Intel FSP Non-Volatile Storage (NVS) HOB version 2 definition from
+ Intel Firmware Support Package External Architecture Specification v2.3.
+
+ Copyright (c) 2021, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __FSP_NON_VOLATILE_STORAGE_HOB2_H__
+#define __FSP_NON_VOLATILE_STORAGE_HOB2_H__
+
+///
+/// The Non-Volatile Storage (NVS) HOB version 2 provides > 64KB buffer support.
+///
+typedef struct {
+ EFI_HOB_GUID_TYPE GuidHob;
+ EFI_PHYSICAL_ADDRESS NvsDataPtr;
+ UINT64 NvsDataLength;
+} FSP_NON_VOLATILE_STORAGE_HOB2;
+
+extern EFI_GUID gFspNonVolatileStorageHob2Guid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/IntelFsp2Pkg/Include/Guid/GuidHobFspEas.h b/src/vendorcode/intel/edk2/edk2-stable202302/IntelFsp2Pkg/Include/Guid/GuidHobFspEas.h
new file mode 100644
index 0000000000..d4617c87c1
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/IntelFsp2Pkg/Include/Guid/GuidHobFspEas.h
@@ -0,0 +1,17 @@
+/** @file
+ Intel FSP Hob Guid definition from Intel Firmware Support Package External
+ Architecture Specification v2.0.
+
+ Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __GUID_HOB_FSP_EAS_GUID__
+#define __GUID_HOB_FSP_EAS_GUID__
+
+extern EFI_GUID gFspBootLoaderTolumHobGuid;
+extern EFI_GUID gFspReservedMemoryResourceHobGuid;
+extern EFI_GUID gFspNonVolatileStorageHobGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/IntelFsp2Pkg/Include/Library/CacheAsRamLib.h b/src/vendorcode/intel/edk2/edk2-stable202302/IntelFsp2Pkg/Include/Library/CacheAsRamLib.h
new file mode 100644
index 0000000000..3e5370fc15
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/IntelFsp2Pkg/Include/Library/CacheAsRamLib.h
@@ -0,0 +1,23 @@
+/** @file
+
+ Copyright (c) 2014, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _CACHE_AS_RAM_LIB_H_
+#define _CACHE_AS_RAM_LIB_H_
+
+/**
+ This function disable CAR.
+
+ @param[in] DisableCar TRUE means use INVD, FALSE means use WBINVD
+
+**/
+VOID
+EFIAPI
+DisableCacheAsRam (
+ IN BOOLEAN DisableCar
+ );
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/IntelFsp2Pkg/Include/Library/CacheLib.h b/src/vendorcode/intel/edk2/edk2-stable202302/IntelFsp2Pkg/Include/Library/CacheLib.h
new file mode 100644
index 0000000000..8f529096ea
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/IntelFsp2Pkg/Include/Library/CacheLib.h
@@ -0,0 +1,55 @@
+/** @file
+
+ Copyright (c) 2014, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _CACHE_LIB_H_
+#define _CACHE_LIB_H_
+
+//
+// EFI_MEMORY_CACHE_TYPE
+//
+typedef INT32 EFI_MEMORY_CACHE_TYPE;
+
+#define EFI_CACHE_UNCACHEABLE 0
+#define EFI_CACHE_WRITECOMBINING 1
+#define EFI_CACHE_WRITETHROUGH 4
+#define EFI_CACHE_WRITEPROTECTED 5
+#define EFI_CACHE_WRITEBACK 6
+
+/**
+ Reset all the MTRRs to a known state.
+
+ @retval EFI_SUCCESS All MTRRs have been reset successfully.
+
+**/
+EFI_STATUS
+EFIAPI
+ResetCacheAttributes (
+ VOID
+ );
+
+/**
+ Given the memory range and cache type, programs the MTRRs.
+
+ @param[in] MemoryAddress Base Address of Memory to program MTRR.
+ @param[in] MemoryLength Length of Memory to program MTRR.
+ @param[in] MemoryCacheType Cache Type.
+
+ @retval EFI_SUCCESS Mtrr are set successfully.
+ @retval EFI_LOAD_ERROR No empty MTRRs to use.
+ @retval EFI_INVALID_PARAMETER The input parameter is not valid.
+ @retval others An error occurs when setting MTTR.
+
+**/
+EFI_STATUS
+EFIAPI
+SetCacheAttributes (
+ IN EFI_PHYSICAL_ADDRESS MemoryAddress,
+ IN UINT64 MemoryLength,
+ IN EFI_MEMORY_CACHE_TYPE MemoryCacheType
+ );
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/IntelFsp2Pkg/Include/Library/DebugDeviceLib.h b/src/vendorcode/intel/edk2/edk2-stable202302/IntelFsp2Pkg/Include/Library/DebugDeviceLib.h
new file mode 100644
index 0000000000..f8611909f0
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/IntelFsp2Pkg/Include/Library/DebugDeviceLib.h
@@ -0,0 +1,23 @@
+/** @file
+
+ Copyright (c) 2014, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __DEBUG_DEVICE_LIB_H__
+#define __DEBUG_DEVICE_LIB_H__
+
+/**
+ Returns the debug print device enable state.
+
+ @return Debug print device enable state.
+
+**/
+UINT8
+EFIAPI
+GetDebugPrintDeviceEnable (
+ VOID
+ );
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/IntelFsp2Pkg/Include/Library/FspCommonLib.h b/src/vendorcode/intel/edk2/edk2-stable202302/IntelFsp2Pkg/Include/Library/FspCommonLib.h
new file mode 100644
index 0000000000..32379c3068
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/IntelFsp2Pkg/Include/Library/FspCommonLib.h
@@ -0,0 +1,308 @@
+/** @file
+
+ Copyright (c) 2014 - 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _FSP_COMMON_LIB_H_
+#define _FSP_COMMON_LIB_H_
+
+#include
+#include
+
+/**
+ This function sets the FSP global data pointer.
+
+ @param[in] FspData Fsp global data pointer.
+
+**/
+VOID
+EFIAPI
+SetFspGlobalDataPointer (
+ IN FSP_GLOBAL_DATA *FspData
+ );
+
+/**
+ This function gets the FSP global data pointer.
+
+**/
+FSP_GLOBAL_DATA *
+EFIAPI
+GetFspGlobalDataPointer (
+ VOID
+ );
+
+/**
+ This function gets back the FSP API first parameter passed by the bootloader.
+
+ @retval ApiParameter FSP API first parameter passed by the bootloader.
+**/
+UINTN
+EFIAPI
+GetFspApiParameter (
+ VOID
+ );
+
+/**
+ This function gets back the FSP API second parameter passed by the bootloader.
+
+ @retval ApiParameter FSP API second parameter passed by the bootloader.
+**/
+UINTN
+EFIAPI
+GetFspApiParameter2 (
+ VOID
+ );
+
+/**
+ This function returns the FSP entry stack pointer from address of the first API parameter.
+
+ @retval FSP entry stack pointer.
+**/
+VOID *
+EFIAPI
+GetFspEntryStack (
+ VOID
+ );
+
+/**
+ This function sets the FSP API parameter in the stack.
+
+ @param[in] Value New parameter value.
+
+**/
+VOID
+EFIAPI
+SetFspApiParameter (
+ IN UINT32 Value
+ );
+
+/**
+ This function set the API status code returned to the BootLoader.
+
+ @param[in] ReturnStatus Status code to return.
+
+**/
+VOID
+EFIAPI
+SetFspApiReturnStatus (
+ IN UINTN ReturnStatus
+ );
+
+/**
+ This function sets the context switching stack to a new stack frame.
+
+ @param[in] NewStackTop New core stack to be set.
+
+**/
+VOID
+EFIAPI
+SetFspCoreStackPointer (
+ IN VOID *NewStackTop
+ );
+
+/**
+ This function sets the platform specific data pointer.
+
+ @param[in] PlatformData Fsp platform specific data pointer.
+
+**/
+VOID
+EFIAPI
+SetFspPlatformDataPointer (
+ IN VOID *PlatformData
+ );
+
+/**
+ This function gets the platform specific data pointer.
+
+ @param[in] PlatformData Fsp platform specific data pointer.
+
+**/
+VOID *
+EFIAPI
+GetFspPlatformDataPointer (
+ VOID
+ );
+
+/**
+ This function sets the UPD data pointer.
+
+ @param[in] UpdDataPtr UPD data pointer.
+**/
+VOID
+EFIAPI
+SetFspUpdDataPointer (
+ IN VOID *UpdDataPtr
+ );
+
+/**
+ This function gets the UPD data pointer.
+
+ @return UpdDataPtr UPD data pointer.
+**/
+VOID *
+EFIAPI
+GetFspUpdDataPointer (
+ VOID
+ );
+
+/**
+ This function sets the memory init UPD data pointer.
+
+ @param[in] MemoryInitUpdPtr memory init UPD data pointer.
+**/
+VOID
+EFIAPI
+SetFspMemoryInitUpdDataPointer (
+ IN VOID *MemoryInitUpdPtr
+ );
+
+/**
+ This function gets the memory init UPD data pointer.
+
+ @return memory init UPD data pointer.
+**/
+VOID *
+EFIAPI
+GetFspMemoryInitUpdDataPointer (
+ VOID
+ );
+
+/**
+ This function sets the silicon init UPD data pointer.
+
+ @param[in] SiliconInitUpdPtr silicon init UPD data pointer.
+**/
+VOID
+EFIAPI
+SetFspSiliconInitUpdDataPointer (
+ IN VOID *SiliconInitUpdPtr
+ );
+
+/**
+ This function gets the silicon init UPD data pointer.
+
+ @return silicon init UPD data pointer.
+**/
+VOID *
+EFIAPI
+GetFspSiliconInitUpdDataPointer (
+ VOID
+ );
+
+/**
+ Set FSP measurement point timestamp.
+
+ @param[in] Id Measurement point ID.
+
+ @return performance timestamp.
+**/
+UINT64
+EFIAPI
+SetFspMeasurePoint (
+ IN UINT8 Id
+ );
+
+/**
+ This function gets the FSP info header pointer.
+
+ @retval FspInfoHeader FSP info header pointer
+**/
+FSP_INFO_HEADER *
+EFIAPI
+GetFspInfoHeader (
+ VOID
+ );
+
+/**
+ This function sets the FSP info header pointer.
+
+ @param[in] FspInfoHeader FSP info header pointer
+**/
+VOID
+EFIAPI
+SetFspInfoHeader (
+ FSP_INFO_HEADER *FspInfoHeader
+ );
+
+/**
+ This function gets the FSP info header pointer from the API context.
+
+ @retval FspInfoHeader FSP info header pointer
+**/
+FSP_INFO_HEADER *
+EFIAPI
+GetFspInfoHeaderFromApiContext (
+ VOID
+ );
+
+/**
+ This function gets the CfgRegion data pointer.
+
+ @return CfgRegion data pointer.
+**/
+VOID *
+EFIAPI
+GetFspCfgRegionDataPointer (
+ VOID
+ );
+
+/**
+ This function gets FSP API calling mode.
+
+ @retval API calling mode
+**/
+UINT8
+EFIAPI
+GetFspApiCallingIndex (
+ VOID
+ );
+
+/**
+ This function sets FSP API calling mode.
+
+ @param[in] Index API calling index
+**/
+VOID
+EFIAPI
+SetFspApiCallingIndex (
+ UINT8 Index
+ );
+
+/**
+ This function gets FSP Phase StatusCode.
+
+ @retval StatusCode
+**/
+UINT32
+EFIAPI
+GetPhaseStatusCode (
+ VOID
+ );
+
+/**
+ This function sets FSP Phase StatusCode.
+
+ @param[in] Mode Phase StatusCode
+**/
+VOID
+EFIAPI
+SetPhaseStatusCode (
+ UINT32 StatusCode
+ );
+
+/**
+ This function updates the return status of the FSP API with requested reset type and returns to Boot Loader.
+
+ @param[in] FspResetType Reset type that needs to returned as API return status
+
+**/
+VOID
+EFIAPI
+FspApiReturnStatusReset (
+ IN EFI_STATUS FspResetType
+ );
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/IntelFsp2Pkg/Include/Library/FspMultiPhaseLib.h b/src/vendorcode/intel/edk2/edk2-stable202302/IntelFsp2Pkg/Include/Library/FspMultiPhaseLib.h
new file mode 100644
index 0000000000..378c1c7337
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/IntelFsp2Pkg/Include/Library/FspMultiPhaseLib.h
@@ -0,0 +1,55 @@
+/** @file
+ FSP MultiPhase Library.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _FSP_MULTIPHASE_LIB_H_
+#define _FSP_MULTIPHASE_LIB_H_
+
+EFI_STATUS
+EFIAPI
+FspMultiPhaseSwitchStack (
+ );
+
+EFI_STATUS
+EFIAPI
+FspVariableRequestSwitchStack (
+ IN FSP_MULTI_PHASE_VARIABLE_REQUEST_INFO_PARAMS *FspVariableRequestParams
+ );
+
+/**
+ This function handles FspMultiPhaseMemInitApi.
+
+ @param[in] ApiIdx Internal index of the FSP API.
+ @param[in] ApiParam Parameter of the FSP API.
+
+ @retval EFI_SUCCESS FSP execution was successful.
+ @retval EFI_INVALID_PARAMETER Input parameters are invalid.
+ @retval EFI_UNSUPPORTED The FSP calling conditions were not met.
+ @retval EFI_DEVICE_ERROR FSP initialization failed.
+**/
+EFI_STATUS
+EFIAPI
+FspMultiPhaseMemInitApiHandler (
+ IN UINT32 ApiIdx,
+ IN VOID *ApiParam
+ );
+
+/**
+ This function handles FspMultiPhaseSiInitApi.
+
+ @param[in] ApiIdx Internal index of the FSP API.
+ @param[in] ApiParam Parameter of the FSP API.
+
+**/
+EFI_STATUS
+EFIAPI
+FspMultiPhaseSiInitApiHandlerV2 (
+ IN UINT32 ApiIdx,
+ IN VOID *ApiParam
+ );
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/IntelFsp2Pkg/Include/Library/FspPlatformLib.h b/src/vendorcode/intel/edk2/edk2-stable202302/IntelFsp2Pkg/Include/Library/FspPlatformLib.h
new file mode 100644
index 0000000000..bb1a649121
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/IntelFsp2Pkg/Include/Library/FspPlatformLib.h
@@ -0,0 +1,124 @@
+/** @file
+
+ Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _FSP_PLATFORM_LIB_H_
+#define _FSP_PLATFORM_LIB_H_
+
+/**
+ Get system memory resource descriptor by owner.
+
+ @param[in] OwnerGuid resource owner guid
+**/
+EFI_HOB_RESOURCE_DESCRIPTOR *
+EFIAPI
+FspGetResourceDescriptorByOwner (
+ IN EFI_GUID *OwnerGuid
+ );
+
+/**
+ Get system memory from HOB.
+
+ @param[in,out] LowMemoryLength less than 4G memory length
+ @param[in,out] HighMemoryLength greater than 4G memory length
+**/
+VOID
+EFIAPI
+FspGetSystemMemorySize (
+ IN OUT UINT64 *LowMemoryLength,
+ IN OUT UINT64 *HighMemoryLength
+ );
+
+/**
+ Set a new stack frame for the continuation function.
+
+**/
+VOID
+EFIAPI
+FspSetNewStackFrame (
+ VOID
+ );
+
+/**
+ This function transfer control back to BootLoader after FspSiliconInit.
+
+**/
+VOID
+EFIAPI
+FspSiliconInitDone (
+ VOID
+ );
+
+/**
+ This function returns control to BootLoader after MemoryInitApi.
+
+ @param[in,out] HobListPtr The address of HobList pointer.
+**/
+VOID
+EFIAPI
+FspMemoryInitDone (
+ IN OUT VOID **HobListPtr
+ );
+
+/**
+ This function returns control to BootLoader after TempRamExitApi.
+
+**/
+VOID
+EFIAPI
+FspTempRamExitDone (
+ VOID
+ );
+
+/**
+ This function handle NotifyPhase API call from the BootLoader.
+ It gives control back to the BootLoader after it is handled. If the
+ Notification code is a ReadyToBoot event, this function will return
+ and FSP continues the remaining execution until it reaches the DxeIpl.
+
+**/
+VOID
+EFIAPI
+FspWaitForNotify (
+ VOID
+ );
+
+/**
+ This function transfer control back to BootLoader after FspSiliconInit.
+
+ @param[in] Status return status for the FspSiliconInit.
+**/
+VOID
+EFIAPI
+FspSiliconInitDone2 (
+ IN EFI_STATUS Status
+ );
+
+/**
+ This function returns control to BootLoader after MemoryInitApi.
+
+ @param[in] Status return status for the MemoryInitApi.
+ @param[in,out] HobListPtr The address of HobList pointer.
+**/
+VOID
+EFIAPI
+FspMemoryInitDone2 (
+ IN EFI_STATUS Status,
+ IN OUT VOID **HobListPtr
+ );
+
+/**
+ This function returns control to BootLoader after TempRamExitApi.
+
+ @param[in] Status return status for the TempRamExitApi.
+**/
+VOID
+EFIAPI
+FspTempRamExitDone2 (
+ IN EFI_STATUS Status
+ );
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/IntelFsp2Pkg/Include/Library/FspSecPlatformLib.h b/src/vendorcode/intel/edk2/edk2-stable202302/IntelFsp2Pkg/Include/Library/FspSecPlatformLib.h
new file mode 100644
index 0000000000..ac4e4315f4
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/IntelFsp2Pkg/Include/Library/FspSecPlatformLib.h
@@ -0,0 +1,119 @@
+/** @file
+
+ Copyright (c) 2015 - 2020, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _FSP_SEC_PLATFORM_LIB_H_
+#define _FSP_SEC_PLATFORM_LIB_H_
+
+/**
+ This function performs platform level initialization.
+
+ This function must be in ASM file, because stack is not established yet.
+ This function is optional. If a library instance does not provide this function, the default empty one will be used.
+
+ The callee should not use XMM6/XMM7.
+ The return address is saved in MM7.
+
+ @retval in saved in EAX/RAX - 0 means platform initialization success.
+ other means platform initialization fail.
+**/
+UINTN
+EFIAPI
+SecPlatformInit (
+ VOID
+ );
+
+/**
+ This function loads Microcode.
+
+ This function must be in ASM file, because stack is not established yet.
+ This function is optional. If a library instance does not provide this function, the default one will be used.
+
+ The callee should not use XMM6/XMM7.
+ The return address is saved in MM7.
+
+ @param[in] FsptUpdDataPtr Address pointer to the FSPT_UPD data structure. It is saved in ESP.
+
+ @retval in saved in EAX/RAX - 0 means Microcode is loaded successfully.
+ other means Microcode is not loaded successfully.
+**/
+UINTN
+EFIAPI
+LoadMicrocode (
+ IN VOID *FsptUpdDataPtr
+ );
+
+/**
+ This function initializes the CAR.
+
+ This function must be in ASM file, because stack is not established yet.
+
+ The callee should not use XMM6/XMM7.
+ The return address is saved in MM7.
+
+ @param[in] FsptUpdDataPtr Address pointer to the FSPT_UPD data structure. It is saved in ESP.
+
+ @retval in saved in EAX/RAX - 0 means CAR initialization success.
+ other means CAR initialization fail.
+**/
+UINTN
+EFIAPI
+SecCarInit (
+ IN VOID *FsptUpdDataPtr
+ );
+
+/**
+ This function check the signature of UPD.
+
+ @param[in] ApiIdx Internal index of the FSP API.
+ @param[in] ApiParam Parameter of the FSP API.
+
+**/
+EFI_STATUS
+EFIAPI
+FspUpdSignatureCheck (
+ IN UINT32 ApiIdx,
+ IN VOID *ApiParam
+ );
+
+/**
+ This function handles FspMultiPhaseSiInitApi.
+ Starting from FSP 2.4 this function is obsolete and FspMultiPhaseSiInitApiHandlerV2 is the replacement.
+
+ @param[in] ApiIdx Internal index of the FSP API.
+ @param[in] ApiParam Parameter of the FSP API.
+
+**/
+EFI_STATUS
+EFIAPI
+FspMultiPhaseSiInitApiHandler (
+ IN UINT32 ApiIdx,
+ IN VOID *ApiParam
+ );
+
+/**
+ FSP MultiPhase Platform Get Number Of Phases Function.
+
+ Allows an FSP binary to dynamically update the number of phases at runtime.
+ For example, UPD settings could negate the need to enter the multi-phase flow
+ in certain scenarios. If this function returns FALSE, the default number of phases
+ provided by PcdMultiPhaseNumberOfPhases will be returned to the bootloader instead.
+
+ @param[in] ApiIdx - Internal index of the FSP API.
+ @param[in] NumberOfPhasesSupported - How many phases are supported by current FSP Component.
+
+ @retval TRUE - NumberOfPhases are modified by Platform during runtime.
+ @retval FALSE - The Default build time NumberOfPhases should be used.
+
+**/
+BOOLEAN
+EFIAPI
+FspMultiPhasePlatformGetNumberOfPhases (
+ IN UINTN ApiIdx,
+ IN OUT UINT32 *NumberOfPhasesSupported
+ );
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/IntelFsp2Pkg/Include/Library/FspSwitchStackLib.h b/src/vendorcode/intel/edk2/edk2-stable202302/IntelFsp2Pkg/Include/Library/FspSwitchStackLib.h
new file mode 100644
index 0000000000..d2a737a4f0
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/IntelFsp2Pkg/Include/Library/FspSwitchStackLib.h
@@ -0,0 +1,55 @@
+/** @file
+
+ Copyright (c) 2014 - 2020, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _FSP_SWITCH_STACK_LIB_H_
+#define _FSP_SWITCH_STACK_LIB_H_
+
+/**
+
+ This function will switch the current stack to the previous saved stack.
+ Before calling the previous stack has to be set in FSP_GLOBAL_DATA.CoreStack.
+ EIP
+ FLAGS 16 bit FLAGS 16 bit
+ EDI
+ ESI
+ EBP
+ ESP
+ EBX
+ EDX
+ ECX
+ EAX
+ DWORD IDT base1
+ StackPointer: DWORD IDT base2
+
+ @return ReturnKey After switching to the saved stack,
+ this value will be saved in eax before returning.
+
+
+**/
+EFI_STATUS
+EFIAPI
+Pei2LoaderSwitchStack (
+ VOID
+ );
+
+/**
+
+ This function is equivalent to Pei2LoaderSwitchStack () but just indicates
+ the stack after switched is FSP stack.
+
+ @return ReturnKey After switching to the saved stack,
+ this value will be saved in eax before returning.
+
+
+**/
+EFI_STATUS
+EFIAPI
+Loader2PeiSwitchStack (
+ VOID
+ );
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/IntelFsp2Pkg/Include/Ppi/FspmArchConfigPpi.h b/src/vendorcode/intel/edk2/edk2-stable202302/IntelFsp2Pkg/Include/Ppi/FspmArchConfigPpi.h
new file mode 100644
index 0000000000..67a335e449
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/IntelFsp2Pkg/Include/Ppi/FspmArchConfigPpi.h
@@ -0,0 +1,47 @@
+/** @file
+ Header file for FSP-M Arch Config PPI for Dispatch mode
+
+ Copyright (c) 2019, Intel Corporation. All rights reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _FSPM_ARCH_CONFIG_PPI_H_
+#define _FSPM_ARCH_CONFIG_PPI_H_
+
+#define FSPM_ARCH_CONFIG_PPI_REVISION 0x1
+
+///
+/// Global ID for the FSPM_ARCH_CONFIG_PPI.
+///
+#define FSPM_ARCH_CONFIG_GUID \
+ { \
+ 0x824d5a3a, 0xaf92, 0x4c0c, { 0x9f, 0x19, 0x19, 0x52, 0x6d, 0xca, 0x4a, 0xbb } \
+ }
+
+///
+/// This PPI provides FSP-M Arch Config PPI.
+///
+typedef struct {
+ ///
+ /// Revision of the structure
+ ///
+ UINT8 Revision;
+ UINT8 Reserved[3];
+ ///
+ /// Pointer to the non-volatile storage (NVS) data buffer.
+ /// If it is NULL it indicates the NVS data is not available.
+ ///
+ VOID *NvsBufferPtr;
+ ///
+ /// Size of memory to be reserved by FSP below "top
+ /// of low usable memory" for bootloader usage.
+ ///
+ UINT32 BootLoaderTolumSize;
+ UINT8 Reserved1[4];
+} FSPM_ARCH_CONFIG_PPI;
+
+extern EFI_GUID gFspmArchConfigPpiGuid;
+
+#endif // _FSPM_ARCH_CONFIG_PPI_H_
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/IntelFsp2Pkg/Include/Ppi/TempRamExitPpi.h b/src/vendorcode/intel/edk2/edk2-stable202302/IntelFsp2Pkg/Include/Ppi/TempRamExitPpi.h
new file mode 100644
index 0000000000..c1e874cd30
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/IntelFsp2Pkg/Include/Ppi/TempRamExitPpi.h
@@ -0,0 +1,52 @@
+/** @file
+ This file defines the Silicon Temp Ram Exit PPI which implements the
+ required programming steps for disabling temporary memory.
+
+Copyright (c) 2019, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _FSP_TEMP_RAM_EXIT_PPI_H_
+#define _FSP_TEMP_RAM_EXIT_PPI_H_
+
+///
+/// Global ID for the FSP_TEMP_RAM_EXIT_PPI.
+///
+#define FSP_TEMP_RAM_EXIT_GUID \
+ { \
+ 0xbc1cfbdb, 0x7e50, 0x42be, { 0xb4, 0x87, 0x22, 0xe0, 0xa9, 0x0c, 0xb0, 0x52 } \
+ }
+
+//
+// Forward declaration for the FSP_TEMP_RAM_EXIT_PPI.
+//
+typedef struct _FSP_TEMP_RAM_EXIT_PPI FSP_TEMP_RAM_EXIT_PPI;
+
+/**
+ Silicon function for disabling temporary memory.
+ @param[in] TempRamExitParamPtr - Pointer to the TempRamExit parameters structure.
+ This structure is normally defined in the Integration
+ Guide. If it is not defined in the Integration Guide,
+ pass NULL.
+ @retval EFI_SUCCESS - FSP execution environment was initialized successfully.
+ @retval EFI_INVALID_PARAMETER - Input parameters are invalid.
+ @retval EFI_UNSUPPORTED - The FSP calling conditions were not met.
+ @retval EFI_DEVICE_ERROR - Temporary memory exit.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *FSP_TEMP_RAM_EXIT)(
+ IN VOID *TempRamExitParamPtr
+ );
+
+///
+/// This PPI provides function to disable temporary memory.
+///
+struct _FSP_TEMP_RAM_EXIT_PPI {
+ FSP_TEMP_RAM_EXIT TempRamExit;
+};
+
+extern EFI_GUID gFspTempRamExitPpiGuid;
+
+#endif // _FSP_TEMP_RAM_EXIT_PPI_H_
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/IntelFsp2Pkg/Include/Ppi/Variable.h b/src/vendorcode/intel/edk2/edk2-stable202302/IntelFsp2Pkg/Include/Ppi/Variable.h
new file mode 100644
index 0000000000..b1f2a95e2c
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/IntelFsp2Pkg/Include/Ppi/Variable.h
@@ -0,0 +1,195 @@
+/** @file
+ EDKII PEI Variable PPI provides an implementation of variables
+ intended for use as a means to store data in the PEI environment.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef EDKII_PEI_VARIABLE_PPI_H_
+#define EDKII_PEI_VARIABLE_PPI_H_
+
+#define EDKII_PEI_VARIABLE_PPI_GUID \
+ { \
+ 0xe7b2cd04, 0x4b14, 0x44c2, { 0xb7, 0x48, 0xce, 0xaf, 0x2b, 0x66, 0x4a, 0xb0 } \
+ }
+
+typedef struct _EDKII_PEI_VARIABLE_PPI EDKII_PEI_VARIABLE_PPI;
+
+/**
+ This service retrieves a variable's value using its name and GUID.
+
+ Read the specified variable from the UEFI variable store. If the Data
+ buffer is too small to hold the contents of the variable,
+ the error EFI_BUFFER_TOO_SMALL is returned and DataSize is set to the
+ required buffer size to obtain the data.
+
+ @param[in] This A pointer to this instance of the EDKII_PEI_VARIABLE_PPI.
+ @param[in] VariableName A pointer to a null-terminated string that is the variable's name.
+ @param[in] VariableGuid A pointer to an EFI_GUID that is the variable's GUID. The combination of
+ VariableGuid and VariableName must be unique.
+ @param[out] Attributes If non-NULL, on return, points to the variable's attributes.
+ @param[in, out] DataSize On entry, points to the size in bytes of the Data buffer.
+ On return, points to the size of the data returned in Data.
+ @param[out] Data Points to the buffer which will hold the returned variable value.
+ May be NULL with a zero DataSize in order to determine the size of the
+ buffer needed.
+
+ @retval EFI_SUCCESS The variable was read successfully.
+ @retval EFI_NOT_FOUND The variable was not found.
+ @retval EFI_BUFFER_TOO_SMALL The DataSize is too small for the resulting data.
+ DataSize is updated with the size required for
+ the specified variable.
+ @retval EFI_INVALID_PARAMETER VariableName, VariableGuid, DataSize or Data is NULL.
+ @retval EFI_DEVICE_ERROR The variable could not be retrieved because of a device error.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EDKII_PEI_GET_VARIABLE)(
+ IN CONST EDKII_PEI_VARIABLE_PPI *This,
+ IN CONST CHAR16 *VariableName,
+ IN CONST EFI_GUID *VariableGuid,
+ OUT UINT32 *Attributes OPTIONAL,
+ IN OUT UINTN *DataSize,
+ OUT VOID *Data OPTIONAL
+ );
+
+/**
+ Return the next variable name and GUID.
+
+ This function is called multiple times to retrieve the VariableName
+ and VariableGuid of all variables currently available in the system.
+ On each call, the previous results are passed into the interface,
+ and, on return, the interface returns the data for the next
+ variable. To get started, VariableName should initially contain L"\0"
+ and VariableNameSize should be sizeof(CHAR16). When the entire
+ variable list has been returned, EFI_NOT_FOUND is returned.
+
+ @param[in] This A pointer to this instance of the EDKII_PEI_VARIABLE_PPI.
+ @param[in, out] VariableNameSize On entry, points to the size of the buffer pointed to by VariableName.
+ On return, the size of the variable name buffer.
+ @param[in, out] VariableName On entry, a pointer to a null-terminated string that is the variable's name.
+ On return, points to the next variable's null-terminated name string.
+ @param[in, out] VariableGuid On entry, a pointer to an EFI_GUID that is the variable's GUID.
+ On return, a pointer to the next variable's GUID.
+
+ @retval EFI_SUCCESS The next variable name was read successfully.
+ @retval EFI_NOT_FOUND All variables have been enumerated.
+ @retval EFI_BUFFER_TOO_SMALL The VariableNameSize is too small for the resulting
+ data. VariableNameSize is updated with the size
+ required for the specified variable.
+ @retval EFI_INVALID_PARAMETER VariableName, VariableGuid or
+ VariableNameSize is NULL.
+ @retval EFI_DEVICE_ERROR The variable could not be retrieved because of a device error.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EDKII_PEI_GET_NEXT_VARIABLE_NAME)(
+ IN CONST EDKII_PEI_VARIABLE_PPI *This,
+ IN OUT UINTN *VariableNameSize,
+ IN OUT CHAR16 *VariableName,
+ IN OUT EFI_GUID *VariableGuid
+ );
+
+/**
+ Sets the value of a variable.
+
+ @param[in] This A pointer to this instance of the EDKII_PEI_VARIABLE_PPI.
+ @param[in] VariableName A Null-terminated string that is the name of the vendor's variable.
+ Each VariableName is unique for each VendorGuid. VariableName must
+ contain 1 or more characters. If VariableName is an empty string,
+ then EFI_INVALID_PARAMETER is returned.
+ @param[in] VendorGuid A unique identifier for the vendor.
+ @param[in] Attributes Attributes bitmask to set for the variable.
+ @param[in] DataSize The size in bytes of the Data buffer. Unless the EFI_VARIABLE_APPEND_WRITE
+ attribute is set, a size of zero causes the variable to be deleted. When the
+ EFI_VARIABLE_APPEND_WRITE attribute is set, then a SetVariable() call with a
+ DataSize of zero will not cause any change to the variable value.
+ @param[in] Data The contents for the variable.
+
+ @retval EFI_SUCCESS The firmware has successfully stored the variable and its data as
+ defined by the Attributes.
+ @retval EFI_INVALID_PARAMETER An invalid combination of attribute bits, name, and GUID was supplied, or the
+ DataSize exceeds the maximum allowed.
+ @retval EFI_INVALID_PARAMETER VariableName is an empty string.
+ @retval EFI_OUT_OF_RESOURCES Not enough storage is available to hold the variable and its data.
+ @retval EFI_DEVICE_ERROR The variable could not be stored due to a hardware error.
+ @retval EFI_WRITE_PROTECTED The variable in question is read-only.
+ @retval EFI_WRITE_PROTECTED The variable in question cannot be deleted.
+ @retval EFI_SECURITY_VIOLATION The variable could not be written due to EFI_VARIABLE_AUTHENTICATED_WRITE_ACCESS,
+ or EFI_VARIABLE_TIME_BASED_AUTHENTICATED_WRITE_ACCESS, or
+ EFI_VARIABLE_ENHANCED_AUTHENTICATED_ACCESS being set. Writing to authenticated
+ variables is not supported in the PEI environment. Updates to authenticated
+ variables can be requested during PEI via the EFI_AUTHENTICATED_VARIABLE_HOB, but
+ these updates won't be written to non-volatile storage until later in DXE.
+ The EFI_AUTHENTICATED_VARIABLE_HOB is a HOB with the GUID
+ gEfiAuthenticatedVariableGuid. This HOB contains a VARIABLE_STORE_HEADER followed
+ by one or more UEFI variables, which are stored as DWORD aligned tuples of
+ (VARIABLE_HEADER + CHAR16 VariableName + VariableData).
+ See MdeModulePkg/Include/Guid/VariableFormat.h for these data structure
+ definitions and MdeModulePkg/Universal/Variable/RuntimeDxe/VariableParsing.c for
+ an example of how to parse these data structures.
+ @retval EFI_NOT_FOUND The variable trying to be updated or deleted was not found.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EDKII_PEI_SET_VARIABLE)(
+ IN CONST EDKII_PEI_VARIABLE_PPI *This,
+ IN CHAR16 *VariableName,
+ IN EFI_GUID *VendorGuid,
+ IN UINT32 Attributes,
+ IN UINTN DataSize,
+ IN VOID *Data
+ );
+
+/**
+ Returns information about the UEFI variables.
+
+ @param[in] This A pointer to this instance of the EDKII_PEI_VARIABLE_PPI.
+ @param[in] Attributes Attributes bitmask to specify the type of variables on
+ which to return information.
+ @param[out] MaximumVariableStorageSize On output the maximum size of the storage space
+ available for the EFI variables associated with the
+ attributes specified.
+ @param[out] RemainingVariableStorageSize Returns the remaining size of the storage space
+ available for the EFI variables associated with the
+ attributes specified.
+ @param[out] MaximumVariableSize Returns the maximum size of the individual EFI
+ variables associated with the attributes specified.
+
+ @retval EFI_SUCCESS Valid answer returned.
+ @retval EFI_INVALID_PARAMETER An invalid combination of attribute bits was supplied
+ @retval EFI_UNSUPPORTED The attribute is not supported on this platform, and the
+ MaximumVariableStorageSize,
+ RemainingVariableStorageSize, MaximumVariableSize
+ are undefined.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EDKII_PEI_QUERY_VARIABLE_INFO)(
+ IN CONST EDKII_PEI_VARIABLE_PPI *This,
+ IN UINT32 Attributes,
+ OUT UINT64 *MaximumVariableStorageSize,
+ OUT UINT64 *RemainingVariableStorageSize,
+ OUT UINT64 *MaximumVariableSize
+ );
+
+///
+/// PEI Variable PPI is intended for use as a means
+/// to store data in the PEI environment.
+///
+struct _EDKII_PEI_VARIABLE_PPI {
+ EDKII_PEI_GET_VARIABLE GetVariable;
+ EDKII_PEI_GET_NEXT_VARIABLE_NAME GetNextVariableName;
+ EDKII_PEI_SET_VARIABLE SetVariable;
+ EDKII_PEI_QUERY_VARIABLE_INFO QueryVariableInfo;
+};
+
+extern EFI_GUID gEdkiiPeiVariablePpiGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/AArch64/ProcessorBind.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/AArch64/ProcessorBind.h
new file mode 100644
index 0000000000..fa7d1db5d4
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/AArch64/ProcessorBind.h
@@ -0,0 +1,207 @@
+/** @file
+ Processor or Compiler specific defines and types for AArch64.
+
+ Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
+ Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __PROCESSOR_BIND_H__
+#define __PROCESSOR_BIND_H__
+
+///
+/// Define the processor type so other code can make processor based choices
+///
+#define MDE_CPU_AARCH64
+
+//
+// Make sure we are using the correct packing rules per EFI specification
+//
+#if !defined (__GNUC__) && !defined (__ASSEMBLER__)
+ #pragma pack()
+#endif
+
+#if defined (_MSC_EXTENSIONS)
+
+//
+// Disable some level 4 compilation warnings (same as IA32 and X64)
+//
+
+//
+// Disabling bitfield type checking warnings.
+//
+ #pragma warning ( disable : 4214 )
+
+//
+// Disabling the unreferenced formal parameter warnings.
+//
+ #pragma warning ( disable : 4100 )
+
+//
+// Disable slightly different base types warning as CHAR8 * can not be set
+// to a constant string.
+//
+ #pragma warning ( disable : 4057 )
+
+//
+// ASSERT(FALSE) or while (TRUE) are legal constructs so suppress this warning
+//
+ #pragma warning ( disable : 4127 )
+
+//
+// This warning is caused by functions defined but not used. For precompiled header only.
+//
+ #pragma warning ( disable : 4505 )
+
+//
+// This warning is caused by empty (after preprocessing) source file. For precompiled header only.
+//
+ #pragma warning ( disable : 4206 )
+
+//
+// Disable 'potentially uninitialized local variable X used' warnings
+//
+ #pragma warning ( disable : 4701 )
+
+//
+// Disable 'potentially uninitialized local pointer variable X used' warnings
+//
+ #pragma warning ( disable : 4703 )
+
+//
+// use Microsoft* C compiler dependent integer width types
+//
+typedef unsigned __int64 UINT64;
+typedef __int64 INT64;
+typedef unsigned __int32 UINT32;
+typedef __int32 INT32;
+typedef unsigned short UINT16;
+typedef unsigned short CHAR16;
+typedef short INT16;
+typedef unsigned char BOOLEAN;
+typedef unsigned char UINT8;
+typedef char CHAR8;
+typedef signed char INT8;
+
+#else
+
+//
+// Assume standard AARCH64 alignment.
+//
+typedef unsigned long long UINT64;
+typedef long long INT64;
+typedef unsigned int UINT32;
+typedef int INT32;
+typedef unsigned short UINT16;
+typedef unsigned short CHAR16;
+typedef short INT16;
+typedef unsigned char BOOLEAN;
+typedef unsigned char UINT8;
+typedef char CHAR8;
+typedef signed char INT8;
+
+#endif
+
+///
+/// Unsigned value of native width. (4 bytes on supported 32-bit processor instructions,
+/// 8 bytes on supported 64-bit processor instructions)
+///
+typedef UINT64 UINTN;
+
+///
+/// Signed value of native width. (4 bytes on supported 32-bit processor instructions,
+/// 8 bytes on supported 64-bit processor instructions)
+///
+typedef INT64 INTN;
+
+//
+// Processor specific defines
+//
+
+///
+/// A value of native width with the highest bit set.
+///
+#define MAX_BIT 0x8000000000000000ULL
+
+///
+/// A value of native width with the two highest bits set.
+///
+#define MAX_2_BITS 0xC000000000000000ULL
+
+///
+/// Maximum legal AARCH64 address
+///
+#define MAX_ADDRESS 0xFFFFFFFFFFFFFFFFULL
+
+///
+/// Maximum usable address at boot time (48 bits using 4 KB pages)
+///
+#define MAX_ALLOC_ADDRESS 0xFFFFFFFFFFFFULL
+
+///
+/// Maximum legal AArch64 INTN and UINTN values.
+///
+#define MAX_INTN ((INTN)0x7FFFFFFFFFFFFFFFULL)
+#define MAX_UINTN ((UINTN)0xFFFFFFFFFFFFFFFFULL)
+
+///
+/// Minimum legal AArch64 INTN value.
+///
+#define MIN_INTN (((INTN)-9223372036854775807LL) - 1)
+
+///
+/// The stack alignment required for AARCH64
+///
+#define CPU_STACK_ALIGNMENT 16
+
+///
+/// Page allocation granularity for AARCH64
+///
+#define DEFAULT_PAGE_ALLOCATION_GRANULARITY (0x1000)
+#define RUNTIME_PAGE_ALLOCATION_GRANULARITY (0x10000)
+
+//
+// Modifier to ensure that all protocol member functions and EFI intrinsics
+// use the correct C calling convention. All protocol member functions and
+// EFI intrinsics are required to modify their member functions with EFIAPI.
+//
+#define EFIAPI
+
+// When compiling with Clang, we still use GNU as for the assembler, so we still
+// need to define the GCC_ASM* macros.
+#if defined (__GNUC__) || defined (__clang__)
+///
+/// For GNU assembly code, .global or .globl can declare global symbols.
+/// Define this macro to unify the usage.
+///
+#define ASM_GLOBAL .globl
+
+#define GCC_ASM_EXPORT(func__) \
+ .global _CONCATENATE (__USER_LABEL_PREFIX__, func__) ;\
+ .type ASM_PFX(func__), %function
+
+#define GCC_ASM_IMPORT(func__) \
+ .extern _CONCATENATE (__USER_LABEL_PREFIX__, func__)
+
+#endif
+
+/**
+ Return the pointer to the first instruction of a function given a function pointer.
+ On ARM CPU architectures, these two pointer values are the same,
+ so the implementation of this macro is very simple.
+
+ @param FunctionPointer A pointer to a function.
+
+ @return The pointer to the first instruction of a function given a function pointer.
+
+**/
+#define FUNCTION_ENTRY_POINT(FunctionPointer) (VOID *)(UINTN)(FunctionPointer)
+
+#ifndef __USER_LABEL_PREFIX__
+#define __USER_LABEL_PREFIX__
+#endif
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Arm/ProcessorBind.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Arm/ProcessorBind.h
new file mode 100644
index 0000000000..c00df3e739
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Arm/ProcessorBind.h
@@ -0,0 +1,238 @@
+/** @file
+ Processor or Compiler specific defines and types for ARM.
+
+ Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __PROCESSOR_BIND_H__
+#define __PROCESSOR_BIND_H__
+
+///
+/// Define the processor type so other code can make processor based choices
+///
+#define MDE_CPU_ARM
+
+//
+// Make sure we are using the correct packing rules per EFI specification
+//
+#if !defined (__GNUC__) && !defined (__ASSEMBLER__)
+ #pragma pack()
+#endif
+
+#if defined (_MSC_EXTENSIONS)
+
+//
+// Disable some level 4 compilation warnings (same as IA32 and X64)
+//
+
+//
+// Disabling bitfield type checking warnings.
+//
+ #pragma warning ( disable : 4214 )
+
+//
+// Disabling the unreferenced formal parameter warnings.
+//
+ #pragma warning ( disable : 4100 )
+
+//
+// Disable slightly different base types warning as CHAR8 * can not be set
+// to a constant string.
+//
+ #pragma warning ( disable : 4057 )
+
+//
+// ASSERT(FALSE) or while (TRUE) are legal constructs so suppress this warning
+//
+ #pragma warning ( disable : 4127 )
+
+//
+// This warning is caused by functions defined but not used. For precompiled header only.
+//
+ #pragma warning ( disable : 4505 )
+
+//
+// This warning is caused by empty (after preprocessing) source file. For precompiled header only.
+//
+ #pragma warning ( disable : 4206 )
+
+//
+// Disable 'potentially uninitialized local variable X used' warnings
+//
+ #pragma warning ( disable : 4701 )
+
+//
+// Disable 'potentially uninitialized local pointer variable X used' warnings
+//
+ #pragma warning ( disable : 4703 )
+
+#endif
+
+//
+// MSFT doesn't support the __builtin_unreachable() macro
+//
+#if defined (_MSC_EXTENSIONS)
+#define UNREACHABLE()
+#endif
+
+#if defined (_MSC_EXTENSIONS)
+//
+// use Microsoft* C compiler dependent integer width types
+//
+typedef unsigned __int64 UINT64;
+typedef __int64 INT64;
+typedef unsigned __int32 UINT32;
+typedef __int32 INT32;
+typedef unsigned short UINT16;
+typedef unsigned short CHAR16;
+typedef short INT16;
+typedef unsigned char BOOLEAN;
+typedef unsigned char UINT8;
+typedef char CHAR8;
+typedef signed char INT8;
+#else
+//
+// Assume standard ARM alignment.
+// Need to check portability of long long
+//
+typedef unsigned long long UINT64;
+typedef long long INT64;
+typedef unsigned int UINT32;
+typedef int INT32;
+typedef unsigned short UINT16;
+typedef unsigned short CHAR16;
+typedef short INT16;
+typedef unsigned char BOOLEAN;
+typedef unsigned char UINT8;
+typedef char CHAR8;
+typedef signed char INT8;
+#endif
+
+///
+/// Unsigned value of native width. (4 bytes on supported 32-bit processor instructions,
+/// 8 bytes on supported 64-bit processor instructions)
+///
+typedef UINT32 UINTN;
+
+///
+/// Signed value of native width. (4 bytes on supported 32-bit processor instructions,
+/// 8 bytes on supported 64-bit processor instructions)
+///
+typedef INT32 INTN;
+
+//
+// Processor specific defines
+//
+
+///
+/// A value of native width with the highest bit set.
+///
+#define MAX_BIT 0x80000000
+
+///
+/// A value of native width with the two highest bits set.
+///
+#define MAX_2_BITS 0xC0000000
+
+///
+/// Maximum legal ARM address
+///
+#define MAX_ADDRESS 0xFFFFFFFF
+
+///
+/// Maximum usable address at boot time
+///
+#define MAX_ALLOC_ADDRESS MAX_ADDRESS
+
+///
+/// Maximum legal ARM INTN and UINTN values.
+///
+#define MAX_INTN ((INTN)0x7FFFFFFF)
+#define MAX_UINTN ((UINTN)0xFFFFFFFF)
+
+///
+/// Minimum legal ARM INTN value.
+///
+#define MIN_INTN (((INTN)-2147483647) - 1)
+
+///
+/// The stack alignment required for ARM
+///
+#define CPU_STACK_ALIGNMENT sizeof(UINT64)
+
+///
+/// Page allocation granularity for ARM
+///
+#define DEFAULT_PAGE_ALLOCATION_GRANULARITY (0x1000)
+#define RUNTIME_PAGE_ALLOCATION_GRANULARITY (0x1000)
+
+//
+// Modifier to ensure that all protocol member functions and EFI intrinsics
+// use the correct C calling convention. All protocol member functions and
+// EFI intrinsics are required to modify their member functions with EFIAPI.
+//
+#define EFIAPI
+
+// When compiling with Clang, we still use GNU as for the assembler, so we still
+// need to define the GCC_ASM* macros.
+#if defined (__GNUC__) || defined (__clang__)
+///
+/// For GNU assembly code, .global or .globl can declare global symbols.
+/// Define this macro to unify the usage.
+///
+#define ASM_GLOBAL .globl
+
+ #if !defined (__APPLE__)
+///
+/// ARM EABI defines that the linker should not manipulate call relocations
+/// (do bl/blx conversion) unless the target symbol has function type.
+/// CodeSourcery 2010.09 started requiring the .type to function properly
+///
+#define INTERWORK_FUNC(func__) .type ASM_PFX(func__), %function
+
+#define GCC_ASM_EXPORT(func__) \
+ .global _CONCATENATE (__USER_LABEL_PREFIX__, func__) ;\
+ .type ASM_PFX(func__), %function
+
+#define GCC_ASM_IMPORT(func__) \
+ .extern _CONCATENATE (__USER_LABEL_PREFIX__, func__)
+
+ #else
+//
+// .type not supported by Apple Xcode tools
+//
+#define INTERWORK_FUNC(func__)
+
+#define GCC_ASM_EXPORT(func__) \
+ .globl _CONCATENATE (__USER_LABEL_PREFIX__, func__) \
+
+#define GCC_ASM_IMPORT(name)
+
+ #endif
+#elif defined (_MSC_EXTENSIONS)
+//
+// PRESERVE8 is not supported by the MSFT assembler.
+//
+#define PRESERVE8
+#endif
+
+/**
+ Return the pointer to the first instruction of a function given a function pointer.
+ On ARM CPU architectures, these two pointer values are the same,
+ so the implementation of this macro is very simple.
+
+ @param FunctionPointer A pointer to a function.
+
+ @return The pointer to the first instruction of a function given a function pointer.
+
+**/
+#define FUNCTION_ENTRY_POINT(FunctionPointer) (VOID *)(UINTN)(FunctionPointer)
+
+#ifndef __USER_LABEL_PREFIX__
+#define __USER_LABEL_PREFIX__
+#endif
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Base.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Base.h
new file mode 100644
index 0000000000..f1b9c1429d
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Base.h
@@ -0,0 +1,1299 @@
+/** @file
+ Root include file for Mde Package Base type modules
+
+ This is the include file for any module of type base. Base modules only use
+ types defined via this include file and can be ported easily to any
+ environment. There are a set of base libraries in the Mde Package that can
+ be used to implement base modules.
+
+Copyright (c) 2006 - 2021, Intel Corporation. All rights reserved.
+Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __BASE_H__
+#define __BASE_H__
+
+//
+// Include processor specific binding
+//
+#include
+
+#if defined (_MSC_EXTENSIONS)
+//
+// Disable warning when last field of data structure is a zero sized array.
+//
+ #pragma warning ( disable : 4200 )
+#endif
+
+//
+// The Microsoft* C compiler can removed references to unreferenced data items
+// if the /OPT:REF linker option is used. We defined a macro as this is a
+// a non standard extension
+//
+#if defined (_MSC_VER) && _MSC_VER < 1800 && !defined (MDE_CPU_EBC)
+///
+/// Remove global variable from the linked image if there are no references to
+/// it after all compiler and linker optimizations have been performed.
+///
+///
+#define GLOBAL_REMOVE_IF_UNREFERENCED __declspec(selectany)
+#else
+///
+/// Remove the global variable from the linked image if there are no references
+/// to it after all compiler and linker optimizations have been performed.
+///
+///
+#define GLOBAL_REMOVE_IF_UNREFERENCED
+#endif
+
+//
+// Should be used in combination with NORETURN to avoid 'noreturn' returns
+// warnings.
+//
+#ifndef UNREACHABLE
+ #ifdef __GNUC__
+///
+/// Signal compilers and analyzers that this call is not reachable. It is
+/// up to the compiler to remove any code past that point.
+///
+#define UNREACHABLE() __builtin_unreachable ()
+ #elif defined (__has_feature)
+ #if __has_builtin (__builtin_unreachable)
+///
+/// Signal compilers and analyzers that this call is not reachable. It is
+/// up to the compiler to remove any code past that point.
+///
+#define UNREACHABLE() __builtin_unreachable ()
+ #endif
+ #endif
+
+ #ifndef UNREACHABLE
+///
+/// Signal compilers and analyzers that this call is not reachable. It is
+/// up to the compiler to remove any code past that point.
+///
+#define UNREACHABLE()
+ #endif
+#endif
+
+//
+// Signaling compilers and analyzers that a certain function cannot return may
+// remove all following code and thus lead to better optimization and less
+// false positives.
+//
+#ifndef NORETURN
+ #if defined (__GNUC__) || defined (__clang__)
+///
+/// Signal compilers and analyzers that the function cannot return.
+/// It is up to the compiler to remove any code past a call to functions
+/// flagged with this attribute.
+///
+#define NORETURN __attribute__((noreturn))
+ #elif defined (_MSC_EXTENSIONS) && !defined (MDE_CPU_EBC)
+///
+/// Signal compilers and analyzers that the function cannot return.
+/// It is up to the compiler to remove any code past a call to functions
+/// flagged with this attribute.
+///
+#define NORETURN __declspec(noreturn)
+ #else
+///
+/// Signal compilers and analyzers that the function cannot return.
+/// It is up to the compiler to remove any code past a call to functions
+/// flagged with this attribute.
+///
+#define NORETURN
+ #endif
+#endif
+
+//
+// Should be used in combination with ANALYZER_NORETURN to avoid 'noreturn'
+// returns warnings.
+//
+#ifndef ANALYZER_UNREACHABLE
+ #ifdef __clang_analyzer__
+ #if __has_builtin (__builtin_unreachable)
+///
+/// Signal the analyzer that this call is not reachable.
+/// This excludes compilers.
+///
+#define ANALYZER_UNREACHABLE() __builtin_unreachable ()
+ #endif
+ #endif
+
+ #ifndef ANALYZER_UNREACHABLE
+///
+/// Signal the analyzer that this call is not reachable.
+/// This excludes compilers.
+///
+#define ANALYZER_UNREACHABLE()
+ #endif
+#endif
+
+//
+// Static Analyzers may issue errors about potential NULL-dereferences when
+// dereferencing a pointer, that has been checked before, outside of a
+// NULL-check. This may lead to false positives, such as when using ASSERT()
+// for verification.
+//
+#ifndef ANALYZER_NORETURN
+ #ifdef __has_feature
+ #if __has_feature (attribute_analyzer_noreturn)
+///
+/// Signal analyzers that the function cannot return.
+/// This excludes compilers.
+///
+#define ANALYZER_NORETURN __attribute__((analyzer_noreturn))
+ #endif
+ #endif
+
+ #ifndef ANALYZER_NORETURN
+///
+/// Signal the analyzer that the function cannot return.
+/// This excludes compilers.
+///
+#define ANALYZER_NORETURN
+ #endif
+#endif
+
+///
+/// Tell the code optimizer that the function will return twice.
+/// This prevents wrong optimizations which can cause bugs.
+///
+#ifndef RETURNS_TWICE
+ #if defined (__GNUC__) || defined (__clang__)
+///
+/// Tell the code optimizer that the function will return twice.
+/// This prevents wrong optimizations which can cause bugs.
+///
+#define RETURNS_TWICE __attribute__((returns_twice))
+ #else
+///
+/// Tell the code optimizer that the function will return twice.
+/// This prevents wrong optimizations which can cause bugs.
+///
+#define RETURNS_TWICE
+ #endif
+#endif
+
+//
+// For symbol name in assembly code, an extra "_" is sometimes necessary
+//
+
+///
+/// Private worker functions for ASM_PFX()
+///
+#define _CONCATENATE(a, b) __CONCATENATE(a, b)
+#define __CONCATENATE(a, b) a ## b
+
+///
+/// The __USER_LABEL_PREFIX__ macro predefined by GNUC represents the prefix
+/// on symbols in assembly language.
+///
+#define ASM_PFX(name) _CONCATENATE (__USER_LABEL_PREFIX__, name)
+
+#ifdef __APPLE__
+//
+// Apple extension that is used by the linker to optimize code size
+// with assembly functions. Put at the end of your .S files
+//
+#define ASM_FUNCTION_REMOVE_IF_UNREFERENCED .subsections_via_symbols
+#else
+#define ASM_FUNCTION_REMOVE_IF_UNREFERENCED
+#endif
+
+#define PACKED
+
+///
+/// 128 bit buffer containing a unique identifier value.
+/// Unless otherwise specified, aligned on a 64 bit boundary.
+///
+typedef struct {
+ UINT32 Data1;
+ UINT16 Data2;
+ UINT16 Data3;
+ UINT8 Data4[8];
+} GUID;
+
+///
+/// 4-byte buffer. An IPv4 internet protocol address.
+///
+typedef struct {
+ UINT8 Addr[4];
+} IPv4_ADDRESS;
+
+///
+/// 16-byte buffer. An IPv6 internet protocol address.
+///
+typedef struct {
+ UINT8 Addr[16];
+} IPv6_ADDRESS;
+
+//
+// 8-bytes unsigned value that represents a physical system address.
+//
+typedef UINT64 PHYSICAL_ADDRESS;
+
+///
+/// LIST_ENTRY structure definition.
+///
+typedef struct _LIST_ENTRY LIST_ENTRY;
+
+///
+/// _LIST_ENTRY structure definition.
+///
+struct _LIST_ENTRY {
+ LIST_ENTRY *ForwardLink;
+ LIST_ENTRY *BackLink;
+};
+
+//
+// Modifiers to abstract standard types to aid in debug of problems
+//
+
+///
+/// Datum is read-only.
+///
+#define CONST const
+
+///
+/// Datum is scoped to the current file or function.
+///
+#define STATIC static
+
+///
+/// Undeclared type.
+///
+#define VOID void
+
+//
+// Modifiers for Data Types used to self document code.
+// This concept is borrowed for UEFI specification.
+//
+
+///
+/// Datum is passed to the function.
+///
+#define IN
+
+///
+/// Datum is returned from the function.
+///
+#define OUT
+
+///
+/// Passing the datum to the function is optional, and a NULL
+/// is passed if the value is not supplied.
+///
+#define OPTIONAL
+
+//
+// UEFI specification claims 1 and 0. We are concerned about the
+// compiler portability so we did it this way.
+//
+
+///
+/// Boolean true value. UEFI Specification defines this value to be 1,
+/// but this form is more portable.
+///
+#define TRUE ((BOOLEAN)(1==1))
+
+///
+/// Boolean false value. UEFI Specification defines this value to be 0,
+/// but this form is more portable.
+///
+#define FALSE ((BOOLEAN)(0==1))
+
+///
+/// NULL pointer (VOID *)
+///
+#ifndef NULL
+#if defined (__cplusplus)
+ #if defined (_MSC_EXTENSIONS)
+#define NULL nullptr
+ #else
+#define NULL __null
+ #endif
+#else
+#define NULL ((VOID *) 0)
+#endif
+#endif
+
+//
+// Null character
+//
+#define CHAR_NULL 0x0000
+
+///
+/// Maximum values for common UEFI Data Types
+///
+#define MAX_INT8 ((INT8)0x7F)
+#define MAX_UINT8 ((UINT8)0xFF)
+#define MAX_INT16 ((INT16)0x7FFF)
+#define MAX_UINT16 ((UINT16)0xFFFF)
+#define MAX_INT32 ((INT32)0x7FFFFFFF)
+#define MAX_UINT32 ((UINT32)0xFFFFFFFF)
+#define MAX_INT64 ((INT64)0x7FFFFFFFFFFFFFFFULL)
+#define MAX_UINT64 ((UINT64)0xFFFFFFFFFFFFFFFFULL)
+
+///
+/// Minimum values for the signed UEFI Data Types
+///
+#define MIN_INT8 (((INT8) -127) - 1)
+#define MIN_INT16 (((INT16) -32767) - 1)
+#define MIN_INT32 (((INT32) -2147483647) - 1)
+#define MIN_INT64 (((INT64) -9223372036854775807LL) - 1)
+
+#define BIT0 0x00000001
+#define BIT1 0x00000002
+#define BIT2 0x00000004
+#define BIT3 0x00000008
+#define BIT4 0x00000010
+#define BIT5 0x00000020
+#define BIT6 0x00000040
+#define BIT7 0x00000080
+#define BIT8 0x00000100
+#define BIT9 0x00000200
+#define BIT10 0x00000400
+#define BIT11 0x00000800
+#define BIT12 0x00001000
+#define BIT13 0x00002000
+#define BIT14 0x00004000
+#define BIT15 0x00008000
+#define BIT16 0x00010000
+#define BIT17 0x00020000
+#define BIT18 0x00040000
+#define BIT19 0x00080000
+#define BIT20 0x00100000
+#define BIT21 0x00200000
+#define BIT22 0x00400000
+#define BIT23 0x00800000
+#define BIT24 0x01000000
+#define BIT25 0x02000000
+#define BIT26 0x04000000
+#define BIT27 0x08000000
+#define BIT28 0x10000000
+#define BIT29 0x20000000
+#define BIT30 0x40000000
+#define BIT31 0x80000000
+#define BIT32 0x0000000100000000ULL
+#define BIT33 0x0000000200000000ULL
+#define BIT34 0x0000000400000000ULL
+#define BIT35 0x0000000800000000ULL
+#define BIT36 0x0000001000000000ULL
+#define BIT37 0x0000002000000000ULL
+#define BIT38 0x0000004000000000ULL
+#define BIT39 0x0000008000000000ULL
+#define BIT40 0x0000010000000000ULL
+#define BIT41 0x0000020000000000ULL
+#define BIT42 0x0000040000000000ULL
+#define BIT43 0x0000080000000000ULL
+#define BIT44 0x0000100000000000ULL
+#define BIT45 0x0000200000000000ULL
+#define BIT46 0x0000400000000000ULL
+#define BIT47 0x0000800000000000ULL
+#define BIT48 0x0001000000000000ULL
+#define BIT49 0x0002000000000000ULL
+#define BIT50 0x0004000000000000ULL
+#define BIT51 0x0008000000000000ULL
+#define BIT52 0x0010000000000000ULL
+#define BIT53 0x0020000000000000ULL
+#define BIT54 0x0040000000000000ULL
+#define BIT55 0x0080000000000000ULL
+#define BIT56 0x0100000000000000ULL
+#define BIT57 0x0200000000000000ULL
+#define BIT58 0x0400000000000000ULL
+#define BIT59 0x0800000000000000ULL
+#define BIT60 0x1000000000000000ULL
+#define BIT61 0x2000000000000000ULL
+#define BIT62 0x4000000000000000ULL
+#define BIT63 0x8000000000000000ULL
+
+#define SIZE_1KB 0x00000400
+#define SIZE_2KB 0x00000800
+#define SIZE_4KB 0x00001000
+#define SIZE_8KB 0x00002000
+#define SIZE_16KB 0x00004000
+#define SIZE_32KB 0x00008000
+#define SIZE_64KB 0x00010000
+#define SIZE_128KB 0x00020000
+#define SIZE_256KB 0x00040000
+#define SIZE_512KB 0x00080000
+#define SIZE_1MB 0x00100000
+#define SIZE_2MB 0x00200000
+#define SIZE_4MB 0x00400000
+#define SIZE_8MB 0x00800000
+#define SIZE_16MB 0x01000000
+#define SIZE_32MB 0x02000000
+#define SIZE_64MB 0x04000000
+#define SIZE_128MB 0x08000000
+#define SIZE_256MB 0x10000000
+#define SIZE_512MB 0x20000000
+#define SIZE_1GB 0x40000000
+#define SIZE_2GB 0x80000000
+#define SIZE_4GB 0x0000000100000000ULL
+#define SIZE_8GB 0x0000000200000000ULL
+#define SIZE_16GB 0x0000000400000000ULL
+#define SIZE_32GB 0x0000000800000000ULL
+#define SIZE_64GB 0x0000001000000000ULL
+#define SIZE_128GB 0x0000002000000000ULL
+#define SIZE_256GB 0x0000004000000000ULL
+#define SIZE_512GB 0x0000008000000000ULL
+#define SIZE_1TB 0x0000010000000000ULL
+#define SIZE_2TB 0x0000020000000000ULL
+#define SIZE_4TB 0x0000040000000000ULL
+#define SIZE_8TB 0x0000080000000000ULL
+#define SIZE_16TB 0x0000100000000000ULL
+#define SIZE_32TB 0x0000200000000000ULL
+#define SIZE_64TB 0x0000400000000000ULL
+#define SIZE_128TB 0x0000800000000000ULL
+#define SIZE_256TB 0x0001000000000000ULL
+#define SIZE_512TB 0x0002000000000000ULL
+#define SIZE_1PB 0x0004000000000000ULL
+#define SIZE_2PB 0x0008000000000000ULL
+#define SIZE_4PB 0x0010000000000000ULL
+#define SIZE_8PB 0x0020000000000000ULL
+#define SIZE_16PB 0x0040000000000000ULL
+#define SIZE_32PB 0x0080000000000000ULL
+#define SIZE_64PB 0x0100000000000000ULL
+#define SIZE_128PB 0x0200000000000000ULL
+#define SIZE_256PB 0x0400000000000000ULL
+#define SIZE_512PB 0x0800000000000000ULL
+#define SIZE_1EB 0x1000000000000000ULL
+#define SIZE_2EB 0x2000000000000000ULL
+#define SIZE_4EB 0x4000000000000000ULL
+#define SIZE_8EB 0x8000000000000000ULL
+
+#define BASE_1KB 0x00000400
+#define BASE_2KB 0x00000800
+#define BASE_4KB 0x00001000
+#define BASE_8KB 0x00002000
+#define BASE_16KB 0x00004000
+#define BASE_32KB 0x00008000
+#define BASE_64KB 0x00010000
+#define BASE_128KB 0x00020000
+#define BASE_256KB 0x00040000
+#define BASE_512KB 0x00080000
+#define BASE_1MB 0x00100000
+#define BASE_2MB 0x00200000
+#define BASE_4MB 0x00400000
+#define BASE_8MB 0x00800000
+#define BASE_16MB 0x01000000
+#define BASE_32MB 0x02000000
+#define BASE_64MB 0x04000000
+#define BASE_128MB 0x08000000
+#define BASE_256MB 0x10000000
+#define BASE_512MB 0x20000000
+#define BASE_1GB 0x40000000
+#define BASE_2GB 0x80000000
+#define BASE_4GB 0x0000000100000000ULL
+#define BASE_8GB 0x0000000200000000ULL
+#define BASE_16GB 0x0000000400000000ULL
+#define BASE_32GB 0x0000000800000000ULL
+#define BASE_64GB 0x0000001000000000ULL
+#define BASE_128GB 0x0000002000000000ULL
+#define BASE_256GB 0x0000004000000000ULL
+#define BASE_512GB 0x0000008000000000ULL
+#define BASE_1TB 0x0000010000000000ULL
+#define BASE_2TB 0x0000020000000000ULL
+#define BASE_4TB 0x0000040000000000ULL
+#define BASE_8TB 0x0000080000000000ULL
+#define BASE_16TB 0x0000100000000000ULL
+#define BASE_32TB 0x0000200000000000ULL
+#define BASE_64TB 0x0000400000000000ULL
+#define BASE_128TB 0x0000800000000000ULL
+#define BASE_256TB 0x0001000000000000ULL
+#define BASE_512TB 0x0002000000000000ULL
+#define BASE_1PB 0x0004000000000000ULL
+#define BASE_2PB 0x0008000000000000ULL
+#define BASE_4PB 0x0010000000000000ULL
+#define BASE_8PB 0x0020000000000000ULL
+#define BASE_16PB 0x0040000000000000ULL
+#define BASE_32PB 0x0080000000000000ULL
+#define BASE_64PB 0x0100000000000000ULL
+#define BASE_128PB 0x0200000000000000ULL
+#define BASE_256PB 0x0400000000000000ULL
+#define BASE_512PB 0x0800000000000000ULL
+#define BASE_1EB 0x1000000000000000ULL
+#define BASE_2EB 0x2000000000000000ULL
+#define BASE_4EB 0x4000000000000000ULL
+#define BASE_8EB 0x8000000000000000ULL
+
+//
+// Support for variable argument lists in freestanding edk2 modules.
+//
+// For modules that use the ISO C library interfaces for variable
+// argument lists, refer to "StdLib/Include/stdarg.h".
+//
+// VA_LIST - typedef for argument list.
+// VA_START (VA_LIST Marker, argument before the ...) - Init Marker for use.
+// VA_END (VA_LIST Marker) - Clear Marker
+// VA_ARG (VA_LIST Marker, var arg type) - Use Marker to get an argument from
+// the ... list. You must know the type and pass it in this macro. Type
+// must be compatible with the type of the actual next argument (as promoted
+// according to the default argument promotions.)
+// VA_COPY (VA_LIST Dest, VA_LIST Start) - Initialize Dest as a copy of Start.
+//
+// Example:
+//
+// UINTN
+// EFIAPI
+// ExampleVarArg (
+// IN UINTN NumberOfArgs,
+// ...
+// )
+// {
+// VA_LIST Marker;
+// UINTN Index;
+// UINTN Result;
+//
+// //
+// // Initialize the Marker
+// //
+// VA_START (Marker, NumberOfArgs);
+// for (Index = 0, Result = 0; Index < NumberOfArgs; Index++) {
+// //
+// // The ... list is a series of UINTN values, so sum them up.
+// //
+// Result += VA_ARG (Marker, UINTN);
+// }
+//
+// VA_END (Marker);
+// return Result;
+// }
+//
+// Notes:
+// - Functions that call VA_START() / VA_END() must have a variable
+// argument list and must be declared EFIAPI.
+// - Functions that call VA_COPY() / VA_END() must be declared EFIAPI.
+// - Functions that only use VA_LIST and VA_ARG() need not be EFIAPI.
+//
+
+/**
+ Return the size of argument that has been aligned to sizeof (UINTN).
+
+ @param n The parameter size to be aligned.
+
+ @return The aligned size.
+**/
+#define _INT_SIZE_OF(n) ((sizeof (n) + sizeof (UINTN) - 1) &~(sizeof (UINTN) - 1))
+
+#if defined (_M_ARM) || defined (_M_ARM64)
+//
+// MSFT ARM variable argument list support.
+//
+
+typedef char *VA_LIST;
+
+#define VA_START(Marker, Parameter) __va_start (&Marker, &Parameter, _INT_SIZE_OF (Parameter), __alignof(Parameter), &Parameter)
+#define VA_ARG(Marker, TYPE) (*(TYPE *) ((Marker += _INT_SIZE_OF (TYPE) + ((-(INTN)Marker) & (sizeof(TYPE) - 1))) - _INT_SIZE_OF (TYPE)))
+#define VA_END(Marker) (Marker = (VA_LIST) 0)
+#define VA_COPY(Dest, Start) ((void)((Dest) = (Start)))
+
+#elif defined (__GNUC__) || defined (__clang__)
+
+ #if defined (MDE_CPU_X64) && !defined (NO_MSABI_VA_FUNCS)
+//
+// X64 only. Use MS ABI version of GCC built-in macros for variable argument lists.
+//
+///
+/// Both GCC and LLVM 3.8 for X64 support new variable argument intrinsics for Microsoft ABI
+///
+
+///
+/// Variable used to traverse the list of arguments. This type can vary by
+/// implementation and could be an array or structure.
+///
+typedef __builtin_ms_va_list VA_LIST;
+
+#define VA_START(Marker, Parameter) __builtin_ms_va_start (Marker, Parameter)
+
+#define VA_ARG(Marker, TYPE) ((sizeof (TYPE) < sizeof (UINTN)) ? (TYPE)(__builtin_va_arg (Marker, UINTN)) : (TYPE)(__builtin_va_arg (Marker, TYPE)))
+
+#define VA_END(Marker) __builtin_ms_va_end (Marker)
+
+#define VA_COPY(Dest, Start) __builtin_ms_va_copy (Dest, Start)
+
+ #else
+//
+// Use GCC built-in macros for variable argument lists.
+//
+
+///
+/// Variable used to traverse the list of arguments. This type can vary by
+/// implementation and could be an array or structure.
+///
+typedef __builtin_va_list VA_LIST;
+
+#define VA_START(Marker, Parameter) __builtin_va_start (Marker, Parameter)
+
+#define VA_ARG(Marker, TYPE) ((sizeof (TYPE) < sizeof (UINTN)) ? (TYPE)(__builtin_va_arg (Marker, UINTN)) : (TYPE)(__builtin_va_arg (Marker, TYPE)))
+
+#define VA_END(Marker) __builtin_va_end (Marker)
+
+#define VA_COPY(Dest, Start) __builtin_va_copy (Dest, Start)
+
+ #endif
+
+#else
+///
+/// Variable used to traverse the list of arguments. This type can vary by
+/// implementation and could be an array or structure.
+///
+typedef CHAR8 *VA_LIST;
+
+/**
+ Retrieves a pointer to the beginning of a variable argument list, based on
+ the name of the parameter that immediately precedes the variable argument list.
+
+ This function initializes Marker to point to the beginning of the variable
+ argument list that immediately follows Parameter. The method for computing the
+ pointer to the next argument in the argument list is CPU-specific following the
+ EFIAPI ABI.
+
+ @param Marker The VA_LIST used to traverse the list of arguments.
+ @param Parameter The name of the parameter that immediately precedes
+ the variable argument list.
+
+ @return A pointer to the beginning of a variable argument list.
+
+**/
+#define VA_START(Marker, Parameter) (Marker = (VA_LIST) ((UINTN) & (Parameter) + _INT_SIZE_OF (Parameter)))
+
+/**
+ Returns an argument of a specified type from a variable argument list and updates
+ the pointer to the variable argument list to point to the next argument.
+
+ This function returns an argument of the type specified by TYPE from the beginning
+ of the variable argument list specified by Marker. Marker is then updated to point
+ to the next argument in the variable argument list. The method for computing the
+ pointer to the next argument in the argument list is CPU-specific following the EFIAPI ABI.
+
+ @param Marker VA_LIST used to traverse the list of arguments.
+ @param TYPE The type of argument to retrieve from the beginning
+ of the variable argument list.
+
+ @return An argument of the type specified by TYPE.
+
+**/
+#define VA_ARG(Marker, TYPE) (*(TYPE *) ((Marker += _INT_SIZE_OF (TYPE)) - _INT_SIZE_OF (TYPE)))
+
+/**
+ Terminates the use of a variable argument list.
+
+ This function initializes Marker so it can no longer be used with VA_ARG().
+ After this macro is used, the only way to access the variable argument list is
+ by using VA_START() again.
+
+ @param Marker VA_LIST used to traverse the list of arguments.
+
+**/
+#define VA_END(Marker) (Marker = (VA_LIST) 0)
+
+/**
+ Initializes a VA_LIST as a copy of an existing VA_LIST.
+
+ This macro initializes Dest as a copy of Start, as if the VA_START macro had been applied to Dest
+ followed by the same sequence of uses of the VA_ARG macro as had previously been used to reach
+ the present state of Start.
+
+ @param Dest VA_LIST used to traverse the list of arguments.
+ @param Start VA_LIST used to traverse the list of arguments.
+
+**/
+#define VA_COPY(Dest, Start) ((void)((Dest) = (Start)))
+
+#endif
+
+///
+/// Pointer to the start of a variable argument list stored in a memory buffer. Same as UINT8 *.
+///
+typedef UINTN *BASE_LIST;
+
+/**
+ Returns the size of a data type in sizeof(UINTN) units rounded up to the nearest UINTN boundary.
+
+ @param TYPE The date type to determine the size of.
+
+ @return The size of TYPE in sizeof (UINTN) units rounded up to the nearest UINTN boundary.
+**/
+#define _BASE_INT_SIZE_OF(TYPE) ((sizeof (TYPE) + sizeof (UINTN) - 1) / sizeof (UINTN))
+
+/**
+ Returns an argument of a specified type from a variable argument list and updates
+ the pointer to the variable argument list to point to the next argument.
+
+ This function returns an argument of the type specified by TYPE from the beginning
+ of the variable argument list specified by Marker. Marker is then updated to point
+ to the next argument in the variable argument list. The method for computing the
+ pointer to the next argument in the argument list is CPU specific following the EFIAPI ABI.
+
+ @param Marker The pointer to the beginning of a variable argument list.
+ @param TYPE The type of argument to retrieve from the beginning
+ of the variable argument list.
+
+ @return An argument of the type specified by TYPE.
+
+**/
+#define BASE_ARG(Marker, TYPE) (*(TYPE *) ((Marker += _BASE_INT_SIZE_OF (TYPE)) - _BASE_INT_SIZE_OF (TYPE)))
+
+/**
+ The macro that returns the byte offset of a field in a data structure.
+
+ This function returns the offset, in bytes, of field specified by Field from the
+ beginning of the data structure specified by TYPE. If TYPE does not contain Field,
+ the module will not compile.
+
+ @param TYPE The name of the data structure that contains the field specified by Field.
+ @param Field The name of the field in the data structure.
+
+ @return Offset, in bytes, of field.
+
+**/
+#if (defined (__GNUC__) && __GNUC__ >= 4) || defined (__clang__)
+#define OFFSET_OF(TYPE, Field) ((UINTN) __builtin_offsetof(TYPE, Field))
+#endif
+
+#ifndef OFFSET_OF
+#define OFFSET_OF(TYPE, Field) ((UINTN) &(((TYPE *)0)->Field))
+#endif
+
+/**
+ Portable definition for compile time assertions.
+ Equivalent to C11 static_assert macro from assert.h.
+
+ @param Expression Boolean expression.
+ @param Message Raised compiler diagnostic message when expression is false.
+
+**/
+#ifdef MDE_CPU_EBC
+#define STATIC_ASSERT(Expression, Message)
+#elif defined (_MSC_EXTENSIONS) || defined (__cplusplus)
+#define STATIC_ASSERT static_assert
+#else
+#define STATIC_ASSERT _Static_assert
+#endif
+
+//
+// Verify that ProcessorBind.h produced UEFI Data Types that are compliant with
+// Section 2.3.1 of the UEFI 2.3 Specification.
+//
+
+STATIC_ASSERT (sizeof (BOOLEAN) == 1, "sizeof (BOOLEAN) does not meet UEFI Specification Data Type requirements");
+STATIC_ASSERT (sizeof (INT8) == 1, "sizeof (INT8) does not meet UEFI Specification Data Type requirements");
+STATIC_ASSERT (sizeof (UINT8) == 1, "sizeof (UINT8) does not meet UEFI Specification Data Type requirements");
+STATIC_ASSERT (sizeof (INT16) == 2, "sizeof (INT16) does not meet UEFI Specification Data Type requirements");
+STATIC_ASSERT (sizeof (UINT16) == 2, "sizeof (UINT16) does not meet UEFI Specification Data Type requirements");
+STATIC_ASSERT (sizeof (INT32) == 4, "sizeof (INT32) does not meet UEFI Specification Data Type requirements");
+STATIC_ASSERT (sizeof (UINT32) == 4, "sizeof (UINT32) does not meet UEFI Specification Data Type requirements");
+STATIC_ASSERT (sizeof (INT64) == 8, "sizeof (INT64) does not meet UEFI Specification Data Type requirements");
+STATIC_ASSERT (sizeof (UINT64) == 8, "sizeof (UINT64) does not meet UEFI Specification Data Type requirements");
+STATIC_ASSERT (sizeof (CHAR8) == 1, "sizeof (CHAR8) does not meet UEFI Specification Data Type requirements");
+STATIC_ASSERT (sizeof (CHAR16) == 2, "sizeof (CHAR16) does not meet UEFI Specification Data Type requirements");
+STATIC_ASSERT (sizeof (L'A') == 2, "sizeof (L'A') does not meet UEFI Specification Data Type requirements");
+STATIC_ASSERT (sizeof (L"A") == 4, "sizeof (L\"A\") does not meet UEFI Specification Data Type requirements");
+
+//
+// The following three enum types are used to verify that the compiler
+// configuration for enum types is compliant with Section 2.3.1 of the
+// UEFI 2.3 Specification. These enum types and enum values are not
+// intended to be used. A prefix of '__' is used avoid conflicts with
+// other types.
+//
+typedef enum {
+ __VerifyUint8EnumValue = 0xff
+} __VERIFY_UINT8_ENUM_SIZE;
+
+typedef enum {
+ __VerifyUint16EnumValue = 0xffff
+} __VERIFY_UINT16_ENUM_SIZE;
+
+typedef enum {
+ __VerifyUint32EnumValue = 0xffffffff
+} __VERIFY_UINT32_ENUM_SIZE;
+
+STATIC_ASSERT (sizeof (__VERIFY_UINT8_ENUM_SIZE) == 4, "Size of enum does not meet UEFI Specification Data Type requirements");
+STATIC_ASSERT (sizeof (__VERIFY_UINT16_ENUM_SIZE) == 4, "Size of enum does not meet UEFI Specification Data Type requirements");
+STATIC_ASSERT (sizeof (__VERIFY_UINT32_ENUM_SIZE) == 4, "Size of enum does not meet UEFI Specification Data Type requirements");
+
+/**
+ Macro that returns a pointer to the data structure that contains a specified field of
+ that data structure. This is a lightweight method to hide information by placing a
+ public data structure inside a larger private data structure and using a pointer to
+ the public data structure to retrieve a pointer to the private data structure.
+
+ This function computes the offset, in bytes, of field specified by Field from the beginning
+ of the data structure specified by TYPE. This offset is subtracted from Record, and is
+ used to return a pointer to a data structure of the type specified by TYPE. If the data type
+ specified by TYPE does not contain the field specified by Field, then the module will not compile.
+
+ @param Record Pointer to the field specified by Field within a data structure of type TYPE.
+ @param TYPE The name of the data structure type to return. This data structure must
+ contain the field specified by Field.
+ @param Field The name of the field in the data structure specified by TYPE to which Record points.
+
+ @return A pointer to the structure from one of it's elements.
+
+**/
+#define BASE_CR(Record, TYPE, Field) ((TYPE *) ((CHAR8 *) (Record) - OFFSET_OF (TYPE, Field)))
+
+/**
+ Rounds a value up to the next boundary using a specified alignment.
+
+ This function rounds Value up to the next boundary using the specified Alignment.
+ This aligned value is returned.
+
+ @param Value The value to round up.
+ @param Alignment The alignment boundary used to return the aligned value.
+
+ @return A value up to the next boundary.
+
+**/
+#define ALIGN_VALUE(Value, Alignment) ((Value) + (((Alignment) - (Value)) & ((Alignment) - 1)))
+
+/**
+ Adjust a pointer by adding the minimum offset required for it to be aligned on
+ a specified alignment boundary.
+
+ This function rounds the pointer specified by Pointer to the next alignment boundary
+ specified by Alignment. The pointer to the aligned address is returned.
+
+ @param Pointer The pointer to round up.
+ @param Alignment The alignment boundary to use to return an aligned pointer.
+
+ @return Pointer to the aligned address.
+
+**/
+#define ALIGN_POINTER(Pointer, Alignment) ((VOID *) (ALIGN_VALUE ((UINTN)(Pointer), (Alignment))))
+
+/**
+ Rounds a value up to the next natural boundary for the current CPU.
+ This is 4-bytes for 32-bit CPUs and 8-bytes for 64-bit CPUs.
+
+ This function rounds the value specified by Value up to the next natural boundary for the
+ current CPU. This rounded value is returned.
+
+ @param Value The value to round up.
+
+ @return Rounded value specified by Value.
+
+**/
+#define ALIGN_VARIABLE(Value) ALIGN_VALUE ((Value), sizeof (UINTN))
+
+/**
+ Return the maximum of two operands.
+
+ This macro returns the maximum of two operand specified by a and b.
+ Both a and b must be the same numerical types, signed or unsigned.
+
+ @param a The first operand with any numerical type.
+ @param b The second operand. Can be any numerical type as long as is
+ the same type as a.
+
+ @return Maximum of two operands.
+
+**/
+#ifndef MAX
+#define MAX(a, b) \
+ (((a) > (b)) ? (a) : (b))
+#endif
+
+/**
+ Return the minimum of two operands.
+
+ This macro returns the minimal of two operand specified by a and b.
+ Both a and b must be the same numerical types, signed or unsigned.
+
+ @param a The first operand with any numerical type.
+ @param b The second operand. It should be the same any numerical type with a.
+
+ @return Minimum of two operands.
+
+**/
+#ifndef MIN
+#define MIN(a, b) \
+ (((a) < (b)) ? (a) : (b))
+#endif
+
+/**
+ Return the absolute value of a signed operand.
+
+ This macro returns the absolute value of the signed operand specified by a.
+
+ @param a The signed operand.
+
+ @return The absolute value of the signed operand.
+
+**/
+#ifndef ABS
+#define ABS(a) \
+ (((a) < 0) ? (-(a)) : (a))
+#endif
+
+//
+// Status codes common to all execution phases
+//
+typedef UINTN RETURN_STATUS;
+
+/**
+ Produces a RETURN_STATUS code with the highest bit set.
+
+ @param StatusCode The status code value to convert into a warning code.
+ StatusCode must be in the range 0x00000000..0x7FFFFFFF.
+
+ @return The value specified by StatusCode with the highest bit set.
+
+**/
+#define ENCODE_ERROR(StatusCode) ((RETURN_STATUS)(MAX_BIT | (StatusCode)))
+
+/**
+ Produces a RETURN_STATUS code with the highest bit clear.
+
+ @param StatusCode The status code value to convert into a warning code.
+ StatusCode must be in the range 0x00000000..0x7FFFFFFF.
+
+ @return The value specified by StatusCode with the highest bit clear.
+
+**/
+#define ENCODE_WARNING(StatusCode) ((RETURN_STATUS)(StatusCode))
+
+/**
+ Returns TRUE if a specified RETURN_STATUS code is an error code.
+
+ This function returns TRUE if StatusCode has the high bit set. Otherwise, FALSE is returned.
+
+ @param StatusCode The status code value to evaluate.
+
+ @retval TRUE The high bit of StatusCode is set.
+ @retval FALSE The high bit of StatusCode is clear.
+
+**/
+#define RETURN_ERROR(StatusCode) (((INTN)(RETURN_STATUS)(StatusCode)) < 0)
+
+///
+/// The operation completed successfully.
+///
+#define RETURN_SUCCESS (RETURN_STATUS)(0)
+
+///
+/// The image failed to load.
+///
+#define RETURN_LOAD_ERROR ENCODE_ERROR (1)
+
+///
+/// The parameter was incorrect.
+///
+#define RETURN_INVALID_PARAMETER ENCODE_ERROR (2)
+
+///
+/// The operation is not supported.
+///
+#define RETURN_UNSUPPORTED ENCODE_ERROR (3)
+
+///
+/// The buffer was not the proper size for the request.
+///
+#define RETURN_BAD_BUFFER_SIZE ENCODE_ERROR (4)
+
+///
+/// The buffer was not large enough to hold the requested data.
+/// The required buffer size is returned in the appropriate
+/// parameter when this error occurs.
+///
+#define RETURN_BUFFER_TOO_SMALL ENCODE_ERROR (5)
+
+///
+/// There is no data pending upon return.
+///
+#define RETURN_NOT_READY ENCODE_ERROR (6)
+
+///
+/// The physical device reported an error while attempting the
+/// operation.
+///
+#define RETURN_DEVICE_ERROR ENCODE_ERROR (7)
+
+///
+/// The device can not be written to.
+///
+#define RETURN_WRITE_PROTECTED ENCODE_ERROR (8)
+
+///
+/// The resource has run out.
+///
+#define RETURN_OUT_OF_RESOURCES ENCODE_ERROR (9)
+
+///
+/// An inconsistency was detected on the file system causing the
+/// operation to fail.
+///
+#define RETURN_VOLUME_CORRUPTED ENCODE_ERROR (10)
+
+///
+/// There is no more space on the file system.
+///
+#define RETURN_VOLUME_FULL ENCODE_ERROR (11)
+
+///
+/// The device does not contain any medium to perform the
+/// operation.
+///
+#define RETURN_NO_MEDIA ENCODE_ERROR (12)
+
+///
+/// The medium in the device has changed since the last
+/// access.
+///
+#define RETURN_MEDIA_CHANGED ENCODE_ERROR (13)
+
+///
+/// The item was not found.
+///
+#define RETURN_NOT_FOUND ENCODE_ERROR (14)
+
+///
+/// Access was denied.
+///
+#define RETURN_ACCESS_DENIED ENCODE_ERROR (15)
+
+///
+/// The server was not found or did not respond to the request.
+///
+#define RETURN_NO_RESPONSE ENCODE_ERROR (16)
+
+///
+/// A mapping to the device does not exist.
+///
+#define RETURN_NO_MAPPING ENCODE_ERROR (17)
+
+///
+/// A timeout time expired.
+///
+#define RETURN_TIMEOUT ENCODE_ERROR (18)
+
+///
+/// The protocol has not been started.
+///
+#define RETURN_NOT_STARTED ENCODE_ERROR (19)
+
+///
+/// The protocol has already been started.
+///
+#define RETURN_ALREADY_STARTED ENCODE_ERROR (20)
+
+///
+/// The operation was aborted.
+///
+#define RETURN_ABORTED ENCODE_ERROR (21)
+
+///
+/// An ICMP error occurred during the network operation.
+///
+#define RETURN_ICMP_ERROR ENCODE_ERROR (22)
+
+///
+/// A TFTP error occurred during the network operation.
+///
+#define RETURN_TFTP_ERROR ENCODE_ERROR (23)
+
+///
+/// A protocol error occurred during the network operation.
+///
+#define RETURN_PROTOCOL_ERROR ENCODE_ERROR (24)
+
+///
+/// A function encountered an internal version that was
+/// incompatible with a version requested by the caller.
+///
+#define RETURN_INCOMPATIBLE_VERSION ENCODE_ERROR (25)
+
+///
+/// The function was not performed due to a security violation.
+///
+#define RETURN_SECURITY_VIOLATION ENCODE_ERROR (26)
+
+///
+/// A CRC error was detected.
+///
+#define RETURN_CRC_ERROR ENCODE_ERROR (27)
+
+///
+/// The beginning or end of media was reached.
+///
+#define RETURN_END_OF_MEDIA ENCODE_ERROR (28)
+
+///
+/// The end of the file was reached.
+///
+#define RETURN_END_OF_FILE ENCODE_ERROR (31)
+
+///
+/// The language specified was invalid.
+///
+#define RETURN_INVALID_LANGUAGE ENCODE_ERROR (32)
+
+///
+/// The security status of the data is unknown or compromised
+/// and the data must be updated or replaced to restore a valid
+/// security status.
+///
+#define RETURN_COMPROMISED_DATA ENCODE_ERROR (33)
+
+///
+/// A HTTP error occurred during the network operation.
+///
+#define RETURN_HTTP_ERROR ENCODE_ERROR (35)
+
+///
+/// The string contained one or more characters that
+/// the device could not render and were skipped.
+///
+#define RETURN_WARN_UNKNOWN_GLYPH ENCODE_WARNING (1)
+
+///
+/// The handle was closed, but the file was not deleted.
+///
+#define RETURN_WARN_DELETE_FAILURE ENCODE_WARNING (2)
+
+///
+/// The handle was closed, but the data to the file was not
+/// flushed properly.
+///
+#define RETURN_WARN_WRITE_FAILURE ENCODE_WARNING (3)
+
+///
+/// The resulting buffer was too small, and the data was
+/// truncated to the buffer size.
+///
+#define RETURN_WARN_BUFFER_TOO_SMALL ENCODE_WARNING (4)
+
+///
+/// The data has not been updated within the timeframe set by
+/// local policy for this type of data.
+///
+#define RETURN_WARN_STALE_DATA ENCODE_WARNING (5)
+
+///
+/// The resulting buffer contains UEFI-compliant file system.
+///
+#define RETURN_WARN_FILE_SYSTEM ENCODE_WARNING (6)
+
+/**
+ Returns a 16-bit signature built from 2 ASCII characters.
+
+ This macro returns a 16-bit value built from the two ASCII characters specified
+ by A and B.
+
+ @param A The first ASCII character.
+ @param B The second ASCII character.
+
+ @return A 16-bit value built from the two ASCII characters specified by A and B.
+
+**/
+#define SIGNATURE_16(A, B) ((A) | (B << 8))
+
+/**
+ Returns a 32-bit signature built from 4 ASCII characters.
+
+ This macro returns a 32-bit value built from the four ASCII characters specified
+ by A, B, C, and D.
+
+ @param A The first ASCII character.
+ @param B The second ASCII character.
+ @param C The third ASCII character.
+ @param D The fourth ASCII character.
+
+ @return A 32-bit value built from the two ASCII characters specified by A, B,
+ C and D.
+
+**/
+#define SIGNATURE_32(A, B, C, D) (SIGNATURE_16 (A, B) | (SIGNATURE_16 (C, D) << 16))
+
+/**
+ Returns a 64-bit signature built from 8 ASCII characters.
+
+ This macro returns a 64-bit value built from the eight ASCII characters specified
+ by A, B, C, D, E, F, G,and H.
+
+ @param A The first ASCII character.
+ @param B The second ASCII character.
+ @param C The third ASCII character.
+ @param D The fourth ASCII character.
+ @param E The fifth ASCII character.
+ @param F The sixth ASCII character.
+ @param G The seventh ASCII character.
+ @param H The eighth ASCII character.
+
+ @return A 64-bit value built from the two ASCII characters specified by A, B,
+ C, D, E, F, G and H.
+
+**/
+#define SIGNATURE_64(A, B, C, D, E, F, G, H) \
+ (SIGNATURE_32 (A, B, C, D) | ((UINT64) (SIGNATURE_32 (E, F, G, H)) << 32))
+
+#if defined (_MSC_EXTENSIONS) && !defined (__INTEL_COMPILER) && !defined (MDE_CPU_EBC)
+void *
+_ReturnAddress (
+ void
+ );
+
+ #pragma intrinsic(_ReturnAddress)
+
+/**
+ Get the return address of the calling function.
+
+ Based on intrinsic function _ReturnAddress that provides the address of
+ the instruction in the calling function that will be executed after
+ control returns to the caller.
+
+ @param L Return Level.
+
+ @return The return address of the calling function or 0 if L != 0.
+
+**/
+#define RETURN_ADDRESS(L) ((L == 0) ? _ReturnAddress() : (VOID *) 0)
+#elif defined (__GNUC__) || defined (__clang__)
+
+/**
+ Get the return address of the calling function.
+
+ Based on built-in Function __builtin_return_address that returns
+ the return address of the current function, or of one of its callers.
+
+ @param L Return Level.
+
+ @return The return address of the calling function.
+
+**/
+#define RETURN_ADDRESS(L) __builtin_return_address (L)
+#else
+
+/**
+ Get the return address of the calling function.
+
+ @param L Return Level.
+
+ @return 0 as compilers don't support this feature.
+
+**/
+#define RETURN_ADDRESS(L) ((VOID *) 0)
+#endif
+
+/**
+ Return the number of elements in an array.
+
+ @param Array An object of array type. Array is only used as an argument to
+ the sizeof operator, therefore Array is never evaluated. The
+ caller is responsible for ensuring that Array's type is not
+ incomplete; that is, Array must have known constant size.
+
+ @return The number of elements in Array. The result has type UINTN.
+
+**/
+#ifndef ARRAY_SIZE
+#define ARRAY_SIZE(Array) (sizeof (Array) / sizeof ((Array)[0]))
+#endif
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/ConfidentialComputingGuestAttr.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/ConfidentialComputingGuestAttr.h
new file mode 100644
index 0000000000..a1d6cbb215
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/ConfidentialComputingGuestAttr.h
@@ -0,0 +1,37 @@
+/** @file
+Definitions for Confidential Computing Guest Attributes
+
+Copyright (c) 2021 AMD Inc. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef CONFIDENTIAL_COMPUTING_GUEST_ATTR_H_
+#define CONFIDENTIAL_COMPUTING_GUEST_ATTR_H_
+
+//
+// Confidential computing guest type
+//
+typedef enum {
+ CcGuestTypeNonEncrypted = 0,
+ CcGuestTypeAmdSev,
+ CcGuestTypeIntelTdx,
+} CC_GUEST_TYPE;
+
+typedef enum {
+ /* The guest is running with memory encryption disabled. */
+ CCAttrNotEncrypted = 0,
+
+ /* The guest is running with AMD SEV memory encryption enabled. */
+ CCAttrAmdSev = 0x100,
+ CCAttrAmdSevEs = 0x101,
+ CCAttrAmdSevSnp = 0x102,
+
+ /* The guest is running with Intel TDX memory encryption enabled. */
+ CCAttrIntelTdx = 0x200,
+} CONFIDENTIAL_COMPUTING_GUEST_ATTR;
+
+#define CC_GUEST_IS_TDX(x) ((x) == CCAttrIntelTdx)
+#define CC_GUEST_IS_SEV(x) ((x) == CCAttrAmdSev || (x) == CCAttrAmdSevEs || (x) == CCAttrAmdSevSnp)
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Ebc/ProcessorBind.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Ebc/ProcessorBind.h
new file mode 100644
index 0000000000..6b3733a82b
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Ebc/ProcessorBind.h
@@ -0,0 +1,155 @@
+/** @file
+ Processor or compiler specific defines and types for EBC.
+
+ We currently only have one EBC compiler so there may be some Intel compiler
+ specific functions in this file.
+
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __PROCESSOR_BIND_H__
+#define __PROCESSOR_BIND_H__
+
+///
+/// Define the processor type so other code can make processor based choices
+///
+#define MDE_CPU_EBC
+
+//
+// Native integer types
+//
+
+///
+/// 1-byte signed value
+///
+typedef signed char INT8;
+///
+/// Logical Boolean. 1-byte value containing 0 for FALSE or a 1 for TRUE. Other
+/// values are undefined.
+///
+typedef unsigned char BOOLEAN;
+///
+/// 1-byte unsigned value.
+///
+typedef unsigned char UINT8;
+///
+/// 1-byte Character.
+///
+typedef char CHAR8;
+///
+/// 2-byte signed value.
+///
+typedef short INT16;
+///
+/// 2-byte unsigned value.
+///
+typedef unsigned short UINT16;
+///
+/// 2-byte Character. Unless otherwise specified all strings are stored in the
+/// UTF-16 encoding format as defined by Unicode 2.1 and ISO/IEC 10646 standards.
+///
+typedef unsigned short CHAR16;
+///
+/// 4-byte signed value.
+///
+typedef int INT32;
+///
+/// 4-byte unsigned value.
+///
+typedef unsigned int UINT32;
+///
+/// 8-byte signed value.
+///
+typedef __int64 INT64;
+///
+/// 8-byte unsigned value.
+///
+typedef unsigned __int64 UINT64;
+
+///
+/// Signed value of native width. (4 bytes on supported 32-bit processor instructions,
+/// 8 bytes on supported 64-bit processor instructions)
+/// "long" type scales to the processor native size with EBC compiler
+///
+typedef long INTN;
+///
+/// The unsigned value of native width. (4 bytes on supported 32-bit processor instructions;
+/// 8 bytes on supported 64-bit processor instructions)
+/// "long" type scales to the processor native size with the EBC compiler.
+///
+typedef unsigned long UINTN;
+
+///
+/// A value of native width with the highest bit set.
+/// Scalable macro to set the most significant bit in a natural number.
+///
+#define MAX_BIT ((UINTN)((1ULL << (sizeof (INTN) * 8 - 1))))
+///
+/// A value of native width with the two highest bits set.
+/// Scalable macro to set the most 2 significant bits in a natural number.
+///
+#define MAX_2_BITS ((UINTN)(3ULL << (sizeof (INTN) * 8 - 2)))
+
+///
+/// Maximum legal EBC address
+///
+#define MAX_ADDRESS ((UINTN)(~0ULL >> (64 - sizeof (INTN) * 8)))
+
+///
+/// Maximum usable address at boot time (48 bits using 4 KB pages)
+///
+#define MAX_ALLOC_ADDRESS MAX_ADDRESS
+
+///
+/// Maximum legal EBC INTN and UINTN values.
+///
+#define MAX_UINTN ((UINTN)(~0ULL >> (64 - sizeof (INTN) * 8)))
+#define MAX_INTN ((INTN)(~0ULL >> (65 - sizeof (INTN) * 8)))
+
+///
+/// Minimum legal EBC INTN value.
+///
+#define MIN_INTN (((INTN)-MAX_INTN) - 1)
+
+///
+/// The stack alignment required for EBC
+///
+#define CPU_STACK_ALIGNMENT sizeof(UINTN)
+
+///
+/// Page allocation granularity for EBC
+///
+#define DEFAULT_PAGE_ALLOCATION_GRANULARITY (0x1000)
+#define RUNTIME_PAGE_ALLOCATION_GRANULARITY (0x1000)
+
+///
+/// Modifier to ensure that all protocol member functions and EFI intrinsics
+/// use the correct C calling convention. All protocol member functions and
+/// EFI intrinsics are required to modify their member functions with EFIAPI.
+///
+#ifdef EFIAPI
+///
+/// If EFIAPI is already defined, then we use that definition.
+///
+#else
+#define EFIAPI
+#endif
+
+/**
+ Return the pointer to the first instruction of a function given a function pointer.
+ On EBC architectures, these two pointer values are the same,
+ so the implementation of this macro is very simple.
+
+ @param FunctionPointer A pointer to a function.
+
+ @return The pointer to the first instruction of a function given a function pointer.
+**/
+#define FUNCTION_ENTRY_POINT(FunctionPointer) (VOID *)(UINTN)(FunctionPointer)
+
+#ifndef __USER_LABEL_PREFIX__
+#define __USER_LABEL_PREFIX__
+#endif
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Guid/Acpi.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Guid/Acpi.h
new file mode 100644
index 0000000000..9e9d6b5f05
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Guid/Acpi.h
@@ -0,0 +1,40 @@
+/** @file
+ GUIDs used for ACPI entries in the EFI system table
+
+ These GUIDs point the ACPI tables as defined in the ACPI specifications.
+ ACPI 2.0 specification defines the ACPI 2.0 GUID. UEFI 2.0 defines the
+ ACPI 2.0 Table GUID and ACPI Table GUID.
+
+ Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Revision Reference:
+ GUIDs defined in UEFI 2.0 spec.
+
+**/
+
+#ifndef __ACPI_GUID_H__
+#define __ACPI_GUID_H__
+
+#define ACPI_TABLE_GUID \
+ { \
+ 0xeb9d2d30, 0x2d88, 0x11d3, {0x9a, 0x16, 0x0, 0x90, 0x27, 0x3f, 0xc1, 0x4d } \
+ }
+
+#define EFI_ACPI_TABLE_GUID \
+ { \
+ 0x8868e871, 0xe4f1, 0x11d3, {0xbc, 0x22, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \
+ }
+
+#define ACPI_10_TABLE_GUID ACPI_TABLE_GUID
+
+//
+// ACPI 2.0 or newer tables should use EFI_ACPI_TABLE_GUID.
+//
+#define EFI_ACPI_20_TABLE_GUID EFI_ACPI_TABLE_GUID
+
+extern EFI_GUID gEfiAcpiTableGuid;
+extern EFI_GUID gEfiAcpi10TableGuid;
+extern EFI_GUID gEfiAcpi20TableGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Guid/Apriori.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Guid/Apriori.h
new file mode 100644
index 0000000000..1016345549
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Guid/Apriori.h
@@ -0,0 +1,24 @@
+/** @file
+ GUID used as an FV filename for A Priori file. The A Priori file contains a
+ list of FV filenames that the DXE dispatcher will schedule reguardless of
+ the dependency grammar.
+
+ Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Revision Reference:
+ GUID introduced in PI Version 1.0.
+
+**/
+
+#ifndef __APRIORI_GUID_H__
+#define __APRIORI_GUID_H__
+
+#define EFI_APRIORI_GUID \
+ { \
+ 0xfc510ee7, 0xffdc, 0x11d4, {0xbd, 0x41, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \
+ }
+
+extern EFI_GUID gAprioriGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Guid/AprioriFileName.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Guid/AprioriFileName.h
new file mode 100644
index 0000000000..902ed86264
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Guid/AprioriFileName.h
@@ -0,0 +1,36 @@
+/** @file
+ The GUID PEI_APRIORI_FILE_NAME_GUID definition is the file
+ name of the PEI a priori file that is stored in a firmware
+ volume.
+
+ Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Revision Reference:
+ GUID introduced in PI Version 1.0.
+
+**/
+
+#ifndef __PEI_APRIORI_FILE_NAME_H__
+#define __PEI_APRIORI_FILE_NAME_H__
+
+#define PEI_APRIORI_FILE_NAME_GUID \
+ { 0x1b45cc0a, 0x156a, 0x428a, { 0x62, 0XAF, 0x49, 0x86, 0x4d, 0xa0, 0xe6, 0xe6 } }
+
+///
+/// This file must be of type EFI_FV_FILETYPE_FREEFORM and must
+/// contain a single section of type EFI_SECTION_RAW. For details on
+/// firmware volumes, firmware file types, and firmware file section
+/// types.
+///
+typedef struct {
+ ///
+ /// An array of zero or more EFI_GUID type entries that match the file names of PEIM
+ /// modules in the same Firmware Volume. The maximum number of entries.
+ ///
+ EFI_GUID FileNamesWithinVolume[1];
+} PEI_APRIORI_FILE_CONTENTS;
+
+extern EFI_GUID gPeiAprioriFileNameGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Guid/Btt.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Guid/Btt.h
new file mode 100644
index 0000000000..9f24120499
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Guid/Btt.h
@@ -0,0 +1,222 @@
+/** @file
+ Block Translation Table (BTT) metadata layout definition.
+
+ BTT is a layout and set of rules for doing block I/O that provide powerfail
+ write atomicity of a single block.
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Revision Reference:
+ This metadata layout definition was introduced in UEFI Specification 2.7.
+
+**/
+
+#ifndef _BTT_H_
+#define _BTT_H_
+
+///
+/// The BTT layout and behavior is described by the GUID as below.
+///
+#define EFI_BTT_ABSTRACTION_GUID \
+ { \
+ 0x18633bfc, 0x1735, 0x4217, { 0x8a, 0xc9, 0x17, 0x23, 0x92, 0x82, 0xd3, 0xf8 } \
+ }
+
+//
+// Alignment of all BTT structures
+//
+#define EFI_BTT_ALIGNMENT 4096
+
+#define EFI_BTT_INFO_UNUSED_LEN 3968
+
+#define EFI_BTT_INFO_BLOCK_SIG_LEN 16
+
+///
+/// Indicate inconsistent metadata or lost metadata due to unrecoverable media errors.
+///
+#define EFI_BTT_INFO_BLOCK_FLAGS_ERROR 0x00000001
+
+#define EFI_BTT_INFO_BLOCK_MAJOR_VERSION 2
+#define EFI_BTT_INFO_BLOCK_MINOR_VERSION 0
+
+///
+/// Block Translation Table (BTT) Info Block
+///
+typedef struct _EFI_BTT_INFO_BLOCK {
+ ///
+ /// Signature of the BTT Index Block data structure.
+ /// Shall be "BTT_ARENA_INFO\0\0".
+ ///
+ CHAR8 Sig[EFI_BTT_INFO_BLOCK_SIG_LEN];
+
+ ///
+ /// UUID identifying this BTT instance.
+ ///
+ GUID Uuid;
+
+ ///
+ /// UUID of containing namespace.
+ ///
+ GUID ParentUuid;
+
+ ///
+ /// Attributes of this BTT Info Block.
+ ///
+ UINT32 Flags;
+
+ ///
+ /// Major version number. Currently at version 2.
+ ///
+ UINT16 Major;
+
+ ///
+ /// Minor version number. Currently at version 0.
+ ///
+ UINT16 Minor;
+
+ ///
+ /// Advertised LBA size in bytes. I/O requests shall be in this size chunk.
+ ///
+ UINT32 ExternalLbaSize;
+
+ ///
+ /// Advertised number of LBAs in this arena.
+ ///
+ UINT32 ExternalNLba;
+
+ ///
+ /// Internal LBA size shall be greater than or equal to ExternalLbaSize and shall not be smaller than 512 bytes.
+ ///
+ UINT32 InternalLbaSize;
+
+ ///
+ /// Number of internal blocks in the arena data area.
+ ///
+ UINT32 InternalNLba;
+
+ ///
+ /// Number of free blocks maintained for writes to this arena.
+ ///
+ UINT32 NFree;
+
+ ///
+ /// The size of this info block in bytes.
+ ///
+ UINT32 InfoSize;
+
+ ///
+ /// Offset of next arena, relative to the beginning of this arena.
+ ///
+ UINT64 NextOff;
+
+ ///
+ /// Offset of the data area for this arena, relative to the beginning of this arena.
+ ///
+ UINT64 DataOff;
+
+ ///
+ /// Offset of the map for this arena, relative to the beginning of this arena.
+ ///
+ UINT64 MapOff;
+
+ ///
+ /// Offset of the flog for this arena, relative to the beginning of this arena.
+ ///
+ UINT64 FlogOff;
+
+ ///
+ /// Offset of the backup copy of this arena's info block, relative to the beginning of this arena.
+ ///
+ UINT64 InfoOff;
+
+ ///
+ /// Shall be zero.
+ ///
+ CHAR8 Unused[EFI_BTT_INFO_UNUSED_LEN];
+
+ ///
+ /// 64-bit Fletcher64 checksum of all fields.
+ ///
+ UINT64 Checksum;
+} EFI_BTT_INFO_BLOCK;
+
+///
+/// BTT Map entry maps an LBA that indexes into the arena, to its actual location.
+///
+typedef struct _EFI_BTT_MAP_ENTRY {
+ ///
+ /// Post-map LBA number (block number in this arena's data area)
+ ///
+ UINT32 PostMapLba : 30;
+
+ ///
+ /// When set and Zero is not set, reads on this block return an error.
+ /// When set and Zero is set, indicate a map entry in its normal, non-error state.
+ ///
+ UINT32 Error : 1;
+
+ ///
+ /// When set and Error is not set, reads on this block return a full block of zeros.
+ /// When set and Error is set, indicate a map entry in its normal, non-error state.
+ ///
+ UINT32 Zero : 1;
+} EFI_BTT_MAP_ENTRY;
+
+///
+/// Alignment of each flog structure
+///
+#define EFI_BTT_FLOG_ENTRY_ALIGNMENT 64
+
+///
+/// The BTT Flog is both a free list and a log.
+/// The Flog size is determined by the EFI_BTT_INFO_BLOCK.NFree which determines how many of these flog
+/// entries there are.
+/// The Flog location is the highest aligned address in the arena after space for the backup info block.
+///
+typedef struct _EFI_BTT_FLOG {
+ ///
+ /// Last pre-map LBA written using this flog entry.
+ ///
+ UINT32 Lba0;
+
+ ///
+ /// Old post-map LBA.
+ ///
+ UINT32 OldMap0;
+
+ ///
+ /// New post-map LBA.
+ ///
+ UINT32 NewMap0;
+
+ ///
+ /// The Seq0 field in each flog entry is used to determine which set of fields is newer between the two sets
+ /// (Lba0, OldMap0, NewMpa0, Seq0 vs Lba1, Oldmap1, NewMap1, Seq1).
+ ///
+ UINT32 Seq0;
+
+ ///
+ /// Alternate lba entry.
+ ///
+ UINT32 Lba1;
+
+ ///
+ /// Alternate old entry.
+ ///
+ UINT32 OldMap1;
+
+ ///
+ /// Alternate new entry.
+ ///
+ UINT32 NewMap1;
+
+ ///
+ /// Alternate Seq entry.
+ ///
+ UINT32 Seq1;
+} EFI_BTT_FLOG;
+
+extern GUID gEfiBttAbstractionGuid;
+
+#endif //_BTT_H_
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Guid/CapsuleReport.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Guid/CapsuleReport.h
new file mode 100644
index 0000000000..6aafde9d1a
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Guid/CapsuleReport.h
@@ -0,0 +1,122 @@
+/** @file
+ Guid & data structure used for Capsule process result variables
+
+ Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Revision Reference:
+ GUIDs defined in UEFI 2.4 spec.
+
+**/
+
+#ifndef _CAPSULE_REPORT_GUID_H__
+#define _CAPSULE_REPORT_GUID_H__
+
+//
+// This is the GUID for capsule result variable.
+//
+#define EFI_CAPSULE_REPORT_GUID \
+ { \
+ 0x39b68c46, 0xf7fb, 0x441b, {0xb6, 0xec, 0x16, 0xb0, 0xf6, 0x98, 0x21, 0xf3 } \
+ }
+
+typedef struct {
+ ///
+ /// Size in bytes of the variable including any data beyond header as specified by CapsuleGuid
+ ///
+ UINT32 VariableTotalSize;
+
+ ///
+ /// For alignment
+ ///
+ UINT32 Reserved;
+
+ ///
+ /// Guid from EFI_CAPSULE_HEADER
+ ///
+ EFI_GUID CapsuleGuid;
+
+ ///
+ /// Timestamp using system time when processing completed
+ ///
+ EFI_TIME CapsuleProcessed;
+
+ ///
+ /// Result of the capsule processing. Exact interpretation of any error code may depend
+ /// upon type of capsule processed
+ ///
+ EFI_STATUS CapsuleStatus;
+} EFI_CAPSULE_RESULT_VARIABLE_HEADER;
+
+typedef struct {
+ ///
+ /// Version of this structure, currently 0x00000001
+ ///
+ UINT16 Version;
+
+ ///
+ /// The index of the payload within the FMP capsule which was processed to generate this report
+ /// Starting from zero
+ ///
+ UINT8 PayloadIndex;
+
+ ///
+ /// The UpdateImageIndex from EFI_FIRMWARE_MANAGEMENT_CAPSULE_IMAGE_HEADER
+ /// (after unsigned conversion from UINT8 to UINT16).
+ ///
+ UINT8 UpdateImageIndex;
+
+ ///
+ /// The UpdateImageTypeId Guid from EFI_FIRMWARE_MANAGEMENT_CAPSULE_IMAGE_HEADER.
+ ///
+ EFI_GUID UpdateImageTypeId;
+
+ ///
+ /// In case of capsule loaded from disk, the zero-terminated array containing file name of capsule that was processed.
+ /// In case of capsule submitted directly to UpdateCapsule() there is no file name, and this field is required to contain a single 16-bit zero character
+ /// which is included in VariableTotalSize.
+ ///
+ /// CHAR16 CapsuleFileName[];
+ ///
+
+ ///
+ /// This field will contain a zero-terminated CHAR16 string containing the text representation of the device path of device publishing Firmware Management Protocol
+ /// (if present). In case where device path is not present and the target is not otherwise known to firmware, or when payload was blocked by policy, or skipped,
+ /// this field is required to contain a single 16-bit zero character which is included in VariableTotalSize.
+ ///
+ /// CHAR16 CapsuleTarget[];
+ ///
+} EFI_CAPSULE_RESULT_VARIABLE_FMP;
+
+typedef struct {
+ ///
+ /// Version of this structure, currently 0x00000001
+ ///
+ UINT32 Version;
+
+ ///
+ /// The unique identifier of the capsule whose processing result is recorded in this variable.
+ /// 0x00000000 - 0xEFFFFFFF - Implementation Reserved
+ /// 0xF0000000 - 0xFFFFFFFF - Specification Reserved
+ /// #define REDFISH_DEFINED_JSON_SCHEMA 0xF000000
+ /// The JSON payload shall conform to a Redfish-defined JSON schema, see DMTF-Redfish
+ /// Specification.
+ ///
+ UINT32 CapsuleId;
+
+ ///
+ /// The length of Resp in bytes.
+ ///
+ UINT32 RespLength;
+
+ ///
+ /// Variable length buffer containing the replied JSON payload to the caller who delivered JSON
+ /// capsule to system. The definition of the JSON schema used in the replied payload is beyond
+ /// the scope of this specification.
+ ///
+ UINT8 Resp[];
+} EFI_CAPSULE_RESULT_VARIABLE_JSON;
+
+extern EFI_GUID gEfiCapsuleReportGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Guid/Cper.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Guid/Cper.h
new file mode 100644
index 0000000000..9b05c8c120
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Guid/Cper.h
@@ -0,0 +1,1251 @@
+/** @file
+ GUIDs and definitions used for Common Platform Error Record.
+
+ Copyright (c) 2011 - 2017, Intel Corporation. All rights reserved.
+ (C) Copyright 2016 Hewlett Packard Enterprise Development LP
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Revision Reference:
+ GUIDs defined in UEFI 2.7 Specification.
+
+**/
+
+#ifndef __CPER_GUID_H__
+#define __CPER_GUID_H__
+
+#pragma pack(1)
+
+#define EFI_ERROR_RECORD_SIGNATURE_START SIGNATURE_32('C', 'P', 'E', 'R')
+#define EFI_ERROR_RECORD_SIGNATURE_END 0xFFFFFFFF
+
+#define EFI_ERROR_RECORD_REVISION 0x0101
+
+///
+/// Error Severity in Error Record Header and Error Section Descriptor
+///@{
+#define EFI_GENERIC_ERROR_RECOVERABLE 0x00000000
+#define EFI_GENERIC_ERROR_FATAL 0x00000001
+#define EFI_GENERIC_ERROR_CORRECTED 0x00000002
+#define EFI_GENERIC_ERROR_INFO 0x00000003
+///@}
+
+///
+/// The validation bit mask indicates the validity of the following fields
+/// in Error Record Header.
+///@{
+#define EFI_ERROR_RECORD_HEADER_PLATFORM_ID_VALID BIT0
+#define EFI_ERROR_RECORD_HEADER_TIME_STAMP_VALID BIT1
+#define EFI_ERROR_RECORD_HEADER_PARTITION_ID_VALID BIT2
+///@}
+
+///
+/// Timestamp is precise if this bit is set and correlates to the time of the
+/// error event.
+///
+#define EFI_ERROR_TIME_STAMP_PRECISE BIT0
+
+///
+/// The timestamp correlates to the time when the error information was collected
+/// by the system software and may not necessarily represent the time of the error
+/// event. The timestamp contains the local time in BCD format.
+///
+typedef struct {
+ UINT8 Seconds;
+ UINT8 Minutes;
+ UINT8 Hours;
+ UINT8 Flag;
+ UINT8 Day;
+ UINT8 Month;
+ UINT8 Year;
+ UINT8 Century;
+} EFI_ERROR_TIME_STAMP;
+
+///
+/// GUID value indicating the record association with an error event notification type.
+///@{
+#define EFI_EVENT_NOTIFICATION_TYEP_CMC_GUID \
+ { \
+ 0x2DCE8BB1, 0xBDD7, 0x450e, { 0xB9, 0xAD, 0x9C, 0xF4, 0xEB, 0xD4, 0xF8, 0x90 } \
+ }
+#define EFI_EVENT_NOTIFICATION_TYEP_CPE_GUID \
+ { \
+ 0x4E292F96, 0xD843, 0x4a55, { 0xA8, 0xC2, 0xD4, 0x81, 0xF2, 0x7E, 0xBE, 0xEE } \
+ }
+#define EFI_EVENT_NOTIFICATION_TYEP_MCE_GUID \
+ { \
+ 0xE8F56FFE, 0x919C, 0x4cc5, { 0xBA, 0x88, 0x65, 0xAB, 0xE1, 0x49, 0x13, 0xBB } \
+ }
+#define EFI_EVENT_NOTIFICATION_TYEP_PCIE_GUID \
+ { \
+ 0xCF93C01F, 0x1A16, 0x4dfc, { 0xB8, 0xBC, 0x9C, 0x4D, 0xAF, 0x67, 0xC1, 0x04 } \
+ }
+#define EFI_EVENT_NOTIFICATION_TYEP_INIT_GUID \
+ { \
+ 0xCC5263E8, 0x9308, 0x454a, { 0x89, 0xD0, 0x34, 0x0B, 0xD3, 0x9B, 0xC9, 0x8E } \
+ }
+#define EFI_EVENT_NOTIFICATION_TYEP_NMI_GUID \
+ { \
+ 0x5BAD89FF, 0xB7E6, 0x42c9, { 0x81, 0x4A, 0xCF, 0x24, 0x85, 0xD6, 0xE9, 0x8A } \
+ }
+#define EFI_EVENT_NOTIFICATION_TYEP_BOOT_GUID \
+ { \
+ 0x3D61A466, 0xAB40, 0x409a, { 0xA6, 0x98, 0xF3, 0x62, 0xD4, 0x64, 0xB3, 0x8F } \
+ }
+#define EFI_EVENT_NOTIFICATION_TYEP_DMAR_GUID \
+ { \
+ 0x667DD791, 0xC6B3, 0x4c27, { 0x8A, 0x6B, 0x0F, 0x8E, 0x72, 0x2D, 0xEB, 0x41 } \
+ }
+#define EFI_EVENT_NOTIFICATION_TYPE_DMAR_SEA \
+ { \
+ 0x9A78788A, 0xBBE8, 0x11E4, { 0x80, 0x9E, 0x67, 0x61, 0x1E, 0x5D, 0x46, 0xB0 } \
+ }
+#define EFI_EVENT_NOTIFICATION_TYPE_DMAR_SEI \
+ { \
+ 0x5C284C81, 0xB0AE, 0x4E87, { 0xA3, 0x22, 0xB0, 0x4C, 0x85, 0x62, 0x43, 0x23 } \
+ }
+#define EFI_EVENT_NOTIFICATION_TYPE_DMAR_PEI \
+ { \
+ 0x09A9D5AC, 0x5204, 0x4214, { 0x96, 0xE5, 0x94, 0x99, 0x2E, 0x75, 0x2B, 0xCD } \
+ }
+///@}
+
+///
+/// Error Record Header Flags
+///@{
+#define EFI_HW_ERROR_FLAGS_RECOVERED 0x00000001
+#define EFI_HW_ERROR_FLAGS_PREVERR 0x00000002
+#define EFI_HW_ERROR_FLAGS_SIMULATED 0x00000004
+///@}
+
+///
+/// Common error record header
+///
+typedef struct {
+ UINT32 SignatureStart;
+ UINT16 Revision;
+ UINT32 SignatureEnd;
+ UINT16 SectionCount;
+ UINT32 ErrorSeverity;
+ UINT32 ValidationBits;
+ UINT32 RecordLength;
+ EFI_ERROR_TIME_STAMP TimeStamp;
+ EFI_GUID PlatformID;
+ EFI_GUID PartitionID;
+ EFI_GUID CreatorID;
+ EFI_GUID NotificationType;
+ UINT64 RecordID;
+ UINT32 Flags;
+ UINT64 PersistenceInfo;
+ UINT8 Resv1[12];
+ ///
+ /// An array of SectionCount descriptors for the associated
+ /// sections. The number of valid sections is equivalent to the
+ /// SectionCount. The buffer size of the record may include
+ /// more space to dynamically add additional Section
+ /// Descriptors to the error record.
+ ///
+} EFI_COMMON_ERROR_RECORD_HEADER;
+
+#define EFI_ERROR_SECTION_REVISION 0x0100
+
+///
+/// Validity Fields in Error Section Descriptor.
+///
+#define EFI_ERROR_SECTION_FRU_ID_VALID BIT0
+#define EFI_ERROR_SECTION_FRU_STRING_VALID BIT1
+
+///
+/// Flag field contains information that describes the error section
+/// in Error Section Descriptor.
+///
+#define EFI_ERROR_SECTION_FLAGS_PRIMARY BIT0
+#define EFI_ERROR_SECTION_FLAGS_CONTAINMENT_WARNING BIT1
+#define EFI_ERROR_SECTION_FLAGS_RESET BIT2
+#define EFI_ERROR_SECTION_FLAGS_ERROR_THRESHOLD_EXCEEDED BIT3
+#define EFI_ERROR_SECTION_FLAGS_RESOURCE_NOT_ACCESSIBLE BIT4
+#define EFI_ERROR_SECTION_FLAGS_LATENT_ERROR BIT5
+
+///
+/// Error Sectition Type GUIDs in Error Section Descriptor
+///@{
+#define EFI_ERROR_SECTION_PROCESSOR_GENERIC_GUID \
+ { \
+ 0x9876ccad, 0x47b4, 0x4bdb, { 0xb6, 0x5e, 0x16, 0xf1, 0x93, 0xc4, 0xf3, 0xdb } \
+ }
+#define EFI_ERROR_SECTION_PROCESSOR_SPECIFIC_GUID \
+ { \
+ 0xdc3ea0b0, 0xa144, 0x4797, { 0xb9, 0x5b, 0x53, 0xfa, 0x24, 0x2b, 0x6e, 0x1d } \
+ }
+#define EFI_ERROR_SECTION_PROCESSOR_SPECIFIC_IA32X64_GUID \
+ { \
+ 0xdc3ea0b0, 0xa144, 0x4797, { 0xb9, 0x5b, 0x53, 0xfa, 0x24, 0x2b, 0x6e, 0x1d } \
+ }
+#define EFI_ERROR_SECTION_PROCESSOR_SPECIFIC_ARM_GUID \
+ { \
+ 0xe19e3d16, 0xbc11, 0x11e4, { 0x9c, 0xaa, 0xc2, 0x05, 0x1d, 0x5d, 0x46, 0xb0 } \
+ }
+#define EFI_ERROR_SECTION_PLATFORM_MEMORY_GUID \
+ { \
+ 0xa5bc1114, 0x6f64, 0x4ede, { 0xb8, 0x63, 0x3e, 0x83, 0xed, 0x7c, 0x83, 0xb1 } \
+ }
+#define EFI_ERROR_SECTION_PLATFORM_MEMORY2_GUID \
+ { \
+ 0x61EC04FC, 0x48E6, 0xD813, { 0x25, 0xC9, 0x8D, 0xAA, 0x44, 0x75, 0x0B, 0x12 } \
+ }
+#define EFI_ERROR_SECTION_PCIE_GUID \
+ { \
+ 0xd995e954, 0xbbc1, 0x430f, { 0xad, 0x91, 0xb4, 0x4d, 0xcb, 0x3c, 0x6f, 0x35 } \
+ }
+#define EFI_ERROR_SECTION_FW_ERROR_RECORD_GUID \
+ { \
+ 0x81212a96, 0x09ed, 0x4996, { 0x94, 0x71, 0x8d, 0x72, 0x9c, 0x8e, 0x69, 0xed } \
+ }
+#define EFI_ERROR_SECTION_PCI_PCIX_BUS_GUID \
+ { \
+ 0xc5753963, 0x3b84, 0x4095, { 0xbf, 0x78, 0xed, 0xda, 0xd3, 0xf9, 0xc9, 0xdd } \
+ }
+#define EFI_ERROR_SECTION_PCI_DEVICE_GUID \
+ { \
+ 0xeb5e4685, 0xca66, 0x4769, { 0xb6, 0xa2, 0x26, 0x06, 0x8b, 0x00, 0x13, 0x26 } \
+ }
+#define EFI_ERROR_SECTION_DMAR_GENERIC_GUID \
+ { \
+ 0x5b51fef7, 0xc79d, 0x4434, { 0x8f, 0x1b, 0xaa, 0x62, 0xde, 0x3e, 0x2c, 0x64 } \
+ }
+#define EFI_ERROR_SECTION_DIRECTED_IO_DMAR_GUID \
+ { \
+ 0x71761d37, 0x32b2, 0x45cd, { 0xa7, 0xd0, 0xb0, 0xfe, 0xdd, 0x93, 0xe8, 0xcf } \
+ }
+#define EFI_ERROR_SECTION_IOMMU_DMAR_GUID \
+ { \
+ 0x036f84e1, 0x7f37, 0x428c, { 0xa7, 0x9e, 0x57, 0x5f, 0xdf, 0xaa, 0x84, 0xec } \
+ }
+///@}
+
+///
+/// Error Section Descriptor
+///
+typedef struct {
+ UINT32 SectionOffset;
+ UINT32 SectionLength;
+ UINT16 Revision;
+ UINT8 SecValidMask;
+ UINT8 Resv1;
+ UINT32 SectionFlags;
+ EFI_GUID SectionType;
+ EFI_GUID FruId;
+ UINT32 Severity;
+ CHAR8 FruString[20];
+} EFI_ERROR_SECTION_DESCRIPTOR;
+
+///
+/// The validation bit mask indicates whether or not each of the following fields are
+/// valid in Proessor Generic Error section.
+///@{
+#define EFI_GENERIC_ERROR_PROC_TYPE_VALID BIT0
+#define EFI_GENERIC_ERROR_PROC_ISA_VALID BIT1
+#define EFI_GENERIC_ERROR_PROC_ERROR_TYPE_VALID BIT2
+#define EFI_GENERIC_ERROR_PROC_OPERATION_VALID BIT3
+#define EFI_GENERIC_ERROR_PROC_FLAGS_VALID BIT4
+#define EFI_GENERIC_ERROR_PROC_LEVEL_VALID BIT5
+#define EFI_GENERIC_ERROR_PROC_VERSION_VALID BIT6
+#define EFI_GENERIC_ERROR_PROC_BRAND_VALID BIT7
+#define EFI_GENERIC_ERROR_PROC_ID_VALID BIT8
+#define EFI_GENERIC_ERROR_PROC_TARGET_ADDR_VALID BIT9
+#define EFI_GENERIC_ERROR_PROC_REQUESTER_ID_VALID BIT10
+#define EFI_GENERIC_ERROR_PROC_RESPONDER_ID_VALID BIT11
+#define EFI_GENERIC_ERROR_PROC_INST_IP_VALID BIT12
+///@}
+
+///
+/// The type of the processor architecture in Proessor Generic Error section.
+///@{
+#define EFI_GENERIC_ERROR_PROC_TYPE_IA32_X64 0x00
+#define EFI_GENERIC_ERROR_PROC_TYPE_IA64 0x01
+#define EFI_GENERIC_ERROR_PROC_TYPE_ARM 0x02
+///@}
+
+///
+/// The type of the instruction set executing when the error occurred in Proessor
+/// Generic Error section.
+///@{
+#define EFI_GENERIC_ERROR_PROC_ISA_IA32 0x00
+#define EFI_GENERIC_ERROR_PROC_ISA_IA64 0x01
+#define EFI_GENERIC_ERROR_PROC_ISA_X64 0x02
+#define EFI_GENERIC_ERROR_PROC_ISA_ARM_A32_T32 0x03
+#define EFI_GENERIC_ERROR_PROC_ISA_ARM_A64 0x04
+///@}
+
+///
+/// The type of error that occurred in Proessor Generic Error section.
+///@{
+#define EFI_GENERIC_ERROR_PROC_ERROR_TYPE_UNKNOWN 0x00
+#define EFI_GENERIC_ERROR_PROC_ERROR_TYPE_CACHE 0x01
+#define EFI_GENERIC_ERROR_PROC_ERROR_TYPE_TLB 0x02
+#define EFI_GENERIC_ERROR_PROC_ERROR_TYPE_BUS 0x04
+#define EFI_GENERIC_ERROR_PROC_ERROR_TYPE_MICRO_ARCH 0x08
+///@}
+
+///
+/// The type of operation in Proessor Generic Error section.
+///@{
+#define EFI_GENERIC_ERROR_PROC_OPERATION_GENERIC 0x00
+#define EFI_GENERIC_ERROR_PROC_OPERATION_DATA_READ 0x01
+#define EFI_GENERIC_ERROR_PROC_OPERATION_DATA_WRITE 0x02
+#define EFI_GENERIC_ERROR_PROC_OPERATION_INSTRUCTION_EXEC 0x03
+///@}
+
+///
+/// Flags bit mask indicates additional information about the error in Proessor Generic
+/// Error section
+///@{
+#define EFI_GENERIC_ERROR_PROC_FLAGS_RESTARTABLE BIT0
+#define EFI_GENERIC_ERROR_PROC_FLAGS_PRECISE_IP BIT1
+#define EFI_GENERIC_ERROR_PROC_FLAGS_OVERFLOW BIT2
+#define EFI_GENERIC_ERROR_PROC_FLAGS_CORRECTED BIT3
+///@}
+
+///
+/// Processor Generic Error Section
+/// describes processor reported hardware errors for logical processors in the system.
+///
+typedef struct {
+ UINT64 ValidFields;
+ UINT8 Type;
+ UINT8 Isa;
+ UINT8 ErrorType;
+ UINT8 Operation;
+ UINT8 Flags;
+ UINT8 Level;
+ UINT16 Resv1;
+ UINT64 VersionInfo;
+ CHAR8 BrandString[128];
+ UINT64 ApicId;
+ UINT64 TargetAddr;
+ UINT64 RequestorId;
+ UINT64 ResponderId;
+ UINT64 InstructionIP;
+} EFI_PROCESSOR_GENERIC_ERROR_DATA;
+
+#if defined (MDE_CPU_IA32) || defined (MDE_CPU_X64)
+///
+/// IA32 and x64 Specific definitions.
+///
+
+///
+/// GUID value indicating the type of Processor Error Information structure
+/// in IA32/X64 Processor Error Information Structure.
+///@{
+#define EFI_IA32_X64_ERROR_TYPE_CACHE_CHECK_GUID \
+ { \
+ 0xA55701F5, 0xE3EF, 0x43de, {0xAC, 0x72, 0x24, 0x9B, 0x57, 0x3F, 0xAD, 0x2C } \
+ }
+#define EFI_IA32_X64_ERROR_TYPE_TLB_CHECK_GUID \
+ { \
+ 0xFC06B535, 0x5E1F, 0x4562, {0x9F, 0x25, 0x0A, 0x3B, 0x9A, 0xDB, 0x63, 0xC3 } \
+ }
+#define EFI_IA32_X64_ERROR_TYPE_BUS_CHECK_GUID \
+ { \
+ 0x1CF3F8B3, 0xC5B1, 0x49a2, {0xAA, 0x59, 0x5E, 0xEF, 0x92, 0xFF, 0xA6, 0x3C } \
+ }
+#define EFI_IA32_X64_ERROR_TYPE_MS_CHECK_GUID \
+ { \
+ 0x48AB7F57, 0xDC34, 0x4f6c, {0xA7, 0xD3, 0xB0, 0xB5, 0xB0, 0xA7, 0x43, 0x14 } \
+ }
+///@}
+
+///
+/// The validation bit mask indicates which fields in the IA32/X64 Processor
+/// Error Record structure are valid.
+///@{
+#define EFI_IA32_X64_PROCESSOR_ERROR_APIC_ID_VALID BIT0
+#define EFI_IA32_X64_PROCESSOR_ERROR_CPU_ID_INFO_VALID BIT1
+///@}
+
+///
+/// IA32/X64 Processor Error Record
+///
+typedef struct {
+ UINT64 ValidFields;
+ UINT64 ApicId;
+ UINT8 CpuIdInfo[48];
+} EFI_IA32_X64_PROCESSOR_ERROR_RECORD;
+
+///
+/// The validation bit mask indicates which fields in the Cache Check structure
+/// are valid.
+///@{
+#define EFI_CACHE_CHECK_TRANSACTION_TYPE_VALID BIT0
+#define EFI_CACHE_CHECK_OPERATION_VALID BIT1
+#define EFI_CACHE_CHECK_LEVEL_VALID BIT2
+#define EFI_CACHE_CHECK_CONTEXT_CORRUPT_VALID BIT3
+#define EFI_CACHE_CHECK_UNCORRECTED_VALID BIT4
+#define EFI_CACHE_CHECK_PRECISE_IP_VALID BIT5
+#define EFI_CACHE_CHECK_RESTARTABLE_VALID BIT6
+#define EFI_CACHE_CHECK_OVERFLOW_VALID BIT7
+///@}
+
+///
+/// Type of cache error in the Cache Check structure
+///@{
+#define EFI_CACHE_CHECK_ERROR_TYPE_INSTRUCTION 0
+#define EFI_CACHE_CHECK_ERROR_TYPE_DATA_ACCESS 1
+#define EFI_CACHE_CHECK_ERROR_TYPE_GENERIC 2
+///@}
+
+///
+/// Type of cache operation that caused the error in the Cache
+/// Check structure
+///@{
+#define EFI_CACHE_CHECK_OPERATION_TYPE_GENERIC 0
+#define EFI_CACHE_CHECK_OPERATION_TYPE_GENERIC_READ 1
+#define EFI_CACHE_CHECK_OPERATION_TYPE_GENERIC_WRITE 2
+#define EFI_CACHE_CHECK_OPERATION_TYPE_DATA_READ 3
+#define EFI_CACHE_CHECK_OPERATION_TYPE_DATA_WRITE 4
+#define EFI_CACHE_CHECK_OPERATION_TYPE_INSTRUCTION_FETCH 5
+#define EFI_CACHE_CHECK_OPERATION_TYPE_PREFETCH 6
+#define EFI_CACHE_CHECK_OPERATION_TYPE_EVICTION 7
+#define EFI_CACHE_CHECK_OPERATION_TYPE_SNOOP 8
+///@}
+
+///
+/// IA32/X64 Cache Check Structure
+///
+typedef struct {
+ UINT64 ValidFields : 16;
+ UINT64 TransactionType : 2;
+ UINT64 Operation : 4;
+ UINT64 Level : 3;
+ UINT64 ContextCorrupt : 1;
+ UINT64 ErrorUncorrected : 1;
+ UINT64 PreciseIp : 1;
+ UINT64 RestartableIp : 1;
+ UINT64 Overflow : 1;
+ UINT64 Resv1 : 34;
+} EFI_IA32_X64_CACHE_CHECK_INFO;
+
+///
+/// The validation bit mask indicates which fields in the TLB Check structure
+/// are valid.
+///@{
+#define EFI_TLB_CHECK_TRANSACTION_TYPE_VALID BIT0
+#define EFI_TLB_CHECK_OPERATION_VALID BIT1
+#define EFI_TLB_CHECK_LEVEL_VALID BIT2
+#define EFI_TLB_CHECK_CONTEXT_CORRUPT_VALID BIT3
+#define EFI_TLB_CHECK_UNCORRECTED_VALID BIT4
+#define EFI_TLB_CHECK_PRECISE_IP_VALID BIT5
+#define EFI_TLB_CHECK_RESTARTABLE_VALID BIT6
+#define EFI_TLB_CHECK_OVERFLOW_VALID BIT7
+///@}
+
+///
+/// Type of cache error in the TLB Check structure
+///@{
+#define EFI_TLB_CHECK_ERROR_TYPE_INSTRUCTION 0
+#define EFI_TLB_CHECK_ERROR_TYPE_DATA_ACCESS 1
+#define EFI_TLB_CHECK_ERROR_TYPE_GENERIC 2
+///@}
+
+///
+/// Type of cache operation that caused the error in the TLB
+/// Check structure
+///@{
+#define EFI_TLB_CHECK_OPERATION_TYPE_GENERIC 0
+#define EFI_TLB_CHECK_OPERATION_TYPE_GENERIC_READ 1
+#define EFI_TLB_CHECK_OPERATION_TYPE_GENERIC_WRITE 2
+#define EFI_TLB_CHECK_OPERATION_TYPE_DATA_READ 3
+#define EFI_TLB_CHECK_OPERATION_TYPE_DATA_WRITE 4
+#define EFI_TLB_CHECK_OPERATION_TYPE_INST_FETCH 5
+#define EFI_TLB_CHECK_OPERATION_TYPE_PREFETCH 6
+///@}
+
+///
+/// IA32/X64 TLB Check Structure
+///
+typedef struct {
+ UINT64 ValidFields : 16;
+ UINT64 TransactionType : 2;
+ UINT64 Operation : 4;
+ UINT64 Level : 3;
+ UINT64 ContextCorrupt : 1;
+ UINT64 ErrorUncorrected : 1;
+ UINT64 PreciseIp : 1;
+ UINT64 RestartableIp : 1;
+ UINT64 Overflow : 1;
+ UINT64 Resv1 : 34;
+} EFI_IA32_X64_TLB_CHECK_INFO;
+
+///
+/// The validation bit mask indicates which fields in the MS Check structure
+/// are valid.
+///@{
+#define EFI_BUS_CHECK_TRANSACTION_TYPE_VALID BIT0
+#define EFI_BUS_CHECK_OPERATION_VALID BIT1
+#define EFI_BUS_CHECK_LEVEL_VALID BIT2
+#define EFI_BUS_CHECK_CONTEXT_CORRUPT_VALID BIT3
+#define EFI_BUS_CHECK_UNCORRECTED_VALID BIT4
+#define EFI_BUS_CHECK_PRECISE_IP_VALID BIT5
+#define EFI_BUS_CHECK_RESTARTABLE_VALID BIT6
+#define EFI_BUS_CHECK_OVERFLOW_VALID BIT7
+#define EFI_BUS_CHECK_PARTICIPATION_TYPE_VALID BIT8
+#define EFI_BUS_CHECK_TIME_OUT_VALID BIT9
+#define EFI_BUS_CHECK_ADDRESS_SPACE_VALID BIT10
+///@}
+
+///
+/// Type of cache error in the Bus Check structure
+///@{
+#define EFI_BUS_CHECK_ERROR_TYPE_INSTRUCTION 0
+#define EFI_BUS_CHECK_ERROR_TYPE_DATA_ACCESS 1
+#define EFI_BUS_CHECK_ERROR_TYPE_GENERIC 2
+///@}
+
+///
+/// Type of cache operation that caused the error in the Bus
+/// Check structure
+///@{
+#define EFI_BUS_CHECK_OPERATION_TYPE_GENERIC 0
+#define EFI_BUS_CHECK_OPERATION_TYPE_GENERIC_READ 1
+#define EFI_BUS_CHECK_OPERATION_TYPE_GENERIC_WRITE 2
+#define EFI_BUS_CHECK_OPERATION_TYPE_DATA_READ 3
+#define EFI_BUS_CHECK_OPERATION_TYPE_DATA_WRITE 4
+#define EFI_BUS_CHECK_OPERATION_TYPE_INST_FETCH 5
+#define EFI_BUS_CHECK_OPERATION_TYPE_PREFETCH 6
+///@}
+
+///
+/// Type of Participation
+///@{
+#define EFI_BUS_CHECK_PARTICIPATION_TYPE_REQUEST 0
+#define EFI_BUS_CHECK_PARTICIPATION_TYPE_RESPONDED 1
+#define EFI_BUS_CHECK_PARTICIPATION_TYPE_OBSERVED 2
+#define EFI_BUS_CHECK_PARTICIPATION_TYPE_GENERIC 3
+///@}
+
+///
+/// Type of Address Space
+///@{
+#define EFI_BUS_CHECK_ADDRESS_SPACE_TYPE_MEMORY 0
+#define EFI_BUS_CHECK_ADDRESS_SPACE_TYPE_RESERVED 1
+#define EFI_BUS_CHECK_ADDRESS_SPACE_TYPE_IO 2
+#define EFI_BUS_CHECK_ADDRESS_SPACE_TYPE_OTHER 3
+///@}
+
+///
+/// IA32/X64 Bus Check Structure
+///
+typedef struct {
+ UINT64 ValidFields : 16;
+ UINT64 TransactionType : 2;
+ UINT64 Operation : 4;
+ UINT64 Level : 3;
+ UINT64 ContextCorrupt : 1;
+ UINT64 ErrorUncorrected : 1;
+ UINT64 PreciseIp : 1;
+ UINT64 RestartableIp : 1;
+ UINT64 Overflow : 1;
+ UINT64 ParticipationType : 2;
+ UINT64 TimeOut : 1;
+ UINT64 AddressSpace : 2;
+ UINT64 Resv1 : 29;
+} EFI_IA32_X64_BUS_CHECK_INFO;
+
+///
+/// The validation bit mask indicates which fields in the MS Check structure
+/// are valid.
+///@{
+#define EFI_MS_CHECK_ERROR_TYPE_VALID BIT0
+#define EFI_MS_CHECK_CONTEXT_CORRUPT_VALID BIT1
+#define EFI_MS_CHECK_UNCORRECTED_VALID BIT2
+#define EFI_MS_CHECK_PRECISE_IP_VALID BIT3
+#define EFI_MS_CHECK_RESTARTABLE_VALID BIT4
+#define EFI_MS_CHECK_OVERFLOW_VALID BIT5
+///@}
+
+///
+/// Error type identifies the operation that caused the error.
+///@{
+#define EFI_MS_CHECK_ERROR_TYPE_NO 0
+#define EFI_MS_CHECK_ERROR_TYPE_UNCLASSIFIED 1
+#define EFI_MS_CHECK_ERROR_TYPE_MICROCODE_PARITY 2
+#define EFI_MS_CHECK_ERROR_TYPE_EXTERNAL 3
+#define EFI_MS_CHECK_ERROR_TYPE_FRC 4
+#define EFI_MS_CHECK_ERROR_TYPE_INTERNAL_UNCLASSIFIED 5
+///@}
+
+///
+/// IA32/X64 MS Check Field Description
+///
+typedef struct {
+ UINT64 ValidFields : 16;
+ UINT64 ErrorType : 3;
+ UINT64 ContextCorrupt : 1;
+ UINT64 ErrorUncorrected : 1;
+ UINT64 PreciseIp : 1;
+ UINT64 RestartableIp : 1;
+ UINT64 Overflow : 1;
+ UINT64 Resv1 : 40;
+} EFI_IA32_X64_MS_CHECK_INFO;
+
+///
+/// IA32/X64 Check Information Item
+///
+typedef union {
+ EFI_IA32_X64_CACHE_CHECK_INFO CacheCheck;
+ EFI_IA32_X64_TLB_CHECK_INFO TlbCheck;
+ EFI_IA32_X64_BUS_CHECK_INFO BusCheck;
+ EFI_IA32_X64_MS_CHECK_INFO MsCheck;
+ UINT64 Data64;
+} EFI_IA32_X64_CHECK_INFO_ITEM;
+
+///
+/// The validation bit mask indicates which fields in the IA32/X64 Processor Error
+/// Information Structure are valid.
+///@{
+#define EFI_IA32_X64_ERROR_PROC_CHECK_INFO_VALID BIT0
+#define EFI_IA32_X64_ERROR_PROC_TARGET_ADDR_VALID BIT1
+#define EFI_IA32_X64_ERROR_PROC_REQUESTER_ID_VALID BIT2
+#define EFI_IA32_X64_ERROR_PROC_RESPONDER_ID_VALID BIT3
+#define EFI_IA32_X64_ERROR_PROC_INST_IP_VALID BIT4
+///@}
+
+///
+/// IA32/X64 Processor Error Information Structure
+///
+typedef struct {
+ EFI_GUID ErrorType;
+ UINT64 ValidFields;
+ EFI_IA32_X64_CHECK_INFO_ITEM CheckInfo;
+ UINT64 TargetId;
+ UINT64 RequestorId;
+ UINT64 ResponderId;
+ UINT64 InstructionIP;
+} EFI_IA32_X64_PROCESS_ERROR_INFO;
+
+///
+/// IA32/X64 Processor Context Information Structure
+///
+typedef struct {
+ UINT16 RegisterType;
+ UINT16 ArraySize;
+ UINT32 MsrAddress;
+ UINT64 MmRegisterAddress;
+ //
+ // This field will provide the contents of the actual registers or raw data.
+ // The number of Registers or size of the raw data reported is determined
+ // by (Array Size / 8) or otherwise specified by the context structure type
+ // definition.
+ //
+} EFI_IA32_X64_PROCESSOR_CONTEXT_INFO;
+
+///
+/// Register Context Type
+///@{
+#define EFI_REG_CONTEXT_TYPE_UNCLASSIFIED 0x0000
+#define EFI_REG_CONTEXT_TYPE_MSR 0x0001
+#define EFI_REG_CONTEXT_TYPE_IA32 0x0002
+#define EFI_REG_CONTEXT_TYPE_X64 0x0003
+#define EFI_REG_CONTEXT_TYPE_FXSAVE 0x0004
+#define EFI_REG_CONTEXT_TYPE_DR_IA32 0x0005
+#define EFI_REG_CONTEXT_TYPE_DR_X64 0x0006
+#define EFI_REG_CONTEXT_TYPE_MEM_MAP 0x0007
+///@}
+
+///
+/// IA32 Register State
+///
+typedef struct {
+ UINT32 Eax;
+ UINT32 Ebx;
+ UINT32 Ecx;
+ UINT32 Edx;
+ UINT32 Esi;
+ UINT32 Edi;
+ UINT32 Ebp;
+ UINT32 Esp;
+ UINT16 Cs;
+ UINT16 Ds;
+ UINT16 Ss;
+ UINT16 Es;
+ UINT16 Fs;
+ UINT16 Gs;
+ UINT32 Eflags;
+ UINT32 Eip;
+ UINT32 Cr0;
+ UINT32 Cr1;
+ UINT32 Cr2;
+ UINT32 Cr3;
+ UINT32 Cr4;
+ UINT32 Gdtr[2];
+ UINT32 Idtr[2];
+ UINT16 Ldtr;
+ UINT16 Tr;
+} EFI_CONTEXT_IA32_REGISTER_STATE;
+
+///
+/// X64 Register State
+///
+typedef struct {
+ UINT64 Rax;
+ UINT64 Rbx;
+ UINT64 Rcx;
+ UINT64 Rdx;
+ UINT64 Rsi;
+ UINT64 Rdi;
+ UINT64 Rbp;
+ UINT64 Rsp;
+ UINT64 R8;
+ UINT64 R9;
+ UINT64 R10;
+ UINT64 R11;
+ UINT64 R12;
+ UINT64 R13;
+ UINT64 R14;
+ UINT64 R15;
+ UINT16 Cs;
+ UINT16 Ds;
+ UINT16 Ss;
+ UINT16 Es;
+ UINT16 Fs;
+ UINT16 Gs;
+ UINT32 Resv1;
+ UINT64 Rflags;
+ UINT64 Rip;
+ UINT64 Cr0;
+ UINT64 Cr1;
+ UINT64 Cr2;
+ UINT64 Cr3;
+ UINT64 Cr4;
+ UINT64 Gdtr[2];
+ UINT64 Idtr[2];
+ UINT16 Ldtr;
+ UINT16 Tr;
+} EFI_CONTEXT_X64_REGISTER_STATE;
+
+///
+/// The validation bit mask indicates each of the following field is in IA32/X64
+/// Processor Error Section.
+///
+typedef struct {
+ UINT64 ApicIdValid : 1;
+ UINT64 CpuIdInforValid : 1;
+ UINT64 ErrorInfoNum : 6;
+ UINT64 ContextNum : 6;
+ UINT64 Resv1 : 50;
+} EFI_IA32_X64_VALID_BITS;
+
+#endif
+
+///
+/// Error Status Fields
+///
+typedef struct {
+ UINT64 Resv1 : 8;
+ UINT64 Type : 8;
+ UINT64 AddressSignal : 1; ///< Error in Address signals or in Address portion of transaction
+ UINT64 ControlSignal : 1; ///< Error in Control signals or in Control portion of transaction
+ UINT64 DataSignal : 1; ///< Error in Data signals or in Data portion of transaction
+ UINT64 DetectedByResponder : 1; ///< Error detected by responder
+ UINT64 DetectedByRequester : 1; ///< Error detected by requestor
+ UINT64 FirstError : 1; ///< First Error in the sequence - option field
+ UINT64 OverflowNotLogged : 1; ///< Additional errors were not logged due to lack of resources
+ UINT64 Resv2 : 41;
+} EFI_GENERIC_ERROR_STATUS;
+
+///
+/// Error Type
+///
+typedef enum {
+ ///
+ /// General Internal errors
+ ///
+ ErrorInternal = 1,
+ ErrorBus = 16,
+ ///
+ /// Component Internal errors
+ ///
+ ErrorMemStorage = 4, // Error in memory device
+ ErrorTlbStorage = 5, // TLB error in cache
+ ErrorCacheStorage = 6,
+ ErrorFunctionalUnit = 7,
+ ErrorSelftest = 8,
+ ErrorOverflow = 9,
+ ///
+ /// Bus internal errors
+ ///
+ ErrorVirtualMap = 17,
+ ErrorAccessInvalid = 18, // Improper access
+ ErrorUnimplAccess = 19, // Unimplemented memory access
+ ErrorLossOfLockstep = 20,
+ ErrorResponseInvalid = 21, // Response not associated with request
+ ErrorParity = 22,
+ ErrorProtocol = 23,
+ ErrorPath = 24, // Detected path error
+ ErrorTimeout = 25, // Bus timeout
+ ErrorPoisoned = 26 // Read data poisoned
+} EFI_GENERIC_ERROR_STATUS_ERROR_TYPE;
+
+///
+/// Validation bit mask indicates which fields in the memory error record are valid
+/// in Memory Error section
+///@{
+#define EFI_PLATFORM_MEMORY_ERROR_STATUS_VALID BIT0
+#define EFI_PLATFORM_MEMORY_PHY_ADDRESS_VALID BIT1
+#define EFI_PLATFORM_MEMORY_PHY_ADDRESS_MASK_VALID BIT2
+#define EFI_PLATFORM_MEMORY_NODE_VALID BIT3
+#define EFI_PLATFORM_MEMORY_CARD_VALID BIT4
+#define EFI_PLATFORM_MEMORY_MODULE_VALID BIT5
+#define EFI_PLATFORM_MEMORY_BANK_VALID BIT6
+#define EFI_PLATFORM_MEMORY_DEVICE_VALID BIT7
+#define EFI_PLATFORM_MEMORY_ROW_VALID BIT8
+#define EFI_PLATFORM_MEMORY_COLUMN_VALID BIT9
+#define EFI_PLATFORM_MEMORY_BIT_POS_VALID BIT10
+#define EFI_PLATFORM_MEMORY_REQUESTOR_ID_VALID BIT11
+#define EFI_PLATFORM_MEMORY_RESPONDER_ID_VALID BIT12
+#define EFI_PLATFORM_MEMORY_TARGET_ID_VALID BIT13
+#define EFI_PLATFORM_MEMORY_ERROR_TYPE_VALID BIT14
+#define EFI_PLATFORM_MEMORY_ERROR_RANK_NUM_VALID BIT15
+#define EFI_PLATFORM_MEMORY_ERROR_CARD_HANDLE_VALID BIT16
+#define EFI_PLATFORM_MEMORY_ERROR_MODULE_HANDLE_VALID BIT17
+#define EFI_PLATFORM_MEMORY_ERROR_EXTENDED_ROW_BIT_16_17_VALID BIT18
+#define EFI_PLATFORM_MEMORY_ERROR_BANK_GROUP_VALID BIT19
+#define EFI_PLATFORM_MEMORY_ERROR_BANK_ADDRESS_VALID BIT20
+#define EFI_PLATFORM_MEMORY_ERROR_CHIP_IDENTIFICATION_VALID BIT21
+///@}
+
+///
+/// Memory Error Type identifies the type of error that occurred in Memory
+/// Error section
+///@{
+#define EFI_PLATFORM_MEMORY_ERROR_UNKNOWN 0x00
+#define EFI_PLATFORM_MEMORY_ERROR_NONE 0x01
+#define EFI_PLATFORM_MEMORY_ERROR_SINGLEBIT_ECC 0x02
+#define EFI_PLATFORM_MEMORY_ERROR_MLTIBIT_ECC 0x03
+#define EFI_PLATFORM_MEMORY_ERROR_SINGLESYMBOLS_CHIPKILL 0x04
+#define EFI_PLATFORM_MEMORY_ERROR_MULTISYMBOL_CHIPKILL 0x05
+#define EFI_PLATFORM_MEMORY_ERROR_MATER_ABORT 0x06
+#define EFI_PLATFORM_MEMORY_ERROR_TARGET_ABORT 0x07
+#define EFI_PLATFORM_MEMORY_ERROR_PARITY 0x08
+#define EFI_PLATFORM_MEMORY_ERROR_WDT 0x09
+#define EFI_PLATFORM_MEMORY_ERROR_INVALID_ADDRESS 0x0A
+#define EFI_PLATFORM_MEMORY_ERROR_MIRROR_FAILED 0x0B
+#define EFI_PLATFORM_MEMORY_ERROR_SPARING 0x0C
+#define EFI_PLATFORM_MEMORY_ERROR_SCRUB_CORRECTED 0x0D
+#define EFI_PLATFORM_MEMORY_ERROR_SCRUB_UNCORRECTED 0x0E
+#define EFI_PLATFORM_MEMORY_ERROR_MEMORY_MAP_EVENT 0x0F
+///@}
+
+///
+/// Memory Error Section
+///
+typedef struct {
+ UINT64 ValidFields;
+ EFI_GENERIC_ERROR_STATUS ErrorStatus;
+ UINT64 PhysicalAddress; // Error physical address
+ UINT64 PhysicalAddressMask; // Grnaularity
+ UINT16 Node; // Node #
+ UINT16 Card;
+ UINT16 ModuleRank; // Module or Rank#
+ UINT16 Bank;
+ UINT16 Device;
+ UINT16 Row;
+ UINT16 Column;
+ UINT16 BitPosition;
+ UINT64 RequestorId;
+ UINT64 ResponderId;
+ UINT64 TargetId;
+ UINT8 ErrorType;
+ UINT8 Extended;
+ UINT16 RankNum;
+ UINT16 CardHandle;
+ UINT16 ModuleHandle;
+} EFI_PLATFORM_MEMORY_ERROR_DATA;
+
+///
+/// Validation bit mask indicates which fields in the memory error record 2 are valid
+/// in Memory Error section 2
+///@{
+#define EFI_PLATFORM_MEMORY2_ERROR_STATUS_VALID BIT0
+#define EFI_PLATFORM_MEMORY2_PHY_ADDRESS_VALID BIT1
+#define EFI_PLATFORM_MEMORY2_PHY_ADDRESS_MASK_VALID BIT2
+#define EFI_PLATFORM_MEMORY2_NODE_VALID BIT3
+#define EFI_PLATFORM_MEMORY2_CARD_VALID BIT4
+#define EFI_PLATFORM_MEMORY2_MODULE_VALID BIT5
+#define EFI_PLATFORM_MEMORY2_BANK_VALID BIT6
+#define EFI_PLATFORM_MEMORY2_DEVICE_VALID BIT7
+#define EFI_PLATFORM_MEMORY2_ROW_VALID BIT8
+#define EFI_PLATFORM_MEMORY2_COLUMN_VALID BIT9
+#define EFI_PLATFORM_MEMORY2_RANK_VALID BIT10
+#define EFI_PLATFORM_MEMORY2_BIT_POS_VALID BIT11
+#define EFI_PLATFORM_MEMORY2_CHIP_ID_VALID BIT12
+#define EFI_PLATFORM_MEMORY2_MEMORY_ERROR_TYPE_VALID BIT13
+#define EFI_PLATFORM_MEMORY2_STATUS_VALID BIT14
+#define EFI_PLATFORM_MEMORY2_REQUESTOR_ID_VALID BIT15
+#define EFI_PLATFORM_MEMORY2_RESPONDER_ID_VALID BIT16
+#define EFI_PLATFORM_MEMORY2_TARGET_ID_VALID BIT17
+#define EFI_PLATFORM_MEMORY2_CARD_HANDLE_VALID BIT18
+#define EFI_PLATFORM_MEMORY2_MODULE_HANDLE_VALID BIT19
+#define EFI_PLATFORM_MEMORY2_BANK_GROUP_VALID BIT20
+#define EFI_PLATFORM_MEMORY2_BANK_ADDRESS_VALID BIT21
+///@}
+
+///
+/// Memory Error Type identifies the type of error that occurred in Memory
+/// Error section 2
+///@{
+#define EFI_PLATFORM_MEMORY2_ERROR_UNKNOWN 0x00
+#define EFI_PLATFORM_MEMORY2_ERROR_NONE 0x01
+#define EFI_PLATFORM_MEMORY2_ERROR_SINGLEBIT_ECC 0x02
+#define EFI_PLATFORM_MEMORY2_ERROR_MLTIBIT_ECC 0x03
+#define EFI_PLATFORM_MEMORY2_ERROR_SINGLESYMBOL_CHIPKILL 0x04
+#define EFI_PLATFORM_MEMORY2_ERROR_MULTISYMBOL_CHIPKILL 0x05
+#define EFI_PLATFORM_MEMORY2_ERROR_MASTER_ABORT 0x06
+#define EFI_PLATFORM_MEMORY2_ERROR_TARGET_ABORT 0x07
+#define EFI_PLATFORM_MEMORY2_ERROR_PARITY 0x08
+#define EFI_PLATFORM_MEMORY2_ERROR_WDT 0x09
+#define EFI_PLATFORM_MEMORY2_ERROR_INVALID_ADDRESS 0x0A
+#define EFI_PLATFORM_MEMORY2_ERROR_MIRROR_BROKEN 0x0B
+#define EFI_PLATFORM_MEMORY2_ERROR_MEMORY_SPARING 0x0C
+#define EFI_PLATFORM_MEMORY2_ERROR_SCRUB_CORRECTED 0x0D
+#define EFI_PLATFORM_MEMORY2_ERROR_SCRUB_UNCORRECTED 0x0E
+#define EFI_PLATFORM_MEMORY2_ERROR_MEMORY_MAP_EVENT 0x0F
+///@}
+
+///
+/// Memory Error Section 2
+///
+typedef struct {
+ UINT64 ValidFields;
+ EFI_GENERIC_ERROR_STATUS ErrorStatus;
+ UINT64 PhysicalAddress; // Error physical address
+ UINT64 PhysicalAddressMask; // Grnaularity
+ UINT16 Node; // Node #
+ UINT16 Card;
+ UINT16 Module; // Module or Rank#
+ UINT16 Bank;
+ UINT32 Device;
+ UINT32 Row;
+ UINT32 Column;
+ UINT32 Rank;
+ UINT32 BitPosition;
+ UINT8 ChipId;
+ UINT8 MemErrorType;
+ UINT8 Status;
+ UINT8 Reserved;
+ UINT64 RequestorId;
+ UINT64 ResponderId;
+ UINT64 TargetId;
+ UINT32 CardHandle;
+ UINT32 ModuleHandle;
+} EFI_PLATFORM_MEMORY2_ERROR_DATA;
+
+///
+/// Validation bits mask indicates which of the following fields is valid
+/// in PCI Express Error Record.
+///@{
+#define EFI_PCIE_ERROR_PORT_TYPE_VALID BIT0
+#define EFI_PCIE_ERROR_VERSION_VALID BIT1
+#define EFI_PCIE_ERROR_COMMAND_STATUS_VALID BIT2
+#define EFI_PCIE_ERROR_DEVICE_ID_VALID BIT3
+#define EFI_PCIE_ERROR_SERIAL_NO_VALID BIT4
+#define EFI_PCIE_ERROR_BRIDGE_CRL_STS_VALID BIT5
+#define EFI_PCIE_ERROR_CAPABILITY_INFO_VALID BIT6
+#define EFI_PCIE_ERROR_AER_INFO_VALID BIT7
+///@}
+
+///
+/// PCIe Device/Port Type as defined in the PCI Express capabilities register
+///@{
+#define EFI_PCIE_ERROR_PORT_PCIE_ENDPOINT 0x00000000
+#define EFI_PCIE_ERROR_PORT_PCI_ENDPOINT 0x00000001
+#define EFI_PCIE_ERROR_PORT_ROOT_PORT 0x00000004
+#define EFI_PCIE_ERROR_PORT_UPSWITCH_PORT 0x00000005
+#define EFI_PCIE_ERROR_PORT_DOWNSWITCH_PORT 0x00000006
+#define EFI_PCIE_ERROR_PORT_PCIE_TO_PCI_BRIDGE 0x00000007
+#define EFI_PCIE_ERROR_PORT_PCI_TO_PCIE_BRIDGE 0x00000008
+#define EFI_PCIE_ERROR_PORT_ROOT_INT_ENDPOINT 0x00000009
+#define EFI_PCIE_ERROR_PORT_ROOT_EVENT_COLLECTOR 0x0000000A
+///@}
+
+///
+/// PCI Slot number
+///
+typedef struct {
+ UINT16 Resv1 : 3;
+ UINT16 Number : 13;
+} EFI_GENERIC_ERROR_PCI_SLOT;
+
+///
+/// PCIe Root Port PCI/bridge PCI compatible device number and
+/// bus number information to uniquely identify the root port or
+/// bridge. Default values for both the bus numbers is zero.
+///
+typedef struct {
+ UINT16 VendorId;
+ UINT16 DeviceId;
+ UINT8 ClassCode[3];
+ UINT8 Function;
+ UINT8 Device;
+ UINT16 Segment;
+ UINT8 PrimaryOrDeviceBus;
+ UINT8 SecondaryBus;
+ EFI_GENERIC_ERROR_PCI_SLOT Slot;
+ UINT8 Resv1;
+} EFI_GENERIC_ERROR_PCIE_DEV_BRIDGE_ID;
+
+///
+/// PCIe Capability Structure
+///
+typedef struct {
+ UINT8 PcieCap[60];
+} EFI_PCIE_ERROR_DATA_CAPABILITY;
+
+///
+/// PCIe Advanced Error Reporting Extended Capability Structure.
+///
+typedef struct {
+ UINT8 PcieAer[96];
+} EFI_PCIE_ERROR_DATA_AER;
+
+///
+/// PCI Express Error Record
+///
+typedef struct {
+ UINT64 ValidFields;
+ UINT32 PortType;
+ UINT32 Version;
+ UINT32 CommandStatus;
+ UINT32 Resv2;
+ EFI_GENERIC_ERROR_PCIE_DEV_BRIDGE_ID DevBridge;
+ UINT64 SerialNo;
+ UINT32 BridgeControlStatus;
+ EFI_PCIE_ERROR_DATA_CAPABILITY Capability;
+ EFI_PCIE_ERROR_DATA_AER AerInfo;
+} EFI_PCIE_ERROR_DATA;
+
+///
+/// Validation bits Indicates which of the following fields is valid
+/// in PCI/PCI-X Bus Error Section.
+///@{
+#define EFI_PCI_PCIX_BUS_ERROR_STATUS_VALID BIT0
+#define EFI_PCI_PCIX_BUS_ERROR_TYPE_VALID BIT1
+#define EFI_PCI_PCIX_BUS_ERROR_BUS_ID_VALID BIT2
+#define EFI_PCI_PCIX_BUS_ERROR_BUS_ADDRESS_VALID BIT3
+#define EFI_PCI_PCIX_BUS_ERROR_BUS_DATA_VALID BIT4
+#define EFI_PCI_PCIX_BUS_ERROR_COMMAND_VALID BIT5
+#define EFI_PCI_PCIX_BUS_ERROR_REQUESTOR_ID_VALID BIT6
+#define EFI_PCI_PCIX_BUS_ERROR_COMPLETER_ID_VALID BIT7
+#define EFI_PCI_PCIX_BUS_ERROR_TARGET_ID_VALID BIT8
+///@}
+
+///
+/// PCI Bus Error Type in PCI/PCI-X Bus Error Section
+///@{
+#define EFI_PCI_PCIX_BUS_ERROR_UNKNOWN 0x0000
+#define EFI_PCI_PCIX_BUS_ERROR_DATA_PARITY 0x0001
+#define EFI_PCI_PCIX_BUS_ERROR_SYSTEM 0x0002
+#define EFI_PCI_PCIX_BUS_ERROR_MASTER_ABORT 0x0003
+#define EFI_PCI_PCIX_BUS_ERROR_BUS_TIMEOUT 0x0004
+#define EFI_PCI_PCIX_BUS_ERROR_MASTER_DATA_PARITY 0x0005
+#define EFI_PCI_PCIX_BUS_ERROR_ADDRESS_PARITY 0x0006
+#define EFI_PCI_PCIX_BUS_ERROR_COMMAND_PARITY 0x0007
+///@}
+
+///
+/// PCI/PCI-X Bus Error Section
+///
+typedef struct {
+ UINT64 ValidFields;
+ EFI_GENERIC_ERROR_STATUS ErrorStatus;
+ UINT16 Type;
+ UINT16 BusId;
+ UINT32 Resv2;
+ UINT64 BusAddress;
+ UINT64 BusData;
+ UINT64 BusCommand;
+ UINT64 RequestorId;
+ UINT64 ResponderId;
+ UINT64 TargetId;
+} EFI_PCI_PCIX_BUS_ERROR_DATA;
+
+///
+/// Validation bits Indicates which of the following fields is valid
+/// in PCI/PCI-X Component Error Section.
+///@{
+#define EFI_PCI_PCIX_DEVICE_ERROR_STATUS_VALID BIT0
+#define EFI_PCI_PCIX_DEVICE_ERROR_ID_INFO_VALID BIT1
+#define EFI_PCI_PCIX_DEVICE_ERROR_MEM_NUM_VALID BIT2
+#define EFI_PCI_PCIX_DEVICE_ERROR_IO_NUM_VALID BIT3
+#define EFI_PCI_PCIX_DEVICE_ERROR_REG_DATA_PAIR_VALID BIT4
+///@}
+
+///
+/// PCI/PCI-X Device Identification Information
+///
+typedef struct {
+ UINT16 VendorId;
+ UINT16 DeviceId;
+ UINT8 ClassCode[3];
+ UINT8 Function;
+ UINT8 Device;
+ UINT8 Bus;
+ UINT8 Segment;
+ UINT8 Resv1;
+ UINT32 Resv2;
+} EFI_GENERIC_ERROR_PCI_DEVICE_ID;
+
+///
+/// Identifies the type of firmware error record
+///@{
+#define EFI_FIRMWARE_ERROR_TYPE_IPF_SAL 0x00
+#define EFI_FIRMWARE_ERROR_TYPE_SOC_TYPE1 0x01
+#define EFI_FIRMWARE_ERROR_TYPE_SOC_TYPE2 0x02
+///@}
+
+///
+/// Firmware Error Record Section
+///
+typedef struct {
+ UINT8 ErrorType;
+ UINT8 Revision;
+ UINT8 Resv1[6];
+ UINT64 RecordId;
+ EFI_GUID RecordIdGuid;
+} EFI_FIRMWARE_ERROR_DATA;
+
+///
+/// Fault Reason in DMAr Generic Error Section
+///@{
+#define EFI_DMA_FAULT_REASON_TABLE_ENTRY_NOT_PRESENT 0x01
+#define EFI_DMA_FAULT_REASON_TABLE_ENTRY_INVALID 0x02
+#define EFI_DMA_FAULT_REASON_ACCESS_MAPPING_TABLE_ERROR 0x03
+#define EFI_DMA_FAULT_REASON_RESV_BIT_ERROR_IN_MAPPING_TABLE 0x04
+#define EFI_DMA_FAULT_REASON_ACCESS_ADDR_OUT_OF_SPACE 0x05
+#define EFI_DMA_FAULT_REASON_INVALID_ACCESS 0x06
+#define EFI_DMA_FAULT_REASON_INVALID_REQUEST 0x07
+#define EFI_DMA_FAULT_REASON_ACCESS_TRANSLATE_TABLE_ERROR 0x08
+#define EFI_DMA_FAULT_REASON_RESV_BIT_ERROR_IN_TRANSLATE_TABLE 0x09
+#define EFI_DMA_FAULT_REASON_INVALID_COMMAOND 0x0A
+#define EFI_DMA_FAULT_REASON_ACCESS_COMMAND_BUFFER_ERROR 0x0B
+///@}
+
+///
+/// DMA access type in DMAr Generic Error Section
+///@{
+#define EFI_DMA_ACCESS_TYPE_READ 0x00
+#define EFI_DMA_ACCESS_TYPE_WRITE 0x01
+///@}
+
+///
+/// DMA address type in DMAr Generic Error Section
+///@{
+#define EFI_DMA_ADDRESS_UNTRANSLATED 0x00
+#define EFI_DMA_ADDRESS_TRANSLATION 0x01
+///@}
+
+///
+/// Architecture type in DMAr Generic Error Section
+///@{
+#define EFI_DMA_ARCH_TYPE_VT 0x01
+#define EFI_DMA_ARCH_TYPE_IOMMU 0x02
+///@}
+
+///
+/// DMAr Generic Error Section
+///
+typedef struct {
+ UINT16 RequesterId;
+ UINT16 SegmentNumber;
+ UINT8 FaultReason;
+ UINT8 AccessType;
+ UINT8 AddressType;
+ UINT8 ArchType;
+ UINT64 DeviceAddr;
+ UINT8 Resv1[16];
+} EFI_DMAR_GENERIC_ERROR_DATA;
+
+///
+/// Intel VT for Directed I/O specific DMAr Errors
+///
+typedef struct {
+ UINT8 Version;
+ UINT8 Revision;
+ UINT8 OemId[6];
+ UINT64 Capability;
+ UINT64 CapabilityEx;
+ UINT32 GlobalCommand;
+ UINT32 GlobalStatus;
+ UINT32 FaultStatus;
+ UINT8 Resv1[12];
+ UINT64 FaultRecord[2];
+ UINT64 RootEntry[2];
+ UINT64 ContextEntry[2];
+ UINT64 PteL6;
+ UINT64 PteL5;
+ UINT64 PteL4;
+ UINT64 PteL3;
+ UINT64 PteL2;
+ UINT64 PteL1;
+} EFI_DIRECTED_IO_DMAR_ERROR_DATA;
+
+///
+/// IOMMU specific DMAr Errors
+///
+typedef struct {
+ UINT8 Revision;
+ UINT8 Resv1[7];
+ UINT64 Control;
+ UINT64 Status;
+ UINT8 Resv2[8];
+ UINT64 EventLogEntry[2];
+ UINT8 Resv3[16];
+ UINT64 DeviceTableEntry[4];
+ UINT64 PteL6;
+ UINT64 PteL5;
+ UINT64 PteL4;
+ UINT64 PteL3;
+ UINT64 PteL2;
+ UINT64 PteL1;
+} EFI_IOMMU_DMAR_ERROR_DATA;
+
+#pragma pack()
+
+extern EFI_GUID gEfiEventNotificationTypeCmcGuid;
+extern EFI_GUID gEfiEventNotificationTypeCpeGuid;
+extern EFI_GUID gEfiEventNotificationTypeMceGuid;
+extern EFI_GUID gEfiEventNotificationTypePcieGuid;
+extern EFI_GUID gEfiEventNotificationTypeInitGuid;
+extern EFI_GUID gEfiEventNotificationTypeNmiGuid;
+extern EFI_GUID gEfiEventNotificationTypeBootGuid;
+extern EFI_GUID gEfiEventNotificationTypeDmarGuid;
+extern EFI_GUID gEfiEventNotificationTypeSeaGuid;
+extern EFI_GUID gEfiEventNotificationTypeSeiGuid;
+extern EFI_GUID gEfiEventNotificationTypePeiGuid;
+
+extern EFI_GUID gEfiProcessorGenericErrorSectionGuid;
+extern EFI_GUID gEfiProcessorSpecificErrorSectionGuid;
+extern EFI_GUID gEfiIa32X64ProcessorErrorSectionGuid;
+extern EFI_GUID gEfiArmProcessorErrorSectionGuid;
+extern EFI_GUID gEfiPlatformMemoryErrorSectionGuid;
+extern EFI_GUID gEfiPlatformMemory2ErrorSectionGuid;
+extern EFI_GUID gEfiPcieErrorSectionGuid;
+extern EFI_GUID gEfiFirmwareErrorSectionGuid;
+extern EFI_GUID gEfiPciBusErrorSectionGuid;
+extern EFI_GUID gEfiPciDevErrorSectionGuid;
+extern EFI_GUID gEfiDMArGenericErrorSectionGuid;
+extern EFI_GUID gEfiDirectedIoDMArErrorSectionGuid;
+extern EFI_GUID gEfiIommuDMArErrorSectionGuid;
+
+#if defined (MDE_CPU_IA32) || defined (MDE_CPU_X64)
+///
+/// IA32 and x64 Specific definitions.
+///
+
+extern EFI_GUID gEfiIa32X64ErrorTypeCacheCheckGuid;
+extern EFI_GUID gEfiIa32X64ErrorTypeTlbCheckGuid;
+extern EFI_GUID gEfiIa32X64ErrorTypeBusCheckGuid;
+extern EFI_GUID gEfiIa32X64ErrorTypeMsCheckGuid;
+
+#endif
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Guid/DebugImageInfoTable.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Guid/DebugImageInfoTable.h
new file mode 100644
index 0000000000..c20cc626a0
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Guid/DebugImageInfoTable.h
@@ -0,0 +1,74 @@
+/** @file
+ GUID and related data structures used with the Debug Image Info Table.
+
+ Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Revision Reference:
+ GUID defined in UEFI 2.0 spec.
+
+**/
+
+#ifndef __DEBUG_IMAGE_INFO_GUID_H__
+#define __DEBUG_IMAGE_INFO_GUID_H__
+
+#include
+
+///
+/// EFI_DEBUG_IMAGE_INFO_TABLE configuration table GUID declaration.
+///
+#define EFI_DEBUG_IMAGE_INFO_TABLE_GUID \
+ { \
+ 0x49152e77, 0x1ada, 0x4764, {0xb7, 0xa2, 0x7a, 0xfe, 0xfe, 0xd9, 0x5e, 0x8b } \
+ }
+
+#define EFI_DEBUG_IMAGE_INFO_UPDATE_IN_PROGRESS 0x01
+#define EFI_DEBUG_IMAGE_INFO_TABLE_MODIFIED 0x02
+
+#define EFI_DEBUG_IMAGE_INFO_TYPE_NORMAL 0x01
+
+typedef struct {
+ UINT64 Signature; ///< A constant UINT64 that has the value EFI_SYSTEM_TABLE_SIGNATURE
+ EFI_PHYSICAL_ADDRESS EfiSystemTableBase; ///< The physical address of the EFI system table.
+ UINT32 Crc32; ///< A 32-bit CRC value that is used to verify the EFI_SYSTEM_TABLE_POINTER structure is valid.
+} EFI_SYSTEM_TABLE_POINTER;
+
+typedef struct {
+ ///
+ /// Indicates the type of image info structure. For PE32 EFI images,
+ /// this is set to EFI_DEBUG_IMAGE_INFO_TYPE_NORMAL.
+ ///
+ UINT32 ImageInfoType;
+ ///
+ /// A pointer to an instance of the loaded image protocol for the associated image.
+ ///
+ EFI_LOADED_IMAGE_PROTOCOL *LoadedImageProtocolInstance;
+ ///
+ /// Indicates the image handle of the associated image.
+ ///
+ EFI_HANDLE ImageHandle;
+} EFI_DEBUG_IMAGE_INFO_NORMAL;
+
+typedef union {
+ UINT32 *ImageInfoType;
+ EFI_DEBUG_IMAGE_INFO_NORMAL *NormalImage;
+} EFI_DEBUG_IMAGE_INFO;
+
+typedef struct {
+ ///
+ /// UpdateStatus is used by the system to indicate the state of the debug image info table.
+ ///
+ volatile UINT32 UpdateStatus;
+ ///
+ /// The number of EFI_DEBUG_IMAGE_INFO elements in the array pointed to by EfiDebugImageInfoTable.
+ ///
+ UINT32 TableSize;
+ ///
+ /// A pointer to the first element of an array of EFI_DEBUG_IMAGE_INFO structures.
+ ///
+ EFI_DEBUG_IMAGE_INFO *EfiDebugImageInfoTable;
+} EFI_DEBUG_IMAGE_INFO_TABLE_HEADER;
+
+extern EFI_GUID gEfiDebugImageInfoTableGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Guid/DxeServices.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Guid/DxeServices.h
new file mode 100644
index 0000000000..3d74ccd368
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Guid/DxeServices.h
@@ -0,0 +1,22 @@
+/** @file
+ GUID used to identify the DXE Services Table
+
+ Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Revision Reference:
+ GUID introduced in PI Version 1.0.
+
+**/
+
+#ifndef __DXE_SERVICES_GUID_H__
+#define __DXE_SERVICES_GUID_H__
+
+#define DXE_SERVICES_TABLE_GUID \
+ { \
+ 0x5ad34ba, 0x6f02, 0x4214, {0x95, 0x2e, 0x4d, 0xa0, 0x39, 0x8e, 0x2b, 0xb9 } \
+ }
+
+extern EFI_GUID gEfiDxeServicesTableGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Guid/EventGroup.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Guid/EventGroup.h
new file mode 100644
index 0000000000..2f70b594a7
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Guid/EventGroup.h
@@ -0,0 +1,52 @@
+/** @file
+ GUIDs for gBS->CreateEventEx Event Groups. Defined in UEFI spec 2.0 and PI 1.2.1.
+
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __EVENT_GROUP_GUID__
+#define __EVENT_GROUP_GUID__
+
+#define EFI_EVENT_GROUP_EXIT_BOOT_SERVICES \
+ { 0x27abf055, 0xb1b8, 0x4c26, { 0x80, 0x48, 0x74, 0x8f, 0x37, 0xba, 0xa2, 0xdf } }
+
+extern EFI_GUID gEfiEventExitBootServicesGuid;
+
+#define EFI_EVENT_GROUP_BEFORE_EXIT_BOOT_SERVICES \
+ { 0x8be0e274, 0x3970, 0x4b44, { 0x80, 0xc5, 0x1a, 0xb9, 0x50, 0x2f, 0x3b, 0xfc } }
+
+extern EFI_GUID gEfiEventBeforeExitBootServicesGuid;
+
+#define EFI_EVENT_GROUP_VIRTUAL_ADDRESS_CHANGE \
+ { 0x13fa7698, 0xc831, 0x49c7, { 0x87, 0xea, 0x8f, 0x43, 0xfc, 0xc2, 0x51, 0x96 } }
+
+extern EFI_GUID gEfiEventVirtualAddressChangeGuid;
+
+#define EFI_EVENT_GROUP_MEMORY_MAP_CHANGE \
+ { 0x78bee926, 0x692f, 0x48fd, { 0x9e, 0xdb, 0x1, 0x42, 0x2e, 0xf0, 0xd7, 0xab } }
+
+extern EFI_GUID gEfiEventMemoryMapChangeGuid;
+
+#define EFI_EVENT_GROUP_READY_TO_BOOT \
+ { 0x7ce88fb3, 0x4bd7, 0x4679, { 0x87, 0xa8, 0xa8, 0xd8, 0xde, 0xe5, 0x0d, 0x2b } }
+
+extern EFI_GUID gEfiEventReadyToBootGuid;
+
+#define EFI_EVENT_GROUP_AFTER_READY_TO_BOOT \
+ { 0x3a2a00ad, 0x98b9, 0x4cdf, { 0xa4, 0x78, 0x70, 0x27, 0x77, 0xf1, 0xc1, 0xb } }
+
+extern EFI_GUID gEfiEventAfterReadyToBootGuid;
+
+#define EFI_EVENT_GROUP_DXE_DISPATCH_GUID \
+ { 0x7081e22f, 0xcac6, 0x4053, { 0x94, 0x68, 0x67, 0x57, 0x82, 0xcf, 0x88, 0xe5 }}
+
+extern EFI_GUID gEfiEventDxeDispatchGuid;
+
+#define EFI_END_OF_DXE_EVENT_GROUP_GUID \
+ { 0x2ce967a, 0xdd7e, 0x4ffc, { 0x9e, 0xe7, 0x81, 0xc, 0xf0, 0x47, 0x8, 0x80 } }
+
+extern EFI_GUID gEfiEndOfDxeEventGroupGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Guid/EventLegacyBios.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Guid/EventLegacyBios.h
new file mode 100644
index 0000000000..f4d93f06b2
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Guid/EventLegacyBios.h
@@ -0,0 +1,22 @@
+/** @file
+ GUID is the name of events used with CreateEventEx in order to be notified
+ when the EFI boot manager is about to boot a legacy boot option.
+ Events of this type are notificated just before Int19h is invoked.
+
+ Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Revision Reference:
+ GUID introduced in PI Version 1.0.
+
+**/
+
+#ifndef __EVENT_LEGACY_BIOS_GUID_H__
+#define __EVENT_LEGACY_BIOS_GUID_H__
+
+#define EFI_EVENT_LEGACY_BOOT_GUID \
+ { 0x2a571201, 0x4966, 0x47f6, {0x8b, 0x86, 0xf3, 0x1e, 0x41, 0xf3, 0x2f, 0x10 } }
+
+extern EFI_GUID gEfiEventLegacyBootGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Guid/FileInfo.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Guid/FileInfo.h
new file mode 100644
index 0000000000..dfe0e8ee06
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Guid/FileInfo.h
@@ -0,0 +1,65 @@
+/** @file
+ Provides a GUID and a data structure that can be used with EFI_FILE_PROTOCOL.SetInfo()
+ and EFI_FILE_PROTOCOL.GetInfo() to set or get generic file information.
+ This GUID is defined in UEFI specification.
+
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __FILE_INFO_H__
+#define __FILE_INFO_H__
+
+#define EFI_FILE_INFO_ID \
+ { \
+ 0x9576e92, 0x6d3f, 0x11d2, {0x8e, 0x39, 0x0, 0xa0, 0xc9, 0x69, 0x72, 0x3b } \
+ }
+
+typedef struct {
+ ///
+ /// The size of the EFI_FILE_INFO structure, including the Null-terminated FileName string.
+ ///
+ UINT64 Size;
+ ///
+ /// The size of the file in bytes.
+ ///
+ UINT64 FileSize;
+ ///
+ /// PhysicalSize The amount of physical space the file consumes on the file system volume.
+ ///
+ UINT64 PhysicalSize;
+ ///
+ /// The time the file was created.
+ ///
+ EFI_TIME CreateTime;
+ ///
+ /// The time when the file was last accessed.
+ ///
+ EFI_TIME LastAccessTime;
+ ///
+ /// The time when the file's contents were last modified.
+ ///
+ EFI_TIME ModificationTime;
+ ///
+ /// The attribute bits for the file.
+ ///
+ UINT64 Attribute;
+ ///
+ /// The Null-terminated name of the file.
+ ///
+ CHAR16 FileName[1];
+} EFI_FILE_INFO;
+
+///
+/// The FileName field of the EFI_FILE_INFO data structure is variable length.
+/// Whenever code needs to know the size of the EFI_FILE_INFO data structure, it needs to
+/// be the size of the data structure without the FileName field. The following macro
+/// computes this size correctly no matter how big the FileName array is declared.
+/// This is required to make the EFI_FILE_INFO data structure ANSI compilant.
+///
+#define SIZE_OF_EFI_FILE_INFO OFFSET_OF (EFI_FILE_INFO, FileName)
+
+extern EFI_GUID gEfiFileInfoGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Guid/FileSystemInfo.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Guid/FileSystemInfo.h
new file mode 100644
index 0000000000..402fc4365b
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Guid/FileSystemInfo.h
@@ -0,0 +1,57 @@
+/** @file
+ Provides a GUID and a data structure that can be used with EFI_FILE_PROTOCOL.GetInfo()
+ or EFI_FILE_PROTOCOL.SetInfo() to get or set information about the system's volume.
+ This GUID is defined in UEFI specification.
+
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __FILE_SYSTEM_INFO_H__
+#define __FILE_SYSTEM_INFO_H__
+
+#define EFI_FILE_SYSTEM_INFO_ID \
+ { \
+ 0x9576e93, 0x6d3f, 0x11d2, {0x8e, 0x39, 0x0, 0xa0, 0xc9, 0x69, 0x72, 0x3b } \
+ }
+
+typedef struct {
+ ///
+ /// The size of the EFI_FILE_SYSTEM_INFO structure, including the Null-terminated VolumeLabel string.
+ ///
+ UINT64 Size;
+ ///
+ /// TRUE if the volume only supports read access.
+ ///
+ BOOLEAN ReadOnly;
+ ///
+ /// The number of bytes managed by the file system.
+ ///
+ UINT64 VolumeSize;
+ ///
+ /// The number of available bytes for use by the file system.
+ ///
+ UINT64 FreeSpace;
+ ///
+ /// The nominal block size by which files are typically grown.
+ ///
+ UINT32 BlockSize;
+ ///
+ /// The Null-terminated string that is the volume's label.
+ ///
+ CHAR16 VolumeLabel[1];
+} EFI_FILE_SYSTEM_INFO;
+
+///
+/// The VolumeLabel field of the EFI_FILE_SYSTEM_INFO data structure is variable length.
+/// Whenever code needs to know the size of the EFI_FILE_SYSTEM_INFO data structure, it needs
+/// to be the size of the data structure without the VolumeLable field. The following macro
+/// computes this size correctly no matter how big the VolumeLable array is declared.
+/// This is required to make the EFI_FILE_SYSTEM_INFO data structure ANSI compilant.
+///
+#define SIZE_OF_EFI_FILE_SYSTEM_INFO OFFSET_OF (EFI_FILE_SYSTEM_INFO, VolumeLabel)
+
+extern EFI_GUID gEfiFileSystemInfoGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Guid/FileSystemVolumeLabelInfo.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Guid/FileSystemVolumeLabelInfo.h
new file mode 100644
index 0000000000..625f6eac00
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Guid/FileSystemVolumeLabelInfo.h
@@ -0,0 +1,31 @@
+/** @file
+ Provides a GUID and a data structure that can be used with EFI_FILE_PROTOCOL.GetInfo()
+ or EFI_FILE_PROTOCOL.SetInfo() to get or set the system's volume label.
+ This GUID is defined in UEFI specification.
+
+ Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __FILE_SYSTEM_VOLUME_LABEL_INFO_H__
+#define __FILE_SYSTEM_VOLUME_LABEL_INFO_H__
+
+#define EFI_FILE_SYSTEM_VOLUME_LABEL_ID \
+ { \
+ 0xDB47D7D3, 0xFE81, 0x11d3, {0x9A, 0x35, 0x00, 0x90, 0x27, 0x3F, 0xC1, 0x4D } \
+ }
+
+typedef struct {
+ ///
+ /// The Null-terminated string that is the volume's label.
+ ///
+ CHAR16 VolumeLabel[1];
+} EFI_FILE_SYSTEM_VOLUME_LABEL;
+
+#define SIZE_OF_EFI_FILE_SYSTEM_VOLUME_LABEL \
+ OFFSET_OF (EFI_FILE_SYSTEM_VOLUME_LABEL, VolumeLabel)
+
+extern EFI_GUID gEfiFileSystemVolumeLabelInfoIdGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Guid/FirmwareContentsSigned.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Guid/FirmwareContentsSigned.h
new file mode 100644
index 0000000000..37f340b99b
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Guid/FirmwareContentsSigned.h
@@ -0,0 +1,20 @@
+/** @file
+ GUID is used to define the signed section.
+
+ Copyright (c) 2013 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Revision Reference:
+ GUID introduced in PI Version 1.2.1.
+
+**/
+
+#ifndef __FIRMWARE_CONTENTS_SIGNED_GUID_H__
+#define __FIRMWARE_CONTENTS_SIGNED_GUID_H__
+
+#define EFI_FIRMWARE_CONTENTS_SIGNED_GUID \
+ { 0xf9d89e8, 0x9259, 0x4f76, {0xa5, 0xaf, 0xc, 0x89, 0xe3, 0x40, 0x23, 0xdf } }
+
+extern EFI_GUID gEfiFirmwareContentsSignedGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Guid/FirmwareFileSystem2.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Guid/FirmwareFileSystem2.h
new file mode 100644
index 0000000000..10c64449f2
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Guid/FirmwareFileSystem2.h
@@ -0,0 +1,33 @@
+/** @file
+ Guid used to define the Firmware File System 2.
+
+ Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Revision Reference:
+ GUIDs introduced in PI Version 1.0.
+
+**/
+
+#ifndef __FIRMWARE_FILE_SYSTEM2_GUID_H__
+#define __FIRMWARE_FILE_SYSTEM2_GUID_H__
+
+///
+/// The firmware volume header contains a data field for
+/// the file system GUID
+///
+#define EFI_FIRMWARE_FILE_SYSTEM2_GUID \
+ { 0x8c8ce578, 0x8a3d, 0x4f1c, { 0x99, 0x35, 0x89, 0x61, 0x85, 0xc3, 0x2d, 0xd3 } }
+
+///
+/// A Volume Top File (VTF) is a file that must be
+/// located such that the last byte of the file is
+/// also the last byte of the firmware volume
+///
+#define EFI_FFS_VOLUME_TOP_FILE_GUID \
+ { 0x1BA0062E, 0xC779, 0x4582, { 0x85, 0x66, 0x33, 0x6A, 0xE8, 0xF7, 0x8F, 0x9 } }
+
+extern EFI_GUID gEfiFirmwareFileSystem2Guid;
+extern EFI_GUID gEfiFirmwareVolumeTopFileGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Guid/FirmwareFileSystem3.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Guid/FirmwareFileSystem3.h
new file mode 100644
index 0000000000..e98ec085eb
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Guid/FirmwareFileSystem3.h
@@ -0,0 +1,24 @@
+/** @file
+ Guid used to define the Firmware File System 3.
+
+ Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Revision Reference:
+ GUIDs introduced in PI Version 1.0.
+
+**/
+
+#ifndef __FIRMWARE_FILE_SYSTEM3_GUID_H__
+#define __FIRMWARE_FILE_SYSTEM3_GUID_H__
+
+///
+/// The firmware volume header contains a data field for the file system GUID
+/// {5473C07A-3DCB-4dca-BD6F-1E9689E7349A}
+///
+#define EFI_FIRMWARE_FILE_SYSTEM3_GUID \
+ { 0x5473c07a, 0x3dcb, 0x4dca, { 0xbd, 0x6f, 0x1e, 0x96, 0x89, 0xe7, 0x34, 0x9a }}
+
+extern EFI_GUID gEfiFirmwareFileSystem3Guid;
+
+#endif // __FIRMWARE_FILE_SYSTEM3_GUID_H__
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Guid/FmpCapsule.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Guid/FmpCapsule.h
new file mode 100644
index 0000000000..fcbf006dad
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Guid/FmpCapsule.h
@@ -0,0 +1,99 @@
+/** @file
+ Guid & data structure used for Delivering Capsules Containing Updates to Firmware
+ Management Protocol
+
+ Copyright (c) 2013 - 2015, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Revision Reference:
+ GUIDs defined in UEFI 2.4 spec.
+
+**/
+
+#ifndef _FMP_CAPSULE_GUID_H__
+#define _FMP_CAPSULE_GUID_H__
+
+//
+// This is the GUID of the capsule for Firmware Management Protocol.
+//
+#define EFI_FIRMWARE_MANAGEMENT_CAPSULE_ID_GUID \
+ { \
+ 0x6dcbd5ed, 0xe82d, 0x4c44, {0xbd, 0xa1, 0x71, 0x94, 0x19, 0x9a, 0xd9, 0x2a } \
+ }
+
+#pragma pack(1)
+
+typedef struct {
+ UINT32 Version;
+
+ ///
+ /// The number of drivers included in the capsule and the number of corresponding
+ /// offsets stored in ItemOffsetList array.
+ ///
+ UINT16 EmbeddedDriverCount;
+
+ ///
+ /// The number of payload items included in the capsule and the number of
+ /// corresponding offsets stored in the ItemOffsetList array.
+ ///
+ UINT16 PayloadItemCount;
+
+ ///
+ /// Variable length array of dimension [EmbeddedDriverCount + PayloadItemCount]
+ /// containing offsets of each of the drivers and payload items contained within the capsule
+ ///
+ // UINT64 ItemOffsetList[];
+} EFI_FIRMWARE_MANAGEMENT_CAPSULE_HEADER;
+
+typedef struct {
+ UINT32 Version;
+
+ ///
+ /// Used to identify device firmware targeted by this update. This guid is matched by
+ /// system firmware against ImageTypeId field within a EFI_FIRMWARE_IMAGE_DESCRIPTOR
+ ///
+ EFI_GUID UpdateImageTypeId;
+
+ ///
+ /// Passed as ImageIndex in call to EFI_FIRMWARE_MANAGEMENT_PROTOCOL.SetImage()
+ ///
+ UINT8 UpdateImageIndex;
+ UINT8 reserved_bytes[3];
+
+ ///
+ /// Size of the binary update image which immediately follows this structure
+ ///
+ UINT32 UpdateImageSize;
+
+ ///
+ /// Size of the VendorCode bytes which optionally immediately follow binary update image in the capsule
+ ///
+ UINT32 UpdateVendorCodeSize;
+
+ ///
+ /// The HardwareInstance to target with this update. If value is zero it means match all
+ /// HardwareInstances. This field allows update software to target only a single device in
+ /// cases where there are more than one device with the same ImageTypeId GUID.
+ /// This header is outside the signed data of the Authentication Info structure and
+ /// therefore can be modified without changing the Auth data.
+ ///
+ UINT64 UpdateHardwareInstance;
+
+ ///
+ /// A 64-bit bitmask that determines what sections are added to the payload.
+ /// #define CAPSULE_SUPPORT_AUTHENTICATION 0x0000000000000001
+ /// #define CAPSULE_SUPPORT_DEPENDENCY 0x0000000000000002
+ ///
+ UINT64 ImageCapsuleSupport;
+} EFI_FIRMWARE_MANAGEMENT_CAPSULE_IMAGE_HEADER;
+
+#pragma pack()
+
+#define EFI_FIRMWARE_MANAGEMENT_CAPSULE_HEADER_INIT_VERSION 0x00000001
+#define EFI_FIRMWARE_MANAGEMENT_CAPSULE_IMAGE_HEADER_INIT_VERSION 0x00000003
+#define CAPSULE_SUPPORT_AUTHENTICATION 0x0000000000000001
+#define CAPSULE_SUPPORT_DEPENDENCY 0x0000000000000002
+
+extern EFI_GUID gEfiFmpCapsuleGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Guid/GlobalVariable.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Guid/GlobalVariable.h
new file mode 100644
index 0000000000..f1dfbc5fa9
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Guid/GlobalVariable.h
@@ -0,0 +1,186 @@
+/** @file
+ GUID for EFI (NVRAM) Variables.
+
+ Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Revision Reference:
+ GUID defined in UEFI 2.1
+**/
+
+#ifndef __GLOBAL_VARIABLE_GUID_H__
+#define __GLOBAL_VARIABLE_GUID_H__
+
+#define EFI_GLOBAL_VARIABLE \
+ { \
+ 0x8BE4DF61, 0x93CA, 0x11d2, {0xAA, 0x0D, 0x00, 0xE0, 0x98, 0x03, 0x2B, 0x8C } \
+ }
+
+extern EFI_GUID gEfiGlobalVariableGuid;
+
+//
+// Follow UEFI 2.4 spec:
+// To prevent name collisions with possible future globally defined variables,
+// other internal firmware data variables that are not defined here must be
+// saved with a unique VendorGuid other than EFI_GLOBAL_VARIABLE or
+// any other GUID defined by the UEFI Specification. Implementations must
+// only permit the creation of variables with a UEFI Specification-defined
+// VendorGuid when these variables are documented in the UEFI Specification.
+//
+// Note: except the globally defined variables defined below, the spec also defines
+// L"Boot####" - A boot load option.
+// L"Driver####" - A driver load option.
+// L"SysPrep####" - A System Prep application load option.
+// L"Key####" - Describes hot key relationship with a Boot#### load option.
+// The attribute for them is NV+BS+RT, #### is a printed hex value, and no 0x or h
+// is included in the hex value. They can not be expressed as a #define like other globally
+// defined variables, it is because we can not list the Boot0000, Boot0001, etc one by one.
+//
+
+///
+/// The language codes that the firmware supports. This value is deprecated.
+/// Its attribute is BS+RT.
+///
+#define EFI_LANG_CODES_VARIABLE_NAME L"LangCodes"
+///
+/// The language code that the system is configured for. This value is deprecated.
+/// Its attribute is NV+BS+RT.
+///
+#define EFI_LANG_VARIABLE_NAME L"Lang"
+///
+/// The firmware's boot managers timeout, in seconds, before initiating the default boot selection.
+/// Its attribute is NV+BS+RT.
+///
+#define EFI_TIME_OUT_VARIABLE_NAME L"Timeout"
+///
+/// The language codes that the firmware supports.
+/// Its attribute is BS+RT.
+///
+#define EFI_PLATFORM_LANG_CODES_VARIABLE_NAME L"PlatformLangCodes"
+///
+/// The language code that the system is configured for.
+/// Its attribute is NV+BS+RT.
+///
+#define EFI_PLATFORM_LANG_VARIABLE_NAME L"PlatformLang"
+///
+/// The device path of the default input/output/error output console.
+/// Its attribute is NV+BS+RT.
+///
+#define EFI_CON_IN_VARIABLE_NAME L"ConIn"
+#define EFI_CON_OUT_VARIABLE_NAME L"ConOut"
+#define EFI_ERR_OUT_VARIABLE_NAME L"ErrOut"
+///
+/// The device path of all possible input/output/error output devices.
+/// Its attribute is BS+RT.
+///
+#define EFI_CON_IN_DEV_VARIABLE_NAME L"ConInDev"
+#define EFI_CON_OUT_DEV_VARIABLE_NAME L"ConOutDev"
+#define EFI_ERR_OUT_DEV_VARIABLE_NAME L"ErrOutDev"
+///
+/// The ordered boot option load list.
+/// Its attribute is NV+BS+RT.
+///
+#define EFI_BOOT_ORDER_VARIABLE_NAME L"BootOrder"
+///
+/// The boot option for the next boot only.
+/// Its attribute is NV+BS+RT.
+///
+#define EFI_BOOT_NEXT_VARIABLE_NAME L"BootNext"
+///
+/// The boot option that was selected for the current boot.
+/// Its attribute is BS+RT.
+///
+#define EFI_BOOT_CURRENT_VARIABLE_NAME L"BootCurrent"
+///
+/// The types of boot options supported by the boot manager. Should be treated as read-only.
+/// Its attribute is BS+RT.
+///
+#define EFI_BOOT_OPTION_SUPPORT_VARIABLE_NAME L"BootOptionSupport"
+///
+/// The ordered driver load option list.
+/// Its attribute is NV+BS+RT.
+///
+#define EFI_DRIVER_ORDER_VARIABLE_NAME L"DriverOrder"
+///
+/// The ordered System Prep Application load option list.
+/// Its attribute is NV+BS+RT.
+///
+#define EFI_SYS_PREP_ORDER_VARIABLE_NAME L"SysPrepOrder"
+///
+/// Identifies the level of hardware error record persistence
+/// support implemented by the platform. This variable is
+/// only modified by firmware and is read-only to the OS.
+/// Its attribute is NV+BS+RT.
+///
+#define EFI_HW_ERR_REC_SUPPORT_VARIABLE_NAME L"HwErrRecSupport"
+///
+/// Whether the system is operating in setup mode (1) or not (0).
+/// All other values are reserved. Should be treated as read-only.
+/// Its attribute is BS+RT.
+///
+#define EFI_SETUP_MODE_NAME L"SetupMode"
+///
+/// The Key Exchange Key Signature Database.
+/// Its attribute is NV+BS+RT+AT.
+///
+#define EFI_KEY_EXCHANGE_KEY_NAME L"KEK"
+///
+/// The public Platform Key.
+/// Its attribute is NV+BS+RT+AT.
+///
+#define EFI_PLATFORM_KEY_NAME L"PK"
+///
+/// Array of GUIDs representing the type of signatures supported
+/// by the platform firmware. Should be treated as read-only.
+/// Its attribute is BS+RT.
+///
+#define EFI_SIGNATURE_SUPPORT_NAME L"SignatureSupport"
+///
+/// Whether the platform firmware is operating in Secure boot mode (1) or not (0).
+/// All other values are reserved. Should be treated as read-only.
+/// Its attribute is BS+RT.
+///
+#define EFI_SECURE_BOOT_MODE_NAME L"SecureBoot"
+///
+/// The OEM's default Key Exchange Key Signature Database. Should be treated as read-only.
+/// Its attribute is BS+RT.
+///
+#define EFI_KEK_DEFAULT_VARIABLE_NAME L"KEKDefault"
+///
+/// The OEM's default public Platform Key. Should be treated as read-only.
+/// Its attribute is BS+RT.
+///
+#define EFI_PK_DEFAULT_VARIABLE_NAME L"PKDefault"
+///
+/// The OEM's default secure boot signature store. Should be treated as read-only.
+/// Its attribute is BS+RT.
+///
+#define EFI_DB_DEFAULT_VARIABLE_NAME L"dbDefault"
+///
+/// The OEM's default secure boot blacklist signature store. Should be treated as read-only.
+/// Its attribute is BS+RT.
+///
+#define EFI_DBX_DEFAULT_VARIABLE_NAME L"dbxDefault"
+///
+/// The OEM's default secure boot timestamp signature store. Should be treated as read-only.
+/// Its attribute is BS+RT.
+///
+#define EFI_DBT_DEFAULT_VARIABLE_NAME L"dbtDefault"
+///
+/// Allows the firmware to indicate supported features and actions to the OS.
+/// Its attribute is BS+RT.
+///
+#define EFI_OS_INDICATIONS_SUPPORT_VARIABLE_NAME L"OsIndicationsSupported"
+///
+/// Allows the OS to request the firmware to enable certain features and to take certain actions.
+/// Its attribute is NV+BS+RT.
+///
+#define EFI_OS_INDICATIONS_VARIABLE_NAME L"OsIndications"
+///
+/// Whether the system is configured to use only vendor provided
+/// keys or not. Should be treated as read-only.
+/// Its attribute is BS+RT.
+///
+#define EFI_VENDOR_KEYS_VARIABLE_NAME L"VendorKeys"
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Guid/Gpt.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Guid/Gpt.h
new file mode 100644
index 0000000000..8e6ec1f6bd
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Guid/Gpt.h
@@ -0,0 +1,37 @@
+/** @file
+ Guids used for the GPT (GUID Partition Table)
+
+ GPT defines a new disk partitioning scheme and also describes
+ usage of the legacy Master Boot Record (MBR) partitioning scheme.
+
+ Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Revision Reference:
+ GUIDs defined in UEFI 2.1 spec.
+
+**/
+
+#ifndef __GPT_GUID_H__
+#define __GPT_GUID_H__
+
+#define EFI_PART_TYPE_UNUSED_GUID \
+ { \
+ 0x00000000, 0x0000, 0x0000, {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 } \
+ }
+
+#define EFI_PART_TYPE_EFI_SYSTEM_PART_GUID \
+ { \
+ 0xc12a7328, 0xf81f, 0x11d2, {0xba, 0x4b, 0x00, 0xa0, 0xc9, 0x3e, 0xc9, 0x3b } \
+ }
+
+#define EFI_PART_TYPE_LEGACY_MBR_GUID \
+ { \
+ 0x024dee41, 0x33e7, 0x11d3, {0x9d, 0x69, 0x00, 0x08, 0xc7, 0x81, 0xf3, 0x9f } \
+ }
+
+extern EFI_GUID gEfiPartTypeUnusedGuid;
+extern EFI_GUID gEfiPartTypeSystemPartGuid;
+extern EFI_GUID gEfiPartTypeLegacyMbrGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Guid/GraphicsInfoHob.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Guid/GraphicsInfoHob.h
new file mode 100644
index 0000000000..20f8b0c3d0
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Guid/GraphicsInfoHob.h
@@ -0,0 +1,45 @@
+/** @file
+ Hob guid for Information about the graphics mode.
+
+ Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Revision Reference:
+ This HOB is introduced in in PI Version 1.4.
+
+**/
+
+#ifndef _GRAPHICS_INFO_HOB_GUID_H_
+#define _GRAPHICS_INFO_HOB_GUID_H_
+
+#include
+
+#define EFI_PEI_GRAPHICS_INFO_HOB_GUID \
+ { \
+ 0x39f62cce, 0x6825, 0x4669, { 0xbb, 0x56, 0x54, 0x1a, 0xba, 0x75, 0x3a, 0x07 } \
+ }
+
+#define EFI_PEI_GRAPHICS_DEVICE_INFO_HOB_GUID \
+ { \
+ 0xe5cb2ac9, 0xd35d, 0x4430, { 0x93, 0x6e, 0x1d, 0xe3, 0x32, 0x47, 0x8d, 0xe7 } \
+ }
+
+typedef struct {
+ EFI_PHYSICAL_ADDRESS FrameBufferBase;
+ UINT32 FrameBufferSize;
+ EFI_GRAPHICS_OUTPUT_MODE_INFORMATION GraphicsMode;
+} EFI_PEI_GRAPHICS_INFO_HOB;
+
+typedef struct {
+ UINT16 VendorId; ///< Ignore if the value is 0xFFFF.
+ UINT16 DeviceId; ///< Ignore if the value is 0xFFFF.
+ UINT16 SubsystemVendorId; ///< Ignore if the value is 0xFFFF.
+ UINT16 SubsystemId; ///< Ignore if the value is 0xFFFF.
+ UINT8 RevisionId; ///< Ignore if the value is 0xFF.
+ UINT8 BarIndex; ///< Ignore if the value is 0xFF.
+} EFI_PEI_GRAPHICS_DEVICE_INFO_HOB;
+
+extern EFI_GUID gEfiGraphicsInfoHobGuid;
+extern EFI_GUID gEfiGraphicsDeviceInfoHobGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Guid/HardwareErrorVariable.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Guid/HardwareErrorVariable.h
new file mode 100644
index 0000000000..8f5d320faf
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Guid/HardwareErrorVariable.h
@@ -0,0 +1,22 @@
+/** @file
+ GUID for hardware error record variables.
+
+ Copyright (c) 2007 - 2009, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Revision Reference:
+ GUID defined in UEFI 2.1.
+
+**/
+
+#ifndef _HARDWARE_ERROR_VARIABLE_GUID_H_
+#define _HARDWARE_ERROR_VARIABLE_GUID_H_
+
+#define EFI_HARDWARE_ERROR_VARIABLE \
+ { \
+ 0x414E6BDD, 0xE47B, 0x47cc, {0xB2, 0x44, 0xBB, 0x61, 0x02, 0x0C, 0xF5, 0x16} \
+ }
+
+extern EFI_GUID gEfiHardwareErrorVariableGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Guid/HiiFormMapMethodGuid.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Guid/HiiFormMapMethodGuid.h
new file mode 100644
index 0000000000..57836a5ae2
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Guid/HiiFormMapMethodGuid.h
@@ -0,0 +1,19 @@
+/** @file
+ Guid used to identify HII FormMap configuration method.
+
+ Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Revision Reference:
+ GUID defined in UEFI 2.2 spec.
+**/
+
+#ifndef __EFI_HII_FORMMAP_GUID_H__
+#define __EFI_HII_FORMMAP_GUID_H__
+
+#define EFI_HII_STANDARD_FORM_GUID \
+ { 0x3bd2f4ec, 0xe524, 0x46e4, { 0xa9, 0xd8, 0x51, 0x1, 0x17, 0x42, 0x55, 0x62 } }
+
+extern EFI_GUID gEfiHiiStandardFormGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Guid/HiiKeyBoardLayout.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Guid/HiiKeyBoardLayout.h
new file mode 100644
index 0000000000..b8888675c0
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Guid/HiiKeyBoardLayout.h
@@ -0,0 +1,21 @@
+/** @file
+
+ HII keyboard layout GUID as defined in UEFI2.1 specification
+
+ Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Revision Reference:
+ GUIDs defined in UEFI 2.1 spec.
+
+**/
+
+#ifndef __HII_KEYBOARD_LAYOUT_GUID_H__
+#define __HII_KEYBOARD_LAYOUT_GUID_H__
+
+#define EFI_HII_SET_KEYBOARD_LAYOUT_EVENT_GUID \
+ { 0x14982a4f, 0xb0ed, 0x45b8, { 0xa8, 0x11, 0x5a, 0x7a, 0x9b, 0xc2, 0x32, 0xdf }}
+
+extern EFI_GUID gEfiHiiKeyBoardLayoutGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Guid/HiiPlatformSetupFormset.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Guid/HiiPlatformSetupFormset.h
new file mode 100644
index 0000000000..4ed0f55c05
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Guid/HiiPlatformSetupFormset.h
@@ -0,0 +1,33 @@
+/** @file
+ GUID indicates that the form set contains forms designed to be used
+ for platform configuration and this form set will be displayed.
+
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Revision Reference:
+ GUID defined in UEFI 2.1.
+
+**/
+
+#ifndef __HII_PLATFORM_SETUP_FORMSET_GUID_H__
+#define __HII_PLATFORM_SETUP_FORMSET_GUID_H__
+
+#define EFI_HII_PLATFORM_SETUP_FORMSET_GUID \
+ { 0x93039971, 0x8545, 0x4b04, { 0xb4, 0x5e, 0x32, 0xeb, 0x83, 0x26, 0x4, 0xe } }
+
+#define EFI_HII_DRIVER_HEALTH_FORMSET_GUID \
+ { 0xf22fc20c, 0x8cf4, 0x45eb, { 0x8e, 0x6, 0xad, 0x4e, 0x50, 0xb9, 0x5d, 0xd3 } }
+
+#define EFI_HII_USER_CREDENTIAL_FORMSET_GUID \
+ { 0x337f4407, 0x5aee, 0x4b83, { 0xb2, 0xa7, 0x4e, 0xad, 0xca, 0x30, 0x88, 0xcd } }
+
+#define EFI_HII_REST_STYLE_FORMSET_GUID \
+ { 0x790217bd, 0xbecf, 0x485b, { 0x91, 0x70, 0x5f, 0xf7, 0x11, 0x31, 0x8b, 0x27 } }
+
+extern EFI_GUID gEfiHiiPlatformSetupFormsetGuid;
+extern EFI_GUID gEfiHiiDriverHealthFormsetGuid;
+extern EFI_GUID gEfiHiiUserCredentialFormsetGuid;
+extern EFI_GUID gEfiHiiRestStyleFormsetGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Guid/HobList.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Guid/HobList.h
new file mode 100644
index 0000000000..f18a9d35f1
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Guid/HobList.h
@@ -0,0 +1,24 @@
+/** @file
+ GUIDs used for HOB List entries
+
+ These GUIDs point the HOB List passed from PEI to DXE.
+
+ Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Revision Reference:
+ GUID introduced in PI Version 1.0.
+
+**/
+
+#ifndef __HOB_LIST_GUID_H__
+#define __HOB_LIST_GUID_H__
+
+#define HOB_LIST_GUID \
+ { \
+ 0x7739f24c, 0x93d7, 0x11d4, {0x9a, 0x3a, 0x0, 0x90, 0x27, 0x3f, 0xc1, 0x4d } \
+ }
+
+extern EFI_GUID gEfiHobListGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Guid/ImageAuthentication.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Guid/ImageAuthentication.h
new file mode 100644
index 0000000000..91d4e27d7a
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Guid/ImageAuthentication.h
@@ -0,0 +1,345 @@
+/** @file
+ Image signature database are defined for the signed image validation.
+
+ Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Revision Reference:
+ GUIDs defined in UEFI 2.5 spec.
+**/
+
+#ifndef __IMAGE_AUTHTICATION_H__
+#define __IMAGE_AUTHTICATION_H__
+
+#include
+#include
+
+#define EFI_IMAGE_SECURITY_DATABASE_GUID \
+ { \
+ 0xd719b2cb, 0x3d3a, 0x4596, { 0xa3, 0xbc, 0xda, 0xd0, 0xe, 0x67, 0x65, 0x6f } \
+ }
+
+///
+/// Varialbe name with guid EFI_IMAGE_SECURITY_DATABASE_GUID
+/// for the authorized signature database.
+///
+#define EFI_IMAGE_SECURITY_DATABASE L"db"
+///
+/// Varialbe name with guid EFI_IMAGE_SECURITY_DATABASE_GUID
+/// for the forbidden signature database.
+///
+#define EFI_IMAGE_SECURITY_DATABASE1 L"dbx"
+///
+/// Variable name with guid EFI_IMAGE_SECURITY_DATABASE_GUID
+/// for the timestamp signature database.
+///
+#define EFI_IMAGE_SECURITY_DATABASE2 L"dbt"
+
+#define SECURE_BOOT_MODE_ENABLE 1
+#define SECURE_BOOT_MODE_DISABLE 0
+
+#define SETUP_MODE 1
+#define USER_MODE 0
+
+// ***********************************************************************
+// Signature Database
+// ***********************************************************************
+///
+/// The format of a signature database.
+///
+#pragma pack(1)
+
+typedef struct {
+ ///
+ /// An identifier which identifies the agent which added the signature to the list.
+ ///
+ EFI_GUID SignatureOwner;
+ ///
+ /// The format of the signature is defined by the SignatureType.
+ ///
+ UINT8 SignatureData[1];
+} EFI_SIGNATURE_DATA;
+
+typedef struct {
+ ///
+ /// Type of the signature. GUID signature types are defined in below.
+ ///
+ EFI_GUID SignatureType;
+ ///
+ /// Total size of the signature list, including this header.
+ ///
+ UINT32 SignatureListSize;
+ ///
+ /// Size of the signature header which precedes the array of signatures.
+ ///
+ UINT32 SignatureHeaderSize;
+ ///
+ /// Size of each signature.
+ ///
+ UINT32 SignatureSize;
+ ///
+ /// Header before the array of signatures. The format of this header is specified
+ /// by the SignatureType.
+ /// UINT8 SignatureHeader[SignatureHeaderSize];
+ ///
+ /// An array of signatures. Each signature is SignatureSize bytes in length.
+ /// EFI_SIGNATURE_DATA Signatures[][SignatureSize];
+ ///
+} EFI_SIGNATURE_LIST;
+
+typedef struct {
+ ///
+ /// The SHA256 hash of an X.509 certificate's To-Be-Signed contents.
+ ///
+ EFI_SHA256_HASH ToBeSignedHash;
+ ///
+ /// The time that the certificate shall be considered to be revoked.
+ ///
+ EFI_TIME TimeOfRevocation;
+} EFI_CERT_X509_SHA256;
+
+typedef struct {
+ ///
+ /// The SHA384 hash of an X.509 certificate's To-Be-Signed contents.
+ ///
+ EFI_SHA384_HASH ToBeSignedHash;
+ ///
+ /// The time that the certificate shall be considered to be revoked.
+ ///
+ EFI_TIME TimeOfRevocation;
+} EFI_CERT_X509_SHA384;
+
+typedef struct {
+ ///
+ /// The SHA512 hash of an X.509 certificate's To-Be-Signed contents.
+ ///
+ EFI_SHA512_HASH ToBeSignedHash;
+ ///
+ /// The time that the certificate shall be considered to be revoked.
+ ///
+ EFI_TIME TimeOfRevocation;
+} EFI_CERT_X509_SHA512;
+
+#pragma pack()
+
+///
+/// This identifies a signature containing a SHA-256 hash. The SignatureHeader size shall
+/// always be 0. The SignatureSize shall always be 16 (size of SignatureOwner component) +
+/// 32 bytes.
+///
+#define EFI_CERT_SHA256_GUID \
+ { \
+ 0xc1c41626, 0x504c, 0x4092, {0xac, 0xa9, 0x41, 0xf9, 0x36, 0x93, 0x43, 0x28} \
+ }
+
+///
+/// This identifies a signature containing an RSA-2048 key. The key (only the modulus
+/// since the public key exponent is known to be 0x10001) shall be stored in big-endian
+/// order.
+/// The SignatureHeader size shall always be 0. The SignatureSize shall always be 16 (size
+/// of SignatureOwner component) + 256 bytes.
+///
+#define EFI_CERT_RSA2048_GUID \
+ { \
+ 0x3c5766e8, 0x269c, 0x4e34, {0xaa, 0x14, 0xed, 0x77, 0x6e, 0x85, 0xb3, 0xb6} \
+ }
+
+///
+/// This identifies a signature containing a RSA-2048 signature of a SHA-256 hash. The
+/// SignatureHeader size shall always be 0. The SignatureSize shall always be 16 (size of
+/// SignatureOwner component) + 256 bytes.
+///
+#define EFI_CERT_RSA2048_SHA256_GUID \
+ { \
+ 0xe2b36190, 0x879b, 0x4a3d, {0xad, 0x8d, 0xf2, 0xe7, 0xbb, 0xa3, 0x27, 0x84} \
+ }
+
+///
+/// This identifies a signature containing a SHA-1 hash. The SignatureSize shall always
+/// be 16 (size of SignatureOwner component) + 20 bytes.
+///
+#define EFI_CERT_SHA1_GUID \
+ { \
+ 0x826ca512, 0xcf10, 0x4ac9, {0xb1, 0x87, 0xbe, 0x1, 0x49, 0x66, 0x31, 0xbd} \
+ }
+
+///
+/// TThis identifies a signature containing a RSA-2048 signature of a SHA-1 hash. The
+/// SignatureHeader size shall always be 0. The SignatureSize shall always be 16 (size of
+/// SignatureOwner component) + 256 bytes.
+///
+#define EFI_CERT_RSA2048_SHA1_GUID \
+ { \
+ 0x67f8444f, 0x8743, 0x48f1, {0xa3, 0x28, 0x1e, 0xaa, 0xb8, 0x73, 0x60, 0x80} \
+ }
+
+///
+/// This identifies a signature based on an X.509 certificate. If the signature is an X.509
+/// certificate then verification of the signature of an image should validate the public
+/// key certificate in the image using certificate path verification, up to this X.509
+/// certificate as a trusted root. The SignatureHeader size shall always be 0. The
+/// SignatureSize may vary but shall always be 16 (size of the SignatureOwner component) +
+/// the size of the certificate itself.
+/// Note: This means that each certificate will normally be in a separate EFI_SIGNATURE_LIST.
+///
+#define EFI_CERT_X509_GUID \
+ { \
+ 0xa5c059a1, 0x94e4, 0x4aa7, {0x87, 0xb5, 0xab, 0x15, 0x5c, 0x2b, 0xf0, 0x72} \
+ }
+
+///
+/// This identifies a signature containing a SHA-224 hash. The SignatureHeader size shall
+/// always be 0. The SignatureSize shall always be 16 (size of SignatureOwner component) +
+/// 28 bytes.
+///
+#define EFI_CERT_SHA224_GUID \
+ { \
+ 0xb6e5233, 0xa65c, 0x44c9, {0x94, 0x7, 0xd9, 0xab, 0x83, 0xbf, 0xc8, 0xbd} \
+ }
+
+///
+/// This identifies a signature containing a SHA-384 hash. The SignatureHeader size shall
+/// always be 0. The SignatureSize shall always be 16 (size of SignatureOwner component) +
+/// 48 bytes.
+///
+#define EFI_CERT_SHA384_GUID \
+ { \
+ 0xff3e5307, 0x9fd0, 0x48c9, {0x85, 0xf1, 0x8a, 0xd5, 0x6c, 0x70, 0x1e, 0x1} \
+ }
+
+///
+/// This identifies a signature containing a SHA-512 hash. The SignatureHeader size shall
+/// always be 0. The SignatureSize shall always be 16 (size of SignatureOwner component) +
+/// 64 bytes.
+///
+#define EFI_CERT_SHA512_GUID \
+ { \
+ 0x93e0fae, 0xa6c4, 0x4f50, {0x9f, 0x1b, 0xd4, 0x1e, 0x2b, 0x89, 0xc1, 0x9a} \
+ }
+
+///
+/// This identifies a signature containing the SHA256 hash of an X.509 certificate's
+/// To-Be-Signed contents, and a time of revocation. The SignatureHeader size shall
+/// always be 0. The SignatureSize shall always be 16 (size of the SignatureOwner component)
+/// + 48 bytes for an EFI_CERT_X509_SHA256 structure. If the TimeOfRevocation is non-zero,
+/// the certificate should be considered to be revoked from that time and onwards, and
+/// otherwise the certificate shall be considered to always be revoked.
+///
+#define EFI_CERT_X509_SHA256_GUID \
+ { \
+ 0x3bd2a492, 0x96c0, 0x4079, {0xb4, 0x20, 0xfc, 0xf9, 0x8e, 0xf1, 0x03, 0xed } \
+ }
+
+///
+/// This identifies a signature containing the SHA384 hash of an X.509 certificate's
+/// To-Be-Signed contents, and a time of revocation. The SignatureHeader size shall
+/// always be 0. The SignatureSize shall always be 16 (size of the SignatureOwner component)
+/// + 64 bytes for an EFI_CERT_X509_SHA384 structure. If the TimeOfRevocation is non-zero,
+/// the certificate should be considered to be revoked from that time and onwards, and
+/// otherwise the certificate shall be considered to always be revoked.
+///
+#define EFI_CERT_X509_SHA384_GUID \
+ { \
+ 0x7076876e, 0x80c2, 0x4ee6, {0xaa, 0xd2, 0x28, 0xb3, 0x49, 0xa6, 0x86, 0x5b } \
+ }
+
+///
+/// This identifies a signature containing the SHA512 hash of an X.509 certificate's
+/// To-Be-Signed contents, and a time of revocation. The SignatureHeader size shall
+/// always be 0. The SignatureSize shall always be 16 (size of the SignatureOwner component)
+/// + 80 bytes for an EFI_CERT_X509_SHA512 structure. If the TimeOfRevocation is non-zero,
+/// the certificate should be considered to be revoked from that time and onwards, and
+/// otherwise the certificate shall be considered to always be revoked.
+///
+#define EFI_CERT_X509_SHA512_GUID \
+ { \
+ 0x446dbf63, 0x2502, 0x4cda, {0xbc, 0xfa, 0x24, 0x65, 0xd2, 0xb0, 0xfe, 0x9d } \
+ }
+
+///
+/// This identifies a signature containing a DER-encoded PKCS #7 version 1.5 [RFC2315]
+/// SignedData value.
+///
+#define EFI_CERT_TYPE_PKCS7_GUID \
+ { \
+ 0x4aafd29d, 0x68df, 0x49ee, {0x8a, 0xa9, 0x34, 0x7d, 0x37, 0x56, 0x65, 0xa7} \
+ }
+
+// ***********************************************************************
+// Image Execution Information Table Definition
+// ***********************************************************************
+typedef UINT32 EFI_IMAGE_EXECUTION_ACTION;
+
+#define EFI_IMAGE_EXECUTION_AUTHENTICATION 0x00000007
+#define EFI_IMAGE_EXECUTION_AUTH_UNTESTED 0x00000000
+#define EFI_IMAGE_EXECUTION_AUTH_SIG_FAILED 0x00000001
+#define EFI_IMAGE_EXECUTION_AUTH_SIG_PASSED 0x00000002
+#define EFI_IMAGE_EXECUTION_AUTH_SIG_NOT_FOUND 0x00000003
+#define EFI_IMAGE_EXECUTION_AUTH_SIG_FOUND 0x00000004
+#define EFI_IMAGE_EXECUTION_POLICY_FAILED 0x00000005
+#define EFI_IMAGE_EXECUTION_INITIALIZED 0x00000008
+
+//
+// EFI_IMAGE_EXECUTION_INFO is added to EFI System Configuration Table
+// and assigned the GUID EFI_IMAGE_SECURITY_DATABASE_GUID.
+//
+typedef struct {
+ ///
+ /// Describes the action taken by the firmware regarding this image.
+ ///
+ EFI_IMAGE_EXECUTION_ACTION Action;
+ ///
+ /// Size of all of the entire structure.
+ ///
+ UINT32 InfoSize;
+ ///
+ /// If this image was a UEFI device driver (for option ROM, for example) this is the
+ /// null-terminated, user-friendly name for the device. If the image was for an application,
+ /// then this is the name of the application. If this cannot be determined, then a simple
+ /// NULL character should be put in this position.
+ /// CHAR16 Name[];
+ ///
+
+ ///
+ /// For device drivers, this is the device path of the device for which this device driver
+ /// was intended. In some cases, the driver itself may be stored as part of the system
+ /// firmware, but this field should record the device's path, not the firmware path. For
+ /// applications, this is the device path of the application. If this cannot be determined,
+ /// a simple end-of-path device node should be put in this position.
+ /// EFI_DEVICE_PATH_PROTOCOL DevicePath;
+ ///
+
+ ///
+ /// Zero or more image signatures. If the image contained no signatures,
+ /// then this field is empty.
+ /// EFI_SIGNATURE_LIST Signature;
+ ///
+} EFI_IMAGE_EXECUTION_INFO;
+
+typedef struct {
+ ///
+ /// Number of EFI_IMAGE_EXECUTION_INFO structures.
+ ///
+ UINTN NumberOfImages;
+ ///
+ /// Number of image instances of EFI_IMAGE_EXECUTION_INFO structures.
+ ///
+ // EFI_IMAGE_EXECUTION_INFO InformationInfo[]
+} EFI_IMAGE_EXECUTION_INFO_TABLE;
+
+extern EFI_GUID gEfiImageSecurityDatabaseGuid;
+extern EFI_GUID gEfiCertSha256Guid;
+extern EFI_GUID gEfiCertRsa2048Guid;
+extern EFI_GUID gEfiCertRsa2048Sha256Guid;
+extern EFI_GUID gEfiCertSha1Guid;
+extern EFI_GUID gEfiCertRsa2048Sha1Guid;
+extern EFI_GUID gEfiCertX509Guid;
+extern EFI_GUID gEfiCertSha224Guid;
+extern EFI_GUID gEfiCertSha384Guid;
+extern EFI_GUID gEfiCertSha512Guid;
+extern EFI_GUID gEfiCertX509Sha256Guid;
+extern EFI_GUID gEfiCertX509Sha384Guid;
+extern EFI_GUID gEfiCertX509Sha512Guid;
+extern EFI_GUID gEfiCertPkcs7Guid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Guid/JsonCapsule.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Guid/JsonCapsule.h
new file mode 100644
index 0000000000..6c96fc3753
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Guid/JsonCapsule.h
@@ -0,0 +1,96 @@
+/** @file
+Guid & data structure for tables defined for reporting firmware configuration data to EFI
+Configuration Tables and also for processing JSON payload capsule.
+
+
+Copyright (c) 2020, American Megatrends International LLC. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __JSON_CAPSULE_GUID_H__
+#define __JSON_CAPSULE_GUID_H__
+
+//
+// The address reported in the table entry identified by EFI_JSON_CAPSULE_DATA_TABLE_GUID will be
+// referenced as physical and will not be fixed up when transition from preboot to runtime phase. The
+// addresses reported in these table entries identified by EFI_JSON_CONFIG_DATA_TABLE_GUID and
+// EFI_JSON_CAPSULE_RESULT_TABLE_GUID will be referenced as virtual and will be fixed up when
+// transition from preboot to runtime phase.
+//
+#define EFI_JSON_CONFIG_DATA_TABLE_GUID \
+ {0x87367f87, 0x1119, 0x41ce, \
+ {0xaa, 0xec, 0x8b, 0xe0, 0x11, 0x1f, 0x55, 0x8a }}
+#define EFI_JSON_CAPSULE_DATA_TABLE_GUID \
+ {0x35e7a725, 0x8dd2, 0x4cac, \
+ {0x80, 0x11, 0x33, 0xcd, 0xa8, 0x10, 0x90, 0x56 }}
+#define EFI_JSON_CAPSULE_RESULT_TABLE_GUID \
+ {0xdbc461c3, 0xb3de, 0x422a,\
+ {0xb9, 0xb4, 0x98, 0x86, 0xfd, 0x49, 0xa1, 0xe5 }}
+#define EFI_JSON_CAPSULE_ID_GUID \
+ {0x67d6f4cd, 0xd6b8, 0x4573, \
+ {0xbf, 0x4a, 0xde, 0x5e, 0x25, 0x2d, 0x61, 0xae }}
+
+#pragma pack(1)
+
+typedef struct {
+ ///
+ /// Version of the structure, initially 0x00000001.
+ ///
+ UINT32 Version;
+
+ ///
+ /// The unique identifier of this capsule.
+ ///
+ UINT32 CapsuleId;
+
+ ///
+ /// The length of the JSON payload immediately following this header, in bytes.
+ ///
+ UINT32 PayloadLength;
+
+ ///
+ /// Variable length buffer containing the JSON payload that should be parsed and applied to the system. The
+ /// definition of the JSON schema used in the payload is beyond the scope of this specification.
+ ///
+ UINT8 Payload[];
+} EFI_JSON_CAPSULE_HEADER;
+
+typedef struct {
+ ///
+ /// The length of the following ConfigData, in bytes.
+ ///
+ UINT32 ConfigDataLength;
+
+ ///
+ /// Variable length buffer containing the JSON payload that describes one group of configuration data within
+ /// current system. The definition of the JSON schema used in this payload is beyond the scope of this specification.
+ ///
+ UINT8 ConfigData[];
+} EFI_JSON_CONFIG_DATA_ITEM;
+
+typedef struct {
+ ///
+ /// Version of the structure, initially 0x00000001.
+ ///
+ UINT32 Version;
+
+ ///
+ ////The total length of EFI_JSON_CAPSULE_CONFIG_DATA, in bytes.
+ ///
+ UINT32 TotalLength;
+
+ ///
+ /// Array of configuration data groups.
+ ///
+ EFI_JSON_CONFIG_DATA_ITEM ConfigDataList[];
+} EFI_JSON_CAPSULE_CONFIG_DATA;
+
+#pragma pack()
+
+extern EFI_GUID gEfiJsonConfigDataTableGuid;
+extern EFI_GUID gEfiJsonCapsuleDataTableGuid;
+extern EFI_GUID gEfiJsonCapsuleResultTableGuid;
+extern EFI_GUID gEfiJsonCapsuleIdGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Guid/LinuxEfiInitrdMedia.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Guid/LinuxEfiInitrdMedia.h
new file mode 100644
index 0000000000..5f62027850
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Guid/LinuxEfiInitrdMedia.h
@@ -0,0 +1,30 @@
+/** @file
+ GUID definition for the Linux Initrd media device path
+
+ Linux distro boot generally relies on an initial ramdisk (initrd) which is
+ provided by the loader, and which contains additional kernel modules (for
+ storage and network, for instance), and the initial user space startup code,
+ i.e., the code which brings up the user space side of the entire OS.
+
+ In order to provide a standard method to locate this initrd, the GUID defined
+ in this file is used to describe the device path for a LoadFile2 Protocol
+ instance that is responsible for loading the initrd file.
+
+ The kernel EFI Stub will locate and use this instance to load the initrd,
+ therefore the firmware/loader should install an instance of this to load the
+ relevant initrd.
+
+ Copyright (c) 2020, Arm, Ltd. All rights reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef LINUX_EFI_INITRD_MEDIA_GUID_H_
+#define LINUX_EFI_INITRD_MEDIA_GUID_H_
+
+#define LINUX_EFI_INITRD_MEDIA_GUID \
+ {0x5568e427, 0x68fc, 0x4f3d, {0xac, 0x74, 0xca, 0x55, 0x52, 0x31, 0xcc, 0x68}}
+
+extern EFI_GUID gLinuxEfiInitrdMediaGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Guid/MdePkgTokenSpace.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Guid/MdePkgTokenSpace.h
new file mode 100644
index 0000000000..3f333f1699
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Guid/MdePkgTokenSpace.h
@@ -0,0 +1,19 @@
+/** @file
+ GUID for MdePkg PCD Token Space
+
+ Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _MDEPKG_TOKEN_SPACE_GUID_H_
+#define _MDEPKG_TOKEN_SPACE_GUID_H_
+
+#define MDEPKG_TOKEN_SPACE_GUID \
+ { \
+ 0x914AEBE7, 0x4635, 0x459b, { 0xAA, 0x1C, 0x11, 0xE2, 0x19, 0xB0, 0x3A, 0x10 } \
+ }
+
+extern EFI_GUID gEfiMdePkgTokenSpaceGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Guid/MemoryAllocationHob.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Guid/MemoryAllocationHob.h
new file mode 100644
index 0000000000..6054a2c097
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Guid/MemoryAllocationHob.h
@@ -0,0 +1,28 @@
+/** @file
+ GUIDs for HOBs used in memory allcation
+
+ Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Revision Reference:
+ GUIDs introduced in PI Version 1.0.
+
+**/
+
+#ifndef __MEMORY_ALLOCATION_GUID_H__
+#define __MEMORY_ALLOCATION_GUID_H__
+
+#define EFI_HOB_MEMORY_ALLOC_BSP_STORE_GUID \
+ {0x564b33cd, 0xc92a, 0x4593, {0x90, 0xbf, 0x24, 0x73, 0xe4, 0x3c, 0x63, 0x22} };
+
+#define EFI_HOB_MEMORY_ALLOC_STACK_GUID \
+ {0x4ed4bf27, 0x4092, 0x42e9, {0x80, 0x7d, 0x52, 0x7b, 0x1d, 0x0, 0xc9, 0xbd} }
+
+#define EFI_HOB_MEMORY_ALLOC_MODULE_GUID \
+ {0xf8e21975, 0x899, 0x4f58, {0xa4, 0xbe, 0x55, 0x25, 0xa9, 0xc6, 0xd7, 0x7a} }
+
+extern EFI_GUID gEfiHobMemoryAllocBspStoreGuid;
+extern EFI_GUID gEfiHobMemoryAllocStackGuid;
+extern EFI_GUID gEfiHobMemoryAllocModuleGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Guid/MemoryAttributesTable.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Guid/MemoryAttributesTable.h
new file mode 100644
index 0000000000..64fa49d490
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Guid/MemoryAttributesTable.h
@@ -0,0 +1,28 @@
+/** @file
+ GUIDs used for UEFI Memory Attributes Table in the UEFI 2.6 specification.
+
+ Copyright (c) 2016, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __UEFI_MEMORY_ATTRIBUTES_TABLE_H__
+#define __UEFI_MEMORY_ATTRIBUTES_TABLE_H__
+
+#define EFI_MEMORY_ATTRIBUTES_TABLE_GUID {\
+ 0xdcfa911d, 0x26eb, 0x469f, {0xa2, 0x20, 0x38, 0xb7, 0xdc, 0x46, 0x12, 0x20} \
+}
+
+typedef struct {
+ UINT32 Version;
+ UINT32 NumberOfEntries;
+ UINT32 DescriptorSize;
+ UINT32 Reserved;
+ // EFI_MEMORY_DESCRIPTOR Entry[1];
+} EFI_MEMORY_ATTRIBUTES_TABLE;
+
+#define EFI_MEMORY_ATTRIBUTES_TABLE_VERSION 0x00000001
+
+extern EFI_GUID gEfiMemoryAttributesTableGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Guid/MemoryOverwriteControl.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Guid/MemoryOverwriteControl.h
new file mode 100644
index 0000000000..8ee9bbe515
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Guid/MemoryOverwriteControl.h
@@ -0,0 +1,70 @@
+/** @file
+ GUID used for MemoryOverwriteRequestControl UEFI variable defined in
+ TCG Platform Reset Attack Mitigation Specification 1.00.
+ See http://trustedcomputinggroup.org for the latest specification
+
+ The purpose of the MemoryOverwriteRequestControl UEFI variable is to give users (e.g., OS, loader) the ability to
+ indicate to the platform that secrets are present in memory and that the platform firmware must clear memory upon
+ a restart. The OS loader should not create the variable. Rather, the firmware is required to create it.
+
+ Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _MEMORY_OVERWRITE_CONTROL_DATA_GUID_H_
+#define _MEMORY_OVERWRITE_CONTROL_DATA_GUID_H_
+
+#define MEMORY_ONLY_RESET_CONTROL_GUID \
+ { \
+ 0xe20939be, 0x32d4, 0x41be, {0xa1, 0x50, 0x89, 0x7f, 0x85, 0xd4, 0x98, 0x29} \
+ }
+
+///
+/// Variable name is "MemoryOverwriteRequestControl" and it is a 1 byte unsigned value.
+/// The attributes should be:
+/// EFI_VARIABLE_NON_VOLATILE |
+/// EFI_VARIABLE_BOOTSERVICE_ACCESS |
+/// EFI_VARIABLE_RUNTIME_ACCESS
+///
+#define MEMORY_OVERWRITE_REQUEST_VARIABLE_NAME L"MemoryOverwriteRequestControl"
+
+///
+/// 0 = Firmware MUST clear the MOR bit
+/// 1 = Firmware MUST set the MOR bit
+///
+#define MOR_CLEAR_MEMORY_BIT_MASK 0x01
+
+///
+/// 0 = Firmware MAY autodetect a clean shutdown of the Static RTM OS.
+/// 1 = Firmware MUST NOT autodetect a clean shutdown of the Static RTM OS.
+///
+#define MOR_DISABLEAUTODETECT_BIT_MASK 0x10
+
+///
+/// MOR field bit offset
+///
+#define MOR_CLEAR_MEMORY_BIT_OFFSET 0
+#define MOR_DISABLEAUTODETECT_BIT_OFFSET 4
+
+/**
+ Return the ClearMemory bit value 0 or 1.
+
+ @param mor 1 byte value that contains ClearMemory and DisableAutoDetect bit.
+
+ @return ClearMemory bit value
+**/
+#define MOR_CLEAR_MEMORY_VALUE(mor) (((UINT8)(mor) & MOR_CLEAR_MEMORY_BIT_MASK) >> MOR_CLEAR_MEMORY_BIT_OFFSET)
+
+/**
+ Return the DisableAutoDetect bit value 0 or 1.
+
+ @param mor 1 byte value that contains ClearMemory and DisableAutoDetect bit.
+
+ @return DisableAutoDetect bit value
+**/
+#define MOR_DISABLE_AUTO_DETECT_VALUE(mor) (((UINT8)(mor) & MOR_DISABLEAUTODETECT_BIT_MASK) >> MOR_DISABLEAUTODETECT_BIT_OFFSET)
+
+extern EFI_GUID gEfiMemoryOverwriteControlDataGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Guid/Mps.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Guid/Mps.h
new file mode 100644
index 0000000000..5911f4efa9
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Guid/Mps.h
@@ -0,0 +1,29 @@
+/** @file
+ GUIDs used for MPS entries in the UEFI 2.0 system table
+ ACPI is the primary means of exporting MPS information to the OS. MPS only was
+ included to support Itanium-based platform power on. So don't use it if you don't have too.
+
+ Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Revision Reference:
+ GUIDs defined in UEFI 2.0 spec.
+
+**/
+
+#ifndef __MPS_GUID_H__
+#define __MPS_GUID_H__
+
+#define EFI_MPS_TABLE_GUID \
+ { \
+ 0xeb9d2d2f, 0x2d88, 0x11d3, {0x9a, 0x16, 0x0, 0x90, 0x27, 0x3f, 0xc1, 0x4d } \
+ }
+
+//
+// GUID name defined in spec.
+//
+#define MPS_TABLE_GUID EFI_MPS_TABLE_GUID
+
+extern EFI_GUID gEfiMpsTableGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Guid/PcAnsi.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Guid/PcAnsi.h
new file mode 100644
index 0000000000..867dfb4df1
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Guid/PcAnsi.h
@@ -0,0 +1,52 @@
+/** @file
+ Terminal Device Path Vendor Guid.
+
+ Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Revision Reference:
+ GUIDs defined in UEFI 2.0 spec.
+
+**/
+
+#ifndef __PC_ANSI_H__
+#define __PC_ANSI_H__
+
+#define EFI_PC_ANSI_GUID \
+ { \
+ 0xe0c14753, 0xf9be, 0x11d2, {0x9a, 0x0c, 0x00, 0x90, 0x27, 0x3f, 0xc1, 0x4d } \
+ }
+
+#define EFI_VT_100_GUID \
+ { \
+ 0xdfa66065, 0xb419, 0x11d3, {0x9a, 0x2d, 0x00, 0x90, 0x27, 0x3f, 0xc1, 0x4d } \
+ }
+
+#define EFI_VT_100_PLUS_GUID \
+ { \
+ 0x7baec70b, 0x57e0, 0x4c76, {0x8e, 0x87, 0x2f, 0x9e, 0x28, 0x08, 0x83, 0x43 } \
+ }
+
+#define EFI_VT_UTF8_GUID \
+ { \
+ 0xad15a0d6, 0x8bec, 0x4acf, {0xa0, 0x73, 0xd0, 0x1d, 0xe7, 0x7e, 0x2d, 0x88 } \
+ }
+
+#define DEVICE_PATH_MESSAGING_UART_FLOW_CONTROL \
+ { \
+ 0x37499a9d, 0x542f, 0x4c89, {0xa0, 0x26, 0x35, 0xda, 0x14, 0x20, 0x94, 0xe4 } \
+ }
+
+#define EFI_SAS_DEVICE_PATH_GUID \
+ { \
+ 0xd487ddb4, 0x008b, 0x11d9, {0xaf, 0xdc, 0x00, 0x10, 0x83, 0xff, 0xca, 0x4d } \
+ }
+
+extern EFI_GUID gEfiPcAnsiGuid;
+extern EFI_GUID gEfiVT100Guid;
+extern EFI_GUID gEfiVT100PlusGuid;
+extern EFI_GUID gEfiVTUTF8Guid;
+extern EFI_GUID gEfiUartDevicePathGuid;
+extern EFI_GUID gEfiSasDevicePathGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Guid/RtPropertiesTable.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Guid/RtPropertiesTable.h
new file mode 100644
index 0000000000..ee88d8f922
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Guid/RtPropertiesTable.h
@@ -0,0 +1,66 @@
+/** @file
+Guid & data structure for EFI_RT _PROPERTIES_TABLE, designed to be published by a
+platform if it no longer supports all EFI runtime services once ExitBootServices()
+has been called by the OS. Introduced in UEFI 2.8a.
+
+
+Copyright (c) 2020, American Megatrends International LLC. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __RT_PROPERTIES_TABLE_GUID_H__
+#define __RT_PROPERTIES_TABLE_GUID_H__
+
+//
+// Table, defined here, should be published by a platform if it no longer supports all EFI runtime
+// services once ExitBootServices() has been called by the OS. Note that this is merely a hint
+// to the OS, which it is free to ignore, and so the platform is still required to provide callable
+// implementations of unsupported runtime services that simply return EFI_UNSUPPORTED.
+//
+#define EFI_RT_PROPERTIES_TABLE_GUID \
+ { 0xeb66918a, 0x7eef, 0x402a, \
+ { 0x84, 0x2e, 0x93, 0x1d, 0x21, 0xc3, 0x8a, 0xe9 }}
+
+#pragma pack(1)
+
+typedef struct {
+ ///
+ /// Version of the structure, must be 0x1.
+ ///
+ UINT16 Version;
+
+ ///
+ /// Size in bytes of the entire EFI_RT_PROPERTIES_TABLE, must be 8.
+ ///
+ UINT16 Length;
+
+ ///
+ /// Bitmask of which calls are or are not supported, where a bit set to 1 indicates
+ /// that the call is supported, and 0 indicates that it is not.
+ ///
+ UINT32 RuntimeServicesSupported;
+} EFI_RT_PROPERTIES_TABLE;
+
+#pragma pack()
+
+#define EFI_RT_PROPERTIES_TABLE_VERSION 0x1
+
+#define EFI_RT_SUPPORTED_GET_TIME 0x0001
+#define EFI_RT_SUPPORTED_SET_TIME 0x0002
+#define EFI_RT_SUPPORTED_GET_WAKEUP_TIME 0x0004
+#define EFI_RT_SUPPORTED_SET_WAKEUP_TIME 0x0008
+#define EFI_RT_SUPPORTED_GET_VARIABLE 0x0010
+#define EFI_RT_SUPPORTED_GET_NEXT_VARIABLE_NAME 0x0020
+#define EFI_RT_SUPPORTED_SET_VARIABLE 0x0040
+#define EFI_RT_SUPPORTED_SET_VIRTUAL_ADDRESS_MAP 0x0080
+#define EFI_RT_SUPPORTED_CONVERT_POINTER 0x0100
+#define EFI_RT_SUPPORTED_GET_NEXT_HIGH_MONOTONIC_COUNT 0x0200
+#define EFI_RT_SUPPORTED_RESET_SYSTEM 0x0400
+#define EFI_RT_SUPPORTED_UPDATE_CAPSULE 0x0800
+#define EFI_RT_SUPPORTED_QUERY_CAPSULE_CAPABILITIES 0x1000
+#define EFI_RT_SUPPORTED_QUERY_VARIABLE_INFO 0x2000
+
+extern EFI_GUID gEfiRtPropertiesTableGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Guid/SmBios.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Guid/SmBios.h
new file mode 100644
index 0000000000..c01617a1a4
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Guid/SmBios.h
@@ -0,0 +1,32 @@
+/** @file
+ GUIDs used to locate the SMBIOS tables in the UEFI 2.5 system table.
+
+ These GUIDs in the system table are the only legal ways to search for and
+ locate the SMBIOS tables. Do not search the 0xF0000 segment to find SMBIOS
+ tables.
+
+ Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Revision Reference:
+ GUIDs defined in UEFI 2.5 spec.
+
+**/
+
+#ifndef __SMBIOS_GUID_H__
+#define __SMBIOS_GUID_H__
+
+#define SMBIOS_TABLE_GUID \
+ { \
+ 0xeb9d2d31, 0x2d88, 0x11d3, {0x9a, 0x16, 0x0, 0x90, 0x27, 0x3f, 0xc1, 0x4d } \
+ }
+
+#define SMBIOS3_TABLE_GUID \
+ { \
+ 0xf2fd1544, 0x9794, 0x4a2c, {0x99, 0x2e, 0xe5, 0xbb, 0xcf, 0x20, 0xe3, 0x94 } \
+ }
+
+extern EFI_GUID gEfiSmbiosTableGuid;
+extern EFI_GUID gEfiSmbios3TableGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Guid/SmramMemoryReserve.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Guid/SmramMemoryReserve.h
new file mode 100644
index 0000000000..4405280279
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Guid/SmramMemoryReserve.h
@@ -0,0 +1,44 @@
+/** @file
+ This is a special GUID extension Hob to describe SMRAM memory regions.
+
+ This file defines:
+ * the GUID used to identify the GUID HOB for reserving SMRAM regions.
+ * the data structure of SMRAM descriptor to describe SMRAM candidate regions
+ * values of state of SMRAM candidate regions
+ * the GUID specific data structure of HOB for reserving SMRAM regions.
+
+ Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Revision Reference:
+ GUIDs defined in PI SPEC version 1.5.
+
+**/
+
+#ifndef _SMRAM_MEMORY_RESERVE_H_
+#define _SMRAM_MEMORY_RESERVE_H_
+
+#define EFI_SMM_SMRAM_MEMORY_GUID \
+ { \
+ 0x6dadf1d1, 0xd4cc, 0x4910, {0xbb, 0x6e, 0x82, 0xb1, 0xfd, 0x80, 0xff, 0x3d } \
+ }
+
+/**
+* The GUID extension hob is to describe SMRAM memory regions supported by the platform.
+**/
+typedef struct {
+ ///
+ /// Designates the number of possible regions in the system
+ /// that can be usable for SMRAM.
+ ///
+ UINT32 NumberOfSmmReservedRegions;
+ ///
+ /// Used throughout this protocol to describe the candidate
+ /// regions for SMRAM that are supported by this platform.
+ ///
+ EFI_SMRAM_DESCRIPTOR Descriptor[1];
+} EFI_SMRAM_HOB_DESCRIPTOR_BLOCK;
+
+extern EFI_GUID gEfiSmmSmramMemoryGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Guid/StatusCodeDataTypeId.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Guid/StatusCodeDataTypeId.h
new file mode 100644
index 0000000000..0e6b119a00
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Guid/StatusCodeDataTypeId.h
@@ -0,0 +1,803 @@
+/** @file
+ GUID used to identify id for the caller who is initiating the Status Code.
+
+ Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Revision Reference:
+ These GUIDs and structures are defined in UEFI Platform Initialization Specification 1.2
+ Volume 3: Shared Architectural Elements
+
+**/
+
+#ifndef __PI_STATUS_CODE_DATA_TYPE_ID_GUID_H__
+#define __PI_STATUS_CODE_DATA_TYPE_ID_GUID_H__
+
+#include
+#include
+
+///
+/// Global ID for the EFI_STATUS_CODE_STRING structure
+///
+#define EFI_STATUS_CODE_DATA_TYPE_STRING_GUID \
+ { 0x92D11080, 0x496F, 0x4D95, { 0xBE, 0x7E, 0x03, 0x74, 0x88, 0x38, 0x2B, 0x0A } }
+
+typedef enum {
+ ///
+ /// A NULL-terminated ASCII string.
+ ///
+ EfiStringAscii,
+ ///
+ /// A double NULL-terminated Unicode string.
+ ///
+ EfiStringUnicode,
+ ///
+ /// An EFI_STATUS_CODE_STRING_TOKEN representing the string. The actual
+ /// string can be obtained by querying the HII Database
+ ///
+ EfiStringToken
+} EFI_STRING_TYPE;
+
+///
+/// Specifies the format of the data in EFI_STATUS_CODE_STRING_DATA.String.
+///
+typedef struct {
+ ///
+ /// The HII package list which contains the string. Handle is a dynamic value that may
+ /// not be the same for different boots. Type EFI_HII_HANDLE is defined in
+ /// EFI_HII_DATABASE_PROTOCOL.NewPackageList() in the UEFI Specification.
+ ///
+ EFI_HII_HANDLE Handle;
+ ///
+ /// When combined with Handle, the string token can be used to retrieve the string.
+ /// Type EFI_STRING_ID is defined in EFI_IFR_OP_HEADER in the UEFI Specification.
+ ///
+ EFI_STRING_ID Token;
+} EFI_STATUS_CODE_STRING_TOKEN;
+
+typedef union {
+ ///
+ /// ASCII formatted string.
+ ///
+ CHAR8 *Ascii;
+ ///
+ /// Unicode formatted string.
+ ///
+ CHAR16 *Unicode;
+ ///
+ /// HII handle/token pair.
+ ///
+ EFI_STATUS_CODE_STRING_TOKEN Hii;
+} EFI_STATUS_CODE_STRING;
+
+///
+/// This data type defines a string type of extended data. A string can accompany
+/// any status code. The string can provide additional information about the
+/// status code. The string can be ASCII, Unicode, or a Human Interface Infrastructure
+/// (HII) token/GUID pair.
+///
+typedef struct {
+ ///
+ /// The data header identifying the data. DataHeader.HeaderSize should be
+ /// sizeof (EFI_STATUS_CODE_DATA), DataHeader.Size should be
+ /// sizeof (EFI_STATUS_CODE_STRING_DATA) - HeaderSize, and
+ /// DataHeader.Type should be
+ /// EFI_STATUS_CODE_DATA_TYPE_STRING_GUID.
+ ///
+ EFI_STATUS_CODE_DATA DataHeader;
+ ///
+ /// Specifies the format of the data in String.
+ ///
+ EFI_STRING_TYPE StringType;
+ ///
+ /// A pointer to the extended data. The data follows the format specified by
+ /// StringType.
+ ///
+ EFI_STATUS_CODE_STRING String;
+} EFI_STATUS_CODE_STRING_DATA;
+
+extern EFI_GUID gEfiStatusCodeDataTypeStringGuid;
+
+///
+/// Global ID for the following structures:
+/// - EFI_DEVICE_PATH_EXTENDED_DATA
+/// - EFI_DEVICE_HANDLE_EXTENDED_DATA
+/// - EFI_RESOURCE_ALLOC_FAILURE_ERROR_DATA
+/// - EFI_COMPUTING_UNIT_VOLTAGE_ERROR_DATA
+/// - EFI_COMPUTING_UNIT_MICROCODE_UPDATE_ERROR_DATA
+/// - EFI_COMPUTING_UNIT_TIMER_EXPIRED_ERROR_DATA
+/// - EFI_HOST_PROCESSOR_MISMATCH_ERROR_DATA
+/// - EFI_MEMORY_RANGE_EXTENDED_DATA
+/// - EFI_DEBUG_ASSERT_DATA
+/// - EFI_STATUS_CODE_EXCEP_EXTENDED_DATA
+/// - EFI_STATUS_CODE_START_EXTENDED_DATA
+/// - EFI_LEGACY_OPROM_EXTENDED_DATA
+/// - EFI_RETURN_STATUS_EXTENDED_DATA
+///
+#define EFI_STATUS_CODE_SPECIFIC_DATA_GUID \
+ { 0x335984bd, 0xe805, 0x409a, { 0xb8, 0xf8, 0xd2, 0x7e, 0xce, 0x5f, 0xf7, 0xa6 } }
+
+///
+/// Extended data about the device path, which is used for many errors and
+/// progress codes to point to the device.
+///
+/// The device path is used to point to the physical device in case there is more than one device
+/// belonging to the same subclass. For example, the system may contain two USB keyboards and one
+/// PS/2* keyboard. The driver that parses the status code can use the device path extended data to
+/// differentiate between the three. The index field is not useful in this case because there is no standard
+/// numbering convention. Device paths are preferred over using device handles because device handles
+/// for a given device can change from one boot to another and do not mean anything beyond Boot
+/// Services time. In certain cases, the bus driver may not create a device handle for a given device if it
+/// detects a critical error. In these cases, the device path extended data can be used to refer to the
+/// device, but there may not be any device handles with an instance of
+/// EFI_DEVICE_PATH_PROTOCOL that matches DevicePath. The variable device path structure
+/// is included in this structure to make it self sufficient.
+///
+typedef struct {
+ ///
+ /// The data header identifying the data. DataHeader.HeaderSize should be
+ /// sizeof (EFI_STATUS_CODE_DATA). DataHeader.Size should be the size
+ /// of variable-length DevicePath, and DataHeader.Size is zero for a virtual
+ /// device that does not have a device path. DataHeader.Type should be
+ /// EFI_STATUS_CODE_SPECIFIC_DATA_GUID.
+ ///
+ EFI_STATUS_CODE_DATA DataHeader;
+ ///
+ /// The device path to the controller or the hardware device. Note that this parameter is a
+ /// variable-length device path structure and not a pointer to such a structure. This structure is
+ /// populated only if it is a physical device. For virtual devices, the Size field in DataHeader
+ /// is set to zero and this field is not populated.
+ ///
+ // EFI_DEVICE_PATH_PROTOCOL DevicePath;
+} EFI_DEVICE_PATH_EXTENDED_DATA;
+
+///
+/// Device handle Extended Data. Used for many
+/// errors and progress codes to point to the device.
+///
+/// The handle of the device with which the progress or error code is associated. The handle is
+/// guaranteed to be accurate only at the time the status code is reported. Handles are dynamic entities
+/// between boots, so handles cannot be considered to be valid if the system has reset subsequent to the
+/// status code being reported. Handles may be used to determine a wide variety of useful information
+/// about the source of the status code.
+///
+typedef struct {
+ ///
+ /// The data header identifying the data. DataHeader.HeaderSize should be
+ /// sizeof (EFI_STATUS_CODE_DATA), DataHeader.Size should be
+ /// sizeof (EFI_DEVICE_HANDLE_EXTENDED_DATA) - HeaderSize, and
+ /// DataHeader.Type should be EFI_STATUS_CODE_SPECIFIC_DATA_GUID.
+ ///
+ EFI_STATUS_CODE_DATA DataHeader;
+ ///
+ /// The device handle.
+ ///
+ EFI_HANDLE Handle;
+} EFI_DEVICE_HANDLE_EXTENDED_DATA;
+
+///
+/// This structure defines extended data describing a PCI resource allocation error.
+///
+/// @par Note:
+/// The following structure contains variable-length fields and cannot be defined as a C-style
+/// structure.
+///
+/// This extended data conveys details for a PCI resource allocation failure error. See the PCI
+/// specification and the ACPI specification for details on PCI resource allocations and the format for
+/// resource descriptors. This error does not detail why the resource allocation failed. It may be due to a
+/// bad resource request or a lack of available resources to satisfy a valid request. The variable device
+/// path structure and the resource structures are included in this structure to make it self sufficient.
+///
+typedef struct {
+ ///
+ /// The data header identifying the data. DataHeader.HeaderSize should be sizeof
+ /// (EFI_STATUS_CODE_DATA), DataHeader.Size should be
+ /// (DevicePathSize + DevicePathSize + DevicePathSize +
+ /// sizeof(UINT32) + 3 * sizeof (UINT16) ), and DataHeader.Type
+ /// should be EFI_STATUS_CODE_SPECIFIC_DATA_GUID.
+ ///
+ EFI_STATUS_CODE_DATA DataHeader;
+ ///
+ /// The PCI BAR. Applicable only for PCI devices. Ignored for all other devices.
+ ///
+ UINT32 Bar;
+ ///
+ /// DevicePathSize should be zero if it is a virtual device that is not associated with
+ /// a device path. Otherwise, this parameter is the length of the variable-length
+ /// DevicePath.
+ ///
+ UINT16 DevicePathSize;
+ ///
+ /// Represents the size the ReqRes parameter. ReqResSize should be zero if the
+ /// requested resources are not provided as a part of extended data.
+ ///
+ UINT16 ReqResSize;
+ ///
+ /// Represents the size the AllocRes parameter. AllocResSize should be zero if the
+ /// allocated resources are not provided as a part of extended data.
+ ///
+ UINT16 AllocResSize;
+ ///
+ /// The device path to the controller or the hardware device that did not get the requested
+ /// resources. Note that this parameter is the variable-length device path structure and not
+ /// a pointer to this structure.
+ ///
+ // EFI_DEVICE_PATH_PROTOCOL DevicePath;
+ ///
+ /// The requested resources in the format of an ACPI 2.0 resource descriptor. This
+ /// parameter is not a pointer; it is the complete resource descriptor.
+ ///
+ // UINT8 ReqRes[];
+ ///
+ /// The allocated resources in the format of an ACPI 2.0 resource descriptor. This
+ /// parameter is not a pointer; it is the complete resource descriptor.
+ ///
+ // UINT8 AllocRes[];
+} EFI_RESOURCE_ALLOC_FAILURE_ERROR_DATA;
+
+///
+/// This structure provides a calculation for base-10 representations.
+///
+/// Not consistent with PI 1.2 Specification.
+/// This data type is not defined in the PI 1.2 Specification, but is
+/// required by several of the other data structures in this file.
+///
+typedef struct {
+ ///
+ /// The INT16 number by which to multiply the base-2 representation.
+ ///
+ INT16 Value;
+ ///
+ /// The INT16 number by which to raise the base-2 calculation.
+ ///
+ INT16 Exponent;
+} EFI_EXP_BASE10_DATA;
+
+///
+/// This structure provides the voltage at the time of error. It also provides
+/// the threshold value indicating the minimum or maximum voltage that is considered
+/// an error. If the voltage is less then the threshold, the error indicates that the
+/// voltage fell below the minimum acceptable value. If the voltage is greater then the threshold,
+/// the error indicates that the voltage rose above the maximum acceptable value.
+///
+typedef struct {
+ ///
+ /// The data header identifying the data. DataHeader.HeaderSize should be
+ /// sizeof (EFI_STATUS_CODE_DATA), DataHeader.Size should be
+ /// sizeof (EFI_COMPUTING_UNIT_VOLTAGE_ERROR_DATA) -
+ /// HeaderSize, and DataHeader.Type should be
+ /// EFI_STATUS_CODE_SPECIFIC_DATA_GUID.
+ ///
+ EFI_STATUS_CODE_DATA DataHeader;
+ ///
+ /// The voltage value at the time of the error.
+ ///
+ EFI_EXP_BASE10_DATA Voltage;
+ ///
+ /// The voltage threshold.
+ ///
+ EFI_EXP_BASE10_DATA Threshold;
+} EFI_COMPUTING_UNIT_VOLTAGE_ERROR_DATA;
+
+///
+/// Microcode Update Extended Error Data
+///
+typedef struct {
+ ///
+ /// The data header identifying the data. DataHeader.HeaderSize should be
+ /// sizeof (EFI_STATUS_CODE_DATA), DataHeader.Size should be
+ /// sizeof (EFI_COMPUTING_UNIT_MICROCODE_UPDATE_ERROR_DATA) -
+ /// HeaderSize, and DataHeader.Type should be
+ /// EFI_STATUS_CODE_SPECIFIC_DATA_GUID.
+ ///
+ EFI_STATUS_CODE_DATA DataHeader;
+ ///
+ /// The version of the microcode update from the header.
+ ///
+ UINT32 Version;
+} EFI_COMPUTING_UNIT_MICROCODE_UPDATE_ERROR_DATA;
+
+///
+/// This structure provides details about the computing unit timer expiration error.
+/// The timer limit provides the timeout value of the timer prior to expiration.
+///
+typedef struct {
+ ///
+ /// The data header identifying the data. DataHeader.HeaderSize should be
+ /// sizeof (EFI_STATUS_CODE_DATA), DataHeader.Size should be
+ /// sizeof (EFI_COMPUTING_UNIT_TIMER_EXPIRED_ERROR_DATA) -
+ /// HeaderSize, and DataHeader.Type should be
+ /// EFI_STATUS_CODE_SPECIFIC_DATA_GUID.
+ ///
+ EFI_STATUS_CODE_DATA DataHeader;
+ ///
+ /// The number of seconds that the computing unit timer was configured to expire.
+ ///
+ EFI_EXP_BASE10_DATA TimerLimit;
+} EFI_COMPUTING_UNIT_TIMER_EXPIRED_ERROR_DATA;
+
+///
+/// Attribute bits for EFI_HOST_PROCESSOR_MISMATCH_ERROR_DATA.Attributes
+/// All other attributes are reserved for future use and must be initialized to 0.
+///
+///@{
+#define EFI_COMPUTING_UNIT_MISMATCH_SPEED 0x0001
+#define EFI_COMPUTING_UNIT_MISMATCH_FSB_SPEED 0x0002
+#define EFI_COMPUTING_UNIT_MISMATCH_FAMILY 0x0004
+#define EFI_COMPUTING_UNIT_MISMATCH_MODEL 0x0008
+#define EFI_COMPUTING_UNIT_MISMATCH_STEPPING 0x0010
+#define EFI_COMPUTING_UNIT_MISMATCH_CACHE_SIZE 0x0020
+#define EFI_COMPUTING_UNIT_MISMATCH_OEM1 0x1000
+#define EFI_COMPUTING_UNIT_MISMATCH_OEM2 0x2000
+#define EFI_COMPUTING_UNIT_MISMATCH_OEM3 0x4000
+#define EFI_COMPUTING_UNIT_MISMATCH_OEM4 0x8000
+///@}
+
+///
+/// This structure defines extended data for processor mismatch errors.
+///
+/// This provides information to indicate which processors mismatch, and how they mismatch. The
+/// status code contains the instance number of the processor that is in error. This structure's
+/// Instance indicates the second processor that does not match. This differentiation allows the
+/// consumer to determine which two processors do not match. The Attributes indicate what
+/// mismatch is being reported. Because Attributes is a bit field, more than one mismatch can be
+/// reported with one error code.
+///
+typedef struct {
+ ///
+ /// The data header identifying the data. DataHeader.HeaderSize should be
+ /// sizeof (EFI_STATUS_CODE_DATA), DataHeader.Size should be
+ /// sizeof (EFI_ HOST_PROCESSOR_MISMATCH_ERROR_DATA) -
+ /// HeaderSize , and DataHeader.Type should be
+ /// EFI_STATUS_CODE_SPECIFIC_DATA_GUID.
+ ///
+ EFI_STATUS_CODE_DATA DataHeader;
+ ///
+ /// The unit number of the computing unit that does not match.
+ ///
+ UINT32 Instance;
+ ///
+ /// The attributes describing the failure.
+ ///
+ UINT16 Attributes;
+} EFI_HOST_PROCESSOR_MISMATCH_ERROR_DATA;
+
+///
+/// This structure provides details about the computing unit thermal failure.
+///
+/// This structure provides the temperature at the time of error. It also provides the threshold value
+/// indicating the minimum temperature that is considered an error.
+///
+typedef struct {
+ ///
+ /// The data header identifying the data. DataHeader.HeaderSize should be
+ /// sizeof (EFI_STATUS_CODE_DATA), DataHeader.Size should be
+ /// sizeof (EFI_COMPUTING_UNIT_THERMAL_ERROR_DATA) -
+ /// HeaderSize , and DataHeader.Type should be
+ /// EFI_STATUS_CODE_SPECIFIC_DATA_GUID.
+ ///
+ EFI_STATUS_CODE_DATA DataHeader;
+ ///
+ /// The thermal value at the time of the error.
+ ///
+ EFI_EXP_BASE10_DATA Temperature;
+ ///
+ /// The thermal threshold.
+ ///
+ EFI_EXP_BASE10_DATA Threshold;
+} EFI_COMPUTING_UNIT_THERMAL_ERROR_DATA;
+
+///
+/// Enumeration of valid cache types
+///
+typedef enum {
+ EfiInitCacheDataOnly,
+ EfiInitCacheInstrOnly,
+ EfiInitCacheBoth,
+ EfiInitCacheUnspecified
+} EFI_INIT_CACHE_TYPE;
+
+///
+/// Embedded cache init extended data
+///
+typedef struct {
+ ///
+ /// The data header identifying the data. DataHeader.HeaderSize should be
+ /// sizeof (EFI_STATUS_CODE_DATA), DataHeader.Size should be
+ /// sizeof (EFI_CACHE_INIT_DATA) - HeaderSize , and
+ /// DataHeader.Type should be EFI_STATUS_CODE_SPECIFIC_DATA_GUID.
+ ///
+ EFI_STATUS_CODE_DATA DataHeader;
+ ///
+ /// The cache level. Starts with 1 for level 1 cache.
+ ///
+ UINT32 Level;
+ ///
+ /// The type of cache.
+ ///
+ EFI_INIT_CACHE_TYPE Type;
+} EFI_CACHE_INIT_DATA;
+
+///
+///
+///
+typedef UINT32 EFI_CPU_STATE_CHANGE_CAUSE;
+
+///
+/// The reasons that the processor is disabled.
+/// Used to fill in EFI_COMPUTING_UNIT_CPU_DISABLED_ERROR_DATA.Cause.
+///
+///@{
+#define EFI_CPU_CAUSE_INTERNAL_ERROR 0x0001
+#define EFI_CPU_CAUSE_THERMAL_ERROR 0x0002
+#define EFI_CPU_CAUSE_SELFTEST_FAILURE 0x0004
+#define EFI_CPU_CAUSE_PREBOOT_TIMEOUT 0x0008
+#define EFI_CPU_CAUSE_FAILED_TO_START 0x0010
+#define EFI_CPU_CAUSE_CONFIG_ERROR 0x0020
+#define EFI_CPU_CAUSE_USER_SELECTION 0x0080
+#define EFI_CPU_CAUSE_BY_ASSOCIATION 0x0100
+#define EFI_CPU_CAUSE_UNSPECIFIED 0x8000
+///@}
+
+///
+/// This structure provides information about the disabled computing unit.
+///
+/// This structure provides details as to why and how the computing unit was disabled. The causes
+/// should cover the typical reasons a processor would be disabled. How the processor was disabled is
+/// important because there are distinct differences between hardware and software disabling.
+///
+typedef struct {
+ ///
+ /// The data header identifying the data. DataHeader.HeaderSize should be
+ /// sizeof (EFI_STATUS_CODE_DATA), DataHeader.Size should be
+ /// sizeof (EFI_COMPUTING_UNIT_CPU_DISABLED_ERROR_DATA) -
+ /// HeaderSize, and DataHeader.Type should be
+ /// EFI_STATUS_CODE_SPECIFIC_DATA_GUID.
+ ///
+ EFI_STATUS_CODE_DATA DataHeader;
+ ///
+ /// The reason for disabling the processor.
+ ///
+ UINT32 Cause;
+ ///
+ /// TRUE if the processor is disabled via software means such as not listing it in the ACPI tables.
+ /// Such a processor will respond to Interprocessor Interrupts (IPIs). FALSE if the processor is hardware
+ /// disabled, which means it is invisible to software and will not respond to IPIs.
+ ///
+ BOOLEAN SoftwareDisabled;
+} EFI_COMPUTING_UNIT_CPU_DISABLED_ERROR_DATA;
+
+///
+/// Memory Error Granularity Definition
+///
+typedef UINT8 EFI_MEMORY_ERROR_GRANULARITY;
+
+///
+/// Memory Error Granularities. Used to fill in EFI_MEMORY_EXTENDED_ERROR_DATA.Granularity.
+///
+///@{
+#define EFI_MEMORY_ERROR_OTHER 0x01
+#define EFI_MEMORY_ERROR_UNKNOWN 0x02
+#define EFI_MEMORY_ERROR_DEVICE 0x03
+#define EFI_MEMORY_ERROR_PARTITION 0x04
+///@}
+
+///
+/// Memory Error Operation Definition
+///
+typedef UINT8 EFI_MEMORY_ERROR_OPERATION;
+
+///
+/// Memory Error Operations. Used to fill in EFI_MEMORY_EXTENDED_ERROR_DATA.Operation.
+///
+///@{
+#define EFI_MEMORY_OPERATION_OTHER 0x01
+#define EFI_MEMORY_OPERATION_UNKNOWN 0x02
+#define EFI_MEMORY_OPERATION_READ 0x03
+#define EFI_MEMORY_OPERATION_WRITE 0x04
+#define EFI_MEMORY_OPERATION_PARTIAL_WRITE 0x05
+///@}
+
+///
+/// This structure provides specific details about the memory error that was detected. It provides
+/// enough information so that consumers can identify the exact failure and provides enough
+/// information to enable corrective action if necessary.
+///
+typedef struct {
+ ///
+ /// The data header identifying the data. DataHeader.HeaderSize should be
+ /// sizeof (EFI_STATUS_CODE_DATA), DataHeader.Size should be
+ /// sizeof (EFI_MEMORY_EXTENDED_ERROR_DATA) - HeaderSize, and
+ /// DataHeader.Type should be EFI_STATUS_CODE_SPECIFIC_DATA_GUID.
+ ///
+ EFI_STATUS_CODE_DATA DataHeader;
+ ///
+ /// The error granularity type.
+ ///
+ EFI_MEMORY_ERROR_GRANULARITY Granularity;
+ ///
+ /// The operation that resulted in the error being detected.
+ ///
+ EFI_MEMORY_ERROR_OPERATION Operation;
+ ///
+ /// The error syndrome, vendor-specific ECC syndrome, or CRC data associated with
+ /// the error. If unknown, should be initialized to 0.
+ /// Inconsistent with specification here:
+ /// This field in StatusCodes spec0.9 is defined as UINT32, keep code unchanged.
+ ///
+ UINTN Syndrome;
+ ///
+ /// The physical address of the error.
+ ///
+ EFI_PHYSICAL_ADDRESS Address;
+ ///
+ /// The range, in bytes, within which the error address can be determined.
+ ///
+ UINTN Resolution;
+} EFI_MEMORY_EXTENDED_ERROR_DATA;
+
+///
+/// A definition to describe that the operation is performed on multiple devices within the array.
+/// May be used for EFI_STATUS_CODE_DIMM_NUMBER.Array and EFI_STATUS_CODE_DIMM_NUMBER.Device.
+///
+#define EFI_MULTIPLE_MEMORY_DEVICE_OPERATION 0xfffe
+
+///
+/// A definition to describe that the operation is performed on all devices within the array.
+/// May be used for EFI_STATUS_CODE_DIMM_NUMBER.Array and EFI_STATUS_CODE_DIMM_NUMBER.Device.
+///
+#define EFI_ALL_MEMORY_DEVICE_OPERATION 0xffff
+
+///
+/// A definition to describe that the operation is performed on multiple arrays.
+/// May be used for EFI_STATUS_CODE_DIMM_NUMBER.Array and EFI_STATUS_CODE_DIMM_NUMBER.Device.
+///
+#define EFI_MULTIPLE_MEMORY_ARRAY_OPERATION 0xfffe
+
+///
+/// A definition to describe that the operation is performed on all the arrays.
+/// May be used for EFI_STATUS_CODE_DIMM_NUMBER.Array and EFI_STATUS_CODE_DIMM_NUMBER.Device.
+///
+#define EFI_ALL_MEMORY_ARRAY_OPERATION 0xffff
+
+///
+/// This extended data provides some context that consumers can use to locate a DIMM within the
+/// overall memory scheme.
+///
+/// This extended data provides some context that consumers can use to locate a DIMM within the
+/// overall memory scheme. The Array and Device numbers may indicate a specific DIMM, or they
+/// may be populated with the group definitions in "Related Definitions" below.
+///
+typedef struct {
+ ///
+ /// The data header identifying the data. DataHeader.HeaderSize should be
+ /// sizeof (EFI_STATUS_CODE_DATA), DataHeader.Size should be
+ /// sizeof (EFI_STATUS_CODE_DIMM_NUMBER) - HeaderSize, and
+ /// DataHeader.Type should be EFI_STATUS_CODE_SPECIFIC_DATA_GUID.
+ ///
+ EFI_STATUS_CODE_DATA DataHeader;
+ ///
+ /// The memory array number.
+ ///
+ UINT16 Array;
+ ///
+ /// The device number within that Array.
+ ///
+ UINT16 Device;
+} EFI_STATUS_CODE_DIMM_NUMBER;
+
+///
+/// This structure defines extended data describing memory modules that do not match.
+///
+/// This extended data may be used to convey the specifics of memory modules that do not match.
+///
+typedef struct {
+ ///
+ /// The data header identifying the data. DataHeader.HeaderSize should be
+ /// sizeof (EFI_STATUS_CODE_DATA), DataHeader.Size should be
+ /// sizeof (EFI_MEMORY_MODULE_MISMATCH_ERROR_DATA) -
+ /// HeaderSize, and DataHeader.Type should be
+ /// EFI_STATUS_CODE_SPECIFIC_DATA_GUID.
+ ///
+ EFI_STATUS_CODE_DATA DataHeader;
+ ///
+ /// The instance number of the memory module that does not match.
+ ///
+ EFI_STATUS_CODE_DIMM_NUMBER Instance;
+} EFI_MEMORY_MODULE_MISMATCH_ERROR_DATA;
+
+///
+/// This structure defines extended data describing a memory range.
+///
+/// This extended data may be used to convey the specifics of a memory range. Ranges are specified
+/// with a start address and a length.
+///
+typedef struct {
+ ///
+ /// The data header identifying the data. DataHeader.HeaderSize should be
+ /// sizeof (EFI_STATUS_CODE_DATA), DataHeader.Size should be
+ /// sizeof (EFI_MEMORY_RANGE_EXTENDED_DATA) - HeaderSize, and
+ /// DataHeader.Type should be EFI_STATUS_CODE_SPECIFIC_DATA_GUID.
+ ///
+ EFI_STATUS_CODE_DATA DataHeader;
+ ///
+ /// The starting address of the memory range.
+ ///
+ EFI_PHYSICAL_ADDRESS Start;
+ ///
+ /// The length in bytes of the memory range.
+ ///
+ EFI_PHYSICAL_ADDRESS Length;
+} EFI_MEMORY_RANGE_EXTENDED_DATA;
+
+///
+/// This structure provides the assert information that is typically associated with a debug assertion failing.
+///
+/// The data indicates the location of the assertion that failed in the source code. This information
+/// includes the file name and line number that are necessary to find the failing assertion in source code.
+///
+typedef struct {
+ ///
+ /// The data header identifying the data. DataHeader.HeaderSize should be
+ /// sizeof (EFI_STATUS_CODE_DATA), DataHeader.Size should be
+ /// sizeof (EFI_DEBUG_ASSERT_DATA) - HeaderSize , and
+ /// DataHeader.Type should be EFI_STATUS_CODE_SPECIFIC_DATA_GUID.
+ ///
+ EFI_STATUS_CODE_DATA DataHeader;
+ ///
+ /// The line number of the source file where the fault was generated.
+ ///
+ UINT32 LineNumber;
+ ///
+ /// The size in bytes of FileName.
+ ///
+ UINT32 FileNameSize;
+ ///
+ /// A pointer to a NULL-terminated ASCII or Unicode string that represents
+ /// the file name of the source file where the fault was generated.
+ ///
+ EFI_STATUS_CODE_STRING_DATA *FileName;
+} EFI_DEBUG_ASSERT_DATA;
+
+///
+/// System Context Data EBC/IA32/IPF
+///
+typedef union {
+ ///
+ /// The context of the EBC virtual machine when the exception was generated. Type
+ /// EFI_SYSTEM_CONTEXT_EBC is defined in EFI_DEBUG_SUPPORT_PROTOCOL
+ /// in the UEFI Specification.
+ ///
+ EFI_SYSTEM_CONTEXT_EBC SystemContextEbc;
+ ///
+ /// The context of the IA-32 processor when the exception was generated. Type
+ /// EFI_SYSTEM_CONTEXT_IA32 is defined in the
+ /// EFI_DEBUG_SUPPORT_PROTOCOL in the UEFI Specification.
+ ///
+ EFI_SYSTEM_CONTEXT_IA32 SystemContextIa32;
+ ///
+ /// The context of the Itanium(R) processor when the exception was generated. Type
+ /// EFI_SYSTEM_CONTEXT_IPF is defined in the
+ /// EFI_DEBUG_SUPPORT_PROTOCOL in the UEFI Specification.
+ ///
+ EFI_SYSTEM_CONTEXT_IPF SystemContextIpf;
+ ///
+ /// The context of the X64 processor when the exception was generated. Type
+ /// EFI_SYSTEM_CONTEXT_X64 is defined in the
+ /// EFI_DEBUG_SUPPORT_PROTOCOL in the UEFI Specification.
+ ///
+ EFI_SYSTEM_CONTEXT_X64 SystemContextX64;
+ ///
+ /// The context of the ARM processor when the exception was generated. Type
+ /// EFI_SYSTEM_CONTEXT_ARM is defined in the
+ /// EFI_DEBUG_SUPPORT_PROTOCOL in the UEFI Specification.
+ ///
+ EFI_SYSTEM_CONTEXT_ARM SystemContextArm;
+} EFI_STATUS_CODE_EXCEP_SYSTEM_CONTEXT;
+
+///
+/// This structure defines extended data describing a processor exception error.
+///
+/// This extended data allows the processor context that is present at the time of the exception to be
+/// reported with the exception. The format and contents of the context data varies depending on the
+/// processor architecture.
+///
+typedef struct {
+ ///
+ /// The data header identifying the data. DataHeader.HeaderSize should be
+ /// sizeof (EFI_STATUS_CODE_DATA), DataHeader.Size should be
+ /// sizeof (EFI_STATUS_CODE_EXCEP_EXTENDED_DATA) - HeaderSize,
+ /// and DataHeader.Type should be
+ /// EFI_STATUS_CODE_SPECIFIC_DATA_GUID.
+ ///
+ EFI_STATUS_CODE_DATA DataHeader;
+ ///
+ /// The system context.
+ ///
+ EFI_STATUS_CODE_EXCEP_SYSTEM_CONTEXT Context;
+} EFI_STATUS_CODE_EXCEP_EXTENDED_DATA;
+
+///
+/// This structure defines extended data describing a call to a driver binding protocol start function.
+///
+/// This extended data records information about a Start() function call. Start() is a member of
+/// the UEFI Driver Binding Protocol.
+///
+typedef struct {
+ ///
+ /// The data header identifying the data. DataHeader.HeaderSize should be
+ /// sizeof (EFI_STATUS_CODE_DATA), DataHeader.Size should be
+ /// sizeof (EFI_STATUS_CODE_START_EXTENDED_DATA) - HeaderSize,
+ /// and DataHeader.Type should be
+ /// EFI_STATUS_CODE_SPECIFIC_DATA_GUID.
+ ///
+ EFI_STATUS_CODE_DATA DataHeader;
+ ///
+ /// The controller handle.
+ ///
+ EFI_HANDLE ControllerHandle;
+ ///
+ /// The driver binding handle.
+ ///
+ EFI_HANDLE DriverBindingHandle;
+ ///
+ /// The size of the RemainingDevicePath. It is zero if the Start() function is
+ /// called with RemainingDevicePath = NULL. The UEFI Specification allows
+ /// that the Start() function of bus drivers can be called in this way.
+ ///
+ UINT16 DevicePathSize;
+ ///
+ /// Matches the RemainingDevicePath parameter being passed to the Start() function.
+ /// Note that this parameter is the variable-length device path and not a pointer
+ /// to the device path.
+ ///
+ // EFI_DEVICE_PATH_PROTOCOL RemainingDevicePath;
+} EFI_STATUS_CODE_START_EXTENDED_DATA;
+
+///
+/// This structure defines extended data describing a legacy option ROM (OpROM).
+///
+/// The device handle and ROM image base can be used by consumers to determine which option ROM
+/// failed. Due to the black-box nature of legacy option ROMs, the amount of information that can be
+/// obtained may be limited.
+///
+typedef struct {
+ ///
+ /// The data header identifying the data. DataHeader.HeaderSize should be
+ /// sizeof (EFI_STATUS_CODE_DATA), DataHeader.Size should be
+ /// sizeof (EFI_LEGACY_OPROM_EXTENDED_DATA) - HeaderSize, and
+ /// DataHeader.Type should be EFI_STATUS_CODE_SPECIFIC_DATA_GUID.
+ ///
+ EFI_STATUS_CODE_DATA DataHeader;
+ ///
+ /// The handle corresponding to the device that this legacy option ROM is being invoked.
+ ///
+ EFI_HANDLE DeviceHandle;
+ ///
+ /// The base address of the shadowed legacy ROM image. May or may not point to the shadow RAM area.
+ ///
+ EFI_PHYSICAL_ADDRESS RomImageBase;
+} EFI_LEGACY_OPROM_EXTENDED_DATA;
+
+///
+/// This structure defines extended data describing an EFI_STATUS return value that stands for a
+/// failed function call (such as a UEFI boot service).
+///
+typedef struct {
+ ///
+ /// The data header identifying the data:
+ /// DataHeader.HeaderSize should be sizeof(EFI_STATUS_CODE_DATA),
+ /// DataHeader.Size should be sizeof(EFI_RETURN_STATUS_EXTENDED_DATA) - HeaderSize,
+ /// DataHeader.Type should be EFI_STATUS_CODE_SPECIFIC_DATA_GUID.
+ ///
+ EFI_STATUS_CODE_DATA DataHeader;
+ ///
+ /// The EFI_STATUS return value of the service or function whose failure triggered the
+ /// reporting of the status code (generally an error code or a debug code).
+ ///
+ EFI_STATUS ReturnStatus;
+} EFI_RETURN_STATUS_EXTENDED_DATA;
+
+extern EFI_GUID gEfiStatusCodeSpecificDataGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Guid/SystemResourceTable.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Guid/SystemResourceTable.h
new file mode 100644
index 0000000000..461066600c
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Guid/SystemResourceTable.h
@@ -0,0 +1,132 @@
+/** @file
+ Guid & data structure used for EFI System Resource Table (ESRT)
+
+ Copyright (c) 2015 - 2020, Intel Corporation. All rights reserved.
+ Copyright (c) Microsoft Corporation.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Revision Reference:
+ GUIDs defined in UEFI 2.5 spec.
+
+**/
+
+#ifndef _SYSTEM_RESOURCE_TABLE_H__
+#define _SYSTEM_RESOURCE_TABLE_H__
+
+#define EFI_SYSTEM_RESOURCE_TABLE_GUID \
+ { \
+ 0xb122a263, 0x3661, 0x4f68, {0x99, 0x29, 0x78, 0xf8, 0xb0, 0xd6, 0x21, 0x80 } \
+ }
+
+///
+/// Current Entry Version
+///
+#define EFI_SYSTEM_RESOURCE_TABLE_FIRMWARE_RESOURCE_VERSION 1
+
+///
+/// Firmware Type Definitions
+///
+#define ESRT_FW_TYPE_UNKNOWN 0x00000000
+#define ESRT_FW_TYPE_SYSTEMFIRMWARE 0x00000001
+#define ESRT_FW_TYPE_DEVICEFIRMWARE 0x00000002
+#define ESRT_FW_TYPE_UEFIDRIVER 0x00000003
+
+///
+/// Last Attempt Status Values
+///
+#define LAST_ATTEMPT_STATUS_SUCCESS 0x00000000
+#define LAST_ATTEMPT_STATUS_ERROR_UNSUCCESSFUL 0x00000001
+#define LAST_ATTEMPT_STATUS_ERROR_INSUFFICIENT_RESOURCES 0x00000002
+#define LAST_ATTEMPT_STATUS_ERROR_INCORRECT_VERSION 0x00000003
+#define LAST_ATTEMPT_STATUS_ERROR_INVALID_FORMAT 0x00000004
+#define LAST_ATTEMPT_STATUS_ERROR_AUTH_ERROR 0x00000005
+#define LAST_ATTEMPT_STATUS_ERROR_PWR_EVT_AC 0x00000006
+#define LAST_ATTEMPT_STATUS_ERROR_PWR_EVT_BATT 0x00000007
+#define LAST_ATTEMPT_STATUS_ERROR_UNSATISFIED_DEPENDENCIES 0x00000008
+
+///
+/// LAST_ATTEMPT_STATUS_ERROR_UNSUCCESSFUL_VENDOR_RANGE_MAX is defined as
+/// 0x4000 as of UEFI Specification 2.8B. This will be modified in the
+/// future to the correct value 0x3FFF. To ensure correct implementation,
+/// this change is preemptively made in the value defined below.
+///
+/// When the UEFI Specification is updated, this comment block can be
+/// removed.
+///
+#define LAST_ATTEMPT_STATUS_ERROR_UNSUCCESSFUL_VENDOR_RANGE_MIN 0x00001000
+#define LAST_ATTEMPT_STATUS_ERROR_UNSUCCESSFUL_VENDOR_RANGE_MAX 0x00003FFF
+
+typedef struct {
+ ///
+ /// The firmware class field contains a GUID that identifies a firmware component
+ /// that can be updated via UpdateCapsule(). This GUID must be unique within all
+ /// entries of the ESRT.
+ ///
+ EFI_GUID FwClass;
+ ///
+ /// Identifies the type of firmware resource.
+ ///
+ UINT32 FwType;
+ ///
+ /// The firmware version field represents the current version of the firmware
+ /// resource, value must always increase as a larger number represents a newer
+ /// version.
+ ///
+ UINT32 FwVersion;
+ ///
+ /// The lowest firmware resource version to which a firmware resource can be
+ /// rolled back for the given system/device. Generally this is used to protect
+ /// against known and fixed security issues.
+ ///
+ UINT32 LowestSupportedFwVersion;
+ ///
+ /// The capsule flags field contains the CapsuleGuid flags (bits 0- 15) as defined
+ /// in the EFI_CAPSULE_HEADER that will be set in the capsule header.
+ ///
+ UINT32 CapsuleFlags;
+ ///
+ /// The last attempt version field describes the last firmware version for which
+ /// an update was attempted (uses the same format as Firmware Version).
+ /// Last Attempt Version is updated each time an UpdateCapsule() is attempted for
+ /// an ESRT entry and is preserved across reboots (non-volatile). However, in
+ /// cases where the attempt version is not recorded due to limitations in the
+ /// update process, the field shall set to zero after a failed update. Similarly,
+ /// in the case of a removable device, this value is set to 0 in cases where the
+ /// device has not been updated since being added to the system.
+ ///
+ UINT32 LastAttemptVersion;
+ ///
+ /// The last attempt status field describes the result of the last firmware update
+ /// attempt for the firmware resource entry.
+ /// LastAttemptStatus is updated each time an UpdateCapsule() is attempted for an
+ /// ESRT entry and is preserved across reboots (non-volatile).
+ /// If a firmware update has never been attempted or is unknown, for example after
+ /// fresh insertion of a removable device, LastAttemptStatus must be set to Success.
+ ///
+ UINT32 LastAttemptStatus;
+} EFI_SYSTEM_RESOURCE_ENTRY;
+
+typedef struct {
+ ///
+ /// The number of firmware resources in the table, must not be zero.
+ ///
+ UINT32 FwResourceCount;
+ ///
+ /// The maximum number of resource array entries that can be within the table
+ /// without reallocating the table, must not be zero.
+ ///
+ UINT32 FwResourceCountMax;
+ ///
+ /// The version of the EFI_SYSTEM_RESOURCE_ENTRY entities used in this table.
+ /// This field should be set to 1.
+ ///
+ UINT64 FwResourceVersion;
+ ///
+ /// Array of EFI_SYSTEM_RESOURCE_ENTRY
+ ///
+ // EFI_SYSTEM_RESOURCE_ENTRY Entries[];
+} EFI_SYSTEM_RESOURCE_TABLE;
+
+extern EFI_GUID gEfiSystemResourceTableGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Guid/VectorHandoffTable.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Guid/VectorHandoffTable.h
new file mode 100644
index 0000000000..9c3bbbf536
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Guid/VectorHandoffTable.h
@@ -0,0 +1,27 @@
+/** @file
+ GUID for system configuration table entry that points to the table
+ in case an entity in DXE wishes to update/change the vector table contents.
+
+ Copyright (c) 2013 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Revision Reference:
+ GUID defined in PI 1.2.1 spec.
+**/
+
+#ifndef __EFI_VECTOR_HANDOFF_TABLE_H__
+#define __EFI_VECTOR_HANDOFF_TABLE_H__
+
+#include
+
+//
+// System configuration table entry that points to the table
+// in case an entity in DXE wishes to update/change the vector
+// table contents.
+//
+#define EFI_VECTOR_HANDOF_TABLE_GUID \
+ { 0x996ec11c, 0x5397, 0x4e73, { 0xb5, 0x8f, 0x82, 0x7e, 0x52, 0x90, 0x6d, 0xef }}
+
+extern EFI_GUID gEfiVectorHandoffTableGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Guid/WinCertificate.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Guid/WinCertificate.h
new file mode 100644
index 0000000000..72d766d22d
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Guid/WinCertificate.h
@@ -0,0 +1,120 @@
+/** @file
+ GUID for UEFI WIN_CERTIFICATE structure.
+
+ Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Revision Reference:
+ GUID defined in UEFI 2.0 spec.
+**/
+
+#ifndef __EFI_WIN_CERTIFICATE_H__
+#define __EFI_WIN_CERTIFICATE_H__
+
+//
+// _WIN_CERTIFICATE.wCertificateType
+//
+#define WIN_CERT_TYPE_PKCS_SIGNED_DATA 0x0002
+#define WIN_CERT_TYPE_EFI_PKCS115 0x0EF0
+#define WIN_CERT_TYPE_EFI_GUID 0x0EF1
+
+///
+/// The WIN_CERTIFICATE structure is part of the PE/COFF specification.
+///
+typedef struct {
+ ///
+ /// The length of the entire certificate,
+ /// including the length of the header, in bytes.
+ ///
+ UINT32 dwLength;
+ ///
+ /// The revision level of the WIN_CERTIFICATE
+ /// structure. The current revision level is 0x0200.
+ ///
+ UINT16 wRevision;
+ ///
+ /// The certificate type. See WIN_CERT_TYPE_xxx for the UEFI
+ /// certificate types. The UEFI specification reserves the range of
+ /// certificate type values from 0x0EF0 to 0x0EFF.
+ ///
+ UINT16 wCertificateType;
+ ///
+ /// The following is the actual certificate. The format of
+ /// the certificate depends on wCertificateType.
+ ///
+ /// UINT8 bCertificate[ANYSIZE_ARRAY];
+ ///
+} WIN_CERTIFICATE;
+
+///
+/// WIN_CERTIFICATE_UEFI_GUID.CertType
+///
+#define EFI_CERT_TYPE_RSA2048_SHA256_GUID \
+ {0xa7717414, 0xc616, 0x4977, {0x94, 0x20, 0x84, 0x47, 0x12, 0xa7, 0x35, 0xbf } }
+
+///
+/// WIN_CERTIFICATE_UEFI_GUID.CertData
+///
+typedef struct {
+ EFI_GUID HashType;
+ UINT8 PublicKey[256];
+ UINT8 Signature[256];
+} EFI_CERT_BLOCK_RSA_2048_SHA256;
+
+///
+/// Certificate which encapsulates a GUID-specific digital signature
+///
+typedef struct {
+ ///
+ /// This is the standard WIN_CERTIFICATE header, where
+ /// wCertificateType is set to WIN_CERT_TYPE_EFI_GUID.
+ ///
+ WIN_CERTIFICATE Hdr;
+ ///
+ /// This is the unique id which determines the
+ /// format of the CertData. .
+ ///
+ EFI_GUID CertType;
+ ///
+ /// The following is the certificate data. The format of
+ /// the data is determined by the CertType.
+ /// If CertType is EFI_CERT_TYPE_RSA2048_SHA256_GUID,
+ /// the CertData will be EFI_CERT_BLOCK_RSA_2048_SHA256 structure.
+ ///
+ UINT8 CertData[1];
+} WIN_CERTIFICATE_UEFI_GUID;
+
+///
+/// Certificate which encapsulates the RSASSA_PKCS1-v1_5 digital signature.
+///
+/// The WIN_CERTIFICATE_UEFI_PKCS1_15 structure is derived from
+/// WIN_CERTIFICATE and encapsulate the information needed to
+/// implement the RSASSA-PKCS1-v1_5 digital signature algorithm as
+/// specified in RFC2437.
+///
+typedef struct {
+ ///
+ /// This is the standard WIN_CERTIFICATE header, where
+ /// wCertificateType is set to WIN_CERT_TYPE_UEFI_PKCS1_15.
+ ///
+ WIN_CERTIFICATE Hdr;
+ ///
+ /// This is the hashing algorithm which was performed on the
+ /// UEFI executable when creating the digital signature.
+ ///
+ EFI_GUID HashAlgorithm;
+ ///
+ /// The following is the actual digital signature. The
+ /// size of the signature is the same size as the key
+ /// (1024-bit key is 128 bytes) and can be determined by
+ /// subtracting the length of the other parts of this header
+ /// from the total length of the certificate as found in
+ /// Hdr.dwLength.
+ ///
+ /// UINT8 Signature[];
+ ///
+} WIN_CERTIFICATE_EFI_PKCS1_15;
+
+extern EFI_GUID gEfiCertTypeRsa2048Sha256Guid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Ia32/Nasm.inc b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Ia32/Nasm.inc
new file mode 100644
index 0000000000..dbd3d7a28e
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Ia32/Nasm.inc
@@ -0,0 +1,48 @@
+;------------------------------------------------------------------------------
+;
+; Copyright (c) 2019 - 2022, Intel Corporation. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Abstract:
+;
+; This file provides macro definitions for NASM files.
+;
+;------------------------------------------------------------------------------
+
+; NASM provides built-in macros STRUC and ENDSTRUC for structure definition.
+; For example, to define a structure called mytype containing a longword,
+; a word, a byte and a string of bytes, you might code
+;
+; struc mytype
+;
+; mt_long: resd 1
+; mt_word: resw 1
+; mt_byte: resb 1
+; mt_str: resb 32
+;
+; endstruc
+;
+; Below macros are help to map the C types and the RESB family of pseudo-instructions.
+; So that the above structure definition can be coded as
+;
+; struc mytype
+;
+; mt_long: CTYPE_UINT32 1
+; mt_word: CTYPE_UINT16 1
+; mt_byte: CTYPE_UINT8 1
+; mt_str: CTYPE_CHAR8 32
+;
+; endstruc
+%define CTYPE_UINT64 resq
+%define CTYPE_INT64 resq
+%define CTYPE_UINT32 resd
+%define CTYPE_INT32 resd
+%define CTYPE_UINT16 resw
+%define CTYPE_INT16 resw
+%define CTYPE_BOOLEAN resb
+%define CTYPE_UINT8 resb
+%define CTYPE_CHAR8 resb
+%define CTYPE_INT8 resb
+
+%define CTYPE_UINTN resd
+%define CTYPE_INTN resd
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Ia32/ProcessorBind.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Ia32/ProcessorBind.h
new file mode 100644
index 0000000000..9267d61f0d
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Ia32/ProcessorBind.h
@@ -0,0 +1,319 @@
+/** @file
+ Processor or Compiler specific defines and types for IA-32 architecture.
+
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __PROCESSOR_BIND_H__
+#define __PROCESSOR_BIND_H__
+
+///
+/// Define the processor type so other code can make processor based choices.
+///
+#define MDE_CPU_IA32
+
+//
+// Make sure we are using the correct packing rules per EFI specification
+//
+#if !defined (__GNUC__)
+ #pragma pack()
+#endif
+
+#if defined (__INTEL_COMPILER)
+//
+// Disable ICC's remark #869: "Parameter" was never referenced warning.
+// This is legal ANSI C code so we disable the remark that is turned on with -Wall
+//
+ #pragma warning ( disable : 869 )
+
+//
+// Disable ICC's remark #1418: external function definition with no prior declaration.
+// This is legal ANSI C code so we disable the remark that is turned on with /W4
+//
+ #pragma warning ( disable : 1418 )
+
+//
+// Disable ICC's remark #1419: external declaration in primary source file
+// This is legal ANSI C code so we disable the remark that is turned on with /W4
+//
+ #pragma warning ( disable : 1419 )
+
+//
+// Disable ICC's remark #593: "Variable" was set but never used.
+// This is legal ANSI C code so we disable the remark that is turned on with /W4
+//
+ #pragma warning ( disable : 593 )
+
+#endif
+
+#if defined (_MSC_EXTENSIONS)
+
+//
+// Disable warning that make it impossible to compile at /W4
+// This only works for Microsoft* tools
+//
+
+//
+// Disabling bitfield type checking warnings.
+//
+ #pragma warning ( disable : 4214 )
+
+//
+// Disabling the unreferenced formal parameter warnings.
+//
+ #pragma warning ( disable : 4100 )
+
+//
+// Disable slightly different base types warning as CHAR8 * can not be set
+// to a constant string.
+//
+ #pragma warning ( disable : 4057 )
+
+//
+// ASSERT(FALSE) or while (TRUE) are legal constructs so suppress this warning
+//
+ #pragma warning ( disable : 4127 )
+
+//
+// This warning is caused by functions defined but not used. For precompiled header only.
+//
+ #pragma warning ( disable : 4505 )
+
+//
+// This warning is caused by empty (after preprocessing) source file. For precompiled header only.
+//
+ #pragma warning ( disable : 4206 )
+
+ #if defined (_MSC_VER) && _MSC_VER >= 1800
+
+//
+// Disable these warnings for VS2013.
+//
+
+//
+// This warning is for potentially uninitialized local variable, and it may cause false
+// positive issues in VS2013 and VS2015 build
+//
+ #pragma warning ( disable : 4701 )
+
+//
+// This warning is for potentially uninitialized local pointer variable, and it may cause
+// false positive issues in VS2013 and VS2015 build
+//
+ #pragma warning ( disable : 4703 )
+
+ #endif
+
+#endif
+
+#if defined (_MSC_EXTENSIONS)
+
+//
+// use Microsoft C compiler dependent integer width types
+//
+
+///
+/// 8-byte unsigned value.
+///
+typedef unsigned __int64 UINT64;
+///
+/// 8-byte signed value.
+///
+typedef __int64 INT64;
+///
+/// 4-byte unsigned value.
+///
+typedef unsigned __int32 UINT32;
+///
+/// 4-byte signed value.
+///
+typedef __int32 INT32;
+///
+/// 2-byte unsigned value.
+///
+typedef unsigned short UINT16;
+///
+/// 2-byte Character. Unless otherwise specified all strings are stored in the
+/// UTF-16 encoding format as defined by Unicode 2.1 and ISO/IEC 10646 standards.
+///
+typedef unsigned short CHAR16;
+///
+/// 2-byte signed value.
+///
+typedef short INT16;
+///
+/// Logical Boolean. 1-byte value containing 0 for FALSE or a 1 for TRUE. Other
+/// values are undefined.
+///
+typedef unsigned char BOOLEAN;
+///
+/// 1-byte unsigned value.
+///
+typedef unsigned char UINT8;
+///
+/// 1-byte Character.
+///
+typedef char CHAR8;
+///
+/// 1-byte signed value.
+///
+typedef signed char INT8;
+#else
+///
+/// 8-byte unsigned value.
+///
+typedef unsigned long long UINT64;
+///
+/// 8-byte signed value.
+///
+typedef long long INT64;
+///
+/// 4-byte unsigned value.
+///
+typedef unsigned int UINT32;
+///
+/// 4-byte signed value.
+///
+typedef int INT32;
+///
+/// 2-byte unsigned value.
+///
+typedef unsigned short UINT16;
+///
+/// 2-byte Character. Unless otherwise specified all strings are stored in the
+/// UTF-16 encoding format as defined by Unicode 2.1 and ISO/IEC 10646 standards.
+///
+typedef unsigned short CHAR16;
+///
+/// 2-byte signed value.
+///
+typedef short INT16;
+///
+/// Logical Boolean. 1-byte value containing 0 for FALSE or a 1 for TRUE. Other
+/// values are undefined.
+///
+typedef unsigned char BOOLEAN;
+///
+/// 1-byte unsigned value.
+///
+typedef unsigned char UINT8;
+///
+/// 1-byte Character
+///
+typedef char CHAR8;
+///
+/// 1-byte signed value
+///
+typedef signed char INT8;
+#endif
+
+///
+/// Unsigned value of native width. (4 bytes on supported 32-bit processor instructions;
+/// 8 bytes on supported 64-bit processor instructions.)
+///
+typedef UINT32 UINTN;
+///
+/// Signed value of native width. (4 bytes on supported 32-bit processor instructions;
+/// 8 bytes on supported 64-bit processor instructions.)
+///
+typedef INT32 INTN;
+
+//
+// Processor specific defines
+//
+
+///
+/// A value of native width with the highest bit set.
+///
+#define MAX_BIT 0x80000000
+///
+/// A value of native width with the two highest bits set.
+///
+#define MAX_2_BITS 0xC0000000
+
+///
+/// Maximum legal IA-32 address.
+///
+#define MAX_ADDRESS 0xFFFFFFFF
+
+///
+/// Maximum usable address at boot time
+///
+#define MAX_ALLOC_ADDRESS MAX_ADDRESS
+
+///
+/// Maximum legal IA-32 INTN and UINTN values.
+///
+#define MAX_INTN ((INTN)0x7FFFFFFF)
+#define MAX_UINTN ((UINTN)0xFFFFFFFF)
+
+///
+/// Minimum legal IA-32 INTN value.
+///
+#define MIN_INTN (((INTN)-2147483647) - 1)
+
+///
+/// The stack alignment required for IA-32.
+///
+#define CPU_STACK_ALIGNMENT sizeof(UINTN)
+
+///
+/// Page allocation granularity for IA-32.
+///
+#define DEFAULT_PAGE_ALLOCATION_GRANULARITY (0x1000)
+#define RUNTIME_PAGE_ALLOCATION_GRANULARITY (0x1000)
+
+//
+// Modifier to ensure that all protocol member functions and EFI intrinsics
+// use the correct C calling convention. All protocol member functions and
+// EFI intrinsics are required to modify their member functions with EFIAPI.
+//
+#ifdef EFIAPI
+///
+/// If EFIAPI is already defined, then we use that definition.
+///
+#elif defined (_MSC_EXTENSIONS)
+///
+/// Microsoft* compiler specific method for EFIAPI calling convention.
+///
+#define EFIAPI __cdecl
+#elif defined (__GNUC__) || defined (__clang__)
+///
+/// GCC specific method for EFIAPI calling convention.
+///
+#define EFIAPI __attribute__((cdecl))
+#else
+///
+/// The default for a non Microsoft* or GCC compiler is to assume the EFI ABI
+/// is the standard.
+///
+#define EFIAPI
+#endif
+
+#if defined (__GNUC__) || defined (__clang__)
+///
+/// For GNU assembly code, .global or .globl can declare global symbols.
+/// Define this macro to unify the usage.
+///
+#define ASM_GLOBAL .globl
+#endif
+
+/**
+ Return the pointer to the first instruction of a function given a function pointer.
+ On IA-32 CPU architectures, these two pointer values are the same,
+ so the implementation of this macro is very simple.
+
+ @param FunctionPointer A pointer to a function.
+
+ @return The pointer to the first instruction of a function given a function pointer.
+
+**/
+#define FUNCTION_ENTRY_POINT(FunctionPointer) (VOID *)(UINTN)(FunctionPointer)
+
+#ifndef __USER_LABEL_PREFIX__
+#define __USER_LABEL_PREFIX__ _
+#endif
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/Acpi.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/Acpi.h
new file mode 100644
index 0000000000..718b393488
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/Acpi.h
@@ -0,0 +1,17 @@
+/** @file
+ This file contains the latest ACPI definitions that are
+ consumed by drivers that do not care about ACPI versions.
+
+ Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.
+ Copyright (c) 2019 - 2021, ARM Ltd. All rights reserved.
+ Copyright (c) 2023, Loongson Technology Corporation Limited. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _ACPI_H_
+#define _ACPI_H_
+
+#include
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/Acpi10.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/Acpi10.h
new file mode 100644
index 0000000000..fb920d8bea
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/Acpi10.h
@@ -0,0 +1,666 @@
+/** @file
+ ACPI 1.0b definitions from the ACPI Specification, revision 1.0b
+
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+Copyright (c) 2020, Arm Limited. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _ACPI_1_0_H_
+#define _ACPI_1_0_H_
+
+#include
+
+///
+/// Common table header, this prefaces all ACPI tables, including FACS, but
+/// excluding the RSD PTR structure.
+///
+typedef struct {
+ UINT32 Signature;
+ UINT32 Length;
+} EFI_ACPI_COMMON_HEADER;
+
+#pragma pack(1)
+///
+/// The common ACPI description table header. This structure prefaces most ACPI tables.
+///
+typedef struct {
+ UINT32 Signature;
+ UINT32 Length;
+ UINT8 Revision;
+ UINT8 Checksum;
+ UINT8 OemId[6];
+ UINT64 OemTableId;
+ UINT32 OemRevision;
+ UINT32 CreatorId;
+ UINT32 CreatorRevision;
+} EFI_ACPI_DESCRIPTION_HEADER;
+#pragma pack()
+
+//
+// Define for Descriptor
+//
+#define ACPI_SMALL_ITEM_FLAG 0x00
+#define ACPI_LARGE_ITEM_FLAG 0x01
+
+//
+// Small Item Descriptor Name
+//
+#define ACPI_SMALL_IRQ_DESCRIPTOR_NAME 0x04
+#define ACPI_SMALL_DMA_DESCRIPTOR_NAME 0x05
+#define ACPI_SMALL_START_DEPENDENT_DESCRIPTOR_NAME 0x06
+#define ACPI_SMALL_END_DEPENDENT_DESCRIPTOR_NAME 0x07
+#define ACPI_SMALL_IO_PORT_DESCRIPTOR_NAME 0x08
+#define ACPI_SMALL_FIXED_IO_PORT_DESCRIPTOR_NAME 0x09
+#define ACPI_SMALL_VENDOR_DEFINED_DESCRIPTOR_NAME 0x0E
+#define ACPI_SMALL_END_TAG_DESCRIPTOR_NAME 0x0F
+
+//
+// Large Item Descriptor Name
+//
+#define ACPI_LARGE_24_BIT_MEMORY_RANGE_DESCRIPTOR_NAME 0x01
+#define ACPI_LARGE_VENDOR_DEFINED_DESCRIPTOR_NAME 0x04
+#define ACPI_LARGE_32_BIT_MEMORY_RANGE_DESCRIPTOR_NAME 0x05
+#define ACPI_LARGE_32_BIT_FIXED_MEMORY_RANGE_DESCRIPTOR_NAME 0x06
+#define ACPI_LARGE_DWORD_ADDRESS_SPACE_DESCRIPTOR_NAME 0x07
+#define ACPI_LARGE_WORD_ADDRESS_SPACE_DESCRIPTOR_NAME 0x08
+#define ACPI_LARGE_EXTENDED_IRQ_DESCRIPTOR_NAME 0x09
+#define ACPI_LARGE_QWORD_ADDRESS_SPACE_DESCRIPTOR_NAME 0x0A
+
+//
+// Small Item Descriptor Value
+//
+#define ACPI_IRQ_NOFLAG_DESCRIPTOR 0x22
+#define ACPI_IRQ_DESCRIPTOR 0x23
+#define ACPI_DMA_DESCRIPTOR 0x2A
+#define ACPI_START_DEPENDENT_DESCRIPTOR 0x30
+#define ACPI_START_DEPENDENT_EX_DESCRIPTOR 0x31
+#define ACPI_END_DEPENDENT_DESCRIPTOR 0x38
+#define ACPI_IO_PORT_DESCRIPTOR 0x47
+#define ACPI_FIXED_LOCATION_IO_PORT_DESCRIPTOR 0x4B
+#define ACPI_END_TAG_DESCRIPTOR 0x79
+
+//
+// Large Item Descriptor Value
+//
+#define ACPI_24_BIT_MEMORY_RANGE_DESCRIPTOR 0x81
+#define ACPI_32_BIT_MEMORY_RANGE_DESCRIPTOR 0x85
+#define ACPI_32_BIT_FIXED_MEMORY_RANGE_DESCRIPTOR 0x86
+#define ACPI_DWORD_ADDRESS_SPACE_DESCRIPTOR 0x87
+#define ACPI_WORD_ADDRESS_SPACE_DESCRIPTOR 0x88
+#define ACPI_EXTENDED_INTERRUPT_DESCRIPTOR 0x89
+#define ACPI_QWORD_ADDRESS_SPACE_DESCRIPTOR 0x8A
+#define ACPI_ADDRESS_SPACE_DESCRIPTOR 0x8A
+
+//
+// Resource Type
+//
+#define ACPI_ADDRESS_SPACE_TYPE_MEM 0x00
+#define ACPI_ADDRESS_SPACE_TYPE_IO 0x01
+#define ACPI_ADDRESS_SPACE_TYPE_BUS 0x02
+
+///
+/// Power Management Timer frequency is fixed at 3.579545MHz.
+///
+#define ACPI_TIMER_FREQUENCY 3579545
+
+//
+// Ensure proper structure formats
+//
+#pragma pack(1)
+
+///
+/// The common definition of QWORD, DWORD, and WORD
+/// Address Space Descriptors.
+///
+typedef PACKED struct {
+ UINT8 Desc;
+ UINT16 Len;
+ UINT8 ResType;
+ UINT8 GenFlag;
+ UINT8 SpecificFlag;
+ UINT64 AddrSpaceGranularity;
+ UINT64 AddrRangeMin;
+ UINT64 AddrRangeMax;
+ UINT64 AddrTranslationOffset;
+ UINT64 AddrLen;
+} EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR;
+
+typedef PACKED union {
+ UINT8 Byte;
+ PACKED struct {
+ UINT8 Length : 3;
+ UINT8 Name : 4;
+ UINT8 Type : 1;
+ } Bits;
+} ACPI_SMALL_RESOURCE_HEADER;
+
+typedef PACKED struct {
+ PACKED union {
+ UINT8 Byte;
+ PACKED struct {
+ UINT8 Name : 7;
+ UINT8 Type : 1;
+ } Bits;
+ } Header;
+ UINT16 Length;
+} ACPI_LARGE_RESOURCE_HEADER;
+
+///
+/// IRQ Descriptor.
+///
+typedef PACKED struct {
+ ACPI_SMALL_RESOURCE_HEADER Header;
+ UINT16 Mask;
+} EFI_ACPI_IRQ_NOFLAG_DESCRIPTOR;
+
+///
+/// IRQ Descriptor.
+///
+typedef PACKED struct {
+ ACPI_SMALL_RESOURCE_HEADER Header;
+ UINT16 Mask;
+ UINT8 Information;
+} EFI_ACPI_IRQ_DESCRIPTOR;
+
+///
+/// DMA Descriptor.
+///
+typedef PACKED struct {
+ ACPI_SMALL_RESOURCE_HEADER Header;
+ UINT8 ChannelMask;
+ UINT8 Information;
+} EFI_ACPI_DMA_DESCRIPTOR;
+
+///
+/// I/O Port Descriptor
+///
+typedef PACKED struct {
+ ACPI_SMALL_RESOURCE_HEADER Header;
+ UINT8 Information;
+ UINT16 BaseAddressMin;
+ UINT16 BaseAddressMax;
+ UINT8 Alignment;
+ UINT8 Length;
+} EFI_ACPI_IO_PORT_DESCRIPTOR;
+
+///
+/// Fixed Location I/O Port Descriptor.
+///
+typedef PACKED struct {
+ ACPI_SMALL_RESOURCE_HEADER Header;
+ UINT16 BaseAddress;
+ UINT8 Length;
+} EFI_ACPI_FIXED_LOCATION_IO_PORT_DESCRIPTOR;
+
+///
+/// 24-Bit Memory Range Descriptor
+///
+typedef PACKED struct {
+ ACPI_LARGE_RESOURCE_HEADER Header;
+ UINT8 Information;
+ UINT16 BaseAddressMin;
+ UINT16 BaseAddressMax;
+ UINT16 Alignment;
+ UINT16 Length;
+} EFI_ACPI_24_BIT_MEMORY_RANGE_DESCRIPTOR;
+
+///
+/// 32-Bit Memory Range Descriptor
+///
+typedef PACKED struct {
+ ACPI_LARGE_RESOURCE_HEADER Header;
+ UINT8 Information;
+ UINT32 BaseAddressMin;
+ UINT32 BaseAddressMax;
+ UINT32 Alignment;
+ UINT32 Length;
+} EFI_ACPI_32_BIT_MEMORY_RANGE_DESCRIPTOR;
+
+///
+/// Fixed 32-Bit Fixed Memory Range Descriptor
+///
+typedef PACKED struct {
+ ACPI_LARGE_RESOURCE_HEADER Header;
+ UINT8 Information;
+ UINT32 BaseAddress;
+ UINT32 Length;
+} EFI_ACPI_32_BIT_FIXED_MEMORY_RANGE_DESCRIPTOR;
+
+///
+/// QWORD Address Space Descriptor
+///
+typedef PACKED struct {
+ ACPI_LARGE_RESOURCE_HEADER Header;
+ UINT8 ResType;
+ UINT8 GenFlag;
+ UINT8 SpecificFlag;
+ UINT64 AddrSpaceGranularity;
+ UINT64 AddrRangeMin;
+ UINT64 AddrRangeMax;
+ UINT64 AddrTranslationOffset;
+ UINT64 AddrLen;
+} EFI_ACPI_QWORD_ADDRESS_SPACE_DESCRIPTOR;
+
+///
+/// DWORD Address Space Descriptor
+///
+typedef PACKED struct {
+ ACPI_LARGE_RESOURCE_HEADER Header;
+ UINT8 ResType;
+ UINT8 GenFlag;
+ UINT8 SpecificFlag;
+ UINT32 AddrSpaceGranularity;
+ UINT32 AddrRangeMin;
+ UINT32 AddrRangeMax;
+ UINT32 AddrTranslationOffset;
+ UINT32 AddrLen;
+} EFI_ACPI_DWORD_ADDRESS_SPACE_DESCRIPTOR;
+
+///
+/// WORD Address Space Descriptor
+///
+typedef PACKED struct {
+ ACPI_LARGE_RESOURCE_HEADER Header;
+ UINT8 ResType;
+ UINT8 GenFlag;
+ UINT8 SpecificFlag;
+ UINT16 AddrSpaceGranularity;
+ UINT16 AddrRangeMin;
+ UINT16 AddrRangeMax;
+ UINT16 AddrTranslationOffset;
+ UINT16 AddrLen;
+} EFI_ACPI_WORD_ADDRESS_SPACE_DESCRIPTOR;
+
+///
+/// Extended Interrupt Descriptor
+///
+typedef PACKED struct {
+ ACPI_LARGE_RESOURCE_HEADER Header;
+ UINT8 InterruptVectorFlags;
+ UINT8 InterruptTableLength;
+ UINT32 InterruptNumber[1];
+} EFI_ACPI_EXTENDED_INTERRUPT_DESCRIPTOR;
+
+#pragma pack()
+
+///
+/// The End tag identifies an end of resource data.
+///
+typedef struct {
+ UINT8 Desc;
+ UINT8 Checksum;
+} EFI_ACPI_END_TAG_DESCRIPTOR;
+
+//
+// General use definitions
+//
+#define EFI_ACPI_RESERVED_BYTE 0x00
+#define EFI_ACPI_RESERVED_WORD 0x0000
+#define EFI_ACPI_RESERVED_DWORD 0x00000000
+#define EFI_ACPI_RESERVED_QWORD 0x0000000000000000
+
+//
+// Resource Type Specific Flags
+// Ref ACPI specification 6.4.3.5.5
+//
+// Bit [0] : Write Status, _RW
+//
+#define EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_READ_WRITE (1 << 0)
+#define EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_READ_ONLY (0 << 0)
+//
+// Bit [2:1] : Memory Attributes, _MEM
+//
+#define EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_NON_CACHEABLE (0 << 1)
+#define EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE (1 << 1)
+#define EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_WRITE_COMBINING (2 << 1)
+#define EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE (3 << 1)
+//
+// Bit [4:3] : Memory Attributes, _MTP
+//
+#define EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_ADDRESS_RANGE_MEMORY (0 << 3)
+#define EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_ADDRESS_RANGE_RESERVED (1 << 3)
+#define EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_ADDRESS_RANGE_ACPI (2 << 3)
+#define EFI_APCI_MEMORY_RESOURCE_SPECIFIC_FLAG_ADDRESS_RANGE_NVS (3 << 3)
+//
+// Bit [5] : Memory to I/O Translation, _TTP
+//
+#define EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_TYPE_TRANSLATION (1 << 5)
+#define EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_TYPE_STATIC (0 << 5)
+
+//
+// IRQ Information
+// Ref ACPI specification 6.4.2.1
+//
+#define EFI_ACPI_IRQ_SHARABLE_MASK 0x10
+#define EFI_ACPI_IRQ_SHARABLE 0x10
+
+#define EFI_ACPI_IRQ_POLARITY_MASK 0x08
+#define EFI_ACPI_IRQ_HIGH_TRUE 0x00
+#define EFI_ACPI_IRQ_LOW_FALSE 0x08
+
+#define EFI_ACPI_IRQ_MODE 0x01
+#define EFI_ACPI_IRQ_LEVEL_TRIGGERED 0x00
+#define EFI_ACPI_IRQ_EDGE_TRIGGERED 0x01
+
+//
+// DMA Information
+// Ref ACPI specification 6.4.2.2
+//
+#define EFI_ACPI_DMA_SPEED_TYPE_MASK 0x60
+#define EFI_ACPI_DMA_SPEED_TYPE_COMPATIBILITY 0x00
+#define EFI_ACPI_DMA_SPEED_TYPE_A 0x20
+#define EFI_ACPI_DMA_SPEED_TYPE_B 0x40
+#define EFI_ACPI_DMA_SPEED_TYPE_F 0x60
+
+#define EFI_ACPI_DMA_BUS_MASTER_MASK 0x04
+#define EFI_ACPI_DMA_BUS_MASTER 0x04
+
+#define EFI_ACPI_DMA_TRANSFER_TYPE_MASK 0x03
+#define EFI_ACPI_DMA_TRANSFER_TYPE_8_BIT 0x00
+#define EFI_ACPI_DMA_TRANSFER_TYPE_8_BIT_AND_16_BIT 0x01
+#define EFI_ACPI_DMA_TRANSFER_TYPE_16_BIT 0x02
+
+//
+// IO Information
+// Ref ACPI specification 6.4.2.5
+//
+#define EFI_ACPI_IO_DECODE_MASK 0x01
+#define EFI_ACPI_IO_DECODE_16_BIT 0x01
+#define EFI_ACPI_IO_DECODE_10_BIT 0x00
+
+//
+// Memory Information
+// Ref ACPI specification 6.4.3.4
+//
+#define EFI_ACPI_MEMORY_WRITE_STATUS_MASK 0x01
+#define EFI_ACPI_MEMORY_WRITABLE 0x01
+#define EFI_ACPI_MEMORY_NON_WRITABLE 0x00
+
+//
+// Interrupt Vector Flags definitions for Extended Interrupt Descriptor
+// Ref ACPI specification 6.4.3.6
+//
+#define EFI_ACPI_EXTENDED_INTERRUPT_FLAG_PRODUCER_CONSUMER_MASK BIT0
+#define EFI_ACPI_EXTENDED_INTERRUPT_FLAG_MODE_MASK BIT1
+#define EFI_ACPI_EXTENDED_INTERRUPT_FLAG_POLARITY_MASK BIT2
+#define EFI_ACPI_EXTENDED_INTERRUPT_FLAG_SHARABLE_MASK BIT3
+#define EFI_ACPI_EXTENDED_INTERRUPT_FLAG_WAKE_CAPABLITY_MASK BIT4
+
+//
+// Ensure proper structure formats
+//
+#pragma pack(1)
+//
+// ACPI 1.0b table structures
+//
+
+///
+/// Root System Description Pointer Structure.
+///
+typedef struct {
+ UINT64 Signature;
+ UINT8 Checksum;
+ UINT8 OemId[6];
+ UINT8 Reserved;
+ UINT32 RsdtAddress;
+} EFI_ACPI_1_0_ROOT_SYSTEM_DESCRIPTION_POINTER;
+
+//
+// Root System Description Table
+// No definition needed as it is a common description table header, the same with
+// EFI_ACPI_DESCRIPTION_HEADER, followed by a variable number of UINT32 table pointers.
+//
+
+///
+/// RSDT Revision (as defined in ACPI 1.0b specification).
+///
+#define EFI_ACPI_1_0_ROOT_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01
+
+///
+/// Fixed ACPI Description Table Structure (FADT).
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 FirmwareCtrl;
+ UINT32 Dsdt;
+ UINT8 IntModel;
+ UINT8 Reserved1;
+ UINT16 SciInt;
+ UINT32 SmiCmd;
+ UINT8 AcpiEnable;
+ UINT8 AcpiDisable;
+ UINT8 S4BiosReq;
+ UINT8 Reserved2;
+ UINT32 Pm1aEvtBlk;
+ UINT32 Pm1bEvtBlk;
+ UINT32 Pm1aCntBlk;
+ UINT32 Pm1bCntBlk;
+ UINT32 Pm2CntBlk;
+ UINT32 PmTmrBlk;
+ UINT32 Gpe0Blk;
+ UINT32 Gpe1Blk;
+ UINT8 Pm1EvtLen;
+ UINT8 Pm1CntLen;
+ UINT8 Pm2CntLen;
+ UINT8 PmTmLen;
+ UINT8 Gpe0BlkLen;
+ UINT8 Gpe1BlkLen;
+ UINT8 Gpe1Base;
+ UINT8 Reserved3;
+ UINT16 PLvl2Lat;
+ UINT16 PLvl3Lat;
+ UINT16 FlushSize;
+ UINT16 FlushStride;
+ UINT8 DutyOffset;
+ UINT8 DutyWidth;
+ UINT8 DayAlrm;
+ UINT8 MonAlrm;
+ UINT8 Century;
+ UINT8 Reserved4;
+ UINT8 Reserved5;
+ UINT8 Reserved6;
+ UINT32 Flags;
+} EFI_ACPI_1_0_FIXED_ACPI_DESCRIPTION_TABLE;
+
+///
+/// FADT Version (as defined in ACPI 1.0b specification).
+///
+#define EFI_ACPI_1_0_FIXED_ACPI_DESCRIPTION_TABLE_REVISION 0x01
+
+#define EFI_ACPI_1_0_INT_MODE_DUAL_PIC 0
+#define EFI_ACPI_1_0_INT_MODE_MULTIPLE_APIC 1
+
+//
+// Fixed ACPI Description Table Fixed Feature Flags
+// All other bits are reserved and must be set to 0.
+//
+#define EFI_ACPI_1_0_WBINVD BIT0
+#define EFI_ACPI_1_0_WBINVD_FLUSH BIT1
+#define EFI_ACPI_1_0_PROC_C1 BIT2
+#define EFI_ACPI_1_0_P_LVL2_UP BIT3
+#define EFI_ACPI_1_0_PWR_BUTTON BIT4
+#define EFI_ACPI_1_0_SLP_BUTTON BIT5
+#define EFI_ACPI_1_0_FIX_RTC BIT6
+#define EFI_ACPI_1_0_RTC_S4 BIT7
+#define EFI_ACPI_1_0_TMR_VAL_EXT BIT8
+#define EFI_ACPI_1_0_DCK_CAP BIT9
+
+///
+/// Firmware ACPI Control Structure.
+///
+typedef struct {
+ UINT32 Signature;
+ UINT32 Length;
+ UINT32 HardwareSignature;
+ UINT32 FirmwareWakingVector;
+ UINT32 GlobalLock;
+ UINT32 Flags;
+ UINT8 Reserved[40];
+} EFI_ACPI_1_0_FIRMWARE_ACPI_CONTROL_STRUCTURE;
+
+///
+/// Firmware Control Structure Feature Flags.
+/// All other bits are reserved and must be set to 0.
+///
+#define EFI_ACPI_1_0_S4BIOS_F BIT0
+
+///
+/// Multiple APIC Description Table header definition. The rest of the table
+/// must be defined in a platform-specific manner.
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 LocalApicAddress;
+ UINT32 Flags;
+} EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER;
+
+///
+/// MADT Revision (as defined in ACPI 1.0b specification).
+///
+#define EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION 0x01
+
+///
+/// Multiple APIC Flags
+/// All other bits are reserved and must be set to 0.
+///
+#define EFI_ACPI_1_0_PCAT_COMPAT BIT0
+
+//
+// Multiple APIC Description Table APIC structure types
+// All other values between 0x05 an 0xFF are reserved and
+// will be ignored by OSPM.
+//
+#define EFI_ACPI_1_0_PROCESSOR_LOCAL_APIC 0x00
+#define EFI_ACPI_1_0_IO_APIC 0x01
+#define EFI_ACPI_1_0_INTERRUPT_SOURCE_OVERRIDE 0x02
+#define EFI_ACPI_1_0_NON_MASKABLE_INTERRUPT_SOURCE 0x03
+#define EFI_ACPI_1_0_LOCAL_APIC_NMI 0x04
+
+//
+// APIC Structure Definitions
+//
+
+///
+/// Processor Local APIC Structure Definition.
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 AcpiProcessorId;
+ UINT8 ApicId;
+ UINT32 Flags;
+} EFI_ACPI_1_0_PROCESSOR_LOCAL_APIC_STRUCTURE;
+
+///
+/// Local APIC Flags. All other bits are reserved and must be 0.
+///
+#define EFI_ACPI_1_0_LOCAL_APIC_ENABLED BIT0
+
+///
+/// IO APIC Structure.
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 IoApicId;
+ UINT8 Reserved;
+ UINT32 IoApicAddress;
+ UINT32 SystemVectorBase;
+} EFI_ACPI_1_0_IO_APIC_STRUCTURE;
+
+///
+/// Interrupt Source Override Structure.
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 Bus;
+ UINT8 Source;
+ UINT32 GlobalSystemInterruptVector;
+ UINT16 Flags;
+} EFI_ACPI_1_0_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE;
+
+///
+/// Non-Maskable Interrupt Source Structure.
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Flags;
+ UINT32 GlobalSystemInterruptVector;
+} EFI_ACPI_1_0_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE;
+
+///
+/// Local APIC NMI Structure.
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 AcpiProcessorId;
+ UINT16 Flags;
+ UINT8 LocalApicInti;
+} EFI_ACPI_1_0_LOCAL_APIC_NMI_STRUCTURE;
+
+///
+/// Smart Battery Description Table (SBST)
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 WarningEnergyLevel;
+ UINT32 LowEnergyLevel;
+ UINT32 CriticalEnergyLevel;
+} EFI_ACPI_1_0_SMART_BATTERY_DESCRIPTION_TABLE;
+
+//
+// Known table signatures
+//
+
+///
+/// "RSD PTR " Root System Description Pointer.
+///
+#define EFI_ACPI_1_0_ROOT_SYSTEM_DESCRIPTION_POINTER_SIGNATURE SIGNATURE_64('R', 'S', 'D', ' ', 'P', 'T', 'R', ' ')
+
+///
+/// "APIC" Multiple APIC Description Table.
+///
+#define EFI_ACPI_1_0_APIC_SIGNATURE SIGNATURE_32('A', 'P', 'I', 'C')
+
+///
+/// "DSDT" Differentiated System Description Table.
+///
+#define EFI_ACPI_1_0_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('D', 'S', 'D', 'T')
+
+///
+/// "FACS" Firmware ACPI Control Structure.
+///
+#define EFI_ACPI_1_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_SIGNATURE SIGNATURE_32('F', 'A', 'C', 'S')
+
+///
+/// "FACP" Fixed ACPI Description Table.
+///
+#define EFI_ACPI_1_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('F', 'A', 'C', 'P')
+
+///
+/// "PSDT" Persistent System Description Table.
+///
+#define EFI_ACPI_1_0_PERSISTENT_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('P', 'S', 'D', 'T')
+
+///
+/// "RSDT" Root System Description Table.
+///
+#define EFI_ACPI_1_0_ROOT_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('R', 'S', 'D', 'T')
+
+///
+/// "SBST" Smart Battery Specification Table.
+///
+#define EFI_ACPI_1_0_SMART_BATTERY_SPECIFICATION_TABLE_SIGNATURE SIGNATURE_32('S', 'B', 'S', 'T')
+
+///
+/// "SSDT" Secondary System Description Table.
+///
+#define EFI_ACPI_1_0_SECONDARY_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('S', 'S', 'D', 'T')
+
+#pragma pack()
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/Acpi20.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/Acpi20.h
new file mode 100644
index 0000000000..4e39452baa
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/Acpi20.h
@@ -0,0 +1,539 @@
+/** @file
+ ACPI 2.0 definitions from the ACPI Specification, revision 2.0
+
+ Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _ACPI_2_0_H_
+#define _ACPI_2_0_H_
+
+#include
+
+//
+// Define for Descriptor
+//
+#define ACPI_LARGE_GENERIC_REGISTER_DESCRIPTOR_NAME 0x02
+
+#define ACPI_GENERIC_REGISTER_DESCRIPTOR 0x82
+
+//
+// Ensure proper structure formats
+//
+#pragma pack(1)
+
+///
+/// Generic Register Descriptor
+///
+typedef PACKED struct {
+ ACPI_LARGE_RESOURCE_HEADER Header;
+ UINT8 AddressSpaceId;
+ UINT8 RegisterBitWidth;
+ UINT8 RegisterBitOffset;
+ UINT8 AddressSize;
+ UINT64 RegisterAddress;
+} EFI_ACPI_GENERIC_REGISTER_DESCRIPTOR;
+
+#pragma pack()
+
+//
+// Ensure proper structure formats
+//
+#pragma pack(1)
+
+///
+/// ACPI 2.0 Generic Address Space definition
+///
+typedef struct {
+ UINT8 AddressSpaceId;
+ UINT8 RegisterBitWidth;
+ UINT8 RegisterBitOffset;
+ UINT8 Reserved;
+ UINT64 Address;
+} EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE;
+
+//
+// Generic Address Space Address IDs
+//
+#define EFI_ACPI_2_0_SYSTEM_MEMORY 0
+#define EFI_ACPI_2_0_SYSTEM_IO 1
+#define EFI_ACPI_2_0_PCI_CONFIGURATION_SPACE 2
+#define EFI_ACPI_2_0_EMBEDDED_CONTROLLER 3
+#define EFI_ACPI_2_0_SMBUS 4
+#define EFI_ACPI_2_0_FUNCTIONAL_FIXED_HARDWARE 0x7F
+
+//
+// ACPI 2.0 table structures
+//
+
+///
+/// Root System Description Pointer Structure
+///
+typedef struct {
+ UINT64 Signature;
+ UINT8 Checksum;
+ UINT8 OemId[6];
+ UINT8 Revision;
+ UINT32 RsdtAddress;
+ UINT32 Length;
+ UINT64 XsdtAddress;
+ UINT8 ExtendedChecksum;
+ UINT8 Reserved[3];
+} EFI_ACPI_2_0_ROOT_SYSTEM_DESCRIPTION_POINTER;
+
+///
+/// RSD_PTR Revision (as defined in ACPI 2.0 spec.)
+///
+#define EFI_ACPI_2_0_ROOT_SYSTEM_DESCRIPTION_POINTER_REVISION 0x02
+
+///
+/// Common table header, this prefaces all ACPI tables, including FACS, but
+/// excluding the RSD PTR structure
+///
+typedef struct {
+ UINT32 Signature;
+ UINT32 Length;
+} EFI_ACPI_2_0_COMMON_HEADER;
+
+//
+// Root System Description Table
+// No definition needed as it is a common description table header, the same with
+// EFI_ACPI_DESCRIPTION_HEADER, followed by a variable number of UINT32 table pointers.
+//
+
+///
+/// RSDT Revision (as defined in ACPI 2.0 spec.)
+///
+#define EFI_ACPI_2_0_ROOT_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01
+
+//
+// Extended System Description Table
+// No definition needed as it is a common description table header, the same with
+// EFI_ACPI_DESCRIPTION_HEADER, followed by a variable number of UINT64 table pointers.
+//
+
+///
+/// XSDT Revision (as defined in ACPI 2.0 spec.)
+///
+#define EFI_ACPI_2_0_EXTENDED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01
+
+///
+/// Fixed ACPI Description Table Structure (FADT)
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 FirmwareCtrl;
+ UINT32 Dsdt;
+ UINT8 Reserved0;
+ UINT8 PreferredPmProfile;
+ UINT16 SciInt;
+ UINT32 SmiCmd;
+ UINT8 AcpiEnable;
+ UINT8 AcpiDisable;
+ UINT8 S4BiosReq;
+ UINT8 PstateCnt;
+ UINT32 Pm1aEvtBlk;
+ UINT32 Pm1bEvtBlk;
+ UINT32 Pm1aCntBlk;
+ UINT32 Pm1bCntBlk;
+ UINT32 Pm2CntBlk;
+ UINT32 PmTmrBlk;
+ UINT32 Gpe0Blk;
+ UINT32 Gpe1Blk;
+ UINT8 Pm1EvtLen;
+ UINT8 Pm1CntLen;
+ UINT8 Pm2CntLen;
+ UINT8 PmTmrLen;
+ UINT8 Gpe0BlkLen;
+ UINT8 Gpe1BlkLen;
+ UINT8 Gpe1Base;
+ UINT8 CstCnt;
+ UINT16 PLvl2Lat;
+ UINT16 PLvl3Lat;
+ UINT16 FlushSize;
+ UINT16 FlushStride;
+ UINT8 DutyOffset;
+ UINT8 DutyWidth;
+ UINT8 DayAlrm;
+ UINT8 MonAlrm;
+ UINT8 Century;
+ UINT16 IaPcBootArch;
+ UINT8 Reserved1;
+ UINT32 Flags;
+ EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE ResetReg;
+ UINT8 ResetValue;
+ UINT8 Reserved2[3];
+ UINT64 XFirmwareCtrl;
+ UINT64 XDsdt;
+ EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE XPm1aEvtBlk;
+ EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE XPm1bEvtBlk;
+ EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE XPm1aCntBlk;
+ EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE XPm1bCntBlk;
+ EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE XPm2CntBlk;
+ EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE XPmTmrBlk;
+ EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE XGpe0Blk;
+ EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE XGpe1Blk;
+} EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE;
+
+///
+/// FADT Version (as defined in ACPI 2.0 spec.)
+///
+#define EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE_REVISION 0x03
+
+//
+// Fixed ACPI Description Table Preferred Power Management Profile
+//
+#define EFI_ACPI_2_0_PM_PROFILE_UNSPECIFIED 0
+#define EFI_ACPI_2_0_PM_PROFILE_DESKTOP 1
+#define EFI_ACPI_2_0_PM_PROFILE_MOBILE 2
+#define EFI_ACPI_2_0_PM_PROFILE_WORKSTATION 3
+#define EFI_ACPI_2_0_PM_PROFILE_ENTERPRISE_SERVER 4
+#define EFI_ACPI_2_0_PM_PROFILE_SOHO_SERVER 5
+#define EFI_ACPI_2_0_PM_PROFILE_APPLIANCE_PC 6
+
+//
+// Fixed ACPI Description Table Boot Architecture Flags
+// All other bits are reserved and must be set to 0.
+//
+#define EFI_ACPI_2_0_LEGACY_DEVICES BIT0
+#define EFI_ACPI_2_0_8042 BIT1
+
+//
+// Fixed ACPI Description Table Fixed Feature Flags
+// All other bits are reserved and must be set to 0.
+//
+#define EFI_ACPI_2_0_WBINVD BIT0
+#define EFI_ACPI_2_0_WBINVD_FLUSH BIT1
+#define EFI_ACPI_2_0_PROC_C1 BIT2
+#define EFI_ACPI_2_0_P_LVL2_UP BIT3
+#define EFI_ACPI_2_0_PWR_BUTTON BIT4
+#define EFI_ACPI_2_0_SLP_BUTTON BIT5
+#define EFI_ACPI_2_0_FIX_RTC BIT6
+#define EFI_ACPI_2_0_RTC_S4 BIT7
+#define EFI_ACPI_2_0_TMR_VAL_EXT BIT8
+#define EFI_ACPI_2_0_DCK_CAP BIT9
+#define EFI_ACPI_2_0_RESET_REG_SUP BIT10
+#define EFI_ACPI_2_0_SEALED_CASE BIT11
+#define EFI_ACPI_2_0_HEADLESS BIT12
+#define EFI_ACPI_2_0_CPU_SW_SLP BIT13
+
+///
+/// Firmware ACPI Control Structure
+///
+typedef struct {
+ UINT32 Signature;
+ UINT32 Length;
+ UINT32 HardwareSignature;
+ UINT32 FirmwareWakingVector;
+ UINT32 GlobalLock;
+ UINT32 Flags;
+ UINT64 XFirmwareWakingVector;
+ UINT8 Version;
+ UINT8 Reserved[31];
+} EFI_ACPI_2_0_FIRMWARE_ACPI_CONTROL_STRUCTURE;
+
+///
+/// FACS Version (as defined in ACPI 2.0 spec.)
+///
+#define EFI_ACPI_2_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_VERSION 0x01
+
+///
+/// Firmware Control Structure Feature Flags
+/// All other bits are reserved and must be set to 0.
+///
+#define EFI_ACPI_2_0_S4BIOS_F BIT0
+
+///
+/// Multiple APIC Description Table header definition. The rest of the table
+/// must be defined in a platform specific manner.
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 LocalApicAddress;
+ UINT32 Flags;
+} EFI_ACPI_2_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER;
+
+///
+/// MADT Revision (as defined in ACPI 2.0 spec.)
+///
+#define EFI_ACPI_2_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION 0x01
+
+///
+/// Multiple APIC Flags
+/// All other bits are reserved and must be set to 0.
+///
+#define EFI_ACPI_2_0_PCAT_COMPAT BIT0
+
+//
+// Multiple APIC Description Table APIC structure types
+// All other values between 0x09 an 0xFF are reserved and
+// will be ignored by OSPM.
+//
+#define EFI_ACPI_2_0_PROCESSOR_LOCAL_APIC 0x00
+#define EFI_ACPI_2_0_IO_APIC 0x01
+#define EFI_ACPI_2_0_INTERRUPT_SOURCE_OVERRIDE 0x02
+#define EFI_ACPI_2_0_NON_MASKABLE_INTERRUPT_SOURCE 0x03
+#define EFI_ACPI_2_0_LOCAL_APIC_NMI 0x04
+#define EFI_ACPI_2_0_LOCAL_APIC_ADDRESS_OVERRIDE 0x05
+#define EFI_ACPI_2_0_IO_SAPIC 0x06
+#define EFI_ACPI_2_0_PROCESSOR_LOCAL_SAPIC 0x07
+#define EFI_ACPI_2_0_PLATFORM_INTERRUPT_SOURCES 0x08
+
+//
+// APIC Structure Definitions
+//
+
+///
+/// Processor Local APIC Structure Definition
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 AcpiProcessorId;
+ UINT8 ApicId;
+ UINT32 Flags;
+} EFI_ACPI_2_0_PROCESSOR_LOCAL_APIC_STRUCTURE;
+
+///
+/// Local APIC Flags. All other bits are reserved and must be 0.
+///
+#define EFI_ACPI_2_0_LOCAL_APIC_ENABLED BIT0
+
+///
+/// IO APIC Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 IoApicId;
+ UINT8 Reserved;
+ UINT32 IoApicAddress;
+ UINT32 GlobalSystemInterruptBase;
+} EFI_ACPI_2_0_IO_APIC_STRUCTURE;
+
+///
+/// Interrupt Source Override Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 Bus;
+ UINT8 Source;
+ UINT32 GlobalSystemInterrupt;
+ UINT16 Flags;
+} EFI_ACPI_2_0_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE;
+
+///
+/// Non-Maskable Interrupt Source Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Flags;
+ UINT32 GlobalSystemInterrupt;
+} EFI_ACPI_2_0_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE;
+
+///
+/// Local APIC NMI Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 AcpiProcessorId;
+ UINT16 Flags;
+ UINT8 LocalApicLint;
+} EFI_ACPI_2_0_LOCAL_APIC_NMI_STRUCTURE;
+
+///
+/// Local APIC Address Override Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Reserved;
+ UINT64 LocalApicAddress;
+} EFI_ACPI_2_0_LOCAL_APIC_ADDRESS_OVERRIDE_STRUCTURE;
+
+///
+/// IO SAPIC Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 IoApicId;
+ UINT8 Reserved;
+ UINT32 GlobalSystemInterruptBase;
+ UINT64 IoSapicAddress;
+} EFI_ACPI_2_0_IO_SAPIC_STRUCTURE;
+
+///
+/// Local SAPIC Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 AcpiProcessorId;
+ UINT8 LocalSapicId;
+ UINT8 LocalSapicEid;
+ UINT8 Reserved[3];
+ UINT32 Flags;
+} EFI_ACPI_2_0_PROCESSOR_LOCAL_SAPIC_STRUCTURE;
+
+///
+/// Platform Interrupt Sources Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Flags;
+ UINT8 InterruptType;
+ UINT8 ProcessorId;
+ UINT8 ProcessorEid;
+ UINT8 IoSapicVector;
+ UINT32 GlobalSystemInterrupt;
+ UINT32 Reserved;
+} EFI_ACPI_2_0_PLATFORM_INTERRUPT_SOURCES_STRUCTURE;
+
+///
+/// Smart Battery Description Table (SBST)
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 WarningEnergyLevel;
+ UINT32 LowEnergyLevel;
+ UINT32 CriticalEnergyLevel;
+} EFI_ACPI_2_0_SMART_BATTERY_DESCRIPTION_TABLE;
+
+///
+/// SBST Version (as defined in ACPI 2.0 spec.)
+///
+#define EFI_ACPI_2_0_SMART_BATTERY_DESCRIPTION_TABLE_REVISION 0x01
+
+///
+/// Embedded Controller Boot Resources Table (ECDT)
+/// The table is followed by a null terminated ASCII string that contains
+/// a fully qualified reference to the name space object.
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE EcControl;
+ EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE EcData;
+ UINT32 Uid;
+ UINT8 GpeBit;
+} EFI_ACPI_2_0_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE;
+
+///
+/// ECDT Version (as defined in ACPI 2.0 spec.)
+///
+#define EFI_ACPI_2_0_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE_REVISION 0x01
+
+//
+// Known table signatures
+//
+
+///
+/// "RSD PTR " Root System Description Pointer
+///
+#define EFI_ACPI_2_0_ROOT_SYSTEM_DESCRIPTION_POINTER_SIGNATURE SIGNATURE_64('R', 'S', 'D', ' ', 'P', 'T', 'R', ' ')
+
+///
+/// "SPIC" Multiple SAPIC Description Table
+///
+/// BUGBUG: Don't know where this came from except SR870BN4 uses it.
+/// #define EFI_ACPI_2_0_MULTIPLE_SAPIC_DESCRIPTION_TABLE_SIGNATURE 0x43495053
+///
+#define EFI_ACPI_2_0_MULTIPLE_SAPIC_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('A', 'P', 'I', 'C')
+
+///
+/// "BOOT" MS Simple Boot Spec
+///
+#define EFI_ACPI_2_0_SIMPLE_BOOT_FLAG_TABLE_SIGNATURE SIGNATURE_32('B', 'O', 'O', 'T')
+
+///
+/// "DBGP" MS Bebug Port Spec
+///
+#define EFI_ACPI_2_0_DEBUG_PORT_TABLE_SIGNATURE SIGNATURE_32('D', 'B', 'G', 'P')
+
+///
+/// "DSDT" Differentiated System Description Table
+///
+#define EFI_ACPI_2_0_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('D', 'S', 'D', 'T')
+
+///
+/// "ECDT" Embedded Controller Boot Resources Table
+///
+#define EFI_ACPI_2_0_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE_SIGNATURE SIGNATURE_32('E', 'C', 'D', 'T')
+
+///
+/// "ETDT" Event Timer Description Table
+///
+#define EFI_ACPI_2_0_EVENT_TIMER_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('E', 'T', 'D', 'T')
+
+///
+/// "FACS" Firmware ACPI Control Structure
+///
+#define EFI_ACPI_2_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_SIGNATURE SIGNATURE_32('F', 'A', 'C', 'S')
+
+///
+/// "FACP" Fixed ACPI Description Table
+///
+#define EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('F', 'A', 'C', 'P')
+
+///
+/// "APIC" Multiple APIC Description Table
+///
+#define EFI_ACPI_2_0_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('A', 'P', 'I', 'C')
+
+///
+/// "PSDT" Persistent System Description Table
+///
+#define EFI_ACPI_2_0_PERSISTENT_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('P', 'S', 'D', 'T')
+
+///
+/// "RSDT" Root System Description Table
+///
+#define EFI_ACPI_2_0_ROOT_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('R', 'S', 'D', 'T')
+
+///
+/// "SBST" Smart Battery Specification Table
+///
+#define EFI_ACPI_2_0_SMART_BATTERY_SPECIFICATION_TABLE_SIGNATURE SIGNATURE_32('S', 'B', 'S', 'T')
+
+///
+/// "SLIT" System Locality Information Table
+///
+#define EFI_ACPI_2_0_SYSTEM_LOCALITY_INFORMATION_TABLE_SIGNATURE SIGNATURE_32('S', 'L', 'I', 'T')
+
+///
+/// "SPCR" Serial Port Console Redirection Table
+///
+#define EFI_ACPI_2_0_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE SIGNATURE_32('S', 'P', 'C', 'R')
+
+///
+/// "SRAT" Static Resource Affinity Table
+///
+#define EFI_ACPI_2_0_STATIC_RESOURCE_AFFINITY_TABLE_SIGNATURE SIGNATURE_32('S', 'R', 'A', 'T')
+
+///
+/// "SSDT" Secondary System Description Table
+///
+#define EFI_ACPI_2_0_SECONDARY_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('S', 'S', 'D', 'T')
+
+///
+/// "SPMI" Server Platform Management Interface Table
+///
+#define EFI_ACPI_2_0_SERVER_PLATFORM_MANAGEMENT_INTERFACE_SIGNATURE SIGNATURE_32('S', 'P', 'M', 'I')
+
+///
+/// "XSDT" Extended System Description Table
+///
+#define EFI_ACPI_2_0_EXTENDED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('X', 'S', 'D', 'T')
+
+///
+/// "MCFG" PCI Express Memory Mapped Configuration Space Base Address Description Table
+///
+#define EFI_ACPI_2_0_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE_SIGNATURE SIGNATURE_32('M', 'C', 'F', 'G')
+
+#pragma pack()
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/Acpi30.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/Acpi30.h
new file mode 100644
index 0000000000..24c565a3c4
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/Acpi30.h
@@ -0,0 +1,723 @@
+/** @file
+ ACPI 3.0 definitions from the ACPI Specification Revision 3.0b October 10, 2006
+
+ Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _ACPI_3_0_H_
+#define _ACPI_3_0_H_
+
+#include
+
+//
+// Define for Descriptor
+//
+#define ACPI_LARGE_EXTENDED_ADDRESS_SPACE_DESCRIPTOR_NAME 0x0B
+
+#define ACPI_EXTENDED_ADDRESS_SPACE_DESCRIPTOR 0x8B
+
+//
+// Ensure proper structure formats
+//
+#pragma pack(1)
+
+///
+/// Extended Address Space Descriptor
+///
+typedef PACKED struct {
+ ACPI_LARGE_RESOURCE_HEADER Header;
+ UINT8 ResType;
+ UINT8 GenFlag;
+ UINT8 SpecificFlag;
+ UINT8 RevisionId;
+ UINT8 Reserved;
+ UINT64 AddrSpaceGranularity;
+ UINT64 AddrRangeMin;
+ UINT64 AddrRangeMax;
+ UINT64 AddrTranslationOffset;
+ UINT64 AddrLen;
+ UINT64 TypeSpecificAttribute;
+} EFI_ACPI_EXTENDED_ADDRESS_SPACE_DESCRIPTOR;
+
+#pragma pack()
+
+//
+// Memory Type Specific Flags
+//
+#define EFI_ACPI_MEMORY_TYPE_SPECIFIC_ATTRIBUTES_UC 0x0000000000000001
+#define EFI_ACPI_MEMORY_TYPE_SPECIFIC_ATTRIBUTES_WC 0x0000000000000002
+#define EFI_ACPI_MEMORY_TYPE_SPECIFIC_ATTRIBUTES_WT 0x0000000000000004
+#define EFI_ACPI_MEMORY_TYPE_SPECIFIC_ATTRIBUTES_WB 0x0000000000000008
+#define EFI_ACPI_MEMORY_TYPE_SPECIFIC_ATTRIBUTES_UCE 0x0000000000000010
+#define EFI_ACPI_MEMORY_TYPE_SPECIFIC_ATTRIBUTES_NV 0x0000000000008000
+
+//
+// Ensure proper structure formats
+//
+#pragma pack(1)
+
+///
+/// ACPI 3.0 Generic Address Space definition
+///
+typedef struct {
+ UINT8 AddressSpaceId;
+ UINT8 RegisterBitWidth;
+ UINT8 RegisterBitOffset;
+ UINT8 AccessSize;
+ UINT64 Address;
+} EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE;
+
+//
+// Generic Address Space Address IDs
+//
+#define EFI_ACPI_3_0_SYSTEM_MEMORY 0
+#define EFI_ACPI_3_0_SYSTEM_IO 1
+#define EFI_ACPI_3_0_PCI_CONFIGURATION_SPACE 2
+#define EFI_ACPI_3_0_EMBEDDED_CONTROLLER 3
+#define EFI_ACPI_3_0_SMBUS 4
+#define EFI_ACPI_3_0_FUNCTIONAL_FIXED_HARDWARE 0x7F
+
+//
+// Generic Address Space Access Sizes
+//
+#define EFI_ACPI_3_0_UNDEFINED 0
+#define EFI_ACPI_3_0_BYTE 1
+#define EFI_ACPI_3_0_WORD 2
+#define EFI_ACPI_3_0_DWORD 3
+#define EFI_ACPI_3_0_QWORD 4
+
+//
+// ACPI 3.0 table structures
+//
+
+///
+/// Root System Description Pointer Structure
+///
+typedef struct {
+ UINT64 Signature;
+ UINT8 Checksum;
+ UINT8 OemId[6];
+ UINT8 Revision;
+ UINT32 RsdtAddress;
+ UINT32 Length;
+ UINT64 XsdtAddress;
+ UINT8 ExtendedChecksum;
+ UINT8 Reserved[3];
+} EFI_ACPI_3_0_ROOT_SYSTEM_DESCRIPTION_POINTER;
+
+///
+/// RSD_PTR Revision (as defined in ACPI 3.0b spec.)
+///
+#define EFI_ACPI_3_0_ROOT_SYSTEM_DESCRIPTION_POINTER_REVISION 0x02 ///< ACPISpec (Revision 3.0b) says current value is 2
+
+///
+/// Common table header, this prefaces all ACPI tables, including FACS, but
+/// excluding the RSD PTR structure
+///
+typedef struct {
+ UINT32 Signature;
+ UINT32 Length;
+} EFI_ACPI_3_0_COMMON_HEADER;
+
+//
+// Root System Description Table
+// No definition needed as it is a common description table header, the same with
+// EFI_ACPI_DESCRIPTION_HEADER, followed by a variable number of UINT32 table pointers.
+//
+
+///
+/// RSDT Revision (as defined in ACPI 3.0 spec.)
+///
+#define EFI_ACPI_3_0_ROOT_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01
+
+//
+// Extended System Description Table
+// No definition needed as it is a common description table header, the same with
+// EFI_ACPI_DESCRIPTION_HEADER, followed by a variable number of UINT64 table pointers.
+//
+
+///
+/// XSDT Revision (as defined in ACPI 3.0 spec.)
+///
+#define EFI_ACPI_3_0_EXTENDED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01
+
+///
+/// Fixed ACPI Description Table Structure (FADT)
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 FirmwareCtrl;
+ UINT32 Dsdt;
+ UINT8 Reserved0;
+ UINT8 PreferredPmProfile;
+ UINT16 SciInt;
+ UINT32 SmiCmd;
+ UINT8 AcpiEnable;
+ UINT8 AcpiDisable;
+ UINT8 S4BiosReq;
+ UINT8 PstateCnt;
+ UINT32 Pm1aEvtBlk;
+ UINT32 Pm1bEvtBlk;
+ UINT32 Pm1aCntBlk;
+ UINT32 Pm1bCntBlk;
+ UINT32 Pm2CntBlk;
+ UINT32 PmTmrBlk;
+ UINT32 Gpe0Blk;
+ UINT32 Gpe1Blk;
+ UINT8 Pm1EvtLen;
+ UINT8 Pm1CntLen;
+ UINT8 Pm2CntLen;
+ UINT8 PmTmrLen;
+ UINT8 Gpe0BlkLen;
+ UINT8 Gpe1BlkLen;
+ UINT8 Gpe1Base;
+ UINT8 CstCnt;
+ UINT16 PLvl2Lat;
+ UINT16 PLvl3Lat;
+ UINT16 FlushSize;
+ UINT16 FlushStride;
+ UINT8 DutyOffset;
+ UINT8 DutyWidth;
+ UINT8 DayAlrm;
+ UINT8 MonAlrm;
+ UINT8 Century;
+ UINT16 IaPcBootArch;
+ UINT8 Reserved1;
+ UINT32 Flags;
+ EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE ResetReg;
+ UINT8 ResetValue;
+ UINT8 Reserved2[3];
+ UINT64 XFirmwareCtrl;
+ UINT64 XDsdt;
+ EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE XPm1aEvtBlk;
+ EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE XPm1bEvtBlk;
+ EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE XPm1aCntBlk;
+ EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE XPm1bCntBlk;
+ EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE XPm2CntBlk;
+ EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE XPmTmrBlk;
+ EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE XGpe0Blk;
+ EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE XGpe1Blk;
+} EFI_ACPI_3_0_FIXED_ACPI_DESCRIPTION_TABLE;
+
+///
+/// FADT Version (as defined in ACPI 3.0 spec.)
+///
+#define EFI_ACPI_3_0_FIXED_ACPI_DESCRIPTION_TABLE_REVISION 0x04
+
+//
+// Fixed ACPI Description Table Preferred Power Management Profile
+//
+#define EFI_ACPI_3_0_PM_PROFILE_UNSPECIFIED 0
+#define EFI_ACPI_3_0_PM_PROFILE_DESKTOP 1
+#define EFI_ACPI_3_0_PM_PROFILE_MOBILE 2
+#define EFI_ACPI_3_0_PM_PROFILE_WORKSTATION 3
+#define EFI_ACPI_3_0_PM_PROFILE_ENTERPRISE_SERVER 4
+#define EFI_ACPI_3_0_PM_PROFILE_SOHO_SERVER 5
+#define EFI_ACPI_3_0_PM_PROFILE_APPLIANCE_PC 6
+#define EFI_ACPI_3_0_PM_PROFILE_PERFORMANCE_SERVER 7
+
+//
+// Fixed ACPI Description Table Boot Architecture Flags
+// All other bits are reserved and must be set to 0.
+//
+#define EFI_ACPI_3_0_LEGACY_DEVICES BIT0
+#define EFI_ACPI_3_0_8042 BIT1
+#define EFI_ACPI_3_0_VGA_NOT_PRESENT BIT2
+#define EFI_ACPI_3_0_MSI_NOT_SUPPORTED BIT3
+#define EFI_ACPI_3_0_PCIE_ASPM_CONTROLS BIT4
+
+//
+// Fixed ACPI Description Table Fixed Feature Flags
+// All other bits are reserved and must be set to 0.
+//
+#define EFI_ACPI_3_0_WBINVD BIT0
+#define EFI_ACPI_3_0_WBINVD_FLUSH BIT1
+#define EFI_ACPI_3_0_PROC_C1 BIT2
+#define EFI_ACPI_3_0_P_LVL2_UP BIT3
+#define EFI_ACPI_3_0_PWR_BUTTON BIT4
+#define EFI_ACPI_3_0_SLP_BUTTON BIT5
+#define EFI_ACPI_3_0_FIX_RTC BIT6
+#define EFI_ACPI_3_0_RTC_S4 BIT7
+#define EFI_ACPI_3_0_TMR_VAL_EXT BIT8
+#define EFI_ACPI_3_0_DCK_CAP BIT9
+#define EFI_ACPI_3_0_RESET_REG_SUP BIT10
+#define EFI_ACPI_3_0_SEALED_CASE BIT11
+#define EFI_ACPI_3_0_HEADLESS BIT12
+#define EFI_ACPI_3_0_CPU_SW_SLP BIT13
+#define EFI_ACPI_3_0_PCI_EXP_WAK BIT14
+#define EFI_ACPI_3_0_USE_PLATFORM_CLOCK BIT15
+#define EFI_ACPI_3_0_S4_RTC_STS_VALID BIT16
+#define EFI_ACPI_3_0_REMOTE_POWER_ON_CAPABLE BIT17
+#define EFI_ACPI_3_0_FORCE_APIC_CLUSTER_MODEL BIT18
+#define EFI_ACPI_3_0_FORCE_APIC_PHYSICAL_DESTINATION_MODE BIT19
+
+///
+/// Firmware ACPI Control Structure
+///
+typedef struct {
+ UINT32 Signature;
+ UINT32 Length;
+ UINT32 HardwareSignature;
+ UINT32 FirmwareWakingVector;
+ UINT32 GlobalLock;
+ UINT32 Flags;
+ UINT64 XFirmwareWakingVector;
+ UINT8 Version;
+ UINT8 Reserved[31];
+} EFI_ACPI_3_0_FIRMWARE_ACPI_CONTROL_STRUCTURE;
+
+///
+/// FACS Version (as defined in ACPI 3.0 spec.)
+///
+#define EFI_ACPI_3_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_VERSION 0x01
+
+///
+/// Firmware Control Structure Feature Flags
+/// All other bits are reserved and must be set to 0.
+///
+#define EFI_ACPI_3_0_S4BIOS_F BIT0
+
+//
+// Differentiated System Description Table,
+// Secondary System Description Table
+// and Persistent System Description Table,
+// no definition needed as they are common description table header, the same with
+// EFI_ACPI_DESCRIPTION_HEADER, followed by a definition block.
+//
+#define EFI_ACPI_3_0_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x02
+#define EFI_ACPI_3_0_SECONDARY_SYSTEM_DESCRIPTION_TABLE_REVISION 0x02
+
+///
+/// Multiple APIC Description Table header definition. The rest of the table
+/// must be defined in a platform specific manner.
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 LocalApicAddress;
+ UINT32 Flags;
+} EFI_ACPI_3_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER;
+
+///
+/// MADT Revision (as defined in ACPI 3.0 spec.)
+///
+#define EFI_ACPI_3_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION 0x02
+
+///
+/// Multiple APIC Flags
+/// All other bits are reserved and must be set to 0.
+///
+#define EFI_ACPI_3_0_PCAT_COMPAT BIT0
+
+//
+// Multiple APIC Description Table APIC structure types
+// All other values between 0x09 an 0xFF are reserved and
+// will be ignored by OSPM.
+//
+#define EFI_ACPI_3_0_PROCESSOR_LOCAL_APIC 0x00
+#define EFI_ACPI_3_0_IO_APIC 0x01
+#define EFI_ACPI_3_0_INTERRUPT_SOURCE_OVERRIDE 0x02
+#define EFI_ACPI_3_0_NON_MASKABLE_INTERRUPT_SOURCE 0x03
+#define EFI_ACPI_3_0_LOCAL_APIC_NMI 0x04
+#define EFI_ACPI_3_0_LOCAL_APIC_ADDRESS_OVERRIDE 0x05
+#define EFI_ACPI_3_0_IO_SAPIC 0x06
+#define EFI_ACPI_3_0_LOCAL_SAPIC 0x07
+#define EFI_ACPI_3_0_PLATFORM_INTERRUPT_SOURCES 0x08
+
+//
+// APIC Structure Definitions
+//
+
+///
+/// Processor Local APIC Structure Definition
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 AcpiProcessorId;
+ UINT8 ApicId;
+ UINT32 Flags;
+} EFI_ACPI_3_0_PROCESSOR_LOCAL_APIC_STRUCTURE;
+
+///
+/// Local APIC Flags. All other bits are reserved and must be 0.
+///
+#define EFI_ACPI_3_0_LOCAL_APIC_ENABLED BIT0
+
+///
+/// IO APIC Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 IoApicId;
+ UINT8 Reserved;
+ UINT32 IoApicAddress;
+ UINT32 GlobalSystemInterruptBase;
+} EFI_ACPI_3_0_IO_APIC_STRUCTURE;
+
+///
+/// Interrupt Source Override Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 Bus;
+ UINT8 Source;
+ UINT32 GlobalSystemInterrupt;
+ UINT16 Flags;
+} EFI_ACPI_3_0_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE;
+
+///
+/// Platform Interrupt Sources Structure Definition
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Flags;
+ UINT8 InterruptType;
+ UINT8 ProcessorId;
+ UINT8 ProcessorEid;
+ UINT8 IoSapicVector;
+ UINT32 GlobalSystemInterrupt;
+ UINT32 PlatformInterruptSourceFlags;
+ UINT8 CpeiProcessorOverride;
+ UINT8 Reserved[31];
+} EFI_ACPI_3_0_PLATFORM_INTERRUPT_APIC_STRUCTURE;
+
+//
+// MPS INTI flags.
+// All other bits are reserved and must be set to 0.
+//
+#define EFI_ACPI_3_0_POLARITY (3 << 0)
+#define EFI_ACPI_3_0_TRIGGER_MODE (3 << 2)
+
+///
+/// Non-Maskable Interrupt Source Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Flags;
+ UINT32 GlobalSystemInterrupt;
+} EFI_ACPI_3_0_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE;
+
+///
+/// Local APIC NMI Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 AcpiProcessorId;
+ UINT16 Flags;
+ UINT8 LocalApicLint;
+} EFI_ACPI_3_0_LOCAL_APIC_NMI_STRUCTURE;
+
+///
+/// Local APIC Address Override Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Reserved;
+ UINT64 LocalApicAddress;
+} EFI_ACPI_3_0_LOCAL_APIC_ADDRESS_OVERRIDE_STRUCTURE;
+
+///
+/// IO SAPIC Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 IoApicId;
+ UINT8 Reserved;
+ UINT32 GlobalSystemInterruptBase;
+ UINT64 IoSapicAddress;
+} EFI_ACPI_3_0_IO_SAPIC_STRUCTURE;
+
+///
+/// Local SAPIC Structure
+/// This struct followed by a null-terminated ASCII string - ACPI Processor UID String
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 AcpiProcessorId;
+ UINT8 LocalSapicId;
+ UINT8 LocalSapicEid;
+ UINT8 Reserved[3];
+ UINT32 Flags;
+ UINT32 ACPIProcessorUIDValue;
+} EFI_ACPI_3_0_PROCESSOR_LOCAL_SAPIC_STRUCTURE;
+
+///
+/// Platform Interrupt Sources Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Flags;
+ UINT8 InterruptType;
+ UINT8 ProcessorId;
+ UINT8 ProcessorEid;
+ UINT8 IoSapicVector;
+ UINT32 GlobalSystemInterrupt;
+ UINT32 PlatformInterruptSourceFlags;
+} EFI_ACPI_3_0_PLATFORM_INTERRUPT_SOURCES_STRUCTURE;
+
+///
+/// Platform Interrupt Source Flags.
+/// All other bits are reserved and must be set to 0.
+///
+#define EFI_ACPI_3_0_CPEI_PROCESSOR_OVERRIDE BIT0
+
+///
+/// Smart Battery Description Table (SBST)
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 WarningEnergyLevel;
+ UINT32 LowEnergyLevel;
+ UINT32 CriticalEnergyLevel;
+} EFI_ACPI_3_0_SMART_BATTERY_DESCRIPTION_TABLE;
+
+///
+/// SBST Version (as defined in ACPI 3.0 spec.)
+///
+#define EFI_ACPI_3_0_SMART_BATTERY_DESCRIPTION_TABLE_REVISION 0x01
+
+///
+/// Embedded Controller Boot Resources Table (ECDT)
+/// The table is followed by a null terminated ASCII string that contains
+/// a fully qualified reference to the name space object.
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE EcControl;
+ EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE EcData;
+ UINT32 Uid;
+ UINT8 GpeBit;
+} EFI_ACPI_3_0_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE;
+
+///
+/// ECDT Version (as defined in ACPI 3.0 spec.)
+///
+#define EFI_ACPI_3_0_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE_REVISION 0x01
+
+///
+/// System Resource Affinity Table (SRAT. The rest of the table
+/// must be defined in a platform specific manner.
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 Reserved1; ///< Must be set to 1
+ UINT64 Reserved2;
+} EFI_ACPI_3_0_SYSTEM_RESOURCE_AFFINITY_TABLE_HEADER;
+
+///
+/// SRAT Version (as defined in ACPI 3.0 spec.)
+///
+#define EFI_ACPI_3_0_SYSTEM_RESOURCE_AFFINITY_TABLE_REVISION 0x02
+
+//
+// SRAT structure types.
+// All other values between 0x02 an 0xFF are reserved and
+// will be ignored by OSPM.
+//
+#define EFI_ACPI_3_0_PROCESSOR_LOCAL_APIC_SAPIC_AFFINITY 0x00
+#define EFI_ACPI_3_0_MEMORY_AFFINITY 0x01
+
+///
+/// Processor Local APIC/SAPIC Affinity Structure Definition
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 ProximityDomain7To0;
+ UINT8 ApicId;
+ UINT32 Flags;
+ UINT8 LocalSapicEid;
+ UINT8 ProximityDomain31To8[3];
+ UINT8 Reserved[4];
+} EFI_ACPI_3_0_PROCESSOR_LOCAL_APIC_SAPIC_AFFINITY_STRUCTURE;
+
+///
+/// Local APIC/SAPIC Flags. All other bits are reserved and must be 0.
+///
+#define EFI_ACPI_3_0_PROCESSOR_LOCAL_APIC_SAPIC_ENABLED (1 << 0)
+
+///
+/// Memory Affinity Structure Definition
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT32 ProximityDomain;
+ UINT16 Reserved1;
+ UINT32 AddressBaseLow;
+ UINT32 AddressBaseHigh;
+ UINT32 LengthLow;
+ UINT32 LengthHigh;
+ UINT32 Reserved2;
+ UINT32 Flags;
+ UINT64 Reserved3;
+} EFI_ACPI_3_0_MEMORY_AFFINITY_STRUCTURE;
+
+//
+// Memory Flags. All other bits are reserved and must be 0.
+//
+#define EFI_ACPI_3_0_MEMORY_ENABLED (1 << 0)
+#define EFI_ACPI_3_0_MEMORY_HOT_PLUGGABLE (1 << 1)
+#define EFI_ACPI_3_0_MEMORY_NONVOLATILE (1 << 2)
+
+///
+/// System Locality Distance Information Table (SLIT).
+/// The rest of the table is a matrix.
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT64 NumberOfSystemLocalities;
+} EFI_ACPI_3_0_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_HEADER;
+
+///
+/// SLIT Version (as defined in ACPI 3.0 spec.)
+///
+#define EFI_ACPI_3_0_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_REVISION 0x01
+
+//
+// Known table signatures
+//
+
+///
+/// "RSD PTR " Root System Description Pointer
+///
+#define EFI_ACPI_3_0_ROOT_SYSTEM_DESCRIPTION_POINTER_SIGNATURE SIGNATURE_64('R', 'S', 'D', ' ', 'P', 'T', 'R', ' ')
+
+///
+/// "APIC" Multiple APIC Description Table
+///
+#define EFI_ACPI_3_0_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('A', 'P', 'I', 'C')
+
+///
+/// "DSDT" Differentiated System Description Table
+///
+#define EFI_ACPI_3_0_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('D', 'S', 'D', 'T')
+
+///
+/// "ECDT" Embedded Controller Boot Resources Table
+///
+#define EFI_ACPI_3_0_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE_SIGNATURE SIGNATURE_32('E', 'C', 'D', 'T')
+
+///
+/// "FACP" Fixed ACPI Description Table
+///
+#define EFI_ACPI_3_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('F', 'A', 'C', 'P')
+
+///
+/// "FACS" Firmware ACPI Control Structure
+///
+#define EFI_ACPI_3_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_SIGNATURE SIGNATURE_32('F', 'A', 'C', 'S')
+
+///
+/// "PSDT" Persistent System Description Table
+///
+#define EFI_ACPI_3_0_PERSISTENT_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('P', 'S', 'D', 'T')
+
+///
+/// "RSDT" Root System Description Table
+///
+#define EFI_ACPI_3_0_ROOT_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('R', 'S', 'D', 'T')
+
+///
+/// "SBST" Smart Battery Specification Table
+///
+#define EFI_ACPI_3_0_SMART_BATTERY_SPECIFICATION_TABLE_SIGNATURE SIGNATURE_32('S', 'B', 'S', 'T')
+
+///
+/// "SLIT" System Locality Information Table
+///
+#define EFI_ACPI_3_0_SYSTEM_LOCALITY_INFORMATION_TABLE_SIGNATURE SIGNATURE_32('S', 'L', 'I', 'T')
+
+///
+/// "SRAT" System Resource Affinity Table
+///
+#define EFI_ACPI_3_0_SYSTEM_RESOURCE_AFFINITY_TABLE_SIGNATURE SIGNATURE_32('S', 'R', 'A', 'T')
+
+///
+/// "SSDT" Secondary System Description Table
+///
+#define EFI_ACPI_3_0_SECONDARY_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('S', 'S', 'D', 'T')
+
+///
+/// "XSDT" Extended System Description Table
+///
+#define EFI_ACPI_3_0_EXTENDED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('X', 'S', 'D', 'T')
+
+///
+/// "BOOT" MS Simple Boot Spec
+///
+#define EFI_ACPI_3_0_SIMPLE_BOOT_FLAG_TABLE_SIGNATURE SIGNATURE_32('B', 'O', 'O', 'T')
+
+///
+/// "CPEP" Corrected Platform Error Polling Table
+///
+#define EFI_ACPI_3_0_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_SIGNATURE SIGNATURE_32('C', 'P', 'E', 'P')
+
+///
+/// "DBGP" MS Debug Port Spec
+///
+#define EFI_ACPI_3_0_DEBUG_PORT_TABLE_SIGNATURE SIGNATURE_32('D', 'B', 'G', 'P')
+
+///
+/// "ETDT" Event Timer Description Table
+///
+#define EFI_ACPI_3_0_EVENT_TIMER_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('E', 'T', 'D', 'T')
+
+///
+/// "HPET" IA-PC High Precision Event Timer Table
+///
+#define EFI_ACPI_3_0_HIGH_PRECISION_EVENT_TIMER_TABLE_SIGNATURE SIGNATURE_32('H', 'P', 'E', 'T')
+
+///
+/// "MCFG" PCI Express Memory Mapped Configuration Space Base Address Description Table
+///
+#define EFI_ACPI_3_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('M', 'C', 'F', 'G')
+
+///
+/// "SPCR" Serial Port Console Redirection Table
+///
+#define EFI_ACPI_3_0_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE SIGNATURE_32('S', 'P', 'C', 'R')
+
+///
+/// "SPMI" Server Platform Management Interface Table
+///
+#define EFI_ACPI_3_0_SERVER_PLATFORM_MANAGEMENT_INTERFACE_TABLE_SIGNATURE SIGNATURE_32('S', 'P', 'M', 'I')
+
+///
+/// "TCPA" Trusted Computing Platform Alliance Capabilities Table
+///
+#define EFI_ACPI_3_0_TRUSTED_COMPUTING_PLATFORM_ALLIANCE_CAPABILITIES_TABLE_SIGNATURE SIGNATURE_32('T', 'C', 'P', 'A')
+
+///
+/// "WDRT" Watchdog Resource Table
+///
+#define EFI_ACPI_3_0_WATCHDOG_RESOURCE_TABLE_SIGNATURE SIGNATURE_32('W', 'D', 'R', 'T')
+
+///
+/// "WDAT" Watchdog Action Table
+///
+#define EFI_ACPI_3_0_WATCHDOG_ACTION_TABLE_SIGNATURE SIGNATURE_32('W', 'D', 'A', 'T')
+
+///
+/// "WSPT" Windows Specific Properties Table
+///
+#define EFI_ACPI_3_0_WINDOWS_SPECIFIC_PROPERTIES_TABLE_SIGNATURE SIGNATURE_32('W', 'S', 'P', 'T')
+
+///
+/// "iBFT" iSCSI Boot Firmware Table
+///
+#define EFI_ACPI_3_0_ISCSI_BOOT_FIRMWARE_TABLE_SIGNATURE SIGNATURE_32('i', 'B', 'F', 'T')
+
+#pragma pack()
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/Acpi40.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/Acpi40.h
new file mode 100644
index 0000000000..5e3493afd8
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/Acpi40.h
@@ -0,0 +1,1304 @@
+/** @file
+ ACPI 4.0 definitions from the ACPI Specification Revision 4.0a April 5, 2010
+
+ Copyright (c) 2010 - 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _ACPI_4_0_H_
+#define _ACPI_4_0_H_
+
+#include
+
+//
+// Ensure proper structure formats
+//
+#pragma pack(1)
+
+///
+/// ACPI 4.0 Generic Address Space definition
+///
+typedef struct {
+ UINT8 AddressSpaceId;
+ UINT8 RegisterBitWidth;
+ UINT8 RegisterBitOffset;
+ UINT8 AccessSize;
+ UINT64 Address;
+} EFI_ACPI_4_0_GENERIC_ADDRESS_STRUCTURE;
+
+//
+// Generic Address Space Address IDs
+//
+#define EFI_ACPI_4_0_SYSTEM_MEMORY 0
+#define EFI_ACPI_4_0_SYSTEM_IO 1
+#define EFI_ACPI_4_0_PCI_CONFIGURATION_SPACE 2
+#define EFI_ACPI_4_0_EMBEDDED_CONTROLLER 3
+#define EFI_ACPI_4_0_SMBUS 4
+#define EFI_ACPI_4_0_FUNCTIONAL_FIXED_HARDWARE 0x7F
+
+//
+// Generic Address Space Access Sizes
+//
+#define EFI_ACPI_4_0_UNDEFINED 0
+#define EFI_ACPI_4_0_BYTE 1
+#define EFI_ACPI_4_0_WORD 2
+#define EFI_ACPI_4_0_DWORD 3
+#define EFI_ACPI_4_0_QWORD 4
+
+//
+// ACPI 4.0 table structures
+//
+
+///
+/// Root System Description Pointer Structure
+///
+typedef struct {
+ UINT64 Signature;
+ UINT8 Checksum;
+ UINT8 OemId[6];
+ UINT8 Revision;
+ UINT32 RsdtAddress;
+ UINT32 Length;
+ UINT64 XsdtAddress;
+ UINT8 ExtendedChecksum;
+ UINT8 Reserved[3];
+} EFI_ACPI_4_0_ROOT_SYSTEM_DESCRIPTION_POINTER;
+
+///
+/// RSD_PTR Revision (as defined in ACPI 4.0b spec.)
+///
+#define EFI_ACPI_4_0_ROOT_SYSTEM_DESCRIPTION_POINTER_REVISION 0x02 ///< ACPISpec (Revision 4.0a) says current value is 2
+
+///
+/// Common table header, this prefaces all ACPI tables, including FACS, but
+/// excluding the RSD PTR structure
+///
+typedef struct {
+ UINT32 Signature;
+ UINT32 Length;
+} EFI_ACPI_4_0_COMMON_HEADER;
+
+//
+// Root System Description Table
+// No definition needed as it is a common description table header, the same with
+// EFI_ACPI_DESCRIPTION_HEADER, followed by a variable number of UINT32 table pointers.
+//
+
+///
+/// RSDT Revision (as defined in ACPI 4.0 spec.)
+///
+#define EFI_ACPI_4_0_ROOT_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01
+
+//
+// Extended System Description Table
+// No definition needed as it is a common description table header, the same with
+// EFI_ACPI_DESCRIPTION_HEADER, followed by a variable number of UINT64 table pointers.
+//
+
+///
+/// XSDT Revision (as defined in ACPI 4.0 spec.)
+///
+#define EFI_ACPI_4_0_EXTENDED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01
+
+///
+/// Fixed ACPI Description Table Structure (FADT)
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 FirmwareCtrl;
+ UINT32 Dsdt;
+ UINT8 Reserved0;
+ UINT8 PreferredPmProfile;
+ UINT16 SciInt;
+ UINT32 SmiCmd;
+ UINT8 AcpiEnable;
+ UINT8 AcpiDisable;
+ UINT8 S4BiosReq;
+ UINT8 PstateCnt;
+ UINT32 Pm1aEvtBlk;
+ UINT32 Pm1bEvtBlk;
+ UINT32 Pm1aCntBlk;
+ UINT32 Pm1bCntBlk;
+ UINT32 Pm2CntBlk;
+ UINT32 PmTmrBlk;
+ UINT32 Gpe0Blk;
+ UINT32 Gpe1Blk;
+ UINT8 Pm1EvtLen;
+ UINT8 Pm1CntLen;
+ UINT8 Pm2CntLen;
+ UINT8 PmTmrLen;
+ UINT8 Gpe0BlkLen;
+ UINT8 Gpe1BlkLen;
+ UINT8 Gpe1Base;
+ UINT8 CstCnt;
+ UINT16 PLvl2Lat;
+ UINT16 PLvl3Lat;
+ UINT16 FlushSize;
+ UINT16 FlushStride;
+ UINT8 DutyOffset;
+ UINT8 DutyWidth;
+ UINT8 DayAlrm;
+ UINT8 MonAlrm;
+ UINT8 Century;
+ UINT16 IaPcBootArch;
+ UINT8 Reserved1;
+ UINT32 Flags;
+ EFI_ACPI_4_0_GENERIC_ADDRESS_STRUCTURE ResetReg;
+ UINT8 ResetValue;
+ UINT8 Reserved2[3];
+ UINT64 XFirmwareCtrl;
+ UINT64 XDsdt;
+ EFI_ACPI_4_0_GENERIC_ADDRESS_STRUCTURE XPm1aEvtBlk;
+ EFI_ACPI_4_0_GENERIC_ADDRESS_STRUCTURE XPm1bEvtBlk;
+ EFI_ACPI_4_0_GENERIC_ADDRESS_STRUCTURE XPm1aCntBlk;
+ EFI_ACPI_4_0_GENERIC_ADDRESS_STRUCTURE XPm1bCntBlk;
+ EFI_ACPI_4_0_GENERIC_ADDRESS_STRUCTURE XPm2CntBlk;
+ EFI_ACPI_4_0_GENERIC_ADDRESS_STRUCTURE XPmTmrBlk;
+ EFI_ACPI_4_0_GENERIC_ADDRESS_STRUCTURE XGpe0Blk;
+ EFI_ACPI_4_0_GENERIC_ADDRESS_STRUCTURE XGpe1Blk;
+} EFI_ACPI_4_0_FIXED_ACPI_DESCRIPTION_TABLE;
+
+///
+/// FADT Version (as defined in ACPI 4.0 spec.)
+///
+#define EFI_ACPI_4_0_FIXED_ACPI_DESCRIPTION_TABLE_REVISION 0x04
+
+//
+// Fixed ACPI Description Table Preferred Power Management Profile
+//
+#define EFI_ACPI_4_0_PM_PROFILE_UNSPECIFIED 0
+#define EFI_ACPI_4_0_PM_PROFILE_DESKTOP 1
+#define EFI_ACPI_4_0_PM_PROFILE_MOBILE 2
+#define EFI_ACPI_4_0_PM_PROFILE_WORKSTATION 3
+#define EFI_ACPI_4_0_PM_PROFILE_ENTERPRISE_SERVER 4
+#define EFI_ACPI_4_0_PM_PROFILE_SOHO_SERVER 5
+#define EFI_ACPI_4_0_PM_PROFILE_APPLIANCE_PC 6
+#define EFI_ACPI_4_0_PM_PROFILE_PERFORMANCE_SERVER 7
+
+//
+// Fixed ACPI Description Table Boot Architecture Flags
+// All other bits are reserved and must be set to 0.
+//
+#define EFI_ACPI_4_0_LEGACY_DEVICES BIT0
+#define EFI_ACPI_4_0_8042 BIT1
+#define EFI_ACPI_4_0_VGA_NOT_PRESENT BIT2
+#define EFI_ACPI_4_0_MSI_NOT_SUPPORTED BIT3
+#define EFI_ACPI_4_0_PCIE_ASPM_CONTROLS BIT4
+
+//
+// Fixed ACPI Description Table Fixed Feature Flags
+// All other bits are reserved and must be set to 0.
+//
+#define EFI_ACPI_4_0_WBINVD BIT0
+#define EFI_ACPI_4_0_WBINVD_FLUSH BIT1
+#define EFI_ACPI_4_0_PROC_C1 BIT2
+#define EFI_ACPI_4_0_P_LVL2_UP BIT3
+#define EFI_ACPI_4_0_PWR_BUTTON BIT4
+#define EFI_ACPI_4_0_SLP_BUTTON BIT5
+#define EFI_ACPI_4_0_FIX_RTC BIT6
+#define EFI_ACPI_4_0_RTC_S4 BIT7
+#define EFI_ACPI_4_0_TMR_VAL_EXT BIT8
+#define EFI_ACPI_4_0_DCK_CAP BIT9
+#define EFI_ACPI_4_0_RESET_REG_SUP BIT10
+#define EFI_ACPI_4_0_SEALED_CASE BIT11
+#define EFI_ACPI_4_0_HEADLESS BIT12
+#define EFI_ACPI_4_0_CPU_SW_SLP BIT13
+#define EFI_ACPI_4_0_PCI_EXP_WAK BIT14
+#define EFI_ACPI_4_0_USE_PLATFORM_CLOCK BIT15
+#define EFI_ACPI_4_0_S4_RTC_STS_VALID BIT16
+#define EFI_ACPI_4_0_REMOTE_POWER_ON_CAPABLE BIT17
+#define EFI_ACPI_4_0_FORCE_APIC_CLUSTER_MODEL BIT18
+#define EFI_ACPI_4_0_FORCE_APIC_PHYSICAL_DESTINATION_MODE BIT19
+
+///
+/// Firmware ACPI Control Structure
+///
+typedef struct {
+ UINT32 Signature;
+ UINT32 Length;
+ UINT32 HardwareSignature;
+ UINT32 FirmwareWakingVector;
+ UINT32 GlobalLock;
+ UINT32 Flags;
+ UINT64 XFirmwareWakingVector;
+ UINT8 Version;
+ UINT8 Reserved0[3];
+ UINT32 OspmFlags;
+ UINT8 Reserved1[24];
+} EFI_ACPI_4_0_FIRMWARE_ACPI_CONTROL_STRUCTURE;
+
+///
+/// FACS Version (as defined in ACPI 4.0 spec.)
+///
+#define EFI_ACPI_4_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_VERSION 0x02
+
+///
+/// Firmware Control Structure Feature Flags
+/// All other bits are reserved and must be set to 0.
+///
+#define EFI_ACPI_4_0_S4BIOS_F BIT0
+#define EFI_ACPI_4_0_64BIT_WAKE_SUPPORTED_F BIT1
+
+///
+/// OSPM Enabled Firmware Control Structure Flags
+/// All other bits are reserved and must be set to 0.
+///
+#define EFI_ACPI_4_0_OSPM_64BIT_WAKE__F BIT0
+
+//
+// Differentiated System Description Table,
+// Secondary System Description Table
+// and Persistent System Description Table,
+// no definition needed as they are common description table header, the same with
+// EFI_ACPI_DESCRIPTION_HEADER, followed by a definition block.
+//
+#define EFI_ACPI_4_0_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x02
+#define EFI_ACPI_4_0_SECONDARY_SYSTEM_DESCRIPTION_TABLE_REVISION 0x02
+
+///
+/// Multiple APIC Description Table header definition. The rest of the table
+/// must be defined in a platform specific manner.
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 LocalApicAddress;
+ UINT32 Flags;
+} EFI_ACPI_4_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER;
+
+///
+/// MADT Revision (as defined in ACPI 4.0 spec.)
+///
+#define EFI_ACPI_4_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION 0x03
+
+///
+/// Multiple APIC Flags
+/// All other bits are reserved and must be set to 0.
+///
+#define EFI_ACPI_4_0_PCAT_COMPAT BIT0
+
+//
+// Multiple APIC Description Table APIC structure types
+// All other values between 0x0B an 0xFF are reserved and
+// will be ignored by OSPM.
+//
+#define EFI_ACPI_4_0_PROCESSOR_LOCAL_APIC 0x00
+#define EFI_ACPI_4_0_IO_APIC 0x01
+#define EFI_ACPI_4_0_INTERRUPT_SOURCE_OVERRIDE 0x02
+#define EFI_ACPI_4_0_NON_MASKABLE_INTERRUPT_SOURCE 0x03
+#define EFI_ACPI_4_0_LOCAL_APIC_NMI 0x04
+#define EFI_ACPI_4_0_LOCAL_APIC_ADDRESS_OVERRIDE 0x05
+#define EFI_ACPI_4_0_IO_SAPIC 0x06
+#define EFI_ACPI_4_0_LOCAL_SAPIC 0x07
+#define EFI_ACPI_4_0_PLATFORM_INTERRUPT_SOURCES 0x08
+#define EFI_ACPI_4_0_PROCESSOR_LOCAL_X2APIC 0x09
+#define EFI_ACPI_4_0_LOCAL_X2APIC_NMI 0x0A
+
+//
+// APIC Structure Definitions
+//
+
+///
+/// Processor Local APIC Structure Definition
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 AcpiProcessorId;
+ UINT8 ApicId;
+ UINT32 Flags;
+} EFI_ACPI_4_0_PROCESSOR_LOCAL_APIC_STRUCTURE;
+
+///
+/// Local APIC Flags. All other bits are reserved and must be 0.
+///
+#define EFI_ACPI_4_0_LOCAL_APIC_ENABLED BIT0
+
+///
+/// IO APIC Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 IoApicId;
+ UINT8 Reserved;
+ UINT32 IoApicAddress;
+ UINT32 GlobalSystemInterruptBase;
+} EFI_ACPI_4_0_IO_APIC_STRUCTURE;
+
+///
+/// Interrupt Source Override Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 Bus;
+ UINT8 Source;
+ UINT32 GlobalSystemInterrupt;
+ UINT16 Flags;
+} EFI_ACPI_4_0_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE;
+
+///
+/// Platform Interrupt Sources Structure Definition
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Flags;
+ UINT8 InterruptType;
+ UINT8 ProcessorId;
+ UINT8 ProcessorEid;
+ UINT8 IoSapicVector;
+ UINT32 GlobalSystemInterrupt;
+ UINT32 PlatformInterruptSourceFlags;
+ UINT8 CpeiProcessorOverride;
+ UINT8 Reserved[31];
+} EFI_ACPI_4_0_PLATFORM_INTERRUPT_APIC_STRUCTURE;
+
+//
+// MPS INTI flags.
+// All other bits are reserved and must be set to 0.
+//
+#define EFI_ACPI_4_0_POLARITY (3 << 0)
+#define EFI_ACPI_4_0_TRIGGER_MODE (3 << 2)
+
+///
+/// Non-Maskable Interrupt Source Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Flags;
+ UINT32 GlobalSystemInterrupt;
+} EFI_ACPI_4_0_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE;
+
+///
+/// Local APIC NMI Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 AcpiProcessorId;
+ UINT16 Flags;
+ UINT8 LocalApicLint;
+} EFI_ACPI_4_0_LOCAL_APIC_NMI_STRUCTURE;
+
+///
+/// Local APIC Address Override Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Reserved;
+ UINT64 LocalApicAddress;
+} EFI_ACPI_4_0_LOCAL_APIC_ADDRESS_OVERRIDE_STRUCTURE;
+
+///
+/// IO SAPIC Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 IoApicId;
+ UINT8 Reserved;
+ UINT32 GlobalSystemInterruptBase;
+ UINT64 IoSapicAddress;
+} EFI_ACPI_4_0_IO_SAPIC_STRUCTURE;
+
+///
+/// Local SAPIC Structure
+/// This struct followed by a null-terminated ASCII string - ACPI Processor UID String
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 AcpiProcessorId;
+ UINT8 LocalSapicId;
+ UINT8 LocalSapicEid;
+ UINT8 Reserved[3];
+ UINT32 Flags;
+ UINT32 ACPIProcessorUIDValue;
+} EFI_ACPI_4_0_PROCESSOR_LOCAL_SAPIC_STRUCTURE;
+
+///
+/// Platform Interrupt Sources Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Flags;
+ UINT8 InterruptType;
+ UINT8 ProcessorId;
+ UINT8 ProcessorEid;
+ UINT8 IoSapicVector;
+ UINT32 GlobalSystemInterrupt;
+ UINT32 PlatformInterruptSourceFlags;
+} EFI_ACPI_4_0_PLATFORM_INTERRUPT_SOURCES_STRUCTURE;
+
+///
+/// Platform Interrupt Source Flags.
+/// All other bits are reserved and must be set to 0.
+///
+#define EFI_ACPI_4_0_CPEI_PROCESSOR_OVERRIDE BIT0
+
+///
+/// Processor Local x2APIC Structure Definition
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 Reserved[2];
+ UINT32 X2ApicId;
+ UINT32 Flags;
+ UINT32 AcpiProcessorUid;
+} EFI_ACPI_4_0_PROCESSOR_LOCAL_X2APIC_STRUCTURE;
+
+///
+/// Local x2APIC NMI Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Flags;
+ UINT32 AcpiProcessorUid;
+ UINT8 LocalX2ApicLint;
+ UINT8 Reserved[3];
+} EFI_ACPI_4_0_LOCAL_X2APIC_NMI_STRUCTURE;
+
+///
+/// Smart Battery Description Table (SBST)
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 WarningEnergyLevel;
+ UINT32 LowEnergyLevel;
+ UINT32 CriticalEnergyLevel;
+} EFI_ACPI_4_0_SMART_BATTERY_DESCRIPTION_TABLE;
+
+///
+/// SBST Version (as defined in ACPI 4.0 spec.)
+///
+#define EFI_ACPI_4_0_SMART_BATTERY_DESCRIPTION_TABLE_REVISION 0x01
+
+///
+/// Embedded Controller Boot Resources Table (ECDT)
+/// The table is followed by a null terminated ASCII string that contains
+/// a fully qualified reference to the name space object.
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ EFI_ACPI_4_0_GENERIC_ADDRESS_STRUCTURE EcControl;
+ EFI_ACPI_4_0_GENERIC_ADDRESS_STRUCTURE EcData;
+ UINT32 Uid;
+ UINT8 GpeBit;
+} EFI_ACPI_4_0_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE;
+
+///
+/// ECDT Version (as defined in ACPI 4.0 spec.)
+///
+#define EFI_ACPI_4_0_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE_REVISION 0x01
+
+///
+/// System Resource Affinity Table (SRAT. The rest of the table
+/// must be defined in a platform specific manner.
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 Reserved1; ///< Must be set to 1
+ UINT64 Reserved2;
+} EFI_ACPI_4_0_SYSTEM_RESOURCE_AFFINITY_TABLE_HEADER;
+
+///
+/// SRAT Version (as defined in ACPI 4.0 spec.)
+///
+#define EFI_ACPI_4_0_SYSTEM_RESOURCE_AFFINITY_TABLE_REVISION 0x03
+
+//
+// SRAT structure types.
+// All other values between 0x03 an 0xFF are reserved and
+// will be ignored by OSPM.
+//
+#define EFI_ACPI_4_0_PROCESSOR_LOCAL_APIC_SAPIC_AFFINITY 0x00
+#define EFI_ACPI_4_0_MEMORY_AFFINITY 0x01
+#define EFI_ACPI_4_0_PROCESSOR_LOCAL_X2APIC_AFFINITY 0x02
+
+///
+/// Processor Local APIC/SAPIC Affinity Structure Definition
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 ProximityDomain7To0;
+ UINT8 ApicId;
+ UINT32 Flags;
+ UINT8 LocalSapicEid;
+ UINT8 ProximityDomain31To8[3];
+ UINT32 ClockDomain;
+} EFI_ACPI_4_0_PROCESSOR_LOCAL_APIC_SAPIC_AFFINITY_STRUCTURE;
+
+///
+/// Local APIC/SAPIC Flags. All other bits are reserved and must be 0.
+///
+#define EFI_ACPI_4_0_PROCESSOR_LOCAL_APIC_SAPIC_ENABLED (1 << 0)
+
+///
+/// Memory Affinity Structure Definition
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT32 ProximityDomain;
+ UINT16 Reserved1;
+ UINT32 AddressBaseLow;
+ UINT32 AddressBaseHigh;
+ UINT32 LengthLow;
+ UINT32 LengthHigh;
+ UINT32 Reserved2;
+ UINT32 Flags;
+ UINT64 Reserved3;
+} EFI_ACPI_4_0_MEMORY_AFFINITY_STRUCTURE;
+
+//
+// Memory Flags. All other bits are reserved and must be 0.
+//
+#define EFI_ACPI_4_0_MEMORY_ENABLED (1 << 0)
+#define EFI_ACPI_4_0_MEMORY_HOT_PLUGGABLE (1 << 1)
+#define EFI_ACPI_4_0_MEMORY_NONVOLATILE (1 << 2)
+
+///
+/// Processor Local x2APIC Affinity Structure Definition
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 Reserved1[2];
+ UINT32 ProximityDomain;
+ UINT32 X2ApicId;
+ UINT32 Flags;
+ UINT32 ClockDomain;
+ UINT8 Reserved2[4];
+} EFI_ACPI_4_0_PROCESSOR_LOCAL_X2APIC_AFFINITY_STRUCTURE;
+
+///
+/// System Locality Distance Information Table (SLIT).
+/// The rest of the table is a matrix.
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT64 NumberOfSystemLocalities;
+} EFI_ACPI_4_0_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_HEADER;
+
+///
+/// SLIT Version (as defined in ACPI 4.0 spec.)
+///
+#define EFI_ACPI_4_0_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_REVISION 0x01
+
+///
+/// Corrected Platform Error Polling Table (CPEP)
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT8 Reserved[8];
+} EFI_ACPI_4_0_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_HEADER;
+
+///
+/// CPEP Version (as defined in ACPI 4.0 spec.)
+///
+#define EFI_ACPI_4_0_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_REVISION 0x01
+
+//
+// CPEP processor structure types.
+//
+#define EFI_ACPI_4_0_CPEP_PROCESSOR_APIC_SAPIC 0x00
+
+///
+/// Corrected Platform Error Polling Processor Structure Definition
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 ProcessorId;
+ UINT8 ProcessorEid;
+ UINT32 PollingInterval;
+} EFI_ACPI_4_0_CPEP_PROCESSOR_APIC_SAPIC_STRUCTURE;
+
+///
+/// Maximum System Characteristics Table (MSCT)
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 OffsetProxDomInfo;
+ UINT32 MaximumNumberOfProximityDomains;
+ UINT32 MaximumNumberOfClockDomains;
+ UINT64 MaximumPhysicalAddress;
+} EFI_ACPI_4_0_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_HEADER;
+
+///
+/// MSCT Version (as defined in ACPI 4.0 spec.)
+///
+#define EFI_ACPI_4_0_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_REVISION 0x01
+
+///
+/// Maximum Proximity Domain Information Structure Definition
+///
+typedef struct {
+ UINT8 Revision;
+ UINT8 Length;
+ UINT32 ProximityDomainRangeLow;
+ UINT32 ProximityDomainRangeHigh;
+ UINT32 MaximumProcessorCapacity;
+ UINT64 MaximumMemoryCapacity;
+} EFI_ACPI_4_0_MAXIMUM_PROXIMITY_DOMAIN_INFORMATION_STRUCTURE;
+
+///
+/// Boot Error Record Table (BERT)
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 BootErrorRegionLength;
+ UINT64 BootErrorRegion;
+} EFI_ACPI_4_0_BOOT_ERROR_RECORD_TABLE_HEADER;
+
+///
+/// BERT Version (as defined in ACPI 4.0 spec.)
+///
+#define EFI_ACPI_4_0_BOOT_ERROR_RECORD_TABLE_REVISION 0x01
+
+///
+/// Boot Error Region Block Status Definition
+///
+typedef struct {
+ UINT32 UncorrectableErrorValid : 1;
+ UINT32 CorrectableErrorValid : 1;
+ UINT32 MultipleUncorrectableErrors : 1;
+ UINT32 MultipleCorrectableErrors : 1;
+ UINT32 ErrorDataEntryCount : 10;
+ UINT32 Reserved : 18;
+} EFI_ACPI_4_0_ERROR_BLOCK_STATUS;
+
+///
+/// Boot Error Region Definition
+///
+typedef struct {
+ EFI_ACPI_4_0_ERROR_BLOCK_STATUS BlockStatus;
+ UINT32 RawDataOffset;
+ UINT32 RawDataLength;
+ UINT32 DataLength;
+ UINT32 ErrorSeverity;
+} EFI_ACPI_4_0_BOOT_ERROR_REGION_STRUCTURE;
+
+//
+// Boot Error Severity types
+//
+#define EFI_ACPI_4_0_ERROR_SEVERITY_CORRECTABLE 0x00
+#define EFI_ACPI_4_0_ERROR_SEVERITY_RECOVERABLE 0x00
+#define EFI_ACPI_4_0_ERROR_SEVERITY_FATAL 0x01
+#define EFI_ACPI_4_0_ERROR_SEVERITY_CORRECTED 0x02
+#define EFI_ACPI_4_0_ERROR_SEVERITY_NONE 0x03
+
+///
+/// Generic Error Data Entry Definition
+///
+typedef struct {
+ UINT8 SectionType[16];
+ UINT32 ErrorSeverity;
+ UINT16 Revision;
+ UINT8 ValidationBits;
+ UINT8 Flags;
+ UINT32 ErrorDataLength;
+ UINT8 FruId[16];
+ UINT8 FruText[20];
+} EFI_ACPI_4_0_GENERIC_ERROR_DATA_ENTRY_STRUCTURE;
+
+///
+/// Generic Error Data Entry Version (as defined in ACPI 4.0 spec.)
+///
+#define EFI_ACPI_4_0_GENERIC_ERROR_DATA_ENTRY_REVISION 0x0201
+
+///
+/// HEST - Hardware Error Source Table
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 ErrorSourceCount;
+} EFI_ACPI_4_0_HARDWARE_ERROR_SOURCE_TABLE_HEADER;
+
+///
+/// HEST Version (as defined in ACPI 4.0 spec.)
+///
+#define EFI_ACPI_4_0_HARDWARE_ERROR_SOURCE_TABLE_REVISION 0x01
+
+//
+// Error Source structure types.
+//
+#define EFI_ACPI_4_0_IA32_ARCHITECTURE_MACHINE_CHECK_EXCEPTION 0x00
+#define EFI_ACPI_4_0_IA32_ARCHITECTURE_CORRECTED_MACHINE_CHECK 0x01
+#define EFI_ACPI_4_0_IA32_ARCHITECTURE_NMI_ERROR 0x02
+#define EFI_ACPI_4_0_PCI_EXPRESS_ROOT_PORT_AER 0x06
+#define EFI_ACPI_4_0_PCI_EXPRESS_DEVICE_AER 0x07
+#define EFI_ACPI_4_0_PCI_EXPRESS_BRIDGE_AER 0x08
+#define EFI_ACPI_4_0_GENERIC_HARDWARE_ERROR 0x09
+
+//
+// Error Source structure flags.
+//
+#define EFI_ACPI_4_0_ERROR_SOURCE_FLAG_FIRMWARE_FIRST (1 << 0)
+#define EFI_ACPI_4_0_ERROR_SOURCE_FLAG_GLOBAL (1 << 1)
+
+///
+/// IA-32 Architecture Machine Check Exception Structure Definition
+///
+typedef struct {
+ UINT16 Type;
+ UINT16 SourceId;
+ UINT8 Reserved0[2];
+ UINT8 Flags;
+ UINT8 Enabled;
+ UINT32 NumberOfRecordsToPreAllocate;
+ UINT32 MaxSectionsPerRecord;
+ UINT64 GlobalCapabilityInitData;
+ UINT64 GlobalControlInitData;
+ UINT8 NumberOfHardwareBanks;
+ UINT8 Reserved1[7];
+} EFI_ACPI_4_0_IA32_ARCHITECTURE_MACHINE_CHECK_EXCEPTION_STRUCTURE;
+
+///
+/// IA-32 Architecture Machine Check Bank Structure Definition
+///
+typedef struct {
+ UINT8 BankNumber;
+ UINT8 ClearStatusOnInitialization;
+ UINT8 StatusDataFormat;
+ UINT8 Reserved0;
+ UINT32 ControlRegisterMsrAddress;
+ UINT64 ControlInitData;
+ UINT32 StatusRegisterMsrAddress;
+ UINT32 AddressRegisterMsrAddress;
+ UINT32 MiscRegisterMsrAddress;
+} EFI_ACPI_4_0_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_BANK_STRUCTURE;
+
+///
+/// IA-32 Architecture Machine Check Bank Structure MCA data format
+///
+#define EFI_ACPI_4_0_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_IA32 0x00
+#define EFI_ACPI_4_0_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_INTEL64 0x01
+#define EFI_ACPI_4_0_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_AMD64 0x02
+
+//
+// Hardware Error Notification types. All other values are reserved
+//
+#define EFI_ACPI_4_0_HARDWARE_ERROR_NOTIFICATION_POLLED 0x00
+#define EFI_ACPI_4_0_HARDWARE_ERROR_NOTIFICATION_EXTERNAL_INTERRUPT 0x01
+#define EFI_ACPI_4_0_HARDWARE_ERROR_NOTIFICATION_LOCAL_INTERRUPT 0x02
+#define EFI_ACPI_4_0_HARDWARE_ERROR_NOTIFICATION_SCI 0x03
+#define EFI_ACPI_4_0_HARDWARE_ERROR_NOTIFICATION_NMI 0x04
+
+///
+/// Hardware Error Notification Configuration Write Enable Structure Definition
+///
+typedef struct {
+ UINT16 Type : 1;
+ UINT16 PollInterval : 1;
+ UINT16 SwitchToPollingThresholdValue : 1;
+ UINT16 SwitchToPollingThresholdWindow : 1;
+ UINT16 ErrorThresholdValue : 1;
+ UINT16 ErrorThresholdWindow : 1;
+ UINT16 Reserved : 10;
+} EFI_ACPI_4_0_HARDWARE_ERROR_NOTIFICATION_CONFIGURATION_WRITE_ENABLE_STRUCTURE;
+
+///
+/// Hardware Error Notification Structure Definition
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ EFI_ACPI_4_0_HARDWARE_ERROR_NOTIFICATION_CONFIGURATION_WRITE_ENABLE_STRUCTURE ConfigurationWriteEnable;
+ UINT32 PollInterval;
+ UINT32 Vector;
+ UINT32 SwitchToPollingThresholdValue;
+ UINT32 SwitchToPollingThresholdWindow;
+ UINT32 ErrorThresholdValue;
+ UINT32 ErrorThresholdWindow;
+} EFI_ACPI_4_0_HARDWARE_ERROR_NOTIFICATION_STRUCTURE;
+
+///
+/// IA-32 Architecture Corrected Machine Check Structure Definition
+///
+typedef struct {
+ UINT16 Type;
+ UINT16 SourceId;
+ UINT8 Reserved0[2];
+ UINT8 Flags;
+ UINT8 Enabled;
+ UINT32 NumberOfRecordsToPreAllocate;
+ UINT32 MaxSectionsPerRecord;
+ EFI_ACPI_4_0_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure;
+ UINT8 NumberOfHardwareBanks;
+ UINT8 Reserved1[3];
+} EFI_ACPI_4_0_IA32_ARCHITECTURE_CORRECTED_MACHINE_CHECK_STRUCTURE;
+
+///
+/// IA-32 Architecture NMI Error Structure Definition
+///
+typedef struct {
+ UINT16 Type;
+ UINT16 SourceId;
+ UINT8 Reserved0[2];
+ UINT32 NumberOfRecordsToPreAllocate;
+ UINT32 MaxSectionsPerRecord;
+ UINT32 MaxRawDataLength;
+} EFI_ACPI_4_0_IA32_ARCHITECTURE_NMI_ERROR_STRUCTURE;
+
+///
+/// PCI Express Root Port AER Structure Definition
+///
+typedef struct {
+ UINT16 Type;
+ UINT16 SourceId;
+ UINT8 Reserved0[2];
+ UINT8 Flags;
+ UINT8 Enabled;
+ UINT32 NumberOfRecordsToPreAllocate;
+ UINT32 MaxSectionsPerRecord;
+ UINT32 Bus;
+ UINT16 Device;
+ UINT16 Function;
+ UINT16 DeviceControl;
+ UINT8 Reserved1[2];
+ UINT32 UncorrectableErrorMask;
+ UINT32 UncorrectableErrorSeverity;
+ UINT32 CorrectableErrorMask;
+ UINT32 AdvancedErrorCapabilitiesAndControl;
+ UINT32 RootErrorCommand;
+} EFI_ACPI_4_0_PCI_EXPRESS_ROOT_PORT_AER_STRUCTURE;
+
+///
+/// PCI Express Device AER Structure Definition
+///
+typedef struct {
+ UINT16 Type;
+ UINT16 SourceId;
+ UINT8 Reserved0[2];
+ UINT8 Flags;
+ UINT8 Enabled;
+ UINT32 NumberOfRecordsToPreAllocate;
+ UINT32 MaxSectionsPerRecord;
+ UINT32 Bus;
+ UINT16 Device;
+ UINT16 Function;
+ UINT16 DeviceControl;
+ UINT8 Reserved1[2];
+ UINT32 UncorrectableErrorMask;
+ UINT32 UncorrectableErrorSeverity;
+ UINT32 CorrectableErrorMask;
+ UINT32 AdvancedErrorCapabilitiesAndControl;
+} EFI_ACPI_4_0_PCI_EXPRESS_DEVICE_AER_STRUCTURE;
+
+///
+/// PCI Express Bridge AER Structure Definition
+///
+typedef struct {
+ UINT16 Type;
+ UINT16 SourceId;
+ UINT8 Reserved0[2];
+ UINT8 Flags;
+ UINT8 Enabled;
+ UINT32 NumberOfRecordsToPreAllocate;
+ UINT32 MaxSectionsPerRecord;
+ UINT32 Bus;
+ UINT16 Device;
+ UINT16 Function;
+ UINT16 DeviceControl;
+ UINT8 Reserved1[2];
+ UINT32 UncorrectableErrorMask;
+ UINT32 UncorrectableErrorSeverity;
+ UINT32 CorrectableErrorMask;
+ UINT32 AdvancedErrorCapabilitiesAndControl;
+ UINT32 SecondaryUncorrectableErrorMask;
+ UINT32 SecondaryUncorrectableErrorSeverity;
+ UINT32 SecondaryAdvancedErrorCapabilitiesAndControl;
+} EFI_ACPI_4_0_PCI_EXPRESS_BRIDGE_AER_STRUCTURE;
+
+///
+/// Generic Hardware Error Source Structure Definition
+///
+typedef struct {
+ UINT16 Type;
+ UINT16 SourceId;
+ UINT16 RelatedSourceId;
+ UINT8 Flags;
+ UINT8 Enabled;
+ UINT32 NumberOfRecordsToPreAllocate;
+ UINT32 MaxSectionsPerRecord;
+ UINT32 MaxRawDataLength;
+ EFI_ACPI_4_0_GENERIC_ADDRESS_STRUCTURE ErrorStatusAddress;
+ EFI_ACPI_4_0_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure;
+ UINT32 ErrorStatusBlockLength;
+} EFI_ACPI_4_0_GENERIC_HARDWARE_ERROR_SOURCE_STRUCTURE;
+
+///
+/// Generic Error Status Definition
+///
+typedef struct {
+ EFI_ACPI_4_0_ERROR_BLOCK_STATUS BlockStatus;
+ UINT32 RawDataOffset;
+ UINT32 RawDataLength;
+ UINT32 DataLength;
+ UINT32 ErrorSeverity;
+} EFI_ACPI_4_0_GENERIC_ERROR_STATUS_STRUCTURE;
+
+///
+/// ERST - Error Record Serialization Table
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 SerializationHeaderSize;
+ UINT8 Reserved0[4];
+ UINT32 InstructionEntryCount;
+} EFI_ACPI_4_0_ERROR_RECORD_SERIALIZATION_TABLE_HEADER;
+
+///
+/// ERST Version (as defined in ACPI 4.0 spec.)
+///
+#define EFI_ACPI_4_0_ERROR_RECORD_SERIALIZATION_TABLE_REVISION 0x01
+
+///
+/// ERST Serialization Actions
+///
+#define EFI_ACPI_4_0_ERST_BEGIN_WRITE_OPERATION 0x00
+#define EFI_ACPI_4_0_ERST_BEGIN_READ_OPERATION 0x01
+#define EFI_ACPI_4_0_ERST_BEGIN_CLEAR_OPERATION 0x02
+#define EFI_ACPI_4_0_ERST_END_OPERATION 0x03
+#define EFI_ACPI_4_0_ERST_SET_RECORD_OFFSET 0x04
+#define EFI_ACPI_4_0_ERST_EXECUTE_OPERATION 0x05
+#define EFI_ACPI_4_0_ERST_CHECK_BUSY_STATUS 0x06
+#define EFI_ACPI_4_0_ERST_GET_COMMAND_STATUS 0x07
+#define EFI_ACPI_4_0_ERST_GET_RECORD_IDENTIFIER 0x08
+#define EFI_ACPI_4_0_ERST_SET_RECORD_IDENTIFIER 0x09
+#define EFI_ACPI_4_0_ERST_GET_RECORD_COUNT 0x0A
+#define EFI_ACPI_4_0_ERST_BEGIN_DUMMY_WRITE_OPERATION 0x0B
+#define EFI_ACPI_4_0_ERST_GET_ERROR_LOG_ADDRESS_RANGE 0x0D
+#define EFI_ACPI_4_0_ERST_GET_ERROR_LOG_ADDRESS_RANGE_LENGTH 0x0E
+#define EFI_ACPI_4_0_ERST_GET_ERROR_LOG_ADDRESS_RANGE_ATTRIBUTES 0x0F
+
+///
+/// ERST Action Command Status
+///
+#define EFI_ACPI_4_0_EINJ_STATUS_SUCCESS 0x00
+#define EFI_ACPI_4_0_EINJ_STATUS_NOT_ENOUGH_SPACE 0x01
+#define EFI_ACPI_4_0_EINJ_STATUS_HARDWARE_NOT_AVAILABLE 0x02
+#define EFI_ACPI_4_0_EINJ_STATUS_FAILED 0x03
+#define EFI_ACPI_4_0_EINJ_STATUS_RECORD_STORE_EMPTY 0x04
+#define EFI_ACPI_4_0_EINJ_STATUS_RECORD_NOT_FOUND 0x05
+
+///
+/// ERST Serialization Instructions
+///
+#define EFI_ACPI_4_0_ERST_READ_REGISTER 0x00
+#define EFI_ACPI_4_0_ERST_READ_REGISTER_VALUE 0x01
+#define EFI_ACPI_4_0_ERST_WRITE_REGISTER 0x02
+#define EFI_ACPI_4_0_ERST_WRITE_REGISTER_VALUE 0x03
+#define EFI_ACPI_4_0_ERST_NOOP 0x04
+#define EFI_ACPI_4_0_ERST_LOAD_VAR1 0x05
+#define EFI_ACPI_4_0_ERST_LOAD_VAR2 0x06
+#define EFI_ACPI_4_0_ERST_STORE_VAR1 0x07
+#define EFI_ACPI_4_0_ERST_ADD 0x08
+#define EFI_ACPI_4_0_ERST_SUBTRACT 0x09
+#define EFI_ACPI_4_0_ERST_ADD_VALUE 0x0A
+#define EFI_ACPI_4_0_ERST_SUBTRACT_VALUE 0x0B
+#define EFI_ACPI_4_0_ERST_STALL 0x0C
+#define EFI_ACPI_4_0_ERST_STALL_WHILE_TRUE 0x0D
+#define EFI_ACPI_4_0_ERST_SKIP_NEXT_INSTRUCTION_IF_TRUE 0x0E
+#define EFI_ACPI_4_0_ERST_GOTO 0x0F
+#define EFI_ACPI_4_0_ERST_SET_SRC_ADDRESS_BASE 0x10
+#define EFI_ACPI_4_0_ERST_SET_DST_ADDRESS_BASE 0x11
+#define EFI_ACPI_4_0_ERST_MOVE_DATA 0x12
+
+///
+/// ERST Instruction Flags
+///
+#define EFI_ACPI_4_0_ERST_PRESERVE_REGISTER 0x01
+
+///
+/// ERST Serialization Instruction Entry
+///
+typedef struct {
+ UINT8 SerializationAction;
+ UINT8 Instruction;
+ UINT8 Flags;
+ UINT8 Reserved0;
+ EFI_ACPI_4_0_GENERIC_ADDRESS_STRUCTURE RegisterRegion;
+ UINT64 Value;
+ UINT64 Mask;
+} EFI_ACPI_4_0_ERST_SERIALIZATION_INSTRUCTION_ENTRY;
+
+///
+/// EINJ - Error Injection Table
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 InjectionHeaderSize;
+ UINT8 InjectionFlags;
+ UINT8 Reserved0[3];
+ UINT32 InjectionEntryCount;
+} EFI_ACPI_4_0_ERROR_INJECTION_TABLE_HEADER;
+
+///
+/// EINJ Version (as defined in ACPI 4.0 spec.)
+///
+#define EFI_ACPI_4_0_ERROR_INJECTION_TABLE_REVISION 0x01
+
+///
+/// EINJ Error Injection Actions
+///
+#define EFI_ACPI_4_0_EINJ_BEGIN_INJECTION_OPERATION 0x00
+#define EFI_ACPI_4_0_EINJ_GET_TRIGGER_ERROR_ACTION_TABLE 0x01
+#define EFI_ACPI_4_0_EINJ_SET_ERROR_TYPE 0x02
+#define EFI_ACPI_4_0_EINJ_GET_ERROR_TYPE 0x03
+#define EFI_ACPI_4_0_EINJ_END_OPERATION 0x04
+#define EFI_ACPI_4_0_EINJ_EXECUTE_OPERATION 0x05
+#define EFI_ACPI_4_0_EINJ_CHECK_BUSY_STATUS 0x06
+#define EFI_ACPI_4_0_EINJ_GET_COMMAND_STATUS 0x07
+#define EFI_ACPI_4_0_EINJ_TRIGGER_ERROR 0xFF
+
+///
+/// EINJ Action Command Status
+///
+#define EFI_ACPI_4_0_EINJ_STATUS_SUCCESS 0x00
+#define EFI_ACPI_4_0_EINJ_STATUS_UNKNOWN_FAILURE 0x01
+#define EFI_ACPI_4_0_EINJ_STATUS_INVALID_ACCESS 0x02
+
+///
+/// EINJ Error Type Definition
+///
+#define EFI_ACPI_4_0_EINJ_ERROR_PROCESSOR_CORRECTABLE (1 << 0)
+#define EFI_ACPI_4_0_EINJ_ERROR_PROCESSOR_UNCORRECTABLE_NONFATAL (1 << 1)
+#define EFI_ACPI_4_0_EINJ_ERROR_PROCESSOR_UNCORRECTABLE_FATAL (1 << 2)
+#define EFI_ACPI_4_0_EINJ_ERROR_MEMORY_CORRECTABLE (1 << 3)
+#define EFI_ACPI_4_0_EINJ_ERROR_MEMORY_UNCORRECTABLE_NONFATAL (1 << 4)
+#define EFI_ACPI_4_0_EINJ_ERROR_MEMORY_UNCORRECTABLE_FATAL (1 << 5)
+#define EFI_ACPI_4_0_EINJ_ERROR_PCI_EXPRESS_CORRECTABLE (1 << 6)
+#define EFI_ACPI_4_0_EINJ_ERROR_PCI_EXPRESS_UNCORRECTABLE_NONFATAL (1 << 7)
+#define EFI_ACPI_4_0_EINJ_ERROR_PCI_EXPRESS_UNCORRECTABLE_FATAL (1 << 8)
+#define EFI_ACPI_4_0_EINJ_ERROR_PLATFORM_CORRECTABLE (1 << 9)
+#define EFI_ACPI_4_0_EINJ_ERROR_PLATFORM_UNCORRECTABLE_NONFATAL (1 << 10)
+#define EFI_ACPI_4_0_EINJ_ERROR_PLATFORM_UNCORRECTABLE_FATAL (1 << 11)
+
+///
+/// EINJ Injection Instructions
+///
+#define EFI_ACPI_4_0_EINJ_READ_REGISTER 0x00
+#define EFI_ACPI_4_0_EINJ_READ_REGISTER_VALUE 0x01
+#define EFI_ACPI_4_0_EINJ_WRITE_REGISTER 0x02
+#define EFI_ACPI_4_0_EINJ_WRITE_REGISTER_VALUE 0x03
+#define EFI_ACPI_4_0_EINJ_NOOP 0x04
+
+///
+/// EINJ Instruction Flags
+///
+#define EFI_ACPI_4_0_EINJ_PRESERVE_REGISTER 0x01
+
+///
+/// EINJ Injection Instruction Entry
+///
+typedef struct {
+ UINT8 InjectionAction;
+ UINT8 Instruction;
+ UINT8 Flags;
+ UINT8 Reserved0;
+ EFI_ACPI_4_0_GENERIC_ADDRESS_STRUCTURE RegisterRegion;
+ UINT64 Value;
+ UINT64 Mask;
+} EFI_ACPI_4_0_EINJ_INJECTION_INSTRUCTION_ENTRY;
+
+///
+/// EINJ Trigger Action Table
+///
+typedef struct {
+ UINT32 HeaderSize;
+ UINT32 Revision;
+ UINT32 TableSize;
+ UINT32 EntryCount;
+} EFI_ACPI_4_0_EINJ_TRIGGER_ACTION_TABLE;
+
+//
+// Known table signatures
+//
+
+///
+/// "RSD PTR " Root System Description Pointer
+///
+#define EFI_ACPI_4_0_ROOT_SYSTEM_DESCRIPTION_POINTER_SIGNATURE SIGNATURE_64('R', 'S', 'D', ' ', 'P', 'T', 'R', ' ')
+
+///
+/// "APIC" Multiple APIC Description Table
+///
+#define EFI_ACPI_4_0_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('A', 'P', 'I', 'C')
+
+///
+/// "BERT" Boot Error Record Table
+///
+#define EFI_ACPI_4_0_BOOT_ERROR_RECORD_TABLE_SIGNATURE SIGNATURE_32('B', 'E', 'R', 'T')
+
+///
+/// "CPEP" Corrected Platform Error Polling Table
+///
+#define EFI_ACPI_4_0_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_SIGNATURE SIGNATURE_32('C', 'P', 'E', 'P')
+
+///
+/// "DSDT" Differentiated System Description Table
+///
+#define EFI_ACPI_4_0_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('D', 'S', 'D', 'T')
+
+///
+/// "ECDT" Embedded Controller Boot Resources Table
+///
+#define EFI_ACPI_4_0_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE_SIGNATURE SIGNATURE_32('E', 'C', 'D', 'T')
+
+///
+/// "EINJ" Error Injection Table
+///
+#define EFI_ACPI_4_0_ERROR_INJECTION_TABLE_SIGNATURE SIGNATURE_32('E', 'I', 'N', 'J')
+
+///
+/// "ERST" Error Record Serialization Table
+///
+#define EFI_ACPI_4_0_ERROR_RECORD_SERIALIZATION_TABLE_SIGNATURE SIGNATURE_32('E', 'R', 'S', 'T')
+
+///
+/// "FACP" Fixed ACPI Description Table
+///
+#define EFI_ACPI_4_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('F', 'A', 'C', 'P')
+
+///
+/// "FACS" Firmware ACPI Control Structure
+///
+#define EFI_ACPI_4_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_SIGNATURE SIGNATURE_32('F', 'A', 'C', 'S')
+
+///
+/// "HEST" Hardware Error Source Table
+///
+#define EFI_ACPI_4_0_HARDWARE_ERROR_SOURCE_TABLE_SIGNATURE SIGNATURE_32('H', 'E', 'S', 'T')
+
+///
+/// "MSCT" Maximum System Characteristics Table
+///
+#define EFI_ACPI_4_0_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_SIGNATURE SIGNATURE_32('M', 'S', 'C', 'T')
+
+///
+/// "PSDT" Persistent System Description Table
+///
+#define EFI_ACPI_4_0_PERSISTENT_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('P', 'S', 'D', 'T')
+
+///
+/// "RSDT" Root System Description Table
+///
+#define EFI_ACPI_4_0_ROOT_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('R', 'S', 'D', 'T')
+
+///
+/// "SBST" Smart Battery Specification Table
+///
+#define EFI_ACPI_4_0_SMART_BATTERY_SPECIFICATION_TABLE_SIGNATURE SIGNATURE_32('S', 'B', 'S', 'T')
+
+///
+/// "SLIT" System Locality Information Table
+///
+#define EFI_ACPI_4_0_SYSTEM_LOCALITY_INFORMATION_TABLE_SIGNATURE SIGNATURE_32('S', 'L', 'I', 'T')
+
+///
+/// "SRAT" System Resource Affinity Table
+///
+#define EFI_ACPI_4_0_SYSTEM_RESOURCE_AFFINITY_TABLE_SIGNATURE SIGNATURE_32('S', 'R', 'A', 'T')
+
+///
+/// "SSDT" Secondary System Description Table
+///
+#define EFI_ACPI_4_0_SECONDARY_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('S', 'S', 'D', 'T')
+
+///
+/// "XSDT" Extended System Description Table
+///
+#define EFI_ACPI_4_0_EXTENDED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('X', 'S', 'D', 'T')
+
+///
+/// "BOOT" MS Simple Boot Spec
+///
+#define EFI_ACPI_4_0_SIMPLE_BOOT_FLAG_TABLE_SIGNATURE SIGNATURE_32('B', 'O', 'O', 'T')
+
+///
+/// "DBGP" MS Debug Port Spec
+///
+#define EFI_ACPI_4_0_DEBUG_PORT_TABLE_SIGNATURE SIGNATURE_32('D', 'B', 'G', 'P')
+
+///
+/// "DMAR" DMA Remapping Table
+///
+#define EFI_ACPI_4_0_DMA_REMAPPING_TABLE_SIGNATURE SIGNATURE_32('D', 'M', 'A', 'R')
+
+///
+/// "ETDT" Event Timer Description Table
+///
+#define EFI_ACPI_4_0_EVENT_TIMER_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('E', 'T', 'D', 'T')
+
+///
+/// "HPET" IA-PC High Precision Event Timer Table
+///
+#define EFI_ACPI_4_0_HIGH_PRECISION_EVENT_TIMER_TABLE_SIGNATURE SIGNATURE_32('H', 'P', 'E', 'T')
+
+///
+/// "iBFT" iSCSI Boot Firmware Table
+///
+#define EFI_ACPI_4_0_ISCSI_BOOT_FIRMWARE_TABLE_SIGNATURE SIGNATURE_32('i', 'B', 'F', 'T')
+
+///
+/// "IVRS" I/O Virtualization Reporting Structure
+///
+#define EFI_ACPI_4_0_IO_VIRTUALIZATION_REPORTING_STRUCTURE_SIGNATURE SIGNATURE_32('I', 'V', 'R', 'S')
+
+///
+/// "MCFG" PCI Express Memory Mapped Configuration Space Base Address Description Table
+///
+#define EFI_ACPI_4_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('M', 'C', 'F', 'G')
+
+///
+/// "MCHI" Management Controller Host Interface Table
+///
+#define EFI_ACPI_4_0_MANAGEMENT_CONTROLLER_HOST_INTERFACE_TABLE_SIGNATURE SIGNATURE_32('M', 'C', 'H', 'I')
+
+///
+/// "SPCR" Serial Port Console Redirection Table
+///
+#define EFI_ACPI_4_0_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE SIGNATURE_32('S', 'P', 'C', 'R')
+
+///
+/// "SPMI" Server Platform Management Interface Table
+///
+#define EFI_ACPI_4_0_SERVER_PLATFORM_MANAGEMENT_INTERFACE_TABLE_SIGNATURE SIGNATURE_32('S', 'P', 'M', 'I')
+
+///
+/// "TCPA" Trusted Computing Platform Alliance Capabilities Table
+///
+#define EFI_ACPI_4_0_TRUSTED_COMPUTING_PLATFORM_ALLIANCE_CAPABILITIES_TABLE_SIGNATURE SIGNATURE_32('T', 'C', 'P', 'A')
+
+///
+/// "UEFI" UEFI ACPI Data Table
+///
+#define EFI_ACPI_4_0_UEFI_ACPI_DATA_TABLE_SIGNATURE SIGNATURE_32('U', 'E', 'F', 'I')
+
+///
+/// "WAET" Windows ACPI Enlightenment Table
+///
+#define EFI_ACPI_4_0_WINDOWS_ACPI_ENLIGHTENMENT_TABLE_SIGNATURE SIGNATURE_32('W', 'A', 'E', 'T')
+
+///
+/// "WDAT" Watchdog Action Table
+///
+#define EFI_ACPI_4_0_WATCHDOG_ACTION_TABLE_SIGNATURE SIGNATURE_32('W', 'D', 'A', 'T')
+
+///
+/// "WDRT" Watchdog Resource Table
+///
+#define EFI_ACPI_4_0_WATCHDOG_RESOURCE_TABLE_SIGNATURE SIGNATURE_32('W', 'D', 'R', 'T')
+
+#pragma pack()
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/Acpi50.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/Acpi50.h
new file mode 100644
index 0000000000..e02daf64b7
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/Acpi50.h
@@ -0,0 +1,2120 @@
+/** @file
+ ACPI 5.0 definitions from the ACPI Specification Revision 5.0a November 13, 2013.
+
+ Copyright (c) 2014 Hewlett-Packard Development Company, L.P.
+ Copyright (c) 2011 - 2022, Intel Corporation. All rights reserved.
+ Copyright (c) 2020, ARM Ltd. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _ACPI_5_0_H_
+#define _ACPI_5_0_H_
+
+#include
+
+//
+// Define for Descriptor
+//
+#define ACPI_SMALL_FIXED_DMA_DESCRIPTOR_NAME 0x0A
+#define ACPI_LARGE_GPIO_CONNECTION_DESCRIPTOR_NAME 0x0C
+#define ACPI_LARGE_GENERIC_SERIAL_BUS_CONNECTION_DESCRIPTOR_NAME 0x0E
+
+#define ACPI_FIXED_DMA_DESCRIPTOR 0x55
+#define ACPI_GPIO_CONNECTION_DESCRIPTOR 0x8C
+#define ACPI_GENERIC_SERIAL_BUS_CONNECTION_DESCRIPTOR 0x8E
+
+#pragma pack(1)
+
+///
+/// Generic DMA Descriptor.
+///
+typedef PACKED struct {
+ ACPI_SMALL_RESOURCE_HEADER Header;
+ UINT16 DmaRequestLine;
+ UINT16 DmaChannel;
+ UINT8 DmaTransferWidth;
+} EFI_ACPI_FIXED_DMA_DESCRIPTOR;
+
+///
+/// GPIO Connection Descriptor
+///
+typedef PACKED struct {
+ ACPI_LARGE_RESOURCE_HEADER Header;
+ UINT8 RevisionId;
+ UINT8 ConnectionType;
+ UINT16 GeneralFlags;
+ UINT16 InterruptFlags;
+ UINT8 PinConfiguration;
+ UINT16 OutputDriveStrength;
+ UINT16 DebounceTimeout;
+ UINT16 PinTableOffset;
+ UINT8 ResourceSourceIndex;
+ UINT16 ResourceSourceNameOffset;
+ UINT16 VendorDataOffset;
+ UINT16 VendorDataLength;
+} EFI_ACPI_GPIO_CONNECTION_DESCRIPTOR;
+
+#define EFI_ACPI_GPIO_CONNECTION_TYPE_INTERRUPT 0x0
+#define EFI_ACPI_GPIO_CONNECTION_TYPE_IO 0x1
+
+///
+/// Serial Bus Resource Descriptor (Generic)
+///
+typedef PACKED struct {
+ ACPI_LARGE_RESOURCE_HEADER Header;
+ UINT8 RevisionId;
+ UINT8 ResourceSourceIndex;
+ UINT8 SerialBusType;
+ UINT8 GeneralFlags;
+ UINT16 TypeSpecificFlags;
+ UINT8 TypeSpecificRevisionId;
+ UINT16 TypeDataLength;
+ // Type specific data
+} EFI_ACPI_SERIAL_BUS_RESOURCE_DESCRIPTOR;
+
+#define EFI_ACPI_SERIAL_BUS_RESOURCE_TYPE_I2C 0x1
+#define EFI_ACPI_SERIAL_BUS_RESOURCE_TYPE_SPI 0x2
+#define EFI_ACPI_SERIAL_BUS_RESOURCE_TYPE_UART 0x3
+
+///
+/// Serial Bus Resource Descriptor (I2C)
+///
+typedef PACKED struct {
+ ACPI_LARGE_RESOURCE_HEADER Header;
+ UINT8 RevisionId;
+ UINT8 ResourceSourceIndex;
+ UINT8 SerialBusType;
+ UINT8 GeneralFlags;
+ UINT16 TypeSpecificFlags;
+ UINT8 TypeSpecificRevisionId;
+ UINT16 TypeDataLength;
+ UINT32 ConnectionSpeed;
+ UINT16 SlaveAddress;
+} EFI_ACPI_SERIAL_BUS_RESOURCE_I2C_DESCRIPTOR;
+
+///
+/// Serial Bus Resource Descriptor (SPI)
+///
+typedef PACKED struct {
+ ACPI_LARGE_RESOURCE_HEADER Header;
+ UINT8 RevisionId;
+ UINT8 ResourceSourceIndex;
+ UINT8 SerialBusType;
+ UINT8 GeneralFlags;
+ UINT16 TypeSpecificFlags;
+ UINT8 TypeSpecificRevisionId;
+ UINT16 TypeDataLength;
+ UINT32 ConnectionSpeed;
+ UINT8 DataBitLength;
+ UINT8 Phase;
+ UINT8 Polarity;
+ UINT16 DeviceSelection;
+} EFI_ACPI_SERIAL_BUS_RESOURCE_SPI_DESCRIPTOR;
+
+///
+/// Serial Bus Resource Descriptor (UART)
+///
+typedef PACKED struct {
+ ACPI_LARGE_RESOURCE_HEADER Header;
+ UINT8 RevisionId;
+ UINT8 ResourceSourceIndex;
+ UINT8 SerialBusType;
+ UINT8 GeneralFlags;
+ UINT16 TypeSpecificFlags;
+ UINT8 TypeSpecificRevisionId;
+ UINT16 TypeDataLength;
+ UINT32 DefaultBaudRate;
+ UINT16 RxFIFO;
+ UINT16 TxFIFO;
+ UINT8 Parity;
+ UINT8 SerialLinesEnabled;
+} EFI_ACPI_SERIAL_BUS_RESOURCE_UART_DESCRIPTOR;
+
+#pragma pack()
+
+//
+// Ensure proper structure formats
+//
+#pragma pack(1)
+
+///
+/// ACPI 5.0 Generic Address Space definition
+///
+typedef struct {
+ UINT8 AddressSpaceId;
+ UINT8 RegisterBitWidth;
+ UINT8 RegisterBitOffset;
+ UINT8 AccessSize;
+ UINT64 Address;
+} EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE;
+
+//
+// Generic Address Space Address IDs
+//
+#define EFI_ACPI_5_0_SYSTEM_MEMORY 0
+#define EFI_ACPI_5_0_SYSTEM_IO 1
+#define EFI_ACPI_5_0_PCI_CONFIGURATION_SPACE 2
+#define EFI_ACPI_5_0_EMBEDDED_CONTROLLER 3
+#define EFI_ACPI_5_0_SMBUS 4
+#define EFI_ACPI_5_0_PLATFORM_COMMUNICATION_CHANNEL 0x0A
+#define EFI_ACPI_5_0_FUNCTIONAL_FIXED_HARDWARE 0x7F
+
+//
+// Generic Address Space Access Sizes
+//
+#define EFI_ACPI_5_0_UNDEFINED 0
+#define EFI_ACPI_5_0_BYTE 1
+#define EFI_ACPI_5_0_WORD 2
+#define EFI_ACPI_5_0_DWORD 3
+#define EFI_ACPI_5_0_QWORD 4
+
+//
+// ACPI 5.0 table structures
+//
+
+///
+/// Root System Description Pointer Structure
+///
+typedef struct {
+ UINT64 Signature;
+ UINT8 Checksum;
+ UINT8 OemId[6];
+ UINT8 Revision;
+ UINT32 RsdtAddress;
+ UINT32 Length;
+ UINT64 XsdtAddress;
+ UINT8 ExtendedChecksum;
+ UINT8 Reserved[3];
+} EFI_ACPI_5_0_ROOT_SYSTEM_DESCRIPTION_POINTER;
+
+///
+/// RSD_PTR Revision (as defined in ACPI 5.0 spec.)
+///
+#define EFI_ACPI_5_0_ROOT_SYSTEM_DESCRIPTION_POINTER_REVISION 0x02 ///< ACPISpec (Revision 5.0) says current value is 2
+
+///
+/// Common table header, this prefaces all ACPI tables, including FACS, but
+/// excluding the RSD PTR structure
+///
+typedef struct {
+ UINT32 Signature;
+ UINT32 Length;
+} EFI_ACPI_5_0_COMMON_HEADER;
+
+//
+// Root System Description Table
+// No definition needed as it is a common description table header, the same with
+// EFI_ACPI_DESCRIPTION_HEADER, followed by a variable number of UINT32 table pointers.
+//
+
+///
+/// RSDT Revision (as defined in ACPI 5.0 spec.)
+///
+#define EFI_ACPI_5_0_ROOT_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01
+
+//
+// Extended System Description Table
+// No definition needed as it is a common description table header, the same with
+// EFI_ACPI_DESCRIPTION_HEADER, followed by a variable number of UINT64 table pointers.
+//
+
+///
+/// XSDT Revision (as defined in ACPI 5.0 spec.)
+///
+#define EFI_ACPI_5_0_EXTENDED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01
+
+///
+/// Fixed ACPI Description Table Structure (FADT)
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 FirmwareCtrl;
+ UINT32 Dsdt;
+ UINT8 Reserved0;
+ UINT8 PreferredPmProfile;
+ UINT16 SciInt;
+ UINT32 SmiCmd;
+ UINT8 AcpiEnable;
+ UINT8 AcpiDisable;
+ UINT8 S4BiosReq;
+ UINT8 PstateCnt;
+ UINT32 Pm1aEvtBlk;
+ UINT32 Pm1bEvtBlk;
+ UINT32 Pm1aCntBlk;
+ UINT32 Pm1bCntBlk;
+ UINT32 Pm2CntBlk;
+ UINT32 PmTmrBlk;
+ UINT32 Gpe0Blk;
+ UINT32 Gpe1Blk;
+ UINT8 Pm1EvtLen;
+ UINT8 Pm1CntLen;
+ UINT8 Pm2CntLen;
+ UINT8 PmTmrLen;
+ UINT8 Gpe0BlkLen;
+ UINT8 Gpe1BlkLen;
+ UINT8 Gpe1Base;
+ UINT8 CstCnt;
+ UINT16 PLvl2Lat;
+ UINT16 PLvl3Lat;
+ UINT16 FlushSize;
+ UINT16 FlushStride;
+ UINT8 DutyOffset;
+ UINT8 DutyWidth;
+ UINT8 DayAlrm;
+ UINT8 MonAlrm;
+ UINT8 Century;
+ UINT16 IaPcBootArch;
+ UINT8 Reserved1;
+ UINT32 Flags;
+ EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE ResetReg;
+ UINT8 ResetValue;
+ UINT8 Reserved2[3];
+ UINT64 XFirmwareCtrl;
+ UINT64 XDsdt;
+ EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPm1aEvtBlk;
+ EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPm1bEvtBlk;
+ EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPm1aCntBlk;
+ EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPm1bCntBlk;
+ EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPm2CntBlk;
+ EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPmTmrBlk;
+ EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XGpe0Blk;
+ EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XGpe1Blk;
+ EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE SleepControlReg;
+ EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE SleepStatusReg;
+} EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE;
+
+///
+/// FADT Version (as defined in ACPI 5.0 spec.)
+///
+#define EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE_REVISION 0x05
+
+//
+// Fixed ACPI Description Table Preferred Power Management Profile
+//
+#define EFI_ACPI_5_0_PM_PROFILE_UNSPECIFIED 0
+#define EFI_ACPI_5_0_PM_PROFILE_DESKTOP 1
+#define EFI_ACPI_5_0_PM_PROFILE_MOBILE 2
+#define EFI_ACPI_5_0_PM_PROFILE_WORKSTATION 3
+#define EFI_ACPI_5_0_PM_PROFILE_ENTERPRISE_SERVER 4
+#define EFI_ACPI_5_0_PM_PROFILE_SOHO_SERVER 5
+#define EFI_ACPI_5_0_PM_PROFILE_APPLIANCE_PC 6
+#define EFI_ACPI_5_0_PM_PROFILE_PERFORMANCE_SERVER 7
+#define EFI_ACPI_5_0_PM_PROFILE_TABLET 8
+
+//
+// Fixed ACPI Description Table Boot Architecture Flags
+// All other bits are reserved and must be set to 0.
+//
+#define EFI_ACPI_5_0_LEGACY_DEVICES BIT0
+#define EFI_ACPI_5_0_8042 BIT1
+#define EFI_ACPI_5_0_VGA_NOT_PRESENT BIT2
+#define EFI_ACPI_5_0_MSI_NOT_SUPPORTED BIT3
+#define EFI_ACPI_5_0_PCIE_ASPM_CONTROLS BIT4
+#define EFI_ACPI_5_0_CMOS_RTC_NOT_PRESENT BIT5
+
+//
+// Fixed ACPI Description Table Fixed Feature Flags
+// All other bits are reserved and must be set to 0.
+//
+#define EFI_ACPI_5_0_WBINVD BIT0
+#define EFI_ACPI_5_0_WBINVD_FLUSH BIT1
+#define EFI_ACPI_5_0_PROC_C1 BIT2
+#define EFI_ACPI_5_0_P_LVL2_UP BIT3
+#define EFI_ACPI_5_0_PWR_BUTTON BIT4
+#define EFI_ACPI_5_0_SLP_BUTTON BIT5
+#define EFI_ACPI_5_0_FIX_RTC BIT6
+#define EFI_ACPI_5_0_RTC_S4 BIT7
+#define EFI_ACPI_5_0_TMR_VAL_EXT BIT8
+#define EFI_ACPI_5_0_DCK_CAP BIT9
+#define EFI_ACPI_5_0_RESET_REG_SUP BIT10
+#define EFI_ACPI_5_0_SEALED_CASE BIT11
+#define EFI_ACPI_5_0_HEADLESS BIT12
+#define EFI_ACPI_5_0_CPU_SW_SLP BIT13
+#define EFI_ACPI_5_0_PCI_EXP_WAK BIT14
+#define EFI_ACPI_5_0_USE_PLATFORM_CLOCK BIT15
+#define EFI_ACPI_5_0_S4_RTC_STS_VALID BIT16
+#define EFI_ACPI_5_0_REMOTE_POWER_ON_CAPABLE BIT17
+#define EFI_ACPI_5_0_FORCE_APIC_CLUSTER_MODEL BIT18
+#define EFI_ACPI_5_0_FORCE_APIC_PHYSICAL_DESTINATION_MODE BIT19
+#define EFI_ACPI_5_0_HW_REDUCED_ACPI BIT20
+#define EFI_ACPI_5_0_LOW_POWER_S0_IDLE_CAPABLE BIT21
+
+///
+/// Firmware ACPI Control Structure
+///
+typedef struct {
+ UINT32 Signature;
+ UINT32 Length;
+ UINT32 HardwareSignature;
+ UINT32 FirmwareWakingVector;
+ UINT32 GlobalLock;
+ UINT32 Flags;
+ UINT64 XFirmwareWakingVector;
+ UINT8 Version;
+ UINT8 Reserved0[3];
+ UINT32 OspmFlags;
+ UINT8 Reserved1[24];
+} EFI_ACPI_5_0_FIRMWARE_ACPI_CONTROL_STRUCTURE;
+
+///
+/// FACS Version (as defined in ACPI 5.0 spec.)
+///
+#define EFI_ACPI_5_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_VERSION 0x02
+
+///
+/// Firmware Control Structure Feature Flags
+/// All other bits are reserved and must be set to 0.
+///
+#define EFI_ACPI_5_0_S4BIOS_F BIT0
+#define EFI_ACPI_5_0_64BIT_WAKE_SUPPORTED_F BIT1
+
+///
+/// OSPM Enabled Firmware Control Structure Flags
+/// All other bits are reserved and must be set to 0.
+///
+#define EFI_ACPI_5_0_OSPM_64BIT_WAKE_F BIT0
+
+//
+// Differentiated System Description Table,
+// Secondary System Description Table
+// and Persistent System Description Table,
+// no definition needed as they are common description table header, the same with
+// EFI_ACPI_DESCRIPTION_HEADER, followed by a definition block.
+//
+#define EFI_ACPI_5_0_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x02
+#define EFI_ACPI_5_0_SECONDARY_SYSTEM_DESCRIPTION_TABLE_REVISION 0x02
+
+///
+/// Multiple APIC Description Table header definition. The rest of the table
+/// must be defined in a platform specific manner.
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 LocalApicAddress;
+ UINT32 Flags;
+} EFI_ACPI_5_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER;
+
+///
+/// MADT Revision (as defined in ACPI 5.0 spec.)
+///
+#define EFI_ACPI_5_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION 0x03
+
+///
+/// Multiple APIC Flags
+/// All other bits are reserved and must be set to 0.
+///
+#define EFI_ACPI_5_0_PCAT_COMPAT BIT0
+
+//
+// Multiple APIC Description Table APIC structure types
+// All other values between 0x0D and 0x7F are reserved and
+// will be ignored by OSPM. 0x80 ~ 0xFF are reserved for OEM.
+//
+#define EFI_ACPI_5_0_PROCESSOR_LOCAL_APIC 0x00
+#define EFI_ACPI_5_0_IO_APIC 0x01
+#define EFI_ACPI_5_0_INTERRUPT_SOURCE_OVERRIDE 0x02
+#define EFI_ACPI_5_0_NON_MASKABLE_INTERRUPT_SOURCE 0x03
+#define EFI_ACPI_5_0_LOCAL_APIC_NMI 0x04
+#define EFI_ACPI_5_0_LOCAL_APIC_ADDRESS_OVERRIDE 0x05
+#define EFI_ACPI_5_0_IO_SAPIC 0x06
+#define EFI_ACPI_5_0_LOCAL_SAPIC 0x07
+#define EFI_ACPI_5_0_PLATFORM_INTERRUPT_SOURCES 0x08
+#define EFI_ACPI_5_0_PROCESSOR_LOCAL_X2APIC 0x09
+#define EFI_ACPI_5_0_LOCAL_X2APIC_NMI 0x0A
+#define EFI_ACPI_5_0_GIC 0x0B
+#define EFI_ACPI_5_0_GICD 0x0C
+
+//
+// APIC Structure Definitions
+//
+
+///
+/// Processor Local APIC Structure Definition
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 AcpiProcessorId;
+ UINT8 ApicId;
+ UINT32 Flags;
+} EFI_ACPI_5_0_PROCESSOR_LOCAL_APIC_STRUCTURE;
+
+///
+/// Local APIC Flags. All other bits are reserved and must be 0.
+///
+#define EFI_ACPI_5_0_LOCAL_APIC_ENABLED BIT0
+
+///
+/// IO APIC Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 IoApicId;
+ UINT8 Reserved;
+ UINT32 IoApicAddress;
+ UINT32 GlobalSystemInterruptBase;
+} EFI_ACPI_5_0_IO_APIC_STRUCTURE;
+
+///
+/// Interrupt Source Override Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 Bus;
+ UINT8 Source;
+ UINT32 GlobalSystemInterrupt;
+ UINT16 Flags;
+} EFI_ACPI_5_0_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE;
+
+///
+/// Platform Interrupt Sources Structure Definition
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Flags;
+ UINT8 InterruptType;
+ UINT8 ProcessorId;
+ UINT8 ProcessorEid;
+ UINT8 IoSapicVector;
+ UINT32 GlobalSystemInterrupt;
+ UINT32 PlatformInterruptSourceFlags;
+ UINT8 CpeiProcessorOverride;
+ UINT8 Reserved[31];
+} EFI_ACPI_5_0_PLATFORM_INTERRUPT_APIC_STRUCTURE;
+
+//
+// MPS INTI flags.
+// All other bits are reserved and must be set to 0.
+//
+#define EFI_ACPI_5_0_POLARITY (3 << 0)
+#define EFI_ACPI_5_0_TRIGGER_MODE (3 << 2)
+
+///
+/// Non-Maskable Interrupt Source Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Flags;
+ UINT32 GlobalSystemInterrupt;
+} EFI_ACPI_5_0_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE;
+
+///
+/// Local APIC NMI Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 AcpiProcessorId;
+ UINT16 Flags;
+ UINT8 LocalApicLint;
+} EFI_ACPI_5_0_LOCAL_APIC_NMI_STRUCTURE;
+
+///
+/// Local APIC Address Override Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Reserved;
+ UINT64 LocalApicAddress;
+} EFI_ACPI_5_0_LOCAL_APIC_ADDRESS_OVERRIDE_STRUCTURE;
+
+///
+/// IO SAPIC Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 IoApicId;
+ UINT8 Reserved;
+ UINT32 GlobalSystemInterruptBase;
+ UINT64 IoSapicAddress;
+} EFI_ACPI_5_0_IO_SAPIC_STRUCTURE;
+
+///
+/// Local SAPIC Structure
+/// This struct followed by a null-terminated ASCII string - ACPI Processor UID String
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 AcpiProcessorId;
+ UINT8 LocalSapicId;
+ UINT8 LocalSapicEid;
+ UINT8 Reserved[3];
+ UINT32 Flags;
+ UINT32 ACPIProcessorUIDValue;
+} EFI_ACPI_5_0_PROCESSOR_LOCAL_SAPIC_STRUCTURE;
+
+///
+/// Platform Interrupt Sources Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Flags;
+ UINT8 InterruptType;
+ UINT8 ProcessorId;
+ UINT8 ProcessorEid;
+ UINT8 IoSapicVector;
+ UINT32 GlobalSystemInterrupt;
+ UINT32 PlatformInterruptSourceFlags;
+} EFI_ACPI_5_0_PLATFORM_INTERRUPT_SOURCES_STRUCTURE;
+
+///
+/// Platform Interrupt Source Flags.
+/// All other bits are reserved and must be set to 0.
+///
+#define EFI_ACPI_5_0_CPEI_PROCESSOR_OVERRIDE BIT0
+
+///
+/// Processor Local x2APIC Structure Definition
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 Reserved[2];
+ UINT32 X2ApicId;
+ UINT32 Flags;
+ UINT32 AcpiProcessorUid;
+} EFI_ACPI_5_0_PROCESSOR_LOCAL_X2APIC_STRUCTURE;
+
+///
+/// Local x2APIC NMI Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Flags;
+ UINT32 AcpiProcessorUid;
+ UINT8 LocalX2ApicLint;
+ UINT8 Reserved[3];
+} EFI_ACPI_5_0_LOCAL_X2APIC_NMI_STRUCTURE;
+
+///
+/// GIC Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Reserved;
+ UINT32 GicId;
+ UINT32 AcpiProcessorUid;
+ UINT32 Flags;
+ UINT32 ParkingProtocolVersion;
+ UINT32 PerformanceInterruptGsiv;
+ UINT64 ParkedAddress;
+ UINT64 PhysicalBaseAddress;
+} EFI_ACPI_5_0_GIC_STRUCTURE;
+
+///
+/// GIC Flags. All other bits are reserved and must be 0.
+///
+#define EFI_ACPI_5_0_GIC_ENABLED BIT0
+#define EFI_ACPI_5_0_PERFORMANCE_INTERRUPT_MODEL BIT1
+
+///
+/// GIC Distributor Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Reserved1;
+ UINT32 GicId;
+ UINT64 PhysicalBaseAddress;
+ UINT32 SystemVectorBase;
+ UINT32 Reserved2;
+} EFI_ACPI_5_0_GIC_DISTRIBUTOR_STRUCTURE;
+
+///
+/// Smart Battery Description Table (SBST)
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 WarningEnergyLevel;
+ UINT32 LowEnergyLevel;
+ UINT32 CriticalEnergyLevel;
+} EFI_ACPI_5_0_SMART_BATTERY_DESCRIPTION_TABLE;
+
+///
+/// SBST Version (as defined in ACPI 5.0 spec.)
+///
+#define EFI_ACPI_5_0_SMART_BATTERY_DESCRIPTION_TABLE_REVISION 0x01
+
+///
+/// Embedded Controller Boot Resources Table (ECDT)
+/// The table is followed by a null terminated ASCII string that contains
+/// a fully qualified reference to the name space object.
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE EcControl;
+ EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE EcData;
+ UINT32 Uid;
+ UINT8 GpeBit;
+} EFI_ACPI_5_0_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE;
+
+///
+/// ECDT Version (as defined in ACPI 5.0 spec.)
+///
+#define EFI_ACPI_5_0_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE_REVISION 0x01
+
+///
+/// System Resource Affinity Table (SRAT). The rest of the table
+/// must be defined in a platform specific manner.
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 Reserved1; ///< Must be set to 1
+ UINT64 Reserved2;
+} EFI_ACPI_5_0_SYSTEM_RESOURCE_AFFINITY_TABLE_HEADER;
+
+///
+/// SRAT Version (as defined in ACPI 5.0 spec.)
+///
+#define EFI_ACPI_5_0_SYSTEM_RESOURCE_AFFINITY_TABLE_REVISION 0x03
+
+//
+// SRAT structure types.
+// All other values between 0x03 an 0xFF are reserved and
+// will be ignored by OSPM.
+//
+#define EFI_ACPI_5_0_PROCESSOR_LOCAL_APIC_SAPIC_AFFINITY 0x00
+#define EFI_ACPI_5_0_MEMORY_AFFINITY 0x01
+#define EFI_ACPI_5_0_PROCESSOR_LOCAL_X2APIC_AFFINITY 0x02
+
+///
+/// Processor Local APIC/SAPIC Affinity Structure Definition
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 ProximityDomain7To0;
+ UINT8 ApicId;
+ UINT32 Flags;
+ UINT8 LocalSapicEid;
+ UINT8 ProximityDomain31To8[3];
+ UINT32 ClockDomain;
+} EFI_ACPI_5_0_PROCESSOR_LOCAL_APIC_SAPIC_AFFINITY_STRUCTURE;
+
+///
+/// Local APIC/SAPIC Flags. All other bits are reserved and must be 0.
+///
+#define EFI_ACPI_5_0_PROCESSOR_LOCAL_APIC_SAPIC_ENABLED (1 << 0)
+
+///
+/// Memory Affinity Structure Definition
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT32 ProximityDomain;
+ UINT16 Reserved1;
+ UINT32 AddressBaseLow;
+ UINT32 AddressBaseHigh;
+ UINT32 LengthLow;
+ UINT32 LengthHigh;
+ UINT32 Reserved2;
+ UINT32 Flags;
+ UINT64 Reserved3;
+} EFI_ACPI_5_0_MEMORY_AFFINITY_STRUCTURE;
+
+//
+// Memory Flags. All other bits are reserved and must be 0.
+//
+#define EFI_ACPI_5_0_MEMORY_ENABLED (1 << 0)
+#define EFI_ACPI_5_0_MEMORY_HOT_PLUGGABLE (1 << 1)
+#define EFI_ACPI_5_0_MEMORY_NONVOLATILE (1 << 2)
+
+///
+/// Processor Local x2APIC Affinity Structure Definition
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 Reserved1[2];
+ UINT32 ProximityDomain;
+ UINT32 X2ApicId;
+ UINT32 Flags;
+ UINT32 ClockDomain;
+ UINT8 Reserved2[4];
+} EFI_ACPI_5_0_PROCESSOR_LOCAL_X2APIC_AFFINITY_STRUCTURE;
+
+///
+/// System Locality Distance Information Table (SLIT).
+/// The rest of the table is a matrix.
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT64 NumberOfSystemLocalities;
+} EFI_ACPI_5_0_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_HEADER;
+
+///
+/// SLIT Version (as defined in ACPI 5.0 spec.)
+///
+#define EFI_ACPI_5_0_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_REVISION 0x01
+
+///
+/// Corrected Platform Error Polling Table (CPEP)
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT8 Reserved[8];
+} EFI_ACPI_5_0_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_HEADER;
+
+///
+/// CPEP Version (as defined in ACPI 5.0 spec.)
+///
+#define EFI_ACPI_5_0_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_REVISION 0x01
+
+//
+// CPEP processor structure types.
+//
+#define EFI_ACPI_5_0_CPEP_PROCESSOR_APIC_SAPIC 0x00
+
+///
+/// Corrected Platform Error Polling Processor Structure Definition
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 ProcessorId;
+ UINT8 ProcessorEid;
+ UINT32 PollingInterval;
+} EFI_ACPI_5_0_CPEP_PROCESSOR_APIC_SAPIC_STRUCTURE;
+
+///
+/// Maximum System Characteristics Table (MSCT)
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 OffsetProxDomInfo;
+ UINT32 MaximumNumberOfProximityDomains;
+ UINT32 MaximumNumberOfClockDomains;
+ UINT64 MaximumPhysicalAddress;
+} EFI_ACPI_5_0_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_HEADER;
+
+///
+/// MSCT Version (as defined in ACPI 5.0 spec.)
+///
+#define EFI_ACPI_5_0_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_REVISION 0x01
+
+///
+/// Maximum Proximity Domain Information Structure Definition
+///
+typedef struct {
+ UINT8 Revision;
+ UINT8 Length;
+ UINT32 ProximityDomainRangeLow;
+ UINT32 ProximityDomainRangeHigh;
+ UINT32 MaximumProcessorCapacity;
+ UINT64 MaximumMemoryCapacity;
+} EFI_ACPI_5_0_MAXIMUM_PROXIMITY_DOMAIN_INFORMATION_STRUCTURE;
+
+///
+/// ACPI RAS Feature Table definition.
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT8 PlatformCommunicationChannelIdentifier[12];
+} EFI_ACPI_5_0_RAS_FEATURE_TABLE;
+
+///
+/// RASF Version (as defined in ACPI 5.0 spec.)
+///
+#define EFI_ACPI_5_0_RAS_FEATURE_TABLE_REVISION 0x01
+
+///
+/// ACPI RASF Platform Communication Channel Shared Memory Region definition.
+///
+typedef struct {
+ UINT32 Signature;
+ UINT16 Command;
+ UINT16 Status;
+ UINT16 Version;
+ UINT8 RASCapabilities[16];
+ UINT8 SetRASCapabilities[16];
+ UINT16 NumberOfRASFParameterBlocks;
+ UINT32 SetRASCapabilitiesStatus;
+} EFI_ACPI_5_0_RASF_PLATFORM_COMMUNICATION_CHANNEL_SHARED_MEMORY_REGION;
+
+///
+/// ACPI RASF PCC command code
+///
+#define EFI_ACPI_5_0_RASF_PCC_COMMAND_CODE_EXECUTE_RASF_COMMAND 0x01
+
+///
+/// ACPI RASF Platform RAS Capabilities
+///
+#define EFI_ACPI_5_0_RASF_PLATFORM_RAS_CAPABILITY_HARDWARE_BASED_PATROL_SCRUB_SUPPOTED 0x01
+#define EFI_ACPI_5_0_RASF_PLATFORM_RAS_CAPABILITY_HARDWARE_BASED_PATROL_SCRUB_SUPPOTED_AND_EXPOSED_TO_SOFTWARE 0x02
+
+///
+/// ACPI RASF Parameter Block structure for PATROL_SCRUB
+///
+typedef struct {
+ UINT16 Type;
+ UINT16 Version;
+ UINT16 Length;
+ UINT16 PatrolScrubCommand;
+ UINT64 RequestedAddressRange[2];
+ UINT64 ActualAddressRange[2];
+ UINT16 Flags;
+ UINT8 RequestedSpeed;
+} EFI_ACPI_5_0_RASF_PATROL_SCRUB_PLATFORM_BLOCK_STRUCTURE;
+
+///
+/// ACPI RASF Patrol Scrub command
+///
+#define EFI_ACPI_5_0_RASF_PATROL_SCRUB_COMMAND_GET_PATROL_PARAMETERS 0x01
+#define EFI_ACPI_5_0_RASF_PATROL_SCRUB_COMMAND_START_PATROL_SCRUBBER 0x02
+#define EFI_ACPI_5_0_RASF_PATROL_SCRUB_COMMAND_STOP_PATROL_SCRUBBER 0x03
+
+///
+/// Memory Power State Table definition.
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT8 PlatformCommunicationChannelIdentifier;
+ UINT8 Reserved[3];
+ // Memory Power Node Structure
+ // Memory Power State Characteristics
+} EFI_ACPI_5_0_MEMORY_POWER_STATUS_TABLE;
+
+///
+/// MPST Version (as defined in ACPI 5.0 spec.)
+///
+#define EFI_ACPI_5_0_MEMORY_POWER_STATE_TABLE_REVISION 0x01
+
+///
+/// MPST Platform Communication Channel Shared Memory Region definition.
+///
+typedef struct {
+ UINT32 Signature;
+ UINT16 Command;
+ UINT16 Status;
+ UINT32 MemoryPowerCommandRegister;
+ UINT32 MemoryPowerStatusRegister;
+ UINT32 PowerStateId;
+ UINT32 MemoryPowerNodeId;
+ UINT64 MemoryEnergyConsumed;
+ UINT64 ExpectedAveragePowerComsuned;
+} EFI_ACPI_5_0_MPST_PLATFORM_COMMUNICATION_CHANNEL_SHARED_MEMORY_REGION;
+
+///
+/// ACPI MPST PCC command code
+///
+#define EFI_ACPI_5_0_MPST_PCC_COMMAND_CODE_EXECUTE_MPST_COMMAND 0x03
+
+///
+/// ACPI MPST Memory Power command
+///
+#define EFI_ACPI_5_0_MPST_MEMORY_POWER_COMMAND_GET_MEMORY_POWER_STATE 0x01
+#define EFI_ACPI_5_0_MPST_MEMORY_POWER_COMMAND_SET_MEMORY_POWER_STATE 0x02
+#define EFI_ACPI_5_0_MPST_MEMORY_POWER_COMMAND_GET_AVERAGE_POWER_CONSUMED 0x03
+#define EFI_ACPI_5_0_MPST_MEMORY_POWER_COMMAND_GET_MEMORY_ENERGY_CONSUMED 0x04
+
+///
+/// MPST Memory Power Node Table
+///
+typedef struct {
+ UINT8 PowerStateValue;
+ UINT8 PowerStateInformationIndex;
+} EFI_ACPI_5_0_MPST_MEMORY_POWER_STATE;
+
+typedef struct {
+ UINT8 Flag;
+ UINT8 Reserved;
+ UINT16 MemoryPowerNodeId;
+ UINT32 Length;
+ UINT64 AddressBase;
+ UINT64 AddressLength;
+ UINT32 NumberOfPowerStates;
+ UINT32 NumberOfPhysicalComponents;
+ // EFI_ACPI_5_0_MPST_MEMORY_POWER_STATE MemoryPowerState[NumberOfPowerStates];
+ // UINT16 PhysicalComponentIdentifier[NumberOfPhysicalComponents];
+} EFI_ACPI_5_0_MPST_MEMORY_POWER_STRUCTURE;
+
+#define EFI_ACPI_5_0_MPST_MEMORY_POWER_STRUCTURE_FLAG_ENABLE 0x01
+#define EFI_ACPI_5_0_MPST_MEMORY_POWER_STRUCTURE_FLAG_POWER_MANAGED 0x02
+#define EFI_ACPI_5_0_MPST_MEMORY_POWER_STRUCTURE_FLAG_HOT_PLUGGABLE 0x04
+
+typedef struct {
+ UINT16 MemoryPowerNodeCount;
+ UINT8 Reserved[2];
+} EFI_ACPI_5_0_MPST_MEMORY_POWER_NODE_TABLE;
+
+///
+/// MPST Memory Power State Characteristics Table
+///
+typedef struct {
+ UINT8 PowerStateStructureID;
+ UINT8 Flag;
+ UINT16 Reserved;
+ UINT32 AveragePowerConsumedInMPS0;
+ UINT32 RelativePowerSavingToMPS0;
+ UINT64 ExitLatencyToMPS0;
+} EFI_ACPI_5_0_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE;
+
+#define EFI_ACPI_5_0_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_MEMORY_CONTENT_PRESERVED 0x01
+#define EFI_ACPI_5_0_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_AUTONOMOUS_MEMORY_POWER_STATE_ENTRY 0x02
+#define EFI_ACPI_5_0_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_AUTONOMOUS_MEMORY_POWER_STATE_EXIT 0x04
+
+typedef struct {
+ UINT16 MemoryPowerStateCharacteristicsCount;
+ UINT8 Reserved[2];
+} EFI_ACPI_5_0_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_TABLE;
+
+///
+/// Memory Topology Table definition.
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 Reserved;
+} EFI_ACPI_5_0_MEMORY_TOPOLOGY_TABLE;
+
+///
+/// PMTT Version (as defined in ACPI 5.0 spec.)
+///
+#define EFI_ACPI_5_0_MEMORY_TOPOLOGY_TABLE_REVISION 0x01
+
+///
+/// Common Memory Aggregator Device Structure.
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Reserved;
+ UINT16 Length;
+ UINT16 Flags;
+ UINT16 Reserved1;
+} EFI_ACPI_5_0_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE;
+
+///
+/// Memory Aggregator Device Type
+///
+#define EFI_ACPI_5_0_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_SOCKET 0x0
+#define EFI_ACPI_5_0_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_MEMORY_CONTROLLER 0x1
+#define EFI_ACPI_5_0_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_DIMM 0x2
+
+///
+/// Socket Memory Aggregator Device Structure.
+///
+typedef struct {
+ EFI_ACPI_5_0_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE Header;
+ UINT16 SocketIdentifier;
+ UINT16 Reserved;
+ // EFI_ACPI_5_0_PMMT_MEMORY_CONTROLLER_MEMORY_AGGREGATOR_DEVICE_STRUCTURE MemoryController[];
+} EFI_ACPI_5_0_PMMT_SOCKET_MEMORY_AGGREGATOR_DEVICE_STRUCTURE;
+
+///
+/// MemoryController Memory Aggregator Device Structure.
+///
+typedef struct {
+ EFI_ACPI_5_0_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE Header;
+ UINT32 ReadLatency;
+ UINT32 WriteLatency;
+ UINT32 ReadBandwidth;
+ UINT32 WriteBandwidth;
+ UINT16 OptimalAccessUnit;
+ UINT16 OptimalAccessAlignment;
+ UINT16 Reserved;
+ UINT16 NumberOfProximityDomains;
+ // UINT32 ProximityDomain[NumberOfProximityDomains];
+ // EFI_ACPI_5_0_PMMT_DIMM_MEMORY_AGGREGATOR_DEVICE_STRUCTURE PhysicalComponent[];
+} EFI_ACPI_5_0_PMMT_MEMORY_CONTROLLER_MEMORY_AGGREGATOR_DEVICE_STRUCTURE;
+
+///
+/// DIMM Memory Aggregator Device Structure.
+///
+typedef struct {
+ EFI_ACPI_5_0_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE Header;
+ UINT16 PhysicalComponentIdentifier;
+ UINT16 Reserved;
+ UINT32 SizeOfDimm;
+ UINT32 SmbiosHandle;
+} EFI_ACPI_5_0_PMMT_DIMM_MEMORY_AGGREGATOR_DEVICE_STRUCTURE;
+
+///
+/// Boot Graphics Resource Table definition.
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ ///
+ /// 2-bytes (16 bit) version ID. This value must be 1.
+ ///
+ UINT16 Version;
+ ///
+ /// 1-byte status field indicating current status about the table.
+ /// Bits[7:1] = Reserved (must be zero)
+ /// Bit [0] = Valid. A one indicates the boot image graphic is valid.
+ ///
+ UINT8 Status;
+ ///
+ /// 1-byte enumerated type field indicating format of the image.
+ /// 0 = Bitmap
+ /// 1 - 255 Reserved (for future use)
+ ///
+ UINT8 ImageType;
+ ///
+ /// 8-byte (64 bit) physical address pointing to the firmware's in-memory copy
+ /// of the image bitmap.
+ ///
+ UINT64 ImageAddress;
+ ///
+ /// A 4-byte (32-bit) unsigned long describing the display X-offset of the boot image.
+ /// (X, Y) display offset of the top left corner of the boot image.
+ /// The top left corner of the display is at offset (0, 0).
+ ///
+ UINT32 ImageOffsetX;
+ ///
+ /// A 4-byte (32-bit) unsigned long describing the display Y-offset of the boot image.
+ /// (X, Y) display offset of the top left corner of the boot image.
+ /// The top left corner of the display is at offset (0, 0).
+ ///
+ UINT32 ImageOffsetY;
+} EFI_ACPI_5_0_BOOT_GRAPHICS_RESOURCE_TABLE;
+
+///
+/// BGRT Revision
+///
+#define EFI_ACPI_5_0_BOOT_GRAPHICS_RESOURCE_TABLE_REVISION 1
+
+///
+/// BGRT Version
+///
+#define EFI_ACPI_5_0_BGRT_VERSION 0x01
+
+///
+/// BGRT Status
+///
+#define EFI_ACPI_5_0_BGRT_STATUS_NOT_DISPLAYED 0x00
+#define EFI_ACPI_5_0_BGRT_STATUS_DISPLAYED 0x01
+#define EFI_ACPI_5_0_BGRT_STATUS_INVALID EFI_ACPI_5_0_BGRT_STATUS_NOT_DISPLAYED
+#define EFI_ACPI_5_0_BGRT_STATUS_VALID EFI_ACPI_5_0_BGRT_STATUS_DISPLAYED
+
+///
+/// BGRT Image Type
+///
+#define EFI_ACPI_5_0_BGRT_IMAGE_TYPE_BMP 0x00
+
+///
+/// FPDT Version (as defined in ACPI 5.0 spec.)
+///
+#define EFI_ACPI_5_0_FIRMWARE_PERFORMANCE_DATA_TABLE_REVISION 0x01
+
+///
+/// FPDT Performance Record Types
+///
+#define EFI_ACPI_5_0_FPDT_RECORD_TYPE_FIRMWARE_BASIC_BOOT_POINTER 0x0000
+#define EFI_ACPI_5_0_FPDT_RECORD_TYPE_S3_PERFORMANCE_TABLE_POINTER 0x0001
+
+///
+/// FPDT Performance Record Revision
+///
+#define EFI_ACPI_5_0_FPDT_RECORD_REVISION_FIRMWARE_BASIC_BOOT_POINTER 0x01
+#define EFI_ACPI_5_0_FPDT_RECORD_REVISION_S3_PERFORMANCE_TABLE_POINTER 0x01
+
+///
+/// FPDT Runtime Performance Record Types
+///
+#define EFI_ACPI_5_0_FPDT_RUNTIME_RECORD_TYPE_S3_RESUME 0x0000
+#define EFI_ACPI_5_0_FPDT_RUNTIME_RECORD_TYPE_S3_SUSPEND 0x0001
+#define EFI_ACPI_5_0_FPDT_RUNTIME_RECORD_TYPE_FIRMWARE_BASIC_BOOT 0x0002
+
+///
+/// FPDT Runtime Performance Record Revision
+///
+#define EFI_ACPI_5_0_FPDT_RUNTIME_RECORD_REVISION_S3_RESUME 0x01
+#define EFI_ACPI_5_0_FPDT_RUNTIME_RECORD_REVISION_S3_SUSPEND 0x01
+#define EFI_ACPI_5_0_FPDT_RUNTIME_RECORD_REVISION_FIRMWARE_BASIC_BOOT 0x02
+
+///
+/// FPDT Performance Record header
+///
+typedef struct {
+ UINT16 Type;
+ UINT8 Length;
+ UINT8 Revision;
+} EFI_ACPI_5_0_FPDT_PERFORMANCE_RECORD_HEADER;
+
+///
+/// FPDT Performance Table header
+///
+typedef struct {
+ UINT32 Signature;
+ UINT32 Length;
+} EFI_ACPI_5_0_FPDT_PERFORMANCE_TABLE_HEADER;
+
+///
+/// FPDT Firmware Basic Boot Performance Pointer Record Structure
+///
+typedef struct {
+ EFI_ACPI_5_0_FPDT_PERFORMANCE_RECORD_HEADER Header;
+ UINT32 Reserved;
+ ///
+ /// 64-bit processor-relative physical address of the Basic Boot Performance Table.
+ ///
+ UINT64 BootPerformanceTablePointer;
+} EFI_ACPI_5_0_FPDT_BOOT_PERFORMANCE_TABLE_POINTER_RECORD;
+
+///
+/// FPDT S3 Performance Table Pointer Record Structure
+///
+typedef struct {
+ EFI_ACPI_5_0_FPDT_PERFORMANCE_RECORD_HEADER Header;
+ UINT32 Reserved;
+ ///
+ /// 64-bit processor-relative physical address of the S3 Performance Table.
+ ///
+ UINT64 S3PerformanceTablePointer;
+} EFI_ACPI_5_0_FPDT_S3_PERFORMANCE_TABLE_POINTER_RECORD;
+
+///
+/// FPDT Firmware Basic Boot Performance Record Structure
+///
+typedef struct {
+ EFI_ACPI_5_0_FPDT_PERFORMANCE_RECORD_HEADER Header;
+ UINT32 Reserved;
+ ///
+ /// Timer value logged at the beginning of firmware image execution.
+ /// This may not always be zero or near zero.
+ ///
+ UINT64 ResetEnd;
+ ///
+ /// Timer value logged just prior to loading the OS boot loader into memory.
+ /// For non-UEFI compatible boots, this field must be zero.
+ ///
+ UINT64 OsLoaderLoadImageStart;
+ ///
+ /// Timer value logged just prior to launching the previously loaded OS boot loader image.
+ /// For non-UEFI compatible boots, the timer value logged will be just prior
+ /// to the INT 19h handler invocation.
+ ///
+ UINT64 OsLoaderStartImageStart;
+ ///
+ /// Timer value logged at the point when the OS loader calls the
+ /// ExitBootServices function for UEFI compatible firmware.
+ /// For non-UEFI compatible boots, this field must be zero.
+ ///
+ UINT64 ExitBootServicesEntry;
+ ///
+ /// Timer value logged at the point just prior to when the OS loader gaining
+ /// control back from calls the ExitBootServices function for UEFI compatible firmware.
+ /// For non-UEFI compatible boots, this field must be zero.
+ ///
+ UINT64 ExitBootServicesExit;
+} EFI_ACPI_5_0_FPDT_FIRMWARE_BASIC_BOOT_RECORD;
+
+///
+/// FPDT Firmware Basic Boot Performance Table signature
+///
+#define EFI_ACPI_5_0_FPDT_BOOT_PERFORMANCE_TABLE_SIGNATURE SIGNATURE_32('F', 'B', 'P', 'T')
+
+//
+// FPDT Firmware Basic Boot Performance Table
+//
+typedef struct {
+ EFI_ACPI_5_0_FPDT_PERFORMANCE_TABLE_HEADER Header;
+ //
+ // one or more Performance Records.
+ //
+} EFI_ACPI_5_0_FPDT_FIRMWARE_BASIC_BOOT_TABLE;
+
+///
+/// FPDT "S3PT" S3 Performance Table
+///
+#define EFI_ACPI_5_0_FPDT_S3_PERFORMANCE_TABLE_SIGNATURE SIGNATURE_32('S', '3', 'P', 'T')
+
+//
+// FPDT Firmware S3 Boot Performance Table
+//
+typedef struct {
+ EFI_ACPI_5_0_FPDT_PERFORMANCE_TABLE_HEADER Header;
+ //
+ // one or more Performance Records.
+ //
+} EFI_ACPI_5_0_FPDT_FIRMWARE_S3_BOOT_TABLE;
+
+///
+/// FPDT Basic S3 Resume Performance Record
+///
+typedef struct {
+ EFI_ACPI_5_0_FPDT_PERFORMANCE_RECORD_HEADER Header;
+ ///
+ /// A count of the number of S3 resume cycles since the last full boot sequence.
+ ///
+ UINT32 ResumeCount;
+ ///
+ /// Timer recorded at the end of BIOS S3 resume, just prior to handoff to the
+ /// OS waking vector. Only the most recent resume cycle's time is retained.
+ ///
+ UINT64 FullResume;
+ ///
+ /// Average timer value of all resume cycles logged since the last full boot
+ /// sequence, including the most recent resume. Note that the entire log of
+ /// timer values does not need to be retained in order to calculate this average.
+ ///
+ UINT64 AverageResume;
+} EFI_ACPI_5_0_FPDT_S3_RESUME_RECORD;
+
+///
+/// FPDT Basic S3 Suspend Performance Record
+///
+typedef struct {
+ EFI_ACPI_5_0_FPDT_PERFORMANCE_RECORD_HEADER Header;
+ ///
+ /// Timer value recorded at the OS write to SLP_TYP upon entry to S3.
+ /// Only the most recent suspend cycle's timer value is retained.
+ ///
+ UINT64 SuspendStart;
+ ///
+ /// Timer value recorded at the final firmware write to SLP_TYP (or other
+ /// mechanism) used to trigger hardware entry to S3.
+ /// Only the most recent suspend cycle's timer value is retained.
+ ///
+ UINT64 SuspendEnd;
+} EFI_ACPI_5_0_FPDT_S3_SUSPEND_RECORD;
+
+///
+/// Firmware Performance Record Table definition.
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+} EFI_ACPI_5_0_FIRMWARE_PERFORMANCE_RECORD_TABLE;
+
+///
+/// Generic Timer Description Table definition.
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT64 PhysicalAddress;
+ UINT32 GlobalFlags;
+ UINT32 SecurePL1TimerGSIV;
+ UINT32 SecurePL1TimerFlags;
+ UINT32 NonSecurePL1TimerGSIV;
+ UINT32 NonSecurePL1TimerFlags;
+ UINT32 VirtualTimerGSIV;
+ UINT32 VirtualTimerFlags;
+ UINT32 NonSecurePL2TimerGSIV;
+ UINT32 NonSecurePL2TimerFlags;
+} EFI_ACPI_5_0_GENERIC_TIMER_DESCRIPTION_TABLE;
+
+///
+/// GTDT Version (as defined in ACPI 5.0 spec.)
+///
+#define EFI_ACPI_5_0_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION 0x01
+
+///
+/// Global Flags. All other bits are reserved and must be 0.
+///
+#define EFI_ACPI_5_0_GTDT_GLOBAL_FLAG_MEMORY_MAPPED_BLOCK_PRESENT BIT0
+#define EFI_ACPI_5_0_GTDT_GLOBAL_FLAG_INTERRUPT_MODE BIT1
+
+///
+/// Timer Flags. All other bits are reserved and must be 0.
+///
+#define EFI_ACPI_5_0_GTDT_TIMER_FLAG_TIMER_INTERRUPT_MODE BIT0
+#define EFI_ACPI_5_0_GTDT_TIMER_FLAG_TIMER_INTERRUPT_POLARITY BIT1
+
+///
+/// Boot Error Record Table (BERT)
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 BootErrorRegionLength;
+ UINT64 BootErrorRegion;
+} EFI_ACPI_5_0_BOOT_ERROR_RECORD_TABLE_HEADER;
+
+///
+/// BERT Version (as defined in ACPI 5.0 spec.)
+///
+#define EFI_ACPI_5_0_BOOT_ERROR_RECORD_TABLE_REVISION 0x01
+
+///
+/// Boot Error Region Block Status Definition
+///
+typedef struct {
+ UINT32 UncorrectableErrorValid : 1;
+ UINT32 CorrectableErrorValid : 1;
+ UINT32 MultipleUncorrectableErrors : 1;
+ UINT32 MultipleCorrectableErrors : 1;
+ UINT32 ErrorDataEntryCount : 10;
+ UINT32 Reserved : 18;
+} EFI_ACPI_5_0_ERROR_BLOCK_STATUS;
+
+///
+/// Boot Error Region Definition
+///
+typedef struct {
+ EFI_ACPI_5_0_ERROR_BLOCK_STATUS BlockStatus;
+ UINT32 RawDataOffset;
+ UINT32 RawDataLength;
+ UINT32 DataLength;
+ UINT32 ErrorSeverity;
+} EFI_ACPI_5_0_BOOT_ERROR_REGION_STRUCTURE;
+
+//
+// Boot Error Severity types
+//
+#define EFI_ACPI_5_0_ERROR_SEVERITY_CORRECTABLE 0x00
+#define EFI_ACPI_5_0_ERROR_SEVERITY_RECOVERABLE 0x00
+#define EFI_ACPI_5_0_ERROR_SEVERITY_FATAL 0x01
+#define EFI_ACPI_5_0_ERROR_SEVERITY_CORRECTED 0x02
+#define EFI_ACPI_5_0_ERROR_SEVERITY_NONE 0x03
+
+///
+/// Generic Error Data Entry Definition
+///
+typedef struct {
+ UINT8 SectionType[16];
+ UINT32 ErrorSeverity;
+ UINT16 Revision;
+ UINT8 ValidationBits;
+ UINT8 Flags;
+ UINT32 ErrorDataLength;
+ UINT8 FruId[16];
+ UINT8 FruText[20];
+} EFI_ACPI_5_0_GENERIC_ERROR_DATA_ENTRY_STRUCTURE;
+
+///
+/// Generic Error Data Entry Version (as defined in ACPI 5.0 spec.)
+///
+#define EFI_ACPI_5_0_GENERIC_ERROR_DATA_ENTRY_REVISION 0x0201
+
+///
+/// HEST - Hardware Error Source Table
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 ErrorSourceCount;
+} EFI_ACPI_5_0_HARDWARE_ERROR_SOURCE_TABLE_HEADER;
+
+///
+/// HEST Version (as defined in ACPI 5.0 spec.)
+///
+#define EFI_ACPI_5_0_HARDWARE_ERROR_SOURCE_TABLE_REVISION 0x01
+
+//
+// Error Source structure types.
+//
+#define EFI_ACPI_5_0_IA32_ARCHITECTURE_MACHINE_CHECK_EXCEPTION 0x00
+#define EFI_ACPI_5_0_IA32_ARCHITECTURE_CORRECTED_MACHINE_CHECK 0x01
+#define EFI_ACPI_5_0_IA32_ARCHITECTURE_NMI_ERROR 0x02
+#define EFI_ACPI_5_0_PCI_EXPRESS_ROOT_PORT_AER 0x06
+#define EFI_ACPI_5_0_PCI_EXPRESS_DEVICE_AER 0x07
+#define EFI_ACPI_5_0_PCI_EXPRESS_BRIDGE_AER 0x08
+#define EFI_ACPI_5_0_GENERIC_HARDWARE_ERROR 0x09
+
+//
+// Error Source structure flags.
+//
+#define EFI_ACPI_5_0_ERROR_SOURCE_FLAG_FIRMWARE_FIRST (1 << 0)
+#define EFI_ACPI_5_0_ERROR_SOURCE_FLAG_GLOBAL (1 << 1)
+
+///
+/// IA-32 Architecture Machine Check Exception Structure Definition
+///
+typedef struct {
+ UINT16 Type;
+ UINT16 SourceId;
+ UINT8 Reserved0[2];
+ UINT8 Flags;
+ UINT8 Enabled;
+ UINT32 NumberOfRecordsToPreAllocate;
+ UINT32 MaxSectionsPerRecord;
+ UINT64 GlobalCapabilityInitData;
+ UINT64 GlobalControlInitData;
+ UINT8 NumberOfHardwareBanks;
+ UINT8 Reserved1[7];
+} EFI_ACPI_5_0_IA32_ARCHITECTURE_MACHINE_CHECK_EXCEPTION_STRUCTURE;
+
+///
+/// IA-32 Architecture Machine Check Bank Structure Definition
+///
+typedef struct {
+ UINT8 BankNumber;
+ UINT8 ClearStatusOnInitialization;
+ UINT8 StatusDataFormat;
+ UINT8 Reserved0;
+ UINT32 ControlRegisterMsrAddress;
+ UINT64 ControlInitData;
+ UINT32 StatusRegisterMsrAddress;
+ UINT32 AddressRegisterMsrAddress;
+ UINT32 MiscRegisterMsrAddress;
+} EFI_ACPI_5_0_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_BANK_STRUCTURE;
+
+///
+/// IA-32 Architecture Machine Check Bank Structure MCA data format
+///
+#define EFI_ACPI_5_0_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_IA32 0x00
+#define EFI_ACPI_5_0_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_INTEL64 0x01
+#define EFI_ACPI_5_0_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_AMD64 0x02
+
+//
+// Hardware Error Notification types. All other values are reserved
+//
+#define EFI_ACPI_5_0_HARDWARE_ERROR_NOTIFICATION_POLLED 0x00
+#define EFI_ACPI_5_0_HARDWARE_ERROR_NOTIFICATION_EXTERNAL_INTERRUPT 0x01
+#define EFI_ACPI_5_0_HARDWARE_ERROR_NOTIFICATION_LOCAL_INTERRUPT 0x02
+#define EFI_ACPI_5_0_HARDWARE_ERROR_NOTIFICATION_SCI 0x03
+#define EFI_ACPI_5_0_HARDWARE_ERROR_NOTIFICATION_NMI 0x04
+
+///
+/// Hardware Error Notification Configuration Write Enable Structure Definition
+///
+typedef struct {
+ UINT16 Type : 1;
+ UINT16 PollInterval : 1;
+ UINT16 SwitchToPollingThresholdValue : 1;
+ UINT16 SwitchToPollingThresholdWindow : 1;
+ UINT16 ErrorThresholdValue : 1;
+ UINT16 ErrorThresholdWindow : 1;
+ UINT16 Reserved : 10;
+} EFI_ACPI_5_0_HARDWARE_ERROR_NOTIFICATION_CONFIGURATION_WRITE_ENABLE_STRUCTURE;
+
+///
+/// Hardware Error Notification Structure Definition
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ EFI_ACPI_5_0_HARDWARE_ERROR_NOTIFICATION_CONFIGURATION_WRITE_ENABLE_STRUCTURE ConfigurationWriteEnable;
+ UINT32 PollInterval;
+ UINT32 Vector;
+ UINT32 SwitchToPollingThresholdValue;
+ UINT32 SwitchToPollingThresholdWindow;
+ UINT32 ErrorThresholdValue;
+ UINT32 ErrorThresholdWindow;
+} EFI_ACPI_5_0_HARDWARE_ERROR_NOTIFICATION_STRUCTURE;
+
+///
+/// IA-32 Architecture Corrected Machine Check Structure Definition
+///
+typedef struct {
+ UINT16 Type;
+ UINT16 SourceId;
+ UINT8 Reserved0[2];
+ UINT8 Flags;
+ UINT8 Enabled;
+ UINT32 NumberOfRecordsToPreAllocate;
+ UINT32 MaxSectionsPerRecord;
+ EFI_ACPI_5_0_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure;
+ UINT8 NumberOfHardwareBanks;
+ UINT8 Reserved1[3];
+} EFI_ACPI_5_0_IA32_ARCHITECTURE_CORRECTED_MACHINE_CHECK_STRUCTURE;
+
+///
+/// IA-32 Architecture NMI Error Structure Definition
+///
+typedef struct {
+ UINT16 Type;
+ UINT16 SourceId;
+ UINT8 Reserved0[2];
+ UINT32 NumberOfRecordsToPreAllocate;
+ UINT32 MaxSectionsPerRecord;
+ UINT32 MaxRawDataLength;
+} EFI_ACPI_5_0_IA32_ARCHITECTURE_NMI_ERROR_STRUCTURE;
+
+///
+/// PCI Express Root Port AER Structure Definition
+///
+typedef struct {
+ UINT16 Type;
+ UINT16 SourceId;
+ UINT8 Reserved0[2];
+ UINT8 Flags;
+ UINT8 Enabled;
+ UINT32 NumberOfRecordsToPreAllocate;
+ UINT32 MaxSectionsPerRecord;
+ UINT32 Bus;
+ UINT16 Device;
+ UINT16 Function;
+ UINT16 DeviceControl;
+ UINT8 Reserved1[2];
+ UINT32 UncorrectableErrorMask;
+ UINT32 UncorrectableErrorSeverity;
+ UINT32 CorrectableErrorMask;
+ UINT32 AdvancedErrorCapabilitiesAndControl;
+ UINT32 RootErrorCommand;
+} EFI_ACPI_5_0_PCI_EXPRESS_ROOT_PORT_AER_STRUCTURE;
+
+///
+/// PCI Express Device AER Structure Definition
+///
+typedef struct {
+ UINT16 Type;
+ UINT16 SourceId;
+ UINT8 Reserved0[2];
+ UINT8 Flags;
+ UINT8 Enabled;
+ UINT32 NumberOfRecordsToPreAllocate;
+ UINT32 MaxSectionsPerRecord;
+ UINT32 Bus;
+ UINT16 Device;
+ UINT16 Function;
+ UINT16 DeviceControl;
+ UINT8 Reserved1[2];
+ UINT32 UncorrectableErrorMask;
+ UINT32 UncorrectableErrorSeverity;
+ UINT32 CorrectableErrorMask;
+ UINT32 AdvancedErrorCapabilitiesAndControl;
+} EFI_ACPI_5_0_PCI_EXPRESS_DEVICE_AER_STRUCTURE;
+
+///
+/// PCI Express Bridge AER Structure Definition
+///
+typedef struct {
+ UINT16 Type;
+ UINT16 SourceId;
+ UINT8 Reserved0[2];
+ UINT8 Flags;
+ UINT8 Enabled;
+ UINT32 NumberOfRecordsToPreAllocate;
+ UINT32 MaxSectionsPerRecord;
+ UINT32 Bus;
+ UINT16 Device;
+ UINT16 Function;
+ UINT16 DeviceControl;
+ UINT8 Reserved1[2];
+ UINT32 UncorrectableErrorMask;
+ UINT32 UncorrectableErrorSeverity;
+ UINT32 CorrectableErrorMask;
+ UINT32 AdvancedErrorCapabilitiesAndControl;
+ UINT32 SecondaryUncorrectableErrorMask;
+ UINT32 SecondaryUncorrectableErrorSeverity;
+ UINT32 SecondaryAdvancedErrorCapabilitiesAndControl;
+} EFI_ACPI_5_0_PCI_EXPRESS_BRIDGE_AER_STRUCTURE;
+
+///
+/// Generic Hardware Error Source Structure Definition
+///
+typedef struct {
+ UINT16 Type;
+ UINT16 SourceId;
+ UINT16 RelatedSourceId;
+ UINT8 Flags;
+ UINT8 Enabled;
+ UINT32 NumberOfRecordsToPreAllocate;
+ UINT32 MaxSectionsPerRecord;
+ UINT32 MaxRawDataLength;
+ EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE ErrorStatusAddress;
+ EFI_ACPI_5_0_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure;
+ UINT32 ErrorStatusBlockLength;
+} EFI_ACPI_5_0_GENERIC_HARDWARE_ERROR_SOURCE_STRUCTURE;
+
+///
+/// Generic Error Status Definition
+///
+typedef struct {
+ EFI_ACPI_5_0_ERROR_BLOCK_STATUS BlockStatus;
+ UINT32 RawDataOffset;
+ UINT32 RawDataLength;
+ UINT32 DataLength;
+ UINT32 ErrorSeverity;
+} EFI_ACPI_5_0_GENERIC_ERROR_STATUS_STRUCTURE;
+
+///
+/// ERST - Error Record Serialization Table
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 SerializationHeaderSize;
+ UINT8 Reserved0[4];
+ UINT32 InstructionEntryCount;
+} EFI_ACPI_5_0_ERROR_RECORD_SERIALIZATION_TABLE_HEADER;
+
+///
+/// ERST Version (as defined in ACPI 5.0 spec.)
+///
+#define EFI_ACPI_5_0_ERROR_RECORD_SERIALIZATION_TABLE_REVISION 0x01
+
+///
+/// ERST Serialization Actions
+///
+#define EFI_ACPI_5_0_ERST_BEGIN_WRITE_OPERATION 0x00
+#define EFI_ACPI_5_0_ERST_BEGIN_READ_OPERATION 0x01
+#define EFI_ACPI_5_0_ERST_BEGIN_CLEAR_OPERATION 0x02
+#define EFI_ACPI_5_0_ERST_END_OPERATION 0x03
+#define EFI_ACPI_5_0_ERST_SET_RECORD_OFFSET 0x04
+#define EFI_ACPI_5_0_ERST_EXECUTE_OPERATION 0x05
+#define EFI_ACPI_5_0_ERST_CHECK_BUSY_STATUS 0x06
+#define EFI_ACPI_5_0_ERST_GET_COMMAND_STATUS 0x07
+#define EFI_ACPI_5_0_ERST_GET_RECORD_IDENTIFIER 0x08
+#define EFI_ACPI_5_0_ERST_SET_RECORD_IDENTIFIER 0x09
+#define EFI_ACPI_5_0_ERST_GET_RECORD_COUNT 0x0A
+#define EFI_ACPI_5_0_ERST_BEGIN_DUMMY_WRITE_OPERATION 0x0B
+#define EFI_ACPI_5_0_ERST_GET_ERROR_LOG_ADDRESS_RANGE 0x0D
+#define EFI_ACPI_5_0_ERST_GET_ERROR_LOG_ADDRESS_RANGE_LENGTH 0x0E
+#define EFI_ACPI_5_0_ERST_GET_ERROR_LOG_ADDRESS_RANGE_ATTRIBUTES 0x0F
+
+///
+/// ERST Action Command Status
+///
+#define EFI_ACPI_5_0_ERST_STATUS_SUCCESS 0x00
+#define EFI_ACPI_5_0_ERST_STATUS_NOT_ENOUGH_SPACE 0x01
+#define EFI_ACPI_5_0_ERST_STATUS_HARDWARE_NOT_AVAILABLE 0x02
+#define EFI_ACPI_5_0_ERST_STATUS_FAILED 0x03
+#define EFI_ACPI_5_0_ERST_STATUS_RECORD_STORE_EMPTY 0x04
+#define EFI_ACPI_5_0_ERST_STATUS_RECORD_NOT_FOUND 0x05
+
+///
+/// ERST Serialization Instructions
+///
+#define EFI_ACPI_5_0_ERST_READ_REGISTER 0x00
+#define EFI_ACPI_5_0_ERST_READ_REGISTER_VALUE 0x01
+#define EFI_ACPI_5_0_ERST_WRITE_REGISTER 0x02
+#define EFI_ACPI_5_0_ERST_WRITE_REGISTER_VALUE 0x03
+#define EFI_ACPI_5_0_ERST_NOOP 0x04
+#define EFI_ACPI_5_0_ERST_LOAD_VAR1 0x05
+#define EFI_ACPI_5_0_ERST_LOAD_VAR2 0x06
+#define EFI_ACPI_5_0_ERST_STORE_VAR1 0x07
+#define EFI_ACPI_5_0_ERST_ADD 0x08
+#define EFI_ACPI_5_0_ERST_SUBTRACT 0x09
+#define EFI_ACPI_5_0_ERST_ADD_VALUE 0x0A
+#define EFI_ACPI_5_0_ERST_SUBTRACT_VALUE 0x0B
+#define EFI_ACPI_5_0_ERST_STALL 0x0C
+#define EFI_ACPI_5_0_ERST_STALL_WHILE_TRUE 0x0D
+#define EFI_ACPI_5_0_ERST_SKIP_NEXT_INSTRUCTION_IF_TRUE 0x0E
+#define EFI_ACPI_5_0_ERST_GOTO 0x0F
+#define EFI_ACPI_5_0_ERST_SET_SRC_ADDRESS_BASE 0x10
+#define EFI_ACPI_5_0_ERST_SET_DST_ADDRESS_BASE 0x11
+#define EFI_ACPI_5_0_ERST_MOVE_DATA 0x12
+
+///
+/// ERST Instruction Flags
+///
+#define EFI_ACPI_5_0_ERST_PRESERVE_REGISTER 0x01
+
+///
+/// ERST Serialization Instruction Entry
+///
+typedef struct {
+ UINT8 SerializationAction;
+ UINT8 Instruction;
+ UINT8 Flags;
+ UINT8 Reserved0;
+ EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE RegisterRegion;
+ UINT64 Value;
+ UINT64 Mask;
+} EFI_ACPI_5_0_ERST_SERIALIZATION_INSTRUCTION_ENTRY;
+
+///
+/// EINJ - Error Injection Table
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 InjectionHeaderSize;
+ UINT8 InjectionFlags;
+ UINT8 Reserved0[3];
+ UINT32 InjectionEntryCount;
+} EFI_ACPI_5_0_ERROR_INJECTION_TABLE_HEADER;
+
+///
+/// EINJ Version (as defined in ACPI 5.0 spec.)
+///
+#define EFI_ACPI_5_0_ERROR_INJECTION_TABLE_REVISION 0x01
+
+///
+/// EINJ Error Injection Actions
+///
+#define EFI_ACPI_5_0_EINJ_BEGIN_INJECTION_OPERATION 0x00
+#define EFI_ACPI_5_0_EINJ_GET_TRIGGER_ERROR_ACTION_TABLE 0x01
+#define EFI_ACPI_5_0_EINJ_SET_ERROR_TYPE 0x02
+#define EFI_ACPI_5_0_EINJ_GET_ERROR_TYPE 0x03
+#define EFI_ACPI_5_0_EINJ_END_OPERATION 0x04
+#define EFI_ACPI_5_0_EINJ_EXECUTE_OPERATION 0x05
+#define EFI_ACPI_5_0_EINJ_CHECK_BUSY_STATUS 0x06
+#define EFI_ACPI_5_0_EINJ_GET_COMMAND_STATUS 0x07
+#define EFI_ACPI_5_0_EINJ_TRIGGER_ERROR 0xFF
+
+///
+/// EINJ Action Command Status
+///
+#define EFI_ACPI_5_0_EINJ_STATUS_SUCCESS 0x00
+#define EFI_ACPI_5_0_EINJ_STATUS_UNKNOWN_FAILURE 0x01
+#define EFI_ACPI_5_0_EINJ_STATUS_INVALID_ACCESS 0x02
+
+///
+/// EINJ Error Type Definition
+///
+#define EFI_ACPI_5_0_EINJ_ERROR_PROCESSOR_CORRECTABLE (1 << 0)
+#define EFI_ACPI_5_0_EINJ_ERROR_PROCESSOR_UNCORRECTABLE_NONFATAL (1 << 1)
+#define EFI_ACPI_5_0_EINJ_ERROR_PROCESSOR_UNCORRECTABLE_FATAL (1 << 2)
+#define EFI_ACPI_5_0_EINJ_ERROR_MEMORY_CORRECTABLE (1 << 3)
+#define EFI_ACPI_5_0_EINJ_ERROR_MEMORY_UNCORRECTABLE_NONFATAL (1 << 4)
+#define EFI_ACPI_5_0_EINJ_ERROR_MEMORY_UNCORRECTABLE_FATAL (1 << 5)
+#define EFI_ACPI_5_0_EINJ_ERROR_PCI_EXPRESS_CORRECTABLE (1 << 6)
+#define EFI_ACPI_5_0_EINJ_ERROR_PCI_EXPRESS_UNCORRECTABLE_NONFATAL (1 << 7)
+#define EFI_ACPI_5_0_EINJ_ERROR_PCI_EXPRESS_UNCORRECTABLE_FATAL (1 << 8)
+#define EFI_ACPI_5_0_EINJ_ERROR_PLATFORM_CORRECTABLE (1 << 9)
+#define EFI_ACPI_5_0_EINJ_ERROR_PLATFORM_UNCORRECTABLE_NONFATAL (1 << 10)
+#define EFI_ACPI_5_0_EINJ_ERROR_PLATFORM_UNCORRECTABLE_FATAL (1 << 11)
+
+///
+/// EINJ Injection Instructions
+///
+#define EFI_ACPI_5_0_EINJ_READ_REGISTER 0x00
+#define EFI_ACPI_5_0_EINJ_READ_REGISTER_VALUE 0x01
+#define EFI_ACPI_5_0_EINJ_WRITE_REGISTER 0x02
+#define EFI_ACPI_5_0_EINJ_WRITE_REGISTER_VALUE 0x03
+#define EFI_ACPI_5_0_EINJ_NOOP 0x04
+
+///
+/// EINJ Instruction Flags
+///
+#define EFI_ACPI_5_0_EINJ_PRESERVE_REGISTER 0x01
+
+///
+/// EINJ Injection Instruction Entry
+///
+typedef struct {
+ UINT8 InjectionAction;
+ UINT8 Instruction;
+ UINT8 Flags;
+ UINT8 Reserved0;
+ EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE RegisterRegion;
+ UINT64 Value;
+ UINT64 Mask;
+} EFI_ACPI_5_0_EINJ_INJECTION_INSTRUCTION_ENTRY;
+
+///
+/// EINJ Trigger Action Table
+///
+typedef struct {
+ UINT32 HeaderSize;
+ UINT32 Revision;
+ UINT32 TableSize;
+ UINT32 EntryCount;
+} EFI_ACPI_5_0_EINJ_TRIGGER_ACTION_TABLE;
+
+///
+/// Platform Communications Channel Table (PCCT)
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 Flags;
+ UINT64 Reserved;
+} EFI_ACPI_5_0_PLATFORM_COMMUNICATION_CHANNEL_TABLE_HEADER;
+
+///
+/// PCCT Version (as defined in ACPI 5.0 spec.)
+///
+#define EFI_ACPI_5_0_PLATFORM_COMMUNICATION_CHANNEL_TABLE_REVISION 0x01
+
+///
+/// PCCT Global Flags
+///
+#define EFI_ACPI_5_0_PCCT_FLAGS_SCI_DOORBELL BIT0
+
+//
+// PCCT Subspace type
+//
+#define EFI_ACPI_5_0_PCCT_SUBSPACE_TYPE_GENERIC 0x00
+
+///
+/// PCC Subspace Structure Header
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+} EFI_ACPI_5_0_PCCT_SUBSPACE_HEADER;
+
+///
+/// Generic Communications Subspace Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 Reserved[6];
+ UINT64 BaseAddress;
+ UINT64 AddressLength;
+ EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE DoorbellRegister;
+ UINT64 DoorbellPreserve;
+ UINT64 DoorbellWrite;
+ UINT32 NominalLatency;
+ UINT32 MaximumPeriodicAccessRate;
+ UINT16 MinimumRequestTurnaroundTime;
+} EFI_ACPI_5_0_PCCT_SUBSPACE_GENERIC;
+
+///
+/// Generic Communications Channel Shared Memory Region
+///
+
+typedef struct {
+ UINT8 Command;
+ UINT8 Reserved : 7;
+ UINT8 GenerateSci : 1;
+} EFI_ACPI_5_0_PCCT_GENERIC_SHARED_MEMORY_REGION_COMMAND;
+
+typedef struct {
+ UINT8 CommandComplete : 1;
+ UINT8 SciDoorbell : 1;
+ UINT8 Error : 1;
+ UINT8 PlatformNotification : 1;
+ UINT8 Reserved : 4;
+ UINT8 Reserved1;
+} EFI_ACPI_5_0_PCCT_GENERIC_SHARED_MEMORY_REGION_STATUS;
+
+typedef struct {
+ UINT32 Signature;
+ EFI_ACPI_5_0_PCCT_GENERIC_SHARED_MEMORY_REGION_COMMAND Command;
+ EFI_ACPI_5_0_PCCT_GENERIC_SHARED_MEMORY_REGION_STATUS Status;
+} EFI_ACPI_5_0_PCCT_GENERIC_SHARED_MEMORY_REGION_HEADER;
+
+//
+// Known table signatures
+//
+
+///
+/// "RSD PTR " Root System Description Pointer
+///
+#define EFI_ACPI_5_0_ROOT_SYSTEM_DESCRIPTION_POINTER_SIGNATURE SIGNATURE_64('R', 'S', 'D', ' ', 'P', 'T', 'R', ' ')
+
+///
+/// "APIC" Multiple APIC Description Table
+///
+#define EFI_ACPI_5_0_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('A', 'P', 'I', 'C')
+
+///
+/// "BERT" Boot Error Record Table
+///
+#define EFI_ACPI_5_0_BOOT_ERROR_RECORD_TABLE_SIGNATURE SIGNATURE_32('B', 'E', 'R', 'T')
+
+///
+/// "BGRT" Boot Graphics Resource Table
+///
+#define EFI_ACPI_5_0_BOOT_GRAPHICS_RESOURCE_TABLE_SIGNATURE SIGNATURE_32('B', 'G', 'R', 'T')
+
+///
+/// "CPEP" Corrected Platform Error Polling Table
+///
+#define EFI_ACPI_5_0_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_SIGNATURE SIGNATURE_32('C', 'P', 'E', 'P')
+
+///
+/// "DSDT" Differentiated System Description Table
+///
+#define EFI_ACPI_5_0_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('D', 'S', 'D', 'T')
+
+///
+/// "ECDT" Embedded Controller Boot Resources Table
+///
+#define EFI_ACPI_5_0_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE_SIGNATURE SIGNATURE_32('E', 'C', 'D', 'T')
+
+///
+/// "EINJ" Error Injection Table
+///
+#define EFI_ACPI_5_0_ERROR_INJECTION_TABLE_SIGNATURE SIGNATURE_32('E', 'I', 'N', 'J')
+
+///
+/// "ERST" Error Record Serialization Table
+///
+#define EFI_ACPI_5_0_ERROR_RECORD_SERIALIZATION_TABLE_SIGNATURE SIGNATURE_32('E', 'R', 'S', 'T')
+
+///
+/// "FACP" Fixed ACPI Description Table
+///
+#define EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('F', 'A', 'C', 'P')
+
+///
+/// "FACS" Firmware ACPI Control Structure
+///
+#define EFI_ACPI_5_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_SIGNATURE SIGNATURE_32('F', 'A', 'C', 'S')
+
+///
+/// "FPDT" Firmware Performance Data Table
+///
+#define EFI_ACPI_5_0_FIRMWARE_PERFORMANCE_DATA_TABLE_SIGNATURE SIGNATURE_32('F', 'P', 'D', 'T')
+
+///
+/// "GTDT" Generic Timer Description Table
+///
+#define EFI_ACPI_5_0_GENERIC_TIMER_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('G', 'T', 'D', 'T')
+
+///
+/// "HEST" Hardware Error Source Table
+///
+#define EFI_ACPI_5_0_HARDWARE_ERROR_SOURCE_TABLE_SIGNATURE SIGNATURE_32('H', 'E', 'S', 'T')
+
+///
+/// "MPST" Memory Power State Table
+///
+#define EFI_ACPI_5_0_MEMORY_POWER_STATE_TABLE_SIGNATURE SIGNATURE_32('M', 'P', 'S', 'T')
+
+///
+/// "MSCT" Maximum System Characteristics Table
+///
+#define EFI_ACPI_5_0_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_SIGNATURE SIGNATURE_32('M', 'S', 'C', 'T')
+
+///
+/// "PMTT" Platform Memory Topology Table
+///
+#define EFI_ACPI_5_0_PLATFORM_MEMORY_TOPOLOGY_TABLE_SIGNATURE SIGNATURE_32('P', 'M', 'T', 'T')
+
+///
+/// "PSDT" Persistent System Description Table
+///
+#define EFI_ACPI_5_0_PERSISTENT_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('P', 'S', 'D', 'T')
+
+///
+/// "RASF" ACPI RAS Feature Table
+///
+#define EFI_ACPI_5_0_ACPI_RAS_FEATURE_TABLE_SIGNATURE SIGNATURE_32('R', 'A', 'S', 'F')
+
+///
+/// "RSDT" Root System Description Table
+///
+#define EFI_ACPI_5_0_ROOT_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('R', 'S', 'D', 'T')
+
+///
+/// "SBST" Smart Battery Specification Table
+///
+#define EFI_ACPI_5_0_SMART_BATTERY_SPECIFICATION_TABLE_SIGNATURE SIGNATURE_32('S', 'B', 'S', 'T')
+
+///
+/// "SLIT" System Locality Information Table
+///
+#define EFI_ACPI_5_0_SYSTEM_LOCALITY_INFORMATION_TABLE_SIGNATURE SIGNATURE_32('S', 'L', 'I', 'T')
+
+///
+/// "SRAT" System Resource Affinity Table
+///
+#define EFI_ACPI_5_0_SYSTEM_RESOURCE_AFFINITY_TABLE_SIGNATURE SIGNATURE_32('S', 'R', 'A', 'T')
+
+///
+/// "SSDT" Secondary System Description Table
+///
+#define EFI_ACPI_5_0_SECONDARY_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('S', 'S', 'D', 'T')
+
+///
+/// "XSDT" Extended System Description Table
+///
+#define EFI_ACPI_5_0_EXTENDED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('X', 'S', 'D', 'T')
+
+///
+/// "BOOT" MS Simple Boot Spec
+///
+#define EFI_ACPI_5_0_SIMPLE_BOOT_FLAG_TABLE_SIGNATURE SIGNATURE_32('B', 'O', 'O', 'T')
+
+///
+/// "CSRT" MS Core System Resource Table
+///
+#define EFI_ACPI_5_0_CORE_SYSTEM_RESOURCE_TABLE_SIGNATURE SIGNATURE_32('C', 'S', 'R', 'T')
+
+///
+/// "DBG2" MS Debug Port 2 Spec
+///
+#define EFI_ACPI_5_0_DEBUG_PORT_2_TABLE_SIGNATURE SIGNATURE_32('D', 'B', 'G', '2')
+
+///
+/// "DBGP" MS Debug Port Spec
+///
+#define EFI_ACPI_5_0_DEBUG_PORT_TABLE_SIGNATURE SIGNATURE_32('D', 'B', 'G', 'P')
+
+///
+/// "DMAR" DMA Remapping Table
+///
+#define EFI_ACPI_5_0_DMA_REMAPPING_TABLE_SIGNATURE SIGNATURE_32('D', 'M', 'A', 'R')
+
+///
+/// "DRTM" Dynamic Root of Trust for Measurement Table
+///
+#define EFI_ACPI_5_0_DYNAMIC_ROOT_OF_TRUST_FOR_MEASUREMENT_TABLE_SIGNATURE SIGNATURE_32('D', 'R', 'T', 'M')
+
+///
+/// "ETDT" Event Timer Description Table
+///
+#define EFI_ACPI_5_0_EVENT_TIMER_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('E', 'T', 'D', 'T')
+
+///
+/// "HPET" IA-PC High Precision Event Timer Table
+///
+#define EFI_ACPI_5_0_HIGH_PRECISION_EVENT_TIMER_TABLE_SIGNATURE SIGNATURE_32('H', 'P', 'E', 'T')
+
+///
+/// "iBFT" iSCSI Boot Firmware Table
+///
+#define EFI_ACPI_5_0_ISCSI_BOOT_FIRMWARE_TABLE_SIGNATURE SIGNATURE_32('i', 'B', 'F', 'T')
+
+///
+/// "IVRS" I/O Virtualization Reporting Structure
+///
+#define EFI_ACPI_5_0_IO_VIRTUALIZATION_REPORTING_STRUCTURE_SIGNATURE SIGNATURE_32('I', 'V', 'R', 'S')
+
+///
+/// "MCFG" PCI Express Memory Mapped Configuration Space Base Address Description Table
+///
+#define EFI_ACPI_5_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('M', 'C', 'F', 'G')
+
+///
+/// "MCHI" Management Controller Host Interface Table
+///
+#define EFI_ACPI_5_0_MANAGEMENT_CONTROLLER_HOST_INTERFACE_TABLE_SIGNATURE SIGNATURE_32('M', 'C', 'H', 'I')
+
+///
+/// "MSDM" MS Data Management Table
+///
+#define EFI_ACPI_5_0_DATA_MANAGEMENT_TABLE_SIGNATURE SIGNATURE_32('M', 'S', 'D', 'M')
+
+///
+/// "PCCT" Platform Communications Channel Table
+///
+#define EFI_ACPI_5_0_PLATFORM_COMMUNICATIONS_CHANNEL_TABLE_SIGNATURE SIGNATURE_32('P', 'C', 'C', 'T')
+
+///
+/// "SLIC" MS Software Licensing Table Specification
+///
+#define EFI_ACPI_5_0_SOFTWARE_LICENSING_TABLE_SIGNATURE SIGNATURE_32('S', 'L', 'I', 'C')
+
+///
+/// "SPCR" Serial Port Console Redirection Table
+///
+#define EFI_ACPI_5_0_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE SIGNATURE_32('S', 'P', 'C', 'R')
+
+///
+/// "SPMI" Server Platform Management Interface Table
+///
+#define EFI_ACPI_5_0_SERVER_PLATFORM_MANAGEMENT_INTERFACE_TABLE_SIGNATURE SIGNATURE_32('S', 'P', 'M', 'I')
+
+///
+/// "TCPA" Trusted Computing Platform Alliance Capabilities Table
+///
+#define EFI_ACPI_5_0_TRUSTED_COMPUTING_PLATFORM_ALLIANCE_CAPABILITIES_TABLE_SIGNATURE SIGNATURE_32('T', 'C', 'P', 'A')
+
+///
+/// "TPM2" Trusted Computing Platform 1 Table
+///
+#define EFI_ACPI_5_0_TRUSTED_COMPUTING_PLATFORM_2_TABLE_SIGNATURE SIGNATURE_32('T', 'P', 'M', '2')
+
+///
+/// "UEFI" UEFI ACPI Data Table
+///
+#define EFI_ACPI_5_0_UEFI_ACPI_DATA_TABLE_SIGNATURE SIGNATURE_32('U', 'E', 'F', 'I')
+
+///
+/// "WAET" Windows ACPI Emulated Devices Table
+///
+#define EFI_ACPI_5_0_WINDOWS_ACPI_EMULATED_DEVICES_TABLE_SIGNATURE SIGNATURE_32('W', 'A', 'E', 'T')
+#define EFI_ACPI_5_0_WINDOWS_ACPI_ENLIGHTENMENT_TABLE_SIGNATURE EFI_ACPI_5_0_WINDOWS_ACPI_EMULATED_DEVICES_TABLE_SIGNATURE
+
+///
+/// "WDAT" Watchdog Action Table
+///
+#define EFI_ACPI_5_0_WATCHDOG_ACTION_TABLE_SIGNATURE SIGNATURE_32('W', 'D', 'A', 'T')
+
+///
+/// "WDRT" Watchdog Resource Table
+///
+#define EFI_ACPI_5_0_WATCHDOG_RESOURCE_TABLE_SIGNATURE SIGNATURE_32('W', 'D', 'R', 'T')
+
+///
+/// "WPBT" MS Platform Binary Table
+///
+#define EFI_ACPI_5_0_PLATFORM_BINARY_TABLE_SIGNATURE SIGNATURE_32('W', 'P', 'B', 'T')
+
+#pragma pack()
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/Acpi51.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/Acpi51.h
new file mode 100644
index 0000000000..d2259890c9
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/Acpi51.h
@@ -0,0 +1,2145 @@
+/** @file
+ ACPI 5.1 definitions from the ACPI Specification Revision 5.1 Errata B January, 2016.
+
+ Copyright (c) 2014 Hewlett-Packard Development Company, L.P.
+ Copyright (c) 2014 - 2022, Intel Corporation. All rights reserved.
+ (C) Copyright 2015 Hewlett Packard Enterprise Development LP
+ Copyright (c) 2020, ARM Ltd. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _ACPI_5_1_H_
+#define _ACPI_5_1_H_
+
+#include
+
+//
+// Ensure proper structure formats
+//
+#pragma pack(1)
+
+///
+/// ACPI 5.1 Generic Address Space definition
+///
+typedef struct {
+ UINT8 AddressSpaceId;
+ UINT8 RegisterBitWidth;
+ UINT8 RegisterBitOffset;
+ UINT8 AccessSize;
+ UINT64 Address;
+} EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE;
+
+//
+// Generic Address Space Address IDs
+//
+#define EFI_ACPI_5_1_SYSTEM_MEMORY 0
+#define EFI_ACPI_5_1_SYSTEM_IO 1
+#define EFI_ACPI_5_1_PCI_CONFIGURATION_SPACE 2
+#define EFI_ACPI_5_1_EMBEDDED_CONTROLLER 3
+#define EFI_ACPI_5_1_SMBUS 4
+#define EFI_ACPI_5_1_PLATFORM_COMMUNICATION_CHANNEL 0x0A
+#define EFI_ACPI_5_1_FUNCTIONAL_FIXED_HARDWARE 0x7F
+
+//
+// Generic Address Space Access Sizes
+//
+#define EFI_ACPI_5_1_UNDEFINED 0
+#define EFI_ACPI_5_1_BYTE 1
+#define EFI_ACPI_5_1_WORD 2
+#define EFI_ACPI_5_1_DWORD 3
+#define EFI_ACPI_5_1_QWORD 4
+
+//
+// ACPI 5.1 table structures
+//
+
+///
+/// Root System Description Pointer Structure
+///
+typedef struct {
+ UINT64 Signature;
+ UINT8 Checksum;
+ UINT8 OemId[6];
+ UINT8 Revision;
+ UINT32 RsdtAddress;
+ UINT32 Length;
+ UINT64 XsdtAddress;
+ UINT8 ExtendedChecksum;
+ UINT8 Reserved[3];
+} EFI_ACPI_5_1_ROOT_SYSTEM_DESCRIPTION_POINTER;
+
+///
+/// RSD_PTR Revision (as defined in ACPI 5.1 spec.)
+///
+#define EFI_ACPI_5_1_ROOT_SYSTEM_DESCRIPTION_POINTER_REVISION 0x02 ///< ACPISpec (Revision 5.1) says current value is 2
+
+///
+/// Common table header, this prefaces all ACPI tables, including FACS, but
+/// excluding the RSD PTR structure
+///
+typedef struct {
+ UINT32 Signature;
+ UINT32 Length;
+} EFI_ACPI_5_1_COMMON_HEADER;
+
+//
+// Root System Description Table
+// No definition needed as it is a common description table header, the same with
+// EFI_ACPI_DESCRIPTION_HEADER, followed by a variable number of UINT32 table pointers.
+//
+
+///
+/// RSDT Revision (as defined in ACPI 5.1 spec.)
+///
+#define EFI_ACPI_5_1_ROOT_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01
+
+//
+// Extended System Description Table
+// No definition needed as it is a common description table header, the same with
+// EFI_ACPI_DESCRIPTION_HEADER, followed by a variable number of UINT64 table pointers.
+//
+
+///
+/// XSDT Revision (as defined in ACPI 5.1 spec.)
+///
+#define EFI_ACPI_5_1_EXTENDED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01
+
+///
+/// Fixed ACPI Description Table Structure (FADT)
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 FirmwareCtrl;
+ UINT32 Dsdt;
+ UINT8 Reserved0;
+ UINT8 PreferredPmProfile;
+ UINT16 SciInt;
+ UINT32 SmiCmd;
+ UINT8 AcpiEnable;
+ UINT8 AcpiDisable;
+ UINT8 S4BiosReq;
+ UINT8 PstateCnt;
+ UINT32 Pm1aEvtBlk;
+ UINT32 Pm1bEvtBlk;
+ UINT32 Pm1aCntBlk;
+ UINT32 Pm1bCntBlk;
+ UINT32 Pm2CntBlk;
+ UINT32 PmTmrBlk;
+ UINT32 Gpe0Blk;
+ UINT32 Gpe1Blk;
+ UINT8 Pm1EvtLen;
+ UINT8 Pm1CntLen;
+ UINT8 Pm2CntLen;
+ UINT8 PmTmrLen;
+ UINT8 Gpe0BlkLen;
+ UINT8 Gpe1BlkLen;
+ UINT8 Gpe1Base;
+ UINT8 CstCnt;
+ UINT16 PLvl2Lat;
+ UINT16 PLvl3Lat;
+ UINT16 FlushSize;
+ UINT16 FlushStride;
+ UINT8 DutyOffset;
+ UINT8 DutyWidth;
+ UINT8 DayAlrm;
+ UINT8 MonAlrm;
+ UINT8 Century;
+ UINT16 IaPcBootArch;
+ UINT8 Reserved1;
+ UINT32 Flags;
+ EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE ResetReg;
+ UINT8 ResetValue;
+ UINT16 ArmBootArch;
+ UINT8 MinorVersion;
+ UINT64 XFirmwareCtrl;
+ UINT64 XDsdt;
+ EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE XPm1aEvtBlk;
+ EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE XPm1bEvtBlk;
+ EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE XPm1aCntBlk;
+ EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE XPm1bCntBlk;
+ EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE XPm2CntBlk;
+ EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE XPmTmrBlk;
+ EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE XGpe0Blk;
+ EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE XGpe1Blk;
+ EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE SleepControlReg;
+ EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE SleepStatusReg;
+} EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE;
+
+///
+/// FADT Version (as defined in ACPI 5.1 spec.)
+///
+#define EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE_REVISION 0x05
+#define EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE_MINOR_REVISION 0x01
+
+//
+// Fixed ACPI Description Table Preferred Power Management Profile
+//
+#define EFI_ACPI_5_1_PM_PROFILE_UNSPECIFIED 0
+#define EFI_ACPI_5_1_PM_PROFILE_DESKTOP 1
+#define EFI_ACPI_5_1_PM_PROFILE_MOBILE 2
+#define EFI_ACPI_5_1_PM_PROFILE_WORKSTATION 3
+#define EFI_ACPI_5_1_PM_PROFILE_ENTERPRISE_SERVER 4
+#define EFI_ACPI_5_1_PM_PROFILE_SOHO_SERVER 5
+#define EFI_ACPI_5_1_PM_PROFILE_APPLIANCE_PC 6
+#define EFI_ACPI_5_1_PM_PROFILE_PERFORMANCE_SERVER 7
+#define EFI_ACPI_5_1_PM_PROFILE_TABLET 8
+
+//
+// Fixed ACPI Description Table Boot Architecture Flags
+// All other bits are reserved and must be set to 0.
+//
+#define EFI_ACPI_5_1_LEGACY_DEVICES BIT0
+#define EFI_ACPI_5_1_8042 BIT1
+#define EFI_ACPI_5_1_VGA_NOT_PRESENT BIT2
+#define EFI_ACPI_5_1_MSI_NOT_SUPPORTED BIT3
+#define EFI_ACPI_5_1_PCIE_ASPM_CONTROLS BIT4
+#define EFI_ACPI_5_1_CMOS_RTC_NOT_PRESENT BIT5
+
+//
+// Fixed ACPI Description Table Arm Boot Architecture Flags
+// All other bits are reserved and must be set to 0.
+//
+#define EFI_ACPI_5_1_ARM_PSCI_COMPLIANT BIT0
+#define EFI_ACPI_5_1_ARM_PSCI_USE_HVC BIT1
+
+//
+// Fixed ACPI Description Table Fixed Feature Flags
+// All other bits are reserved and must be set to 0.
+//
+#define EFI_ACPI_5_1_WBINVD BIT0
+#define EFI_ACPI_5_1_WBINVD_FLUSH BIT1
+#define EFI_ACPI_5_1_PROC_C1 BIT2
+#define EFI_ACPI_5_1_P_LVL2_UP BIT3
+#define EFI_ACPI_5_1_PWR_BUTTON BIT4
+#define EFI_ACPI_5_1_SLP_BUTTON BIT5
+#define EFI_ACPI_5_1_FIX_RTC BIT6
+#define EFI_ACPI_5_1_RTC_S4 BIT7
+#define EFI_ACPI_5_1_TMR_VAL_EXT BIT8
+#define EFI_ACPI_5_1_DCK_CAP BIT9
+#define EFI_ACPI_5_1_RESET_REG_SUP BIT10
+#define EFI_ACPI_5_1_SEALED_CASE BIT11
+#define EFI_ACPI_5_1_HEADLESS BIT12
+#define EFI_ACPI_5_1_CPU_SW_SLP BIT13
+#define EFI_ACPI_5_1_PCI_EXP_WAK BIT14
+#define EFI_ACPI_5_1_USE_PLATFORM_CLOCK BIT15
+#define EFI_ACPI_5_1_S4_RTC_STS_VALID BIT16
+#define EFI_ACPI_5_1_REMOTE_POWER_ON_CAPABLE BIT17
+#define EFI_ACPI_5_1_FORCE_APIC_CLUSTER_MODEL BIT18
+#define EFI_ACPI_5_1_FORCE_APIC_PHYSICAL_DESTINATION_MODE BIT19
+#define EFI_ACPI_5_1_HW_REDUCED_ACPI BIT20
+#define EFI_ACPI_5_1_LOW_POWER_S0_IDLE_CAPABLE BIT21
+
+///
+/// Firmware ACPI Control Structure
+///
+typedef struct {
+ UINT32 Signature;
+ UINT32 Length;
+ UINT32 HardwareSignature;
+ UINT32 FirmwareWakingVector;
+ UINT32 GlobalLock;
+ UINT32 Flags;
+ UINT64 XFirmwareWakingVector;
+ UINT8 Version;
+ UINT8 Reserved0[3];
+ UINT32 OspmFlags;
+ UINT8 Reserved1[24];
+} EFI_ACPI_5_1_FIRMWARE_ACPI_CONTROL_STRUCTURE;
+
+///
+/// FACS Version (as defined in ACPI 5.1 spec.)
+///
+#define EFI_ACPI_5_1_FIRMWARE_ACPI_CONTROL_STRUCTURE_VERSION 0x02
+
+///
+/// Firmware Control Structure Feature Flags
+/// All other bits are reserved and must be set to 0.
+///
+#define EFI_ACPI_5_1_S4BIOS_F BIT0
+#define EFI_ACPI_5_1_64BIT_WAKE_SUPPORTED_F BIT1
+
+///
+/// OSPM Enabled Firmware Control Structure Flags
+/// All other bits are reserved and must be set to 0.
+///
+#define EFI_ACPI_5_1_OSPM_64BIT_WAKE_F BIT0
+
+//
+// Differentiated System Description Table,
+// Secondary System Description Table
+// and Persistent System Description Table,
+// no definition needed as they are common description table header, the same with
+// EFI_ACPI_DESCRIPTION_HEADER, followed by a definition block.
+//
+#define EFI_ACPI_5_1_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x02
+#define EFI_ACPI_5_1_SECONDARY_SYSTEM_DESCRIPTION_TABLE_REVISION 0x02
+
+///
+/// Multiple APIC Description Table header definition. The rest of the table
+/// must be defined in a platform specific manner.
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 LocalApicAddress;
+ UINT32 Flags;
+} EFI_ACPI_5_1_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER;
+
+///
+/// MADT Revision (as defined in ACPI 5.1 spec.)
+///
+#define EFI_ACPI_5_1_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION 0x03
+
+///
+/// Multiple APIC Flags
+/// All other bits are reserved and must be set to 0.
+///
+#define EFI_ACPI_5_1_PCAT_COMPAT BIT0
+
+//
+// Multiple APIC Description Table APIC structure types
+// All other values between 0x0D and 0x7F are reserved and
+// will be ignored by OSPM. 0x80 ~ 0xFF are reserved for OEM.
+//
+#define EFI_ACPI_5_1_PROCESSOR_LOCAL_APIC 0x00
+#define EFI_ACPI_5_1_IO_APIC 0x01
+#define EFI_ACPI_5_1_INTERRUPT_SOURCE_OVERRIDE 0x02
+#define EFI_ACPI_5_1_NON_MASKABLE_INTERRUPT_SOURCE 0x03
+#define EFI_ACPI_5_1_LOCAL_APIC_NMI 0x04
+#define EFI_ACPI_5_1_LOCAL_APIC_ADDRESS_OVERRIDE 0x05
+#define EFI_ACPI_5_1_IO_SAPIC 0x06
+#define EFI_ACPI_5_1_LOCAL_SAPIC 0x07
+#define EFI_ACPI_5_1_PLATFORM_INTERRUPT_SOURCES 0x08
+#define EFI_ACPI_5_1_PROCESSOR_LOCAL_X2APIC 0x09
+#define EFI_ACPI_5_1_LOCAL_X2APIC_NMI 0x0A
+#define EFI_ACPI_5_1_GIC 0x0B
+#define EFI_ACPI_5_1_GICD 0x0C
+#define EFI_ACPI_5_1_GIC_MSI_FRAME 0x0D
+#define EFI_ACPI_5_1_GICR 0x0E
+
+//
+// APIC Structure Definitions
+//
+
+///
+/// Processor Local APIC Structure Definition
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 AcpiProcessorId;
+ UINT8 ApicId;
+ UINT32 Flags;
+} EFI_ACPI_5_1_PROCESSOR_LOCAL_APIC_STRUCTURE;
+
+///
+/// Local APIC Flags. All other bits are reserved and must be 0.
+///
+#define EFI_ACPI_5_1_LOCAL_APIC_ENABLED BIT0
+
+///
+/// IO APIC Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 IoApicId;
+ UINT8 Reserved;
+ UINT32 IoApicAddress;
+ UINT32 GlobalSystemInterruptBase;
+} EFI_ACPI_5_1_IO_APIC_STRUCTURE;
+
+///
+/// Interrupt Source Override Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 Bus;
+ UINT8 Source;
+ UINT32 GlobalSystemInterrupt;
+ UINT16 Flags;
+} EFI_ACPI_5_1_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE;
+
+///
+/// Platform Interrupt Sources Structure Definition
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Flags;
+ UINT8 InterruptType;
+ UINT8 ProcessorId;
+ UINT8 ProcessorEid;
+ UINT8 IoSapicVector;
+ UINT32 GlobalSystemInterrupt;
+ UINT32 PlatformInterruptSourceFlags;
+ UINT8 CpeiProcessorOverride;
+ UINT8 Reserved[31];
+} EFI_ACPI_5_1_PLATFORM_INTERRUPT_APIC_STRUCTURE;
+
+//
+// MPS INTI flags.
+// All other bits are reserved and must be set to 0.
+//
+#define EFI_ACPI_5_1_POLARITY (3 << 0)
+#define EFI_ACPI_5_1_TRIGGER_MODE (3 << 2)
+
+///
+/// Non-Maskable Interrupt Source Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Flags;
+ UINT32 GlobalSystemInterrupt;
+} EFI_ACPI_5_1_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE;
+
+///
+/// Local APIC NMI Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 AcpiProcessorId;
+ UINT16 Flags;
+ UINT8 LocalApicLint;
+} EFI_ACPI_5_1_LOCAL_APIC_NMI_STRUCTURE;
+
+///
+/// Local APIC Address Override Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Reserved;
+ UINT64 LocalApicAddress;
+} EFI_ACPI_5_1_LOCAL_APIC_ADDRESS_OVERRIDE_STRUCTURE;
+
+///
+/// IO SAPIC Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 IoApicId;
+ UINT8 Reserved;
+ UINT32 GlobalSystemInterruptBase;
+ UINT64 IoSapicAddress;
+} EFI_ACPI_5_1_IO_SAPIC_STRUCTURE;
+
+///
+/// Local SAPIC Structure
+/// This struct followed by a null-terminated ASCII string - ACPI Processor UID String
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 AcpiProcessorId;
+ UINT8 LocalSapicId;
+ UINT8 LocalSapicEid;
+ UINT8 Reserved[3];
+ UINT32 Flags;
+ UINT32 ACPIProcessorUIDValue;
+} EFI_ACPI_5_1_PROCESSOR_LOCAL_SAPIC_STRUCTURE;
+
+///
+/// Platform Interrupt Sources Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Flags;
+ UINT8 InterruptType;
+ UINT8 ProcessorId;
+ UINT8 ProcessorEid;
+ UINT8 IoSapicVector;
+ UINT32 GlobalSystemInterrupt;
+ UINT32 PlatformInterruptSourceFlags;
+} EFI_ACPI_5_1_PLATFORM_INTERRUPT_SOURCES_STRUCTURE;
+
+///
+/// Platform Interrupt Source Flags.
+/// All other bits are reserved and must be set to 0.
+///
+#define EFI_ACPI_5_1_CPEI_PROCESSOR_OVERRIDE BIT0
+
+///
+/// Processor Local x2APIC Structure Definition
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 Reserved[2];
+ UINT32 X2ApicId;
+ UINT32 Flags;
+ UINT32 AcpiProcessorUid;
+} EFI_ACPI_5_1_PROCESSOR_LOCAL_X2APIC_STRUCTURE;
+
+///
+/// Local x2APIC NMI Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Flags;
+ UINT32 AcpiProcessorUid;
+ UINT8 LocalX2ApicLint;
+ UINT8 Reserved[3];
+} EFI_ACPI_5_1_LOCAL_X2APIC_NMI_STRUCTURE;
+
+///
+/// GIC Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Reserved;
+ UINT32 CPUInterfaceNumber;
+ UINT32 AcpiProcessorUid;
+ UINT32 Flags;
+ UINT32 ParkingProtocolVersion;
+ UINT32 PerformanceInterruptGsiv;
+ UINT64 ParkedAddress;
+ UINT64 PhysicalBaseAddress;
+ UINT64 GICV;
+ UINT64 GICH;
+ UINT32 VGICMaintenanceInterrupt;
+ UINT64 GICRBaseAddress;
+ UINT64 MPIDR;
+} EFI_ACPI_5_1_GIC_STRUCTURE;
+
+///
+/// GIC Flags. All other bits are reserved and must be 0.
+///
+#define EFI_ACPI_5_1_GIC_ENABLED BIT0
+#define EFI_ACPI_5_1_PERFORMANCE_INTERRUPT_MODEL BIT1
+#define EFI_ACPI_5_1_VGIC_MAINTENANCE_INTERRUPT_MODE_FLAGS BIT2
+
+///
+/// GIC Distributor Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Reserved1;
+ UINT32 GicId;
+ UINT64 PhysicalBaseAddress;
+ UINT32 SystemVectorBase;
+ UINT8 GicVersion;
+ UINT8 Reserved2[3];
+} EFI_ACPI_5_1_GIC_DISTRIBUTOR_STRUCTURE;
+
+///
+/// GIC Version
+///
+#define EFI_ACPI_5_1_GIC_V1 0x01
+#define EFI_ACPI_5_1_GIC_V2 0x02
+#define EFI_ACPI_5_1_GIC_V3 0x03
+#define EFI_ACPI_5_1_GIC_V4 0x04
+
+///
+/// GIC MSI Frame Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Reserved1;
+ UINT32 GicMsiFrameId;
+ UINT64 PhysicalBaseAddress;
+ UINT32 Flags;
+ UINT16 SPICount;
+ UINT16 SPIBase;
+} EFI_ACPI_5_1_GIC_MSI_FRAME_STRUCTURE;
+
+///
+/// GIC MSI Frame Flags. All other bits are reserved and must be 0.
+///
+#define EFI_ACPI_5_1_SPI_COUNT_BASE_SELECT BIT0
+
+///
+/// GICR Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Reserved;
+ UINT64 DiscoveryRangeBaseAddress;
+ UINT32 DiscoveryRangeLength;
+} EFI_ACPI_5_1_GICR_STRUCTURE;
+
+///
+/// Smart Battery Description Table (SBST)
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 WarningEnergyLevel;
+ UINT32 LowEnergyLevel;
+ UINT32 CriticalEnergyLevel;
+} EFI_ACPI_5_1_SMART_BATTERY_DESCRIPTION_TABLE;
+
+///
+/// SBST Version (as defined in ACPI 5.1 spec.)
+///
+#define EFI_ACPI_5_1_SMART_BATTERY_DESCRIPTION_TABLE_REVISION 0x01
+
+///
+/// Embedded Controller Boot Resources Table (ECDT)
+/// The table is followed by a null terminated ASCII string that contains
+/// a fully qualified reference to the name space object.
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE EcControl;
+ EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE EcData;
+ UINT32 Uid;
+ UINT8 GpeBit;
+} EFI_ACPI_5_1_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE;
+
+///
+/// ECDT Version (as defined in ACPI 5.1 spec.)
+///
+#define EFI_ACPI_5_1_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE_REVISION 0x01
+
+///
+/// System Resource Affinity Table (SRAT). The rest of the table
+/// must be defined in a platform specific manner.
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 Reserved1; ///< Must be set to 1
+ UINT64 Reserved2;
+} EFI_ACPI_5_1_SYSTEM_RESOURCE_AFFINITY_TABLE_HEADER;
+
+///
+/// SRAT Version (as defined in ACPI 5.1 spec.)
+///
+#define EFI_ACPI_5_1_SYSTEM_RESOURCE_AFFINITY_TABLE_REVISION 0x03
+
+//
+// SRAT structure types.
+// All other values between 0x04 an 0xFF are reserved and
+// will be ignored by OSPM.
+//
+#define EFI_ACPI_5_1_PROCESSOR_LOCAL_APIC_SAPIC_AFFINITY 0x00
+#define EFI_ACPI_5_1_MEMORY_AFFINITY 0x01
+#define EFI_ACPI_5_1_PROCESSOR_LOCAL_X2APIC_AFFINITY 0x02
+#define EFI_ACPI_5_1_GICC_AFFINITY 0x03
+
+///
+/// Processor Local APIC/SAPIC Affinity Structure Definition
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 ProximityDomain7To0;
+ UINT8 ApicId;
+ UINT32 Flags;
+ UINT8 LocalSapicEid;
+ UINT8 ProximityDomain31To8[3];
+ UINT32 ClockDomain;
+} EFI_ACPI_5_1_PROCESSOR_LOCAL_APIC_SAPIC_AFFINITY_STRUCTURE;
+
+///
+/// Local APIC/SAPIC Flags. All other bits are reserved and must be 0.
+///
+#define EFI_ACPI_5_1_PROCESSOR_LOCAL_APIC_SAPIC_ENABLED (1 << 0)
+
+///
+/// Memory Affinity Structure Definition
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT32 ProximityDomain;
+ UINT16 Reserved1;
+ UINT32 AddressBaseLow;
+ UINT32 AddressBaseHigh;
+ UINT32 LengthLow;
+ UINT32 LengthHigh;
+ UINT32 Reserved2;
+ UINT32 Flags;
+ UINT64 Reserved3;
+} EFI_ACPI_5_1_MEMORY_AFFINITY_STRUCTURE;
+
+//
+// Memory Flags. All other bits are reserved and must be 0.
+//
+#define EFI_ACPI_5_1_MEMORY_ENABLED (1 << 0)
+#define EFI_ACPI_5_1_MEMORY_HOT_PLUGGABLE (1 << 1)
+#define EFI_ACPI_5_1_MEMORY_NONVOLATILE (1 << 2)
+
+///
+/// Processor Local x2APIC Affinity Structure Definition
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 Reserved1[2];
+ UINT32 ProximityDomain;
+ UINT32 X2ApicId;
+ UINT32 Flags;
+ UINT32 ClockDomain;
+ UINT8 Reserved2[4];
+} EFI_ACPI_5_1_PROCESSOR_LOCAL_X2APIC_AFFINITY_STRUCTURE;
+
+///
+/// GICC Affinity Structure Definition
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT32 ProximityDomain;
+ UINT32 AcpiProcessorUid;
+ UINT32 Flags;
+ UINT32 ClockDomain;
+} EFI_ACPI_5_1_GICC_AFFINITY_STRUCTURE;
+
+///
+/// GICC Flags. All other bits are reserved and must be 0.
+///
+#define EFI_ACPI_5_1_GICC_ENABLED (1 << 0)
+
+///
+/// System Locality Distance Information Table (SLIT).
+/// The rest of the table is a matrix.
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT64 NumberOfSystemLocalities;
+} EFI_ACPI_5_1_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_HEADER;
+
+///
+/// SLIT Version (as defined in ACPI 5.1 spec.)
+///
+#define EFI_ACPI_5_1_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_REVISION 0x01
+
+///
+/// Corrected Platform Error Polling Table (CPEP)
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT8 Reserved[8];
+} EFI_ACPI_5_1_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_HEADER;
+
+///
+/// CPEP Version (as defined in ACPI 5.1 spec.)
+///
+#define EFI_ACPI_5_1_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_REVISION 0x01
+
+//
+// CPEP processor structure types.
+//
+#define EFI_ACPI_5_1_CPEP_PROCESSOR_APIC_SAPIC 0x00
+
+///
+/// Corrected Platform Error Polling Processor Structure Definition
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 ProcessorId;
+ UINT8 ProcessorEid;
+ UINT32 PollingInterval;
+} EFI_ACPI_5_1_CPEP_PROCESSOR_APIC_SAPIC_STRUCTURE;
+
+///
+/// Maximum System Characteristics Table (MSCT)
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 OffsetProxDomInfo;
+ UINT32 MaximumNumberOfProximityDomains;
+ UINT32 MaximumNumberOfClockDomains;
+ UINT64 MaximumPhysicalAddress;
+} EFI_ACPI_5_1_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_HEADER;
+
+///
+/// MSCT Version (as defined in ACPI 5.1 spec.)
+///
+#define EFI_ACPI_5_1_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_REVISION 0x01
+
+///
+/// Maximum Proximity Domain Information Structure Definition
+///
+typedef struct {
+ UINT8 Revision;
+ UINT8 Length;
+ UINT32 ProximityDomainRangeLow;
+ UINT32 ProximityDomainRangeHigh;
+ UINT32 MaximumProcessorCapacity;
+ UINT64 MaximumMemoryCapacity;
+} EFI_ACPI_5_1_MAXIMUM_PROXIMITY_DOMAIN_INFORMATION_STRUCTURE;
+
+///
+/// ACPI RAS Feature Table definition.
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT8 PlatformCommunicationChannelIdentifier[12];
+} EFI_ACPI_5_1_RAS_FEATURE_TABLE;
+
+///
+/// RASF Version (as defined in ACPI 5.1 spec.)
+///
+#define EFI_ACPI_5_1_RAS_FEATURE_TABLE_REVISION 0x01
+
+///
+/// ACPI RASF Platform Communication Channel Shared Memory Region definition.
+///
+typedef struct {
+ UINT32 Signature;
+ UINT16 Command;
+ UINT16 Status;
+ UINT16 Version;
+ UINT8 RASCapabilities[16];
+ UINT8 SetRASCapabilities[16];
+ UINT16 NumberOfRASFParameterBlocks;
+ UINT32 SetRASCapabilitiesStatus;
+} EFI_ACPI_5_1_RASF_PLATFORM_COMMUNICATION_CHANNEL_SHARED_MEMORY_REGION;
+
+///
+/// ACPI RASF PCC command code
+///
+#define EFI_ACPI_5_1_RASF_PCC_COMMAND_CODE_EXECUTE_RASF_COMMAND 0x01
+
+///
+/// ACPI RASF Platform RAS Capabilities
+///
+#define EFI_ACPI_5_1_RASF_PLATFORM_RAS_CAPABILITY_HARDWARE_BASED_PATROL_SCRUB_SUPPOTED 0x01
+#define EFI_ACPI_5_1_RASF_PLATFORM_RAS_CAPABILITY_HARDWARE_BASED_PATROL_SCRUB_SUPPOTED_AND_EXPOSED_TO_SOFTWARE 0x02
+
+///
+/// ACPI RASF Parameter Block structure for PATROL_SCRUB
+///
+typedef struct {
+ UINT16 Type;
+ UINT16 Version;
+ UINT16 Length;
+ UINT16 PatrolScrubCommand;
+ UINT64 RequestedAddressRange[2];
+ UINT64 ActualAddressRange[2];
+ UINT16 Flags;
+ UINT8 RequestedSpeed;
+} EFI_ACPI_5_1_RASF_PATROL_SCRUB_PLATFORM_BLOCK_STRUCTURE;
+
+///
+/// ACPI RASF Patrol Scrub command
+///
+#define EFI_ACPI_5_1_RASF_PATROL_SCRUB_COMMAND_GET_PATROL_PARAMETERS 0x01
+#define EFI_ACPI_5_1_RASF_PATROL_SCRUB_COMMAND_START_PATROL_SCRUBBER 0x02
+#define EFI_ACPI_5_1_RASF_PATROL_SCRUB_COMMAND_STOP_PATROL_SCRUBBER 0x03
+
+///
+/// Memory Power State Table definition.
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT8 PlatformCommunicationChannelIdentifier;
+ UINT8 Reserved[3];
+ // Memory Power Node Structure
+ // Memory Power State Characteristics
+} EFI_ACPI_5_1_MEMORY_POWER_STATUS_TABLE;
+
+///
+/// MPST Version (as defined in ACPI 5.1 spec.)
+///
+#define EFI_ACPI_5_1_MEMORY_POWER_STATE_TABLE_REVISION 0x01
+
+///
+/// MPST Platform Communication Channel Shared Memory Region definition.
+///
+typedef struct {
+ UINT32 Signature;
+ UINT16 Command;
+ UINT16 Status;
+ UINT32 MemoryPowerCommandRegister;
+ UINT32 MemoryPowerStatusRegister;
+ UINT32 PowerStateId;
+ UINT32 MemoryPowerNodeId;
+ UINT64 MemoryEnergyConsumed;
+ UINT64 ExpectedAveragePowerComsuned;
+} EFI_ACPI_5_1_MPST_PLATFORM_COMMUNICATION_CHANNEL_SHARED_MEMORY_REGION;
+
+///
+/// ACPI MPST PCC command code
+///
+#define EFI_ACPI_5_1_MPST_PCC_COMMAND_CODE_EXECUTE_MPST_COMMAND 0x03
+
+///
+/// ACPI MPST Memory Power command
+///
+#define EFI_ACPI_5_1_MPST_MEMORY_POWER_COMMAND_GET_MEMORY_POWER_STATE 0x01
+#define EFI_ACPI_5_1_MPST_MEMORY_POWER_COMMAND_SET_MEMORY_POWER_STATE 0x02
+#define EFI_ACPI_5_1_MPST_MEMORY_POWER_COMMAND_GET_AVERAGE_POWER_CONSUMED 0x03
+#define EFI_ACPI_5_1_MPST_MEMORY_POWER_COMMAND_GET_MEMORY_ENERGY_CONSUMED 0x04
+
+///
+/// MPST Memory Power Node Table
+///
+typedef struct {
+ UINT8 PowerStateValue;
+ UINT8 PowerStateInformationIndex;
+} EFI_ACPI_5_1_MPST_MEMORY_POWER_STATE;
+
+typedef struct {
+ UINT8 Flag;
+ UINT8 Reserved;
+ UINT16 MemoryPowerNodeId;
+ UINT32 Length;
+ UINT64 AddressBase;
+ UINT64 AddressLength;
+ UINT32 NumberOfPowerStates;
+ UINT32 NumberOfPhysicalComponents;
+ // EFI_ACPI_5_1_MPST_MEMORY_POWER_STATE MemoryPowerState[NumberOfPowerStates];
+ // UINT16 PhysicalComponentIdentifier[NumberOfPhysicalComponents];
+} EFI_ACPI_5_1_MPST_MEMORY_POWER_STRUCTURE;
+
+#define EFI_ACPI_5_1_MPST_MEMORY_POWER_STRUCTURE_FLAG_ENABLE 0x01
+#define EFI_ACPI_5_1_MPST_MEMORY_POWER_STRUCTURE_FLAG_POWER_MANAGED 0x02
+#define EFI_ACPI_5_1_MPST_MEMORY_POWER_STRUCTURE_FLAG_HOT_PLUGGABLE 0x04
+
+typedef struct {
+ UINT16 MemoryPowerNodeCount;
+ UINT8 Reserved[2];
+} EFI_ACPI_5_1_MPST_MEMORY_POWER_NODE_TABLE;
+
+///
+/// MPST Memory Power State Characteristics Table
+///
+typedef struct {
+ UINT8 PowerStateStructureID;
+ UINT8 Flag;
+ UINT16 Reserved;
+ UINT32 AveragePowerConsumedInMPS0;
+ UINT32 RelativePowerSavingToMPS0;
+ UINT64 ExitLatencyToMPS0;
+} EFI_ACPI_5_1_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE;
+
+#define EFI_ACPI_5_1_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_MEMORY_CONTENT_PRESERVED 0x01
+#define EFI_ACPI_5_1_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_AUTONOMOUS_MEMORY_POWER_STATE_ENTRY 0x02
+#define EFI_ACPI_5_1_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_AUTONOMOUS_MEMORY_POWER_STATE_EXIT 0x04
+
+typedef struct {
+ UINT16 MemoryPowerStateCharacteristicsCount;
+ UINT8 Reserved[2];
+} EFI_ACPI_5_1_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_TABLE;
+
+///
+/// Memory Topology Table definition.
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 Reserved;
+} EFI_ACPI_5_1_MEMORY_TOPOLOGY_TABLE;
+
+///
+/// PMTT Version (as defined in ACPI 5.1 spec.)
+///
+#define EFI_ACPI_5_1_MEMORY_TOPOLOGY_TABLE_REVISION 0x01
+
+///
+/// Common Memory Aggregator Device Structure.
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Reserved;
+ UINT16 Length;
+ UINT16 Flags;
+ UINT16 Reserved1;
+} EFI_ACPI_5_1_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE;
+
+///
+/// Memory Aggregator Device Type
+///
+#define EFI_ACPI_5_1_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_SOCKET 0x0
+#define EFI_ACPI_5_1_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_MEMORY_CONTROLLER 0x1
+#define EFI_ACPI_5_1_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_DIMM 0x2
+
+///
+/// Socket Memory Aggregator Device Structure.
+///
+typedef struct {
+ EFI_ACPI_5_1_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE Header;
+ UINT16 SocketIdentifier;
+ UINT16 Reserved;
+ // EFI_ACPI_5_1_PMMT_MEMORY_CONTROLLER_MEMORY_AGGREGATOR_DEVICE_STRUCTURE MemoryController[];
+} EFI_ACPI_5_1_PMMT_SOCKET_MEMORY_AGGREGATOR_DEVICE_STRUCTURE;
+
+///
+/// MemoryController Memory Aggregator Device Structure.
+///
+typedef struct {
+ EFI_ACPI_5_1_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE Header;
+ UINT32 ReadLatency;
+ UINT32 WriteLatency;
+ UINT32 ReadBandwidth;
+ UINT32 WriteBandwidth;
+ UINT16 OptimalAccessUnit;
+ UINT16 OptimalAccessAlignment;
+ UINT16 Reserved;
+ UINT16 NumberOfProximityDomains;
+ // UINT32 ProximityDomain[NumberOfProximityDomains];
+ // EFI_ACPI_5_1_PMMT_DIMM_MEMORY_AGGREGATOR_DEVICE_STRUCTURE PhysicalComponent[];
+} EFI_ACPI_5_1_PMMT_MEMORY_CONTROLLER_MEMORY_AGGREGATOR_DEVICE_STRUCTURE;
+
+///
+/// DIMM Memory Aggregator Device Structure.
+///
+typedef struct {
+ EFI_ACPI_5_1_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE Header;
+ UINT16 PhysicalComponentIdentifier;
+ UINT16 Reserved;
+ UINT32 SizeOfDimm;
+ UINT32 SmbiosHandle;
+} EFI_ACPI_5_1_PMMT_DIMM_MEMORY_AGGREGATOR_DEVICE_STRUCTURE;
+
+///
+/// Boot Graphics Resource Table definition.
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ ///
+ /// 2-bytes (16 bit) version ID. This value must be 1.
+ ///
+ UINT16 Version;
+ ///
+ /// 1-byte status field indicating current status about the table.
+ /// Bits[7:1] = Reserved (must be zero)
+ /// Bit [0] = Valid. A one indicates the boot image graphic is valid.
+ ///
+ UINT8 Status;
+ ///
+ /// 1-byte enumerated type field indicating format of the image.
+ /// 0 = Bitmap
+ /// 1 - 255 Reserved (for future use)
+ ///
+ UINT8 ImageType;
+ ///
+ /// 8-byte (64 bit) physical address pointing to the firmware's in-memory copy
+ /// of the image bitmap.
+ ///
+ UINT64 ImageAddress;
+ ///
+ /// A 4-byte (32-bit) unsigned long describing the display X-offset of the boot image.
+ /// (X, Y) display offset of the top left corner of the boot image.
+ /// The top left corner of the display is at offset (0, 0).
+ ///
+ UINT32 ImageOffsetX;
+ ///
+ /// A 4-byte (32-bit) unsigned long describing the display Y-offset of the boot image.
+ /// (X, Y) display offset of the top left corner of the boot image.
+ /// The top left corner of the display is at offset (0, 0).
+ ///
+ UINT32 ImageOffsetY;
+} EFI_ACPI_5_1_BOOT_GRAPHICS_RESOURCE_TABLE;
+
+///
+/// BGRT Revision
+///
+#define EFI_ACPI_5_1_BOOT_GRAPHICS_RESOURCE_TABLE_REVISION 1
+
+///
+/// BGRT Version
+///
+#define EFI_ACPI_5_1_BGRT_VERSION 0x01
+
+///
+/// BGRT Status
+///
+#define EFI_ACPI_5_1_BGRT_STATUS_NOT_DISPLAYED 0x00
+#define EFI_ACPI_5_1_BGRT_STATUS_DISPLAYED 0x01
+
+///
+/// BGRT Image Type
+///
+#define EFI_ACPI_5_1_BGRT_IMAGE_TYPE_BMP 0x00
+
+///
+/// FPDT Version (as defined in ACPI 5.1 spec.)
+///
+#define EFI_ACPI_5_1_FIRMWARE_PERFORMANCE_DATA_TABLE_REVISION 0x01
+
+///
+/// FPDT Performance Record Types
+///
+#define EFI_ACPI_5_1_FPDT_RECORD_TYPE_FIRMWARE_BASIC_BOOT_POINTER 0x0000
+#define EFI_ACPI_5_1_FPDT_RECORD_TYPE_S3_PERFORMANCE_TABLE_POINTER 0x0001
+
+///
+/// FPDT Performance Record Revision
+///
+#define EFI_ACPI_5_1_FPDT_RECORD_REVISION_FIRMWARE_BASIC_BOOT_POINTER 0x01
+#define EFI_ACPI_5_1_FPDT_RECORD_REVISION_S3_PERFORMANCE_TABLE_POINTER 0x01
+
+///
+/// FPDT Runtime Performance Record Types
+///
+#define EFI_ACPI_5_1_FPDT_RUNTIME_RECORD_TYPE_S3_RESUME 0x0000
+#define EFI_ACPI_5_1_FPDT_RUNTIME_RECORD_TYPE_S3_SUSPEND 0x0001
+#define EFI_ACPI_5_1_FPDT_RUNTIME_RECORD_TYPE_FIRMWARE_BASIC_BOOT 0x0002
+
+///
+/// FPDT Runtime Performance Record Revision
+///
+#define EFI_ACPI_5_1_FPDT_RUNTIME_RECORD_REVISION_S3_RESUME 0x01
+#define EFI_ACPI_5_1_FPDT_RUNTIME_RECORD_REVISION_S3_SUSPEND 0x01
+#define EFI_ACPI_5_1_FPDT_RUNTIME_RECORD_REVISION_FIRMWARE_BASIC_BOOT 0x02
+
+///
+/// FPDT Performance Record header
+///
+typedef struct {
+ UINT16 Type;
+ UINT8 Length;
+ UINT8 Revision;
+} EFI_ACPI_5_1_FPDT_PERFORMANCE_RECORD_HEADER;
+
+///
+/// FPDT Performance Table header
+///
+typedef struct {
+ UINT32 Signature;
+ UINT32 Length;
+} EFI_ACPI_5_1_FPDT_PERFORMANCE_TABLE_HEADER;
+
+///
+/// FPDT Firmware Basic Boot Performance Pointer Record Structure
+///
+typedef struct {
+ EFI_ACPI_5_1_FPDT_PERFORMANCE_RECORD_HEADER Header;
+ UINT32 Reserved;
+ ///
+ /// 64-bit processor-relative physical address of the Basic Boot Performance Table.
+ ///
+ UINT64 BootPerformanceTablePointer;
+} EFI_ACPI_5_1_FPDT_BOOT_PERFORMANCE_TABLE_POINTER_RECORD;
+
+///
+/// FPDT S3 Performance Table Pointer Record Structure
+///
+typedef struct {
+ EFI_ACPI_5_1_FPDT_PERFORMANCE_RECORD_HEADER Header;
+ UINT32 Reserved;
+ ///
+ /// 64-bit processor-relative physical address of the S3 Performance Table.
+ ///
+ UINT64 S3PerformanceTablePointer;
+} EFI_ACPI_5_1_FPDT_S3_PERFORMANCE_TABLE_POINTER_RECORD;
+
+///
+/// FPDT Firmware Basic Boot Performance Record Structure
+///
+typedef struct {
+ EFI_ACPI_5_1_FPDT_PERFORMANCE_RECORD_HEADER Header;
+ UINT32 Reserved;
+ ///
+ /// Timer value logged at the beginning of firmware image execution.
+ /// This may not always be zero or near zero.
+ ///
+ UINT64 ResetEnd;
+ ///
+ /// Timer value logged just prior to loading the OS boot loader into memory.
+ /// For non-UEFI compatible boots, this field must be zero.
+ ///
+ UINT64 OsLoaderLoadImageStart;
+ ///
+ /// Timer value logged just prior to launching the previously loaded OS boot loader image.
+ /// For non-UEFI compatible boots, the timer value logged will be just prior
+ /// to the INT 19h handler invocation.
+ ///
+ UINT64 OsLoaderStartImageStart;
+ ///
+ /// Timer value logged at the point when the OS loader calls the
+ /// ExitBootServices function for UEFI compatible firmware.
+ /// For non-UEFI compatible boots, this field must be zero.
+ ///
+ UINT64 ExitBootServicesEntry;
+ ///
+ /// Timer value logged at the point just prior to when the OS loader gaining
+ /// control back from calls the ExitBootServices function for UEFI compatible firmware.
+ /// For non-UEFI compatible boots, this field must be zero.
+ ///
+ UINT64 ExitBootServicesExit;
+} EFI_ACPI_5_1_FPDT_FIRMWARE_BASIC_BOOT_RECORD;
+
+///
+/// FPDT Firmware Basic Boot Performance Table signature
+///
+#define EFI_ACPI_5_1_FPDT_BOOT_PERFORMANCE_TABLE_SIGNATURE SIGNATURE_32('F', 'B', 'P', 'T')
+
+//
+// FPDT Firmware Basic Boot Performance Table
+//
+typedef struct {
+ EFI_ACPI_5_1_FPDT_PERFORMANCE_TABLE_HEADER Header;
+ //
+ // one or more Performance Records.
+ //
+} EFI_ACPI_5_1_FPDT_FIRMWARE_BASIC_BOOT_TABLE;
+
+///
+/// FPDT "S3PT" S3 Performance Table
+///
+#define EFI_ACPI_5_1_FPDT_S3_PERFORMANCE_TABLE_SIGNATURE SIGNATURE_32('S', '3', 'P', 'T')
+
+//
+// FPDT Firmware S3 Boot Performance Table
+//
+typedef struct {
+ EFI_ACPI_5_1_FPDT_PERFORMANCE_TABLE_HEADER Header;
+ //
+ // one or more Performance Records.
+ //
+} EFI_ACPI_5_1_FPDT_FIRMWARE_S3_BOOT_TABLE;
+
+///
+/// FPDT Basic S3 Resume Performance Record
+///
+typedef struct {
+ EFI_ACPI_5_1_FPDT_PERFORMANCE_RECORD_HEADER Header;
+ ///
+ /// A count of the number of S3 resume cycles since the last full boot sequence.
+ ///
+ UINT32 ResumeCount;
+ ///
+ /// Timer recorded at the end of BIOS S3 resume, just prior to handoff to the
+ /// OS waking vector. Only the most recent resume cycle's time is retained.
+ ///
+ UINT64 FullResume;
+ ///
+ /// Average timer value of all resume cycles logged since the last full boot
+ /// sequence, including the most recent resume. Note that the entire log of
+ /// timer values does not need to be retained in order to calculate this average.
+ ///
+ UINT64 AverageResume;
+} EFI_ACPI_5_1_FPDT_S3_RESUME_RECORD;
+
+///
+/// FPDT Basic S3 Suspend Performance Record
+///
+typedef struct {
+ EFI_ACPI_5_1_FPDT_PERFORMANCE_RECORD_HEADER Header;
+ ///
+ /// Timer value recorded at the OS write to SLP_TYP upon entry to S3.
+ /// Only the most recent suspend cycle's timer value is retained.
+ ///
+ UINT64 SuspendStart;
+ ///
+ /// Timer value recorded at the final firmware write to SLP_TYP (or other
+ /// mechanism) used to trigger hardware entry to S3.
+ /// Only the most recent suspend cycle's timer value is retained.
+ ///
+ UINT64 SuspendEnd;
+} EFI_ACPI_5_1_FPDT_S3_SUSPEND_RECORD;
+
+///
+/// Firmware Performance Record Table definition.
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+} EFI_ACPI_5_1_FIRMWARE_PERFORMANCE_RECORD_TABLE;
+
+///
+/// Generic Timer Description Table definition.
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT64 CntControlBasePhysicalAddress;
+ UINT32 Reserved;
+ UINT32 SecurePL1TimerGSIV;
+ UINT32 SecurePL1TimerFlags;
+ UINT32 NonSecurePL1TimerGSIV;
+ UINT32 NonSecurePL1TimerFlags;
+ UINT32 VirtualTimerGSIV;
+ UINT32 VirtualTimerFlags;
+ UINT32 NonSecurePL2TimerGSIV;
+ UINT32 NonSecurePL2TimerFlags;
+ UINT64 CntReadBasePhysicalAddress;
+ UINT32 PlatformTimerCount;
+ UINT32 PlatformTimerOffset;
+} EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE;
+
+///
+/// GTDT Version (as defined in ACPI 5.1 spec.)
+///
+#define EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION 0x02
+
+///
+/// Timer Flags. All other bits are reserved and must be 0.
+///
+#define EFI_ACPI_5_1_GTDT_TIMER_FLAG_TIMER_INTERRUPT_MODE BIT0
+#define EFI_ACPI_5_1_GTDT_TIMER_FLAG_TIMER_INTERRUPT_POLARITY BIT1
+#define EFI_ACPI_5_1_GTDT_TIMER_FLAG_ALWAYS_ON_CAPABILITY BIT2
+
+///
+/// Platform Timer Type
+///
+#define EFI_ACPI_5_1_GTDT_GT_BLOCK 0
+#define EFI_ACPI_5_1_GTDT_SBSA_GENERIC_WATCHDOG 1
+
+///
+/// GT Block Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT16 Length;
+ UINT8 Reserved;
+ UINT64 CntCtlBase;
+ UINT32 GTBlockTimerCount;
+ UINT32 GTBlockTimerOffset;
+} EFI_ACPI_5_1_GTDT_GT_BLOCK_STRUCTURE;
+
+///
+/// GT Block Timer Structure
+///
+typedef struct {
+ UINT8 GTFrameNumber;
+ UINT8 Reserved[3];
+ UINT64 CntBaseX;
+ UINT64 CntEL0BaseX;
+ UINT32 GTxPhysicalTimerGSIV;
+ UINT32 GTxPhysicalTimerFlags;
+ UINT32 GTxVirtualTimerGSIV;
+ UINT32 GTxVirtualTimerFlags;
+ UINT32 GTxCommonFlags;
+} EFI_ACPI_5_1_GTDT_GT_BLOCK_TIMER_STRUCTURE;
+
+///
+/// GT Block Physical Timers and Virtual Timers Flags. All other bits are reserved and must be 0.
+///
+#define EFI_ACPI_5_1_GTDT_GT_BLOCK_TIMER_FLAG_TIMER_INTERRUPT_MODE BIT0
+#define EFI_ACPI_5_1_GTDT_GT_BLOCK_TIMER_FLAG_TIMER_INTERRUPT_POLARITY BIT1
+
+///
+/// Common Flags Flags. All other bits are reserved and must be 0.
+///
+#define EFI_ACPI_5_1_GTDT_GT_BLOCK_COMMON_FLAG_SECURE_TIMER BIT0
+#define EFI_ACPI_5_1_GTDT_GT_BLOCK_COMMON_FLAG_ALWAYS_ON_CAPABILITY BIT1
+
+///
+/// SBSA Generic Watchdog Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT16 Length;
+ UINT8 Reserved;
+ UINT64 RefreshFramePhysicalAddress;
+ UINT64 WatchdogControlFramePhysicalAddress;
+ UINT32 WatchdogTimerGSIV;
+ UINT32 WatchdogTimerFlags;
+} EFI_ACPI_5_1_GTDT_SBSA_GENERIC_WATCHDOG_STRUCTURE;
+
+///
+/// SBSA Generic Watchdog Timer Flags. All other bits are reserved and must be 0.
+///
+#define EFI_ACPI_5_1_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_TIMER_INTERRUPT_MODE BIT0
+#define EFI_ACPI_5_1_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_TIMER_INTERRUPT_POLARITY BIT1
+#define EFI_ACPI_5_1_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_SECURE_TIMER BIT2
+
+///
+/// Boot Error Record Table (BERT)
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 BootErrorRegionLength;
+ UINT64 BootErrorRegion;
+} EFI_ACPI_5_1_BOOT_ERROR_RECORD_TABLE_HEADER;
+
+///
+/// BERT Version (as defined in ACPI 5.1 spec.)
+///
+#define EFI_ACPI_5_1_BOOT_ERROR_RECORD_TABLE_REVISION 0x01
+
+///
+/// Boot Error Region Block Status Definition
+///
+typedef struct {
+ UINT32 UncorrectableErrorValid : 1;
+ UINT32 CorrectableErrorValid : 1;
+ UINT32 MultipleUncorrectableErrors : 1;
+ UINT32 MultipleCorrectableErrors : 1;
+ UINT32 ErrorDataEntryCount : 10;
+ UINT32 Reserved : 18;
+} EFI_ACPI_5_1_ERROR_BLOCK_STATUS;
+
+///
+/// Boot Error Region Definition
+///
+typedef struct {
+ EFI_ACPI_5_1_ERROR_BLOCK_STATUS BlockStatus;
+ UINT32 RawDataOffset;
+ UINT32 RawDataLength;
+ UINT32 DataLength;
+ UINT32 ErrorSeverity;
+} EFI_ACPI_5_1_BOOT_ERROR_REGION_STRUCTURE;
+
+//
+// Boot Error Severity types
+//
+#define EFI_ACPI_5_1_ERROR_SEVERITY_RECOVERABLE 0x00
+#define EFI_ACPI_5_1_ERROR_SEVERITY_FATAL 0x01
+#define EFI_ACPI_5_1_ERROR_SEVERITY_CORRECTED 0x02
+#define EFI_ACPI_5_1_ERROR_SEVERITY_NONE 0x03
+//
+// The term 'Correctable' is no longer being used as an error severity of the
+// reported error since ACPI Specification Version 5.1 Errata B.
+// The below macro is considered as deprecated and should no longer be used.
+//
+#define EFI_ACPI_5_1_ERROR_SEVERITY_CORRECTABLE 0x00
+
+///
+/// Generic Error Data Entry Definition
+///
+typedef struct {
+ UINT8 SectionType[16];
+ UINT32 ErrorSeverity;
+ UINT16 Revision;
+ UINT8 ValidationBits;
+ UINT8 Flags;
+ UINT32 ErrorDataLength;
+ UINT8 FruId[16];
+ UINT8 FruText[20];
+} EFI_ACPI_5_1_GENERIC_ERROR_DATA_ENTRY_STRUCTURE;
+
+///
+/// Generic Error Data Entry Version (as defined in ACPI 5.1 spec.)
+///
+#define EFI_ACPI_5_1_GENERIC_ERROR_DATA_ENTRY_REVISION 0x0201
+
+///
+/// HEST - Hardware Error Source Table
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 ErrorSourceCount;
+} EFI_ACPI_5_1_HARDWARE_ERROR_SOURCE_TABLE_HEADER;
+
+///
+/// HEST Version (as defined in ACPI 5.1 spec.)
+///
+#define EFI_ACPI_5_1_HARDWARE_ERROR_SOURCE_TABLE_REVISION 0x01
+
+//
+// Error Source structure types.
+//
+#define EFI_ACPI_5_1_IA32_ARCHITECTURE_MACHINE_CHECK_EXCEPTION 0x00
+#define EFI_ACPI_5_1_IA32_ARCHITECTURE_CORRECTED_MACHINE_CHECK 0x01
+#define EFI_ACPI_5_1_IA32_ARCHITECTURE_NMI_ERROR 0x02
+#define EFI_ACPI_5_1_PCI_EXPRESS_ROOT_PORT_AER 0x06
+#define EFI_ACPI_5_1_PCI_EXPRESS_DEVICE_AER 0x07
+#define EFI_ACPI_5_1_PCI_EXPRESS_BRIDGE_AER 0x08
+#define EFI_ACPI_5_1_GENERIC_HARDWARE_ERROR 0x09
+
+//
+// Error Source structure flags.
+//
+#define EFI_ACPI_5_1_ERROR_SOURCE_FLAG_FIRMWARE_FIRST (1 << 0)
+#define EFI_ACPI_5_1_ERROR_SOURCE_FLAG_GLOBAL (1 << 1)
+
+///
+/// IA-32 Architecture Machine Check Exception Structure Definition
+///
+typedef struct {
+ UINT16 Type;
+ UINT16 SourceId;
+ UINT8 Reserved0[2];
+ UINT8 Flags;
+ UINT8 Enabled;
+ UINT32 NumberOfRecordsToPreAllocate;
+ UINT32 MaxSectionsPerRecord;
+ UINT64 GlobalCapabilityInitData;
+ UINT64 GlobalControlInitData;
+ UINT8 NumberOfHardwareBanks;
+ UINT8 Reserved1[7];
+} EFI_ACPI_5_1_IA32_ARCHITECTURE_MACHINE_CHECK_EXCEPTION_STRUCTURE;
+
+///
+/// IA-32 Architecture Machine Check Bank Structure Definition
+///
+typedef struct {
+ UINT8 BankNumber;
+ UINT8 ClearStatusOnInitialization;
+ UINT8 StatusDataFormat;
+ UINT8 Reserved0;
+ UINT32 ControlRegisterMsrAddress;
+ UINT64 ControlInitData;
+ UINT32 StatusRegisterMsrAddress;
+ UINT32 AddressRegisterMsrAddress;
+ UINT32 MiscRegisterMsrAddress;
+} EFI_ACPI_5_1_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_BANK_STRUCTURE;
+
+///
+/// IA-32 Architecture Machine Check Bank Structure MCA data format
+///
+#define EFI_ACPI_5_1_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_IA32 0x00
+#define EFI_ACPI_5_1_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_INTEL64 0x01
+#define EFI_ACPI_5_1_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_AMD64 0x02
+
+//
+// Hardware Error Notification types. All other values are reserved
+//
+#define EFI_ACPI_5_1_HARDWARE_ERROR_NOTIFICATION_POLLED 0x00
+#define EFI_ACPI_5_1_HARDWARE_ERROR_NOTIFICATION_EXTERNAL_INTERRUPT 0x01
+#define EFI_ACPI_5_1_HARDWARE_ERROR_NOTIFICATION_LOCAL_INTERRUPT 0x02
+#define EFI_ACPI_5_1_HARDWARE_ERROR_NOTIFICATION_SCI 0x03
+#define EFI_ACPI_5_1_HARDWARE_ERROR_NOTIFICATION_NMI 0x04
+
+///
+/// Hardware Error Notification Configuration Write Enable Structure Definition
+///
+typedef struct {
+ UINT16 Type : 1;
+ UINT16 PollInterval : 1;
+ UINT16 SwitchToPollingThresholdValue : 1;
+ UINT16 SwitchToPollingThresholdWindow : 1;
+ UINT16 ErrorThresholdValue : 1;
+ UINT16 ErrorThresholdWindow : 1;
+ UINT16 Reserved : 10;
+} EFI_ACPI_5_1_HARDWARE_ERROR_NOTIFICATION_CONFIGURATION_WRITE_ENABLE_STRUCTURE;
+
+///
+/// Hardware Error Notification Structure Definition
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ EFI_ACPI_5_1_HARDWARE_ERROR_NOTIFICATION_CONFIGURATION_WRITE_ENABLE_STRUCTURE ConfigurationWriteEnable;
+ UINT32 PollInterval;
+ UINT32 Vector;
+ UINT32 SwitchToPollingThresholdValue;
+ UINT32 SwitchToPollingThresholdWindow;
+ UINT32 ErrorThresholdValue;
+ UINT32 ErrorThresholdWindow;
+} EFI_ACPI_5_1_HARDWARE_ERROR_NOTIFICATION_STRUCTURE;
+
+///
+/// IA-32 Architecture Corrected Machine Check Structure Definition
+///
+typedef struct {
+ UINT16 Type;
+ UINT16 SourceId;
+ UINT8 Reserved0[2];
+ UINT8 Flags;
+ UINT8 Enabled;
+ UINT32 NumberOfRecordsToPreAllocate;
+ UINT32 MaxSectionsPerRecord;
+ EFI_ACPI_5_1_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure;
+ UINT8 NumberOfHardwareBanks;
+ UINT8 Reserved1[3];
+} EFI_ACPI_5_1_IA32_ARCHITECTURE_CORRECTED_MACHINE_CHECK_STRUCTURE;
+
+///
+/// IA-32 Architecture NMI Error Structure Definition
+///
+typedef struct {
+ UINT16 Type;
+ UINT16 SourceId;
+ UINT8 Reserved0[2];
+ UINT32 NumberOfRecordsToPreAllocate;
+ UINT32 MaxSectionsPerRecord;
+ UINT32 MaxRawDataLength;
+} EFI_ACPI_5_1_IA32_ARCHITECTURE_NMI_ERROR_STRUCTURE;
+
+///
+/// PCI Express Root Port AER Structure Definition
+///
+typedef struct {
+ UINT16 Type;
+ UINT16 SourceId;
+ UINT8 Reserved0[2];
+ UINT8 Flags;
+ UINT8 Enabled;
+ UINT32 NumberOfRecordsToPreAllocate;
+ UINT32 MaxSectionsPerRecord;
+ UINT32 Bus;
+ UINT16 Device;
+ UINT16 Function;
+ UINT16 DeviceControl;
+ UINT8 Reserved1[2];
+ UINT32 UncorrectableErrorMask;
+ UINT32 UncorrectableErrorSeverity;
+ UINT32 CorrectableErrorMask;
+ UINT32 AdvancedErrorCapabilitiesAndControl;
+ UINT32 RootErrorCommand;
+} EFI_ACPI_5_1_PCI_EXPRESS_ROOT_PORT_AER_STRUCTURE;
+
+///
+/// PCI Express Device AER Structure Definition
+///
+typedef struct {
+ UINT16 Type;
+ UINT16 SourceId;
+ UINT8 Reserved0[2];
+ UINT8 Flags;
+ UINT8 Enabled;
+ UINT32 NumberOfRecordsToPreAllocate;
+ UINT32 MaxSectionsPerRecord;
+ UINT32 Bus;
+ UINT16 Device;
+ UINT16 Function;
+ UINT16 DeviceControl;
+ UINT8 Reserved1[2];
+ UINT32 UncorrectableErrorMask;
+ UINT32 UncorrectableErrorSeverity;
+ UINT32 CorrectableErrorMask;
+ UINT32 AdvancedErrorCapabilitiesAndControl;
+} EFI_ACPI_5_1_PCI_EXPRESS_DEVICE_AER_STRUCTURE;
+
+///
+/// PCI Express Bridge AER Structure Definition
+///
+typedef struct {
+ UINT16 Type;
+ UINT16 SourceId;
+ UINT8 Reserved0[2];
+ UINT8 Flags;
+ UINT8 Enabled;
+ UINT32 NumberOfRecordsToPreAllocate;
+ UINT32 MaxSectionsPerRecord;
+ UINT32 Bus;
+ UINT16 Device;
+ UINT16 Function;
+ UINT16 DeviceControl;
+ UINT8 Reserved1[2];
+ UINT32 UncorrectableErrorMask;
+ UINT32 UncorrectableErrorSeverity;
+ UINT32 CorrectableErrorMask;
+ UINT32 AdvancedErrorCapabilitiesAndControl;
+ UINT32 SecondaryUncorrectableErrorMask;
+ UINT32 SecondaryUncorrectableErrorSeverity;
+ UINT32 SecondaryAdvancedErrorCapabilitiesAndControl;
+} EFI_ACPI_5_1_PCI_EXPRESS_BRIDGE_AER_STRUCTURE;
+
+///
+/// Generic Hardware Error Source Structure Definition
+///
+typedef struct {
+ UINT16 Type;
+ UINT16 SourceId;
+ UINT16 RelatedSourceId;
+ UINT8 Flags;
+ UINT8 Enabled;
+ UINT32 NumberOfRecordsToPreAllocate;
+ UINT32 MaxSectionsPerRecord;
+ UINT32 MaxRawDataLength;
+ EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE ErrorStatusAddress;
+ EFI_ACPI_5_1_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure;
+ UINT32 ErrorStatusBlockLength;
+} EFI_ACPI_5_1_GENERIC_HARDWARE_ERROR_SOURCE_STRUCTURE;
+
+///
+/// Generic Error Status Definition
+///
+typedef struct {
+ EFI_ACPI_5_1_ERROR_BLOCK_STATUS BlockStatus;
+ UINT32 RawDataOffset;
+ UINT32 RawDataLength;
+ UINT32 DataLength;
+ UINT32 ErrorSeverity;
+} EFI_ACPI_5_1_GENERIC_ERROR_STATUS_STRUCTURE;
+
+///
+/// ERST - Error Record Serialization Table
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 SerializationHeaderSize;
+ UINT8 Reserved0[4];
+ UINT32 InstructionEntryCount;
+} EFI_ACPI_5_1_ERROR_RECORD_SERIALIZATION_TABLE_HEADER;
+
+///
+/// ERST Version (as defined in ACPI 5.1 spec.)
+///
+#define EFI_ACPI_5_1_ERROR_RECORD_SERIALIZATION_TABLE_REVISION 0x01
+
+///
+/// ERST Serialization Actions
+///
+#define EFI_ACPI_5_1_ERST_BEGIN_WRITE_OPERATION 0x00
+#define EFI_ACPI_5_1_ERST_BEGIN_READ_OPERATION 0x01
+#define EFI_ACPI_5_1_ERST_BEGIN_CLEAR_OPERATION 0x02
+#define EFI_ACPI_5_1_ERST_END_OPERATION 0x03
+#define EFI_ACPI_5_1_ERST_SET_RECORD_OFFSET 0x04
+#define EFI_ACPI_5_1_ERST_EXECUTE_OPERATION 0x05
+#define EFI_ACPI_5_1_ERST_CHECK_BUSY_STATUS 0x06
+#define EFI_ACPI_5_1_ERST_GET_COMMAND_STATUS 0x07
+#define EFI_ACPI_5_1_ERST_GET_RECORD_IDENTIFIER 0x08
+#define EFI_ACPI_5_1_ERST_SET_RECORD_IDENTIFIER 0x09
+#define EFI_ACPI_5_1_ERST_GET_RECORD_COUNT 0x0A
+#define EFI_ACPI_5_1_ERST_BEGIN_DUMMY_WRITE_OPERATION 0x0B
+#define EFI_ACPI_5_1_ERST_GET_ERROR_LOG_ADDRESS_RANGE 0x0D
+#define EFI_ACPI_5_1_ERST_GET_ERROR_LOG_ADDRESS_RANGE_LENGTH 0x0E
+#define EFI_ACPI_5_1_ERST_GET_ERROR_LOG_ADDRESS_RANGE_ATTRIBUTES 0x0F
+
+///
+/// ERST Action Command Status
+///
+#define EFI_ACPI_5_1_ERST_STATUS_SUCCESS 0x00
+#define EFI_ACPI_5_1_ERST_STATUS_NOT_ENOUGH_SPACE 0x01
+#define EFI_ACPI_5_1_ERST_STATUS_HARDWARE_NOT_AVAILABLE 0x02
+#define EFI_ACPI_5_1_ERST_STATUS_FAILED 0x03
+#define EFI_ACPI_5_1_ERST_STATUS_RECORD_STORE_EMPTY 0x04
+#define EFI_ACPI_5_1_ERST_STATUS_RECORD_NOT_FOUND 0x05
+
+///
+/// ERST Serialization Instructions
+///
+#define EFI_ACPI_5_1_ERST_READ_REGISTER 0x00
+#define EFI_ACPI_5_1_ERST_READ_REGISTER_VALUE 0x01
+#define EFI_ACPI_5_1_ERST_WRITE_REGISTER 0x02
+#define EFI_ACPI_5_1_ERST_WRITE_REGISTER_VALUE 0x03
+#define EFI_ACPI_5_1_ERST_NOOP 0x04
+#define EFI_ACPI_5_1_ERST_LOAD_VAR1 0x05
+#define EFI_ACPI_5_1_ERST_LOAD_VAR2 0x06
+#define EFI_ACPI_5_1_ERST_STORE_VAR1 0x07
+#define EFI_ACPI_5_1_ERST_ADD 0x08
+#define EFI_ACPI_5_1_ERST_SUBTRACT 0x09
+#define EFI_ACPI_5_1_ERST_ADD_VALUE 0x0A
+#define EFI_ACPI_5_1_ERST_SUBTRACT_VALUE 0x0B
+#define EFI_ACPI_5_1_ERST_STALL 0x0C
+#define EFI_ACPI_5_1_ERST_STALL_WHILE_TRUE 0x0D
+#define EFI_ACPI_5_1_ERST_SKIP_NEXT_INSTRUCTION_IF_TRUE 0x0E
+#define EFI_ACPI_5_1_ERST_GOTO 0x0F
+#define EFI_ACPI_5_1_ERST_SET_SRC_ADDRESS_BASE 0x10
+#define EFI_ACPI_5_1_ERST_SET_DST_ADDRESS_BASE 0x11
+#define EFI_ACPI_5_1_ERST_MOVE_DATA 0x12
+
+///
+/// ERST Instruction Flags
+///
+#define EFI_ACPI_5_1_ERST_PRESERVE_REGISTER 0x01
+
+///
+/// ERST Serialization Instruction Entry
+///
+typedef struct {
+ UINT8 SerializationAction;
+ UINT8 Instruction;
+ UINT8 Flags;
+ UINT8 Reserved0;
+ EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE RegisterRegion;
+ UINT64 Value;
+ UINT64 Mask;
+} EFI_ACPI_5_1_ERST_SERIALIZATION_INSTRUCTION_ENTRY;
+
+///
+/// EINJ - Error Injection Table
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 InjectionHeaderSize;
+ UINT8 InjectionFlags;
+ UINT8 Reserved0[3];
+ UINT32 InjectionEntryCount;
+} EFI_ACPI_5_1_ERROR_INJECTION_TABLE_HEADER;
+
+///
+/// EINJ Version (as defined in ACPI 5.1 spec.)
+///
+#define EFI_ACPI_5_1_ERROR_INJECTION_TABLE_REVISION 0x01
+
+///
+/// EINJ Error Injection Actions
+///
+#define EFI_ACPI_5_1_EINJ_BEGIN_INJECTION_OPERATION 0x00
+#define EFI_ACPI_5_1_EINJ_GET_TRIGGER_ERROR_ACTION_TABLE 0x01
+#define EFI_ACPI_5_1_EINJ_SET_ERROR_TYPE 0x02
+#define EFI_ACPI_5_1_EINJ_GET_ERROR_TYPE 0x03
+#define EFI_ACPI_5_1_EINJ_END_OPERATION 0x04
+#define EFI_ACPI_5_1_EINJ_EXECUTE_OPERATION 0x05
+#define EFI_ACPI_5_1_EINJ_CHECK_BUSY_STATUS 0x06
+#define EFI_ACPI_5_1_EINJ_GET_COMMAND_STATUS 0x07
+#define EFI_ACPI_5_1_EINJ_TRIGGER_ERROR 0xFF
+
+///
+/// EINJ Action Command Status
+///
+#define EFI_ACPI_5_1_EINJ_STATUS_SUCCESS 0x00
+#define EFI_ACPI_5_1_EINJ_STATUS_UNKNOWN_FAILURE 0x01
+#define EFI_ACPI_5_1_EINJ_STATUS_INVALID_ACCESS 0x02
+
+///
+/// EINJ Error Type Definition
+///
+#define EFI_ACPI_5_1_EINJ_ERROR_PROCESSOR_CORRECTABLE (1 << 0)
+#define EFI_ACPI_5_1_EINJ_ERROR_PROCESSOR_UNCORRECTABLE_NONFATAL (1 << 1)
+#define EFI_ACPI_5_1_EINJ_ERROR_PROCESSOR_UNCORRECTABLE_FATAL (1 << 2)
+#define EFI_ACPI_5_1_EINJ_ERROR_MEMORY_CORRECTABLE (1 << 3)
+#define EFI_ACPI_5_1_EINJ_ERROR_MEMORY_UNCORRECTABLE_NONFATAL (1 << 4)
+#define EFI_ACPI_5_1_EINJ_ERROR_MEMORY_UNCORRECTABLE_FATAL (1 << 5)
+#define EFI_ACPI_5_1_EINJ_ERROR_PCI_EXPRESS_CORRECTABLE (1 << 6)
+#define EFI_ACPI_5_1_EINJ_ERROR_PCI_EXPRESS_UNCORRECTABLE_NONFATAL (1 << 7)
+#define EFI_ACPI_5_1_EINJ_ERROR_PCI_EXPRESS_UNCORRECTABLE_FATAL (1 << 8)
+#define EFI_ACPI_5_1_EINJ_ERROR_PLATFORM_CORRECTABLE (1 << 9)
+#define EFI_ACPI_5_1_EINJ_ERROR_PLATFORM_UNCORRECTABLE_NONFATAL (1 << 10)
+#define EFI_ACPI_5_1_EINJ_ERROR_PLATFORM_UNCORRECTABLE_FATAL (1 << 11)
+
+///
+/// EINJ Injection Instructions
+///
+#define EFI_ACPI_5_1_EINJ_READ_REGISTER 0x00
+#define EFI_ACPI_5_1_EINJ_READ_REGISTER_VALUE 0x01
+#define EFI_ACPI_5_1_EINJ_WRITE_REGISTER 0x02
+#define EFI_ACPI_5_1_EINJ_WRITE_REGISTER_VALUE 0x03
+#define EFI_ACPI_5_1_EINJ_NOOP 0x04
+
+///
+/// EINJ Instruction Flags
+///
+#define EFI_ACPI_5_1_EINJ_PRESERVE_REGISTER 0x01
+
+///
+/// EINJ Injection Instruction Entry
+///
+typedef struct {
+ UINT8 InjectionAction;
+ UINT8 Instruction;
+ UINT8 Flags;
+ UINT8 Reserved0;
+ EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE RegisterRegion;
+ UINT64 Value;
+ UINT64 Mask;
+} EFI_ACPI_5_1_EINJ_INJECTION_INSTRUCTION_ENTRY;
+
+///
+/// EINJ Trigger Action Table
+///
+typedef struct {
+ UINT32 HeaderSize;
+ UINT32 Revision;
+ UINT32 TableSize;
+ UINT32 EntryCount;
+} EFI_ACPI_5_1_EINJ_TRIGGER_ACTION_TABLE;
+
+///
+/// Platform Communications Channel Table (PCCT)
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 Flags;
+ UINT64 Reserved;
+} EFI_ACPI_5_1_PLATFORM_COMMUNICATION_CHANNEL_TABLE_HEADER;
+
+///
+/// PCCT Version (as defined in ACPI 5.1 spec.)
+///
+#define EFI_ACPI_5_1_PLATFORM_COMMUNICATION_CHANNEL_TABLE_REVISION 0x01
+
+///
+/// PCCT Global Flags
+///
+#define EFI_ACPI_5_1_PCCT_FLAGS_SCI_DOORBELL BIT0
+
+//
+// PCCT Subspace type
+//
+#define EFI_ACPI_5_1_PCCT_SUBSPACE_TYPE_GENERIC 0x00
+
+///
+/// PCC Subspace Structure Header
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+} EFI_ACPI_5_1_PCCT_SUBSPACE_HEADER;
+
+///
+/// Generic Communications Subspace Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 Reserved[6];
+ UINT64 BaseAddress;
+ UINT64 AddressLength;
+ EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE DoorbellRegister;
+ UINT64 DoorbellPreserve;
+ UINT64 DoorbellWrite;
+ UINT32 NominalLatency;
+ UINT32 MaximumPeriodicAccessRate;
+ UINT16 MinimumRequestTurnaroundTime;
+} EFI_ACPI_5_1_PCCT_SUBSPACE_GENERIC;
+
+///
+/// Generic Communications Channel Shared Memory Region
+///
+
+typedef struct {
+ UINT8 Command;
+ UINT8 Reserved : 7;
+ UINT8 GenerateSci : 1;
+} EFI_ACPI_5_1_PCCT_GENERIC_SHARED_MEMORY_REGION_COMMAND;
+
+typedef struct {
+ UINT8 CommandComplete : 1;
+ UINT8 SciDoorbell : 1;
+ UINT8 Error : 1;
+ UINT8 PlatformNotification : 1;
+ UINT8 Reserved : 4;
+ UINT8 Reserved1;
+} EFI_ACPI_5_1_PCCT_GENERIC_SHARED_MEMORY_REGION_STATUS;
+
+typedef struct {
+ UINT32 Signature;
+ EFI_ACPI_5_1_PCCT_GENERIC_SHARED_MEMORY_REGION_COMMAND Command;
+ EFI_ACPI_5_1_PCCT_GENERIC_SHARED_MEMORY_REGION_STATUS Status;
+} EFI_ACPI_5_1_PCCT_GENERIC_SHARED_MEMORY_REGION_HEADER;
+
+//
+// Known table signatures
+//
+
+///
+/// "RSD PTR " Root System Description Pointer
+///
+#define EFI_ACPI_5_1_ROOT_SYSTEM_DESCRIPTION_POINTER_SIGNATURE SIGNATURE_64('R', 'S', 'D', ' ', 'P', 'T', 'R', ' ')
+
+///
+/// "APIC" Multiple APIC Description Table
+///
+#define EFI_ACPI_5_1_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('A', 'P', 'I', 'C')
+
+///
+/// "BERT" Boot Error Record Table
+///
+#define EFI_ACPI_5_1_BOOT_ERROR_RECORD_TABLE_SIGNATURE SIGNATURE_32('B', 'E', 'R', 'T')
+
+///
+/// "BGRT" Boot Graphics Resource Table
+///
+#define EFI_ACPI_5_1_BOOT_GRAPHICS_RESOURCE_TABLE_SIGNATURE SIGNATURE_32('B', 'G', 'R', 'T')
+
+///
+/// "CPEP" Corrected Platform Error Polling Table
+///
+#define EFI_ACPI_5_1_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_SIGNATURE SIGNATURE_32('C', 'P', 'E', 'P')
+
+///
+/// "DSDT" Differentiated System Description Table
+///
+#define EFI_ACPI_5_1_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('D', 'S', 'D', 'T')
+
+///
+/// "ECDT" Embedded Controller Boot Resources Table
+///
+#define EFI_ACPI_5_1_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE_SIGNATURE SIGNATURE_32('E', 'C', 'D', 'T')
+
+///
+/// "EINJ" Error Injection Table
+///
+#define EFI_ACPI_5_1_ERROR_INJECTION_TABLE_SIGNATURE SIGNATURE_32('E', 'I', 'N', 'J')
+
+///
+/// "ERST" Error Record Serialization Table
+///
+#define EFI_ACPI_5_1_ERROR_RECORD_SERIALIZATION_TABLE_SIGNATURE SIGNATURE_32('E', 'R', 'S', 'T')
+
+///
+/// "FACP" Fixed ACPI Description Table
+///
+#define EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('F', 'A', 'C', 'P')
+
+///
+/// "FACS" Firmware ACPI Control Structure
+///
+#define EFI_ACPI_5_1_FIRMWARE_ACPI_CONTROL_STRUCTURE_SIGNATURE SIGNATURE_32('F', 'A', 'C', 'S')
+
+///
+/// "FPDT" Firmware Performance Data Table
+///
+#define EFI_ACPI_5_1_FIRMWARE_PERFORMANCE_DATA_TABLE_SIGNATURE SIGNATURE_32('F', 'P', 'D', 'T')
+
+///
+/// "GTDT" Generic Timer Description Table
+///
+#define EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('G', 'T', 'D', 'T')
+
+///
+/// "HEST" Hardware Error Source Table
+///
+#define EFI_ACPI_5_1_HARDWARE_ERROR_SOURCE_TABLE_SIGNATURE SIGNATURE_32('H', 'E', 'S', 'T')
+
+///
+/// "MPST" Memory Power State Table
+///
+#define EFI_ACPI_5_1_MEMORY_POWER_STATE_TABLE_SIGNATURE SIGNATURE_32('M', 'P', 'S', 'T')
+
+///
+/// "MSCT" Maximum System Characteristics Table
+///
+#define EFI_ACPI_5_1_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_SIGNATURE SIGNATURE_32('M', 'S', 'C', 'T')
+
+///
+/// "PMTT" Platform Memory Topology Table
+///
+#define EFI_ACPI_5_1_PLATFORM_MEMORY_TOPOLOGY_TABLE_SIGNATURE SIGNATURE_32('P', 'M', 'T', 'T')
+
+///
+/// "PSDT" Persistent System Description Table
+///
+#define EFI_ACPI_5_1_PERSISTENT_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('P', 'S', 'D', 'T')
+
+///
+/// "RASF" ACPI RAS Feature Table
+///
+#define EFI_ACPI_5_1_ACPI_RAS_FEATURE_TABLE_SIGNATURE SIGNATURE_32('R', 'A', 'S', 'F')
+
+///
+/// "RSDT" Root System Description Table
+///
+#define EFI_ACPI_5_1_ROOT_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('R', 'S', 'D', 'T')
+
+///
+/// "SBST" Smart Battery Specification Table
+///
+#define EFI_ACPI_5_1_SMART_BATTERY_SPECIFICATION_TABLE_SIGNATURE SIGNATURE_32('S', 'B', 'S', 'T')
+
+///
+/// "SLIT" System Locality Information Table
+///
+#define EFI_ACPI_5_1_SYSTEM_LOCALITY_INFORMATION_TABLE_SIGNATURE SIGNATURE_32('S', 'L', 'I', 'T')
+
+///
+/// "SRAT" System Resource Affinity Table
+///
+#define EFI_ACPI_5_1_SYSTEM_RESOURCE_AFFINITY_TABLE_SIGNATURE SIGNATURE_32('S', 'R', 'A', 'T')
+
+///
+/// "SSDT" Secondary System Description Table
+///
+#define EFI_ACPI_5_1_SECONDARY_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('S', 'S', 'D', 'T')
+
+///
+/// "XSDT" Extended System Description Table
+///
+#define EFI_ACPI_5_1_EXTENDED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('X', 'S', 'D', 'T')
+
+///
+/// "BOOT" MS Simple Boot Spec
+///
+#define EFI_ACPI_5_1_SIMPLE_BOOT_FLAG_TABLE_SIGNATURE SIGNATURE_32('B', 'O', 'O', 'T')
+
+///
+/// "CSRT" MS Core System Resource Table
+///
+#define EFI_ACPI_5_1_CORE_SYSTEM_RESOURCE_TABLE_SIGNATURE SIGNATURE_32('C', 'S', 'R', 'T')
+
+///
+/// "DBG2" MS Debug Port 2 Spec
+///
+#define EFI_ACPI_5_1_DEBUG_PORT_2_TABLE_SIGNATURE SIGNATURE_32('D', 'B', 'G', '2')
+
+///
+/// "DBGP" MS Debug Port Spec
+///
+#define EFI_ACPI_5_1_DEBUG_PORT_TABLE_SIGNATURE SIGNATURE_32('D', 'B', 'G', 'P')
+
+///
+/// "DMAR" DMA Remapping Table
+///
+#define EFI_ACPI_5_1_DMA_REMAPPING_TABLE_SIGNATURE SIGNATURE_32('D', 'M', 'A', 'R')
+
+///
+/// "DRTM" Dynamic Root of Trust for Measurement Table
+///
+#define EFI_ACPI_5_1_DYNAMIC_ROOT_OF_TRUST_FOR_MEASUREMENT_TABLE_SIGNATURE SIGNATURE_32('D', 'R', 'T', 'M')
+
+///
+/// "ETDT" Event Timer Description Table
+///
+#define EFI_ACPI_5_1_EVENT_TIMER_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('E', 'T', 'D', 'T')
+
+///
+/// "HPET" IA-PC High Precision Event Timer Table
+///
+#define EFI_ACPI_5_1_HIGH_PRECISION_EVENT_TIMER_TABLE_SIGNATURE SIGNATURE_32('H', 'P', 'E', 'T')
+
+///
+/// "iBFT" iSCSI Boot Firmware Table
+///
+#define EFI_ACPI_5_1_ISCSI_BOOT_FIRMWARE_TABLE_SIGNATURE SIGNATURE_32('i', 'B', 'F', 'T')
+
+///
+/// "IVRS" I/O Virtualization Reporting Structure
+///
+#define EFI_ACPI_5_1_IO_VIRTUALIZATION_REPORTING_STRUCTURE_SIGNATURE SIGNATURE_32('I', 'V', 'R', 'S')
+
+///
+/// "LPIT" Low Power Idle Table
+///
+#define EFI_ACPI_5_1_IO_LOW_POWER_IDLE_TABLE_STRUCTURE_SIGNATURE SIGNATURE_32('L', 'P', 'I', 'T')
+
+///
+/// "MCFG" PCI Express Memory Mapped Configuration Space Base Address Description Table
+///
+#define EFI_ACPI_5_1_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('M', 'C', 'F', 'G')
+
+///
+/// "MCHI" Management Controller Host Interface Table
+///
+#define EFI_ACPI_5_1_MANAGEMENT_CONTROLLER_HOST_INTERFACE_TABLE_SIGNATURE SIGNATURE_32('M', 'C', 'H', 'I')
+
+///
+/// "MSDM" MS Data Management Table
+///
+#define EFI_ACPI_5_1_DATA_MANAGEMENT_TABLE_SIGNATURE SIGNATURE_32('M', 'S', 'D', 'M')
+
+///
+/// "PCCT" Platform Communications Channel Table
+///
+#define EFI_ACPI_5_1_PLATFORM_COMMUNICATIONS_CHANNEL_TABLE_SIGNATURE SIGNATURE_32('P', 'C', 'C', 'T')
+
+///
+/// "SLIC" MS Software Licensing Table Specification
+///
+#define EFI_ACPI_5_1_SOFTWARE_LICENSING_TABLE_SIGNATURE SIGNATURE_32('S', 'L', 'I', 'C')
+
+///
+/// "SPCR" Serial Port Console Redirection Table
+///
+#define EFI_ACPI_5_1_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE SIGNATURE_32('S', 'P', 'C', 'R')
+
+///
+/// "SPMI" Server Platform Management Interface Table
+///
+#define EFI_ACPI_5_1_SERVER_PLATFORM_MANAGEMENT_INTERFACE_TABLE_SIGNATURE SIGNATURE_32('S', 'P', 'M', 'I')
+
+///
+/// "TCPA" Trusted Computing Platform Alliance Capabilities Table
+///
+#define EFI_ACPI_5_1_TRUSTED_COMPUTING_PLATFORM_ALLIANCE_CAPABILITIES_TABLE_SIGNATURE SIGNATURE_32('T', 'C', 'P', 'A')
+
+///
+/// "TPM2" Trusted Computing Platform 1 Table
+///
+#define EFI_ACPI_5_1_TRUSTED_COMPUTING_PLATFORM_2_TABLE_SIGNATURE SIGNATURE_32('T', 'P', 'M', '2')
+
+///
+/// "UEFI" UEFI ACPI Data Table
+///
+#define EFI_ACPI_5_1_UEFI_ACPI_DATA_TABLE_SIGNATURE SIGNATURE_32('U', 'E', 'F', 'I')
+
+///
+/// "WAET" Windows ACPI Emulated Devices Table
+///
+#define EFI_ACPI_5_1_WINDOWS_ACPI_EMULATED_DEVICES_TABLE_SIGNATURE SIGNATURE_32('W', 'A', 'E', 'T')
+
+///
+/// "WDAT" Watchdog Action Table
+///
+#define EFI_ACPI_5_1_WATCHDOG_ACTION_TABLE_SIGNATURE SIGNATURE_32('W', 'D', 'A', 'T')
+
+///
+/// "WDRT" Watchdog Resource Table
+///
+#define EFI_ACPI_5_1_WATCHDOG_RESOURCE_TABLE_SIGNATURE SIGNATURE_32('W', 'D', 'R', 'T')
+
+///
+/// "WPBT" MS Platform Binary Table
+///
+#define EFI_ACPI_5_1_PLATFORM_BINARY_TABLE_SIGNATURE SIGNATURE_32('W', 'P', 'B', 'T')
+
+#pragma pack()
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/Acpi60.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/Acpi60.h
new file mode 100644
index 0000000000..c3a5a2223a
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/Acpi60.h
@@ -0,0 +1,2398 @@
+/** @file
+ ACPI 6.0 definitions from the ACPI Specification Revision 6.0 Errata A January, 2016.
+
+ Copyright (c) 2015 - 2022, Intel Corporation. All rights reserved.
+ (C) Copyright 2015-2016 Hewlett Packard Enterprise Development LP
+ Copyright (c) 2020, ARM Ltd. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _ACPI_6_0_H_
+#define _ACPI_6_0_H_
+
+#include
+
+//
+// Ensure proper structure formats
+//
+#pragma pack(1)
+
+///
+/// ACPI 6.0 Generic Address Space definition
+///
+typedef struct {
+ UINT8 AddressSpaceId;
+ UINT8 RegisterBitWidth;
+ UINT8 RegisterBitOffset;
+ UINT8 AccessSize;
+ UINT64 Address;
+} EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE;
+
+//
+// Generic Address Space Address IDs
+//
+#define EFI_ACPI_6_0_SYSTEM_MEMORY 0
+#define EFI_ACPI_6_0_SYSTEM_IO 1
+#define EFI_ACPI_6_0_PCI_CONFIGURATION_SPACE 2
+#define EFI_ACPI_6_0_EMBEDDED_CONTROLLER 3
+#define EFI_ACPI_6_0_SMBUS 4
+#define EFI_ACPI_6_0_PLATFORM_COMMUNICATION_CHANNEL 0x0A
+#define EFI_ACPI_6_0_FUNCTIONAL_FIXED_HARDWARE 0x7F
+
+//
+// Generic Address Space Access Sizes
+//
+#define EFI_ACPI_6_0_UNDEFINED 0
+#define EFI_ACPI_6_0_BYTE 1
+#define EFI_ACPI_6_0_WORD 2
+#define EFI_ACPI_6_0_DWORD 3
+#define EFI_ACPI_6_0_QWORD 4
+
+//
+// ACPI 6.0 table structures
+//
+
+///
+/// Root System Description Pointer Structure
+///
+typedef struct {
+ UINT64 Signature;
+ UINT8 Checksum;
+ UINT8 OemId[6];
+ UINT8 Revision;
+ UINT32 RsdtAddress;
+ UINT32 Length;
+ UINT64 XsdtAddress;
+ UINT8 ExtendedChecksum;
+ UINT8 Reserved[3];
+} EFI_ACPI_6_0_ROOT_SYSTEM_DESCRIPTION_POINTER;
+
+///
+/// RSD_PTR Revision (as defined in ACPI 6.0 spec.)
+///
+#define EFI_ACPI_6_0_ROOT_SYSTEM_DESCRIPTION_POINTER_REVISION 0x02 ///< ACPISpec (Revision 6.0) says current value is 2
+
+///
+/// Common table header, this prefaces all ACPI tables, including FACS, but
+/// excluding the RSD PTR structure
+///
+typedef struct {
+ UINT32 Signature;
+ UINT32 Length;
+} EFI_ACPI_6_0_COMMON_HEADER;
+
+//
+// Root System Description Table
+// No definition needed as it is a common description table header, the same with
+// EFI_ACPI_DESCRIPTION_HEADER, followed by a variable number of UINT32 table pointers.
+//
+
+///
+/// RSDT Revision (as defined in ACPI 6.0 spec.)
+///
+#define EFI_ACPI_6_0_ROOT_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01
+
+//
+// Extended System Description Table
+// No definition needed as it is a common description table header, the same with
+// EFI_ACPI_DESCRIPTION_HEADER, followed by a variable number of UINT64 table pointers.
+//
+
+///
+/// XSDT Revision (as defined in ACPI 6.0 spec.)
+///
+#define EFI_ACPI_6_0_EXTENDED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01
+
+///
+/// Fixed ACPI Description Table Structure (FADT)
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 FirmwareCtrl;
+ UINT32 Dsdt;
+ UINT8 Reserved0;
+ UINT8 PreferredPmProfile;
+ UINT16 SciInt;
+ UINT32 SmiCmd;
+ UINT8 AcpiEnable;
+ UINT8 AcpiDisable;
+ UINT8 S4BiosReq;
+ UINT8 PstateCnt;
+ UINT32 Pm1aEvtBlk;
+ UINT32 Pm1bEvtBlk;
+ UINT32 Pm1aCntBlk;
+ UINT32 Pm1bCntBlk;
+ UINT32 Pm2CntBlk;
+ UINT32 PmTmrBlk;
+ UINT32 Gpe0Blk;
+ UINT32 Gpe1Blk;
+ UINT8 Pm1EvtLen;
+ UINT8 Pm1CntLen;
+ UINT8 Pm2CntLen;
+ UINT8 PmTmrLen;
+ UINT8 Gpe0BlkLen;
+ UINT8 Gpe1BlkLen;
+ UINT8 Gpe1Base;
+ UINT8 CstCnt;
+ UINT16 PLvl2Lat;
+ UINT16 PLvl3Lat;
+ UINT16 FlushSize;
+ UINT16 FlushStride;
+ UINT8 DutyOffset;
+ UINT8 DutyWidth;
+ UINT8 DayAlrm;
+ UINT8 MonAlrm;
+ UINT8 Century;
+ UINT16 IaPcBootArch;
+ UINT8 Reserved1;
+ UINT32 Flags;
+ EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE ResetReg;
+ UINT8 ResetValue;
+ UINT16 ArmBootArch;
+ UINT8 MinorVersion;
+ UINT64 XFirmwareCtrl;
+ UINT64 XDsdt;
+ EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE XPm1aEvtBlk;
+ EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE XPm1bEvtBlk;
+ EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE XPm1aCntBlk;
+ EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE XPm1bCntBlk;
+ EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE XPm2CntBlk;
+ EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE XPmTmrBlk;
+ EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE XGpe0Blk;
+ EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE XGpe1Blk;
+ EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE SleepControlReg;
+ EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE SleepStatusReg;
+ UINT64 HypervisorVendorIdentity;
+} EFI_ACPI_6_0_FIXED_ACPI_DESCRIPTION_TABLE;
+
+///
+/// FADT Version (as defined in ACPI 6.0 spec.)
+///
+#define EFI_ACPI_6_0_FIXED_ACPI_DESCRIPTION_TABLE_REVISION 0x06
+#define EFI_ACPI_6_0_FIXED_ACPI_DESCRIPTION_TABLE_MINOR_REVISION 0x00
+
+//
+// Fixed ACPI Description Table Preferred Power Management Profile
+//
+#define EFI_ACPI_6_0_PM_PROFILE_UNSPECIFIED 0
+#define EFI_ACPI_6_0_PM_PROFILE_DESKTOP 1
+#define EFI_ACPI_6_0_PM_PROFILE_MOBILE 2
+#define EFI_ACPI_6_0_PM_PROFILE_WORKSTATION 3
+#define EFI_ACPI_6_0_PM_PROFILE_ENTERPRISE_SERVER 4
+#define EFI_ACPI_6_0_PM_PROFILE_SOHO_SERVER 5
+#define EFI_ACPI_6_0_PM_PROFILE_APPLIANCE_PC 6
+#define EFI_ACPI_6_0_PM_PROFILE_PERFORMANCE_SERVER 7
+#define EFI_ACPI_6_0_PM_PROFILE_TABLET 8
+
+//
+// Fixed ACPI Description Table Boot Architecture Flags
+// All other bits are reserved and must be set to 0.
+//
+#define EFI_ACPI_6_0_LEGACY_DEVICES BIT0
+#define EFI_ACPI_6_0_8042 BIT1
+#define EFI_ACPI_6_0_VGA_NOT_PRESENT BIT2
+#define EFI_ACPI_6_0_MSI_NOT_SUPPORTED BIT3
+#define EFI_ACPI_6_0_PCIE_ASPM_CONTROLS BIT4
+#define EFI_ACPI_6_0_CMOS_RTC_NOT_PRESENT BIT5
+
+//
+// Fixed ACPI Description Table Arm Boot Architecture Flags
+// All other bits are reserved and must be set to 0.
+//
+#define EFI_ACPI_6_0_ARM_PSCI_COMPLIANT BIT0
+#define EFI_ACPI_6_0_ARM_PSCI_USE_HVC BIT1
+
+//
+// Fixed ACPI Description Table Fixed Feature Flags
+// All other bits are reserved and must be set to 0.
+//
+#define EFI_ACPI_6_0_WBINVD BIT0
+#define EFI_ACPI_6_0_WBINVD_FLUSH BIT1
+#define EFI_ACPI_6_0_PROC_C1 BIT2
+#define EFI_ACPI_6_0_P_LVL2_UP BIT3
+#define EFI_ACPI_6_0_PWR_BUTTON BIT4
+#define EFI_ACPI_6_0_SLP_BUTTON BIT5
+#define EFI_ACPI_6_0_FIX_RTC BIT6
+#define EFI_ACPI_6_0_RTC_S4 BIT7
+#define EFI_ACPI_6_0_TMR_VAL_EXT BIT8
+#define EFI_ACPI_6_0_DCK_CAP BIT9
+#define EFI_ACPI_6_0_RESET_REG_SUP BIT10
+#define EFI_ACPI_6_0_SEALED_CASE BIT11
+#define EFI_ACPI_6_0_HEADLESS BIT12
+#define EFI_ACPI_6_0_CPU_SW_SLP BIT13
+#define EFI_ACPI_6_0_PCI_EXP_WAK BIT14
+#define EFI_ACPI_6_0_USE_PLATFORM_CLOCK BIT15
+#define EFI_ACPI_6_0_S4_RTC_STS_VALID BIT16
+#define EFI_ACPI_6_0_REMOTE_POWER_ON_CAPABLE BIT17
+#define EFI_ACPI_6_0_FORCE_APIC_CLUSTER_MODEL BIT18
+#define EFI_ACPI_6_0_FORCE_APIC_PHYSICAL_DESTINATION_MODE BIT19
+#define EFI_ACPI_6_0_HW_REDUCED_ACPI BIT20
+#define EFI_ACPI_6_0_LOW_POWER_S0_IDLE_CAPABLE BIT21
+
+///
+/// Firmware ACPI Control Structure
+///
+typedef struct {
+ UINT32 Signature;
+ UINT32 Length;
+ UINT32 HardwareSignature;
+ UINT32 FirmwareWakingVector;
+ UINT32 GlobalLock;
+ UINT32 Flags;
+ UINT64 XFirmwareWakingVector;
+ UINT8 Version;
+ UINT8 Reserved0[3];
+ UINT32 OspmFlags;
+ UINT8 Reserved1[24];
+} EFI_ACPI_6_0_FIRMWARE_ACPI_CONTROL_STRUCTURE;
+
+///
+/// FACS Version (as defined in ACPI 6.0 spec.)
+///
+#define EFI_ACPI_6_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_VERSION 0x02
+
+///
+/// Firmware Control Structure Feature Flags
+/// All other bits are reserved and must be set to 0.
+///
+#define EFI_ACPI_6_0_S4BIOS_F BIT0
+#define EFI_ACPI_6_0_64BIT_WAKE_SUPPORTED_F BIT1
+
+///
+/// OSPM Enabled Firmware Control Structure Flags
+/// All other bits are reserved and must be set to 0.
+///
+#define EFI_ACPI_6_0_OSPM_64BIT_WAKE_F BIT0
+
+//
+// Differentiated System Description Table,
+// Secondary System Description Table
+// and Persistent System Description Table,
+// no definition needed as they are common description table header, the same with
+// EFI_ACPI_DESCRIPTION_HEADER, followed by a definition block.
+//
+#define EFI_ACPI_6_0_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x02
+#define EFI_ACPI_6_0_SECONDARY_SYSTEM_DESCRIPTION_TABLE_REVISION 0x02
+
+///
+/// Multiple APIC Description Table header definition. The rest of the table
+/// must be defined in a platform specific manner.
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 LocalApicAddress;
+ UINT32 Flags;
+} EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER;
+
+///
+/// MADT Revision (as defined in ACPI 6.0 Errata A spec.)
+///
+#define EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION 0x04
+
+///
+/// Multiple APIC Flags
+/// All other bits are reserved and must be set to 0.
+///
+#define EFI_ACPI_6_0_PCAT_COMPAT BIT0
+
+//
+// Multiple APIC Description Table APIC structure types
+// All other values between 0x0D and 0x7F are reserved and
+// will be ignored by OSPM. 0x80 ~ 0xFF are reserved for OEM.
+//
+#define EFI_ACPI_6_0_PROCESSOR_LOCAL_APIC 0x00
+#define EFI_ACPI_6_0_IO_APIC 0x01
+#define EFI_ACPI_6_0_INTERRUPT_SOURCE_OVERRIDE 0x02
+#define EFI_ACPI_6_0_NON_MASKABLE_INTERRUPT_SOURCE 0x03
+#define EFI_ACPI_6_0_LOCAL_APIC_NMI 0x04
+#define EFI_ACPI_6_0_LOCAL_APIC_ADDRESS_OVERRIDE 0x05
+#define EFI_ACPI_6_0_IO_SAPIC 0x06
+#define EFI_ACPI_6_0_LOCAL_SAPIC 0x07
+#define EFI_ACPI_6_0_PLATFORM_INTERRUPT_SOURCES 0x08
+#define EFI_ACPI_6_0_PROCESSOR_LOCAL_X2APIC 0x09
+#define EFI_ACPI_6_0_LOCAL_X2APIC_NMI 0x0A
+#define EFI_ACPI_6_0_GIC 0x0B
+#define EFI_ACPI_6_0_GICD 0x0C
+#define EFI_ACPI_6_0_GIC_MSI_FRAME 0x0D
+#define EFI_ACPI_6_0_GICR 0x0E
+#define EFI_ACPI_6_0_GIC_ITS 0x0F
+
+//
+// APIC Structure Definitions
+//
+
+///
+/// Processor Local APIC Structure Definition
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 AcpiProcessorUid;
+ UINT8 ApicId;
+ UINT32 Flags;
+} EFI_ACPI_6_0_PROCESSOR_LOCAL_APIC_STRUCTURE;
+
+///
+/// Local APIC Flags. All other bits are reserved and must be 0.
+///
+#define EFI_ACPI_6_0_LOCAL_APIC_ENABLED BIT0
+
+///
+/// IO APIC Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 IoApicId;
+ UINT8 Reserved;
+ UINT32 IoApicAddress;
+ UINT32 GlobalSystemInterruptBase;
+} EFI_ACPI_6_0_IO_APIC_STRUCTURE;
+
+///
+/// Interrupt Source Override Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 Bus;
+ UINT8 Source;
+ UINT32 GlobalSystemInterrupt;
+ UINT16 Flags;
+} EFI_ACPI_6_0_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE;
+
+///
+/// Platform Interrupt Sources Structure Definition
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Flags;
+ UINT8 InterruptType;
+ UINT8 ProcessorId;
+ UINT8 ProcessorEid;
+ UINT8 IoSapicVector;
+ UINT32 GlobalSystemInterrupt;
+ UINT32 PlatformInterruptSourceFlags;
+ UINT8 CpeiProcessorOverride;
+ UINT8 Reserved[31];
+} EFI_ACPI_6_0_PLATFORM_INTERRUPT_APIC_STRUCTURE;
+
+//
+// MPS INTI flags.
+// All other bits are reserved and must be set to 0.
+//
+#define EFI_ACPI_6_0_POLARITY (3 << 0)
+#define EFI_ACPI_6_0_TRIGGER_MODE (3 << 2)
+
+///
+/// Non-Maskable Interrupt Source Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Flags;
+ UINT32 GlobalSystemInterrupt;
+} EFI_ACPI_6_0_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE;
+
+///
+/// Local APIC NMI Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 AcpiProcessorUid;
+ UINT16 Flags;
+ UINT8 LocalApicLint;
+} EFI_ACPI_6_0_LOCAL_APIC_NMI_STRUCTURE;
+
+///
+/// Local APIC Address Override Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Reserved;
+ UINT64 LocalApicAddress;
+} EFI_ACPI_6_0_LOCAL_APIC_ADDRESS_OVERRIDE_STRUCTURE;
+
+///
+/// IO SAPIC Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 IoApicId;
+ UINT8 Reserved;
+ UINT32 GlobalSystemInterruptBase;
+ UINT64 IoSapicAddress;
+} EFI_ACPI_6_0_IO_SAPIC_STRUCTURE;
+
+///
+/// Local SAPIC Structure
+/// This struct followed by a null-terminated ASCII string - ACPI Processor UID String
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 AcpiProcessorId;
+ UINT8 LocalSapicId;
+ UINT8 LocalSapicEid;
+ UINT8 Reserved[3];
+ UINT32 Flags;
+ UINT32 ACPIProcessorUIDValue;
+} EFI_ACPI_6_0_PROCESSOR_LOCAL_SAPIC_STRUCTURE;
+
+///
+/// Platform Interrupt Sources Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Flags;
+ UINT8 InterruptType;
+ UINT8 ProcessorId;
+ UINT8 ProcessorEid;
+ UINT8 IoSapicVector;
+ UINT32 GlobalSystemInterrupt;
+ UINT32 PlatformInterruptSourceFlags;
+} EFI_ACPI_6_0_PLATFORM_INTERRUPT_SOURCES_STRUCTURE;
+
+///
+/// Platform Interrupt Source Flags.
+/// All other bits are reserved and must be set to 0.
+///
+#define EFI_ACPI_6_0_CPEI_PROCESSOR_OVERRIDE BIT0
+
+///
+/// Processor Local x2APIC Structure Definition
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 Reserved[2];
+ UINT32 X2ApicId;
+ UINT32 Flags;
+ UINT32 AcpiProcessorUid;
+} EFI_ACPI_6_0_PROCESSOR_LOCAL_X2APIC_STRUCTURE;
+
+///
+/// Local x2APIC NMI Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Flags;
+ UINT32 AcpiProcessorUid;
+ UINT8 LocalX2ApicLint;
+ UINT8 Reserved[3];
+} EFI_ACPI_6_0_LOCAL_X2APIC_NMI_STRUCTURE;
+
+///
+/// GIC Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Reserved;
+ UINT32 CPUInterfaceNumber;
+ UINT32 AcpiProcessorUid;
+ UINT32 Flags;
+ UINT32 ParkingProtocolVersion;
+ UINT32 PerformanceInterruptGsiv;
+ UINT64 ParkedAddress;
+ UINT64 PhysicalBaseAddress;
+ UINT64 GICV;
+ UINT64 GICH;
+ UINT32 VGICMaintenanceInterrupt;
+ UINT64 GICRBaseAddress;
+ UINT64 MPIDR;
+ UINT8 ProcessorPowerEfficiencyClass;
+ UINT8 Reserved2[3];
+} EFI_ACPI_6_0_GIC_STRUCTURE;
+
+///
+/// GIC Flags. All other bits are reserved and must be 0.
+///
+#define EFI_ACPI_6_0_GIC_ENABLED BIT0
+#define EFI_ACPI_6_0_PERFORMANCE_INTERRUPT_MODEL BIT1
+#define EFI_ACPI_6_0_VGIC_MAINTENANCE_INTERRUPT_MODE_FLAGS BIT2
+
+///
+/// GIC Distributor Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Reserved1;
+ UINT32 GicId;
+ UINT64 PhysicalBaseAddress;
+ UINT32 SystemVectorBase;
+ UINT8 GicVersion;
+ UINT8 Reserved2[3];
+} EFI_ACPI_6_0_GIC_DISTRIBUTOR_STRUCTURE;
+
+///
+/// GIC Version
+///
+#define EFI_ACPI_6_0_GIC_V1 0x01
+#define EFI_ACPI_6_0_GIC_V2 0x02
+#define EFI_ACPI_6_0_GIC_V3 0x03
+#define EFI_ACPI_6_0_GIC_V4 0x04
+
+///
+/// GIC MSI Frame Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Reserved1;
+ UINT32 GicMsiFrameId;
+ UINT64 PhysicalBaseAddress;
+ UINT32 Flags;
+ UINT16 SPICount;
+ UINT16 SPIBase;
+} EFI_ACPI_6_0_GIC_MSI_FRAME_STRUCTURE;
+
+///
+/// GIC MSI Frame Flags. All other bits are reserved and must be 0.
+///
+#define EFI_ACPI_6_0_SPI_COUNT_BASE_SELECT BIT0
+
+///
+/// GICR Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Reserved;
+ UINT64 DiscoveryRangeBaseAddress;
+ UINT32 DiscoveryRangeLength;
+} EFI_ACPI_6_0_GICR_STRUCTURE;
+
+///
+/// GIC Interrupt Translation Service Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Reserved;
+ UINT32 GicItsId;
+ UINT64 PhysicalBaseAddress;
+ UINT32 Reserved2;
+} EFI_ACPI_6_0_GIC_ITS_STRUCTURE;
+
+///
+/// Smart Battery Description Table (SBST)
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 WarningEnergyLevel;
+ UINT32 LowEnergyLevel;
+ UINT32 CriticalEnergyLevel;
+} EFI_ACPI_6_0_SMART_BATTERY_DESCRIPTION_TABLE;
+
+///
+/// SBST Version (as defined in ACPI 6.0 spec.)
+///
+#define EFI_ACPI_6_0_SMART_BATTERY_DESCRIPTION_TABLE_REVISION 0x01
+
+///
+/// Embedded Controller Boot Resources Table (ECDT)
+/// The table is followed by a null terminated ASCII string that contains
+/// a fully qualified reference to the name space object.
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE EcControl;
+ EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE EcData;
+ UINT32 Uid;
+ UINT8 GpeBit;
+} EFI_ACPI_6_0_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE;
+
+///
+/// ECDT Version (as defined in ACPI 6.0 spec.)
+///
+#define EFI_ACPI_6_0_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE_REVISION 0x01
+
+///
+/// System Resource Affinity Table (SRAT). The rest of the table
+/// must be defined in a platform specific manner.
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 Reserved1; ///< Must be set to 1
+ UINT64 Reserved2;
+} EFI_ACPI_6_0_SYSTEM_RESOURCE_AFFINITY_TABLE_HEADER;
+
+///
+/// SRAT Version (as defined in ACPI 6.0 spec.)
+///
+#define EFI_ACPI_6_0_SYSTEM_RESOURCE_AFFINITY_TABLE_REVISION 0x03
+
+//
+// SRAT structure types.
+// All other values between 0x04 an 0xFF are reserved and
+// will be ignored by OSPM.
+//
+#define EFI_ACPI_6_0_PROCESSOR_LOCAL_APIC_SAPIC_AFFINITY 0x00
+#define EFI_ACPI_6_0_MEMORY_AFFINITY 0x01
+#define EFI_ACPI_6_0_PROCESSOR_LOCAL_X2APIC_AFFINITY 0x02
+#define EFI_ACPI_6_0_GICC_AFFINITY 0x03
+
+///
+/// Processor Local APIC/SAPIC Affinity Structure Definition
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 ProximityDomain7To0;
+ UINT8 ApicId;
+ UINT32 Flags;
+ UINT8 LocalSapicEid;
+ UINT8 ProximityDomain31To8[3];
+ UINT32 ClockDomain;
+} EFI_ACPI_6_0_PROCESSOR_LOCAL_APIC_SAPIC_AFFINITY_STRUCTURE;
+
+///
+/// Local APIC/SAPIC Flags. All other bits are reserved and must be 0.
+///
+#define EFI_ACPI_6_0_PROCESSOR_LOCAL_APIC_SAPIC_ENABLED (1 << 0)
+
+///
+/// Memory Affinity Structure Definition
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT32 ProximityDomain;
+ UINT16 Reserved1;
+ UINT32 AddressBaseLow;
+ UINT32 AddressBaseHigh;
+ UINT32 LengthLow;
+ UINT32 LengthHigh;
+ UINT32 Reserved2;
+ UINT32 Flags;
+ UINT64 Reserved3;
+} EFI_ACPI_6_0_MEMORY_AFFINITY_STRUCTURE;
+
+//
+// Memory Flags. All other bits are reserved and must be 0.
+//
+#define EFI_ACPI_6_0_MEMORY_ENABLED (1 << 0)
+#define EFI_ACPI_6_0_MEMORY_HOT_PLUGGABLE (1 << 1)
+#define EFI_ACPI_6_0_MEMORY_NONVOLATILE (1 << 2)
+
+///
+/// Processor Local x2APIC Affinity Structure Definition
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 Reserved1[2];
+ UINT32 ProximityDomain;
+ UINT32 X2ApicId;
+ UINT32 Flags;
+ UINT32 ClockDomain;
+ UINT8 Reserved2[4];
+} EFI_ACPI_6_0_PROCESSOR_LOCAL_X2APIC_AFFINITY_STRUCTURE;
+
+///
+/// GICC Affinity Structure Definition
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT32 ProximityDomain;
+ UINT32 AcpiProcessorUid;
+ UINT32 Flags;
+ UINT32 ClockDomain;
+} EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE;
+
+///
+/// GICC Flags. All other bits are reserved and must be 0.
+///
+#define EFI_ACPI_6_0_GICC_ENABLED (1 << 0)
+
+///
+/// System Locality Distance Information Table (SLIT).
+/// The rest of the table is a matrix.
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT64 NumberOfSystemLocalities;
+} EFI_ACPI_6_0_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_HEADER;
+
+///
+/// SLIT Version (as defined in ACPI 6.0 spec.)
+///
+#define EFI_ACPI_6_0_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_REVISION 0x01
+
+///
+/// Corrected Platform Error Polling Table (CPEP)
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT8 Reserved[8];
+} EFI_ACPI_6_0_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_HEADER;
+
+///
+/// CPEP Version (as defined in ACPI 6.0 spec.)
+///
+#define EFI_ACPI_6_0_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_REVISION 0x01
+
+//
+// CPEP processor structure types.
+//
+#define EFI_ACPI_6_0_CPEP_PROCESSOR_APIC_SAPIC 0x00
+
+///
+/// Corrected Platform Error Polling Processor Structure Definition
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 ProcessorId;
+ UINT8 ProcessorEid;
+ UINT32 PollingInterval;
+} EFI_ACPI_6_0_CPEP_PROCESSOR_APIC_SAPIC_STRUCTURE;
+
+///
+/// Maximum System Characteristics Table (MSCT)
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 OffsetProxDomInfo;
+ UINT32 MaximumNumberOfProximityDomains;
+ UINT32 MaximumNumberOfClockDomains;
+ UINT64 MaximumPhysicalAddress;
+} EFI_ACPI_6_0_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_HEADER;
+
+///
+/// MSCT Version (as defined in ACPI 6.0 spec.)
+///
+#define EFI_ACPI_6_0_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_REVISION 0x01
+
+///
+/// Maximum Proximity Domain Information Structure Definition
+///
+typedef struct {
+ UINT8 Revision;
+ UINT8 Length;
+ UINT32 ProximityDomainRangeLow;
+ UINT32 ProximityDomainRangeHigh;
+ UINT32 MaximumProcessorCapacity;
+ UINT64 MaximumMemoryCapacity;
+} EFI_ACPI_6_0_MAXIMUM_PROXIMITY_DOMAIN_INFORMATION_STRUCTURE;
+
+///
+/// ACPI RAS Feature Table definition.
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT8 PlatformCommunicationChannelIdentifier[12];
+} EFI_ACPI_6_0_RAS_FEATURE_TABLE;
+
+///
+/// RASF Version (as defined in ACPI 6.0 spec.)
+///
+#define EFI_ACPI_6_0_RAS_FEATURE_TABLE_REVISION 0x01
+
+///
+/// ACPI RASF Platform Communication Channel Shared Memory Region definition.
+///
+typedef struct {
+ UINT32 Signature;
+ UINT16 Command;
+ UINT16 Status;
+ UINT16 Version;
+ UINT8 RASCapabilities[16];
+ UINT8 SetRASCapabilities[16];
+ UINT16 NumberOfRASFParameterBlocks;
+ UINT32 SetRASCapabilitiesStatus;
+} EFI_ACPI_6_0_RASF_PLATFORM_COMMUNICATION_CHANNEL_SHARED_MEMORY_REGION;
+
+///
+/// ACPI RASF PCC command code
+///
+#define EFI_ACPI_6_0_RASF_PCC_COMMAND_CODE_EXECUTE_RASF_COMMAND 0x01
+
+///
+/// ACPI RASF Platform RAS Capabilities
+///
+#define EFI_ACPI_6_0_RASF_PLATFORM_RAS_CAPABILITY_HARDWARE_BASED_PATROL_SCRUB_SUPPOTED 0x01
+#define EFI_ACPI_6_0_RASF_PLATFORM_RAS_CAPABILITY_HARDWARE_BASED_PATROL_SCRUB_SUPPOTED_AND_EXPOSED_TO_SOFTWARE 0x02
+
+///
+/// ACPI RASF Parameter Block structure for PATROL_SCRUB
+///
+typedef struct {
+ UINT16 Type;
+ UINT16 Version;
+ UINT16 Length;
+ UINT16 PatrolScrubCommand;
+ UINT64 RequestedAddressRange[2];
+ UINT64 ActualAddressRange[2];
+ UINT16 Flags;
+ UINT8 RequestedSpeed;
+} EFI_ACPI_6_0_RASF_PATROL_SCRUB_PLATFORM_BLOCK_STRUCTURE;
+
+///
+/// ACPI RASF Patrol Scrub command
+///
+#define EFI_ACPI_6_0_RASF_PATROL_SCRUB_COMMAND_GET_PATROL_PARAMETERS 0x01
+#define EFI_ACPI_6_0_RASF_PATROL_SCRUB_COMMAND_START_PATROL_SCRUBBER 0x02
+#define EFI_ACPI_6_0_RASF_PATROL_SCRUB_COMMAND_STOP_PATROL_SCRUBBER 0x03
+
+///
+/// Memory Power State Table definition.
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT8 PlatformCommunicationChannelIdentifier;
+ UINT8 Reserved[3];
+ // Memory Power Node Structure
+ // Memory Power State Characteristics
+} EFI_ACPI_6_0_MEMORY_POWER_STATUS_TABLE;
+
+///
+/// MPST Version (as defined in ACPI 6.0 spec.)
+///
+#define EFI_ACPI_6_0_MEMORY_POWER_STATE_TABLE_REVISION 0x01
+
+///
+/// MPST Platform Communication Channel Shared Memory Region definition.
+///
+typedef struct {
+ UINT32 Signature;
+ UINT16 Command;
+ UINT16 Status;
+ UINT32 MemoryPowerCommandRegister;
+ UINT32 MemoryPowerStatusRegister;
+ UINT32 PowerStateId;
+ UINT32 MemoryPowerNodeId;
+ UINT64 MemoryEnergyConsumed;
+ UINT64 ExpectedAveragePowerComsuned;
+} EFI_ACPI_6_0_MPST_PLATFORM_COMMUNICATION_CHANNEL_SHARED_MEMORY_REGION;
+
+///
+/// ACPI MPST PCC command code
+///
+#define EFI_ACPI_6_0_MPST_PCC_COMMAND_CODE_EXECUTE_MPST_COMMAND 0x03
+
+///
+/// ACPI MPST Memory Power command
+///
+#define EFI_ACPI_6_0_MPST_MEMORY_POWER_COMMAND_GET_MEMORY_POWER_STATE 0x01
+#define EFI_ACPI_6_0_MPST_MEMORY_POWER_COMMAND_SET_MEMORY_POWER_STATE 0x02
+#define EFI_ACPI_6_0_MPST_MEMORY_POWER_COMMAND_GET_AVERAGE_POWER_CONSUMED 0x03
+#define EFI_ACPI_6_0_MPST_MEMORY_POWER_COMMAND_GET_MEMORY_ENERGY_CONSUMED 0x04
+
+///
+/// MPST Memory Power Node Table
+///
+typedef struct {
+ UINT8 PowerStateValue;
+ UINT8 PowerStateInformationIndex;
+} EFI_ACPI_6_0_MPST_MEMORY_POWER_STATE;
+
+typedef struct {
+ UINT8 Flag;
+ UINT8 Reserved;
+ UINT16 MemoryPowerNodeId;
+ UINT32 Length;
+ UINT64 AddressBase;
+ UINT64 AddressLength;
+ UINT32 NumberOfPowerStates;
+ UINT32 NumberOfPhysicalComponents;
+ // EFI_ACPI_6_0_MPST_MEMORY_POWER_STATE MemoryPowerState[NumberOfPowerStates];
+ // UINT16 PhysicalComponentIdentifier[NumberOfPhysicalComponents];
+} EFI_ACPI_6_0_MPST_MEMORY_POWER_STRUCTURE;
+
+#define EFI_ACPI_6_0_MPST_MEMORY_POWER_STRUCTURE_FLAG_ENABLE 0x01
+#define EFI_ACPI_6_0_MPST_MEMORY_POWER_STRUCTURE_FLAG_POWER_MANAGED 0x02
+#define EFI_ACPI_6_0_MPST_MEMORY_POWER_STRUCTURE_FLAG_HOT_PLUGGABLE 0x04
+
+typedef struct {
+ UINT16 MemoryPowerNodeCount;
+ UINT8 Reserved[2];
+} EFI_ACPI_6_0_MPST_MEMORY_POWER_NODE_TABLE;
+
+///
+/// MPST Memory Power State Characteristics Table
+///
+typedef struct {
+ UINT8 PowerStateStructureID;
+ UINT8 Flag;
+ UINT16 Reserved;
+ UINT32 AveragePowerConsumedInMPS0;
+ UINT32 RelativePowerSavingToMPS0;
+ UINT64 ExitLatencyToMPS0;
+} EFI_ACPI_6_0_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE;
+
+#define EFI_ACPI_6_0_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_MEMORY_CONTENT_PRESERVED 0x01
+#define EFI_ACPI_6_0_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_AUTONOMOUS_MEMORY_POWER_STATE_ENTRY 0x02
+#define EFI_ACPI_6_0_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_AUTONOMOUS_MEMORY_POWER_STATE_EXIT 0x04
+
+typedef struct {
+ UINT16 MemoryPowerStateCharacteristicsCount;
+ UINT8 Reserved[2];
+} EFI_ACPI_6_0_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_TABLE;
+
+///
+/// Memory Topology Table definition.
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 Reserved;
+} EFI_ACPI_6_0_MEMORY_TOPOLOGY_TABLE;
+
+///
+/// PMTT Version (as defined in ACPI 6.0 spec.)
+///
+#define EFI_ACPI_6_0_MEMORY_TOPOLOGY_TABLE_REVISION 0x01
+
+///
+/// Common Memory Aggregator Device Structure.
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Reserved;
+ UINT16 Length;
+ UINT16 Flags;
+ UINT16 Reserved1;
+} EFI_ACPI_6_0_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE;
+
+///
+/// Memory Aggregator Device Type
+///
+#define EFI_ACPI_6_0_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_SOCKET 0x0
+#define EFI_ACPI_6_0_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_MEMORY_CONTROLLER 0x1
+#define EFI_ACPI_6_0_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_DIMM 0x2
+
+///
+/// Socket Memory Aggregator Device Structure.
+///
+typedef struct {
+ EFI_ACPI_6_0_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE Header;
+ UINT16 SocketIdentifier;
+ UINT16 Reserved;
+ // EFI_ACPI_6_0_PMMT_MEMORY_CONTROLLER_MEMORY_AGGREGATOR_DEVICE_STRUCTURE MemoryController[];
+} EFI_ACPI_6_0_PMMT_SOCKET_MEMORY_AGGREGATOR_DEVICE_STRUCTURE;
+
+///
+/// MemoryController Memory Aggregator Device Structure.
+///
+typedef struct {
+ EFI_ACPI_6_0_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE Header;
+ UINT32 ReadLatency;
+ UINT32 WriteLatency;
+ UINT32 ReadBandwidth;
+ UINT32 WriteBandwidth;
+ UINT16 OptimalAccessUnit;
+ UINT16 OptimalAccessAlignment;
+ UINT16 Reserved;
+ UINT16 NumberOfProximityDomains;
+ // UINT32 ProximityDomain[NumberOfProximityDomains];
+ // EFI_ACPI_6_0_PMMT_DIMM_MEMORY_AGGREGATOR_DEVICE_STRUCTURE PhysicalComponent[];
+} EFI_ACPI_6_0_PMMT_MEMORY_CONTROLLER_MEMORY_AGGREGATOR_DEVICE_STRUCTURE;
+
+///
+/// DIMM Memory Aggregator Device Structure.
+///
+typedef struct {
+ EFI_ACPI_6_0_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE Header;
+ UINT16 PhysicalComponentIdentifier;
+ UINT16 Reserved;
+ UINT32 SizeOfDimm;
+ UINT32 SmbiosHandle;
+} EFI_ACPI_6_0_PMMT_DIMM_MEMORY_AGGREGATOR_DEVICE_STRUCTURE;
+
+///
+/// Boot Graphics Resource Table definition.
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ ///
+ /// 2-bytes (16 bit) version ID. This value must be 1.
+ ///
+ UINT16 Version;
+ ///
+ /// 1-byte status field indicating current status about the table.
+ /// Bits[7:1] = Reserved (must be zero)
+ /// Bit [0] = Valid. A one indicates the boot image graphic is valid.
+ ///
+ UINT8 Status;
+ ///
+ /// 1-byte enumerated type field indicating format of the image.
+ /// 0 = Bitmap
+ /// 1 - 255 Reserved (for future use)
+ ///
+ UINT8 ImageType;
+ ///
+ /// 8-byte (64 bit) physical address pointing to the firmware's in-memory copy
+ /// of the image bitmap.
+ ///
+ UINT64 ImageAddress;
+ ///
+ /// A 4-byte (32-bit) unsigned long describing the display X-offset of the boot image.
+ /// (X, Y) display offset of the top left corner of the boot image.
+ /// The top left corner of the display is at offset (0, 0).
+ ///
+ UINT32 ImageOffsetX;
+ ///
+ /// A 4-byte (32-bit) unsigned long describing the display Y-offset of the boot image.
+ /// (X, Y) display offset of the top left corner of the boot image.
+ /// The top left corner of the display is at offset (0, 0).
+ ///
+ UINT32 ImageOffsetY;
+} EFI_ACPI_6_0_BOOT_GRAPHICS_RESOURCE_TABLE;
+
+///
+/// BGRT Revision
+///
+#define EFI_ACPI_6_0_BOOT_GRAPHICS_RESOURCE_TABLE_REVISION 1
+
+///
+/// BGRT Version
+///
+#define EFI_ACPI_6_0_BGRT_VERSION 0x01
+
+///
+/// BGRT Status
+///
+#define EFI_ACPI_6_0_BGRT_STATUS_NOT_DISPLAYED 0x00
+#define EFI_ACPI_6_0_BGRT_STATUS_DISPLAYED 0x01
+
+///
+/// BGRT Image Type
+///
+#define EFI_ACPI_6_0_BGRT_IMAGE_TYPE_BMP 0x00
+
+///
+/// FPDT Version (as defined in ACPI 6.0 spec.)
+///
+#define EFI_ACPI_6_0_FIRMWARE_PERFORMANCE_DATA_TABLE_REVISION 0x01
+
+///
+/// FPDT Performance Record Types
+///
+#define EFI_ACPI_6_0_FPDT_RECORD_TYPE_FIRMWARE_BASIC_BOOT_POINTER 0x0000
+#define EFI_ACPI_6_0_FPDT_RECORD_TYPE_S3_PERFORMANCE_TABLE_POINTER 0x0001
+
+///
+/// FPDT Performance Record Revision
+///
+#define EFI_ACPI_6_0_FPDT_RECORD_REVISION_FIRMWARE_BASIC_BOOT_POINTER 0x01
+#define EFI_ACPI_6_0_FPDT_RECORD_REVISION_S3_PERFORMANCE_TABLE_POINTER 0x01
+
+///
+/// FPDT Runtime Performance Record Types
+///
+#define EFI_ACPI_6_0_FPDT_RUNTIME_RECORD_TYPE_S3_RESUME 0x0000
+#define EFI_ACPI_6_0_FPDT_RUNTIME_RECORD_TYPE_S3_SUSPEND 0x0001
+#define EFI_ACPI_6_0_FPDT_RUNTIME_RECORD_TYPE_FIRMWARE_BASIC_BOOT 0x0002
+
+///
+/// FPDT Runtime Performance Record Revision
+///
+#define EFI_ACPI_6_0_FPDT_RUNTIME_RECORD_REVISION_S3_RESUME 0x01
+#define EFI_ACPI_6_0_FPDT_RUNTIME_RECORD_REVISION_S3_SUSPEND 0x01
+#define EFI_ACPI_6_0_FPDT_RUNTIME_RECORD_REVISION_FIRMWARE_BASIC_BOOT 0x02
+
+///
+/// FPDT Performance Record header
+///
+typedef struct {
+ UINT16 Type;
+ UINT8 Length;
+ UINT8 Revision;
+} EFI_ACPI_6_0_FPDT_PERFORMANCE_RECORD_HEADER;
+
+///
+/// FPDT Performance Table header
+///
+typedef struct {
+ UINT32 Signature;
+ UINT32 Length;
+} EFI_ACPI_6_0_FPDT_PERFORMANCE_TABLE_HEADER;
+
+///
+/// FPDT Firmware Basic Boot Performance Pointer Record Structure
+///
+typedef struct {
+ EFI_ACPI_6_0_FPDT_PERFORMANCE_RECORD_HEADER Header;
+ UINT32 Reserved;
+ ///
+ /// 64-bit processor-relative physical address of the Basic Boot Performance Table.
+ ///
+ UINT64 BootPerformanceTablePointer;
+} EFI_ACPI_6_0_FPDT_BOOT_PERFORMANCE_TABLE_POINTER_RECORD;
+
+///
+/// FPDT S3 Performance Table Pointer Record Structure
+///
+typedef struct {
+ EFI_ACPI_6_0_FPDT_PERFORMANCE_RECORD_HEADER Header;
+ UINT32 Reserved;
+ ///
+ /// 64-bit processor-relative physical address of the S3 Performance Table.
+ ///
+ UINT64 S3PerformanceTablePointer;
+} EFI_ACPI_6_0_FPDT_S3_PERFORMANCE_TABLE_POINTER_RECORD;
+
+///
+/// FPDT Firmware Basic Boot Performance Record Structure
+///
+typedef struct {
+ EFI_ACPI_6_0_FPDT_PERFORMANCE_RECORD_HEADER Header;
+ UINT32 Reserved;
+ ///
+ /// Timer value logged at the beginning of firmware image execution.
+ /// This may not always be zero or near zero.
+ ///
+ UINT64 ResetEnd;
+ ///
+ /// Timer value logged just prior to loading the OS boot loader into memory.
+ /// For non-UEFI compatible boots, this field must be zero.
+ ///
+ UINT64 OsLoaderLoadImageStart;
+ ///
+ /// Timer value logged just prior to launching the previously loaded OS boot loader image.
+ /// For non-UEFI compatible boots, the timer value logged will be just prior
+ /// to the INT 19h handler invocation.
+ ///
+ UINT64 OsLoaderStartImageStart;
+ ///
+ /// Timer value logged at the point when the OS loader calls the
+ /// ExitBootServices function for UEFI compatible firmware.
+ /// For non-UEFI compatible boots, this field must be zero.
+ ///
+ UINT64 ExitBootServicesEntry;
+ ///
+ /// Timer value logged at the point just prior to when the OS loader gaining
+ /// control back from calls the ExitBootServices function for UEFI compatible firmware.
+ /// For non-UEFI compatible boots, this field must be zero.
+ ///
+ UINT64 ExitBootServicesExit;
+} EFI_ACPI_6_0_FPDT_FIRMWARE_BASIC_BOOT_RECORD;
+
+///
+/// FPDT Firmware Basic Boot Performance Table signature
+///
+#define EFI_ACPI_6_0_FPDT_BOOT_PERFORMANCE_TABLE_SIGNATURE SIGNATURE_32('F', 'B', 'P', 'T')
+
+//
+// FPDT Firmware Basic Boot Performance Table
+//
+typedef struct {
+ EFI_ACPI_6_0_FPDT_PERFORMANCE_TABLE_HEADER Header;
+ //
+ // one or more Performance Records.
+ //
+} EFI_ACPI_6_0_FPDT_FIRMWARE_BASIC_BOOT_TABLE;
+
+///
+/// FPDT "S3PT" S3 Performance Table
+///
+#define EFI_ACPI_6_0_FPDT_S3_PERFORMANCE_TABLE_SIGNATURE SIGNATURE_32('S', '3', 'P', 'T')
+
+//
+// FPDT Firmware S3 Boot Performance Table
+//
+typedef struct {
+ EFI_ACPI_6_0_FPDT_PERFORMANCE_TABLE_HEADER Header;
+ //
+ // one or more Performance Records.
+ //
+} EFI_ACPI_6_0_FPDT_FIRMWARE_S3_BOOT_TABLE;
+
+///
+/// FPDT Basic S3 Resume Performance Record
+///
+typedef struct {
+ EFI_ACPI_6_0_FPDT_PERFORMANCE_RECORD_HEADER Header;
+ ///
+ /// A count of the number of S3 resume cycles since the last full boot sequence.
+ ///
+ UINT32 ResumeCount;
+ ///
+ /// Timer recorded at the end of BIOS S3 resume, just prior to handoff to the
+ /// OS waking vector. Only the most recent resume cycle's time is retained.
+ ///
+ UINT64 FullResume;
+ ///
+ /// Average timer value of all resume cycles logged since the last full boot
+ /// sequence, including the most recent resume. Note that the entire log of
+ /// timer values does not need to be retained in order to calculate this average.
+ ///
+ UINT64 AverageResume;
+} EFI_ACPI_6_0_FPDT_S3_RESUME_RECORD;
+
+///
+/// FPDT Basic S3 Suspend Performance Record
+///
+typedef struct {
+ EFI_ACPI_6_0_FPDT_PERFORMANCE_RECORD_HEADER Header;
+ ///
+ /// Timer value recorded at the OS write to SLP_TYP upon entry to S3.
+ /// Only the most recent suspend cycle's timer value is retained.
+ ///
+ UINT64 SuspendStart;
+ ///
+ /// Timer value recorded at the final firmware write to SLP_TYP (or other
+ /// mechanism) used to trigger hardware entry to S3.
+ /// Only the most recent suspend cycle's timer value is retained.
+ ///
+ UINT64 SuspendEnd;
+} EFI_ACPI_6_0_FPDT_S3_SUSPEND_RECORD;
+
+///
+/// Firmware Performance Record Table definition.
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+} EFI_ACPI_6_0_FIRMWARE_PERFORMANCE_RECORD_TABLE;
+
+///
+/// Generic Timer Description Table definition.
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT64 CntControlBasePhysicalAddress;
+ UINT32 Reserved;
+ UINT32 SecurePL1TimerGSIV;
+ UINT32 SecurePL1TimerFlags;
+ UINT32 NonSecurePL1TimerGSIV;
+ UINT32 NonSecurePL1TimerFlags;
+ UINT32 VirtualTimerGSIV;
+ UINT32 VirtualTimerFlags;
+ UINT32 NonSecurePL2TimerGSIV;
+ UINT32 NonSecurePL2TimerFlags;
+ UINT64 CntReadBasePhysicalAddress;
+ UINT32 PlatformTimerCount;
+ UINT32 PlatformTimerOffset;
+} EFI_ACPI_6_0_GENERIC_TIMER_DESCRIPTION_TABLE;
+
+///
+/// GTDT Version (as defined in ACPI 6.0 spec.)
+///
+#define EFI_ACPI_6_0_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION 0x02
+
+///
+/// Timer Flags. All other bits are reserved and must be 0.
+///
+#define EFI_ACPI_6_0_GTDT_TIMER_FLAG_TIMER_INTERRUPT_MODE BIT0
+#define EFI_ACPI_6_0_GTDT_TIMER_FLAG_TIMER_INTERRUPT_POLARITY BIT1
+#define EFI_ACPI_6_0_GTDT_TIMER_FLAG_ALWAYS_ON_CAPABILITY BIT2
+
+///
+/// Platform Timer Type
+///
+#define EFI_ACPI_6_0_GTDT_GT_BLOCK 0
+#define EFI_ACPI_6_0_GTDT_SBSA_GENERIC_WATCHDOG 1
+
+///
+/// GT Block Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT16 Length;
+ UINT8 Reserved;
+ UINT64 CntCtlBase;
+ UINT32 GTBlockTimerCount;
+ UINT32 GTBlockTimerOffset;
+} EFI_ACPI_6_0_GTDT_GT_BLOCK_STRUCTURE;
+
+///
+/// GT Block Timer Structure
+///
+typedef struct {
+ UINT8 GTFrameNumber;
+ UINT8 Reserved[3];
+ UINT64 CntBaseX;
+ UINT64 CntEL0BaseX;
+ UINT32 GTxPhysicalTimerGSIV;
+ UINT32 GTxPhysicalTimerFlags;
+ UINT32 GTxVirtualTimerGSIV;
+ UINT32 GTxVirtualTimerFlags;
+ UINT32 GTxCommonFlags;
+} EFI_ACPI_6_0_GTDT_GT_BLOCK_TIMER_STRUCTURE;
+
+///
+/// GT Block Physical Timers and Virtual Timers Flags. All other bits are reserved and must be 0.
+///
+#define EFI_ACPI_6_0_GTDT_GT_BLOCK_TIMER_FLAG_TIMER_INTERRUPT_MODE BIT0
+#define EFI_ACPI_6_0_GTDT_GT_BLOCK_TIMER_FLAG_TIMER_INTERRUPT_POLARITY BIT1
+
+///
+/// Common Flags Flags. All other bits are reserved and must be 0.
+///
+#define EFI_ACPI_6_0_GTDT_GT_BLOCK_COMMON_FLAG_SECURE_TIMER BIT0
+#define EFI_ACPI_6_0_GTDT_GT_BLOCK_COMMON_FLAG_ALWAYS_ON_CAPABILITY BIT1
+
+///
+/// SBSA Generic Watchdog Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT16 Length;
+ UINT8 Reserved;
+ UINT64 RefreshFramePhysicalAddress;
+ UINT64 WatchdogControlFramePhysicalAddress;
+ UINT32 WatchdogTimerGSIV;
+ UINT32 WatchdogTimerFlags;
+} EFI_ACPI_6_0_GTDT_SBSA_GENERIC_WATCHDOG_STRUCTURE;
+
+///
+/// SBSA Generic Watchdog Timer Flags. All other bits are reserved and must be 0.
+///
+#define EFI_ACPI_6_0_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_TIMER_INTERRUPT_MODE BIT0
+#define EFI_ACPI_6_0_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_TIMER_INTERRUPT_POLARITY BIT1
+#define EFI_ACPI_6_0_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_SECURE_TIMER BIT2
+
+//
+// NVDIMM Firmware Interface Table definition.
+//
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 Reserved;
+} EFI_ACPI_6_0_NVDIMM_FIRMWARE_INTERFACE_TABLE;
+
+//
+// NFIT Version (as defined in ACPI 6.0 spec.)
+//
+#define EFI_ACPI_6_0_NVDIMM_FIRMWARE_INTERFACE_TABLE_REVISION 0x1
+
+//
+// Definition for NFIT Table Structure Types
+//
+#define EFI_ACPI_6_0_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_STRUCTURE_TYPE 0
+#define EFI_ACPI_6_0_NFIT_MEMORY_DEVICE_TO_SYSTEM_ADDRESS_RANGE_MAP_STRUCTURE_TYPE 1
+#define EFI_ACPI_6_0_NFIT_INTERLEAVE_STRUCTURE_TYPE 2
+#define EFI_ACPI_6_0_NFIT_SMBIOS_MANAGEMENT_INFORMATION_STRUCTURE_TYPE 3
+#define EFI_ACPI_6_0_NFIT_NVDIMM_CONTROL_REGION_STRUCTURE_TYPE 4
+#define EFI_ACPI_6_0_NFIT_NVDIMM_BLOCK_DATA_WINDOW_REGION_STRUCTURE_TYPE 5
+#define EFI_ACPI_6_0_NFIT_FLUSH_HINT_ADDRESS_STRUCTURE_TYPE 6
+
+//
+// Definition for NFIT Structure Header
+//
+typedef struct {
+ UINT16 Type;
+ UINT16 Length;
+} EFI_ACPI_6_0_NFIT_STRUCTURE_HEADER;
+
+//
+// Definition for System Physical Address Range Structure
+//
+#define EFI_ACPI_6_0_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_FLAGS_CONTROL_REGION_FOR_MANAGEMENT BIT0
+#define EFI_ACPI_6_0_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_FLAGS_PROXIMITY_DOMAIN_VALID BIT1
+#define EFI_ACPI_6_0_NFIT_GUID_VOLATILE_MEMORY_REGION { 0x7305944F, 0xFDDA, 0x44E3, { 0xB1, 0x6C, 0x3F, 0x22, 0xD2, 0x52, 0xE5, 0xD0 }}
+#define EFI_ACPI_6_0_NFIT_GUID_BYTE_ADDRESSABLE_PERSISTENT_MEMORY_REGION { 0x66F0D379, 0xB4F3, 0x4074, { 0xAC, 0x43, 0x0D, 0x33, 0x18, 0xB7, 0x8C, 0xDB }}
+#define EFI_ACPI_6_0_NFIT_GUID_NVDIMM_CONTROL_REGION { 0x92F701F6, 0x13B4, 0x405D, { 0x91, 0x0B, 0x29, 0x93, 0x67, 0xE8, 0x23, 0x4C }}
+#define EFI_ACPI_6_0_NFIT_GUID_NVDIMM_BLOCK_DATA_WINDOW_REGION { 0x91AF0530, 0x5D86, 0x470E, { 0xA6, 0xB0, 0x0A, 0x2D, 0xB9, 0x40, 0x82, 0x49 }}
+#define EFI_ACPI_6_0_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_DISK_REGION_VOLATILE { 0x77AB535A, 0x45FC, 0x624B, { 0x55, 0x60, 0xF7, 0xB2, 0x81, 0xD1, 0xF9, 0x6E }}
+#define EFI_ACPI_6_0_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_CD_REGION_VOLATILE { 0x3D5ABD30, 0x4175, 0x87CE, { 0x6D, 0x64, 0xD2, 0xAD, 0xE5, 0x23, 0xC4, 0xBB }}
+#define EFI_ACPI_6_0_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_DISK_REGION_PERSISTENT { 0x5CEA02C9, 0x4D07, 0x69D3, { 0x26, 0x9F ,0x44, 0x96, 0xFB, 0xE0, 0x96, 0xF9 }}
+#define EFI_ACPI_6_0_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_CD_REGION_PERSISTENT { 0x08018188, 0x42CD, 0xBB48, { 0x10, 0x0F, 0x53, 0x87, 0xD5, 0x3D, 0xED, 0x3D }}
+typedef struct {
+ UINT16 Type;
+ UINT16 Length;
+ UINT16 SPARangeStructureIndex;
+ UINT16 Flags;
+ UINT32 Reserved_8;
+ UINT32 ProximityDomain;
+ GUID AddressRangeTypeGUID;
+ UINT64 SystemPhysicalAddressRangeBase;
+ UINT64 SystemPhysicalAddressRangeLength;
+ UINT64 AddressRangeMemoryMappingAttribute;
+} EFI_ACPI_6_0_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_STRUCTURE;
+
+//
+// Definition for Memory Device to System Physical Address Range Mapping Structure
+//
+typedef struct {
+ UINT32 DIMMNumber : 4;
+ UINT32 MemoryChannelNumber : 4;
+ UINT32 MemoryControllerID : 4;
+ UINT32 SocketID : 4;
+ UINT32 NodeControllerID : 12;
+ UINT32 Reserved_28 : 4;
+} EFI_ACPI_6_0_NFIT_DEVICE_HANDLE;
+
+#define EFI_ACPI_6_0_NFIT_MEMORY_DEVICE_STATE_FLAGS_PREVIOUS_SAVE_FAIL BIT0
+#define EFI_ACPI_6_0_NFIT_MEMORY_DEVICE_STATE_FLAGS_LAST_RESTORE_FAIL BIT1
+#define EFI_ACPI_6_0_NFIT_MEMORY_DEVICE_STATE_FLAGS_PLATFORM_FLUSH_FAIL BIT2
+#define EFI_ACPI_6_0_NFIT_MEMORY_DEVICE_STATE_FLAGS_NOT_ARMED_PRIOR_TO_OSPM_HAND_OFF BIT3
+#define EFI_ACPI_6_0_NFIT_MEMORY_DEVICE_STATE_FLAGS_SMART_HEALTH_EVENTS_PRIOR_OSPM_HAND_OFF BIT4
+#define EFI_ACPI_6_0_NFIT_MEMORY_DEVICE_STATE_FLAGS_FIRMWARE_ENABLED_TO_NOTIFY_OSPM_ON_SMART_HEALTH_EVENTS BIT5
+typedef struct {
+ UINT16 Type;
+ UINT16 Length;
+ EFI_ACPI_6_0_NFIT_DEVICE_HANDLE NFITDeviceHandle;
+ UINT16 MemoryDevicePhysicalID;
+ UINT16 MemoryDeviceRegionID;
+ UINT16 SPARangeStructureIndex;
+ UINT16 NVDIMMControlRegionStructureIndex;
+ UINT64 MemoryDeviceRegionSize;
+ UINT64 RegionOffset;
+ UINT64 MemoryDevicePhysicalAddressRegionBase;
+ UINT16 InterleaveStructureIndex;
+ UINT16 InterleaveWays;
+ UINT16 MemoryDeviceStateFlags;
+ UINT16 Reserved_46;
+} EFI_ACPI_6_0_NFIT_MEMORY_DEVICE_TO_SYSTEM_ADDRESS_RANGE_MAP_STRUCTURE;
+
+//
+// Definition for Interleave Structure
+//
+typedef struct {
+ UINT16 Type;
+ UINT16 Length;
+ UINT16 InterleaveStructureIndex;
+ UINT16 Reserved_6;
+ UINT32 NumberOfLines;
+ UINT32 LineSize;
+ // UINT32 LineOffset[NumberOfLines];
+} EFI_ACPI_6_0_NFIT_INTERLEAVE_STRUCTURE;
+
+//
+// Definition for SMBIOS Management Information Structure
+//
+typedef struct {
+ UINT16 Type;
+ UINT16 Length;
+ UINT32 Reserved_4;
+ // UINT8 Data[];
+} EFI_ACPI_6_0_NFIT_SMBIOS_MANAGEMENT_INFORMATION_STRUCTURE;
+
+//
+// Definition for NVDIMM Control Region Structure
+//
+#define EFI_ACPI_6_0_NFIT_NVDIMM_CONTROL_REGION_FLAGS_BLOCK_DATA_WINDOWS_BUFFERED BIT0
+typedef struct {
+ UINT16 Type;
+ UINT16 Length;
+ UINT16 NVDIMMControlRegionStructureIndex;
+ UINT16 VendorID;
+ UINT16 DeviceID;
+ UINT16 RevisionID;
+ UINT16 SubsystemVendorID;
+ UINT16 SubsystemDeviceID;
+ UINT16 SubsystemRevisionID;
+ UINT8 Reserved_18[6];
+ UINT32 SerialNumber;
+ UINT16 RegionFormatInterfaceCode;
+ UINT16 NumberOfBlockControlWindows;
+ UINT64 SizeOfBlockControlWindow;
+ UINT64 CommandRegisterOffsetInBlockControlWindow;
+ UINT64 SizeOfCommandRegisterInBlockControlWindows;
+ UINT64 StatusRegisterOffsetInBlockControlWindow;
+ UINT64 SizeOfStatusRegisterInBlockControlWindows;
+ UINT16 NVDIMMControlRegionFlag;
+ UINT8 Reserved_74[6];
+} EFI_ACPI_6_0_NFIT_NVDIMM_CONTROL_REGION_STRUCTURE;
+
+//
+// Definition for NVDIMM Block Data Window Region Structure
+//
+typedef struct {
+ UINT16 Type;
+ UINT16 Length;
+ UINT16 NVDIMMControlRegionStructureIndex;
+ UINT16 NumberOfBlockDataWindows;
+ UINT64 BlockDataWindowStartOffset;
+ UINT64 SizeOfBlockDataWindow;
+ UINT64 BlockAccessibleMemoryCapacity;
+ UINT64 BeginningAddressOfFirstBlockInBlockAccessibleMemory;
+} EFI_ACPI_6_0_NFIT_NVDIMM_BLOCK_DATA_WINDOW_REGION_STRUCTURE;
+
+//
+// Definition for Flush Hint Address Structure
+//
+typedef struct {
+ UINT16 Type;
+ UINT16 Length;
+ EFI_ACPI_6_0_NFIT_DEVICE_HANDLE NFITDeviceHandle;
+ UINT16 NumberOfFlushHintAddresses;
+ UINT8 Reserved_10[6];
+ // UINT64 FlushHintAddress[NumberOfFlushHintAddresses];
+} EFI_ACPI_6_0_NFIT_FLUSH_HINT_ADDRESS_STRUCTURE;
+
+///
+/// Boot Error Record Table (BERT)
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 BootErrorRegionLength;
+ UINT64 BootErrorRegion;
+} EFI_ACPI_6_0_BOOT_ERROR_RECORD_TABLE_HEADER;
+
+///
+/// BERT Version (as defined in ACPI 6.0 spec.)
+///
+#define EFI_ACPI_6_0_BOOT_ERROR_RECORD_TABLE_REVISION 0x01
+
+///
+/// Boot Error Region Block Status Definition
+///
+typedef struct {
+ UINT32 UncorrectableErrorValid : 1;
+ UINT32 CorrectableErrorValid : 1;
+ UINT32 MultipleUncorrectableErrors : 1;
+ UINT32 MultipleCorrectableErrors : 1;
+ UINT32 ErrorDataEntryCount : 10;
+ UINT32 Reserved : 18;
+} EFI_ACPI_6_0_ERROR_BLOCK_STATUS;
+
+///
+/// Boot Error Region Definition
+///
+typedef struct {
+ EFI_ACPI_6_0_ERROR_BLOCK_STATUS BlockStatus;
+ UINT32 RawDataOffset;
+ UINT32 RawDataLength;
+ UINT32 DataLength;
+ UINT32 ErrorSeverity;
+} EFI_ACPI_6_0_BOOT_ERROR_REGION_STRUCTURE;
+
+//
+// Boot Error Severity types
+//
+#define EFI_ACPI_6_0_ERROR_SEVERITY_RECOVERABLE 0x00
+#define EFI_ACPI_6_0_ERROR_SEVERITY_FATAL 0x01
+#define EFI_ACPI_6_0_ERROR_SEVERITY_CORRECTED 0x02
+#define EFI_ACPI_6_0_ERROR_SEVERITY_NONE 0x03
+//
+// The term 'Correctable' is no longer being used as an error severity of the
+// reported error since ACPI Specification Version 5.1 Errata B.
+// The below macro is considered as deprecated and should no longer be used.
+//
+#define EFI_ACPI_6_0_ERROR_SEVERITY_CORRECTABLE 0x00
+
+///
+/// Generic Error Data Entry Definition
+///
+typedef struct {
+ UINT8 SectionType[16];
+ UINT32 ErrorSeverity;
+ UINT16 Revision;
+ UINT8 ValidationBits;
+ UINT8 Flags;
+ UINT32 ErrorDataLength;
+ UINT8 FruId[16];
+ UINT8 FruText[20];
+} EFI_ACPI_6_0_GENERIC_ERROR_DATA_ENTRY_STRUCTURE;
+
+///
+/// Generic Error Data Entry Version (as defined in ACPI 6.0 spec.)
+///
+#define EFI_ACPI_6_0_GENERIC_ERROR_DATA_ENTRY_REVISION 0x0201
+
+///
+/// HEST - Hardware Error Source Table
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 ErrorSourceCount;
+} EFI_ACPI_6_0_HARDWARE_ERROR_SOURCE_TABLE_HEADER;
+
+///
+/// HEST Version (as defined in ACPI 6.0 spec.)
+///
+#define EFI_ACPI_6_0_HARDWARE_ERROR_SOURCE_TABLE_REVISION 0x01
+
+//
+// Error Source structure types.
+//
+#define EFI_ACPI_6_0_IA32_ARCHITECTURE_MACHINE_CHECK_EXCEPTION 0x00
+#define EFI_ACPI_6_0_IA32_ARCHITECTURE_CORRECTED_MACHINE_CHECK 0x01
+#define EFI_ACPI_6_0_IA32_ARCHITECTURE_NMI_ERROR 0x02
+#define EFI_ACPI_6_0_PCI_EXPRESS_ROOT_PORT_AER 0x06
+#define EFI_ACPI_6_0_PCI_EXPRESS_DEVICE_AER 0x07
+#define EFI_ACPI_6_0_PCI_EXPRESS_BRIDGE_AER 0x08
+#define EFI_ACPI_6_0_GENERIC_HARDWARE_ERROR 0x09
+
+//
+// Error Source structure flags.
+//
+#define EFI_ACPI_6_0_ERROR_SOURCE_FLAG_FIRMWARE_FIRST (1 << 0)
+#define EFI_ACPI_6_0_ERROR_SOURCE_FLAG_GLOBAL (1 << 1)
+
+///
+/// IA-32 Architecture Machine Check Exception Structure Definition
+///
+typedef struct {
+ UINT16 Type;
+ UINT16 SourceId;
+ UINT8 Reserved0[2];
+ UINT8 Flags;
+ UINT8 Enabled;
+ UINT32 NumberOfRecordsToPreAllocate;
+ UINT32 MaxSectionsPerRecord;
+ UINT64 GlobalCapabilityInitData;
+ UINT64 GlobalControlInitData;
+ UINT8 NumberOfHardwareBanks;
+ UINT8 Reserved1[7];
+} EFI_ACPI_6_0_IA32_ARCHITECTURE_MACHINE_CHECK_EXCEPTION_STRUCTURE;
+
+///
+/// IA-32 Architecture Machine Check Bank Structure Definition
+///
+typedef struct {
+ UINT8 BankNumber;
+ UINT8 ClearStatusOnInitialization;
+ UINT8 StatusDataFormat;
+ UINT8 Reserved0;
+ UINT32 ControlRegisterMsrAddress;
+ UINT64 ControlInitData;
+ UINT32 StatusRegisterMsrAddress;
+ UINT32 AddressRegisterMsrAddress;
+ UINT32 MiscRegisterMsrAddress;
+} EFI_ACPI_6_0_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_BANK_STRUCTURE;
+
+///
+/// IA-32 Architecture Machine Check Bank Structure MCA data format
+///
+#define EFI_ACPI_6_0_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_IA32 0x00
+#define EFI_ACPI_6_0_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_INTEL64 0x01
+#define EFI_ACPI_6_0_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_AMD64 0x02
+
+//
+// Hardware Error Notification types. All other values are reserved
+//
+#define EFI_ACPI_6_0_HARDWARE_ERROR_NOTIFICATION_POLLED 0x00
+#define EFI_ACPI_6_0_HARDWARE_ERROR_NOTIFICATION_EXTERNAL_INTERRUPT 0x01
+#define EFI_ACPI_6_0_HARDWARE_ERROR_NOTIFICATION_LOCAL_INTERRUPT 0x02
+#define EFI_ACPI_6_0_HARDWARE_ERROR_NOTIFICATION_SCI 0x03
+#define EFI_ACPI_6_0_HARDWARE_ERROR_NOTIFICATION_NMI 0x04
+#define EFI_ACPI_6_0_HARDWARE_ERROR_NOTIFICATION_CMCI 0x05
+#define EFI_ACPI_6_0_HARDWARE_ERROR_NOTIFICATION_MCE 0x06
+#define EFI_ACPI_6_0_HARDWARE_ERROR_NOTIFICATION_GPIO_SIGNAL 0x07
+
+///
+/// Hardware Error Notification Configuration Write Enable Structure Definition
+///
+typedef struct {
+ UINT16 Type : 1;
+ UINT16 PollInterval : 1;
+ UINT16 SwitchToPollingThresholdValue : 1;
+ UINT16 SwitchToPollingThresholdWindow : 1;
+ UINT16 ErrorThresholdValue : 1;
+ UINT16 ErrorThresholdWindow : 1;
+ UINT16 Reserved : 10;
+} EFI_ACPI_6_0_HARDWARE_ERROR_NOTIFICATION_CONFIGURATION_WRITE_ENABLE_STRUCTURE;
+
+///
+/// Hardware Error Notification Structure Definition
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ EFI_ACPI_6_0_HARDWARE_ERROR_NOTIFICATION_CONFIGURATION_WRITE_ENABLE_STRUCTURE ConfigurationWriteEnable;
+ UINT32 PollInterval;
+ UINT32 Vector;
+ UINT32 SwitchToPollingThresholdValue;
+ UINT32 SwitchToPollingThresholdWindow;
+ UINT32 ErrorThresholdValue;
+ UINT32 ErrorThresholdWindow;
+} EFI_ACPI_6_0_HARDWARE_ERROR_NOTIFICATION_STRUCTURE;
+
+///
+/// IA-32 Architecture Corrected Machine Check Structure Definition
+///
+typedef struct {
+ UINT16 Type;
+ UINT16 SourceId;
+ UINT8 Reserved0[2];
+ UINT8 Flags;
+ UINT8 Enabled;
+ UINT32 NumberOfRecordsToPreAllocate;
+ UINT32 MaxSectionsPerRecord;
+ EFI_ACPI_6_0_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure;
+ UINT8 NumberOfHardwareBanks;
+ UINT8 Reserved1[3];
+} EFI_ACPI_6_0_IA32_ARCHITECTURE_CORRECTED_MACHINE_CHECK_STRUCTURE;
+
+///
+/// IA-32 Architecture NMI Error Structure Definition
+///
+typedef struct {
+ UINT16 Type;
+ UINT16 SourceId;
+ UINT8 Reserved0[2];
+ UINT32 NumberOfRecordsToPreAllocate;
+ UINT32 MaxSectionsPerRecord;
+ UINT32 MaxRawDataLength;
+} EFI_ACPI_6_0_IA32_ARCHITECTURE_NMI_ERROR_STRUCTURE;
+
+///
+/// PCI Express Root Port AER Structure Definition
+///
+typedef struct {
+ UINT16 Type;
+ UINT16 SourceId;
+ UINT8 Reserved0[2];
+ UINT8 Flags;
+ UINT8 Enabled;
+ UINT32 NumberOfRecordsToPreAllocate;
+ UINT32 MaxSectionsPerRecord;
+ UINT32 Bus;
+ UINT16 Device;
+ UINT16 Function;
+ UINT16 DeviceControl;
+ UINT8 Reserved1[2];
+ UINT32 UncorrectableErrorMask;
+ UINT32 UncorrectableErrorSeverity;
+ UINT32 CorrectableErrorMask;
+ UINT32 AdvancedErrorCapabilitiesAndControl;
+ UINT32 RootErrorCommand;
+} EFI_ACPI_6_0_PCI_EXPRESS_ROOT_PORT_AER_STRUCTURE;
+
+///
+/// PCI Express Device AER Structure Definition
+///
+typedef struct {
+ UINT16 Type;
+ UINT16 SourceId;
+ UINT8 Reserved0[2];
+ UINT8 Flags;
+ UINT8 Enabled;
+ UINT32 NumberOfRecordsToPreAllocate;
+ UINT32 MaxSectionsPerRecord;
+ UINT32 Bus;
+ UINT16 Device;
+ UINT16 Function;
+ UINT16 DeviceControl;
+ UINT8 Reserved1[2];
+ UINT32 UncorrectableErrorMask;
+ UINT32 UncorrectableErrorSeverity;
+ UINT32 CorrectableErrorMask;
+ UINT32 AdvancedErrorCapabilitiesAndControl;
+} EFI_ACPI_6_0_PCI_EXPRESS_DEVICE_AER_STRUCTURE;
+
+///
+/// PCI Express Bridge AER Structure Definition
+///
+typedef struct {
+ UINT16 Type;
+ UINT16 SourceId;
+ UINT8 Reserved0[2];
+ UINT8 Flags;
+ UINT8 Enabled;
+ UINT32 NumberOfRecordsToPreAllocate;
+ UINT32 MaxSectionsPerRecord;
+ UINT32 Bus;
+ UINT16 Device;
+ UINT16 Function;
+ UINT16 DeviceControl;
+ UINT8 Reserved1[2];
+ UINT32 UncorrectableErrorMask;
+ UINT32 UncorrectableErrorSeverity;
+ UINT32 CorrectableErrorMask;
+ UINT32 AdvancedErrorCapabilitiesAndControl;
+ UINT32 SecondaryUncorrectableErrorMask;
+ UINT32 SecondaryUncorrectableErrorSeverity;
+ UINT32 SecondaryAdvancedErrorCapabilitiesAndControl;
+} EFI_ACPI_6_0_PCI_EXPRESS_BRIDGE_AER_STRUCTURE;
+
+///
+/// Generic Hardware Error Source Structure Definition
+///
+typedef struct {
+ UINT16 Type;
+ UINT16 SourceId;
+ UINT16 RelatedSourceId;
+ UINT8 Flags;
+ UINT8 Enabled;
+ UINT32 NumberOfRecordsToPreAllocate;
+ UINT32 MaxSectionsPerRecord;
+ UINT32 MaxRawDataLength;
+ EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE ErrorStatusAddress;
+ EFI_ACPI_6_0_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure;
+ UINT32 ErrorStatusBlockLength;
+} EFI_ACPI_6_0_GENERIC_HARDWARE_ERROR_SOURCE_STRUCTURE;
+
+///
+/// Generic Error Status Definition
+///
+typedef struct {
+ EFI_ACPI_6_0_ERROR_BLOCK_STATUS BlockStatus;
+ UINT32 RawDataOffset;
+ UINT32 RawDataLength;
+ UINT32 DataLength;
+ UINT32 ErrorSeverity;
+} EFI_ACPI_6_0_GENERIC_ERROR_STATUS_STRUCTURE;
+
+///
+/// ERST - Error Record Serialization Table
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 SerializationHeaderSize;
+ UINT8 Reserved0[4];
+ UINT32 InstructionEntryCount;
+} EFI_ACPI_6_0_ERROR_RECORD_SERIALIZATION_TABLE_HEADER;
+
+///
+/// ERST Version (as defined in ACPI 6.0 spec.)
+///
+#define EFI_ACPI_6_0_ERROR_RECORD_SERIALIZATION_TABLE_REVISION 0x01
+
+///
+/// ERST Serialization Actions
+///
+#define EFI_ACPI_6_0_ERST_BEGIN_WRITE_OPERATION 0x00
+#define EFI_ACPI_6_0_ERST_BEGIN_READ_OPERATION 0x01
+#define EFI_ACPI_6_0_ERST_BEGIN_CLEAR_OPERATION 0x02
+#define EFI_ACPI_6_0_ERST_END_OPERATION 0x03
+#define EFI_ACPI_6_0_ERST_SET_RECORD_OFFSET 0x04
+#define EFI_ACPI_6_0_ERST_EXECUTE_OPERATION 0x05
+#define EFI_ACPI_6_0_ERST_CHECK_BUSY_STATUS 0x06
+#define EFI_ACPI_6_0_ERST_GET_COMMAND_STATUS 0x07
+#define EFI_ACPI_6_0_ERST_GET_RECORD_IDENTIFIER 0x08
+#define EFI_ACPI_6_0_ERST_SET_RECORD_IDENTIFIER 0x09
+#define EFI_ACPI_6_0_ERST_GET_RECORD_COUNT 0x0A
+#define EFI_ACPI_6_0_ERST_BEGIN_DUMMY_WRITE_OPERATION 0x0B
+#define EFI_ACPI_6_0_ERST_GET_ERROR_LOG_ADDRESS_RANGE 0x0D
+#define EFI_ACPI_6_0_ERST_GET_ERROR_LOG_ADDRESS_RANGE_LENGTH 0x0E
+#define EFI_ACPI_6_0_ERST_GET_ERROR_LOG_ADDRESS_RANGE_ATTRIBUTES 0x0F
+
+///
+/// ERST Action Command Status
+///
+#define EFI_ACPI_6_0_ERST_STATUS_SUCCESS 0x00
+#define EFI_ACPI_6_0_ERST_STATUS_NOT_ENOUGH_SPACE 0x01
+#define EFI_ACPI_6_0_ERST_STATUS_HARDWARE_NOT_AVAILABLE 0x02
+#define EFI_ACPI_6_0_ERST_STATUS_FAILED 0x03
+#define EFI_ACPI_6_0_ERST_STATUS_RECORD_STORE_EMPTY 0x04
+#define EFI_ACPI_6_0_ERST_STATUS_RECORD_NOT_FOUND 0x05
+
+///
+/// ERST Serialization Instructions
+///
+#define EFI_ACPI_6_0_ERST_READ_REGISTER 0x00
+#define EFI_ACPI_6_0_ERST_READ_REGISTER_VALUE 0x01
+#define EFI_ACPI_6_0_ERST_WRITE_REGISTER 0x02
+#define EFI_ACPI_6_0_ERST_WRITE_REGISTER_VALUE 0x03
+#define EFI_ACPI_6_0_ERST_NOOP 0x04
+#define EFI_ACPI_6_0_ERST_LOAD_VAR1 0x05
+#define EFI_ACPI_6_0_ERST_LOAD_VAR2 0x06
+#define EFI_ACPI_6_0_ERST_STORE_VAR1 0x07
+#define EFI_ACPI_6_0_ERST_ADD 0x08
+#define EFI_ACPI_6_0_ERST_SUBTRACT 0x09
+#define EFI_ACPI_6_0_ERST_ADD_VALUE 0x0A
+#define EFI_ACPI_6_0_ERST_SUBTRACT_VALUE 0x0B
+#define EFI_ACPI_6_0_ERST_STALL 0x0C
+#define EFI_ACPI_6_0_ERST_STALL_WHILE_TRUE 0x0D
+#define EFI_ACPI_6_0_ERST_SKIP_NEXT_INSTRUCTION_IF_TRUE 0x0E
+#define EFI_ACPI_6_0_ERST_GOTO 0x0F
+#define EFI_ACPI_6_0_ERST_SET_SRC_ADDRESS_BASE 0x10
+#define EFI_ACPI_6_0_ERST_SET_DST_ADDRESS_BASE 0x11
+#define EFI_ACPI_6_0_ERST_MOVE_DATA 0x12
+
+///
+/// ERST Instruction Flags
+///
+#define EFI_ACPI_6_0_ERST_PRESERVE_REGISTER 0x01
+
+///
+/// ERST Serialization Instruction Entry
+///
+typedef struct {
+ UINT8 SerializationAction;
+ UINT8 Instruction;
+ UINT8 Flags;
+ UINT8 Reserved0;
+ EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE RegisterRegion;
+ UINT64 Value;
+ UINT64 Mask;
+} EFI_ACPI_6_0_ERST_SERIALIZATION_INSTRUCTION_ENTRY;
+
+///
+/// EINJ - Error Injection Table
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 InjectionHeaderSize;
+ UINT8 InjectionFlags;
+ UINT8 Reserved0[3];
+ UINT32 InjectionEntryCount;
+} EFI_ACPI_6_0_ERROR_INJECTION_TABLE_HEADER;
+
+///
+/// EINJ Version (as defined in ACPI 6.0 spec.)
+///
+#define EFI_ACPI_6_0_ERROR_INJECTION_TABLE_REVISION 0x01
+
+///
+/// EINJ Error Injection Actions
+///
+#define EFI_ACPI_6_0_EINJ_BEGIN_INJECTION_OPERATION 0x00
+#define EFI_ACPI_6_0_EINJ_GET_TRIGGER_ERROR_ACTION_TABLE 0x01
+#define EFI_ACPI_6_0_EINJ_SET_ERROR_TYPE 0x02
+#define EFI_ACPI_6_0_EINJ_GET_ERROR_TYPE 0x03
+#define EFI_ACPI_6_0_EINJ_END_OPERATION 0x04
+#define EFI_ACPI_6_0_EINJ_EXECUTE_OPERATION 0x05
+#define EFI_ACPI_6_0_EINJ_CHECK_BUSY_STATUS 0x06
+#define EFI_ACPI_6_0_EINJ_GET_COMMAND_STATUS 0x07
+#define EFI_ACPI_6_0_EINJ_TRIGGER_ERROR 0xFF
+
+///
+/// EINJ Action Command Status
+///
+#define EFI_ACPI_6_0_EINJ_STATUS_SUCCESS 0x00
+#define EFI_ACPI_6_0_EINJ_STATUS_UNKNOWN_FAILURE 0x01
+#define EFI_ACPI_6_0_EINJ_STATUS_INVALID_ACCESS 0x02
+
+///
+/// EINJ Error Type Definition
+///
+#define EFI_ACPI_6_0_EINJ_ERROR_PROCESSOR_CORRECTABLE (1 << 0)
+#define EFI_ACPI_6_0_EINJ_ERROR_PROCESSOR_UNCORRECTABLE_NONFATAL (1 << 1)
+#define EFI_ACPI_6_0_EINJ_ERROR_PROCESSOR_UNCORRECTABLE_FATAL (1 << 2)
+#define EFI_ACPI_6_0_EINJ_ERROR_MEMORY_CORRECTABLE (1 << 3)
+#define EFI_ACPI_6_0_EINJ_ERROR_MEMORY_UNCORRECTABLE_NONFATAL (1 << 4)
+#define EFI_ACPI_6_0_EINJ_ERROR_MEMORY_UNCORRECTABLE_FATAL (1 << 5)
+#define EFI_ACPI_6_0_EINJ_ERROR_PCI_EXPRESS_CORRECTABLE (1 << 6)
+#define EFI_ACPI_6_0_EINJ_ERROR_PCI_EXPRESS_UNCORRECTABLE_NONFATAL (1 << 7)
+#define EFI_ACPI_6_0_EINJ_ERROR_PCI_EXPRESS_UNCORRECTABLE_FATAL (1 << 8)
+#define EFI_ACPI_6_0_EINJ_ERROR_PLATFORM_CORRECTABLE (1 << 9)
+#define EFI_ACPI_6_0_EINJ_ERROR_PLATFORM_UNCORRECTABLE_NONFATAL (1 << 10)
+#define EFI_ACPI_6_0_EINJ_ERROR_PLATFORM_UNCORRECTABLE_FATAL (1 << 11)
+
+///
+/// EINJ Injection Instructions
+///
+#define EFI_ACPI_6_0_EINJ_READ_REGISTER 0x00
+#define EFI_ACPI_6_0_EINJ_READ_REGISTER_VALUE 0x01
+#define EFI_ACPI_6_0_EINJ_WRITE_REGISTER 0x02
+#define EFI_ACPI_6_0_EINJ_WRITE_REGISTER_VALUE 0x03
+#define EFI_ACPI_6_0_EINJ_NOOP 0x04
+
+///
+/// EINJ Instruction Flags
+///
+#define EFI_ACPI_6_0_EINJ_PRESERVE_REGISTER 0x01
+
+///
+/// EINJ Injection Instruction Entry
+///
+typedef struct {
+ UINT8 InjectionAction;
+ UINT8 Instruction;
+ UINT8 Flags;
+ UINT8 Reserved0;
+ EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE RegisterRegion;
+ UINT64 Value;
+ UINT64 Mask;
+} EFI_ACPI_6_0_EINJ_INJECTION_INSTRUCTION_ENTRY;
+
+///
+/// EINJ Trigger Action Table
+///
+typedef struct {
+ UINT32 HeaderSize;
+ UINT32 Revision;
+ UINT32 TableSize;
+ UINT32 EntryCount;
+} EFI_ACPI_6_0_EINJ_TRIGGER_ACTION_TABLE;
+
+///
+/// Platform Communications Channel Table (PCCT)
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 Flags;
+ UINT64 Reserved;
+} EFI_ACPI_6_0_PLATFORM_COMMUNICATION_CHANNEL_TABLE_HEADER;
+
+///
+/// PCCT Version (as defined in ACPI 6.0 spec.)
+///
+#define EFI_ACPI_6_0_PLATFORM_COMMUNICATION_CHANNEL_TABLE_REVISION 0x01
+
+///
+/// PCCT Global Flags
+///
+#define EFI_ACPI_6_0_PCCT_FLAGS_SCI_DOORBELL BIT0
+
+//
+// PCCT Subspace type
+//
+#define EFI_ACPI_6_0_PCCT_SUBSPACE_TYPE_GENERIC 0x00
+#define EFI_ACPI_6_0_PCCT_SUBSPACE_TYPE_1_HW_REDUCED_COMMUNICATIONS 0x01
+#define EFI_ACPI_6_0_PCCT_SUBSPACE_TYPE_2_HW_REDUCED_COMMUNICATIONS 0x02
+
+///
+/// PCC Subspace Structure Header
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+} EFI_ACPI_6_0_PCCT_SUBSPACE_HEADER;
+
+///
+/// Generic Communications Subspace Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 Reserved[6];
+ UINT64 BaseAddress;
+ UINT64 AddressLength;
+ EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE DoorbellRegister;
+ UINT64 DoorbellPreserve;
+ UINT64 DoorbellWrite;
+ UINT32 NominalLatency;
+ UINT32 MaximumPeriodicAccessRate;
+ UINT16 MinimumRequestTurnaroundTime;
+} EFI_ACPI_6_0_PCCT_SUBSPACE_GENERIC;
+
+///
+/// Generic Communications Channel Shared Memory Region
+///
+
+typedef struct {
+ UINT8 Command;
+ UINT8 Reserved : 7;
+ UINT8 GenerateSci : 1;
+} EFI_ACPI_6_0_PCCT_GENERIC_SHARED_MEMORY_REGION_COMMAND;
+
+typedef struct {
+ UINT8 CommandComplete : 1;
+ UINT8 SciDoorbell : 1;
+ UINT8 Error : 1;
+ UINT8 PlatformNotification : 1;
+ UINT8 Reserved : 4;
+ UINT8 Reserved1;
+} EFI_ACPI_6_0_PCCT_GENERIC_SHARED_MEMORY_REGION_STATUS;
+
+typedef struct {
+ UINT32 Signature;
+ EFI_ACPI_6_0_PCCT_GENERIC_SHARED_MEMORY_REGION_COMMAND Command;
+ EFI_ACPI_6_0_PCCT_GENERIC_SHARED_MEMORY_REGION_STATUS Status;
+} EFI_ACPI_6_0_PCCT_GENERIC_SHARED_MEMORY_REGION_HEADER;
+
+#define EFI_ACPI_6_0_PCCT_SUBSPACE_DOORBELL_INTERRUPT_FLAGS_POLARITY BIT0
+#define EFI_ACPI_6_0_PCCT_SUBSPACE_DOORBELL_INTERRUPT_FLAGS_MODE BIT1
+
+///
+/// Type 1 HW-Reduced Communications Subspace Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT32 DoorbellInterrupt;
+ UINT8 DoorbellInterruptFlags;
+ UINT8 Reserved;
+ UINT64 BaseAddress;
+ UINT64 AddressLength;
+ EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE DoorbellRegister;
+ UINT64 DoorbellPreserve;
+ UINT64 DoorbellWrite;
+ UINT32 NominalLatency;
+ UINT32 MaximumPeriodicAccessRate;
+ UINT16 MinimumRequestTurnaroundTime;
+} EFI_ACPI_6_0_PCCT_SUBSPACE_1_HW_REDUCED_COMMUNICATIONS;
+
+///
+/// Type 2 HW-Reduced Communications Subspace Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT32 DoorbellInterrupt;
+ UINT8 DoorbellInterruptFlags;
+ UINT8 Reserved;
+ UINT64 BaseAddress;
+ UINT64 AddressLength;
+ EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE DoorbellRegister;
+ UINT64 DoorbellPreserve;
+ UINT64 DoorbellWrite;
+ UINT32 NominalLatency;
+ UINT32 MaximumPeriodicAccessRate;
+ UINT16 MinimumRequestTurnaroundTime;
+ EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE DoorbellAckRegister;
+ UINT64 DoorbellAckPreserve;
+ UINT64 DoorbellAckWrite;
+} EFI_ACPI_6_0_PCCT_SUBSPACE_2_HW_REDUCED_COMMUNICATIONS;
+
+//
+// Known table signatures
+//
+
+///
+/// "RSD PTR " Root System Description Pointer
+///
+#define EFI_ACPI_6_0_ROOT_SYSTEM_DESCRIPTION_POINTER_SIGNATURE SIGNATURE_64('R', 'S', 'D', ' ', 'P', 'T', 'R', ' ')
+
+///
+/// "APIC" Multiple APIC Description Table
+///
+#define EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('A', 'P', 'I', 'C')
+
+///
+/// "BERT" Boot Error Record Table
+///
+#define EFI_ACPI_6_0_BOOT_ERROR_RECORD_TABLE_SIGNATURE SIGNATURE_32('B', 'E', 'R', 'T')
+
+///
+/// "BGRT" Boot Graphics Resource Table
+///
+#define EFI_ACPI_6_0_BOOT_GRAPHICS_RESOURCE_TABLE_SIGNATURE SIGNATURE_32('B', 'G', 'R', 'T')
+
+///
+/// "CPEP" Corrected Platform Error Polling Table
+///
+#define EFI_ACPI_6_0_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_SIGNATURE SIGNATURE_32('C', 'P', 'E', 'P')
+
+///
+/// "DSDT" Differentiated System Description Table
+///
+#define EFI_ACPI_6_0_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('D', 'S', 'D', 'T')
+
+///
+/// "ECDT" Embedded Controller Boot Resources Table
+///
+#define EFI_ACPI_6_0_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE_SIGNATURE SIGNATURE_32('E', 'C', 'D', 'T')
+
+///
+/// "EINJ" Error Injection Table
+///
+#define EFI_ACPI_6_0_ERROR_INJECTION_TABLE_SIGNATURE SIGNATURE_32('E', 'I', 'N', 'J')
+
+///
+/// "ERST" Error Record Serialization Table
+///
+#define EFI_ACPI_6_0_ERROR_RECORD_SERIALIZATION_TABLE_SIGNATURE SIGNATURE_32('E', 'R', 'S', 'T')
+
+///
+/// "FACP" Fixed ACPI Description Table
+///
+#define EFI_ACPI_6_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('F', 'A', 'C', 'P')
+
+///
+/// "FACS" Firmware ACPI Control Structure
+///
+#define EFI_ACPI_6_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_SIGNATURE SIGNATURE_32('F', 'A', 'C', 'S')
+
+///
+/// "FPDT" Firmware Performance Data Table
+///
+#define EFI_ACPI_6_0_FIRMWARE_PERFORMANCE_DATA_TABLE_SIGNATURE SIGNATURE_32('F', 'P', 'D', 'T')
+
+///
+/// "GTDT" Generic Timer Description Table
+///
+#define EFI_ACPI_6_0_GENERIC_TIMER_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('G', 'T', 'D', 'T')
+
+///
+/// "HEST" Hardware Error Source Table
+///
+#define EFI_ACPI_6_0_HARDWARE_ERROR_SOURCE_TABLE_SIGNATURE SIGNATURE_32('H', 'E', 'S', 'T')
+
+///
+/// "MPST" Memory Power State Table
+///
+#define EFI_ACPI_6_0_MEMORY_POWER_STATE_TABLE_SIGNATURE SIGNATURE_32('M', 'P', 'S', 'T')
+
+///
+/// "MSCT" Maximum System Characteristics Table
+///
+#define EFI_ACPI_6_0_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_SIGNATURE SIGNATURE_32('M', 'S', 'C', 'T')
+
+///
+/// "NFIT" NVDIMM Firmware Interface Table
+///
+#define EFI_ACPI_6_0_NVDIMM_FIRMWARE_INTERFACE_TABLE_STRUCTURE_SIGNATURE SIGNATURE_32('N', 'F', 'I', 'T')
+
+///
+/// "PMTT" Platform Memory Topology Table
+///
+#define EFI_ACPI_6_0_PLATFORM_MEMORY_TOPOLOGY_TABLE_SIGNATURE SIGNATURE_32('P', 'M', 'T', 'T')
+
+///
+/// "PSDT" Persistent System Description Table
+///
+#define EFI_ACPI_6_0_PERSISTENT_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('P', 'S', 'D', 'T')
+
+///
+/// "RASF" ACPI RAS Feature Table
+///
+#define EFI_ACPI_6_0_ACPI_RAS_FEATURE_TABLE_SIGNATURE SIGNATURE_32('R', 'A', 'S', 'F')
+
+///
+/// "RSDT" Root System Description Table
+///
+#define EFI_ACPI_6_0_ROOT_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('R', 'S', 'D', 'T')
+
+///
+/// "SBST" Smart Battery Specification Table
+///
+#define EFI_ACPI_6_0_SMART_BATTERY_SPECIFICATION_TABLE_SIGNATURE SIGNATURE_32('S', 'B', 'S', 'T')
+
+///
+/// "SLIT" System Locality Information Table
+///
+#define EFI_ACPI_6_0_SYSTEM_LOCALITY_INFORMATION_TABLE_SIGNATURE SIGNATURE_32('S', 'L', 'I', 'T')
+
+///
+/// "SRAT" System Resource Affinity Table
+///
+#define EFI_ACPI_6_0_SYSTEM_RESOURCE_AFFINITY_TABLE_SIGNATURE SIGNATURE_32('S', 'R', 'A', 'T')
+
+///
+/// "SSDT" Secondary System Description Table
+///
+#define EFI_ACPI_6_0_SECONDARY_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('S', 'S', 'D', 'T')
+
+///
+/// "XSDT" Extended System Description Table
+///
+#define EFI_ACPI_6_0_EXTENDED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('X', 'S', 'D', 'T')
+
+///
+/// "BOOT" MS Simple Boot Spec
+///
+#define EFI_ACPI_6_0_SIMPLE_BOOT_FLAG_TABLE_SIGNATURE SIGNATURE_32('B', 'O', 'O', 'T')
+
+///
+/// "CSRT" MS Core System Resource Table
+///
+#define EFI_ACPI_6_0_CORE_SYSTEM_RESOURCE_TABLE_SIGNATURE SIGNATURE_32('C', 'S', 'R', 'T')
+
+///
+/// "DBG2" MS Debug Port 2 Spec
+///
+#define EFI_ACPI_6_0_DEBUG_PORT_2_TABLE_SIGNATURE SIGNATURE_32('D', 'B', 'G', '2')
+
+///
+/// "DBGP" MS Debug Port Spec
+///
+#define EFI_ACPI_6_0_DEBUG_PORT_TABLE_SIGNATURE SIGNATURE_32('D', 'B', 'G', 'P')
+
+///
+/// "DMAR" DMA Remapping Table
+///
+#define EFI_ACPI_6_0_DMA_REMAPPING_TABLE_SIGNATURE SIGNATURE_32('D', 'M', 'A', 'R')
+
+///
+/// "DRTM" Dynamic Root of Trust for Measurement Table
+///
+#define EFI_ACPI_6_0_DYNAMIC_ROOT_OF_TRUST_FOR_MEASUREMENT_TABLE_SIGNATURE SIGNATURE_32('D', 'R', 'T', 'M')
+
+///
+/// "ETDT" Event Timer Description Table
+///
+#define EFI_ACPI_6_0_EVENT_TIMER_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('E', 'T', 'D', 'T')
+
+///
+/// "HPET" IA-PC High Precision Event Timer Table
+///
+#define EFI_ACPI_6_0_HIGH_PRECISION_EVENT_TIMER_TABLE_SIGNATURE SIGNATURE_32('H', 'P', 'E', 'T')
+
+///
+/// "iBFT" iSCSI Boot Firmware Table
+///
+#define EFI_ACPI_6_0_ISCSI_BOOT_FIRMWARE_TABLE_SIGNATURE SIGNATURE_32('i', 'B', 'F', 'T')
+
+///
+/// "IORT" I/O Remapping Table
+///
+#define EFI_ACPI_6_0_IO_REMAPPING_TABLE_SIGNATURE SIGNATURE_32('I', 'O', 'R', 'T')
+
+///
+/// "IVRS" I/O Virtualization Reporting Structure
+///
+#define EFI_ACPI_6_0_IO_VIRTUALIZATION_REPORTING_STRUCTURE_SIGNATURE SIGNATURE_32('I', 'V', 'R', 'S')
+
+///
+/// "LPIT" Low Power Idle Table
+///
+#define EFI_ACPI_6_0_LOW_POWER_IDLE_TABLE_STRUCTURE_SIGNATURE SIGNATURE_32('L', 'P', 'I', 'T')
+
+///
+/// "MCFG" PCI Express Memory Mapped Configuration Space Base Address Description Table
+///
+#define EFI_ACPI_6_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('M', 'C', 'F', 'G')
+
+///
+/// "MCHI" Management Controller Host Interface Table
+///
+#define EFI_ACPI_6_0_MANAGEMENT_CONTROLLER_HOST_INTERFACE_TABLE_SIGNATURE SIGNATURE_32('M', 'C', 'H', 'I')
+
+///
+/// "MSDM" MS Data Management Table
+///
+#define EFI_ACPI_6_0_DATA_MANAGEMENT_TABLE_SIGNATURE SIGNATURE_32('M', 'S', 'D', 'M')
+
+///
+/// "PCCT" Platform Communications Channel Table
+///
+#define EFI_ACPI_6_0_PLATFORM_COMMUNICATIONS_CHANNEL_TABLE_SIGNATURE SIGNATURE_32('P', 'C', 'C', 'T')
+
+///
+/// "SLIC" MS Software Licensing Table Specification
+///
+#define EFI_ACPI_6_0_SOFTWARE_LICENSING_TABLE_SIGNATURE SIGNATURE_32('S', 'L', 'I', 'C')
+
+///
+/// "SPCR" Serial Port Console Redirection Table
+///
+#define EFI_ACPI_6_0_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE SIGNATURE_32('S', 'P', 'C', 'R')
+
+///
+/// "SPMI" Server Platform Management Interface Table
+///
+#define EFI_ACPI_6_0_SERVER_PLATFORM_MANAGEMENT_INTERFACE_TABLE_SIGNATURE SIGNATURE_32('S', 'P', 'M', 'I')
+
+///
+/// "STAO" _STA Override Table
+///
+#define EFI_ACPI_6_0_STA_OVERRIDE_TABLE_SIGNATURE SIGNATURE_32('S', 'T', 'A', 'O')
+
+///
+/// "TCPA" Trusted Computing Platform Alliance Capabilities Table
+///
+#define EFI_ACPI_6_0_TRUSTED_COMPUTING_PLATFORM_ALLIANCE_CAPABILITIES_TABLE_SIGNATURE SIGNATURE_32('T', 'C', 'P', 'A')
+
+///
+/// "TPM2" Trusted Computing Platform 1 Table
+///
+#define EFI_ACPI_6_0_TRUSTED_COMPUTING_PLATFORM_2_TABLE_SIGNATURE SIGNATURE_32('T', 'P', 'M', '2')
+
+///
+/// "UEFI" UEFI ACPI Data Table
+///
+#define EFI_ACPI_6_0_UEFI_ACPI_DATA_TABLE_SIGNATURE SIGNATURE_32('U', 'E', 'F', 'I')
+
+///
+/// "WAET" Windows ACPI Emulated Devices Table
+///
+#define EFI_ACPI_6_0_WINDOWS_ACPI_EMULATED_DEVICES_TABLE_SIGNATURE SIGNATURE_32('W', 'A', 'E', 'T')
+
+///
+/// "WDAT" Watchdog Action Table
+///
+#define EFI_ACPI_6_0_WATCHDOG_ACTION_TABLE_SIGNATURE SIGNATURE_32('W', 'D', 'A', 'T')
+
+///
+/// "WDRT" Watchdog Resource Table
+///
+#define EFI_ACPI_6_0_WATCHDOG_RESOURCE_TABLE_SIGNATURE SIGNATURE_32('W', 'D', 'R', 'T')
+
+///
+/// "WPBT" MS Platform Binary Table
+///
+#define EFI_ACPI_6_0_PLATFORM_BINARY_TABLE_SIGNATURE SIGNATURE_32('W', 'P', 'B', 'T')
+
+///
+/// "XENV" Xen Project Table
+///
+#define EFI_ACPI_6_0_XEN_PROJECT_TABLE_SIGNATURE SIGNATURE_32('X', 'E', 'N', 'V')
+
+#pragma pack()
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/Acpi61.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/Acpi61.h
new file mode 100644
index 0000000000..94cfe8b08a
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/Acpi61.h
@@ -0,0 +1,2430 @@
+/** @file
+ ACPI 6.1 definitions from the ACPI Specification Revision 6.1 January, 2016.
+
+ Copyright (c) 2016 - 2022, Intel Corporation. All rights reserved.
+ (C) Copyright 2016 Hewlett Packard Enterprise Development LP
+ Copyright (c) 2020, ARM Ltd. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _ACPI_6_1_H_
+#define _ACPI_6_1_H_
+
+#include
+
+//
+// Ensure proper structure formats
+//
+#pragma pack(1)
+
+///
+/// ACPI 6.1 Generic Address Space definition
+///
+typedef struct {
+ UINT8 AddressSpaceId;
+ UINT8 RegisterBitWidth;
+ UINT8 RegisterBitOffset;
+ UINT8 AccessSize;
+ UINT64 Address;
+} EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE;
+
+//
+// Generic Address Space Address IDs
+//
+#define EFI_ACPI_6_1_SYSTEM_MEMORY 0
+#define EFI_ACPI_6_1_SYSTEM_IO 1
+#define EFI_ACPI_6_1_PCI_CONFIGURATION_SPACE 2
+#define EFI_ACPI_6_1_EMBEDDED_CONTROLLER 3
+#define EFI_ACPI_6_1_SMBUS 4
+#define EFI_ACPI_6_1_PLATFORM_COMMUNICATION_CHANNEL 0x0A
+#define EFI_ACPI_6_1_FUNCTIONAL_FIXED_HARDWARE 0x7F
+
+//
+// Generic Address Space Access Sizes
+//
+#define EFI_ACPI_6_1_UNDEFINED 0
+#define EFI_ACPI_6_1_BYTE 1
+#define EFI_ACPI_6_1_WORD 2
+#define EFI_ACPI_6_1_DWORD 3
+#define EFI_ACPI_6_1_QWORD 4
+
+//
+// ACPI 6.1 table structures
+//
+
+///
+/// Root System Description Pointer Structure
+///
+typedef struct {
+ UINT64 Signature;
+ UINT8 Checksum;
+ UINT8 OemId[6];
+ UINT8 Revision;
+ UINT32 RsdtAddress;
+ UINT32 Length;
+ UINT64 XsdtAddress;
+ UINT8 ExtendedChecksum;
+ UINT8 Reserved[3];
+} EFI_ACPI_6_1_ROOT_SYSTEM_DESCRIPTION_POINTER;
+
+///
+/// RSD_PTR Revision (as defined in ACPI 6.1 spec.)
+///
+#define EFI_ACPI_6_1_ROOT_SYSTEM_DESCRIPTION_POINTER_REVISION 0x02 ///< ACPISpec (Revision 6.1) says current value is 2
+
+///
+/// Common table header, this prefaces all ACPI tables, including FACS, but
+/// excluding the RSD PTR structure
+///
+typedef struct {
+ UINT32 Signature;
+ UINT32 Length;
+} EFI_ACPI_6_1_COMMON_HEADER;
+
+//
+// Root System Description Table
+// No definition needed as it is a common description table header, the same with
+// EFI_ACPI_DESCRIPTION_HEADER, followed by a variable number of UINT32 table pointers.
+//
+
+///
+/// RSDT Revision (as defined in ACPI 6.1 spec.)
+///
+#define EFI_ACPI_6_1_ROOT_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01
+
+//
+// Extended System Description Table
+// No definition needed as it is a common description table header, the same with
+// EFI_ACPI_DESCRIPTION_HEADER, followed by a variable number of UINT64 table pointers.
+//
+
+///
+/// XSDT Revision (as defined in ACPI 6.1 spec.)
+///
+#define EFI_ACPI_6_1_EXTENDED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01
+
+///
+/// Fixed ACPI Description Table Structure (FADT)
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 FirmwareCtrl;
+ UINT32 Dsdt;
+ UINT8 Reserved0;
+ UINT8 PreferredPmProfile;
+ UINT16 SciInt;
+ UINT32 SmiCmd;
+ UINT8 AcpiEnable;
+ UINT8 AcpiDisable;
+ UINT8 S4BiosReq;
+ UINT8 PstateCnt;
+ UINT32 Pm1aEvtBlk;
+ UINT32 Pm1bEvtBlk;
+ UINT32 Pm1aCntBlk;
+ UINT32 Pm1bCntBlk;
+ UINT32 Pm2CntBlk;
+ UINT32 PmTmrBlk;
+ UINT32 Gpe0Blk;
+ UINT32 Gpe1Blk;
+ UINT8 Pm1EvtLen;
+ UINT8 Pm1CntLen;
+ UINT8 Pm2CntLen;
+ UINT8 PmTmrLen;
+ UINT8 Gpe0BlkLen;
+ UINT8 Gpe1BlkLen;
+ UINT8 Gpe1Base;
+ UINT8 CstCnt;
+ UINT16 PLvl2Lat;
+ UINT16 PLvl3Lat;
+ UINT16 FlushSize;
+ UINT16 FlushStride;
+ UINT8 DutyOffset;
+ UINT8 DutyWidth;
+ UINT8 DayAlrm;
+ UINT8 MonAlrm;
+ UINT8 Century;
+ UINT16 IaPcBootArch;
+ UINT8 Reserved1;
+ UINT32 Flags;
+ EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE ResetReg;
+ UINT8 ResetValue;
+ UINT16 ArmBootArch;
+ UINT8 MinorVersion;
+ UINT64 XFirmwareCtrl;
+ UINT64 XDsdt;
+ EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE XPm1aEvtBlk;
+ EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE XPm1bEvtBlk;
+ EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE XPm1aCntBlk;
+ EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE XPm1bCntBlk;
+ EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE XPm2CntBlk;
+ EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE XPmTmrBlk;
+ EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE XGpe0Blk;
+ EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE XGpe1Blk;
+ EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE SleepControlReg;
+ EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE SleepStatusReg;
+ UINT64 HypervisorVendorIdentity;
+} EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE;
+
+///
+/// FADT Version (as defined in ACPI 6.1 spec.)
+///
+#define EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE_REVISION 0x06
+#define EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE_MINOR_REVISION 0x01
+
+//
+// Fixed ACPI Description Table Preferred Power Management Profile
+//
+#define EFI_ACPI_6_1_PM_PROFILE_UNSPECIFIED 0
+#define EFI_ACPI_6_1_PM_PROFILE_DESKTOP 1
+#define EFI_ACPI_6_1_PM_PROFILE_MOBILE 2
+#define EFI_ACPI_6_1_PM_PROFILE_WORKSTATION 3
+#define EFI_ACPI_6_1_PM_PROFILE_ENTERPRISE_SERVER 4
+#define EFI_ACPI_6_1_PM_PROFILE_SOHO_SERVER 5
+#define EFI_ACPI_6_1_PM_PROFILE_APPLIANCE_PC 6
+#define EFI_ACPI_6_1_PM_PROFILE_PERFORMANCE_SERVER 7
+#define EFI_ACPI_6_1_PM_PROFILE_TABLET 8
+
+//
+// Fixed ACPI Description Table Boot Architecture Flags
+// All other bits are reserved and must be set to 0.
+//
+#define EFI_ACPI_6_1_LEGACY_DEVICES BIT0
+#define EFI_ACPI_6_1_8042 BIT1
+#define EFI_ACPI_6_1_VGA_NOT_PRESENT BIT2
+#define EFI_ACPI_6_1_MSI_NOT_SUPPORTED BIT3
+#define EFI_ACPI_6_1_PCIE_ASPM_CONTROLS BIT4
+#define EFI_ACPI_6_1_CMOS_RTC_NOT_PRESENT BIT5
+
+//
+// Fixed ACPI Description Table Arm Boot Architecture Flags
+// All other bits are reserved and must be set to 0.
+//
+#define EFI_ACPI_6_1_ARM_PSCI_COMPLIANT BIT0
+#define EFI_ACPI_6_1_ARM_PSCI_USE_HVC BIT1
+
+//
+// Fixed ACPI Description Table Fixed Feature Flags
+// All other bits are reserved and must be set to 0.
+//
+#define EFI_ACPI_6_1_WBINVD BIT0
+#define EFI_ACPI_6_1_WBINVD_FLUSH BIT1
+#define EFI_ACPI_6_1_PROC_C1 BIT2
+#define EFI_ACPI_6_1_P_LVL2_UP BIT3
+#define EFI_ACPI_6_1_PWR_BUTTON BIT4
+#define EFI_ACPI_6_1_SLP_BUTTON BIT5
+#define EFI_ACPI_6_1_FIX_RTC BIT6
+#define EFI_ACPI_6_1_RTC_S4 BIT7
+#define EFI_ACPI_6_1_TMR_VAL_EXT BIT8
+#define EFI_ACPI_6_1_DCK_CAP BIT9
+#define EFI_ACPI_6_1_RESET_REG_SUP BIT10
+#define EFI_ACPI_6_1_SEALED_CASE BIT11
+#define EFI_ACPI_6_1_HEADLESS BIT12
+#define EFI_ACPI_6_1_CPU_SW_SLP BIT13
+#define EFI_ACPI_6_1_PCI_EXP_WAK BIT14
+#define EFI_ACPI_6_1_USE_PLATFORM_CLOCK BIT15
+#define EFI_ACPI_6_1_S4_RTC_STS_VALID BIT16
+#define EFI_ACPI_6_1_REMOTE_POWER_ON_CAPABLE BIT17
+#define EFI_ACPI_6_1_FORCE_APIC_CLUSTER_MODEL BIT18
+#define EFI_ACPI_6_1_FORCE_APIC_PHYSICAL_DESTINATION_MODE BIT19
+#define EFI_ACPI_6_1_HW_REDUCED_ACPI BIT20
+#define EFI_ACPI_6_1_LOW_POWER_S0_IDLE_CAPABLE BIT21
+
+///
+/// Firmware ACPI Control Structure
+///
+typedef struct {
+ UINT32 Signature;
+ UINT32 Length;
+ UINT32 HardwareSignature;
+ UINT32 FirmwareWakingVector;
+ UINT32 GlobalLock;
+ UINT32 Flags;
+ UINT64 XFirmwareWakingVector;
+ UINT8 Version;
+ UINT8 Reserved0[3];
+ UINT32 OspmFlags;
+ UINT8 Reserved1[24];
+} EFI_ACPI_6_1_FIRMWARE_ACPI_CONTROL_STRUCTURE;
+
+///
+/// FACS Version (as defined in ACPI 6.1 spec.)
+///
+#define EFI_ACPI_6_1_FIRMWARE_ACPI_CONTROL_STRUCTURE_VERSION 0x02
+
+///
+/// Firmware Control Structure Feature Flags
+/// All other bits are reserved and must be set to 0.
+///
+#define EFI_ACPI_6_1_S4BIOS_F BIT0
+#define EFI_ACPI_6_1_64BIT_WAKE_SUPPORTED_F BIT1
+
+///
+/// OSPM Enabled Firmware Control Structure Flags
+/// All other bits are reserved and must be set to 0.
+///
+#define EFI_ACPI_6_1_OSPM_64BIT_WAKE_F BIT0
+
+//
+// Differentiated System Description Table,
+// Secondary System Description Table
+// and Persistent System Description Table,
+// no definition needed as they are common description table header, the same with
+// EFI_ACPI_DESCRIPTION_HEADER, followed by a definition block.
+//
+#define EFI_ACPI_6_1_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x02
+#define EFI_ACPI_6_1_SECONDARY_SYSTEM_DESCRIPTION_TABLE_REVISION 0x02
+
+///
+/// Multiple APIC Description Table header definition. The rest of the table
+/// must be defined in a platform specific manner.
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 LocalApicAddress;
+ UINT32 Flags;
+} EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER;
+
+///
+/// MADT Revision (as defined in ACPI 6.1 spec.)
+///
+#define EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION 0x04
+
+///
+/// Multiple APIC Flags
+/// All other bits are reserved and must be set to 0.
+///
+#define EFI_ACPI_6_1_PCAT_COMPAT BIT0
+
+//
+// Multiple APIC Description Table APIC structure types
+// All other values between 0x0D and 0x7F are reserved and
+// will be ignored by OSPM. 0x80 ~ 0xFF are reserved for OEM.
+//
+#define EFI_ACPI_6_1_PROCESSOR_LOCAL_APIC 0x00
+#define EFI_ACPI_6_1_IO_APIC 0x01
+#define EFI_ACPI_6_1_INTERRUPT_SOURCE_OVERRIDE 0x02
+#define EFI_ACPI_6_1_NON_MASKABLE_INTERRUPT_SOURCE 0x03
+#define EFI_ACPI_6_1_LOCAL_APIC_NMI 0x04
+#define EFI_ACPI_6_1_LOCAL_APIC_ADDRESS_OVERRIDE 0x05
+#define EFI_ACPI_6_1_IO_SAPIC 0x06
+#define EFI_ACPI_6_1_LOCAL_SAPIC 0x07
+#define EFI_ACPI_6_1_PLATFORM_INTERRUPT_SOURCES 0x08
+#define EFI_ACPI_6_1_PROCESSOR_LOCAL_X2APIC 0x09
+#define EFI_ACPI_6_1_LOCAL_X2APIC_NMI 0x0A
+#define EFI_ACPI_6_1_GIC 0x0B
+#define EFI_ACPI_6_1_GICD 0x0C
+#define EFI_ACPI_6_1_GIC_MSI_FRAME 0x0D
+#define EFI_ACPI_6_1_GICR 0x0E
+#define EFI_ACPI_6_1_GIC_ITS 0x0F
+
+//
+// APIC Structure Definitions
+//
+
+///
+/// Processor Local APIC Structure Definition
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 AcpiProcessorUid;
+ UINT8 ApicId;
+ UINT32 Flags;
+} EFI_ACPI_6_1_PROCESSOR_LOCAL_APIC_STRUCTURE;
+
+///
+/// Local APIC Flags. All other bits are reserved and must be 0.
+///
+#define EFI_ACPI_6_1_LOCAL_APIC_ENABLED BIT0
+
+///
+/// IO APIC Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 IoApicId;
+ UINT8 Reserved;
+ UINT32 IoApicAddress;
+ UINT32 GlobalSystemInterruptBase;
+} EFI_ACPI_6_1_IO_APIC_STRUCTURE;
+
+///
+/// Interrupt Source Override Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 Bus;
+ UINT8 Source;
+ UINT32 GlobalSystemInterrupt;
+ UINT16 Flags;
+} EFI_ACPI_6_1_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE;
+
+///
+/// Platform Interrupt Sources Structure Definition
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Flags;
+ UINT8 InterruptType;
+ UINT8 ProcessorId;
+ UINT8 ProcessorEid;
+ UINT8 IoSapicVector;
+ UINT32 GlobalSystemInterrupt;
+ UINT32 PlatformInterruptSourceFlags;
+ UINT8 CpeiProcessorOverride;
+ UINT8 Reserved[31];
+} EFI_ACPI_6_1_PLATFORM_INTERRUPT_APIC_STRUCTURE;
+
+//
+// MPS INTI flags.
+// All other bits are reserved and must be set to 0.
+//
+#define EFI_ACPI_6_1_POLARITY (3 << 0)
+#define EFI_ACPI_6_1_TRIGGER_MODE (3 << 2)
+
+///
+/// Non-Maskable Interrupt Source Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Flags;
+ UINT32 GlobalSystemInterrupt;
+} EFI_ACPI_6_1_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE;
+
+///
+/// Local APIC NMI Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 AcpiProcessorUid;
+ UINT16 Flags;
+ UINT8 LocalApicLint;
+} EFI_ACPI_6_1_LOCAL_APIC_NMI_STRUCTURE;
+
+///
+/// Local APIC Address Override Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Reserved;
+ UINT64 LocalApicAddress;
+} EFI_ACPI_6_1_LOCAL_APIC_ADDRESS_OVERRIDE_STRUCTURE;
+
+///
+/// IO SAPIC Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 IoApicId;
+ UINT8 Reserved;
+ UINT32 GlobalSystemInterruptBase;
+ UINT64 IoSapicAddress;
+} EFI_ACPI_6_1_IO_SAPIC_STRUCTURE;
+
+///
+/// Local SAPIC Structure
+/// This struct followed by a null-terminated ASCII string - ACPI Processor UID String
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 AcpiProcessorId;
+ UINT8 LocalSapicId;
+ UINT8 LocalSapicEid;
+ UINT8 Reserved[3];
+ UINT32 Flags;
+ UINT32 ACPIProcessorUIDValue;
+} EFI_ACPI_6_1_PROCESSOR_LOCAL_SAPIC_STRUCTURE;
+
+///
+/// Platform Interrupt Sources Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Flags;
+ UINT8 InterruptType;
+ UINT8 ProcessorId;
+ UINT8 ProcessorEid;
+ UINT8 IoSapicVector;
+ UINT32 GlobalSystemInterrupt;
+ UINT32 PlatformInterruptSourceFlags;
+} EFI_ACPI_6_1_PLATFORM_INTERRUPT_SOURCES_STRUCTURE;
+
+///
+/// Platform Interrupt Source Flags.
+/// All other bits are reserved and must be set to 0.
+///
+#define EFI_ACPI_6_1_CPEI_PROCESSOR_OVERRIDE BIT0
+
+///
+/// Processor Local x2APIC Structure Definition
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 Reserved[2];
+ UINT32 X2ApicId;
+ UINT32 Flags;
+ UINT32 AcpiProcessorUid;
+} EFI_ACPI_6_1_PROCESSOR_LOCAL_X2APIC_STRUCTURE;
+
+///
+/// Local x2APIC NMI Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Flags;
+ UINT32 AcpiProcessorUid;
+ UINT8 LocalX2ApicLint;
+ UINT8 Reserved[3];
+} EFI_ACPI_6_1_LOCAL_X2APIC_NMI_STRUCTURE;
+
+///
+/// GIC Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Reserved;
+ UINT32 CPUInterfaceNumber;
+ UINT32 AcpiProcessorUid;
+ UINT32 Flags;
+ UINT32 ParkingProtocolVersion;
+ UINT32 PerformanceInterruptGsiv;
+ UINT64 ParkedAddress;
+ UINT64 PhysicalBaseAddress;
+ UINT64 GICV;
+ UINT64 GICH;
+ UINT32 VGICMaintenanceInterrupt;
+ UINT64 GICRBaseAddress;
+ UINT64 MPIDR;
+ UINT8 ProcessorPowerEfficiencyClass;
+ UINT8 Reserved2[3];
+} EFI_ACPI_6_1_GIC_STRUCTURE;
+
+///
+/// GIC Flags. All other bits are reserved and must be 0.
+///
+#define EFI_ACPI_6_1_GIC_ENABLED BIT0
+#define EFI_ACPI_6_1_PERFORMANCE_INTERRUPT_MODEL BIT1
+#define EFI_ACPI_6_1_VGIC_MAINTENANCE_INTERRUPT_MODE_FLAGS BIT2
+
+///
+/// GIC Distributor Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Reserved1;
+ UINT32 GicId;
+ UINT64 PhysicalBaseAddress;
+ UINT32 SystemVectorBase;
+ UINT8 GicVersion;
+ UINT8 Reserved2[3];
+} EFI_ACPI_6_1_GIC_DISTRIBUTOR_STRUCTURE;
+
+///
+/// GIC Version
+///
+#define EFI_ACPI_6_1_GIC_V1 0x01
+#define EFI_ACPI_6_1_GIC_V2 0x02
+#define EFI_ACPI_6_1_GIC_V3 0x03
+#define EFI_ACPI_6_1_GIC_V4 0x04
+
+///
+/// GIC MSI Frame Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Reserved1;
+ UINT32 GicMsiFrameId;
+ UINT64 PhysicalBaseAddress;
+ UINT32 Flags;
+ UINT16 SPICount;
+ UINT16 SPIBase;
+} EFI_ACPI_6_1_GIC_MSI_FRAME_STRUCTURE;
+
+///
+/// GIC MSI Frame Flags. All other bits are reserved and must be 0.
+///
+#define EFI_ACPI_6_1_SPI_COUNT_BASE_SELECT BIT0
+
+///
+/// GICR Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Reserved;
+ UINT64 DiscoveryRangeBaseAddress;
+ UINT32 DiscoveryRangeLength;
+} EFI_ACPI_6_1_GICR_STRUCTURE;
+
+///
+/// GIC Interrupt Translation Service Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Reserved;
+ UINT32 GicItsId;
+ UINT64 PhysicalBaseAddress;
+ UINT32 Reserved2;
+} EFI_ACPI_6_1_GIC_ITS_STRUCTURE;
+
+///
+/// Smart Battery Description Table (SBST)
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 WarningEnergyLevel;
+ UINT32 LowEnergyLevel;
+ UINT32 CriticalEnergyLevel;
+} EFI_ACPI_6_1_SMART_BATTERY_DESCRIPTION_TABLE;
+
+///
+/// SBST Version (as defined in ACPI 6.1 spec.)
+///
+#define EFI_ACPI_6_1_SMART_BATTERY_DESCRIPTION_TABLE_REVISION 0x01
+
+///
+/// Embedded Controller Boot Resources Table (ECDT)
+/// The table is followed by a null terminated ASCII string that contains
+/// a fully qualified reference to the name space object.
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE EcControl;
+ EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE EcData;
+ UINT32 Uid;
+ UINT8 GpeBit;
+} EFI_ACPI_6_1_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE;
+
+///
+/// ECDT Version (as defined in ACPI 6.1 spec.)
+///
+#define EFI_ACPI_6_1_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE_REVISION 0x01
+
+///
+/// System Resource Affinity Table (SRAT). The rest of the table
+/// must be defined in a platform specific manner.
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 Reserved1; ///< Must be set to 1
+ UINT64 Reserved2;
+} EFI_ACPI_6_1_SYSTEM_RESOURCE_AFFINITY_TABLE_HEADER;
+
+///
+/// SRAT Version (as defined in ACPI 6.1 spec.)
+///
+#define EFI_ACPI_6_1_SYSTEM_RESOURCE_AFFINITY_TABLE_REVISION 0x03
+
+//
+// SRAT structure types.
+// All other values between 0x04 an 0xFF are reserved and
+// will be ignored by OSPM.
+//
+#define EFI_ACPI_6_1_PROCESSOR_LOCAL_APIC_SAPIC_AFFINITY 0x00
+#define EFI_ACPI_6_1_MEMORY_AFFINITY 0x01
+#define EFI_ACPI_6_1_PROCESSOR_LOCAL_X2APIC_AFFINITY 0x02
+#define EFI_ACPI_6_1_GICC_AFFINITY 0x03
+
+///
+/// Processor Local APIC/SAPIC Affinity Structure Definition
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 ProximityDomain7To0;
+ UINT8 ApicId;
+ UINT32 Flags;
+ UINT8 LocalSapicEid;
+ UINT8 ProximityDomain31To8[3];
+ UINT32 ClockDomain;
+} EFI_ACPI_6_1_PROCESSOR_LOCAL_APIC_SAPIC_AFFINITY_STRUCTURE;
+
+///
+/// Local APIC/SAPIC Flags. All other bits are reserved and must be 0.
+///
+#define EFI_ACPI_6_1_PROCESSOR_LOCAL_APIC_SAPIC_ENABLED (1 << 0)
+
+///
+/// Memory Affinity Structure Definition
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT32 ProximityDomain;
+ UINT16 Reserved1;
+ UINT32 AddressBaseLow;
+ UINT32 AddressBaseHigh;
+ UINT32 LengthLow;
+ UINT32 LengthHigh;
+ UINT32 Reserved2;
+ UINT32 Flags;
+ UINT64 Reserved3;
+} EFI_ACPI_6_1_MEMORY_AFFINITY_STRUCTURE;
+
+//
+// Memory Flags. All other bits are reserved and must be 0.
+//
+#define EFI_ACPI_6_1_MEMORY_ENABLED (1 << 0)
+#define EFI_ACPI_6_1_MEMORY_HOT_PLUGGABLE (1 << 1)
+#define EFI_ACPI_6_1_MEMORY_NONVOLATILE (1 << 2)
+
+///
+/// Processor Local x2APIC Affinity Structure Definition
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 Reserved1[2];
+ UINT32 ProximityDomain;
+ UINT32 X2ApicId;
+ UINT32 Flags;
+ UINT32 ClockDomain;
+ UINT8 Reserved2[4];
+} EFI_ACPI_6_1_PROCESSOR_LOCAL_X2APIC_AFFINITY_STRUCTURE;
+
+///
+/// GICC Affinity Structure Definition
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT32 ProximityDomain;
+ UINT32 AcpiProcessorUid;
+ UINT32 Flags;
+ UINT32 ClockDomain;
+} EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE;
+
+///
+/// GICC Flags. All other bits are reserved and must be 0.
+///
+#define EFI_ACPI_6_1_GICC_ENABLED (1 << 0)
+
+///
+/// System Locality Distance Information Table (SLIT).
+/// The rest of the table is a matrix.
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT64 NumberOfSystemLocalities;
+} EFI_ACPI_6_1_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_HEADER;
+
+///
+/// SLIT Version (as defined in ACPI 6.1 spec.)
+///
+#define EFI_ACPI_6_1_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_REVISION 0x01
+
+///
+/// Corrected Platform Error Polling Table (CPEP)
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT8 Reserved[8];
+} EFI_ACPI_6_1_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_HEADER;
+
+///
+/// CPEP Version (as defined in ACPI 6.1 spec.)
+///
+#define EFI_ACPI_6_1_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_REVISION 0x01
+
+//
+// CPEP processor structure types.
+//
+#define EFI_ACPI_6_1_CPEP_PROCESSOR_APIC_SAPIC 0x00
+
+///
+/// Corrected Platform Error Polling Processor Structure Definition
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 ProcessorId;
+ UINT8 ProcessorEid;
+ UINT32 PollingInterval;
+} EFI_ACPI_6_1_CPEP_PROCESSOR_APIC_SAPIC_STRUCTURE;
+
+///
+/// Maximum System Characteristics Table (MSCT)
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 OffsetProxDomInfo;
+ UINT32 MaximumNumberOfProximityDomains;
+ UINT32 MaximumNumberOfClockDomains;
+ UINT64 MaximumPhysicalAddress;
+} EFI_ACPI_6_1_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_HEADER;
+
+///
+/// MSCT Version (as defined in ACPI 6.1 spec.)
+///
+#define EFI_ACPI_6_1_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_REVISION 0x01
+
+///
+/// Maximum Proximity Domain Information Structure Definition
+///
+typedef struct {
+ UINT8 Revision;
+ UINT8 Length;
+ UINT32 ProximityDomainRangeLow;
+ UINT32 ProximityDomainRangeHigh;
+ UINT32 MaximumProcessorCapacity;
+ UINT64 MaximumMemoryCapacity;
+} EFI_ACPI_6_1_MAXIMUM_PROXIMITY_DOMAIN_INFORMATION_STRUCTURE;
+
+///
+/// ACPI RAS Feature Table definition.
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT8 PlatformCommunicationChannelIdentifier[12];
+} EFI_ACPI_6_1_RAS_FEATURE_TABLE;
+
+///
+/// RASF Version (as defined in ACPI 6.1 spec.)
+///
+#define EFI_ACPI_6_1_RAS_FEATURE_TABLE_REVISION 0x01
+
+///
+/// ACPI RASF Platform Communication Channel Shared Memory Region definition.
+///
+typedef struct {
+ UINT32 Signature;
+ UINT16 Command;
+ UINT16 Status;
+ UINT16 Version;
+ UINT8 RASCapabilities[16];
+ UINT8 SetRASCapabilities[16];
+ UINT16 NumberOfRASFParameterBlocks;
+ UINT32 SetRASCapabilitiesStatus;
+} EFI_ACPI_6_1_RASF_PLATFORM_COMMUNICATION_CHANNEL_SHARED_MEMORY_REGION;
+
+///
+/// ACPI RASF PCC command code
+///
+#define EFI_ACPI_6_1_RASF_PCC_COMMAND_CODE_EXECUTE_RASF_COMMAND 0x01
+
+///
+/// ACPI RASF Platform RAS Capabilities
+///
+#define EFI_ACPI_6_1_RASF_PLATFORM_RAS_CAPABILITY_HARDWARE_BASED_PATROL_SCRUB_SUPPOTED 0x01
+#define EFI_ACPI_6_1_RASF_PLATFORM_RAS_CAPABILITY_HARDWARE_BASED_PATROL_SCRUB_SUPPOTED_AND_EXPOSED_TO_SOFTWARE 0x02
+
+///
+/// ACPI RASF Parameter Block structure for PATROL_SCRUB
+///
+typedef struct {
+ UINT16 Type;
+ UINT16 Version;
+ UINT16 Length;
+ UINT16 PatrolScrubCommand;
+ UINT64 RequestedAddressRange[2];
+ UINT64 ActualAddressRange[2];
+ UINT16 Flags;
+ UINT8 RequestedSpeed;
+} EFI_ACPI_6_1_RASF_PATROL_SCRUB_PLATFORM_BLOCK_STRUCTURE;
+
+///
+/// ACPI RASF Patrol Scrub command
+///
+#define EFI_ACPI_6_1_RASF_PATROL_SCRUB_COMMAND_GET_PATROL_PARAMETERS 0x01
+#define EFI_ACPI_6_1_RASF_PATROL_SCRUB_COMMAND_START_PATROL_SCRUBBER 0x02
+#define EFI_ACPI_6_1_RASF_PATROL_SCRUB_COMMAND_STOP_PATROL_SCRUBBER 0x03
+
+///
+/// Memory Power State Table definition.
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT8 PlatformCommunicationChannelIdentifier;
+ UINT8 Reserved[3];
+ // Memory Power Node Structure
+ // Memory Power State Characteristics
+} EFI_ACPI_6_1_MEMORY_POWER_STATUS_TABLE;
+
+///
+/// MPST Version (as defined in ACPI 6.1 spec.)
+///
+#define EFI_ACPI_6_1_MEMORY_POWER_STATE_TABLE_REVISION 0x01
+
+///
+/// MPST Platform Communication Channel Shared Memory Region definition.
+///
+typedef struct {
+ UINT32 Signature;
+ UINT16 Command;
+ UINT16 Status;
+ UINT32 MemoryPowerCommandRegister;
+ UINT32 MemoryPowerStatusRegister;
+ UINT32 PowerStateId;
+ UINT32 MemoryPowerNodeId;
+ UINT64 MemoryEnergyConsumed;
+ UINT64 ExpectedAveragePowerComsuned;
+} EFI_ACPI_6_1_MPST_PLATFORM_COMMUNICATION_CHANNEL_SHARED_MEMORY_REGION;
+
+///
+/// ACPI MPST PCC command code
+///
+#define EFI_ACPI_6_1_MPST_PCC_COMMAND_CODE_EXECUTE_MPST_COMMAND 0x03
+
+///
+/// ACPI MPST Memory Power command
+///
+#define EFI_ACPI_6_1_MPST_MEMORY_POWER_COMMAND_GET_MEMORY_POWER_STATE 0x01
+#define EFI_ACPI_6_1_MPST_MEMORY_POWER_COMMAND_SET_MEMORY_POWER_STATE 0x02
+#define EFI_ACPI_6_1_MPST_MEMORY_POWER_COMMAND_GET_AVERAGE_POWER_CONSUMED 0x03
+#define EFI_ACPI_6_1_MPST_MEMORY_POWER_COMMAND_GET_MEMORY_ENERGY_CONSUMED 0x04
+
+///
+/// MPST Memory Power Node Table
+///
+typedef struct {
+ UINT8 PowerStateValue;
+ UINT8 PowerStateInformationIndex;
+} EFI_ACPI_6_1_MPST_MEMORY_POWER_STATE;
+
+typedef struct {
+ UINT8 Flag;
+ UINT8 Reserved;
+ UINT16 MemoryPowerNodeId;
+ UINT32 Length;
+ UINT64 AddressBase;
+ UINT64 AddressLength;
+ UINT32 NumberOfPowerStates;
+ UINT32 NumberOfPhysicalComponents;
+ // EFI_ACPI_6_1_MPST_MEMORY_POWER_STATE MemoryPowerState[NumberOfPowerStates];
+ // UINT16 PhysicalComponentIdentifier[NumberOfPhysicalComponents];
+} EFI_ACPI_6_1_MPST_MEMORY_POWER_STRUCTURE;
+
+#define EFI_ACPI_6_1_MPST_MEMORY_POWER_STRUCTURE_FLAG_ENABLE 0x01
+#define EFI_ACPI_6_1_MPST_MEMORY_POWER_STRUCTURE_FLAG_POWER_MANAGED 0x02
+#define EFI_ACPI_6_1_MPST_MEMORY_POWER_STRUCTURE_FLAG_HOT_PLUGGABLE 0x04
+
+typedef struct {
+ UINT16 MemoryPowerNodeCount;
+ UINT8 Reserved[2];
+} EFI_ACPI_6_1_MPST_MEMORY_POWER_NODE_TABLE;
+
+///
+/// MPST Memory Power State Characteristics Table
+///
+typedef struct {
+ UINT8 PowerStateStructureID;
+ UINT8 Flag;
+ UINT16 Reserved;
+ UINT32 AveragePowerConsumedInMPS0;
+ UINT32 RelativePowerSavingToMPS0;
+ UINT64 ExitLatencyToMPS0;
+} EFI_ACPI_6_1_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE;
+
+#define EFI_ACPI_6_1_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_MEMORY_CONTENT_PRESERVED 0x01
+#define EFI_ACPI_6_1_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_AUTONOMOUS_MEMORY_POWER_STATE_ENTRY 0x02
+#define EFI_ACPI_6_1_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_AUTONOMOUS_MEMORY_POWER_STATE_EXIT 0x04
+
+typedef struct {
+ UINT16 MemoryPowerStateCharacteristicsCount;
+ UINT8 Reserved[2];
+} EFI_ACPI_6_1_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_TABLE;
+
+///
+/// Memory Topology Table definition.
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 Reserved;
+} EFI_ACPI_6_1_MEMORY_TOPOLOGY_TABLE;
+
+///
+/// PMTT Version (as defined in ACPI 6.1 spec.)
+///
+#define EFI_ACPI_6_1_MEMORY_TOPOLOGY_TABLE_REVISION 0x01
+
+///
+/// Common Memory Aggregator Device Structure.
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Reserved;
+ UINT16 Length;
+ UINT16 Flags;
+ UINT16 Reserved1;
+} EFI_ACPI_6_1_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE;
+
+///
+/// Memory Aggregator Device Type
+///
+#define EFI_ACPI_6_1_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_SOCKET 0x0
+#define EFI_ACPI_6_1_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_MEMORY_CONTROLLER 0x1
+#define EFI_ACPI_6_1_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_DIMM 0x2
+
+///
+/// Socket Memory Aggregator Device Structure.
+///
+typedef struct {
+ EFI_ACPI_6_1_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE Header;
+ UINT16 SocketIdentifier;
+ UINT16 Reserved;
+ // EFI_ACPI_6_1_PMMT_MEMORY_CONTROLLER_MEMORY_AGGREGATOR_DEVICE_STRUCTURE MemoryController[];
+} EFI_ACPI_6_1_PMMT_SOCKET_MEMORY_AGGREGATOR_DEVICE_STRUCTURE;
+
+///
+/// MemoryController Memory Aggregator Device Structure.
+///
+typedef struct {
+ EFI_ACPI_6_1_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE Header;
+ UINT32 ReadLatency;
+ UINT32 WriteLatency;
+ UINT32 ReadBandwidth;
+ UINT32 WriteBandwidth;
+ UINT16 OptimalAccessUnit;
+ UINT16 OptimalAccessAlignment;
+ UINT16 Reserved;
+ UINT16 NumberOfProximityDomains;
+ // UINT32 ProximityDomain[NumberOfProximityDomains];
+ // EFI_ACPI_6_1_PMMT_DIMM_MEMORY_AGGREGATOR_DEVICE_STRUCTURE PhysicalComponent[];
+} EFI_ACPI_6_1_PMMT_MEMORY_CONTROLLER_MEMORY_AGGREGATOR_DEVICE_STRUCTURE;
+
+///
+/// DIMM Memory Aggregator Device Structure.
+///
+typedef struct {
+ EFI_ACPI_6_1_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE Header;
+ UINT16 PhysicalComponentIdentifier;
+ UINT16 Reserved;
+ UINT32 SizeOfDimm;
+ UINT32 SmbiosHandle;
+} EFI_ACPI_6_1_PMMT_DIMM_MEMORY_AGGREGATOR_DEVICE_STRUCTURE;
+
+///
+/// Boot Graphics Resource Table definition.
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ ///
+ /// 2-bytes (16 bit) version ID. This value must be 1.
+ ///
+ UINT16 Version;
+ ///
+ /// 1-byte status field indicating current status about the table.
+ /// Bits[7:1] = Reserved (must be zero)
+ /// Bit [0] = Valid. A one indicates the boot image graphic is valid.
+ ///
+ UINT8 Status;
+ ///
+ /// 1-byte enumerated type field indicating format of the image.
+ /// 0 = Bitmap
+ /// 1 - 255 Reserved (for future use)
+ ///
+ UINT8 ImageType;
+ ///
+ /// 8-byte (64 bit) physical address pointing to the firmware's in-memory copy
+ /// of the image bitmap.
+ ///
+ UINT64 ImageAddress;
+ ///
+ /// A 4-byte (32-bit) unsigned long describing the display X-offset of the boot image.
+ /// (X, Y) display offset of the top left corner of the boot image.
+ /// The top left corner of the display is at offset (0, 0).
+ ///
+ UINT32 ImageOffsetX;
+ ///
+ /// A 4-byte (32-bit) unsigned long describing the display Y-offset of the boot image.
+ /// (X, Y) display offset of the top left corner of the boot image.
+ /// The top left corner of the display is at offset (0, 0).
+ ///
+ UINT32 ImageOffsetY;
+} EFI_ACPI_6_1_BOOT_GRAPHICS_RESOURCE_TABLE;
+
+///
+/// BGRT Revision
+///
+#define EFI_ACPI_6_1_BOOT_GRAPHICS_RESOURCE_TABLE_REVISION 1
+
+///
+/// BGRT Version
+///
+#define EFI_ACPI_6_1_BGRT_VERSION 0x01
+
+///
+/// BGRT Status
+///
+#define EFI_ACPI_6_1_BGRT_STATUS_NOT_DISPLAYED 0x00
+#define EFI_ACPI_6_1_BGRT_STATUS_DISPLAYED 0x01
+
+///
+/// BGRT Image Type
+///
+#define EFI_ACPI_6_1_BGRT_IMAGE_TYPE_BMP 0x00
+
+///
+/// FPDT Version (as defined in ACPI 6.1 spec.)
+///
+#define EFI_ACPI_6_1_FIRMWARE_PERFORMANCE_DATA_TABLE_REVISION 0x01
+
+///
+/// FPDT Performance Record Types
+///
+#define EFI_ACPI_6_1_FPDT_RECORD_TYPE_FIRMWARE_BASIC_BOOT_POINTER 0x0000
+#define EFI_ACPI_6_1_FPDT_RECORD_TYPE_S3_PERFORMANCE_TABLE_POINTER 0x0001
+
+///
+/// FPDT Performance Record Revision
+///
+#define EFI_ACPI_6_1_FPDT_RECORD_REVISION_FIRMWARE_BASIC_BOOT_POINTER 0x01
+#define EFI_ACPI_6_1_FPDT_RECORD_REVISION_S3_PERFORMANCE_TABLE_POINTER 0x01
+
+///
+/// FPDT Runtime Performance Record Types
+///
+#define EFI_ACPI_6_1_FPDT_RUNTIME_RECORD_TYPE_S3_RESUME 0x0000
+#define EFI_ACPI_6_1_FPDT_RUNTIME_RECORD_TYPE_S3_SUSPEND 0x0001
+#define EFI_ACPI_6_1_FPDT_RUNTIME_RECORD_TYPE_FIRMWARE_BASIC_BOOT 0x0002
+
+///
+/// FPDT Runtime Performance Record Revision
+///
+#define EFI_ACPI_6_1_FPDT_RUNTIME_RECORD_REVISION_S3_RESUME 0x01
+#define EFI_ACPI_6_1_FPDT_RUNTIME_RECORD_REVISION_S3_SUSPEND 0x01
+#define EFI_ACPI_6_1_FPDT_RUNTIME_RECORD_REVISION_FIRMWARE_BASIC_BOOT 0x02
+
+///
+/// FPDT Performance Record header
+///
+typedef struct {
+ UINT16 Type;
+ UINT8 Length;
+ UINT8 Revision;
+} EFI_ACPI_6_1_FPDT_PERFORMANCE_RECORD_HEADER;
+
+///
+/// FPDT Performance Table header
+///
+typedef struct {
+ UINT32 Signature;
+ UINT32 Length;
+} EFI_ACPI_6_1_FPDT_PERFORMANCE_TABLE_HEADER;
+
+///
+/// FPDT Firmware Basic Boot Performance Pointer Record Structure
+///
+typedef struct {
+ EFI_ACPI_6_1_FPDT_PERFORMANCE_RECORD_HEADER Header;
+ UINT32 Reserved;
+ ///
+ /// 64-bit processor-relative physical address of the Basic Boot Performance Table.
+ ///
+ UINT64 BootPerformanceTablePointer;
+} EFI_ACPI_6_1_FPDT_BOOT_PERFORMANCE_TABLE_POINTER_RECORD;
+
+///
+/// FPDT S3 Performance Table Pointer Record Structure
+///
+typedef struct {
+ EFI_ACPI_6_1_FPDT_PERFORMANCE_RECORD_HEADER Header;
+ UINT32 Reserved;
+ ///
+ /// 64-bit processor-relative physical address of the S3 Performance Table.
+ ///
+ UINT64 S3PerformanceTablePointer;
+} EFI_ACPI_6_1_FPDT_S3_PERFORMANCE_TABLE_POINTER_RECORD;
+
+///
+/// FPDT Firmware Basic Boot Performance Record Structure
+///
+typedef struct {
+ EFI_ACPI_6_1_FPDT_PERFORMANCE_RECORD_HEADER Header;
+ UINT32 Reserved;
+ ///
+ /// Timer value logged at the beginning of firmware image execution.
+ /// This may not always be zero or near zero.
+ ///
+ UINT64 ResetEnd;
+ ///
+ /// Timer value logged just prior to loading the OS boot loader into memory.
+ /// For non-UEFI compatible boots, this field must be zero.
+ ///
+ UINT64 OsLoaderLoadImageStart;
+ ///
+ /// Timer value logged just prior to launching the previously loaded OS boot loader image.
+ /// For non-UEFI compatible boots, the timer value logged will be just prior
+ /// to the INT 19h handler invocation.
+ ///
+ UINT64 OsLoaderStartImageStart;
+ ///
+ /// Timer value logged at the point when the OS loader calls the
+ /// ExitBootServices function for UEFI compatible firmware.
+ /// For non-UEFI compatible boots, this field must be zero.
+ ///
+ UINT64 ExitBootServicesEntry;
+ ///
+ /// Timer value logged at the point just prior to when the OS loader gaining
+ /// control back from calls the ExitBootServices function for UEFI compatible firmware.
+ /// For non-UEFI compatible boots, this field must be zero.
+ ///
+ UINT64 ExitBootServicesExit;
+} EFI_ACPI_6_1_FPDT_FIRMWARE_BASIC_BOOT_RECORD;
+
+///
+/// FPDT Firmware Basic Boot Performance Table signature
+///
+#define EFI_ACPI_6_1_FPDT_BOOT_PERFORMANCE_TABLE_SIGNATURE SIGNATURE_32('F', 'B', 'P', 'T')
+
+//
+// FPDT Firmware Basic Boot Performance Table
+//
+typedef struct {
+ EFI_ACPI_6_1_FPDT_PERFORMANCE_TABLE_HEADER Header;
+ //
+ // one or more Performance Records.
+ //
+} EFI_ACPI_6_1_FPDT_FIRMWARE_BASIC_BOOT_TABLE;
+
+///
+/// FPDT "S3PT" S3 Performance Table
+///
+#define EFI_ACPI_6_1_FPDT_S3_PERFORMANCE_TABLE_SIGNATURE SIGNATURE_32('S', '3', 'P', 'T')
+
+//
+// FPDT Firmware S3 Boot Performance Table
+//
+typedef struct {
+ EFI_ACPI_6_1_FPDT_PERFORMANCE_TABLE_HEADER Header;
+ //
+ // one or more Performance Records.
+ //
+} EFI_ACPI_6_1_FPDT_FIRMWARE_S3_BOOT_TABLE;
+
+///
+/// FPDT Basic S3 Resume Performance Record
+///
+typedef struct {
+ EFI_ACPI_6_1_FPDT_PERFORMANCE_RECORD_HEADER Header;
+ ///
+ /// A count of the number of S3 resume cycles since the last full boot sequence.
+ ///
+ UINT32 ResumeCount;
+ ///
+ /// Timer recorded at the end of BIOS S3 resume, just prior to handoff to the
+ /// OS waking vector. Only the most recent resume cycle's time is retained.
+ ///
+ UINT64 FullResume;
+ ///
+ /// Average timer value of all resume cycles logged since the last full boot
+ /// sequence, including the most recent resume. Note that the entire log of
+ /// timer values does not need to be retained in order to calculate this average.
+ ///
+ UINT64 AverageResume;
+} EFI_ACPI_6_1_FPDT_S3_RESUME_RECORD;
+
+///
+/// FPDT Basic S3 Suspend Performance Record
+///
+typedef struct {
+ EFI_ACPI_6_1_FPDT_PERFORMANCE_RECORD_HEADER Header;
+ ///
+ /// Timer value recorded at the OS write to SLP_TYP upon entry to S3.
+ /// Only the most recent suspend cycle's timer value is retained.
+ ///
+ UINT64 SuspendStart;
+ ///
+ /// Timer value recorded at the final firmware write to SLP_TYP (or other
+ /// mechanism) used to trigger hardware entry to S3.
+ /// Only the most recent suspend cycle's timer value is retained.
+ ///
+ UINT64 SuspendEnd;
+} EFI_ACPI_6_1_FPDT_S3_SUSPEND_RECORD;
+
+///
+/// Firmware Performance Record Table definition.
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+} EFI_ACPI_6_1_FIRMWARE_PERFORMANCE_RECORD_TABLE;
+
+///
+/// Generic Timer Description Table definition.
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT64 CntControlBasePhysicalAddress;
+ UINT32 Reserved;
+ UINT32 SecurePL1TimerGSIV;
+ UINT32 SecurePL1TimerFlags;
+ UINT32 NonSecurePL1TimerGSIV;
+ UINT32 NonSecurePL1TimerFlags;
+ UINT32 VirtualTimerGSIV;
+ UINT32 VirtualTimerFlags;
+ UINT32 NonSecurePL2TimerGSIV;
+ UINT32 NonSecurePL2TimerFlags;
+ UINT64 CntReadBasePhysicalAddress;
+ UINT32 PlatformTimerCount;
+ UINT32 PlatformTimerOffset;
+} EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLE;
+
+///
+/// GTDT Version (as defined in ACPI 6.1 spec.)
+///
+#define EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION 0x02
+
+///
+/// Timer Flags. All other bits are reserved and must be 0.
+///
+#define EFI_ACPI_6_1_GTDT_TIMER_FLAG_TIMER_INTERRUPT_MODE BIT0
+#define EFI_ACPI_6_1_GTDT_TIMER_FLAG_TIMER_INTERRUPT_POLARITY BIT1
+#define EFI_ACPI_6_1_GTDT_TIMER_FLAG_ALWAYS_ON_CAPABILITY BIT2
+
+///
+/// Platform Timer Type
+///
+#define EFI_ACPI_6_1_GTDT_GT_BLOCK 0
+#define EFI_ACPI_6_1_GTDT_SBSA_GENERIC_WATCHDOG 1
+
+///
+/// GT Block Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT16 Length;
+ UINT8 Reserved;
+ UINT64 CntCtlBase;
+ UINT32 GTBlockTimerCount;
+ UINT32 GTBlockTimerOffset;
+} EFI_ACPI_6_1_GTDT_GT_BLOCK_STRUCTURE;
+
+///
+/// GT Block Timer Structure
+///
+typedef struct {
+ UINT8 GTFrameNumber;
+ UINT8 Reserved[3];
+ UINT64 CntBaseX;
+ UINT64 CntEL0BaseX;
+ UINT32 GTxPhysicalTimerGSIV;
+ UINT32 GTxPhysicalTimerFlags;
+ UINT32 GTxVirtualTimerGSIV;
+ UINT32 GTxVirtualTimerFlags;
+ UINT32 GTxCommonFlags;
+} EFI_ACPI_6_1_GTDT_GT_BLOCK_TIMER_STRUCTURE;
+
+///
+/// GT Block Physical Timers and Virtual Timers Flags. All other bits are reserved and must be 0.
+///
+#define EFI_ACPI_6_1_GTDT_GT_BLOCK_TIMER_FLAG_TIMER_INTERRUPT_MODE BIT0
+#define EFI_ACPI_6_1_GTDT_GT_BLOCK_TIMER_FLAG_TIMER_INTERRUPT_POLARITY BIT1
+
+///
+/// Common Flags Flags. All other bits are reserved and must be 0.
+///
+#define EFI_ACPI_6_1_GTDT_GT_BLOCK_COMMON_FLAG_SECURE_TIMER BIT0
+#define EFI_ACPI_6_1_GTDT_GT_BLOCK_COMMON_FLAG_ALWAYS_ON_CAPABILITY BIT1
+
+///
+/// SBSA Generic Watchdog Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT16 Length;
+ UINT8 Reserved;
+ UINT64 RefreshFramePhysicalAddress;
+ UINT64 WatchdogControlFramePhysicalAddress;
+ UINT32 WatchdogTimerGSIV;
+ UINT32 WatchdogTimerFlags;
+} EFI_ACPI_6_1_GTDT_SBSA_GENERIC_WATCHDOG_STRUCTURE;
+
+///
+/// SBSA Generic Watchdog Timer Flags. All other bits are reserved and must be 0.
+///
+#define EFI_ACPI_6_1_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_TIMER_INTERRUPT_MODE BIT0
+#define EFI_ACPI_6_1_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_TIMER_INTERRUPT_POLARITY BIT1
+#define EFI_ACPI_6_1_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_SECURE_TIMER BIT2
+
+//
+// NVDIMM Firmware Interface Table definition.
+//
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 Reserved;
+} EFI_ACPI_6_1_NVDIMM_FIRMWARE_INTERFACE_TABLE;
+
+//
+// NFIT Version (as defined in ACPI 6.1 spec.)
+//
+#define EFI_ACPI_6_1_NVDIMM_FIRMWARE_INTERFACE_TABLE_REVISION 0x1
+
+//
+// Definition for NFIT Table Structure Types
+//
+#define EFI_ACPI_6_1_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_STRUCTURE_TYPE 0
+#define EFI_ACPI_6_1_NFIT_NVDIMM_REGION_MAPPING_STRUCTURE_TYPE 1
+#define EFI_ACPI_6_1_NFIT_INTERLEAVE_STRUCTURE_TYPE 2
+#define EFI_ACPI_6_1_NFIT_SMBIOS_MANAGEMENT_INFORMATION_STRUCTURE_TYPE 3
+#define EFI_ACPI_6_1_NFIT_NVDIMM_CONTROL_REGION_STRUCTURE_TYPE 4
+#define EFI_ACPI_6_1_NFIT_NVDIMM_BLOCK_DATA_WINDOW_REGION_STRUCTURE_TYPE 5
+#define EFI_ACPI_6_1_NFIT_FLUSH_HINT_ADDRESS_STRUCTURE_TYPE 6
+
+//
+// Definition for NFIT Structure Header
+//
+typedef struct {
+ UINT16 Type;
+ UINT16 Length;
+} EFI_ACPI_6_1_NFIT_STRUCTURE_HEADER;
+
+//
+// Definition for System Physical Address Range Structure
+//
+#define EFI_ACPI_6_1_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_FLAGS_CONTROL_REGION_FOR_MANAGEMENT BIT0
+#define EFI_ACPI_6_1_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_FLAGS_PROXIMITY_DOMAIN_VALID BIT1
+#define EFI_ACPI_6_1_NFIT_GUID_VOLATILE_MEMORY_REGION { 0x7305944F, 0xFDDA, 0x44E3, { 0xB1, 0x6C, 0x3F, 0x22, 0xD2, 0x52, 0xE5, 0xD0 }}
+#define EFI_ACPI_6_1_NFIT_GUID_BYTE_ADDRESSABLE_PERSISTENT_MEMORY_REGION { 0x66F0D379, 0xB4F3, 0x4074, { 0xAC, 0x43, 0x0D, 0x33, 0x18, 0xB7, 0x8C, 0xDB }}
+#define EFI_ACPI_6_1_NFIT_GUID_NVDIMM_CONTROL_REGION { 0x92F701F6, 0x13B4, 0x405D, { 0x91, 0x0B, 0x29, 0x93, 0x67, 0xE8, 0x23, 0x4C }}
+#define EFI_ACPI_6_1_NFIT_GUID_NVDIMM_BLOCK_DATA_WINDOW_REGION { 0x91AF0530, 0x5D86, 0x470E, { 0xA6, 0xB0, 0x0A, 0x2D, 0xB9, 0x40, 0x82, 0x49 }}
+#define EFI_ACPI_6_1_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_DISK_REGION_VOLATILE { 0x77AB535A, 0x45FC, 0x624B, { 0x55, 0x60, 0xF7, 0xB2, 0x81, 0xD1, 0xF9, 0x6E }}
+#define EFI_ACPI_6_1_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_CD_REGION_VOLATILE { 0x3D5ABD30, 0x4175, 0x87CE, { 0x6D, 0x64, 0xD2, 0xAD, 0xE5, 0x23, 0xC4, 0xBB }}
+#define EFI_ACPI_6_1_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_DISK_REGION_PERSISTENT { 0x5CEA02C9, 0x4D07, 0x69D3, { 0x26, 0x9F ,0x44, 0x96, 0xFB, 0xE0, 0x96, 0xF9 }}
+#define EFI_ACPI_6_1_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_CD_REGION_PERSISTENT { 0x08018188, 0x42CD, 0xBB48, { 0x10, 0x0F, 0x53, 0x87, 0xD5, 0x3D, 0xED, 0x3D }}
+typedef struct {
+ UINT16 Type;
+ UINT16 Length;
+ UINT16 SPARangeStructureIndex;
+ UINT16 Flags;
+ UINT32 Reserved_8;
+ UINT32 ProximityDomain;
+ GUID AddressRangeTypeGUID;
+ UINT64 SystemPhysicalAddressRangeBase;
+ UINT64 SystemPhysicalAddressRangeLength;
+ UINT64 AddressRangeMemoryMappingAttribute;
+} EFI_ACPI_6_1_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_STRUCTURE;
+
+//
+// Definition for Memory Device to System Physical Address Range Mapping Structure
+//
+typedef struct {
+ UINT32 DIMMNumber : 4;
+ UINT32 MemoryChannelNumber : 4;
+ UINT32 MemoryControllerID : 4;
+ UINT32 SocketID : 4;
+ UINT32 NodeControllerID : 12;
+ UINT32 Reserved_28 : 4;
+} EFI_ACPI_6_1_NFIT_DEVICE_HANDLE;
+
+#define EFI_ACPI_6_1_NFIT_MEMORY_DEVICE_STATE_FLAGS_PREVIOUS_SAVE_FAIL BIT0
+#define EFI_ACPI_6_1_NFIT_MEMORY_DEVICE_STATE_FLAGS_LAST_RESTORE_FAIL BIT1
+#define EFI_ACPI_6_1_NFIT_MEMORY_DEVICE_STATE_FLAGS_PLATFORM_FLUSH_FAIL BIT2
+#define EFI_ACPI_6_1_NFIT_MEMORY_DEVICE_STATE_FLAGS_NOT_ARMED_PRIOR_TO_OSPM_HAND_OFF BIT3
+#define EFI_ACPI_6_1_NFIT_MEMORY_DEVICE_STATE_FLAGS_SMART_HEALTH_EVENTS_PRIOR_OSPM_HAND_OFF BIT4
+#define EFI_ACPI_6_1_NFIT_MEMORY_DEVICE_STATE_FLAGS_FIRMWARE_ENABLED_TO_NOTIFY_OSPM_ON_SMART_HEALTH_EVENTS BIT5
+#define EFI_ACPI_6_1_NFIT_MEMORY_DEVICE_STATE_FLAGS_FIRMWARE_NOT_MAP_NVDIMM_TO_SPA BIT6
+typedef struct {
+ UINT16 Type;
+ UINT16 Length;
+ EFI_ACPI_6_1_NFIT_DEVICE_HANDLE NFITDeviceHandle;
+ UINT16 NVDIMMPhysicalID;
+ UINT16 NVDIMMRegionID;
+ UINT16 SPARangeStructureIndex;
+ UINT16 NVDIMMControlRegionStructureIndex;
+ UINT64 NVDIMMRegionSize;
+ UINT64 RegionOffset;
+ UINT64 NVDIMMPhysicalAddressRegionBase;
+ UINT16 InterleaveStructureIndex;
+ UINT16 InterleaveWays;
+ UINT16 NVDIMMStateFlags;
+ UINT16 Reserved_46;
+} EFI_ACPI_6_1_NFIT_NVDIMM_REGION_MAPPING_STRUCTURE;
+
+//
+// Definition for Interleave Structure
+//
+typedef struct {
+ UINT16 Type;
+ UINT16 Length;
+ UINT16 InterleaveStructureIndex;
+ UINT16 Reserved_6;
+ UINT32 NumberOfLines;
+ UINT32 LineSize;
+ // UINT32 LineOffset[NumberOfLines];
+} EFI_ACPI_6_1_NFIT_INTERLEAVE_STRUCTURE;
+
+//
+// Definition for SMBIOS Management Information Structure
+//
+typedef struct {
+ UINT16 Type;
+ UINT16 Length;
+ UINT32 Reserved_4;
+ // UINT8 Data[];
+} EFI_ACPI_6_1_NFIT_SMBIOS_MANAGEMENT_INFORMATION_STRUCTURE;
+
+//
+// Definition for NVDIMM Control Region Structure
+//
+#define EFI_ACPI_6_1_NFIT_NVDIMM_CONTROL_REGION_VALID_FIELDS_MANUFACTURING BIT0
+
+#define EFI_ACPI_6_1_NFIT_NVDIMM_CONTROL_REGION_FLAGS_BLOCK_DATA_WINDOWS_BUFFERED BIT0
+typedef struct {
+ UINT16 Type;
+ UINT16 Length;
+ UINT16 NVDIMMControlRegionStructureIndex;
+ UINT16 VendorID;
+ UINT16 DeviceID;
+ UINT16 RevisionID;
+ UINT16 SubsystemVendorID;
+ UINT16 SubsystemDeviceID;
+ UINT16 SubsystemRevisionID;
+ UINT8 ValidFields;
+ UINT8 ManufacturingLocation;
+ UINT16 ManufacturingDate;
+ UINT8 Reserved_22[2];
+ UINT32 SerialNumber;
+ UINT16 RegionFormatInterfaceCode;
+ UINT16 NumberOfBlockControlWindows;
+ UINT64 SizeOfBlockControlWindow;
+ UINT64 CommandRegisterOffsetInBlockControlWindow;
+ UINT64 SizeOfCommandRegisterInBlockControlWindows;
+ UINT64 StatusRegisterOffsetInBlockControlWindow;
+ UINT64 SizeOfStatusRegisterInBlockControlWindows;
+ UINT16 NVDIMMControlRegionFlag;
+ UINT8 Reserved_74[6];
+} EFI_ACPI_6_1_NFIT_NVDIMM_CONTROL_REGION_STRUCTURE;
+
+//
+// Definition for NVDIMM Block Data Window Region Structure
+//
+typedef struct {
+ UINT16 Type;
+ UINT16 Length;
+ UINT16 NVDIMMControlRegionStructureIndex;
+ UINT16 NumberOfBlockDataWindows;
+ UINT64 BlockDataWindowStartOffset;
+ UINT64 SizeOfBlockDataWindow;
+ UINT64 BlockAccessibleMemoryCapacity;
+ UINT64 BeginningAddressOfFirstBlockInBlockAccessibleMemory;
+} EFI_ACPI_6_1_NFIT_NVDIMM_BLOCK_DATA_WINDOW_REGION_STRUCTURE;
+
+//
+// Definition for Flush Hint Address Structure
+//
+typedef struct {
+ UINT16 Type;
+ UINT16 Length;
+ EFI_ACPI_6_1_NFIT_DEVICE_HANDLE NFITDeviceHandle;
+ UINT16 NumberOfFlushHintAddresses;
+ UINT8 Reserved_10[6];
+ // UINT64 FlushHintAddress[NumberOfFlushHintAddresses];
+} EFI_ACPI_6_1_NFIT_FLUSH_HINT_ADDRESS_STRUCTURE;
+
+///
+/// Boot Error Record Table (BERT)
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 BootErrorRegionLength;
+ UINT64 BootErrorRegion;
+} EFI_ACPI_6_1_BOOT_ERROR_RECORD_TABLE_HEADER;
+
+///
+/// BERT Version (as defined in ACPI 6.1 spec.)
+///
+#define EFI_ACPI_6_1_BOOT_ERROR_RECORD_TABLE_REVISION 0x01
+
+///
+/// Boot Error Region Block Status Definition
+///
+typedef struct {
+ UINT32 UncorrectableErrorValid : 1;
+ UINT32 CorrectableErrorValid : 1;
+ UINT32 MultipleUncorrectableErrors : 1;
+ UINT32 MultipleCorrectableErrors : 1;
+ UINT32 ErrorDataEntryCount : 10;
+ UINT32 Reserved : 18;
+} EFI_ACPI_6_1_ERROR_BLOCK_STATUS;
+
+///
+/// Boot Error Region Definition
+///
+typedef struct {
+ EFI_ACPI_6_1_ERROR_BLOCK_STATUS BlockStatus;
+ UINT32 RawDataOffset;
+ UINT32 RawDataLength;
+ UINT32 DataLength;
+ UINT32 ErrorSeverity;
+} EFI_ACPI_6_1_BOOT_ERROR_REGION_STRUCTURE;
+
+//
+// Boot Error Severity types
+//
+#define EFI_ACPI_6_1_ERROR_SEVERITY_RECOVERABLE 0x00
+#define EFI_ACPI_6_1_ERROR_SEVERITY_FATAL 0x01
+#define EFI_ACPI_6_1_ERROR_SEVERITY_CORRECTED 0x02
+#define EFI_ACPI_6_1_ERROR_SEVERITY_NONE 0x03
+//
+// The term 'Correctable' is no longer being used as an error severity of the
+// reported error since ACPI Specification Version 5.1 Errata B.
+// The below macro is considered as deprecated and should no longer be used.
+//
+#define EFI_ACPI_6_1_ERROR_SEVERITY_CORRECTABLE 0x00
+
+///
+/// Generic Error Data Entry Definition
+///
+typedef struct {
+ UINT8 SectionType[16];
+ UINT32 ErrorSeverity;
+ UINT16 Revision;
+ UINT8 ValidationBits;
+ UINT8 Flags;
+ UINT32 ErrorDataLength;
+ UINT8 FruId[16];
+ UINT8 FruText[20];
+ UINT8 Timestamp[8];
+} EFI_ACPI_6_1_GENERIC_ERROR_DATA_ENTRY_STRUCTURE;
+
+///
+/// Generic Error Data Entry Version (as defined in ACPI 6.1 spec.)
+///
+#define EFI_ACPI_6_1_GENERIC_ERROR_DATA_ENTRY_REVISION 0x0300
+
+///
+/// HEST - Hardware Error Source Table
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 ErrorSourceCount;
+} EFI_ACPI_6_1_HARDWARE_ERROR_SOURCE_TABLE_HEADER;
+
+///
+/// HEST Version (as defined in ACPI 6.1 spec.)
+///
+#define EFI_ACPI_6_1_HARDWARE_ERROR_SOURCE_TABLE_REVISION 0x01
+
+//
+// Error Source structure types.
+//
+#define EFI_ACPI_6_1_IA32_ARCHITECTURE_MACHINE_CHECK_EXCEPTION 0x00
+#define EFI_ACPI_6_1_IA32_ARCHITECTURE_CORRECTED_MACHINE_CHECK 0x01
+#define EFI_ACPI_6_1_IA32_ARCHITECTURE_NMI_ERROR 0x02
+#define EFI_ACPI_6_1_PCI_EXPRESS_ROOT_PORT_AER 0x06
+#define EFI_ACPI_6_1_PCI_EXPRESS_DEVICE_AER 0x07
+#define EFI_ACPI_6_1_PCI_EXPRESS_BRIDGE_AER 0x08
+#define EFI_ACPI_6_1_GENERIC_HARDWARE_ERROR 0x09
+#define EFI_ACPI_6_1_GENERIC_HARDWARE_ERROR_VERSION_2 0x0A
+
+//
+// Error Source structure flags.
+//
+#define EFI_ACPI_6_1_ERROR_SOURCE_FLAG_FIRMWARE_FIRST (1 << 0)
+#define EFI_ACPI_6_1_ERROR_SOURCE_FLAG_GLOBAL (1 << 1)
+
+///
+/// IA-32 Architecture Machine Check Exception Structure Definition
+///
+typedef struct {
+ UINT16 Type;
+ UINT16 SourceId;
+ UINT8 Reserved0[2];
+ UINT8 Flags;
+ UINT8 Enabled;
+ UINT32 NumberOfRecordsToPreAllocate;
+ UINT32 MaxSectionsPerRecord;
+ UINT64 GlobalCapabilityInitData;
+ UINT64 GlobalControlInitData;
+ UINT8 NumberOfHardwareBanks;
+ UINT8 Reserved1[7];
+} EFI_ACPI_6_1_IA32_ARCHITECTURE_MACHINE_CHECK_EXCEPTION_STRUCTURE;
+
+///
+/// IA-32 Architecture Machine Check Bank Structure Definition
+///
+typedef struct {
+ UINT8 BankNumber;
+ UINT8 ClearStatusOnInitialization;
+ UINT8 StatusDataFormat;
+ UINT8 Reserved0;
+ UINT32 ControlRegisterMsrAddress;
+ UINT64 ControlInitData;
+ UINT32 StatusRegisterMsrAddress;
+ UINT32 AddressRegisterMsrAddress;
+ UINT32 MiscRegisterMsrAddress;
+} EFI_ACPI_6_1_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_BANK_STRUCTURE;
+
+///
+/// IA-32 Architecture Machine Check Bank Structure MCA data format
+///
+#define EFI_ACPI_6_1_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_IA32 0x00
+#define EFI_ACPI_6_1_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_INTEL64 0x01
+#define EFI_ACPI_6_1_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_AMD64 0x02
+
+//
+// Hardware Error Notification types. All other values are reserved
+//
+#define EFI_ACPI_6_1_HARDWARE_ERROR_NOTIFICATION_POLLED 0x00
+#define EFI_ACPI_6_1_HARDWARE_ERROR_NOTIFICATION_EXTERNAL_INTERRUPT 0x01
+#define EFI_ACPI_6_1_HARDWARE_ERROR_NOTIFICATION_LOCAL_INTERRUPT 0x02
+#define EFI_ACPI_6_1_HARDWARE_ERROR_NOTIFICATION_SCI 0x03
+#define EFI_ACPI_6_1_HARDWARE_ERROR_NOTIFICATION_NMI 0x04
+#define EFI_ACPI_6_1_HARDWARE_ERROR_NOTIFICATION_CMCI 0x05
+#define EFI_ACPI_6_1_HARDWARE_ERROR_NOTIFICATION_MCE 0x06
+#define EFI_ACPI_6_1_HARDWARE_ERROR_NOTIFICATION_GPIO_SIGNAL 0x07
+#define EFI_ACPI_6_1_HARDWARE_ERROR_NOTIFICATION_ARMV8_SEA 0x08
+#define EFI_ACPI_6_1_HARDWARE_ERROR_NOTIFICATION_ARMV8_SEI 0x09
+#define EFI_ACPI_6_1_HARDWARE_ERROR_NOTIFICATION_GSIV 0x0A
+
+///
+/// Hardware Error Notification Configuration Write Enable Structure Definition
+///
+typedef struct {
+ UINT16 Type : 1;
+ UINT16 PollInterval : 1;
+ UINT16 SwitchToPollingThresholdValue : 1;
+ UINT16 SwitchToPollingThresholdWindow : 1;
+ UINT16 ErrorThresholdValue : 1;
+ UINT16 ErrorThresholdWindow : 1;
+ UINT16 Reserved : 10;
+} EFI_ACPI_6_1_HARDWARE_ERROR_NOTIFICATION_CONFIGURATION_WRITE_ENABLE_STRUCTURE;
+
+///
+/// Hardware Error Notification Structure Definition
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ EFI_ACPI_6_1_HARDWARE_ERROR_NOTIFICATION_CONFIGURATION_WRITE_ENABLE_STRUCTURE ConfigurationWriteEnable;
+ UINT32 PollInterval;
+ UINT32 Vector;
+ UINT32 SwitchToPollingThresholdValue;
+ UINT32 SwitchToPollingThresholdWindow;
+ UINT32 ErrorThresholdValue;
+ UINT32 ErrorThresholdWindow;
+} EFI_ACPI_6_1_HARDWARE_ERROR_NOTIFICATION_STRUCTURE;
+
+///
+/// IA-32 Architecture Corrected Machine Check Structure Definition
+///
+typedef struct {
+ UINT16 Type;
+ UINT16 SourceId;
+ UINT8 Reserved0[2];
+ UINT8 Flags;
+ UINT8 Enabled;
+ UINT32 NumberOfRecordsToPreAllocate;
+ UINT32 MaxSectionsPerRecord;
+ EFI_ACPI_6_1_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure;
+ UINT8 NumberOfHardwareBanks;
+ UINT8 Reserved1[3];
+} EFI_ACPI_6_1_IA32_ARCHITECTURE_CORRECTED_MACHINE_CHECK_STRUCTURE;
+
+///
+/// IA-32 Architecture NMI Error Structure Definition
+///
+typedef struct {
+ UINT16 Type;
+ UINT16 SourceId;
+ UINT8 Reserved0[2];
+ UINT32 NumberOfRecordsToPreAllocate;
+ UINT32 MaxSectionsPerRecord;
+ UINT32 MaxRawDataLength;
+} EFI_ACPI_6_1_IA32_ARCHITECTURE_NMI_ERROR_STRUCTURE;
+
+///
+/// PCI Express Root Port AER Structure Definition
+///
+typedef struct {
+ UINT16 Type;
+ UINT16 SourceId;
+ UINT8 Reserved0[2];
+ UINT8 Flags;
+ UINT8 Enabled;
+ UINT32 NumberOfRecordsToPreAllocate;
+ UINT32 MaxSectionsPerRecord;
+ UINT32 Bus;
+ UINT16 Device;
+ UINT16 Function;
+ UINT16 DeviceControl;
+ UINT8 Reserved1[2];
+ UINT32 UncorrectableErrorMask;
+ UINT32 UncorrectableErrorSeverity;
+ UINT32 CorrectableErrorMask;
+ UINT32 AdvancedErrorCapabilitiesAndControl;
+ UINT32 RootErrorCommand;
+} EFI_ACPI_6_1_PCI_EXPRESS_ROOT_PORT_AER_STRUCTURE;
+
+///
+/// PCI Express Device AER Structure Definition
+///
+typedef struct {
+ UINT16 Type;
+ UINT16 SourceId;
+ UINT8 Reserved0[2];
+ UINT8 Flags;
+ UINT8 Enabled;
+ UINT32 NumberOfRecordsToPreAllocate;
+ UINT32 MaxSectionsPerRecord;
+ UINT32 Bus;
+ UINT16 Device;
+ UINT16 Function;
+ UINT16 DeviceControl;
+ UINT8 Reserved1[2];
+ UINT32 UncorrectableErrorMask;
+ UINT32 UncorrectableErrorSeverity;
+ UINT32 CorrectableErrorMask;
+ UINT32 AdvancedErrorCapabilitiesAndControl;
+} EFI_ACPI_6_1_PCI_EXPRESS_DEVICE_AER_STRUCTURE;
+
+///
+/// PCI Express Bridge AER Structure Definition
+///
+typedef struct {
+ UINT16 Type;
+ UINT16 SourceId;
+ UINT8 Reserved0[2];
+ UINT8 Flags;
+ UINT8 Enabled;
+ UINT32 NumberOfRecordsToPreAllocate;
+ UINT32 MaxSectionsPerRecord;
+ UINT32 Bus;
+ UINT16 Device;
+ UINT16 Function;
+ UINT16 DeviceControl;
+ UINT8 Reserved1[2];
+ UINT32 UncorrectableErrorMask;
+ UINT32 UncorrectableErrorSeverity;
+ UINT32 CorrectableErrorMask;
+ UINT32 AdvancedErrorCapabilitiesAndControl;
+ UINT32 SecondaryUncorrectableErrorMask;
+ UINT32 SecondaryUncorrectableErrorSeverity;
+ UINT32 SecondaryAdvancedErrorCapabilitiesAndControl;
+} EFI_ACPI_6_1_PCI_EXPRESS_BRIDGE_AER_STRUCTURE;
+
+///
+/// Generic Hardware Error Source Structure Definition
+///
+typedef struct {
+ UINT16 Type;
+ UINT16 SourceId;
+ UINT16 RelatedSourceId;
+ UINT8 Flags;
+ UINT8 Enabled;
+ UINT32 NumberOfRecordsToPreAllocate;
+ UINT32 MaxSectionsPerRecord;
+ UINT32 MaxRawDataLength;
+ EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE ErrorStatusAddress;
+ EFI_ACPI_6_1_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure;
+ UINT32 ErrorStatusBlockLength;
+} EFI_ACPI_6_1_GENERIC_HARDWARE_ERROR_SOURCE_STRUCTURE;
+
+///
+/// Generic Hardware Error Source Version 2 Structure Definition
+///
+typedef struct {
+ UINT16 Type;
+ UINT16 SourceId;
+ UINT16 RelatedSourceId;
+ UINT8 Flags;
+ UINT8 Enabled;
+ UINT32 NumberOfRecordsToPreAllocate;
+ UINT32 MaxSectionsPerRecord;
+ UINT32 MaxRawDataLength;
+ EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE ErrorStatusAddress;
+ EFI_ACPI_6_1_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure;
+ UINT32 ErrorStatusBlockLength;
+ EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE ReadAckRegister;
+ UINT64 ReadAckPreserve;
+ UINT64 ReadAckWrite;
+} EFI_ACPI_6_1_GENERIC_HARDWARE_ERROR_SOURCE_VERSION_2_STRUCTURE;
+
+///
+/// Generic Error Status Definition
+///
+typedef struct {
+ EFI_ACPI_6_1_ERROR_BLOCK_STATUS BlockStatus;
+ UINT32 RawDataOffset;
+ UINT32 RawDataLength;
+ UINT32 DataLength;
+ UINT32 ErrorSeverity;
+} EFI_ACPI_6_1_GENERIC_ERROR_STATUS_STRUCTURE;
+
+///
+/// ERST - Error Record Serialization Table
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 SerializationHeaderSize;
+ UINT8 Reserved0[4];
+ UINT32 InstructionEntryCount;
+} EFI_ACPI_6_1_ERROR_RECORD_SERIALIZATION_TABLE_HEADER;
+
+///
+/// ERST Version (as defined in ACPI 6.1 spec.)
+///
+#define EFI_ACPI_6_1_ERROR_RECORD_SERIALIZATION_TABLE_REVISION 0x01
+
+///
+/// ERST Serialization Actions
+///
+#define EFI_ACPI_6_1_ERST_BEGIN_WRITE_OPERATION 0x00
+#define EFI_ACPI_6_1_ERST_BEGIN_READ_OPERATION 0x01
+#define EFI_ACPI_6_1_ERST_BEGIN_CLEAR_OPERATION 0x02
+#define EFI_ACPI_6_1_ERST_END_OPERATION 0x03
+#define EFI_ACPI_6_1_ERST_SET_RECORD_OFFSET 0x04
+#define EFI_ACPI_6_1_ERST_EXECUTE_OPERATION 0x05
+#define EFI_ACPI_6_1_ERST_CHECK_BUSY_STATUS 0x06
+#define EFI_ACPI_6_1_ERST_GET_COMMAND_STATUS 0x07
+#define EFI_ACPI_6_1_ERST_GET_RECORD_IDENTIFIER 0x08
+#define EFI_ACPI_6_1_ERST_SET_RECORD_IDENTIFIER 0x09
+#define EFI_ACPI_6_1_ERST_GET_RECORD_COUNT 0x0A
+#define EFI_ACPI_6_1_ERST_BEGIN_DUMMY_WRITE_OPERATION 0x0B
+#define EFI_ACPI_6_1_ERST_GET_ERROR_LOG_ADDRESS_RANGE 0x0D
+#define EFI_ACPI_6_1_ERST_GET_ERROR_LOG_ADDRESS_RANGE_LENGTH 0x0E
+#define EFI_ACPI_6_1_ERST_GET_ERROR_LOG_ADDRESS_RANGE_ATTRIBUTES 0x0F
+#define EFI_ACPI_6_1_ERST_GET_EXECUTE_OPERATION_TIMINGS 0x10
+
+///
+/// ERST Action Command Status
+///
+#define EFI_ACPI_6_1_ERST_STATUS_SUCCESS 0x00
+#define EFI_ACPI_6_1_ERST_STATUS_NOT_ENOUGH_SPACE 0x01
+#define EFI_ACPI_6_1_ERST_STATUS_HARDWARE_NOT_AVAILABLE 0x02
+#define EFI_ACPI_6_1_ERST_STATUS_FAILED 0x03
+#define EFI_ACPI_6_1_ERST_STATUS_RECORD_STORE_EMPTY 0x04
+#define EFI_ACPI_6_1_ERST_STATUS_RECORD_NOT_FOUND 0x05
+
+///
+/// ERST Serialization Instructions
+///
+#define EFI_ACPI_6_1_ERST_READ_REGISTER 0x00
+#define EFI_ACPI_6_1_ERST_READ_REGISTER_VALUE 0x01
+#define EFI_ACPI_6_1_ERST_WRITE_REGISTER 0x02
+#define EFI_ACPI_6_1_ERST_WRITE_REGISTER_VALUE 0x03
+#define EFI_ACPI_6_1_ERST_NOOP 0x04
+#define EFI_ACPI_6_1_ERST_LOAD_VAR1 0x05
+#define EFI_ACPI_6_1_ERST_LOAD_VAR2 0x06
+#define EFI_ACPI_6_1_ERST_STORE_VAR1 0x07
+#define EFI_ACPI_6_1_ERST_ADD 0x08
+#define EFI_ACPI_6_1_ERST_SUBTRACT 0x09
+#define EFI_ACPI_6_1_ERST_ADD_VALUE 0x0A
+#define EFI_ACPI_6_1_ERST_SUBTRACT_VALUE 0x0B
+#define EFI_ACPI_6_1_ERST_STALL 0x0C
+#define EFI_ACPI_6_1_ERST_STALL_WHILE_TRUE 0x0D
+#define EFI_ACPI_6_1_ERST_SKIP_NEXT_INSTRUCTION_IF_TRUE 0x0E
+#define EFI_ACPI_6_1_ERST_GOTO 0x0F
+#define EFI_ACPI_6_1_ERST_SET_SRC_ADDRESS_BASE 0x10
+#define EFI_ACPI_6_1_ERST_SET_DST_ADDRESS_BASE 0x11
+#define EFI_ACPI_6_1_ERST_MOVE_DATA 0x12
+
+///
+/// ERST Instruction Flags
+///
+#define EFI_ACPI_6_1_ERST_PRESERVE_REGISTER 0x01
+
+///
+/// ERST Serialization Instruction Entry
+///
+typedef struct {
+ UINT8 SerializationAction;
+ UINT8 Instruction;
+ UINT8 Flags;
+ UINT8 Reserved0;
+ EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE RegisterRegion;
+ UINT64 Value;
+ UINT64 Mask;
+} EFI_ACPI_6_1_ERST_SERIALIZATION_INSTRUCTION_ENTRY;
+
+///
+/// EINJ - Error Injection Table
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 InjectionHeaderSize;
+ UINT8 InjectionFlags;
+ UINT8 Reserved0[3];
+ UINT32 InjectionEntryCount;
+} EFI_ACPI_6_1_ERROR_INJECTION_TABLE_HEADER;
+
+///
+/// EINJ Version (as defined in ACPI 6.1 spec.)
+///
+#define EFI_ACPI_6_1_ERROR_INJECTION_TABLE_REVISION 0x01
+
+///
+/// EINJ Error Injection Actions
+///
+#define EFI_ACPI_6_1_EINJ_BEGIN_INJECTION_OPERATION 0x00
+#define EFI_ACPI_6_1_EINJ_GET_TRIGGER_ERROR_ACTION_TABLE 0x01
+#define EFI_ACPI_6_1_EINJ_SET_ERROR_TYPE 0x02
+#define EFI_ACPI_6_1_EINJ_GET_ERROR_TYPE 0x03
+#define EFI_ACPI_6_1_EINJ_END_OPERATION 0x04
+#define EFI_ACPI_6_1_EINJ_EXECUTE_OPERATION 0x05
+#define EFI_ACPI_6_1_EINJ_CHECK_BUSY_STATUS 0x06
+#define EFI_ACPI_6_1_EINJ_GET_COMMAND_STATUS 0x07
+#define EFI_ACPI_6_1_EINJ_TRIGGER_ERROR 0xFF
+
+///
+/// EINJ Action Command Status
+///
+#define EFI_ACPI_6_1_EINJ_STATUS_SUCCESS 0x00
+#define EFI_ACPI_6_1_EINJ_STATUS_UNKNOWN_FAILURE 0x01
+#define EFI_ACPI_6_1_EINJ_STATUS_INVALID_ACCESS 0x02
+
+///
+/// EINJ Error Type Definition
+///
+#define EFI_ACPI_6_1_EINJ_ERROR_PROCESSOR_CORRECTABLE (1 << 0)
+#define EFI_ACPI_6_1_EINJ_ERROR_PROCESSOR_UNCORRECTABLE_NONFATAL (1 << 1)
+#define EFI_ACPI_6_1_EINJ_ERROR_PROCESSOR_UNCORRECTABLE_FATAL (1 << 2)
+#define EFI_ACPI_6_1_EINJ_ERROR_MEMORY_CORRECTABLE (1 << 3)
+#define EFI_ACPI_6_1_EINJ_ERROR_MEMORY_UNCORRECTABLE_NONFATAL (1 << 4)
+#define EFI_ACPI_6_1_EINJ_ERROR_MEMORY_UNCORRECTABLE_FATAL (1 << 5)
+#define EFI_ACPI_6_1_EINJ_ERROR_PCI_EXPRESS_CORRECTABLE (1 << 6)
+#define EFI_ACPI_6_1_EINJ_ERROR_PCI_EXPRESS_UNCORRECTABLE_NONFATAL (1 << 7)
+#define EFI_ACPI_6_1_EINJ_ERROR_PCI_EXPRESS_UNCORRECTABLE_FATAL (1 << 8)
+#define EFI_ACPI_6_1_EINJ_ERROR_PLATFORM_CORRECTABLE (1 << 9)
+#define EFI_ACPI_6_1_EINJ_ERROR_PLATFORM_UNCORRECTABLE_NONFATAL (1 << 10)
+#define EFI_ACPI_6_1_EINJ_ERROR_PLATFORM_UNCORRECTABLE_FATAL (1 << 11)
+
+///
+/// EINJ Injection Instructions
+///
+#define EFI_ACPI_6_1_EINJ_READ_REGISTER 0x00
+#define EFI_ACPI_6_1_EINJ_READ_REGISTER_VALUE 0x01
+#define EFI_ACPI_6_1_EINJ_WRITE_REGISTER 0x02
+#define EFI_ACPI_6_1_EINJ_WRITE_REGISTER_VALUE 0x03
+#define EFI_ACPI_6_1_EINJ_NOOP 0x04
+
+///
+/// EINJ Instruction Flags
+///
+#define EFI_ACPI_6_1_EINJ_PRESERVE_REGISTER 0x01
+
+///
+/// EINJ Injection Instruction Entry
+///
+typedef struct {
+ UINT8 InjectionAction;
+ UINT8 Instruction;
+ UINT8 Flags;
+ UINT8 Reserved0;
+ EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE RegisterRegion;
+ UINT64 Value;
+ UINT64 Mask;
+} EFI_ACPI_6_1_EINJ_INJECTION_INSTRUCTION_ENTRY;
+
+///
+/// EINJ Trigger Action Table
+///
+typedef struct {
+ UINT32 HeaderSize;
+ UINT32 Revision;
+ UINT32 TableSize;
+ UINT32 EntryCount;
+} EFI_ACPI_6_1_EINJ_TRIGGER_ACTION_TABLE;
+
+///
+/// Platform Communications Channel Table (PCCT)
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 Flags;
+ UINT64 Reserved;
+} EFI_ACPI_6_1_PLATFORM_COMMUNICATION_CHANNEL_TABLE_HEADER;
+
+///
+/// PCCT Version (as defined in ACPI 6.1 spec.)
+///
+#define EFI_ACPI_6_1_PLATFORM_COMMUNICATION_CHANNEL_TABLE_REVISION 0x01
+
+///
+/// PCCT Global Flags
+///
+#define EFI_ACPI_6_1_PCCT_FLAGS_SCI_DOORBELL BIT0
+
+//
+// PCCT Subspace type
+//
+#define EFI_ACPI_6_1_PCCT_SUBSPACE_TYPE_GENERIC 0x00
+#define EFI_ACPI_6_1_PCCT_SUBSPACE_TYPE_1_HW_REDUCED_COMMUNICATIONS 0x01
+#define EFI_ACPI_6_1_PCCT_SUBSPACE_TYPE_2_HW_REDUCED_COMMUNICATIONS 0x02
+
+///
+/// PCC Subspace Structure Header
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+} EFI_ACPI_6_1_PCCT_SUBSPACE_HEADER;
+
+///
+/// Generic Communications Subspace Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 Reserved[6];
+ UINT64 BaseAddress;
+ UINT64 AddressLength;
+ EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE DoorbellRegister;
+ UINT64 DoorbellPreserve;
+ UINT64 DoorbellWrite;
+ UINT32 NominalLatency;
+ UINT32 MaximumPeriodicAccessRate;
+ UINT16 MinimumRequestTurnaroundTime;
+} EFI_ACPI_6_1_PCCT_SUBSPACE_GENERIC;
+
+///
+/// Generic Communications Channel Shared Memory Region
+///
+
+typedef struct {
+ UINT8 Command;
+ UINT8 Reserved : 7;
+ UINT8 GenerateSci : 1;
+} EFI_ACPI_6_1_PCCT_GENERIC_SHARED_MEMORY_REGION_COMMAND;
+
+typedef struct {
+ UINT8 CommandComplete : 1;
+ UINT8 SciDoorbell : 1;
+ UINT8 Error : 1;
+ UINT8 PlatformNotification : 1;
+ UINT8 Reserved : 4;
+ UINT8 Reserved1;
+} EFI_ACPI_6_1_PCCT_GENERIC_SHARED_MEMORY_REGION_STATUS;
+
+typedef struct {
+ UINT32 Signature;
+ EFI_ACPI_6_1_PCCT_GENERIC_SHARED_MEMORY_REGION_COMMAND Command;
+ EFI_ACPI_6_1_PCCT_GENERIC_SHARED_MEMORY_REGION_STATUS Status;
+} EFI_ACPI_6_1_PCCT_GENERIC_SHARED_MEMORY_REGION_HEADER;
+
+#define EFI_ACPI_6_1_PCCT_SUBSPACE_DOORBELL_INTERRUPT_FLAGS_POLARITY BIT0
+#define EFI_ACPI_6_1_PCCT_SUBSPACE_DOORBELL_INTERRUPT_FLAGS_MODE BIT1
+
+///
+/// Type 1 HW-Reduced Communications Subspace Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT32 DoorbellInterrupt;
+ UINT8 DoorbellInterruptFlags;
+ UINT8 Reserved;
+ UINT64 BaseAddress;
+ UINT64 AddressLength;
+ EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE DoorbellRegister;
+ UINT64 DoorbellPreserve;
+ UINT64 DoorbellWrite;
+ UINT32 NominalLatency;
+ UINT32 MaximumPeriodicAccessRate;
+ UINT16 MinimumRequestTurnaroundTime;
+} EFI_ACPI_6_1_PCCT_SUBSPACE_1_HW_REDUCED_COMMUNICATIONS;
+
+///
+/// Type 2 HW-Reduced Communications Subspace Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT32 DoorbellInterrupt;
+ UINT8 DoorbellInterruptFlags;
+ UINT8 Reserved;
+ UINT64 BaseAddress;
+ UINT64 AddressLength;
+ EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE DoorbellRegister;
+ UINT64 DoorbellPreserve;
+ UINT64 DoorbellWrite;
+ UINT32 NominalLatency;
+ UINT32 MaximumPeriodicAccessRate;
+ UINT16 MinimumRequestTurnaroundTime;
+ EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE DoorbellAckRegister;
+ UINT64 DoorbellAckPreserve;
+ UINT64 DoorbellAckWrite;
+} EFI_ACPI_6_1_PCCT_SUBSPACE_2_HW_REDUCED_COMMUNICATIONS;
+
+//
+// Known table signatures
+//
+
+///
+/// "RSD PTR " Root System Description Pointer
+///
+#define EFI_ACPI_6_1_ROOT_SYSTEM_DESCRIPTION_POINTER_SIGNATURE SIGNATURE_64('R', 'S', 'D', ' ', 'P', 'T', 'R', ' ')
+
+///
+/// "APIC" Multiple APIC Description Table
+///
+#define EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('A', 'P', 'I', 'C')
+
+///
+/// "BERT" Boot Error Record Table
+///
+#define EFI_ACPI_6_1_BOOT_ERROR_RECORD_TABLE_SIGNATURE SIGNATURE_32('B', 'E', 'R', 'T')
+
+///
+/// "BGRT" Boot Graphics Resource Table
+///
+#define EFI_ACPI_6_1_BOOT_GRAPHICS_RESOURCE_TABLE_SIGNATURE SIGNATURE_32('B', 'G', 'R', 'T')
+
+///
+/// "CPEP" Corrected Platform Error Polling Table
+///
+#define EFI_ACPI_6_1_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_SIGNATURE SIGNATURE_32('C', 'P', 'E', 'P')
+
+///
+/// "DSDT" Differentiated System Description Table
+///
+#define EFI_ACPI_6_1_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('D', 'S', 'D', 'T')
+
+///
+/// "ECDT" Embedded Controller Boot Resources Table
+///
+#define EFI_ACPI_6_1_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE_SIGNATURE SIGNATURE_32('E', 'C', 'D', 'T')
+
+///
+/// "EINJ" Error Injection Table
+///
+#define EFI_ACPI_6_1_ERROR_INJECTION_TABLE_SIGNATURE SIGNATURE_32('E', 'I', 'N', 'J')
+
+///
+/// "ERST" Error Record Serialization Table
+///
+#define EFI_ACPI_6_1_ERROR_RECORD_SERIALIZATION_TABLE_SIGNATURE SIGNATURE_32('E', 'R', 'S', 'T')
+
+///
+/// "FACP" Fixed ACPI Description Table
+///
+#define EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('F', 'A', 'C', 'P')
+
+///
+/// "FACS" Firmware ACPI Control Structure
+///
+#define EFI_ACPI_6_1_FIRMWARE_ACPI_CONTROL_STRUCTURE_SIGNATURE SIGNATURE_32('F', 'A', 'C', 'S')
+
+///
+/// "FPDT" Firmware Performance Data Table
+///
+#define EFI_ACPI_6_1_FIRMWARE_PERFORMANCE_DATA_TABLE_SIGNATURE SIGNATURE_32('F', 'P', 'D', 'T')
+
+///
+/// "GTDT" Generic Timer Description Table
+///
+#define EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('G', 'T', 'D', 'T')
+
+///
+/// "HEST" Hardware Error Source Table
+///
+#define EFI_ACPI_6_1_HARDWARE_ERROR_SOURCE_TABLE_SIGNATURE SIGNATURE_32('H', 'E', 'S', 'T')
+
+///
+/// "MPST" Memory Power State Table
+///
+#define EFI_ACPI_6_1_MEMORY_POWER_STATE_TABLE_SIGNATURE SIGNATURE_32('M', 'P', 'S', 'T')
+
+///
+/// "MSCT" Maximum System Characteristics Table
+///
+#define EFI_ACPI_6_1_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_SIGNATURE SIGNATURE_32('M', 'S', 'C', 'T')
+
+///
+/// "NFIT" NVDIMM Firmware Interface Table
+///
+#define EFI_ACPI_6_1_NVDIMM_FIRMWARE_INTERFACE_TABLE_STRUCTURE_SIGNATURE SIGNATURE_32('N', 'F', 'I', 'T')
+
+///
+/// "PMTT" Platform Memory Topology Table
+///
+#define EFI_ACPI_6_1_PLATFORM_MEMORY_TOPOLOGY_TABLE_SIGNATURE SIGNATURE_32('P', 'M', 'T', 'T')
+
+///
+/// "PSDT" Persistent System Description Table
+///
+#define EFI_ACPI_6_1_PERSISTENT_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('P', 'S', 'D', 'T')
+
+///
+/// "RASF" ACPI RAS Feature Table
+///
+#define EFI_ACPI_6_1_ACPI_RAS_FEATURE_TABLE_SIGNATURE SIGNATURE_32('R', 'A', 'S', 'F')
+
+///
+/// "RSDT" Root System Description Table
+///
+#define EFI_ACPI_6_1_ROOT_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('R', 'S', 'D', 'T')
+
+///
+/// "SBST" Smart Battery Specification Table
+///
+#define EFI_ACPI_6_1_SMART_BATTERY_SPECIFICATION_TABLE_SIGNATURE SIGNATURE_32('S', 'B', 'S', 'T')
+
+///
+/// "SLIT" System Locality Information Table
+///
+#define EFI_ACPI_6_1_SYSTEM_LOCALITY_INFORMATION_TABLE_SIGNATURE SIGNATURE_32('S', 'L', 'I', 'T')
+
+///
+/// "SRAT" System Resource Affinity Table
+///
+#define EFI_ACPI_6_1_SYSTEM_RESOURCE_AFFINITY_TABLE_SIGNATURE SIGNATURE_32('S', 'R', 'A', 'T')
+
+///
+/// "SSDT" Secondary System Description Table
+///
+#define EFI_ACPI_6_1_SECONDARY_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('S', 'S', 'D', 'T')
+
+///
+/// "XSDT" Extended System Description Table
+///
+#define EFI_ACPI_6_1_EXTENDED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('X', 'S', 'D', 'T')
+
+///
+/// "BOOT" MS Simple Boot Spec
+///
+#define EFI_ACPI_6_1_SIMPLE_BOOT_FLAG_TABLE_SIGNATURE SIGNATURE_32('B', 'O', 'O', 'T')
+
+///
+/// "CSRT" MS Core System Resource Table
+///
+#define EFI_ACPI_6_1_CORE_SYSTEM_RESOURCE_TABLE_SIGNATURE SIGNATURE_32('C', 'S', 'R', 'T')
+
+///
+/// "DBG2" MS Debug Port 2 Spec
+///
+#define EFI_ACPI_6_1_DEBUG_PORT_2_TABLE_SIGNATURE SIGNATURE_32('D', 'B', 'G', '2')
+
+///
+/// "DBGP" MS Debug Port Spec
+///
+#define EFI_ACPI_6_1_DEBUG_PORT_TABLE_SIGNATURE SIGNATURE_32('D', 'B', 'G', 'P')
+
+///
+/// "DMAR" DMA Remapping Table
+///
+#define EFI_ACPI_6_1_DMA_REMAPPING_TABLE_SIGNATURE SIGNATURE_32('D', 'M', 'A', 'R')
+
+///
+/// "DRTM" Dynamic Root of Trust for Measurement Table
+///
+#define EFI_ACPI_6_1_DYNAMIC_ROOT_OF_TRUST_FOR_MEASUREMENT_TABLE_SIGNATURE SIGNATURE_32('D', 'R', 'T', 'M')
+
+///
+/// "ETDT" Event Timer Description Table
+///
+#define EFI_ACPI_6_1_EVENT_TIMER_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('E', 'T', 'D', 'T')
+
+///
+/// "HPET" IA-PC High Precision Event Timer Table
+///
+#define EFI_ACPI_6_1_HIGH_PRECISION_EVENT_TIMER_TABLE_SIGNATURE SIGNATURE_32('H', 'P', 'E', 'T')
+
+///
+/// "iBFT" iSCSI Boot Firmware Table
+///
+#define EFI_ACPI_6_1_ISCSI_BOOT_FIRMWARE_TABLE_SIGNATURE SIGNATURE_32('i', 'B', 'F', 'T')
+
+///
+/// "IORT" I/O Remapping Table
+///
+#define EFI_ACPI_6_1_IO_REMAPPING_TABLE_SIGNATURE SIGNATURE_32('I', 'O', 'R', 'T')
+
+///
+/// "IVRS" I/O Virtualization Reporting Structure
+///
+#define EFI_ACPI_6_1_IO_VIRTUALIZATION_REPORTING_STRUCTURE_SIGNATURE SIGNATURE_32('I', 'V', 'R', 'S')
+
+///
+/// "LPIT" Low Power Idle Table
+///
+#define EFI_ACPI_6_1_LOW_POWER_IDLE_TABLE_STRUCTURE_SIGNATURE SIGNATURE_32('L', 'P', 'I', 'T')
+
+///
+/// "MCFG" PCI Express Memory Mapped Configuration Space Base Address Description Table
+///
+#define EFI_ACPI_6_1_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('M', 'C', 'F', 'G')
+
+///
+/// "MCHI" Management Controller Host Interface Table
+///
+#define EFI_ACPI_6_1_MANAGEMENT_CONTROLLER_HOST_INTERFACE_TABLE_SIGNATURE SIGNATURE_32('M', 'C', 'H', 'I')
+
+///
+/// "MSDM" MS Data Management Table
+///
+#define EFI_ACPI_6_1_DATA_MANAGEMENT_TABLE_SIGNATURE SIGNATURE_32('M', 'S', 'D', 'M')
+
+///
+/// "PCCT" Platform Communications Channel Table
+///
+#define EFI_ACPI_6_1_PLATFORM_COMMUNICATIONS_CHANNEL_TABLE_SIGNATURE SIGNATURE_32('P', 'C', 'C', 'T')
+
+///
+/// "SLIC" MS Software Licensing Table Specification
+///
+#define EFI_ACPI_6_1_SOFTWARE_LICENSING_TABLE_SIGNATURE SIGNATURE_32('S', 'L', 'I', 'C')
+
+///
+/// "SPCR" Serial Port Console Redirection Table
+///
+#define EFI_ACPI_6_1_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE SIGNATURE_32('S', 'P', 'C', 'R')
+
+///
+/// "SPMI" Server Platform Management Interface Table
+///
+#define EFI_ACPI_6_1_SERVER_PLATFORM_MANAGEMENT_INTERFACE_TABLE_SIGNATURE SIGNATURE_32('S', 'P', 'M', 'I')
+
+///
+/// "STAO" _STA Override Table
+///
+#define EFI_ACPI_6_1_STA_OVERRIDE_TABLE_SIGNATURE SIGNATURE_32('S', 'T', 'A', 'O')
+
+///
+/// "TCPA" Trusted Computing Platform Alliance Capabilities Table
+///
+#define EFI_ACPI_6_1_TRUSTED_COMPUTING_PLATFORM_ALLIANCE_CAPABILITIES_TABLE_SIGNATURE SIGNATURE_32('T', 'C', 'P', 'A')
+
+///
+/// "TPM2" Trusted Computing Platform 1 Table
+///
+#define EFI_ACPI_6_1_TRUSTED_COMPUTING_PLATFORM_2_TABLE_SIGNATURE SIGNATURE_32('T', 'P', 'M', '2')
+
+///
+/// "UEFI" UEFI ACPI Data Table
+///
+#define EFI_ACPI_6_1_UEFI_ACPI_DATA_TABLE_SIGNATURE SIGNATURE_32('U', 'E', 'F', 'I')
+
+///
+/// "WAET" Windows ACPI Emulated Devices Table
+///
+#define EFI_ACPI_6_1_WINDOWS_ACPI_EMULATED_DEVICES_TABLE_SIGNATURE SIGNATURE_32('W', 'A', 'E', 'T')
+
+///
+/// "WDAT" Watchdog Action Table
+///
+#define EFI_ACPI_6_1_WATCHDOG_ACTION_TABLE_SIGNATURE SIGNATURE_32('W', 'D', 'A', 'T')
+
+///
+/// "WDRT" Watchdog Resource Table
+///
+#define EFI_ACPI_6_1_WATCHDOG_RESOURCE_TABLE_SIGNATURE SIGNATURE_32('W', 'D', 'R', 'T')
+
+///
+/// "WPBT" MS Platform Binary Table
+///
+#define EFI_ACPI_6_1_PLATFORM_BINARY_TABLE_SIGNATURE SIGNATURE_32('W', 'P', 'B', 'T')
+
+///
+/// "XENV" Xen Project Table
+///
+#define EFI_ACPI_6_1_XEN_PROJECT_TABLE_SIGNATURE SIGNATURE_32('X', 'E', 'N', 'V')
+
+#pragma pack()
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/Acpi62.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/Acpi62.h
new file mode 100644
index 0000000000..c174e6d484
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/Acpi62.h
@@ -0,0 +1,2983 @@
+/** @file
+ ACPI 6.2 definitions from the ACPI Specification Revision 6.2 May, 2017.
+
+ Copyright (c) 2017 - 2022, Intel Corporation. All rights reserved.
+ Copyright (c) 2020, ARM Ltd. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _ACPI_6_2_H_
+#define _ACPI_6_2_H_
+
+#include
+
+//
+// Large Item Descriptor Name
+//
+#define ACPI_LARGE_PIN_FUNCTION_DESCRIPTOR_NAME 0x0D
+#define ACPI_LARGE_PIN_CONFIGURATION_DESCRIPTOR_NAME 0x0F
+#define ACPI_LARGE_PIN_GROUP_DESCRIPTOR_NAME 0x10
+#define ACPI_LARGE_PIN_GROUP_FUNCTION_DESCRIPTOR_NAME 0x11
+#define ACPI_LARGE_PIN_GROUP_CONFIGURATION_DESCRIPTOR_NAME 0x12
+
+//
+// Large Item Descriptor Value
+//
+#define ACPI_PIN_FUNCTION_DESCRIPTOR 0x8D
+#define ACPI_PIN_CONFIGURATION_DESCRIPTOR 0x8F
+#define ACPI_PIN_GROUP_DESCRIPTOR 0x90
+#define ACPI_PIN_GROUP_FUNCTION_DESCRIPTOR 0x91
+#define ACPI_PIN_GROUP_CONFIGURATION_DESCRIPTOR 0x92
+
+#pragma pack(1)
+
+///
+/// Pin Function Descriptor
+///
+typedef PACKED struct {
+ ACPI_LARGE_RESOURCE_HEADER Header;
+ UINT8 RevisionId;
+ UINT16 Flags;
+ UINT8 PinPullConfiguration;
+ UINT16 FunctionNumber;
+ UINT16 PinTableOffset;
+ UINT8 ResourceSourceIndex;
+ UINT16 ResourceSourceNameOffset;
+ UINT16 VendorDataOffset;
+ UINT16 VendorDataLength;
+} EFI_ACPI_PIN_FUNCTION_DESCRIPTOR;
+
+///
+/// Pin Configuration Descriptor
+///
+typedef PACKED struct {
+ ACPI_LARGE_RESOURCE_HEADER Header;
+ UINT8 RevisionId;
+ UINT16 Flags;
+ UINT8 PinConfigurationType;
+ UINT32 PinConfigurationValue;
+ UINT16 PinTableOffset;
+ UINT8 ResourceSourceIndex;
+ UINT16 ResourceSourceNameOffset;
+ UINT16 VendorDataOffset;
+ UINT16 VendorDataLength;
+} EFI_ACPI_PIN_CONFIGURATION_DESCRIPTOR;
+
+///
+/// Pin Group Descriptor
+///
+typedef PACKED struct {
+ ACPI_LARGE_RESOURCE_HEADER Header;
+ UINT8 RevisionId;
+ UINT16 Flags;
+ UINT16 PinTableOffset;
+ UINT16 ResourceLabelOffset;
+ UINT16 VendorDataOffset;
+ UINT16 VendorDataLength;
+} EFI_ACPI_PIN_GROUP_DESCRIPTOR;
+
+///
+/// Pin Group Function Descriptor
+///
+typedef PACKED struct {
+ ACPI_LARGE_RESOURCE_HEADER Header;
+ UINT8 RevisionId;
+ UINT16 Flags;
+ UINT16 FunctionNumber;
+ UINT8 ResourceSourceIndex;
+ UINT16 ResourceSourceNameOffset;
+ UINT16 ResourceSourceLabelOffset;
+ UINT16 VendorDataOffset;
+ UINT16 VendorDataLength;
+} EFI_ACPI_PIN_GROUP_FUNCTION_DESCRIPTOR;
+
+///
+/// Pin Group Configuration Descriptor
+///
+typedef PACKED struct {
+ ACPI_LARGE_RESOURCE_HEADER Header;
+ UINT8 RevisionId;
+ UINT16 Flags;
+ UINT8 PinConfigurationType;
+ UINT32 PinConfigurationValue;
+ UINT8 ResourceSourceIndex;
+ UINT16 ResourceSourceNameOffset;
+ UINT16 ResourceSourceLabelOffset;
+ UINT16 VendorDataOffset;
+ UINT16 VendorDataLength;
+} EFI_ACPI_PIN_GROUP_CONFIGURATION_DESCRIPTOR;
+
+#pragma pack()
+
+//
+// Ensure proper structure formats
+//
+#pragma pack(1)
+
+///
+/// ACPI 6.2 Generic Address Space definition
+///
+typedef struct {
+ UINT8 AddressSpaceId;
+ UINT8 RegisterBitWidth;
+ UINT8 RegisterBitOffset;
+ UINT8 AccessSize;
+ UINT64 Address;
+} EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE;
+
+//
+// Generic Address Space Address IDs
+//
+#define EFI_ACPI_6_2_SYSTEM_MEMORY 0
+#define EFI_ACPI_6_2_SYSTEM_IO 1
+#define EFI_ACPI_6_2_PCI_CONFIGURATION_SPACE 2
+#define EFI_ACPI_6_2_EMBEDDED_CONTROLLER 3
+#define EFI_ACPI_6_2_SMBUS 4
+#define EFI_ACPI_6_2_PLATFORM_COMMUNICATION_CHANNEL 0x0A
+#define EFI_ACPI_6_2_FUNCTIONAL_FIXED_HARDWARE 0x7F
+
+//
+// Generic Address Space Access Sizes
+//
+#define EFI_ACPI_6_2_UNDEFINED 0
+#define EFI_ACPI_6_2_BYTE 1
+#define EFI_ACPI_6_2_WORD 2
+#define EFI_ACPI_6_2_DWORD 3
+#define EFI_ACPI_6_2_QWORD 4
+
+//
+// ACPI 6.2 table structures
+//
+
+///
+/// Root System Description Pointer Structure
+///
+typedef struct {
+ UINT64 Signature;
+ UINT8 Checksum;
+ UINT8 OemId[6];
+ UINT8 Revision;
+ UINT32 RsdtAddress;
+ UINT32 Length;
+ UINT64 XsdtAddress;
+ UINT8 ExtendedChecksum;
+ UINT8 Reserved[3];
+} EFI_ACPI_6_2_ROOT_SYSTEM_DESCRIPTION_POINTER;
+
+///
+/// RSD_PTR Revision (as defined in ACPI 6.2 spec.)
+///
+#define EFI_ACPI_6_2_ROOT_SYSTEM_DESCRIPTION_POINTER_REVISION 0x02 ///< ACPISpec (Revision 6.2) says current value is 2
+
+///
+/// Common table header, this prefaces all ACPI tables, including FACS, but
+/// excluding the RSD PTR structure
+///
+typedef struct {
+ UINT32 Signature;
+ UINT32 Length;
+} EFI_ACPI_6_2_COMMON_HEADER;
+
+//
+// Root System Description Table
+// No definition needed as it is a common description table header, the same with
+// EFI_ACPI_DESCRIPTION_HEADER, followed by a variable number of UINT32 table pointers.
+//
+
+///
+/// RSDT Revision (as defined in ACPI 6.2 spec.)
+///
+#define EFI_ACPI_6_2_ROOT_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01
+
+//
+// Extended System Description Table
+// No definition needed as it is a common description table header, the same with
+// EFI_ACPI_DESCRIPTION_HEADER, followed by a variable number of UINT64 table pointers.
+//
+
+///
+/// XSDT Revision (as defined in ACPI 6.2 spec.)
+///
+#define EFI_ACPI_6_2_EXTENDED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01
+
+///
+/// Fixed ACPI Description Table Structure (FADT)
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 FirmwareCtrl;
+ UINT32 Dsdt;
+ UINT8 Reserved0;
+ UINT8 PreferredPmProfile;
+ UINT16 SciInt;
+ UINT32 SmiCmd;
+ UINT8 AcpiEnable;
+ UINT8 AcpiDisable;
+ UINT8 S4BiosReq;
+ UINT8 PstateCnt;
+ UINT32 Pm1aEvtBlk;
+ UINT32 Pm1bEvtBlk;
+ UINT32 Pm1aCntBlk;
+ UINT32 Pm1bCntBlk;
+ UINT32 Pm2CntBlk;
+ UINT32 PmTmrBlk;
+ UINT32 Gpe0Blk;
+ UINT32 Gpe1Blk;
+ UINT8 Pm1EvtLen;
+ UINT8 Pm1CntLen;
+ UINT8 Pm2CntLen;
+ UINT8 PmTmrLen;
+ UINT8 Gpe0BlkLen;
+ UINT8 Gpe1BlkLen;
+ UINT8 Gpe1Base;
+ UINT8 CstCnt;
+ UINT16 PLvl2Lat;
+ UINT16 PLvl3Lat;
+ UINT16 FlushSize;
+ UINT16 FlushStride;
+ UINT8 DutyOffset;
+ UINT8 DutyWidth;
+ UINT8 DayAlrm;
+ UINT8 MonAlrm;
+ UINT8 Century;
+ UINT16 IaPcBootArch;
+ UINT8 Reserved1;
+ UINT32 Flags;
+ EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE ResetReg;
+ UINT8 ResetValue;
+ UINT16 ArmBootArch;
+ UINT8 MinorVersion;
+ UINT64 XFirmwareCtrl;
+ UINT64 XDsdt;
+ EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE XPm1aEvtBlk;
+ EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE XPm1bEvtBlk;
+ EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE XPm1aCntBlk;
+ EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE XPm1bCntBlk;
+ EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE XPm2CntBlk;
+ EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE XPmTmrBlk;
+ EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE XGpe0Blk;
+ EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE XGpe1Blk;
+ EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE SleepControlReg;
+ EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE SleepStatusReg;
+ UINT64 HypervisorVendorIdentity;
+} EFI_ACPI_6_2_FIXED_ACPI_DESCRIPTION_TABLE;
+
+///
+/// FADT Version (as defined in ACPI 6.2 spec.)
+///
+#define EFI_ACPI_6_2_FIXED_ACPI_DESCRIPTION_TABLE_REVISION 0x06
+#define EFI_ACPI_6_2_FIXED_ACPI_DESCRIPTION_TABLE_MINOR_REVISION 0x02
+
+//
+// Fixed ACPI Description Table Preferred Power Management Profile
+//
+#define EFI_ACPI_6_2_PM_PROFILE_UNSPECIFIED 0
+#define EFI_ACPI_6_2_PM_PROFILE_DESKTOP 1
+#define EFI_ACPI_6_2_PM_PROFILE_MOBILE 2
+#define EFI_ACPI_6_2_PM_PROFILE_WORKSTATION 3
+#define EFI_ACPI_6_2_PM_PROFILE_ENTERPRISE_SERVER 4
+#define EFI_ACPI_6_2_PM_PROFILE_SOHO_SERVER 5
+#define EFI_ACPI_6_2_PM_PROFILE_APPLIANCE_PC 6
+#define EFI_ACPI_6_2_PM_PROFILE_PERFORMANCE_SERVER 7
+#define EFI_ACPI_6_2_PM_PROFILE_TABLET 8
+
+//
+// Fixed ACPI Description Table Boot Architecture Flags
+// All other bits are reserved and must be set to 0.
+//
+#define EFI_ACPI_6_2_LEGACY_DEVICES BIT0
+#define EFI_ACPI_6_2_8042 BIT1
+#define EFI_ACPI_6_2_VGA_NOT_PRESENT BIT2
+#define EFI_ACPI_6_2_MSI_NOT_SUPPORTED BIT3
+#define EFI_ACPI_6_2_PCIE_ASPM_CONTROLS BIT4
+#define EFI_ACPI_6_2_CMOS_RTC_NOT_PRESENT BIT5
+
+//
+// Fixed ACPI Description Table Arm Boot Architecture Flags
+// All other bits are reserved and must be set to 0.
+//
+#define EFI_ACPI_6_2_ARM_PSCI_COMPLIANT BIT0
+#define EFI_ACPI_6_2_ARM_PSCI_USE_HVC BIT1
+
+//
+// Fixed ACPI Description Table Fixed Feature Flags
+// All other bits are reserved and must be set to 0.
+//
+#define EFI_ACPI_6_2_WBINVD BIT0
+#define EFI_ACPI_6_2_WBINVD_FLUSH BIT1
+#define EFI_ACPI_6_2_PROC_C1 BIT2
+#define EFI_ACPI_6_2_P_LVL2_UP BIT3
+#define EFI_ACPI_6_2_PWR_BUTTON BIT4
+#define EFI_ACPI_6_2_SLP_BUTTON BIT5
+#define EFI_ACPI_6_2_FIX_RTC BIT6
+#define EFI_ACPI_6_2_RTC_S4 BIT7
+#define EFI_ACPI_6_2_TMR_VAL_EXT BIT8
+#define EFI_ACPI_6_2_DCK_CAP BIT9
+#define EFI_ACPI_6_2_RESET_REG_SUP BIT10
+#define EFI_ACPI_6_2_SEALED_CASE BIT11
+#define EFI_ACPI_6_2_HEADLESS BIT12
+#define EFI_ACPI_6_2_CPU_SW_SLP BIT13
+#define EFI_ACPI_6_2_PCI_EXP_WAK BIT14
+#define EFI_ACPI_6_2_USE_PLATFORM_CLOCK BIT15
+#define EFI_ACPI_6_2_S4_RTC_STS_VALID BIT16
+#define EFI_ACPI_6_2_REMOTE_POWER_ON_CAPABLE BIT17
+#define EFI_ACPI_6_2_FORCE_APIC_CLUSTER_MODEL BIT18
+#define EFI_ACPI_6_2_FORCE_APIC_PHYSICAL_DESTINATION_MODE BIT19
+#define EFI_ACPI_6_2_HW_REDUCED_ACPI BIT20
+#define EFI_ACPI_6_2_LOW_POWER_S0_IDLE_CAPABLE BIT21
+
+///
+/// Firmware ACPI Control Structure
+///
+typedef struct {
+ UINT32 Signature;
+ UINT32 Length;
+ UINT32 HardwareSignature;
+ UINT32 FirmwareWakingVector;
+ UINT32 GlobalLock;
+ UINT32 Flags;
+ UINT64 XFirmwareWakingVector;
+ UINT8 Version;
+ UINT8 Reserved0[3];
+ UINT32 OspmFlags;
+ UINT8 Reserved1[24];
+} EFI_ACPI_6_2_FIRMWARE_ACPI_CONTROL_STRUCTURE;
+
+///
+/// FACS Version (as defined in ACPI 6.2 spec.)
+///
+#define EFI_ACPI_6_2_FIRMWARE_ACPI_CONTROL_STRUCTURE_VERSION 0x02
+
+///
+/// Firmware Control Structure Feature Flags
+/// All other bits are reserved and must be set to 0.
+///
+#define EFI_ACPI_6_2_S4BIOS_F BIT0
+#define EFI_ACPI_6_2_64BIT_WAKE_SUPPORTED_F BIT1
+
+///
+/// OSPM Enabled Firmware Control Structure Flags
+/// All other bits are reserved and must be set to 0.
+///
+#define EFI_ACPI_6_2_OSPM_64BIT_WAKE_F BIT0
+
+//
+// Differentiated System Description Table,
+// Secondary System Description Table
+// and Persistent System Description Table,
+// no definition needed as they are common description table header, the same with
+// EFI_ACPI_DESCRIPTION_HEADER, followed by a definition block.
+//
+#define EFI_ACPI_6_2_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x02
+#define EFI_ACPI_6_2_SECONDARY_SYSTEM_DESCRIPTION_TABLE_REVISION 0x02
+
+///
+/// Multiple APIC Description Table header definition. The rest of the table
+/// must be defined in a platform specific manner.
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 LocalApicAddress;
+ UINT32 Flags;
+} EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER;
+
+///
+/// MADT Revision (as defined in ACPI 6.2 spec.)
+///
+#define EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION 0x04
+
+///
+/// Multiple APIC Flags
+/// All other bits are reserved and must be set to 0.
+///
+#define EFI_ACPI_6_2_PCAT_COMPAT BIT0
+
+//
+// Multiple APIC Description Table APIC structure types
+// All other values between 0x0D and 0x7F are reserved and
+// will be ignored by OSPM. 0x80 ~ 0xFF are reserved for OEM.
+//
+#define EFI_ACPI_6_2_PROCESSOR_LOCAL_APIC 0x00
+#define EFI_ACPI_6_2_IO_APIC 0x01
+#define EFI_ACPI_6_2_INTERRUPT_SOURCE_OVERRIDE 0x02
+#define EFI_ACPI_6_2_NON_MASKABLE_INTERRUPT_SOURCE 0x03
+#define EFI_ACPI_6_2_LOCAL_APIC_NMI 0x04
+#define EFI_ACPI_6_2_LOCAL_APIC_ADDRESS_OVERRIDE 0x05
+#define EFI_ACPI_6_2_IO_SAPIC 0x06
+#define EFI_ACPI_6_2_LOCAL_SAPIC 0x07
+#define EFI_ACPI_6_2_PLATFORM_INTERRUPT_SOURCES 0x08
+#define EFI_ACPI_6_2_PROCESSOR_LOCAL_X2APIC 0x09
+#define EFI_ACPI_6_2_LOCAL_X2APIC_NMI 0x0A
+#define EFI_ACPI_6_2_GIC 0x0B
+#define EFI_ACPI_6_2_GICD 0x0C
+#define EFI_ACPI_6_2_GIC_MSI_FRAME 0x0D
+#define EFI_ACPI_6_2_GICR 0x0E
+#define EFI_ACPI_6_2_GIC_ITS 0x0F
+
+//
+// APIC Structure Definitions
+//
+
+///
+/// Processor Local APIC Structure Definition
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 AcpiProcessorUid;
+ UINT8 ApicId;
+ UINT32 Flags;
+} EFI_ACPI_6_2_PROCESSOR_LOCAL_APIC_STRUCTURE;
+
+///
+/// Local APIC Flags. All other bits are reserved and must be 0.
+///
+#define EFI_ACPI_6_2_LOCAL_APIC_ENABLED BIT0
+
+///
+/// IO APIC Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 IoApicId;
+ UINT8 Reserved;
+ UINT32 IoApicAddress;
+ UINT32 GlobalSystemInterruptBase;
+} EFI_ACPI_6_2_IO_APIC_STRUCTURE;
+
+///
+/// Interrupt Source Override Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 Bus;
+ UINT8 Source;
+ UINT32 GlobalSystemInterrupt;
+ UINT16 Flags;
+} EFI_ACPI_6_2_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE;
+
+///
+/// Platform Interrupt Sources Structure Definition
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Flags;
+ UINT8 InterruptType;
+ UINT8 ProcessorId;
+ UINT8 ProcessorEid;
+ UINT8 IoSapicVector;
+ UINT32 GlobalSystemInterrupt;
+ UINT32 PlatformInterruptSourceFlags;
+ UINT8 CpeiProcessorOverride;
+ UINT8 Reserved[31];
+} EFI_ACPI_6_2_PLATFORM_INTERRUPT_APIC_STRUCTURE;
+
+//
+// MPS INTI flags.
+// All other bits are reserved and must be set to 0.
+//
+#define EFI_ACPI_6_2_POLARITY (3 << 0)
+#define EFI_ACPI_6_2_TRIGGER_MODE (3 << 2)
+
+///
+/// Non-Maskable Interrupt Source Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Flags;
+ UINT32 GlobalSystemInterrupt;
+} EFI_ACPI_6_2_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE;
+
+///
+/// Local APIC NMI Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 AcpiProcessorUid;
+ UINT16 Flags;
+ UINT8 LocalApicLint;
+} EFI_ACPI_6_2_LOCAL_APIC_NMI_STRUCTURE;
+
+///
+/// Local APIC Address Override Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Reserved;
+ UINT64 LocalApicAddress;
+} EFI_ACPI_6_2_LOCAL_APIC_ADDRESS_OVERRIDE_STRUCTURE;
+
+///
+/// IO SAPIC Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 IoApicId;
+ UINT8 Reserved;
+ UINT32 GlobalSystemInterruptBase;
+ UINT64 IoSapicAddress;
+} EFI_ACPI_6_2_IO_SAPIC_STRUCTURE;
+
+///
+/// Local SAPIC Structure
+/// This struct followed by a null-terminated ASCII string - ACPI Processor UID String
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 AcpiProcessorId;
+ UINT8 LocalSapicId;
+ UINT8 LocalSapicEid;
+ UINT8 Reserved[3];
+ UINT32 Flags;
+ UINT32 ACPIProcessorUIDValue;
+} EFI_ACPI_6_2_PROCESSOR_LOCAL_SAPIC_STRUCTURE;
+
+///
+/// Platform Interrupt Sources Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Flags;
+ UINT8 InterruptType;
+ UINT8 ProcessorId;
+ UINT8 ProcessorEid;
+ UINT8 IoSapicVector;
+ UINT32 GlobalSystemInterrupt;
+ UINT32 PlatformInterruptSourceFlags;
+} EFI_ACPI_6_2_PLATFORM_INTERRUPT_SOURCES_STRUCTURE;
+
+///
+/// Platform Interrupt Source Flags.
+/// All other bits are reserved and must be set to 0.
+///
+#define EFI_ACPI_6_2_CPEI_PROCESSOR_OVERRIDE BIT0
+
+///
+/// Processor Local x2APIC Structure Definition
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 Reserved[2];
+ UINT32 X2ApicId;
+ UINT32 Flags;
+ UINT32 AcpiProcessorUid;
+} EFI_ACPI_6_2_PROCESSOR_LOCAL_X2APIC_STRUCTURE;
+
+///
+/// Local x2APIC NMI Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Flags;
+ UINT32 AcpiProcessorUid;
+ UINT8 LocalX2ApicLint;
+ UINT8 Reserved[3];
+} EFI_ACPI_6_2_LOCAL_X2APIC_NMI_STRUCTURE;
+
+///
+/// GIC Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Reserved;
+ UINT32 CPUInterfaceNumber;
+ UINT32 AcpiProcessorUid;
+ UINT32 Flags;
+ UINT32 ParkingProtocolVersion;
+ UINT32 PerformanceInterruptGsiv;
+ UINT64 ParkedAddress;
+ UINT64 PhysicalBaseAddress;
+ UINT64 GICV;
+ UINT64 GICH;
+ UINT32 VGICMaintenanceInterrupt;
+ UINT64 GICRBaseAddress;
+ UINT64 MPIDR;
+ UINT8 ProcessorPowerEfficiencyClass;
+ UINT8 Reserved2[3];
+} EFI_ACPI_6_2_GIC_STRUCTURE;
+
+///
+/// GIC Flags. All other bits are reserved and must be 0.
+///
+#define EFI_ACPI_6_2_GIC_ENABLED BIT0
+#define EFI_ACPI_6_2_PERFORMANCE_INTERRUPT_MODEL BIT1
+#define EFI_ACPI_6_2_VGIC_MAINTENANCE_INTERRUPT_MODE_FLAGS BIT2
+
+///
+/// GIC Distributor Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Reserved1;
+ UINT32 GicId;
+ UINT64 PhysicalBaseAddress;
+ UINT32 SystemVectorBase;
+ UINT8 GicVersion;
+ UINT8 Reserved2[3];
+} EFI_ACPI_6_2_GIC_DISTRIBUTOR_STRUCTURE;
+
+///
+/// GIC Version
+///
+#define EFI_ACPI_6_2_GIC_V1 0x01
+#define EFI_ACPI_6_2_GIC_V2 0x02
+#define EFI_ACPI_6_2_GIC_V3 0x03
+#define EFI_ACPI_6_2_GIC_V4 0x04
+
+///
+/// GIC MSI Frame Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Reserved1;
+ UINT32 GicMsiFrameId;
+ UINT64 PhysicalBaseAddress;
+ UINT32 Flags;
+ UINT16 SPICount;
+ UINT16 SPIBase;
+} EFI_ACPI_6_2_GIC_MSI_FRAME_STRUCTURE;
+
+///
+/// GIC MSI Frame Flags. All other bits are reserved and must be 0.
+///
+#define EFI_ACPI_6_2_SPI_COUNT_BASE_SELECT BIT0
+
+///
+/// GICR Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Reserved;
+ UINT64 DiscoveryRangeBaseAddress;
+ UINT32 DiscoveryRangeLength;
+} EFI_ACPI_6_2_GICR_STRUCTURE;
+
+///
+/// GIC Interrupt Translation Service Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Reserved;
+ UINT32 GicItsId;
+ UINT64 PhysicalBaseAddress;
+ UINT32 Reserved2;
+} EFI_ACPI_6_2_GIC_ITS_STRUCTURE;
+
+///
+/// Smart Battery Description Table (SBST)
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 WarningEnergyLevel;
+ UINT32 LowEnergyLevel;
+ UINT32 CriticalEnergyLevel;
+} EFI_ACPI_6_2_SMART_BATTERY_DESCRIPTION_TABLE;
+
+///
+/// SBST Version (as defined in ACPI 6.2 spec.)
+///
+#define EFI_ACPI_6_2_SMART_BATTERY_DESCRIPTION_TABLE_REVISION 0x01
+
+///
+/// Embedded Controller Boot Resources Table (ECDT)
+/// The table is followed by a null terminated ASCII string that contains
+/// a fully qualified reference to the name space object.
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE EcControl;
+ EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE EcData;
+ UINT32 Uid;
+ UINT8 GpeBit;
+} EFI_ACPI_6_2_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE;
+
+///
+/// ECDT Version (as defined in ACPI 6.2 spec.)
+///
+#define EFI_ACPI_6_2_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE_REVISION 0x01
+
+///
+/// System Resource Affinity Table (SRAT). The rest of the table
+/// must be defined in a platform specific manner.
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 Reserved1; ///< Must be set to 1
+ UINT64 Reserved2;
+} EFI_ACPI_6_2_SYSTEM_RESOURCE_AFFINITY_TABLE_HEADER;
+
+///
+/// SRAT Version (as defined in ACPI 6.2 spec.)
+///
+#define EFI_ACPI_6_2_SYSTEM_RESOURCE_AFFINITY_TABLE_REVISION 0x03
+
+//
+// SRAT structure types.
+// All other values between 0x05 an 0xFF are reserved and
+// will be ignored by OSPM.
+//
+#define EFI_ACPI_6_2_PROCESSOR_LOCAL_APIC_SAPIC_AFFINITY 0x00
+#define EFI_ACPI_6_2_MEMORY_AFFINITY 0x01
+#define EFI_ACPI_6_2_PROCESSOR_LOCAL_X2APIC_AFFINITY 0x02
+#define EFI_ACPI_6_2_GICC_AFFINITY 0x03
+#define EFI_ACPI_6_2_GIC_ITS_AFFINITY 0x04
+
+///
+/// Processor Local APIC/SAPIC Affinity Structure Definition
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 ProximityDomain7To0;
+ UINT8 ApicId;
+ UINT32 Flags;
+ UINT8 LocalSapicEid;
+ UINT8 ProximityDomain31To8[3];
+ UINT32 ClockDomain;
+} EFI_ACPI_6_2_PROCESSOR_LOCAL_APIC_SAPIC_AFFINITY_STRUCTURE;
+
+///
+/// Local APIC/SAPIC Flags. All other bits are reserved and must be 0.
+///
+#define EFI_ACPI_6_2_PROCESSOR_LOCAL_APIC_SAPIC_ENABLED (1 << 0)
+
+///
+/// Memory Affinity Structure Definition
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT32 ProximityDomain;
+ UINT16 Reserved1;
+ UINT32 AddressBaseLow;
+ UINT32 AddressBaseHigh;
+ UINT32 LengthLow;
+ UINT32 LengthHigh;
+ UINT32 Reserved2;
+ UINT32 Flags;
+ UINT64 Reserved3;
+} EFI_ACPI_6_2_MEMORY_AFFINITY_STRUCTURE;
+
+//
+// Memory Flags. All other bits are reserved and must be 0.
+//
+#define EFI_ACPI_6_2_MEMORY_ENABLED (1 << 0)
+#define EFI_ACPI_6_2_MEMORY_HOT_PLUGGABLE (1 << 1)
+#define EFI_ACPI_6_2_MEMORY_NONVOLATILE (1 << 2)
+
+///
+/// Processor Local x2APIC Affinity Structure Definition
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 Reserved1[2];
+ UINT32 ProximityDomain;
+ UINT32 X2ApicId;
+ UINT32 Flags;
+ UINT32 ClockDomain;
+ UINT8 Reserved2[4];
+} EFI_ACPI_6_2_PROCESSOR_LOCAL_X2APIC_AFFINITY_STRUCTURE;
+
+///
+/// GICC Affinity Structure Definition
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT32 ProximityDomain;
+ UINT32 AcpiProcessorUid;
+ UINT32 Flags;
+ UINT32 ClockDomain;
+} EFI_ACPI_6_2_GICC_AFFINITY_STRUCTURE;
+
+///
+/// GICC Flags. All other bits are reserved and must be 0.
+///
+#define EFI_ACPI_6_2_GICC_ENABLED (1 << 0)
+
+///
+/// GIC Interrupt Translation Service (ITS) Affinity Structure Definition
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT32 ProximityDomain;
+ UINT8 Reserved[2];
+ UINT32 ItsId;
+} EFI_ACPI_6_2_GIC_ITS_AFFINITY_STRUCTURE;
+
+///
+/// System Locality Distance Information Table (SLIT).
+/// The rest of the table is a matrix.
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT64 NumberOfSystemLocalities;
+} EFI_ACPI_6_2_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_HEADER;
+
+///
+/// SLIT Version (as defined in ACPI 6.2 spec.)
+///
+#define EFI_ACPI_6_2_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_REVISION 0x01
+
+///
+/// Corrected Platform Error Polling Table (CPEP)
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT8 Reserved[8];
+} EFI_ACPI_6_2_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_HEADER;
+
+///
+/// CPEP Version (as defined in ACPI 6.2 spec.)
+///
+#define EFI_ACPI_6_2_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_REVISION 0x01
+
+//
+// CPEP processor structure types.
+//
+#define EFI_ACPI_6_2_CPEP_PROCESSOR_APIC_SAPIC 0x00
+
+///
+/// Corrected Platform Error Polling Processor Structure Definition
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 ProcessorId;
+ UINT8 ProcessorEid;
+ UINT32 PollingInterval;
+} EFI_ACPI_6_2_CPEP_PROCESSOR_APIC_SAPIC_STRUCTURE;
+
+///
+/// Maximum System Characteristics Table (MSCT)
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 OffsetProxDomInfo;
+ UINT32 MaximumNumberOfProximityDomains;
+ UINT32 MaximumNumberOfClockDomains;
+ UINT64 MaximumPhysicalAddress;
+} EFI_ACPI_6_2_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_HEADER;
+
+///
+/// MSCT Version (as defined in ACPI 6.2 spec.)
+///
+#define EFI_ACPI_6_2_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_REVISION 0x01
+
+///
+/// Maximum Proximity Domain Information Structure Definition
+///
+typedef struct {
+ UINT8 Revision;
+ UINT8 Length;
+ UINT32 ProximityDomainRangeLow;
+ UINT32 ProximityDomainRangeHigh;
+ UINT32 MaximumProcessorCapacity;
+ UINT64 MaximumMemoryCapacity;
+} EFI_ACPI_6_2_MAXIMUM_PROXIMITY_DOMAIN_INFORMATION_STRUCTURE;
+
+///
+/// ACPI RAS Feature Table definition.
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT8 PlatformCommunicationChannelIdentifier[12];
+} EFI_ACPI_6_2_RAS_FEATURE_TABLE;
+
+///
+/// RASF Version (as defined in ACPI 6.2 spec.)
+///
+#define EFI_ACPI_6_2_RAS_FEATURE_TABLE_REVISION 0x01
+
+///
+/// ACPI RASF Platform Communication Channel Shared Memory Region definition.
+///
+typedef struct {
+ UINT32 Signature;
+ UINT16 Command;
+ UINT16 Status;
+ UINT16 Version;
+ UINT8 RASCapabilities[16];
+ UINT8 SetRASCapabilities[16];
+ UINT16 NumberOfRASFParameterBlocks;
+ UINT32 SetRASCapabilitiesStatus;
+} EFI_ACPI_6_2_RASF_PLATFORM_COMMUNICATION_CHANNEL_SHARED_MEMORY_REGION;
+
+///
+/// ACPI RASF PCC command code
+///
+#define EFI_ACPI_6_2_RASF_PCC_COMMAND_CODE_EXECUTE_RASF_COMMAND 0x01
+
+///
+/// ACPI RASF Platform RAS Capabilities
+///
+#define EFI_ACPI_6_2_RASF_PLATFORM_RAS_CAPABILITY_HARDWARE_BASED_PATROL_SCRUB_SUPPORTED BIT0
+#define EFI_ACPI_6_2_RASF_PLATFORM_RAS_CAPABILITY_HARDWARE_BASED_PATROL_SCRUB_SUPPORTED_AND_EXPOSED_TO_SOFTWARE BIT1
+#define EFI_ACPI_6_2_RASF_PLATFORM_RAS_CAPABILITY_CPU_CACHE_FLUSH_TO_NVDIMM_DURABILITY_ON_POWER_LOSS BIT2
+#define EFI_ACPI_6_2_RASF_PLATFORM_RAS_CAPABILITY_MEMORY_CONTROLLER_FLUSH_TO_NVDIMM_DURABILITY_ON_POWER_LOSS BIT3
+#define EFI_ACPI_6_2_RASF_PLATFORM_RAS_CAPABILITY_BYTE_ADDRESSABLE_PERSISTENT_MEMORY_HARDWARE_MIRRORING BIT4
+
+///
+/// ACPI RASF Parameter Block structure for PATROL_SCRUB
+///
+typedef struct {
+ UINT16 Type;
+ UINT16 Version;
+ UINT16 Length;
+ UINT16 PatrolScrubCommand;
+ UINT64 RequestedAddressRange[2];
+ UINT64 ActualAddressRange[2];
+ UINT16 Flags;
+ UINT8 RequestedSpeed;
+} EFI_ACPI_6_2_RASF_PATROL_SCRUB_PLATFORM_BLOCK_STRUCTURE;
+
+///
+/// ACPI RASF Patrol Scrub command
+///
+#define EFI_ACPI_6_2_RASF_PATROL_SCRUB_COMMAND_GET_PATROL_PARAMETERS 0x01
+#define EFI_ACPI_6_2_RASF_PATROL_SCRUB_COMMAND_START_PATROL_SCRUBBER 0x02
+#define EFI_ACPI_6_2_RASF_PATROL_SCRUB_COMMAND_STOP_PATROL_SCRUBBER 0x03
+
+///
+/// Memory Power State Table definition.
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT8 PlatformCommunicationChannelIdentifier;
+ UINT8 Reserved[3];
+ // Memory Power Node Structure
+ // Memory Power State Characteristics
+} EFI_ACPI_6_2_MEMORY_POWER_STATUS_TABLE;
+
+///
+/// MPST Version (as defined in ACPI 6.2 spec.)
+///
+#define EFI_ACPI_6_2_MEMORY_POWER_STATE_TABLE_REVISION 0x01
+
+///
+/// MPST Platform Communication Channel Shared Memory Region definition.
+///
+typedef struct {
+ UINT32 Signature;
+ UINT16 Command;
+ UINT16 Status;
+ UINT32 MemoryPowerCommandRegister;
+ UINT32 MemoryPowerStatusRegister;
+ UINT32 PowerStateId;
+ UINT32 MemoryPowerNodeId;
+ UINT64 MemoryEnergyConsumed;
+ UINT64 ExpectedAveragePowerComsuned;
+} EFI_ACPI_6_2_MPST_PLATFORM_COMMUNICATION_CHANNEL_SHARED_MEMORY_REGION;
+
+///
+/// ACPI MPST PCC command code
+///
+#define EFI_ACPI_6_2_MPST_PCC_COMMAND_CODE_EXECUTE_MPST_COMMAND 0x03
+
+///
+/// ACPI MPST Memory Power command
+///
+#define EFI_ACPI_6_2_MPST_MEMORY_POWER_COMMAND_GET_MEMORY_POWER_STATE 0x01
+#define EFI_ACPI_6_2_MPST_MEMORY_POWER_COMMAND_SET_MEMORY_POWER_STATE 0x02
+#define EFI_ACPI_6_2_MPST_MEMORY_POWER_COMMAND_GET_AVERAGE_POWER_CONSUMED 0x03
+#define EFI_ACPI_6_2_MPST_MEMORY_POWER_COMMAND_GET_MEMORY_ENERGY_CONSUMED 0x04
+
+///
+/// MPST Memory Power Node Table
+///
+typedef struct {
+ UINT8 PowerStateValue;
+ UINT8 PowerStateInformationIndex;
+} EFI_ACPI_6_2_MPST_MEMORY_POWER_STATE;
+
+typedef struct {
+ UINT8 Flag;
+ UINT8 Reserved;
+ UINT16 MemoryPowerNodeId;
+ UINT32 Length;
+ UINT64 AddressBase;
+ UINT64 AddressLength;
+ UINT32 NumberOfPowerStates;
+ UINT32 NumberOfPhysicalComponents;
+ // EFI_ACPI_6_2_MPST_MEMORY_POWER_STATE MemoryPowerState[NumberOfPowerStates];
+ // UINT16 PhysicalComponentIdentifier[NumberOfPhysicalComponents];
+} EFI_ACPI_6_2_MPST_MEMORY_POWER_STRUCTURE;
+
+#define EFI_ACPI_6_2_MPST_MEMORY_POWER_STRUCTURE_FLAG_ENABLE 0x01
+#define EFI_ACPI_6_2_MPST_MEMORY_POWER_STRUCTURE_FLAG_POWER_MANAGED 0x02
+#define EFI_ACPI_6_2_MPST_MEMORY_POWER_STRUCTURE_FLAG_HOT_PLUGGABLE 0x04
+
+typedef struct {
+ UINT16 MemoryPowerNodeCount;
+ UINT8 Reserved[2];
+} EFI_ACPI_6_2_MPST_MEMORY_POWER_NODE_TABLE;
+
+///
+/// MPST Memory Power State Characteristics Table
+///
+typedef struct {
+ UINT8 PowerStateStructureID;
+ UINT8 Flag;
+ UINT16 Reserved;
+ UINT32 AveragePowerConsumedInMPS0;
+ UINT32 RelativePowerSavingToMPS0;
+ UINT64 ExitLatencyToMPS0;
+} EFI_ACPI_6_2_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE;
+
+#define EFI_ACPI_6_2_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_MEMORY_CONTENT_PRESERVED 0x01
+#define EFI_ACPI_6_2_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_AUTONOMOUS_MEMORY_POWER_STATE_ENTRY 0x02
+#define EFI_ACPI_6_2_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_AUTONOMOUS_MEMORY_POWER_STATE_EXIT 0x04
+
+typedef struct {
+ UINT16 MemoryPowerStateCharacteristicsCount;
+ UINT8 Reserved[2];
+} EFI_ACPI_6_2_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_TABLE;
+
+///
+/// Memory Topology Table definition.
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 Reserved;
+} EFI_ACPI_6_2_MEMORY_TOPOLOGY_TABLE;
+
+///
+/// PMTT Version (as defined in ACPI 6.2 spec.)
+///
+#define EFI_ACPI_6_2_MEMORY_TOPOLOGY_TABLE_REVISION 0x01
+
+///
+/// Common Memory Aggregator Device Structure.
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Reserved;
+ UINT16 Length;
+ UINT16 Flags;
+ UINT16 Reserved1;
+} EFI_ACPI_6_2_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE;
+
+///
+/// Memory Aggregator Device Type
+///
+#define EFI_ACPI_6_2_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_SOCKET 0x0
+#define EFI_ACPI_6_2_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_MEMORY_CONTROLLER 0x1
+#define EFI_ACPI_6_2_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_DIMM 0x2
+
+///
+/// Socket Memory Aggregator Device Structure.
+///
+typedef struct {
+ EFI_ACPI_6_2_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE Header;
+ UINT16 SocketIdentifier;
+ UINT16 Reserved;
+ // EFI_ACPI_6_2_PMMT_MEMORY_CONTROLLER_MEMORY_AGGREGATOR_DEVICE_STRUCTURE MemoryController[];
+} EFI_ACPI_6_2_PMMT_SOCKET_MEMORY_AGGREGATOR_DEVICE_STRUCTURE;
+
+///
+/// MemoryController Memory Aggregator Device Structure.
+///
+typedef struct {
+ EFI_ACPI_6_2_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE Header;
+ UINT32 ReadLatency;
+ UINT32 WriteLatency;
+ UINT32 ReadBandwidth;
+ UINT32 WriteBandwidth;
+ UINT16 OptimalAccessUnit;
+ UINT16 OptimalAccessAlignment;
+ UINT16 Reserved;
+ UINT16 NumberOfProximityDomains;
+ // UINT32 ProximityDomain[NumberOfProximityDomains];
+ // EFI_ACPI_6_2_PMMT_DIMM_MEMORY_AGGREGATOR_DEVICE_STRUCTURE PhysicalComponent[];
+} EFI_ACPI_6_2_PMMT_MEMORY_CONTROLLER_MEMORY_AGGREGATOR_DEVICE_STRUCTURE;
+
+///
+/// DIMM Memory Aggregator Device Structure.
+///
+typedef struct {
+ EFI_ACPI_6_2_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE Header;
+ UINT16 PhysicalComponentIdentifier;
+ UINT16 Reserved;
+ UINT32 SizeOfDimm;
+ UINT32 SmbiosHandle;
+} EFI_ACPI_6_2_PMMT_DIMM_MEMORY_AGGREGATOR_DEVICE_STRUCTURE;
+
+///
+/// Boot Graphics Resource Table definition.
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ ///
+ /// 2-bytes (16 bit) version ID. This value must be 1.
+ ///
+ UINT16 Version;
+ ///
+ /// 1-byte status field indicating current status about the table.
+ /// Bits[7:1] = Reserved (must be zero)
+ /// Bit [0] = Valid. A one indicates the boot image graphic is valid.
+ ///
+ UINT8 Status;
+ ///
+ /// 1-byte enumerated type field indicating format of the image.
+ /// 0 = Bitmap
+ /// 1 - 255 Reserved (for future use)
+ ///
+ UINT8 ImageType;
+ ///
+ /// 8-byte (64 bit) physical address pointing to the firmware's in-memory copy
+ /// of the image bitmap.
+ ///
+ UINT64 ImageAddress;
+ ///
+ /// A 4-byte (32-bit) unsigned long describing the display X-offset of the boot image.
+ /// (X, Y) display offset of the top left corner of the boot image.
+ /// The top left corner of the display is at offset (0, 0).
+ ///
+ UINT32 ImageOffsetX;
+ ///
+ /// A 4-byte (32-bit) unsigned long describing the display Y-offset of the boot image.
+ /// (X, Y) display offset of the top left corner of the boot image.
+ /// The top left corner of the display is at offset (0, 0).
+ ///
+ UINT32 ImageOffsetY;
+} EFI_ACPI_6_2_BOOT_GRAPHICS_RESOURCE_TABLE;
+
+///
+/// BGRT Revision
+///
+#define EFI_ACPI_6_2_BOOT_GRAPHICS_RESOURCE_TABLE_REVISION 1
+
+///
+/// BGRT Version
+///
+#define EFI_ACPI_6_2_BGRT_VERSION 0x01
+
+///
+/// BGRT Status
+///
+#define EFI_ACPI_6_2_BGRT_STATUS_NOT_DISPLAYED 0x00
+#define EFI_ACPI_6_2_BGRT_STATUS_DISPLAYED 0x01
+
+///
+/// BGRT Image Type
+///
+#define EFI_ACPI_6_2_BGRT_IMAGE_TYPE_BMP 0x00
+
+///
+/// FPDT Version (as defined in ACPI 6.2 spec.)
+///
+#define EFI_ACPI_6_2_FIRMWARE_PERFORMANCE_DATA_TABLE_REVISION 0x01
+
+///
+/// FPDT Performance Record Types
+///
+#define EFI_ACPI_6_2_FPDT_RECORD_TYPE_FIRMWARE_BASIC_BOOT_POINTER 0x0000
+#define EFI_ACPI_6_2_FPDT_RECORD_TYPE_S3_PERFORMANCE_TABLE_POINTER 0x0001
+
+///
+/// FPDT Performance Record Revision
+///
+#define EFI_ACPI_6_2_FPDT_RECORD_REVISION_FIRMWARE_BASIC_BOOT_POINTER 0x01
+#define EFI_ACPI_6_2_FPDT_RECORD_REVISION_S3_PERFORMANCE_TABLE_POINTER 0x01
+
+///
+/// FPDT Runtime Performance Record Types
+///
+#define EFI_ACPI_6_2_FPDT_RUNTIME_RECORD_TYPE_S3_RESUME 0x0000
+#define EFI_ACPI_6_2_FPDT_RUNTIME_RECORD_TYPE_S3_SUSPEND 0x0001
+#define EFI_ACPI_6_2_FPDT_RUNTIME_RECORD_TYPE_FIRMWARE_BASIC_BOOT 0x0002
+
+///
+/// FPDT Runtime Performance Record Revision
+///
+#define EFI_ACPI_6_2_FPDT_RUNTIME_RECORD_REVISION_S3_RESUME 0x01
+#define EFI_ACPI_6_2_FPDT_RUNTIME_RECORD_REVISION_S3_SUSPEND 0x01
+#define EFI_ACPI_6_2_FPDT_RUNTIME_RECORD_REVISION_FIRMWARE_BASIC_BOOT 0x02
+
+///
+/// FPDT Performance Record header
+///
+typedef struct {
+ UINT16 Type;
+ UINT8 Length;
+ UINT8 Revision;
+} EFI_ACPI_6_2_FPDT_PERFORMANCE_RECORD_HEADER;
+
+///
+/// FPDT Performance Table header
+///
+typedef struct {
+ UINT32 Signature;
+ UINT32 Length;
+} EFI_ACPI_6_2_FPDT_PERFORMANCE_TABLE_HEADER;
+
+///
+/// FPDT Firmware Basic Boot Performance Pointer Record Structure
+///
+typedef struct {
+ EFI_ACPI_6_2_FPDT_PERFORMANCE_RECORD_HEADER Header;
+ UINT32 Reserved;
+ ///
+ /// 64-bit processor-relative physical address of the Basic Boot Performance Table.
+ ///
+ UINT64 BootPerformanceTablePointer;
+} EFI_ACPI_6_2_FPDT_BOOT_PERFORMANCE_TABLE_POINTER_RECORD;
+
+///
+/// FPDT S3 Performance Table Pointer Record Structure
+///
+typedef struct {
+ EFI_ACPI_6_2_FPDT_PERFORMANCE_RECORD_HEADER Header;
+ UINT32 Reserved;
+ ///
+ /// 64-bit processor-relative physical address of the S3 Performance Table.
+ ///
+ UINT64 S3PerformanceTablePointer;
+} EFI_ACPI_6_2_FPDT_S3_PERFORMANCE_TABLE_POINTER_RECORD;
+
+///
+/// FPDT Firmware Basic Boot Performance Record Structure
+///
+typedef struct {
+ EFI_ACPI_6_2_FPDT_PERFORMANCE_RECORD_HEADER Header;
+ UINT32 Reserved;
+ ///
+ /// Timer value logged at the beginning of firmware image execution.
+ /// This may not always be zero or near zero.
+ ///
+ UINT64 ResetEnd;
+ ///
+ /// Timer value logged just prior to loading the OS boot loader into memory.
+ /// For non-UEFI compatible boots, this field must be zero.
+ ///
+ UINT64 OsLoaderLoadImageStart;
+ ///
+ /// Timer value logged just prior to launching the previously loaded OS boot loader image.
+ /// For non-UEFI compatible boots, the timer value logged will be just prior
+ /// to the INT 19h handler invocation.
+ ///
+ UINT64 OsLoaderStartImageStart;
+ ///
+ /// Timer value logged at the point when the OS loader calls the
+ /// ExitBootServices function for UEFI compatible firmware.
+ /// For non-UEFI compatible boots, this field must be zero.
+ ///
+ UINT64 ExitBootServicesEntry;
+ ///
+ /// Timer value logged at the point just prior to when the OS loader gaining
+ /// control back from calls the ExitBootServices function for UEFI compatible firmware.
+ /// For non-UEFI compatible boots, this field must be zero.
+ ///
+ UINT64 ExitBootServicesExit;
+} EFI_ACPI_6_2_FPDT_FIRMWARE_BASIC_BOOT_RECORD;
+
+///
+/// FPDT Firmware Basic Boot Performance Table signature
+///
+#define EFI_ACPI_6_2_FPDT_BOOT_PERFORMANCE_TABLE_SIGNATURE SIGNATURE_32('F', 'B', 'P', 'T')
+
+//
+// FPDT Firmware Basic Boot Performance Table
+//
+typedef struct {
+ EFI_ACPI_6_2_FPDT_PERFORMANCE_TABLE_HEADER Header;
+ //
+ // one or more Performance Records.
+ //
+} EFI_ACPI_6_2_FPDT_FIRMWARE_BASIC_BOOT_TABLE;
+
+///
+/// FPDT "S3PT" S3 Performance Table
+///
+#define EFI_ACPI_6_2_FPDT_S3_PERFORMANCE_TABLE_SIGNATURE SIGNATURE_32('S', '3', 'P', 'T')
+
+//
+// FPDT Firmware S3 Boot Performance Table
+//
+typedef struct {
+ EFI_ACPI_6_2_FPDT_PERFORMANCE_TABLE_HEADER Header;
+ //
+ // one or more Performance Records.
+ //
+} EFI_ACPI_6_2_FPDT_FIRMWARE_S3_BOOT_TABLE;
+
+///
+/// FPDT Basic S3 Resume Performance Record
+///
+typedef struct {
+ EFI_ACPI_6_2_FPDT_PERFORMANCE_RECORD_HEADER Header;
+ ///
+ /// A count of the number of S3 resume cycles since the last full boot sequence.
+ ///
+ UINT32 ResumeCount;
+ ///
+ /// Timer recorded at the end of BIOS S3 resume, just prior to handoff to the
+ /// OS waking vector. Only the most recent resume cycle's time is retained.
+ ///
+ UINT64 FullResume;
+ ///
+ /// Average timer value of all resume cycles logged since the last full boot
+ /// sequence, including the most recent resume. Note that the entire log of
+ /// timer values does not need to be retained in order to calculate this average.
+ ///
+ UINT64 AverageResume;
+} EFI_ACPI_6_2_FPDT_S3_RESUME_RECORD;
+
+///
+/// FPDT Basic S3 Suspend Performance Record
+///
+typedef struct {
+ EFI_ACPI_6_2_FPDT_PERFORMANCE_RECORD_HEADER Header;
+ ///
+ /// Timer value recorded at the OS write to SLP_TYP upon entry to S3.
+ /// Only the most recent suspend cycle's timer value is retained.
+ ///
+ UINT64 SuspendStart;
+ ///
+ /// Timer value recorded at the final firmware write to SLP_TYP (or other
+ /// mechanism) used to trigger hardware entry to S3.
+ /// Only the most recent suspend cycle's timer value is retained.
+ ///
+ UINT64 SuspendEnd;
+} EFI_ACPI_6_2_FPDT_S3_SUSPEND_RECORD;
+
+///
+/// Firmware Performance Record Table definition.
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+} EFI_ACPI_6_2_FIRMWARE_PERFORMANCE_RECORD_TABLE;
+
+///
+/// Generic Timer Description Table definition.
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT64 CntControlBasePhysicalAddress;
+ UINT32 Reserved;
+ UINT32 SecurePL1TimerGSIV;
+ UINT32 SecurePL1TimerFlags;
+ UINT32 NonSecurePL1TimerGSIV;
+ UINT32 NonSecurePL1TimerFlags;
+ UINT32 VirtualTimerGSIV;
+ UINT32 VirtualTimerFlags;
+ UINT32 NonSecurePL2TimerGSIV;
+ UINT32 NonSecurePL2TimerFlags;
+ UINT64 CntReadBasePhysicalAddress;
+ UINT32 PlatformTimerCount;
+ UINT32 PlatformTimerOffset;
+} EFI_ACPI_6_2_GENERIC_TIMER_DESCRIPTION_TABLE;
+
+///
+/// GTDT Version (as defined in ACPI 6.2 spec.)
+///
+#define EFI_ACPI_6_2_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION 0x02
+
+///
+/// Timer Flags. All other bits are reserved and must be 0.
+///
+#define EFI_ACPI_6_2_GTDT_TIMER_FLAG_TIMER_INTERRUPT_MODE BIT0
+#define EFI_ACPI_6_2_GTDT_TIMER_FLAG_TIMER_INTERRUPT_POLARITY BIT1
+#define EFI_ACPI_6_2_GTDT_TIMER_FLAG_ALWAYS_ON_CAPABILITY BIT2
+
+///
+/// Platform Timer Type
+///
+#define EFI_ACPI_6_2_GTDT_GT_BLOCK 0
+#define EFI_ACPI_6_2_GTDT_SBSA_GENERIC_WATCHDOG 1
+
+///
+/// GT Block Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT16 Length;
+ UINT8 Reserved;
+ UINT64 CntCtlBase;
+ UINT32 GTBlockTimerCount;
+ UINT32 GTBlockTimerOffset;
+} EFI_ACPI_6_2_GTDT_GT_BLOCK_STRUCTURE;
+
+///
+/// GT Block Timer Structure
+///
+typedef struct {
+ UINT8 GTFrameNumber;
+ UINT8 Reserved[3];
+ UINT64 CntBaseX;
+ UINT64 CntEL0BaseX;
+ UINT32 GTxPhysicalTimerGSIV;
+ UINT32 GTxPhysicalTimerFlags;
+ UINT32 GTxVirtualTimerGSIV;
+ UINT32 GTxVirtualTimerFlags;
+ UINT32 GTxCommonFlags;
+} EFI_ACPI_6_2_GTDT_GT_BLOCK_TIMER_STRUCTURE;
+
+///
+/// GT Block Physical Timers and Virtual Timers Flags. All other bits are reserved and must be 0.
+///
+#define EFI_ACPI_6_2_GTDT_GT_BLOCK_TIMER_FLAG_TIMER_INTERRUPT_MODE BIT0
+#define EFI_ACPI_6_2_GTDT_GT_BLOCK_TIMER_FLAG_TIMER_INTERRUPT_POLARITY BIT1
+
+///
+/// Common Flags Flags. All other bits are reserved and must be 0.
+///
+#define EFI_ACPI_6_2_GTDT_GT_BLOCK_COMMON_FLAG_SECURE_TIMER BIT0
+#define EFI_ACPI_6_2_GTDT_GT_BLOCK_COMMON_FLAG_ALWAYS_ON_CAPABILITY BIT1
+
+///
+/// SBSA Generic Watchdog Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT16 Length;
+ UINT8 Reserved;
+ UINT64 RefreshFramePhysicalAddress;
+ UINT64 WatchdogControlFramePhysicalAddress;
+ UINT32 WatchdogTimerGSIV;
+ UINT32 WatchdogTimerFlags;
+} EFI_ACPI_6_2_GTDT_SBSA_GENERIC_WATCHDOG_STRUCTURE;
+
+///
+/// SBSA Generic Watchdog Timer Flags. All other bits are reserved and must be 0.
+///
+#define EFI_ACPI_6_2_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_TIMER_INTERRUPT_MODE BIT0
+#define EFI_ACPI_6_2_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_TIMER_INTERRUPT_POLARITY BIT1
+#define EFI_ACPI_6_2_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_SECURE_TIMER BIT2
+
+//
+// NVDIMM Firmware Interface Table definition.
+//
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 Reserved;
+} EFI_ACPI_6_2_NVDIMM_FIRMWARE_INTERFACE_TABLE;
+
+//
+// NFIT Version (as defined in ACPI 6.2 spec.)
+//
+#define EFI_ACPI_6_2_NVDIMM_FIRMWARE_INTERFACE_TABLE_REVISION 0x1
+
+//
+// Definition for NFIT Table Structure Types
+//
+#define EFI_ACPI_6_2_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_STRUCTURE_TYPE 0
+#define EFI_ACPI_6_2_NFIT_NVDIMM_REGION_MAPPING_STRUCTURE_TYPE 1
+#define EFI_ACPI_6_2_NFIT_INTERLEAVE_STRUCTURE_TYPE 2
+#define EFI_ACPI_6_2_NFIT_SMBIOS_MANAGEMENT_INFORMATION_STRUCTURE_TYPE 3
+#define EFI_ACPI_6_2_NFIT_NVDIMM_CONTROL_REGION_STRUCTURE_TYPE 4
+#define EFI_ACPI_6_2_NFIT_NVDIMM_BLOCK_DATA_WINDOW_REGION_STRUCTURE_TYPE 5
+#define EFI_ACPI_6_2_NFIT_FLUSH_HINT_ADDRESS_STRUCTURE_TYPE 6
+#define EFI_ACPI_6_2_NFIT_PLATFORM_CAPABILITIES_STRUCTURE_TYPE 7
+
+//
+// Definition for NFIT Structure Header
+//
+typedef struct {
+ UINT16 Type;
+ UINT16 Length;
+} EFI_ACPI_6_2_NFIT_STRUCTURE_HEADER;
+
+//
+// Definition for System Physical Address Range Structure
+//
+#define EFI_ACPI_6_2_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_FLAGS_CONTROL_REGION_FOR_MANAGEMENT BIT0
+#define EFI_ACPI_6_2_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_FLAGS_PROXIMITY_DOMAIN_VALID BIT1
+#define EFI_ACPI_6_2_NFIT_GUID_VOLATILE_MEMORY_REGION { 0x7305944F, 0xFDDA, 0x44E3, { 0xB1, 0x6C, 0x3F, 0x22, 0xD2, 0x52, 0xE5, 0xD0 }}
+#define EFI_ACPI_6_2_NFIT_GUID_BYTE_ADDRESSABLE_PERSISTENT_MEMORY_REGION { 0x66F0D379, 0xB4F3, 0x4074, { 0xAC, 0x43, 0x0D, 0x33, 0x18, 0xB7, 0x8C, 0xDB }}
+#define EFI_ACPI_6_2_NFIT_GUID_NVDIMM_CONTROL_REGION { 0x92F701F6, 0x13B4, 0x405D, { 0x91, 0x0B, 0x29, 0x93, 0x67, 0xE8, 0x23, 0x4C }}
+#define EFI_ACPI_6_2_NFIT_GUID_NVDIMM_BLOCK_DATA_WINDOW_REGION { 0x91AF0530, 0x5D86, 0x470E, { 0xA6, 0xB0, 0x0A, 0x2D, 0xB9, 0x40, 0x82, 0x49 }}
+#define EFI_ACPI_6_2_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_DISK_REGION_VOLATILE { 0x77AB535A, 0x45FC, 0x624B, { 0x55, 0x60, 0xF7, 0xB2, 0x81, 0xD1, 0xF9, 0x6E }}
+#define EFI_ACPI_6_2_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_CD_REGION_VOLATILE { 0x3D5ABD30, 0x4175, 0x87CE, { 0x6D, 0x64, 0xD2, 0xAD, 0xE5, 0x23, 0xC4, 0xBB }}
+#define EFI_ACPI_6_2_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_DISK_REGION_PERSISTENT { 0x5CEA02C9, 0x4D07, 0x69D3, { 0x26, 0x9F ,0x44, 0x96, 0xFB, 0xE0, 0x96, 0xF9 }}
+#define EFI_ACPI_6_2_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_CD_REGION_PERSISTENT { 0x08018188, 0x42CD, 0xBB48, { 0x10, 0x0F, 0x53, 0x87, 0xD5, 0x3D, 0xED, 0x3D }}
+typedef struct {
+ UINT16 Type;
+ UINT16 Length;
+ UINT16 SPARangeStructureIndex;
+ UINT16 Flags;
+ UINT32 Reserved_8;
+ UINT32 ProximityDomain;
+ GUID AddressRangeTypeGUID;
+ UINT64 SystemPhysicalAddressRangeBase;
+ UINT64 SystemPhysicalAddressRangeLength;
+ UINT64 AddressRangeMemoryMappingAttribute;
+} EFI_ACPI_6_2_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_STRUCTURE;
+
+//
+// Definition for Memory Device to System Physical Address Range Mapping Structure
+//
+typedef struct {
+ UINT32 DIMMNumber : 4;
+ UINT32 MemoryChannelNumber : 4;
+ UINT32 MemoryControllerID : 4;
+ UINT32 SocketID : 4;
+ UINT32 NodeControllerID : 12;
+ UINT32 Reserved_28 : 4;
+} EFI_ACPI_6_2_NFIT_DEVICE_HANDLE;
+
+#define EFI_ACPI_6_2_NFIT_MEMORY_DEVICE_STATE_FLAGS_PREVIOUS_SAVE_FAIL BIT0
+#define EFI_ACPI_6_2_NFIT_MEMORY_DEVICE_STATE_FLAGS_LAST_RESTORE_FAIL BIT1
+#define EFI_ACPI_6_2_NFIT_MEMORY_DEVICE_STATE_FLAGS_PLATFORM_FLUSH_FAIL BIT2
+#define EFI_ACPI_6_2_NFIT_MEMORY_DEVICE_STATE_FLAGS_NOT_ARMED_PRIOR_TO_OSPM_HAND_OFF BIT3
+#define EFI_ACPI_6_2_NFIT_MEMORY_DEVICE_STATE_FLAGS_SMART_HEALTH_EVENTS_PRIOR_OSPM_HAND_OFF BIT4
+#define EFI_ACPI_6_2_NFIT_MEMORY_DEVICE_STATE_FLAGS_FIRMWARE_ENABLED_TO_NOTIFY_OSPM_ON_SMART_HEALTH_EVENTS BIT5
+#define EFI_ACPI_6_2_NFIT_MEMORY_DEVICE_STATE_FLAGS_FIRMWARE_NOT_MAP_NVDIMM_TO_SPA BIT6
+typedef struct {
+ UINT16 Type;
+ UINT16 Length;
+ EFI_ACPI_6_2_NFIT_DEVICE_HANDLE NFITDeviceHandle;
+ UINT16 NVDIMMPhysicalID;
+ UINT16 NVDIMMRegionID;
+ UINT16 SPARangeStructureIndex;
+ UINT16 NVDIMMControlRegionStructureIndex;
+ UINT64 NVDIMMRegionSize;
+ UINT64 RegionOffset;
+ UINT64 NVDIMMPhysicalAddressRegionBase;
+ UINT16 InterleaveStructureIndex;
+ UINT16 InterleaveWays;
+ UINT16 NVDIMMStateFlags;
+ UINT16 Reserved_46;
+} EFI_ACPI_6_2_NFIT_NVDIMM_REGION_MAPPING_STRUCTURE;
+
+//
+// Definition for Interleave Structure
+//
+typedef struct {
+ UINT16 Type;
+ UINT16 Length;
+ UINT16 InterleaveStructureIndex;
+ UINT16 Reserved_6;
+ UINT32 NumberOfLines;
+ UINT32 LineSize;
+ // UINT32 LineOffset[NumberOfLines];
+} EFI_ACPI_6_2_NFIT_INTERLEAVE_STRUCTURE;
+
+//
+// Definition for SMBIOS Management Information Structure
+//
+typedef struct {
+ UINT16 Type;
+ UINT16 Length;
+ UINT32 Reserved_4;
+ // UINT8 Data[];
+} EFI_ACPI_6_2_NFIT_SMBIOS_MANAGEMENT_INFORMATION_STRUCTURE;
+
+//
+// Definition for NVDIMM Control Region Structure
+//
+#define EFI_ACPI_6_2_NFIT_NVDIMM_CONTROL_REGION_VALID_FIELDS_MANUFACTURING BIT0
+
+#define EFI_ACPI_6_2_NFIT_NVDIMM_CONTROL_REGION_FLAGS_BLOCK_DATA_WINDOWS_BUFFERED BIT0
+typedef struct {
+ UINT16 Type;
+ UINT16 Length;
+ UINT16 NVDIMMControlRegionStructureIndex;
+ UINT16 VendorID;
+ UINT16 DeviceID;
+ UINT16 RevisionID;
+ UINT16 SubsystemVendorID;
+ UINT16 SubsystemDeviceID;
+ UINT16 SubsystemRevisionID;
+ UINT8 ValidFields;
+ UINT8 ManufacturingLocation;
+ UINT16 ManufacturingDate;
+ UINT8 Reserved_22[2];
+ UINT32 SerialNumber;
+ UINT16 RegionFormatInterfaceCode;
+ UINT16 NumberOfBlockControlWindows;
+ UINT64 SizeOfBlockControlWindow;
+ UINT64 CommandRegisterOffsetInBlockControlWindow;
+ UINT64 SizeOfCommandRegisterInBlockControlWindows;
+ UINT64 StatusRegisterOffsetInBlockControlWindow;
+ UINT64 SizeOfStatusRegisterInBlockControlWindows;
+ UINT16 NVDIMMControlRegionFlag;
+ UINT8 Reserved_74[6];
+} EFI_ACPI_6_2_NFIT_NVDIMM_CONTROL_REGION_STRUCTURE;
+
+//
+// Definition for NVDIMM Block Data Window Region Structure
+//
+typedef struct {
+ UINT16 Type;
+ UINT16 Length;
+ UINT16 NVDIMMControlRegionStructureIndex;
+ UINT16 NumberOfBlockDataWindows;
+ UINT64 BlockDataWindowStartOffset;
+ UINT64 SizeOfBlockDataWindow;
+ UINT64 BlockAccessibleMemoryCapacity;
+ UINT64 BeginningAddressOfFirstBlockInBlockAccessibleMemory;
+} EFI_ACPI_6_2_NFIT_NVDIMM_BLOCK_DATA_WINDOW_REGION_STRUCTURE;
+
+//
+// Definition for Flush Hint Address Structure
+//
+typedef struct {
+ UINT16 Type;
+ UINT16 Length;
+ EFI_ACPI_6_2_NFIT_DEVICE_HANDLE NFITDeviceHandle;
+ UINT16 NumberOfFlushHintAddresses;
+ UINT8 Reserved_10[6];
+ // UINT64 FlushHintAddress[NumberOfFlushHintAddresses];
+} EFI_ACPI_6_2_NFIT_FLUSH_HINT_ADDRESS_STRUCTURE;
+
+//
+// Definition for Platform Capabilities Structure
+//
+typedef struct {
+ UINT16 Type;
+ UINT16 Length;
+ UINT8 HighestValidCapability;
+ UINT8 Reserved_5[3];
+ UINT32 Capabilities;
+ UINT8 Reserved_12[4];
+} EFI_ACPI_6_2_NFIT_PLATFORM_CAPABILITIES_STRUCTURE;
+
+#define EFI_ACPI_6_2_NFIT_PLATFORM_CAPABILITY_CPU_CACHE_FLUSH_TO_NVDIMM_DURABILITY_ON_POWER_LOSS BIT0
+#define EFI_ACPI_6_2_NFIT_PLATFORM_CAPABILITY_MEMORY_CONTROLLER_FLUSH_TO_NVDIMM_DURABILITY_ON_POWER_LOSS BIT1
+#define EFI_ACPI_6_2_NFIT_PLATFORM_CAPABILITY_BYTE_ADDRESSABLE_PERSISTENT_MEMORY_HARDWARE_MIRRORING BIT2
+
+///
+/// Secure DEVices Table (SDEV)
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+} EFI_ACPI_6_2_SECURE_DEVICES_TABLE_HEADER;
+
+///
+/// SDEV Revision (as defined in ACPI 6.2 spec.)
+///
+#define EFI_ACPI_6_2_SECURE_DEVICES_TABLE_REVISION 0x01
+
+///
+/// Secure Device types
+///
+#define EFI_ACPI_6_2_SDEV_TYPE_PCIE_ENDPOINT_DEVICE 0x01
+#define EFI_ACPI_6_2_SDEV_TYPE_ACPI_NAMESPACE_DEVICE 0x00
+
+///
+/// Secure Device flags
+///
+#define EFI_ACPI_6_2_SDEV_FLAG_ALLOW_HANDOFF BIT0
+
+///
+/// SDEV Structure Header
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Flags;
+ UINT16 Length;
+} EFI_ACPI_6_2_SDEV_STRUCTURE_HEADER;
+
+///
+/// PCIe Endpoint Device based Secure Device Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Flags;
+ UINT16 Length;
+ UINT16 PciSegmentNumber;
+ UINT16 StartBusNumber;
+ UINT16 PciPathOffset;
+ UINT16 PciPathLength;
+ UINT16 VendorSpecificDataOffset;
+ UINT16 VendorSpecificDataLength;
+} EFI_ACPI_6_2_SDEV_STRUCTURE_PCIE_ENDPOINT_DEVICE;
+
+///
+/// ACPI_NAMESPACE_DEVICE based Secure Device Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Flags;
+ UINT16 Length;
+ UINT16 DeviceIdentifierOffset;
+ UINT16 DeviceIdentifierLength;
+ UINT16 VendorSpecificDataOffset;
+ UINT16 VendorSpecificDataLength;
+} EFI_ACPI_6_2_SDEV_STRUCTURE_ACPI_NAMESPACE_DEVICE;
+
+///
+/// Boot Error Record Table (BERT)
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 BootErrorRegionLength;
+ UINT64 BootErrorRegion;
+} EFI_ACPI_6_2_BOOT_ERROR_RECORD_TABLE_HEADER;
+
+///
+/// BERT Version (as defined in ACPI 6.2 spec.)
+///
+#define EFI_ACPI_6_2_BOOT_ERROR_RECORD_TABLE_REVISION 0x01
+
+///
+/// Boot Error Region Block Status Definition
+///
+typedef struct {
+ UINT32 UncorrectableErrorValid : 1;
+ UINT32 CorrectableErrorValid : 1;
+ UINT32 MultipleUncorrectableErrors : 1;
+ UINT32 MultipleCorrectableErrors : 1;
+ UINT32 ErrorDataEntryCount : 10;
+ UINT32 Reserved : 18;
+} EFI_ACPI_6_2_ERROR_BLOCK_STATUS;
+
+///
+/// Boot Error Region Definition
+///
+typedef struct {
+ EFI_ACPI_6_2_ERROR_BLOCK_STATUS BlockStatus;
+ UINT32 RawDataOffset;
+ UINT32 RawDataLength;
+ UINT32 DataLength;
+ UINT32 ErrorSeverity;
+} EFI_ACPI_6_2_BOOT_ERROR_REGION_STRUCTURE;
+
+//
+// Boot Error Severity types
+//
+#define EFI_ACPI_6_2_ERROR_SEVERITY_RECOVERABLE 0x00
+#define EFI_ACPI_6_2_ERROR_SEVERITY_FATAL 0x01
+#define EFI_ACPI_6_2_ERROR_SEVERITY_CORRECTED 0x02
+#define EFI_ACPI_6_2_ERROR_SEVERITY_NONE 0x03
+//
+// The term 'Correctable' is no longer being used as an error severity of the
+// reported error since ACPI Specification Version 5.1 Errata B.
+// The below macro is considered as deprecated and should no longer be used.
+//
+#define EFI_ACPI_6_2_ERROR_SEVERITY_CORRECTABLE 0x00
+
+///
+/// Generic Error Data Entry Definition
+///
+typedef struct {
+ UINT8 SectionType[16];
+ UINT32 ErrorSeverity;
+ UINT16 Revision;
+ UINT8 ValidationBits;
+ UINT8 Flags;
+ UINT32 ErrorDataLength;
+ UINT8 FruId[16];
+ UINT8 FruText[20];
+ UINT8 Timestamp[8];
+} EFI_ACPI_6_2_GENERIC_ERROR_DATA_ENTRY_STRUCTURE;
+
+///
+/// Generic Error Data Entry Version (as defined in ACPI 6.2 spec.)
+///
+#define EFI_ACPI_6_2_GENERIC_ERROR_DATA_ENTRY_REVISION 0x0300
+
+///
+/// HEST - Hardware Error Source Table
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 ErrorSourceCount;
+} EFI_ACPI_6_2_HARDWARE_ERROR_SOURCE_TABLE_HEADER;
+
+///
+/// HEST Version (as defined in ACPI 6.2 spec.)
+///
+#define EFI_ACPI_6_2_HARDWARE_ERROR_SOURCE_TABLE_REVISION 0x01
+
+//
+// Error Source structure types.
+//
+#define EFI_ACPI_6_2_IA32_ARCHITECTURE_MACHINE_CHECK_EXCEPTION 0x00
+#define EFI_ACPI_6_2_IA32_ARCHITECTURE_CORRECTED_MACHINE_CHECK 0x01
+#define EFI_ACPI_6_2_IA32_ARCHITECTURE_NMI_ERROR 0x02
+#define EFI_ACPI_6_2_PCI_EXPRESS_ROOT_PORT_AER 0x06
+#define EFI_ACPI_6_2_PCI_EXPRESS_DEVICE_AER 0x07
+#define EFI_ACPI_6_2_PCI_EXPRESS_BRIDGE_AER 0x08
+#define EFI_ACPI_6_2_GENERIC_HARDWARE_ERROR 0x09
+#define EFI_ACPI_6_2_GENERIC_HARDWARE_ERROR_VERSION_2 0x0A
+#define EFI_ACPI_6_2_IA32_ARCHITECTURE_DEFERRED_MACHINE_CHECK 0x0B
+
+//
+// Error Source structure flags.
+//
+#define EFI_ACPI_6_2_ERROR_SOURCE_FLAG_FIRMWARE_FIRST (1 << 0)
+#define EFI_ACPI_6_2_ERROR_SOURCE_FLAG_GLOBAL (1 << 1)
+#define EFI_ACPI_6_2_ERROR_SOURCE_FLAG_GHES_ASSIST (1 << 2)
+
+///
+/// IA-32 Architecture Machine Check Exception Structure Definition
+///
+typedef struct {
+ UINT16 Type;
+ UINT16 SourceId;
+ UINT8 Reserved0[2];
+ UINT8 Flags;
+ UINT8 Enabled;
+ UINT32 NumberOfRecordsToPreAllocate;
+ UINT32 MaxSectionsPerRecord;
+ UINT64 GlobalCapabilityInitData;
+ UINT64 GlobalControlInitData;
+ UINT8 NumberOfHardwareBanks;
+ UINT8 Reserved1[7];
+} EFI_ACPI_6_2_IA32_ARCHITECTURE_MACHINE_CHECK_EXCEPTION_STRUCTURE;
+
+///
+/// IA-32 Architecture Machine Check Bank Structure Definition
+///
+typedef struct {
+ UINT8 BankNumber;
+ UINT8 ClearStatusOnInitialization;
+ UINT8 StatusDataFormat;
+ UINT8 Reserved0;
+ UINT32 ControlRegisterMsrAddress;
+ UINT64 ControlInitData;
+ UINT32 StatusRegisterMsrAddress;
+ UINT32 AddressRegisterMsrAddress;
+ UINT32 MiscRegisterMsrAddress;
+} EFI_ACPI_6_2_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_BANK_STRUCTURE;
+
+///
+/// IA-32 Architecture Machine Check Bank Structure MCA data format
+///
+#define EFI_ACPI_6_2_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_IA32 0x00
+#define EFI_ACPI_6_2_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_INTEL64 0x01
+#define EFI_ACPI_6_2_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_AMD64 0x02
+
+//
+// Hardware Error Notification types. All other values are reserved
+//
+#define EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_POLLED 0x00
+#define EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_EXTERNAL_INTERRUPT 0x01
+#define EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_LOCAL_INTERRUPT 0x02
+#define EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_SCI 0x03
+#define EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_NMI 0x04
+#define EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_CMCI 0x05
+#define EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_MCE 0x06
+#define EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_GPIO_SIGNAL 0x07
+#define EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_ARMV8_SEA 0x08
+#define EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_ARMV8_SEI 0x09
+#define EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_GSIV 0x0A
+#define EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_SOFTWARE_DELEGATED_EXCEPTION 0x0B
+
+///
+/// Hardware Error Notification Configuration Write Enable Structure Definition
+///
+typedef struct {
+ UINT16 Type : 1;
+ UINT16 PollInterval : 1;
+ UINT16 SwitchToPollingThresholdValue : 1;
+ UINT16 SwitchToPollingThresholdWindow : 1;
+ UINT16 ErrorThresholdValue : 1;
+ UINT16 ErrorThresholdWindow : 1;
+ UINT16 Reserved : 10;
+} EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_CONFIGURATION_WRITE_ENABLE_STRUCTURE;
+
+///
+/// Hardware Error Notification Structure Definition
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_CONFIGURATION_WRITE_ENABLE_STRUCTURE ConfigurationWriteEnable;
+ UINT32 PollInterval;
+ UINT32 Vector;
+ UINT32 SwitchToPollingThresholdValue;
+ UINT32 SwitchToPollingThresholdWindow;
+ UINT32 ErrorThresholdValue;
+ UINT32 ErrorThresholdWindow;
+} EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_STRUCTURE;
+
+///
+/// IA-32 Architecture Corrected Machine Check Structure Definition
+///
+typedef struct {
+ UINT16 Type;
+ UINT16 SourceId;
+ UINT8 Reserved0[2];
+ UINT8 Flags;
+ UINT8 Enabled;
+ UINT32 NumberOfRecordsToPreAllocate;
+ UINT32 MaxSectionsPerRecord;
+ EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure;
+ UINT8 NumberOfHardwareBanks;
+ UINT8 Reserved1[3];
+} EFI_ACPI_6_2_IA32_ARCHITECTURE_CORRECTED_MACHINE_CHECK_STRUCTURE;
+
+///
+/// IA-32 Architecture NMI Error Structure Definition
+///
+typedef struct {
+ UINT16 Type;
+ UINT16 SourceId;
+ UINT8 Reserved0[2];
+ UINT32 NumberOfRecordsToPreAllocate;
+ UINT32 MaxSectionsPerRecord;
+ UINT32 MaxRawDataLength;
+} EFI_ACPI_6_2_IA32_ARCHITECTURE_NMI_ERROR_STRUCTURE;
+
+///
+/// PCI Express Root Port AER Structure Definition
+///
+typedef struct {
+ UINT16 Type;
+ UINT16 SourceId;
+ UINT8 Reserved0[2];
+ UINT8 Flags;
+ UINT8 Enabled;
+ UINT32 NumberOfRecordsToPreAllocate;
+ UINT32 MaxSectionsPerRecord;
+ UINT32 Bus;
+ UINT16 Device;
+ UINT16 Function;
+ UINT16 DeviceControl;
+ UINT8 Reserved1[2];
+ UINT32 UncorrectableErrorMask;
+ UINT32 UncorrectableErrorSeverity;
+ UINT32 CorrectableErrorMask;
+ UINT32 AdvancedErrorCapabilitiesAndControl;
+ UINT32 RootErrorCommand;
+} EFI_ACPI_6_2_PCI_EXPRESS_ROOT_PORT_AER_STRUCTURE;
+
+///
+/// PCI Express Device AER Structure Definition
+///
+typedef struct {
+ UINT16 Type;
+ UINT16 SourceId;
+ UINT8 Reserved0[2];
+ UINT8 Flags;
+ UINT8 Enabled;
+ UINT32 NumberOfRecordsToPreAllocate;
+ UINT32 MaxSectionsPerRecord;
+ UINT32 Bus;
+ UINT16 Device;
+ UINT16 Function;
+ UINT16 DeviceControl;
+ UINT8 Reserved1[2];
+ UINT32 UncorrectableErrorMask;
+ UINT32 UncorrectableErrorSeverity;
+ UINT32 CorrectableErrorMask;
+ UINT32 AdvancedErrorCapabilitiesAndControl;
+} EFI_ACPI_6_2_PCI_EXPRESS_DEVICE_AER_STRUCTURE;
+
+///
+/// PCI Express Bridge AER Structure Definition
+///
+typedef struct {
+ UINT16 Type;
+ UINT16 SourceId;
+ UINT8 Reserved0[2];
+ UINT8 Flags;
+ UINT8 Enabled;
+ UINT32 NumberOfRecordsToPreAllocate;
+ UINT32 MaxSectionsPerRecord;
+ UINT32 Bus;
+ UINT16 Device;
+ UINT16 Function;
+ UINT16 DeviceControl;
+ UINT8 Reserved1[2];
+ UINT32 UncorrectableErrorMask;
+ UINT32 UncorrectableErrorSeverity;
+ UINT32 CorrectableErrorMask;
+ UINT32 AdvancedErrorCapabilitiesAndControl;
+ UINT32 SecondaryUncorrectableErrorMask;
+ UINT32 SecondaryUncorrectableErrorSeverity;
+ UINT32 SecondaryAdvancedErrorCapabilitiesAndControl;
+} EFI_ACPI_6_2_PCI_EXPRESS_BRIDGE_AER_STRUCTURE;
+
+///
+/// Generic Hardware Error Source Structure Definition
+///
+typedef struct {
+ UINT16 Type;
+ UINT16 SourceId;
+ UINT16 RelatedSourceId;
+ UINT8 Flags;
+ UINT8 Enabled;
+ UINT32 NumberOfRecordsToPreAllocate;
+ UINT32 MaxSectionsPerRecord;
+ UINT32 MaxRawDataLength;
+ EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE ErrorStatusAddress;
+ EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure;
+ UINT32 ErrorStatusBlockLength;
+} EFI_ACPI_6_2_GENERIC_HARDWARE_ERROR_SOURCE_STRUCTURE;
+
+///
+/// Generic Hardware Error Source Version 2 Structure Definition
+///
+typedef struct {
+ UINT16 Type;
+ UINT16 SourceId;
+ UINT16 RelatedSourceId;
+ UINT8 Flags;
+ UINT8 Enabled;
+ UINT32 NumberOfRecordsToPreAllocate;
+ UINT32 MaxSectionsPerRecord;
+ UINT32 MaxRawDataLength;
+ EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE ErrorStatusAddress;
+ EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure;
+ UINT32 ErrorStatusBlockLength;
+ EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE ReadAckRegister;
+ UINT64 ReadAckPreserve;
+ UINT64 ReadAckWrite;
+} EFI_ACPI_6_2_GENERIC_HARDWARE_ERROR_SOURCE_VERSION_2_STRUCTURE;
+
+///
+/// Generic Error Status Definition
+///
+typedef struct {
+ EFI_ACPI_6_2_ERROR_BLOCK_STATUS BlockStatus;
+ UINT32 RawDataOffset;
+ UINT32 RawDataLength;
+ UINT32 DataLength;
+ UINT32 ErrorSeverity;
+} EFI_ACPI_6_2_GENERIC_ERROR_STATUS_STRUCTURE;
+
+///
+/// IA-32 Architecture Deferred Machine Check Structure Definition
+///
+typedef struct {
+ UINT16 Type;
+ UINT16 SourceId;
+ UINT8 Reserved0[2];
+ UINT8 Flags;
+ UINT8 Enabled;
+ UINT32 NumberOfRecordsToPreAllocate;
+ UINT32 MaxSectionsPerRecord;
+ EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure;
+ UINT8 NumberOfHardwareBanks;
+ UINT8 Reserved1[3];
+} EFI_ACPI_6_2_IA32_ARCHITECTURE_DEFERRED_MACHINE_CHECK_STRUCTURE;
+
+///
+/// HMAT - Heterogeneous Memory Attribute Table
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT8 Reserved[4];
+} EFI_ACPI_6_2_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_HEADER;
+
+///
+/// HMAT Revision (as defined in ACPI 6.2 spec.)
+///
+#define EFI_ACPI_6_2_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_REVISION 0x01
+
+///
+/// HMAT types
+///
+#define EFI_ACPI_6_2_HMAT_TYPE_MEMORY_SUBSYSTEM_ADDRESS_RANGE 0x00
+#define EFI_ACPI_6_2_HMAT_TYPE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO 0x01
+#define EFI_ACPI_6_2_HMAT_TYPE_MEMORY_SIDE_CACHE_INFO 0x02
+
+///
+/// HMAT Structure Header
+///
+typedef struct {
+ UINT16 Type;
+ UINT8 Reserved[2];
+ UINT32 Length;
+} EFI_ACPI_6_2_HMAT_STRUCTURE_HEADER;
+
+///
+/// Memory Subsystem Address Range Structure flags
+///
+typedef struct {
+ UINT16 ProcessorProximityDomainValid : 1;
+ UINT16 MemoryProximityDomainValid : 1;
+ UINT16 ReservationHint : 1;
+ UINT16 Reserved : 13;
+} EFI_ACPI_6_2_HMAT_STRUCTURE_MEMORY_SUBSYSTEM_ADDRESS_RANGE_FLAGS;
+
+///
+/// Memory Subsystem Address Range Structure
+///
+typedef struct {
+ UINT16 Type;
+ UINT8 Reserved[2];
+ UINT32 Length;
+ EFI_ACPI_6_2_HMAT_STRUCTURE_MEMORY_SUBSYSTEM_ADDRESS_RANGE_FLAGS Flags;
+ UINT8 Reserved1[2];
+ UINT32 ProcessorProximityDomain;
+ UINT32 MemoryProximityDomain;
+ UINT8 Reserved2[4];
+ UINT64 SystemPhysicalAddressRangeBase;
+ UINT64 SystemPhysicalAddressRangeLength;
+} EFI_ACPI_6_2_HMAT_STRUCTURE_MEMORY_SUBSYSTEM_ADDRESS_RANGE;
+
+///
+/// System Locality Latency and Bandwidth Information Structure flags
+///
+typedef struct {
+ UINT8 MemoryHierarchy : 5;
+ UINT8 Reserved : 3;
+} EFI_ACPI_6_2_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO_FLAGS;
+
+///
+/// System Locality Latency and Bandwidth Information Structure
+///
+typedef struct {
+ UINT16 Type;
+ UINT8 Reserved[2];
+ UINT32 Length;
+ EFI_ACPI_6_2_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO_FLAGS Flags;
+ UINT8 DataType;
+ UINT8 Reserved1[2];
+ UINT32 NumberOfInitiatorProximityDomains;
+ UINT32 NumberOfTargetProximityDomains;
+ UINT8 Reserved2[4];
+ UINT64 EntryBaseUnit;
+} EFI_ACPI_6_2_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO;
+
+///
+/// Memory Side Cache Information Structure cache attributes
+///
+typedef struct {
+ UINT32 TotalCacheLevels : 4;
+ UINT32 CacheLevel : 4;
+ UINT32 CacheAssociativity : 4;
+ UINT32 WritePolicy : 4;
+ UINT32 CacheLineSize : 16;
+} EFI_ACPI_6_2_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_CACHE_ATTRIBUTES;
+
+///
+/// Memory Side Cache Information Structure
+///
+typedef struct {
+ UINT16 Type;
+ UINT8 Reserved[2];
+ UINT32 Length;
+ UINT32 MemoryProximityDomain;
+ UINT8 Reserved1[4];
+ UINT64 MemorySideCacheSize;
+ EFI_ACPI_6_2_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_CACHE_ATTRIBUTES CacheAttributes;
+ UINT8 Reserved2[2];
+ UINT16 NumberOfSmbiosHandles;
+} EFI_ACPI_6_2_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO;
+
+///
+/// ERST - Error Record Serialization Table
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 SerializationHeaderSize;
+ UINT8 Reserved0[4];
+ UINT32 InstructionEntryCount;
+} EFI_ACPI_6_2_ERROR_RECORD_SERIALIZATION_TABLE_HEADER;
+
+///
+/// ERST Version (as defined in ACPI 6.2 spec.)
+///
+#define EFI_ACPI_6_2_ERROR_RECORD_SERIALIZATION_TABLE_REVISION 0x01
+
+///
+/// ERST Serialization Actions
+///
+#define EFI_ACPI_6_2_ERST_BEGIN_WRITE_OPERATION 0x00
+#define EFI_ACPI_6_2_ERST_BEGIN_READ_OPERATION 0x01
+#define EFI_ACPI_6_2_ERST_BEGIN_CLEAR_OPERATION 0x02
+#define EFI_ACPI_6_2_ERST_END_OPERATION 0x03
+#define EFI_ACPI_6_2_ERST_SET_RECORD_OFFSET 0x04
+#define EFI_ACPI_6_2_ERST_EXECUTE_OPERATION 0x05
+#define EFI_ACPI_6_2_ERST_CHECK_BUSY_STATUS 0x06
+#define EFI_ACPI_6_2_ERST_GET_COMMAND_STATUS 0x07
+#define EFI_ACPI_6_2_ERST_GET_RECORD_IDENTIFIER 0x08
+#define EFI_ACPI_6_2_ERST_SET_RECORD_IDENTIFIER 0x09
+#define EFI_ACPI_6_2_ERST_GET_RECORD_COUNT 0x0A
+#define EFI_ACPI_6_2_ERST_BEGIN_DUMMY_WRITE_OPERATION 0x0B
+#define EFI_ACPI_6_2_ERST_GET_ERROR_LOG_ADDRESS_RANGE 0x0D
+#define EFI_ACPI_6_2_ERST_GET_ERROR_LOG_ADDRESS_RANGE_LENGTH 0x0E
+#define EFI_ACPI_6_2_ERST_GET_ERROR_LOG_ADDRESS_RANGE_ATTRIBUTES 0x0F
+#define EFI_ACPI_6_2_ERST_GET_EXECUTE_OPERATION_TIMINGS 0x10
+
+///
+/// ERST Action Command Status
+///
+#define EFI_ACPI_6_2_ERST_STATUS_SUCCESS 0x00
+#define EFI_ACPI_6_2_ERST_STATUS_NOT_ENOUGH_SPACE 0x01
+#define EFI_ACPI_6_2_ERST_STATUS_HARDWARE_NOT_AVAILABLE 0x02
+#define EFI_ACPI_6_2_ERST_STATUS_FAILED 0x03
+#define EFI_ACPI_6_2_ERST_STATUS_RECORD_STORE_EMPTY 0x04
+#define EFI_ACPI_6_2_ERST_STATUS_RECORD_NOT_FOUND 0x05
+
+///
+/// ERST Serialization Instructions
+///
+#define EFI_ACPI_6_2_ERST_READ_REGISTER 0x00
+#define EFI_ACPI_6_2_ERST_READ_REGISTER_VALUE 0x01
+#define EFI_ACPI_6_2_ERST_WRITE_REGISTER 0x02
+#define EFI_ACPI_6_2_ERST_WRITE_REGISTER_VALUE 0x03
+#define EFI_ACPI_6_2_ERST_NOOP 0x04
+#define EFI_ACPI_6_2_ERST_LOAD_VAR1 0x05
+#define EFI_ACPI_6_2_ERST_LOAD_VAR2 0x06
+#define EFI_ACPI_6_2_ERST_STORE_VAR1 0x07
+#define EFI_ACPI_6_2_ERST_ADD 0x08
+#define EFI_ACPI_6_2_ERST_SUBTRACT 0x09
+#define EFI_ACPI_6_2_ERST_ADD_VALUE 0x0A
+#define EFI_ACPI_6_2_ERST_SUBTRACT_VALUE 0x0B
+#define EFI_ACPI_6_2_ERST_STALL 0x0C
+#define EFI_ACPI_6_2_ERST_STALL_WHILE_TRUE 0x0D
+#define EFI_ACPI_6_2_ERST_SKIP_NEXT_INSTRUCTION_IF_TRUE 0x0E
+#define EFI_ACPI_6_2_ERST_GOTO 0x0F
+#define EFI_ACPI_6_2_ERST_SET_SRC_ADDRESS_BASE 0x10
+#define EFI_ACPI_6_2_ERST_SET_DST_ADDRESS_BASE 0x11
+#define EFI_ACPI_6_2_ERST_MOVE_DATA 0x12
+
+///
+/// ERST Instruction Flags
+///
+#define EFI_ACPI_6_2_ERST_PRESERVE_REGISTER 0x01
+
+///
+/// ERST Serialization Instruction Entry
+///
+typedef struct {
+ UINT8 SerializationAction;
+ UINT8 Instruction;
+ UINT8 Flags;
+ UINT8 Reserved0;
+ EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE RegisterRegion;
+ UINT64 Value;
+ UINT64 Mask;
+} EFI_ACPI_6_2_ERST_SERIALIZATION_INSTRUCTION_ENTRY;
+
+///
+/// EINJ - Error Injection Table
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 InjectionHeaderSize;
+ UINT8 InjectionFlags;
+ UINT8 Reserved0[3];
+ UINT32 InjectionEntryCount;
+} EFI_ACPI_6_2_ERROR_INJECTION_TABLE_HEADER;
+
+///
+/// EINJ Version (as defined in ACPI 6.2 spec.)
+///
+#define EFI_ACPI_6_2_ERROR_INJECTION_TABLE_REVISION 0x01
+
+///
+/// EINJ Error Injection Actions
+///
+#define EFI_ACPI_6_2_EINJ_BEGIN_INJECTION_OPERATION 0x00
+#define EFI_ACPI_6_2_EINJ_GET_TRIGGER_ERROR_ACTION_TABLE 0x01
+#define EFI_ACPI_6_2_EINJ_SET_ERROR_TYPE 0x02
+#define EFI_ACPI_6_2_EINJ_GET_ERROR_TYPE 0x03
+#define EFI_ACPI_6_2_EINJ_END_OPERATION 0x04
+#define EFI_ACPI_6_2_EINJ_EXECUTE_OPERATION 0x05
+#define EFI_ACPI_6_2_EINJ_CHECK_BUSY_STATUS 0x06
+#define EFI_ACPI_6_2_EINJ_GET_COMMAND_STATUS 0x07
+#define EFI_ACPI_6_2_EINJ_TRIGGER_ERROR 0xFF
+
+///
+/// EINJ Action Command Status
+///
+#define EFI_ACPI_6_2_EINJ_STATUS_SUCCESS 0x00
+#define EFI_ACPI_6_2_EINJ_STATUS_UNKNOWN_FAILURE 0x01
+#define EFI_ACPI_6_2_EINJ_STATUS_INVALID_ACCESS 0x02
+
+///
+/// EINJ Error Type Definition
+///
+#define EFI_ACPI_6_2_EINJ_ERROR_PROCESSOR_CORRECTABLE (1 << 0)
+#define EFI_ACPI_6_2_EINJ_ERROR_PROCESSOR_UNCORRECTABLE_NONFATAL (1 << 1)
+#define EFI_ACPI_6_2_EINJ_ERROR_PROCESSOR_UNCORRECTABLE_FATAL (1 << 2)
+#define EFI_ACPI_6_2_EINJ_ERROR_MEMORY_CORRECTABLE (1 << 3)
+#define EFI_ACPI_6_2_EINJ_ERROR_MEMORY_UNCORRECTABLE_NONFATAL (1 << 4)
+#define EFI_ACPI_6_2_EINJ_ERROR_MEMORY_UNCORRECTABLE_FATAL (1 << 5)
+#define EFI_ACPI_6_2_EINJ_ERROR_PCI_EXPRESS_CORRECTABLE (1 << 6)
+#define EFI_ACPI_6_2_EINJ_ERROR_PCI_EXPRESS_UNCORRECTABLE_NONFATAL (1 << 7)
+#define EFI_ACPI_6_2_EINJ_ERROR_PCI_EXPRESS_UNCORRECTABLE_FATAL (1 << 8)
+#define EFI_ACPI_6_2_EINJ_ERROR_PLATFORM_CORRECTABLE (1 << 9)
+#define EFI_ACPI_6_2_EINJ_ERROR_PLATFORM_UNCORRECTABLE_NONFATAL (1 << 10)
+#define EFI_ACPI_6_2_EINJ_ERROR_PLATFORM_UNCORRECTABLE_FATAL (1 << 11)
+
+///
+/// EINJ Injection Instructions
+///
+#define EFI_ACPI_6_2_EINJ_READ_REGISTER 0x00
+#define EFI_ACPI_6_2_EINJ_READ_REGISTER_VALUE 0x01
+#define EFI_ACPI_6_2_EINJ_WRITE_REGISTER 0x02
+#define EFI_ACPI_6_2_EINJ_WRITE_REGISTER_VALUE 0x03
+#define EFI_ACPI_6_2_EINJ_NOOP 0x04
+
+///
+/// EINJ Instruction Flags
+///
+#define EFI_ACPI_6_2_EINJ_PRESERVE_REGISTER 0x01
+
+///
+/// EINJ Injection Instruction Entry
+///
+typedef struct {
+ UINT8 InjectionAction;
+ UINT8 Instruction;
+ UINT8 Flags;
+ UINT8 Reserved0;
+ EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE RegisterRegion;
+ UINT64 Value;
+ UINT64 Mask;
+} EFI_ACPI_6_2_EINJ_INJECTION_INSTRUCTION_ENTRY;
+
+///
+/// EINJ Trigger Action Table
+///
+typedef struct {
+ UINT32 HeaderSize;
+ UINT32 Revision;
+ UINT32 TableSize;
+ UINT32 EntryCount;
+} EFI_ACPI_6_2_EINJ_TRIGGER_ACTION_TABLE;
+
+///
+/// Platform Communications Channel Table (PCCT)
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 Flags;
+ UINT64 Reserved;
+} EFI_ACPI_6_2_PLATFORM_COMMUNICATION_CHANNEL_TABLE_HEADER;
+
+///
+/// PCCT Version (as defined in ACPI 6.2 spec.)
+///
+#define EFI_ACPI_6_2_PLATFORM_COMMUNICATION_CHANNEL_TABLE_REVISION 0x02
+
+///
+/// PCCT Global Flags
+///
+#define EFI_ACPI_6_2_PCCT_FLAGS_PLATFORM_INTERRUPT BIT0
+
+//
+// PCCT Subspace type
+//
+#define EFI_ACPI_6_2_PCCT_SUBSPACE_TYPE_GENERIC 0x00
+#define EFI_ACPI_6_2_PCCT_SUBSPACE_TYPE_1_HW_REDUCED_COMMUNICATIONS 0x01
+#define EFI_ACPI_6_2_PCCT_SUBSPACE_TYPE_2_HW_REDUCED_COMMUNICATIONS 0x02
+#define EFI_ACPI_6_2_PCCT_SUBSPACE_TYPE_3_EXTENDED_PCC 0x03
+#define EFI_ACPI_6_2_PCCT_SUBSPACE_TYPE_4_EXTENDED_PCC 0x04
+
+///
+/// PCC Subspace Structure Header
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+} EFI_ACPI_6_2_PCCT_SUBSPACE_HEADER;
+
+///
+/// Generic Communications Subspace Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 Reserved[6];
+ UINT64 BaseAddress;
+ UINT64 AddressLength;
+ EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE DoorbellRegister;
+ UINT64 DoorbellPreserve;
+ UINT64 DoorbellWrite;
+ UINT32 NominalLatency;
+ UINT32 MaximumPeriodicAccessRate;
+ UINT16 MinimumRequestTurnaroundTime;
+} EFI_ACPI_6_2_PCCT_SUBSPACE_GENERIC;
+
+///
+/// Generic Communications Channel Shared Memory Region
+///
+
+typedef struct {
+ UINT8 Command;
+ UINT8 Reserved : 7;
+ UINT8 NotifyOnCompletion : 1;
+} EFI_ACPI_6_2_PCCT_GENERIC_SHARED_MEMORY_REGION_COMMAND;
+
+typedef struct {
+ UINT8 CommandComplete : 1;
+ UINT8 PlatformInterrupt : 1;
+ UINT8 Error : 1;
+ UINT8 PlatformNotification : 1;
+ UINT8 Reserved : 4;
+ UINT8 Reserved1;
+} EFI_ACPI_6_2_PCCT_GENERIC_SHARED_MEMORY_REGION_STATUS;
+
+typedef struct {
+ UINT32 Signature;
+ EFI_ACPI_6_2_PCCT_GENERIC_SHARED_MEMORY_REGION_COMMAND Command;
+ EFI_ACPI_6_2_PCCT_GENERIC_SHARED_MEMORY_REGION_STATUS Status;
+} EFI_ACPI_6_2_PCCT_GENERIC_SHARED_MEMORY_REGION_HEADER;
+
+#define EFI_ACPI_6_2_PCCT_SUBSPACE_PLATFORM_INTERRUPT_FLAGS_POLARITY BIT0
+#define EFI_ACPI_6_2_PCCT_SUBSPACE_PLATFORM_INTERRUPT_FLAGS_MODE BIT1
+
+///
+/// Type 1 HW-Reduced Communications Subspace Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT32 PlatformInterrupt;
+ UINT8 PlatformInterruptFlags;
+ UINT8 Reserved;
+ UINT64 BaseAddress;
+ UINT64 AddressLength;
+ EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE DoorbellRegister;
+ UINT64 DoorbellPreserve;
+ UINT64 DoorbellWrite;
+ UINT32 NominalLatency;
+ UINT32 MaximumPeriodicAccessRate;
+ UINT16 MinimumRequestTurnaroundTime;
+} EFI_ACPI_6_2_PCCT_SUBSPACE_1_HW_REDUCED_COMMUNICATIONS;
+
+///
+/// Type 2 HW-Reduced Communications Subspace Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT32 PlatformInterrupt;
+ UINT8 PlatformInterruptFlags;
+ UINT8 Reserved;
+ UINT64 BaseAddress;
+ UINT64 AddressLength;
+ EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE DoorbellRegister;
+ UINT64 DoorbellPreserve;
+ UINT64 DoorbellWrite;
+ UINT32 NominalLatency;
+ UINT32 MaximumPeriodicAccessRate;
+ UINT16 MinimumRequestTurnaroundTime;
+ EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE PlatformInterruptAckRegister;
+ UINT64 PlatformInterruptAckPreserve;
+ UINT64 PlatformInterruptAckWrite;
+} EFI_ACPI_6_2_PCCT_SUBSPACE_2_HW_REDUCED_COMMUNICATIONS;
+
+///
+/// Type 3 Extended PCC Subspace Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT32 PlatformInterrupt;
+ UINT8 PlatformInterruptFlags;
+ UINT8 Reserved;
+ UINT64 BaseAddress;
+ UINT32 AddressLength;
+ EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE DoorbellRegister;
+ UINT64 DoorbellPreserve;
+ UINT64 DoorbellWrite;
+ UINT32 NominalLatency;
+ UINT32 MaximumPeriodicAccessRate;
+ UINT32 MinimumRequestTurnaroundTime;
+ EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE PlatformInterruptAckRegister;
+ UINT64 PlatformInterruptAckPreserve;
+ UINT64 PlatformInterruptAckSet;
+ UINT8 Reserved1[8];
+ EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE CommandCompleteCheckRegister;
+ UINT64 CommandCompleteCheckMask;
+ EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE CommandCompleteUpdateRegister;
+ UINT64 CommandCompleteUpdatePreserve;
+ UINT64 CommandCompleteUpdateSet;
+ EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE ErrorStatusRegister;
+ UINT64 ErrorStatusMask;
+} EFI_ACPI_6_2_PCCT_SUBSPACE_3_EXTENDED_PCC;
+
+///
+/// Type 4 Extended PCC Subspace Structure
+///
+typedef EFI_ACPI_6_2_PCCT_SUBSPACE_3_EXTENDED_PCC EFI_ACPI_6_2_PCCT_SUBSPACE_4_EXTENDED_PCC;
+
+#define EFI_ACPI_6_2_PCCT_MASTER_SLAVE_COMMUNICATIONS_CHANNEL_FLAGS_NOTIFY_ON_COMPLETION BIT0
+
+typedef struct {
+ UINT32 Signature;
+ UINT32 Flags;
+ UINT32 Length;
+ UINT32 Command;
+} EFI_ACPI_6_2_PCCT_EXTENDED_PCC_SHARED_MEMORY_REGION_HEADER;
+
+///
+/// Platform Debug Trigger Table (PDTT)
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT8 TriggerCount;
+ UINT8 Reserved[3];
+ UINT32 TriggerIdentifierArrayOffset;
+} EFI_ACPI_6_2_PLATFORM_DEBUG_TRIGGER_TABLE_HEADER;
+
+///
+/// PDTT Revision (as defined in ACPI 6.2 spec.)
+///
+#define EFI_ACPI_6_2_PLATFORM_DEBUG_TRIGGER_TABLE_REVISION 0x00
+
+///
+/// PDTT Platform Communication Channel Identifier Structure
+///
+typedef struct {
+ UINT16 SubChannelIdentifer : 8;
+ UINT16 Runtime : 1;
+ UINT16 WaitForCompletion : 1;
+ UINT16 Reserved : 6;
+} EFI_ACPI_6_2_PDTT_PCC_IDENTIFIER;
+
+///
+/// PCC Commands Codes used by Platform Debug Trigger Table
+///
+#define EFI_ACPI_6_2_PDTT_PCC_COMMAND_DOORBELL_ONLY 0x00
+#define EFI_ACPI_6_2_PDTT_PCC_COMMAND_VENDOR_SPECIFIC 0x01
+
+///
+/// PPTT Platform Communication Channel
+///
+typedef EFI_ACPI_6_2_PCCT_GENERIC_SHARED_MEMORY_REGION_HEADER EFI_ACPI_6_2_PDTT_PCC;
+
+///
+/// Processor Properties Topology Table (PPTT)
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+} EFI_ACPI_6_2_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER;
+
+///
+/// PPTT Revision (as defined in ACPI 6.2 spec.)
+///
+#define EFI_ACPI_6_2_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION 0x01
+
+///
+/// PPTT types
+///
+#define EFI_ACPI_6_2_PPTT_TYPE_PROCESSOR 0x00
+#define EFI_ACPI_6_2_PPTT_TYPE_CACHE 0x01
+#define EFI_ACPI_6_2_PPTT_TYPE_ID 0x02
+
+///
+/// PPTT Structure Header
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 Reserved[2];
+} EFI_ACPI_6_2_PPTT_STRUCTURE_HEADER;
+
+///
+/// For PPTT struct processor flags
+///
+#define EFI_ACPI_6_2_PPTT_PROCESSOR_ID_INVALID 0x0
+#define EFI_ACPI_6_2_PPTT_PROCESSOR_ID_VALID 0x1
+
+///
+/// Processor hierarchy node structure flags
+///
+typedef struct {
+ UINT32 PhysicalPackage : 1;
+ UINT32 AcpiProcessorIdValid : 1;
+ UINT32 Reserved : 30;
+} EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR_FLAGS;
+
+///
+/// Processor hierarchy node structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 Reserved[2];
+ EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR_FLAGS Flags;
+ UINT32 Parent;
+ UINT32 AcpiProcessorId;
+ UINT32 NumberOfPrivateResources;
+} EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR;
+
+///
+/// Cache Type Structure flags
+///
+typedef struct {
+ UINT32 SizePropertyValid : 1;
+ UINT32 NumberOfSetsValid : 1;
+ UINT32 AssociativityValid : 1;
+ UINT32 AllocationTypeValid : 1;
+ UINT32 CacheTypeValid : 1;
+ UINT32 WritePolicyValid : 1;
+ UINT32 LineSizeValid : 1;
+ UINT32 Reserved : 25;
+} EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE_FLAGS;
+
+///
+/// For cache attributes
+///
+#define EFI_ACPI_6_2_CACHE_ATTRIBUTES_ALLOCATION_READ 0x0
+#define EFI_ACPI_6_2_CACHE_ATTRIBUTES_ALLOCATION_WRITE 0x1
+#define EFI_ACPI_6_2_CACHE_ATTRIBUTES_ALLOCATION_READ_WRITE 0x2
+#define EFI_ACPI_6_2_CACHE_ATTRIBUTES_CACHE_TYPE_DATA 0x0
+#define EFI_ACPI_6_2_CACHE_ATTRIBUTES_CACHE_TYPE_INSTRUCTION 0x1
+#define EFI_ACPI_6_2_CACHE_ATTRIBUTES_CACHE_TYPE_UNIFIED 0x2
+#define EFI_ACPI_6_2_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK 0x0
+#define EFI_ACPI_6_2_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_THROUGH 0x1
+
+///
+/// Cache Type Structure cache attributes
+///
+typedef struct {
+ UINT8 AllocationType : 2;
+ UINT8 CacheType : 2;
+ UINT8 WritePolicy : 1;
+ UINT8 Reserved : 3;
+} EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE_ATTRIBUTES;
+
+///
+/// Cache Type Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 Reserved[2];
+ EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE_FLAGS Flags;
+ UINT32 NextLevelOfCache;
+ UINT32 Size;
+ UINT32 NumberOfSets;
+ UINT8 Associativity;
+ EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE_ATTRIBUTES Attributes;
+ UINT16 LineSize;
+} EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE;
+
+///
+/// ID structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 Reserved[2];
+ UINT32 VendorId;
+ UINT64 Level1Id;
+ UINT64 Level2Id;
+ UINT16 MajorRev;
+ UINT16 MinorRev;
+ UINT16 SpinRev;
+} EFI_ACPI_6_2_PPTT_STRUCTURE_ID;
+
+//
+// Known table signatures
+//
+
+///
+/// "RSD PTR " Root System Description Pointer
+///
+#define EFI_ACPI_6_2_ROOT_SYSTEM_DESCRIPTION_POINTER_SIGNATURE SIGNATURE_64('R', 'S', 'D', ' ', 'P', 'T', 'R', ' ')
+
+///
+/// "APIC" Multiple APIC Description Table
+///
+#define EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('A', 'P', 'I', 'C')
+
+///
+/// "BERT" Boot Error Record Table
+///
+#define EFI_ACPI_6_2_BOOT_ERROR_RECORD_TABLE_SIGNATURE SIGNATURE_32('B', 'E', 'R', 'T')
+
+///
+/// "BGRT" Boot Graphics Resource Table
+///
+#define EFI_ACPI_6_2_BOOT_GRAPHICS_RESOURCE_TABLE_SIGNATURE SIGNATURE_32('B', 'G', 'R', 'T')
+
+///
+/// "CPEP" Corrected Platform Error Polling Table
+///
+#define EFI_ACPI_6_2_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_SIGNATURE SIGNATURE_32('C', 'P', 'E', 'P')
+
+///
+/// "DSDT" Differentiated System Description Table
+///
+#define EFI_ACPI_6_2_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('D', 'S', 'D', 'T')
+
+///
+/// "ECDT" Embedded Controller Boot Resources Table
+///
+#define EFI_ACPI_6_2_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE_SIGNATURE SIGNATURE_32('E', 'C', 'D', 'T')
+
+///
+/// "EINJ" Error Injection Table
+///
+#define EFI_ACPI_6_2_ERROR_INJECTION_TABLE_SIGNATURE SIGNATURE_32('E', 'I', 'N', 'J')
+
+///
+/// "ERST" Error Record Serialization Table
+///
+#define EFI_ACPI_6_2_ERROR_RECORD_SERIALIZATION_TABLE_SIGNATURE SIGNATURE_32('E', 'R', 'S', 'T')
+
+///
+/// "FACP" Fixed ACPI Description Table
+///
+#define EFI_ACPI_6_2_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('F', 'A', 'C', 'P')
+
+///
+/// "FACS" Firmware ACPI Control Structure
+///
+#define EFI_ACPI_6_2_FIRMWARE_ACPI_CONTROL_STRUCTURE_SIGNATURE SIGNATURE_32('F', 'A', 'C', 'S')
+
+///
+/// "FPDT" Firmware Performance Data Table
+///
+#define EFI_ACPI_6_2_FIRMWARE_PERFORMANCE_DATA_TABLE_SIGNATURE SIGNATURE_32('F', 'P', 'D', 'T')
+
+///
+/// "GTDT" Generic Timer Description Table
+///
+#define EFI_ACPI_6_2_GENERIC_TIMER_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('G', 'T', 'D', 'T')
+
+///
+/// "HEST" Hardware Error Source Table
+///
+#define EFI_ACPI_6_2_HARDWARE_ERROR_SOURCE_TABLE_SIGNATURE SIGNATURE_32('H', 'E', 'S', 'T')
+
+///
+/// "HMAT" Heterogeneous Memory Attribute Table
+///
+#define EFI_ACPI_6_2_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_SIGNATURE SIGNATURE_32('H', 'M', 'A', 'T')
+
+///
+/// "MPST" Memory Power State Table
+///
+#define EFI_ACPI_6_2_MEMORY_POWER_STATE_TABLE_SIGNATURE SIGNATURE_32('M', 'P', 'S', 'T')
+
+///
+/// "MSCT" Maximum System Characteristics Table
+///
+#define EFI_ACPI_6_2_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_SIGNATURE SIGNATURE_32('M', 'S', 'C', 'T')
+
+///
+/// "NFIT" NVDIMM Firmware Interface Table
+///
+#define EFI_ACPI_6_2_NVDIMM_FIRMWARE_INTERFACE_TABLE_STRUCTURE_SIGNATURE SIGNATURE_32('N', 'F', 'I', 'T')
+
+///
+/// "PDTT" Platform Debug Trigger Table
+///
+#define EFI_ACPI_6_2_PLATFORM_DEBUG_TRIGGER_TABLE_STRUCTURE_SIGNATURE SIGNATURE_32('P', 'D', 'T', 'T')
+
+///
+/// "PMTT" Platform Memory Topology Table
+///
+#define EFI_ACPI_6_2_PLATFORM_MEMORY_TOPOLOGY_TABLE_SIGNATURE SIGNATURE_32('P', 'M', 'T', 'T')
+
+///
+/// "PPTT" Processor Properties Topology Table
+///
+#define EFI_ACPI_6_2_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE SIGNATURE_32('P', 'P', 'T', 'T')
+
+///
+/// "PSDT" Persistent System Description Table
+///
+#define EFI_ACPI_6_2_PERSISTENT_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('P', 'S', 'D', 'T')
+
+///
+/// "RASF" ACPI RAS Feature Table
+///
+#define EFI_ACPI_6_2_ACPI_RAS_FEATURE_TABLE_SIGNATURE SIGNATURE_32('R', 'A', 'S', 'F')
+
+///
+/// "RSDT" Root System Description Table
+///
+#define EFI_ACPI_6_2_ROOT_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('R', 'S', 'D', 'T')
+
+///
+/// "SBST" Smart Battery Specification Table
+///
+#define EFI_ACPI_6_2_SMART_BATTERY_SPECIFICATION_TABLE_SIGNATURE SIGNATURE_32('S', 'B', 'S', 'T')
+
+///
+/// "SDEV" Secure DEVices Table
+///
+#define EFI_ACPI_6_2_SECURE_DEVICES_TABLE_SIGNATURE SIGNATURE_32('S', 'D', 'E', 'V')
+
+///
+/// "SLIT" System Locality Information Table
+///
+#define EFI_ACPI_6_2_SYSTEM_LOCALITY_INFORMATION_TABLE_SIGNATURE SIGNATURE_32('S', 'L', 'I', 'T')
+
+///
+/// "SRAT" System Resource Affinity Table
+///
+#define EFI_ACPI_6_2_SYSTEM_RESOURCE_AFFINITY_TABLE_SIGNATURE SIGNATURE_32('S', 'R', 'A', 'T')
+
+///
+/// "SSDT" Secondary System Description Table
+///
+#define EFI_ACPI_6_2_SECONDARY_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('S', 'S', 'D', 'T')
+
+///
+/// "XSDT" Extended System Description Table
+///
+#define EFI_ACPI_6_2_EXTENDED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('X', 'S', 'D', 'T')
+
+///
+/// "BOOT" MS Simple Boot Spec
+///
+#define EFI_ACPI_6_2_SIMPLE_BOOT_FLAG_TABLE_SIGNATURE SIGNATURE_32('B', 'O', 'O', 'T')
+
+///
+/// "CSRT" MS Core System Resource Table
+///
+#define EFI_ACPI_6_2_CORE_SYSTEM_RESOURCE_TABLE_SIGNATURE SIGNATURE_32('C', 'S', 'R', 'T')
+
+///
+/// "DBG2" MS Debug Port 2 Spec
+///
+#define EFI_ACPI_6_2_DEBUG_PORT_2_TABLE_SIGNATURE SIGNATURE_32('D', 'B', 'G', '2')
+
+///
+/// "DBGP" MS Debug Port Spec
+///
+#define EFI_ACPI_6_2_DEBUG_PORT_TABLE_SIGNATURE SIGNATURE_32('D', 'B', 'G', 'P')
+
+///
+/// "DMAR" DMA Remapping Table
+///
+#define EFI_ACPI_6_2_DMA_REMAPPING_TABLE_SIGNATURE SIGNATURE_32('D', 'M', 'A', 'R')
+
+///
+/// "DPPT" DMA Protection Policy Table
+///
+#define EFI_ACPI_6_2_DMA_PROTECTION_POLICY_TABLE_SIGNATURE SIGNATURE_32('D', 'P', 'P', 'T')
+
+///
+/// "DRTM" Dynamic Root of Trust for Measurement Table
+///
+#define EFI_ACPI_6_2_DYNAMIC_ROOT_OF_TRUST_FOR_MEASUREMENT_TABLE_SIGNATURE SIGNATURE_32('D', 'R', 'T', 'M')
+
+///
+/// "ETDT" Event Timer Description Table
+///
+#define EFI_ACPI_6_2_EVENT_TIMER_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('E', 'T', 'D', 'T')
+
+///
+/// "HPET" IA-PC High Precision Event Timer Table
+///
+#define EFI_ACPI_6_2_HIGH_PRECISION_EVENT_TIMER_TABLE_SIGNATURE SIGNATURE_32('H', 'P', 'E', 'T')
+
+///
+/// "iBFT" iSCSI Boot Firmware Table
+///
+#define EFI_ACPI_6_2_ISCSI_BOOT_FIRMWARE_TABLE_SIGNATURE SIGNATURE_32('i', 'B', 'F', 'T')
+
+///
+/// "IORT" I/O Remapping Table
+///
+#define EFI_ACPI_6_2_IO_REMAPPING_TABLE_SIGNATURE SIGNATURE_32('I', 'O', 'R', 'T')
+
+///
+/// "IVRS" I/O Virtualization Reporting Structure
+///
+#define EFI_ACPI_6_2_IO_VIRTUALIZATION_REPORTING_STRUCTURE_SIGNATURE SIGNATURE_32('I', 'V', 'R', 'S')
+
+///
+/// "LPIT" Low Power Idle Table
+///
+#define EFI_ACPI_6_2_LOW_POWER_IDLE_TABLE_STRUCTURE_SIGNATURE SIGNATURE_32('L', 'P', 'I', 'T')
+
+///
+/// "MCFG" PCI Express Memory Mapped Configuration Space Base Address Description Table
+///
+#define EFI_ACPI_6_2_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('M', 'C', 'F', 'G')
+
+///
+/// "MCHI" Management Controller Host Interface Table
+///
+#define EFI_ACPI_6_2_MANAGEMENT_CONTROLLER_HOST_INTERFACE_TABLE_SIGNATURE SIGNATURE_32('M', 'C', 'H', 'I')
+
+///
+/// "MSDM" MS Data Management Table
+///
+#define EFI_ACPI_6_2_DATA_MANAGEMENT_TABLE_SIGNATURE SIGNATURE_32('M', 'S', 'D', 'M')
+
+///
+/// "PCCT" Platform Communications Channel Table
+///
+#define EFI_ACPI_6_2_PLATFORM_COMMUNICATIONS_CHANNEL_TABLE_SIGNATURE SIGNATURE_32('P', 'C', 'C', 'T')
+
+///
+/// "SDEI" Software Delegated Exceptions Interface Table
+///
+#define EFI_ACPI_6_2_SOFTWARE_DELEGATED_EXCEPTIONS_INTERFACE_TABLE_SIGNATURE SIGNATURE_32('S', 'D', 'E', 'I')
+
+///
+/// "SLIC" MS Software Licensing Table Specification
+///
+#define EFI_ACPI_6_2_SOFTWARE_LICENSING_TABLE_SIGNATURE SIGNATURE_32('S', 'L', 'I', 'C')
+
+///
+/// "SPCR" Serial Port Console Redirection Table
+///
+#define EFI_ACPI_6_2_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE SIGNATURE_32('S', 'P', 'C', 'R')
+
+///
+/// "SPMI" Server Platform Management Interface Table
+///
+#define EFI_ACPI_6_2_SERVER_PLATFORM_MANAGEMENT_INTERFACE_TABLE_SIGNATURE SIGNATURE_32('S', 'P', 'M', 'I')
+
+///
+/// "STAO" _STA Override Table
+///
+#define EFI_ACPI_6_2_STA_OVERRIDE_TABLE_SIGNATURE SIGNATURE_32('S', 'T', 'A', 'O')
+
+///
+/// "TCPA" Trusted Computing Platform Alliance Capabilities Table
+///
+#define EFI_ACPI_6_2_TRUSTED_COMPUTING_PLATFORM_ALLIANCE_CAPABILITIES_TABLE_SIGNATURE SIGNATURE_32('T', 'C', 'P', 'A')
+
+///
+/// "TPM2" Trusted Computing Platform 1 Table
+///
+#define EFI_ACPI_6_2_TRUSTED_COMPUTING_PLATFORM_2_TABLE_SIGNATURE SIGNATURE_32('T', 'P', 'M', '2')
+
+///
+/// "UEFI" UEFI ACPI Data Table
+///
+#define EFI_ACPI_6_2_UEFI_ACPI_DATA_TABLE_SIGNATURE SIGNATURE_32('U', 'E', 'F', 'I')
+
+///
+/// "WAET" Windows ACPI Emulated Devices Table
+///
+#define EFI_ACPI_6_2_WINDOWS_ACPI_EMULATED_DEVICES_TABLE_SIGNATURE SIGNATURE_32('W', 'A', 'E', 'T')
+
+///
+/// "WDAT" Watchdog Action Table
+///
+#define EFI_ACPI_6_2_WATCHDOG_ACTION_TABLE_SIGNATURE SIGNATURE_32('W', 'D', 'A', 'T')
+
+///
+/// "WDRT" Watchdog Resource Table
+///
+#define EFI_ACPI_6_2_WATCHDOG_RESOURCE_TABLE_SIGNATURE SIGNATURE_32('W', 'D', 'R', 'T')
+
+///
+/// "WPBT" MS Platform Binary Table
+///
+#define EFI_ACPI_6_2_PLATFORM_BINARY_TABLE_SIGNATURE SIGNATURE_32('W', 'P', 'B', 'T')
+
+///
+/// "WSMT" Windows SMM Security Mitigation Table
+///
+#define EFI_ACPI_6_2_WINDOWS_SMM_SECURITY_MITIGATION_TABLE_SIGNATURE SIGNATURE_32('W', 'S', 'M', 'T')
+
+///
+/// "XENV" Xen Project Table
+///
+#define EFI_ACPI_6_2_XEN_PROJECT_TABLE_SIGNATURE SIGNATURE_32('X', 'E', 'N', 'V')
+
+#pragma pack()
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/Acpi63.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/Acpi63.h
new file mode 100644
index 0000000000..75f6ccbcef
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/Acpi63.h
@@ -0,0 +1,2983 @@
+/** @file
+ ACPI 6.3 definitions from the ACPI Specification Revision 6.3 Jan, 2019.
+
+ Copyright (c) 2017 - 2022, Intel Corporation. All rights reserved.
+ Copyright (c) 2019 - 2020, ARM Ltd. All rights reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _ACPI_6_3_H_
+#define _ACPI_6_3_H_
+
+#include
+
+//
+// Ensure proper structure formats
+//
+#pragma pack(1)
+
+///
+/// ACPI 6.3 Generic Address Space definition
+///
+typedef struct {
+ UINT8 AddressSpaceId;
+ UINT8 RegisterBitWidth;
+ UINT8 RegisterBitOffset;
+ UINT8 AccessSize;
+ UINT64 Address;
+} EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE;
+
+//
+// Generic Address Space Address IDs
+//
+#define EFI_ACPI_6_3_SYSTEM_MEMORY 0x00
+#define EFI_ACPI_6_3_SYSTEM_IO 0x01
+#define EFI_ACPI_6_3_PCI_CONFIGURATION_SPACE 0x02
+#define EFI_ACPI_6_3_EMBEDDED_CONTROLLER 0x03
+#define EFI_ACPI_6_3_SMBUS 0x04
+#define EFI_ACPI_6_3_SYSTEM_CMOS 0x05
+#define EFI_ACPI_6_3_PCI_BAR_TARGET 0x06
+#define EFI_ACPI_6_3_IPMI 0x07
+#define EFI_ACPI_6_3_GENERAL_PURPOSE_IO 0x08
+#define EFI_ACPI_6_3_GENERIC_SERIAL_BUS 0x09
+#define EFI_ACPI_6_3_PLATFORM_COMMUNICATION_CHANNEL 0x0A
+#define EFI_ACPI_6_3_FUNCTIONAL_FIXED_HARDWARE 0x7F
+
+//
+// Generic Address Space Access Sizes
+//
+#define EFI_ACPI_6_3_UNDEFINED 0
+#define EFI_ACPI_6_3_BYTE 1
+#define EFI_ACPI_6_3_WORD 2
+#define EFI_ACPI_6_3_DWORD 3
+#define EFI_ACPI_6_3_QWORD 4
+
+//
+// ACPI 6.3 table structures
+//
+
+///
+/// Root System Description Pointer Structure
+///
+typedef struct {
+ UINT64 Signature;
+ UINT8 Checksum;
+ UINT8 OemId[6];
+ UINT8 Revision;
+ UINT32 RsdtAddress;
+ UINT32 Length;
+ UINT64 XsdtAddress;
+ UINT8 ExtendedChecksum;
+ UINT8 Reserved[3];
+} EFI_ACPI_6_3_ROOT_SYSTEM_DESCRIPTION_POINTER;
+
+///
+/// RSD_PTR Revision (as defined in ACPI 6.3 spec.)
+///
+#define EFI_ACPI_6_3_ROOT_SYSTEM_DESCRIPTION_POINTER_REVISION 0x02 ///< ACPISpec (Revision 6.3) says current value is 2
+
+///
+/// Common table header, this prefaces all ACPI tables, including FACS, but
+/// excluding the RSD PTR structure
+///
+typedef struct {
+ UINT32 Signature;
+ UINT32 Length;
+} EFI_ACPI_6_3_COMMON_HEADER;
+
+//
+// Root System Description Table
+// No definition needed as it is a common description table header, the same with
+// EFI_ACPI_DESCRIPTION_HEADER, followed by a variable number of UINT32 table pointers.
+//
+
+///
+/// RSDT Revision (as defined in ACPI 6.3 spec.)
+///
+#define EFI_ACPI_6_3_ROOT_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01
+
+//
+// Extended System Description Table
+// No definition needed as it is a common description table header, the same with
+// EFI_ACPI_DESCRIPTION_HEADER, followed by a variable number of UINT64 table pointers.
+//
+
+///
+/// XSDT Revision (as defined in ACPI 6.3 spec.)
+///
+#define EFI_ACPI_6_3_EXTENDED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01
+
+///
+/// Fixed ACPI Description Table Structure (FADT)
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 FirmwareCtrl;
+ UINT32 Dsdt;
+ UINT8 Reserved0;
+ UINT8 PreferredPmProfile;
+ UINT16 SciInt;
+ UINT32 SmiCmd;
+ UINT8 AcpiEnable;
+ UINT8 AcpiDisable;
+ UINT8 S4BiosReq;
+ UINT8 PstateCnt;
+ UINT32 Pm1aEvtBlk;
+ UINT32 Pm1bEvtBlk;
+ UINT32 Pm1aCntBlk;
+ UINT32 Pm1bCntBlk;
+ UINT32 Pm2CntBlk;
+ UINT32 PmTmrBlk;
+ UINT32 Gpe0Blk;
+ UINT32 Gpe1Blk;
+ UINT8 Pm1EvtLen;
+ UINT8 Pm1CntLen;
+ UINT8 Pm2CntLen;
+ UINT8 PmTmrLen;
+ UINT8 Gpe0BlkLen;
+ UINT8 Gpe1BlkLen;
+ UINT8 Gpe1Base;
+ UINT8 CstCnt;
+ UINT16 PLvl2Lat;
+ UINT16 PLvl3Lat;
+ UINT16 FlushSize;
+ UINT16 FlushStride;
+ UINT8 DutyOffset;
+ UINT8 DutyWidth;
+ UINT8 DayAlrm;
+ UINT8 MonAlrm;
+ UINT8 Century;
+ UINT16 IaPcBootArch;
+ UINT8 Reserved1;
+ UINT32 Flags;
+ EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE ResetReg;
+ UINT8 ResetValue;
+ UINT16 ArmBootArch;
+ UINT8 MinorVersion;
+ UINT64 XFirmwareCtrl;
+ UINT64 XDsdt;
+ EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE XPm1aEvtBlk;
+ EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE XPm1bEvtBlk;
+ EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE XPm1aCntBlk;
+ EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE XPm1bCntBlk;
+ EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE XPm2CntBlk;
+ EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE XPmTmrBlk;
+ EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE XGpe0Blk;
+ EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE XGpe1Blk;
+ EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE SleepControlReg;
+ EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE SleepStatusReg;
+ UINT64 HypervisorVendorIdentity;
+} EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE;
+
+///
+/// FADT Version (as defined in ACPI 6.3 spec.)
+///
+#define EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE_REVISION 0x06
+#define EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE_MINOR_REVISION 0x03
+
+//
+// Fixed ACPI Description Table Preferred Power Management Profile
+//
+#define EFI_ACPI_6_3_PM_PROFILE_UNSPECIFIED 0
+#define EFI_ACPI_6_3_PM_PROFILE_DESKTOP 1
+#define EFI_ACPI_6_3_PM_PROFILE_MOBILE 2
+#define EFI_ACPI_6_3_PM_PROFILE_WORKSTATION 3
+#define EFI_ACPI_6_3_PM_PROFILE_ENTERPRISE_SERVER 4
+#define EFI_ACPI_6_3_PM_PROFILE_SOHO_SERVER 5
+#define EFI_ACPI_6_3_PM_PROFILE_APPLIANCE_PC 6
+#define EFI_ACPI_6_3_PM_PROFILE_PERFORMANCE_SERVER 7
+#define EFI_ACPI_6_3_PM_PROFILE_TABLET 8
+
+//
+// Fixed ACPI Description Table Boot Architecture Flags
+// All other bits are reserved and must be set to 0.
+//
+#define EFI_ACPI_6_3_LEGACY_DEVICES BIT0
+#define EFI_ACPI_6_3_8042 BIT1
+#define EFI_ACPI_6_3_VGA_NOT_PRESENT BIT2
+#define EFI_ACPI_6_3_MSI_NOT_SUPPORTED BIT3
+#define EFI_ACPI_6_3_PCIE_ASPM_CONTROLS BIT4
+#define EFI_ACPI_6_3_CMOS_RTC_NOT_PRESENT BIT5
+
+//
+// Fixed ACPI Description Table Arm Boot Architecture Flags
+// All other bits are reserved and must be set to 0.
+//
+#define EFI_ACPI_6_3_ARM_PSCI_COMPLIANT BIT0
+#define EFI_ACPI_6_3_ARM_PSCI_USE_HVC BIT1
+
+//
+// Fixed ACPI Description Table Fixed Feature Flags
+// All other bits are reserved and must be set to 0.
+//
+#define EFI_ACPI_6_3_WBINVD BIT0
+#define EFI_ACPI_6_3_WBINVD_FLUSH BIT1
+#define EFI_ACPI_6_3_PROC_C1 BIT2
+#define EFI_ACPI_6_3_P_LVL2_UP BIT3
+#define EFI_ACPI_6_3_PWR_BUTTON BIT4
+#define EFI_ACPI_6_3_SLP_BUTTON BIT5
+#define EFI_ACPI_6_3_FIX_RTC BIT6
+#define EFI_ACPI_6_3_RTC_S4 BIT7
+#define EFI_ACPI_6_3_TMR_VAL_EXT BIT8
+#define EFI_ACPI_6_3_DCK_CAP BIT9
+#define EFI_ACPI_6_3_RESET_REG_SUP BIT10
+#define EFI_ACPI_6_3_SEALED_CASE BIT11
+#define EFI_ACPI_6_3_HEADLESS BIT12
+#define EFI_ACPI_6_3_CPU_SW_SLP BIT13
+#define EFI_ACPI_6_3_PCI_EXP_WAK BIT14
+#define EFI_ACPI_6_3_USE_PLATFORM_CLOCK BIT15
+#define EFI_ACPI_6_3_S4_RTC_STS_VALID BIT16
+#define EFI_ACPI_6_3_REMOTE_POWER_ON_CAPABLE BIT17
+#define EFI_ACPI_6_3_FORCE_APIC_CLUSTER_MODEL BIT18
+#define EFI_ACPI_6_3_FORCE_APIC_PHYSICAL_DESTINATION_MODE BIT19
+#define EFI_ACPI_6_3_HW_REDUCED_ACPI BIT20
+#define EFI_ACPI_6_3_LOW_POWER_S0_IDLE_CAPABLE BIT21
+
+///
+/// Firmware ACPI Control Structure
+///
+typedef struct {
+ UINT32 Signature;
+ UINT32 Length;
+ UINT32 HardwareSignature;
+ UINT32 FirmwareWakingVector;
+ UINT32 GlobalLock;
+ UINT32 Flags;
+ UINT64 XFirmwareWakingVector;
+ UINT8 Version;
+ UINT8 Reserved0[3];
+ UINT32 OspmFlags;
+ UINT8 Reserved1[24];
+} EFI_ACPI_6_3_FIRMWARE_ACPI_CONTROL_STRUCTURE;
+
+///
+/// FACS Version (as defined in ACPI 6.3 spec.)
+///
+#define EFI_ACPI_6_3_FIRMWARE_ACPI_CONTROL_STRUCTURE_VERSION 0x02
+
+///
+/// Firmware Control Structure Feature Flags
+/// All other bits are reserved and must be set to 0.
+///
+#define EFI_ACPI_6_3_S4BIOS_F BIT0
+#define EFI_ACPI_6_3_64BIT_WAKE_SUPPORTED_F BIT1
+
+///
+/// OSPM Enabled Firmware Control Structure Flags
+/// All other bits are reserved and must be set to 0.
+///
+#define EFI_ACPI_6_3_OSPM_64BIT_WAKE_F BIT0
+
+//
+// Differentiated System Description Table,
+// Secondary System Description Table
+// and Persistent System Description Table,
+// no definition needed as they are common description table header, the same with
+// EFI_ACPI_DESCRIPTION_HEADER, followed by a definition block.
+//
+#define EFI_ACPI_6_3_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x02
+#define EFI_ACPI_6_3_SECONDARY_SYSTEM_DESCRIPTION_TABLE_REVISION 0x02
+
+///
+/// Multiple APIC Description Table header definition. The rest of the table
+/// must be defined in a platform specific manner.
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 LocalApicAddress;
+ UINT32 Flags;
+} EFI_ACPI_6_3_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER;
+
+///
+/// MADT Revision (as defined in ACPI 6.3 spec.)
+///
+#define EFI_ACPI_6_3_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION 0x05
+
+///
+/// Multiple APIC Flags
+/// All other bits are reserved and must be set to 0.
+///
+#define EFI_ACPI_6_3_PCAT_COMPAT BIT0
+
+//
+// Multiple APIC Description Table APIC structure types
+// All other values between 0x0D and 0x7F are reserved and
+// will be ignored by OSPM. 0x80 ~ 0xFF are reserved for OEM.
+//
+#define EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC 0x00
+#define EFI_ACPI_6_3_IO_APIC 0x01
+#define EFI_ACPI_6_3_INTERRUPT_SOURCE_OVERRIDE 0x02
+#define EFI_ACPI_6_3_NON_MASKABLE_INTERRUPT_SOURCE 0x03
+#define EFI_ACPI_6_3_LOCAL_APIC_NMI 0x04
+#define EFI_ACPI_6_3_LOCAL_APIC_ADDRESS_OVERRIDE 0x05
+#define EFI_ACPI_6_3_IO_SAPIC 0x06
+#define EFI_ACPI_6_3_LOCAL_SAPIC 0x07
+#define EFI_ACPI_6_3_PLATFORM_INTERRUPT_SOURCES 0x08
+#define EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC 0x09
+#define EFI_ACPI_6_3_LOCAL_X2APIC_NMI 0x0A
+#define EFI_ACPI_6_3_GIC 0x0B
+#define EFI_ACPI_6_3_GICD 0x0C
+#define EFI_ACPI_6_3_GIC_MSI_FRAME 0x0D
+#define EFI_ACPI_6_3_GICR 0x0E
+#define EFI_ACPI_6_3_GIC_ITS 0x0F
+
+//
+// APIC Structure Definitions
+//
+
+///
+/// Processor Local APIC Structure Definition
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 AcpiProcessorUid;
+ UINT8 ApicId;
+ UINT32 Flags;
+} EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC_STRUCTURE;
+
+///
+/// Local APIC Flags. All other bits are reserved and must be 0.
+///
+#define EFI_ACPI_6_3_LOCAL_APIC_ENABLED BIT0
+#define EFI_ACPI_6_3_LOCAL_APIC_ONLINE_CAPABLE BIT1
+
+///
+/// IO APIC Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 IoApicId;
+ UINT8 Reserved;
+ UINT32 IoApicAddress;
+ UINT32 GlobalSystemInterruptBase;
+} EFI_ACPI_6_3_IO_APIC_STRUCTURE;
+
+///
+/// Interrupt Source Override Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 Bus;
+ UINT8 Source;
+ UINT32 GlobalSystemInterrupt;
+ UINT16 Flags;
+} EFI_ACPI_6_3_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE;
+
+///
+/// Platform Interrupt Sources Structure Definition
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Flags;
+ UINT8 InterruptType;
+ UINT8 ProcessorId;
+ UINT8 ProcessorEid;
+ UINT8 IoSapicVector;
+ UINT32 GlobalSystemInterrupt;
+ UINT32 PlatformInterruptSourceFlags;
+ UINT8 CpeiProcessorOverride;
+ UINT8 Reserved[31];
+} EFI_ACPI_6_3_PLATFORM_INTERRUPT_APIC_STRUCTURE;
+
+//
+// MPS INTI flags.
+// All other bits are reserved and must be set to 0.
+//
+#define EFI_ACPI_6_3_POLARITY (3 << 0)
+#define EFI_ACPI_6_3_TRIGGER_MODE (3 << 2)
+
+///
+/// Non-Maskable Interrupt Source Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Flags;
+ UINT32 GlobalSystemInterrupt;
+} EFI_ACPI_6_3_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE;
+
+///
+/// Local APIC NMI Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 AcpiProcessorUid;
+ UINT16 Flags;
+ UINT8 LocalApicLint;
+} EFI_ACPI_6_3_LOCAL_APIC_NMI_STRUCTURE;
+
+///
+/// Local APIC Address Override Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Reserved;
+ UINT64 LocalApicAddress;
+} EFI_ACPI_6_3_LOCAL_APIC_ADDRESS_OVERRIDE_STRUCTURE;
+
+///
+/// IO SAPIC Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 IoApicId;
+ UINT8 Reserved;
+ UINT32 GlobalSystemInterruptBase;
+ UINT64 IoSapicAddress;
+} EFI_ACPI_6_3_IO_SAPIC_STRUCTURE;
+
+///
+/// Local SAPIC Structure
+/// This struct followed by a null-terminated ASCII string - ACPI Processor UID String
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 AcpiProcessorId;
+ UINT8 LocalSapicId;
+ UINT8 LocalSapicEid;
+ UINT8 Reserved[3];
+ UINT32 Flags;
+ UINT32 ACPIProcessorUIDValue;
+} EFI_ACPI_6_3_PROCESSOR_LOCAL_SAPIC_STRUCTURE;
+
+///
+/// Platform Interrupt Sources Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Flags;
+ UINT8 InterruptType;
+ UINT8 ProcessorId;
+ UINT8 ProcessorEid;
+ UINT8 IoSapicVector;
+ UINT32 GlobalSystemInterrupt;
+ UINT32 PlatformInterruptSourceFlags;
+} EFI_ACPI_6_3_PLATFORM_INTERRUPT_SOURCES_STRUCTURE;
+
+///
+/// Platform Interrupt Source Flags.
+/// All other bits are reserved and must be set to 0.
+///
+#define EFI_ACPI_6_3_CPEI_PROCESSOR_OVERRIDE BIT0
+
+///
+/// Processor Local x2APIC Structure Definition
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 Reserved[2];
+ UINT32 X2ApicId;
+ UINT32 Flags;
+ UINT32 AcpiProcessorUid;
+} EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC_STRUCTURE;
+
+///
+/// Local x2APIC NMI Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Flags;
+ UINT32 AcpiProcessorUid;
+ UINT8 LocalX2ApicLint;
+ UINT8 Reserved[3];
+} EFI_ACPI_6_3_LOCAL_X2APIC_NMI_STRUCTURE;
+
+///
+/// GIC Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Reserved;
+ UINT32 CPUInterfaceNumber;
+ UINT32 AcpiProcessorUid;
+ UINT32 Flags;
+ UINT32 ParkingProtocolVersion;
+ UINT32 PerformanceInterruptGsiv;
+ UINT64 ParkedAddress;
+ UINT64 PhysicalBaseAddress;
+ UINT64 GICV;
+ UINT64 GICH;
+ UINT32 VGICMaintenanceInterrupt;
+ UINT64 GICRBaseAddress;
+ UINT64 MPIDR;
+ UINT8 ProcessorPowerEfficiencyClass;
+ UINT8 Reserved2;
+ UINT16 SpeOverflowInterrupt;
+} EFI_ACPI_6_3_GIC_STRUCTURE;
+
+///
+/// GIC Flags. All other bits are reserved and must be 0.
+///
+#define EFI_ACPI_6_3_GIC_ENABLED BIT0
+#define EFI_ACPI_6_3_PERFORMANCE_INTERRUPT_MODEL BIT1
+#define EFI_ACPI_6_3_VGIC_MAINTENANCE_INTERRUPT_MODE_FLAGS BIT2
+
+///
+/// GIC Distributor Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Reserved1;
+ UINT32 GicId;
+ UINT64 PhysicalBaseAddress;
+ UINT32 SystemVectorBase;
+ UINT8 GicVersion;
+ UINT8 Reserved2[3];
+} EFI_ACPI_6_3_GIC_DISTRIBUTOR_STRUCTURE;
+
+///
+/// GIC Version
+///
+#define EFI_ACPI_6_3_GIC_V1 0x01
+#define EFI_ACPI_6_3_GIC_V2 0x02
+#define EFI_ACPI_6_3_GIC_V3 0x03
+#define EFI_ACPI_6_3_GIC_V4 0x04
+
+///
+/// GIC MSI Frame Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Reserved1;
+ UINT32 GicMsiFrameId;
+ UINT64 PhysicalBaseAddress;
+ UINT32 Flags;
+ UINT16 SPICount;
+ UINT16 SPIBase;
+} EFI_ACPI_6_3_GIC_MSI_FRAME_STRUCTURE;
+
+///
+/// GIC MSI Frame Flags. All other bits are reserved and must be 0.
+///
+#define EFI_ACPI_6_3_SPI_COUNT_BASE_SELECT BIT0
+
+///
+/// GICR Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Reserved;
+ UINT64 DiscoveryRangeBaseAddress;
+ UINT32 DiscoveryRangeLength;
+} EFI_ACPI_6_3_GICR_STRUCTURE;
+
+///
+/// GIC Interrupt Translation Service Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Reserved;
+ UINT32 GicItsId;
+ UINT64 PhysicalBaseAddress;
+ UINT32 Reserved2;
+} EFI_ACPI_6_3_GIC_ITS_STRUCTURE;
+
+///
+/// Smart Battery Description Table (SBST)
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 WarningEnergyLevel;
+ UINT32 LowEnergyLevel;
+ UINT32 CriticalEnergyLevel;
+} EFI_ACPI_6_3_SMART_BATTERY_DESCRIPTION_TABLE;
+
+///
+/// SBST Version (as defined in ACPI 6.3 spec.)
+///
+#define EFI_ACPI_6_3_SMART_BATTERY_DESCRIPTION_TABLE_REVISION 0x01
+
+///
+/// Embedded Controller Boot Resources Table (ECDT)
+/// The table is followed by a null terminated ASCII string that contains
+/// a fully qualified reference to the name space object.
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE EcControl;
+ EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE EcData;
+ UINT32 Uid;
+ UINT8 GpeBit;
+} EFI_ACPI_6_3_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE;
+
+///
+/// ECDT Version (as defined in ACPI 6.3 spec.)
+///
+#define EFI_ACPI_6_3_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE_REVISION 0x01
+
+///
+/// System Resource Affinity Table (SRAT). The rest of the table
+/// must be defined in a platform specific manner.
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 Reserved1; ///< Must be set to 1
+ UINT64 Reserved2;
+} EFI_ACPI_6_3_SYSTEM_RESOURCE_AFFINITY_TABLE_HEADER;
+
+///
+/// SRAT Version (as defined in ACPI 6.3 spec.)
+///
+#define EFI_ACPI_6_3_SYSTEM_RESOURCE_AFFINITY_TABLE_REVISION 0x03
+
+//
+// SRAT structure types.
+// All other values between 0x06 an 0xFF are reserved and
+// will be ignored by OSPM.
+//
+#define EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC_SAPIC_AFFINITY 0x00
+#define EFI_ACPI_6_3_MEMORY_AFFINITY 0x01
+#define EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC_AFFINITY 0x02
+#define EFI_ACPI_6_3_GICC_AFFINITY 0x03
+#define EFI_ACPI_6_3_GIC_ITS_AFFINITY 0x04
+#define EFI_ACPI_6_3_GENERIC_INITIATOR_AFFINITY 0x05
+
+///
+/// Processor Local APIC/SAPIC Affinity Structure Definition
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 ProximityDomain7To0;
+ UINT8 ApicId;
+ UINT32 Flags;
+ UINT8 LocalSapicEid;
+ UINT8 ProximityDomain31To8[3];
+ UINT32 ClockDomain;
+} EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC_SAPIC_AFFINITY_STRUCTURE;
+
+///
+/// Local APIC/SAPIC Flags. All other bits are reserved and must be 0.
+///
+#define EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC_SAPIC_ENABLED (1 << 0)
+
+///
+/// Memory Affinity Structure Definition
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT32 ProximityDomain;
+ UINT16 Reserved1;
+ UINT32 AddressBaseLow;
+ UINT32 AddressBaseHigh;
+ UINT32 LengthLow;
+ UINT32 LengthHigh;
+ UINT32 Reserved2;
+ UINT32 Flags;
+ UINT64 Reserved3;
+} EFI_ACPI_6_3_MEMORY_AFFINITY_STRUCTURE;
+
+//
+// Memory Flags. All other bits are reserved and must be 0.
+//
+#define EFI_ACPI_6_3_MEMORY_ENABLED (1 << 0)
+#define EFI_ACPI_6_3_MEMORY_HOT_PLUGGABLE (1 << 1)
+#define EFI_ACPI_6_3_MEMORY_NONVOLATILE (1 << 2)
+
+///
+/// Processor Local x2APIC Affinity Structure Definition
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 Reserved1[2];
+ UINT32 ProximityDomain;
+ UINT32 X2ApicId;
+ UINT32 Flags;
+ UINT32 ClockDomain;
+ UINT8 Reserved2[4];
+} EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC_AFFINITY_STRUCTURE;
+
+///
+/// GICC Affinity Structure Definition
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT32 ProximityDomain;
+ UINT32 AcpiProcessorUid;
+ UINT32 Flags;
+ UINT32 ClockDomain;
+} EFI_ACPI_6_3_GICC_AFFINITY_STRUCTURE;
+
+///
+/// GICC Flags. All other bits are reserved and must be 0.
+///
+#define EFI_ACPI_6_3_GICC_ENABLED (1 << 0)
+
+///
+/// GIC Interrupt Translation Service (ITS) Affinity Structure Definition
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT32 ProximityDomain;
+ UINT8 Reserved[2];
+ UINT32 ItsId;
+} EFI_ACPI_6_3_GIC_ITS_AFFINITY_STRUCTURE;
+
+//
+// Generic Initiator Affinity Structure Device Handle Types
+// All other values between 0x02 an 0xFF are reserved and
+// will be ignored by OSPM.
+//
+#define EFI_ACPI_6_3_ACPI_DEVICE_HANDLE 0x00
+#define EFI_ACPI_6_3_PCI_DEVICE_HANDLE 0x01
+
+///
+/// Device Handle - ACPI
+///
+typedef struct {
+ UINT64 AcpiHid;
+ UINT32 AcpiUid;
+ UINT8 Reserved[4];
+} EFI_ACPI_6_3_DEVICE_HANDLE_ACPI;
+
+///
+/// Device Handle - PCI
+///
+typedef struct {
+ UINT16 PciSegment;
+ UINT16 PciBdfNumber;
+ UINT8 Reserved[12];
+} EFI_ACPI_6_3_DEVICE_HANDLE_PCI;
+
+///
+/// Generic Initiator Affinity Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 Reserved1;
+ UINT8 DeviceHandleType;
+ UINT32 ProximityDomain;
+
+ union {
+ EFI_ACPI_6_3_DEVICE_HANDLE_ACPI Acpi;
+ EFI_ACPI_6_3_DEVICE_HANDLE_PCI Pci;
+ } DeviceHandle;
+
+ UINT32 Flags;
+ UINT8 Reserved2[4];
+} EFI_ACPI_6_3_GENERIC_INITIATOR_AFFINITY_STRUCTURE;
+
+///
+/// Generic Initiator Affinity Structure Flags. All other bits are reserved
+/// and must be 0.
+///
+#define EFI_ACPI_6_3_GENERIC_INITIATOR_AFFINITY_STRUCTURE_ENABLED (1 << 0)
+
+///
+/// System Locality Distance Information Table (SLIT).
+/// The rest of the table is a matrix.
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT64 NumberOfSystemLocalities;
+} EFI_ACPI_6_3_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_HEADER;
+
+///
+/// SLIT Version (as defined in ACPI 6.3 spec.)
+///
+#define EFI_ACPI_6_3_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_REVISION 0x01
+
+///
+/// Corrected Platform Error Polling Table (CPEP)
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT8 Reserved[8];
+} EFI_ACPI_6_3_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_HEADER;
+
+///
+/// CPEP Version (as defined in ACPI 6.3 spec.)
+///
+#define EFI_ACPI_6_3_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_REVISION 0x01
+
+//
+// CPEP processor structure types.
+//
+#define EFI_ACPI_6_3_CPEP_PROCESSOR_APIC_SAPIC 0x00
+
+///
+/// Corrected Platform Error Polling Processor Structure Definition
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 ProcessorId;
+ UINT8 ProcessorEid;
+ UINT32 PollingInterval;
+} EFI_ACPI_6_3_CPEP_PROCESSOR_APIC_SAPIC_STRUCTURE;
+
+///
+/// Maximum System Characteristics Table (MSCT)
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 OffsetProxDomInfo;
+ UINT32 MaximumNumberOfProximityDomains;
+ UINT32 MaximumNumberOfClockDomains;
+ UINT64 MaximumPhysicalAddress;
+} EFI_ACPI_6_3_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_HEADER;
+
+///
+/// MSCT Version (as defined in ACPI 6.3 spec.)
+///
+#define EFI_ACPI_6_3_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_REVISION 0x01
+
+///
+/// Maximum Proximity Domain Information Structure Definition
+///
+typedef struct {
+ UINT8 Revision;
+ UINT8 Length;
+ UINT32 ProximityDomainRangeLow;
+ UINT32 ProximityDomainRangeHigh;
+ UINT32 MaximumProcessorCapacity;
+ UINT64 MaximumMemoryCapacity;
+} EFI_ACPI_6_3_MAXIMUM_PROXIMITY_DOMAIN_INFORMATION_STRUCTURE;
+
+///
+/// ACPI RAS Feature Table definition.
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT8 PlatformCommunicationChannelIdentifier[12];
+} EFI_ACPI_6_3_RAS_FEATURE_TABLE;
+
+///
+/// RASF Version (as defined in ACPI 6.3 spec.)
+///
+#define EFI_ACPI_6_3_RAS_FEATURE_TABLE_REVISION 0x01
+
+///
+/// ACPI RASF Platform Communication Channel Shared Memory Region definition.
+///
+typedef struct {
+ UINT32 Signature;
+ UINT16 Command;
+ UINT16 Status;
+ UINT16 Version;
+ UINT8 RASCapabilities[16];
+ UINT8 SetRASCapabilities[16];
+ UINT16 NumberOfRASFParameterBlocks;
+ UINT32 SetRASCapabilitiesStatus;
+} EFI_ACPI_6_3_RASF_PLATFORM_COMMUNICATION_CHANNEL_SHARED_MEMORY_REGION;
+
+///
+/// ACPI RASF PCC command code
+///
+#define EFI_ACPI_6_3_RASF_PCC_COMMAND_CODE_EXECUTE_RASF_COMMAND 0x01
+
+///
+/// ACPI RASF Platform RAS Capabilities
+///
+#define EFI_ACPI_6_3_RASF_PLATFORM_RAS_CAPABILITY_HARDWARE_BASED_PATROL_SCRUB_SUPPORTED BIT0
+#define EFI_ACPI_6_3_RASF_PLATFORM_RAS_CAPABILITY_HARDWARE_BASED_PATROL_SCRUB_SUPPORTED_AND_EXPOSED_TO_SOFTWARE BIT1
+#define EFI_ACPI_6_3_RASF_PLATFORM_RAS_CAPABILITY_CPU_CACHE_FLUSH_TO_NVDIMM_DURABILITY_ON_POWER_LOSS BIT2
+#define EFI_ACPI_6_3_RASF_PLATFORM_RAS_CAPABILITY_MEMORY_CONTROLLER_FLUSH_TO_NVDIMM_DURABILITY_ON_POWER_LOSS BIT3
+#define EFI_ACPI_6_3_RASF_PLATFORM_RAS_CAPABILITY_BYTE_ADDRESSABLE_PERSISTENT_MEMORY_HARDWARE_MIRRORING BIT4
+
+///
+/// ACPI RASF Parameter Block structure for PATROL_SCRUB
+///
+typedef struct {
+ UINT16 Type;
+ UINT16 Version;
+ UINT16 Length;
+ UINT16 PatrolScrubCommand;
+ UINT64 RequestedAddressRange[2];
+ UINT64 ActualAddressRange[2];
+ UINT16 Flags;
+ UINT8 RequestedSpeed;
+} EFI_ACPI_6_3_RASF_PATROL_SCRUB_PLATFORM_BLOCK_STRUCTURE;
+
+///
+/// ACPI RASF Patrol Scrub command
+///
+#define EFI_ACPI_6_3_RASF_PATROL_SCRUB_COMMAND_GET_PATROL_PARAMETERS 0x01
+#define EFI_ACPI_6_3_RASF_PATROL_SCRUB_COMMAND_START_PATROL_SCRUBBER 0x02
+#define EFI_ACPI_6_3_RASF_PATROL_SCRUB_COMMAND_STOP_PATROL_SCRUBBER 0x03
+
+///
+/// Memory Power State Table definition.
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT8 PlatformCommunicationChannelIdentifier;
+ UINT8 Reserved[3];
+ // Memory Power Node Structure
+ // Memory Power State Characteristics
+} EFI_ACPI_6_3_MEMORY_POWER_STATUS_TABLE;
+
+///
+/// MPST Version (as defined in ACPI 6.3 spec.)
+///
+#define EFI_ACPI_6_3_MEMORY_POWER_STATE_TABLE_REVISION 0x01
+
+///
+/// MPST Platform Communication Channel Shared Memory Region definition.
+///
+typedef struct {
+ UINT32 Signature;
+ UINT16 Command;
+ UINT16 Status;
+ UINT32 MemoryPowerCommandRegister;
+ UINT32 MemoryPowerStatusRegister;
+ UINT32 PowerStateId;
+ UINT32 MemoryPowerNodeId;
+ UINT64 MemoryEnergyConsumed;
+ UINT64 ExpectedAveragePowerComsuned;
+} EFI_ACPI_6_3_MPST_PLATFORM_COMMUNICATION_CHANNEL_SHARED_MEMORY_REGION;
+
+///
+/// ACPI MPST PCC command code
+///
+#define EFI_ACPI_6_3_MPST_PCC_COMMAND_CODE_EXECUTE_MPST_COMMAND 0x03
+
+///
+/// ACPI MPST Memory Power command
+///
+#define EFI_ACPI_6_3_MPST_MEMORY_POWER_COMMAND_GET_MEMORY_POWER_STATE 0x01
+#define EFI_ACPI_6_3_MPST_MEMORY_POWER_COMMAND_SET_MEMORY_POWER_STATE 0x02
+#define EFI_ACPI_6_3_MPST_MEMORY_POWER_COMMAND_GET_AVERAGE_POWER_CONSUMED 0x03
+#define EFI_ACPI_6_3_MPST_MEMORY_POWER_COMMAND_GET_MEMORY_ENERGY_CONSUMED 0x04
+
+///
+/// MPST Memory Power Node Table
+///
+typedef struct {
+ UINT8 PowerStateValue;
+ UINT8 PowerStateInformationIndex;
+} EFI_ACPI_6_3_MPST_MEMORY_POWER_STATE;
+
+typedef struct {
+ UINT8 Flag;
+ UINT8 Reserved;
+ UINT16 MemoryPowerNodeId;
+ UINT32 Length;
+ UINT64 AddressBase;
+ UINT64 AddressLength;
+ UINT32 NumberOfPowerStates;
+ UINT32 NumberOfPhysicalComponents;
+ // EFI_ACPI_6_3_MPST_MEMORY_POWER_STATE MemoryPowerState[NumberOfPowerStates];
+ // UINT16 PhysicalComponentIdentifier[NumberOfPhysicalComponents];
+} EFI_ACPI_6_3_MPST_MEMORY_POWER_STRUCTURE;
+
+#define EFI_ACPI_6_3_MPST_MEMORY_POWER_STRUCTURE_FLAG_ENABLE 0x01
+#define EFI_ACPI_6_3_MPST_MEMORY_POWER_STRUCTURE_FLAG_POWER_MANAGED 0x02
+#define EFI_ACPI_6_3_MPST_MEMORY_POWER_STRUCTURE_FLAG_HOT_PLUGGABLE 0x04
+
+typedef struct {
+ UINT16 MemoryPowerNodeCount;
+ UINT8 Reserved[2];
+} EFI_ACPI_6_3_MPST_MEMORY_POWER_NODE_TABLE;
+
+///
+/// MPST Memory Power State Characteristics Table
+///
+typedef struct {
+ UINT8 PowerStateStructureID;
+ UINT8 Flag;
+ UINT16 Reserved;
+ UINT32 AveragePowerConsumedInMPS0;
+ UINT32 RelativePowerSavingToMPS0;
+ UINT64 ExitLatencyToMPS0;
+} EFI_ACPI_6_3_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE;
+
+#define EFI_ACPI_6_3_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_MEMORY_CONTENT_PRESERVED 0x01
+#define EFI_ACPI_6_3_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_AUTONOMOUS_MEMORY_POWER_STATE_ENTRY 0x02
+#define EFI_ACPI_6_3_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_AUTONOMOUS_MEMORY_POWER_STATE_EXIT 0x04
+
+typedef struct {
+ UINT16 MemoryPowerStateCharacteristicsCount;
+ UINT8 Reserved[2];
+} EFI_ACPI_6_3_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_TABLE;
+
+///
+/// Memory Topology Table definition.
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 Reserved;
+} EFI_ACPI_6_3_MEMORY_TOPOLOGY_TABLE;
+
+///
+/// PMTT Version (as defined in ACPI 6.3 spec.)
+///
+#define EFI_ACPI_6_3_MEMORY_TOPOLOGY_TABLE_REVISION 0x01
+
+///
+/// Common Memory Aggregator Device Structure.
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Reserved;
+ UINT16 Length;
+ UINT16 Flags;
+ UINT16 Reserved1;
+} EFI_ACPI_6_3_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE;
+
+///
+/// Memory Aggregator Device Type
+///
+#define EFI_ACPI_6_3_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_SOCKET 0x0
+#define EFI_ACPI_6_3_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_MEMORY_CONTROLLER 0x1
+#define EFI_ACPI_6_3_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_DIMM 0x2
+
+///
+/// Socket Memory Aggregator Device Structure.
+///
+typedef struct {
+ EFI_ACPI_6_3_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE Header;
+ UINT16 SocketIdentifier;
+ UINT16 Reserved;
+ // EFI_ACPI_6_3_PMMT_MEMORY_CONTROLLER_MEMORY_AGGREGATOR_DEVICE_STRUCTURE MemoryController[];
+} EFI_ACPI_6_3_PMMT_SOCKET_MEMORY_AGGREGATOR_DEVICE_STRUCTURE;
+
+///
+/// MemoryController Memory Aggregator Device Structure.
+///
+typedef struct {
+ EFI_ACPI_6_3_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE Header;
+ UINT32 ReadLatency;
+ UINT32 WriteLatency;
+ UINT32 ReadBandwidth;
+ UINT32 WriteBandwidth;
+ UINT16 OptimalAccessUnit;
+ UINT16 OptimalAccessAlignment;
+ UINT16 Reserved;
+ UINT16 NumberOfProximityDomains;
+ // UINT32 ProximityDomain[NumberOfProximityDomains];
+ // EFI_ACPI_6_3_PMMT_DIMM_MEMORY_AGGREGATOR_DEVICE_STRUCTURE PhysicalComponent[];
+} EFI_ACPI_6_3_PMMT_MEMORY_CONTROLLER_MEMORY_AGGREGATOR_DEVICE_STRUCTURE;
+
+///
+/// DIMM Memory Aggregator Device Structure.
+///
+typedef struct {
+ EFI_ACPI_6_3_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE Header;
+ UINT16 PhysicalComponentIdentifier;
+ UINT16 Reserved;
+ UINT32 SizeOfDimm;
+ UINT32 SmbiosHandle;
+} EFI_ACPI_6_3_PMMT_DIMM_MEMORY_AGGREGATOR_DEVICE_STRUCTURE;
+
+///
+/// Boot Graphics Resource Table definition.
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ ///
+ /// 2-bytes (16 bit) version ID. This value must be 1.
+ ///
+ UINT16 Version;
+ ///
+ /// 1-byte status field indicating current status about the table.
+ /// Bits[7:1] = Reserved (must be zero)
+ /// Bit [0] = Valid. A one indicates the boot image graphic is valid.
+ ///
+ UINT8 Status;
+ ///
+ /// 1-byte enumerated type field indicating format of the image.
+ /// 0 = Bitmap
+ /// 1 - 255 Reserved (for future use)
+ ///
+ UINT8 ImageType;
+ ///
+ /// 8-byte (64 bit) physical address pointing to the firmware's in-memory copy
+ /// of the image bitmap.
+ ///
+ UINT64 ImageAddress;
+ ///
+ /// A 4-byte (32-bit) unsigned long describing the display X-offset of the boot image.
+ /// (X, Y) display offset of the top left corner of the boot image.
+ /// The top left corner of the display is at offset (0, 0).
+ ///
+ UINT32 ImageOffsetX;
+ ///
+ /// A 4-byte (32-bit) unsigned long describing the display Y-offset of the boot image.
+ /// (X, Y) display offset of the top left corner of the boot image.
+ /// The top left corner of the display is at offset (0, 0).
+ ///
+ UINT32 ImageOffsetY;
+} EFI_ACPI_6_3_BOOT_GRAPHICS_RESOURCE_TABLE;
+
+///
+/// BGRT Revision
+///
+#define EFI_ACPI_6_3_BOOT_GRAPHICS_RESOURCE_TABLE_REVISION 1
+
+///
+/// BGRT Version
+///
+#define EFI_ACPI_6_3_BGRT_VERSION 0x01
+
+///
+/// BGRT Status
+///
+#define EFI_ACPI_6_3_BGRT_STATUS_NOT_DISPLAYED 0x00
+#define EFI_ACPI_6_3_BGRT_STATUS_DISPLAYED 0x01
+
+///
+/// BGRT Image Type
+///
+#define EFI_ACPI_6_3_BGRT_IMAGE_TYPE_BMP 0x00
+
+///
+/// FPDT Version (as defined in ACPI 6.3 spec.)
+///
+#define EFI_ACPI_6_3_FIRMWARE_PERFORMANCE_DATA_TABLE_REVISION 0x01
+
+///
+/// FPDT Performance Record Types
+///
+#define EFI_ACPI_6_3_FPDT_RECORD_TYPE_FIRMWARE_BASIC_BOOT_POINTER 0x0000
+#define EFI_ACPI_6_3_FPDT_RECORD_TYPE_S3_PERFORMANCE_TABLE_POINTER 0x0001
+
+///
+/// FPDT Performance Record Revision
+///
+#define EFI_ACPI_6_3_FPDT_RECORD_REVISION_FIRMWARE_BASIC_BOOT_POINTER 0x01
+#define EFI_ACPI_6_3_FPDT_RECORD_REVISION_S3_PERFORMANCE_TABLE_POINTER 0x01
+
+///
+/// FPDT Runtime Performance Record Types
+///
+#define EFI_ACPI_6_3_FPDT_RUNTIME_RECORD_TYPE_S3_RESUME 0x0000
+#define EFI_ACPI_6_3_FPDT_RUNTIME_RECORD_TYPE_S3_SUSPEND 0x0001
+#define EFI_ACPI_6_3_FPDT_RUNTIME_RECORD_TYPE_FIRMWARE_BASIC_BOOT 0x0002
+
+///
+/// FPDT Runtime Performance Record Revision
+///
+#define EFI_ACPI_6_3_FPDT_RUNTIME_RECORD_REVISION_S3_RESUME 0x01
+#define EFI_ACPI_6_3_FPDT_RUNTIME_RECORD_REVISION_S3_SUSPEND 0x01
+#define EFI_ACPI_6_3_FPDT_RUNTIME_RECORD_REVISION_FIRMWARE_BASIC_BOOT 0x02
+
+///
+/// FPDT Performance Record header
+///
+typedef struct {
+ UINT16 Type;
+ UINT8 Length;
+ UINT8 Revision;
+} EFI_ACPI_6_3_FPDT_PERFORMANCE_RECORD_HEADER;
+
+///
+/// FPDT Performance Table header
+///
+typedef struct {
+ UINT32 Signature;
+ UINT32 Length;
+} EFI_ACPI_6_3_FPDT_PERFORMANCE_TABLE_HEADER;
+
+///
+/// FPDT Firmware Basic Boot Performance Pointer Record Structure
+///
+typedef struct {
+ EFI_ACPI_6_3_FPDT_PERFORMANCE_RECORD_HEADER Header;
+ UINT32 Reserved;
+ ///
+ /// 64-bit processor-relative physical address of the Basic Boot Performance Table.
+ ///
+ UINT64 BootPerformanceTablePointer;
+} EFI_ACPI_6_3_FPDT_BOOT_PERFORMANCE_TABLE_POINTER_RECORD;
+
+///
+/// FPDT S3 Performance Table Pointer Record Structure
+///
+typedef struct {
+ EFI_ACPI_6_3_FPDT_PERFORMANCE_RECORD_HEADER Header;
+ UINT32 Reserved;
+ ///
+ /// 64-bit processor-relative physical address of the S3 Performance Table.
+ ///
+ UINT64 S3PerformanceTablePointer;
+} EFI_ACPI_6_3_FPDT_S3_PERFORMANCE_TABLE_POINTER_RECORD;
+
+///
+/// FPDT Firmware Basic Boot Performance Record Structure
+///
+typedef struct {
+ EFI_ACPI_6_3_FPDT_PERFORMANCE_RECORD_HEADER Header;
+ UINT32 Reserved;
+ ///
+ /// Timer value logged at the beginning of firmware image execution.
+ /// This may not always be zero or near zero.
+ ///
+ UINT64 ResetEnd;
+ ///
+ /// Timer value logged just prior to loading the OS boot loader into memory.
+ /// For non-UEFI compatible boots, this field must be zero.
+ ///
+ UINT64 OsLoaderLoadImageStart;
+ ///
+ /// Timer value logged just prior to launching the previously loaded OS boot loader image.
+ /// For non-UEFI compatible boots, the timer value logged will be just prior
+ /// to the INT 19h handler invocation.
+ ///
+ UINT64 OsLoaderStartImageStart;
+ ///
+ /// Timer value logged at the point when the OS loader calls the
+ /// ExitBootServices function for UEFI compatible firmware.
+ /// For non-UEFI compatible boots, this field must be zero.
+ ///
+ UINT64 ExitBootServicesEntry;
+ ///
+ /// Timer value logged at the point just prior towhen the OS loader gaining
+ /// control back from calls the ExitBootServices function for UEFI compatible firmware.
+ /// For non-UEFI compatible boots, this field must be zero.
+ ///
+ UINT64 ExitBootServicesExit;
+} EFI_ACPI_6_3_FPDT_FIRMWARE_BASIC_BOOT_RECORD;
+
+///
+/// FPDT Firmware Basic Boot Performance Table signature
+///
+#define EFI_ACPI_6_3_FPDT_BOOT_PERFORMANCE_TABLE_SIGNATURE SIGNATURE_32('F', 'B', 'P', 'T')
+
+//
+// FPDT Firmware Basic Boot Performance Table
+//
+typedef struct {
+ EFI_ACPI_6_3_FPDT_PERFORMANCE_TABLE_HEADER Header;
+ //
+ // one or more Performance Records.
+ //
+} EFI_ACPI_6_3_FPDT_FIRMWARE_BASIC_BOOT_TABLE;
+
+///
+/// FPDT "S3PT" S3 Performance Table
+///
+#define EFI_ACPI_6_3_FPDT_S3_PERFORMANCE_TABLE_SIGNATURE SIGNATURE_32('S', '3', 'P', 'T')
+
+//
+// FPDT Firmware S3 Boot Performance Table
+//
+typedef struct {
+ EFI_ACPI_6_3_FPDT_PERFORMANCE_TABLE_HEADER Header;
+ //
+ // one or more Performance Records.
+ //
+} EFI_ACPI_6_3_FPDT_FIRMWARE_S3_BOOT_TABLE;
+
+///
+/// FPDT Basic S3 Resume Performance Record
+///
+typedef struct {
+ EFI_ACPI_6_3_FPDT_PERFORMANCE_RECORD_HEADER Header;
+ ///
+ /// A count of the number of S3 resume cycles since the last full boot sequence.
+ ///
+ UINT32 ResumeCount;
+ ///
+ /// Timer recorded at the end of BIOS S3 resume, just prior to handoff to the
+ /// OS waking vector. Only the most recent resume cycle's time is retained.
+ ///
+ UINT64 FullResume;
+ ///
+ /// Average timer value of all resume cycles logged since the last full boot
+ /// sequence, including the most recent resume. Note that the entire log of
+ /// timer values does not need to be retained in order to calculate this average.
+ ///
+ UINT64 AverageResume;
+} EFI_ACPI_6_3_FPDT_S3_RESUME_RECORD;
+
+///
+/// FPDT Basic S3 Suspend Performance Record
+///
+typedef struct {
+ EFI_ACPI_6_3_FPDT_PERFORMANCE_RECORD_HEADER Header;
+ ///
+ /// Timer value recorded at the OS write to SLP_TYP upon entry to S3.
+ /// Only the most recent suspend cycle's timer value is retained.
+ ///
+ UINT64 SuspendStart;
+ ///
+ /// Timer value recorded at the final firmware write to SLP_TYP (or other
+ /// mechanism) used to trigger hardware entry to S3.
+ /// Only the most recent suspend cycle's timer value is retained.
+ ///
+ UINT64 SuspendEnd;
+} EFI_ACPI_6_3_FPDT_S3_SUSPEND_RECORD;
+
+///
+/// Firmware Performance Record Table definition.
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+} EFI_ACPI_6_3_FIRMWARE_PERFORMANCE_RECORD_TABLE;
+
+///
+/// Generic Timer Description Table definition.
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT64 CntControlBasePhysicalAddress;
+ UINT32 Reserved;
+ UINT32 SecurePL1TimerGSIV;
+ UINT32 SecurePL1TimerFlags;
+ UINT32 NonSecurePL1TimerGSIV;
+ UINT32 NonSecurePL1TimerFlags;
+ UINT32 VirtualTimerGSIV;
+ UINT32 VirtualTimerFlags;
+ UINT32 NonSecurePL2TimerGSIV;
+ UINT32 NonSecurePL2TimerFlags;
+ UINT64 CntReadBasePhysicalAddress;
+ UINT32 PlatformTimerCount;
+ UINT32 PlatformTimerOffset;
+ UINT32 VirtualPL2TimerGSIV;
+ UINT32 VirtualPL2TimerFlags;
+} EFI_ACPI_6_3_GENERIC_TIMER_DESCRIPTION_TABLE;
+
+///
+/// GTDT Version (as defined in ACPI 6.3 spec.)
+///
+#define EFI_ACPI_6_3_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION 0x03
+
+///
+/// Timer Flags. All other bits are reserved and must be 0.
+///
+#define EFI_ACPI_6_3_GTDT_TIMER_FLAG_TIMER_INTERRUPT_MODE BIT0
+#define EFI_ACPI_6_3_GTDT_TIMER_FLAG_TIMER_INTERRUPT_POLARITY BIT1
+#define EFI_ACPI_6_3_GTDT_TIMER_FLAG_ALWAYS_ON_CAPABILITY BIT2
+
+///
+/// Platform Timer Type
+///
+#define EFI_ACPI_6_3_GTDT_GT_BLOCK 0
+#define EFI_ACPI_6_3_GTDT_SBSA_GENERIC_WATCHDOG 1
+
+///
+/// GT Block Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT16 Length;
+ UINT8 Reserved;
+ UINT64 CntCtlBase;
+ UINT32 GTBlockTimerCount;
+ UINT32 GTBlockTimerOffset;
+} EFI_ACPI_6_3_GTDT_GT_BLOCK_STRUCTURE;
+
+///
+/// GT Block Timer Structure
+///
+typedef struct {
+ UINT8 GTFrameNumber;
+ UINT8 Reserved[3];
+ UINT64 CntBaseX;
+ UINT64 CntEL0BaseX;
+ UINT32 GTxPhysicalTimerGSIV;
+ UINT32 GTxPhysicalTimerFlags;
+ UINT32 GTxVirtualTimerGSIV;
+ UINT32 GTxVirtualTimerFlags;
+ UINT32 GTxCommonFlags;
+} EFI_ACPI_6_3_GTDT_GT_BLOCK_TIMER_STRUCTURE;
+
+///
+/// GT Block Physical Timers and Virtual Timers Flags. All other bits are reserved and must be 0.
+///
+#define EFI_ACPI_6_3_GTDT_GT_BLOCK_TIMER_FLAG_TIMER_INTERRUPT_MODE BIT0
+#define EFI_ACPI_6_3_GTDT_GT_BLOCK_TIMER_FLAG_TIMER_INTERRUPT_POLARITY BIT1
+
+///
+/// Common Flags Flags. All other bits are reserved and must be 0.
+///
+#define EFI_ACPI_6_3_GTDT_GT_BLOCK_COMMON_FLAG_SECURE_TIMER BIT0
+#define EFI_ACPI_6_3_GTDT_GT_BLOCK_COMMON_FLAG_ALWAYS_ON_CAPABILITY BIT1
+
+///
+/// SBSA Generic Watchdog Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT16 Length;
+ UINT8 Reserved;
+ UINT64 RefreshFramePhysicalAddress;
+ UINT64 WatchdogControlFramePhysicalAddress;
+ UINT32 WatchdogTimerGSIV;
+ UINT32 WatchdogTimerFlags;
+} EFI_ACPI_6_3_GTDT_SBSA_GENERIC_WATCHDOG_STRUCTURE;
+
+///
+/// SBSA Generic Watchdog Timer Flags. All other bits are reserved and must be 0.
+///
+#define EFI_ACPI_6_3_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_TIMER_INTERRUPT_MODE BIT0
+#define EFI_ACPI_6_3_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_TIMER_INTERRUPT_POLARITY BIT1
+#define EFI_ACPI_6_3_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_SECURE_TIMER BIT2
+
+//
+// NVDIMM Firmware Interface Table definition.
+//
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 Reserved;
+} EFI_ACPI_6_3_NVDIMM_FIRMWARE_INTERFACE_TABLE;
+
+//
+// NFIT Version (as defined in ACPI 6.3 spec.)
+//
+#define EFI_ACPI_6_3_NVDIMM_FIRMWARE_INTERFACE_TABLE_REVISION 0x1
+
+//
+// Definition for NFIT Table Structure Types
+//
+#define EFI_ACPI_6_3_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_STRUCTURE_TYPE 0
+#define EFI_ACPI_6_3_NFIT_NVDIMM_REGION_MAPPING_STRUCTURE_TYPE 1
+#define EFI_ACPI_6_3_NFIT_INTERLEAVE_STRUCTURE_TYPE 2
+#define EFI_ACPI_6_3_NFIT_SMBIOS_MANAGEMENT_INFORMATION_STRUCTURE_TYPE 3
+#define EFI_ACPI_6_3_NFIT_NVDIMM_CONTROL_REGION_STRUCTURE_TYPE 4
+#define EFI_ACPI_6_3_NFIT_NVDIMM_BLOCK_DATA_WINDOW_REGION_STRUCTURE_TYPE 5
+#define EFI_ACPI_6_3_NFIT_FLUSH_HINT_ADDRESS_STRUCTURE_TYPE 6
+#define EFI_ACPI_6_3_NFIT_PLATFORM_CAPABILITIES_STRUCTURE_TYPE 7
+
+//
+// Definition for NFIT Structure Header
+//
+typedef struct {
+ UINT16 Type;
+ UINT16 Length;
+} EFI_ACPI_6_3_NFIT_STRUCTURE_HEADER;
+
+//
+// Definition for System Physical Address Range Structure
+//
+#define EFI_ACPI_6_3_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_FLAGS_CONTROL_REGION_FOR_MANAGEMENT BIT0
+#define EFI_ACPI_6_3_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_FLAGS_PROXIMITY_DOMAIN_VALID BIT1
+#define EFI_ACPI_6_3_NFIT_GUID_VOLATILE_MEMORY_REGION { 0x7305944F, 0xFDDA, 0x44E3, { 0xB1, 0x6C, 0x3F, 0x22, 0xD2, 0x52, 0xE5, 0xD0 }}
+#define EFI_ACPI_6_3_NFIT_GUID_BYTE_ADDRESSABLE_PERSISTENT_MEMORY_REGION { 0x66F0D379, 0xB4F3, 0x4074, { 0xAC, 0x43, 0x0D, 0x33, 0x18, 0xB7, 0x8C, 0xDB }}
+#define EFI_ACPI_6_3_NFIT_GUID_NVDIMM_CONTROL_REGION { 0x92F701F6, 0x13B4, 0x405D, { 0x91, 0x0B, 0x29, 0x93, 0x67, 0xE8, 0x23, 0x4C }}
+#define EFI_ACPI_6_3_NFIT_GUID_NVDIMM_BLOCK_DATA_WINDOW_REGION { 0x91AF0530, 0x5D86, 0x470E, { 0xA6, 0xB0, 0x0A, 0x2D, 0xB9, 0x40, 0x82, 0x49 }}
+#define EFI_ACPI_6_3_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_DISK_REGION_VOLATILE { 0x77AB535A, 0x45FC, 0x624B, { 0x55, 0x60, 0xF7, 0xB2, 0x81, 0xD1, 0xF9, 0x6E }}
+#define EFI_ACPI_6_3_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_CD_REGION_VOLATILE { 0x3D5ABD30, 0x4175, 0x87CE, { 0x6D, 0x64, 0xD2, 0xAD, 0xE5, 0x23, 0xC4, 0xBB }}
+#define EFI_ACPI_6_3_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_DISK_REGION_PERSISTENT { 0x5CEA02C9, 0x4D07, 0x69D3, { 0x26, 0x9F ,0x44, 0x96, 0xFB, 0xE0, 0x96, 0xF9 }}
+#define EFI_ACPI_6_3_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_CD_REGION_PERSISTENT { 0x08018188, 0x42CD, 0xBB48, { 0x10, 0x0F, 0x53, 0x87, 0xD5, 0x3D, 0xED, 0x3D }}
+typedef struct {
+ UINT16 Type;
+ UINT16 Length;
+ UINT16 SPARangeStructureIndex;
+ UINT16 Flags;
+ UINT32 Reserved_8;
+ UINT32 ProximityDomain;
+ GUID AddressRangeTypeGUID;
+ UINT64 SystemPhysicalAddressRangeBase;
+ UINT64 SystemPhysicalAddressRangeLength;
+ UINT64 AddressRangeMemoryMappingAttribute;
+} EFI_ACPI_6_3_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_STRUCTURE;
+
+//
+// Definition for Memory Device to System Physical Address Range Mapping Structure
+//
+typedef struct {
+ UINT32 DIMMNumber : 4;
+ UINT32 MemoryChannelNumber : 4;
+ UINT32 MemoryControllerID : 4;
+ UINT32 SocketID : 4;
+ UINT32 NodeControllerID : 12;
+ UINT32 Reserved_28 : 4;
+} EFI_ACPI_6_3_NFIT_DEVICE_HANDLE;
+
+#define EFI_ACPI_6_3_NFIT_MEMORY_DEVICE_STATE_FLAGS_PREVIOUS_SAVE_FAIL BIT0
+#define EFI_ACPI_6_3_NFIT_MEMORY_DEVICE_STATE_FLAGS_LAST_RESTORE_FAIL BIT1
+#define EFI_ACPI_6_3_NFIT_MEMORY_DEVICE_STATE_FLAGS_PLATFORM_FLUSH_FAIL BIT2
+#define EFI_ACPI_6_3_NFIT_MEMORY_DEVICE_STATE_FLAGS_NOT_ARMED_PRIOR_TO_OSPM_HAND_OFF BIT3
+#define EFI_ACPI_6_3_NFIT_MEMORY_DEVICE_STATE_FLAGS_SMART_HEALTH_EVENTS_PRIOR_OSPM_HAND_OFF BIT4
+#define EFI_ACPI_6_3_NFIT_MEMORY_DEVICE_STATE_FLAGS_FIRMWARE_ENABLED_TO_NOTIFY_OSPM_ON_SMART_HEALTH_EVENTS BIT5
+#define EFI_ACPI_6_3_NFIT_MEMORY_DEVICE_STATE_FLAGS_FIRMWARE_NOT_MAP_NVDIMM_TO_SPA BIT6
+typedef struct {
+ UINT16 Type;
+ UINT16 Length;
+ EFI_ACPI_6_3_NFIT_DEVICE_HANDLE NFITDeviceHandle;
+ UINT16 NVDIMMPhysicalID;
+ UINT16 NVDIMMRegionID;
+ UINT16 SPARangeStructureIndex;
+ UINT16 NVDIMMControlRegionStructureIndex;
+ UINT64 NVDIMMRegionSize;
+ UINT64 RegionOffset;
+ UINT64 NVDIMMPhysicalAddressRegionBase;
+ UINT16 InterleaveStructureIndex;
+ UINT16 InterleaveWays;
+ UINT16 NVDIMMStateFlags;
+ UINT16 Reserved_46;
+} EFI_ACPI_6_3_NFIT_NVDIMM_REGION_MAPPING_STRUCTURE;
+
+//
+// Definition for Interleave Structure
+//
+typedef struct {
+ UINT16 Type;
+ UINT16 Length;
+ UINT16 InterleaveStructureIndex;
+ UINT16 Reserved_6;
+ UINT32 NumberOfLines;
+ UINT32 LineSize;
+ // UINT32 LineOffset[NumberOfLines];
+} EFI_ACPI_6_3_NFIT_INTERLEAVE_STRUCTURE;
+
+//
+// Definition for SMBIOS Management Information Structure
+//
+typedef struct {
+ UINT16 Type;
+ UINT16 Length;
+ UINT32 Reserved_4;
+ // UINT8 Data[];
+} EFI_ACPI_6_3_NFIT_SMBIOS_MANAGEMENT_INFORMATION_STRUCTURE;
+
+//
+// Definition for NVDIMM Control Region Structure
+//
+#define EFI_ACPI_6_3_NFIT_NVDIMM_CONTROL_REGION_VALID_FIELDS_MANUFACTURING BIT0
+
+#define EFI_ACPI_6_3_NFIT_NVDIMM_CONTROL_REGION_FLAGS_BLOCK_DATA_WINDOWS_BUFFERED BIT0
+typedef struct {
+ UINT16 Type;
+ UINT16 Length;
+ UINT16 NVDIMMControlRegionStructureIndex;
+ UINT16 VendorID;
+ UINT16 DeviceID;
+ UINT16 RevisionID;
+ UINT16 SubsystemVendorID;
+ UINT16 SubsystemDeviceID;
+ UINT16 SubsystemRevisionID;
+ UINT8 ValidFields;
+ UINT8 ManufacturingLocation;
+ UINT16 ManufacturingDate;
+ UINT8 Reserved_22[2];
+ UINT32 SerialNumber;
+ UINT16 RegionFormatInterfaceCode;
+ UINT16 NumberOfBlockControlWindows;
+ UINT64 SizeOfBlockControlWindow;
+ UINT64 CommandRegisterOffsetInBlockControlWindow;
+ UINT64 SizeOfCommandRegisterInBlockControlWindows;
+ UINT64 StatusRegisterOffsetInBlockControlWindow;
+ UINT64 SizeOfStatusRegisterInBlockControlWindows;
+ UINT16 NVDIMMControlRegionFlag;
+ UINT8 Reserved_74[6];
+} EFI_ACPI_6_3_NFIT_NVDIMM_CONTROL_REGION_STRUCTURE;
+
+//
+// Definition for NVDIMM Block Data Window Region Structure
+//
+typedef struct {
+ UINT16 Type;
+ UINT16 Length;
+ UINT16 NVDIMMControlRegionStructureIndex;
+ UINT16 NumberOfBlockDataWindows;
+ UINT64 BlockDataWindowStartOffset;
+ UINT64 SizeOfBlockDataWindow;
+ UINT64 BlockAccessibleMemoryCapacity;
+ UINT64 BeginningAddressOfFirstBlockInBlockAccessibleMemory;
+} EFI_ACPI_6_3_NFIT_NVDIMM_BLOCK_DATA_WINDOW_REGION_STRUCTURE;
+
+//
+// Definition for Flush Hint Address Structure
+//
+typedef struct {
+ UINT16 Type;
+ UINT16 Length;
+ EFI_ACPI_6_3_NFIT_DEVICE_HANDLE NFITDeviceHandle;
+ UINT16 NumberOfFlushHintAddresses;
+ UINT8 Reserved_10[6];
+ // UINT64 FlushHintAddress[NumberOfFlushHintAddresses];
+} EFI_ACPI_6_3_NFIT_FLUSH_HINT_ADDRESS_STRUCTURE;
+
+//
+// Definition for Platform Capabilities Structure
+//
+typedef struct {
+ UINT16 Type;
+ UINT16 Length;
+ UINT8 HighestValidCapability;
+ UINT8 Reserved_5[3];
+ UINT32 Capabilities;
+ UINT8 Reserved_12[4];
+} EFI_ACPI_6_3_NFIT_PLATFORM_CAPABILITIES_STRUCTURE;
+
+#define EFI_ACPI_6_3_NFIT_PLATFORM_CAPABILITY_CPU_CACHE_FLUSH_TO_NVDIMM_DURABILITY_ON_POWER_LOSS BIT0
+#define EFI_ACPI_6_3_NFIT_PLATFORM_CAPABILITY_MEMORY_CONTROLLER_FLUSH_TO_NVDIMM_DURABILITY_ON_POWER_LOSS BIT1
+#define EFI_ACPI_6_3_NFIT_PLATFORM_CAPABILITY_BYTE_ADDRESSABLE_PERSISTENT_MEMORY_HARDWARE_MIRRORING BIT2
+
+///
+/// Secure DEVices Table (SDEV)
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+} EFI_ACPI_6_3_SECURE_DEVICES_TABLE_HEADER;
+
+///
+/// SDEV Revision (as defined in ACPI 6.3 spec.)
+///
+#define EFI_ACPI_6_3_SECURE_DEVICES_TABLE_REVISION 0x01
+
+///
+/// Secure Devcice types
+///
+#define EFI_ACPI_6_3_SDEV_TYPE_PCIE_ENDPOINT_DEVICE 0x01
+#define EFI_ACPI_6_3_SDEV_TYPE_ACPI_NAMESPACE_DEVICE 0x00
+
+///
+/// Secure Devcice flags
+///
+#define EFI_ACPI_6_3_SDEV_FLAG_ALLOW_HANDOFF BIT0
+
+///
+/// SDEV Structure Header
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Flags;
+ UINT16 Length;
+} EFI_ACPI_6_3_SDEV_STRUCTURE_HEADER;
+
+///
+/// PCIe Endpoint Device based Secure Device Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Flags;
+ UINT16 Length;
+ UINT16 PciSegmentNumber;
+ UINT16 StartBusNumber;
+ UINT16 PciPathOffset;
+ UINT16 PciPathLength;
+ UINT16 VendorSpecificDataOffset;
+ UINT16 VendorSpecificDataLength;
+} EFI_ACPI_6_3_SDEV_STRUCTURE_PCIE_ENDPOINT_DEVICE;
+
+///
+/// ACPI_NAMESPACE_DEVICE based Secure Device Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Flags;
+ UINT16 Length;
+ UINT16 DeviceIdentifierOffset;
+ UINT16 DeviceIdentifierLength;
+ UINT16 VendorSpecificDataOffset;
+ UINT16 VendorSpecificDataLength;
+} EFI_ACPI_6_3_SDEV_STRUCTURE_ACPI_NAMESPACE_DEVICE;
+
+///
+/// Boot Error Record Table (BERT)
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 BootErrorRegionLength;
+ UINT64 BootErrorRegion;
+} EFI_ACPI_6_3_BOOT_ERROR_RECORD_TABLE_HEADER;
+
+///
+/// BERT Version (as defined in ACPI 6.3 spec.)
+///
+#define EFI_ACPI_6_3_BOOT_ERROR_RECORD_TABLE_REVISION 0x01
+
+///
+/// Boot Error Region Block Status Definition
+///
+typedef struct {
+ UINT32 UncorrectableErrorValid : 1;
+ UINT32 CorrectableErrorValid : 1;
+ UINT32 MultipleUncorrectableErrors : 1;
+ UINT32 MultipleCorrectableErrors : 1;
+ UINT32 ErrorDataEntryCount : 10;
+ UINT32 Reserved : 18;
+} EFI_ACPI_6_3_ERROR_BLOCK_STATUS;
+
+///
+/// Boot Error Region Definition
+///
+typedef struct {
+ EFI_ACPI_6_3_ERROR_BLOCK_STATUS BlockStatus;
+ UINT32 RawDataOffset;
+ UINT32 RawDataLength;
+ UINT32 DataLength;
+ UINT32 ErrorSeverity;
+} EFI_ACPI_6_3_BOOT_ERROR_REGION_STRUCTURE;
+
+//
+// Boot Error Severity types
+//
+#define EFI_ACPI_6_3_ERROR_SEVERITY_RECOVERABLE 0x00
+#define EFI_ACPI_6_3_ERROR_SEVERITY_FATAL 0x01
+#define EFI_ACPI_6_3_ERROR_SEVERITY_CORRECTED 0x02
+#define EFI_ACPI_6_3_ERROR_SEVERITY_NONE 0x03
+//
+// The term 'Correctable' is no longer being used as an error severity of the
+// reported error since ACPI Specification Version 5.1 Errata B.
+// The below macro is considered as deprecated and should no longer be used.
+//
+#define EFI_ACPI_6_3_ERROR_SEVERITY_CORRECTABLE 0x00
+
+///
+/// Generic Error Data Entry Definition
+///
+typedef struct {
+ UINT8 SectionType[16];
+ UINT32 ErrorSeverity;
+ UINT16 Revision;
+ UINT8 ValidationBits;
+ UINT8 Flags;
+ UINT32 ErrorDataLength;
+ UINT8 FruId[16];
+ UINT8 FruText[20];
+ UINT8 Timestamp[8];
+} EFI_ACPI_6_3_GENERIC_ERROR_DATA_ENTRY_STRUCTURE;
+
+///
+/// Generic Error Data Entry Version (as defined in ACPI 6.3 spec.)
+///
+#define EFI_ACPI_6_3_GENERIC_ERROR_DATA_ENTRY_REVISION 0x0300
+
+///
+/// HEST - Hardware Error Source Table
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 ErrorSourceCount;
+} EFI_ACPI_6_3_HARDWARE_ERROR_SOURCE_TABLE_HEADER;
+
+///
+/// HEST Version (as defined in ACPI 6.3 spec.)
+///
+#define EFI_ACPI_6_3_HARDWARE_ERROR_SOURCE_TABLE_REVISION 0x01
+
+//
+// Error Source structure types.
+//
+#define EFI_ACPI_6_3_IA32_ARCHITECTURE_MACHINE_CHECK_EXCEPTION 0x00
+#define EFI_ACPI_6_3_IA32_ARCHITECTURE_CORRECTED_MACHINE_CHECK 0x01
+#define EFI_ACPI_6_3_IA32_ARCHITECTURE_NMI_ERROR 0x02
+#define EFI_ACPI_6_3_PCI_EXPRESS_ROOT_PORT_AER 0x06
+#define EFI_ACPI_6_3_PCI_EXPRESS_DEVICE_AER 0x07
+#define EFI_ACPI_6_3_PCI_EXPRESS_BRIDGE_AER 0x08
+#define EFI_ACPI_6_3_GENERIC_HARDWARE_ERROR 0x09
+#define EFI_ACPI_6_3_GENERIC_HARDWARE_ERROR_VERSION_2 0x0A
+#define EFI_ACPI_6_3_IA32_ARCHITECTURE_DEFERRED_MACHINE_CHECK 0x0B
+
+//
+// Error Source structure flags.
+//
+#define EFI_ACPI_6_3_ERROR_SOURCE_FLAG_FIRMWARE_FIRST (1 << 0)
+#define EFI_ACPI_6_3_ERROR_SOURCE_FLAG_GLOBAL (1 << 1)
+#define EFI_ACPI_6_3_ERROR_SOURCE_FLAG_GHES_ASSIST (1 << 2)
+
+///
+/// IA-32 Architecture Machine Check Exception Structure Definition
+///
+typedef struct {
+ UINT16 Type;
+ UINT16 SourceId;
+ UINT8 Reserved0[2];
+ UINT8 Flags;
+ UINT8 Enabled;
+ UINT32 NumberOfRecordsToPreAllocate;
+ UINT32 MaxSectionsPerRecord;
+ UINT64 GlobalCapabilityInitData;
+ UINT64 GlobalControlInitData;
+ UINT8 NumberOfHardwareBanks;
+ UINT8 Reserved1[7];
+} EFI_ACPI_6_3_IA32_ARCHITECTURE_MACHINE_CHECK_EXCEPTION_STRUCTURE;
+
+///
+/// IA-32 Architecture Machine Check Bank Structure Definition
+///
+typedef struct {
+ UINT8 BankNumber;
+ UINT8 ClearStatusOnInitialization;
+ UINT8 StatusDataFormat;
+ UINT8 Reserved0;
+ UINT32 ControlRegisterMsrAddress;
+ UINT64 ControlInitData;
+ UINT32 StatusRegisterMsrAddress;
+ UINT32 AddressRegisterMsrAddress;
+ UINT32 MiscRegisterMsrAddress;
+} EFI_ACPI_6_3_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_BANK_STRUCTURE;
+
+///
+/// IA-32 Architecture Machine Check Bank Structure MCA data format
+///
+#define EFI_ACPI_6_3_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_IA32 0x00
+#define EFI_ACPI_6_3_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_INTEL64 0x01
+#define EFI_ACPI_6_3_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_AMD64 0x02
+
+//
+// Hardware Error Notification types. All other values are reserved
+//
+#define EFI_ACPI_6_3_HARDWARE_ERROR_NOTIFICATION_POLLED 0x00
+#define EFI_ACPI_6_3_HARDWARE_ERROR_NOTIFICATION_EXTERNAL_INTERRUPT 0x01
+#define EFI_ACPI_6_3_HARDWARE_ERROR_NOTIFICATION_LOCAL_INTERRUPT 0x02
+#define EFI_ACPI_6_3_HARDWARE_ERROR_NOTIFICATION_SCI 0x03
+#define EFI_ACPI_6_3_HARDWARE_ERROR_NOTIFICATION_NMI 0x04
+#define EFI_ACPI_6_3_HARDWARE_ERROR_NOTIFICATION_CMCI 0x05
+#define EFI_ACPI_6_3_HARDWARE_ERROR_NOTIFICATION_MCE 0x06
+#define EFI_ACPI_6_3_HARDWARE_ERROR_NOTIFICATION_GPIO_SIGNAL 0x07
+#define EFI_ACPI_6_3_HARDWARE_ERROR_NOTIFICATION_ARMV8_SEA 0x08
+#define EFI_ACPI_6_3_HARDWARE_ERROR_NOTIFICATION_ARMV8_SEI 0x09
+#define EFI_ACPI_6_3_HARDWARE_ERROR_NOTIFICATION_GSIV 0x0A
+#define EFI_ACPI_6_3_HARDWARE_ERROR_NOTIFICATION_SOFTWARE_DELEGATED_EXCEPTION 0x0B
+
+///
+/// Hardware Error Notification Configuration Write Enable Structure Definition
+///
+typedef struct {
+ UINT16 Type : 1;
+ UINT16 PollInterval : 1;
+ UINT16 SwitchToPollingThresholdValue : 1;
+ UINT16 SwitchToPollingThresholdWindow : 1;
+ UINT16 ErrorThresholdValue : 1;
+ UINT16 ErrorThresholdWindow : 1;
+ UINT16 Reserved : 10;
+} EFI_ACPI_6_3_HARDWARE_ERROR_NOTIFICATION_CONFIGURATION_WRITE_ENABLE_STRUCTURE;
+
+///
+/// Hardware Error Notification Structure Definition
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ EFI_ACPI_6_3_HARDWARE_ERROR_NOTIFICATION_CONFIGURATION_WRITE_ENABLE_STRUCTURE ConfigurationWriteEnable;
+ UINT32 PollInterval;
+ UINT32 Vector;
+ UINT32 SwitchToPollingThresholdValue;
+ UINT32 SwitchToPollingThresholdWindow;
+ UINT32 ErrorThresholdValue;
+ UINT32 ErrorThresholdWindow;
+} EFI_ACPI_6_3_HARDWARE_ERROR_NOTIFICATION_STRUCTURE;
+
+///
+/// IA-32 Architecture Corrected Machine Check Structure Definition
+///
+typedef struct {
+ UINT16 Type;
+ UINT16 SourceId;
+ UINT8 Reserved0[2];
+ UINT8 Flags;
+ UINT8 Enabled;
+ UINT32 NumberOfRecordsToPreAllocate;
+ UINT32 MaxSectionsPerRecord;
+ EFI_ACPI_6_3_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure;
+ UINT8 NumberOfHardwareBanks;
+ UINT8 Reserved1[3];
+} EFI_ACPI_6_3_IA32_ARCHITECTURE_CORRECTED_MACHINE_CHECK_STRUCTURE;
+
+///
+/// IA-32 Architecture NMI Error Structure Definition
+///
+typedef struct {
+ UINT16 Type;
+ UINT16 SourceId;
+ UINT8 Reserved0[2];
+ UINT32 NumberOfRecordsToPreAllocate;
+ UINT32 MaxSectionsPerRecord;
+ UINT32 MaxRawDataLength;
+} EFI_ACPI_6_3_IA32_ARCHITECTURE_NMI_ERROR_STRUCTURE;
+
+///
+/// PCI Express Root Port AER Structure Definition
+///
+typedef struct {
+ UINT16 Type;
+ UINT16 SourceId;
+ UINT8 Reserved0[2];
+ UINT8 Flags;
+ UINT8 Enabled;
+ UINT32 NumberOfRecordsToPreAllocate;
+ UINT32 MaxSectionsPerRecord;
+ UINT32 Bus;
+ UINT16 Device;
+ UINT16 Function;
+ UINT16 DeviceControl;
+ UINT8 Reserved1[2];
+ UINT32 UncorrectableErrorMask;
+ UINT32 UncorrectableErrorSeverity;
+ UINT32 CorrectableErrorMask;
+ UINT32 AdvancedErrorCapabilitiesAndControl;
+ UINT32 RootErrorCommand;
+} EFI_ACPI_6_3_PCI_EXPRESS_ROOT_PORT_AER_STRUCTURE;
+
+///
+/// PCI Express Device AER Structure Definition
+///
+typedef struct {
+ UINT16 Type;
+ UINT16 SourceId;
+ UINT8 Reserved0[2];
+ UINT8 Flags;
+ UINT8 Enabled;
+ UINT32 NumberOfRecordsToPreAllocate;
+ UINT32 MaxSectionsPerRecord;
+ UINT32 Bus;
+ UINT16 Device;
+ UINT16 Function;
+ UINT16 DeviceControl;
+ UINT8 Reserved1[2];
+ UINT32 UncorrectableErrorMask;
+ UINT32 UncorrectableErrorSeverity;
+ UINT32 CorrectableErrorMask;
+ UINT32 AdvancedErrorCapabilitiesAndControl;
+} EFI_ACPI_6_3_PCI_EXPRESS_DEVICE_AER_STRUCTURE;
+
+///
+/// PCI Express Bridge AER Structure Definition
+///
+typedef struct {
+ UINT16 Type;
+ UINT16 SourceId;
+ UINT8 Reserved0[2];
+ UINT8 Flags;
+ UINT8 Enabled;
+ UINT32 NumberOfRecordsToPreAllocate;
+ UINT32 MaxSectionsPerRecord;
+ UINT32 Bus;
+ UINT16 Device;
+ UINT16 Function;
+ UINT16 DeviceControl;
+ UINT8 Reserved1[2];
+ UINT32 UncorrectableErrorMask;
+ UINT32 UncorrectableErrorSeverity;
+ UINT32 CorrectableErrorMask;
+ UINT32 AdvancedErrorCapabilitiesAndControl;
+ UINT32 SecondaryUncorrectableErrorMask;
+ UINT32 SecondaryUncorrectableErrorSeverity;
+ UINT32 SecondaryAdvancedErrorCapabilitiesAndControl;
+} EFI_ACPI_6_3_PCI_EXPRESS_BRIDGE_AER_STRUCTURE;
+
+///
+/// Generic Hardware Error Source Structure Definition
+///
+typedef struct {
+ UINT16 Type;
+ UINT16 SourceId;
+ UINT16 RelatedSourceId;
+ UINT8 Flags;
+ UINT8 Enabled;
+ UINT32 NumberOfRecordsToPreAllocate;
+ UINT32 MaxSectionsPerRecord;
+ UINT32 MaxRawDataLength;
+ EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE ErrorStatusAddress;
+ EFI_ACPI_6_3_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure;
+ UINT32 ErrorStatusBlockLength;
+} EFI_ACPI_6_3_GENERIC_HARDWARE_ERROR_SOURCE_STRUCTURE;
+
+///
+/// Generic Hardware Error Source Version 2 Structure Definition
+///
+typedef struct {
+ UINT16 Type;
+ UINT16 SourceId;
+ UINT16 RelatedSourceId;
+ UINT8 Flags;
+ UINT8 Enabled;
+ UINT32 NumberOfRecordsToPreAllocate;
+ UINT32 MaxSectionsPerRecord;
+ UINT32 MaxRawDataLength;
+ EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE ErrorStatusAddress;
+ EFI_ACPI_6_3_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure;
+ UINT32 ErrorStatusBlockLength;
+ EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE ReadAckRegister;
+ UINT64 ReadAckPreserve;
+ UINT64 ReadAckWrite;
+} EFI_ACPI_6_3_GENERIC_HARDWARE_ERROR_SOURCE_VERSION_2_STRUCTURE;
+
+///
+/// Generic Error Status Definition
+///
+typedef struct {
+ EFI_ACPI_6_3_ERROR_BLOCK_STATUS BlockStatus;
+ UINT32 RawDataOffset;
+ UINT32 RawDataLength;
+ UINT32 DataLength;
+ UINT32 ErrorSeverity;
+} EFI_ACPI_6_3_GENERIC_ERROR_STATUS_STRUCTURE;
+
+///
+/// IA-32 Architecture Deferred Machine Check Structure Definition
+///
+typedef struct {
+ UINT16 Type;
+ UINT16 SourceId;
+ UINT8 Reserved0[2];
+ UINT8 Flags;
+ UINT8 Enabled;
+ UINT32 NumberOfRecordsToPreAllocate;
+ UINT32 MaxSectionsPerRecord;
+ EFI_ACPI_6_3_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure;
+ UINT8 NumberOfHardwareBanks;
+ UINT8 Reserved1[3];
+} EFI_ACPI_6_3_IA32_ARCHITECTURE_DEFERRED_MACHINE_CHECK_STRUCTURE;
+
+///
+/// HMAT - Heterogeneous Memory Attribute Table
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT8 Reserved[4];
+} EFI_ACPI_6_3_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_HEADER;
+
+///
+/// HMAT Revision (as defined in ACPI 6.3 spec.)
+///
+#define EFI_ACPI_6_3_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_REVISION 0x02
+
+///
+/// HMAT types
+///
+#define EFI_ACPI_6_3_HMAT_TYPE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES 0x00
+#define EFI_ACPI_6_3_HMAT_TYPE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO 0x01
+#define EFI_ACPI_6_3_HMAT_TYPE_MEMORY_SIDE_CACHE_INFO 0x02
+
+///
+/// HMAT Structure Header
+///
+typedef struct {
+ UINT16 Type;
+ UINT8 Reserved[2];
+ UINT32 Length;
+} EFI_ACPI_6_3_HMAT_STRUCTURE_HEADER;
+
+///
+/// Memory Proximity Domain Attributes Structure flags
+///
+typedef struct {
+ UINT16 InitiatorProximityDomainValid : 1;
+ UINT16 Reserved : 15;
+} EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES_FLAGS;
+
+///
+/// Memory Proximity Domain Attributes Structure
+///
+typedef struct {
+ UINT16 Type;
+ UINT8 Reserved[2];
+ UINT32 Length;
+ EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES_FLAGS Flags;
+ UINT8 Reserved1[2];
+ UINT32 InitiatorProximityDomain;
+ UINT32 MemoryProximityDomain;
+ UINT8 Reserved2[20];
+} EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES;
+
+///
+/// System Locality Latency and Bandwidth Information Structure flags
+///
+typedef struct {
+ UINT8 MemoryHierarchy : 4;
+ UINT8 Reserved : 4;
+} EFI_ACPI_6_3_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO_FLAGS;
+
+///
+/// System Locality Latency and Bandwidth Information Structure
+///
+typedef struct {
+ UINT16 Type;
+ UINT8 Reserved[2];
+ UINT32 Length;
+ EFI_ACPI_6_3_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO_FLAGS Flags;
+ UINT8 DataType;
+ UINT8 Reserved1[2];
+ UINT32 NumberOfInitiatorProximityDomains;
+ UINT32 NumberOfTargetProximityDomains;
+ UINT8 Reserved2[4];
+ UINT64 EntryBaseUnit;
+} EFI_ACPI_6_3_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO;
+
+///
+/// Memory Side Cache Information Structure cache attributes
+///
+typedef struct {
+ UINT32 TotalCacheLevels : 4;
+ UINT32 CacheLevel : 4;
+ UINT32 CacheAssociativity : 4;
+ UINT32 WritePolicy : 4;
+ UINT32 CacheLineSize : 16;
+} EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_CACHE_ATTRIBUTES;
+
+///
+/// Memory Side Cache Information Structure
+///
+typedef struct {
+ UINT16 Type;
+ UINT8 Reserved[2];
+ UINT32 Length;
+ UINT32 MemoryProximityDomain;
+ UINT8 Reserved1[4];
+ UINT64 MemorySideCacheSize;
+ EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_CACHE_ATTRIBUTES CacheAttributes;
+ UINT8 Reserved2[2];
+ UINT16 NumberOfSmbiosHandles;
+} EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO;
+
+///
+/// ERST - Error Record Serialization Table
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 SerializationHeaderSize;
+ UINT8 Reserved0[4];
+ UINT32 InstructionEntryCount;
+} EFI_ACPI_6_3_ERROR_RECORD_SERIALIZATION_TABLE_HEADER;
+
+///
+/// ERST Version (as defined in ACPI 6.3 spec.)
+///
+#define EFI_ACPI_6_3_ERROR_RECORD_SERIALIZATION_TABLE_REVISION 0x01
+
+///
+/// ERST Serialization Actions
+///
+#define EFI_ACPI_6_3_ERST_BEGIN_WRITE_OPERATION 0x00
+#define EFI_ACPI_6_3_ERST_BEGIN_READ_OPERATION 0x01
+#define EFI_ACPI_6_3_ERST_BEGIN_CLEAR_OPERATION 0x02
+#define EFI_ACPI_6_3_ERST_END_OPERATION 0x03
+#define EFI_ACPI_6_3_ERST_SET_RECORD_OFFSET 0x04
+#define EFI_ACPI_6_3_ERST_EXECUTE_OPERATION 0x05
+#define EFI_ACPI_6_3_ERST_CHECK_BUSY_STATUS 0x06
+#define EFI_ACPI_6_3_ERST_GET_COMMAND_STATUS 0x07
+#define EFI_ACPI_6_3_ERST_GET_RECORD_IDENTIFIER 0x08
+#define EFI_ACPI_6_3_ERST_SET_RECORD_IDENTIFIER 0x09
+#define EFI_ACPI_6_3_ERST_GET_RECORD_COUNT 0x0A
+#define EFI_ACPI_6_3_ERST_BEGIN_DUMMY_WRITE_OPERATION 0x0B
+#define EFI_ACPI_6_3_ERST_GET_ERROR_LOG_ADDRESS_RANGE 0x0D
+#define EFI_ACPI_6_3_ERST_GET_ERROR_LOG_ADDRESS_RANGE_LENGTH 0x0E
+#define EFI_ACPI_6_3_ERST_GET_ERROR_LOG_ADDRESS_RANGE_ATTRIBUTES 0x0F
+#define EFI_ACPI_6_3_ERST_GET_EXECUTE_OPERATION_TIMINGS 0x10
+
+///
+/// ERST Action Command Status
+///
+#define EFI_ACPI_6_3_ERST_STATUS_SUCCESS 0x00
+#define EFI_ACPI_6_3_ERST_STATUS_NOT_ENOUGH_SPACE 0x01
+#define EFI_ACPI_6_3_ERST_STATUS_HARDWARE_NOT_AVAILABLE 0x02
+#define EFI_ACPI_6_3_ERST_STATUS_FAILED 0x03
+#define EFI_ACPI_6_3_ERST_STATUS_RECORD_STORE_EMPTY 0x04
+#define EFI_ACPI_6_3_ERST_STATUS_RECORD_NOT_FOUND 0x05
+
+///
+/// ERST Serialization Instructions
+///
+#define EFI_ACPI_6_3_ERST_READ_REGISTER 0x00
+#define EFI_ACPI_6_3_ERST_READ_REGISTER_VALUE 0x01
+#define EFI_ACPI_6_3_ERST_WRITE_REGISTER 0x02
+#define EFI_ACPI_6_3_ERST_WRITE_REGISTER_VALUE 0x03
+#define EFI_ACPI_6_3_ERST_NOOP 0x04
+#define EFI_ACPI_6_3_ERST_LOAD_VAR1 0x05
+#define EFI_ACPI_6_3_ERST_LOAD_VAR2 0x06
+#define EFI_ACPI_6_3_ERST_STORE_VAR1 0x07
+#define EFI_ACPI_6_3_ERST_ADD 0x08
+#define EFI_ACPI_6_3_ERST_SUBTRACT 0x09
+#define EFI_ACPI_6_3_ERST_ADD_VALUE 0x0A
+#define EFI_ACPI_6_3_ERST_SUBTRACT_VALUE 0x0B
+#define EFI_ACPI_6_3_ERST_STALL 0x0C
+#define EFI_ACPI_6_3_ERST_STALL_WHILE_TRUE 0x0D
+#define EFI_ACPI_6_3_ERST_SKIP_NEXT_INSTRUCTION_IF_TRUE 0x0E
+#define EFI_ACPI_6_3_ERST_GOTO 0x0F
+#define EFI_ACPI_6_3_ERST_SET_SRC_ADDRESS_BASE 0x10
+#define EFI_ACPI_6_3_ERST_SET_DST_ADDRESS_BASE 0x11
+#define EFI_ACPI_6_3_ERST_MOVE_DATA 0x12
+
+///
+/// ERST Instruction Flags
+///
+#define EFI_ACPI_6_3_ERST_PRESERVE_REGISTER 0x01
+
+///
+/// ERST Serialization Instruction Entry
+///
+typedef struct {
+ UINT8 SerializationAction;
+ UINT8 Instruction;
+ UINT8 Flags;
+ UINT8 Reserved0;
+ EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE RegisterRegion;
+ UINT64 Value;
+ UINT64 Mask;
+} EFI_ACPI_6_3_ERST_SERIALIZATION_INSTRUCTION_ENTRY;
+
+///
+/// EINJ - Error Injection Table
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 InjectionHeaderSize;
+ UINT8 InjectionFlags;
+ UINT8 Reserved0[3];
+ UINT32 InjectionEntryCount;
+} EFI_ACPI_6_3_ERROR_INJECTION_TABLE_HEADER;
+
+///
+/// EINJ Version (as defined in ACPI 6.3 spec.)
+///
+#define EFI_ACPI_6_3_ERROR_INJECTION_TABLE_REVISION 0x01
+
+///
+/// EINJ Error Injection Actions
+///
+#define EFI_ACPI_6_3_EINJ_BEGIN_INJECTION_OPERATION 0x00
+#define EFI_ACPI_6_3_EINJ_GET_TRIGGER_ERROR_ACTION_TABLE 0x01
+#define EFI_ACPI_6_3_EINJ_SET_ERROR_TYPE 0x02
+#define EFI_ACPI_6_3_EINJ_GET_ERROR_TYPE 0x03
+#define EFI_ACPI_6_3_EINJ_END_OPERATION 0x04
+#define EFI_ACPI_6_3_EINJ_EXECUTE_OPERATION 0x05
+#define EFI_ACPI_6_3_EINJ_CHECK_BUSY_STATUS 0x06
+#define EFI_ACPI_6_3_EINJ_GET_COMMAND_STATUS 0x07
+#define EFI_ACPI_6_3_EINJ_TRIGGER_ERROR 0xFF
+
+///
+/// EINJ Action Command Status
+///
+#define EFI_ACPI_6_3_EINJ_STATUS_SUCCESS 0x00
+#define EFI_ACPI_6_3_EINJ_STATUS_UNKNOWN_FAILURE 0x01
+#define EFI_ACPI_6_3_EINJ_STATUS_INVALID_ACCESS 0x02
+
+///
+/// EINJ Error Type Definition
+///
+#define EFI_ACPI_6_3_EINJ_ERROR_PROCESSOR_CORRECTABLE (1 << 0)
+#define EFI_ACPI_6_3_EINJ_ERROR_PROCESSOR_UNCORRECTABLE_NONFATAL (1 << 1)
+#define EFI_ACPI_6_3_EINJ_ERROR_PROCESSOR_UNCORRECTABLE_FATAL (1 << 2)
+#define EFI_ACPI_6_3_EINJ_ERROR_MEMORY_CORRECTABLE (1 << 3)
+#define EFI_ACPI_6_3_EINJ_ERROR_MEMORY_UNCORRECTABLE_NONFATAL (1 << 4)
+#define EFI_ACPI_6_3_EINJ_ERROR_MEMORY_UNCORRECTABLE_FATAL (1 << 5)
+#define EFI_ACPI_6_3_EINJ_ERROR_PCI_EXPRESS_CORRECTABLE (1 << 6)
+#define EFI_ACPI_6_3_EINJ_ERROR_PCI_EXPRESS_UNCORRECTABLE_NONFATAL (1 << 7)
+#define EFI_ACPI_6_3_EINJ_ERROR_PCI_EXPRESS_UNCORRECTABLE_FATAL (1 << 8)
+#define EFI_ACPI_6_3_EINJ_ERROR_PLATFORM_CORRECTABLE (1 << 9)
+#define EFI_ACPI_6_3_EINJ_ERROR_PLATFORM_UNCORRECTABLE_NONFATAL (1 << 10)
+#define EFI_ACPI_6_3_EINJ_ERROR_PLATFORM_UNCORRECTABLE_FATAL (1 << 11)
+
+///
+/// EINJ Injection Instructions
+///
+#define EFI_ACPI_6_3_EINJ_READ_REGISTER 0x00
+#define EFI_ACPI_6_3_EINJ_READ_REGISTER_VALUE 0x01
+#define EFI_ACPI_6_3_EINJ_WRITE_REGISTER 0x02
+#define EFI_ACPI_6_3_EINJ_WRITE_REGISTER_VALUE 0x03
+#define EFI_ACPI_6_3_EINJ_NOOP 0x04
+
+///
+/// EINJ Instruction Flags
+///
+#define EFI_ACPI_6_3_EINJ_PRESERVE_REGISTER 0x01
+
+///
+/// EINJ Injection Instruction Entry
+///
+typedef struct {
+ UINT8 InjectionAction;
+ UINT8 Instruction;
+ UINT8 Flags;
+ UINT8 Reserved0;
+ EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE RegisterRegion;
+ UINT64 Value;
+ UINT64 Mask;
+} EFI_ACPI_6_3_EINJ_INJECTION_INSTRUCTION_ENTRY;
+
+///
+/// EINJ Trigger Action Table
+///
+typedef struct {
+ UINT32 HeaderSize;
+ UINT32 Revision;
+ UINT32 TableSize;
+ UINT32 EntryCount;
+} EFI_ACPI_6_3_EINJ_TRIGGER_ACTION_TABLE;
+
+///
+/// Platform Communications Channel Table (PCCT)
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 Flags;
+ UINT64 Reserved;
+} EFI_ACPI_6_3_PLATFORM_COMMUNICATION_CHANNEL_TABLE_HEADER;
+
+///
+/// PCCT Version (as defined in ACPI 6.3 spec.)
+///
+#define EFI_ACPI_6_3_PLATFORM_COMMUNICATION_CHANNEL_TABLE_REVISION 0x02
+
+///
+/// PCCT Global Flags
+///
+#define EFI_ACPI_6_3_PCCT_FLAGS_PLATFORM_INTERRUPT BIT0
+
+//
+// PCCT Subspace type
+//
+#define EFI_ACPI_6_3_PCCT_SUBSPACE_TYPE_GENERIC 0x00
+#define EFI_ACPI_6_3_PCCT_SUBSPACE_TYPE_1_HW_REDUCED_COMMUNICATIONS 0x01
+#define EFI_ACPI_6_3_PCCT_SUBSPACE_TYPE_2_HW_REDUCED_COMMUNICATIONS 0x02
+#define EFI_ACPI_6_3_PCCT_SUBSPACE_TYPE_3_EXTENDED_PCC 0x03
+#define EFI_ACPI_6_3_PCCT_SUBSPACE_TYPE_4_EXTENDED_PCC 0x04
+
+///
+/// PCC Subspace Structure Header
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+} EFI_ACPI_6_3_PCCT_SUBSPACE_HEADER;
+
+///
+/// Generic Communications Subspace Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 Reserved[6];
+ UINT64 BaseAddress;
+ UINT64 AddressLength;
+ EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE DoorbellRegister;
+ UINT64 DoorbellPreserve;
+ UINT64 DoorbellWrite;
+ UINT32 NominalLatency;
+ UINT32 MaximumPeriodicAccessRate;
+ UINT16 MinimumRequestTurnaroundTime;
+} EFI_ACPI_6_3_PCCT_SUBSPACE_GENERIC;
+
+///
+/// Generic Communications Channel Shared Memory Region
+///
+
+typedef struct {
+ UINT8 Command;
+ UINT8 Reserved : 7;
+ UINT8 NotifyOnCompletion : 1;
+} EFI_ACPI_6_3_PCCT_GENERIC_SHARED_MEMORY_REGION_COMMAND;
+
+typedef struct {
+ UINT8 CommandComplete : 1;
+ UINT8 PlatformInterrupt : 1;
+ UINT8 Error : 1;
+ UINT8 PlatformNotification : 1;
+ UINT8 Reserved : 4;
+ UINT8 Reserved1;
+} EFI_ACPI_6_3_PCCT_GENERIC_SHARED_MEMORY_REGION_STATUS;
+
+typedef struct {
+ UINT32 Signature;
+ EFI_ACPI_6_3_PCCT_GENERIC_SHARED_MEMORY_REGION_COMMAND Command;
+ EFI_ACPI_6_3_PCCT_GENERIC_SHARED_MEMORY_REGION_STATUS Status;
+} EFI_ACPI_6_3_PCCT_GENERIC_SHARED_MEMORY_REGION_HEADER;
+
+#define EFI_ACPI_6_3_PCCT_SUBSPACE_PLATFORM_INTERRUPT_FLAGS_POLARITY BIT0
+#define EFI_ACPI_6_3_PCCT_SUBSPACE_PLATFORM_INTERRUPT_FLAGS_MODE BIT1
+
+///
+/// Type 1 HW-Reduced Communications Subspace Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT32 PlatformInterrupt;
+ UINT8 PlatformInterruptFlags;
+ UINT8 Reserved;
+ UINT64 BaseAddress;
+ UINT64 AddressLength;
+ EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE DoorbellRegister;
+ UINT64 DoorbellPreserve;
+ UINT64 DoorbellWrite;
+ UINT32 NominalLatency;
+ UINT32 MaximumPeriodicAccessRate;
+ UINT16 MinimumRequestTurnaroundTime;
+} EFI_ACPI_6_3_PCCT_SUBSPACE_1_HW_REDUCED_COMMUNICATIONS;
+
+///
+/// Type 2 HW-Reduced Communications Subspace Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT32 PlatformInterrupt;
+ UINT8 PlatformInterruptFlags;
+ UINT8 Reserved;
+ UINT64 BaseAddress;
+ UINT64 AddressLength;
+ EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE DoorbellRegister;
+ UINT64 DoorbellPreserve;
+ UINT64 DoorbellWrite;
+ UINT32 NominalLatency;
+ UINT32 MaximumPeriodicAccessRate;
+ UINT16 MinimumRequestTurnaroundTime;
+ EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE PlatformInterruptAckRegister;
+ UINT64 PlatformInterruptAckPreserve;
+ UINT64 PlatformInterruptAckWrite;
+} EFI_ACPI_6_3_PCCT_SUBSPACE_2_HW_REDUCED_COMMUNICATIONS;
+
+///
+/// Type 3 Extended PCC Subspace Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT32 PlatformInterrupt;
+ UINT8 PlatformInterruptFlags;
+ UINT8 Reserved;
+ UINT64 BaseAddress;
+ UINT32 AddressLength;
+ EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE DoorbellRegister;
+ UINT64 DoorbellPreserve;
+ UINT64 DoorbellWrite;
+ UINT32 NominalLatency;
+ UINT32 MaximumPeriodicAccessRate;
+ UINT32 MinimumRequestTurnaroundTime;
+ EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE PlatformInterruptAckRegister;
+ UINT64 PlatformInterruptAckPreserve;
+ UINT64 PlatformInterruptAckSet;
+ UINT8 Reserved1[8];
+ EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE CommandCompleteCheckRegister;
+ UINT64 CommandCompleteCheckMask;
+ EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE CommandCompleteUpdateRegister;
+ UINT64 CommandCompleteUpdatePreserve;
+ UINT64 CommandCompleteUpdateSet;
+ EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE ErrorStatusRegister;
+ UINT64 ErrorStatusMask;
+} EFI_ACPI_6_3_PCCT_SUBSPACE_3_EXTENDED_PCC;
+
+///
+/// Type 4 Extended PCC Subspace Structure
+///
+typedef EFI_ACPI_6_3_PCCT_SUBSPACE_3_EXTENDED_PCC EFI_ACPI_6_3_PCCT_SUBSPACE_4_EXTENDED_PCC;
+
+#define EFI_ACPI_6_3_PCCT_MASTER_SLAVE_COMMUNICATIONS_CHANNEL_FLAGS_NOTIFY_ON_COMPLETION BIT0
+
+typedef struct {
+ UINT32 Signature;
+ UINT32 Flags;
+ UINT32 Length;
+ UINT32 Command;
+} EFI_ACPI_6_3_PCCT_EXTENDED_PCC_SHARED_MEMORY_REGION_HEADER;
+
+///
+/// Platform Debug Trigger Table (PDTT)
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT8 TriggerCount;
+ UINT8 Reserved[3];
+ UINT32 TriggerIdentifierArrayOffset;
+} EFI_ACPI_6_3_PLATFORM_DEBUG_TRIGGER_TABLE_HEADER;
+
+///
+/// PDTT Revision (as defined in ACPI 6.3 spec.)
+///
+#define EFI_ACPI_6_3_PLATFORM_DEBUG_TRIGGER_TABLE_REVISION 0x00
+
+///
+/// PDTT Platform Communication Channel Identifier Structure
+///
+typedef struct {
+ UINT16 SubChannelIdentifer : 8;
+ UINT16 Runtime : 1;
+ UINT16 WaitForCompletion : 1;
+ UINT16 TriggerOrder : 1;
+ UINT16 Reserved : 5;
+} EFI_ACPI_6_3_PDTT_PCC_IDENTIFIER;
+
+///
+/// PCC Commands Codes used by Platform Debug Trigger Table
+///
+#define EFI_ACPI_6_3_PDTT_PCC_COMMAND_DOORBELL_ONLY 0x00
+#define EFI_ACPI_6_3_PDTT_PCC_COMMAND_VENDOR_SPECIFIC 0x01
+
+///
+/// PPTT Platform Communication Channel
+///
+typedef EFI_ACPI_6_3_PCCT_GENERIC_SHARED_MEMORY_REGION_HEADER EFI_ACPI_6_3_PDTT_PCC;
+
+///
+/// Processor Properties Topology Table (PPTT)
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+} EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER;
+
+///
+/// PPTT Revision (as defined in ACPI 6.3 spec.)
+///
+#define EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION 0x02
+
+///
+/// PPTT types
+///
+#define EFI_ACPI_6_3_PPTT_TYPE_PROCESSOR 0x00
+#define EFI_ACPI_6_3_PPTT_TYPE_CACHE 0x01
+#define EFI_ACPI_6_3_PPTT_TYPE_ID 0x02
+
+///
+/// PPTT Structure Header
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 Reserved[2];
+} EFI_ACPI_6_3_PPTT_STRUCTURE_HEADER;
+
+///
+/// For PPTT struct processor flags
+///
+#define EFI_ACPI_6_3_PPTT_PACKAGE_NOT_PHYSICAL 0x0
+#define EFI_ACPI_6_3_PPTT_PACKAGE_PHYSICAL 0x1
+#define EFI_ACPI_6_3_PPTT_PROCESSOR_ID_INVALID 0x0
+#define EFI_ACPI_6_3_PPTT_PROCESSOR_ID_VALID 0x1
+#define EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD 0x0
+#define EFI_ACPI_6_3_PPTT_PROCESSOR_IS_THREAD 0x1
+#define EFI_ACPI_6_3_PPTT_NODE_IS_NOT_LEAF 0x0
+#define EFI_ACPI_6_3_PPTT_NODE_IS_LEAF 0x1
+#define EFI_ACPI_6_3_PPTT_IMPLEMENTATION_NOT_IDENTICAL 0x0
+#define EFI_ACPI_6_3_PPTT_IMPLEMENTATION_IDENTICAL 0x1
+
+///
+/// Processor hierarchy node structure flags
+///
+typedef struct {
+ UINT32 PhysicalPackage : 1;
+ UINT32 AcpiProcessorIdValid : 1;
+ UINT32 ProcessorIsAThread : 1;
+ UINT32 NodeIsALeaf : 1;
+ UINT32 IdenticalImplementation : 1;
+ UINT32 Reserved : 27;
+} EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_FLAGS;
+
+///
+/// Processor hierarchy node structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 Reserved[2];
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_FLAGS Flags;
+ UINT32 Parent;
+ UINT32 AcpiProcessorId;
+ UINT32 NumberOfPrivateResources;
+} EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR;
+
+///
+/// For PPTT struct cache flags
+///
+#define EFI_ACPI_6_3_PPTT_CACHE_SIZE_INVALID 0x0
+#define EFI_ACPI_6_3_PPTT_CACHE_SIZE_VALID 0x1
+#define EFI_ACPI_6_3_PPTT_NUMBER_OF_SETS_INVALID 0x0
+#define EFI_ACPI_6_3_PPTT_NUMBER_OF_SETS_VALID 0x1
+#define EFI_ACPI_6_3_PPTT_ASSOCIATIVITY_INVALID 0x0
+#define EFI_ACPI_6_3_PPTT_ASSOCIATIVITY_VALID 0x1
+#define EFI_ACPI_6_3_PPTT_ALLOCATION_TYPE_INVALID 0x0
+#define EFI_ACPI_6_3_PPTT_ALLOCATION_TYPE_VALID 0x1
+#define EFI_ACPI_6_3_PPTT_CACHE_TYPE_INVALID 0x0
+#define EFI_ACPI_6_3_PPTT_CACHE_TYPE_VALID 0x1
+#define EFI_ACPI_6_3_PPTT_WRITE_POLICY_INVALID 0x0
+#define EFI_ACPI_6_3_PPTT_WRITE_POLICY_VALID 0x1
+#define EFI_ACPI_6_3_PPTT_LINE_SIZE_INVALID 0x0
+#define EFI_ACPI_6_3_PPTT_LINE_SIZE_VALID 0x1
+
+///
+/// Cache Type Structure flags
+///
+typedef struct {
+ UINT32 SizePropertyValid : 1;
+ UINT32 NumberOfSetsValid : 1;
+ UINT32 AssociativityValid : 1;
+ UINT32 AllocationTypeValid : 1;
+ UINT32 CacheTypeValid : 1;
+ UINT32 WritePolicyValid : 1;
+ UINT32 LineSizeValid : 1;
+ UINT32 Reserved : 25;
+} EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_FLAGS;
+
+///
+/// For cache attributes
+///
+#define EFI_ACPI_6_3_CACHE_ATTRIBUTES_ALLOCATION_READ 0x0
+#define EFI_ACPI_6_3_CACHE_ATTRIBUTES_ALLOCATION_WRITE 0x1
+#define EFI_ACPI_6_3_CACHE_ATTRIBUTES_ALLOCATION_READ_WRITE 0x2
+#define EFI_ACPI_6_3_CACHE_ATTRIBUTES_CACHE_TYPE_DATA 0x0
+#define EFI_ACPI_6_3_CACHE_ATTRIBUTES_CACHE_TYPE_INSTRUCTION 0x1
+#define EFI_ACPI_6_3_CACHE_ATTRIBUTES_CACHE_TYPE_UNIFIED 0x2
+#define EFI_ACPI_6_3_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK 0x0
+#define EFI_ACPI_6_3_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_THROUGH 0x1
+
+///
+/// Cache Type Structure cache attributes
+///
+typedef struct {
+ UINT8 AllocationType : 2;
+ UINT8 CacheType : 2;
+ UINT8 WritePolicy : 1;
+ UINT8 Reserved : 3;
+} EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_ATTRIBUTES;
+
+///
+/// Cache Type Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 Reserved[2];
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_FLAGS Flags;
+ UINT32 NextLevelOfCache;
+ UINT32 Size;
+ UINT32 NumberOfSets;
+ UINT8 Associativity;
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_ATTRIBUTES Attributes;
+ UINT16 LineSize;
+} EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE;
+
+///
+/// ID structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 Reserved[2];
+ UINT32 VendorId;
+ UINT64 Level1Id;
+ UINT64 Level2Id;
+ UINT16 MajorRev;
+ UINT16 MinorRev;
+ UINT16 SpinRev;
+} EFI_ACPI_6_3_PPTT_STRUCTURE_ID;
+
+//
+// Known table signatures
+//
+
+///
+/// "RSD PTR " Root System Description Pointer
+///
+#define EFI_ACPI_6_3_ROOT_SYSTEM_DESCRIPTION_POINTER_SIGNATURE SIGNATURE_64('R', 'S', 'D', ' ', 'P', 'T', 'R', ' ')
+
+///
+/// "APIC" Multiple APIC Description Table
+///
+#define EFI_ACPI_6_3_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('A', 'P', 'I', 'C')
+
+///
+/// "BERT" Boot Error Record Table
+///
+#define EFI_ACPI_6_3_BOOT_ERROR_RECORD_TABLE_SIGNATURE SIGNATURE_32('B', 'E', 'R', 'T')
+
+///
+/// "BGRT" Boot Graphics Resource Table
+///
+#define EFI_ACPI_6_3_BOOT_GRAPHICS_RESOURCE_TABLE_SIGNATURE SIGNATURE_32('B', 'G', 'R', 'T')
+
+///
+/// "CDIT" Component Distance Information Table
+///
+#define EFI_ACPI_6_3_COMPONENT_DISTANCE_INFORMATION_TABLE_SIGNATURE SIGNATURE_32('C', 'D', 'I', 'T')
+
+///
+/// "CPEP" Corrected Platform Error Polling Table
+///
+#define EFI_ACPI_6_3_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_SIGNATURE SIGNATURE_32('C', 'P', 'E', 'P')
+
+///
+/// "CRAT" Component Resource Attribute Table
+///
+#define EFI_ACPI_6_3_COMPONENT_RESOURCE_ATTRIBUTE_TABLE_SIGNATURE SIGNATURE_32('C', 'R', 'A', 'T')
+
+///
+/// "DSDT" Differentiated System Description Table
+///
+#define EFI_ACPI_6_3_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('D', 'S', 'D', 'T')
+
+///
+/// "ECDT" Embedded Controller Boot Resources Table
+///
+#define EFI_ACPI_6_3_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE_SIGNATURE SIGNATURE_32('E', 'C', 'D', 'T')
+
+///
+/// "EINJ" Error Injection Table
+///
+#define EFI_ACPI_6_3_ERROR_INJECTION_TABLE_SIGNATURE SIGNATURE_32('E', 'I', 'N', 'J')
+
+///
+/// "ERST" Error Record Serialization Table
+///
+#define EFI_ACPI_6_3_ERROR_RECORD_SERIALIZATION_TABLE_SIGNATURE SIGNATURE_32('E', 'R', 'S', 'T')
+
+///
+/// "FACP" Fixed ACPI Description Table
+///
+#define EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('F', 'A', 'C', 'P')
+
+///
+/// "FACS" Firmware ACPI Control Structure
+///
+#define EFI_ACPI_6_3_FIRMWARE_ACPI_CONTROL_STRUCTURE_SIGNATURE SIGNATURE_32('F', 'A', 'C', 'S')
+
+///
+/// "FPDT" Firmware Performance Data Table
+///
+#define EFI_ACPI_6_3_FIRMWARE_PERFORMANCE_DATA_TABLE_SIGNATURE SIGNATURE_32('F', 'P', 'D', 'T')
+
+///
+/// "GTDT" Generic Timer Description Table
+///
+#define EFI_ACPI_6_3_GENERIC_TIMER_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('G', 'T', 'D', 'T')
+
+///
+/// "HEST" Hardware Error Source Table
+///
+#define EFI_ACPI_6_3_HARDWARE_ERROR_SOURCE_TABLE_SIGNATURE SIGNATURE_32('H', 'E', 'S', 'T')
+
+///
+/// "HMAT" Heterogeneous Memory Attribute Table
+///
+#define EFI_ACPI_6_3_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_SIGNATURE SIGNATURE_32('H', 'M', 'A', 'T')
+
+///
+/// "MPST" Memory Power State Table
+///
+#define EFI_ACPI_6_3_MEMORY_POWER_STATE_TABLE_SIGNATURE SIGNATURE_32('M', 'P', 'S', 'T')
+
+///
+/// "MSCT" Maximum System Characteristics Table
+///
+#define EFI_ACPI_6_3_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_SIGNATURE SIGNATURE_32('M', 'S', 'C', 'T')
+
+///
+/// "NFIT" NVDIMM Firmware Interface Table
+///
+#define EFI_ACPI_6_3_NVDIMM_FIRMWARE_INTERFACE_TABLE_STRUCTURE_SIGNATURE SIGNATURE_32('N', 'F', 'I', 'T')
+
+///
+/// "PDTT" Platform Debug Trigger Table
+///
+#define EFI_ACPI_6_3_PLATFORM_DEBUG_TRIGGER_TABLE_STRUCTURE_SIGNATURE SIGNATURE_32('P', 'D', 'T', 'T')
+
+///
+/// "PMTT" Platform Memory Topology Table
+///
+#define EFI_ACPI_6_3_PLATFORM_MEMORY_TOPOLOGY_TABLE_SIGNATURE SIGNATURE_32('P', 'M', 'T', 'T')
+
+///
+/// "PPTT" Processor Properties Topology Table
+///
+#define EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE SIGNATURE_32('P', 'P', 'T', 'T')
+
+///
+/// "PSDT" Persistent System Description Table
+///
+#define EFI_ACPI_6_3_PERSISTENT_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('P', 'S', 'D', 'T')
+
+///
+/// "RASF" ACPI RAS Feature Table
+///
+#define EFI_ACPI_6_3_ACPI_RAS_FEATURE_TABLE_SIGNATURE SIGNATURE_32('R', 'A', 'S', 'F')
+
+///
+/// "RSDT" Root System Description Table
+///
+#define EFI_ACPI_6_3_ROOT_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('R', 'S', 'D', 'T')
+
+///
+/// "SBST" Smart Battery Specification Table
+///
+#define EFI_ACPI_6_3_SMART_BATTERY_SPECIFICATION_TABLE_SIGNATURE SIGNATURE_32('S', 'B', 'S', 'T')
+
+///
+/// "SDEV" Secure DEVices Table
+///
+#define EFI_ACPI_6_3_SECURE_DEVICES_TABLE_SIGNATURE SIGNATURE_32('S', 'D', 'E', 'V')
+
+///
+/// "SLIT" System Locality Information Table
+///
+#define EFI_ACPI_6_3_SYSTEM_LOCALITY_INFORMATION_TABLE_SIGNATURE SIGNATURE_32('S', 'L', 'I', 'T')
+
+///
+/// "SRAT" System Resource Affinity Table
+///
+#define EFI_ACPI_6_3_SYSTEM_RESOURCE_AFFINITY_TABLE_SIGNATURE SIGNATURE_32('S', 'R', 'A', 'T')
+
+///
+/// "SSDT" Secondary System Description Table
+///
+#define EFI_ACPI_6_3_SECONDARY_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('S', 'S', 'D', 'T')
+
+///
+/// "XSDT" Extended System Description Table
+///
+#define EFI_ACPI_6_3_EXTENDED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('X', 'S', 'D', 'T')
+
+///
+/// "BOOT" MS Simple Boot Spec
+///
+#define EFI_ACPI_6_3_SIMPLE_BOOT_FLAG_TABLE_SIGNATURE SIGNATURE_32('B', 'O', 'O', 'T')
+
+///
+/// "CSRT" MS Core System Resource Table
+///
+#define EFI_ACPI_6_3_CORE_SYSTEM_RESOURCE_TABLE_SIGNATURE SIGNATURE_32('C', 'S', 'R', 'T')
+
+///
+/// "DBG2" MS Debug Port 2 Spec
+///
+#define EFI_ACPI_6_3_DEBUG_PORT_2_TABLE_SIGNATURE SIGNATURE_32('D', 'B', 'G', '2')
+
+///
+/// "DBGP" MS Debug Port Spec
+///
+#define EFI_ACPI_6_3_DEBUG_PORT_TABLE_SIGNATURE SIGNATURE_32('D', 'B', 'G', 'P')
+
+///
+/// "DMAR" DMA Remapping Table
+///
+#define EFI_ACPI_6_3_DMA_REMAPPING_TABLE_SIGNATURE SIGNATURE_32('D', 'M', 'A', 'R')
+
+///
+/// "DPPT" DMA Protection Policy Table
+///
+#define EFI_ACPI_6_3_DMA_PROTECTION_POLICY_TABLE_SIGNATURE SIGNATURE_32('D', 'P', 'P', 'T')
+
+///
+/// "DRTM" Dynamic Root of Trust for Measurement Table
+///
+#define EFI_ACPI_6_3_DYNAMIC_ROOT_OF_TRUST_FOR_MEASUREMENT_TABLE_SIGNATURE SIGNATURE_32('D', 'R', 'T', 'M')
+
+///
+/// "ETDT" Event Timer Description Table
+///
+#define EFI_ACPI_6_3_EVENT_TIMER_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('E', 'T', 'D', 'T')
+
+///
+/// "HPET" IA-PC High Precision Event Timer Table
+///
+#define EFI_ACPI_6_3_HIGH_PRECISION_EVENT_TIMER_TABLE_SIGNATURE SIGNATURE_32('H', 'P', 'E', 'T')
+
+///
+/// "iBFT" iSCSI Boot Firmware Table
+///
+#define EFI_ACPI_6_3_ISCSI_BOOT_FIRMWARE_TABLE_SIGNATURE SIGNATURE_32('i', 'B', 'F', 'T')
+
+///
+/// "IORT" I/O Remapping Table
+///
+#define EFI_ACPI_6_3_IO_REMAPPING_TABLE_SIGNATURE SIGNATURE_32('I', 'O', 'R', 'T')
+
+///
+/// "IVRS" I/O Virtualization Reporting Structure
+///
+#define EFI_ACPI_6_3_IO_VIRTUALIZATION_REPORTING_STRUCTURE_SIGNATURE SIGNATURE_32('I', 'V', 'R', 'S')
+
+///
+/// "LPIT" Low Power Idle Table
+///
+#define EFI_ACPI_6_3_LOW_POWER_IDLE_TABLE_STRUCTURE_SIGNATURE SIGNATURE_32('L', 'P', 'I', 'T')
+
+///
+/// "MCFG" PCI Express Memory Mapped Configuration Space Base Address Description Table
+///
+#define EFI_ACPI_6_3_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('M', 'C', 'F', 'G')
+
+///
+/// "MCHI" Management Controller Host Interface Table
+///
+#define EFI_ACPI_6_3_MANAGEMENT_CONTROLLER_HOST_INTERFACE_TABLE_SIGNATURE SIGNATURE_32('M', 'C', 'H', 'I')
+
+///
+/// "MSDM" MS Data Management Table
+///
+#define EFI_ACPI_6_3_DATA_MANAGEMENT_TABLE_SIGNATURE SIGNATURE_32('M', 'S', 'D', 'M')
+
+///
+/// "PCCT" Platform Communications Channel Table
+///
+#define EFI_ACPI_6_3_PLATFORM_COMMUNICATIONS_CHANNEL_TABLE_SIGNATURE SIGNATURE_32('P', 'C', 'C', 'T')
+
+///
+/// "SDEI" Software Delegated Exceptions Interface Table
+///
+#define EFI_ACPI_6_3_SOFTWARE_DELEGATED_EXCEPTIONS_INTERFACE_TABLE_SIGNATURE SIGNATURE_32('S', 'D', 'E', 'I')
+
+///
+/// "SLIC" MS Software Licensing Table Specification
+///
+#define EFI_ACPI_6_3_SOFTWARE_LICENSING_TABLE_SIGNATURE SIGNATURE_32('S', 'L', 'I', 'C')
+
+///
+/// "SPCR" Serial Port Concole Redirection Table
+///
+#define EFI_ACPI_6_3_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE SIGNATURE_32('S', 'P', 'C', 'R')
+
+///
+/// "SPMI" Server Platform Management Interface Table
+///
+#define EFI_ACPI_6_3_SERVER_PLATFORM_MANAGEMENT_INTERFACE_TABLE_SIGNATURE SIGNATURE_32('S', 'P', 'M', 'I')
+
+///
+/// "STAO" _STA Override Table
+///
+#define EFI_ACPI_6_3_STA_OVERRIDE_TABLE_SIGNATURE SIGNATURE_32('S', 'T', 'A', 'O')
+
+///
+/// "TCPA" Trusted Computing Platform Alliance Capabilities Table
+///
+#define EFI_ACPI_6_3_TRUSTED_COMPUTING_PLATFORM_ALLIANCE_CAPABILITIES_TABLE_SIGNATURE SIGNATURE_32('T', 'C', 'P', 'A')
+
+///
+/// "TPM2" Trusted Computing Platform 1 Table
+///
+#define EFI_ACPI_6_3_TRUSTED_COMPUTING_PLATFORM_2_TABLE_SIGNATURE SIGNATURE_32('T', 'P', 'M', '2')
+
+///
+/// "UEFI" UEFI ACPI Data Table
+///
+#define EFI_ACPI_6_3_UEFI_ACPI_DATA_TABLE_SIGNATURE SIGNATURE_32('U', 'E', 'F', 'I')
+
+///
+/// "WAET" Windows ACPI Emulated Devices Table
+///
+#define EFI_ACPI_6_3_WINDOWS_ACPI_EMULATED_DEVICES_TABLE_SIGNATURE SIGNATURE_32('W', 'A', 'E', 'T')
+
+///
+/// "WDAT" Watchdog Action Table
+///
+#define EFI_ACPI_6_3_WATCHDOG_ACTION_TABLE_SIGNATURE SIGNATURE_32('W', 'D', 'A', 'T')
+
+///
+/// "WDRT" Watchdog Resource Table
+///
+#define EFI_ACPI_6_3_WATCHDOG_RESOURCE_TABLE_SIGNATURE SIGNATURE_32('W', 'D', 'R', 'T')
+
+///
+/// "WPBT" MS Platform Binary Table
+///
+#define EFI_ACPI_6_3_PLATFORM_BINARY_TABLE_SIGNATURE SIGNATURE_32('W', 'P', 'B', 'T')
+
+///
+/// "WSMT" Windows SMM Security Mitigation Table
+///
+#define EFI_ACPI_6_3_WINDOWS_SMM_SECURITY_MITIGATION_TABLE_SIGNATURE SIGNATURE_32('W', 'S', 'M', 'T')
+
+///
+/// "XENV" Xen Project Table
+///
+#define EFI_ACPI_6_3_XEN_PROJECT_TABLE_SIGNATURE SIGNATURE_32('X', 'E', 'N', 'V')
+
+#pragma pack()
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/Acpi64.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/Acpi64.h
new file mode 100644
index 0000000000..16ea03e994
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/Acpi64.h
@@ -0,0 +1,3162 @@
+/** @file
+ ACPI 6.4 definitions from the ACPI Specification Revision 6.4 Jan, 2021.
+
+ Copyright (c) 2017 - 2022, Intel Corporation. All rights reserved.
+ Copyright (c) 2019 - 2021, ARM Ltd. All rights reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef ACPI_6_4_H_
+#define ACPI_6_4_H_
+
+#include
+
+//
+// Ensure proper structure formats
+//
+#pragma pack(1)
+
+///
+/// ACPI 6.4 Generic Address Space definition
+///
+typedef struct {
+ UINT8 AddressSpaceId;
+ UINT8 RegisterBitWidth;
+ UINT8 RegisterBitOffset;
+ UINT8 AccessSize;
+ UINT64 Address;
+} EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE;
+
+//
+// Generic Address Space Address IDs
+//
+#define EFI_ACPI_6_4_SYSTEM_MEMORY 0x00
+#define EFI_ACPI_6_4_SYSTEM_IO 0x01
+#define EFI_ACPI_6_4_PCI_CONFIGURATION_SPACE 0x02
+#define EFI_ACPI_6_4_EMBEDDED_CONTROLLER 0x03
+#define EFI_ACPI_6_4_SMBUS 0x04
+#define EFI_ACPI_6_4_SYSTEM_CMOS 0x05
+#define EFI_ACPI_6_4_PCI_BAR_TARGET 0x06
+#define EFI_ACPI_6_4_IPMI 0x07
+#define EFI_ACPI_6_4_GENERAL_PURPOSE_IO 0x08
+#define EFI_ACPI_6_4_GENERIC_SERIAL_BUS 0x09
+#define EFI_ACPI_6_4_PLATFORM_COMMUNICATION_CHANNEL 0x0A
+#define EFI_ACPI_6_4_FUNCTIONAL_FIXED_HARDWARE 0x7F
+
+//
+// Generic Address Space Access Sizes
+//
+#define EFI_ACPI_6_4_UNDEFINED 0
+#define EFI_ACPI_6_4_BYTE 1
+#define EFI_ACPI_6_4_WORD 2
+#define EFI_ACPI_6_4_DWORD 3
+#define EFI_ACPI_6_4_QWORD 4
+
+//
+// ACPI 6.4 table structures
+//
+
+///
+/// Root System Description Pointer Structure
+///
+typedef struct {
+ UINT64 Signature;
+ UINT8 Checksum;
+ UINT8 OemId[6];
+ UINT8 Revision;
+ UINT32 RsdtAddress;
+ UINT32 Length;
+ UINT64 XsdtAddress;
+ UINT8 ExtendedChecksum;
+ UINT8 Reserved[3];
+} EFI_ACPI_6_4_ROOT_SYSTEM_DESCRIPTION_POINTER;
+
+///
+/// RSD_PTR Revision (as defined in ACPI 6.4 spec.)
+///
+#define EFI_ACPI_6_4_ROOT_SYSTEM_DESCRIPTION_POINTER_REVISION 0x02 ///< ACPISpec (Revision 6.4) says current value is 2
+
+///
+/// Common table header, this prefaces all ACPI tables, including FACS, but
+/// excluding the RSD PTR structure
+///
+typedef struct {
+ UINT32 Signature;
+ UINT32 Length;
+} EFI_ACPI_6_4_COMMON_HEADER;
+
+//
+// Root System Description Table
+// No definition needed as it is a common description table header, the same with
+// EFI_ACPI_DESCRIPTION_HEADER, followed by a variable number of UINT32 table pointers.
+//
+
+///
+/// RSDT Revision (as defined in ACPI 6.4 spec.)
+///
+#define EFI_ACPI_6_4_ROOT_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01
+
+//
+// Extended System Description Table
+// No definition needed as it is a common description table header, the same with
+// EFI_ACPI_DESCRIPTION_HEADER, followed by a variable number of UINT64 table pointers.
+//
+
+///
+/// XSDT Revision (as defined in ACPI 6.4 spec.)
+///
+#define EFI_ACPI_6_4_EXTENDED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01
+
+///
+/// Fixed ACPI Description Table Structure (FADT)
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 FirmwareCtrl;
+ UINT32 Dsdt;
+ UINT8 Reserved0;
+ UINT8 PreferredPmProfile;
+ UINT16 SciInt;
+ UINT32 SmiCmd;
+ UINT8 AcpiEnable;
+ UINT8 AcpiDisable;
+ UINT8 S4BiosReq;
+ UINT8 PstateCnt;
+ UINT32 Pm1aEvtBlk;
+ UINT32 Pm1bEvtBlk;
+ UINT32 Pm1aCntBlk;
+ UINT32 Pm1bCntBlk;
+ UINT32 Pm2CntBlk;
+ UINT32 PmTmrBlk;
+ UINT32 Gpe0Blk;
+ UINT32 Gpe1Blk;
+ UINT8 Pm1EvtLen;
+ UINT8 Pm1CntLen;
+ UINT8 Pm2CntLen;
+ UINT8 PmTmrLen;
+ UINT8 Gpe0BlkLen;
+ UINT8 Gpe1BlkLen;
+ UINT8 Gpe1Base;
+ UINT8 CstCnt;
+ UINT16 PLvl2Lat;
+ UINT16 PLvl3Lat;
+ UINT16 FlushSize;
+ UINT16 FlushStride;
+ UINT8 DutyOffset;
+ UINT8 DutyWidth;
+ UINT8 DayAlrm;
+ UINT8 MonAlrm;
+ UINT8 Century;
+ UINT16 IaPcBootArch;
+ UINT8 Reserved1;
+ UINT32 Flags;
+ EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE ResetReg;
+ UINT8 ResetValue;
+ UINT16 ArmBootArch;
+ UINT8 MinorVersion;
+ UINT64 XFirmwareCtrl;
+ UINT64 XDsdt;
+ EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE XPm1aEvtBlk;
+ EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE XPm1bEvtBlk;
+ EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE XPm1aCntBlk;
+ EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE XPm1bCntBlk;
+ EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE XPm2CntBlk;
+ EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE XPmTmrBlk;
+ EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE XGpe0Blk;
+ EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE XGpe1Blk;
+ EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE SleepControlReg;
+ EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE SleepStatusReg;
+ UINT64 HypervisorVendorIdentity;
+} EFI_ACPI_6_4_FIXED_ACPI_DESCRIPTION_TABLE;
+
+///
+/// FADT Version (as defined in ACPI 6.4 spec.)
+///
+#define EFI_ACPI_6_4_FIXED_ACPI_DESCRIPTION_TABLE_REVISION 0x06
+#define EFI_ACPI_6_4_FIXED_ACPI_DESCRIPTION_TABLE_MINOR_REVISION 0x04
+
+//
+// Fixed ACPI Description Table Preferred Power Management Profile
+//
+#define EFI_ACPI_6_4_PM_PROFILE_UNSPECIFIED 0
+#define EFI_ACPI_6_4_PM_PROFILE_DESKTOP 1
+#define EFI_ACPI_6_4_PM_PROFILE_MOBILE 2
+#define EFI_ACPI_6_4_PM_PROFILE_WORKSTATION 3
+#define EFI_ACPI_6_4_PM_PROFILE_ENTERPRISE_SERVER 4
+#define EFI_ACPI_6_4_PM_PROFILE_SOHO_SERVER 5
+#define EFI_ACPI_6_4_PM_PROFILE_APPLIANCE_PC 6
+#define EFI_ACPI_6_4_PM_PROFILE_PERFORMANCE_SERVER 7
+#define EFI_ACPI_6_4_PM_PROFILE_TABLET 8
+
+//
+// Fixed ACPI Description Table Boot Architecture Flags
+// All other bits are reserved and must be set to 0.
+//
+#define EFI_ACPI_6_4_LEGACY_DEVICES BIT0
+#define EFI_ACPI_6_4_8042 BIT1
+#define EFI_ACPI_6_4_VGA_NOT_PRESENT BIT2
+#define EFI_ACPI_6_4_MSI_NOT_SUPPORTED BIT3
+#define EFI_ACPI_6_4_PCIE_ASPM_CONTROLS BIT4
+#define EFI_ACPI_6_4_CMOS_RTC_NOT_PRESENT BIT5
+
+//
+// Fixed ACPI Description Table Arm Boot Architecture Flags
+// All other bits are reserved and must be set to 0.
+//
+#define EFI_ACPI_6_4_ARM_PSCI_COMPLIANT BIT0
+#define EFI_ACPI_6_4_ARM_PSCI_USE_HVC BIT1
+
+//
+// Fixed ACPI Description Table Fixed Feature Flags
+// All other bits are reserved and must be set to 0.
+//
+#define EFI_ACPI_6_4_WBINVD BIT0
+#define EFI_ACPI_6_4_WBINVD_FLUSH BIT1
+#define EFI_ACPI_6_4_PROC_C1 BIT2
+#define EFI_ACPI_6_4_P_LVL2_UP BIT3
+#define EFI_ACPI_6_4_PWR_BUTTON BIT4
+#define EFI_ACPI_6_4_SLP_BUTTON BIT5
+#define EFI_ACPI_6_4_FIX_RTC BIT6
+#define EFI_ACPI_6_4_RTC_S4 BIT7
+#define EFI_ACPI_6_4_TMR_VAL_EXT BIT8
+#define EFI_ACPI_6_4_DCK_CAP BIT9
+#define EFI_ACPI_6_4_RESET_REG_SUP BIT10
+#define EFI_ACPI_6_4_SEALED_CASE BIT11
+#define EFI_ACPI_6_4_HEADLESS BIT12
+#define EFI_ACPI_6_4_CPU_SW_SLP BIT13
+#define EFI_ACPI_6_4_PCI_EXP_WAK BIT14
+#define EFI_ACPI_6_4_USE_PLATFORM_CLOCK BIT15
+#define EFI_ACPI_6_4_S4_RTC_STS_VALID BIT16
+#define EFI_ACPI_6_4_REMOTE_POWER_ON_CAPABLE BIT17
+#define EFI_ACPI_6_4_FORCE_APIC_CLUSTER_MODEL BIT18
+#define EFI_ACPI_6_4_FORCE_APIC_PHYSICAL_DESTINATION_MODE BIT19
+#define EFI_ACPI_6_4_HW_REDUCED_ACPI BIT20
+#define EFI_ACPI_6_4_LOW_POWER_S0_IDLE_CAPABLE BIT21
+
+///
+/// Firmware ACPI Control Structure
+///
+typedef struct {
+ UINT32 Signature;
+ UINT32 Length;
+ UINT32 HardwareSignature;
+ UINT32 FirmwareWakingVector;
+ UINT32 GlobalLock;
+ UINT32 Flags;
+ UINT64 XFirmwareWakingVector;
+ UINT8 Version;
+ UINT8 Reserved0[3];
+ UINT32 OspmFlags;
+ UINT8 Reserved1[24];
+} EFI_ACPI_6_4_FIRMWARE_ACPI_CONTROL_STRUCTURE;
+
+///
+/// FACS Version (as defined in ACPI 6.4 spec.)
+///
+#define EFI_ACPI_6_4_FIRMWARE_ACPI_CONTROL_STRUCTURE_VERSION 0x02
+
+///
+/// Firmware Control Structure Feature Flags
+/// All other bits are reserved and must be set to 0.
+///
+#define EFI_ACPI_6_4_S4BIOS_F BIT0
+#define EFI_ACPI_6_4_64BIT_WAKE_SUPPORTED_F BIT1
+
+///
+/// OSPM Enabled Firmware Control Structure Flags
+/// All other bits are reserved and must be set to 0.
+///
+#define EFI_ACPI_6_4_OSPM_64BIT_WAKE_F BIT0
+
+//
+// Differentiated System Description Table,
+// Secondary System Description Table
+// and Persistent System Description Table,
+// no definition needed as they are common description table header, the same with
+// EFI_ACPI_DESCRIPTION_HEADER, followed by a definition block.
+//
+#define EFI_ACPI_6_4_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x02
+#define EFI_ACPI_6_4_SECONDARY_SYSTEM_DESCRIPTION_TABLE_REVISION 0x02
+
+///
+/// Multiple APIC Description Table header definition. The rest of the table
+/// must be defined in a platform specific manner.
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 LocalApicAddress;
+ UINT32 Flags;
+} EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER;
+
+///
+/// MADT Revision (as defined in ACPI 6.4 spec.)
+///
+#define EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION 0x05
+
+///
+/// Multiple APIC Flags
+/// All other bits are reserved and must be set to 0.
+///
+#define EFI_ACPI_6_4_PCAT_COMPAT BIT0
+
+//
+// Multiple APIC Description Table APIC structure types
+// All other values between 0x10 and 0x7F are reserved and
+// will be ignored by OSPM. 0x80 ~ 0xFF are reserved for OEM.
+//
+#define EFI_ACPI_6_4_PROCESSOR_LOCAL_APIC 0x00
+#define EFI_ACPI_6_4_IO_APIC 0x01
+#define EFI_ACPI_6_4_INTERRUPT_SOURCE_OVERRIDE 0x02
+#define EFI_ACPI_6_4_NON_MASKABLE_INTERRUPT_SOURCE 0x03
+#define EFI_ACPI_6_4_LOCAL_APIC_NMI 0x04
+#define EFI_ACPI_6_4_LOCAL_APIC_ADDRESS_OVERRIDE 0x05
+#define EFI_ACPI_6_4_IO_SAPIC 0x06
+#define EFI_ACPI_6_4_LOCAL_SAPIC 0x07
+#define EFI_ACPI_6_4_PLATFORM_INTERRUPT_SOURCES 0x08
+#define EFI_ACPI_6_4_PROCESSOR_LOCAL_X2APIC 0x09
+#define EFI_ACPI_6_4_LOCAL_X2APIC_NMI 0x0A
+#define EFI_ACPI_6_4_GIC 0x0B
+#define EFI_ACPI_6_4_GICD 0x0C
+#define EFI_ACPI_6_4_GIC_MSI_FRAME 0x0D
+#define EFI_ACPI_6_4_GICR 0x0E
+#define EFI_ACPI_6_4_GIC_ITS 0x0F
+#define EFI_ACPI_6_4_MULTIPROCESSOR_WAKEUP 0x10
+
+//
+// APIC Structure Definitions
+//
+
+///
+/// Processor Local APIC Structure Definition
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 AcpiProcessorUid;
+ UINT8 ApicId;
+ UINT32 Flags;
+} EFI_ACPI_6_4_PROCESSOR_LOCAL_APIC_STRUCTURE;
+
+///
+/// Local APIC Flags. All other bits are reserved and must be 0.
+///
+#define EFI_ACPI_6_4_LOCAL_APIC_ENABLED BIT0
+#define EFI_ACPI_6_4_LOCAL_APIC_ONLINE_CAPABLE BIT1
+
+///
+/// IO APIC Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 IoApicId;
+ UINT8 Reserved;
+ UINT32 IoApicAddress;
+ UINT32 GlobalSystemInterruptBase;
+} EFI_ACPI_6_4_IO_APIC_STRUCTURE;
+
+///
+/// Interrupt Source Override Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 Bus;
+ UINT8 Source;
+ UINT32 GlobalSystemInterrupt;
+ UINT16 Flags;
+} EFI_ACPI_6_4_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE;
+
+///
+/// Platform Interrupt Sources Structure Definition
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Flags;
+ UINT8 InterruptType;
+ UINT8 ProcessorId;
+ UINT8 ProcessorEid;
+ UINT8 IoSapicVector;
+ UINT32 GlobalSystemInterrupt;
+ UINT32 PlatformInterruptSourceFlags;
+ UINT8 CpeiProcessorOverride;
+ UINT8 Reserved[31];
+} EFI_ACPI_6_4_PLATFORM_INTERRUPT_APIC_STRUCTURE;
+
+//
+// MPS INTI flags.
+// All other bits are reserved and must be set to 0.
+//
+#define EFI_ACPI_6_4_POLARITY (3 << 0)
+#define EFI_ACPI_6_4_TRIGGER_MODE (3 << 2)
+
+///
+/// Non-Maskable Interrupt Source Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Flags;
+ UINT32 GlobalSystemInterrupt;
+} EFI_ACPI_6_4_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE;
+
+///
+/// Local APIC NMI Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 AcpiProcessorUid;
+ UINT16 Flags;
+ UINT8 LocalApicLint;
+} EFI_ACPI_6_4_LOCAL_APIC_NMI_STRUCTURE;
+
+///
+/// Local APIC Address Override Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Reserved;
+ UINT64 LocalApicAddress;
+} EFI_ACPI_6_4_LOCAL_APIC_ADDRESS_OVERRIDE_STRUCTURE;
+
+///
+/// IO SAPIC Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 IoApicId;
+ UINT8 Reserved;
+ UINT32 GlobalSystemInterruptBase;
+ UINT64 IoSapicAddress;
+} EFI_ACPI_6_4_IO_SAPIC_STRUCTURE;
+
+///
+/// Local SAPIC Structure
+/// This struct followed by a null-terminated ASCII string - ACPI Processor UID String
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 AcpiProcessorId;
+ UINT8 LocalSapicId;
+ UINT8 LocalSapicEid;
+ UINT8 Reserved[3];
+ UINT32 Flags;
+ UINT32 ACPIProcessorUIDValue;
+} EFI_ACPI_6_4_PROCESSOR_LOCAL_SAPIC_STRUCTURE;
+
+///
+/// Platform Interrupt Sources Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Flags;
+ UINT8 InterruptType;
+ UINT8 ProcessorId;
+ UINT8 ProcessorEid;
+ UINT8 IoSapicVector;
+ UINT32 GlobalSystemInterrupt;
+ UINT32 PlatformInterruptSourceFlags;
+} EFI_ACPI_6_4_PLATFORM_INTERRUPT_SOURCES_STRUCTURE;
+
+///
+/// Platform Interrupt Source Flags.
+/// All other bits are reserved and must be set to 0.
+///
+#define EFI_ACPI_6_4_CPEI_PROCESSOR_OVERRIDE BIT0
+
+///
+/// Processor Local x2APIC Structure Definition
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 Reserved[2];
+ UINT32 X2ApicId;
+ UINT32 Flags;
+ UINT32 AcpiProcessorUid;
+} EFI_ACPI_6_4_PROCESSOR_LOCAL_X2APIC_STRUCTURE;
+
+///
+/// Local x2APIC NMI Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Flags;
+ UINT32 AcpiProcessorUid;
+ UINT8 LocalX2ApicLint;
+ UINT8 Reserved[3];
+} EFI_ACPI_6_4_LOCAL_X2APIC_NMI_STRUCTURE;
+
+///
+/// GIC Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Reserved;
+ UINT32 CPUInterfaceNumber;
+ UINT32 AcpiProcessorUid;
+ UINT32 Flags;
+ UINT32 ParkingProtocolVersion;
+ UINT32 PerformanceInterruptGsiv;
+ UINT64 ParkedAddress;
+ UINT64 PhysicalBaseAddress;
+ UINT64 GICV;
+ UINT64 GICH;
+ UINT32 VGICMaintenanceInterrupt;
+ UINT64 GICRBaseAddress;
+ UINT64 MPIDR;
+ UINT8 ProcessorPowerEfficiencyClass;
+ UINT8 Reserved2;
+ UINT16 SpeOverflowInterrupt;
+} EFI_ACPI_6_4_GIC_STRUCTURE;
+
+///
+/// GIC Flags. All other bits are reserved and must be 0.
+///
+#define EFI_ACPI_6_4_GIC_ENABLED BIT0
+#define EFI_ACPI_6_4_PERFORMANCE_INTERRUPT_MODEL BIT1
+#define EFI_ACPI_6_4_VGIC_MAINTENANCE_INTERRUPT_MODE_FLAGS BIT2
+
+///
+/// GIC Distributor Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Reserved1;
+ UINT32 GicId;
+ UINT64 PhysicalBaseAddress;
+ UINT32 SystemVectorBase;
+ UINT8 GicVersion;
+ UINT8 Reserved2[3];
+} EFI_ACPI_6_4_GIC_DISTRIBUTOR_STRUCTURE;
+
+///
+/// GIC Version
+///
+#define EFI_ACPI_6_4_GIC_V1 0x01
+#define EFI_ACPI_6_4_GIC_V2 0x02
+#define EFI_ACPI_6_4_GIC_V3 0x03
+#define EFI_ACPI_6_4_GIC_V4 0x04
+
+///
+/// GIC MSI Frame Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Reserved1;
+ UINT32 GicMsiFrameId;
+ UINT64 PhysicalBaseAddress;
+ UINT32 Flags;
+ UINT16 SPICount;
+ UINT16 SPIBase;
+} EFI_ACPI_6_4_GIC_MSI_FRAME_STRUCTURE;
+
+///
+/// GIC MSI Frame Flags. All other bits are reserved and must be 0.
+///
+#define EFI_ACPI_6_4_SPI_COUNT_BASE_SELECT BIT0
+
+///
+/// GICR Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Reserved;
+ UINT64 DiscoveryRangeBaseAddress;
+ UINT32 DiscoveryRangeLength;
+} EFI_ACPI_6_4_GICR_STRUCTURE;
+
+///
+/// GIC Interrupt Translation Service Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Reserved;
+ UINT32 GicItsId;
+ UINT64 PhysicalBaseAddress;
+ UINT32 Reserved2;
+} EFI_ACPI_6_4_GIC_ITS_STRUCTURE;
+
+///
+/// Multiprocessor Wakeup Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 MailBoxVersion;
+ UINT32 Reserved;
+ UINT64 MailBoxAddress;
+} EFI_ACPI_6_4_MULTIPROCESSOR_WAKEUP_STRUCTURE;
+
+///
+/// Multiprocessor Wakeup Mailbox Structure
+///
+typedef struct {
+ UINT16 Command;
+ UINT16 Reserved;
+ UINT32 AcpiId;
+ UINT64 WakeupVector;
+ UINT8 ReservedForOs[2032];
+ UINT8 ReservedForFirmware[2048];
+} EFI_ACPI_6_4_MULTIPROCESSOR_WAKEUP_MAILBOX_STRUCTURE;
+
+#define EFI_ACPI_6_4_MULTIPROCESSOR_WAKEUP_MAILBOX_COMMAND_NOOP 0x0000
+#define EFI_ACPI_6_4_MULTIPROCESSOR_WAKEUP_MAILBOX_COMMAND_WAKEUP 0x0001
+
+///
+/// Smart Battery Description Table (SBST)
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 WarningEnergyLevel;
+ UINT32 LowEnergyLevel;
+ UINT32 CriticalEnergyLevel;
+} EFI_ACPI_6_4_SMART_BATTERY_DESCRIPTION_TABLE;
+
+///
+/// SBST Version (as defined in ACPI 6.4 spec.)
+///
+#define EFI_ACPI_6_4_SMART_BATTERY_DESCRIPTION_TABLE_REVISION 0x01
+
+///
+/// Embedded Controller Boot Resources Table (ECDT)
+/// The table is followed by a null terminated ASCII string that contains
+/// a fully qualified reference to the name space object.
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE EcControl;
+ EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE EcData;
+ UINT32 Uid;
+ UINT8 GpeBit;
+} EFI_ACPI_6_4_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE;
+
+///
+/// ECDT Version (as defined in ACPI 6.4 spec.)
+///
+#define EFI_ACPI_6_4_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE_REVISION 0x01
+
+///
+/// System Resource Affinity Table (SRAT). The rest of the table
+/// must be defined in a platform specific manner.
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 Reserved1; ///< Must be set to 1
+ UINT64 Reserved2;
+} EFI_ACPI_6_4_SYSTEM_RESOURCE_AFFINITY_TABLE_HEADER;
+
+///
+/// SRAT Version (as defined in ACPI 6.4 spec.)
+///
+#define EFI_ACPI_6_4_SYSTEM_RESOURCE_AFFINITY_TABLE_REVISION 0x03
+
+//
+// SRAT structure types.
+// All other values between 0x06 an 0xFF are reserved and
+// will be ignored by OSPM.
+//
+#define EFI_ACPI_6_4_PROCESSOR_LOCAL_APIC_SAPIC_AFFINITY 0x00
+#define EFI_ACPI_6_4_MEMORY_AFFINITY 0x01
+#define EFI_ACPI_6_4_PROCESSOR_LOCAL_X2APIC_AFFINITY 0x02
+#define EFI_ACPI_6_4_GICC_AFFINITY 0x03
+#define EFI_ACPI_6_4_GIC_ITS_AFFINITY 0x04
+#define EFI_ACPI_6_4_GENERIC_INITIATOR_AFFINITY 0x05
+
+///
+/// Processor Local APIC/SAPIC Affinity Structure Definition
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 ProximityDomain7To0;
+ UINT8 ApicId;
+ UINT32 Flags;
+ UINT8 LocalSapicEid;
+ UINT8 ProximityDomain31To8[3];
+ UINT32 ClockDomain;
+} EFI_ACPI_6_4_PROCESSOR_LOCAL_APIC_SAPIC_AFFINITY_STRUCTURE;
+
+///
+/// Local APIC/SAPIC Flags. All other bits are reserved and must be 0.
+///
+#define EFI_ACPI_6_4_PROCESSOR_LOCAL_APIC_SAPIC_ENABLED (1 << 0)
+
+///
+/// Memory Affinity Structure Definition
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT32 ProximityDomain;
+ UINT16 Reserved1;
+ UINT32 AddressBaseLow;
+ UINT32 AddressBaseHigh;
+ UINT32 LengthLow;
+ UINT32 LengthHigh;
+ UINT32 Reserved2;
+ UINT32 Flags;
+ UINT64 Reserved3;
+} EFI_ACPI_6_4_MEMORY_AFFINITY_STRUCTURE;
+
+//
+// Memory Flags. All other bits are reserved and must be 0.
+//
+#define EFI_ACPI_6_4_MEMORY_ENABLED (1 << 0)
+#define EFI_ACPI_6_4_MEMORY_HOT_PLUGGABLE (1 << 1)
+#define EFI_ACPI_6_4_MEMORY_NONVOLATILE (1 << 2)
+
+///
+/// Processor Local x2APIC Affinity Structure Definition
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 Reserved1[2];
+ UINT32 ProximityDomain;
+ UINT32 X2ApicId;
+ UINT32 Flags;
+ UINT32 ClockDomain;
+ UINT8 Reserved2[4];
+} EFI_ACPI_6_4_PROCESSOR_LOCAL_X2APIC_AFFINITY_STRUCTURE;
+
+///
+/// GICC Affinity Structure Definition
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT32 ProximityDomain;
+ UINT32 AcpiProcessorUid;
+ UINT32 Flags;
+ UINT32 ClockDomain;
+} EFI_ACPI_6_4_GICC_AFFINITY_STRUCTURE;
+
+///
+/// GICC Flags. All other bits are reserved and must be 0.
+///
+#define EFI_ACPI_6_4_GICC_ENABLED (1 << 0)
+
+///
+/// GIC Interrupt Translation Service (ITS) Affinity Structure Definition
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT32 ProximityDomain;
+ UINT8 Reserved[2];
+ UINT32 ItsId;
+} EFI_ACPI_6_4_GIC_ITS_AFFINITY_STRUCTURE;
+
+//
+// Generic Initiator Affinity Structure Device Handle Types
+// All other values between 0x02 an 0xFF are reserved and
+// will be ignored by OSPM.
+//
+#define EFI_ACPI_6_4_ACPI_DEVICE_HANDLE 0x00
+#define EFI_ACPI_6_4_PCI_DEVICE_HANDLE 0x01
+
+///
+/// Device Handle - ACPI
+///
+typedef struct {
+ UINT64 AcpiHid;
+ UINT32 AcpiUid;
+ UINT8 Reserved[4];
+} EFI_ACPI_6_4_DEVICE_HANDLE_ACPI;
+
+///
+/// Device Handle - PCI
+///
+typedef struct {
+ UINT16 PciSegment;
+ UINT16 PciBdfNumber;
+ UINT8 Reserved[12];
+} EFI_ACPI_6_4_DEVICE_HANDLE_PCI;
+
+///
+/// Device Handle
+///
+typedef union {
+ EFI_ACPI_6_4_DEVICE_HANDLE_ACPI Acpi;
+ EFI_ACPI_6_4_DEVICE_HANDLE_PCI Pci;
+} EFI_ACPI_6_4_DEVICE_HANDLE;
+
+///
+/// Generic Initiator Affinity Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 Reserved1;
+ UINT8 DeviceHandleType;
+ UINT32 ProximityDomain;
+ EFI_ACPI_6_4_DEVICE_HANDLE DeviceHandle;
+ UINT32 Flags;
+ UINT8 Reserved2[4];
+} EFI_ACPI_6_4_GENERIC_INITIATOR_AFFINITY_STRUCTURE;
+
+///
+/// Generic Initiator Affinity Structure Flags. All other bits are reserved
+/// and must be 0.
+///
+#define EFI_ACPI_6_4_GENERIC_INITIATOR_AFFINITY_STRUCTURE_ENABLED BIT0
+#define EFI_ACPI_6_4_GENERIC_INITIATOR_AFFINITY_STRUCTURE_ARCHITECTURAL_TRANSACTIONS BIT1
+
+///
+/// System Locality Distance Information Table (SLIT).
+/// The rest of the table is a matrix.
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT64 NumberOfSystemLocalities;
+} EFI_ACPI_6_4_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_HEADER;
+
+///
+/// SLIT Version (as defined in ACPI 6.4 spec.)
+///
+#define EFI_ACPI_6_4_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_REVISION 0x01
+
+///
+/// Corrected Platform Error Polling Table (CPEP)
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT8 Reserved[8];
+} EFI_ACPI_6_4_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_HEADER;
+
+///
+/// CPEP Version (as defined in ACPI 6.4 spec.)
+///
+#define EFI_ACPI_6_4_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_REVISION 0x01
+
+//
+// CPEP processor structure types.
+//
+#define EFI_ACPI_6_4_CPEP_PROCESSOR_APIC_SAPIC 0x00
+
+///
+/// Corrected Platform Error Polling Processor Structure Definition
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 ProcessorId;
+ UINT8 ProcessorEid;
+ UINT32 PollingInterval;
+} EFI_ACPI_6_4_CPEP_PROCESSOR_APIC_SAPIC_STRUCTURE;
+
+///
+/// Maximum System Characteristics Table (MSCT)
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 OffsetProxDomInfo;
+ UINT32 MaximumNumberOfProximityDomains;
+ UINT32 MaximumNumberOfClockDomains;
+ UINT64 MaximumPhysicalAddress;
+} EFI_ACPI_6_4_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_HEADER;
+
+///
+/// MSCT Version (as defined in ACPI 6.4 spec.)
+///
+#define EFI_ACPI_6_4_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_REVISION 0x01
+
+///
+/// Maximum Proximity Domain Information Structure Definition
+///
+typedef struct {
+ UINT8 Revision;
+ UINT8 Length;
+ UINT32 ProximityDomainRangeLow;
+ UINT32 ProximityDomainRangeHigh;
+ UINT32 MaximumProcessorCapacity;
+ UINT64 MaximumMemoryCapacity;
+} EFI_ACPI_6_4_MAXIMUM_PROXIMITY_DOMAIN_INFORMATION_STRUCTURE;
+
+///
+/// ACPI RAS Feature Table definition.
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT8 PlatformCommunicationChannelIdentifier[12];
+} EFI_ACPI_6_4_RAS_FEATURE_TABLE;
+
+///
+/// RASF Version (as defined in ACPI 6.4 spec.)
+///
+#define EFI_ACPI_6_4_RAS_FEATURE_TABLE_REVISION 0x01
+
+///
+/// ACPI RASF Platform Communication Channel Shared Memory Region definition.
+///
+typedef struct {
+ UINT32 Signature;
+ UINT16 Command;
+ UINT16 Status;
+ UINT16 Version;
+ UINT8 RASCapabilities[16];
+ UINT8 SetRASCapabilities[16];
+ UINT16 NumberOfRASFParameterBlocks;
+ UINT32 SetRASCapabilitiesStatus;
+} EFI_ACPI_6_4_RASF_PLATFORM_COMMUNICATION_CHANNEL_SHARED_MEMORY_REGION;
+
+///
+/// ACPI RASF PCC command code
+///
+#define EFI_ACPI_6_4_RASF_PCC_COMMAND_CODE_EXECUTE_RASF_COMMAND 0x01
+
+///
+/// ACPI RASF Platform RAS Capabilities
+///
+#define EFI_ACPI_6_4_RASF_PLATFORM_RAS_CAPABILITY_HARDWARE_BASED_PATROL_SCRUB_SUPPORTED BIT0
+#define EFI_ACPI_6_4_RASF_PLATFORM_RAS_CAPABILITY_HARDWARE_BASED_PATROL_SCRUB_SUPPORTED_AND_EXPOSED_TO_SOFTWARE BIT1
+#define EFI_ACPI_6_4_RASF_PLATFORM_RAS_CAPABILITY_CPU_CACHE_FLUSH_TO_NVDIMM_DURABILITY_ON_POWER_LOSS BIT2
+#define EFI_ACPI_6_4_RASF_PLATFORM_RAS_CAPABILITY_MEMORY_CONTROLLER_FLUSH_TO_NVDIMM_DURABILITY_ON_POWER_LOSS BIT3
+#define EFI_ACPI_6_4_RASF_PLATFORM_RAS_CAPABILITY_BYTE_ADDRESSABLE_PERSISTENT_MEMORY_HARDWARE_MIRRORING BIT4
+
+///
+/// ACPI RASF Parameter Block structure for PATROL_SCRUB
+///
+typedef struct {
+ UINT16 Type;
+ UINT16 Version;
+ UINT16 Length;
+ UINT16 PatrolScrubCommand;
+ UINT64 RequestedAddressRange[2];
+ UINT64 ActualAddressRange[2];
+ UINT16 Flags;
+ UINT8 RequestedSpeed;
+} EFI_ACPI_6_4_RASF_PATROL_SCRUB_PLATFORM_BLOCK_STRUCTURE;
+
+///
+/// ACPI RASF Patrol Scrub command
+///
+#define EFI_ACPI_6_4_RASF_PATROL_SCRUB_COMMAND_GET_PATROL_PARAMETERS 0x01
+#define EFI_ACPI_6_4_RASF_PATROL_SCRUB_COMMAND_START_PATROL_SCRUBBER 0x02
+#define EFI_ACPI_6_4_RASF_PATROL_SCRUB_COMMAND_STOP_PATROL_SCRUBBER 0x03
+
+///
+/// Memory Power State Table definition.
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT8 PlatformCommunicationChannelIdentifier;
+ UINT8 Reserved[3];
+ // Memory Power Node Structure
+ // Memory Power State Characteristics
+} EFI_ACPI_6_4_MEMORY_POWER_STATUS_TABLE;
+
+///
+/// MPST Version (as defined in ACPI 6.4 spec.)
+///
+#define EFI_ACPI_6_4_MEMORY_POWER_STATE_TABLE_REVISION 0x01
+
+///
+/// MPST Platform Communication Channel Shared Memory Region definition.
+///
+typedef struct {
+ UINT32 Signature;
+ UINT16 Command;
+ UINT16 Status;
+ UINT32 MemoryPowerCommandRegister;
+ UINT32 MemoryPowerStatusRegister;
+ UINT32 PowerStateId;
+ UINT32 MemoryPowerNodeId;
+ UINT64 MemoryEnergyConsumed;
+ UINT64 ExpectedAveragePowerComsuned;
+} EFI_ACPI_6_4_MPST_PLATFORM_COMMUNICATION_CHANNEL_SHARED_MEMORY_REGION;
+
+///
+/// ACPI MPST PCC command code
+///
+#define EFI_ACPI_6_4_MPST_PCC_COMMAND_CODE_EXECUTE_MPST_COMMAND 0x03
+
+///
+/// ACPI MPST Memory Power command
+///
+#define EFI_ACPI_6_4_MPST_MEMORY_POWER_COMMAND_GET_MEMORY_POWER_STATE 0x01
+#define EFI_ACPI_6_4_MPST_MEMORY_POWER_COMMAND_SET_MEMORY_POWER_STATE 0x02
+#define EFI_ACPI_6_4_MPST_MEMORY_POWER_COMMAND_GET_AVERAGE_POWER_CONSUMED 0x03
+#define EFI_ACPI_6_4_MPST_MEMORY_POWER_COMMAND_GET_MEMORY_ENERGY_CONSUMED 0x04
+
+///
+/// MPST Memory Power Node Table
+///
+typedef struct {
+ UINT8 PowerStateValue;
+ UINT8 PowerStateInformationIndex;
+} EFI_ACPI_6_4_MPST_MEMORY_POWER_STATE;
+
+typedef struct {
+ UINT8 Flag;
+ UINT8 Reserved;
+ UINT16 MemoryPowerNodeId;
+ UINT32 Length;
+ UINT64 AddressBase;
+ UINT64 AddressLength;
+ UINT32 NumberOfPowerStates;
+ UINT32 NumberOfPhysicalComponents;
+ // EFI_ACPI_6_4_MPST_MEMORY_POWER_STATE MemoryPowerState[NumberOfPowerStates];
+ // UINT16 PhysicalComponentIdentifier[NumberOfPhysicalComponents];
+} EFI_ACPI_6_4_MPST_MEMORY_POWER_STRUCTURE;
+
+#define EFI_ACPI_6_4_MPST_MEMORY_POWER_STRUCTURE_FLAG_ENABLE 0x01
+#define EFI_ACPI_6_4_MPST_MEMORY_POWER_STRUCTURE_FLAG_POWER_MANAGED 0x02
+#define EFI_ACPI_6_4_MPST_MEMORY_POWER_STRUCTURE_FLAG_HOT_PLUGGABLE 0x04
+
+typedef struct {
+ UINT16 MemoryPowerNodeCount;
+ UINT8 Reserved[2];
+} EFI_ACPI_6_4_MPST_MEMORY_POWER_NODE_TABLE;
+
+///
+/// MPST Memory Power State Characteristics Table
+///
+typedef struct {
+ UINT8 PowerStateStructureID;
+ UINT8 Flag;
+ UINT16 Reserved;
+ UINT32 AveragePowerConsumedInMPS0;
+ UINT32 RelativePowerSavingToMPS0;
+ UINT64 ExitLatencyToMPS0;
+} EFI_ACPI_6_4_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE;
+
+#define EFI_ACPI_6_4_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_MEMORY_CONTENT_PRESERVED 0x01
+#define EFI_ACPI_6_4_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_AUTONOMOUS_MEMORY_POWER_STATE_ENTRY 0x02
+#define EFI_ACPI_6_4_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_AUTONOMOUS_MEMORY_POWER_STATE_EXIT 0x04
+
+typedef struct {
+ UINT16 MemoryPowerStateCharacteristicsCount;
+ UINT8 Reserved[2];
+} EFI_ACPI_6_4_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_TABLE;
+
+///
+/// Platform Memory Topology Table definition.
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 NumberOfMemoryDevices;
+ // EFI_ACPI_6_4_PMTT_COMMON_MEMORY_DEVICE MemoryDeviceStructure[NumberOfMemoryDevices];
+} EFI_ACPI_6_4_PLATFORM_MEMORY_TOPOLOGY_TABLE;
+
+///
+/// PMTT Version (as defined in ACPI 6.4 spec.)
+///
+#define EFI_ACPI_6_4_MEMORY_TOPOLOGY_TABLE_REVISION 0x02
+
+///
+/// Common Memory Device.
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Reserved;
+ UINT16 Length;
+ UINT16 Flags;
+ UINT16 Reserved1;
+ UINT32 NumberOfMemoryDevices;
+ // UINT8 TypeSpecificData[];
+ // EFI_ACPI_6_4_PMTT_COMMON_MEMORY_DEVICE MemoryDeviceStructure[NumberOfMemoryDevices];
+} EFI_ACPI_6_4_PMTT_COMMON_MEMORY_DEVICE;
+
+///
+/// Memory Device Type.
+///
+#define EFI_ACPI_6_4_PMTT_MEMORY_DEVICE_TYPE_SOCKET 0x0
+#define EFI_ACPI_6_4_PMTT_MEMORY_DEVICE_TYPE_MEMORY_CONTROLLER 0x1
+#define EFI_ACPI_6_4_PMTT_MEMORY_DEVICE_TYPE_DIMM 0x2
+#define EFI_ACPI_6_4_PMTT_MEMORY_DEVICE_TYPE_VENDOR_SPECIFIC_TYPE 0xFF
+
+///
+/// Socket Type Data.
+///
+typedef struct {
+ EFI_ACPI_6_4_PMTT_COMMON_MEMORY_DEVICE CommonMemoryDeviceHeader;
+ UINT16 SocketIdentifier;
+ UINT16 Reserved;
+ // EFI_ACPI_6_4_PMTT_COMMON_MEMORY_DEVICE MemoryDeviceStructure[];
+} EFI_ACPI_6_4_PMTT_SOCKET_TYPE_DATA;
+
+///
+/// Memory Controller Type Data.
+///
+typedef struct {
+ EFI_ACPI_6_4_PMTT_COMMON_MEMORY_DEVICE CommonMemoryDeviceHeader;
+ UINT16 MemoryControllerIdentifier;
+ UINT16 Reserved;
+ // EFI_ACPI_6_4_PMTT_COMMON_MEMORY_DEVICE MemoryDeviceStructure[];
+} EFI_ACPI_6_4_PMTT_MEMORY_CONTROLLER_TYPE_DATA;
+
+///
+/// DIMM Type Specific Data.
+///
+typedef struct {
+ EFI_ACPI_6_4_PMTT_COMMON_MEMORY_DEVICE CommonMemoryDeviceHeader;
+ UINT32 SmbiosHandle;
+} EFI_ACPI_6_4_PMTT_DIMM_TYPE_SPECIFIC_DATA;
+
+///
+/// Vendor Specific Type Data.
+///
+typedef struct {
+ EFI_ACPI_6_4_PMTT_COMMON_MEMORY_DEVICE CommonMemoryDeviceHeader;
+ UINT8 TypeUuid[16];
+ // EFI_ACPI_6_4_PMTT_VENDOR_SPECIFIC_TYPE_DATA VendorSpecificData[];
+ // EFI_ACPI_6_4_PMTT_COMMON_MEMORY_DEVICE MemoryDeviceStructure[];
+} EFI_ACPI_6_4_PMTT_VENDOR_SPECIFIC_TYPE_DATA;
+
+///
+/// Boot Graphics Resource Table definition.
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ ///
+ /// 2-bytes (16 bit) version ID. This value must be 1.
+ ///
+ UINT16 Version;
+ ///
+ /// 1-byte status field indicating current status about the table.
+ /// Bits[7:3] = Reserved (must be zero)
+ /// Bits[2:1] = Orientation Offset. These bits describe the clockwise
+ /// degree offset from the image's default orientation.
+ /// [00] = 0, no offset
+ /// [01] = 90
+ /// [10] = 180
+ /// [11] = 270
+ /// Bit [0] = Displayed. A one indicates the boot image graphic is
+ /// displayed.
+ ///
+ UINT8 Status;
+ ///
+ /// 1-byte enumerated type field indicating format of the image.
+ /// 0 = Bitmap
+ /// 1 - 255 Reserved (for future use)
+ ///
+ UINT8 ImageType;
+ ///
+ /// 8-byte (64 bit) physical address pointing to the firmware's in-memory copy
+ /// of the image bitmap.
+ ///
+ UINT64 ImageAddress;
+ ///
+ /// A 4-byte (32-bit) unsigned long describing the display X-offset of the boot image.
+ /// (X, Y) display offset of the top left corner of the boot image.
+ /// The top left corner of the display is at offset (0, 0).
+ ///
+ UINT32 ImageOffsetX;
+ ///
+ /// A 4-byte (32-bit) unsigned long describing the display Y-offset of the boot image.
+ /// (X, Y) display offset of the top left corner of the boot image.
+ /// The top left corner of the display is at offset (0, 0).
+ ///
+ UINT32 ImageOffsetY;
+} EFI_ACPI_6_4_BOOT_GRAPHICS_RESOURCE_TABLE;
+
+///
+/// BGRT Revision
+///
+#define EFI_ACPI_6_4_BOOT_GRAPHICS_RESOURCE_TABLE_REVISION 1
+
+///
+/// BGRT Version
+///
+#define EFI_ACPI_6_4_BGRT_VERSION 0x01
+
+///
+/// BGRT Status
+///
+#define EFI_ACPI_6_4_BGRT_STATUS_NOT_DISPLAYED 0x00
+#define EFI_ACPI_6_4_BGRT_STATUS_DISPLAYED 0x01
+
+///
+/// BGRT Image Type
+///
+#define EFI_ACPI_6_4_BGRT_IMAGE_TYPE_BMP 0x00
+
+///
+/// FPDT Version (as defined in ACPI 6.4 spec.)
+///
+#define EFI_ACPI_6_4_FIRMWARE_PERFORMANCE_DATA_TABLE_REVISION 0x01
+
+///
+/// FPDT Performance Record Types
+///
+#define EFI_ACPI_6_4_FPDT_RECORD_TYPE_FIRMWARE_BASIC_BOOT_POINTER 0x0000
+#define EFI_ACPI_6_4_FPDT_RECORD_TYPE_S3_PERFORMANCE_TABLE_POINTER 0x0001
+
+///
+/// FPDT Performance Record Revision
+///
+#define EFI_ACPI_6_4_FPDT_RECORD_REVISION_FIRMWARE_BASIC_BOOT_POINTER 0x01
+#define EFI_ACPI_6_4_FPDT_RECORD_REVISION_S3_PERFORMANCE_TABLE_POINTER 0x01
+
+///
+/// FPDT Runtime Performance Record Types
+///
+#define EFI_ACPI_6_4_FPDT_RUNTIME_RECORD_TYPE_S3_RESUME 0x0000
+#define EFI_ACPI_6_4_FPDT_RUNTIME_RECORD_TYPE_S3_SUSPEND 0x0001
+#define EFI_ACPI_6_4_FPDT_RUNTIME_RECORD_TYPE_FIRMWARE_BASIC_BOOT 0x0002
+
+///
+/// FPDT Runtime Performance Record Revision
+///
+#define EFI_ACPI_6_4_FPDT_RUNTIME_RECORD_REVISION_S3_RESUME 0x01
+#define EFI_ACPI_6_4_FPDT_RUNTIME_RECORD_REVISION_S3_SUSPEND 0x01
+#define EFI_ACPI_6_4_FPDT_RUNTIME_RECORD_REVISION_FIRMWARE_BASIC_BOOT 0x02
+
+///
+/// FPDT Performance Record header
+///
+typedef struct {
+ UINT16 Type;
+ UINT8 Length;
+ UINT8 Revision;
+} EFI_ACPI_6_4_FPDT_PERFORMANCE_RECORD_HEADER;
+
+///
+/// FPDT Performance Table header
+///
+typedef struct {
+ UINT32 Signature;
+ UINT32 Length;
+} EFI_ACPI_6_4_FPDT_PERFORMANCE_TABLE_HEADER;
+
+///
+/// FPDT Firmware Basic Boot Performance Pointer Record Structure
+///
+typedef struct {
+ EFI_ACPI_6_4_FPDT_PERFORMANCE_RECORD_HEADER Header;
+ UINT32 Reserved;
+ ///
+ /// 64-bit processor-relative physical address of the Basic Boot Performance Table.
+ ///
+ UINT64 BootPerformanceTablePointer;
+} EFI_ACPI_6_4_FPDT_BOOT_PERFORMANCE_TABLE_POINTER_RECORD;
+
+///
+/// FPDT S3 Performance Table Pointer Record Structure
+///
+typedef struct {
+ EFI_ACPI_6_4_FPDT_PERFORMANCE_RECORD_HEADER Header;
+ UINT32 Reserved;
+ ///
+ /// 64-bit processor-relative physical address of the S3 Performance Table.
+ ///
+ UINT64 S3PerformanceTablePointer;
+} EFI_ACPI_6_4_FPDT_S3_PERFORMANCE_TABLE_POINTER_RECORD;
+
+///
+/// FPDT Firmware Basic Boot Performance Record Structure
+///
+typedef struct {
+ EFI_ACPI_6_4_FPDT_PERFORMANCE_RECORD_HEADER Header;
+ UINT32 Reserved;
+ ///
+ /// Timer value logged at the beginning of firmware image execution.
+ /// This may not always be zero or near zero.
+ ///
+ UINT64 ResetEnd;
+ ///
+ /// Timer value logged just prior to loading the OS boot loader into memory.
+ /// For non-UEFI compatible boots, this field must be zero.
+ ///
+ UINT64 OsLoaderLoadImageStart;
+ ///
+ /// Timer value logged just prior to launching the previously loaded OS boot loader image.
+ /// For non-UEFI compatible boots, the timer value logged will be just prior
+ /// to the INT 19h handler invocation.
+ ///
+ UINT64 OsLoaderStartImageStart;
+ ///
+ /// Timer value logged at the point when the OS loader calls the
+ /// ExitBootServices function for UEFI compatible firmware.
+ /// For non-UEFI compatible boots, this field must be zero.
+ ///
+ UINT64 ExitBootServicesEntry;
+ ///
+ /// Timer value logged at the point just prior towhen the OS loader gaining
+ /// control back from calls the ExitBootServices function for UEFI compatible firmware.
+ /// For non-UEFI compatible boots, this field must be zero.
+ ///
+ UINT64 ExitBootServicesExit;
+} EFI_ACPI_6_4_FPDT_FIRMWARE_BASIC_BOOT_RECORD;
+
+///
+/// FPDT Firmware Basic Boot Performance Table signature
+///
+#define EFI_ACPI_6_4_FPDT_BOOT_PERFORMANCE_TABLE_SIGNATURE SIGNATURE_32('F', 'B', 'P', 'T')
+
+//
+// FPDT Firmware Basic Boot Performance Table
+//
+typedef struct {
+ EFI_ACPI_6_4_FPDT_PERFORMANCE_TABLE_HEADER Header;
+ //
+ // one or more Performance Records.
+ //
+} EFI_ACPI_6_4_FPDT_FIRMWARE_BASIC_BOOT_TABLE;
+
+///
+/// FPDT "S3PT" S3 Performance Table
+///
+#define EFI_ACPI_6_4_FPDT_S3_PERFORMANCE_TABLE_SIGNATURE SIGNATURE_32('S', '3', 'P', 'T')
+
+//
+// FPDT Firmware S3 Boot Performance Table
+//
+typedef struct {
+ EFI_ACPI_6_4_FPDT_PERFORMANCE_TABLE_HEADER Header;
+ //
+ // one or more Performance Records.
+ //
+} EFI_ACPI_6_4_FPDT_FIRMWARE_S3_BOOT_TABLE;
+
+///
+/// FPDT Basic S3 Resume Performance Record
+///
+typedef struct {
+ EFI_ACPI_6_4_FPDT_PERFORMANCE_RECORD_HEADER Header;
+ ///
+ /// A count of the number of S3 resume cycles since the last full boot sequence.
+ ///
+ UINT32 ResumeCount;
+ ///
+ /// Timer recorded at the end of BIOS S3 resume, just prior to handoff to the
+ /// OS waking vector. Only the most recent resume cycle's time is retained.
+ ///
+ UINT64 FullResume;
+ ///
+ /// Average timer value of all resume cycles logged since the last full boot
+ /// sequence, including the most recent resume. Note that the entire log of
+ /// timer values does not need to be retained in order to calculate this average.
+ ///
+ UINT64 AverageResume;
+} EFI_ACPI_6_4_FPDT_S3_RESUME_RECORD;
+
+///
+/// FPDT Basic S3 Suspend Performance Record
+///
+typedef struct {
+ EFI_ACPI_6_4_FPDT_PERFORMANCE_RECORD_HEADER Header;
+ ///
+ /// Timer value recorded at the OS write to SLP_TYP upon entry to S3.
+ /// Only the most recent suspend cycle's timer value is retained.
+ ///
+ UINT64 SuspendStart;
+ ///
+ /// Timer value recorded at the final firmware write to SLP_TYP (or other
+ /// mechanism) used to trigger hardware entry to S3.
+ /// Only the most recent suspend cycle's timer value is retained.
+ ///
+ UINT64 SuspendEnd;
+} EFI_ACPI_6_4_FPDT_S3_SUSPEND_RECORD;
+
+///
+/// Firmware Performance Record Table definition.
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+} EFI_ACPI_6_4_FIRMWARE_PERFORMANCE_RECORD_TABLE;
+
+///
+/// Generic Timer Description Table definition.
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT64 CntControlBasePhysicalAddress;
+ UINT32 Reserved;
+ UINT32 SecurePL1TimerGSIV;
+ UINT32 SecurePL1TimerFlags;
+ UINT32 NonSecurePL1TimerGSIV;
+ UINT32 NonSecurePL1TimerFlags;
+ UINT32 VirtualTimerGSIV;
+ UINT32 VirtualTimerFlags;
+ UINT32 NonSecurePL2TimerGSIV;
+ UINT32 NonSecurePL2TimerFlags;
+ UINT64 CntReadBasePhysicalAddress;
+ UINT32 PlatformTimerCount;
+ UINT32 PlatformTimerOffset;
+ UINT32 VirtualPL2TimerGSIV;
+ UINT32 VirtualPL2TimerFlags;
+} EFI_ACPI_6_4_GENERIC_TIMER_DESCRIPTION_TABLE;
+
+///
+/// GTDT Version (as defined in ACPI 6.4 spec.)
+///
+#define EFI_ACPI_6_4_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION 0x03
+
+///
+/// Timer Flags. All other bits are reserved and must be 0.
+///
+#define EFI_ACPI_6_4_GTDT_TIMER_FLAG_TIMER_INTERRUPT_MODE BIT0
+#define EFI_ACPI_6_4_GTDT_TIMER_FLAG_TIMER_INTERRUPT_POLARITY BIT1
+#define EFI_ACPI_6_4_GTDT_TIMER_FLAG_ALWAYS_ON_CAPABILITY BIT2
+
+///
+/// Platform Timer Type
+///
+#define EFI_ACPI_6_4_GTDT_GT_BLOCK 0
+#define EFI_ACPI_6_4_GTDT_ARM_GENERIC_WATCHDOG 1
+
+///
+/// GT Block Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT16 Length;
+ UINT8 Reserved;
+ UINT64 CntCtlBase;
+ UINT32 GTBlockTimerCount;
+ UINT32 GTBlockTimerOffset;
+} EFI_ACPI_6_4_GTDT_GT_BLOCK_STRUCTURE;
+
+///
+/// GT Block Timer Structure
+///
+typedef struct {
+ UINT8 GTFrameNumber;
+ UINT8 Reserved[3];
+ UINT64 CntBaseX;
+ UINT64 CntEL0BaseX;
+ UINT32 GTxPhysicalTimerGSIV;
+ UINT32 GTxPhysicalTimerFlags;
+ UINT32 GTxVirtualTimerGSIV;
+ UINT32 GTxVirtualTimerFlags;
+ UINT32 GTxCommonFlags;
+} EFI_ACPI_6_4_GTDT_GT_BLOCK_TIMER_STRUCTURE;
+
+///
+/// GT Block Physical Timers and Virtual Timers Flags. All other bits are reserved and must be 0.
+///
+#define EFI_ACPI_6_4_GTDT_GT_BLOCK_TIMER_FLAG_TIMER_INTERRUPT_MODE BIT0
+#define EFI_ACPI_6_4_GTDT_GT_BLOCK_TIMER_FLAG_TIMER_INTERRUPT_POLARITY BIT1
+
+///
+/// Common Flags Flags. All other bits are reserved and must be 0.
+///
+#define EFI_ACPI_6_4_GTDT_GT_BLOCK_COMMON_FLAG_SECURE_TIMER BIT0
+#define EFI_ACPI_6_4_GTDT_GT_BLOCK_COMMON_FLAG_ALWAYS_ON_CAPABILITY BIT1
+
+///
+/// Arm Generic Watchdog Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT16 Length;
+ UINT8 Reserved;
+ UINT64 RefreshFramePhysicalAddress;
+ UINT64 WatchdogControlFramePhysicalAddress;
+ UINT32 WatchdogTimerGSIV;
+ UINT32 WatchdogTimerFlags;
+} EFI_ACPI_6_4_GTDT_ARM_GENERIC_WATCHDOG_STRUCTURE;
+
+///
+/// Arm Generic Watchdog Timer Flags. All other bits are reserved and must be 0.
+///
+#define EFI_ACPI_6_4_GTDT_ARM_GENERIC_WATCHDOG_FLAG_TIMER_INTERRUPT_MODE BIT0
+#define EFI_ACPI_6_4_GTDT_ARM_GENERIC_WATCHDOG_FLAG_TIMER_INTERRUPT_POLARITY BIT1
+#define EFI_ACPI_6_4_GTDT_ARM_GENERIC_WATCHDOG_FLAG_SECURE_TIMER BIT2
+
+//
+// NVDIMM Firmware Interface Table definition.
+//
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 Reserved;
+} EFI_ACPI_6_4_NVDIMM_FIRMWARE_INTERFACE_TABLE;
+
+//
+// NFIT Version (as defined in ACPI 6.4 spec.)
+//
+#define EFI_ACPI_6_4_NVDIMM_FIRMWARE_INTERFACE_TABLE_REVISION 0x1
+
+//
+// Definition for NFIT Table Structure Types
+//
+#define EFI_ACPI_6_4_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_STRUCTURE_TYPE 0
+#define EFI_ACPI_6_4_NFIT_NVDIMM_REGION_MAPPING_STRUCTURE_TYPE 1
+#define EFI_ACPI_6_4_NFIT_INTERLEAVE_STRUCTURE_TYPE 2
+#define EFI_ACPI_6_4_NFIT_SMBIOS_MANAGEMENT_INFORMATION_STRUCTURE_TYPE 3
+#define EFI_ACPI_6_4_NFIT_NVDIMM_CONTROL_REGION_STRUCTURE_TYPE 4
+#define EFI_ACPI_6_4_NFIT_NVDIMM_BLOCK_DATA_WINDOW_REGION_STRUCTURE_TYPE 5
+#define EFI_ACPI_6_4_NFIT_FLUSH_HINT_ADDRESS_STRUCTURE_TYPE 6
+#define EFI_ACPI_6_4_NFIT_PLATFORM_CAPABILITIES_STRUCTURE_TYPE 7
+
+//
+// Definition for NFIT Structure Header
+//
+typedef struct {
+ UINT16 Type;
+ UINT16 Length;
+} EFI_ACPI_6_4_NFIT_STRUCTURE_HEADER;
+
+//
+// Definition for System Physical Address Range Structure
+//
+#define EFI_ACPI_6_4_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_FLAGS_CONTROL_REGION_FOR_MANAGEMENT BIT0
+#define EFI_ACPI_6_4_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_FLAGS_PROXIMITY_DOMAIN_VALID BIT1
+#define EFI_ACPI_6_4_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_FLAGS_SPA_LOCATION_COOKIE_VALID BIT2
+
+#define EFI_ACPI_6_4_NFIT_GUID_VOLATILE_MEMORY_REGION { 0x7305944F, 0xFDDA, 0x44E3, { 0xB1, 0x6C, 0x3F, 0x22, 0xD2, 0x52, 0xE5, 0xD0 }}
+#define EFI_ACPI_6_4_NFIT_GUID_BYTE_ADDRESSABLE_PERSISTENT_MEMORY_REGION { 0x66F0D379, 0xB4F3, 0x4074, { 0xAC, 0x43, 0x0D, 0x33, 0x18, 0xB7, 0x8C, 0xDB }}
+#define EFI_ACPI_6_4_NFIT_GUID_NVDIMM_CONTROL_REGION { 0x92F701F6, 0x13B4, 0x405D, { 0x91, 0x0B, 0x29, 0x93, 0x67, 0xE8, 0x23, 0x4C }}
+#define EFI_ACPI_6_4_NFIT_GUID_NVDIMM_BLOCK_DATA_WINDOW_REGION { 0x91AF0530, 0x5D86, 0x470E, { 0xA6, 0xB0, 0x0A, 0x2D, 0xB9, 0x40, 0x82, 0x49 }}
+#define EFI_ACPI_6_4_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_DISK_REGION_VOLATILE { 0x77AB535A, 0x45FC, 0x624B, { 0x55, 0x60, 0xF7, 0xB2, 0x81, 0xD1, 0xF9, 0x6E }}
+#define EFI_ACPI_6_4_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_CD_REGION_VOLATILE { 0x3D5ABD30, 0x4175, 0x87CE, { 0x6D, 0x64, 0xD2, 0xAD, 0xE5, 0x23, 0xC4, 0xBB }}
+#define EFI_ACPI_6_4_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_DISK_REGION_PERSISTENT { 0x5CEA02C9, 0x4D07, 0x69D3, { 0x26, 0x9F ,0x44, 0x96, 0xFB, 0xE0, 0x96, 0xF9 }}
+#define EFI_ACPI_6_4_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_CD_REGION_PERSISTENT { 0x08018188, 0x42CD, 0xBB48, { 0x10, 0x0F, 0x53, 0x87, 0xD5, 0x3D, 0xED, 0x3D }}
+
+typedef struct {
+ UINT16 Type;
+ UINT16 Length;
+ UINT16 SPARangeStructureIndex;
+ UINT16 Flags;
+ UINT32 Reserved_8;
+ UINT32 ProximityDomain;
+ GUID AddressRangeTypeGUID;
+ UINT64 SystemPhysicalAddressRangeBase;
+ UINT64 SystemPhysicalAddressRangeLength;
+ UINT64 AddressRangeMemoryMappingAttribute;
+ UINT64 SPALocationCookie;
+} EFI_ACPI_6_4_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_STRUCTURE;
+
+//
+// Definition for Memory Device to System Physical Address Range Mapping Structure
+//
+typedef struct {
+ UINT32 DIMMNumber : 4;
+ UINT32 MemoryChannelNumber : 4;
+ UINT32 MemoryControllerID : 4;
+ UINT32 SocketID : 4;
+ UINT32 NodeControllerID : 12;
+ UINT32 Reserved_28 : 4;
+} EFI_ACPI_6_4_NFIT_DEVICE_HANDLE;
+
+#define EFI_ACPI_6_4_NFIT_MEMORY_DEVICE_STATE_FLAGS_PREVIOUS_SAVE_FAIL BIT0
+#define EFI_ACPI_6_4_NFIT_MEMORY_DEVICE_STATE_FLAGS_LAST_RESTORE_FAIL BIT1
+#define EFI_ACPI_6_4_NFIT_MEMORY_DEVICE_STATE_FLAGS_PLATFORM_FLUSH_FAIL BIT2
+#define EFI_ACPI_6_4_NFIT_MEMORY_DEVICE_STATE_FLAGS_NOT_ARMED_PRIOR_TO_OSPM_HAND_OFF BIT3
+#define EFI_ACPI_6_4_NFIT_MEMORY_DEVICE_STATE_FLAGS_SMART_HEALTH_EVENTS_PRIOR_OSPM_HAND_OFF BIT4
+#define EFI_ACPI_6_4_NFIT_MEMORY_DEVICE_STATE_FLAGS_FIRMWARE_ENABLED_TO_NOTIFY_OSPM_ON_SMART_HEALTH_EVENTS BIT5
+#define EFI_ACPI_6_4_NFIT_MEMORY_DEVICE_STATE_FLAGS_FIRMWARE_NOT_MAP_NVDIMM_TO_SPA BIT6
+
+typedef struct {
+ UINT16 Type;
+ UINT16 Length;
+ EFI_ACPI_6_4_NFIT_DEVICE_HANDLE NFITDeviceHandle;
+ UINT16 NVDIMMPhysicalID;
+ UINT16 NVDIMMRegionID;
+ UINT16 SPARangeStructureIndex;
+ UINT16 NVDIMMControlRegionStructureIndex;
+ UINT64 NVDIMMRegionSize;
+ UINT64 RegionOffset;
+ UINT64 NVDIMMPhysicalAddressRegionBase;
+ UINT16 InterleaveStructureIndex;
+ UINT16 InterleaveWays;
+ UINT16 NVDIMMStateFlags;
+ UINT16 Reserved_46;
+} EFI_ACPI_6_4_NFIT_NVDIMM_REGION_MAPPING_STRUCTURE;
+
+//
+// Definition for Interleave Structure
+//
+typedef struct {
+ UINT16 Type;
+ UINT16 Length;
+ UINT16 InterleaveStructureIndex;
+ UINT16 Reserved_6;
+ UINT32 NumberOfLines;
+ UINT32 LineSize;
+ // UINT32 LineOffset[NumberOfLines];
+} EFI_ACPI_6_4_NFIT_INTERLEAVE_STRUCTURE;
+
+//
+// Definition for SMBIOS Management Information Structure
+//
+typedef struct {
+ UINT16 Type;
+ UINT16 Length;
+ UINT32 Reserved_4;
+ // UINT8 Data[];
+} EFI_ACPI_6_4_NFIT_SMBIOS_MANAGEMENT_INFORMATION_STRUCTURE;
+
+//
+// Definition for NVDIMM Control Region Structure
+//
+#define EFI_ACPI_6_4_NFIT_NVDIMM_CONTROL_REGION_VALID_FIELDS_MANUFACTURING BIT0
+
+#define EFI_ACPI_6_4_NFIT_NVDIMM_CONTROL_REGION_FLAGS_BLOCK_DATA_WINDOWS_BUFFERED BIT0
+
+typedef struct {
+ UINT16 Type;
+ UINT16 Length;
+ UINT16 NVDIMMControlRegionStructureIndex;
+ UINT16 VendorID;
+ UINT16 DeviceID;
+ UINT16 RevisionID;
+ UINT16 SubsystemVendorID;
+ UINT16 SubsystemDeviceID;
+ UINT16 SubsystemRevisionID;
+ UINT8 ValidFields;
+ UINT8 ManufacturingLocation;
+ UINT16 ManufacturingDate;
+ UINT8 Reserved_22[2];
+ UINT32 SerialNumber;
+ UINT16 RegionFormatInterfaceCode;
+ UINT16 NumberOfBlockControlWindows;
+ UINT64 SizeOfBlockControlWindow;
+ UINT64 CommandRegisterOffsetInBlockControlWindow;
+ UINT64 SizeOfCommandRegisterInBlockControlWindows;
+ UINT64 StatusRegisterOffsetInBlockControlWindow;
+ UINT64 SizeOfStatusRegisterInBlockControlWindows;
+ UINT16 NVDIMMControlRegionFlag;
+ UINT8 Reserved_74[6];
+} EFI_ACPI_6_4_NFIT_NVDIMM_CONTROL_REGION_STRUCTURE;
+
+//
+// Definition for NVDIMM Block Data Window Region Structure
+//
+typedef struct {
+ UINT16 Type;
+ UINT16 Length;
+ UINT16 NVDIMMControlRegionStructureIndex;
+ UINT16 NumberOfBlockDataWindows;
+ UINT64 BlockDataWindowStartOffset;
+ UINT64 SizeOfBlockDataWindow;
+ UINT64 BlockAccessibleMemoryCapacity;
+ UINT64 BeginningAddressOfFirstBlockInBlockAccessibleMemory;
+} EFI_ACPI_6_4_NFIT_NVDIMM_BLOCK_DATA_WINDOW_REGION_STRUCTURE;
+
+//
+// Definition for Flush Hint Address Structure
+//
+typedef struct {
+ UINT16 Type;
+ UINT16 Length;
+ EFI_ACPI_6_4_NFIT_DEVICE_HANDLE NFITDeviceHandle;
+ UINT16 NumberOfFlushHintAddresses;
+ UINT8 Reserved_10[6];
+ // UINT64 FlushHintAddress[NumberOfFlushHintAddresses];
+} EFI_ACPI_6_4_NFIT_FLUSH_HINT_ADDRESS_STRUCTURE;
+
+//
+// Definition for Platform Capabilities Structure
+//
+typedef struct {
+ UINT16 Type;
+ UINT16 Length;
+ UINT8 HighestValidCapability;
+ UINT8 Reserved_5[3];
+ UINT32 Capabilities;
+ UINT8 Reserved_12[4];
+} EFI_ACPI_6_4_NFIT_PLATFORM_CAPABILITIES_STRUCTURE;
+
+#define EFI_ACPI_6_4_NFIT_PLATFORM_CAPABILITY_CPU_CACHE_FLUSH_TO_NVDIMM_DURABILITY_ON_POWER_LOSS BIT0
+#define EFI_ACPI_6_4_NFIT_PLATFORM_CAPABILITY_MEMORY_CONTROLLER_FLUSH_TO_NVDIMM_DURABILITY_ON_POWER_LOSS BIT1
+#define EFI_ACPI_6_4_NFIT_PLATFORM_CAPABILITY_BYTE_ADDRESSABLE_PERSISTENT_MEMORY_HARDWARE_MIRRORING BIT2
+
+///
+/// Secure DEVices Table (SDEV)
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+} EFI_ACPI_6_4_SECURE_DEVICES_TABLE_HEADER;
+
+///
+/// SDEV Revision (as defined in ACPI 6.4 spec.)
+///
+#define EFI_ACPI_6_4_SECURE_DEVICES_TABLE_REVISION 0x01
+
+///
+/// Secure Device types
+///
+#define EFI_ACPI_6_4_SDEV_TYPE_ACPI_NAMESPACE_DEVICE 0x00
+#define EFI_ACPI_6_4_SDEV_TYPE_PCIE_ENDPOINT_DEVICE 0x01
+
+///
+/// Secure Device flags
+///
+#define EFI_ACPI_6_4_SDEV_FLAG_ALLOW_HANDOFF BIT0
+#define EFI_ACPI_6_4_SDEV_FLAG_SECURE_ACCESS_COMPONENTS_PRESENT BIT1
+
+///
+/// SDEV Structure Header
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Flags;
+ UINT16 Length;
+} EFI_ACPI_6_4_SDEV_STRUCTURE_HEADER;
+
+///
+/// ACPI_NAMESPACE_DEVICE based Secure Device Structure
+///
+typedef struct {
+ EFI_ACPI_6_4_SDEV_STRUCTURE_HEADER Header;
+ UINT16 DeviceIdentifierOffset;
+ UINT16 DeviceIdentifierLength;
+ UINT16 VendorSpecificDataOffset;
+ UINT16 VendorSpecificDataLength;
+ UINT16 SecureAccessComponentsOffset;
+ UINT16 SecureAccessComponentsLength;
+} EFI_ACPI_6_4_SDEV_STRUCTURE_ACPI_NAMESPACE_DEVICE;
+
+///
+/// Secure Access Component Types
+///
+#define EFI_ACPI_6_4_SDEV_SECURE_ACCESS_COMPONENT_TYPE_IDENTIFICATION 0x00
+#define EFI_ACPI_6_4_SDEV_SECURE_ACCESS_COMPONENT_TYPE_MEMORY 0x01
+
+///
+/// Identification Based Secure Access Component
+///
+typedef struct {
+ EFI_ACPI_6_4_SDEV_STRUCTURE_HEADER Header;
+ UINT16 HardwareIdentifierOffset;
+ UINT16 HardwareIdentifierLength;
+ UINT16 SubsystemIdentifierOffset;
+ UINT16 SubsystemIdentifierLength;
+ UINT16 HardwareRevision;
+ UINT8 HardwareRevisionPresent;
+ UINT8 ClassCodePresent;
+ UINT8 PciCompatibleBaseClass;
+ UINT8 PciCompatibleSubClass;
+ UINT8 PciCompatibleProgrammingInterface;
+} EFI_ACPI_6_4_SDEV_SECURE_ACCESS_COMPONENT_IDENTIFICATION_STRUCTURE;
+
+///
+/// Memory-based Secure Access Component
+///
+typedef struct {
+ EFI_ACPI_6_4_SDEV_STRUCTURE_HEADER Header;
+ UINT32 Reserved;
+ UINT64 MemoryAddressBase;
+ UINT64 MemoryLength;
+} EFI_ACPI_6_4_SDEV_SECURE_ACCESS_COMPONENT_MEMORY_STRUCTURE;
+
+///
+/// PCIe Endpoint Device based Secure Device Structure
+///
+typedef struct {
+ EFI_ACPI_6_4_SDEV_STRUCTURE_HEADER Header;
+ UINT16 PciSegmentNumber;
+ UINT16 StartBusNumber;
+ UINT16 PciPathOffset;
+ UINT16 PciPathLength;
+ UINT16 VendorSpecificDataOffset;
+ UINT16 VendorSpecificDataLength;
+} EFI_ACPI_6_4_SDEV_STRUCTURE_PCIE_ENDPOINT_DEVICE;
+
+///
+/// Boot Error Record Table (BERT)
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 BootErrorRegionLength;
+ UINT64 BootErrorRegion;
+} EFI_ACPI_6_4_BOOT_ERROR_RECORD_TABLE_HEADER;
+
+///
+/// BERT Version (as defined in ACPI 6.4 spec.)
+///
+#define EFI_ACPI_6_4_BOOT_ERROR_RECORD_TABLE_REVISION 0x01
+
+///
+/// Boot Error Region Block Status Definition
+///
+typedef struct {
+ UINT32 UncorrectableErrorValid : 1;
+ UINT32 CorrectableErrorValid : 1;
+ UINT32 MultipleUncorrectableErrors : 1;
+ UINT32 MultipleCorrectableErrors : 1;
+ UINT32 ErrorDataEntryCount : 10;
+ UINT32 Reserved : 18;
+} EFI_ACPI_6_4_ERROR_BLOCK_STATUS;
+
+///
+/// Boot Error Region Definition
+///
+typedef struct {
+ EFI_ACPI_6_4_ERROR_BLOCK_STATUS BlockStatus;
+ UINT32 RawDataOffset;
+ UINT32 RawDataLength;
+ UINT32 DataLength;
+ UINT32 ErrorSeverity;
+} EFI_ACPI_6_4_BOOT_ERROR_REGION_STRUCTURE;
+
+//
+// Boot Error Severity types
+//
+#define EFI_ACPI_6_4_ERROR_SEVERITY_RECOVERABLE 0x00
+#define EFI_ACPI_6_4_ERROR_SEVERITY_FATAL 0x01
+#define EFI_ACPI_6_4_ERROR_SEVERITY_CORRECTED 0x02
+#define EFI_ACPI_6_4_ERROR_SEVERITY_NONE 0x03
+//
+// The term 'Correctable' is no longer being used as an error severity of the
+// reported error since ACPI Specification Version 5.1 Errata B.
+// The below macro is considered as deprecated and should no longer be used.
+//
+#define EFI_ACPI_6_4_ERROR_SEVERITY_CORRECTABLE 0x00
+
+///
+/// Generic Error Data Entry Definition
+///
+typedef struct {
+ UINT8 SectionType[16];
+ UINT32 ErrorSeverity;
+ UINT16 Revision;
+ UINT8 ValidationBits;
+ UINT8 Flags;
+ UINT32 ErrorDataLength;
+ UINT8 FruId[16];
+ UINT8 FruText[20];
+ UINT8 Timestamp[8];
+} EFI_ACPI_6_4_GENERIC_ERROR_DATA_ENTRY_STRUCTURE;
+
+///
+/// Generic Error Data Entry Version (as defined in ACPI 6.4 spec.)
+///
+#define EFI_ACPI_6_4_GENERIC_ERROR_DATA_ENTRY_REVISION 0x0300
+
+///
+/// HEST - Hardware Error Source Table
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 ErrorSourceCount;
+} EFI_ACPI_6_4_HARDWARE_ERROR_SOURCE_TABLE_HEADER;
+
+///
+/// HEST Version (as defined in ACPI 6.4 spec.)
+///
+#define EFI_ACPI_6_4_HARDWARE_ERROR_SOURCE_TABLE_REVISION 0x01
+
+//
+// Error Source structure types.
+//
+#define EFI_ACPI_6_4_IA32_ARCHITECTURE_MACHINE_CHECK_EXCEPTION 0x00
+#define EFI_ACPI_6_4_IA32_ARCHITECTURE_CORRECTED_MACHINE_CHECK 0x01
+#define EFI_ACPI_6_4_IA32_ARCHITECTURE_NMI_ERROR 0x02
+#define EFI_ACPI_6_4_PCI_EXPRESS_ROOT_PORT_AER 0x06
+#define EFI_ACPI_6_4_PCI_EXPRESS_DEVICE_AER 0x07
+#define EFI_ACPI_6_4_PCI_EXPRESS_BRIDGE_AER 0x08
+#define EFI_ACPI_6_4_GENERIC_HARDWARE_ERROR 0x09
+#define EFI_ACPI_6_4_GENERIC_HARDWARE_ERROR_VERSION_2 0x0A
+#define EFI_ACPI_6_4_IA32_ARCHITECTURE_DEFERRED_MACHINE_CHECK 0x0B
+
+//
+// Error Source structure flags.
+//
+#define EFI_ACPI_6_4_ERROR_SOURCE_FLAG_FIRMWARE_FIRST (1 << 0)
+#define EFI_ACPI_6_4_ERROR_SOURCE_FLAG_GLOBAL (1 << 1)
+#define EFI_ACPI_6_4_ERROR_SOURCE_FLAG_GHES_ASSIST (1 << 2)
+
+///
+/// IA-32 Architecture Machine Check Exception Structure Definition
+///
+typedef struct {
+ UINT16 Type;
+ UINT16 SourceId;
+ UINT8 Reserved0[2];
+ UINT8 Flags;
+ UINT8 Enabled;
+ UINT32 NumberOfRecordsToPreAllocate;
+ UINT32 MaxSectionsPerRecord;
+ UINT64 GlobalCapabilityInitData;
+ UINT64 GlobalControlInitData;
+ UINT8 NumberOfHardwareBanks;
+ UINT8 Reserved1[7];
+} EFI_ACPI_6_4_IA32_ARCHITECTURE_MACHINE_CHECK_EXCEPTION_STRUCTURE;
+
+///
+/// IA-32 Architecture Machine Check Bank Structure Definition
+///
+typedef struct {
+ UINT8 BankNumber;
+ UINT8 ClearStatusOnInitialization;
+ UINT8 StatusDataFormat;
+ UINT8 Reserved0;
+ UINT32 ControlRegisterMsrAddress;
+ UINT64 ControlInitData;
+ UINT32 StatusRegisterMsrAddress;
+ UINT32 AddressRegisterMsrAddress;
+ UINT32 MiscRegisterMsrAddress;
+} EFI_ACPI_6_4_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_BANK_STRUCTURE;
+
+///
+/// IA-32 Architecture Machine Check Bank Structure MCA data format
+///
+#define EFI_ACPI_6_4_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_IA32 0x00
+#define EFI_ACPI_6_4_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_INTEL64 0x01
+#define EFI_ACPI_6_4_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_AMD64 0x02
+
+//
+// Hardware Error Notification types. All other values are reserved
+//
+#define EFI_ACPI_6_4_HARDWARE_ERROR_NOTIFICATION_POLLED 0x00
+#define EFI_ACPI_6_4_HARDWARE_ERROR_NOTIFICATION_EXTERNAL_INTERRUPT 0x01
+#define EFI_ACPI_6_4_HARDWARE_ERROR_NOTIFICATION_LOCAL_INTERRUPT 0x02
+#define EFI_ACPI_6_4_HARDWARE_ERROR_NOTIFICATION_SCI 0x03
+#define EFI_ACPI_6_4_HARDWARE_ERROR_NOTIFICATION_NMI 0x04
+#define EFI_ACPI_6_4_HARDWARE_ERROR_NOTIFICATION_CMCI 0x05
+#define EFI_ACPI_6_4_HARDWARE_ERROR_NOTIFICATION_MCE 0x06
+#define EFI_ACPI_6_4_HARDWARE_ERROR_NOTIFICATION_GPIO_SIGNAL 0x07
+#define EFI_ACPI_6_4_HARDWARE_ERROR_NOTIFICATION_ARMV8_SEA 0x08
+#define EFI_ACPI_6_4_HARDWARE_ERROR_NOTIFICATION_ARMV8_SEI 0x09
+#define EFI_ACPI_6_4_HARDWARE_ERROR_NOTIFICATION_GSIV 0x0A
+#define EFI_ACPI_6_4_HARDWARE_ERROR_NOTIFICATION_SOFTWARE_DELEGATED_EXCEPTION 0x0B
+
+///
+/// Hardware Error Notification Configuration Write Enable Structure Definition
+///
+typedef struct {
+ UINT16 Type : 1;
+ UINT16 PollInterval : 1;
+ UINT16 SwitchToPollingThresholdValue : 1;
+ UINT16 SwitchToPollingThresholdWindow : 1;
+ UINT16 ErrorThresholdValue : 1;
+ UINT16 ErrorThresholdWindow : 1;
+ UINT16 Reserved : 10;
+} EFI_ACPI_6_4_HARDWARE_ERROR_NOTIFICATION_CONFIGURATION_WRITE_ENABLE_STRUCTURE;
+
+///
+/// Hardware Error Notification Structure Definition
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ EFI_ACPI_6_4_HARDWARE_ERROR_NOTIFICATION_CONFIGURATION_WRITE_ENABLE_STRUCTURE ConfigurationWriteEnable;
+ UINT32 PollInterval;
+ UINT32 Vector;
+ UINT32 SwitchToPollingThresholdValue;
+ UINT32 SwitchToPollingThresholdWindow;
+ UINT32 ErrorThresholdValue;
+ UINT32 ErrorThresholdWindow;
+} EFI_ACPI_6_4_HARDWARE_ERROR_NOTIFICATION_STRUCTURE;
+
+///
+/// IA-32 Architecture Corrected Machine Check Structure Definition
+///
+typedef struct {
+ UINT16 Type;
+ UINT16 SourceId;
+ UINT8 Reserved0[2];
+ UINT8 Flags;
+ UINT8 Enabled;
+ UINT32 NumberOfRecordsToPreAllocate;
+ UINT32 MaxSectionsPerRecord;
+ EFI_ACPI_6_4_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure;
+ UINT8 NumberOfHardwareBanks;
+ UINT8 Reserved1[3];
+} EFI_ACPI_6_4_IA32_ARCHITECTURE_CORRECTED_MACHINE_CHECK_STRUCTURE;
+
+///
+/// IA-32 Architecture NMI Error Structure Definition
+///
+typedef struct {
+ UINT16 Type;
+ UINT16 SourceId;
+ UINT8 Reserved0[2];
+ UINT32 NumberOfRecordsToPreAllocate;
+ UINT32 MaxSectionsPerRecord;
+ UINT32 MaxRawDataLength;
+} EFI_ACPI_6_4_IA32_ARCHITECTURE_NMI_ERROR_STRUCTURE;
+
+///
+/// PCI Express Root Port AER Structure Definition
+///
+typedef struct {
+ UINT16 Type;
+ UINT16 SourceId;
+ UINT8 Reserved0[2];
+ UINT8 Flags;
+ UINT8 Enabled;
+ UINT32 NumberOfRecordsToPreAllocate;
+ UINT32 MaxSectionsPerRecord;
+ UINT32 Bus;
+ UINT16 Device;
+ UINT16 Function;
+ UINT16 DeviceControl;
+ UINT8 Reserved1[2];
+ UINT32 UncorrectableErrorMask;
+ UINT32 UncorrectableErrorSeverity;
+ UINT32 CorrectableErrorMask;
+ UINT32 AdvancedErrorCapabilitiesAndControl;
+ UINT32 RootErrorCommand;
+} EFI_ACPI_6_4_PCI_EXPRESS_ROOT_PORT_AER_STRUCTURE;
+
+///
+/// PCI Express Device AER Structure Definition
+///
+typedef struct {
+ UINT16 Type;
+ UINT16 SourceId;
+ UINT8 Reserved0[2];
+ UINT8 Flags;
+ UINT8 Enabled;
+ UINT32 NumberOfRecordsToPreAllocate;
+ UINT32 MaxSectionsPerRecord;
+ UINT32 Bus;
+ UINT16 Device;
+ UINT16 Function;
+ UINT16 DeviceControl;
+ UINT8 Reserved1[2];
+ UINT32 UncorrectableErrorMask;
+ UINT32 UncorrectableErrorSeverity;
+ UINT32 CorrectableErrorMask;
+ UINT32 AdvancedErrorCapabilitiesAndControl;
+} EFI_ACPI_6_4_PCI_EXPRESS_DEVICE_AER_STRUCTURE;
+
+///
+/// PCI Express Bridge AER Structure Definition
+///
+typedef struct {
+ UINT16 Type;
+ UINT16 SourceId;
+ UINT8 Reserved0[2];
+ UINT8 Flags;
+ UINT8 Enabled;
+ UINT32 NumberOfRecordsToPreAllocate;
+ UINT32 MaxSectionsPerRecord;
+ UINT32 Bus;
+ UINT16 Device;
+ UINT16 Function;
+ UINT16 DeviceControl;
+ UINT8 Reserved1[2];
+ UINT32 UncorrectableErrorMask;
+ UINT32 UncorrectableErrorSeverity;
+ UINT32 CorrectableErrorMask;
+ UINT32 AdvancedErrorCapabilitiesAndControl;
+ UINT32 SecondaryUncorrectableErrorMask;
+ UINT32 SecondaryUncorrectableErrorSeverity;
+ UINT32 SecondaryAdvancedErrorCapabilitiesAndControl;
+} EFI_ACPI_6_4_PCI_EXPRESS_BRIDGE_AER_STRUCTURE;
+
+///
+/// Generic Hardware Error Source Structure Definition
+///
+typedef struct {
+ UINT16 Type;
+ UINT16 SourceId;
+ UINT16 RelatedSourceId;
+ UINT8 Flags;
+ UINT8 Enabled;
+ UINT32 NumberOfRecordsToPreAllocate;
+ UINT32 MaxSectionsPerRecord;
+ UINT32 MaxRawDataLength;
+ EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE ErrorStatusAddress;
+ EFI_ACPI_6_4_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure;
+ UINT32 ErrorStatusBlockLength;
+} EFI_ACPI_6_4_GENERIC_HARDWARE_ERROR_SOURCE_STRUCTURE;
+
+///
+/// Generic Hardware Error Source Version 2 Structure Definition
+///
+typedef struct {
+ UINT16 Type;
+ UINT16 SourceId;
+ UINT16 RelatedSourceId;
+ UINT8 Flags;
+ UINT8 Enabled;
+ UINT32 NumberOfRecordsToPreAllocate;
+ UINT32 MaxSectionsPerRecord;
+ UINT32 MaxRawDataLength;
+ EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE ErrorStatusAddress;
+ EFI_ACPI_6_4_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure;
+ UINT32 ErrorStatusBlockLength;
+ EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE ReadAckRegister;
+ UINT64 ReadAckPreserve;
+ UINT64 ReadAckWrite;
+} EFI_ACPI_6_4_GENERIC_HARDWARE_ERROR_SOURCE_VERSION_2_STRUCTURE;
+
+///
+/// Generic Error Status Definition
+///
+typedef struct {
+ EFI_ACPI_6_4_ERROR_BLOCK_STATUS BlockStatus;
+ UINT32 RawDataOffset;
+ UINT32 RawDataLength;
+ UINT32 DataLength;
+ UINT32 ErrorSeverity;
+} EFI_ACPI_6_4_GENERIC_ERROR_STATUS_STRUCTURE;
+
+///
+/// IA-32 Architecture Deferred Machine Check Structure Definition
+///
+typedef struct {
+ UINT16 Type;
+ UINT16 SourceId;
+ UINT8 Reserved0[2];
+ UINT8 Flags;
+ UINT8 Enabled;
+ UINT32 NumberOfRecordsToPreAllocate;
+ UINT32 MaxSectionsPerRecord;
+ EFI_ACPI_6_4_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure;
+ UINT8 NumberOfHardwareBanks;
+ UINT8 Reserved1[3];
+} EFI_ACPI_6_4_IA32_ARCHITECTURE_DEFERRED_MACHINE_CHECK_STRUCTURE;
+
+///
+/// HMAT - Heterogeneous Memory Attribute Table
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT8 Reserved[4];
+} EFI_ACPI_6_4_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_HEADER;
+
+///
+/// HMAT Revision (as defined in ACPI 6.4 spec.)
+///
+#define EFI_ACPI_6_4_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_REVISION 0x02
+
+///
+/// HMAT types
+///
+#define EFI_ACPI_6_4_HMAT_TYPE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES 0x00
+#define EFI_ACPI_6_4_HMAT_TYPE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO 0x01
+#define EFI_ACPI_6_4_HMAT_TYPE_MEMORY_SIDE_CACHE_INFO 0x02
+
+///
+/// HMAT Structure Header
+///
+typedef struct {
+ UINT16 Type;
+ UINT8 Reserved[2];
+ UINT32 Length;
+} EFI_ACPI_6_4_HMAT_STRUCTURE_HEADER;
+
+///
+/// Memory Proximity Domain Attributes Structure flags
+///
+typedef struct {
+ UINT16 InitiatorProximityDomainValid : 1;
+ UINT16 Reserved : 15;
+} EFI_ACPI_6_4_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES_FLAGS;
+
+///
+/// Memory Proximity Domain Attributes Structure
+///
+typedef struct {
+ UINT16 Type;
+ UINT8 Reserved[2];
+ UINT32 Length;
+ EFI_ACPI_6_4_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES_FLAGS Flags;
+ UINT8 Reserved1[2];
+ UINT32 InitiatorProximityDomain;
+ UINT32 MemoryProximityDomain;
+ UINT8 Reserved2[20];
+} EFI_ACPI_6_4_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES;
+
+///
+/// System Locality Latency and Bandwidth Information Structure flags
+///
+typedef struct {
+ UINT8 MemoryHierarchy : 4;
+ UINT8 AccessAttributes : 2;
+ UINT8 Reserved : 2;
+} EFI_ACPI_6_4_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO_FLAGS;
+
+///
+/// System Locality Latency and Bandwidth Information Structure
+///
+typedef struct {
+ UINT16 Type;
+ UINT8 Reserved[2];
+ UINT32 Length;
+ EFI_ACPI_6_4_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO_FLAGS Flags;
+ UINT8 DataType;
+ UINT8 MinTransferSize;
+ UINT8 Reserved1;
+ UINT32 NumberOfInitiatorProximityDomains;
+ UINT32 NumberOfTargetProximityDomains;
+ UINT8 Reserved2[4];
+ UINT64 EntryBaseUnit;
+} EFI_ACPI_6_4_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO;
+
+///
+/// Memory Side Cache Information Structure cache attributes
+///
+typedef struct {
+ UINT32 TotalCacheLevels : 4;
+ UINT32 CacheLevel : 4;
+ UINT32 CacheAssociativity : 4;
+ UINT32 WritePolicy : 4;
+ UINT32 CacheLineSize : 16;
+} EFI_ACPI_6_4_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_CACHE_ATTRIBUTES;
+
+///
+/// Memory Side Cache Information Structure
+///
+typedef struct {
+ UINT16 Type;
+ UINT8 Reserved[2];
+ UINT32 Length;
+ UINT32 MemoryProximityDomain;
+ UINT8 Reserved1[4];
+ UINT64 MemorySideCacheSize;
+ EFI_ACPI_6_4_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_CACHE_ATTRIBUTES CacheAttributes;
+ UINT8 Reserved2[2];
+ UINT16 NumberOfSmbiosHandles;
+} EFI_ACPI_6_4_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO;
+
+///
+/// ERST - Error Record Serialization Table
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 SerializationHeaderSize;
+ UINT8 Reserved0[4];
+ UINT32 InstructionEntryCount;
+} EFI_ACPI_6_4_ERROR_RECORD_SERIALIZATION_TABLE_HEADER;
+
+///
+/// ERST Version (as defined in ACPI 6.4 spec.)
+///
+#define EFI_ACPI_6_4_ERROR_RECORD_SERIALIZATION_TABLE_REVISION 0x01
+
+///
+/// ERST Serialization Actions
+///
+#define EFI_ACPI_6_4_ERST_BEGIN_WRITE_OPERATION 0x00
+#define EFI_ACPI_6_4_ERST_BEGIN_READ_OPERATION 0x01
+#define EFI_ACPI_6_4_ERST_BEGIN_CLEAR_OPERATION 0x02
+#define EFI_ACPI_6_4_ERST_END_OPERATION 0x03
+#define EFI_ACPI_6_4_ERST_SET_RECORD_OFFSET 0x04
+#define EFI_ACPI_6_4_ERST_EXECUTE_OPERATION 0x05
+#define EFI_ACPI_6_4_ERST_CHECK_BUSY_STATUS 0x06
+#define EFI_ACPI_6_4_ERST_GET_COMMAND_STATUS 0x07
+#define EFI_ACPI_6_4_ERST_GET_RECORD_IDENTIFIER 0x08
+#define EFI_ACPI_6_4_ERST_SET_RECORD_IDENTIFIER 0x09
+#define EFI_ACPI_6_4_ERST_GET_RECORD_COUNT 0x0A
+#define EFI_ACPI_6_4_ERST_BEGIN_DUMMY_WRITE_OPERATION 0x0B
+#define EFI_ACPI_6_4_ERST_GET_ERROR_LOG_ADDRESS_RANGE 0x0D
+#define EFI_ACPI_6_4_ERST_GET_ERROR_LOG_ADDRESS_RANGE_LENGTH 0x0E
+#define EFI_ACPI_6_4_ERST_GET_ERROR_LOG_ADDRESS_RANGE_ATTRIBUTES 0x0F
+#define EFI_ACPI_6_4_ERST_GET_EXECUTE_OPERATION_TIMINGS 0x10
+
+///
+/// ERST Action Command Status
+///
+#define EFI_ACPI_6_4_ERST_STATUS_SUCCESS 0x00
+#define EFI_ACPI_6_4_ERST_STATUS_NOT_ENOUGH_SPACE 0x01
+#define EFI_ACPI_6_4_ERST_STATUS_HARDWARE_NOT_AVAILABLE 0x02
+#define EFI_ACPI_6_4_ERST_STATUS_FAILED 0x03
+#define EFI_ACPI_6_4_ERST_STATUS_RECORD_STORE_EMPTY 0x04
+#define EFI_ACPI_6_4_ERST_STATUS_RECORD_NOT_FOUND 0x05
+
+///
+/// ERST Serialization Instructions
+///
+#define EFI_ACPI_6_4_ERST_READ_REGISTER 0x00
+#define EFI_ACPI_6_4_ERST_READ_REGISTER_VALUE 0x01
+#define EFI_ACPI_6_4_ERST_WRITE_REGISTER 0x02
+#define EFI_ACPI_6_4_ERST_WRITE_REGISTER_VALUE 0x03
+#define EFI_ACPI_6_4_ERST_NOOP 0x04
+#define EFI_ACPI_6_4_ERST_LOAD_VAR1 0x05
+#define EFI_ACPI_6_4_ERST_LOAD_VAR2 0x06
+#define EFI_ACPI_6_4_ERST_STORE_VAR1 0x07
+#define EFI_ACPI_6_4_ERST_ADD 0x08
+#define EFI_ACPI_6_4_ERST_SUBTRACT 0x09
+#define EFI_ACPI_6_4_ERST_ADD_VALUE 0x0A
+#define EFI_ACPI_6_4_ERST_SUBTRACT_VALUE 0x0B
+#define EFI_ACPI_6_4_ERST_STALL 0x0C
+#define EFI_ACPI_6_4_ERST_STALL_WHILE_TRUE 0x0D
+#define EFI_ACPI_6_4_ERST_SKIP_NEXT_INSTRUCTION_IF_TRUE 0x0E
+#define EFI_ACPI_6_4_ERST_GOTO 0x0F
+#define EFI_ACPI_6_4_ERST_SET_SRC_ADDRESS_BASE 0x10
+#define EFI_ACPI_6_4_ERST_SET_DST_ADDRESS_BASE 0x11
+#define EFI_ACPI_6_4_ERST_MOVE_DATA 0x12
+
+///
+/// ERST Instruction Flags
+///
+#define EFI_ACPI_6_4_ERST_PRESERVE_REGISTER 0x01
+
+///
+/// ERST Serialization Instruction Entry
+///
+typedef struct {
+ UINT8 SerializationAction;
+ UINT8 Instruction;
+ UINT8 Flags;
+ UINT8 Reserved0;
+ EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE RegisterRegion;
+ UINT64 Value;
+ UINT64 Mask;
+} EFI_ACPI_6_4_ERST_SERIALIZATION_INSTRUCTION_ENTRY;
+
+///
+/// EINJ - Error Injection Table
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 InjectionHeaderSize;
+ UINT8 InjectionFlags;
+ UINT8 Reserved0[3];
+ UINT32 InjectionEntryCount;
+} EFI_ACPI_6_4_ERROR_INJECTION_TABLE_HEADER;
+
+///
+/// EINJ Version (as defined in ACPI 6.4 spec.)
+///
+#define EFI_ACPI_6_4_ERROR_INJECTION_TABLE_REVISION 0x01
+
+///
+/// EINJ Error Injection Actions
+///
+#define EFI_ACPI_6_4_EINJ_BEGIN_INJECTION_OPERATION 0x00
+#define EFI_ACPI_6_4_EINJ_GET_TRIGGER_ERROR_ACTION_TABLE 0x01
+#define EFI_ACPI_6_4_EINJ_SET_ERROR_TYPE 0x02
+#define EFI_ACPI_6_4_EINJ_GET_ERROR_TYPE 0x03
+#define EFI_ACPI_6_4_EINJ_END_OPERATION 0x04
+#define EFI_ACPI_6_4_EINJ_EXECUTE_OPERATION 0x05
+#define EFI_ACPI_6_4_EINJ_CHECK_BUSY_STATUS 0x06
+#define EFI_ACPI_6_4_EINJ_GET_COMMAND_STATUS 0x07
+#define EFI_ACPI_6_4_EINJ_TRIGGER_ERROR 0xFF
+
+///
+/// EINJ Action Command Status
+///
+#define EFI_ACPI_6_4_EINJ_STATUS_SUCCESS 0x00
+#define EFI_ACPI_6_4_EINJ_STATUS_UNKNOWN_FAILURE 0x01
+#define EFI_ACPI_6_4_EINJ_STATUS_INVALID_ACCESS 0x02
+
+///
+/// EINJ Error Type Definition
+///
+#define EFI_ACPI_6_4_EINJ_ERROR_PROCESSOR_CORRECTABLE (1 << 0)
+#define EFI_ACPI_6_4_EINJ_ERROR_PROCESSOR_UNCORRECTABLE_NONFATAL (1 << 1)
+#define EFI_ACPI_6_4_EINJ_ERROR_PROCESSOR_UNCORRECTABLE_FATAL (1 << 2)
+#define EFI_ACPI_6_4_EINJ_ERROR_MEMORY_CORRECTABLE (1 << 3)
+#define EFI_ACPI_6_4_EINJ_ERROR_MEMORY_UNCORRECTABLE_NONFATAL (1 << 4)
+#define EFI_ACPI_6_4_EINJ_ERROR_MEMORY_UNCORRECTABLE_FATAL (1 << 5)
+#define EFI_ACPI_6_4_EINJ_ERROR_PCI_EXPRESS_CORRECTABLE (1 << 6)
+#define EFI_ACPI_6_4_EINJ_ERROR_PCI_EXPRESS_UNCORRECTABLE_NONFATAL (1 << 7)
+#define EFI_ACPI_6_4_EINJ_ERROR_PCI_EXPRESS_UNCORRECTABLE_FATAL (1 << 8)
+#define EFI_ACPI_6_4_EINJ_ERROR_PLATFORM_CORRECTABLE (1 << 9)
+#define EFI_ACPI_6_4_EINJ_ERROR_PLATFORM_UNCORRECTABLE_NONFATAL (1 << 10)
+#define EFI_ACPI_6_4_EINJ_ERROR_PLATFORM_UNCORRECTABLE_FATAL (1 << 11)
+
+///
+/// EINJ Injection Instructions
+///
+#define EFI_ACPI_6_4_EINJ_READ_REGISTER 0x00
+#define EFI_ACPI_6_4_EINJ_READ_REGISTER_VALUE 0x01
+#define EFI_ACPI_6_4_EINJ_WRITE_REGISTER 0x02
+#define EFI_ACPI_6_4_EINJ_WRITE_REGISTER_VALUE 0x03
+#define EFI_ACPI_6_4_EINJ_NOOP 0x04
+
+///
+/// EINJ Instruction Flags
+///
+#define EFI_ACPI_6_4_EINJ_PRESERVE_REGISTER 0x01
+
+///
+/// EINJ Injection Instruction Entry
+///
+typedef struct {
+ UINT8 InjectionAction;
+ UINT8 Instruction;
+ UINT8 Flags;
+ UINT8 Reserved0;
+ EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE RegisterRegion;
+ UINT64 Value;
+ UINT64 Mask;
+} EFI_ACPI_6_4_EINJ_INJECTION_INSTRUCTION_ENTRY;
+
+///
+/// EINJ Trigger Action Table
+///
+typedef struct {
+ UINT32 HeaderSize;
+ UINT32 Revision;
+ UINT32 TableSize;
+ UINT32 EntryCount;
+} EFI_ACPI_6_4_EINJ_TRIGGER_ACTION_TABLE;
+
+///
+/// Platform Communications Channel Table (PCCT)
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 Flags;
+ UINT64 Reserved;
+} EFI_ACPI_6_4_PLATFORM_COMMUNICATION_CHANNEL_TABLE_HEADER;
+
+///
+/// PCCT Version (as defined in ACPI 6.4 spec.)
+///
+#define EFI_ACPI_6_4_PLATFORM_COMMUNICATION_CHANNEL_TABLE_REVISION 0x02
+
+///
+/// PCCT Global Flags
+///
+#define EFI_ACPI_6_4_PCCT_FLAGS_PLATFORM_INTERRUPT BIT0
+
+//
+// PCCT Subspace type
+//
+#define EFI_ACPI_6_4_PCCT_SUBSPACE_TYPE_GENERIC 0x00
+#define EFI_ACPI_6_4_PCCT_SUBSPACE_TYPE_1_HW_REDUCED_COMMUNICATIONS 0x01
+#define EFI_ACPI_6_4_PCCT_SUBSPACE_TYPE_2_HW_REDUCED_COMMUNICATIONS 0x02
+#define EFI_ACPI_6_4_PCCT_SUBSPACE_TYPE_3_EXTENDED_PCC 0x03
+#define EFI_ACPI_6_4_PCCT_SUBSPACE_TYPE_4_EXTENDED_PCC 0x04
+#define EFI_ACPI_6_4_PCCT_SUBSPACE_TYPE_5_HW_REGISTERS_COMMUNICATIONS 0x05
+
+///
+/// PCC Subspace Structure Header
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+} EFI_ACPI_6_4_PCCT_SUBSPACE_HEADER;
+
+///
+/// Generic Communications Subspace Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 Reserved[6];
+ UINT64 BaseAddress;
+ UINT64 AddressLength;
+ EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE DoorbellRegister;
+ UINT64 DoorbellPreserve;
+ UINT64 DoorbellWrite;
+ UINT32 NominalLatency;
+ UINT32 MaximumPeriodicAccessRate;
+ UINT16 MinimumRequestTurnaroundTime;
+} EFI_ACPI_6_4_PCCT_SUBSPACE_GENERIC;
+
+///
+/// Generic Communications Channel Shared Memory Region
+///
+
+typedef struct {
+ UINT8 Command;
+ UINT8 Reserved : 7;
+ UINT8 NotifyOnCompletion : 1;
+} EFI_ACPI_6_4_PCCT_GENERIC_SHARED_MEMORY_REGION_COMMAND;
+
+typedef struct {
+ UINT8 CommandComplete : 1;
+ UINT8 PlatformInterrupt : 1;
+ UINT8 Error : 1;
+ UINT8 PlatformNotification : 1;
+ UINT8 Reserved : 4;
+ UINT8 Reserved1;
+} EFI_ACPI_6_4_PCCT_GENERIC_SHARED_MEMORY_REGION_STATUS;
+
+typedef struct {
+ UINT32 Signature;
+ EFI_ACPI_6_4_PCCT_GENERIC_SHARED_MEMORY_REGION_COMMAND Command;
+ EFI_ACPI_6_4_PCCT_GENERIC_SHARED_MEMORY_REGION_STATUS Status;
+} EFI_ACPI_6_4_PCCT_GENERIC_SHARED_MEMORY_REGION_HEADER;
+
+#define EFI_ACPI_6_4_PCCT_SUBSPACE_PLATFORM_INTERRUPT_FLAGS_POLARITY BIT0
+#define EFI_ACPI_6_4_PCCT_SUBSPACE_PLATFORM_INTERRUPT_FLAGS_MODE BIT1
+
+///
+/// Type 1 HW-Reduced Communications Subspace Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT32 PlatformInterrupt;
+ UINT8 PlatformInterruptFlags;
+ UINT8 Reserved;
+ UINT64 BaseAddress;
+ UINT64 AddressLength;
+ EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE DoorbellRegister;
+ UINT64 DoorbellPreserve;
+ UINT64 DoorbellWrite;
+ UINT32 NominalLatency;
+ UINT32 MaximumPeriodicAccessRate;
+ UINT16 MinimumRequestTurnaroundTime;
+} EFI_ACPI_6_4_PCCT_SUBSPACE_1_HW_REDUCED_COMMUNICATIONS;
+
+///
+/// Type 2 HW-Reduced Communications Subspace Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT32 PlatformInterrupt;
+ UINT8 PlatformInterruptFlags;
+ UINT8 Reserved;
+ UINT64 BaseAddress;
+ UINT64 AddressLength;
+ EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE DoorbellRegister;
+ UINT64 DoorbellPreserve;
+ UINT64 DoorbellWrite;
+ UINT32 NominalLatency;
+ UINT32 MaximumPeriodicAccessRate;
+ UINT16 MinimumRequestTurnaroundTime;
+ EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE PlatformInterruptAckRegister;
+ UINT64 PlatformInterruptAckPreserve;
+ UINT64 PlatformInterruptAckWrite;
+} EFI_ACPI_6_4_PCCT_SUBSPACE_2_HW_REDUCED_COMMUNICATIONS;
+
+///
+/// Type 3 Extended PCC Subspace Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT32 PlatformInterrupt;
+ UINT8 PlatformInterruptFlags;
+ UINT8 Reserved;
+ UINT64 BaseAddress;
+ UINT32 AddressLength;
+ EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE DoorbellRegister;
+ UINT64 DoorbellPreserve;
+ UINT64 DoorbellWrite;
+ UINT32 NominalLatency;
+ UINT32 MaximumPeriodicAccessRate;
+ UINT32 MinimumRequestTurnaroundTime;
+ EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE PlatformInterruptAckRegister;
+ UINT64 PlatformInterruptAckPreserve;
+ UINT64 PlatformInterruptAckSet;
+ UINT8 Reserved1[8];
+ EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE CommandCompleteCheckRegister;
+ UINT64 CommandCompleteCheckMask;
+ EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE CommandCompleteUpdateRegister;
+ UINT64 CommandCompleteUpdatePreserve;
+ UINT64 CommandCompleteUpdateSet;
+ EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE ErrorStatusRegister;
+ UINT64 ErrorStatusMask;
+} EFI_ACPI_6_4_PCCT_SUBSPACE_3_EXTENDED_PCC;
+
+///
+/// Type 4 Extended PCC Subspace Structure
+///
+typedef EFI_ACPI_6_4_PCCT_SUBSPACE_3_EXTENDED_PCC EFI_ACPI_6_4_PCCT_SUBSPACE_4_EXTENDED_PCC;
+
+#define EFI_ACPI_6_4_PCCT_MASTER_SLAVE_COMMUNICATIONS_CHANNEL_FLAGS_NOTIFY_ON_COMPLETION BIT0
+
+typedef struct {
+ UINT32 Signature;
+ UINT32 Flags;
+ UINT32 Length;
+ UINT32 Command;
+} EFI_ACPI_6_4_PCCT_EXTENDED_PCC_SHARED_MEMORY_REGION_HEADER;
+
+///
+/// Type 5 HW Registers based Communications Subspace Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Version;
+ UINT64 BaseAddress;
+ UINT64 SharedMemoryRangeLength;
+ EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE DoorbellRegister;
+ UINT64 DoorbellPreserve;
+ UINT64 DoorbellWrite;
+ EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE CommandCompleteCheckRegister;
+ UINT64 CommandCompleteCheckMask;
+ EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE ErrorStatusRegister;
+ UINT64 ErrorStatusMask;
+ UINT32 NominalLatency;
+ UINT32 MinimumRequestTurnaroundTime;
+} EFI_ACPI_6_4_PCCT_SUBSPACE_5_HW_REGISTERS_COMMUNICATIONS;
+
+///
+/// Reduced PCC Subspace Shared Memory Region
+///
+typedef struct {
+ UINT32 Signature;
+ // UINT8 CommunicationSubspace[];
+} EFI_6_4_PCCT_REDUCED_PCC_SUBSPACE_SHARED_MEMORY_REGION;
+
+///
+/// Platform Debug Trigger Table (PDTT)
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT8 TriggerCount;
+ UINT8 Reserved[3];
+ UINT32 TriggerIdentifierArrayOffset;
+} EFI_ACPI_6_4_PLATFORM_DEBUG_TRIGGER_TABLE_HEADER;
+
+///
+/// PDTT Revision (as defined in ACPI 6.4 spec.)
+///
+#define EFI_ACPI_6_4_PLATFORM_DEBUG_TRIGGER_TABLE_REVISION 0x00
+
+///
+/// PDTT Platform Communication Channel Identifier Structure
+///
+typedef struct {
+ UINT16 SubChannelIdentifer : 8;
+ UINT16 Runtime : 1;
+ UINT16 WaitForCompletion : 1;
+ UINT16 TriggerOrder : 1;
+ UINT16 Reserved : 5;
+} EFI_ACPI_6_4_PDTT_PCC_IDENTIFIER;
+
+///
+/// PCC Commands Codes used by Platform Debug Trigger Table
+///
+#define EFI_ACPI_6_4_PDTT_PCC_COMMAND_DOORBELL_ONLY 0x00
+#define EFI_ACPI_6_4_PDTT_PCC_COMMAND_VENDOR_SPECIFIC 0x01
+
+///
+/// PDTT Platform Communication Channel
+///
+typedef EFI_ACPI_6_4_PCCT_GENERIC_SHARED_MEMORY_REGION_HEADER EFI_ACPI_6_4_PDTT_PCC;
+
+///
+/// Processor Properties Topology Table (PPTT)
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+} EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER;
+
+///
+/// PPTT Revision (as defined in ACPI 6.4 spec.)
+///
+#define EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION 0x03
+
+///
+/// PPTT types
+///
+#define EFI_ACPI_6_4_PPTT_TYPE_PROCESSOR 0x00
+#define EFI_ACPI_6_4_PPTT_TYPE_CACHE 0x01
+
+///
+/// PPTT Structure Header
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 Reserved[2];
+} EFI_ACPI_6_4_PPTT_STRUCTURE_HEADER;
+
+///
+/// For PPTT struct processor flags
+///
+#define EFI_ACPI_6_4_PPTT_PACKAGE_NOT_PHYSICAL 0x0
+#define EFI_ACPI_6_4_PPTT_PACKAGE_PHYSICAL 0x1
+#define EFI_ACPI_6_4_PPTT_PROCESSOR_ID_INVALID 0x0
+#define EFI_ACPI_6_4_PPTT_PROCESSOR_ID_VALID 0x1
+#define EFI_ACPI_6_4_PPTT_PROCESSOR_IS_NOT_THREAD 0x0
+#define EFI_ACPI_6_4_PPTT_PROCESSOR_IS_THREAD 0x1
+#define EFI_ACPI_6_4_PPTT_NODE_IS_NOT_LEAF 0x0
+#define EFI_ACPI_6_4_PPTT_NODE_IS_LEAF 0x1
+#define EFI_ACPI_6_4_PPTT_IMPLEMENTATION_NOT_IDENTICAL 0x0
+#define EFI_ACPI_6_4_PPTT_IMPLEMENTATION_IDENTICAL 0x1
+
+///
+/// Processor hierarchy node structure flags
+///
+typedef struct {
+ UINT32 PhysicalPackage : 1;
+ UINT32 AcpiProcessorIdValid : 1;
+ UINT32 ProcessorIsAThread : 1;
+ UINT32 NodeIsALeaf : 1;
+ UINT32 IdenticalImplementation : 1;
+ UINT32 Reserved : 27;
+} EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR_FLAGS;
+
+///
+/// Processor hierarchy node structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 Reserved[2];
+ EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR_FLAGS Flags;
+ UINT32 Parent;
+ UINT32 AcpiProcessorId;
+ UINT32 NumberOfPrivateResources;
+} EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR;
+
+///
+/// For PPTT struct cache flags
+///
+#define EFI_ACPI_6_4_PPTT_CACHE_SIZE_INVALID 0x0
+#define EFI_ACPI_6_4_PPTT_CACHE_SIZE_VALID 0x1
+#define EFI_ACPI_6_4_PPTT_NUMBER_OF_SETS_INVALID 0x0
+#define EFI_ACPI_6_4_PPTT_NUMBER_OF_SETS_VALID 0x1
+#define EFI_ACPI_6_4_PPTT_ASSOCIATIVITY_INVALID 0x0
+#define EFI_ACPI_6_4_PPTT_ASSOCIATIVITY_VALID 0x1
+#define EFI_ACPI_6_4_PPTT_ALLOCATION_TYPE_INVALID 0x0
+#define EFI_ACPI_6_4_PPTT_ALLOCATION_TYPE_VALID 0x1
+#define EFI_ACPI_6_4_PPTT_CACHE_TYPE_INVALID 0x0
+#define EFI_ACPI_6_4_PPTT_CACHE_TYPE_VALID 0x1
+#define EFI_ACPI_6_4_PPTT_WRITE_POLICY_INVALID 0x0
+#define EFI_ACPI_6_4_PPTT_WRITE_POLICY_VALID 0x1
+#define EFI_ACPI_6_4_PPTT_LINE_SIZE_INVALID 0x0
+#define EFI_ACPI_6_4_PPTT_LINE_SIZE_VALID 0x1
+#define EFI_ACPI_6_4_PPTT_CACHE_ID_INVALID 0x0
+#define EFI_ACPI_6_4_PPTT_CACHE_ID_VALID 0x1
+
+///
+/// Cache Type Structure flags
+///
+typedef struct {
+ UINT32 SizePropertyValid : 1;
+ UINT32 NumberOfSetsValid : 1;
+ UINT32 AssociativityValid : 1;
+ UINT32 AllocationTypeValid : 1;
+ UINT32 CacheTypeValid : 1;
+ UINT32 WritePolicyValid : 1;
+ UINT32 LineSizeValid : 1;
+ UINT32 CacheIdValid : 1;
+ UINT32 Reserved : 24;
+} EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE_FLAGS;
+
+///
+/// For cache attributes
+///
+#define EFI_ACPI_6_4_CACHE_ATTRIBUTES_ALLOCATION_READ 0x0
+#define EFI_ACPI_6_4_CACHE_ATTRIBUTES_ALLOCATION_WRITE 0x1
+#define EFI_ACPI_6_4_CACHE_ATTRIBUTES_ALLOCATION_READ_WRITE 0x2
+#define EFI_ACPI_6_4_CACHE_ATTRIBUTES_CACHE_TYPE_DATA 0x0
+#define EFI_ACPI_6_4_CACHE_ATTRIBUTES_CACHE_TYPE_INSTRUCTION 0x1
+#define EFI_ACPI_6_4_CACHE_ATTRIBUTES_CACHE_TYPE_UNIFIED 0x2
+#define EFI_ACPI_6_4_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK 0x0
+#define EFI_ACPI_6_4_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_THROUGH 0x1
+
+///
+/// Cache Type Structure cache attributes
+///
+typedef struct {
+ UINT8 AllocationType : 2;
+ UINT8 CacheType : 2;
+ UINT8 WritePolicy : 1;
+ UINT8 Reserved : 3;
+} EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE_ATTRIBUTES;
+
+///
+/// Cache Type Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 Reserved[2];
+ EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE_FLAGS Flags;
+ UINT32 NextLevelOfCache;
+ UINT32 Size;
+ UINT32 NumberOfSets;
+ UINT8 Associativity;
+ EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE_ATTRIBUTES Attributes;
+ UINT16 LineSize;
+ UINT32 CacheId;
+} EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE;
+
+///
+/// Platform Health Assessment Table (PHAT) Format
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ // UINT8 PlatformTelemetryRecords[];
+} EFI_ACPI_6_4_PLATFORM_HEALTH_ASSESSMENT_TABLE;
+
+#define EFI_ACPI_6_4_PLATFORM_HEALTH_ASSESSMENT_TABLE_REVISION 0x01
+
+///
+/// PHAT Record Format
+///
+typedef struct {
+ UINT16 PlatformHealthAssessmentRecordType;
+ UINT16 RecordLength;
+ UINT8 Revision;
+ // UINT8 Data[];
+} EFI_ACPI_6_4_PHAT_RECORD;
+
+///
+/// PHAT Record Type Format
+///
+#define EFI_ACPI_6_4_PHAT_RECORD_TYPE_FIRMWARE_VERSION_DATA_RECORD 0x0000
+#define EFI_ACPI_6_4_PHAT_RECORD_TYPE_FIRMWARE_HEALTH_DATA_RECORD 0x0001
+
+///
+/// PHAT Version Element
+///
+typedef struct {
+ GUID ComponentId;
+ UINT64 VersionValue;
+ UINT32 ProducerId;
+} EFI_ACPI_6_4_PHAT_VERSION_ELEMENT;
+
+///
+/// PHAT Firmware Version Data Record
+///
+typedef struct {
+ UINT16 PlatformRecordType;
+ UINT16 RecordLength;
+ UINT8 Revision;
+ UINT8 Reserved[3];
+ UINT32 RecordCount;
+ // UINT8 PhatVersionElement[];
+} EFI_ACPI_6_4_PHAT_FIRMWARE_VERISON_DATA_RECORD;
+
+#define EFI_ACPI_6_4_PHAT_FIRMWARE_VERSION_DATA_RECORD_REVISION 0x01
+
+///
+/// Firmware Health Data Record Structure
+///
+typedef struct {
+ UINT16 PlatformRecordType;
+ UINT16 RecordLength;
+ UINT8 Revision;
+ UINT16 Reserved;
+ UINT8 AmHealthy;
+ GUID DeviceSignature;
+ UINT32 DeviceSpecificDataOffset;
+ // UINT8 DevicePath[];
+ // UINT8 DeviceSpecificData[];
+} EFI_ACPI_6_4_PHAT_FIRMWARE_HEALTH_DATA_RECORD_STRUCTURE;
+
+#define EFI_ACPI_6_4_PHAT_FIRMWARE_HEALTH_DATA_RECORD_REVISION 0x01
+
+///
+/// Firmware Health Data Record device health state
+///
+#define EFI_ACPI_6_4_PHAT_FIRMWARE_HEALTH_DATA_RECORD_ERRORS_FOUND 0x00
+#define EFI_ACPI_6_4_PHAT_FIRMWARE_HEALTH_DATA_RECORD_NO_ERRORS_FOUND 0x01
+#define EFI_ACPI_6_4_PHAT_FIRMWARE_HEALTH_DATA_RECORD_UNKNOWN 0x02
+#define EFI_ACPI_6_4_PHAT_FIRMWARE_HEALTH_DATA_RECORD_ADVISORY 0x03
+
+//
+// Known table signatures
+//
+
+///
+/// "RSD PTR " Root System Description Pointer
+///
+#define EFI_ACPI_6_4_ROOT_SYSTEM_DESCRIPTION_POINTER_SIGNATURE SIGNATURE_64('R', 'S', 'D', ' ', 'P', 'T', 'R', ' ')
+
+///
+/// "APIC" Multiple APIC Description Table
+///
+#define EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('A', 'P', 'I', 'C')
+
+///
+/// "APMT" Arm Performance Monitoring Unit Table
+///
+#define EFI_ACPI_6_4_ARM_PERFORMANCE_MONITORING_UNIT_TABLE_SIGNATURE SIGNATURE_32('A', 'P', 'M', 'T')
+
+///
+/// "BERT" Boot Error Record Table
+///
+#define EFI_ACPI_6_4_BOOT_ERROR_RECORD_TABLE_SIGNATURE SIGNATURE_32('B', 'E', 'R', 'T')
+
+///
+/// "BGRT" Boot Graphics Resource Table
+///
+#define EFI_ACPI_6_4_BOOT_GRAPHICS_RESOURCE_TABLE_SIGNATURE SIGNATURE_32('B', 'G', 'R', 'T')
+
+///
+/// "CDIT" Component Distance Information Table
+///
+#define EFI_ACPI_6_4_COMPONENT_DISTANCE_INFORMATION_TABLE_SIGNATURE SIGNATURE_32('C', 'D', 'I', 'T')
+
+///
+/// "CPEP" Corrected Platform Error Polling Table
+///
+#define EFI_ACPI_6_4_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_SIGNATURE SIGNATURE_32('C', 'P', 'E', 'P')
+
+///
+/// "CRAT" Component Resource Attribute Table
+///
+#define EFI_ACPI_6_4_COMPONENT_RESOURCE_ATTRIBUTE_TABLE_SIGNATURE SIGNATURE_32('C', 'R', 'A', 'T')
+
+///
+/// "DSDT" Differentiated System Description Table
+///
+#define EFI_ACPI_6_4_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('D', 'S', 'D', 'T')
+
+///
+/// "ECDT" Embedded Controller Boot Resources Table
+///
+#define EFI_ACPI_6_4_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE_SIGNATURE SIGNATURE_32('E', 'C', 'D', 'T')
+
+///
+/// "EINJ" Error Injection Table
+///
+#define EFI_ACPI_6_4_ERROR_INJECTION_TABLE_SIGNATURE SIGNATURE_32('E', 'I', 'N', 'J')
+
+///
+/// "ERST" Error Record Serialization Table
+///
+#define EFI_ACPI_6_4_ERROR_RECORD_SERIALIZATION_TABLE_SIGNATURE SIGNATURE_32('E', 'R', 'S', 'T')
+
+///
+/// "FACP" Fixed ACPI Description Table
+///
+#define EFI_ACPI_6_4_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('F', 'A', 'C', 'P')
+
+///
+/// "FACS" Firmware ACPI Control Structure
+///
+#define EFI_ACPI_6_4_FIRMWARE_ACPI_CONTROL_STRUCTURE_SIGNATURE SIGNATURE_32('F', 'A', 'C', 'S')
+
+///
+/// "FPDT" Firmware Performance Data Table
+///
+#define EFI_ACPI_6_4_FIRMWARE_PERFORMANCE_DATA_TABLE_SIGNATURE SIGNATURE_32('F', 'P', 'D', 'T')
+
+///
+/// "GTDT" Generic Timer Description Table
+///
+#define EFI_ACPI_6_4_GENERIC_TIMER_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('G', 'T', 'D', 'T')
+
+///
+/// "HEST" Hardware Error Source Table
+///
+#define EFI_ACPI_6_4_HARDWARE_ERROR_SOURCE_TABLE_SIGNATURE SIGNATURE_32('H', 'E', 'S', 'T')
+
+///
+/// "HMAT" Heterogeneous Memory Attribute Table
+///
+#define EFI_ACPI_6_4_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_SIGNATURE SIGNATURE_32('H', 'M', 'A', 'T')
+
+///
+/// "MPST" Memory Power State Table
+///
+#define EFI_ACPI_6_4_MEMORY_POWER_STATE_TABLE_SIGNATURE SIGNATURE_32('M', 'P', 'S', 'T')
+
+///
+/// "MSCT" Maximum System Characteristics Table
+///
+#define EFI_ACPI_6_4_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_SIGNATURE SIGNATURE_32('M', 'S', 'C', 'T')
+
+///
+/// "NFIT" NVDIMM Firmware Interface Table
+///
+#define EFI_ACPI_6_4_NVDIMM_FIRMWARE_INTERFACE_TABLE_STRUCTURE_SIGNATURE SIGNATURE_32('N', 'F', 'I', 'T')
+
+///
+/// "PDTT" Platform Debug Trigger Table
+///
+#define EFI_ACPI_6_4_PLATFORM_DEBUG_TRIGGER_TABLE_STRUCTURE_SIGNATURE SIGNATURE_32('P', 'D', 'T', 'T')
+
+///
+/// "PMTT" Platform Memory Topology Table
+///
+#define EFI_ACPI_6_4_PLATFORM_MEMORY_TOPOLOGY_TABLE_SIGNATURE SIGNATURE_32('P', 'M', 'T', 'T')
+
+///
+/// "PPTT" Processor Properties Topology Table
+///
+#define EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE SIGNATURE_32('P', 'P', 'T', 'T')
+
+///
+/// "PSDT" Persistent System Description Table
+///
+#define EFI_ACPI_6_4_PERSISTENT_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('P', 'S', 'D', 'T')
+
+///
+/// "RASF" ACPI RAS Feature Table
+///
+#define EFI_ACPI_6_4_ACPI_RAS_FEATURE_TABLE_SIGNATURE SIGNATURE_32('R', 'A', 'S', 'F')
+
+///
+/// "RSDT" Root System Description Table
+///
+#define EFI_ACPI_6_4_ROOT_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('R', 'S', 'D', 'T')
+
+///
+/// "SBST" Smart Battery Specification Table
+///
+#define EFI_ACPI_6_4_SMART_BATTERY_SPECIFICATION_TABLE_SIGNATURE SIGNATURE_32('S', 'B', 'S', 'T')
+
+///
+/// "SDEV" Secure DEVices Table
+///
+#define EFI_ACPI_6_4_SECURE_DEVICES_TABLE_SIGNATURE SIGNATURE_32('S', 'D', 'E', 'V')
+
+///
+/// "SLIT" System Locality Information Table
+///
+#define EFI_ACPI_6_4_SYSTEM_LOCALITY_INFORMATION_TABLE_SIGNATURE SIGNATURE_32('S', 'L', 'I', 'T')
+
+///
+/// "SRAT" System Resource Affinity Table
+///
+#define EFI_ACPI_6_4_SYSTEM_RESOURCE_AFFINITY_TABLE_SIGNATURE SIGNATURE_32('S', 'R', 'A', 'T')
+
+///
+/// "SSDT" Secondary System Description Table
+///
+#define EFI_ACPI_6_4_SECONDARY_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('S', 'S', 'D', 'T')
+
+///
+/// "XSDT" Extended System Description Table
+///
+#define EFI_ACPI_6_4_EXTENDED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('X', 'S', 'D', 'T')
+
+///
+/// "BOOT" MS Simple Boot Spec
+///
+#define EFI_ACPI_6_4_SIMPLE_BOOT_FLAG_TABLE_SIGNATURE SIGNATURE_32('B', 'O', 'O', 'T')
+
+///
+/// "CSRT" MS Core System Resource Table
+///
+#define EFI_ACPI_6_4_CORE_SYSTEM_RESOURCE_TABLE_SIGNATURE SIGNATURE_32('C', 'S', 'R', 'T')
+
+///
+/// "DBG2" MS Debug Port 2 Spec
+///
+#define EFI_ACPI_6_4_DEBUG_PORT_2_TABLE_SIGNATURE SIGNATURE_32('D', 'B', 'G', '2')
+
+///
+/// "DBGP" MS Debug Port Spec
+///
+#define EFI_ACPI_6_4_DEBUG_PORT_TABLE_SIGNATURE SIGNATURE_32('D', 'B', 'G', 'P')
+
+///
+/// "DMAR" DMA Remapping Table
+///
+#define EFI_ACPI_6_4_DMA_REMAPPING_TABLE_SIGNATURE SIGNATURE_32('D', 'M', 'A', 'R')
+
+///
+/// "DRTM" Dynamic Root of Trust for Measurement Table
+///
+#define EFI_ACPI_6_4_DYNAMIC_ROOT_OF_TRUST_FOR_MEASUREMENT_TABLE_SIGNATURE SIGNATURE_32('D', 'R', 'T', 'M')
+
+///
+/// "ETDT" Event Timer Description Table
+///
+#define EFI_ACPI_6_4_EVENT_TIMER_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('E', 'T', 'D', 'T')
+
+///
+/// "HPET" IA-PC High Precision Event Timer Table
+///
+#define EFI_ACPI_6_4_HIGH_PRECISION_EVENT_TIMER_TABLE_SIGNATURE SIGNATURE_32('H', 'P', 'E', 'T')
+
+///
+/// "iBFT" iSCSI Boot Firmware Table
+///
+#define EFI_ACPI_6_4_ISCSI_BOOT_FIRMWARE_TABLE_SIGNATURE SIGNATURE_32('i', 'B', 'F', 'T')
+
+///
+/// "IORT" I/O Remapping Table
+///
+#define EFI_ACPI_6_4_IO_REMAPPING_TABLE_SIGNATURE SIGNATURE_32('I', 'O', 'R', 'T')
+
+///
+/// "IVRS" I/O Virtualization Reporting Structure
+///
+#define EFI_ACPI_6_4_IO_VIRTUALIZATION_REPORTING_STRUCTURE_SIGNATURE SIGNATURE_32('I', 'V', 'R', 'S')
+
+///
+/// "LPIT" Low Power Idle Table
+///
+#define EFI_ACPI_6_4_LOW_POWER_IDLE_TABLE_STRUCTURE_SIGNATURE SIGNATURE_32('L', 'P', 'I', 'T')
+
+///
+/// "MCFG" PCI Express Memory Mapped Configuration Space Base Address Description Table
+///
+#define EFI_ACPI_6_4_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('M', 'C', 'F', 'G')
+
+///
+/// "MCHI" Management Controller Host Interface Table
+///
+#define EFI_ACPI_6_4_MANAGEMENT_CONTROLLER_HOST_INTERFACE_TABLE_SIGNATURE SIGNATURE_32('M', 'C', 'H', 'I')
+
+///
+/// "MSDM" MS Data Management Table
+///
+#define EFI_ACPI_6_4_DATA_MANAGEMENT_TABLE_SIGNATURE SIGNATURE_32('M', 'S', 'D', 'M')
+
+///
+/// "PCCT" Platform Communications Channel Table
+///
+#define EFI_ACPI_6_4_PLATFORM_COMMUNICATIONS_CHANNEL_TABLE_SIGNATURE SIGNATURE_32('P', 'C', 'C', 'T')
+
+///
+/// "PHAT" Platform Health Assessment Table
+///
+#define EFI_ACPI_6_4_PLATFORM_HEALTH_ASSESSMENT_TABLE_SIGNATURE SIGNATURE_32('P', 'H', 'A', 'T')
+
+///
+/// "SDEI" Software Delegated Exceptions Interface Table
+///
+#define EFI_ACPI_6_4_SOFTWARE_DELEGATED_EXCEPTIONS_INTERFACE_TABLE_SIGNATURE SIGNATURE_32('S', 'D', 'E', 'I')
+
+///
+/// "SLIC" MS Software Licensing Table Specification
+///
+#define EFI_ACPI_6_4_SOFTWARE_LICENSING_TABLE_SIGNATURE SIGNATURE_32('S', 'L', 'I', 'C')
+
+///
+/// "SPCR" Serial Port Concole Redirection Table
+///
+#define EFI_ACPI_6_4_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE SIGNATURE_32('S', 'P', 'C', 'R')
+
+///
+/// "SPMI" Server Platform Management Interface Table
+///
+#define EFI_ACPI_6_4_SERVER_PLATFORM_MANAGEMENT_INTERFACE_TABLE_SIGNATURE SIGNATURE_32('S', 'P', 'M', 'I')
+
+///
+/// "STAO" _STA Override Table
+///
+#define EFI_ACPI_6_4_STA_OVERRIDE_TABLE_SIGNATURE SIGNATURE_32('S', 'T', 'A', 'O')
+
+///
+/// "TCPA" Trusted Computing Platform Alliance Capabilities Table
+///
+#define EFI_ACPI_6_4_TRUSTED_COMPUTING_PLATFORM_ALLIANCE_CAPABILITIES_TABLE_SIGNATURE SIGNATURE_32('T', 'C', 'P', 'A')
+
+///
+/// "TPM2" Trusted Computing Platform 1 Table
+///
+#define EFI_ACPI_6_4_TRUSTED_COMPUTING_PLATFORM_2_TABLE_SIGNATURE SIGNATURE_32('T', 'P', 'M', '2')
+
+///
+/// "UEFI" UEFI ACPI Data Table
+///
+#define EFI_ACPI_6_4_UEFI_ACPI_DATA_TABLE_SIGNATURE SIGNATURE_32('U', 'E', 'F', 'I')
+
+///
+/// "WAET" Windows ACPI Emulated Devices Table
+///
+#define EFI_ACPI_6_4_WINDOWS_ACPI_EMULATED_DEVICES_TABLE_SIGNATURE SIGNATURE_32('W', 'A', 'E', 'T')
+
+///
+/// "WDAT" Watchdog Action Table
+///
+#define EFI_ACPI_6_4_WATCHDOG_ACTION_TABLE_SIGNATURE SIGNATURE_32('W', 'D', 'A', 'T')
+
+///
+/// "WDRT" Watchdog Resource Table
+///
+#define EFI_ACPI_6_4_WATCHDOG_RESOURCE_TABLE_SIGNATURE SIGNATURE_32('W', 'D', 'R', 'T')
+
+///
+/// "WPBT" MS Platform Binary Table
+///
+#define EFI_ACPI_6_4_PLATFORM_BINARY_TABLE_SIGNATURE SIGNATURE_32('W', 'P', 'B', 'T')
+
+///
+/// "WSMT" Windows SMM Security Mitigation Table
+///
+#define EFI_ACPI_6_4_WINDOWS_SMM_SECURITY_MITIGATION_TABLE_SIGNATURE SIGNATURE_32('W', 'S', 'M', 'T')
+
+///
+/// "XENV" Xen Project Table
+///
+#define EFI_ACPI_6_4_XEN_PROJECT_TABLE_SIGNATURE SIGNATURE_32('X', 'E', 'N', 'V')
+
+#pragma pack()
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/Acpi65.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/Acpi65.h
new file mode 100644
index 0000000000..67b17701d5
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/Acpi65.h
@@ -0,0 +1,3256 @@
+/** @file
+ ACPI 6.5 definitions from the ACPI Specification Revision 6.5 Aug, 2022.
+
+ Copyright (c) 2017 - 2022, Intel Corporation. All rights reserved.
+ Copyright (c) 2019 - 2021, ARM Ltd. All rights reserved.
+ Copyright (c) 2023, Loongson Technology Corporation Limited. All rights reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef ACPI_6_5_H_
+#define ACPI_6_5_H_
+
+#include
+
+//
+// Ensure proper structure formats
+//
+#pragma pack(1)
+
+///
+/// ACPI 6.5 Generic Address Space definition
+///
+typedef struct {
+ UINT8 AddressSpaceId;
+ UINT8 RegisterBitWidth;
+ UINT8 RegisterBitOffset;
+ UINT8 AccessSize;
+ UINT64 Address;
+} EFI_ACPI_6_5_GENERIC_ADDRESS_STRUCTURE;
+
+//
+// Generic Address Space Address IDs
+//
+#define EFI_ACPI_6_5_SYSTEM_MEMORY 0x00
+#define EFI_ACPI_6_5_SYSTEM_IO 0x01
+#define EFI_ACPI_6_5_PCI_CONFIGURATION_SPACE 0x02
+#define EFI_ACPI_6_5_EMBEDDED_CONTROLLER 0x03
+#define EFI_ACPI_6_5_SMBUS 0x04
+#define EFI_ACPI_6_5_SYSTEM_CMOS 0x05
+#define EFI_ACPI_6_5_PCI_BAR_TARGET 0x06
+#define EFI_ACPI_6_5_IPMI 0x07
+#define EFI_ACPI_6_5_GENERAL_PURPOSE_IO 0x08
+#define EFI_ACPI_6_5_GENERIC_SERIAL_BUS 0x09
+#define EFI_ACPI_6_5_PLATFORM_COMMUNICATION_CHANNEL 0x0A
+#define EFI_ACPI_6_5_FUNCTIONAL_FIXED_HARDWARE 0x7F
+
+//
+// Generic Address Space Access Sizes
+//
+#define EFI_ACPI_6_5_UNDEFINED 0
+#define EFI_ACPI_6_5_BYTE 1
+#define EFI_ACPI_6_5_WORD 2
+#define EFI_ACPI_6_5_DWORD 3
+#define EFI_ACPI_6_5_QWORD 4
+
+//
+// ACPI 6.5 table structures
+//
+
+///
+/// Root System Description Pointer Structure
+///
+typedef struct {
+ UINT64 Signature;
+ UINT8 Checksum;
+ UINT8 OemId[6];
+ UINT8 Revision;
+ UINT32 RsdtAddress;
+ UINT32 Length;
+ UINT64 XsdtAddress;
+ UINT8 ExtendedChecksum;
+ UINT8 Reserved[3];
+} EFI_ACPI_6_5_ROOT_SYSTEM_DESCRIPTION_POINTER;
+
+///
+/// RSD_PTR Revision (as defined in ACPI 6.5 spec.)
+///
+#define EFI_ACPI_6_5_ROOT_SYSTEM_DESCRIPTION_POINTER_REVISION 0x02 ///< ACPISpec (Revision 6.5) says current value is 2
+
+///
+/// Common table header, this prefaces all ACPI tables, including FACS, but
+/// excluding the RSD PTR structure
+///
+typedef struct {
+ UINT32 Signature;
+ UINT32 Length;
+} EFI_ACPI_6_5_COMMON_HEADER;
+
+//
+// Root System Description Table
+// No definition needed as it is a common description table header, the same with
+// EFI_ACPI_DESCRIPTION_HEADER, followed by a variable number of UINT32 table pointers.
+//
+
+///
+/// RSDT Revision (as defined in ACPI 6.5 spec.)
+///
+#define EFI_ACPI_6_5_ROOT_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01
+
+//
+// Extended System Description Table
+// No definition needed as it is a common description table header, the same with
+// EFI_ACPI_DESCRIPTION_HEADER, followed by a variable number of UINT64 table pointers.
+//
+
+///
+/// XSDT Revision (as defined in ACPI 6.5 spec.)
+///
+#define EFI_ACPI_6_5_EXTENDED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01
+
+///
+/// Fixed ACPI Description Table Structure (FADT)
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 FirmwareCtrl;
+ UINT32 Dsdt;
+ UINT8 Reserved0;
+ UINT8 PreferredPmProfile;
+ UINT16 SciInt;
+ UINT32 SmiCmd;
+ UINT8 AcpiEnable;
+ UINT8 AcpiDisable;
+ UINT8 S4BiosReq;
+ UINT8 PstateCnt;
+ UINT32 Pm1aEvtBlk;
+ UINT32 Pm1bEvtBlk;
+ UINT32 Pm1aCntBlk;
+ UINT32 Pm1bCntBlk;
+ UINT32 Pm2CntBlk;
+ UINT32 PmTmrBlk;
+ UINT32 Gpe0Blk;
+ UINT32 Gpe1Blk;
+ UINT8 Pm1EvtLen;
+ UINT8 Pm1CntLen;
+ UINT8 Pm2CntLen;
+ UINT8 PmTmrLen;
+ UINT8 Gpe0BlkLen;
+ UINT8 Gpe1BlkLen;
+ UINT8 Gpe1Base;
+ UINT8 CstCnt;
+ UINT16 PLvl2Lat;
+ UINT16 PLvl3Lat;
+ UINT16 FlushSize;
+ UINT16 FlushStride;
+ UINT8 DutyOffset;
+ UINT8 DutyWidth;
+ UINT8 DayAlrm;
+ UINT8 MonAlrm;
+ UINT8 Century;
+ UINT16 IaPcBootArch;
+ UINT8 Reserved1;
+ UINT32 Flags;
+ EFI_ACPI_6_5_GENERIC_ADDRESS_STRUCTURE ResetReg;
+ UINT8 ResetValue;
+ UINT16 ArmBootArch;
+ UINT8 MinorVersion;
+ UINT64 XFirmwareCtrl;
+ UINT64 XDsdt;
+ EFI_ACPI_6_5_GENERIC_ADDRESS_STRUCTURE XPm1aEvtBlk;
+ EFI_ACPI_6_5_GENERIC_ADDRESS_STRUCTURE XPm1bEvtBlk;
+ EFI_ACPI_6_5_GENERIC_ADDRESS_STRUCTURE XPm1aCntBlk;
+ EFI_ACPI_6_5_GENERIC_ADDRESS_STRUCTURE XPm1bCntBlk;
+ EFI_ACPI_6_5_GENERIC_ADDRESS_STRUCTURE XPm2CntBlk;
+ EFI_ACPI_6_5_GENERIC_ADDRESS_STRUCTURE XPmTmrBlk;
+ EFI_ACPI_6_5_GENERIC_ADDRESS_STRUCTURE XGpe0Blk;
+ EFI_ACPI_6_5_GENERIC_ADDRESS_STRUCTURE XGpe1Blk;
+ EFI_ACPI_6_5_GENERIC_ADDRESS_STRUCTURE SleepControlReg;
+ EFI_ACPI_6_5_GENERIC_ADDRESS_STRUCTURE SleepStatusReg;
+ UINT64 HypervisorVendorIdentity;
+} EFI_ACPI_6_5_FIXED_ACPI_DESCRIPTION_TABLE;
+
+///
+/// FADT Version (as defined in ACPI 6.5 spec.)
+///
+#define EFI_ACPI_6_5_FIXED_ACPI_DESCRIPTION_TABLE_REVISION 0x06
+#define EFI_ACPI_6_5_FIXED_ACPI_DESCRIPTION_TABLE_MINOR_REVISION 0x05
+
+//
+// Fixed ACPI Description Table Preferred Power Management Profile
+//
+#define EFI_ACPI_6_5_PM_PROFILE_UNSPECIFIED 0
+#define EFI_ACPI_6_5_PM_PROFILE_DESKTOP 1
+#define EFI_ACPI_6_5_PM_PROFILE_MOBILE 2
+#define EFI_ACPI_6_5_PM_PROFILE_WORKSTATION 3
+#define EFI_ACPI_6_5_PM_PROFILE_ENTERPRISE_SERVER 4
+#define EFI_ACPI_6_5_PM_PROFILE_SOHO_SERVER 5
+#define EFI_ACPI_6_5_PM_PROFILE_APPLIANCE_PC 6
+#define EFI_ACPI_6_5_PM_PROFILE_PERFORMANCE_SERVER 7
+#define EFI_ACPI_6_5_PM_PROFILE_TABLET 8
+
+//
+// Fixed ACPI Description Table Boot Architecture Flags
+// All other bits are reserved and must be set to 0.
+//
+#define EFI_ACPI_6_5_LEGACY_DEVICES BIT0
+#define EFI_ACPI_6_5_8042 BIT1
+#define EFI_ACPI_6_5_VGA_NOT_PRESENT BIT2
+#define EFI_ACPI_6_5_MSI_NOT_SUPPORTED BIT3
+#define EFI_ACPI_6_5_PCIE_ASPM_CONTROLS BIT4
+#define EFI_ACPI_6_5_CMOS_RTC_NOT_PRESENT BIT5
+
+//
+// Fixed ACPI Description Table Arm Boot Architecture Flags
+// All other bits are reserved and must be set to 0.
+//
+#define EFI_ACPI_6_5_ARM_PSCI_COMPLIANT BIT0
+#define EFI_ACPI_6_5_ARM_PSCI_USE_HVC BIT1
+
+//
+// Fixed ACPI Description Table Fixed Feature Flags
+// All other bits are reserved and must be set to 0.
+//
+#define EFI_ACPI_6_5_WBINVD BIT0
+#define EFI_ACPI_6_5_WBINVD_FLUSH BIT1
+#define EFI_ACPI_6_5_PROC_C1 BIT2
+#define EFI_ACPI_6_5_P_LVL2_UP BIT3
+#define EFI_ACPI_6_5_PWR_BUTTON BIT4
+#define EFI_ACPI_6_5_SLP_BUTTON BIT5
+#define EFI_ACPI_6_5_FIX_RTC BIT6
+#define EFI_ACPI_6_5_RTC_S4 BIT7
+#define EFI_ACPI_6_5_TMR_VAL_EXT BIT8
+#define EFI_ACPI_6_5_DCK_CAP BIT9
+#define EFI_ACPI_6_5_RESET_REG_SUP BIT10
+#define EFI_ACPI_6_5_SEALED_CASE BIT11
+#define EFI_ACPI_6_5_HEADLESS BIT12
+#define EFI_ACPI_6_5_CPU_SW_SLP BIT13
+#define EFI_ACPI_6_5_PCI_EXP_WAK BIT14
+#define EFI_ACPI_6_5_USE_PLATFORM_CLOCK BIT15
+#define EFI_ACPI_6_5_S4_RTC_STS_VALID BIT16
+#define EFI_ACPI_6_5_REMOTE_POWER_ON_CAPABLE BIT17
+#define EFI_ACPI_6_5_FORCE_APIC_CLUSTER_MODEL BIT18
+#define EFI_ACPI_6_5_FORCE_APIC_PHYSICAL_DESTINATION_MODE BIT19
+#define EFI_ACPI_6_5_HW_REDUCED_ACPI BIT20
+#define EFI_ACPI_6_5_LOW_POWER_S0_IDLE_CAPABLE BIT21
+
+///
+/// Firmware ACPI Control Structure
+///
+typedef struct {
+ UINT32 Signature;
+ UINT32 Length;
+ UINT32 HardwareSignature;
+ UINT32 FirmwareWakingVector;
+ UINT32 GlobalLock;
+ UINT32 Flags;
+ UINT64 XFirmwareWakingVector;
+ UINT8 Version;
+ UINT8 Reserved0[3];
+ UINT32 OspmFlags;
+ UINT8 Reserved1[24];
+} EFI_ACPI_6_5_FIRMWARE_ACPI_CONTROL_STRUCTURE;
+
+///
+/// FACS Version (as defined in ACPI 6.5 spec.)
+///
+#define EFI_ACPI_6_5_FIRMWARE_ACPI_CONTROL_STRUCTURE_VERSION 0x02
+
+///
+/// Firmware Control Structure Feature Flags
+/// All other bits are reserved and must be set to 0.
+///
+#define EFI_ACPI_6_5_S4BIOS_F BIT0
+#define EFI_ACPI_6_5_64BIT_WAKE_SUPPORTED_F BIT1
+
+///
+/// OSPM Enabled Firmware Control Structure Flags
+/// All other bits are reserved and must be set to 0.
+///
+#define EFI_ACPI_6_5_OSPM_64BIT_WAKE_F BIT0
+
+//
+// Differentiated System Description Table,
+// Secondary System Description Table
+// and Persistent System Description Table,
+// no definition needed as they are common description table header, the same with
+// EFI_ACPI_DESCRIPTION_HEADER, followed by a definition block.
+//
+#define EFI_ACPI_6_5_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x02
+#define EFI_ACPI_6_5_SECONDARY_SYSTEM_DESCRIPTION_TABLE_REVISION 0x02
+
+///
+/// Multiple APIC Description Table header definition. The rest of the table
+/// must be defined in a platform specific manner.
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 LocalApicAddress;
+ UINT32 Flags;
+} EFI_ACPI_6_5_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER;
+
+///
+/// MADT Revision (as defined in ACPI 6.5 spec.)
+///
+#define EFI_ACPI_6_5_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION 0x05
+
+///
+/// Multiple APIC Flags
+/// All other bits are reserved and must be set to 0.
+///
+#define EFI_ACPI_6_5_PCAT_COMPAT BIT0
+
+//
+// Multiple APIC Description Table APIC structure types
+// All other values between 0x18 and 0x7F are reserved and
+// will be ignored by OSPM. 0x80 ~ 0xFF are reserved for OEM.
+//
+#define EFI_ACPI_6_5_PROCESSOR_LOCAL_APIC 0x00
+#define EFI_ACPI_6_5_IO_APIC 0x01
+#define EFI_ACPI_6_5_INTERRUPT_SOURCE_OVERRIDE 0x02
+#define EFI_ACPI_6_5_NON_MASKABLE_INTERRUPT_SOURCE 0x03
+#define EFI_ACPI_6_5_LOCAL_APIC_NMI 0x04
+#define EFI_ACPI_6_5_LOCAL_APIC_ADDRESS_OVERRIDE 0x05
+#define EFI_ACPI_6_5_IO_SAPIC 0x06
+#define EFI_ACPI_6_5_LOCAL_SAPIC 0x07
+#define EFI_ACPI_6_5_PLATFORM_INTERRUPT_SOURCES 0x08
+#define EFI_ACPI_6_5_PROCESSOR_LOCAL_X2APIC 0x09
+#define EFI_ACPI_6_5_LOCAL_X2APIC_NMI 0x0A
+#define EFI_ACPI_6_5_GIC 0x0B
+#define EFI_ACPI_6_5_GICD 0x0C
+#define EFI_ACPI_6_5_GIC_MSI_FRAME 0x0D
+#define EFI_ACPI_6_5_GICR 0x0E
+#define EFI_ACPI_6_5_GIC_ITS 0x0F
+#define EFI_ACPI_6_5_MULTIPROCESSOR_WAKEUP 0x10
+#define EFI_ACPI_6_5_CORE_PIC 0x11
+#define EFI_ACPI_6_5_LIO_PIC 0x12
+#define EFI_ACPI_6_5_HT_PIC 0x13
+#define EFI_ACPI_6_5_EIO_PIC 0x14
+#define EFI_ACPI_6_5_MSI_PIC 0x15
+#define EFI_ACPI_6_5_BIO_PIC 0x16
+#define EFI_ACPI_6_5_LPC_PIC 0x17
+
+//
+// APIC Structure Definitions
+//
+
+///
+/// Processor Local APIC Structure Definition
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 AcpiProcessorUid;
+ UINT8 ApicId;
+ UINT32 Flags;
+} EFI_ACPI_6_5_PROCESSOR_LOCAL_APIC_STRUCTURE;
+
+///
+/// Local APIC Flags. All other bits are reserved and must be 0.
+///
+#define EFI_ACPI_6_5_LOCAL_APIC_ENABLED BIT0
+#define EFI_ACPI_6_5_LOCAL_APIC_ONLINE_CAPABLE BIT1
+
+///
+/// IO APIC Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 IoApicId;
+ UINT8 Reserved;
+ UINT32 IoApicAddress;
+ UINT32 GlobalSystemInterruptBase;
+} EFI_ACPI_6_5_IO_APIC_STRUCTURE;
+
+///
+/// Interrupt Source Override Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 Bus;
+ UINT8 Source;
+ UINT32 GlobalSystemInterrupt;
+ UINT16 Flags;
+} EFI_ACPI_6_5_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE;
+
+///
+/// Platform Interrupt Sources Structure Definition
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Flags;
+ UINT8 InterruptType;
+ UINT8 ProcessorId;
+ UINT8 ProcessorEid;
+ UINT8 IoSapicVector;
+ UINT32 GlobalSystemInterrupt;
+ UINT32 PlatformInterruptSourceFlags;
+ UINT8 CpeiProcessorOverride;
+ UINT8 Reserved[31];
+} EFI_ACPI_6_5_PLATFORM_INTERRUPT_APIC_STRUCTURE;
+
+//
+// MPS INTI flags.
+// All other bits are reserved and must be set to 0.
+//
+#define EFI_ACPI_6_5_POLARITY (3 << 0)
+#define EFI_ACPI_6_5_TRIGGER_MODE (3 << 2)
+
+///
+/// Non-Maskable Interrupt Source Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Flags;
+ UINT32 GlobalSystemInterrupt;
+} EFI_ACPI_6_5_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE;
+
+///
+/// Local APIC NMI Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 AcpiProcessorUid;
+ UINT16 Flags;
+ UINT8 LocalApicLint;
+} EFI_ACPI_6_5_LOCAL_APIC_NMI_STRUCTURE;
+
+///
+/// Local APIC Address Override Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Reserved;
+ UINT64 LocalApicAddress;
+} EFI_ACPI_6_5_LOCAL_APIC_ADDRESS_OVERRIDE_STRUCTURE;
+
+///
+/// IO SAPIC Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 IoApicId;
+ UINT8 Reserved;
+ UINT32 GlobalSystemInterruptBase;
+ UINT64 IoSapicAddress;
+} EFI_ACPI_6_5_IO_SAPIC_STRUCTURE;
+
+///
+/// Local SAPIC Structure
+/// This struct followed by a null-terminated ASCII string - ACPI Processor UID String
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 AcpiProcessorId;
+ UINT8 LocalSapicId;
+ UINT8 LocalSapicEid;
+ UINT8 Reserved[3];
+ UINT32 Flags;
+ UINT32 ACPIProcessorUIDValue;
+} EFI_ACPI_6_5_PROCESSOR_LOCAL_SAPIC_STRUCTURE;
+
+///
+/// Platform Interrupt Sources Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Flags;
+ UINT8 InterruptType;
+ UINT8 ProcessorId;
+ UINT8 ProcessorEid;
+ UINT8 IoSapicVector;
+ UINT32 GlobalSystemInterrupt;
+ UINT32 PlatformInterruptSourceFlags;
+} EFI_ACPI_6_5_PLATFORM_INTERRUPT_SOURCES_STRUCTURE;
+
+///
+/// Platform Interrupt Source Flags.
+/// All other bits are reserved and must be set to 0.
+///
+#define EFI_ACPI_6_5_CPEI_PROCESSOR_OVERRIDE BIT0
+
+///
+/// Processor Local x2APIC Structure Definition
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 Reserved[2];
+ UINT32 X2ApicId;
+ UINT32 Flags;
+ UINT32 AcpiProcessorUid;
+} EFI_ACPI_6_5_PROCESSOR_LOCAL_X2APIC_STRUCTURE;
+
+///
+/// Local x2APIC NMI Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Flags;
+ UINT32 AcpiProcessorUid;
+ UINT8 LocalX2ApicLint;
+ UINT8 Reserved[3];
+} EFI_ACPI_6_5_LOCAL_X2APIC_NMI_STRUCTURE;
+
+///
+/// GIC Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Reserved;
+ UINT32 CPUInterfaceNumber;
+ UINT32 AcpiProcessorUid;
+ UINT32 Flags;
+ UINT32 ParkingProtocolVersion;
+ UINT32 PerformanceInterruptGsiv;
+ UINT64 ParkedAddress;
+ UINT64 PhysicalBaseAddress;
+ UINT64 GICV;
+ UINT64 GICH;
+ UINT32 VGICMaintenanceInterrupt;
+ UINT64 GICRBaseAddress;
+ UINT64 MPIDR;
+ UINT8 ProcessorPowerEfficiencyClass;
+ UINT8 Reserved2;
+ UINT16 SpeOverflowInterrupt;
+} EFI_ACPI_6_5_GIC_STRUCTURE;
+
+///
+/// GIC Flags. All other bits are reserved and must be 0.
+///
+#define EFI_ACPI_6_5_GIC_ENABLED BIT0
+#define EFI_ACPI_6_5_PERFORMANCE_INTERRUPT_MODEL BIT1
+#define EFI_ACPI_6_5_VGIC_MAINTENANCE_INTERRUPT_MODE_FLAGS BIT2
+
+///
+/// GIC Distributor Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Reserved1;
+ UINT32 GicId;
+ UINT64 PhysicalBaseAddress;
+ UINT32 SystemVectorBase;
+ UINT8 GicVersion;
+ UINT8 Reserved2[3];
+} EFI_ACPI_6_5_GIC_DISTRIBUTOR_STRUCTURE;
+
+///
+/// GIC Version
+///
+#define EFI_ACPI_6_5_GIC_V1 0x01
+#define EFI_ACPI_6_5_GIC_V2 0x02
+#define EFI_ACPI_6_5_GIC_V3 0x03
+#define EFI_ACPI_6_5_GIC_V4 0x04
+
+///
+/// GIC MSI Frame Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Reserved1;
+ UINT32 GicMsiFrameId;
+ UINT64 PhysicalBaseAddress;
+ UINT32 Flags;
+ UINT16 SPICount;
+ UINT16 SPIBase;
+} EFI_ACPI_6_5_GIC_MSI_FRAME_STRUCTURE;
+
+///
+/// GIC MSI Frame Flags. All other bits are reserved and must be 0.
+///
+#define EFI_ACPI_6_5_SPI_COUNT_BASE_SELECT BIT0
+
+///
+/// GICR Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Reserved;
+ UINT64 DiscoveryRangeBaseAddress;
+ UINT32 DiscoveryRangeLength;
+} EFI_ACPI_6_5_GICR_STRUCTURE;
+
+///
+/// GIC Interrupt Translation Service Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Reserved;
+ UINT32 GicItsId;
+ UINT64 PhysicalBaseAddress;
+ UINT32 Reserved2;
+} EFI_ACPI_6_5_GIC_ITS_STRUCTURE;
+
+///
+/// Multiprocessor Wakeup Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 MailBoxVersion;
+ UINT32 Reserved;
+ UINT64 MailBoxAddress;
+} EFI_ACPI_6_5_MULTIPROCESSOR_WAKEUP_STRUCTURE;
+
+///
+/// Multiprocessor Wakeup Mailbox Structure
+///
+typedef struct {
+ UINT16 Command;
+ UINT16 Reserved;
+ UINT32 AcpiId;
+ UINT64 WakeupVector;
+ UINT8 ReservedForOs[2032];
+ UINT8 ReservedForFirmware[2048];
+} EFI_ACPI_6_5_MULTIPROCESSOR_WAKEUP_MAILBOX_STRUCTURE;
+
+#define EFI_ACPI_6_5_MULTIPROCESSOR_WAKEUP_MAILBOX_COMMAND_NOOP 0x0000
+#define EFI_ACPI_6_5_MULTIPROCESSOR_WAKEUP_MAILBOX_COMMAND_WAKEUP 0x0001
+
+///
+/// Core Programmable Interrupt Controller
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 Version;
+ UINT32 ProcessorId;
+ UINT32 CoreId;
+ UINT32 Flags;
+} EFI_ACPI_6_5_CORE_PIC_STRUCTURE;
+
+///
+/// Legacy I/O Programmable Interrupt Controller
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 Version;
+ UINT64 Address;
+ UINT16 Size;
+ UINT8 Cascade[2];
+ UINT32 CascadeMap[2];
+} EFI_ACPI_6_5_LIO_PIC_STRUCTURE;
+
+///
+/// HyperTransport Programmable Interrupt Controller
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 Version;
+ UINT64 Address;
+ UINT16 Size;
+ UINT8 Cascade[8];
+} EFI_ACPI_6_5_HT_PIC_STRUCTURE;
+
+///
+/// Extend I/O Programmable Interrupt Controller
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 Version;
+ UINT8 Cascade;
+ UINT8 Node;
+ UINT64 NodeMap;
+} EFI_ACPI_6_5_EIO_PIC_STRUCTURE;
+
+///
+/// MSI Programmable Interrupt Controller
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 Version;
+ UINT64 MsgAddress;
+ UINT32 Start;
+ UINT32 Count;
+} EFI_ACPI_6_5_MSI_PIC_STRUCTURE;
+
+///
+/// Bridge I/O Programmable Interrupt Controller
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 Version;
+ UINT64 Address;
+ UINT16 Size;
+ UINT16 Id;
+ UINT16 GsiBase;
+} EFI_ACPI_6_5_BIO_PIC_STRUCTURE;
+
+///
+/// Low Pin Count Programmable Interrupt Controller
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 Version;
+ UINT64 Address;
+ UINT16 Size;
+ UINT8 Cascade;
+} EFI_ACPI_6_5_LPC_PIC_STRUCTURE;
+
+///
+/// Smart Battery Description Table (SBST)
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 WarningEnergyLevel;
+ UINT32 LowEnergyLevel;
+ UINT32 CriticalEnergyLevel;
+} EFI_ACPI_6_5_SMART_BATTERY_DESCRIPTION_TABLE;
+
+///
+/// SBST Version (as defined in ACPI 6.5 spec.)
+///
+#define EFI_ACPI_6_5_SMART_BATTERY_DESCRIPTION_TABLE_REVISION 0x01
+
+///
+/// Embedded Controller Boot Resources Table (ECDT)
+/// The table is followed by a null terminated ASCII string that contains
+/// a fully qualified reference to the name space object.
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ EFI_ACPI_6_5_GENERIC_ADDRESS_STRUCTURE EcControl;
+ EFI_ACPI_6_5_GENERIC_ADDRESS_STRUCTURE EcData;
+ UINT32 Uid;
+ UINT8 GpeBit;
+} EFI_ACPI_6_5_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE;
+
+///
+/// ECDT Version (as defined in ACPI 6.5 spec.)
+///
+#define EFI_ACPI_6_5_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE_REVISION 0x01
+
+///
+/// System Resource Affinity Table (SRAT). The rest of the table
+/// must be defined in a platform specific manner.
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 Reserved1; ///< Must be set to 1
+ UINT64 Reserved2;
+} EFI_ACPI_6_5_SYSTEM_RESOURCE_AFFINITY_TABLE_HEADER;
+
+///
+/// SRAT Version (as defined in ACPI 6.5 spec.)
+///
+#define EFI_ACPI_6_5_SYSTEM_RESOURCE_AFFINITY_TABLE_REVISION 0x03
+
+//
+// SRAT structure types.
+// All other values between 0x06 an 0xFF are reserved and
+// will be ignored by OSPM.
+//
+#define EFI_ACPI_6_5_PROCESSOR_LOCAL_APIC_SAPIC_AFFINITY 0x00
+#define EFI_ACPI_6_5_MEMORY_AFFINITY 0x01
+#define EFI_ACPI_6_5_PROCESSOR_LOCAL_X2APIC_AFFINITY 0x02
+#define EFI_ACPI_6_5_GICC_AFFINITY 0x03
+#define EFI_ACPI_6_5_GIC_ITS_AFFINITY 0x04
+#define EFI_ACPI_6_5_GENERIC_INITIATOR_AFFINITY 0x05
+
+///
+/// Processor Local APIC/SAPIC Affinity Structure Definition
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 ProximityDomain7To0;
+ UINT8 ApicId;
+ UINT32 Flags;
+ UINT8 LocalSapicEid;
+ UINT8 ProximityDomain31To8[3];
+ UINT32 ClockDomain;
+} EFI_ACPI_6_5_PROCESSOR_LOCAL_APIC_SAPIC_AFFINITY_STRUCTURE;
+
+///
+/// Local APIC/SAPIC Flags. All other bits are reserved and must be 0.
+///
+#define EFI_ACPI_6_5_PROCESSOR_LOCAL_APIC_SAPIC_ENABLED (1 << 0)
+
+///
+/// Memory Affinity Structure Definition
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT32 ProximityDomain;
+ UINT16 Reserved1;
+ UINT32 AddressBaseLow;
+ UINT32 AddressBaseHigh;
+ UINT32 LengthLow;
+ UINT32 LengthHigh;
+ UINT32 Reserved2;
+ UINT32 Flags;
+ UINT64 Reserved3;
+} EFI_ACPI_6_5_MEMORY_AFFINITY_STRUCTURE;
+
+//
+// Memory Flags. All other bits are reserved and must be 0.
+//
+#define EFI_ACPI_6_5_MEMORY_ENABLED (1 << 0)
+#define EFI_ACPI_6_5_MEMORY_HOT_PLUGGABLE (1 << 1)
+#define EFI_ACPI_6_5_MEMORY_NONVOLATILE (1 << 2)
+
+///
+/// Processor Local x2APIC Affinity Structure Definition
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 Reserved1[2];
+ UINT32 ProximityDomain;
+ UINT32 X2ApicId;
+ UINT32 Flags;
+ UINT32 ClockDomain;
+ UINT8 Reserved2[4];
+} EFI_ACPI_6_5_PROCESSOR_LOCAL_X2APIC_AFFINITY_STRUCTURE;
+
+///
+/// GICC Affinity Structure Definition
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT32 ProximityDomain;
+ UINT32 AcpiProcessorUid;
+ UINT32 Flags;
+ UINT32 ClockDomain;
+} EFI_ACPI_6_5_GICC_AFFINITY_STRUCTURE;
+
+///
+/// GICC Flags. All other bits are reserved and must be 0.
+///
+#define EFI_ACPI_6_5_GICC_ENABLED (1 << 0)
+
+///
+/// GIC Interrupt Translation Service (ITS) Affinity Structure Definition
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT32 ProximityDomain;
+ UINT8 Reserved[2];
+ UINT32 ItsId;
+} EFI_ACPI_6_5_GIC_ITS_AFFINITY_STRUCTURE;
+
+//
+// Generic Initiator Affinity Structure Device Handle Types
+// All other values between 0x02 an 0xFF are reserved and
+// will be ignored by OSPM.
+//
+#define EFI_ACPI_6_5_ACPI_DEVICE_HANDLE 0x00
+#define EFI_ACPI_6_5_PCI_DEVICE_HANDLE 0x01
+
+///
+/// Device Handle - ACPI
+///
+typedef struct {
+ UINT64 AcpiHid;
+ UINT32 AcpiUid;
+ UINT8 Reserved[4];
+} EFI_ACPI_6_5_DEVICE_HANDLE_ACPI;
+
+///
+/// Device Handle - PCI
+///
+typedef struct {
+ UINT16 PciSegment;
+ UINT16 PciBdfNumber;
+ UINT8 Reserved[12];
+} EFI_ACPI_6_5_DEVICE_HANDLE_PCI;
+
+///
+/// Device Handle
+///
+typedef union {
+ EFI_ACPI_6_5_DEVICE_HANDLE_ACPI Acpi;
+ EFI_ACPI_6_5_DEVICE_HANDLE_PCI Pci;
+} EFI_ACPI_6_5_DEVICE_HANDLE;
+
+///
+/// Generic Initiator Affinity Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 Reserved1;
+ UINT8 DeviceHandleType;
+ UINT32 ProximityDomain;
+ EFI_ACPI_6_5_DEVICE_HANDLE DeviceHandle;
+ UINT32 Flags;
+ UINT8 Reserved2[4];
+} EFI_ACPI_6_5_GENERIC_INITIATOR_AFFINITY_STRUCTURE;
+
+///
+/// Generic Initiator Affinity Structure Flags. All other bits are reserved
+/// and must be 0.
+///
+#define EFI_ACPI_6_5_GENERIC_INITIATOR_AFFINITY_STRUCTURE_ENABLED BIT0
+#define EFI_ACPI_6_5_GENERIC_INITIATOR_AFFINITY_STRUCTURE_ARCHITECTURAL_TRANSACTIONS BIT1
+
+///
+/// System Locality Distance Information Table (SLIT).
+/// The rest of the table is a matrix.
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT64 NumberOfSystemLocalities;
+} EFI_ACPI_6_5_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_HEADER;
+
+///
+/// SLIT Version (as defined in ACPI 6.5 spec.)
+///
+#define EFI_ACPI_6_5_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_REVISION 0x01
+
+///
+/// Corrected Platform Error Polling Table (CPEP)
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT8 Reserved[8];
+} EFI_ACPI_6_5_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_HEADER;
+
+///
+/// CPEP Version (as defined in ACPI 6.5 spec.)
+///
+#define EFI_ACPI_6_5_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_REVISION 0x01
+
+//
+// CPEP processor structure types.
+//
+#define EFI_ACPI_6_5_CPEP_PROCESSOR_APIC_SAPIC 0x00
+
+///
+/// Corrected Platform Error Polling Processor Structure Definition
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 ProcessorId;
+ UINT8 ProcessorEid;
+ UINT32 PollingInterval;
+} EFI_ACPI_6_5_CPEP_PROCESSOR_APIC_SAPIC_STRUCTURE;
+
+///
+/// Maximum System Characteristics Table (MSCT)
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 OffsetProxDomInfo;
+ UINT32 MaximumNumberOfProximityDomains;
+ UINT32 MaximumNumberOfClockDomains;
+ UINT64 MaximumPhysicalAddress;
+} EFI_ACPI_6_5_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_HEADER;
+
+///
+/// MSCT Version (as defined in ACPI 6.5 spec.)
+///
+#define EFI_ACPI_6_5_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_REVISION 0x01
+
+///
+/// Maximum Proximity Domain Information Structure Definition
+///
+typedef struct {
+ UINT8 Revision;
+ UINT8 Length;
+ UINT32 ProximityDomainRangeLow;
+ UINT32 ProximityDomainRangeHigh;
+ UINT32 MaximumProcessorCapacity;
+ UINT64 MaximumMemoryCapacity;
+} EFI_ACPI_6_5_MAXIMUM_PROXIMITY_DOMAIN_INFORMATION_STRUCTURE;
+
+///
+/// ACPI RAS Feature Table definition.
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT8 PlatformCommunicationChannelIdentifier[12];
+} EFI_ACPI_6_5_RAS_FEATURE_TABLE;
+
+///
+/// RASF Version (as defined in ACPI 6.5 spec.)
+///
+#define EFI_ACPI_6_5_RAS_FEATURE_TABLE_REVISION 0x01
+
+///
+/// ACPI RASF Platform Communication Channel Shared Memory Region definition.
+///
+typedef struct {
+ UINT32 Signature;
+ UINT16 Command;
+ UINT16 Status;
+ UINT16 Version;
+ UINT8 RASCapabilities[16];
+ UINT8 SetRASCapabilities[16];
+ UINT16 NumberOfRASFParameterBlocks;
+ UINT32 SetRASCapabilitiesStatus;
+} EFI_ACPI_6_5_RASF_PLATFORM_COMMUNICATION_CHANNEL_SHARED_MEMORY_REGION;
+
+///
+/// ACPI RASF PCC command code
+///
+#define EFI_ACPI_6_5_RASF_PCC_COMMAND_CODE_EXECUTE_RASF_COMMAND 0x01
+
+///
+/// ACPI RASF Platform RAS Capabilities
+///
+#define EFI_ACPI_6_5_RASF_PLATFORM_RAS_CAPABILITY_HARDWARE_BASED_PATROL_SCRUB_SUPPORTED BIT0
+#define EFI_ACPI_6_5_RASF_PLATFORM_RAS_CAPABILITY_HARDWARE_BASED_PATROL_SCRUB_SUPPORTED_AND_EXPOSED_TO_SOFTWARE BIT1
+#define EFI_ACPI_6_5_RASF_PLATFORM_RAS_CAPABILITY_CPU_CACHE_FLUSH_TO_NVDIMM_DURABILITY_ON_POWER_LOSS BIT2
+#define EFI_ACPI_6_5_RASF_PLATFORM_RAS_CAPABILITY_MEMORY_CONTROLLER_FLUSH_TO_NVDIMM_DURABILITY_ON_POWER_LOSS BIT3
+#define EFI_ACPI_6_5_RASF_PLATFORM_RAS_CAPABILITY_BYTE_ADDRESSABLE_PERSISTENT_MEMORY_HARDWARE_MIRRORING BIT4
+
+///
+/// ACPI RASF Parameter Block structure for PATROL_SCRUB
+///
+typedef struct {
+ UINT16 Type;
+ UINT16 Version;
+ UINT16 Length;
+ UINT16 PatrolScrubCommand;
+ UINT64 RequestedAddressRange[2];
+ UINT64 ActualAddressRange[2];
+ UINT16 Flags;
+ UINT8 RequestedSpeed;
+} EFI_ACPI_6_5_RASF_PATROL_SCRUB_PLATFORM_BLOCK_STRUCTURE;
+
+///
+/// ACPI RASF Patrol Scrub command
+///
+#define EFI_ACPI_6_5_RASF_PATROL_SCRUB_COMMAND_GET_PATROL_PARAMETERS 0x01
+#define EFI_ACPI_6_5_RASF_PATROL_SCRUB_COMMAND_START_PATROL_SCRUBBER 0x02
+#define EFI_ACPI_6_5_RASF_PATROL_SCRUB_COMMAND_STOP_PATROL_SCRUBBER 0x03
+
+///
+/// Memory Power State Table definition.
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT8 PlatformCommunicationChannelIdentifier;
+ UINT8 Reserved[3];
+ // Memory Power Node Structure
+ // Memory Power State Characteristics
+} EFI_ACPI_6_5_MEMORY_POWER_STATUS_TABLE;
+
+///
+/// MPST Version (as defined in ACPI 6.5 spec.)
+///
+#define EFI_ACPI_6_5_MEMORY_POWER_STATE_TABLE_REVISION 0x01
+
+///
+/// MPST Platform Communication Channel Shared Memory Region definition.
+///
+typedef struct {
+ UINT32 Signature;
+ UINT16 Command;
+ UINT16 Status;
+ UINT32 MemoryPowerCommandRegister;
+ UINT32 MemoryPowerStatusRegister;
+ UINT32 PowerStateId;
+ UINT32 MemoryPowerNodeId;
+ UINT64 MemoryEnergyConsumed;
+ UINT64 ExpectedAveragePowerComsuned;
+} EFI_ACPI_6_5_MPST_PLATFORM_COMMUNICATION_CHANNEL_SHARED_MEMORY_REGION;
+
+///
+/// ACPI MPST PCC command code
+///
+#define EFI_ACPI_6_5_MPST_PCC_COMMAND_CODE_EXECUTE_MPST_COMMAND 0x03
+
+///
+/// ACPI MPST Memory Power command
+///
+#define EFI_ACPI_6_5_MPST_MEMORY_POWER_COMMAND_GET_MEMORY_POWER_STATE 0x01
+#define EFI_ACPI_6_5_MPST_MEMORY_POWER_COMMAND_SET_MEMORY_POWER_STATE 0x02
+#define EFI_ACPI_6_5_MPST_MEMORY_POWER_COMMAND_GET_AVERAGE_POWER_CONSUMED 0x03
+#define EFI_ACPI_6_5_MPST_MEMORY_POWER_COMMAND_GET_MEMORY_ENERGY_CONSUMED 0x04
+
+///
+/// MPST Memory Power Node Table
+///
+typedef struct {
+ UINT8 PowerStateValue;
+ UINT8 PowerStateInformationIndex;
+} EFI_ACPI_6_5_MPST_MEMORY_POWER_STATE;
+
+typedef struct {
+ UINT8 Flag;
+ UINT8 Reserved;
+ UINT16 MemoryPowerNodeId;
+ UINT32 Length;
+ UINT64 AddressBase;
+ UINT64 AddressLength;
+ UINT32 NumberOfPowerStates;
+ UINT32 NumberOfPhysicalComponents;
+ // EFI_ACPI_6_5_MPST_MEMORY_POWER_STATE MemoryPowerState[NumberOfPowerStates];
+ // UINT16 PhysicalComponentIdentifier[NumberOfPhysicalComponents];
+} EFI_ACPI_6_5_MPST_MEMORY_POWER_STRUCTURE;
+
+#define EFI_ACPI_6_5_MPST_MEMORY_POWER_STRUCTURE_FLAG_ENABLE 0x01
+#define EFI_ACPI_6_5_MPST_MEMORY_POWER_STRUCTURE_FLAG_POWER_MANAGED 0x02
+#define EFI_ACPI_6_5_MPST_MEMORY_POWER_STRUCTURE_FLAG_HOT_PLUGGABLE 0x04
+
+typedef struct {
+ UINT16 MemoryPowerNodeCount;
+ UINT8 Reserved[2];
+} EFI_ACPI_6_5_MPST_MEMORY_POWER_NODE_TABLE;
+
+///
+/// MPST Memory Power State Characteristics Table
+///
+typedef struct {
+ UINT8 PowerStateStructureID;
+ UINT8 Flag;
+ UINT16 Reserved;
+ UINT32 AveragePowerConsumedInMPS0;
+ UINT32 RelativePowerSavingToMPS0;
+ UINT64 ExitLatencyToMPS0;
+} EFI_ACPI_6_5_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE;
+
+#define EFI_ACPI_6_5_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_MEMORY_CONTENT_PRESERVED 0x01
+#define EFI_ACPI_6_5_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_AUTONOMOUS_MEMORY_POWER_STATE_ENTRY 0x02
+#define EFI_ACPI_6_5_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_AUTONOMOUS_MEMORY_POWER_STATE_EXIT 0x04
+
+typedef struct {
+ UINT16 MemoryPowerStateCharacteristicsCount;
+ UINT8 Reserved[2];
+} EFI_ACPI_6_5_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_TABLE;
+
+///
+/// Platform Memory Topology Table definition.
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 NumberOfMemoryDevices;
+ // EFI_ACPI_6_5_PMTT_COMMON_MEMORY_DEVICE MemoryDeviceStructure[NumberOfMemoryDevices];
+} EFI_ACPI_6_5_PLATFORM_MEMORY_TOPOLOGY_TABLE;
+
+///
+/// PMTT Version (as defined in ACPI 6.5 spec.)
+///
+#define EFI_ACPI_6_5_MEMORY_TOPOLOGY_TABLE_REVISION 0x02
+
+///
+/// Common Memory Device.
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Reserved;
+ UINT16 Length;
+ UINT16 Flags;
+ UINT16 Reserved1;
+ UINT32 NumberOfMemoryDevices;
+ // UINT8 TypeSpecificData[];
+ // EFI_ACPI_6_5_PMTT_COMMON_MEMORY_DEVICE MemoryDeviceStructure[NumberOfMemoryDevices];
+} EFI_ACPI_6_5_PMTT_COMMON_MEMORY_DEVICE;
+
+///
+/// Memory Device Type.
+///
+#define EFI_ACPI_6_5_PMTT_MEMORY_DEVICE_TYPE_SOCKET 0x0
+#define EFI_ACPI_6_5_PMTT_MEMORY_DEVICE_TYPE_MEMORY_CONTROLLER 0x1
+#define EFI_ACPI_6_5_PMTT_MEMORY_DEVICE_TYPE_DIMM 0x2
+#define EFI_ACPI_6_5_PMTT_MEMORY_DEVICE_TYPE_VENDOR_SPECIFIC_TYPE 0xFF
+
+///
+/// Socket Type Data.
+///
+typedef struct {
+ EFI_ACPI_6_5_PMTT_COMMON_MEMORY_DEVICE CommonMemoryDeviceHeader;
+ UINT16 SocketIdentifier;
+ UINT16 Reserved;
+ // EFI_ACPI_6_5_PMTT_COMMON_MEMORY_DEVICE MemoryDeviceStructure[];
+} EFI_ACPI_6_5_PMTT_SOCKET_TYPE_DATA;
+
+///
+/// Memory Controller Type Data.
+///
+typedef struct {
+ EFI_ACPI_6_5_PMTT_COMMON_MEMORY_DEVICE CommonMemoryDeviceHeader;
+ UINT16 MemoryControllerIdentifier;
+ UINT16 Reserved;
+ // EFI_ACPI_6_5_PMTT_COMMON_MEMORY_DEVICE MemoryDeviceStructure[];
+} EFI_ACPI_6_5_PMTT_MEMORY_CONTROLLER_TYPE_DATA;
+
+///
+/// DIMM Type Specific Data.
+///
+typedef struct {
+ EFI_ACPI_6_5_PMTT_COMMON_MEMORY_DEVICE CommonMemoryDeviceHeader;
+ UINT32 SmbiosHandle;
+} EFI_ACPI_6_5_PMTT_DIMM_TYPE_SPECIFIC_DATA;
+
+///
+/// Vendor Specific Type Data.
+///
+typedef struct {
+ EFI_ACPI_6_5_PMTT_COMMON_MEMORY_DEVICE CommonMemoryDeviceHeader;
+ UINT8 TypeUuid[16];
+ // EFI_ACPI_6_5_PMTT_VENDOR_SPECIFIC_TYPE_DATA VendorSpecificData[];
+ // EFI_ACPI_6_5_PMTT_COMMON_MEMORY_DEVICE MemoryDeviceStructure[];
+} EFI_ACPI_6_5_PMTT_VENDOR_SPECIFIC_TYPE_DATA;
+
+///
+/// Boot Graphics Resource Table definition.
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ ///
+ /// 2-bytes (16 bit) version ID. This value must be 1.
+ ///
+ UINT16 Version;
+ ///
+ /// 1-byte status field indicating current status about the table.
+ /// Bits[7:3] = Reserved (must be zero)
+ /// Bits[2:1] = Orientation Offset. These bits describe the clockwise
+ /// degree offset from the image's default orientation.
+ /// [00] = 0, no offset
+ /// [01] = 90
+ /// [10] = 180
+ /// [11] = 270
+ /// Bit [0] = Displayed. A one indicates the boot image graphic is
+ /// displayed.
+ ///
+ UINT8 Status;
+ ///
+ /// 1-byte enumerated type field indicating format of the image.
+ /// 0 = Bitmap
+ /// 1 - 255 Reserved (for future use)
+ ///
+ UINT8 ImageType;
+ ///
+ /// 8-byte (64 bit) physical address pointing to the firmware's in-memory copy
+ /// of the image bitmap.
+ ///
+ UINT64 ImageAddress;
+ ///
+ /// A 4-byte (32-bit) unsigned long describing the display X-offset of the boot image.
+ /// (X, Y) display offset of the top left corner of the boot image.
+ /// The top left corner of the display is at offset (0, 0).
+ ///
+ UINT32 ImageOffsetX;
+ ///
+ /// A 4-byte (32-bit) unsigned long describing the display Y-offset of the boot image.
+ /// (X, Y) display offset of the top left corner of the boot image.
+ /// The top left corner of the display is at offset (0, 0).
+ ///
+ UINT32 ImageOffsetY;
+} EFI_ACPI_6_5_BOOT_GRAPHICS_RESOURCE_TABLE;
+
+///
+/// BGRT Revision
+///
+#define EFI_ACPI_6_5_BOOT_GRAPHICS_RESOURCE_TABLE_REVISION 1
+
+///
+/// BGRT Version
+///
+#define EFI_ACPI_6_5_BGRT_VERSION 0x01
+
+///
+/// BGRT Status
+///
+#define EFI_ACPI_6_5_BGRT_STATUS_NOT_DISPLAYED 0x00
+#define EFI_ACPI_6_5_BGRT_STATUS_DISPLAYED 0x01
+
+///
+/// BGRT Image Type
+///
+#define EFI_ACPI_6_5_BGRT_IMAGE_TYPE_BMP 0x00
+
+///
+/// FPDT Version (as defined in ACPI 6.5 spec.)
+///
+#define EFI_ACPI_6_5_FIRMWARE_PERFORMANCE_DATA_TABLE_REVISION 0x01
+
+///
+/// FPDT Performance Record Types
+///
+#define EFI_ACPI_6_5_FPDT_RECORD_TYPE_FIRMWARE_BASIC_BOOT_POINTER 0x0000
+#define EFI_ACPI_6_5_FPDT_RECORD_TYPE_S3_PERFORMANCE_TABLE_POINTER 0x0001
+
+///
+/// FPDT Performance Record Revision
+///
+#define EFI_ACPI_6_5_FPDT_RECORD_REVISION_FIRMWARE_BASIC_BOOT_POINTER 0x01
+#define EFI_ACPI_6_5_FPDT_RECORD_REVISION_S3_PERFORMANCE_TABLE_POINTER 0x01
+
+///
+/// FPDT Runtime Performance Record Types
+///
+#define EFI_ACPI_6_5_FPDT_RUNTIME_RECORD_TYPE_S3_RESUME 0x0000
+#define EFI_ACPI_6_5_FPDT_RUNTIME_RECORD_TYPE_S3_SUSPEND 0x0001
+#define EFI_ACPI_6_5_FPDT_RUNTIME_RECORD_TYPE_FIRMWARE_BASIC_BOOT 0x0002
+
+///
+/// FPDT Runtime Performance Record Revision
+///
+#define EFI_ACPI_6_5_FPDT_RUNTIME_RECORD_REVISION_S3_RESUME 0x01
+#define EFI_ACPI_6_5_FPDT_RUNTIME_RECORD_REVISION_S3_SUSPEND 0x01
+#define EFI_ACPI_6_5_FPDT_RUNTIME_RECORD_REVISION_FIRMWARE_BASIC_BOOT 0x02
+
+///
+/// FPDT Performance Record header
+///
+typedef struct {
+ UINT16 Type;
+ UINT8 Length;
+ UINT8 Revision;
+} EFI_ACPI_6_5_FPDT_PERFORMANCE_RECORD_HEADER;
+
+///
+/// FPDT Performance Table header
+///
+typedef struct {
+ UINT32 Signature;
+ UINT32 Length;
+} EFI_ACPI_6_5_FPDT_PERFORMANCE_TABLE_HEADER;
+
+///
+/// FPDT Firmware Basic Boot Performance Pointer Record Structure
+///
+typedef struct {
+ EFI_ACPI_6_5_FPDT_PERFORMANCE_RECORD_HEADER Header;
+ UINT32 Reserved;
+ ///
+ /// 64-bit processor-relative physical address of the Basic Boot Performance Table.
+ ///
+ UINT64 BootPerformanceTablePointer;
+} EFI_ACPI_6_5_FPDT_BOOT_PERFORMANCE_TABLE_POINTER_RECORD;
+
+///
+/// FPDT S3 Performance Table Pointer Record Structure
+///
+typedef struct {
+ EFI_ACPI_6_5_FPDT_PERFORMANCE_RECORD_HEADER Header;
+ UINT32 Reserved;
+ ///
+ /// 64-bit processor-relative physical address of the S3 Performance Table.
+ ///
+ UINT64 S3PerformanceTablePointer;
+} EFI_ACPI_6_5_FPDT_S3_PERFORMANCE_TABLE_POINTER_RECORD;
+
+///
+/// FPDT Firmware Basic Boot Performance Record Structure
+///
+typedef struct {
+ EFI_ACPI_6_5_FPDT_PERFORMANCE_RECORD_HEADER Header;
+ UINT32 Reserved;
+ ///
+ /// Timer value logged at the beginning of firmware image execution.
+ /// This may not always be zero or near zero.
+ ///
+ UINT64 ResetEnd;
+ ///
+ /// Timer value logged just prior to loading the OS boot loader into memory.
+ /// For non-UEFI compatible boots, this field must be zero.
+ ///
+ UINT64 OsLoaderLoadImageStart;
+ ///
+ /// Timer value logged just prior to launching the previously loaded OS boot loader image.
+ /// For non-UEFI compatible boots, the timer value logged will be just prior
+ /// to the INT 19h handler invocation.
+ ///
+ UINT64 OsLoaderStartImageStart;
+ ///
+ /// Timer value logged at the point when the OS loader calls the
+ /// ExitBootServices function for UEFI compatible firmware.
+ /// For non-UEFI compatible boots, this field must be zero.
+ ///
+ UINT64 ExitBootServicesEntry;
+ ///
+ /// Timer value logged at the point just prior towhen the OS loader gaining
+ /// control back from calls the ExitBootServices function for UEFI compatible firmware.
+ /// For non-UEFI compatible boots, this field must be zero.
+ ///
+ UINT64 ExitBootServicesExit;
+} EFI_ACPI_6_5_FPDT_FIRMWARE_BASIC_BOOT_RECORD;
+
+///
+/// FPDT Firmware Basic Boot Performance Table signature
+///
+#define EFI_ACPI_6_5_FPDT_BOOT_PERFORMANCE_TABLE_SIGNATURE SIGNATURE_32('F', 'B', 'P', 'T')
+
+//
+// FPDT Firmware Basic Boot Performance Table
+//
+typedef struct {
+ EFI_ACPI_6_5_FPDT_PERFORMANCE_TABLE_HEADER Header;
+ //
+ // one or more Performance Records.
+ //
+} EFI_ACPI_6_5_FPDT_FIRMWARE_BASIC_BOOT_TABLE;
+
+///
+/// FPDT "S3PT" S3 Performance Table
+///
+#define EFI_ACPI_6_5_FPDT_S3_PERFORMANCE_TABLE_SIGNATURE SIGNATURE_32('S', '3', 'P', 'T')
+
+//
+// FPDT Firmware S3 Boot Performance Table
+//
+typedef struct {
+ EFI_ACPI_6_5_FPDT_PERFORMANCE_TABLE_HEADER Header;
+ //
+ // one or more Performance Records.
+ //
+} EFI_ACPI_6_5_FPDT_FIRMWARE_S3_BOOT_TABLE;
+
+///
+/// FPDT Basic S3 Resume Performance Record
+///
+typedef struct {
+ EFI_ACPI_6_5_FPDT_PERFORMANCE_RECORD_HEADER Header;
+ ///
+ /// A count of the number of S3 resume cycles since the last full boot sequence.
+ ///
+ UINT32 ResumeCount;
+ ///
+ /// Timer recorded at the end of BIOS S3 resume, just prior to handoff to the
+ /// OS waking vector. Only the most recent resume cycle's time is retained.
+ ///
+ UINT64 FullResume;
+ ///
+ /// Average timer value of all resume cycles logged since the last full boot
+ /// sequence, including the most recent resume. Note that the entire log of
+ /// timer values does not need to be retained in order to calculate this average.
+ ///
+ UINT64 AverageResume;
+} EFI_ACPI_6_5_FPDT_S3_RESUME_RECORD;
+
+///
+/// FPDT Basic S3 Suspend Performance Record
+///
+typedef struct {
+ EFI_ACPI_6_5_FPDT_PERFORMANCE_RECORD_HEADER Header;
+ ///
+ /// Timer value recorded at the OS write to SLP_TYP upon entry to S3.
+ /// Only the most recent suspend cycle's timer value is retained.
+ ///
+ UINT64 SuspendStart;
+ ///
+ /// Timer value recorded at the final firmware write to SLP_TYP (or other
+ /// mechanism) used to trigger hardware entry to S3.
+ /// Only the most recent suspend cycle's timer value is retained.
+ ///
+ UINT64 SuspendEnd;
+} EFI_ACPI_6_5_FPDT_S3_SUSPEND_RECORD;
+
+///
+/// Firmware Performance Record Table definition.
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+} EFI_ACPI_6_5_FIRMWARE_PERFORMANCE_RECORD_TABLE;
+
+///
+/// Generic Timer Description Table definition.
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT64 CntControlBasePhysicalAddress;
+ UINT32 Reserved;
+ UINT32 SecurePL1TimerGSIV;
+ UINT32 SecurePL1TimerFlags;
+ UINT32 NonSecurePL1TimerGSIV;
+ UINT32 NonSecurePL1TimerFlags;
+ UINT32 VirtualTimerGSIV;
+ UINT32 VirtualTimerFlags;
+ UINT32 NonSecurePL2TimerGSIV;
+ UINT32 NonSecurePL2TimerFlags;
+ UINT64 CntReadBasePhysicalAddress;
+ UINT32 PlatformTimerCount;
+ UINT32 PlatformTimerOffset;
+ UINT32 VirtualPL2TimerGSIV;
+ UINT32 VirtualPL2TimerFlags;
+} EFI_ACPI_6_5_GENERIC_TIMER_DESCRIPTION_TABLE;
+
+///
+/// GTDT Version (as defined in ACPI 6.5 spec.)
+///
+#define EFI_ACPI_6_5_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION 0x03
+
+///
+/// Timer Flags. All other bits are reserved and must be 0.
+///
+#define EFI_ACPI_6_5_GTDT_TIMER_FLAG_TIMER_INTERRUPT_MODE BIT0
+#define EFI_ACPI_6_5_GTDT_TIMER_FLAG_TIMER_INTERRUPT_POLARITY BIT1
+#define EFI_ACPI_6_5_GTDT_TIMER_FLAG_ALWAYS_ON_CAPABILITY BIT2
+
+///
+/// Platform Timer Type
+///
+#define EFI_ACPI_6_5_GTDT_GT_BLOCK 0
+#define EFI_ACPI_6_5_GTDT_ARM_GENERIC_WATCHDOG 1
+
+///
+/// GT Block Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT16 Length;
+ UINT8 Reserved;
+ UINT64 CntCtlBase;
+ UINT32 GTBlockTimerCount;
+ UINT32 GTBlockTimerOffset;
+} EFI_ACPI_6_5_GTDT_GT_BLOCK_STRUCTURE;
+
+///
+/// GT Block Timer Structure
+///
+typedef struct {
+ UINT8 GTFrameNumber;
+ UINT8 Reserved[3];
+ UINT64 CntBaseX;
+ UINT64 CntEL0BaseX;
+ UINT32 GTxPhysicalTimerGSIV;
+ UINT32 GTxPhysicalTimerFlags;
+ UINT32 GTxVirtualTimerGSIV;
+ UINT32 GTxVirtualTimerFlags;
+ UINT32 GTxCommonFlags;
+} EFI_ACPI_6_5_GTDT_GT_BLOCK_TIMER_STRUCTURE;
+
+///
+/// GT Block Physical Timers and Virtual Timers Flags. All other bits are reserved and must be 0.
+///
+#define EFI_ACPI_6_5_GTDT_GT_BLOCK_TIMER_FLAG_TIMER_INTERRUPT_MODE BIT0
+#define EFI_ACPI_6_5_GTDT_GT_BLOCK_TIMER_FLAG_TIMER_INTERRUPT_POLARITY BIT1
+
+///
+/// Common Flags Flags. All other bits are reserved and must be 0.
+///
+#define EFI_ACPI_6_5_GTDT_GT_BLOCK_COMMON_FLAG_SECURE_TIMER BIT0
+#define EFI_ACPI_6_5_GTDT_GT_BLOCK_COMMON_FLAG_ALWAYS_ON_CAPABILITY BIT1
+
+///
+/// Arm Generic Watchdog Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT16 Length;
+ UINT8 Reserved;
+ UINT64 RefreshFramePhysicalAddress;
+ UINT64 WatchdogControlFramePhysicalAddress;
+ UINT32 WatchdogTimerGSIV;
+ UINT32 WatchdogTimerFlags;
+} EFI_ACPI_6_5_GTDT_ARM_GENERIC_WATCHDOG_STRUCTURE;
+
+///
+/// Arm Generic Watchdog Timer Flags. All other bits are reserved and must be 0.
+///
+#define EFI_ACPI_6_5_GTDT_ARM_GENERIC_WATCHDOG_FLAG_TIMER_INTERRUPT_MODE BIT0
+#define EFI_ACPI_6_5_GTDT_ARM_GENERIC_WATCHDOG_FLAG_TIMER_INTERRUPT_POLARITY BIT1
+#define EFI_ACPI_6_5_GTDT_ARM_GENERIC_WATCHDOG_FLAG_SECURE_TIMER BIT2
+
+//
+// NVDIMM Firmware Interface Table definition.
+//
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 Reserved;
+} EFI_ACPI_6_5_NVDIMM_FIRMWARE_INTERFACE_TABLE;
+
+//
+// NFIT Version (as defined in ACPI 6.5 spec.)
+//
+#define EFI_ACPI_6_5_NVDIMM_FIRMWARE_INTERFACE_TABLE_REVISION 0x1
+
+//
+// Definition for NFIT Table Structure Types
+//
+#define EFI_ACPI_6_5_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_STRUCTURE_TYPE 0
+#define EFI_ACPI_6_5_NFIT_NVDIMM_REGION_MAPPING_STRUCTURE_TYPE 1
+#define EFI_ACPI_6_5_NFIT_INTERLEAVE_STRUCTURE_TYPE 2
+#define EFI_ACPI_6_5_NFIT_SMBIOS_MANAGEMENT_INFORMATION_STRUCTURE_TYPE 3
+#define EFI_ACPI_6_5_NFIT_NVDIMM_CONTROL_REGION_STRUCTURE_TYPE 4
+#define EFI_ACPI_6_5_NFIT_NVDIMM_BLOCK_DATA_WINDOW_REGION_STRUCTURE_TYPE 5
+#define EFI_ACPI_6_5_NFIT_FLUSH_HINT_ADDRESS_STRUCTURE_TYPE 6
+#define EFI_ACPI_6_5_NFIT_PLATFORM_CAPABILITIES_STRUCTURE_TYPE 7
+
+//
+// Definition for NFIT Structure Header
+//
+typedef struct {
+ UINT16 Type;
+ UINT16 Length;
+} EFI_ACPI_6_5_NFIT_STRUCTURE_HEADER;
+
+//
+// Definition for System Physical Address Range Structure
+//
+#define EFI_ACPI_6_5_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_FLAGS_CONTROL_REGION_FOR_MANAGEMENT BIT0
+#define EFI_ACPI_6_5_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_FLAGS_PROXIMITY_DOMAIN_VALID BIT1
+#define EFI_ACPI_6_5_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_FLAGS_SPA_LOCATION_COOKIE_VALID BIT2
+
+#define EFI_ACPI_6_5_NFIT_GUID_VOLATILE_MEMORY_REGION { 0x7305944F, 0xFDDA, 0x44E3, { 0xB1, 0x6C, 0x3F, 0x22, 0xD2, 0x52, 0xE5, 0xD0 }}
+#define EFI_ACPI_6_5_NFIT_GUID_BYTE_ADDRESSABLE_PERSISTENT_MEMORY_REGION { 0x66F0D379, 0xB4F3, 0x4074, { 0xAC, 0x43, 0x0D, 0x33, 0x18, 0xB7, 0x8C, 0xDB }}
+#define EFI_ACPI_6_5_NFIT_GUID_NVDIMM_CONTROL_REGION { 0x92F701F6, 0x13B4, 0x405D, { 0x91, 0x0B, 0x29, 0x93, 0x67, 0xE8, 0x23, 0x4C }}
+#define EFI_ACPI_6_5_NFIT_GUID_NVDIMM_BLOCK_DATA_WINDOW_REGION { 0x91AF0530, 0x5D86, 0x470E, { 0xA6, 0xB0, 0x0A, 0x2D, 0xB9, 0x40, 0x82, 0x49 }}
+#define EFI_ACPI_6_5_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_DISK_REGION_VOLATILE { 0x77AB535A, 0x45FC, 0x6.5B, { 0x55, 0x60, 0xF7, 0xB2, 0x81, 0xD1, 0xF9, 0x6E }}
+#define EFI_ACPI_6_5_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_CD_REGION_VOLATILE { 0x3D5ABD30, 0x4175, 0x87CE, { 0x6D, 0x64, 0xD2, 0xAD, 0xE5, 0x23, 0xC4, 0xBB }}
+#define EFI_ACPI_6_5_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_DISK_REGION_PERSISTENT { 0x5CEA02C9, 0x4D07, 0x69D3, { 0x26, 0x9F ,0x44, 0x96, 0xFB, 0xE0, 0x96, 0xF9 }}
+#define EFI_ACPI_6_5_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_CD_REGION_PERSISTENT { 0x08018188, 0x42CD, 0xBB48, { 0x10, 0x0F, 0x53, 0x87, 0xD5, 0x3D, 0xED, 0x3D }}
+
+typedef struct {
+ UINT16 Type;
+ UINT16 Length;
+ UINT16 SPARangeStructureIndex;
+ UINT16 Flags;
+ UINT32 Reserved_8;
+ UINT32 ProximityDomain;
+ GUID AddressRangeTypeGUID;
+ UINT64 SystemPhysicalAddressRangeBase;
+ UINT64 SystemPhysicalAddressRangeLength;
+ UINT64 AddressRangeMemoryMappingAttribute;
+ UINT64 SPALocationCookie;
+} EFI_ACPI_6_5_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_STRUCTURE;
+
+//
+// Definition for Memory Device to System Physical Address Range Mapping Structure
+//
+typedef struct {
+ UINT32 DIMMNumber : 4;
+ UINT32 MemoryChannelNumber : 4;
+ UINT32 MemoryControllerID : 4;
+ UINT32 SocketID : 4;
+ UINT32 NodeControllerID : 12;
+ UINT32 Reserved_28 : 4;
+} EFI_ACPI_6_5_NFIT_DEVICE_HANDLE;
+
+#define EFI_ACPI_6_5_NFIT_MEMORY_DEVICE_STATE_FLAGS_PREVIOUS_SAVE_FAIL BIT0
+#define EFI_ACPI_6_5_NFIT_MEMORY_DEVICE_STATE_FLAGS_LAST_RESTORE_FAIL BIT1
+#define EFI_ACPI_6_5_NFIT_MEMORY_DEVICE_STATE_FLAGS_PLATFORM_FLUSH_FAIL BIT2
+#define EFI_ACPI_6_5_NFIT_MEMORY_DEVICE_STATE_FLAGS_NOT_ARMED_PRIOR_TO_OSPM_HAND_OFF BIT3
+#define EFI_ACPI_6_5_NFIT_MEMORY_DEVICE_STATE_FLAGS_SMART_HEALTH_EVENTS_PRIOR_OSPM_HAND_OFF BIT4
+#define EFI_ACPI_6_5_NFIT_MEMORY_DEVICE_STATE_FLAGS_FIRMWARE_ENABLED_TO_NOTIFY_OSPM_ON_SMART_HEALTH_EVENTS BIT5
+#define EFI_ACPI_6_5_NFIT_MEMORY_DEVICE_STATE_FLAGS_FIRMWARE_NOT_MAP_NVDIMM_TO_SPA BIT6
+
+typedef struct {
+ UINT16 Type;
+ UINT16 Length;
+ EFI_ACPI_6_5_NFIT_DEVICE_HANDLE NFITDeviceHandle;
+ UINT16 NVDIMMPhysicalID;
+ UINT16 NVDIMMRegionID;
+ UINT16 SPARangeStructureIndex;
+ UINT16 NVDIMMControlRegionStructureIndex;
+ UINT64 NVDIMMRegionSize;
+ UINT64 RegionOffset;
+ UINT64 NVDIMMPhysicalAddressRegionBase;
+ UINT16 InterleaveStructureIndex;
+ UINT16 InterleaveWays;
+ UINT16 NVDIMMStateFlags;
+ UINT16 Reserved_46;
+} EFI_ACPI_6_5_NFIT_NVDIMM_REGION_MAPPING_STRUCTURE;
+
+//
+// Definition for Interleave Structure
+//
+typedef struct {
+ UINT16 Type;
+ UINT16 Length;
+ UINT16 InterleaveStructureIndex;
+ UINT16 Reserved_6;
+ UINT32 NumberOfLines;
+ UINT32 LineSize;
+ // UINT32 LineOffset[NumberOfLines];
+} EFI_ACPI_6_5_NFIT_INTERLEAVE_STRUCTURE;
+
+//
+// Definition for SMBIOS Management Information Structure
+//
+typedef struct {
+ UINT16 Type;
+ UINT16 Length;
+ UINT32 Reserved_4;
+ // UINT8 Data[];
+} EFI_ACPI_6_5_NFIT_SMBIOS_MANAGEMENT_INFORMATION_STRUCTURE;
+
+//
+// Definition for NVDIMM Control Region Structure
+//
+#define EFI_ACPI_6_5_NFIT_NVDIMM_CONTROL_REGION_VALID_FIELDS_MANUFACTURING BIT0
+
+#define EFI_ACPI_6_5_NFIT_NVDIMM_CONTROL_REGION_FLAGS_BLOCK_DATA_WINDOWS_BUFFERED BIT0
+
+typedef struct {
+ UINT16 Type;
+ UINT16 Length;
+ UINT16 NVDIMMControlRegionStructureIndex;
+ UINT16 VendorID;
+ UINT16 DeviceID;
+ UINT16 RevisionID;
+ UINT16 SubsystemVendorID;
+ UINT16 SubsystemDeviceID;
+ UINT16 SubsystemRevisionID;
+ UINT8 ValidFields;
+ UINT8 ManufacturingLocation;
+ UINT16 ManufacturingDate;
+ UINT8 Reserved_22[2];
+ UINT32 SerialNumber;
+ UINT16 RegionFormatInterfaceCode;
+ UINT16 NumberOfBlockControlWindows;
+ UINT64 SizeOfBlockControlWindow;
+ UINT64 CommandRegisterOffsetInBlockControlWindow;
+ UINT64 SizeOfCommandRegisterInBlockControlWindows;
+ UINT64 StatusRegisterOffsetInBlockControlWindow;
+ UINT64 SizeOfStatusRegisterInBlockControlWindows;
+ UINT16 NVDIMMControlRegionFlag;
+ UINT8 Reserved_74[6];
+} EFI_ACPI_6_5_NFIT_NVDIMM_CONTROL_REGION_STRUCTURE;
+
+//
+// Definition for NVDIMM Block Data Window Region Structure
+//
+typedef struct {
+ UINT16 Type;
+ UINT16 Length;
+ UINT16 NVDIMMControlRegionStructureIndex;
+ UINT16 NumberOfBlockDataWindows;
+ UINT64 BlockDataWindowStartOffset;
+ UINT64 SizeOfBlockDataWindow;
+ UINT64 BlockAccessibleMemoryCapacity;
+ UINT64 BeginningAddressOfFirstBlockInBlockAccessibleMemory;
+} EFI_ACPI_6_5_NFIT_NVDIMM_BLOCK_DATA_WINDOW_REGION_STRUCTURE;
+
+//
+// Definition for Flush Hint Address Structure
+//
+typedef struct {
+ UINT16 Type;
+ UINT16 Length;
+ EFI_ACPI_6_5_NFIT_DEVICE_HANDLE NFITDeviceHandle;
+ UINT16 NumberOfFlushHintAddresses;
+ UINT8 Reserved_10[6];
+ // UINT64 FlushHintAddress[NumberOfFlushHintAddresses];
+} EFI_ACPI_6_5_NFIT_FLUSH_HINT_ADDRESS_STRUCTURE;
+
+//
+// Definition for Platform Capabilities Structure
+//
+typedef struct {
+ UINT16 Type;
+ UINT16 Length;
+ UINT8 HighestValidCapability;
+ UINT8 Reserved_5[3];
+ UINT32 Capabilities;
+ UINT8 Reserved_12[4];
+} EFI_ACPI_6_5_NFIT_PLATFORM_CAPABILITIES_STRUCTURE;
+
+#define EFI_ACPI_6_5_NFIT_PLATFORM_CAPABILITY_CPU_CACHE_FLUSH_TO_NVDIMM_DURABILITY_ON_POWER_LOSS BIT0
+#define EFI_ACPI_6_5_NFIT_PLATFORM_CAPABILITY_MEMORY_CONTROLLER_FLUSH_TO_NVDIMM_DURABILITY_ON_POWER_LOSS BIT1
+#define EFI_ACPI_6_5_NFIT_PLATFORM_CAPABILITY_BYTE_ADDRESSABLE_PERSISTENT_MEMORY_HARDWARE_MIRRORING BIT2
+
+///
+/// Secure DEVices Table (SDEV)
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+} EFI_ACPI_6_5_SECURE_DEVICES_TABLE_HEADER;
+
+///
+/// SDEV Revision (as defined in ACPI 6.5 spec.)
+///
+#define EFI_ACPI_6_5_SECURE_DEVICES_TABLE_REVISION 0x01
+
+///
+/// Secure Device types
+///
+#define EFI_ACPI_6_5_SDEV_TYPE_ACPI_NAMESPACE_DEVICE 0x00
+#define EFI_ACPI_6_5_SDEV_TYPE_PCIE_ENDPOINT_DEVICE 0x01
+
+///
+/// Secure Device flags
+///
+#define EFI_ACPI_6_5_SDEV_FLAG_ALLOW_HANDOFF BIT0
+#define EFI_ACPI_6_5_SDEV_FLAG_SECURE_ACCESS_COMPONENTS_PRESENT BIT1
+
+///
+/// SDEV Structure Header
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Flags;
+ UINT16 Length;
+} EFI_ACPI_6_5_SDEV_STRUCTURE_HEADER;
+
+///
+/// ACPI_NAMESPACE_DEVICE based Secure Device Structure
+///
+typedef struct {
+ EFI_ACPI_6_5_SDEV_STRUCTURE_HEADER Header;
+ UINT16 DeviceIdentifierOffset;
+ UINT16 DeviceIdentifierLength;
+ UINT16 VendorSpecificDataOffset;
+ UINT16 VendorSpecificDataLength;
+ UINT16 SecureAccessComponentsOffset;
+ UINT16 SecureAccessComponentsLength;
+} EFI_ACPI_6_5_SDEV_STRUCTURE_ACPI_NAMESPACE_DEVICE;
+
+///
+/// Secure Access Component Types
+///
+#define EFI_ACPI_6_5_SDEV_SECURE_ACCESS_COMPONENT_TYPE_IDENTIFICATION 0x00
+#define EFI_ACPI_6_5_SDEV_SECURE_ACCESS_COMPONENT_TYPE_MEMORY 0x01
+
+///
+/// Identification Based Secure Access Component
+///
+typedef struct {
+ EFI_ACPI_6_5_SDEV_STRUCTURE_HEADER Header;
+ UINT16 HardwareIdentifierOffset;
+ UINT16 HardwareIdentifierLength;
+ UINT16 SubsystemIdentifierOffset;
+ UINT16 SubsystemIdentifierLength;
+ UINT16 HardwareRevision;
+ UINT8 HardwareRevisionPresent;
+ UINT8 ClassCodePresent;
+ UINT8 PciCompatibleBaseClass;
+ UINT8 PciCompatibleSubClass;
+ UINT8 PciCompatibleProgrammingInterface;
+} EFI_ACPI_6_5_SDEV_SECURE_ACCESS_COMPONENT_IDENTIFICATION_STRUCTURE;
+
+///
+/// Memory-based Secure Access Component
+///
+typedef struct {
+ EFI_ACPI_6_5_SDEV_STRUCTURE_HEADER Header;
+ UINT32 Reserved;
+ UINT64 MemoryAddressBase;
+ UINT64 MemoryLength;
+} EFI_ACPI_6_5_SDEV_SECURE_ACCESS_COMPONENT_MEMORY_STRUCTURE;
+
+///
+/// PCIe Endpoint Device based Secure Device Structure
+///
+typedef struct {
+ EFI_ACPI_6_5_SDEV_STRUCTURE_HEADER Header;
+ UINT16 PciSegmentNumber;
+ UINT16 StartBusNumber;
+ UINT16 PciPathOffset;
+ UINT16 PciPathLength;
+ UINT16 VendorSpecificDataOffset;
+ UINT16 VendorSpecificDataLength;
+} EFI_ACPI_6_5_SDEV_STRUCTURE_PCIE_ENDPOINT_DEVICE;
+
+///
+/// Boot Error Record Table (BERT)
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 BootErrorRegionLength;
+ UINT64 BootErrorRegion;
+} EFI_ACPI_6_5_BOOT_ERROR_RECORD_TABLE_HEADER;
+
+///
+/// BERT Version (as defined in ACPI 6.5 spec.)
+///
+#define EFI_ACPI_6_5_BOOT_ERROR_RECORD_TABLE_REVISION 0x01
+
+///
+/// Boot Error Region Block Status Definition
+///
+typedef struct {
+ UINT32 UncorrectableErrorValid : 1;
+ UINT32 CorrectableErrorValid : 1;
+ UINT32 MultipleUncorrectableErrors : 1;
+ UINT32 MultipleCorrectableErrors : 1;
+ UINT32 ErrorDataEntryCount : 10;
+ UINT32 Reserved : 18;
+} EFI_ACPI_6_5_ERROR_BLOCK_STATUS;
+
+///
+/// Boot Error Region Definition
+///
+typedef struct {
+ EFI_ACPI_6_5_ERROR_BLOCK_STATUS BlockStatus;
+ UINT32 RawDataOffset;
+ UINT32 RawDataLength;
+ UINT32 DataLength;
+ UINT32 ErrorSeverity;
+} EFI_ACPI_6_5_BOOT_ERROR_REGION_STRUCTURE;
+
+//
+// Boot Error Severity types
+//
+#define EFI_ACPI_6_5_ERROR_SEVERITY_RECOVERABLE 0x00
+#define EFI_ACPI_6_5_ERROR_SEVERITY_FATAL 0x01
+#define EFI_ACPI_6_5_ERROR_SEVERITY_CORRECTED 0x02
+#define EFI_ACPI_6_5_ERROR_SEVERITY_NONE 0x03
+//
+// The term 'Correctable' is no longer being used as an error severity of the
+// reported error since ACPI Specification Version 5.1 Errata B.
+// The below macro is considered as deprecated and should no longer be used.
+//
+#define EFI_ACPI_6_5_ERROR_SEVERITY_CORRECTABLE 0x00
+
+///
+/// Generic Error Data Entry Definition
+///
+typedef struct {
+ UINT8 SectionType[16];
+ UINT32 ErrorSeverity;
+ UINT16 Revision;
+ UINT8 ValidationBits;
+ UINT8 Flags;
+ UINT32 ErrorDataLength;
+ UINT8 FruId[16];
+ UINT8 FruText[20];
+ UINT8 Timestamp[8];
+} EFI_ACPI_6_5_GENERIC_ERROR_DATA_ENTRY_STRUCTURE;
+
+///
+/// Generic Error Data Entry Version (as defined in ACPI 6.5 spec.)
+///
+#define EFI_ACPI_6_5_GENERIC_ERROR_DATA_ENTRY_REVISION 0x0300
+
+///
+/// HEST - Hardware Error Source Table
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 ErrorSourceCount;
+} EFI_ACPI_6_5_HARDWARE_ERROR_SOURCE_TABLE_HEADER;
+
+///
+/// HEST Version (as defined in ACPI 6.5 spec.)
+///
+#define EFI_ACPI_6_5_HARDWARE_ERROR_SOURCE_TABLE_REVISION 0x01
+
+//
+// Error Source structure types.
+//
+#define EFI_ACPI_6_5_IA32_ARCHITECTURE_MACHINE_CHECK_EXCEPTION 0x00
+#define EFI_ACPI_6_5_IA32_ARCHITECTURE_CORRECTED_MACHINE_CHECK 0x01
+#define EFI_ACPI_6_5_IA32_ARCHITECTURE_NMI_ERROR 0x02
+#define EFI_ACPI_6_5_PCI_EXPRESS_ROOT_PORT_AER 0x06
+#define EFI_ACPI_6_5_PCI_EXPRESS_DEVICE_AER 0x07
+#define EFI_ACPI_6_5_PCI_EXPRESS_BRIDGE_AER 0x08
+#define EFI_ACPI_6_5_GENERIC_HARDWARE_ERROR 0x09
+#define EFI_ACPI_6_5_GENERIC_HARDWARE_ERROR_VERSION_2 0x0A
+#define EFI_ACPI_6_5_IA32_ARCHITECTURE_DEFERRED_MACHINE_CHECK 0x0B
+
+//
+// Error Source structure flags.
+//
+#define EFI_ACPI_6_5_ERROR_SOURCE_FLAG_FIRMWARE_FIRST (1 << 0)
+#define EFI_ACPI_6_5_ERROR_SOURCE_FLAG_GLOBAL (1 << 1)
+#define EFI_ACPI_6_5_ERROR_SOURCE_FLAG_GHES_ASSIST (1 << 2)
+
+///
+/// IA-32 Architecture Machine Check Exception Structure Definition
+///
+typedef struct {
+ UINT16 Type;
+ UINT16 SourceId;
+ UINT8 Reserved0[2];
+ UINT8 Flags;
+ UINT8 Enabled;
+ UINT32 NumberOfRecordsToPreAllocate;
+ UINT32 MaxSectionsPerRecord;
+ UINT64 GlobalCapabilityInitData;
+ UINT64 GlobalControlInitData;
+ UINT8 NumberOfHardwareBanks;
+ UINT8 Reserved1[7];
+} EFI_ACPI_6_5_IA32_ARCHITECTURE_MACHINE_CHECK_EXCEPTION_STRUCTURE;
+
+///
+/// IA-32 Architecture Machine Check Bank Structure Definition
+///
+typedef struct {
+ UINT8 BankNumber;
+ UINT8 ClearStatusOnInitialization;
+ UINT8 StatusDataFormat;
+ UINT8 Reserved0;
+ UINT32 ControlRegisterMsrAddress;
+ UINT64 ControlInitData;
+ UINT32 StatusRegisterMsrAddress;
+ UINT32 AddressRegisterMsrAddress;
+ UINT32 MiscRegisterMsrAddress;
+} EFI_ACPI_6_5_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_BANK_STRUCTURE;
+
+///
+/// IA-32 Architecture Machine Check Bank Structure MCA data format
+///
+#define EFI_ACPI_6_5_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_IA32 0x00
+#define EFI_ACPI_6_5_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_INTEL64 0x01
+#define EFI_ACPI_6_5_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_AMD64 0x02
+
+//
+// Hardware Error Notification types. All other values are reserved
+//
+#define EFI_ACPI_6_5_HARDWARE_ERROR_NOTIFICATION_POLLED 0x00
+#define EFI_ACPI_6_5_HARDWARE_ERROR_NOTIFICATION_EXTERNAL_INTERRUPT 0x01
+#define EFI_ACPI_6_5_HARDWARE_ERROR_NOTIFICATION_LOCAL_INTERRUPT 0x02
+#define EFI_ACPI_6_5_HARDWARE_ERROR_NOTIFICATION_SCI 0x03
+#define EFI_ACPI_6_5_HARDWARE_ERROR_NOTIFICATION_NMI 0x04
+#define EFI_ACPI_6_5_HARDWARE_ERROR_NOTIFICATION_CMCI 0x05
+#define EFI_ACPI_6_5_HARDWARE_ERROR_NOTIFICATION_MCE 0x06
+#define EFI_ACPI_6_5_HARDWARE_ERROR_NOTIFICATION_GPIO_SIGNAL 0x07
+#define EFI_ACPI_6_5_HARDWARE_ERROR_NOTIFICATION_ARMV8_SEA 0x08
+#define EFI_ACPI_6_5_HARDWARE_ERROR_NOTIFICATION_ARMV8_SEI 0x09
+#define EFI_ACPI_6_5_HARDWARE_ERROR_NOTIFICATION_GSIV 0x0A
+#define EFI_ACPI_6_5_HARDWARE_ERROR_NOTIFICATION_SOFTWARE_DELEGATED_EXCEPTION 0x0B
+
+///
+/// Hardware Error Notification Configuration Write Enable Structure Definition
+///
+typedef struct {
+ UINT16 Type : 1;
+ UINT16 PollInterval : 1;
+ UINT16 SwitchToPollingThresholdValue : 1;
+ UINT16 SwitchToPollingThresholdWindow : 1;
+ UINT16 ErrorThresholdValue : 1;
+ UINT16 ErrorThresholdWindow : 1;
+ UINT16 Reserved : 10;
+} EFI_ACPI_6_5_HARDWARE_ERROR_NOTIFICATION_CONFIGURATION_WRITE_ENABLE_STRUCTURE;
+
+///
+/// Hardware Error Notification Structure Definition
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ EFI_ACPI_6_5_HARDWARE_ERROR_NOTIFICATION_CONFIGURATION_WRITE_ENABLE_STRUCTURE ConfigurationWriteEnable;
+ UINT32 PollInterval;
+ UINT32 Vector;
+ UINT32 SwitchToPollingThresholdValue;
+ UINT32 SwitchToPollingThresholdWindow;
+ UINT32 ErrorThresholdValue;
+ UINT32 ErrorThresholdWindow;
+} EFI_ACPI_6_5_HARDWARE_ERROR_NOTIFICATION_STRUCTURE;
+
+///
+/// IA-32 Architecture Corrected Machine Check Structure Definition
+///
+typedef struct {
+ UINT16 Type;
+ UINT16 SourceId;
+ UINT8 Reserved0[2];
+ UINT8 Flags;
+ UINT8 Enabled;
+ UINT32 NumberOfRecordsToPreAllocate;
+ UINT32 MaxSectionsPerRecord;
+ EFI_ACPI_6_5_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure;
+ UINT8 NumberOfHardwareBanks;
+ UINT8 Reserved1[3];
+} EFI_ACPI_6_5_IA32_ARCHITECTURE_CORRECTED_MACHINE_CHECK_STRUCTURE;
+
+///
+/// IA-32 Architecture NMI Error Structure Definition
+///
+typedef struct {
+ UINT16 Type;
+ UINT16 SourceId;
+ UINT8 Reserved0[2];
+ UINT32 NumberOfRecordsToPreAllocate;
+ UINT32 MaxSectionsPerRecord;
+ UINT32 MaxRawDataLength;
+} EFI_ACPI_6_5_IA32_ARCHITECTURE_NMI_ERROR_STRUCTURE;
+
+///
+/// PCI Express Root Port AER Structure Definition
+///
+typedef struct {
+ UINT16 Type;
+ UINT16 SourceId;
+ UINT8 Reserved0[2];
+ UINT8 Flags;
+ UINT8 Enabled;
+ UINT32 NumberOfRecordsToPreAllocate;
+ UINT32 MaxSectionsPerRecord;
+ UINT32 Bus;
+ UINT16 Device;
+ UINT16 Function;
+ UINT16 DeviceControl;
+ UINT8 Reserved1[2];
+ UINT32 UncorrectableErrorMask;
+ UINT32 UncorrectableErrorSeverity;
+ UINT32 CorrectableErrorMask;
+ UINT32 AdvancedErrorCapabilitiesAndControl;
+ UINT32 RootErrorCommand;
+} EFI_ACPI_6_5_PCI_EXPRESS_ROOT_PORT_AER_STRUCTURE;
+
+///
+/// PCI Express Device AER Structure Definition
+///
+typedef struct {
+ UINT16 Type;
+ UINT16 SourceId;
+ UINT8 Reserved0[2];
+ UINT8 Flags;
+ UINT8 Enabled;
+ UINT32 NumberOfRecordsToPreAllocate;
+ UINT32 MaxSectionsPerRecord;
+ UINT32 Bus;
+ UINT16 Device;
+ UINT16 Function;
+ UINT16 DeviceControl;
+ UINT8 Reserved1[2];
+ UINT32 UncorrectableErrorMask;
+ UINT32 UncorrectableErrorSeverity;
+ UINT32 CorrectableErrorMask;
+ UINT32 AdvancedErrorCapabilitiesAndControl;
+} EFI_ACPI_6_5_PCI_EXPRESS_DEVICE_AER_STRUCTURE;
+
+///
+/// PCI Express Bridge AER Structure Definition
+///
+typedef struct {
+ UINT16 Type;
+ UINT16 SourceId;
+ UINT8 Reserved0[2];
+ UINT8 Flags;
+ UINT8 Enabled;
+ UINT32 NumberOfRecordsToPreAllocate;
+ UINT32 MaxSectionsPerRecord;
+ UINT32 Bus;
+ UINT16 Device;
+ UINT16 Function;
+ UINT16 DeviceControl;
+ UINT8 Reserved1[2];
+ UINT32 UncorrectableErrorMask;
+ UINT32 UncorrectableErrorSeverity;
+ UINT32 CorrectableErrorMask;
+ UINT32 AdvancedErrorCapabilitiesAndControl;
+ UINT32 SecondaryUncorrectableErrorMask;
+ UINT32 SecondaryUncorrectableErrorSeverity;
+ UINT32 SecondaryAdvancedErrorCapabilitiesAndControl;
+} EFI_ACPI_6_5_PCI_EXPRESS_BRIDGE_AER_STRUCTURE;
+
+///
+/// Generic Hardware Error Source Structure Definition
+///
+typedef struct {
+ UINT16 Type;
+ UINT16 SourceId;
+ UINT16 RelatedSourceId;
+ UINT8 Flags;
+ UINT8 Enabled;
+ UINT32 NumberOfRecordsToPreAllocate;
+ UINT32 MaxSectionsPerRecord;
+ UINT32 MaxRawDataLength;
+ EFI_ACPI_6_5_GENERIC_ADDRESS_STRUCTURE ErrorStatusAddress;
+ EFI_ACPI_6_5_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure;
+ UINT32 ErrorStatusBlockLength;
+} EFI_ACPI_6_5_GENERIC_HARDWARE_ERROR_SOURCE_STRUCTURE;
+
+///
+/// Generic Hardware Error Source Version 2 Structure Definition
+///
+typedef struct {
+ UINT16 Type;
+ UINT16 SourceId;
+ UINT16 RelatedSourceId;
+ UINT8 Flags;
+ UINT8 Enabled;
+ UINT32 NumberOfRecordsToPreAllocate;
+ UINT32 MaxSectionsPerRecord;
+ UINT32 MaxRawDataLength;
+ EFI_ACPI_6_5_GENERIC_ADDRESS_STRUCTURE ErrorStatusAddress;
+ EFI_ACPI_6_5_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure;
+ UINT32 ErrorStatusBlockLength;
+ EFI_ACPI_6_5_GENERIC_ADDRESS_STRUCTURE ReadAckRegister;
+ UINT64 ReadAckPreserve;
+ UINT64 ReadAckWrite;
+} EFI_ACPI_6_5_GENERIC_HARDWARE_ERROR_SOURCE_VERSION_2_STRUCTURE;
+
+///
+/// Generic Error Status Definition
+///
+typedef struct {
+ EFI_ACPI_6_5_ERROR_BLOCK_STATUS BlockStatus;
+ UINT32 RawDataOffset;
+ UINT32 RawDataLength;
+ UINT32 DataLength;
+ UINT32 ErrorSeverity;
+} EFI_ACPI_6_5_GENERIC_ERROR_STATUS_STRUCTURE;
+
+///
+/// IA-32 Architecture Deferred Machine Check Structure Definition
+///
+typedef struct {
+ UINT16 Type;
+ UINT16 SourceId;
+ UINT8 Reserved0[2];
+ UINT8 Flags;
+ UINT8 Enabled;
+ UINT32 NumberOfRecordsToPreAllocate;
+ UINT32 MaxSectionsPerRecord;
+ EFI_ACPI_6_5_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure;
+ UINT8 NumberOfHardwareBanks;
+ UINT8 Reserved1[3];
+} EFI_ACPI_6_5_IA32_ARCHITECTURE_DEFERRED_MACHINE_CHECK_STRUCTURE;
+
+///
+/// HMAT - Heterogeneous Memory Attribute Table
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT8 Reserved[4];
+} EFI_ACPI_6_5_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_HEADER;
+
+///
+/// HMAT Revision (as defined in ACPI 6.5 spec.)
+///
+#define EFI_ACPI_6_5_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_REVISION 0x02
+
+///
+/// HMAT types
+///
+#define EFI_ACPI_6_5_HMAT_TYPE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES 0x00
+#define EFI_ACPI_6_5_HMAT_TYPE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO 0x01
+#define EFI_ACPI_6_5_HMAT_TYPE_MEMORY_SIDE_CACHE_INFO 0x02
+
+///
+/// HMAT Structure Header
+///
+typedef struct {
+ UINT16 Type;
+ UINT8 Reserved[2];
+ UINT32 Length;
+} EFI_ACPI_6_5_HMAT_STRUCTURE_HEADER;
+
+///
+/// Memory Proximity Domain Attributes Structure flags
+///
+typedef struct {
+ UINT16 InitiatorProximityDomainValid : 1;
+ UINT16 Reserved : 15;
+} EFI_ACPI_6_5_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES_FLAGS;
+
+///
+/// Memory Proximity Domain Attributes Structure
+///
+typedef struct {
+ UINT16 Type;
+ UINT8 Reserved[2];
+ UINT32 Length;
+ EFI_ACPI_6_5_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES_FLAGS Flags;
+ UINT8 Reserved1[2];
+ UINT32 InitiatorProximityDomain;
+ UINT32 MemoryProximityDomain;
+ UINT8 Reserved2[20];
+} EFI_ACPI_6_5_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES;
+
+///
+/// System Locality Latency and Bandwidth Information Structure flags
+///
+typedef struct {
+ UINT8 MemoryHierarchy : 4;
+ UINT8 AccessAttributes : 2;
+ UINT8 Reserved : 2;
+} EFI_ACPI_6_5_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO_FLAGS;
+
+///
+/// System Locality Latency and Bandwidth Information Structure
+///
+typedef struct {
+ UINT16 Type;
+ UINT8 Reserved[2];
+ UINT32 Length;
+ EFI_ACPI_6_5_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO_FLAGS Flags;
+ UINT8 DataType;
+ UINT8 MinTransferSize;
+ UINT8 Reserved1;
+ UINT32 NumberOfInitiatorProximityDomains;
+ UINT32 NumberOfTargetProximityDomains;
+ UINT8 Reserved2[4];
+ UINT64 EntryBaseUnit;
+} EFI_ACPI_6_5_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO;
+
+///
+/// Memory Side Cache Information Structure cache attributes
+///
+typedef struct {
+ UINT32 TotalCacheLevels : 4;
+ UINT32 CacheLevel : 4;
+ UINT32 CacheAssociativity : 4;
+ UINT32 WritePolicy : 4;
+ UINT32 CacheLineSize : 16;
+} EFI_ACPI_6_5_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_CACHE_ATTRIBUTES;
+
+///
+/// Memory Side Cache Information Structure
+///
+typedef struct {
+ UINT16 Type;
+ UINT8 Reserved[2];
+ UINT32 Length;
+ UINT32 MemoryProximityDomain;
+ UINT8 Reserved1[4];
+ UINT64 MemorySideCacheSize;
+ EFI_ACPI_6_5_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_CACHE_ATTRIBUTES CacheAttributes;
+ UINT8 Reserved2[2];
+ UINT16 NumberOfSmbiosHandles;
+} EFI_ACPI_6_5_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO;
+
+///
+/// ERST - Error Record Serialization Table
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 SerializationHeaderSize;
+ UINT8 Reserved0[4];
+ UINT32 InstructionEntryCount;
+} EFI_ACPI_6_5_ERROR_RECORD_SERIALIZATION_TABLE_HEADER;
+
+///
+/// ERST Version (as defined in ACPI 6.5 spec.)
+///
+#define EFI_ACPI_6_5_ERROR_RECORD_SERIALIZATION_TABLE_REVISION 0x01
+
+///
+/// ERST Serialization Actions
+///
+#define EFI_ACPI_6_5_ERST_BEGIN_WRITE_OPERATION 0x00
+#define EFI_ACPI_6_5_ERST_BEGIN_READ_OPERATION 0x01
+#define EFI_ACPI_6_5_ERST_BEGIN_CLEAR_OPERATION 0x02
+#define EFI_ACPI_6_5_ERST_END_OPERATION 0x03
+#define EFI_ACPI_6_5_ERST_SET_RECORD_OFFSET 0x04
+#define EFI_ACPI_6_5_ERST_EXECUTE_OPERATION 0x05
+#define EFI_ACPI_6_5_ERST_CHECK_BUSY_STATUS 0x06
+#define EFI_ACPI_6_5_ERST_GET_COMMAND_STATUS 0x07
+#define EFI_ACPI_6_5_ERST_GET_RECORD_IDENTIFIER 0x08
+#define EFI_ACPI_6_5_ERST_SET_RECORD_IDENTIFIER 0x09
+#define EFI_ACPI_6_5_ERST_GET_RECORD_COUNT 0x0A
+#define EFI_ACPI_6_5_ERST_BEGIN_DUMMY_WRITE_OPERATION 0x0B
+#define EFI_ACPI_6_5_ERST_GET_ERROR_LOG_ADDRESS_RANGE 0x0D
+#define EFI_ACPI_6_5_ERST_GET_ERROR_LOG_ADDRESS_RANGE_LENGTH 0x0E
+#define EFI_ACPI_6_5_ERST_GET_ERROR_LOG_ADDRESS_RANGE_ATTRIBUTES 0x0F
+#define EFI_ACPI_6_5_ERST_GET_EXECUTE_OPERATION_TIMINGS 0x10
+
+///
+/// ERST Action Command Status
+///
+#define EFI_ACPI_6_5_ERST_STATUS_SUCCESS 0x00
+#define EFI_ACPI_6_5_ERST_STATUS_NOT_ENOUGH_SPACE 0x01
+#define EFI_ACPI_6_5_ERST_STATUS_HARDWARE_NOT_AVAILABLE 0x02
+#define EFI_ACPI_6_5_ERST_STATUS_FAILED 0x03
+#define EFI_ACPI_6_5_ERST_STATUS_RECORD_STORE_EMPTY 0x04
+#define EFI_ACPI_6_5_ERST_STATUS_RECORD_NOT_FOUND 0x05
+
+///
+/// ERST Serialization Instructions
+///
+#define EFI_ACPI_6_5_ERST_READ_REGISTER 0x00
+#define EFI_ACPI_6_5_ERST_READ_REGISTER_VALUE 0x01
+#define EFI_ACPI_6_5_ERST_WRITE_REGISTER 0x02
+#define EFI_ACPI_6_5_ERST_WRITE_REGISTER_VALUE 0x03
+#define EFI_ACPI_6_5_ERST_NOOP 0x04
+#define EFI_ACPI_6_5_ERST_LOAD_VAR1 0x05
+#define EFI_ACPI_6_5_ERST_LOAD_VAR2 0x06
+#define EFI_ACPI_6_5_ERST_STORE_VAR1 0x07
+#define EFI_ACPI_6_5_ERST_ADD 0x08
+#define EFI_ACPI_6_5_ERST_SUBTRACT 0x09
+#define EFI_ACPI_6_5_ERST_ADD_VALUE 0x0A
+#define EFI_ACPI_6_5_ERST_SUBTRACT_VALUE 0x0B
+#define EFI_ACPI_6_5_ERST_STALL 0x0C
+#define EFI_ACPI_6_5_ERST_STALL_WHILE_TRUE 0x0D
+#define EFI_ACPI_6_5_ERST_SKIP_NEXT_INSTRUCTION_IF_TRUE 0x0E
+#define EFI_ACPI_6_5_ERST_GOTO 0x0F
+#define EFI_ACPI_6_5_ERST_SET_SRC_ADDRESS_BASE 0x10
+#define EFI_ACPI_6_5_ERST_SET_DST_ADDRESS_BASE 0x11
+#define EFI_ACPI_6_5_ERST_MOVE_DATA 0x12
+
+///
+/// ERST Instruction Flags
+///
+#define EFI_ACPI_6_5_ERST_PRESERVE_REGISTER 0x01
+
+///
+/// ERST Serialization Instruction Entry
+///
+typedef struct {
+ UINT8 SerializationAction;
+ UINT8 Instruction;
+ UINT8 Flags;
+ UINT8 Reserved0;
+ EFI_ACPI_6_5_GENERIC_ADDRESS_STRUCTURE RegisterRegion;
+ UINT64 Value;
+ UINT64 Mask;
+} EFI_ACPI_6_5_ERST_SERIALIZATION_INSTRUCTION_ENTRY;
+
+///
+/// EINJ - Error Injection Table
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 InjectionHeaderSize;
+ UINT8 InjectionFlags;
+ UINT8 Reserved0[3];
+ UINT32 InjectionEntryCount;
+} EFI_ACPI_6_5_ERROR_INJECTION_TABLE_HEADER;
+
+///
+/// EINJ Version (as defined in ACPI 6.5 spec.)
+///
+#define EFI_ACPI_6_5_ERROR_INJECTION_TABLE_REVISION 0x01
+
+///
+/// EINJ Error Injection Actions
+///
+#define EFI_ACPI_6_5_EINJ_BEGIN_INJECTION_OPERATION 0x00
+#define EFI_ACPI_6_5_EINJ_GET_TRIGGER_ERROR_ACTION_TABLE 0x01
+#define EFI_ACPI_6_5_EINJ_SET_ERROR_TYPE 0x02
+#define EFI_ACPI_6_5_EINJ_GET_ERROR_TYPE 0x03
+#define EFI_ACPI_6_5_EINJ_END_OPERATION 0x04
+#define EFI_ACPI_6_5_EINJ_EXECUTE_OPERATION 0x05
+#define EFI_ACPI_6_5_EINJ_CHECK_BUSY_STATUS 0x06
+#define EFI_ACPI_6_5_EINJ_GET_COMMAND_STATUS 0x07
+#define EFI_ACPI_6_5_EINJ_TRIGGER_ERROR 0xFF
+
+///
+/// EINJ Action Command Status
+///
+#define EFI_ACPI_6_5_EINJ_STATUS_SUCCESS 0x00
+#define EFI_ACPI_6_5_EINJ_STATUS_UNKNOWN_FAILURE 0x01
+#define EFI_ACPI_6_5_EINJ_STATUS_INVALID_ACCESS 0x02
+
+///
+/// EINJ Error Type Definition
+///
+#define EFI_ACPI_6_5_EINJ_ERROR_PROCESSOR_CORRECTABLE (1 << 0)
+#define EFI_ACPI_6_5_EINJ_ERROR_PROCESSOR_UNCORRECTABLE_NONFATAL (1 << 1)
+#define EFI_ACPI_6_5_EINJ_ERROR_PROCESSOR_UNCORRECTABLE_FATAL (1 << 2)
+#define EFI_ACPI_6_5_EINJ_ERROR_MEMORY_CORRECTABLE (1 << 3)
+#define EFI_ACPI_6_5_EINJ_ERROR_MEMORY_UNCORRECTABLE_NONFATAL (1 << 4)
+#define EFI_ACPI_6_5_EINJ_ERROR_MEMORY_UNCORRECTABLE_FATAL (1 << 5)
+#define EFI_ACPI_6_5_EINJ_ERROR_PCI_EXPRESS_CORRECTABLE (1 << 6)
+#define EFI_ACPI_6_5_EINJ_ERROR_PCI_EXPRESS_UNCORRECTABLE_NONFATAL (1 << 7)
+#define EFI_ACPI_6_5_EINJ_ERROR_PCI_EXPRESS_UNCORRECTABLE_FATAL (1 << 8)
+#define EFI_ACPI_6_5_EINJ_ERROR_PLATFORM_CORRECTABLE (1 << 9)
+#define EFI_ACPI_6_5_EINJ_ERROR_PLATFORM_UNCORRECTABLE_NONFATAL (1 << 10)
+#define EFI_ACPI_6_5_EINJ_ERROR_PLATFORM_UNCORRECTABLE_FATAL (1 << 11)
+
+///
+/// EINJ Injection Instructions
+///
+#define EFI_ACPI_6_5_EINJ_READ_REGISTER 0x00
+#define EFI_ACPI_6_5_EINJ_READ_REGISTER_VALUE 0x01
+#define EFI_ACPI_6_5_EINJ_WRITE_REGISTER 0x02
+#define EFI_ACPI_6_5_EINJ_WRITE_REGISTER_VALUE 0x03
+#define EFI_ACPI_6_5_EINJ_NOOP 0x04
+
+///
+/// EINJ Instruction Flags
+///
+#define EFI_ACPI_6_5_EINJ_PRESERVE_REGISTER 0x01
+
+///
+/// EINJ Injection Instruction Entry
+///
+typedef struct {
+ UINT8 InjectionAction;
+ UINT8 Instruction;
+ UINT8 Flags;
+ UINT8 Reserved0;
+ EFI_ACPI_6_5_GENERIC_ADDRESS_STRUCTURE RegisterRegion;
+ UINT64 Value;
+ UINT64 Mask;
+} EFI_ACPI_6_5_EINJ_INJECTION_INSTRUCTION_ENTRY;
+
+///
+/// EINJ Trigger Action Table
+///
+typedef struct {
+ UINT32 HeaderSize;
+ UINT32 Revision;
+ UINT32 TableSize;
+ UINT32 EntryCount;
+} EFI_ACPI_6_5_EINJ_TRIGGER_ACTION_TABLE;
+
+///
+/// Platform Communications Channel Table (PCCT)
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 Flags;
+ UINT64 Reserved;
+} EFI_ACPI_6_5_PLATFORM_COMMUNICATION_CHANNEL_TABLE_HEADER;
+
+///
+/// PCCT Version (as defined in ACPI 6.5 spec.)
+///
+#define EFI_ACPI_6_5_PLATFORM_COMMUNICATION_CHANNEL_TABLE_REVISION 0x02
+
+///
+/// PCCT Global Flags
+///
+#define EFI_ACPI_6_5_PCCT_FLAGS_PLATFORM_INTERRUPT BIT0
+
+//
+// PCCT Subspace type
+//
+#define EFI_ACPI_6_5_PCCT_SUBSPACE_TYPE_GENERIC 0x00
+#define EFI_ACPI_6_5_PCCT_SUBSPACE_TYPE_1_HW_REDUCED_COMMUNICATIONS 0x01
+#define EFI_ACPI_6_5_PCCT_SUBSPACE_TYPE_2_HW_REDUCED_COMMUNICATIONS 0x02
+#define EFI_ACPI_6_5_PCCT_SUBSPACE_TYPE_3_EXTENDED_PCC 0x03
+#define EFI_ACPI_6_5_PCCT_SUBSPACE_TYPE_4_EXTENDED_PCC 0x04
+#define EFI_ACPI_6_5_PCCT_SUBSPACE_TYPE_5_HW_REGISTERS_COMMUNICATIONS 0x05
+
+///
+/// PCC Subspace Structure Header
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+} EFI_ACPI_6_5_PCCT_SUBSPACE_HEADER;
+
+///
+/// Generic Communications Subspace Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 Reserved[6];
+ UINT64 BaseAddress;
+ UINT64 AddressLength;
+ EFI_ACPI_6_5_GENERIC_ADDRESS_STRUCTURE DoorbellRegister;
+ UINT64 DoorbellPreserve;
+ UINT64 DoorbellWrite;
+ UINT32 NominalLatency;
+ UINT32 MaximumPeriodicAccessRate;
+ UINT16 MinimumRequestTurnaroundTime;
+} EFI_ACPI_6_5_PCCT_SUBSPACE_GENERIC;
+
+///
+/// Generic Communications Channel Shared Memory Region
+///
+
+typedef struct {
+ UINT8 Command;
+ UINT8 Reserved : 7;
+ UINT8 NotifyOnCompletion : 1;
+} EFI_ACPI_6_5_PCCT_GENERIC_SHARED_MEMORY_REGION_COMMAND;
+
+typedef struct {
+ UINT8 CommandComplete : 1;
+ UINT8 PlatformInterrupt : 1;
+ UINT8 Error : 1;
+ UINT8 PlatformNotification : 1;
+ UINT8 Reserved : 4;
+ UINT8 Reserved1;
+} EFI_ACPI_6_5_PCCT_GENERIC_SHARED_MEMORY_REGION_STATUS;
+
+typedef struct {
+ UINT32 Signature;
+ EFI_ACPI_6_5_PCCT_GENERIC_SHARED_MEMORY_REGION_COMMAND Command;
+ EFI_ACPI_6_5_PCCT_GENERIC_SHARED_MEMORY_REGION_STATUS Status;
+} EFI_ACPI_6_5_PCCT_GENERIC_SHARED_MEMORY_REGION_HEADER;
+
+#define EFI_ACPI_6_5_PCCT_SUBSPACE_PLATFORM_INTERRUPT_FLAGS_POLARITY BIT0
+#define EFI_ACPI_6_5_PCCT_SUBSPACE_PLATFORM_INTERRUPT_FLAGS_MODE BIT1
+
+///
+/// Type 1 HW-Reduced Communications Subspace Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT32 PlatformInterrupt;
+ UINT8 PlatformInterruptFlags;
+ UINT8 Reserved;
+ UINT64 BaseAddress;
+ UINT64 AddressLength;
+ EFI_ACPI_6_5_GENERIC_ADDRESS_STRUCTURE DoorbellRegister;
+ UINT64 DoorbellPreserve;
+ UINT64 DoorbellWrite;
+ UINT32 NominalLatency;
+ UINT32 MaximumPeriodicAccessRate;
+ UINT16 MinimumRequestTurnaroundTime;
+} EFI_ACPI_6_5_PCCT_SUBSPACE_1_HW_REDUCED_COMMUNICATIONS;
+
+///
+/// Type 2 HW-Reduced Communications Subspace Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT32 PlatformInterrupt;
+ UINT8 PlatformInterruptFlags;
+ UINT8 Reserved;
+ UINT64 BaseAddress;
+ UINT64 AddressLength;
+ EFI_ACPI_6_5_GENERIC_ADDRESS_STRUCTURE DoorbellRegister;
+ UINT64 DoorbellPreserve;
+ UINT64 DoorbellWrite;
+ UINT32 NominalLatency;
+ UINT32 MaximumPeriodicAccessRate;
+ UINT16 MinimumRequestTurnaroundTime;
+ EFI_ACPI_6_5_GENERIC_ADDRESS_STRUCTURE PlatformInterruptAckRegister;
+ UINT64 PlatformInterruptAckPreserve;
+ UINT64 PlatformInterruptAckWrite;
+} EFI_ACPI_6_5_PCCT_SUBSPACE_2_HW_REDUCED_COMMUNICATIONS;
+
+///
+/// Type 3 Extended PCC Subspace Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT32 PlatformInterrupt;
+ UINT8 PlatformInterruptFlags;
+ UINT8 Reserved;
+ UINT64 BaseAddress;
+ UINT32 AddressLength;
+ EFI_ACPI_6_5_GENERIC_ADDRESS_STRUCTURE DoorbellRegister;
+ UINT64 DoorbellPreserve;
+ UINT64 DoorbellWrite;
+ UINT32 NominalLatency;
+ UINT32 MaximumPeriodicAccessRate;
+ UINT32 MinimumRequestTurnaroundTime;
+ EFI_ACPI_6_5_GENERIC_ADDRESS_STRUCTURE PlatformInterruptAckRegister;
+ UINT64 PlatformInterruptAckPreserve;
+ UINT64 PlatformInterruptAckSet;
+ UINT8 Reserved1[8];
+ EFI_ACPI_6_5_GENERIC_ADDRESS_STRUCTURE CommandCompleteCheckRegister;
+ UINT64 CommandCompleteCheckMask;
+ EFI_ACPI_6_5_GENERIC_ADDRESS_STRUCTURE CommandCompleteUpdateRegister;
+ UINT64 CommandCompleteUpdatePreserve;
+ UINT64 CommandCompleteUpdateSet;
+ EFI_ACPI_6_5_GENERIC_ADDRESS_STRUCTURE ErrorStatusRegister;
+ UINT64 ErrorStatusMask;
+} EFI_ACPI_6_5_PCCT_SUBSPACE_3_EXTENDED_PCC;
+
+///
+/// Type 4 Extended PCC Subspace Structure
+///
+typedef EFI_ACPI_6_5_PCCT_SUBSPACE_3_EXTENDED_PCC EFI_ACPI_6_5_PCCT_SUBSPACE_4_EXTENDED_PCC;
+
+#define EFI_ACPI_6_5_PCCT_MASTER_SLAVE_COMMUNICATIONS_CHANNEL_FLAGS_NOTIFY_ON_COMPLETION BIT0
+
+typedef struct {
+ UINT32 Signature;
+ UINT32 Flags;
+ UINT32 Length;
+ UINT32 Command;
+} EFI_ACPI_6_5_PCCT_EXTENDED_PCC_SHARED_MEMORY_REGION_HEADER;
+
+///
+/// Type 5 HW Registers based Communications Subspace Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Version;
+ UINT64 BaseAddress;
+ UINT64 SharedMemoryRangeLength;
+ EFI_ACPI_6_5_GENERIC_ADDRESS_STRUCTURE DoorbellRegister;
+ UINT64 DoorbellPreserve;
+ UINT64 DoorbellWrite;
+ EFI_ACPI_6_5_GENERIC_ADDRESS_STRUCTURE CommandCompleteCheckRegister;
+ UINT64 CommandCompleteCheckMask;
+ EFI_ACPI_6_5_GENERIC_ADDRESS_STRUCTURE ErrorStatusRegister;
+ UINT64 ErrorStatusMask;
+ UINT32 NominalLatency;
+ UINT32 MinimumRequestTurnaroundTime;
+} EFI_ACPI_6_5_PCCT_SUBSPACE_5_HW_REGISTERS_COMMUNICATIONS;
+
+///
+/// Reduced PCC Subspace Shared Memory Region
+///
+typedef struct {
+ UINT32 Signature;
+ // UINT8 CommunicationSubspace[];
+} EFI_6_5_PCCT_REDUCED_PCC_SUBSPACE_SHARED_MEMORY_REGION;
+
+///
+/// Platform Debug Trigger Table (PDTT)
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT8 TriggerCount;
+ UINT8 Reserved[3];
+ UINT32 TriggerIdentifierArrayOffset;
+} EFI_ACPI_6_5_PLATFORM_DEBUG_TRIGGER_TABLE_HEADER;
+
+///
+/// PDTT Revision (as defined in ACPI 6.5 spec.)
+///
+#define EFI_ACPI_6_5_PLATFORM_DEBUG_TRIGGER_TABLE_REVISION 0x00
+
+///
+/// PDTT Platform Communication Channel Identifier Structure
+///
+typedef struct {
+ UINT16 SubChannelIdentifer : 8;
+ UINT16 Runtime : 1;
+ UINT16 WaitForCompletion : 1;
+ UINT16 TriggerOrder : 1;
+ UINT16 Reserved : 5;
+} EFI_ACPI_6_5_PDTT_PCC_IDENTIFIER;
+
+///
+/// PCC Commands Codes used by Platform Debug Trigger Table
+///
+#define EFI_ACPI_6_5_PDTT_PCC_COMMAND_DOORBELL_ONLY 0x00
+#define EFI_ACPI_6_5_PDTT_PCC_COMMAND_VENDOR_SPECIFIC 0x01
+
+///
+/// PDTT Platform Communication Channel
+///
+typedef EFI_ACPI_6_5_PCCT_GENERIC_SHARED_MEMORY_REGION_HEADER EFI_ACPI_6_5_PDTT_PCC;
+
+///
+/// Processor Properties Topology Table (PPTT)
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+} EFI_ACPI_6_5_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER;
+
+///
+/// PPTT Revision (as defined in ACPI 6.5 spec.)
+///
+#define EFI_ACPI_6_5_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION 0x03
+
+///
+/// PPTT types
+///
+#define EFI_ACPI_6_5_PPTT_TYPE_PROCESSOR 0x00
+#define EFI_ACPI_6_5_PPTT_TYPE_CACHE 0x01
+
+///
+/// PPTT Structure Header
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 Reserved[2];
+} EFI_ACPI_6_5_PPTT_STRUCTURE_HEADER;
+
+///
+/// For PPTT struct processor flags
+///
+#define EFI_ACPI_6_5_PPTT_PACKAGE_NOT_PHYSICAL 0x0
+#define EFI_ACPI_6_5_PPTT_PACKAGE_PHYSICAL 0x1
+#define EFI_ACPI_6_5_PPTT_PROCESSOR_ID_INVALID 0x0
+#define EFI_ACPI_6_5_PPTT_PROCESSOR_ID_VALID 0x1
+#define EFI_ACPI_6_5_PPTT_PROCESSOR_IS_NOT_THREAD 0x0
+#define EFI_ACPI_6_5_PPTT_PROCESSOR_IS_THREAD 0x1
+#define EFI_ACPI_6_5_PPTT_NODE_IS_NOT_LEAF 0x0
+#define EFI_ACPI_6_5_PPTT_NODE_IS_LEAF 0x1
+#define EFI_ACPI_6_5_PPTT_IMPLEMENTATION_NOT_IDENTICAL 0x0
+#define EFI_ACPI_6_5_PPTT_IMPLEMENTATION_IDENTICAL 0x1
+
+///
+/// Processor hierarchy node structure flags
+///
+typedef struct {
+ UINT32 PhysicalPackage : 1;
+ UINT32 AcpiProcessorIdValid : 1;
+ UINT32 ProcessorIsAThread : 1;
+ UINT32 NodeIsALeaf : 1;
+ UINT32 IdenticalImplementation : 1;
+ UINT32 Reserved : 27;
+} EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR_FLAGS;
+
+///
+/// Processor hierarchy node structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 Reserved[2];
+ EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR_FLAGS Flags;
+ UINT32 Parent;
+ UINT32 AcpiProcessorId;
+ UINT32 NumberOfPrivateResources;
+} EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR;
+
+///
+/// For PPTT struct cache flags
+///
+#define EFI_ACPI_6_5_PPTT_CACHE_SIZE_INVALID 0x0
+#define EFI_ACPI_6_5_PPTT_CACHE_SIZE_VALID 0x1
+#define EFI_ACPI_6_5_PPTT_NUMBER_OF_SETS_INVALID 0x0
+#define EFI_ACPI_6_5_PPTT_NUMBER_OF_SETS_VALID 0x1
+#define EFI_ACPI_6_5_PPTT_ASSOCIATIVITY_INVALID 0x0
+#define EFI_ACPI_6_5_PPTT_ASSOCIATIVITY_VALID 0x1
+#define EFI_ACPI_6_5_PPTT_ALLOCATION_TYPE_INVALID 0x0
+#define EFI_ACPI_6_5_PPTT_ALLOCATION_TYPE_VALID 0x1
+#define EFI_ACPI_6_5_PPTT_CACHE_TYPE_INVALID 0x0
+#define EFI_ACPI_6_5_PPTT_CACHE_TYPE_VALID 0x1
+#define EFI_ACPI_6_5_PPTT_WRITE_POLICY_INVALID 0x0
+#define EFI_ACPI_6_5_PPTT_WRITE_POLICY_VALID 0x1
+#define EFI_ACPI_6_5_PPTT_LINE_SIZE_INVALID 0x0
+#define EFI_ACPI_6_5_PPTT_LINE_SIZE_VALID 0x1
+#define EFI_ACPI_6_5_PPTT_CACHE_ID_INVALID 0x0
+#define EFI_ACPI_6_5_PPTT_CACHE_ID_VALID 0x1
+
+///
+/// Cache Type Structure flags
+///
+typedef struct {
+ UINT32 SizePropertyValid : 1;
+ UINT32 NumberOfSetsValid : 1;
+ UINT32 AssociativityValid : 1;
+ UINT32 AllocationTypeValid : 1;
+ UINT32 CacheTypeValid : 1;
+ UINT32 WritePolicyValid : 1;
+ UINT32 LineSizeValid : 1;
+ UINT32 CacheIdValid : 1;
+ UINT32 Reserved : 24;
+} EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE_FLAGS;
+
+///
+/// For cache attributes
+///
+#define EFI_ACPI_6_5_CACHE_ATTRIBUTES_ALLOCATION_READ 0x0
+#define EFI_ACPI_6_5_CACHE_ATTRIBUTES_ALLOCATION_WRITE 0x1
+#define EFI_ACPI_6_5_CACHE_ATTRIBUTES_ALLOCATION_READ_WRITE 0x2
+#define EFI_ACPI_6_5_CACHE_ATTRIBUTES_CACHE_TYPE_DATA 0x0
+#define EFI_ACPI_6_5_CACHE_ATTRIBUTES_CACHE_TYPE_INSTRUCTION 0x1
+#define EFI_ACPI_6_5_CACHE_ATTRIBUTES_CACHE_TYPE_UNIFIED 0x2
+#define EFI_ACPI_6_5_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK 0x0
+#define EFI_ACPI_6_5_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_THROUGH 0x1
+
+///
+/// Cache Type Structure cache attributes
+///
+typedef struct {
+ UINT8 AllocationType : 2;
+ UINT8 CacheType : 2;
+ UINT8 WritePolicy : 1;
+ UINT8 Reserved : 3;
+} EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE_ATTRIBUTES;
+
+///
+/// Cache Type Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 Reserved[2];
+ EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE_FLAGS Flags;
+ UINT32 NextLevelOfCache;
+ UINT32 Size;
+ UINT32 NumberOfSets;
+ UINT8 Associativity;
+ EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE_ATTRIBUTES Attributes;
+ UINT16 LineSize;
+ UINT32 CacheId;
+} EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE;
+
+///
+/// Platform Health Assessment Table (PHAT) Format
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ // UINT8 PlatformTelemetryRecords[];
+} EFI_ACPI_6_5_PLATFORM_HEALTH_ASSESSMENT_TABLE;
+
+#define EFI_ACPI_6_5_PLATFORM_HEALTH_ASSESSMENT_TABLE_REVISION 0x01
+
+///
+/// PHAT Record Format
+///
+typedef struct {
+ UINT16 PlatformHealthAssessmentRecordType;
+ UINT16 RecordLength;
+ UINT8 Revision;
+ // UINT8 Data[];
+} EFI_ACPI_6_5_PHAT_RECORD;
+
+///
+/// PHAT Record Type Format
+///
+#define EFI_ACPI_6_5_PHAT_RECORD_TYPE_FIRMWARE_VERSION_DATA_RECORD 0x0000
+#define EFI_ACPI_6_5_PHAT_RECORD_TYPE_FIRMWARE_HEALTH_DATA_RECORD 0x0001
+
+///
+/// PHAT Version Element
+///
+typedef struct {
+ GUID ComponentId;
+ UINT64 VersionValue;
+ UINT32 ProducerId;
+} EFI_ACPI_6_5_PHAT_VERSION_ELEMENT;
+
+///
+/// PHAT Firmware Version Data Record
+///
+typedef struct {
+ UINT16 PlatformRecordType;
+ UINT16 RecordLength;
+ UINT8 Revision;
+ UINT8 Reserved[3];
+ UINT32 RecordCount;
+ // UINT8 PhatVersionElement[];
+} EFI_ACPI_6_5_PHAT_FIRMWARE_VERISON_DATA_RECORD;
+
+#define EFI_ACPI_6_5_PHAT_FIRMWARE_VERSION_DATA_RECORD_REVISION 0x01
+
+///
+/// Firmware Health Data Record Structure
+///
+typedef struct {
+ UINT16 PlatformRecordType;
+ UINT16 RecordLength;
+ UINT8 Revision;
+ UINT16 Reserved;
+ UINT8 AmHealthy;
+ GUID DeviceSignature;
+ UINT32 DeviceSpecificDataOffset;
+ // UINT8 DevicePath[];
+ // UINT8 DeviceSpecificData[];
+} EFI_ACPI_6_5_PHAT_FIRMWARE_HEALTH_DATA_RECORD_STRUCTURE;
+
+#define EFI_ACPI_6_5_PHAT_FIRMWARE_HEALTH_DATA_RECORD_REVISION 0x01
+
+///
+/// Firmware Health Data Record device health state
+///
+#define EFI_ACPI_6_5_PHAT_FIRMWARE_HEALTH_DATA_RECORD_ERRORS_FOUND 0x00
+#define EFI_ACPI_6_5_PHAT_FIRMWARE_HEALTH_DATA_RECORD_NO_ERRORS_FOUND 0x01
+#define EFI_ACPI_6_5_PHAT_FIRMWARE_HEALTH_DATA_RECORD_UNKNOWN 0x02
+#define EFI_ACPI_6_5_PHAT_FIRMWARE_HEALTH_DATA_RECORD_ADVISORY 0x03
+
+//
+// Known table signatures
+//
+
+///
+/// "RSD PTR " Root System Description Pointer
+///
+#define EFI_ACPI_6_5_ROOT_SYSTEM_DESCRIPTION_POINTER_SIGNATURE SIGNATURE_64('R', 'S', 'D', ' ', 'P', 'T', 'R', ' ')
+
+///
+/// "APIC" Multiple APIC Description Table
+///
+#define EFI_ACPI_6_5_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('A', 'P', 'I', 'C')
+
+///
+/// "APMT" Arm Performance Monitoring Unit Table
+///
+#define EFI_ACPI_6_5_ARM_PERFORMANCE_MONITORING_UNIT_TABLE_SIGNATURE SIGNATURE_32('A', 'P', 'M', 'T')
+
+///
+/// "BERT" Boot Error Record Table
+///
+#define EFI_ACPI_6_5_BOOT_ERROR_RECORD_TABLE_SIGNATURE SIGNATURE_32('B', 'E', 'R', 'T')
+
+///
+/// "BGRT" Boot Graphics Resource Table
+///
+#define EFI_ACPI_6_5_BOOT_GRAPHICS_RESOURCE_TABLE_SIGNATURE SIGNATURE_32('B', 'G', 'R', 'T')
+
+///
+/// "CDIT" Component Distance Information Table
+///
+#define EFI_ACPI_6_5_COMPONENT_DISTANCE_INFORMATION_TABLE_SIGNATURE SIGNATURE_32('C', 'D', 'I', 'T')
+
+///
+/// "CPEP" Corrected Platform Error Polling Table
+///
+#define EFI_ACPI_6_5_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_SIGNATURE SIGNATURE_32('C', 'P', 'E', 'P')
+
+///
+/// "CRAT" Component Resource Attribute Table
+///
+#define EFI_ACPI_6_5_COMPONENT_RESOURCE_ATTRIBUTE_TABLE_SIGNATURE SIGNATURE_32('C', 'R', 'A', 'T')
+
+///
+/// "DSDT" Differentiated System Description Table
+///
+#define EFI_ACPI_6_5_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('D', 'S', 'D', 'T')
+
+///
+/// "ECDT" Embedded Controller Boot Resources Table
+///
+#define EFI_ACPI_6_5_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE_SIGNATURE SIGNATURE_32('E', 'C', 'D', 'T')
+
+///
+/// "EINJ" Error Injection Table
+///
+#define EFI_ACPI_6_5_ERROR_INJECTION_TABLE_SIGNATURE SIGNATURE_32('E', 'I', 'N', 'J')
+
+///
+/// "ERST" Error Record Serialization Table
+///
+#define EFI_ACPI_6_5_ERROR_RECORD_SERIALIZATION_TABLE_SIGNATURE SIGNATURE_32('E', 'R', 'S', 'T')
+
+///
+/// "FACP" Fixed ACPI Description Table
+///
+#define EFI_ACPI_6_5_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('F', 'A', 'C', 'P')
+
+///
+/// "FACS" Firmware ACPI Control Structure
+///
+#define EFI_ACPI_6_5_FIRMWARE_ACPI_CONTROL_STRUCTURE_SIGNATURE SIGNATURE_32('F', 'A', 'C', 'S')
+
+///
+/// "FPDT" Firmware Performance Data Table
+///
+#define EFI_ACPI_6_5_FIRMWARE_PERFORMANCE_DATA_TABLE_SIGNATURE SIGNATURE_32('F', 'P', 'D', 'T')
+
+///
+/// "GTDT" Generic Timer Description Table
+///
+#define EFI_ACPI_6_5_GENERIC_TIMER_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('G', 'T', 'D', 'T')
+
+///
+/// "HEST" Hardware Error Source Table
+///
+#define EFI_ACPI_6_5_HARDWARE_ERROR_SOURCE_TABLE_SIGNATURE SIGNATURE_32('H', 'E', 'S', 'T')
+
+///
+/// "HMAT" Heterogeneous Memory Attribute Table
+///
+#define EFI_ACPI_6_5_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_SIGNATURE SIGNATURE_32('H', 'M', 'A', 'T')
+
+///
+/// "MPST" Memory Power State Table
+///
+#define EFI_ACPI_6_5_MEMORY_POWER_STATE_TABLE_SIGNATURE SIGNATURE_32('M', 'P', 'S', 'T')
+
+///
+/// "MSCT" Maximum System Characteristics Table
+///
+#define EFI_ACPI_6_5_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_SIGNATURE SIGNATURE_32('M', 'S', 'C', 'T')
+
+///
+/// "NFIT" NVDIMM Firmware Interface Table
+///
+#define EFI_ACPI_6_5_NVDIMM_FIRMWARE_INTERFACE_TABLE_STRUCTURE_SIGNATURE SIGNATURE_32('N', 'F', 'I', 'T')
+
+///
+/// "PDTT" Platform Debug Trigger Table
+///
+#define EFI_ACPI_6_5_PLATFORM_DEBUG_TRIGGER_TABLE_STRUCTURE_SIGNATURE SIGNATURE_32('P', 'D', 'T', 'T')
+
+///
+/// "PMTT" Platform Memory Topology Table
+///
+#define EFI_ACPI_6_5_PLATFORM_MEMORY_TOPOLOGY_TABLE_SIGNATURE SIGNATURE_32('P', 'M', 'T', 'T')
+
+///
+/// "PPTT" Processor Properties Topology Table
+///
+#define EFI_ACPI_6_5_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE SIGNATURE_32('P', 'P', 'T', 'T')
+
+///
+/// "PSDT" Persistent System Description Table
+///
+#define EFI_ACPI_6_5_PERSISTENT_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('P', 'S', 'D', 'T')
+
+///
+/// "RASF" ACPI RAS Feature Table
+///
+#define EFI_ACPI_6_5_ACPI_RAS_FEATURE_TABLE_SIGNATURE SIGNATURE_32('R', 'A', 'S', 'F')
+
+///
+/// "RSDT" Root System Description Table
+///
+#define EFI_ACPI_6_5_ROOT_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('R', 'S', 'D', 'T')
+
+///
+/// "SBST" Smart Battery Specification Table
+///
+#define EFI_ACPI_6_5_SMART_BATTERY_SPECIFICATION_TABLE_SIGNATURE SIGNATURE_32('S', 'B', 'S', 'T')
+
+///
+/// "SDEV" Secure DEVices Table
+///
+#define EFI_ACPI_6_5_SECURE_DEVICES_TABLE_SIGNATURE SIGNATURE_32('S', 'D', 'E', 'V')
+
+///
+/// "SLIT" System Locality Information Table
+///
+#define EFI_ACPI_6_5_SYSTEM_LOCALITY_INFORMATION_TABLE_SIGNATURE SIGNATURE_32('S', 'L', 'I', 'T')
+
+///
+/// "SRAT" System Resource Affinity Table
+///
+#define EFI_ACPI_6_5_SYSTEM_RESOURCE_AFFINITY_TABLE_SIGNATURE SIGNATURE_32('S', 'R', 'A', 'T')
+
+///
+/// "SSDT" Secondary System Description Table
+///
+#define EFI_ACPI_6_5_SECONDARY_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('S', 'S', 'D', 'T')
+
+///
+/// "XSDT" Extended System Description Table
+///
+#define EFI_ACPI_6_5_EXTENDED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('X', 'S', 'D', 'T')
+
+///
+/// "BOOT" MS Simple Boot Spec
+///
+#define EFI_ACPI_6_5_SIMPLE_BOOT_FLAG_TABLE_SIGNATURE SIGNATURE_32('B', 'O', 'O', 'T')
+
+///
+/// "CSRT" MS Core System Resource Table
+///
+#define EFI_ACPI_6_5_CORE_SYSTEM_RESOURCE_TABLE_SIGNATURE SIGNATURE_32('C', 'S', 'R', 'T')
+
+///
+/// "DBG2" MS Debug Port 2 Spec
+///
+#define EFI_ACPI_6_5_DEBUG_PORT_2_TABLE_SIGNATURE SIGNATURE_32('D', 'B', 'G', '2')
+
+///
+/// "DBGP" MS Debug Port Spec
+///
+#define EFI_ACPI_6_5_DEBUG_PORT_TABLE_SIGNATURE SIGNATURE_32('D', 'B', 'G', 'P')
+
+///
+/// "DMAR" DMA Remapping Table
+///
+#define EFI_ACPI_6_5_DMA_REMAPPING_TABLE_SIGNATURE SIGNATURE_32('D', 'M', 'A', 'R')
+
+///
+/// "DRTM" Dynamic Root of Trust for Measurement Table
+///
+#define EFI_ACPI_6_5_DYNAMIC_ROOT_OF_TRUST_FOR_MEASUREMENT_TABLE_SIGNATURE SIGNATURE_32('D', 'R', 'T', 'M')
+
+///
+/// "ETDT" Event Timer Description Table
+///
+#define EFI_ACPI_6_5_EVENT_TIMER_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('E', 'T', 'D', 'T')
+
+///
+/// "HPET" IA-PC High Precision Event Timer Table
+///
+#define EFI_ACPI_6_5_HIGH_PRECISION_EVENT_TIMER_TABLE_SIGNATURE SIGNATURE_32('H', 'P', 'E', 'T')
+
+///
+/// "iBFT" iSCSI Boot Firmware Table
+///
+#define EFI_ACPI_6_5_ISCSI_BOOT_FIRMWARE_TABLE_SIGNATURE SIGNATURE_32('i', 'B', 'F', 'T')
+
+///
+/// "IORT" I/O Remapping Table
+///
+#define EFI_ACPI_6_5_IO_REMAPPING_TABLE_SIGNATURE SIGNATURE_32('I', 'O', 'R', 'T')
+
+///
+/// "IVRS" I/O Virtualization Reporting Structure
+///
+#define EFI_ACPI_6_5_IO_VIRTUALIZATION_REPORTING_STRUCTURE_SIGNATURE SIGNATURE_32('I', 'V', 'R', 'S')
+
+///
+/// "LPIT" Low Power Idle Table
+///
+#define EFI_ACPI_6_5_LOW_POWER_IDLE_TABLE_STRUCTURE_SIGNATURE SIGNATURE_32('L', 'P', 'I', 'T')
+
+///
+/// "MCFG" PCI Express Memory Mapped Configuration Space Base Address Description Table
+///
+#define EFI_ACPI_6_5_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('M', 'C', 'F', 'G')
+
+///
+/// "MCHI" Management Controller Host Interface Table
+///
+#define EFI_ACPI_6_5_MANAGEMENT_CONTROLLER_HOST_INTERFACE_TABLE_SIGNATURE SIGNATURE_32('M', 'C', 'H', 'I')
+
+///
+/// "MSDM" MS Data Management Table
+///
+#define EFI_ACPI_6_5_DATA_MANAGEMENT_TABLE_SIGNATURE SIGNATURE_32('M', 'S', 'D', 'M')
+
+///
+/// "PCCT" Platform Communications Channel Table
+///
+#define EFI_ACPI_6_5_PLATFORM_COMMUNICATIONS_CHANNEL_TABLE_SIGNATURE SIGNATURE_32('P', 'C', 'C', 'T')
+
+///
+/// "PHAT" Platform Health Assessment Table
+///
+#define EFI_ACPI_6_5_PLATFORM_HEALTH_ASSESSMENT_TABLE_SIGNATURE SIGNATURE_32('P', 'H', 'A', 'T')
+
+///
+/// "SDEI" Software Delegated Exceptions Interface Table
+///
+#define EFI_ACPI_6_5_SOFTWARE_DELEGATED_EXCEPTIONS_INTERFACE_TABLE_SIGNATURE SIGNATURE_32('S', 'D', 'E', 'I')
+
+///
+/// "SLIC" MS Software Licensing Table Specification
+///
+#define EFI_ACPI_6_5_SOFTWARE_LICENSING_TABLE_SIGNATURE SIGNATURE_32('S', 'L', 'I', 'C')
+
+///
+/// "SPCR" Serial Port Concole Redirection Table
+///
+#define EFI_ACPI_6_5_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE SIGNATURE_32('S', 'P', 'C', 'R')
+
+///
+/// "SPMI" Server Platform Management Interface Table
+///
+#define EFI_ACPI_6_5_SERVER_PLATFORM_MANAGEMENT_INTERFACE_TABLE_SIGNATURE SIGNATURE_32('S', 'P', 'M', 'I')
+
+///
+/// "STAO" _STA Override Table
+///
+#define EFI_ACPI_6_5_STA_OVERRIDE_TABLE_SIGNATURE SIGNATURE_32('S', 'T', 'A', 'O')
+
+///
+/// "TCPA" Trusted Computing Platform Alliance Capabilities Table
+///
+#define EFI_ACPI_6_5_TRUSTED_COMPUTING_PLATFORM_ALLIANCE_CAPABILITIES_TABLE_SIGNATURE SIGNATURE_32('T', 'C', 'P', 'A')
+
+///
+/// "TPM2" Trusted Computing Platform 1 Table
+///
+#define EFI_ACPI_6_5_TRUSTED_COMPUTING_PLATFORM_2_TABLE_SIGNATURE SIGNATURE_32('T', 'P', 'M', '2')
+
+///
+/// "UEFI" UEFI ACPI Data Table
+///
+#define EFI_ACPI_6_5_UEFI_ACPI_DATA_TABLE_SIGNATURE SIGNATURE_32('U', 'E', 'F', 'I')
+
+///
+/// "WAET" Windows ACPI Emulated Devices Table
+///
+#define EFI_ACPI_6_5_WINDOWS_ACPI_EMULATED_DEVICES_TABLE_SIGNATURE SIGNATURE_32('W', 'A', 'E', 'T')
+
+///
+/// "WDAT" Watchdog Action Table
+///
+#define EFI_ACPI_6_5_WATCHDOG_ACTION_TABLE_SIGNATURE SIGNATURE_32('W', 'D', 'A', 'T')
+
+///
+/// "WDRT" Watchdog Resource Table
+///
+#define EFI_ACPI_6_5_WATCHDOG_RESOURCE_TABLE_SIGNATURE SIGNATURE_32('W', 'D', 'R', 'T')
+
+///
+/// "WPBT" MS Platform Binary Table
+///
+#define EFI_ACPI_6_5_PLATFORM_BINARY_TABLE_SIGNATURE SIGNATURE_32('W', 'P', 'B', 'T')
+
+///
+/// "WSMT" Windows SMM Security Mitigation Table
+///
+#define EFI_ACPI_6_5_WINDOWS_SMM_SECURITY_MITIGATION_TABLE_SIGNATURE SIGNATURE_32('W', 'S', 'M', 'T')
+
+///
+/// "XENV" Xen Project Table
+///
+#define EFI_ACPI_6_5_XEN_PROJECT_TABLE_SIGNATURE SIGNATURE_32('X', 'E', 'N', 'V')
+
+#pragma pack()
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/AcpiAml.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/AcpiAml.h
new file mode 100644
index 0000000000..79e30b7b58
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/AcpiAml.h
@@ -0,0 +1,184 @@
+/** @file
+ This file contains AML code definition in the latest ACPI spec.
+
+ Copyright (c) 2011, Intel Corporation. All rights reserved.
+ Copyright (c) 2019 - 2021, Arm Limited. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _ACPI_AML_H_
+#define _ACPI_AML_H_
+
+//
+// ACPI AML definition
+//
+
+//
+// Primary OpCode
+//
+#define AML_ZERO_OP 0x00
+#define AML_ONE_OP 0x01
+#define AML_ALIAS_OP 0x06
+#define AML_NAME_OP 0x08
+#define AML_BYTE_PREFIX 0x0a
+#define AML_WORD_PREFIX 0x0b
+#define AML_DWORD_PREFIX 0x0c
+#define AML_STRING_PREFIX 0x0d
+#define AML_QWORD_PREFIX 0x0e
+#define AML_SCOPE_OP 0x10
+#define AML_BUFFER_OP 0x11
+#define AML_PACKAGE_OP 0x12
+#define AML_VAR_PACKAGE_OP 0x13
+#define AML_METHOD_OP 0x14
+#define AML_EXTERNAL_OP 0x15
+#define AML_DUAL_NAME_PREFIX 0x2e
+#define AML_MULTI_NAME_PREFIX 0x2f
+#define AML_NAME_CHAR_A 0x41
+#define AML_NAME_CHAR_B 0x42
+#define AML_NAME_CHAR_C 0x43
+#define AML_NAME_CHAR_D 0x44
+#define AML_NAME_CHAR_E 0x45
+#define AML_NAME_CHAR_F 0x46
+#define AML_NAME_CHAR_G 0x47
+#define AML_NAME_CHAR_H 0x48
+#define AML_NAME_CHAR_I 0x49
+#define AML_NAME_CHAR_J 0x4a
+#define AML_NAME_CHAR_K 0x4b
+#define AML_NAME_CHAR_L 0x4c
+#define AML_NAME_CHAR_M 0x4d
+#define AML_NAME_CHAR_N 0x4e
+#define AML_NAME_CHAR_O 0x4f
+#define AML_NAME_CHAR_P 0x50
+#define AML_NAME_CHAR_Q 0x51
+#define AML_NAME_CHAR_R 0x52
+#define AML_NAME_CHAR_S 0x53
+#define AML_NAME_CHAR_T 0x54
+#define AML_NAME_CHAR_U 0x55
+#define AML_NAME_CHAR_V 0x56
+#define AML_NAME_CHAR_W 0x57
+#define AML_NAME_CHAR_X 0x58
+#define AML_NAME_CHAR_Y 0x59
+#define AML_NAME_CHAR_Z 0x5a
+#define AML_ROOT_CHAR 0x5c
+#define AML_PARENT_PREFIX_CHAR 0x5e
+#define AML_NAME_CHAR__ 0x5f
+#define AML_LOCAL0 0x60
+#define AML_LOCAL1 0x61
+#define AML_LOCAL2 0x62
+#define AML_LOCAL3 0x63
+#define AML_LOCAL4 0x64
+#define AML_LOCAL5 0x65
+#define AML_LOCAL6 0x66
+#define AML_LOCAL7 0x67
+#define AML_ARG0 0x68
+#define AML_ARG1 0x69
+#define AML_ARG2 0x6a
+#define AML_ARG3 0x6b
+#define AML_ARG4 0x6c
+#define AML_ARG5 0x6d
+#define AML_ARG6 0x6e
+#define AML_STORE_OP 0x70
+#define AML_REF_OF_OP 0x71
+#define AML_ADD_OP 0x72
+#define AML_CONCAT_OP 0x73
+#define AML_SUBTRACT_OP 0x74
+#define AML_INCREMENT_OP 0x75
+#define AML_DECREMENT_OP 0x76
+#define AML_MULTIPLY_OP 0x77
+#define AML_DIVIDE_OP 0x78
+#define AML_SHIFT_LEFT_OP 0x79
+#define AML_SHIFT_RIGHT_OP 0x7a
+#define AML_AND_OP 0x7b
+#define AML_NAND_OP 0x7c
+#define AML_OR_OP 0x7d
+#define AML_NOR_OP 0x7e
+#define AML_XOR_OP 0x7f
+#define AML_NOT_OP 0x80
+#define AML_FIND_SET_LEFT_BIT_OP 0x81
+#define AML_FIND_SET_RIGHT_BIT_OP 0x82
+#define AML_DEREF_OF_OP 0x83
+#define AML_CONCAT_RES_OP 0x84
+#define AML_MOD_OP 0x85
+#define AML_NOTIFY_OP 0x86
+#define AML_SIZE_OF_OP 0x87
+#define AML_INDEX_OP 0x88
+#define AML_MATCH_OP 0x89
+#define AML_CREATE_DWORD_FIELD_OP 0x8a
+#define AML_CREATE_WORD_FIELD_OP 0x8b
+#define AML_CREATE_BYTE_FIELD_OP 0x8c
+#define AML_CREATE_BIT_FIELD_OP 0x8d
+#define AML_OBJECT_TYPE_OP 0x8e
+#define AML_CREATE_QWORD_FIELD_OP 0x8f
+#define AML_LAND_OP 0x90
+#define AML_LOR_OP 0x91
+#define AML_LNOT_OP 0x92
+#define AML_LEQUAL_OP 0x93
+#define AML_LGREATER_OP 0x94
+#define AML_LLESS_OP 0x95
+#define AML_TO_BUFFER_OP 0x96
+#define AML_TO_DEC_STRING_OP 0x97
+#define AML_TO_HEX_STRING_OP 0x98
+#define AML_TO_INTEGER_OP 0x99
+#define AML_TO_STRING_OP 0x9c
+#define AML_COPY_OBJECT_OP 0x9d
+#define AML_MID_OP 0x9e
+#define AML_CONTINUE_OP 0x9f
+#define AML_IF_OP 0xa0
+#define AML_ELSE_OP 0xa1
+#define AML_WHILE_OP 0xa2
+#define AML_NOOP_OP 0xa3
+#define AML_RETURN_OP 0xa4
+#define AML_BREAK_OP 0xa5
+#define AML_BREAK_POINT_OP 0xcc
+#define AML_ONES_OP 0xff
+
+//
+// Extended OpCode
+//
+#define AML_EXT_OP 0x5b
+
+#define AML_EXT_MUTEX_OP 0x01
+#define AML_EXT_EVENT_OP 0x02
+#define AML_EXT_COND_REF_OF_OP 0x12
+#define AML_EXT_CREATE_FIELD_OP 0x13
+#define AML_EXT_LOAD_TABLE_OP 0x1f
+#define AML_EXT_LOAD_OP 0x20
+#define AML_EXT_STALL_OP 0x21
+#define AML_EXT_SLEEP_OP 0x22
+#define AML_EXT_ACQUIRE_OP 0x23
+#define AML_EXT_SIGNAL_OP 0x24
+#define AML_EXT_WAIT_OP 0x25
+#define AML_EXT_RESET_OP 0x26
+#define AML_EXT_RELEASE_OP 0x27
+#define AML_EXT_FROM_BCD_OP 0x28
+#define AML_EXT_TO_BCD_OP 0x29
+#define AML_EXT_UNLOAD_OP 0x2a
+#define AML_EXT_REVISION_OP 0x30
+#define AML_EXT_DEBUG_OP 0x31
+#define AML_EXT_FATAL_OP 0x32
+#define AML_EXT_TIMER_OP 0x33
+#define AML_EXT_REGION_OP 0x80
+#define AML_EXT_FIELD_OP 0x81
+#define AML_EXT_DEVICE_OP 0x82
+#define AML_EXT_PROCESSOR_OP 0x83
+#define AML_EXT_POWER_RES_OP 0x84
+#define AML_EXT_THERMAL_ZONE_OP 0x85
+#define AML_EXT_INDEX_FIELD_OP 0x86
+#define AML_EXT_BANK_FIELD_OP 0x87
+#define AML_EXT_DATA_REGION_OP 0x88
+
+//
+// FieldElement OpCode
+//
+#define AML_FIELD_RESERVED_OP 0x00
+#define AML_FIELD_ACCESS_OP 0x01
+#define AML_FIELD_CONNECTION_OP 0x02
+#define AML_FIELD_EXT_ACCESS_OP 0x03
+
+//
+// AML Name segment definitions
+//
+#define AML_NAME_SEG_SIZE 4
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/AlertStandardFormatTable.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/AlertStandardFormatTable.h
new file mode 100644
index 0000000000..0fb73c15da
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/AlertStandardFormatTable.h
@@ -0,0 +1,139 @@
+/** @file
+ ACPI Alert Standard Format Description Table ASF! as described in the ASF2.0 Specification
+
+ Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _ALERT_STANDARD_FORMAT_TABLE_H_
+#define _ALERT_STANDARD_FORMAT_TABLE_H_
+
+#include
+
+//
+// Ensure proper structure formats
+//
+#pragma pack (1)
+
+///
+/// Information Record header that appears at the beginning of each record
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Reserved;
+ UINT16 RecordLength;
+} EFI_ACPI_ASF_RECORD_HEADER;
+
+///
+/// This structure contains information that identifies the system's type
+/// and configuration
+///
+typedef struct {
+ EFI_ACPI_ASF_RECORD_HEADER RecordHeader;
+ UINT8 MinWatchDogResetValue;
+ UINT8 MinPollingInterval;
+ UINT16 SystemID;
+ UINT32 IANAManufactureID;
+ UINT8 FeatureFlags;
+ UINT8 Reserved[3];
+} EFI_ACPI_ASF_INFO;
+
+///
+/// ASF Alert Data
+///
+typedef struct {
+ UINT8 DeviceAddress;
+ UINT8 Command;
+ UINT8 DataMask;
+ UINT8 CompareValue;
+ UINT8 EventSenseType;
+ UINT8 EventType;
+ UINT8 EventOffset;
+ UINT8 EventSourceType;
+ UINT8 EventSeverity;
+ UINT8 SensorNumber;
+ UINT8 Entity;
+ UINT8 EntityInstance;
+} EFI_ACPI_ASF_ALERTDATA;
+
+///
+/// Alert sensors definition
+///
+typedef struct {
+ EFI_ACPI_ASF_RECORD_HEADER RecordHeader;
+ UINT8 AssertionEventBitMask;
+ UINT8 DeassertionEventBitMask;
+ UINT8 NumberOfAlerts;
+ UINT8 ArrayElementLength; ///< For ASF version 1.0 and later, this filed is set to 0x0C
+ ///
+ /// EFI_ACPI_ASF_ALERTDATA DeviceArray[ANYSIZE_ARRAY];
+ ///
+} EFI_ACPI_ASF_ALRT;
+
+///
+/// Alert Control Data
+///
+typedef struct {
+ UINT8 Function;
+ UINT8 DeviceAddress;
+ UINT8 Command;
+ UINT8 DataValue;
+} EFI_ACPI_ASF_CONTROLDATA;
+
+///
+/// Alert Remote Control System Actions
+///
+typedef struct {
+ EFI_ACPI_ASF_RECORD_HEADER RecordHeader;
+ UINT8 NumberOfControls;
+ UINT8 ArrayElementLength; ///< For ASF version 1.0 and later, this filed is set to 0x4
+ UINT16 RctlReserved;
+ ///
+ /// EFI_ACPI_ASF_CONTROLDATA; DeviceArray[ANYSIZE_ARRAY];
+ ///
+} EFI_ACPI_ASF_RCTL;
+
+///
+/// Remote Control Capabilities
+///
+typedef struct {
+ EFI_ACPI_ASF_RECORD_HEADER RecordHeader;
+ UINT8 RemoteControlCapabilities[7];
+ UINT8 RMCPCompletionCode;
+ UINT32 RMCPIANA;
+ UINT8 RMCPSpecialCommand;
+ UINT8 RMCPSpecialCommandParameter[2];
+ UINT8 RMCPBootOptions[2];
+ UINT8 RMCPOEMParameters[2];
+} EFI_ACPI_ASF_RMCP;
+
+///
+/// SMBus Devices with fixed addresses
+///
+typedef struct {
+ EFI_ACPI_ASF_RECORD_HEADER RecordHeader;
+ UINT8 SEEPROMAddress;
+ UINT8 NumberOfDevices;
+ ///
+ /// UINT8 FixedSmbusAddresses[ANYSIZE_ARRAY];
+ ///
+} EFI_ACPI_ASF_ADDR;
+
+///
+/// ASF! Description Table Header
+///
+typedef EFI_ACPI_DESCRIPTION_HEADER EFI_ACPI_ASF_DESCRIPTION_HEADER;
+
+///
+/// The revision stored in ASF! DESCRIPTION TABLE as BCD value
+///
+#define EFI_ACPI_2_0_ASF_DESCRIPTION_TABLE_REVISION 0x20
+
+///
+/// "ASF!" ASF Description Table Signature
+///
+#define EFI_ACPI_ASF_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32 ('A', 'S', 'F', '!')
+
+#pragma pack ()
+
+#endif // _ALERT_STANDARD_FORMAT_TABLE_H
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/ArmErrorSourceTable.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/ArmErrorSourceTable.h
new file mode 100644
index 0000000000..ea3aeba129
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/ArmErrorSourceTable.h
@@ -0,0 +1,357 @@
+/** @file
+ Arm Error Source Table as described in the
+ 'ACPI for the Armv8 RAS Extensions 1.1' Specification.
+
+ Copyright (c) 2020 Arm Limited.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Reference(s):
+ - ACPI for the Armv8 RAS Extensions 1.1 Platform Design Document,
+ dated 28 September 2020.
+ (https://developer.arm.com/documentation/den0085/0101/)
+
+ @par Glossary
+ - Ref : Reference
+ - Id : Identifier
+**/
+
+#ifndef ARM_ERROR_SOURCE_TABLE_H_
+#define ARM_ERROR_SOURCE_TABLE_H_
+
+///
+/// "AEST" Arm Error Source Table
+///
+#define EFI_ACPI_6_3_ARM_ERROR_SOURCE_TABLE_SIGNATURE SIGNATURE_32('A', 'E', 'S', 'T')
+
+#define EFI_ACPI_ARM_ERROR_SOURCE_TABLE_REVISION 1
+
+#pragma pack(1)
+
+///
+/// Arm Error Source Table definition.
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+} EFI_ACPI_ARM_ERROR_SOURCE_TABLE;
+
+///
+/// AEST Node structure.
+///
+typedef struct {
+ /// Node type:
+ /// 0x00 - Processor error node
+ /// 0x01 - Memory error node
+ /// 0x02 - SMMU error node
+ /// 0x03 - Vendor-defined error node
+ /// 0x04 - GIC error node
+ UINT8 Type;
+
+ /// Length of structure in bytes.
+ UINT16 Length;
+
+ /// Reserved - Must be zero.
+ UINT8 Reserved;
+
+ /// Offset from the start of the node to node-specific data.
+ UINT32 DataOffset;
+
+ /// Offset from the start of the node to the node interface structure.
+ UINT32 InterfaceOffset;
+
+ /// Offset from the start of the node to node interrupt array.
+ UINT32 InterruptArrayOffset;
+
+ /// Number of entries in the interrupt array.
+ UINT32 InterruptArrayCount;
+
+ // Generic node data
+
+ /// The timestamp frequency of the counter in Hz.
+ UINT64 TimestampRate;
+
+ /// Reserved - Must be zero.
+ UINT64 Reserved1;
+
+ /// The rate in Hz at which the Error Generation Counter decrements.
+ UINT64 ErrorInjectionCountdownRate;
+} EFI_ACPI_AEST_NODE_STRUCT;
+
+// AEST Node type definitions
+#define EFI_ACPI_AEST_NODE_TYPE_PROCESSOR 0x0
+#define EFI_ACPI_AEST_NODE_TYPE_MEMORY 0x1
+#define EFI_ACPI_AEST_NODE_TYPE_SMMU 0x2
+#define EFI_ACPI_AEST_NODE_TYPE_VENDOR_DEFINED 0x3
+#define EFI_ACPI_AEST_NODE_TYPE_GIC 0x4
+
+///
+/// AEST Node Interface structure.
+///
+typedef struct {
+ /// Interface type:
+ /// 0x0 - System register (SR)
+ /// 0x1 - Memory mapped (MMIO)
+ UINT8 Type;
+
+ /// Reserved - Must be zero.
+ UINT8 Reserved[3];
+
+ /// AEST node interface flags.
+ UINT32 Flags;
+
+ /// Base address of error group that contains the error node.
+ UINT64 BaseAddress;
+
+ /// Zero-based index of the first standard error record that
+ /// belongs to this node.
+ UINT32 StartErrorRecordIndex;
+
+ /// Number of error records in this node including both
+ /// implemented and unimplemented records.
+ UINT32 NumberErrorRecords;
+
+ /// A bitmap indicating the error records within this
+ /// node that are implemented in the current system.
+ UINT64 ErrorRecordImplemented;
+
+ /// A bitmap indicating the error records within this node that
+ /// support error status reporting through the ERRGSR register.
+ UINT64 ErrorRecordStatusReportingSupported;
+
+ /// A bitmap indicating the addressing mode used by each error
+ /// record within this node to populate the ERR_ADDR register.
+ UINT64 AddressingMode;
+} EFI_ACPI_AEST_INTERFACE_STRUCT;
+
+// AEST Interface node type definitions.
+#define EFI_ACPI_AEST_INTERFACE_TYPE_SR 0x0
+#define EFI_ACPI_AEST_INTERFACE_TYPE_MMIO 0x1
+
+// AEST node interface flag definitions.
+#define EFI_ACPI_AEST_INTERFACE_FLAG_PRIVATE 0
+#define EFI_ACPI_AEST_INTERFACE_FLAG_SHARED BIT0
+#define EFI_ACPI_AEST_INTERFACE_FLAG_CLEAR_MISCX BIT1
+
+///
+/// AEST Node Interrupt structure.
+///
+typedef struct {
+ /// Interrupt type:
+ /// 0x0 - Fault Handling Interrupt
+ /// 0x1 - Error Recovery Interrupt
+ UINT8 InterruptType;
+
+ /// Reserved - Must be zero.
+ UINT8 Reserved[2];
+
+ /// Interrupt flags
+ /// Bits [31:1]: Must be zero.
+ /// Bit 0:
+ /// 0b - Interrupt is edge-triggered
+ /// 1b - Interrupt is level-triggered
+ UINT8 InterruptFlags;
+
+ /// GSIV of interrupt, if interrupt is an SPI or a PPI.
+ UINT32 InterruptGsiv;
+
+ /// If MSI is supported, then this field must be set to the
+ /// Identifier field of the IORT ITS Group node.
+ UINT8 ItsGroupRefId;
+
+ /// Reserved - must be zero.
+ UINT8 Reserved1[3];
+} EFI_ACPI_AEST_INTERRUPT_STRUCT;
+
+// AEST Interrupt node - interrupt type defintions.
+#define EFI_ACPI_AEST_INTERRUPT_TYPE_FAULT_HANDLING 0x0
+#define EFI_ACPI_AEST_INTERRUPT_TYPE_ERROR_RECOVERY 0x1
+
+// AEST Interrupt node - interrupt flag defintions.
+#define EFI_ACPI_AEST_INTERRUPT_FLAG_TRIGGER_TYPE_EDGE 0
+#define EFI_ACPI_AEST_INTERRUPT_FLAG_TRIGGER_TYPE_LEVEL BIT0
+
+///
+/// Cache Processor Resource structure.
+///
+typedef struct {
+ /// Reference to the cache structure in the PPTT table.
+ UINT32 CacheRefId;
+
+ /// Reserved
+ UINT32 Reserved;
+} EFI_ACPI_AEST_PROCESSOR_CACHE_RESOURCE_STRUCT;
+
+///
+/// TLB Processor Resource structure.
+///
+typedef struct {
+ /// TLB level from perspective of current processor.
+ UINT32 TlbRefId;
+
+ /// Reserved
+ UINT32 Reserved;
+} EFI_ACPI_AEST_PROCESSOR_TLB_RESOURCE_STRUCT;
+
+///
+/// Processor Generic Resource structure.
+///
+typedef struct {
+ /// Vendor-defined supplementary data.
+ UINT32 Data;
+} EFI_ACPI_AEST_PROCESSOR_GENERIC_RESOURCE_STRUCT;
+
+///
+/// AEST Processor Resource union.
+///
+typedef union {
+ /// Processor Cache resource.
+ EFI_ACPI_AEST_PROCESSOR_CACHE_RESOURCE_STRUCT Cache;
+
+ /// Processor TLB resource.
+ EFI_ACPI_AEST_PROCESSOR_TLB_RESOURCE_STRUCT Tlb;
+
+ /// Processor Generic resource.
+ EFI_ACPI_AEST_PROCESSOR_GENERIC_RESOURCE_STRUCT Generic;
+} EFI_ACPI_AEST_PROCESSOR_RESOURCE;
+
+///
+/// AEST Processor structure.
+///
+typedef struct {
+ /// AEST Node header
+ EFI_ACPI_AEST_NODE_STRUCT NodeHeader;
+
+ /// Processor ID of node.
+ UINT32 AcpiProcessorId;
+
+ /// Resource type of the processor node.
+ /// 0x0 - Cache
+ /// 0x1 - TLB
+ /// 0x2 - Generic
+ UINT8 ResourceType;
+
+ /// Reserved - must be zero.
+ UINT8 Reserved;
+
+ /// Processor structure flags.
+ UINT8 Flags;
+
+ /// Processor structure revision.
+ UINT8 Revision;
+
+ /// Processor affinity descriptor for the resource that this
+ /// error node pertains to.
+ UINT64 ProcessorAffinityLevelIndicator;
+
+ /// Processor resource
+ EFI_ACPI_AEST_PROCESSOR_RESOURCE Resource;
+
+ // Node Interface
+ // EFI_ACPI_AEST_INTERFACE_STRUCT NodeInterface;
+
+ // Node Interrupt Array
+ // EFI_ACPI_AEST_INTERRUPT_STRUCT NodeInterruptArray[n];
+} EFI_ACPI_AEST_PROCESSOR_STRUCT;
+
+// AEST Processor resource type definitions.
+#define EFI_ACPI_AEST_PROCESSOR_RESOURCE_TYPE_CACHE 0x0
+#define EFI_ACPI_AEST_PROCESSOR_RESOURCE_TYPE_TLB 0x1
+#define EFI_ACPI_AEST_PROCESSOR_RESOURCE_TYPE_GENERIC 0x2
+
+// AEST Processor flag definitions.
+#define EFI_ACPI_AEST_PROCESSOR_FLAG_GLOBAL BIT0
+#define EFI_ACPI_AEST_PROCESSOR_FLAG_SHARED BIT1
+
+///
+/// Memory Controller structure.
+///
+typedef struct {
+ /// AEST Node header
+ EFI_ACPI_AEST_NODE_STRUCT NodeHeader;
+
+ /// SRAT proximity domain.
+ UINT32 ProximityDomain;
+
+ // Node Interface
+ // EFI_ACPI_AEST_INTERFACE_STRUCT NodeInterface;
+
+ // Node Interrupt Array
+ // EFI_ACPI_AEST_INTERRUPT_STRUCT NodeInterruptArray[n];
+} EFI_ACPI_AEST_MEMORY_CONTROLLER_STRUCT;
+
+///
+/// SMMU structure.
+///
+typedef struct {
+ /// AEST Node header
+ EFI_ACPI_AEST_NODE_STRUCT NodeHeader;
+
+ /// Reference to the IORT table node that describes this SMMU.
+ UINT32 SmmuRefId;
+
+ /// Reference to the IORT table node that is associated with the
+ /// sub-component within this SMMU.
+ UINT32 SubComponentRefId;
+
+ // Node Interface
+ // EFI_ACPI_AEST_INTERFACE_STRUCT NodeInterface;
+
+ // Node Interrupt Array
+ // EFI_ACPI_AEST_INTERRUPT_STRUCT NodeInterruptArray[n];
+} EFI_ACPI_AEST_SMMU_STRUCT;
+
+///
+/// Vendor-Defined structure.
+///
+typedef struct {
+ /// AEST Node header
+ EFI_ACPI_AEST_NODE_STRUCT NodeHeader;
+
+ /// ACPI HID of the component.
+ UINT32 HardwareId;
+
+ /// The ACPI Unique identifier of the component.
+ UINT32 UniqueId;
+
+ /// Vendor-specific data, for example to identify this error source.
+ UINT8 VendorData[16];
+
+ // Node Interface
+ // EFI_ACPI_AEST_INTERFACE_STRUCT NodeInterface;
+
+ // Node Interrupt Array
+ // EFI_ACPI_AEST_INTERRUPT_STRUCT NodeInterruptArray[n];
+} EFI_ACPI_AEST_VENDOR_DEFINED_STRUCT;
+
+///
+/// GIC structure.
+///
+typedef struct {
+ /// AEST Node header
+ EFI_ACPI_AEST_NODE_STRUCT NodeHeader;
+
+ /// Type of GIC interface that is associated with this error node.
+ /// 0x0 - GIC CPU (GICC)
+ /// 0x1 - GIC Distributor (GICD)
+ /// 0x2 - GIC Resistributor (GICR)
+ /// 0x3 - GIC ITS (GITS)
+ UINT32 InterfaceType;
+
+ /// Identifier for the interface instance.
+ UINT32 GicInterfaceRefId;
+
+ // Node Interface
+ // EFI_ACPI_AEST_INTERFACE_STRUCT NodeInterface;
+
+ // Node Interrupt Array
+ // EFI_ACPI_AEST_INTERRUPT_STRUCT NodeInterruptArray[n];
+} EFI_ACPI_AEST_GIC_STRUCT;
+
+// AEST GIC interface type definitions.
+#define EFI_ACPI_AEST_GIC_INTERFACE_TYPE_GICC 0x0
+#define EFI_ACPI_AEST_GIC_INTERFACE_TYPE_GICD 0x1
+#define EFI_ACPI_AEST_GIC_INTERFACE_TYPE_GICR 0x2
+#define EFI_ACPI_AEST_GIC_INTERFACE_TYPE_GITS 0x3
+
+#pragma pack()
+
+#endif // ARM_ERROR_SOURCE_TABLE_H_
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/ArmPerformanceMonitoringUnitTable.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/ArmPerformanceMonitoringUnitTable.h
new file mode 100644
index 0000000000..a80a24479d
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/ArmPerformanceMonitoringUnitTable.h
@@ -0,0 +1,69 @@
+/** @file
+ ACPI Arm Performance Monitoring Unit (APMT) table
+ as specified in ARM spec DEN0117
+
+ Copyright (c) 2022, NVIDIA CORPORATION. All rights reserved.
+ Copyright (c) 2022, ARM Limited. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef ARM_PERFORMANCE_MONITORING_UNIT_TABLE_H_
+#define ARM_PERFORMANCE_MONITORING_UNIT_TABLE_H_
+
+#include
+
+#pragma pack(1)
+
+///
+/// Arm Performance Monitoring Unit (APMT) tabl
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+} EFI_ACPI_ARM_PERFORMANCE_MONITORING_UNIT_TABLE_HEADER;
+
+///
+/// APMT Revision (as defined in DEN0117.)
+///
+#define EFI_ACPI_ARM_PERFORMANCE_MONITORING_UNIT_TABLE_REVISION 0x00
+
+///
+/// Arm PMU Node Structure
+///
+
+// Node Flags
+#define EFI_ACPI_APMT_DUAL_PAGE_EXTENSION_SUPPORTED BIT0
+#define EFI_ACPI_APMT_PROCESSOR_AFFINITY_TYPE_CONTAINER BIT1
+#define EFI_ACPI_APMT_PROCESSOR_AFFINITY_TYPE_PROCESSOR 0 // BIT 1
+#define EFI_ACPI_APMT_64BIT_SINGLE_COPY_ATOMICITY_SUPPORTED BIT2
+
+// Interrupt Flags
+#define EFI_ACPI_APMT_INTERRUPT_MODE_EDGE_TRIGGERED BIT0
+#define EFI_ACPI_APMT_INTERRUPT_MODE_LEVEL_TRIGGERED 0 // BIT 0
+#define EFI_ACPI_APMT_INTERRUPT_TYPE_WIRED 0 // BIT 1
+
+// Node Type
+#define EFI_ACPI_APMT_NODE_TYPE_MEMORY_CONTROLLER 0x00
+#define EFI_ACPI_APMT_NODE_TYPE_SMMU 0x01
+#define EFI_ACPI_APMT_NODE_TYPE_PCIE_ROOT_COMPLEX 0x02
+#define EFI_ACPI_APMT_NODE_TYPE_ACPI_DEVICE 0x03
+#define EFI_ACPI_APMT_NODE_TYPE_CPU_CACHE 0x04
+
+typedef struct {
+ UINT16 Length;
+ UINT8 NodeFlags;
+ UINT8 NodeType;
+ UINT32 Identifier;
+ UINT64 NodeInstancePrimary;
+ UINT32 NodeInstanceSecondary;
+ UINT64 BaseAddress0;
+ UINT64 BaseAddress1;
+ UINT32 OverflowInterrupt;
+ UINT32 Reserved1;
+ UINT32 OverflowInterruptFlags;
+ UINT32 ProcessorAffinity;
+ UINT32 ImplementationId;
+} EFI_ACPI_ARM_PERFORMANCE_MONITORING_UNIT_NODE;
+
+#pragma pack()
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/Atapi.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/Atapi.h
new file mode 100644
index 0000000000..7f11302bfa
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/Atapi.h
@@ -0,0 +1,849 @@
+/** @file
+ This file contains just some basic definitions that are needed by drivers
+ that dealing with ATA/ATAPI interface.
+
+Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _ATAPI_H_
+#define _ATAPI_H_
+
+#pragma pack(1)
+
+///
+/// ATA5_IDENTIFY_DATA is defined in ATA-5.
+/// (This structure is provided mainly for backward-compatibility support.
+/// Old drivers may reference fields that are marked "obsolete" in
+/// ATA_IDENTIFY_DATA, which currently conforms to ATA-8.)
+///
+typedef struct {
+ UINT16 config; ///< General Configuration.
+ UINT16 cylinders; ///< Number of Cylinders.
+ UINT16 reserved_2;
+ UINT16 heads; ///< Number of logical heads.
+ UINT16 vendor_data1;
+ UINT16 vendor_data2;
+ UINT16 sectors_per_track;
+ UINT16 vendor_specific_7_9[3];
+ CHAR8 SerialNo[20]; ///< ASCII
+ UINT16 vendor_specific_20_21[2];
+ UINT16 ecc_bytes_available;
+ CHAR8 FirmwareVer[8]; ///< ASCII
+ CHAR8 ModelName[40]; ///< ASCII
+ UINT16 multi_sector_cmd_max_sct_cnt;
+ UINT16 reserved_48;
+ UINT16 capabilities;
+ UINT16 reserved_50;
+ UINT16 pio_cycle_timing;
+ UINT16 reserved_52;
+ UINT16 field_validity;
+ UINT16 current_cylinders;
+ UINT16 current_heads;
+ UINT16 current_sectors;
+ UINT16 CurrentCapacityLsb;
+ UINT16 CurrentCapacityMsb;
+ UINT16 reserved_59;
+ UINT16 user_addressable_sectors_lo;
+ UINT16 user_addressable_sectors_hi;
+ UINT16 reserved_62;
+ UINT16 multi_word_dma_mode;
+ UINT16 advanced_pio_modes;
+ UINT16 min_multi_word_dma_cycle_time;
+ UINT16 rec_multi_word_dma_cycle_time;
+ UINT16 min_pio_cycle_time_without_flow_control;
+ UINT16 min_pio_cycle_time_with_flow_control;
+ UINT16 reserved_69_79[11];
+ UINT16 major_version_no;
+ UINT16 minor_version_no;
+ UINT16 command_set_supported_82; ///< word 82
+ UINT16 command_set_supported_83; ///< word 83
+ UINT16 command_set_feature_extn; ///< word 84
+ UINT16 command_set_feature_enb_85; ///< word 85
+ UINT16 command_set_feature_enb_86; ///< word 86
+ UINT16 command_set_feature_default; ///< word 87
+ UINT16 ultra_dma_mode; ///< word 88
+ UINT16 reserved_89_127[39];
+ UINT16 security_status;
+ UINT16 vendor_data_129_159[31];
+ UINT16 reserved_160_255[96];
+} ATA5_IDENTIFY_DATA;
+
+///
+/// ATA_IDENTIFY_DATA strictly complies with ATA/ATAPI-8 Spec
+/// to define the data returned by an ATA device upon successful
+/// completion of the ATA IDENTIFY_DEVICE command.
+///
+typedef struct {
+ UINT16 config; ///< General Configuration.
+ UINT16 obsolete_1;
+ UINT16 specific_config; ///< Specific Configuration.
+ UINT16 obsolete_3;
+ UINT16 retired_4_5[2];
+ UINT16 obsolete_6;
+ UINT16 cfa_reserved_7_8[2];
+ UINT16 retired_9;
+ CHAR8 SerialNo[20]; ///< word 10~19
+ UINT16 retired_20_21[2];
+ UINT16 obsolete_22;
+ CHAR8 FirmwareVer[8]; ///< word 23~26
+ CHAR8 ModelName[40]; ///< word 27~46
+ UINT16 multi_sector_cmd_max_sct_cnt;
+ UINT16 trusted_computing_support;
+ UINT16 capabilities_49;
+ UINT16 capabilities_50;
+ UINT16 obsolete_51_52[2];
+ UINT16 field_validity;
+ UINT16 obsolete_54_58[5];
+ UINT16 multi_sector_setting;
+ UINT16 user_addressable_sectors_lo;
+ UINT16 user_addressable_sectors_hi;
+ UINT16 obsolete_62;
+ UINT16 multi_word_dma_mode;
+ UINT16 advanced_pio_modes;
+ UINT16 min_multi_word_dma_cycle_time;
+ UINT16 rec_multi_word_dma_cycle_time;
+ UINT16 min_pio_cycle_time_without_flow_control;
+ UINT16 min_pio_cycle_time_with_flow_control;
+ UINT16 additional_supported; ///< word 69
+ UINT16 reserved_70;
+ UINT16 reserved_71_74[4]; ///< Reserved for IDENTIFY PACKET DEVICE cmd.
+ UINT16 queue_depth;
+ UINT16 serial_ata_capabilities;
+ UINT16 reserved_77; ///< Reserved for Serial ATA
+ UINT16 serial_ata_features_supported;
+ UINT16 serial_ata_features_enabled;
+ UINT16 major_version_no;
+ UINT16 minor_version_no;
+ UINT16 command_set_supported_82; ///< word 82
+ UINT16 command_set_supported_83; ///< word 83
+ UINT16 command_set_feature_extn; ///< word 84
+ UINT16 command_set_feature_enb_85; ///< word 85
+ UINT16 command_set_feature_enb_86; ///< word 86
+ UINT16 command_set_feature_default; ///< word 87
+ UINT16 ultra_dma_mode; ///< word 88
+ UINT16 time_for_security_erase_unit;
+ UINT16 time_for_enhanced_security_erase_unit;
+ UINT16 advanced_power_management_level;
+ UINT16 master_password_identifier;
+ UINT16 hardware_configuration_test_result;
+ UINT16 obsolete_94;
+ UINT16 stream_minimum_request_size;
+ UINT16 streaming_transfer_time_for_dma;
+ UINT16 streaming_access_latency_for_dma_and_pio;
+ UINT16 streaming_performance_granularity[2]; ///< word 98~99
+ UINT16 maximum_lba_for_48bit_addressing[4]; ///< word 100~103
+ UINT16 streaming_transfer_time_for_pio;
+ UINT16 max_no_of_512byte_blocks_per_data_set_cmd;
+ UINT16 phy_logic_sector_support; ///< word 106
+ UINT16 interseek_delay_for_iso7779;
+ UINT16 world_wide_name[4]; ///< word 108~111
+ UINT16 reserved_for_128bit_wwn_112_115[4];
+ UINT16 reserved_for_technical_report;
+ UINT16 logic_sector_size_lo; ///< word 117
+ UINT16 logic_sector_size_hi; ///< word 118
+ UINT16 features_and_command_sets_supported_ext; ///< word 119
+ UINT16 features_and_command_sets_enabled_ext; ///< word 120
+ UINT16 reserved_121_126[6];
+ UINT16 obsolete_127;
+ UINT16 security_status; ///< word 128
+ UINT16 vendor_specific_129_159[31];
+ UINT16 cfa_power_mode; ///< word 160
+ UINT16 reserved_for_compactflash_161_167[7];
+ UINT16 device_nominal_form_factor;
+ UINT16 is_data_set_cmd_supported;
+ CHAR8 additional_product_identifier[8];
+ UINT16 reserved_174_175[2];
+ CHAR8 media_serial_number[60]; ///< word 176~205
+ UINT16 sct_command_transport; ///< word 206
+ UINT16 reserved_207_208[2];
+ UINT16 alignment_logic_in_phy_blocks; ///< word 209
+ UINT16 write_read_verify_sector_count_mode3[2]; ///< word 210~211
+ UINT16 verify_sector_count_mode2[2];
+ UINT16 nv_cache_capabilities;
+ UINT16 nv_cache_size_in_logical_block_lsw; ///< word 215
+ UINT16 nv_cache_size_in_logical_block_msw; ///< word 216
+ UINT16 nominal_media_rotation_rate;
+ UINT16 reserved_218;
+ UINT16 nv_cache_options; ///< word 219
+ UINT16 write_read_verify_mode; ///< word 220
+ UINT16 reserved_221;
+ UINT16 transport_major_revision_number;
+ UINT16 transport_minor_revision_number;
+ UINT16 reserved_224_229[6];
+ UINT64 extended_no_of_addressable_sectors;
+ UINT16 min_number_per_download_microcode_mode3; ///< word 234
+ UINT16 max_number_per_download_microcode_mode3; ///< word 235
+ UINT16 reserved_236_254[19];
+ UINT16 integrity_word;
+} ATA_IDENTIFY_DATA;
+
+///
+/// ATAPI_IDENTIFY_DATA strictly complies with ATA/ATAPI-8 Spec
+/// to define the data returned by an ATAPI device upon successful
+/// completion of the ATA IDENTIFY_PACKET_DEVICE command.
+///
+typedef struct {
+ UINT16 config; ///< General Configuration.
+ UINT16 reserved_1;
+ UINT16 specific_config; ///< Specific Configuration.
+ UINT16 reserved_3_9[7];
+ CHAR8 SerialNo[20]; ///< word 10~19
+ UINT16 reserved_20_22[3];
+ CHAR8 FirmwareVer[8]; ///< word 23~26
+ CHAR8 ModelName[40]; ///< word 27~46
+ UINT16 reserved_47_48[2];
+ UINT16 capabilities_49;
+ UINT16 capabilities_50;
+ UINT16 obsolete_51;
+ UINT16 reserved_52;
+ UINT16 field_validity; ///< word 53
+ UINT16 reserved_54_61[8];
+ UINT16 dma_dir;
+ UINT16 multi_word_dma_mode; ///< word 63
+ UINT16 advanced_pio_modes; ///< word 64
+ UINT16 min_multi_word_dma_cycle_time;
+ UINT16 rec_multi_word_dma_cycle_time;
+ UINT16 min_pio_cycle_time_without_flow_control;
+ UINT16 min_pio_cycle_time_with_flow_control;
+ UINT16 reserved_69_70[2];
+ UINT16 obsolete_71_72[2];
+ UINT16 reserved_73_74[2];
+ UINT16 obsolete_75;
+ UINT16 serial_ata_capabilities;
+ UINT16 reserved_77; ///< Reserved for Serial ATA
+ UINT16 serial_ata_features_supported;
+ UINT16 serial_ata_features_enabled;
+ UINT16 major_version_no; ///< word 80
+ UINT16 minor_version_no; ///< word 81
+ UINT16 cmd_set_support_82;
+ UINT16 cmd_set_support_83;
+ UINT16 cmd_feature_support;
+ UINT16 cmd_feature_enable_85;
+ UINT16 cmd_feature_enable_86;
+ UINT16 cmd_feature_default;
+ UINT16 ultra_dma_select;
+ UINT16 time_required_for_sec_erase; ///< word 89
+ UINT16 time_required_for_enhanced_sec_erase; ///< word 90
+ UINT16 advanced_power_management_level;
+ UINT16 master_pwd_revison_code;
+ UINT16 hardware_reset_result; ///< word 93
+ UINT16 obsolete_94;
+ UINT16 reserved_95_107[13];
+ UINT16 world_wide_name[4]; ///< word 108~111
+ UINT16 reserved_for_128bit_wwn_112_115[4];
+ UINT16 reserved_116_118[3];
+ UINT16 command_and_feature_sets_supported; ///< word 119
+ UINT16 command_and_feature_sets_supported_enabled;
+ UINT16 reserved_121_124[4];
+ UINT16 atapi_byte_count_0_behavior; ///< word 125
+ UINT16 obsolete_126_127[2];
+ UINT16 security_status;
+ UINT16 reserved_129_159[31];
+ UINT16 cfa_reserved_160_175[16];
+ UINT16 reserved_176_221[46];
+ UINT16 transport_major_version;
+ UINT16 transport_minor_version;
+ UINT16 reserved_224_254[31];
+ UINT16 integrity_word;
+} ATAPI_IDENTIFY_DATA;
+
+///
+/// Standard Quiry Data format, defined in SFF-8070i(ATAPI Removable Rewritable Specification).
+///
+typedef struct {
+ UINT8 peripheral_type;
+ UINT8 RMB;
+ UINT8 version;
+ UINT8 response_data_format;
+ UINT8 addnl_length; ///< n - 4, Numbers of bytes following this one.
+ UINT8 reserved_5;
+ UINT8 reserved_6;
+ UINT8 reserved_7;
+ UINT8 vendor_info[8];
+ UINT8 product_id[16];
+ UINT8 product_revision_level[4];
+ UINT8 vendor_specific_36_55[55 - 36 + 1];
+ UINT8 reserved_56_95[95 - 56 + 1];
+ ///
+ /// Vendor-specific parameters fields. The sizeof (ATAPI_INQUIRY_DATA) is 254
+ /// since allocation_length is one byte in ATAPI_INQUIRY_CMD.
+ ///
+ UINT8 vendor_specific_96_253[253 - 96 + 1];
+} ATAPI_INQUIRY_DATA;
+
+///
+/// Request Sense Standard Data, defined in SFF-8070i(ATAPI Removable Rewritable Specification).
+///
+typedef struct {
+ UINT8 error_code : 7;
+ UINT8 valid : 1;
+ UINT8 reserved_1;
+ UINT8 sense_key : 4;
+ UINT8 reserved_2 : 1;
+ UINT8 Vendor_specifc_1 : 3;
+ UINT8 vendor_specific_3;
+ UINT8 vendor_specific_4;
+ UINT8 vendor_specific_5;
+ UINT8 vendor_specific_6;
+ UINT8 addnl_sense_length; ///< n - 7
+ UINT8 vendor_specific_8;
+ UINT8 vendor_specific_9;
+ UINT8 vendor_specific_10;
+ UINT8 vendor_specific_11;
+ UINT8 addnl_sense_code; ///< mandatory
+ UINT8 addnl_sense_code_qualifier; ///< mandatory
+ UINT8 field_replaceable_unit_code; ///< optional
+ UINT8 sense_key_specific_15 : 7;
+ UINT8 SKSV : 1;
+ UINT8 sense_key_specific_16;
+ UINT8 sense_key_specific_17;
+} ATAPI_REQUEST_SENSE_DATA;
+
+///
+/// READ CAPACITY Data, defined in SFF-8070i(ATAPI Removable Rewritable Specification).
+///
+typedef struct {
+ UINT8 LastLba3;
+ UINT8 LastLba2;
+ UINT8 LastLba1;
+ UINT8 LastLba0;
+ UINT8 BlockSize3;
+ UINT8 BlockSize2;
+ UINT8 BlockSize1;
+ UINT8 BlockSize0;
+} ATAPI_READ_CAPACITY_DATA;
+
+///
+/// Capacity List Header + Current/Maximum Capacity Descriptor,
+/// defined in SFF-8070i(ATAPI Removable Rewritable Specification).
+///
+typedef struct {
+ UINT8 reserved_0;
+ UINT8 reserved_1;
+ UINT8 reserved_2;
+ UINT8 Capacity_Length;
+ UINT8 LastLba3;
+ UINT8 LastLba2;
+ UINT8 LastLba1;
+ UINT8 LastLba0;
+ UINT8 DesCode : 2;
+ UINT8 reserved_9 : 6;
+ UINT8 BlockSize2;
+ UINT8 BlockSize1;
+ UINT8 BlockSize0;
+} ATAPI_READ_FORMAT_CAPACITY_DATA;
+
+///
+/// Test Unit Ready Command, defined in SFF-8070i(ATAPI Removable Rewritable Specification).
+///
+typedef struct {
+ UINT8 opcode;
+ UINT8 reserved_1;
+ UINT8 reserved_2;
+ UINT8 reserved_3;
+ UINT8 reserved_4;
+ UINT8 reserved_5;
+ UINT8 reserved_6;
+ UINT8 reserved_7;
+ UINT8 reserved_8;
+ UINT8 reserved_9;
+ UINT8 reserved_10;
+ UINT8 reserved_11;
+} ATAPI_TEST_UNIT_READY_CMD;
+
+///
+/// INQUIRY Command, defined in SFF-8070i(ATAPI Removable Rewritable Specification).
+///
+typedef struct {
+ UINT8 opcode;
+ UINT8 reserved_1 : 5;
+ UINT8 lun : 3;
+ UINT8 page_code; ///< defined in SFF8090i, V6
+ UINT8 reserved_3;
+ UINT8 allocation_length;
+ UINT8 reserved_5;
+ UINT8 reserved_6;
+ UINT8 reserved_7;
+ UINT8 reserved_8;
+ UINT8 reserved_9;
+ UINT8 reserved_10;
+ UINT8 reserved_11;
+} ATAPI_INQUIRY_CMD;
+
+///
+/// REQUEST SENSE Command, defined in SFF-8070i(ATAPI Removable Rewritable Specification).
+///
+typedef struct {
+ UINT8 opcode;
+ UINT8 reserved_1 : 5;
+ UINT8 lun : 3;
+ UINT8 reserved_2;
+ UINT8 reserved_3;
+ UINT8 allocation_length;
+ UINT8 reserved_5;
+ UINT8 reserved_6;
+ UINT8 reserved_7;
+ UINT8 reserved_8;
+ UINT8 reserved_9;
+ UINT8 reserved_10;
+ UINT8 reserved_11;
+} ATAPI_REQUEST_SENSE_CMD;
+
+///
+/// READ (10) Command, defined in SFF-8070i(ATAPI Removable Rewritable Specification).
+///
+typedef struct {
+ UINT8 opcode;
+ UINT8 reserved_1 : 5;
+ UINT8 lun : 3;
+ UINT8 Lba0;
+ UINT8 Lba1;
+ UINT8 Lba2;
+ UINT8 Lba3;
+ UINT8 reserved_6;
+ UINT8 TranLen0;
+ UINT8 TranLen1;
+ UINT8 reserved_9;
+ UINT8 reserved_10;
+ UINT8 reserved_11;
+} ATAPI_READ10_CMD;
+
+///
+/// READ Format Capacity Command, defined in SFF-8070i(ATAPI Removable Rewritable Specification).
+///
+typedef struct {
+ UINT8 opcode;
+ UINT8 reserved_1 : 5;
+ UINT8 lun : 3;
+ UINT8 reserved_2;
+ UINT8 reserved_3;
+ UINT8 reserved_4;
+ UINT8 reserved_5;
+ UINT8 reserved_6;
+ UINT8 allocation_length_hi;
+ UINT8 allocation_length_lo;
+ UINT8 reserved_9;
+ UINT8 reserved_10;
+ UINT8 reserved_11;
+} ATAPI_READ_FORMAT_CAP_CMD;
+
+///
+/// MODE SENSE Command, defined in SFF-8070i(ATAPI Removable Rewritable Specification).
+///
+typedef struct {
+ UINT8 opcode;
+ UINT8 reserved_1 : 5;
+ UINT8 lun : 3;
+ UINT8 page_code : 6;
+ UINT8 page_control : 2;
+ UINT8 reserved_3;
+ UINT8 reserved_4;
+ UINT8 reserved_5;
+ UINT8 reserved_6;
+ UINT8 parameter_list_length_hi;
+ UINT8 parameter_list_length_lo;
+ UINT8 reserved_9;
+ UINT8 reserved_10;
+ UINT8 reserved_11;
+} ATAPI_MODE_SENSE_CMD;
+
+///
+/// ATAPI_PACKET_COMMAND is not defined in the ATA specification.
+/// We add it here for the convenience of ATA/ATAPI module writers.
+///
+typedef union {
+ UINT16 Data16[6];
+ ATAPI_TEST_UNIT_READY_CMD TestUnitReady;
+ ATAPI_READ10_CMD Read10;
+ ATAPI_REQUEST_SENSE_CMD RequestSence;
+ ATAPI_INQUIRY_CMD Inquiry;
+ ATAPI_MODE_SENSE_CMD ModeSense;
+ ATAPI_READ_FORMAT_CAP_CMD ReadFormatCapacity;
+} ATAPI_PACKET_COMMAND;
+
+#pragma pack()
+
+#define ATAPI_MAX_DMA_EXT_CMD_SECTORS 0x10000
+#define ATAPI_MAX_DMA_CMD_SECTORS 0x100
+
+// ATA/ATAPI Signature equates
+#define ATA_SIGNATURE 0x0101 ///< defined in ACS-3
+#define ATAPI_SIGNATURE 0xeb14 ///< defined in ACS-3
+#define ATAPI_SIGNATURE_32 0xeb140101 ///< defined in ACS-3
+
+// Spin Up Configuration definitions
+#define ATA_SPINUP_CFG_REQUIRED_IDD_INCOMPLETE 0x37c8 ///< defined in ACS-3
+#define ATA_SPINUP_CFG_REQUIRED_IDD_COMPLETE 0x738c ///< defined in ACS-3
+#define ATA_SPINUP_CFG_NOT_REQUIRED_IDD_INCOMPLETE 0x8c73 ///< defined in ACS-3
+#define ATA_SPINUP_CFG_NOT_REQUIRED_IDD_COMPLETE 0xc837 ///< defined in ACS-3
+
+//
+// ATA Packet Command Code
+//
+#define ATA_CMD_FORMAT_UNIT 0x04 ///< defined in ATAPI Removable Rewritable Media Devices
+#define ATA_CMD_SOFT_RESET 0x08 ///< defined from ATA-3
+#define ATA_CMD_PACKET 0xA0 ///< defined from ATA-3
+#define ATA_CMD_IDENTIFY_DEVICE 0xA1 ///< defined from ATA-3
+#define ATA_CMD_SERVICE 0xA2 ///< defined from ATA-3
+#define ATA_CMD_TEST_UNIT_READY 0x00 ///< defined from ATA-1
+#define ATA_CMD_REQUEST_SENSE 0x03 ///< defined from ATA-4
+#define ATA_CMD_INQUIRY 0x12 ///< defined in ATAPI Removable Rewritable Media Devices
+#define ATA_CMD_READ_FORMAT_CAPACITY 0x23 ///< defined in ATAPI Removable Rewritable Media Devices
+#define ATA_CMD_READ_CAPACITY 0x25 ///< defined in ATAPI Removable Rewritable Media Devices
+#define ATA_CMD_READ_10 0x28 ///< defined in ATAPI Removable Rewritable Media Devices
+#define ATA_CMD_WRITE_10 0x2A ///< defined in ATAPI Removable Rewritable Media Devices
+#define ATA_CMD_ATAPI_SEEK 0x2B ///< defined in ATAPI Removable Rewritable Media Devices
+#define ATA_CMD_WRITE_AND_VERIFY 0x2E ///< defined in ATAPI Removable Rewritable Media Devices
+#define ATA_CMD_VERIFY 0x2F ///< defined in ATAPI Removable Rewritable Media Devices
+#define ATA_CMD_READ_12 0xA8 ///< defined in ATAPI Removable Rewritable Media Devices
+#define ATA_CMD_WRITE_12 0xAA ///< defined in ATAPI Removable Rewritable Media Devices
+#define ATA_CMD_START_STOP_UNIT 0x1B ///< defined in ATAPI Removable Rewritable Media Devices
+#define ATA_CMD_PREVENT_ALLOW_MEDIA_REMOVAL 0x1E ///< defined in ATAPI Removable Rewritable Media Devices
+#define ATA_CMD_MODE_SELECT 0x55 ///< defined in ATAPI Removable Rewritable Media Devices
+
+#define ATA_CMD_MODE_SENSE 0x5A ///< defined in ATAPI Removable Rewritable Media Devices
+#define ATA_PAGE_CODE_READ_WRITE_ERROR 0x01 ///< defined in ATAPI Removable Rewritable Media Devices
+#define ATA_PAGE_CODE_CACHING_PAGE 0x08 ///< defined in ATAPI Removable Rewritable Media Devices
+#define ATA_PAGE_CODE_REMOVABLE_BLOCK_CAPABILITIES 0x1B ///< defined in ATAPI Removable Rewritable Media Devices
+#define ATA_PAGE_CODE_TIMER_PROTECT_PAGE 0x1C ///< defined in ATAPI Removable Rewritable Media Devices
+#define ATA_PAGE_CODE_RETURN_ALL_PAGES 0x3F ///< defined in ATAPI Removable Rewritable Media Devices
+
+#define ATA_CMD_GET_CONFIGURATION 0x46 ///< defined in ATAPI Multimedia Devices
+#define ATA_GCCD_RT_FIELD_VALUE_ALL 0x00 ///< defined in ATAPI Multimedia Devices
+#define ATA_GCCD_RT_FIELD_VALUE_CURRENT 0x01 ///< defined in ATAPI Multimedia Devices
+#define ATA_GCCD_RT_FIELD_VALUE_SINGLE 0x02 ///< defined in ATAPI Multimedia Devices
+#define ATA_GCCD_RT_FIELD_VALUE_RESERVED 0x03 ///< defined in ATAPI Multimedia Devices
+
+#define ATA_FEATURE_LIST_PROFILE_LIST 0x0000 ///< defined in ATAPI Multimedia Devices
+#define ATA_FEATURE_LIST_CORE 0x0001 ///< defined in ATAPI Multimedia Devices
+#define ATA_FEATURE_LIST_MORPHING 0x0002 ///< defined in ATAPI Multimedia Devices
+#define ATA_FEATURE_LIST_REMOVEABLE_MEDIUM 0x0003 ///< defined in ATAPI Multimedia Devices
+#define ATA_FEATURE_LIST_WRITE_PROTECT 0x0004 ///< defined in ATAPI Multimedia Devices
+
+///
+/// Start/Stop and Eject Operations
+///
+///@{
+#define ATA_CMD_SUBOP_STOP_DISC 0x00 ///< Stop the Disc
+#define ATA_CMD_SUBOP_START_DISC 0x01 ///< Start the Disc and acquire the format type
+#define ATA_CMD_SUBOP_EJECT_DISC 0x02 ///< Eject the Disc if possible
+#define ATA_CMD_SUBOP_CLOSE_TRAY 0x03 ///< Load the Disc (Close Tray)
+///@}
+
+//
+// ATA Commands Code
+//
+
+//
+// Class 1: PIO Data-In Commands
+//
+#define ATA_CMD_IDENTIFY_DRIVE 0xec ///< defined from ATA-3
+#define ATA_CMD_READ_BUFFER 0xe4 ///< defined from ATA-1
+#define ATA_CMD_READ_SECTORS 0x20 ///< defined from ATA-1
+#define ATA_CMD_READ_SECTORS_WITH_RETRY 0x21 ///< defined from ATA-1, obsoleted from ATA-5
+#define ATA_CMD_READ_LONG 0x22 ///< defined from ATA-1, obsoleted from ATA-5
+#define ATA_CMD_READ_LONG_WITH_RETRY 0x23 ///< defined from ATA-1, obsoleted from ATA-5
+#define ATA_CMD_READ_SECTORS_EXT 0x24 ///< defined from ATA-6
+#define ATA_CMD_READ_MULTIPLE 0xc4 ///< defined in ACS-3
+#define ATA_CMD_READ_MULTIPLE_EXT 0x29 ///< defined in ACS-3
+#define ATA_CMD_READ_LOG_EXT 0x2f ///< defined in ACS-3
+
+//
+// Class 2: PIO Data-Out Commands
+//
+#define ATA_CMD_FORMAT_TRACK 0x50 ///< defined from ATA-1, obsoleted from ATA-4
+#define ATA_CMD_WRITE_BUFFER 0xe8 ///< defined from ATA-1
+#define ATA_CMD_WRITE_SECTORS 0x30 ///< defined from ATA-1
+#define ATA_CMD_WRITE_SECTORS_WITH_RETRY 0x31 ///< defined from ATA-1, obsoleted from ATA-5
+#define ATA_CMD_WRITE_LONG 0x32 ///< defined from ATA-1, obsoleted from ATA-5
+#define ATA_CMD_WRITE_LONG_WITH_RETRY 0x33 ///< defined from ATA-1, obsoleted from ATA-5
+#define ATA_CMD_WRITE_VERIFY 0x3c ///< defined from ATA-1, obsoleted from ATA-5
+#define ATA_CMD_WRITE_SECTORS_EXT 0x34 ///< defined from ATA-6
+#define ATA_CMD_WRITE_MULTIPLE 0xc5 ///< defined in ACS-3
+#define ATA_CMD_WRITE_MULTIPLE_EXT 0x39 ///< defined in ACS-3
+
+//
+// Class 3 No Data Command
+//
+#define ATA_CMD_ACK_MEDIA_CHANGE 0xdb ///< defined from ATA-1, obsoleted from ATA-5
+#define ATA_CMD_BOOT_POST_BOOT 0xdc ///< defined from ATA-1, obsoleted from ATA-3
+#define ATA_CMD_BOOT_PRE_BOOT 0xdd ///< defined from ATA-1, obsoleted from ATA-3
+#define ATA_CMD_CHECK_POWER_MODE 0x98 ///< defined from ATA-1, obsoleted from ATA-4
+#define ATA_CMD_CHECK_POWER_MODE_ALIAS 0xe5 ///< defined from ATA-1
+#define ATA_CMD_DOOR_LOCK 0xde ///< defined from ATA-1
+#define ATA_CMD_DOOR_UNLOCK 0xdf ///< defined from ATA-1
+#define ATA_CMD_EXEC_DRIVE_DIAG 0x90 ///< defined from ATA-1
+#define ATA_CMD_IDLE_ALIAS 0x97 ///< defined from ATA-1, obsoleted from ATA-4
+#define ATA_CMD_IDLE 0xe3 ///< defined from ATA-1
+#define ATA_CMD_IDLE_IMMEDIATE 0x95 ///< defined from ATA-1, obsoleted from ATA-4
+#define ATA_CMD_IDLE_IMMEDIATE_ALIAS 0xe1 ///< defined from ATA-1
+#define ATA_CMD_INIT_DRIVE_PARAM 0x91 ///< defined from ATA-1, obsoleted from ATA-6
+#define ATA_CMD_RECALIBRATE 0x10 ///< defined from ATA-1, obsoleted from ATA-4
+#define ATA_CMD_READ_DRIVE_STATE 0xe9 ///< defined from ATA-1, obsoleted from ATA-3
+#define ATA_CMD_SET_MULTIPLE_MODE 0xC6 ///< defined from ATA-2
+#define ATA_CMD_READ_VERIFY 0x40 ///< defined from ATA-1
+#define ATA_CMD_READ_VERIFY_WITH_RETRY 0x41 ///< defined from ATA-1, obsoleted from ATA-5
+#define ATA_CMD_SEEK 0x70 ///< defined from ATA-1
+#define ATA_CMD_SET_FEATURES 0xef ///< defined from ATA-1
+#define ATA_CMD_STANDBY 0x96 ///< defined from ATA-1, obsoleted from ATA-4
+#define ATA_CMD_STANDBY_ALIAS 0xe2 ///< defined from ATA-1
+#define ATA_CMD_STANDBY_IMMEDIATE 0x94 ///< defined from ATA-1, obsoleted from ATA-4
+#define ATA_CMD_STANDBY_IMMEDIATE_ALIAS 0xe0 ///< defined from ATA-1
+#define ATA_CMD_SLEEP 0xe6 ///< defined in ACS-3
+#define ATA_CMD_READ_NATIVE_MAX_ADDRESS 0xf8 ///< defined in ATA-6
+#define ATA_CMD_READ_NATIVE_MAX_ADDRESS_EXT 0x27 ///< defined in ATA-6
+
+//
+// Set Features Sub Command
+//
+#define ATA_SUB_CMD_ENABLE_VOLATILE_WRITE_CACHE 0x02 ///< defined in ACS-3
+#define ATA_SUB_CMD_SET_TRANSFER_MODE 0x03 ///< defined in ACS-3
+#define ATA_SUB_CMD_ENABLE_APM 0x05 ///< defined in ACS-3
+#define ATA_SUB_CMD_ENABLE_PUIS 0x06 ///< defined in ACS-3
+#define ATA_SUB_CMD_PUIS_SET_DEVICE_SPINUP 0x07 ///< defined in ACS-3
+#define ATA_SUB_CMD_ENABLE_WRITE_READ_VERIFY 0x0b ///< defined in ACS-3
+#define ATA_SUB_CMD_ENABLE_SATA_FEATURE 0x10 ///< defined in ACS-3
+#define ATA_SUB_CMD_DISABLE_MEDIA_STATUS_NOTIFICATION 0x31 ///< defined in ACS-3
+#define ATA_SUB_CMD_ENABLE_FREE_FALL_CONTROL 0x41 ///< defined in ACS-3
+#define ATA_SUB_CMD_ACOUSTIC_MANAGEMENT_ENABLE 0x42 ///< defined in ACS-3
+#define ATA_SUB_CMD_SET_MAX_HOST_INTERFACE_SECTOR_TIMES 0x43 ///< defined in ACS-3
+#define ATA_SUB_CMD_EXTENDED_POWER_CONDITIONS 0x4a ///< defined in ACS-3
+#define ATA_SUB_CMD_DISABLE_READ_LOOK_AHEAD 0x55 ///< defined in ACS-3
+#define ATA_SUB_CMD_EN_DIS_DSN_FEATURE 0x63 ///< defined in ACS-3
+#define ATA_SUB_CMD_DISABLE_REVERT_TO_POWER_ON_DEFAULTS 0x66 ///< defined in ACS-3
+#define ATA_SUB_CMD_DISABLE_VOLATILE_WRITE_CACHE 0x82 ///< defined in ACS-3
+#define ATA_SUB_CMD_DISABLE_APM 0x85 ///< defined in ACS-3
+#define ATA_SUB_CMD_DISABLE_PUIS 0x86 ///< defined in ACS-3
+#define ATA_SUB_CMD_DISABLE_WRITE_READ_VERIFY 0x8b ///< defined in ACS-3
+#define ATA_SUB_CMD_DISABLE_SATA_FEATURE 0x90 ///< defined in ACS-3
+#define ATA_SUB_CMD_ENABLE_MEDIA_STATUS_NOTIFICATION 0x95 ///< defined in ACS-3
+#define ATA_SUB_CMD_ENABLE_READ_LOOK_AHEAD 0xaa ///< defined in ACS-3
+#define ATA_SUB_CMD_DISABLE_FREE_FALL_CONTROL 0xc1 ///< defined in ACS-3
+#define ATA_SUB_CMD_ACOUSTIC_MANAGEMENT_DISABLE 0xc2 ///< defined in ACS-3
+#define ATA_SUB_CMD_EN_DIS_SENSE_DATA_REPORTING 0xc3 ///< defined in ACS-3
+#define ATA_SUB_CMD_ENABLE_REVERT_TO_POWER_ON_DEFAULTS 0xcc ///< defined in ACS-3
+
+//
+// S.M.A.R.T
+//
+#define ATA_CMD_SMART 0xb0 ///< defined from ATA-3
+#define ATA_CONSTANT_C2 0xc2 ///< reserved
+#define ATA_CONSTANT_4F 0x4f ///< reserved
+
+#define ATA_SMART_READ_DATA 0xd0 ///< defined in ACS-3
+
+#define ATA_SMART_AUTOSAVE 0xd2 ///< defined in ACS-3
+#define ATA_AUTOSAVE_DISABLE_ATTR 0x00
+#define ATA_AUTOSAVE_ENABLE_ATTR 0xf1
+
+#define ATA_SMART_EXECUTE_OFFLINE_IMMEDIATE 0xd4 ///< defined in ACS-3
+#define ATA_EXECUTE_SMART_OFFLINE_ROUTINE 0x00 ///< defined in ACS-3
+#define ATA_EXECUTE_SMART_OFFLINE_SHORT_SELFTEST 0x01 ///< defined in ACS-3
+#define ATA_EXECUTE_SMART_OFFLINE_EXTENDED_SELFTEST 0x02 ///< defined in ACS-3
+#define ATA_EXECUTE_SMART_OFFLINE_CONVEYANCE_SELFTEST 0x03 ///< defined in ACS-3
+#define ATA_EXECUTE_SMART_OFFLINE_SELECTIVE_SELFTEST 0x04 ///< defined in ACS-3
+#define ATA_SMART_ABORT_SELF_TEST_SUBROUTINE 0x7f ///< defined in ACS-3
+#define ATA_EXECUTE_SMART_CAPTIVE_SHORT_SELFTEST 0x81 ///< defined in ACS-3
+#define ATA_EXECUTE_SMART_CAPTIVE_EXTENDED_SELFTEST 0x82 ///< defined in ACS-3
+#define ATA_EXECUTE_SMART_CAPTIVE_CONVEYANCE_SELFTEST 0x83 ///< defined in ACS-3
+#define ATA_EXECUTE_SMART_CAPTIVE_SELECTIVE_SELFTEST 0x84 ///< defined in ACS-3
+
+#define ATA_SMART_READLOG 0xd5 ///< defined in ACS-3
+#define ATA_SMART_WRITELOG 0xd6 ///< defined in ACS-3
+#define ATA_SMART_ENABLE_OPERATION 0xd8 ///< reserved
+#define ATA_SMART_DISABLE_OPERATION 0xd9 ///< defined in ACS-3
+#define ATA_SMART_RETURN_STATUS 0xda ///< defined from ATA-3
+
+#define ATA_SMART_THRESHOLD_NOT_EXCEEDED_VALUE 0xc24f ///< defined in ACS-3
+#define ATA_SMART_THRESHOLD_EXCEEDED_VALUE 0x2cf4 ///< defined in ACS-3
+
+// SMART Log Definitions
+#define ATA_SMART_LOG_DIRECTORY 0x00 ///< defined in ACS-3
+#define ATA_SMART_SUM_SMART_ERROR_LOG 0x01 ///< defined in ACS-3
+#define ATA_SMART_COMP_SMART_ERROR_LOG 0x02 ///< defined in ACS-3
+#define ATA_SMART_EXT_COMP_SMART_ERROR_LOG 0x03 ///< defined in ACS-3
+#define ATA_SMART_SMART_SELFTEST_LOG 0x06 ///< defined in ACS-3
+#define ATA_SMART_EXT_SMART_SELFTEST_LOG 0x07 ///< defined in ACS-3
+#define ATA_SMART_SELECTIVE_SELFTEST_LOG 0x09 ///< defined in ACS-3
+#define ATA_SMART_HOST_VENDOR_SPECIFIC 0x80 ///< defined in ACS-3
+#define ATA_SMART_DEVICE_VENDOR_SPECIFIC 0xa0 ///< defined in ACS-3
+
+//
+// Class 4: DMA Command
+//
+#define ATA_CMD_READ_DMA 0xc8 ///< defined from ATA-1
+#define ATA_CMD_READ_DMA_WITH_RETRY 0xc9 ///< defined from ATA-1, obsoleted from ATA-5
+#define ATA_CMD_READ_DMA_EXT 0x25 ///< defined from ATA-6
+#define ATA_CMD_WRITE_DMA 0xca ///< defined from ATA-1
+#define ATA_CMD_WRITE_DMA_WITH_RETRY 0xcb ///< defined from ATA-1, obsoleted from ATA-
+#define ATA_CMD_WRITE_DMA_EXT 0x35 ///< defined from ATA-6
+
+//
+// ATA Security commands
+//
+#define ATA_CMD_SECURITY_SET_PASSWORD 0xf1 ///< defined in ACS-3
+#define ATA_CMD_SECURITY_UNLOCK 0xf2 ///< defined in ACS-3
+#define ATA_CMD_SECURITY_ERASE_PREPARE 0xf3 ///< defined in ACS-3
+#define ATA_CMD_SECURITY_ERASE_UNIT 0xf4 ///< defined in ACS-3
+#define ATA_CMD_SECURITY_FREEZE_LOCK 0xf5 ///< defined in ACS-3
+#define ATA_CMD_SECURITY_DISABLE_PASSWORD 0xf6 ///< defined in ACS-3
+
+#define ATA_SECURITY_BUFFER_LENGTH 512 ///< defined in ACS-3
+
+//
+// ATA Device Config Overlay
+//
+#define ATA_CMD_DEV_CONFIG_OVERLAY 0xb1 ///< defined from ATA-6
+#define ATA_CMD_DEV_CONFIG_RESTORE_FEATURE 0xc0 ///< defined from ATA-6
+#define ATA_CMD_DEV_CONFIG_FREEZELOCK_FEATURE 0xc1 ///< defined from ATA-6
+#define ATA_CMD_DEV_CONFIG_IDENTIFY_FEATURE 0xc2 ///< defined from ATA-6
+#define ATA_CMD_DEV_CONFIG_SET_FEATURE 0xc3 ///< defined from ATA-6
+
+//
+// ATA Trusted Computing Feature Set Commands
+//
+#define ATA_CMD_TRUSTED_NON_DATA 0x5b ///< defined in ACS-3
+#define ATA_CMD_TRUSTED_RECEIVE 0x5c ///< defined in ACS-3
+#define ATA_CMD_TRUSTED_RECEIVE_DMA 0x5d ///< defined in ACS-3
+#define ATA_CMD_TRUSTED_SEND 0x5e ///< defined in ACS-3
+#define ATA_CMD_TRUSTED_SEND_DMA 0x5f ///< defined in ACS-3
+
+//
+// ATA Trusted Receive Fields
+//
+#define ATA_TR_RETURN_SECURITY_PROTOCOL_INFORMATION 0x00 ///< defined in ACS-3
+#define ATA_TR_SECURITY_PROTOCOL_JEDEC_RESERVED 0xec ///< defined in ACS-3
+#define ATA_TR_SECURITY_PROTOCOL_SDCARD_RESERVED 0xed ///< defined in ACS-3
+#define ATA_TR_SECURITY_PROTOCOL_IEEE1667_RESERVED 0xee ///< defined in ACS-3
+
+//
+// Equates used for Acoustic Flags
+//
+#define ATA_ACOUSTIC_LEVEL_BYPASS 0xff ///< defined from ATA-6
+#define ATA_ACOUSTIC_LEVEL_MAXIMUM_PERFORMANCE 0xfe ///< defined from ATA-6
+#define ATA_ACOUSTIC_LEVEL_QUIET 0x80 ///< defined from ATA-6
+
+//
+// Equates used for DiPM Support
+//
+#define ATA_CMD_DIPM_SUB 0x03 // defined in ACS-3 : Count value in SetFeature identification : 03h Device-initiated interface power state transitions
+#define ATA_DIPM_ENABLE 0x10 // defined in ACS-3
+#define ATA_DIPM_DISABLE 0x90 // defined in ACS-3
+
+//
+// Equates used for DevSleep Support
+//
+#define ATA_CMD_DEVSLEEP_SUB 0x09 // defined in SATA 3.2 Gold Spec : Count value in SetFeature identification : 09h Device Sleep
+#define ATA_DEVSLEEP_ENABLE 0x10 // defined in SATA 3.2 Gold Spec
+#define ATA_DEVSLEEP_DISABLE 0x90 // defined in SATA 3.2 Gold Spec
+
+#define ATA_DEVSLP_EXIT_TIMEOUT 20 // MDAT - 20 ms
+#define ATA_DEVSLP_MINIMUM_DETECTION_TIME 10 // DMDT - 10 us
+#define ATA_DEVSLP_MINIMUM_ASSERTION_TIME 10 // DETO - 10 ms
+
+//
+// Set MAX Commands
+//
+#define ATA_CMD_SET_MAX_ADDRESS_EXT 0x37 ///< defined from ATA-6
+#define ATA_CMD_SET_MAX_ADDRESS 0xf9 ///< defined from ATA-6
+#define ATA_SET_MAX_SET_PASSWORD 0x01 ///< defined from ATA-6
+#define ATA_SET_MAX_LOCK 0x02 ///< defined from ATA-6
+#define ATA_SET_MAX_UNLOCK 0x03 ///< defined from ATA-6
+#define ATA_SET_MAX_FREEZE_LOCK 0x04 ///< defined from ATA-6
+
+///
+/// Default content of device control register, disable INT,
+/// Bit3 is set to 1 according ATA-1
+///
+#define ATA_DEFAULT_CTL (0x0a)
+///
+/// Default context of Device/Head Register,
+/// Bit7 and Bit5 are set to 1 for back-compatibilities.
+///
+#define ATA_DEFAULT_CMD (0xa0)
+
+#define ATAPI_MAX_BYTE_COUNT (0xfffe)
+
+#define ATA_REQUEST_SENSE_ERROR (0x70) ///< defined in SFF-8070i
+
+//
+// Sense Key, Additional Sense Codes and Additional Sense Code Qualifier
+// defined in MultiMedia Commands (MMC, MMC-2)
+//
+// Sense Key
+//
+#define ATA_SK_NO_SENSE (0x0)
+#define ATA_SK_RECOVERY_ERROR (0x1)
+#define ATA_SK_NOT_READY (0x2)
+#define ATA_SK_MEDIUM_ERROR (0x3)
+#define ATA_SK_HARDWARE_ERROR (0x4)
+#define ATA_SK_ILLEGAL_REQUEST (0x5)
+#define ATA_SK_UNIT_ATTENTION (0x6)
+#define ATA_SK_DATA_PROTECT (0x7)
+#define ATA_SK_BLANK_CHECK (0x8)
+#define ATA_SK_VENDOR_SPECIFIC (0x9)
+#define ATA_SK_RESERVED_A (0xA)
+#define ATA_SK_ABORT (0xB)
+#define ATA_SK_RESERVED_C (0xC)
+#define ATA_SK_OVERFLOW (0xD)
+#define ATA_SK_MISCOMPARE (0xE)
+#define ATA_SK_RESERVED_F (0xF)
+
+//
+// Additional Sense Codes
+//
+#define ATA_ASC_NOT_READY (0x04)
+#define ATA_ASC_MEDIA_ERR1 (0x10)
+#define ATA_ASC_MEDIA_ERR2 (0x11)
+#define ATA_ASC_MEDIA_ERR3 (0x14)
+#define ATA_ASC_MEDIA_ERR4 (0x30)
+#define ATA_ASC_MEDIA_UPSIDE_DOWN (0x06)
+#define ATA_ASC_INVALID_CMD (0x20)
+#define ATA_ASC_LBA_OUT_OF_RANGE (0x21)
+#define ATA_ASC_INVALID_FIELD (0x24)
+#define ATA_ASC_WRITE_PROTECTED (0x27)
+#define ATA_ASC_MEDIA_CHANGE (0x28)
+#define ATA_ASC_RESET (0x29) ///< Power On Reset or Bus Reset occurred.
+#define ATA_ASC_ILLEGAL_FIELD (0x26)
+#define ATA_ASC_NO_MEDIA (0x3A)
+#define ATA_ASC_ILLEGAL_MODE_FOR_THIS_TRACK (0x64)
+
+//
+// Additional Sense Code Qualifier
+//
+#define ATA_ASCQ_IN_PROGRESS (0x01)
+
+//
+// Error Register
+//
+#define ATA_ERRREG_BBK BIT7 ///< Bad block detected defined from ATA-1, obsoleted from ATA-2
+#define ATA_ERRREG_UNC BIT6 ///< Uncorrectable Data defined from ATA-1, obsoleted from ATA-4
+#define ATA_ERRREG_MC BIT5 ///< Media Change defined from ATA-1, obsoleted from ATA-4
+#define ATA_ERRREG_IDNF BIT4 ///< ID Not Found defined from ATA-1, obsoleted from ATA-4
+#define ATA_ERRREG_MCR BIT3 ///< Media Change Requested defined from ATA-1, obsoleted from ATA-4
+#define ATA_ERRREG_ABRT BIT2 ///< Aborted Command defined from ATA-1
+#define ATA_ERRREG_TK0NF BIT1 ///< Track 0 Not Found defined from ATA-1, obsoleted from ATA-4
+#define ATA_ERRREG_AMNF BIT0 ///< Address Mark Not Found defined from ATA-1, obsoleted from ATA-4
+
+//
+// Status Register
+//
+#define ATA_STSREG_BSY BIT7 ///< Controller Busy defined from ATA-1
+#define ATA_STSREG_DRDY BIT6 ///< Drive Ready defined from ATA-1
+#define ATA_STSREG_DWF BIT5 ///< Drive Write Fault defined from ATA-1, obsoleted from ATA-4
+#define ATA_STSREG_DF BIT5 ///< Drive Fault defined from ATA-6
+#define ATA_STSREG_DSC BIT4 ///< Disk Seek Complete defined from ATA-1, obsoleted from ATA-4
+#define ATA_STSREG_DRQ BIT3 ///< Data Request defined from ATA-1
+#define ATA_STSREG_CORR BIT2 ///< Corrected Data defined from ATA-1, obsoleted from ATA-4
+#define ATA_STSREG_IDX BIT1 ///< Index defined from ATA-1, obsoleted from ATA-4
+#define ATA_STSREG_ERR BIT0 ///< Error defined from ATA-1
+
+//
+// Device Control Register
+//
+#define ATA_CTLREG_SRST BIT2 ///< Software Reset.
+#define ATA_CTLREG_IEN_L BIT1 ///< Interrupt Enable #.
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/Bluetooth.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/Bluetooth.h
new file mode 100644
index 0000000000..c22dbff9b7
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/Bluetooth.h
@@ -0,0 +1,56 @@
+/** @file
+ This file contains the Bluetooth definitions that are consumed by drivers.
+ These definitions are from Bluetooth Core Specification Version 4.0 June, 2010
+
+ Copyright (c) 2015 - 2017, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _BLUETOOTH_H_
+#define _BLUETOOTH_H_
+
+#pragma pack(1)
+
+///
+/// BLUETOOTH_ADDRESS
+///
+typedef struct {
+ ///
+ /// 48bit Bluetooth device address.
+ ///
+ UINT8 Address[6];
+} BLUETOOTH_ADDRESS;
+
+///
+/// BLUETOOTH_CLASS_OF_DEVICE. See Bluetooth specification for detail.
+///
+typedef struct {
+ UINT8 FormatType : 2;
+ UINT8 MinorDeviceClass : 6;
+ UINT16 MajorDeviceClass : 5;
+ UINT16 MajorServiceClass : 11;
+} BLUETOOTH_CLASS_OF_DEVICE;
+
+///
+/// BLUETOOTH_LE_ADDRESS
+///
+typedef struct {
+ ///
+ /// 48-bit Bluetooth device address
+ ///
+ UINT8 Address[6];
+ ///
+ /// 0x00 - Public Device Address
+ /// 0x01 - Random Device Address
+ ///
+ UINT8 Type;
+} BLUETOOTH_LE_ADDRESS;
+
+#pragma pack()
+
+#define BLUETOOTH_HCI_COMMAND_LOCAL_READABLE_NAME_MAX_SIZE 248
+
+#define BLUETOOTH_HCI_LINK_KEY_SIZE 16
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/Bmp.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/Bmp.h
new file mode 100644
index 0000000000..5d66483ddd
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/Bmp.h
@@ -0,0 +1,42 @@
+/** @file
+ This file defines BMP file header data structures.
+
+Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _BMP_H_
+#define _BMP_H_
+
+#pragma pack(1)
+
+typedef struct {
+ UINT8 Blue;
+ UINT8 Green;
+ UINT8 Red;
+ UINT8 Reserved;
+} BMP_COLOR_MAP;
+
+typedef struct {
+ CHAR8 CharB;
+ CHAR8 CharM;
+ UINT32 Size;
+ UINT16 Reserved[2];
+ UINT32 ImageOffset;
+ UINT32 HeaderSize;
+ UINT32 PixelWidth;
+ UINT32 PixelHeight;
+ UINT16 Planes; ///< Must be 1
+ UINT16 BitPerPixel; ///< 1, 4, 8, or 24
+ UINT32 CompressionType;
+ UINT32 ImageSize; ///< Compressed image size in bytes
+ UINT32 XPixelsPerMeter;
+ UINT32 YPixelsPerMeter;
+ UINT32 NumberOfColors;
+ UINT32 ImportantColors;
+} BMP_IMAGE_HEADER;
+
+#pragma pack()
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/Cxl.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/Cxl.h
new file mode 100644
index 0000000000..64642bb453
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/Cxl.h
@@ -0,0 +1,21 @@
+/** @file
+ Support for the latest CXL standard
+
+ The main header to reference all versions of CXL Base specification registers
+ from the MDE
+
+Copyright (c) 2020, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _CXL_MAIN_H_
+#define _CXL_MAIN_H_
+
+#include
+//
+// CXL assigned new Vendor ID
+//
+#define CXL_DVSEC_VENDOR_ID 0x1E98
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/Cxl11.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/Cxl11.h
new file mode 100644
index 0000000000..f525cb661e
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/Cxl11.h
@@ -0,0 +1,658 @@
+/** @file
+ CXL 1.1 Register definitions
+
+ This file contains the register definitions based on the Compute Express Link
+ (CXL) Specification Revision 1.1.
+
+Copyright (c) 2020, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _CXL11_H_
+#define _CXL11_H_
+
+#include
+//
+// DVSEC Vendor ID
+// Compute Express Link Specification Revision: 1.1 - Chapter 7.1.1 - Table 58
+// (subject to change as per CXL assigned Vendor ID)
+//
+#define INTEL_CXL_DVSEC_VENDOR_ID 0x8086
+
+//
+// CXL Flex Bus Device default device and function number
+// Compute Express Link Specification Revision: 1.1 - Chapter 7.1.1
+//
+#define CXL_DEV_DEV 0
+#define CXL_DEV_FUNC 0
+
+//
+// Ensure proper structure formats
+//
+#pragma pack(1)
+
+/**
+ Macro used to verify the size of a data type at compile time and trigger a
+ STATIC_ASSERT() with an error message if the size of the data type does not
+ match the expected size.
+
+ @param TypeName Type name of data type to verify.
+ @param ExpectedSize The expected size, in bytes, of the data type specified
+ by TypeName.
+**/
+#define CXL_11_SIZE_ASSERT(TypeName, ExpectedSize) \
+ STATIC_ASSERT ( \
+ sizeof (TypeName) == ExpectedSize, \
+ "Size of " #TypeName \
+ " does not meet CXL 1.1 Specification requirements." \
+ )
+
+/**
+ Macro used to verify the offset of a field in a data type at compile time and
+ trigger a STATIC_ASSERT() with an error message if the offset of the field in
+ the data type does not match the expected offset.
+
+ @param TypeName Type name of data type to verify.
+ @param FieldName Field name in the data type specified by TypeName to
+ verify.
+ @param ExpectedOffset The expected offset, in bytes, of the field specified
+ by TypeName and FieldName.
+**/
+#define CXL_11_OFFSET_ASSERT(TypeName, FieldName, ExpectedOffset) \
+ STATIC_ASSERT ( \
+ OFFSET_OF (TypeName, FieldName) == ExpectedOffset, \
+ "Offset of " #TypeName "." #FieldName \
+ " does not meet CXL 1.1 Specification requirements." \
+ )
+
+///
+/// The PCIe DVSEC for Flex Bus Device
+///@{
+typedef union {
+ struct {
+ UINT16 CacheCapable : 1; // bit 0
+ UINT16 IoCapable : 1; // bit 1
+ UINT16 MemCapable : 1; // bit 2
+ UINT16 MemHwInitMode : 1; // bit 3
+ UINT16 HdmCount : 2; // bit 4..5
+ UINT16 Reserved1 : 8; // bit 6..13
+ UINT16 ViralCapable : 1; // bit 14
+ UINT16 Reserved2 : 1; // bit 15
+ } Bits;
+ UINT16 Uint16;
+} CXL_DVSEC_FLEX_BUS_DEVICE_CAPABILITY;
+
+typedef union {
+ struct {
+ UINT16 CacheEnable : 1; // bit 0
+ UINT16 IoEnable : 1; // bit 1
+ UINT16 MemEnable : 1; // bit 2
+ UINT16 CacheSfCoverage : 5; // bit 3..7
+ UINT16 CacheSfGranularity : 3; // bit 8..10
+ UINT16 CacheCleanEviction : 1; // bit 11
+ UINT16 Reserved1 : 2; // bit 12..13
+ UINT16 ViralEnable : 1; // bit 14
+ UINT16 Reserved2 : 1; // bit 15
+ } Bits;
+ UINT16 Uint16;
+} CXL_DVSEC_FLEX_BUS_DEVICE_CONTROL;
+
+typedef union {
+ struct {
+ UINT16 Reserved1 : 14; // bit 0..13
+ UINT16 ViralStatus : 1; // bit 14
+ UINT16 Reserved2 : 1; // bit 15
+ } Bits;
+ UINT16 Uint16;
+} CXL_DVSEC_FLEX_BUS_DEVICE_STATUS;
+
+typedef union {
+ struct {
+ UINT16 Reserved1 : 1; // bit 0
+ UINT16 Reserved2 : 1; // bit 1
+ UINT16 Reserved3 : 1; // bit 2
+ UINT16 Reserved4 : 13; // bit 3..15
+ } Bits;
+ UINT16 Uint16;
+} CXL_1_1_DVSEC_FLEX_BUS_DEVICE_CONTROL2;
+
+typedef union {
+ struct {
+ UINT16 Reserved1 : 1; // bit 0
+ UINT16 Reserved2 : 1; // bit 1
+ UINT16 Reserved3 : 14; // bit 2..15
+ } Bits;
+ UINT16 Uint16;
+} CXL_1_1_DVSEC_FLEX_BUS_DEVICE_STATUS2;
+
+typedef union {
+ struct {
+ UINT16 ConfigLock : 1; // bit 0
+ UINT16 Reserved1 : 15; // bit 1..15
+ } Bits;
+ UINT16 Uint16;
+} CXL_DVSEC_FLEX_BUS_DEVICE_LOCK;
+
+typedef union {
+ struct {
+ UINT32 MemorySizeHigh : 32; // bit 0..31
+ } Bits;
+ UINT32 Uint32;
+} CXL_DVSEC_FLEX_BUS_DEVICE_RANGE1_SIZE_HIGH;
+
+typedef union {
+ struct {
+ UINT32 MemoryInfoValid : 1; // bit 0
+ UINT32 MemoryActive : 1; // bit 1
+ UINT32 MediaType : 3; // bit 2..4
+ UINT32 MemoryClass : 3; // bit 5..7
+ UINT32 DesiredInterleave : 3; // bit 8..10
+ UINT32 Reserved : 17; // bit 11..27
+ UINT32 MemorySizeLow : 4; // bit 28..31
+ } Bits;
+ UINT32 Uint32;
+} CXL_DVSEC_FLEX_BUS_DEVICE_RANGE1_SIZE_LOW;
+
+typedef union {
+ struct {
+ UINT32 MemoryBaseHigh : 32; // bit 0..31
+ } Bits;
+ UINT32 Uint32;
+} CXL_DVSEC_FLEX_BUS_DEVICE_RANGE1_BASE_HIGH;
+
+typedef union {
+ struct {
+ UINT32 Reserved : 28; // bit 0..27
+ UINT32 MemoryBaseLow : 4; // bit 28..31
+ } Bits;
+ UINT32 Uint32;
+} CXL_DVSEC_FLEX_BUS_DEVICE_RANGE1_BASE_LOW;
+
+typedef union {
+ struct {
+ UINT32 MemorySizeHigh : 32; // bit 0..31
+ } Bits;
+ UINT32 Uint32;
+} CXL_DVSEC_FLEX_BUS_DEVICE_RANGE2_SIZE_HIGH;
+
+typedef union {
+ struct {
+ UINT32 MemoryInfoValid : 1; // bit 0
+ UINT32 MemoryActive : 1; // bit 1
+ UINT32 MediaType : 3; // bit 2..4
+ UINT32 MemoryClass : 3; // bit 5..7
+ UINT32 DesiredInterleave : 3; // bit 8..10
+ UINT32 Reserved : 17; // bit 11..27
+ UINT32 MemorySizeLow : 4; // bit 28..31
+ } Bits;
+ UINT32 Uint32;
+} CXL_DVSEC_FLEX_BUS_DEVICE_RANGE2_SIZE_LOW;
+
+typedef union {
+ struct {
+ UINT32 MemoryBaseHigh : 32; // bit 0..31
+ } Bits;
+ UINT32 Uint32;
+} CXL_DVSEC_FLEX_BUS_DEVICE_RANGE2_BASE_HIGH;
+
+typedef union {
+ struct {
+ UINT32 Reserved : 28; // bit 0..27
+ UINT32 MemoryBaseLow : 4; // bit 28..31
+ } Bits;
+ UINT32 Uint32;
+} CXL_DVSEC_FLEX_BUS_DEVICE_RANGE2_BASE_LOW;
+
+//
+// Flex Bus Device DVSEC ID
+// Compute Express Link Specification Revision: 1.1 - Chapter 7.1.1, Table 58
+//
+#define FLEX_BUS_DEVICE_DVSEC_ID 0
+
+//
+// PCIe DVSEC for Flex Bus Device
+// Compute Express Link Specification Revision: 1.1 - Chapter 7.1.1, Figure 95
+//
+typedef struct {
+ PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header; // offset 0
+ PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_1 DesignatedVendorSpecificHeader1; // offset 4
+ PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_2 DesignatedVendorSpecificHeader2; // offset 8
+ CXL_DVSEC_FLEX_BUS_DEVICE_CAPABILITY DeviceCapability; // offset 10
+ CXL_DVSEC_FLEX_BUS_DEVICE_CONTROL DeviceControl; // offset 12
+ CXL_DVSEC_FLEX_BUS_DEVICE_STATUS DeviceStatus; // offset 14
+ CXL_1_1_DVSEC_FLEX_BUS_DEVICE_CONTROL2 DeviceControl2; // offset 16
+ CXL_1_1_DVSEC_FLEX_BUS_DEVICE_STATUS2 DeviceStatus2; // offset 18
+ CXL_DVSEC_FLEX_BUS_DEVICE_LOCK DeviceLock; // offset 20
+ UINT16 Reserved; // offset 22
+ CXL_DVSEC_FLEX_BUS_DEVICE_RANGE1_SIZE_HIGH DeviceRange1SizeHigh; // offset 24
+ CXL_DVSEC_FLEX_BUS_DEVICE_RANGE1_SIZE_LOW DeviceRange1SizeLow; // offset 28
+ CXL_DVSEC_FLEX_BUS_DEVICE_RANGE1_BASE_HIGH DeviceRange1BaseHigh; // offset 32
+ CXL_DVSEC_FLEX_BUS_DEVICE_RANGE1_BASE_LOW DeviceRange1BaseLow; // offset 36
+ CXL_DVSEC_FLEX_BUS_DEVICE_RANGE2_SIZE_HIGH DeviceRange2SizeHigh; // offset 40
+ CXL_DVSEC_FLEX_BUS_DEVICE_RANGE2_SIZE_LOW DeviceRange2SizeLow; // offset 44
+ CXL_DVSEC_FLEX_BUS_DEVICE_RANGE2_BASE_HIGH DeviceRange2BaseHigh; // offset 48
+ CXL_DVSEC_FLEX_BUS_DEVICE_RANGE2_BASE_LOW DeviceRange2BaseLow; // offset 52
+} CXL_1_1_DVSEC_FLEX_BUS_DEVICE;
+
+CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, Header, 0x00);
+CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DesignatedVendorSpecificHeader1, 0x04);
+CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DesignatedVendorSpecificHeader2, 0x08);
+CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceCapability, 0x0A);
+CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceControl, 0x0C);
+CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceStatus, 0x0E);
+CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceControl2, 0x10);
+CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceStatus2, 0x12);
+CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceLock, 0x14);
+CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceRange1SizeHigh, 0x18);
+CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceRange1SizeLow, 0x1C);
+CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceRange1BaseHigh, 0x20);
+CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceRange1BaseLow, 0x24);
+CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceRange2SizeHigh, 0x28);
+CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceRange2SizeLow, 0x2C);
+CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceRange2BaseHigh, 0x30);
+CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceRange2BaseLow, 0x34);
+CXL_11_SIZE_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, 0x38);
+///@}
+
+///
+/// PCIe DVSEC for FLex Bus Port
+///@{
+typedef union {
+ struct {
+ UINT16 CacheCapable : 1; // bit 0
+ UINT16 IoCapable : 1; // bit 1
+ UINT16 MemCapable : 1; // bit 2
+ UINT16 Reserved : 13; // bit 3..15
+ } Bits;
+ UINT16 Uint16;
+} CXL_1_1_DVSEC_FLEX_BUS_PORT_CAPABILITY;
+
+typedef union {
+ struct {
+ UINT16 CacheEnable : 1; // bit 0
+ UINT16 IoEnable : 1; // bit 1
+ UINT16 MemEnable : 1; // bit 2
+ UINT16 CxlSyncBypassEnable : 1; // bit 3
+ UINT16 DriftBufferEnable : 1; // bit 4
+ UINT16 Reserved : 3; // bit 5..7
+ UINT16 Retimer1Present : 1; // bit 8
+ UINT16 Retimer2Present : 1; // bit 9
+ UINT16 Reserved2 : 6; // bit 10..15
+ } Bits;
+ UINT16 Uint16;
+} CXL_1_1_DVSEC_FLEX_BUS_PORT_CONTROL;
+
+typedef union {
+ struct {
+ UINT16 CacheEnable : 1; // bit 0
+ UINT16 IoEnable : 1; // bit 1
+ UINT16 MemEnable : 1; // bit 2
+ UINT16 CxlSyncBypassEnable : 1; // bit 3
+ UINT16 DriftBufferEnable : 1; // bit 4
+ UINT16 Reserved : 3; // bit 5..7
+ UINT16 CxlCorrectableProtocolIdFramingError : 1; // bit 8
+ UINT16 CxlUncorrectableProtocolIdFramingError : 1; // bit 9
+ UINT16 CxlUnexpectedProtocolIdDropped : 1; // bit 10
+ UINT16 Reserved2 : 5; // bit 11..15
+ } Bits;
+ UINT16 Uint16;
+} CXL_1_1_DVSEC_FLEX_BUS_PORT_STATUS;
+
+//
+// Flex Bus Port DVSEC ID
+// Compute Express Link Specification Revision: 1.1 - Chapter 7.2.1.3, Table 62
+//
+#define FLEX_BUS_PORT_DVSEC_ID 7
+
+//
+// PCIe DVSEC for Flex Bus Port
+// Compute Express Link Specification Revision: 1.1 - Chapter 7.2.1.3, Figure 99
+//
+typedef struct {
+ PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header; // offset 0
+ PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_1 DesignatedVendorSpecificHeader1; // offset 4
+ PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_2 DesignatedVendorSpecificHeader2; // offset 8
+ CXL_1_1_DVSEC_FLEX_BUS_PORT_CAPABILITY PortCapability; // offset 10
+ CXL_1_1_DVSEC_FLEX_BUS_PORT_CONTROL PortControl; // offset 12
+ CXL_1_1_DVSEC_FLEX_BUS_PORT_STATUS PortStatus; // offset 14
+} CXL_1_1_DVSEC_FLEX_BUS_PORT;
+
+CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_PORT, Header, 0x00);
+CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_PORT, DesignatedVendorSpecificHeader1, 0x04);
+CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_PORT, DesignatedVendorSpecificHeader2, 0x08);
+CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_PORT, PortCapability, 0x0A);
+CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_PORT, PortControl, 0x0C);
+CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_PORT, PortStatus, 0x0E);
+CXL_11_SIZE_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_PORT, 0x10);
+///@}
+
+///
+/// CXL 1.1 Upstream and Downstream Port Subsystem Component registers
+///
+
+/// The CXL.Cache and CXL.Memory Architectural register definitions
+/// Based on chapter 7.2.2 of Compute Express Link Specification Revision: 1.1
+///@{
+
+#define CXL_CAPABILITY_HEADER_OFFSET 0
+typedef union {
+ struct {
+ UINT32 CxlCapabilityId : 16; // bit 0..15
+ UINT32 CxlCapabilityVersion : 4; // bit 16..19
+ UINT32 CxlCacheMemVersion : 4; // bit 20..23
+ UINT32 ArraySize : 8; // bit 24..31
+ } Bits;
+ UINT32 Uint32;
+} CXL_CAPABILITY_HEADER;
+
+#define CXL_RAS_CAPABILITY_HEADER_OFFSET 4
+typedef union {
+ struct {
+ UINT32 CxlCapabilityId : 16; // bit 0..15
+ UINT32 CxlCapabilityVersion : 4; // bit 16..19
+ UINT32 CxlRasCapabilityPointer : 12; // bit 20..31
+ } Bits;
+ UINT32 Uint32;
+} CXL_RAS_CAPABILITY_HEADER;
+
+#define CXL_SECURITY_CAPABILITY_HEADER_OFFSET 8
+typedef union {
+ struct {
+ UINT32 CxlCapabilityId : 16; // bit 0..15
+ UINT32 CxlCapabilityVersion : 4; // bit 16..19
+ UINT32 CxlSecurityCapabilityPointer : 12; // bit 20..31
+ } Bits;
+ UINT32 Uint32;
+} CXL_SECURITY_CAPABILITY_HEADER;
+
+#define CXL_LINK_CAPABILITY_HEADER_OFFSET 0xC
+typedef union {
+ struct {
+ UINT32 CxlCapabilityId : 16; // bit 0..15
+ UINT32 CxlCapabilityVersion : 4; // bit 16..19
+ UINT32 CxlLinkCapabilityPointer : 12; // bit 20..31
+ } Bits;
+ UINT32 Uint32;
+} CXL_LINK_CAPABILITY_HEADER;
+
+typedef union {
+ struct {
+ UINT32 CacheDataParity : 1; // bit 0..0
+ UINT32 CacheAddressParity : 1; // bit 1..1
+ UINT32 CacheByteEnableParity : 1; // bit 2..2
+ UINT32 CacheDataEcc : 1; // bit 3..3
+ UINT32 MemDataParity : 1; // bit 4..4
+ UINT32 MemAddressParity : 1; // bit 5..5
+ UINT32 MemByteEnableParity : 1; // bit 6..6
+ UINT32 MemDataEcc : 1; // bit 7..7
+ UINT32 ReInitThreshold : 1; // bit 8..8
+ UINT32 RsvdEncodingViolation : 1; // bit 9..9
+ UINT32 PoisonReceived : 1; // bit 10..10
+ UINT32 ReceiverOverflow : 1; // bit 11..11
+ UINT32 Reserved : 20; // bit 12..31
+ } Bits;
+ UINT32 Uint32;
+} CXL_1_1_UNCORRECTABLE_ERROR_STATUS;
+
+typedef union {
+ struct {
+ UINT32 CacheDataParityMask : 1; // bit 0..0
+ UINT32 CacheAddressParityMask : 1; // bit 1..1
+ UINT32 CacheByteEnableParityMask : 1; // bit 2..2
+ UINT32 CacheDataEccMask : 1; // bit 3..3
+ UINT32 MemDataParityMask : 1; // bit 4..4
+ UINT32 MemAddressParityMask : 1; // bit 5..5
+ UINT32 MemByteEnableParityMask : 1; // bit 6..6
+ UINT32 MemDataEccMask : 1; // bit 7..7
+ UINT32 ReInitThresholdMask : 1; // bit 8..8
+ UINT32 RsvdEncodingViolationMask : 1; // bit 9..9
+ UINT32 PoisonReceivedMask : 1; // bit 10..10
+ UINT32 ReceiverOverflowMask : 1; // bit 11..11
+ UINT32 Reserved : 20; // bit 12..31
+ } Bits;
+ UINT32 Uint32;
+} CXL_1_1_UNCORRECTABLE_ERROR_MASK;
+
+typedef union {
+ struct {
+ UINT32 CacheDataParitySeverity : 1; // bit 0..0
+ UINT32 CacheAddressParitySeverity : 1; // bit 1..1
+ UINT32 CacheByteEnableParitySeverity : 1; // bit 2..2
+ UINT32 CacheDataEccSeverity : 1; // bit 3..3
+ UINT32 MemDataParitySeverity : 1; // bit 4..4
+ UINT32 MemAddressParitySeverity : 1; // bit 5..5
+ UINT32 MemByteEnableParitySeverity : 1; // bit 6..6
+ UINT32 MemDataEccSeverity : 1; // bit 7..7
+ UINT32 ReInitThresholdSeverity : 1; // bit 8..8
+ UINT32 RsvdEncodingViolationSeverity : 1; // bit 9..9
+ UINT32 PoisonReceivedSeverity : 1; // bit 10..10
+ UINT32 ReceiverOverflowSeverity : 1; // bit 11..11
+ UINT32 Reserved : 20; // bit 12..31
+ } Bits;
+ UINT32 Uint32;
+} CXL_1_1_UNCORRECTABLE_ERROR_SEVERITY;
+
+typedef union {
+ struct {
+ UINT32 CacheDataEcc : 1; // bit 0..0
+ UINT32 MemoryDataEcc : 1; // bit 1..1
+ UINT32 CrcThreshold : 1; // bit 2..2
+ UINT32 RetryThreshold : 1; // bit 3..3
+ UINT32 CachePoisonReceived : 1; // bit 4..4
+ UINT32 MemoryPoisonReceived : 1; // bit 5..5
+ UINT32 PhysicalLayerError : 1; // bit 6..6
+ UINT32 Reserved : 25; // bit 7..31
+ } Bits;
+ UINT32 Uint32;
+} CXL_CORRECTABLE_ERROR_STATUS;
+
+typedef union {
+ struct {
+ UINT32 CacheDataEccMask : 1; // bit 0..0
+ UINT32 MemoryDataEccMask : 1; // bit 1..1
+ UINT32 CrcThresholdMask : 1; // bit 2..2
+ UINT32 RetryThresholdMask : 1; // bit 3..3
+ UINT32 CachePoisonReceivedMask : 1; // bit 4..4
+ UINT32 MemoryPoisonReceivedMask : 1; // bit 5..5
+ UINT32 PhysicalLayerErrorMask : 1; // bit 6..6
+ UINT32 Reserved : 25; // bit 7..31
+ } Bits;
+ UINT32 Uint32;
+} CXL_CORRECTABLE_ERROR_MASK;
+
+typedef union {
+ struct {
+ UINT32 FirstErrorPointer : 4; // bit 0..3
+ UINT32 Reserved1 : 5; // bit 4..8
+ UINT32 MultipleHeaderRecordingCapability : 1; // bit 9..9
+ UINT32 Reserved2 : 3; // bit 10..12
+ UINT32 PoisonEnabled : 1; // bit 13..13
+ UINT32 Reserved3 : 18; // bit 14..31
+ } Bits;
+ UINT32 Uint32;
+} CXL_ERROR_CAPABILITIES_AND_CONTROL;
+
+typedef struct {
+ CXL_1_1_UNCORRECTABLE_ERROR_STATUS UncorrectableErrorStatus;
+ CXL_1_1_UNCORRECTABLE_ERROR_MASK UncorrectableErrorMask;
+ CXL_1_1_UNCORRECTABLE_ERROR_SEVERITY UncorrectableErrorSeverity;
+ CXL_CORRECTABLE_ERROR_STATUS CorrectableErrorStatus;
+ CXL_CORRECTABLE_ERROR_MASK CorrectableErrorMask;
+ CXL_ERROR_CAPABILITIES_AND_CONTROL ErrorCapabilitiesAndControl;
+ UINT32 HeaderLog[16];
+} CXL_1_1_RAS_CAPABILITY_STRUCTURE;
+
+CXL_11_OFFSET_ASSERT (CXL_1_1_RAS_CAPABILITY_STRUCTURE, UncorrectableErrorStatus, 0x00);
+CXL_11_OFFSET_ASSERT (CXL_1_1_RAS_CAPABILITY_STRUCTURE, UncorrectableErrorMask, 0x04);
+CXL_11_OFFSET_ASSERT (CXL_1_1_RAS_CAPABILITY_STRUCTURE, UncorrectableErrorSeverity, 0x08);
+CXL_11_OFFSET_ASSERT (CXL_1_1_RAS_CAPABILITY_STRUCTURE, CorrectableErrorStatus, 0x0C);
+CXL_11_OFFSET_ASSERT (CXL_1_1_RAS_CAPABILITY_STRUCTURE, CorrectableErrorMask, 0x10);
+CXL_11_OFFSET_ASSERT (CXL_1_1_RAS_CAPABILITY_STRUCTURE, ErrorCapabilitiesAndControl, 0x14);
+CXL_11_OFFSET_ASSERT (CXL_1_1_RAS_CAPABILITY_STRUCTURE, HeaderLog, 0x18);
+CXL_11_SIZE_ASSERT (CXL_1_1_RAS_CAPABILITY_STRUCTURE, 0x58);
+
+typedef union {
+ struct {
+ UINT32 DeviceTrustLevel : 2; // bit 0..1
+ UINT32 Reserved : 30; // bit 2..31
+ } Bits;
+ UINT32 Uint32;
+} CXL_1_1_SECURITY_POLICY;
+
+typedef struct {
+ CXL_1_1_SECURITY_POLICY SecurityPolicy;
+} CXL_1_1_SECURITY_CAPABILITY_STRUCTURE;
+
+CXL_11_OFFSET_ASSERT (CXL_1_1_SECURITY_CAPABILITY_STRUCTURE, SecurityPolicy, 0x0);
+CXL_11_SIZE_ASSERT (CXL_1_1_SECURITY_CAPABILITY_STRUCTURE, 0x4);
+
+typedef union {
+ struct {
+ UINT64 CxlLinkVersionSupported : 4; // bit 0..3
+ UINT64 CxlLinkVersionReceived : 4; // bit 4..7
+ UINT64 LlrWrapValueSupported : 8; // bit 8..15
+ UINT64 LlrWrapValueReceived : 8; // bit 16..23
+ UINT64 NumRetryReceived : 5; // bit 24..28
+ UINT64 NumPhyReinitReceived : 5; // bit 29..33
+ UINT64 WrPtrReceived : 8; // bit 34..41
+ UINT64 EchoEseqReceived : 8; // bit 42..49
+ UINT64 NumFreeBufReceived : 8; // bit 50..57
+ UINT64 Reserved : 6; // bit 58..63
+ } Bits;
+ UINT64 Uint64;
+} CXL_LINK_LAYER_CAPABILITY;
+
+typedef union {
+ struct {
+ UINT16 LlReset : 1; // bit 0..0
+ UINT16 LlInitStall : 1; // bit 1..1
+ UINT16 LlCrdStall : 1; // bit 2..2
+ UINT16 InitState : 2; // bit 3..4
+ UINT16 LlRetryBufferConsumed : 8; // bit 5..12
+ UINT16 Reserved : 3; // bit 13..15
+ } Bits;
+ UINT64 Uint64;
+} CXL_LINK_LAYER_CONTROL_AND_STATUS;
+
+typedef union {
+ struct {
+ UINT64 CacheReqCredits : 10; // bit 0..9
+ UINT64 CacheRspCredits : 10; // bit 10..19
+ UINT64 CacheDataCredits : 10; // bit 20..29
+ UINT64 MemReqRspCredits : 10; // bit 30..39
+ UINT64 MemDataCredits : 10; // bit 40..49
+ } Bits;
+ UINT64 Uint64;
+} CXL_LINK_LAYER_RX_CREDIT_CONTROL;
+
+typedef union {
+ struct {
+ UINT64 CacheReqCredits : 10; // bit 0..9
+ UINT64 CacheRspCredits : 10; // bit 10..19
+ UINT64 CacheDataCredits : 10; // bit 20..29
+ UINT64 MemReqRspCredits : 10; // bit 30..39
+ UINT64 MemDataCredits : 10; // bit 40..49
+ } Bits;
+ UINT64 Uint64;
+} CXL_LINK_LAYER_RX_CREDIT_RETURN_STATUS;
+
+typedef union {
+ struct {
+ UINT64 CacheReqCredits : 10; // bit 0..9
+ UINT64 CacheRspCredits : 10; // bit 10..19
+ UINT64 CacheDataCredits : 10; // bit 20..29
+ UINT64 MemReqRspCredits : 10; // bit 30..39
+ UINT64 MemDataCredits : 10; // bit 40..49
+ } Bits;
+ UINT64 Uint64;
+} CXL_LINK_LAYER_TX_CREDIT_STATUS;
+
+typedef union {
+ struct {
+ UINT32 AckForceThreshold : 8; // bit 0..7
+ UINT32 AckFLushRetimer : 10; // bit 8..17
+ } Bits;
+ UINT64 Uint64;
+} CXL_LINK_LAYER_ACK_TIMER_CONTROL;
+
+typedef union {
+ struct {
+ UINT32 MdhDisable : 1; // bit 0..0
+ UINT32 Reserved : 31; // bit 1..31
+ } Bits;
+ UINT64 Uint64;
+} CXL_LINK_LAYER_DEFEATURE;
+
+typedef struct {
+ CXL_LINK_LAYER_CAPABILITY LinkLayerCapability;
+ CXL_LINK_LAYER_CONTROL_AND_STATUS LinkLayerControlStatus;
+ CXL_LINK_LAYER_RX_CREDIT_CONTROL LinkLayerRxCreditControl;
+ CXL_LINK_LAYER_RX_CREDIT_RETURN_STATUS LinkLayerRxCreditReturnStatus;
+ CXL_LINK_LAYER_TX_CREDIT_STATUS LinkLayerTxCreditStatus;
+ CXL_LINK_LAYER_ACK_TIMER_CONTROL LinkLayerAckTimerControl;
+ CXL_LINK_LAYER_DEFEATURE LinkLayerDefeature;
+} CXL_1_1_LINK_CAPABILITY_STRUCTURE;
+
+CXL_11_OFFSET_ASSERT (CXL_1_1_LINK_CAPABILITY_STRUCTURE, LinkLayerCapability, 0x00);
+CXL_11_OFFSET_ASSERT (CXL_1_1_LINK_CAPABILITY_STRUCTURE, LinkLayerControlStatus, 0x08);
+CXL_11_OFFSET_ASSERT (CXL_1_1_LINK_CAPABILITY_STRUCTURE, LinkLayerRxCreditControl, 0x10);
+CXL_11_OFFSET_ASSERT (CXL_1_1_LINK_CAPABILITY_STRUCTURE, LinkLayerRxCreditReturnStatus, 0x18);
+CXL_11_OFFSET_ASSERT (CXL_1_1_LINK_CAPABILITY_STRUCTURE, LinkLayerTxCreditStatus, 0x20);
+CXL_11_OFFSET_ASSERT (CXL_1_1_LINK_CAPABILITY_STRUCTURE, LinkLayerAckTimerControl, 0x28);
+CXL_11_OFFSET_ASSERT (CXL_1_1_LINK_CAPABILITY_STRUCTURE, LinkLayerDefeature, 0x30);
+CXL_11_SIZE_ASSERT (CXL_1_1_LINK_CAPABILITY_STRUCTURE, 0x38);
+
+#define CXL_IO_ARBITRATION_CONTROL_OFFSET 0x180
+typedef union {
+ struct {
+ UINT32 Reserved1 : 4; // bit 0..3
+ UINT32 WeightedRoundRobinArbitrationWeight : 4; // bit 4..7
+ UINT32 Reserved2 : 24; // bit 8..31
+ } Bits;
+ UINT32 Uint32;
+} CXL_IO_ARBITRATION_CONTROL;
+
+CXL_11_SIZE_ASSERT (CXL_IO_ARBITRATION_CONTROL, 0x4);
+
+#define CXL_CACHE_MEMORY_ARBITRATION_CONTROL_OFFSET 0x1C0
+typedef union {
+ struct {
+ UINT32 Reserved1 : 4; // bit 0..3
+ UINT32 WeightedRoundRobinArbitrationWeight : 4; // bit 4..7
+ UINT32 Reserved2 : 24; // bit 8..31
+ } Bits;
+ UINT32 Uint32;
+} CXL_CACHE_MEMORY_ARBITRATION_CONTROL;
+
+CXL_11_SIZE_ASSERT (CXL_CACHE_MEMORY_ARBITRATION_CONTROL, 0x4);
+
+///@}
+
+/// The CXL.RCRB base register definition
+/// Based on chapter 7.3 of Compute Express Link Specification Revision: 1.1
+///@{
+typedef union {
+ struct {
+ UINT64 RcrbEnable : 1; // bit 0..0
+ UINT64 Reserved : 12; // bit 1..12
+ UINT64 RcrbBaseAddress : 51; // bit 13..63
+ } Bits;
+ UINT64 Uint64;
+} CXL_RCRB_BASE;
+
+CXL_11_SIZE_ASSERT (CXL_RCRB_BASE, 0x8);
+
+///@}
+
+#pragma pack()
+
+//
+// CXL Downstream / Upstream Port RCRB space register offsets
+// Compute Express Link Specification Revision: 1.1 - Chapter 7.2.1.1 - Figure 97
+//
+#define CXL_PORT_RCRB_MEMBAR0_LOW_OFFSET 0x010
+#define CXL_PORT_RCRB_MEMBAR0_HIGH_OFFSET 0x014
+#define CXL_PORT_RCRB_EXTENDED_CAPABILITY_BASE_OFFSET 0x100
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/DebugPort2Table.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/DebugPort2Table.h
new file mode 100644
index 0000000000..904586ec60
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/DebugPort2Table.h
@@ -0,0 +1,74 @@
+/** @file
+ ACPI debug port 2 table definition, defined at
+ Microsoft DebugPort2Specification.
+
+ Copyright (c) 2012 - 2018, Intel Corporation. All rights reserved.
+ Copyright (c) 2012 - 2016, ARM Limited. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _DEBUG_PORT_2_TABLE_H_
+#define _DEBUG_PORT_2_TABLE_H_
+
+#include
+
+//
+// Ensure proper structure formats
+//
+#pragma pack(1)
+
+//
+// Debug Device Information structure.
+//
+typedef struct {
+ UINT8 Revision;
+ UINT16 Length;
+ UINT8 NumberofGenericAddressRegisters;
+ UINT16 NameSpaceStringLength;
+ UINT16 NameSpaceStringOffset;
+ UINT16 OemDataLength;
+ UINT16 OemDataOffset;
+ UINT16 PortType;
+ UINT16 PortSubtype;
+ UINT8 Reserved[2];
+ UINT16 BaseAddressRegisterOffset;
+ UINT16 AddressSizeOffset;
+} EFI_ACPI_DBG2_DEBUG_DEVICE_INFORMATION_STRUCT;
+
+#define EFI_ACPI_DBG2_DEBUG_DEVICE_INFORMATION_STRUCT_REVISION 0x00
+
+#define EFI_ACPI_DBG2_PORT_TYPE_SERIAL 0x8000
+#define EFI_ACPI_DBG2_PORT_SUBTYPE_SERIAL_FULL_16550 0x0000
+#define EFI_ACPI_DBG2_PORT_SUBTYPE_SERIAL_16550_SUBSET_COMPATIBLE_WITH_MS_DBGP_SPEC 0x0001
+#define EFI_ACPI_DBG2_PORT_SUBTYPE_SERIAL_ARM_PL011_UART 0x0003
+#define EFI_ACPI_DBG2_PORT_SUBTYPE_SERIAL_NVIDIA_16550_UART 0x0005
+#define EFI_ACPI_DBG2_PORT_SUBTYPE_SERIAL_ARM_SBSA_GENERIC_UART_2X 0x000d
+#define EFI_ACPI_DBG2_PORT_SUBTYPE_SERIAL_ARM_SBSA_GENERIC_UART 0x000e
+#define EFI_ACPI_DBG2_PORT_SUBTYPE_SERIAL_DCC 0x000f
+#define EFI_ACPI_DBG2_PORT_SUBTYPE_SERIAL_BCM2835_UART 0x0010
+#define EFI_ACPI_DBG2_PORT_SUBTYPE_SERIAL_16550_WITH_GAS 0x0012
+#define EFI_ACPI_DBG2_PORT_TYPE_1394 0x8001
+#define EFI_ACPI_DBG2_PORT_SUBTYPE_1394_STANDARD 0x0000
+#define EFI_ACPI_DBG2_PORT_TYPE_USB 0x8002
+#define EFI_ACPI_DBG2_PORT_SUBTYPE_USB_XHCI 0x0000
+#define EFI_ACPI_DBG2_PORT_SUBTYPE_USB_EHCI 0x0001
+#define EFI_ACPI_DBG2_PORT_TYPE_NET 0x8003
+
+//
+// Debug Port 2 Table definition.
+//
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 OffsetDbgDeviceInfo;
+ UINT32 NumberDbgDeviceInfo;
+} EFI_ACPI_DEBUG_PORT_2_DESCRIPTION_TABLE;
+
+#pragma pack()
+
+//
+// DBG2 Revision (defined in spec)
+//
+#define EFI_ACPI_DEBUG_PORT_2_TABLE_REVISION 0x00
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/DebugPortTable.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/DebugPortTable.h
new file mode 100644
index 0000000000..7852d59563
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/DebugPortTable.h
@@ -0,0 +1,43 @@
+/** @file
+ ACPI debug port table definition, defined at
+ Microsoft DebugPortSpecification.
+
+ Copyright (c) 2012 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _DEBUG_PORT_TABLE_H_
+#define _DEBUG_PORT_TABLE_H_
+
+#include
+
+//
+// Ensure proper structure formats
+//
+#pragma pack(1)
+
+//
+// Debug Port Table definition.
+//
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT8 InterfaceType;
+ UINT8 Reserved_37[3];
+ EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE BaseAddress;
+} EFI_ACPI_DEBUG_PORT_DESCRIPTION_TABLE;
+
+#pragma pack()
+
+//
+// DBGP Revision (defined in spec)
+//
+#define EFI_ACPI_DEBUG_PORT_TABLE_REVISION 0x01
+
+//
+// Interface Type
+//
+#define EFI_ACPI_DBGP_INTERFACE_TYPE_FULL_16550 0
+#define EFI_ACPI_DBGP_INTERFACE_TYPE_16550_SUBSET_COMPATIBLE_WITH_MS_DBGP_SPEC 1
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/Dhcp.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/Dhcp.h
new file mode 100644
index 0000000000..f6a5adb0ea
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/Dhcp.h
@@ -0,0 +1,287 @@
+/** @file
+ This file contains the DHCPv4 and DHCPv6 option definitions and other configuration.
+ They are used to carry additional information and parameters in DHCP messages.
+
+ Copyright (c) 2016, Intel Corporation. All rights reserved.
+ Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.
+ Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _DHCP_H_
+#define _DHCP_H_
+
+///
+/// Dynamic Host Configuration Protocol for IPv4 (DHCPv4)
+///
+/// Dhcpv4 Options, definitions from RFC 2132
+///
+#define DHCP4_TAG_PAD 0 /// Pad Option
+#define DHCP4_TAG_EOP 255 /// End Option
+#define DHCP4_TAG_NETMASK 1 /// Subnet Mask
+#define DHCP4_TAG_TIME_OFFSET 2 /// Time Offset from UTC
+#define DHCP4_TAG_ROUTER 3 /// Router option,
+#define DHCP4_TAG_TIME_SERVER 4 /// Time Server
+#define DHCP4_TAG_NAME_SERVER 5 /// Name Server
+#define DHCP4_TAG_DNS_SERVER 6 /// Domain Name Server
+#define DHCP4_TAG_LOG_SERVER 7 /// Log Server
+#define DHCP4_TAG_COOKIE_SERVER 8 /// Cookie Server
+#define DHCP4_TAG_LPR_SERVER 9 /// LPR Print Server
+#define DHCP4_TAG_IMPRESS_SERVER 10 /// Impress Server
+#define DHCP4_TAG_RL_SERVER 11 /// Resource Location Server
+#define DHCP4_TAG_HOSTNAME 12 /// Host Name
+#define DHCP4_TAG_BOOTFILE_LEN 13 /// Boot File Size
+#define DHCP4_TAG_DUMP 14 /// Merit Dump File
+#define DHCP4_TAG_DOMAINNAME 15 /// Domain Name
+#define DHCP4_TAG_SWAP_SERVER 16 /// Swap Server
+#define DHCP4_TAG_ROOTPATH 17 /// Root path
+#define DHCP4_TAG_EXTEND_PATH 18 /// Extensions Path
+#define DHCP4_TAG_IPFORWARD 19 /// IP Forwarding Enable/Disable
+#define DHCP4_TAG_NONLOCAL_SRR 20 /// on-Local Source Routing Enable/Disable
+#define DHCP4_TAG_POLICY_SRR 21 /// Policy Filter
+#define DHCP4_TAG_EMTU 22 /// Maximum Datagram Reassembly Size
+#define DHCP4_TAG_TTL 23 /// Default IP Time-to-live
+#define DHCP4_TAG_PATHMTU_AGE 24 /// Path MTU Aging Timeout
+#define DHCP4_TAG_PATHMTU_PLATEAU 25 /// Path MTU Plateau Table
+#define DHCP4_TAG_IFMTU 26 /// Interface MTU
+#define DHCP4_TAG_SUBNET_LOCAL 27 /// All Subnets are Local
+#define DHCP4_TAG_BROADCAST 28 /// Broadcast Address
+#define DHCP4_TAG_DISCOVER_MASK 29 /// Perform Mask Discovery
+#define DHCP4_TAG_SUPPLY_MASK 30 /// Mask Supplier
+#define DHCP4_TAG_DISCOVER_ROUTE 31 /// Perform Router Discovery
+#define DHCP4_TAG_ROUTER_SOLICIT 32 /// Router Solicitation Address
+#define DHCP4_TAG_STATIC_ROUTE 33 /// Static Route
+#define DHCP4_TAG_TRAILER 34 /// Trailer Encapsulation
+#define DHCP4_TAG_ARPAGE 35 /// ARP Cache Timeout
+#define DHCP4_TAG_ETHER_ENCAP 36 /// Ethernet Encapsulation
+#define DHCP4_TAG_TCP_TTL 37 /// TCP Default TTL
+#define DHCP4_TAG_KEEP_INTERVAL 38 /// TCP Keepalive Interval
+#define DHCP4_TAG_KEEP_GARBAGE 39 /// TCP Keepalive Garbage
+#define DHCP4_TAG_NIS_DOMAIN 40 /// Network Information Service Domain
+#define DHCP4_TAG_NIS_SERVER 41 /// Network Information Servers
+#define DHCP4_TAG_NTP_SERVER 42 /// Network Time Protocol Servers
+#define DHCP4_TAG_VENDOR 43 /// Vendor Specific Information
+#define DHCP4_TAG_NBNS 44 /// NetBIOS over TCP/IP Name Server
+#define DHCP4_TAG_NBDD 45 /// NetBIOS Datagram Distribution Server
+#define DHCP4_TAG_NBTYPE 46 /// NetBIOS over TCP/IP Node Type
+#define DHCP4_TAG_NBSCOPE 47 /// NetBIOS over TCP/IP Scope
+#define DHCP4_TAG_XFONT 48 /// X Window System Font Server
+#define DHCP4_TAG_XDM 49 /// X Window System Display Manager
+#define DHCP4_TAG_REQUEST_IP 50 /// Requested IP Address
+#define DHCP4_TAG_LEASE 51 /// IP Address Lease Time
+#define DHCP4_TAG_OVERLOAD 52 /// Option Overload
+#define DHCP4_TAG_MSG_TYPE 53 /// DHCP Message Type
+#define DHCP4_TAG_SERVER_ID 54 /// Server Identifier
+#define DHCP4_TAG_PARA_LIST 55 /// Parameter Request List
+#define DHCP4_TAG_MESSAGE 56 /// Message
+#define DHCP4_TAG_MAXMSG 57 /// Maximum DHCP Message Size
+#define DHCP4_TAG_T1 58 /// Renewal (T1) Time Value
+#define DHCP4_TAG_T2 59 /// Rebinding (T2) Time Value
+#define DHCP4_TAG_VENDOR_CLASS_ID 60 /// Vendor class identifier
+#define DHCP4_TAG_CLIENT_ID 61 /// Client-identifier
+#define DHCP4_TAG_NISPLUS 64 /// Network Information Service+ Domain
+#define DHCP4_TAG_NISPLUS_SERVER 65 /// Network Information Service+ Servers
+#define DHCP4_TAG_TFTP 66 /// TFTP server name
+#define DHCP4_TAG_BOOTFILE 67 /// Bootfile name
+#define DHCP4_TAG_MOBILEIP 68 /// Mobile IP Home Agent
+#define DHCP4_TAG_SMTP 69 /// Simple Mail Transport Protocol Server
+#define DHCP4_TAG_POP3 70 /// Post Office Protocol (POP3) Server
+#define DHCP4_TAG_NNTP 71 /// Network News Transport Protocol Server
+#define DHCP4_TAG_WWW 72 /// Default World Wide Web (WWW) Server
+#define DHCP4_TAG_FINGER 73 /// Default Finger Server
+#define DHCP4_TAG_IRC 74 /// Default Internet Relay Chat (IRC) Server
+#define DHCP4_TAG_STTALK 75 /// StreetTalk Server
+#define DHCP4_TAG_STDA 76 /// StreetTalk Directory Assistance Server
+#define DHCP4_TAG_USER_CLASS_ID 77 /// User class identifier
+#define DHCP4_TAG_ARCH 93 /// Client System Architecture Type, RFC 4578
+#define DHCP4_TAG_UNDI 94 /// Client Network Interface Identifier, RFC 4578
+#define DHCP4_TAG_UUID 97 /// Client Machine Identifier, RFC 4578
+#define DHCP4_TAG_CLASSLESS_ROUTE 121 /// Classless Route
+
+///
+/// Dynamic Host Configuration Protocol for IPv6 (DHCPv6)
+///
+/// Enumeration of Dhcp6 message type, refers to section-5.3 of rfc-3315.
+///
+typedef enum {
+ Dhcp6MsgSolicit = 1,
+ Dhcp6MsgAdvertise = 2,
+ Dhcp6MsgRequest = 3,
+ Dhcp6MsgConfirm = 4,
+ Dhcp6MsgRenew = 5,
+ Dhcp6MsgRebind = 6,
+ Dhcp6MsgReply = 7,
+ Dhcp6MsgRelease = 8,
+ Dhcp6MsgDecline = 9,
+ Dhcp6MsgReconfigure = 10,
+ Dhcp6MsgInfoRequest = 11
+} DHCP6_MSG_TYPE;
+
+///
+/// Enumeration of option code in Dhcp6 packet, refers to section-24.3 of rfc-3315.
+///
+typedef enum {
+ Dhcp6OptClientId = 1,
+ Dhcp6OptServerId = 2,
+ Dhcp6OptIana = 3,
+ Dhcp6OptIata = 4,
+ Dhcp6OptIaAddr = 5,
+ Dhcp6OptRequestOption = 6,
+ Dhcp6OptPreference = 7,
+ Dhcp6OptElapsedTime = 8,
+ Dhcp6OptReplayMessage = 9,
+ Dhcp6OptAuthentication = 11,
+ Dhcp6OptServerUnicast = 12,
+ Dhcp6OptStatusCode = 13,
+ Dhcp6OptRapidCommit = 14,
+ Dhcp6OptUserClass = 15,
+ Dhcp6OptVendorClass = 16,
+ Dhcp6OptVendorInfo = 17,
+ Dhcp6OptInterfaceId = 18,
+ Dhcp6OptReconfigMessage = 19,
+ Dhcp6OptReconfigureAccept = 20
+} DHCP6_OPT_CODE;
+
+///
+/// Enumeration of status code recorded by IANA, refers to section-24.4 of rfc-3315.
+///
+typedef enum {
+ Dhcp6StsSuccess = 0,
+ Dhcp6StsUnspecFail = 1,
+ Dhcp6StsNoAddrsAvail = 2,
+ Dhcp6StsNoBinding = 3,
+ Dhcp6StsNotOnLink = 4,
+ Dhcp6StsUseMulticast = 5
+} DHCP6_STS_CODE;
+
+///
+/// Enumeration of Duid type recorded by IANA, refers to section-24.5 of rfc-3315.
+///
+typedef enum {
+ Dhcp6DuidTypeLlt = 1,
+ Dhcp6DuidTypeEn = 2,
+ Dhcp6DuidTypeLl = 3,
+ Dhcp6DuidTypeUuid = 4
+} DHCP6_DUID_TYPE;
+
+/// Transmission and Retransmission Parameters
+/// This section presents a table of values used to describe the message
+/// transmission behavior of clients and servers.
+///
+/// Transmit parameters of solicit message, refers to section-5.5 of rfc-3315.
+///
+#define DHCP6_SOL_MAX_DELAY 1
+#define DHCP6_SOL_IRT 1
+#define DHCP6_SOL_MRC 0
+#define DHCP6_SOL_MRT 120
+#define DHCP6_SOL_MRD 0
+///
+/// Transmit parameters of request message, refers to section-5.5 of rfc-3315.
+///
+#define DHCP6_REQ_IRT 1
+#define DHCP6_REQ_MRC 10
+#define DHCP6_REQ_MRT 30
+#define DHCP6_REQ_MRD 0
+///
+/// Transmit parameters of confirm message, refers to section-5.5 of rfc-3315.
+///
+#define DHCP6_CNF_MAX_DELAY 1
+#define DHCP6_CNF_IRT 1
+#define DHCP6_CNF_MRC 0
+#define DHCP6_CNF_MRT 4
+#define DHCP6_CNF_MRD 10
+///
+/// Transmit parameters of renew message, refers to section-5.5 of rfc-3315.
+///
+#define DHCP6_REN_IRT 10
+#define DHCP6_REN_MRC 0
+#define DHCP6_REN_MRT 600
+#define DHCP6_REN_MRD 0
+///
+/// Transmit parameters of rebind message, refers to section-5.5 of rfc-3315.
+///
+#define DHCP6_REB_IRT 10
+#define DHCP6_REB_MRC 0
+#define DHCP6_REB_MRT 600
+#define DHCP6_REB_MRD 0
+///
+/// Transmit parameters of information request message, refers to section-5.5 of rfc-3315.
+///
+#define DHCP6_INF_MAX_DELAY 1
+#define DHCP6_INF_IRT 1
+#define DHCP6_INF_MRC 0
+#define DHCP6_INF_MRT 120
+#define DHCP6_INF_MRD 0
+///
+/// Transmit parameters of release message, refers to section-5.5 of rfc-3315.
+///
+#define DHCP6_REL_IRT 1
+#define DHCP6_REL_MRC 5
+#define DHCP6_REL_MRT 0
+#define DHCP6_REL_MRD 0
+///
+/// Transmit parameters of decline message, refers to section-5.5 of rfc-3315.
+///
+#define DHCP6_DEC_IRT 1
+#define DHCP6_DEC_MRC 5
+#define DHCP6_DEC_MRT 0
+#define DHCP6_DEC_MRD 0
+
+////
+//// DHCPv6 Options, definitions from RFC 3315,RFC 5970 and RFC 3646.
+////
+#define DHCP6_OPT_CLIENT_ID 1 /// Client Identifier Option
+#define DHCP6_OPT_SERVER_ID 2 /// Server Identifier Option
+#define DHCP6_OPT_IA_NA 3 /// The Identity Association for Non-temporary Addresses option
+#define DHCP6_OPT_IA_TA 4 /// The Identity Association for the Temporary Addresses
+#define DHCP6_OPT_IAADDR 5 /// IA Address option
+#define DHCP6_OPT_ORO 6 /// Request option
+#define DHCP6_OPT_PREFERENCE 7 /// Preference option
+#define DHCP6_OPT_ELAPSED_TIME 8 /// Elapsed Time Option
+#define DHCP6_OPT_REPLAY_MSG 9 /// Relay Message option
+#define DHCP6_OPT_AUTH 11 /// Authentication option
+#define DHCP6_OPT_UNICAST 12 /// Server Unicast Option
+#define DHCP6_OPT_STATUS_CODE 13 /// Status Code Option
+#define DHCP6_OPT_RAPID_COMMIT 14 /// Rapid Commit option
+#define DHCP6_OPT_USER_CLASS 15 /// User Class option
+#define DHCP6_OPT_VENDOR_CLASS 16 /// Vendor Class Option
+#define DHCP6_OPT_VENDOR_OPTS 17 /// Vendor-specific Information Option
+#define DHCP6_OPT_INTERFACE_ID 18 /// Interface-Id Option
+#define DHCP6_OPT_RECONFIG_MSG 19 /// Reconfigure Message Option
+#define DHCP6_OPT_RECONFIG_ACCEPT 20 /// Reconfigure Accept Option
+#define DHCP6_OPT_DNS_SERVERS 23 /// DNS Configuration options, RFC 3646
+#define DHCP6_OPT_BOOT_FILE_URL 59 /// Assigned by IANA, RFC 5970
+#define DHCP6_OPT_BOOT_FILE_PARAM 60 /// Assigned by IANA, RFC 5970
+#define DHCP6_OPT_ARCH 61 /// Assigned by IANA, RFC 5970
+#define DHCP6_OPT_UNDI 62 /// Assigned by IANA, RFC 5970
+
+///
+/// Processor Architecture Types
+/// These identifiers are defined by IANA:
+/// https://www.iana.org/assignments/dhcpv6-parameters/dhcpv6-parameters.xhtml
+///
+#define PXE_CLIENT_ARCH_X86_BIOS 0x0000 /// x86 BIOS for PXE
+#define PXE_CLIENT_ARCH_IPF 0x0002 /// Itanium for PXE
+#define PXE_CLIENT_ARCH_IA32 0x0006 /// x86 uefi for PXE
+#define PXE_CLIENT_ARCH_X64 0x0007 /// x64 uefi for PXE
+#define PXE_CLIENT_ARCH_EBC 0x0009 /// EBC for PXE
+#define PXE_CLIENT_ARCH_ARM 0x000A /// Arm uefi 32 for PXE
+#define PXE_CLIENT_ARCH_AARCH64 0x000B /// Arm uefi 64 for PXE
+#define PXE_CLIENT_ARCH_RISCV32 0x0019 /// RISC-V uefi 32 for PXE
+#define PXE_CLIENT_ARCH_RISCV64 0x001B /// RISC-V uefi 64 for PXE
+#define PXE_CLIENT_ARCH_RISCV128 0x001D /// RISC-V uefi 128 for PXE
+#define PXE_CLIENT_ARCH_LOONGARCH32 0x0025 /// LoongArch uefi 32 for PXE
+#define PXE_CLIENT_ARCH_LOONGARCH64 0x0027 /// LoongArch uefi 64 for PXE
+
+#define HTTP_CLIENT_ARCH_IA32 0x000F /// x86 uefi boot from http
+#define HTTP_CLIENT_ARCH_X64 0x0010 /// x64 uefi boot from http
+#define HTTP_CLIENT_ARCH_EBC 0x0011 /// EBC boot from http
+#define HTTP_CLIENT_ARCH_ARM 0x0012 /// Arm uefi 32 boot from http
+#define HTTP_CLIENT_ARCH_AARCH64 0x0013 /// Arm uefi 64 boot from http
+#define HTTP_CLIENT_ARCH_RISCV32 0x001A /// RISC-V uefi 32 boot from http
+#define HTTP_CLIENT_ARCH_RISCV64 0x001C /// RISC-V uefi 64 boot from http
+#define HTTP_CLIENT_ARCH_RISCV128 0x001E /// RISC-V uefi 128 boot from http
+#define HTTP_CLIENT_ARCH_LOONGARCH32 0x0026 /// LoongArch uefi 32 boot from http
+#define HTTP_CLIENT_ARCH_LOONGARCH64 0x0028 /// LoongArch uefi 64 boot from http
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/DmaRemappingReportingTable.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/DmaRemappingReportingTable.h
new file mode 100644
index 0000000000..8a04bfaef2
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/DmaRemappingReportingTable.h
@@ -0,0 +1,329 @@
+/** @file
+ DMA Remapping Reporting (DMAR) ACPI table definition from Intel(R)
+ Virtualization Technology for Directed I/O (VT-D) Architecture Specification.
+
+ Copyright (c) 2016 - 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Revision Reference:
+ - Intel(R) Virtualization Technology for Directed I/O (VT-D) Architecture
+ Specification v4.0, Dated June 2022.
+ https://software.intel.com/content/dam/develop/external/us/en/documents/vt-directed-io-spec.pdf
+
+ @par Glossary:
+ - HPET - High Precision Event Timer
+ - NUMA - Non-uniform Memory Access
+**/
+
+#ifndef _DMA_REMAPPING_REPORTING_TABLE_H_
+#define _DMA_REMAPPING_REPORTING_TABLE_H_
+
+#include
+
+#pragma pack(1)
+
+///
+/// DMA-Remapping Reporting Structure definitions from section 8.1
+///@{
+#define EFI_ACPI_DMAR_REVISION 0x01
+
+#define EFI_ACPI_DMAR_FLAGS_INTR_REMAP BIT0
+#define EFI_ACPI_DMAR_FLAGS_X2APIC_OPT_OUT BIT1
+#define EFI_ACPI_DMAR_FLAGS_DMA_CTRL_PLATFORM_OPT_IN_FLAG BIT2
+///@}
+
+///
+/// Remapping Structure Types definitions from section 8.2
+///@{
+#define EFI_ACPI_DMAR_TYPE_DRHD 0x00
+#define EFI_ACPI_DMAR_TYPE_RMRR 0x01
+#define EFI_ACPI_DMAR_TYPE_ATSR 0x02
+#define EFI_ACPI_DMAR_TYPE_RHSA 0x03
+#define EFI_ACPI_DMAR_TYPE_ANDD 0x04
+#define EFI_ACPI_DMAR_TYPE_SATC 0x05
+#define EFI_ACPI_DMAR_TYPE_SIDP 0x06
+///@}
+
+///
+/// DMA-Remapping Hardware Unit definitions from section 8.3
+///
+#define EFI_ACPI_DMAR_DRHD_FLAGS_INCLUDE_PCI_ALL BIT0
+
+///
+/// DMA-Remapping Device Scope Entry Structure definitions from section 8.3.1
+///@{
+#define EFI_ACPI_DEVICE_SCOPE_ENTRY_TYPE_PCI_ENDPOINT 0x01
+#define EFI_ACPI_DEVICE_SCOPE_ENTRY_TYPE_PCI_BRIDGE 0x02
+#define EFI_ACPI_DEVICE_SCOPE_ENTRY_TYPE_IOAPIC 0x03
+#define EFI_ACPI_DEVICE_SCOPE_ENTRY_TYPE_MSI_CAPABLE_HPET 0x04
+#define EFI_ACPI_DEVICE_SCOPE_ENTRY_TYPE_ACPI_NAMESPACE_DEVICE 0x05
+
+#define EFI_ACPI_DEVICE_SCOPE_REQ_WO_PASID_NESTED_NOTALLOWED BIT0
+#define EFI_ACPI_DEVICE_SCOPE_REQ_WO_PASID_PWSNP_NOTALLOWED BIT1
+#define EFI_ACPI_DEVICE_SCOPE_REQ_WO_PASID_PGSNP_NOTALLOWED BIT2
+#define EFI_ACPI_DEVICE_SCOPE_REQ_WO_PASID_ATC_HARDENED BIT3
+#define EFI_ACPI_DEVICE_SCOPE_REQ_WO_PASID_ATC_REQUIRED BIT4
+///@}
+
+///
+/// Root Port ATS Capability Reporting Structure definitions from section 8.5
+///
+#define EFI_ACPI_DMAR_ATSR_FLAGS_ALL_PORTS BIT0
+
+///
+/// Definition for DMA Remapping Structure Header
+///
+typedef struct {
+ UINT16 Type;
+ UINT16 Length;
+} EFI_ACPI_DMAR_STRUCTURE_HEADER;
+
+///
+/// Definition for DMA-Remapping PCI Path
+///
+typedef struct {
+ UINT8 Device;
+ UINT8 Function;
+} EFI_ACPI_DMAR_PCI_PATH;
+
+///
+/// Device Scope Structure is defined in section 8.3.1
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 Flags;
+ UINT8 Reserved;
+ UINT8 EnumerationId;
+ UINT8 StartBusNumber;
+} EFI_ACPI_DMAR_DEVICE_SCOPE_STRUCTURE_HEADER;
+
+/**
+ DMA-remapping hardware unit definition (DRHD) structure is defined in
+ section 8.3. This uniquely represents a remapping hardware unit present
+ in the platform. There must be at least one instance of this structure
+ for each PCI segment in the platform.
+**/
+typedef struct {
+ EFI_ACPI_DMAR_STRUCTURE_HEADER Header;
+
+ /**
+ - Bit[0]: INCLUDE_PCI_ALL
+ - If Set, this remapping hardware unit has under its scope all
+ PCI compatible devices in the specified Segment, except devices
+ reported under the scope of other remapping hardware units for
+ the same Segment.
+ - If Clear, this remapping hardware unit has under its scope only
+ devices in the specified Segment that are explicitly identified
+ through the DeviceScope field.
+ - Bits[7:1] Reserved.
+ **/
+ UINT8 Flags;
+
+ /**
+ - Bits[3:0]: Indicates the size of the remapping hardware register set for
+ this remapping unit. If the value in this field is N, the size
+ of the register set is 2^N 4 KB pages
+ - Bits[7:4]: Reserved.
+ **/
+ UINT8 Size;
+ ///
+ /// The PCI Segment associated with this unit.
+ ///
+ UINT16 SegmentNumber;
+ ///
+ /// Base address of remapping hardware register-set for this unit.
+ ///
+ UINT64 RegisterBaseAddress;
+} EFI_ACPI_DMAR_DRHD_HEADER;
+
+/**
+ Reserved Memory Region Reporting Structure (RMRR) is described in section 8.4
+ Reserved memory ranges that may be DMA targets may be reported through the
+ RMRR structures, along with the devices that requires access to the specified
+ reserved memory region.
+**/
+typedef struct {
+ EFI_ACPI_DMAR_STRUCTURE_HEADER Header;
+ UINT8 Reserved[2];
+ ///
+ /// PCI Segment Number associated with devices identified through
+ /// the Device Scope field.
+ ///
+ UINT16 SegmentNumber;
+ ///
+ /// Base address of 4KB-aligned reserved memory region
+ ///
+ UINT64 ReservedMemoryRegionBaseAddress;
+
+ /**
+ Last address of the reserved memory region. Value in this field must be
+ greater than the value in Reserved Memory Region Base Address field.
+ The reserved memory region size (Limit - Base + 1) must be an integer
+ multiple of 4KB.
+ **/
+ UINT64 ReservedMemoryRegionLimitAddress;
+} EFI_ACPI_DMAR_RMRR_HEADER;
+
+/**
+ Root Port ATS Capability Reporting (ATSR) structure is defined in section 8.5.
+ This structure is applicable only for platforms supporting Device-TLBs as
+ reported through the Extended Capability Register. For each PCI Segment in
+ the platform that supports Device-TLBs, BIOS provides an ATSR structure. The
+ ATSR structures identifies PCI-Express Root-Ports supporting Address
+ Translation Services (ATS) transactions. Software must enable ATS on endpoint
+ devices behind a Root Port only if the Root Port is reported as supporting
+ ATS transactions.
+**/
+typedef struct {
+ EFI_ACPI_DMAR_STRUCTURE_HEADER Header;
+
+ /**
+ - Bit[0]: ALL_PORTS:
+ - If Set, indicates all PCI Express Root Ports in the specified
+ PCI Segment supports ATS transactions.
+ - If Clear, indicates ATS transactions are supported only on
+ Root Ports identified through the Device Scope field.
+ - Bits[7:1] Reserved.
+ **/
+ UINT8 Flags;
+ UINT8 Reserved;
+ ///
+ /// The PCI Segment associated with this ATSR structure
+ ///
+ UINT16 SegmentNumber;
+} EFI_ACPI_DMAR_ATSR_HEADER;
+
+/**
+ Remapping Hardware Static Affinity (RHSA) is an optional structure defined
+ in section 8.6. This is intended to be used only on NUMA platforms with
+ Remapping hardware units and memory spanned across multiple nodes.
+ When used, there must be a RHSA structure for each Remapping hardware unit
+ reported through DRHD structure.
+**/
+typedef struct {
+ EFI_ACPI_DMAR_STRUCTURE_HEADER Header;
+ UINT8 Reserved[4];
+ ///
+ /// Register Base Address of this Remap hardware unit reported in the
+ /// corresponding DRHD structure.
+ ///
+ UINT64 RegisterBaseAddress;
+ ///
+ /// Proximity Domain to which the Remap hardware unit identified by the
+ /// Register Base Address field belongs.
+ ///
+ UINT32 ProximityDomain;
+} EFI_ACPI_DMAR_RHSA_HEADER;
+
+/**
+ An ACPI Name-space Device Declaration (ANDD) structure is defined in section
+ 8.7 and uniquely represents an ACPI name-space enumerated device capable of
+ issuing DMA requests in the platform. ANDD structures are used in conjunction
+ with Device-Scope entries of type ACPI_NAMESPACE_DEVICE.
+**/
+typedef struct {
+ EFI_ACPI_DMAR_STRUCTURE_HEADER Header;
+ UINT8 Reserved[3];
+
+ /**
+ Each ACPI device enumerated through an ANDD structure must have a unique
+ value for this field. To report an ACPI device with ACPI Device Number
+ value of X, under the scope of a DRHD unit, a Device-Scope entry of type
+ ACPI_NAMESPACE_DEVICE is used with value of X in the Enumeration ID field.
+ The Start Bus Number and Path fields in the Device-Scope together
+ provides the 16-bit source-id allocated by platform for the ACPI device.
+ **/
+ UINT8 AcpiDeviceNumber;
+} EFI_ACPI_DMAR_ANDD_HEADER;
+
+/**
+ An SoC Integrated Address Translation Cache (SATC) reporting structure is
+ defined in section 8.8.
+**/
+typedef struct {
+ EFI_ACPI_DMAR_STRUCTURE_HEADER Header;
+
+ /**
+ - Bit[0]: ATC_REQUIRED:
+ - If Set, indicates that every SoC integrated device enumerated
+ in this table has a functional requirement to enable its ATC
+ (via the ATS capability) for device operation.
+ - If Clear, any device enumerated in this table can operate when
+ its respective ATC is not enabled (albeit with reduced
+ performance or functionality).
+ - Bits[7:1] Reserved.
+ **/
+ UINT8 Flags;
+ UINT8 Reserved;
+ ///
+ /// The PCI Segment associated with this SATC structure. All SoC integrated
+ /// devices within a PCI segment with same value for Flags field must be
+ /// enumerated in the same SATC structure.
+ ///
+ UINT16 SegmentNumber;
+} EFI_ACPI_DMAR_SATC_HEADER;
+
+/**
+ SoC Integrated Device Property (SIDP) Reporting Structure is defined in
+ section 8.9.
+**/
+typedef struct {
+ EFI_ACPI_DMAR_STRUCTURE_HEADER Header;
+
+ UINT16 Reserved;
+ ///
+ /// The PCI Segment associated with this SIDP structure.
+ ///
+ UINT16 SegmentNumber;
+} EFI_ACPI_DMAR_SIDP_HEADER;
+
+/**
+ DMA Remapping Reporting Structure Header as defined in section 8.1
+ This header will be followed by list of Remapping Structures listed below
+ - DMA Remapping Hardware Unit Definition (DRHD)
+ - Reserved Memory Region Reporting (RMRR)
+ - Root Port ATS Capability Reporting (ATSR)
+ - Remapping Hardware Static Affinity (RHSA)
+ - ACPI Name-space Device Declaration (ANDD)
+ - SoC Integrated Address Translation Cache reporting (SATC)
+ - SoC Integrated Device Property reporting (SIDP)
+ These structure types must by reported in numerical order.
+ i.e., All remapping structures of type 0 (DRHD) enumerated before remapping
+ structures of type 1 (RMRR), and so forth.
+**/
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+
+ /**
+ This field indicates the maximum DMA physical addressability supported by
+ this platform. The system address map reported by the BIOS indicates what
+ portions of this addresses are populated. The Host Address Width (HAW) of
+ the platform is computed as (N+1), where N is the value reported in this
+ field.
+ For example, for a platform supporting 40 bits of physical addressability,
+ the value of 100111b is reported in this field.
+ **/
+ UINT8 HostAddressWidth;
+
+ /**
+ - Bit[0]: INTR_REMAP - If Clear, the platform does not support interrupt
+ remapping. If Set, the platform supports interrupt remapping.
+ - Bit[1]: X2APIC_OPT_OUT - For firmware compatibility reasons, platform
+ firmware may Set this field to request system software to opt
+ out of enabling Extended xAPIC (X2APIC) mode. This field is
+ valid only when the INTR_REMAP field (bit 0) is Set.
+ - Bit[2]: DMA_CTRL_PLATFORM_OPT_IN_FLAG - Platform firmware is
+ recommended to Set this field to report any platform initiated
+ DMA is restricted to only reserved memory regions (reported in
+ RMRR structures) when transferring control to system software
+ such as on ExitBootServices().
+ - Bits[7:3] Reserved.
+ **/
+ UINT8 Flags;
+ UINT8 Reserved[10];
+} EFI_ACPI_DMAR_HEADER;
+
+#pragma pack()
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/ElTorito.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/ElTorito.h
new file mode 100644
index 0000000000..b6a8b1a5a0
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/ElTorito.h
@@ -0,0 +1,138 @@
+/** @file
+ ElTorito Partitions Format Definition.
+ This file includes some definitions from
+ 1. "El Torito" Bootable CD-ROM Format Specification, Version 1.0.
+ 2. Volume and File Structure of CDROM for Information Interchange,
+ Standard ECMA-119. (IS0 9660)
+
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _ELTORITO_H_
+#define _ELTORITO_H_
+
+//
+// CDROM_VOLUME_DESCRIPTOR.Types, defined in ISO 9660
+//
+#define CDVOL_TYPE_STANDARD 0x0
+#define CDVOL_TYPE_CODED 0x1
+#define CDVOL_TYPE_END 0xFF
+
+///
+/// CDROM_VOLUME_DESCRIPTOR.Id
+///
+#define CDVOL_ID "CD001"
+
+///
+/// CDROM_VOLUME_DESCRIPTOR.SystemId
+///
+#define CDVOL_ELTORITO_ID "EL TORITO SPECIFICATION"
+
+//
+// Indicator types
+//
+#define ELTORITO_ID_CATALOG 0x01
+#define ELTORITO_ID_SECTION_BOOTABLE 0x88
+#define ELTORITO_ID_SECTION_NOT_BOOTABLE 0x00
+#define ELTORITO_ID_SECTION_HEADER 0x90
+#define ELTORITO_ID_SECTION_HEADER_FINAL 0x91
+
+//
+// ELTORITO_CATALOG.Boot.MediaTypes
+//
+#define ELTORITO_NO_EMULATION 0x00
+#define ELTORITO_12_DISKETTE 0x01
+#define ELTORITO_14_DISKETTE 0x02
+#define ELTORITO_28_DISKETTE 0x03
+#define ELTORITO_HARD_DISK 0x04
+
+#pragma pack(1)
+
+///
+/// CD-ROM Volume Descriptor
+///
+typedef union {
+ struct {
+ UINT8 Type;
+ CHAR8 Id[5]; ///< "CD001"
+ CHAR8 Reserved[82];
+ } Unknown;
+
+ ///
+ /// Boot Record Volume Descriptor, defined in "El Torito" Specification.
+ ///
+ struct {
+ UINT8 Type; ///< Must be 0
+ CHAR8 Id[5]; ///< "CD001"
+ UINT8 Version; ///< Must be 1
+ CHAR8 SystemId[32]; ///< "EL TORITO SPECIFICATION"
+ CHAR8 Unused[32]; ///< Must be 0
+ UINT8 EltCatalog[4]; ///< Absolute pointer to first sector of Boot Catalog
+ CHAR8 Unused2[13]; ///< Must be 0
+ } BootRecordVolume;
+
+ ///
+ /// Primary Volume Descriptor, defined in ISO 9660.
+ ///
+ struct {
+ UINT8 Type;
+ CHAR8 Id[5]; ///< "CD001"
+ UINT8 Version;
+ UINT8 Unused; ///< Must be 0
+ CHAR8 SystemId[32];
+ CHAR8 VolumeId[32];
+ UINT8 Unused2[8]; ///< Must be 0
+ UINT32 VolSpaceSize[2]; ///< the number of Logical Blocks
+ } PrimaryVolume;
+} CDROM_VOLUME_DESCRIPTOR;
+
+///
+/// Catalog Entry
+///
+typedef union {
+ struct {
+ CHAR8 Reserved[0x20];
+ } Unknown;
+
+ ///
+ /// Catalog validation entry (Catalog header)
+ ///
+ struct {
+ UINT8 Indicator; ///< Must be 01
+ UINT8 PlatformId;
+ UINT16 Reserved;
+ CHAR8 ManufacId[24];
+ UINT16 Checksum;
+ UINT16 Id55AA;
+ } Catalog;
+
+ ///
+ /// Initial/Default Entry or Section Entry
+ ///
+ struct {
+ UINT8 Indicator; ///< 88 = Bootable, 00 = Not Bootable
+ UINT8 MediaType : 4;
+ UINT8 Reserved1 : 4; ///< Must be 0
+ UINT16 LoadSegment;
+ UINT8 SystemType;
+ UINT8 Reserved2; ///< Must be 0
+ UINT16 SectorCount;
+ UINT32 Lba;
+ } Boot;
+
+ ///
+ /// Section Header Entry
+ ///
+ struct {
+ UINT8 Indicator; ///< 90 - Header, more header follw, 91 - Final Header
+ UINT8 PlatformId;
+ UINT16 SectionEntries; ///< Number of section entries following this header
+ CHAR8 Id[28];
+ } Section;
+} ELTORITO_CATALOG;
+
+#pragma pack()
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/Emmc.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/Emmc.h
new file mode 100644
index 0000000000..a2ff5b731e
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/Emmc.h
@@ -0,0 +1,291 @@
+/** @file
+ Header file for eMMC support.
+
+ This header file contains some definitions defined in EMMC4.5/EMMC5.0 spec.
+
+ Copyright (c) 2015, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __EMMC_H__
+#define __EMMC_H__
+
+//
+// EMMC command index
+//
+#define EMMC_GO_IDLE_STATE 0
+#define EMMC_SEND_OP_COND 1
+#define EMMC_ALL_SEND_CID 2
+#define EMMC_SET_RELATIVE_ADDR 3
+#define EMMC_SET_DSR 4
+#define EMMC_SLEEP_AWAKE 5
+#define EMMC_SWITCH 6
+#define EMMC_SELECT_DESELECT_CARD 7
+#define EMMC_SEND_EXT_CSD 8
+#define EMMC_SEND_CSD 9
+#define EMMC_SEND_CID 10
+#define EMMC_STOP_TRANSMISSION 12
+#define EMMC_SEND_STATUS 13
+#define EMMC_BUSTEST_R 14
+#define EMMC_GO_INACTIVE_STATE 15
+#define EMMC_SET_BLOCKLEN 16
+#define EMMC_READ_SINGLE_BLOCK 17
+#define EMMC_READ_MULTIPLE_BLOCK 18
+#define EMMC_BUSTEST_W 19
+#define EMMC_SEND_TUNING_BLOCK 21
+#define EMMC_SET_BLOCK_COUNT 23
+#define EMMC_WRITE_BLOCK 24
+#define EMMC_WRITE_MULTIPLE_BLOCK 25
+#define EMMC_PROGRAM_CID 26
+#define EMMC_PROGRAM_CSD 27
+#define EMMC_SET_WRITE_PROT 28
+#define EMMC_CLR_WRITE_PROT 29
+#define EMMC_SEND_WRITE_PROT 30
+#define EMMC_SEND_WRITE_PROT_TYPE 31
+#define EMMC_ERASE_GROUP_START 35
+#define EMMC_ERASE_GROUP_END 36
+#define EMMC_ERASE 38
+#define EMMC_FAST_IO 39
+#define EMMC_GO_IRQ_STATE 40
+#define EMMC_LOCK_UNLOCK 42
+#define EMMC_SET_TIME 49
+#define EMMC_PROTOCOL_RD 53
+#define EMMC_PROTOCOL_WR 54
+#define EMMC_APP_CMD 55
+#define EMMC_GEN_CMD 56
+
+typedef enum {
+ EmmcPartitionUserData = 0,
+ EmmcPartitionBoot1 = 1,
+ EmmcPartitionBoot2 = 2,
+ EmmcPartitionRPMB = 3,
+ EmmcPartitionGP1 = 4,
+ EmmcPartitionGP2 = 5,
+ EmmcPartitionGP3 = 6,
+ EmmcPartitionGP4 = 7,
+ EmmcPartitionUnknown
+} EMMC_PARTITION_TYPE;
+
+#pragma pack(1)
+typedef struct {
+ UINT8 NotUsed : 1; // Not used [0:0]
+ UINT8 Crc : 7; // CRC [7:1]
+ UINT8 ManufacturingDate; // Manufacturing date [15:8]
+ UINT8 ProductSerialNumber[4]; // Product serial number [47:16]
+ UINT8 ProductRevision; // Product revision [55:48]
+ UINT8 ProductName[6]; // Product name [103:56]
+ UINT8 OemId; // OEM/Application ID [111:104]
+ UINT8 DeviceType : 2; // Device/BGA [113:112]
+ UINT8 Reserved : 6; // Reserved [119:114]
+ UINT8 ManufacturerId; // Manufacturer ID [127:120]
+} EMMC_CID;
+
+typedef struct {
+ UINT32 NotUsed : 1; // Not used [0:0]
+ UINT32 Crc : 7; // CRC [7:1]
+ UINT32 Ecc : 2; // ECC code [9:8]
+ UINT32 FileFormat : 2; // File format [11:10]
+ UINT32 TmpWriteProtect : 1; // Temporary write protection [12:12]
+ UINT32 PermWriteProtect : 1; // Permanent write protection [13:13]
+ UINT32 Copy : 1; // Copy flag (OTP) [14:14]
+ UINT32 FileFormatGrp : 1; // File format group [15:15]
+ UINT32 ContentProtApp : 1; // Content protection application [16:16]
+ UINT32 Reserved : 4; // Reserved [20:17]
+ UINT32 WriteBlPartial : 1; // Partial blocks for write allowed [21:21]
+ UINT32 WriteBlLen : 4; // Max. write data block length [25:22]
+ UINT32 R2WFactor : 3; // Write speed factor [28:26]
+ UINT32 DefaultEcc : 2; // Manufacturer default ECC [30:29]
+ UINT32 WpGrpEnable : 1; // Write protect group enable [31:31]
+
+ UINT32 WpGrpSize : 5; // Write protect group size [36:32]
+ UINT32 EraseGrpMult : 5; // Erase group size multiplier [41:37]
+ UINT32 EraseGrpSize : 5; // Erase group size [46:42]
+ UINT32 CSizeMult : 3; // Device size multiplier [49:47]
+ UINT32 VddWCurrMax : 3; // Max. write current @ VDD max [52:50]
+ UINT32 VddWCurrMin : 3; // Max. write current @ VDD min [55:53]
+ UINT32 VddRCurrMax : 3; // Max. read current @ VDD max [58:56]
+ UINT32 VddRCurrMin : 3; // Max. read current @ VDD min [61:59]
+ UINT32 CSizeLow : 2; // Device size low two bits [63:62]
+
+ UINT32 CSizeHigh : 10; // Device size high eight bits [73:64]
+ UINT32 Reserved1 : 2; // Reserved [75:74]
+ UINT32 DsrImp : 1; // DSR implemented [76:76]
+ UINT32 ReadBlkMisalign : 1; // Read block misalignment [77:77]
+ UINT32 WriteBlkMisalign : 1; // Write block misalignment [78:78]
+ UINT32 ReadBlPartial : 1; // Partial blocks for read allowed [79:79]
+ UINT32 ReadBlLen : 4; // Max. read data block length [83:80]
+ UINT32 Ccc : 12; // Device command classes [95:84]
+
+ UINT32 TranSpeed : 8; // Max. bus clock frequency [103:96]
+ UINT32 Nsac : 8; // Data read access-time 2 in CLK cycles (NSAC*100) [111:104]
+ UINT32 Taac : 8; // Data read access-time 1 [119:112]
+ UINT32 Reserved2 : 2; // Reserved [121:120]
+ UINT32 SpecVers : 4; // System specification version [125:122]
+ UINT32 CsdStructure : 2; // CSD structure [127:126]
+} EMMC_CSD;
+
+typedef struct {
+ //
+ // Modes Segment
+ //
+ UINT8 Reserved[16]; // Reserved [15:0]
+ UINT8 SecureRemovalType; // Secure Removal Type R/W & R [16]
+ UINT8 ProductStateAwarenessEnablement; // Product state awareness enablement R/W/E & R [17]
+ UINT8 MaxPreLoadingDataSize[4]; // Max pre loading data size R [21:18]
+ UINT8 PreLoadingDataSize[4]; // Pre loading data size R/W/EP [25:22]
+ UINT8 FfuStatus; // FFU status R [26]
+ UINT8 Reserved1[2]; // Reserved [28:27]
+ UINT8 ModeOperationCodes; // Mode operation codes W/EP [29]
+ UINT8 ModeConfig; // Mode config R/W/EP [30]
+ UINT8 Reserved2; // Reserved [31]
+ UINT8 FlushCache; // Flushing of the cache W/EP [32]
+ UINT8 CacheCtrl; // Control to turn the Cache ON/OFF R/W/EP [33]
+ UINT8 PowerOffNotification; // Power Off Notification R/W/EP [34]
+ UINT8 PackedFailureIndex; // Packed command failure index R [35]
+ UINT8 PackedCommandStatus; // Packed command status R [36]
+ UINT8 ContextConf[15]; // Context configuration R/W/EP [51:37]
+ UINT8 ExtPartitionsAttribute[2]; // Extended Partitions Attribute R/W [53:52]
+ UINT8 ExceptionEventsStatus[2]; // Exception events status R [55:54]
+ UINT8 ExceptionEventsCtrl[2]; // Exception events control R/W/EP [57:56]
+ UINT8 DyncapNeeded; // Number of addressed group to be Released R [58]
+ UINT8 Class6Ctrl; // Class 6 commands control R/W/EP [59]
+ UINT8 IniTimeoutEmu; // 1st initialization after disabling sector size emulation R [60]
+ UINT8 DataSectorSize; // Sector size R [61]
+ UINT8 UseNativeSector; // Sector size emulation R/W [62]
+ UINT8 NativeSectorSize; // Native sector size R [63]
+ UINT8 VendorSpecificField[64]; // Vendor Specific Fields [127:64]
+ UINT8 Reserved3[2]; // Reserved [129:128]
+ UINT8 ProgramCidCsdDdrSupport; // Program CID/CSD in DDR mode support R [130]
+ UINT8 PeriodicWakeup; // Periodic Wake-up R/W/E [131]
+ UINT8 TcaseSupport; // Package Case Temperature is controlled W/EP [132]
+ UINT8 ProductionStateAwareness; // Production state awareness R/W/E [133]
+ UINT8 SecBadBlkMgmnt; // Bad Block Management mode R/W [134]
+ UINT8 Reserved4; // Reserved [135]
+ UINT8 EnhStartAddr[4]; // Enhanced User Data Start Address R/W [139:136]
+ UINT8 EnhSizeMult[3]; // Enhanced User Data Area Size R/W [142:140]
+ UINT8 GpSizeMult[12]; // General Purpose Partition Size R/W [154:143]
+ UINT8 PartitionSettingCompleted; // Partitioning Setting R/W [155]
+ UINT8 PartitionsAttribute; // Partitions attribute R/W [156]
+ UINT8 MaxEnhSizeMult[3]; // Max Enhanced Area Size R [159:157]
+ UINT8 PartitioningSupport; // Partitioning Support R [160]
+ UINT8 HpiMgmt; // HPI management R/W/EP [161]
+ UINT8 RstFunction; // H/W reset function R/W [162]
+ UINT8 BkopsEn; // Enable background operations handshake R/W [163]
+ UINT8 BkopsStart; // Manually start background operations W/EP [164]
+ UINT8 SanitizeStart; // Start Sanitize operation W/EP [165]
+ UINT8 WrRelParam; // Write reliability parameter register R [166]
+ UINT8 WrRelSet; // Write reliability setting register R/W [167]
+ UINT8 RpmbSizeMult; // RPMB Size R [168]
+ UINT8 FwConfig; // FW configuration R/W [169]
+ UINT8 Reserved5; // Reserved [170]
+ UINT8 UserWp; // User area write protection register R/W,R/W/CP&R/W/EP [171]
+ UINT8 Reserved6; // Reserved [172]
+ UINT8 BootWp; // Boot area write protection register R/W&R/W/CP[173]
+ UINT8 BootWpStatus; // Boot write protection status registers R [174]
+ UINT8 EraseGroupDef; // High-density erase group definition R/W/EP [175]
+ UINT8 Reserved7; // Reserved [176]
+ UINT8 BootBusConditions; // Boot bus Conditions R/W/E [177]
+ UINT8 BootConfigProt; // Boot config protection R/W&R/W/CP[178]
+ UINT8 PartitionConfig; // Partition configuration R/W/E&R/W/EP[179]
+ UINT8 Reserved8; // Reserved [180]
+ UINT8 ErasedMemCont; // Erased memory content R [181]
+ UINT8 Reserved9; // Reserved [182]
+ UINT8 BusWidth; // Bus width mode W/EP [183]
+ UINT8 Reserved10; // Reserved [184]
+ UINT8 HsTiming; // High-speed interface timing R/W/EP [185]
+ UINT8 Reserved11; // Reserved [186]
+ UINT8 PowerClass; // Power class R/W/EP [187]
+ UINT8 Reserved12; // Reserved [188]
+ UINT8 CmdSetRev; // Command set revision R [189]
+ UINT8 Reserved13; // Reserved [190]
+ UINT8 CmdSet; // Command set R/W/EP [191]
+ //
+ // Properties Segment
+ //
+ UINT8 ExtCsdRev; // Extended CSD revision [192]
+ UINT8 Reserved14; // Reserved [193]
+ UINT8 CsdStructure; // CSD STRUCTURE [194]
+ UINT8 Reserved15; // Reserved [195]
+ UINT8 DeviceType; // Device type [196]
+ UINT8 DriverStrength; // I/O Driver Strength [197]
+ UINT8 OutOfInterruptTime; // Out-of-interrupt busy timing[198]
+ UINT8 PartitionSwitchTime; // Partition switching timing [199]
+ UINT8 PwrCl52M195V; // Power class for 52MHz at 1.95V [200]
+ UINT8 PwrCl26M195V; // Power class for 26MHz at 1.95V [201]
+ UINT8 PwrCl52M360V; // Power class for 52MHz at 3.6V [202]
+ UINT8 PwrCl26M360V; // Power class for 26MHz at 3.6V [203]
+ UINT8 Reserved16; // Reserved [204]
+ UINT8 MinPerfR4B26M; // Minimum Read Performance for 4bit at 26MHz [205]
+ UINT8 MinPerfW4B26M; // Minimum Write Performance for 4bit at 26MHz [206]
+ UINT8 MinPerfR8B26M4B52M; // Minimum Read Performance for 8bit at 26MHz, for 4bit at 52MHz [207]
+ UINT8 MinPerfW8B26M4B52M; // Minimum Write Performance for 8bit at 26MHz, for 4bit at 52MHz [208]
+ UINT8 MinPerfR8B52M; // Minimum Read Performance for 8bit at 52MHz [209]
+ UINT8 MinPerfW8B52M; // Minimum Write Performance for 8bit at 52MHz [210]
+ UINT8 Reserved17; // Reserved [211]
+ UINT8 SecCount[4]; // Sector Count [215:212]
+ UINT8 SleepNotificationTime; // Sleep Notification Timeout [216]
+ UINT8 SATimeout; // Sleep/awake timeout [217]
+ UINT8 ProductionStateAwarenessTimeout; // Production state awareness timeout [218]
+ UINT8 SCVccq; // Sleep current (VCCQ) [219]
+ UINT8 SCVcc; // Sleep current (VCC) [220]
+ UINT8 HcWpGrpSize; // High-capacity write protect group size [221]
+ UINT8 RelWrSecC; // Reliable write sector count [222]
+ UINT8 EraseTimeoutMult; // High-capacity erase timeout [223]
+ UINT8 HcEraseGrpSize; // High-capacity erase unit size [224]
+ UINT8 AccSize; // Access size [225]
+ UINT8 BootSizeMult; // Boot partition size [226]
+ UINT8 Reserved18; // Reserved [227]
+ UINT8 BootInfo; // Boot information [228]
+ UINT8 SecTrimMult; // Secure TRIM Multiplier [229]
+ UINT8 SecEraseMult; // Secure Erase Multiplier [230]
+ UINT8 SecFeatureSupport; // Secure Feature support [231]
+ UINT8 TrimMult; // TRIM Multiplier [232]
+ UINT8 Reserved19; // Reserved [233]
+ UINT8 MinPerfDdrR8b52M; // Minimum Read Performance for 8bit at 52MHz in DDR mode [234]
+ UINT8 MinPerfDdrW8b52M; // Minimum Write Performance for 8bit at 52MHz in DDR mode [235]
+ UINT8 PwrCl200M130V; // Power class for 200MHz, at VCCQ=1.3V, VCC = 3.6V [236]
+ UINT8 PwrCl200M195V; // Power class for 200MHz at VCCQ=1.95V, VCC = 3.6V [237]
+ UINT8 PwrClDdr52M195V; // Power class for 52MHz, DDR at VCC= 1.95V [238]
+ UINT8 PwrClDdr52M360V; // Power class for 52MHz, DDR at VCC= 3.6V [239]
+ UINT8 Reserved20; // Reserved [240]
+ UINT8 IniTimeoutAp; // 1st initialization time after partitioning [241]
+ UINT8 CorrectlyPrgSectorsNum[4]; // Number of correctly programmed sectors [245:242]
+ UINT8 BkopsStatus; // Background operations status [246]
+ UINT8 PowerOffLongTime; // Power off notification(long) timeout [247]
+ UINT8 GenericCmd6Time; // Generic CMD6 timeout [248]
+ UINT8 CacheSize[4]; // Cache size [252:249]
+ UINT8 PwrClDdr200M360V; // Power class for 200MHz, DDR at VCC= 3.6V [253]
+ UINT8 FirmwareVersion[8]; // Firmware version [261:254]
+ UINT8 DeviceVersion[2]; // Device version [263:262]
+ UINT8 OptimalTrimUnitSize; // Optimal trim unit size[264]
+ UINT8 OptimalWriteSize; // Optimal write size [265]
+ UINT8 OptimalReadSize; // Optimal read size [266]
+ UINT8 PreEolInfo; // Pre EOL information [267]
+ UINT8 DeviceLifeTimeEstTypA; // Device life time estimation type A [268]
+ UINT8 DeviceLifeTimeEstTypB; // Device life time estimation type B [269]
+ UINT8 VendorProprietaryHealthReport[32]; // Vendor proprietary health report [301:270]
+ UINT8 NumOfFwSectorsProgrammed[4]; // Number of FW sectors correctly programmed [305:302]
+ UINT8 Reserved21[181]; // Reserved [486:306]
+ UINT8 FfuArg[4]; // FFU Argument [490:487]
+ UINT8 OperationCodeTimeout; // Operation codes timeout [491]
+ UINT8 FfuFeatures; // FFU features [492]
+ UINT8 SupportedModes; // Supported modes [493]
+ UINT8 ExtSupport; // Extended partitions attribute support [494]
+ UINT8 LargeUnitSizeM1; // Large Unit size [495]
+ UINT8 ContextCapabilities; // Context management capabilities [496]
+ UINT8 TagResSize; // Tag Resources Size [497]
+ UINT8 TagUnitSize; // Tag Unit Size [498]
+ UINT8 DataTagSupport; // Data Tag Support [499]
+ UINT8 MaxPackedWrites; // Max packed write commands [500]
+ UINT8 MaxPackedReads; // Max packed read commands[501]
+ UINT8 BkOpsSupport; // Background operations support [502]
+ UINT8 HpiFeatures; // HPI features [503]
+ UINT8 SupportedCmdSet; // Supported Command Sets [504]
+ UINT8 ExtSecurityErr; // Extended Security Commands Error [505]
+ UINT8 Reserved22[6]; // Reserved [511:506]
+} EMMC_EXT_CSD;
+
+#pragma pack()
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/HighPrecisionEventTimerTable.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/HighPrecisionEventTimerTable.h
new file mode 100644
index 0000000000..9d16104fa5
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/HighPrecisionEventTimerTable.h
@@ -0,0 +1,61 @@
+/** @file
+ ACPI high precision event timer table definition, at www.intel.com
+ Specification name is IA-PC HPET (High Precision Event Timers) Specification.
+
+ Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _HIGH_PRECISION_EVENT_TIMER_TABLE_H_
+#define _HIGH_PRECISION_EVENT_TIMER_TABLE_H_
+
+#include
+
+//
+// Ensure proper structure formats
+//
+#pragma pack(1)
+
+///
+/// HPET Event Timer Block ID described in IA-PC HPET Specification, 3.2.4.
+///
+typedef union {
+ struct {
+ UINT32 Revision : 8;
+ UINT32 NumberOfTimers : 5;
+ UINT32 CounterSize : 1;
+ UINT32 Reserved : 1;
+ UINT32 LegacyRoute : 1;
+ UINT32 VendorId : 16;
+ } Bits;
+ UINT32 Uint32;
+} EFI_ACPI_HIGH_PRECISION_EVENT_TIMER_BLOCK_ID;
+
+///
+/// High Precision Event Timer Table header definition.
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 EventTimerBlockId;
+ EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE BaseAddressLower32Bit;
+ UINT8 HpetNumber;
+ UINT16 MainCounterMinimumClockTickInPeriodicMode;
+ UINT8 PageProtectionAndOemAttribute;
+} EFI_ACPI_HIGH_PRECISION_EVENT_TIMER_TABLE_HEADER;
+
+///
+/// HPET Revision (defined in spec)
+///
+#define EFI_ACPI_HIGH_PRECISION_EVENT_TIMER_TABLE_REVISION 0x01
+
+//
+// Page protection setting
+// Values 3 through 15 are reserved for use by the specification
+//
+#define EFI_ACPI_NO_PAGE_PROTECTION 0
+#define EFI_ACPI_4KB_PAGE_PROTECTION 1
+#define EFI_ACPI_64KB_PAGE_PROTECTION 2
+
+#pragma pack()
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/Hsti.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/Hsti.h
new file mode 100644
index 0000000000..a836b17bdb
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/Hsti.h
@@ -0,0 +1,76 @@
+/** @file
+ Support for HSTI 1.1a specification, defined at
+ Microsoft Hardware Security Testability Specification.
+
+ Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __HSTI_H__
+#define __HSTI_H__
+
+#pragma pack(1)
+
+#define ADAPTER_INFO_PLATFORM_SECURITY_GUID \
+ {0x6be272c7, 0x1320, 0x4ccd, { 0x90, 0x17, 0xd4, 0x61, 0x2c, 0x01, 0x2b, 0x25 }}
+
+#define PLATFORM_SECURITY_VERSION_VNEXTCS 0x00000003
+
+#define PLATFORM_SECURITY_ROLE_PLATFORM_REFERENCE 0x00000001 // IHV
+#define PLATFORM_SECURITY_ROLE_PLATFORM_IBV 0x00000002
+#define PLATFORM_SECURITY_ROLE_IMPLEMENTOR_OEM 0x00000003
+#define PLATFORM_SECURITY_ROLE_IMPLEMENTOR_ODM 0x00000004
+
+typedef struct {
+ //
+ // Return PLATFORM_SECURITY_VERSION_VNEXTCS
+ //
+ UINT32 Version;
+ //
+ // The role of the publisher of this interface. Reference platform designers
+ // such as IHVs and IBVs are expected to return PLATFORM_SECURITY_ROLE_PLATFORM_REFERENCE
+ // and PLATFORM_SECURITY_ROLE_PLATFORM_IBV respectively.
+ // If the test modules from the designers are unable to fully verify all
+ // security features, then the platform implementers, OEMs and ODMs, will
+ // need to publish this interface with a role of Implementer.
+ //
+ UINT32 Role;
+ //
+ // Human readable vendor, model, & version of this implementation.
+ //
+ CHAR16 ImplementationID[256];
+ //
+ // The size in bytes of the SecurityFeaturesRequired and SecurityFeaturesEnabled arrays.
+ // The arrays must be the same size.
+ //
+ UINT32 SecurityFeaturesSize;
+ //
+ // IHV-defined bitfield corresponding to all security features which must be
+ // implemented to meet the security requirements defined by PLATFORM_SECURITY_VERSION Version.
+ //
+ // UINT8 SecurityFeaturesRequired[]; //Ignored for non-IHV
+ //
+ // Publisher-defined bitfield corresponding to all security features which
+ // have implemented programmatic tests in this module.
+ //
+ // UINT8 SecurityFeaturesImplemented[];
+ //
+ // Publisher-defined bitfield corresponding to all security features which
+ // have been verified implemented by this implementation.
+ //
+ // UINT8 SecurityFeaturesVerified[];
+ //
+ // A Null-terminated string, one failure per line (CR/LF terminated), with a
+ // unique identifier that the OEM/ODM can use to locate the documentation
+ // which will describe the steps to remediate the failure - a URL to the
+ // documentation is recommended.
+ //
+ // CHAR16 ErrorString[];
+} ADAPTER_INFO_PLATFORM_SECURITY;
+
+#pragma pack()
+
+extern EFI_GUID gAdapterInfoPlatformSecurityGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/Http11.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/Http11.h
new file mode 100644
index 0000000000..bb7aaa5a66
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/Http11.h
@@ -0,0 +1,253 @@
+/** @file
+ Hypertext Transfer Protocol -- HTTP/1.1 Standard definitions, from RFC 2616
+
+ This file contains common HTTP 1.1 definitions from RFC 2616
+
+ (C) Copyright 2015-2016 Hewlett Packard Enterprise Development LP
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef __HTTP_11_H__
+#define __HTTP_11_H__
+
+#pragma pack(1)
+
+///
+/// HTTP Version (currently HTTP 1.1)
+///
+/// The version of an HTTP message is indicated by an HTTP-Version field
+/// in the first line of the message.
+///
+#define HTTP_VERSION "HTTP/1.1"
+
+///
+/// HTTP Request Method definitions
+///
+/// The Method token indicates the method to be performed on the
+/// resource identified by the Request-URI. The method is case-sensitive.
+///
+#define HTTP_METHOD_OPTIONS "OPTIONS"
+#define HTTP_METHOD_GET "GET"
+#define HTTP_METHOD_HEAD "HEAD"
+#define HTTP_METHOD_POST "POST"
+#define HTTP_METHOD_PUT "PUT"
+#define HTTP_METHOD_DELETE "DELETE"
+#define HTTP_METHOD_TRACE "TRACE"
+#define HTTP_METHOD_CONNECT "CONNECT"
+#define HTTP_METHOD_PATCH "PATCH"
+
+///
+/// Connect method has maximum length according to EFI_HTTP_METHOD defined in
+/// UEFI2.5 spec so use this.
+///
+#define HTTP_METHOD_MAXIMUM_LEN sizeof (HTTP_METHOD_CONNECT)
+
+///
+/// Accept Request Header
+/// The Accept request-header field can be used to specify certain media types which are
+/// acceptable for the response. Accept headers can be used to indicate that the request
+/// is specifically limited to a small set of desired types, as in the case of a request
+/// for an in-line image.
+///
+#define HTTP_HEADER_ACCEPT "Accept"
+
+///
+/// Accept-Charset Request Header
+/// The Accept-Charset request-header field can be used to indicate what character sets
+/// are acceptable for the response. This field allows clients capable of understanding
+/// more comprehensive or special-purpose character sets to signal that capability to a
+/// server which is capable of representing documents in those character sets.
+///
+#define HTTP_HEADER_ACCEPT_CHARSET "Accept-Charset"
+
+///
+/// Accept-Language Request Header
+/// The Accept-Language request-header field is similar to Accept,
+/// but restricts the set of natural languages that are preferred
+/// as a response to the request.
+///
+#define HTTP_HEADER_ACCEPT_LANGUAGE "Accept-Language"
+
+///
+/// Accept-Ranges Request Header
+/// The Accept-Ranges response-header field allows the server to
+/// indicate its acceptance of range requests for a resource:
+///
+#define HTTP_HEADER_ACCEPT_RANGES "Accept-Ranges"
+
+///
+/// Accept-Encoding Request Header
+/// The Accept-Encoding request-header field is similar to Accept,
+/// but restricts the content-codings that are acceptable in the response.
+///
+#define HTTP_HEADER_ACCEPT_ENCODING "Accept-Encoding"
+
+///
+/// Content-Encoding Header
+/// The Content-Encoding entity-header field is used as a modifier to the media-type.
+/// When present, its value indicates what additional content codings have been applied
+/// to the entity-body, and thus what decoding mechanisms must be applied in order to
+/// obtain the media-type referenced by the Content-Type header field. Content-Encoding
+/// is primarily used to allow a document to be compressed without losing the identity
+/// of its underlying media type.
+///
+#define HTTP_HEADER_CONTENT_ENCODING "Content-Encoding"
+
+///
+/// HTTP Content-Encoding Compression types
+///
+
+#define HTTP_CONTENT_ENCODING_IDENTITY "identity" /// No transformation is used. This is the default value for content coding.
+#define HTTP_CONTENT_ENCODING_GZIP "gzip" /// Content-Encoding: GNU zip format (described in RFC 1952).
+#define HTTP_CONTENT_ENCODING_COMPRESS "compress" /// encoding format produced by the common UNIX file compression program "compress".
+#define HTTP_CONTENT_ENCODING_DEFLATE "deflate" /// The "zlib" format defined in RFC 1950 in combination with the "deflate"
+ /// compression mechanism described in RFC 1951.
+
+///
+/// Content-Type Header
+/// The Content-Type entity-header field indicates the media type of the entity-body sent to
+/// the recipient or, in the case of the HEAD method, the media type that would have been sent
+/// had the request been a GET.
+///
+#define HTTP_HEADER_CONTENT_TYPE "Content-Type"
+//
+// Common Media Types defined in http://www.iana.org/assignments/media-types/media-types.xhtml
+//
+#define HTTP_CONTENT_TYPE_APP_JSON "application/json"
+#define HTTP_CONTENT_TYPE_APP_OCTET_STREAM "application/octet-stream"
+
+#define HTTP_CONTENT_TYPE_TEXT_HTML "text/html"
+#define HTTP_CONTENT_TYPE_TEXT_PLAIN "text/plain"
+#define HTTP_CONTENT_TYPE_TEXT_CSS "text/css"
+#define HTTP_CONTENT_TYPE_TEXT_XML "text/xml"
+
+#define HTTP_CONTENT_TYPE_IMAGE_GIF "image/gif"
+#define HTTP_CONTENT_TYPE_IMAGE_JPEG "image/jpeg"
+#define HTTP_CONTENT_TYPE_IMAGE_PNG "image/png"
+#define HTTP_CONTENT_TYPE_IMAGE_SVG_XML "image/svg+xml"
+
+///
+/// Content-Length Header
+/// The Content-Length entity-header field indicates the size of the entity-body,
+/// in decimal number of OCTETs, sent to the recipient or, in the case of the HEAD
+/// method, the size of the entity-body that would have been sent had the request been a GET.
+///
+#define HTTP_HEADER_CONTENT_LENGTH "Content-Length"
+
+///
+/// Transfer-Encoding Header
+/// The Transfer-Encoding general-header field indicates what (if any) type of transformation
+/// has been applied to the message body in order to safely transfer it between the sender
+/// and the recipient. This differs from the content-coding in that the transfer-coding
+/// is a property of the message, not of the entity.
+///
+#define HTTP_HEADER_TRANSFER_ENCODING "Transfer-Encoding"
+#define HTTP_HEADER_TRANSFER_ENCODING_CHUNKED "chunked"
+#define CHUNKED_TRANSFER_CODING_CR '\r'
+#define CHUNKED_TRANSFER_CODING_LF '\n'
+#define CHUNKED_TRANSFER_CODING_LAST_CHUNK '0'
+#define CHUNKED_TRANSFER_CODING_EXTENSION_SEPARATOR ';'
+
+///
+/// User Agent Request Header
+///
+/// The User-Agent request-header field contains information about the user agent originating
+/// the request. This is for statistical purposes, the tracing of protocol violations, and
+/// automated recognition of user agents for the sake of tailoring responses to avoid
+/// particular user agent limitations. User agents SHOULD include this field with requests.
+/// The field can contain multiple product tokens and comments identifying the agent and any
+/// subproducts which form a significant part of the user agent.
+/// By convention, the product tokens are listed in order of their significance for
+/// identifying the application.
+///
+#define HTTP_HEADER_USER_AGENT "User-Agent"
+
+///
+/// Host Request Header
+///
+/// The Host request-header field specifies the Internet host and port number of the resource
+/// being requested, as obtained from the original URI given by the user or referring resource
+///
+#define HTTP_HEADER_HOST "Host"
+
+///
+/// Location Response Header
+///
+/// The Location response-header field is used to redirect the recipient to a location other than
+/// the Request-URI for completion of the request or identification of a new resource.
+/// For 201 (Created) responses, the Location is that of the new resource which was created by
+/// the request. For 3xx responses, the location SHOULD indicate the server's preferred URI for
+/// automatic redirection to the resource. The field value consists of a single absolute URI.
+///
+#define HTTP_HEADER_LOCATION "Location"
+
+///
+/// The If-Match request-header field is used with a method to make it conditional.
+/// A client that has one or more entities previously obtained from the resource
+/// can verify that one of those entities is current by including a list of their
+/// associated entity tags in the If-Match header field.
+/// The purpose of this feature is to allow efficient updates of cached information
+/// with a minimum amount of transaction overhead. It is also used, on updating requests,
+/// to prevent inadvertent modification of the wrong version of a resource.
+/// As a special case, the value "*" matches any current entity of the resource.
+///
+#define HTTP_HEADER_IF_MATCH "If-Match"
+
+///
+/// The If-None-Match request-header field is used with a method to make it conditional.
+/// A client that has one or more entities previously obtained from the resource can verify
+/// that none of those entities is current by including a list of their associated entity
+/// tags in the If-None-Match header field. The purpose of this feature is to allow efficient
+/// updates of cached information with a minimum amount of transaction overhead. It is also used
+/// to prevent a method (e.g. PUT) from inadvertently modifying an existing resource when the
+/// client believes that the resource does not exist.
+///
+#define HTTP_HEADER_IF_NONE_MATCH "If-None-Match"
+
+///
+/// The WWW-Authenticate Response Header
+/// If a server receives a request for an access-protected object, and an
+/// acceptable Authorization header is not sent, the server responds with
+/// a "401 Unauthorized" status code, and a WWW-Authenticate header.
+///
+#define HTTP_HEADER_WWW_AUTHENTICATE "WWW-Authenticate"
+
+///
+/// Authorization Request Header
+/// The Authorization field value consists of credentials
+/// containing the authentication information of the user agent for
+/// the realm of the resource being requested.
+///
+#define HTTP_HEADER_AUTHORIZATION "Authorization"
+
+///
+/// ETAG Response Header
+/// The ETag response-header field provides the current value of the entity tag
+/// for the requested variant.
+///
+#define HTTP_HEADER_ETAG "ETag"
+
+///
+/// Custom header field checked by the iLO web server to
+/// specify a client session key.
+/// Example: X-Auth-Token: 24de6b1f8fa147ad59f6452def628798
+///
+#define HTTP_HEADER_X_AUTH_TOKEN "X-Auth-Token"
+
+///
+/// Expect Header
+/// The "Expect" header field in a request indicates a certain set of
+/// behaviors (expectations) that need to be supported by the server in
+/// order to properly handle this request. The only such expectation
+/// defined by this specification is 100-continue.
+///
+#define HTTP_HEADER_EXPECT "Expect"
+
+///
+/// Expect Header Value
+///
+#define HTTP_EXPECT_100_CONTINUE "100-continue"
+
+#pragma pack()
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/IScsiBootFirmwareTable.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/IScsiBootFirmwareTable.h
new file mode 100644
index 0000000000..c3a44b6ca1
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/IScsiBootFirmwareTable.h
@@ -0,0 +1,160 @@
+/** @file
+ The definition for iSCSI Boot Firmware Table, it's defined in Microsoft's
+ iSCSI Boot Firmware Table(iBFT) as Defined in ACPI 3.0b Specification.
+
+ Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _ISCSI_BOOT_FIRMWARE_TABLE_H_
+#define _ISCSI_BOOT_FIRMWARE_TABLE_H_
+
+#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_REVISION 0x01
+#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_STRUCTURE_ALIGNMENT 8
+
+///
+/// Structure Type/ID
+///
+#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_RESERVED_STRUCTURE_ID 0
+#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_CONTROL_STRUCTURE_ID 1
+#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_INITIATOR_STRUCTURE_ID 2
+#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_NIC_STRUCTURE_ID 3
+#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_TARGET_STRUCTURE_ID 4
+#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_EXTERNSIONS_STRUCTURE_ID 5
+
+///
+/// from the definition of IP_PREFIX_ORIGIN Enumeration in MSDN,
+/// not defined in Microsoft iBFT document.
+///
+typedef enum {
+ IpPrefixOriginOther = 0,
+ IpPrefixOriginManual,
+ IpPrefixOriginWellKnown,
+ IpPrefixOriginDhcp,
+ IpPrefixOriginRouterAdvertisement,
+ IpPrefixOriginUnchanged = 16
+} IP_PREFIX_VALUE;
+
+#pragma pack(1)
+
+///
+/// iBF Table Header
+///
+typedef struct {
+ UINT32 Signature;
+ UINT32 Length;
+ UINT8 Revision;
+ UINT8 Checksum;
+ UINT8 OemId[6];
+ UINT64 OemTableId;
+ UINT8 Reserved[24];
+} EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_HEADER;
+
+///
+/// Common Header of Boot Firmware Table Structure
+///
+typedef struct {
+ UINT8 StructureId;
+ UINT8 Version;
+ UINT16 Length;
+ UINT8 Index;
+ UINT8 Flags;
+} EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_STRUCTURE_HEADER;
+
+///
+/// Control Structure
+///
+typedef struct {
+ EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_STRUCTURE_HEADER Header;
+ UINT16 Extensions;
+ UINT16 InitiatorOffset;
+ UINT16 NIC0Offset;
+ UINT16 Target0Offset;
+ UINT16 NIC1Offset;
+ UINT16 Target1Offset;
+} EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_CONTROL_STRUCTURE;
+
+#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_CONTROL_STRUCTURE_VERSION 0x1
+
+#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_CONTROL_STRUCTURE_FLAG_BOOT_FAILOVER BIT0
+
+///
+/// Initiator Structure
+///
+typedef struct {
+ EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_STRUCTURE_HEADER Header;
+ EFI_IPv6_ADDRESS ISnsServer;
+ EFI_IPv6_ADDRESS SlpServer;
+ EFI_IPv6_ADDRESS PrimaryRadiusServer;
+ EFI_IPv6_ADDRESS SecondaryRadiusServer;
+ UINT16 IScsiNameLength;
+ UINT16 IScsiNameOffset;
+} EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_INITIATOR_STRUCTURE;
+
+#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_INITIATOR_STRUCTURE_VERSION 0x1
+
+#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_INITIATOR_STRUCTURE_FLAG_BLOCK_VALID BIT0
+#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_INITIATOR_STRUCTURE_FLAG_BOOT_SELECTED BIT1
+
+///
+/// NIC Structure
+///
+typedef struct {
+ EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_STRUCTURE_HEADER Header;
+ EFI_IPv6_ADDRESS Ip;
+ UINT8 SubnetMaskPrefixLength;
+ UINT8 Origin;
+ EFI_IPv6_ADDRESS Gateway;
+ EFI_IPv6_ADDRESS PrimaryDns;
+ EFI_IPv6_ADDRESS SecondaryDns;
+ EFI_IPv6_ADDRESS DhcpServer;
+ UINT16 VLanTag;
+ UINT8 Mac[6];
+ UINT16 PciLocation;
+ UINT16 HostNameLength;
+ UINT16 HostNameOffset;
+} EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_NIC_STRUCTURE;
+
+#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_NIC_STRUCTURE_VERSION 0x1
+
+#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_NIC_STRUCTURE_FLAG_BLOCK_VALID BIT0
+#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_NIC_STRUCTURE_FLAG_BOOT_SELECTED BIT1
+#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_NIC_STRUCTURE_FLAG_GLOBAL BIT2
+
+///
+/// Target Structure
+///
+typedef struct {
+ EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_STRUCTURE_HEADER Header;
+ EFI_IPv6_ADDRESS Ip;
+ UINT16 Port;
+ UINT8 BootLun[8];
+ UINT8 CHAPType;
+ UINT8 NicIndex;
+ UINT16 IScsiNameLength;
+ UINT16 IScsiNameOffset;
+ UINT16 CHAPNameLength;
+ UINT16 CHAPNameOffset;
+ UINT16 CHAPSecretLength;
+ UINT16 CHAPSecretOffset;
+ UINT16 ReverseCHAPNameLength;
+ UINT16 ReverseCHAPNameOffset;
+ UINT16 ReverseCHAPSecretLength;
+ UINT16 ReverseCHAPSecretOffset;
+} EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_TARGET_STRUCTURE;
+
+#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_TARGET_STRUCTURE_VERSION 0x1
+
+#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_TARGET_STRUCTURE_FLAG_BLOCK_VALID BIT0
+#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_TARGET_STRUCTURE_FLAG_BOOT_SELECTED BIT1
+#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_TARGET_STRUCTURE_FLAG_RADIUS_CHAP BIT2
+#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_TARGET_STRUCTURE_FLAG_RADIUS_RCHAP BIT3
+
+#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_TARGET_STRUCTURE_CHAP_TYPE_NO_CHAP 0
+#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_TARGET_STRUCTURE_CHAP_TYPE_CHAP 1
+#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_TARGET_STRUCTURE_CHAP_TYPE_MUTUAL_CHAP 2
+
+#pragma pack()
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/IoRemappingTable.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/IoRemappingTable.h
new file mode 100644
index 0000000000..f5f924c2d3
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/IoRemappingTable.h
@@ -0,0 +1,277 @@
+/** @file
+ ACPI IO Remapping Table (IORT) definitions.
+
+ Copyright (c) 2017, Linaro Limited. All rights reserved.
+ Copyright (c) 2018 - 2022, Arm Limited. All rights reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Reference(s):
+ - IO Remapping Table, Platform Design Document, Revision E.d, Feb 2022
+ (https://developer.arm.com/documentation/den0049/)
+ - IO Remapping Table, Platform Design Document, Revision E.e, Sept 2022
+ (https://developer.arm.com/documentation/den0049/)
+
+ @par Glossary:
+ - Ref : Reference
+ - Mem : Memory
+ - Desc : Descriptor
+**/
+
+#ifndef __IO_REMAPPING_TABLE_H__
+#define __IO_REMAPPING_TABLE_H__
+
+#include
+
+#define EFI_ACPI_IO_REMAPPING_TABLE_REVISION_00 0x0
+#define EFI_ACPI_IO_REMAPPING_TABLE_REVISION_04 0x4 // Deprecated
+#define EFI_ACPI_IO_REMAPPING_TABLE_REVISION_05 0x5
+#define EFI_ACPI_IO_REMAPPING_TABLE_REVISION_06 0x6
+
+#define EFI_ACPI_IORT_TYPE_ITS_GROUP 0x0
+#define EFI_ACPI_IORT_TYPE_NAMED_COMP 0x1
+#define EFI_ACPI_IORT_TYPE_ROOT_COMPLEX 0x2
+#define EFI_ACPI_IORT_TYPE_SMMUv1v2 0x3
+#define EFI_ACPI_IORT_TYPE_SMMUv3 0x4
+#define EFI_ACPI_IORT_TYPE_PMCG 0x5
+#define EFI_ACPI_IORT_TYPE_RMR 0x6
+
+#define EFI_ACPI_IORT_MEM_ACCESS_PROP_CCA BIT0
+
+#define EFI_ACPI_IORT_MEM_ACCESS_PROP_AH_TR BIT0
+#define EFI_ACPI_IORT_MEM_ACCESS_PROP_AH_WA BIT1
+#define EFI_ACPI_IORT_MEM_ACCESS_PROP_AH_RA BIT2
+#define EFI_ACPI_IORT_MEM_ACCESS_PROP_AH_AHO BIT3
+
+#define EFI_ACPI_IORT_MEM_ACCESS_FLAGS_CPM BIT0
+#define EFI_ACPI_IORT_MEM_ACCESS_FLAGS_DACS BIT1
+
+#define EFI_ACPI_IORT_SMMUv1v2_MODEL_v1 0x0
+#define EFI_ACPI_IORT_SMMUv1v2_MODEL_v2 0x1
+#define EFI_ACPI_IORT_SMMUv1v2_MODEL_MMU400 0x2
+#define EFI_ACPI_IORT_SMMUv1v2_MODEL_MMU500 0x3
+#define EFI_ACPI_IORT_SMMUv1v2_MODEL_MMU401 0x4
+#define EFI_ACPI_IORT_SMMUv1v2_MODEL_CAVIUM_THX_v2 0x5
+
+#define EFI_ACPI_IORT_SMMUv1v2_FLAG_DVM BIT0
+#define EFI_ACPI_IORT_SMMUv1v2_FLAG_COH_WALK BIT1
+
+#define EFI_ACPI_IORT_SMMUv1v2_INT_FLAG_LEVEL 0x0
+#define EFI_ACPI_IORT_SMMUv1v2_INT_FLAG_EDGE 0x1
+
+#define EFI_ACPI_IORT_SMMUv3_FLAG_COHAC_OVERRIDE BIT0
+#define EFI_ACPI_IORT_SMMUv3_FLAG_HTTU_OVERRIDE BIT1
+#define EFI_ACPI_IORT_SMMUv3_FLAG_PROXIMITY_DOMAIN BIT3
+#define EFI_ACPI_IORT_SMMUv3_FLAG_DEVICEID_VALID BIT4
+
+#define EFI_ACPI_IORT_SMMUv3_MODEL_GENERIC 0x0
+#define EFI_ACPI_IORT_SMMUv3_MODEL_HISILICON_HI161X 0x1
+#define EFI_ACPI_IORT_SMMUv3_MODEL_CAVIUM_CN99XX 0x2
+
+#define EFI_ACPI_IORT_ROOT_COMPLEX_ATS_UNSUPPORTED 0x0
+#define EFI_ACPI_IORT_ROOT_COMPLEX_ATS_SUPPORTED BIT0
+
+#define EFI_ACPI_IORT_ROOT_COMPLEX_PRI_UNSUPPORTED 0x0
+#define EFI_ACPI_IORT_ROOT_COMPLEX_PRI_SUPPORTED BIT1
+
+#define EFI_ACPI_IORT_ROOT_COMPLEX_PASID_FWD_UNSUPPORTED 0x0
+#define EFI_ACPI_IORT_ROOT_COMPLEX_PASID_FWD_SUPPORTED BIT2
+
+#define EFI_ACPI_IORT_ROOT_COMPLEX_PASID_UNSUPPORTED 0x0
+#define EFI_ACPI_IORT_ROOT_COMPLEX_PASID_SUPPORTED BIT1
+
+#define EFI_ACPI_IORT_RMR_REMAP_NOT_PERMITTED 0x0
+#define EFI_ACPI_IORT_RMR_REMAP_PERMITTED BIT0
+
+#define EFI_ACPI_IORT_RMR_ACCESS_REQ_NOT_PRIVILEGED 0x0
+#define EFI_ACPI_IORT_RMR_ACCESS_REQ_PRIVILEGED BIT1
+
+#define EFI_ACPI_IORT_RMR_ACCESS_ATTRIB_DEV_NGNRNE 0x0
+#define EFI_ACPI_IORT_RMR_ACCESS_ATTRIB_DEV_NGNRE 0x1
+#define EFI_ACPI_IORT_RMR_ACCESS_ATTRIB_DEV_NGRE 0x2
+#define EFI_ACPI_IORT_RMR_ACCESS_ATTRIB_DEV_GRE 0x3
+#define EFI_ACPI_IORT_RMR_ACCESS_ATTRIB_NORM_IN_NC_OUT_NC 0x4
+#define EFI_ACPI_IORT_RMR_ACCESS_ATTRIB_NORM_IN_WB_OUT_WB_ISH 0x5
+
+#define EFI_ACPI_IORT_ID_MAPPING_FLAGS_SINGLE BIT0
+
+#define EFI_ACPI_IORT_RMR_NODE_REVISION_02 0x2 // Deprecated
+
+#pragma pack(1)
+
+///
+/// Table header
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 NumNodes;
+ UINT32 NodeOffset;
+ UINT32 Reserved;
+} EFI_ACPI_6_0_IO_REMAPPING_TABLE;
+
+///
+/// Definition for ID mapping table shared by all node types
+///
+typedef struct {
+ UINT32 InputBase;
+ UINT32 NumIds;
+ UINT32 OutputBase;
+ UINT32 OutputReference;
+ UINT32 Flags;
+} EFI_ACPI_6_0_IO_REMAPPING_ID_TABLE;
+
+///
+/// Node header definition shared by all node types
+///
+typedef struct {
+ UINT8 Type;
+ UINT16 Length;
+ UINT8 Revision;
+ UINT32 Identifier;
+ UINT32 NumIdMappings;
+ UINT32 IdReference;
+} EFI_ACPI_6_0_IO_REMAPPING_NODE;
+
+///
+/// Node type 0: ITS node
+///
+typedef struct {
+ EFI_ACPI_6_0_IO_REMAPPING_NODE Node;
+
+ UINT32 NumItsIdentifiers;
+ // UINT32 ItsIdentifiers[NumItsIdentifiers];
+} EFI_ACPI_6_0_IO_REMAPPING_ITS_NODE;
+
+///
+/// Node type 1: root complex node
+///
+typedef struct {
+ EFI_ACPI_6_0_IO_REMAPPING_NODE Node;
+
+ UINT32 CacheCoherent;
+ UINT8 AllocationHints;
+ UINT16 Reserved;
+ UINT8 MemoryAccessFlags;
+
+ UINT32 AtsAttribute;
+ UINT32 PciSegmentNumber;
+ UINT8 MemoryAddressSize;
+ UINT16 PasidCapabilities;
+ UINT8 Reserved1[1];
+ UINT32 Flags;
+} EFI_ACPI_6_0_IO_REMAPPING_RC_NODE;
+
+///
+/// Node type 2: named component node
+///
+typedef struct {
+ EFI_ACPI_6_0_IO_REMAPPING_NODE Node;
+
+ UINT32 Flags;
+ UINT32 CacheCoherent;
+ UINT8 AllocationHints;
+ UINT16 Reserved;
+ UINT8 MemoryAccessFlags;
+ UINT8 AddressSizeLimit;
+ // UINT8 ObjectName[];
+} EFI_ACPI_6_0_IO_REMAPPING_NAMED_COMP_NODE;
+
+///
+/// Node type 3: SMMUv1 or SMMUv2 node
+///
+typedef struct {
+ UINT32 Interrupt;
+ UINT32 InterruptFlags;
+} EFI_ACPI_6_0_IO_REMAPPING_SMMU_INT;
+
+typedef struct {
+ EFI_ACPI_6_0_IO_REMAPPING_NODE Node;
+
+ UINT64 Base;
+ UINT64 Span;
+ UINT32 Model;
+ UINT32 Flags;
+ UINT32 GlobalInterruptArrayRef;
+ UINT32 NumContextInterrupts;
+ UINT32 ContextInterruptArrayRef;
+ UINT32 NumPmuInterrupts;
+ UINT32 PmuInterruptArrayRef;
+
+ UINT32 SMMU_NSgIrpt;
+ UINT32 SMMU_NSgIrptFlags;
+ UINT32 SMMU_NSgCfgIrpt;
+ UINT32 SMMU_NSgCfgIrptFlags;
+
+ // EFI_ACPI_6_0_IO_REMAPPING_SMMU_CTX_INT ContextInterrupt[NumContextInterrupts];
+ // EFI_ACPI_6_0_IO_REMAPPING_SMMU_CTX_INT PmuInterrupt[NumPmuInterrupts];
+} EFI_ACPI_6_0_IO_REMAPPING_SMMU_NODE;
+
+///
+/// Node type 4: SMMUv3 node
+///
+typedef struct {
+ EFI_ACPI_6_0_IO_REMAPPING_NODE Node;
+
+ UINT64 Base;
+ UINT32 Flags;
+ UINT32 Reserved;
+ UINT64 VatosAddress;
+ UINT32 Model;
+ UINT32 Event;
+ UINT32 Pri;
+ UINT32 Gerr;
+ UINT32 Sync;
+ UINT32 ProximityDomain;
+ UINT32 DeviceIdMappingIndex;
+} EFI_ACPI_6_0_IO_REMAPPING_SMMU3_NODE;
+
+///
+/// Node type 5: PMCG node
+///
+typedef struct {
+ EFI_ACPI_6_0_IO_REMAPPING_NODE Node;
+
+ UINT64 Base;
+ UINT32 OverflowInterruptGsiv;
+ UINT32 NodeReference;
+ UINT64 Page1Base;
+ // EFI_ACPI_6_0_IO_REMAPPING_ID_TABLE OverflowInterruptMsiMapping[1];
+} EFI_ACPI_6_0_IO_REMAPPING_PMCG_NODE;
+
+///
+/// Memory Range Descriptor.
+///
+typedef struct {
+ /// Base address of Reserved Memory Range,
+ /// aligned to a page size of 64K.
+ UINT64 Base;
+
+ /// Length of the Reserved Memory range.
+ /// Must be a multiple of the page size of 64K.
+ UINT64 Length;
+
+ /// Reserved, must be zero.
+ UINT32 Reserved;
+} EFI_ACPI_6_0_IO_REMAPPING_MEM_RANGE_DESC;
+
+///
+/// Node type 6: Reserved Memory Range (RMR) node
+///
+typedef struct {
+ EFI_ACPI_6_0_IO_REMAPPING_NODE Node;
+
+ /// RMR flags
+ UINT32 Flags;
+
+ /// Memory range descriptor count.
+ UINT32 NumMemRangeDesc;
+
+ /// Offset of the memory range descriptor array.
+ UINT32 MemRangeDescRef;
+ // EFI_ACPI_6_0_IO_REMAPPING_ID_TABLE IdMapping[1];
+ // EFI_ACPI_6_0_IO_REMAPPING_MEM_RANGE_DESC MemRangeDesc[1];
+} EFI_ACPI_6_0_IO_REMAPPING_RMR_NODE;
+
+#pragma pack()
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/Ipmi.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/Ipmi.h
new file mode 100644
index 0000000000..0a16ad639d
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/Ipmi.h
@@ -0,0 +1,72 @@
+/** @file
+ IPMI 2.0 definitions from the IPMI Specification Version 2.0, Revision 1.1.
+ IPMI Platform Management FRU Information Storage Definition v1.0 Revision 1.3.
+
+ See IPMI specification, Appendix G, Command Assignments
+ and Appendix H, Sub-function Assignments.
+
+ Copyright (c) 1999 - 2018, Intel Corporation. All rights reserved.
+ Copyright (C) 2023 Advanced Micro Devices, Inc. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _IPMI_H_
+#define _IPMI_H_
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+
+//
+// Generic Completion Codes definitions
+//
+#define IPMI_COMP_CODE_NORMAL 0x00
+#define IPMI_COMP_CODE_NODE_BUSY 0xC0
+#define IPMI_COMP_CODE_INVALID_COMMAND 0xC1
+#define IPMI_COMP_CODE_INVALID_FOR_GIVEN_LUN 0xC2
+#define IPMI_COMP_CODE_TIMEOUT 0xC3
+#define IPMI_COMP_CODE_OUT_OF_SPACE 0xC4
+#define IPMI_COMP_CODE_RESERVATION_CANCELED_OR_INVALID 0xC5
+#define IPMI_COMP_CODE_REQUEST_DATA_TRUNCATED 0xC6
+#define IPMI_COMP_CODE_INVALID_REQUEST_DATA_LENGTH 0xC7
+#define IPMI_COMP_CODE_REQUEST_EXCEED_LIMIT 0xC8
+#define IPMI_COMP_CODE_OUT_OF_RANGE 0xC9
+#define IPMI_COMP_CODE_CANNOT_RETURN 0xCA
+#define IPMI_COMP_CODE_NOT_PRESENT 0xCB
+#define IPMI_COMP_CODE_INVALID_DATA_FIELD 0xCC
+#define IPMI_COMP_CODE_COMMAND_ILLEGAL 0xCD
+#define IPMI_COMP_CODE_CMD_RESP_NOT_PROVIDED 0xCE
+#define IPMI_COMP_CODE_FAIL_DUP_REQUEST 0xCF
+#define IPMI_COMP_CODE_SDR_REP_IN_UPDATE_MODE 0xD0
+#define IPMI_COMP_CODE_DEV_IN_FW_UPDATE_MODE 0xD1
+#define IPMI_COMP_CODE_BMC_INIT_IN_PROGRESS 0xD2
+#define IPMI_COMP_CODE_DEST_UNAVAILABLE 0xD3
+#define IPMI_COMP_CODE_INSUFFICIENT_PRIVILEGE 0xD4
+#define IPMI_COMP_CODE_UNSUPPORTED_IN_PRESENT_STATE 0xD5
+#define IPMI_COMP_CODE_SUBFUNCTION_DISABLED 0xD6
+#define IPMI_COMP_CODE_UNSPECIFIED 0xFF
+
+#define IPMI_CHANNEL_NUMBER_PRIMARY_IPMB 0x00
+#define IPMI_CHANNEL_NUMBER_IMPLEMENTATION_SPECIFIC_1 0x01
+#define IPMI_CHANNEL_NUMBER_IMPLEMENTATION_SPECIFIC_2 0x02
+#define IPMI_CHANNEL_NUMBER_IMPLEMENTATION_SPECIFIC_3 0x03
+#define IPMI_CHANNEL_NUMBER_IMPLEMENTATION_SPECIFIC_4 0x04
+#define IPMI_CHANNEL_NUMBER_IMPLEMENTATION_SPECIFIC_5 0x05
+#define IPMI_CHANNEL_NUMBER_IMPLEMENTATION_SPECIFIC_6 0x06
+#define IPMI_CHANNEL_NUMBER_IMPLEMENTATION_SPECIFIC_7 0x07
+#define IPMI_CHANNEL_NUMBER_IMPLEMENTATION_SPECIFIC_8 0x08
+#define IPMI_CHANNEL_NUMBER_IMPLEMENTATION_SPECIFIC_9 0x09
+#define IPMI_CHANNEL_NUMBER_IMPLEMENTATION_SPECIFIC_10 0x0A
+#define IPMI_CHANNEL_NUMBER_IMPLEMENTATION_SPECIFIC_11 0x0B
+#define IPMI_CHANNEL_NUMBER_IMPLEMENTATION_RESERVED_12 0x0C
+#define IPMI_CHANNEL_NUMBER_IMPLEMENTATION_RESERVED_13 0x0D
+#define IPMI_CHANNEL_NUMBER_PRIMARY_PRESENT_IF 0x0E
+#define IPMI_CHANNEL_NUMBER_PRIMARY_SYSTEM_INTERFACE 0x0F
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/IpmiFruInformationStorage.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/IpmiFruInformationStorage.h
new file mode 100644
index 0000000000..d317045095
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/IpmiFruInformationStorage.h
@@ -0,0 +1,86 @@
+/** @file
+ IPMI Platform Management FRU Information Storage Definitions
+
+ This file contains the definitions for:
+ Common Header Format (Chapter 8)
+ MultiRecord Header (Section 16.1)
+
+ Copyright (c) 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Revision Reference:
+ - IPMI Platform Management FRU Information Storage Definition v1.0 Revision
+ 1.3, Dated March 24, 2015.
+ https://www.intel.com/content/dam/www/public/us/en/documents/specification-updates/ipmi-platform-mgt-fru-info-storage-def-v1-0-rev-1-3-spec-update.pdf
+**/
+
+#ifndef _IPMI_FRU_INFORMATION_STORAGE_H_
+#define _IPMI_FRU_INFORMATION_STORAGE_H_
+
+#pragma pack(1)
+
+//
+// Structure definitions for FRU Common Header
+//
+typedef union {
+ ///
+ /// Individual bit fields
+ ///
+ struct {
+ UINT8 FormatVersionNumber : 4;
+ UINT8 Reserved : 4;
+ } Bits;
+ ///
+ /// All bit fields as a 8-bit value
+ ///
+ UINT8 Uint8;
+} IPMI_FRU_COMMON_HEADER_FORMAT_VERSION;
+
+typedef struct {
+ IPMI_FRU_COMMON_HEADER_FORMAT_VERSION FormatVersion;
+ UINT8 InternalUseStartingOffset;
+ UINT8 ChassisInfoStartingOffset;
+ UINT8 BoardAreaStartingOffset;
+ UINT8 ProductInfoStartingOffset;
+ UINT8 MultiRecInfoStartingOffset;
+ UINT8 Pad;
+ UINT8 Checksum;
+} IPMI_FRU_COMMON_HEADER;
+
+//
+// Structure definition for FRU MultiRecord Header
+//
+typedef union {
+ ///
+ /// Individual bit fields
+ ///
+ struct {
+ UINT8 RecordFormatVersion : 4;
+ UINT8 Reserved : 3;
+ UINT8 EndofList : 1;
+ } Bits;
+ ///
+ /// All bit fields as a 8-bit value
+ ///
+ UINT8 Uint8;
+} IPMI_FRU_MULTI_RECORD_HEADER_FORMAT_VERSION;
+
+typedef struct {
+ UINT8 RecordTypeId;
+ IPMI_FRU_MULTI_RECORD_HEADER_FORMAT_VERSION FormatVersion;
+ UINT8 RecordLength;
+ UINT8 RecordChecksum;
+ UINT8 HeaderChecksum;
+} IPMI_FRU_MULTI_RECORD_HEADER;
+
+//
+// Structure definition for System UUID Subrecord with checksum.
+//
+typedef struct {
+ UINT8 RecordCheckSum;
+ UINT8 SubRecordId;
+ EFI_GUID Uuid;
+} IPMI_SYSTEM_UUID_SUB_RECORD_WITH_CHECKSUM;
+
+#pragma pack()
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/IpmiNetFnApp.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/IpmiNetFnApp.h
new file mode 100644
index 0000000000..eb9addbd08
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/IpmiNetFnApp.h
@@ -0,0 +1,1057 @@
+/** @file
+ IPMI 2.0 definitions from the IPMI Specification Version 2.0, Revision 1.1.
+
+ This file contains all NetFn App commands, including:
+ IPM Device "Global" Commands (Chapter 20)
+ Firmware Firewall & Command Discovery Commands (Chapter 21)
+ BMC Watchdog Timer Commands (Chapter 27)
+ IPMI Messaging Support Commands (Chapter 22)
+ RMCP+ Support and Payload Commands (Chapter 24)
+
+ See IPMI specification, Appendix G, Command Assignments
+ and Appendix H, Sub-function Assignments.
+
+ Copyright (c) 1999 - 2018, Intel Corporation. All rights reserved.
+ Copyright (C) 2023 Advanced Micro Devices, Inc. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _IPMI_NET_FN_APP_H_
+#define _IPMI_NET_FN_APP_H_
+
+#pragma pack(1)
+//
+// Net function definition for App command
+//
+#define IPMI_NETFN_APP 0x06
+
+//
+// Below is Definitions for IPM Device "Global" Commands (Chapter 20)
+//
+
+//
+// Definitions for Get Device ID command
+//
+#define IPMI_APP_GET_DEVICE_ID 0x1
+
+//
+// Constants and Structure definitions for "Get Device ID" command to follow here
+//
+typedef union {
+ struct {
+ UINT8 DeviceRevision : 4;
+ UINT8 Reserved : 3;
+ UINT8 DeviceSdr : 1;
+ } Bits;
+ UINT8 Uint8;
+} IPMI_GET_DEVICE_ID_DEVICE_REV;
+
+typedef union {
+ struct {
+ UINT8 MajorFirmwareRev : 7;
+ UINT8 UpdateMode : 1;
+ } Bits;
+ UINT8 Uint8;
+} IPMI_GET_DEVICE_ID_FIRMWARE_REV_1;
+
+typedef union {
+ struct {
+ UINT8 SensorDeviceSupport : 1;
+ UINT8 SdrRepositorySupport : 1;
+ UINT8 SelDeviceSupport : 1;
+ UINT8 FruInventorySupport : 1;
+ UINT8 IpmbMessageReceiver : 1;
+ UINT8 IpmbMessageGenerator : 1;
+ UINT8 BridgeSupport : 1;
+ UINT8 ChassisSupport : 1;
+ } Bits;
+ UINT8 Uint8;
+} IPMI_GET_DEVICE_ID_DEVICE_SUPPORT;
+
+typedef struct {
+ UINT8 CompletionCode;
+ UINT8 DeviceId;
+ IPMI_GET_DEVICE_ID_DEVICE_REV DeviceRevision;
+ IPMI_GET_DEVICE_ID_FIRMWARE_REV_1 FirmwareRev1;
+ UINT8 MinorFirmwareRev;
+ UINT8 SpecificationVersion;
+ IPMI_GET_DEVICE_ID_DEVICE_SUPPORT DeviceSupport;
+ UINT8 ManufacturerId[3];
+ UINT16 ProductId;
+ UINT32 AuxFirmwareRevInfo;
+} IPMI_GET_DEVICE_ID_RESPONSE;
+
+//
+// Definitions for Cold Reset command
+//
+#define IPMI_APP_COLD_RESET 0x2
+
+//
+// Constants and Structure definitions for "Cold Reset" command to follow here
+//
+
+//
+// Definitions for Warm Reset command
+//
+#define IPMI_APP_WARM_RESET 0x3
+
+//
+// Constants and Structure definitions for "Warm Reset" command to follow here
+//
+
+//
+// Definitions for Get Self Results command
+//
+#define IPMI_APP_GET_SELFTEST_RESULTS 0x4
+
+//
+// Constants and Structure definitions for "Get Self Test Results" command to follow here
+//
+typedef struct {
+ UINT8 CompletionCode;
+ UINT8 Result;
+ UINT8 Param;
+} IPMI_SELF_TEST_RESULT_RESPONSE;
+
+#define IPMI_APP_SELFTEST_NO_ERROR 0x55
+#define IPMI_APP_SELFTEST_NOT_IMPLEMENTED 0x56
+#define IPMI_APP_SELFTEST_ERROR 0x57
+#define IPMI_APP_SELFTEST_FATAL_HW_ERROR 0x58
+#define IPMI_APP_SELFTEST_INACCESSIBLE_SEL 0x80
+#define IPMI_APP_SELFTEST_INACCESSIBLE_SDR 0x40
+#define IPMI_APP_SELFTEST_INACCESSIBLE_FRU 0x20
+#define IPMI_APP_SELFTEST_IPMB_SIGNAL_FAIL 0x10
+#define IPMI_APP_SELFTEST_SDR_REPOSITORY_EMPTY 0x08
+#define IPMI_APP_SELFTEST_FRU_CORRUPT 0x04
+#define IPMI_APP_SELFTEST_FW_BOOTBLOCK_CORRUPT 0x02
+#define IPMI_APP_SELFTEST_FW_CORRUPT 0x01
+
+//
+// Definitions for Manufacturing Test ON command
+//
+#define IPMI_APP_MANUFACTURING_TEST_ON 0x5
+
+//
+// Constants and Structure definitions for "Manufacturing Test ON" command to follow here
+//
+
+//
+// Definitions for Set ACPI Power State command
+//
+#define IPMI_APP_SET_ACPI_POWERSTATE 0x6
+
+//
+// Constants and Structure definitions for "Set ACPI Power State" command to follow here
+//
+
+//
+// Definitions for System Power State
+//
+// Working
+#define IPMI_SYSTEM_POWER_STATE_S0_G0 0x0
+#define IPMI_SYSTEM_POWER_STATE_S1 0x1
+#define IPMI_SYSTEM_POWER_STATE_S2 0x2
+#define IPMI_SYSTEM_POWER_STATE_S3 0x3
+#define IPMI_SYSTEM_POWER_STATE_S4 0x4
+// Soft off
+#define IPMI_SYSTEM_POWER_STATE_S5_G2 0x5
+// Sent when message source cannot differentiate between S4 and S5
+#define IPMI_SYSTEM_POWER_STATE_S4_S5 0x6
+// Mechanical off
+#define IPMI_SYSTEM_POWER_STATE_G3 0x7
+// Sleeping - cannot differentiate between S1-S3
+#define IPMI_SYSTEM_POWER_STATE_SLEEPING 0x8
+// Sleeping - cannot differentiate between S1-S4
+#define IPMI_SYSTEM_POWER_STATE_G1_SLEEPING 0x9
+// S5 entered by override
+#define IPMI_SYSTEM_POWER_STATE_OVERRIDE 0xA
+#define IPMI_SYSTEM_POWER_STATE_LEGACY_ON 0x20
+#define IPMI_SYSTEM_POWER_STATE_LEGACY_OFF 0x21
+#define IPMI_SYSTEM_POWER_STATE_UNKNOWN 0x2A
+#define IPMI_SYSTEM_POWER_STATE_NO_CHANGE 0x7F
+
+//
+// Definitions for Device Power State
+//
+#define IPMI_DEVICE_POWER_STATE_D0 0x0
+#define IPMI_DEVICE_POWER_STATE_D1 0x1
+#define IPMI_DEVICE_POWER_STATE_D2 0x2
+#define IPMI_DEVICE_POWER_STATE_D3 0x3
+#define IPMI_DEVICE_POWER_STATE_UNKNOWN 0x2A
+#define IPMI_DEVICE_POWER_STATE_NO_CHANGE 0x7F
+
+typedef union {
+ struct {
+ UINT8 PowerState : 7;
+ UINT8 StateChange : 1;
+ } Bits;
+ UINT8 Uint8;
+} IPMI_ACPI_POWER_STATE;
+
+typedef struct {
+ IPMI_ACPI_POWER_STATE SystemPowerState;
+ IPMI_ACPI_POWER_STATE DevicePowerState;
+} IPMI_SET_ACPI_POWER_STATE_REQUEST;
+
+//
+// Definitions for Get ACPI Power State command
+//
+#define IPMI_APP_GET_ACPI_POWERSTATE 0x7
+
+//
+// Constants and Structure definitions for "Get ACPI Power State" command to follow here
+//
+
+//
+// Definitions for Get Device GUID command
+//
+#define IPMI_APP_GET_DEVICE_GUID 0x8
+
+//
+// Constants and Structure definitions for "Get Device GUID" command to follow here
+//
+//
+// Message structure definition for "Get Device Guid" IPMI command
+//
+typedef struct {
+ UINT8 CompletionCode;
+ UINT8 Guid[16];
+} IPMI_GET_DEVICE_GUID_RESPONSE;
+
+//
+// Below is Definitions for BMC Watchdog Timer Commands (Chapter 27)
+//
+
+//
+// Definitions for Reset WatchDog Timer command
+//
+#define IPMI_APP_RESET_WATCHDOG_TIMER 0x22
+
+//
+// Definitions for Set WatchDog Timer command
+//
+#define IPMI_APP_SET_WATCHDOG_TIMER 0x24
+
+//
+// Constants and Structure definitions for "Set WatchDog Timer" command to follow here
+//
+
+//
+// Definitions for watchdog timer use
+//
+#define IPMI_WATCHDOG_TIMER_BIOS_FRB2 0x1
+#define IPMI_WATCHDOG_TIMER_BIOS_POST 0x2
+#define IPMI_WATCHDOG_TIMER_OS_LOADER 0x3
+#define IPMI_WATCHDOG_TIMER_SMS 0x4
+#define IPMI_WATCHDOG_TIMER_OEM 0x5
+
+//
+// Structure definition for timer Use
+//
+typedef union {
+ struct {
+ UINT8 TimerUse : 3;
+ UINT8 Reserved : 3;
+ UINT8 TimerRunning : 1;
+ UINT8 TimerUseExpirationFlagLog : 1;
+ } Bits;
+ UINT8 Uint8;
+} IPMI_WATCHDOG_TIMER_USE;
+
+//
+// Definitions for watchdog timeout action
+//
+#define IPMI_WATCHDOG_TIMER_ACTION_NO_ACTION 0x0
+#define IPMI_WATCHDOG_TIMER_ACTION_HARD_RESET 0x1
+#define IPMI_WATCHDOG_TIMER_ACTION_POWER_DONW 0x2
+#define IPMI_WATCHDOG_TIMER_ACTION_POWER_CYCLE 0x3
+
+//
+// Definitions for watchdog pre-timeout interrupt
+//
+#define IPMI_WATCHDOG_PRE_TIMEOUT_INTERRUPT_NONE 0x0
+#define IPMI_WATCHDOG_PRE_TIMEOUT_INTERRUPT_SMI 0x1
+#define IPMI_WATCHDOG_PRE_TIMEOUT_INTERRUPT_NMI 0x2
+#define IPMI_WATCHDOG_PRE_TIMEOUT_INTERRUPT_MESSAGING 0x3
+
+//
+// Structure definitions for Timer Actions
+//
+typedef union {
+ struct {
+ UINT8 TimeoutAction : 3;
+ UINT8 Reserved1 : 1;
+ UINT8 PreTimeoutInterrupt : 3;
+ UINT8 Reserved2 : 1;
+ } Bits;
+ UINT8 Uint8;
+} IPMI_WATCHDOG_TIMER_ACTIONS;
+
+//
+// Bit definitions for Timer use expiration flags
+//
+#define IPMI_WATCHDOG_TIMER_EXPIRATION_FLAG_BIOS_FRB2 BIT1
+#define IPMI_WATCHDOG_TIMER_EXPIRATION_FLAG_BIOS_POST BIT2
+#define IPMI_WATCHDOG_TIMER_EXPIRATION_FLAG_OS_LOAD BIT3
+#define IPMI_WATCHDOG_TIMER_EXPIRATION_FLAG_SMS_OS BIT4
+#define IPMI_WATCHDOG_TIMER_EXPIRATION_FLAG_OEM BIT5
+
+typedef struct {
+ IPMI_WATCHDOG_TIMER_USE TimerUse;
+ IPMI_WATCHDOG_TIMER_ACTIONS TimerActions;
+ UINT8 PretimeoutInterval;
+ UINT8 TimerUseExpirationFlagsClear;
+ UINT16 InitialCountdownValue;
+} IPMI_SET_WATCHDOG_TIMER_REQUEST;
+
+//
+// Definitions for Get WatchDog Timer command
+//
+#define IPMI_APP_GET_WATCHDOG_TIMER 0x25
+
+//
+// Constants and Structure definitions for "Get WatchDog Timer" command to follow here
+//
+typedef struct {
+ UINT8 CompletionCode;
+ IPMI_WATCHDOG_TIMER_USE TimerUse;
+ IPMI_WATCHDOG_TIMER_ACTIONS TimerActions;
+ UINT8 PretimeoutInterval;
+ UINT8 TimerUseExpirationFlagsClear;
+ UINT16 InitialCountdownValue;
+ UINT16 PresentCountdownValue;
+} IPMI_GET_WATCHDOG_TIMER_RESPONSE;
+
+//
+// Below is Definitions for IPMI Messaging Support Commands (Chapter 22)
+//
+
+//
+// Definitions for Set BMC Global Enables command
+//
+#define IPMI_APP_SET_BMC_GLOBAL_ENABLES 0x2E
+
+//
+// Constants and Structure definitions for "Set BMC Global Enables " command to follow here
+//
+typedef union {
+ struct {
+ UINT8 ReceiveMessageQueueInterrupt : 1;
+ UINT8 EventMessageBufferFullInterrupt : 1;
+ UINT8 EventMessageBuffer : 1;
+ UINT8 SystemEventLogging : 1;
+ UINT8 Reserved : 1;
+ UINT8 Oem0Enable : 1;
+ UINT8 Oem1Enable : 1;
+ UINT8 Oem2Enable : 1;
+ } Bits;
+ UINT8 Uint8;
+} IPMI_BMC_GLOBAL_ENABLES;
+
+typedef struct {
+ IPMI_BMC_GLOBAL_ENABLES SetEnables;
+} IPMI_SET_BMC_GLOBAL_ENABLES_REQUEST;
+
+//
+// Definitions for Get BMC Global Enables command
+//
+#define IPMI_APP_GET_BMC_GLOBAL_ENABLES 0x2F
+
+//
+// Constants and Structure definitions for "Get BMC Global Enables " command to follow here
+//
+typedef struct {
+ UINT8 CompletionCode;
+ IPMI_BMC_GLOBAL_ENABLES GetEnables;
+} IPMI_GET_BMC_GLOBAL_ENABLES_RESPONSE;
+
+//
+// Definitions for Clear Message Flags command
+//
+#define IPMI_APP_CLEAR_MESSAGE_FLAGS 0x30
+
+//
+// Constants and Structure definitions for "Clear Message Flags" command to follow here
+//
+typedef union {
+ struct {
+ UINT8 ReceiveMessageQueue : 1;
+ UINT8 EventMessageBuffer : 1;
+ UINT8 Reserved1 : 1;
+ UINT8 WatchdogPerTimeoutInterrupt : 1;
+ UINT8 Reserved2 : 1;
+ UINT8 Oem0 : 1;
+ UINT8 Oem1 : 1;
+ UINT8 Oem2 : 1;
+ } Bits;
+ UINT8 Uint8;
+} IPMI_MESSAGE_FLAGS;
+
+typedef struct {
+ IPMI_MESSAGE_FLAGS ClearFlags;
+} IPMI_CLEAR_MESSAGE_FLAGS_REQUEST;
+
+//
+// Definitions for Get Message Flags command
+//
+#define IPMI_APP_GET_MESSAGE_FLAGS 0x31
+
+//
+// Constants and Structure definitions for "Get Message Flags" command to follow here
+//
+typedef struct {
+ UINT8 CompletionCode;
+ IPMI_MESSAGE_FLAGS GetFlags;
+} IPMI_GET_MESSAGE_FLAGS_RESPONSE;
+
+//
+// Definitions for Enable Message Channel Receive command
+//
+#define IPMI_APP_ENABLE_MESSAGE_CHANNEL_RECEIVE 0x32
+
+//
+// Constants and Structure definitions for "Enable Message Channel Receive" command to follow here
+//
+
+//
+// Definitions for Get Message command
+//
+#define IPMI_APP_GET_MESSAGE 0x33
+
+//
+// Constants and Structure definitions for "Get Message" command to follow here
+//
+typedef union {
+ struct {
+ UINT8 ChannelNumber : 4;
+ UINT8 InferredPrivilegeLevel : 4;
+ } Bits;
+ UINT8 Uint8;
+} IPMI_GET_MESSAGE_CHANNEL_NUMBER;
+
+typedef struct {
+ UINT8 CompletionCode;
+ IPMI_GET_MESSAGE_CHANNEL_NUMBER ChannelNumber;
+ UINT8 MessageData[0];
+} IPMI_GET_MESSAGE_RESPONSE;
+
+//
+// Definitions for Send Message command
+//
+#define IPMI_APP_SEND_MESSAGE 0x34
+
+//
+// Constants and Structure definitions for "Send Message" command to follow here
+//
+typedef union {
+ struct {
+ UINT8 ChannelNumber : 4;
+ UINT8 Authentication : 1;
+ UINT8 Encryption : 1;
+ UINT8 Tracking : 2;
+ } Bits;
+ UINT8 Uint8;
+} IPMI_SEND_MESSAGE_CHANNEL_NUMBER;
+
+typedef struct {
+ UINT8 CompletionCode;
+ IPMI_SEND_MESSAGE_CHANNEL_NUMBER ChannelNumber;
+ UINT8 MessageData[0];
+} IPMI_SEND_MESSAGE_REQUEST;
+
+typedef struct {
+ UINT8 CompletionCode;
+ UINT8 ResponseData[0];
+} IPMI_SEND_MESSAGE_RESPONSE;
+
+//
+// Definitions for Read Event Message Buffer command
+//
+#define IPMI_APP_READ_EVENT_MSG_BUFFER 0x35
+
+//
+// Constants and Structure definitions for "Read Event Message Buffer" command to follow here
+//
+
+//
+// Definitions for Get BT Interface Capabilities command
+//
+#define IPMI_APP_GET_BT_INTERFACE_CAPABILITY 0x36
+
+//
+// Constants and Structure definitions for "Get BT Interface Capabilities" command to follow here
+//
+
+//
+// Definitions for Get System GUID command
+//
+#define IPMI_APP_GET_SYSTEM_GUID 0x37
+
+typedef struct {
+ UINT8 CompletionCode;
+ EFI_GUID SystemUuid;
+} IPMI_GET_SYSTEM_UUID_RESPONSE;
+
+//
+// Constants and Structure definitions for "Get System GUID" command to follow here
+//
+
+//
+// Definitions for Get Channel Authentication Capabilities command
+//
+#define IPMI_APP_GET_CHANNEL_AUTHENTICATION_CAPABILITIES 0x38
+
+//
+// Constants and Structure definitions for "Get Channel Authentication Capabilities" command to follow here
+//
+
+//
+// Definitions for Get Session Challenge command
+//
+#define IPMI_APP_GET_SESSION_CHALLENGE 0x39
+
+//
+// Constants and Structure definitions for "Get Session Challenge" command to follow here
+//
+
+//
+// Definitions for Activate Session command
+//
+#define IPMI_APP_ACTIVATE_SESSION 0x3A
+
+//
+// Constants and Structure definitions for "Activate Session" command to follow here
+//
+
+//
+// Definitions for Set Session Privelege Level command
+//
+#define IPMI_APP_SET_SESSION_PRIVELEGE_LEVEL 0x3B
+
+//
+// Constants and Structure definitions for "Set Session Privelege Level" command to follow here
+//
+
+//
+// Definitions for Close Session command
+//
+#define IPMI_APP_CLOSE_SESSION 0x3C
+
+//
+// Constants and Structure definitions for "Close Session" command to follow here
+//
+
+//
+// Definitions for Get Session Info command
+//
+#define IPMI_APP_GET_SESSION_INFO 0x3D
+
+//
+// Constants and Structure definitions for "Get Session Info" command to follow here
+//
+
+//
+// Definitions for Get Auth Code command
+//
+#define IPMI_APP_GET_AUTHCODE 0x3F
+
+//
+// Constants and Structure definitions for "Get AuthCode" command to follow here
+//
+
+//
+// Definitions for Set Channel Access command
+//
+#define IPMI_APP_SET_CHANNEL_ACCESS 0x40
+
+//
+// Constants and Structure definitions for "Set Channel Access" command to follow here
+//
+
+//
+// Definitions for Get Channel Access command
+//
+#define IPMI_APP_GET_CHANNEL_ACCESS 0x41
+
+//
+// Constants and Structure definitions for "Get Channel Access" command to follow here
+//
+
+//
+// Definitions for channel access memory type in Get Channel Access command request
+//
+#define IPMI_CHANNEL_ACCESS_MEMORY_TYPE_NON_VOLATILE 0x1
+#define IPMI_CHANNEL_ACCESS_MEMORY_TYPE_PRESENT_VOLATILE_SETTING 0x2
+
+//
+// Definitions for channel access modes in Get Channel Access command response
+//
+#define IPMI_CHANNEL_ACCESS_MODES_DISABLED 0x0
+#define IPMI_CHANNEL_ACCESS_MODES_PRE_BOOT_ONLY 0x1
+#define IPMI_CHANNEL_ACCESS_MODES_ALWAYS_AVAILABLE 0x2
+#define IPMI_CHANNEL_ACCESS_MODES_SHARED 0x3
+
+typedef union {
+ struct {
+ UINT8 ChannelNo : 4;
+ UINT8 Reserved : 4;
+ } Bits;
+ UINT8 Uint8;
+} IPMI_GET_CHANNEL_ACCESS_CHANNEL_NUMBER;
+
+typedef union {
+ struct {
+ UINT8 Reserved : 6;
+ UINT8 MemoryType : 2;
+ } Bits;
+ UINT8 Uint8;
+} IPMI_GET_CHANNEL_ACCESS_TYPE;
+
+typedef struct {
+ IPMI_GET_CHANNEL_ACCESS_CHANNEL_NUMBER ChannelNumber;
+ IPMI_GET_CHANNEL_ACCESS_TYPE AccessType;
+} IPMI_GET_CHANNEL_ACCESS_REQUEST;
+
+typedef union {
+ struct {
+ UINT8 AccessMode : 3;
+ UINT8 UserLevelAuthEnabled : 1;
+ UINT8 MessageAuthEnable : 1;
+ UINT8 Alert : 1;
+ UINT8 Reserved : 2;
+ } Bits;
+ UINT8 Uint8;
+} IPMI_GET_CHANNEL_ACCESS_CHANNEL_ACCESS;
+
+typedef union {
+ struct {
+ UINT8 ChannelPriviledgeLimit : 4;
+ UINT8 Reserved : 4;
+ } Bits;
+ UINT8 Uint8;
+} IPMI_GET_CHANNEL_ACCESS_PRIVILEGE_LIMIT;
+
+typedef struct {
+ UINT8 CompletionCode;
+ IPMI_GET_CHANNEL_ACCESS_CHANNEL_ACCESS ChannelAccess;
+ IPMI_GET_CHANNEL_ACCESS_PRIVILEGE_LIMIT PrivilegeLimit;
+} IPMI_GET_CHANNEL_ACCESS_RESPONSE;
+
+//
+// Definitions for Get Channel Info command
+//
+#define IPMI_APP_GET_CHANNEL_INFO 0x42
+
+//
+// Constants and Structure definitions for "Get Channel Info" command to follow here
+//
+
+//
+// Definitions for channel media type
+//
+// IPMB (I2C)
+#define IPMI_CHANNEL_MEDIA_TYPE_IPMB 0x1
+// ICMB v1.0
+#define IPMI_CHANNEL_MEDIA_TYPE_ICMB_1_0 0x2
+// ICMB v0.9
+#define IPMI_CHANNEL_MEDIA_TYPE_ICMB_0_9 0x3
+// 802.3 LAN
+#define IPMI_CHANNEL_MEDIA_TYPE_802_3_LAN 0x4
+// Asynch. Serial/Modem (RS-232)
+#define IPMI_CHANNEL_MEDIA_TYPE_RS_232 0x5
+// Other LAN
+#define IPMI_CHANNEL_MEDIA_TYPE_OTHER_LAN 0x6
+// PCI SMBus
+#define IPMI_CHANNEL_MEDIA_TYPE_PCI_SM_BUS 0x7
+// SMBus v1.0/1.1
+#define IPMI_CHANNEL_MEDIA_TYPE_SM_BUS_V1 0x8
+// SMBus v2.0
+#define IPMI_CHANNEL_MEDIA_TYPE_SM_BUS_V2 0x9
+// USB 1.x
+#define IPMI_CHANNEL_MEDIA_TYPE_USB1 0xA
+// USB 2.x
+#define IPMI_CHANNEL_MEDIA_TYPE_USB2 0xB
+// System Interface (KCS, SMIC, or BT)
+#define IPMI_CHANNEL_MEDIA_TYPE_SYSTEM_INTERFACE 0xC
+// OEM
+#define IPMI_CHANNEL_MEDIA_TYPE_OEM_START 0x60
+#define IPMI_CHANNEL_MEDIA_TYPE_OEM_END 0x7F
+
+//
+// Definitions for channel protocol type
+//
+// Not available
+#define IPMI_CHANNEL_PROTOCOL_TYPE_NA 0x00
+// IPMB-1.0
+#define IPMI_CHANNEL_PROTOCOL_TYPE_IPMB_1_0 0x01
+// ICMB-1.0
+#define IPMI_CHANNEL_PROTOCOL_TYPE_ICMB_1_0 0x02
+// Reserved
+#define IPMI_CHANNEL_PROTOCOL_TYPE_RESERVED 0x03
+// IPMI SMBUS
+#define IPMI_CHANNEL_PROTOCOL_TYPE_IPMI_SMBUS 0x04
+// KCS
+#define IPMI_CHANNEL_PROTOCOL_TYPE_KCS 0x05
+// SMIC
+#define IPMI_CHANNEL_PROTOCOL_TYPE_SMIC 0x06
+// BT-10
+#define IPMI_CHANNEL_PROTOCOL_TYPE_BT_10 0x07
+// BT-15
+#define IPMI_CHANNEL_PROTOCOL_TYPE_BT_15 0x08
+// TMode
+#define IPMI_CHANNEL_PROTOCOL_TYPE_TMODE 0x09
+
+typedef union {
+ struct {
+ UINT8 ChannelNo : 4;
+ UINT8 Reserved : 4;
+ } Bits;
+ UINT8 Uint8;
+} IPMI_CHANNEL_INFO_CHANNEL_NUMBER;
+
+typedef union {
+ struct {
+ UINT8 ChannelMediumType : 7;
+ UINT8 Reserved : 1;
+ } Bits;
+ UINT8 Uint8;
+} IPMI_CHANNEL_INFO_MEDIUM_TYPE;
+
+typedef union {
+ struct {
+ UINT8 ChannelProtocolType : 5;
+ UINT8 Reserved : 3;
+ } Bits;
+ UINT8 Uint8;
+} IPMI_CHANNEL_INFO_PROTOCOL_TYPE;
+
+typedef union {
+ struct {
+ UINT8 ActiveSessionCount : 6;
+ UINT8 SessionSupport : 2;
+ } Bits;
+ UINT8 Uint8;
+} IPMI_CHANNEL_INFO_SESSION_SUPPORT;
+
+typedef struct {
+ UINT8 CompletionCode;
+ IPMI_CHANNEL_INFO_CHANNEL_NUMBER ChannelNumber;
+ IPMI_CHANNEL_INFO_MEDIUM_TYPE MediumType;
+ IPMI_CHANNEL_INFO_PROTOCOL_TYPE ProtocolType;
+ IPMI_CHANNEL_INFO_SESSION_SUPPORT SessionSupport;
+ UINT8 VendorId[3];
+ UINT16 AuxChannelInfo;
+} IPMI_GET_CHANNEL_INFO_RESPONSE;
+
+typedef struct {
+ IPMI_CHANNEL_INFO_CHANNEL_NUMBER ChannelNumber;
+} IPMI_GET_CHANNEL_INFO_REQUEST;
+
+//
+// Constants and Structure definitions for "Get Channel Info" command to follow here
+//
+
+//
+// Definitions for Set User Access command
+//
+#define IPMI_APP_SET_USER_ACCESS 0x43
+
+//
+// Constants and Structure definitions for "Set User Access" command to follow here
+//
+
+//
+// Definitions for Get User Access command
+//
+#define IPMI_APP_GET_USER_ACCESS 0x44
+
+//
+// Constants and Structure definitions for "Get User Access" command to follow here
+//
+typedef union {
+ struct {
+ UINT8 ChannelNo : 4;
+ UINT8 Reserved : 4;
+ } Bits;
+ UINT8 Uint8;
+} IPMI_GET_USER_ACCESS_CHANNEL_NUMBER;
+
+typedef union {
+ struct {
+ UINT8 UserId : 6;
+ UINT8 Reserved : 2;
+ } Bits;
+ UINT8 Uint8;
+} IPMI_USER_ID;
+
+typedef struct {
+ IPMI_GET_USER_ACCESS_CHANNEL_NUMBER ChannelNumber;
+ IPMI_USER_ID UserId;
+} IPMI_GET_USER_ACCESS_REQUEST;
+
+typedef union {
+ struct {
+ UINT8 MaxUserId : 6;
+ UINT8 Reserved : 2;
+ } Bits;
+ UINT8 Uint8;
+} IPMI_GET_USER_ACCESS_MAX_USER_ID;
+
+typedef union {
+ struct {
+ UINT8 CurrentUserId : 6;
+ UINT8 UserIdEnableStatus : 2;
+ } Bits;
+ UINT8 Uint8;
+} IPMI_GET_USER_ACCESS_CURRENT_USER;
+
+typedef union {
+ struct {
+ UINT8 FixedUserId : 6;
+ UINT8 Reserved : 2;
+ } Bits;
+ UINT8 Uint8;
+} IPMI_GET_USER_ACCESS_FIXED_NAME_USER;
+
+typedef union {
+ struct {
+ UINT8 UserPrivilegeLimit : 4;
+ UINT8 EnableIpmiMessaging : 1;
+ UINT8 EnableUserLinkAuthetication : 1;
+ UINT8 UserAccessAvailable : 1;
+ UINT8 Reserved : 1;
+ } Bits;
+ UINT8 Uint8;
+} IPMI_GET_USER_ACCESS_CHANNEL_ACCESS;
+
+typedef struct {
+ UINT8 CompletionCode;
+ IPMI_GET_USER_ACCESS_MAX_USER_ID MaxUserId;
+ IPMI_GET_USER_ACCESS_CURRENT_USER CurrentUser;
+ IPMI_GET_USER_ACCESS_FIXED_NAME_USER FixedNameUser;
+ IPMI_GET_USER_ACCESS_CHANNEL_ACCESS ChannelAccess;
+} IPMI_GET_USER_ACCESS_RESPONSE;
+
+//
+// Definitions for Set User Name command
+//
+#define IPMI_APP_SET_USER_NAME 0x45
+
+//
+// Constants and Structure definitions for "Set User Name" command to follow here
+//
+typedef struct {
+ IPMI_USER_ID UserId;
+ UINT8 UserName[16];
+} IPMI_SET_USER_NAME_REQUEST;
+
+//
+// Definitions for Get User Name command
+//
+#define IPMI_APP_GET_USER_NAME 0x46
+
+//
+// Constants and Structure definitions for "Get User Name" command to follow here
+//
+typedef struct {
+ IPMI_USER_ID UserId;
+} IPMI_GET_USER_NAME_REQUEST;
+
+typedef struct {
+ UINT8 CompletionCode;
+ UINT8 UserName[16];
+} IPMI_GET_USER_NAME_RESPONSE;
+
+//
+// Definitions for Set User Password command
+//
+#define IPMI_APP_SET_USER_PASSWORD 0x47
+
+//
+// Constants and Structure definitions for "Set User Password" command to follow here
+//
+
+//
+// Definitions for Set User password command operation type
+//
+#define IPMI_SET_USER_PASSWORD_OPERATION_TYPE_DISABLE_USER 0x0
+#define IPMI_SET_USER_PASSWORD_OPERATION_TYPE_ENABLE_USER 0x1
+#define IPMI_SET_USER_PASSWORD_OPERATION_TYPE_SET_PASSWORD 0x2
+#define IPMI_SET_USER_PASSWORD_OPERATION_TYPE_TEST_PASSWORD 0x3
+
+//
+// Definitions for Set user password command password size
+//
+#define IPMI_SET_USER_PASSWORD_PASSWORD_SIZE_16 0x0
+#define IPMI_SET_USER_PASSWORD_PASSWORD_SIZE_20 0x1
+
+typedef union {
+ struct {
+ UINT8 UserId : 6;
+ UINT8 Reserved : 1;
+ UINT8 PasswordSize : 1;
+ } Bits;
+ UINT8 Uint8;
+} IPMI_SET_USER_PASSWORD_USER_ID;
+
+typedef union {
+ struct {
+ UINT8 Operation : 2;
+ UINT8 Reserved : 6;
+ } Bits;
+ UINT8 Uint8;
+} IPMI_SET_USER_PASSWORD_OPERATION;
+
+typedef struct {
+ IPMI_SET_USER_PASSWORD_USER_ID UserId;
+ IPMI_SET_USER_PASSWORD_OPERATION Operation;
+ UINT8 PasswordData[0]; // 16 or 20 bytes, depending on the 'PasswordSize' field
+} IPMI_SET_USER_PASSWORD_REQUEST;
+
+//
+// Below is Definitions for RMCP+ Support and Payload Commands (Chapter 24)
+//
+
+//
+// Definitions for Activate Payload command
+//
+#define IPMI_APP_ACTIVATE_PAYLOAD 0x48
+
+//
+// Constants and Structure definitions for "Activate Payload" command to follow here
+//
+
+//
+// Definitions for De-Activate Payload command
+//
+#define IPMI_APP_DEACTIVATE_PAYLOAD 0x49
+
+//
+// Constants and Structure definitions for "DeActivate Payload" command to follow here
+//
+
+//
+// Definitions for Get Payload activation Status command
+//
+#define IPMI_APP_GET_PAYLOAD_ACTIVATION_STATUS 0x4a
+
+//
+// Constants and Structure definitions for "Get Payload activation Status" command to follow here
+//
+
+//
+// Definitions for Get Payload Instance Info command
+//
+#define IPMI_APP_GET_PAYLOAD_INSTANCE_INFO 0x4b
+
+//
+// Constants and Structure definitions for "Get Payload Instance Info" command to follow here
+//
+
+//
+// Definitions for Set User Payload Access command
+//
+#define IPMI_APP_SET_USER_PAYLOAD_ACCESS 0x4C
+
+//
+// Constants and Structure definitions for "Set User Payload Access" command to follow here
+//
+
+//
+// Definitions for Get User Payload Access command
+//
+#define IPMI_APP_GET_USER_PAYLOAD_ACCESS 0x4D
+
+//
+// Constants and Structure definitions for "Get User Payload Access" command to follow here
+//
+
+//
+// Definitions for Get Channel Payload Support command
+//
+#define IPMI_APP_GET_CHANNEL_PAYLOAD_SUPPORT 0x4E
+
+//
+// Constants and Structure definitions for "Get Channel Payload Support" command to follow here
+//
+
+//
+// Definitions for Get Channel Payload Version command
+//
+#define IPMI_APP_GET_CHANNEL_PAYLOAD_VERSION 0x4F
+
+//
+// Constants and Structure definitions for "Get Channel Payload Version" command to follow here
+//
+
+//
+// Definitions for Get Channel OEM Payload Info command
+//
+#define IPMI_APP_GET_CHANNEL_OEM_PAYLOAD_INFO 0x50
+
+//
+// Constants and Structure definitions for "Get Channel OEM Payload Info" command to follow here
+//
+
+//
+// Definitions for Master Write-Read command
+//
+#define IPMI_APP_MASTER_WRITE_READ 0x52
+
+//
+// Constants and Structure definitions for "Master Write Read" command to follow here
+//
+
+//
+// Definitions for Get Channel Cipher Suites command
+//
+#define IPMI_APP_GET_CHANNEL_CIPHER_SUITES 0x54
+
+//
+// Constants and Structure definitions for "Get Channel Cipher Suites" command to follow here
+//
+
+//
+// Below is Definitions for RMCP+ Support and Payload Commands (Chapter 24, Section 3)
+//
+
+//
+// Definitions for Suspend-Resume Payload Encryption command
+//
+#define IPMI_APP_SUSPEND_RESUME_PAYLOAD_ENCRYPTION 0x55
+
+//
+// Constants and Structure definitions for "Suspend-Resume Payload Encryption" command to follow here
+//
+
+//
+// Below is Definitions for IPMI Messaging Support Commands (Chapter 22, Section 25 and 9)
+//
+
+//
+// Definitions for Set Channel Security Keys command
+//
+#define IPMI_APP_SET_CHANNEL_SECURITY_KEYS 0x56
+
+//
+// Constants and Structure definitions for "Set Channel Security Keys" command to follow here
+//
+
+//
+// Definitions for Get System Interface Capabilities command
+//
+#define IPMI_APP_GET_SYSTEM_INTERFACE_CAPABILITIES 0x57
+
+//
+// Constants and Structure definitions for "Get System Interface Capabilities" command to follow here
+//
+
+//
+// Definitions for Get System Interface Capabilities command SSIF transaction support
+//
+#define IPMI_GET_SYSTEM_INTERFACE_CAPABILITIES_SSIF_TRANSACTION_SUPPORT_SINGLE_PARTITION_RW 0x0
+#define IPMI_GET_SYSTEM_INTERFACE_CAPABILITIES_SSIF_TRANSACTION_SUPPORT_MULTI_PARTITION_RW 0x1
+#define IPMI_GET_SYSTEM_INTERFACE_CAPABILITIES_SSIF_TRANSACTION_SUPPORT_MULTI_PARTITION_RW_WITH_MIDDLE 0x2
+
+#pragma pack()
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/IpmiNetFnBridge.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/IpmiNetFnBridge.h
new file mode 100644
index 0000000000..11b904d642
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/IpmiNetFnBridge.h
@@ -0,0 +1,237 @@
+/** @file
+ IPMI 2.0 definitions from the IPMI Specification Version 2.0, Revision 1.1.
+ IPMI Intelligent Chassis Management Bus Bridge Specification Version 1.0,
+ Revision 1.3.
+
+ See IPMI specification, Appendix G, Command Assignments
+ and Appendix H, Sub-function Assignments.
+
+ Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _IPMI_NET_FN_BRIDGE_H_
+#define _IPMI_NET_FN_BRIDGE_H_
+
+//
+// Net function definition for Bridge command
+//
+#define IPMI_NETFN_BRIDGE 0x02
+
+//
+// Definitions for Get Bridge State command
+//
+#define IPMI_BRIDGE_GET_STATE 0x00
+
+//
+// Constants and Structure definitions for "Get Bridge State" command to follow here
+//
+
+//
+// Definitions for Set Bridge State command
+//
+#define IPMI_BRIDGE_SET_STATE 0x01
+
+//
+// Constants and Structure definitions for "Set Bridge State" command to follow here
+//
+
+//
+// Definitions for Get ICMB Address command
+//
+#define IPMI_BRIDGE_GET_ICMB_ADDRESS 0x02
+
+//
+// Constants and Structure definitions for "Get ICMB Address" command to follow here
+//
+
+//
+// Definitions for Set ICMB Address command
+//
+#define IPMI_BRIDGE_SET_ICMB_ADDRESS 0x03
+
+//
+// Constants and Structure definitions for "Set ICMB Address" command to follow here
+//
+
+//
+// Definitions for Set Bridge Proxy Address command
+//
+#define IPMI_BRIDGE_SET_PROXY_ADDRESS 0x04
+
+//
+// Constants and Structure definitions for "Set Bridge Proxy Address" command to follow here
+//
+
+//
+// Definitions for Get Bridge Statistics command
+//
+#define IPMI_BRIDGE_GET_BRIDGE_STATISTICS 0x05
+
+//
+// Constants and Structure definitions for "Get Bridge Statistics" command to follow here
+//
+
+//
+// Definitions for Get ICMB Capabilities command
+//
+#define IPMI_BRIDGE_GET_ICMB_CAPABILITIES 0x06
+
+//
+// Constants and Structure definitions for "Get ICMB Capabilities" command to follow here
+//
+
+//
+// Definitions for Clear Bridge Statistics command
+//
+#define IPMI_BRIDGE_CLEAR_STATISTICS 0x08
+
+//
+// Constants and Structure definitions for "Clear Bridge Statistics" command to follow here
+//
+
+//
+// Definitions for Get Bridge Proxy Address command
+//
+#define IPMI_BRIDGE_GET_PROXY_ADDRESS 0x09
+
+//
+// Constants and Structure definitions for "Get Bridge Proxy Address" command to follow here
+//
+
+//
+// Definitions for Get ICMB Connector Info command
+//
+#define IPMI_BRIDGE_GET_ICMB_CONNECTOR_INFO 0x0A
+
+//
+// Constants and Structure definitions for "Get ICMB Connector Info " command to follow here
+//
+
+//
+// Definitions for Get ICMB Connection ID command
+//
+#define IPMI_BRIDGE_GET_ICMB_CONNECTION_ID 0x0B
+
+//
+// Constants and Structure definitions for "Get ICMB Connection ID" command to follow here
+//
+
+//
+// Definitions for Get ICMB Connection ID command
+//
+#define IPMI_BRIDGE_SEND_ICMB_CONNECTION_ID 0x0C
+
+//
+// Constants and Structure definitions for "Send ICMB Connection ID" command to follow here
+//
+
+//
+// Definitions for Prepare for Discovery command
+//
+#define IPMI_BRIDGE_PREPARE_FOR_DISCOVERY 0x10
+
+//
+// Constants and Structure definitions for "Prepare for Discovery" command to follow here
+//
+
+//
+// Definitions for Get Addresses command
+//
+#define IPMI_BRIDGE_GET_ADDRESSES 0x11
+
+//
+// Constants and Structure definitions for "Get Addresses" command to follow here
+//
+
+//
+// Definitions for Set Discovered command
+//
+#define IPMI_BRIDGE_SET_DISCOVERED 0x12
+
+//
+// Constants and Structure definitions for "Set Discovered" command to follow here
+//
+
+//
+// Definitions for Get Chassis Device ID command
+//
+#define IPMI_BRIDGE_GET_CHASSIS_DEVICEID 0x13
+
+//
+// Constants and Structure definitions for "Get Chassis Device ID" command to follow here
+//
+
+//
+// Definitions for Set Chassis Device ID command
+//
+#define IPMI_BRIDGE_SET_CHASSIS_DEVICEID 0x14
+
+//
+// Constants and Structure definitions for "Set Chassis Device ID" command to follow here
+//
+
+//
+// Definitions for Bridge Request command
+//
+#define IPMI_BRIDGE_REQUEST 0x20
+
+//
+// Constants and Structure definitions for "Bridge Request" command to follow here
+//
+
+//
+// Definitions for Bridge Message command
+//
+#define IPMI_BRIDGE_MESSAGE 0x21
+
+//
+// Constants and Structure definitions for "Bridge Message" command to follow here
+//
+
+//
+// Definitions for Get Event Count command
+//
+#define IPMI_BRIDGE_GET_EVENT_COUNT 0x30
+
+//
+// Constants and Structure definitions for "Get Event Count" command to follow here
+//
+
+//
+// Definitions for Set Event Destination command
+//
+#define IPMI_BRIDGE_SET_EVENT_DESTINATION 0x31
+
+//
+// Constants and Structure definitions for "Set Event Destination" command to follow here
+//
+
+//
+// Definitions for Set Event Reception State command
+//
+#define IPMI_BRIDGE_SET_EVENT_RECEPTION_STATE 0x32
+
+//
+// Constants and Structure definitions for "Set Event Reception State" command to follow here
+//
+
+//
+// Definitions for Set Event Reception State command
+//
+#define IPMI_BRIDGE_SET_EVENT_RECEPTION_STATE 0x32
+
+//
+// Constants and Structure definitions for "Set Event Reception State" command to follow here
+//
+
+//
+// Definitions for Send ICMB Event Message command
+//
+#define IPMI_BRIDGE_SEND_ICMB_EVENT_MESSAGE 0x33
+
+//
+// Constants and Structure definitions for "Send ICMB Event Message" command to follow here
+//
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/IpmiNetFnChassis.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/IpmiNetFnChassis.h
new file mode 100644
index 0000000000..ead94a1626
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/IpmiNetFnChassis.h
@@ -0,0 +1,462 @@
+/** @file
+ IPMI 2.0 definitions from the IPMI Specification Version 2.0, Revision 1.1.
+
+ This file contains all NetFn Chassis commands, including:
+ Chassis Commands (Chapter 28)
+
+ See IPMI specification, Appendix G, Command Assignments
+ and Appendix H, Sub-function Assignments.
+
+ Copyright (c) 1999 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _IPMI_NET_FN_CHASSIS_H_
+#define _IPMI_NET_FN_CHASSIS_H_
+
+#pragma pack (1)
+//
+// Net function definition for Chassis command
+//
+#define IPMI_NETFN_CHASSIS 0x00
+
+//
+// Below is Definitions for Chassis commands (Chapter 28)
+//
+
+//
+// Definitions for Get Chassis Capabilities command
+//
+#define IPMI_CHASSIS_GET_CAPABILITIES 0x00
+
+//
+// Constants and Structure definitions for "Get Chassis Capabilities" command to follow here
+//
+typedef struct {
+ UINT8 CompletionCode;
+ UINT8 CapabilitiesFlags;
+ UINT8 ChassisFruInfoDeviceAddress;
+ UINT8 ChassisSDRDeviceAddress;
+ UINT8 ChassisSELDeviceAddress;
+ UINT8 ChassisSystemManagementDeviceAddress;
+ UINT8 ChassisBridgeDeviceAddress;
+} IPMI_GET_CHASSIS_CAPABILITIES_RESPONSE;
+
+//
+// Definitions for Get Chassis Status command
+//
+#define IPMI_CHASSIS_GET_STATUS 0x01
+
+//
+// Constants and Structure definitions for "Get Chassis Status" command to follow here
+//
+typedef struct {
+ UINT8 CompletionCode;
+ UINT8 CurrentPowerState;
+ UINT8 LastPowerEvent;
+ UINT8 MiscChassisState;
+ UINT8 FrontPanelButtonCapabilities;
+} IPMI_GET_CHASSIS_STATUS_RESPONSE;
+
+//
+// Definitions for Chassis Control command
+//
+#define IPMI_CHASSIS_CONTROL 0x02
+
+//
+// Constants and Structure definitions for "Chassis Control" command to follow here
+//
+typedef union {
+ struct {
+ UINT8 ChassisControl : 4;
+ UINT8 Reserved : 4;
+ } Bits;
+ UINT8 Uint8;
+} IPMI_CHASSIS_CONTROL_CHASSIS_CONTROL;
+
+typedef struct {
+ IPMI_CHASSIS_CONTROL_CHASSIS_CONTROL ChassisControl;
+} IPMI_CHASSIS_CONTROL_REQUEST;
+
+//
+// Definitions for Chassis Reset command
+//
+#define IPMI_CHASSIS_RESET 0x03
+
+//
+// Constants and Structure definitions for "Chassis Reset" command to follow here
+//
+
+//
+// Definitions for Chassis Identify command
+//
+#define IPMI_CHASSIS_IDENTIFY 0x04
+
+//
+// Constants and Structure definitions for "Chassis Identify" command to follow here
+//
+
+//
+// Definitions for Set Chassis Capabilities command
+//
+#define IPMI_CHASSIS_SET_CAPABILITIES 0x05
+
+//
+// Constants and Structure definitions for "Set Chassis Capabilities" command to follow here
+//
+
+//
+// Definitions for Set Power Restore Policy command
+//
+#define IPMI_CHASSIS_SET_POWER_RESTORE_POLICY 0x06
+
+//
+// Constants and Structure definitions for "Set Power Restore Policy" command to follow here
+//
+typedef union {
+ struct {
+ UINT8 PowerRestorePolicy : 3;
+ UINT8 Reserved : 5;
+ } Bits;
+ UINT8 Uint8;
+} IPMI_POWER_RESTORE_POLICY;
+
+typedef struct {
+ IPMI_POWER_RESTORE_POLICY PowerRestorePolicy;
+} IPMI_SET_POWER_RESTORE_POLICY_REQUEST;
+
+typedef struct {
+ UINT8 CompletionCode;
+ UINT8 PowerRestorePolicySupport;
+} IPMI_SET_POWER_RESTORE_POLICY_RESPONSE;
+
+//
+// Definitions for Get System Restart Cause command
+//
+#define IPMI_CHASSIS_GET_SYSTEM_RESTART_CAUSE 0x07
+
+//
+// Constants and Structure definitions for "Get System Restart Cause" command to follow here
+//
+#define IPMI_SYSTEM_RESTART_CAUSE_UNKNOWN 0x0
+#define IPMI_SYSTEM_RESTART_CAUSE_CHASSIS_CONTROL_COMMAND 0x1
+#define IPMI_SYSTEM_RESTART_CAUSE_PUSHBUTTON_RESET 0x2
+#define IPMI_SYSTEM_RESTART_CAUSE_PUSHBUTTON_POWERUP 0x3
+#define IPMI_SYSTEM_RESTART_CAUSE_WATCHDOG_EXPIRE 0x4
+#define IPMI_SYSTEM_RESTART_CAUSE_OEM 0x5
+#define IPMI_SYSTEM_RESTART_CAUSE_AUTO_POWER_ALWAYS_RESTORE 0x6
+#define IPMI_SYSTEM_RESTART_CAUSE_AUTO_POWER_RESTORE_PREV 0x7
+#define IPMI_SYSTEM_RESTART_CAUSE_PEF_RESET 0x8
+#define IPMI_SYSTEM_RESTART_CAUSE_PEF_POWERCYCLE 0x9
+#define IPMI_SYSTEM_RESTART_CAUSE_SOFT_RESET 0xA
+#define IPMI_SYSTEM_RESTART_CAUSE_RTC_POWERUP 0xB
+
+typedef union {
+ struct {
+ UINT8 Cause : 4;
+ UINT8 Reserved : 4;
+ } Bits;
+ UINT8 Uint8;
+} IPMI_SYSTEM_RESTART_CAUSE;
+
+typedef struct {
+ UINT8 CompletionCode;
+ IPMI_SYSTEM_RESTART_CAUSE RestartCause;
+ UINT8 ChannelNumber;
+} IPMI_GET_SYSTEM_RESTART_CAUSE_RESPONSE;
+
+//
+// Definitions for Set System BOOT options command
+//
+#define IPMI_CHASSIS_SET_SYSTEM_BOOT_OPTIONS 0x08
+
+//
+// Constants and Structure definitions for "Set System boot options" command to follow here
+//
+typedef union {
+ struct {
+ UINT8 ParameterSelector : 7;
+ UINT8 MarkParameterInvalid : 1;
+ } Bits;
+ UINT8 Uint8;
+} IPMI_SET_BOOT_OPTIONS_PARAMETER_VALID;
+
+typedef struct {
+ IPMI_SET_BOOT_OPTIONS_PARAMETER_VALID ParameterValid;
+ UINT8 ParameterData[0];
+} IPMI_SET_BOOT_OPTIONS_REQUEST;
+
+typedef struct {
+ UINT8 CompletionCode : 8;
+} IPMI_SET_BOOT_OPTIONS_RESPONSE;
+
+//
+// Definitions for Get System Boot options command
+//
+#define IPMI_CHASSIS_GET_SYSTEM_BOOT_OPTIONS 0x09
+
+//
+// Constants and Structure definitions for "Get System boot options" command to follow here
+//
+typedef union {
+ struct {
+ UINT8 ParameterSelector : 7;
+ UINT8 Reserved : 1;
+ } Bits;
+ UINT8 Uint8;
+} IPMI_GET_BOOT_OPTIONS_PARAMETER_SELECTOR;
+
+typedef struct {
+ IPMI_GET_BOOT_OPTIONS_PARAMETER_SELECTOR ParameterSelector;
+ UINT8 SetSelector;
+ UINT8 BlockSelector;
+} IPMI_GET_BOOT_OPTIONS_REQUEST;
+
+typedef struct {
+ UINT8 Parameter;
+ UINT8 Valid;
+ UINT8 Data1;
+ UINT8 Data2;
+ UINT8 Data3;
+ UINT8 Data4;
+ UINT8 Data5;
+} IPMI_GET_THE_SYSTEM_BOOT_OPTIONS;
+
+typedef struct {
+ UINT8 ParameterVersion;
+ UINT8 ParameterValid;
+ UINT8 ChannelNumber;
+ UINT32 SessionId;
+ UINT32 TimeStamp;
+ UINT8 Reserved[3];
+} IPMI_BOOT_INITIATOR;
+
+//
+// Definitions for boot option parameter selector
+//
+#define IPMI_BOOT_OPTIONS_PARAMETER_SELECTOR_SET_IN_PROGRESS 0x0
+#define IPMI_BOOT_OPTIONS_PARAMETER_SELECTOR_SERVICE_PARTITION_SELECTOR 0x1
+#define IPMI_BOOT_OPTIONS_PARAMETER_SELECTOR_SERVICE_PARTITION_SCAN 0x2
+#define IPMI_BOOT_OPTIONS_PARAMETER_SELECTOR_BMC_BOOT_FLAG 0x3
+#define IPMI_BOOT_OPTIONS_PARAMETER_BOOT_INFO_ACK 0x4
+#define IPMI_BOOT_OPTIONS_PARAMETER_BOOT_FLAGS 0x5
+#define IPMI_BOOT_OPTIONS_PARAMETER_BOOT_INITIATOR_INFO 0x6
+#define IPMI_BOOT_OPTIONS_PARAMETER_BOOT_INITIATOR_MAILBOX 0x7
+#define IPMI_BOOT_OPTIONS_PARAMETER_OEM_BEGIN 0x60
+#define IPMI_BOOT_OPTIONS_PARAMETER_OEM_END 0x7F
+
+//
+// Response Parameters for IPMI Get Boot Options
+//
+typedef union {
+ struct {
+ UINT8 SetInProgress : 2;
+ UINT8 Reserved : 6;
+ } Bits;
+ UINT8 Uint8;
+} IPMI_BOOT_OPTIONS_RESPONSE_PARAMETER_0;
+
+typedef struct {
+ UINT8 ServicePartitionSelector;
+} IPMI_BOOT_OPTIONS_RESPONSE_PARAMETER_1;
+
+typedef union {
+ struct {
+ UINT8 ServicePartitionDiscovered : 1;
+ UINT8 ServicePartitionScanRequest : 1;
+ UINT8 Reserved : 6;
+ } Bits;
+ UINT8 Uint8;
+} IPMI_BOOT_OPTIONS_RESPONSE_PARAMETER_2;
+
+typedef union {
+ struct {
+ UINT8 BmcBootFlagValid : 5;
+ UINT8 Reserved : 3;
+ } Bits;
+ UINT8 Uint8;
+} IPMI_BOOT_OPTIONS_RESPONSE_PARAMETER_3;
+
+typedef struct {
+ UINT8 WriteMask;
+ UINT8 BootInitiatorAcknowledgeData;
+} IPMI_BOOT_OPTIONS_RESPONSE_PARAMETER_4;
+
+//
+// Definitions for the 'Boot device selector' field of Boot Option Parameters #5
+//
+#define IPMI_BOOT_DEVICE_SELECTOR_NO_OVERRIDE 0x0
+#define IPMI_BOOT_DEVICE_SELECTOR_PXE 0x1
+#define IPMI_BOOT_DEVICE_SELECTOR_HARDDRIVE 0x2
+#define IPMI_BOOT_DEVICE_SELECTOR_HARDDRIVE_SAFE_MODE 0x3
+#define IPMI_BOOT_DEVICE_SELECTOR_DIAGNOSTIC_PARTITION 0x4
+#define IPMI_BOOT_DEVICE_SELECTOR_CD_DVD 0x5
+#define IPMI_BOOT_DEVICE_SELECTOR_BIOS_SETUP 0x6
+#define IPMI_BOOT_DEVICE_SELECTOR_REMOTE_FLOPPY 0x7
+#define IPMI_BOOT_DEVICE_SELECTOR_REMOTE_CD_DVD 0x8
+#define IPMI_BOOT_DEVICE_SELECTOR_PRIMARY_REMOTE_MEDIA 0x9
+#define IPMI_BOOT_DEVICE_SELECTOR_REMOTE_HARDDRIVE 0xB
+#define IPMI_BOOT_DEVICE_SELECTOR_FLOPPY 0xF
+
+#define BOOT_OPTION_HANDLED_BY_BIOS 0x01
+
+//
+// Constant definitions for the 'BIOS Mux Control Override' field of Boot Option Parameters #5
+//
+#define BIOS_MUX_CONTROL_OVERRIDE_RECOMMEND_SETTING 0x00
+#define BIOS_MUX_CONTROL_OVERRIDE_FORCE_TO_BMC 0x01
+#define BIOS_MUX_CONTROL_OVERRIDE_FORCE_TO_SYSTEM 0x02
+
+typedef union {
+ struct {
+ UINT8 Reserved : 5;
+ UINT8 BiosBootType : 1;
+ UINT8 PersistentOptions : 1;
+ UINT8 BootFlagValid : 1;
+ } Bits;
+ UINT8 Uint8;
+} IPMI_BOOT_OPTIONS_RESPONSE_PARAMETER_5_DATA_1;
+
+typedef union {
+ struct {
+ UINT8 LockReset : 1;
+ UINT8 ScreenBlank : 1;
+ UINT8 BootDeviceSelector : 4;
+ UINT8 LockKeyboard : 1;
+ UINT8 CmosClear : 1;
+ } Bits;
+ UINT8 Uint8;
+} IPMI_BOOT_OPTIONS_RESPONSE_PARAMETER_5_DATA_2;
+
+typedef union {
+ struct {
+ UINT8 ConsoleRedirection : 2;
+ UINT8 LockSleep : 1;
+ UINT8 UserPasswordBypass : 1;
+ UINT8 ForceProgressEventTrap : 1;
+ UINT8 BiosVerbosity : 2;
+ UINT8 LockPower : 1;
+ } Bits;
+ UINT8 Uint8;
+} IPMI_BOOT_OPTIONS_RESPONSE_PARAMETER_5_DATA_3;
+
+typedef union {
+ struct {
+ UINT8 BiosMuxControlOverride : 3;
+ UINT8 BiosSharedModeOverride : 1;
+ UINT8 Reserved : 4;
+ } Bits;
+ UINT8 Uint8;
+} IPMI_BOOT_OPTIONS_RESPONSE_PARAMETER_5_DATA_4;
+
+typedef union {
+ struct {
+ UINT8 DeviceInstanceSelector : 5;
+ UINT8 Reserved : 3;
+ } Bits;
+ UINT8 Uint8;
+} IPMI_BOOT_OPTIONS_RESPONSE_PARAMETER_5_DATA_5;
+
+typedef struct {
+ IPMI_BOOT_OPTIONS_RESPONSE_PARAMETER_5_DATA_1 Data1;
+ IPMI_BOOT_OPTIONS_RESPONSE_PARAMETER_5_DATA_2 Data2;
+ IPMI_BOOT_OPTIONS_RESPONSE_PARAMETER_5_DATA_3 Data3;
+ IPMI_BOOT_OPTIONS_RESPONSE_PARAMETER_5_DATA_4 Data4;
+ IPMI_BOOT_OPTIONS_RESPONSE_PARAMETER_5_DATA_5 Data5;
+} IPMI_BOOT_OPTIONS_RESPONSE_PARAMETER_5;
+
+typedef union {
+ struct {
+ UINT8 ChannelNumber : 4;
+ UINT8 Reserved : 4;
+ } Bits;
+ UINT8 Uint8;
+} IPMI_BOOT_OPTIONS_CHANNEL_NUMBER;
+
+typedef struct {
+ IPMI_BOOT_OPTIONS_CHANNEL_NUMBER ChannelNumber;
+ UINT8 SessionId[4];
+ UINT8 BootInfoTimeStamp[4];
+} IPMI_BOOT_OPTIONS_RESPONSE_PARAMETER_6;
+
+typedef struct {
+ UINT8 SetSelector;
+ UINT8 BlockData[16];
+} IPMI_BOOT_OPTIONS_RESPONSE_PARAMETER_7;
+
+typedef union {
+ IPMI_BOOT_OPTIONS_RESPONSE_PARAMETER_0 Parm0;
+ IPMI_BOOT_OPTIONS_RESPONSE_PARAMETER_1 Parm1;
+ IPMI_BOOT_OPTIONS_RESPONSE_PARAMETER_2 Parm2;
+ IPMI_BOOT_OPTIONS_RESPONSE_PARAMETER_3 Parm3;
+ IPMI_BOOT_OPTIONS_RESPONSE_PARAMETER_4 Parm4;
+ IPMI_BOOT_OPTIONS_RESPONSE_PARAMETER_5 Parm5;
+ IPMI_BOOT_OPTIONS_RESPONSE_PARAMETER_6 Parm6;
+ IPMI_BOOT_OPTIONS_RESPONSE_PARAMETER_7 Parm7;
+} IPMI_BOOT_OPTIONS_PARAMETERS;
+
+typedef union {
+ struct {
+ UINT8 ParameterVersion : 4;
+ UINT8 Reserved : 4;
+ } Bits;
+ UINT8 Uint8;
+} IPMI_GET_BOOT_OPTIONS_PARAMETER_VERSION;
+
+typedef union {
+ struct {
+ UINT8 ParameterSelector : 7;
+ UINT8 ParameterValid : 1;
+ } Bits;
+ UINT8 Uint8;
+} IPMI_GET_BOOT_OPTIONS_PARAMETER_VALID;
+
+typedef struct {
+ UINT8 CompletionCode;
+ IPMI_GET_BOOT_OPTIONS_PARAMETER_VERSION ParameterVersion;
+ IPMI_GET_BOOT_OPTIONS_PARAMETER_VALID ParameterValid;
+ UINT8 ParameterData[0];
+} IPMI_GET_BOOT_OPTIONS_RESPONSE;
+
+//
+// Definitions for Set front panel button enables command
+//
+#define IPMI_CHASSIS_SET_FRONT_PANEL_BUTTON_ENABLES 0x0A
+
+//
+// Constants and Structure definitions for "Set front panel button enables" command to follow here
+//
+typedef union {
+ struct {
+ UINT8 DisablePoweroffButton : 1;
+ UINT8 DisableResetButton : 1;
+ UINT8 DisableDiagnosticInterruptButton : 1;
+ UINT8 DisableStandbyButton : 1;
+ UINT8 Reserved : 4;
+ } Bits;
+ UINT8 Uint8;
+} IPMI_FRONT_PANEL_BUTTON_ENABLES;
+
+typedef struct {
+ IPMI_FRONT_PANEL_BUTTON_ENABLES FrontPanelButtonEnables;
+} IPMI_CHASSIS_SET_FRONT_PANEL_BUTTON_ENABLES_REQUEST;
+
+//
+// Definitions for Set Power Cycle Interval command
+//
+#define IPMI_CHASSIS_SET_POWER_CYCLE_INTERVALS 0x0B
+
+//
+// Constants and Structure definitions for "Set Power Cycle Interval" command to follow here
+//
+
+//
+// Definitions for Get POH Counter command
+//
+#define IPMI_CHASSIS_GET_POH_COUNTER 0x0F
+
+//
+// Constants and Structure definitions for "Get POH Counter" command to follow here
+//
+#pragma pack()
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/IpmiNetFnFirmware.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/IpmiNetFnFirmware.h
new file mode 100644
index 0000000000..1761197835
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/IpmiNetFnFirmware.h
@@ -0,0 +1,38 @@
+/** @file
+ IPMI 2.0 definitions from the IPMI Specification Version 2.0, Revision 1.1.
+
+ Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _IPMI_NET_FN_FIRMWARE_H_
+#define _IPMI_NET_FN_FIRMWARE_H_
+
+//
+// Net function definition for Firmware command
+//
+#define IPMI_NETFN_FIRMWARE 0x08
+
+//
+// All Firmware commands and their structure definitions to follow here
+//
+
+// ----------------------------------------------------------------------------------------
+// Definitions for Get BMC Execution Context
+// ----------------------------------------------------------------------------------------
+#define IPMI_GET_BMC_EXECUTION_CONTEXT 0x23
+
+//
+// Constants and Structure definitions for "Get Device ID" command to follow here
+//
+typedef struct {
+ UINT8 CurrentExecutionContext;
+ UINT8 PartitionPointer;
+} IPMI_MSG_GET_BMC_EXEC_RSP;
+
+//
+// Current Execution Context responses
+//
+#define IPMI_BMC_IN_FORCED_UPDATE_MODE 0x11
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/IpmiNetFnGroupExtension.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/IpmiNetFnGroupExtension.h
new file mode 100644
index 0000000000..fbadfcd7f0
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/IpmiNetFnGroupExtension.h
@@ -0,0 +1,20 @@
+/** @file
+ IPMI 2.0 definitions from the IPMI Specification Version 2.0, Revision 1.1.
+
+ Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _IPMI_NET_FN_GROUP_EXTENSION_H_
+#define _IPMI_NET_FN_GROUP_EXTENSION_H_
+
+//
+// Net function definition for Group Extension command
+//
+#define IPMI_NETFN_GROUP_EXT 0x2C
+
+//
+// All Group Extension commands and their structure definitions to follow here
+//
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/IpmiNetFnSensorEvent.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/IpmiNetFnSensorEvent.h
new file mode 100644
index 0000000000..861e43df36
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/IpmiNetFnSensorEvent.h
@@ -0,0 +1,46 @@
+/** @file
+ IPMI 2.0 definitions from the IPMI Specification Version 2.0, Revision 1.1.
+
+ This file contains all NetFn Sensor/Event commands, including:
+ Event Commands (Chapter 29)
+ PEF and Alerting Commands (Chapter 30)
+ Sensor Device Commands (Chapter 35)
+
+ See IPMI specification, Appendix G, Command Assignments
+ and Appendix H, Sub-function Assignments.
+
+ Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _IPMI_NET_FN_SENSOR_EVENT_H_
+#define _IPMI_NET_FN_SENSOR_EVENT_H_
+
+#pragma pack(1)
+//
+// Net function definition for Sensor command
+//
+#define IPMI_NETFN_SENSOR_EVENT 0x04
+
+//
+// All Sensor commands and their structure definitions to follow here
+//
+
+//
+// Definitions for Send Platform Event Message command
+//
+#define IPMI_SENSOR_PLATFORM_EVENT_MESSAGE 0x02
+
+typedef struct {
+ UINT8 GeneratorId;
+ UINT8 EvMRevision;
+ UINT8 SensorType;
+ UINT8 SensorNumber;
+ UINT8 EventDirType;
+ UINT8 OEMEvData1;
+ UINT8 OEMEvData2;
+ UINT8 OEMEvData3;
+} IPMI_PLATFORM_EVENT_MESSAGE_DATA_REQUEST;
+
+#pragma pack()
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/IpmiNetFnStorage.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/IpmiNetFnStorage.h
new file mode 100644
index 0000000000..cb273133de
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/IpmiNetFnStorage.h
@@ -0,0 +1,783 @@
+/** @file
+ IPMI 2.0 definitions from the IPMI Specification Version 2.0, Revision 1.1.
+
+ This file contains all NetFn Storage commands, including:
+ FRU Inventory Commands (Chapter 34)
+ SDR Repository (Chapter 33)
+ System Event Log(SEL) Commands (Chapter 31)
+ SEL Record Formats (Chapter 32)
+
+ See IPMI specification, Appendix G, Command Assignments
+ and Appendix H, Sub-function Assignments.
+
+ Copyright (c) 1999 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _IPMI_NET_FN_STORAGE_H_
+#define _IPMI_NET_FN_STORAGE_H_
+
+#pragma pack(1)
+//
+// Net function definition for Storage command
+//
+#define IPMI_NETFN_STORAGE 0x0A
+
+//
+// All Storage commands and their structure definitions to follow here
+//
+
+//
+// Below is Definitions for FRU Inventory Commands (Chapter 34)
+//
+
+//
+// Definitions for Get Fru Inventory Area Info command
+//
+#define IPMI_STORAGE_GET_FRU_INVENTORY_AREAINFO 0x10
+
+//
+// Constants and Structure definitions for "Get Fru Inventory Area Info" command to follow here
+//
+typedef struct {
+ UINT8 DeviceId;
+} IPMI_GET_FRU_INVENTORY_AREA_INFO_REQUEST;
+
+typedef struct {
+ UINT8 CompletionCode;
+ UINT16 InventoryAreaSize;
+ UINT8 AccessType;
+} IPMI_GET_FRU_INVENTORY_AREA_INFO_RESPONSE;
+
+//
+// Definitions for Read Fru Data command
+//
+#define IPMI_STORAGE_READ_FRU_DATA 0x11
+
+//
+// Constants and Structure definitions for "Read Fru Data" command to follow here
+//
+typedef struct {
+ UINT8 FruDeviceId;
+ UINT16 FruOffset;
+} IPMI_FRU_COMMON_DATA;
+
+typedef struct {
+ IPMI_FRU_COMMON_DATA Data;
+ UINT8 Count;
+} IPMI_FRU_READ_COMMAND;
+
+typedef struct {
+ UINT8 DeviceId;
+ UINT16 InventoryOffset;
+ UINT8 CountToRead;
+} IPMI_READ_FRU_DATA_REQUEST;
+
+typedef struct {
+ UINT8 CompletionCode;
+ UINT8 CountReturned;
+ UINT8 Data[0];
+} IPMI_READ_FRU_DATA_RESPONSE;
+
+//
+// Definitions for Write Fru Data command
+//
+#define IPMI_STORAGE_WRITE_FRU_DATA 0x12
+
+//
+// Constants and Structure definitions for "Write Fru Data" command to follow here
+//
+typedef struct {
+ IPMI_FRU_COMMON_DATA Data;
+ UINT8 FruData[16];
+} IPMI_FRU_WRITE_COMMAND;
+
+typedef struct {
+ UINT8 DeviceId;
+ UINT16 InventoryOffset;
+ UINT8 Data[0];
+} IPMI_WRITE_FRU_DATA_REQUEST;
+
+typedef struct {
+ UINT8 CompletionCode;
+ UINT8 CountWritten;
+} IPMI_WRITE_FRU_DATA_RESPONSE;
+
+//
+// Below is Definitions for SDR Repository (Chapter 33)
+//
+
+//
+// Definitions for Get SDR Repository Info command
+//
+#define IPMI_STORAGE_GET_SDR_REPOSITORY_INFO 0x20
+
+//
+// Constants and Structure definitions for "Get SDR Repository Info" command to follow here
+//
+typedef union {
+ struct {
+ UINT8 SdrRepAllocInfoCmd : 1;
+ UINT8 SdrRepReserveCmd : 1;
+ UINT8 PartialAddSdrCmd : 1;
+ UINT8 DeleteSdrRepCmd : 1;
+ UINT8 Reserved : 1;
+ UINT8 SdrRepUpdateOp : 2;
+ UINT8 Overflow : 1;
+ } Bits;
+ UINT8 Uint8;
+} IPMI_SDR_OPERATION_SUPPORT;
+
+typedef struct {
+ UINT8 CompletionCode;
+ UINT8 Version;
+ UINT16 RecordCount;
+ UINT16 FreeSpace;
+ UINT32 RecentAdditionTimeStamp;
+ UINT32 RecentEraseTimeStamp;
+ IPMI_SDR_OPERATION_SUPPORT OperationSupport;
+} IPMI_GET_SDR_REPOSITORY_INFO_RESPONSE;
+
+//
+// Definitions for Get SDR Repository Allocateion Info command
+//
+#define IPMI_STORAGE_GET_SDR_REPOSITORY_ALLOCATION_INFO 0x21
+
+//
+// Constants and Structure definitions for "Get SDR Repository Allocateion Info" command to follow here
+//
+
+//
+// Definitions for Reserve SDR Repository command
+//
+#define IPMI_STORAGE_RESERVE_SDR_REPOSITORY 0x22
+
+//
+// Constants and Structure definitions for "Reserve SDR Repository" command to follow here
+//
+typedef struct {
+ UINT8 CompletionCode;
+ UINT8 ReservationId[2]; // Reservation ID. LS byte first.
+} IPMI_RESERVE_SDR_REPOSITORY_RESPONSE;
+
+//
+// Definitions for Get SDR command
+//
+#define IPMI_STORAGE_GET_SDR 0x23
+
+//
+// Constants and Structure definitions for "Get SDR" command to follow here
+//
+typedef union {
+ struct {
+ UINT8 EventScanningEnabled : 1;
+ UINT8 EventScanningDisabled : 1;
+ UINT8 InitSensorType : 1;
+ UINT8 InitHysteresis : 1;
+ UINT8 InitThresholds : 1;
+ UINT8 InitEvent : 1;
+ UINT8 InitScanning : 1;
+ UINT8 SettableSensor : 1;
+ } Bits;
+ UINT8 Uint8;
+} IPMI_SDR_RECORD_SENSOR_INIT;
+
+typedef union {
+ struct {
+ UINT8 EventMessageControl : 2;
+ UINT8 ThresholdAccessSupport : 2;
+ UINT8 HysteresisSupport : 2;
+ UINT8 ReArmSupport : 1;
+ UINT8 IgnoreSensor : 1;
+ } Bits;
+ UINT8 Uint8;
+} IPMI_SDR_RECORD_SENSOR_CAP;
+
+typedef union {
+ struct {
+ UINT8 Linearization : 7;
+ UINT8 Reserved : 1;
+ } Bits;
+ UINT8 Uint8;
+} IPMI_SDR_RECORD_LINEARIZATION;
+
+typedef union {
+ struct {
+ UINT8 Toleremce : 6;
+ UINT8 MHi : 2;
+ } Bits;
+ UINT8 Uint8;
+} IPMI_SDR_RECORD_M_TOLERANCE;
+
+typedef union {
+ struct {
+ UINT8 AccuracyLow : 6;
+ UINT8 BHi : 2;
+ } Bits;
+ UINT8 Uint8;
+} IPMI_SDR_RECORD_B_ACCURACY;
+
+typedef union {
+ struct {
+ UINT8 Reserved : 2;
+ UINT8 AccuracyExp : 2;
+ UINT8 AccuracyHi : 4;
+ } Bits;
+ UINT8 Uint8;
+} IPMI_SDR_RECORD_ACCURACY_SENSOR_DIR;
+
+typedef union {
+ struct {
+ UINT8 BExp : 4;
+ UINT8 RExp : 4;
+ } Bits;
+ UINT8 Uint8;
+} IPMI_SDR_RECORD_R_EXP_B_EXP;
+
+typedef union {
+ struct {
+ UINT8 NominalReadingSpscified : 1;
+ UINT8 NominalMaxSpscified : 1;
+ UINT8 NominalMinSpscified : 1;
+ UINT8 Reserved : 5;
+ } Bits;
+ UINT8 Uint8;
+} IPMI_SDR_RECORD_ANALOG_FLAGS;
+
+typedef struct {
+ UINT16 RecordId; // 1
+ UINT8 Version; // 3
+ UINT8 RecordType; // 4
+ UINT8 RecordLength; // 5
+ UINT8 OwnerId; // 6
+ UINT8 OwnerLun; // 7
+ UINT8 SensorNumber; // 8
+ UINT8 EntityId; // 9
+ UINT8 EntityInstance; // 10
+ IPMI_SDR_RECORD_SENSOR_INIT SensorInitialization; // 11
+ IPMI_SDR_RECORD_SENSOR_CAP SensorCapabilities; // 12
+ UINT8 SensorType; // 13
+ UINT8 EventType; // 14
+ UINT8 Reserved1[7]; // 15
+ UINT8 UnitType; // 22
+ UINT8 Reserved2; // 23
+ IPMI_SDR_RECORD_LINEARIZATION Linearization; // 24
+ UINT8 MLo; // 25
+ IPMI_SDR_RECORD_M_TOLERANCE MHiTolerance; // 26
+ UINT8 BLo; // 27
+ IPMI_SDR_RECORD_B_ACCURACY BHiAccuracyLo; // 28
+ IPMI_SDR_RECORD_ACCURACY_SENSOR_DIR AccuracySensorDirection; // 29
+ IPMI_SDR_RECORD_R_EXP_B_EXP RExpBExp; // 30
+ IPMI_SDR_RECORD_ANALOG_FLAGS AnalogFlags; // 31
+ UINT8 NominalReading; // 32
+ UINT8 Reserved3[4]; // 33
+ UINT8 UpperNonRecoverThreshold; // 37
+ UINT8 UpperCriticalThreshold; // 38
+ UINT8 UpperNonCriticalThreshold; // 39
+ UINT8 LowerNonRecoverThreshold; // 40
+ UINT8 LowerCriticalThreshold; // 41
+ UINT8 LowerNonCriticalThreshold; // 42
+ UINT8 Reserved4[5]; // 43
+ UINT8 IdStringLength; // 48
+ UINT8 AsciiIdString[16]; // 49 - 64
+} IPMI_SDR_RECORD_STRUCT_1;
+
+typedef struct {
+ UINT16 RecordId; // 1
+ UINT8 Version; // 3
+ UINT8 RecordType; // 4
+ UINT8 RecordLength; // 5
+ UINT8 OwnerId; // 6
+ UINT8 OwnerLun; // 7
+ UINT8 SensorNumber; // 8
+ UINT8 EntityId; // 9
+ UINT8 EntityInstance; // 10
+ IPMI_SDR_RECORD_SENSOR_INIT SensorInitialization; // 11
+ IPMI_SDR_RECORD_SENSOR_CAP SensorCapabilities; // 12
+ UINT8 SensorType; // 13
+ UINT8 EventType; // 14
+ UINT8 Reserved1[7]; // 15
+ UINT8 UnitType; // 22
+ UINT8 Reserved2[9]; // 23
+ UINT8 IdStringLength; // 32
+ UINT8 AsciiIdString[16]; // 33 - 48
+} IPMI_SDR_RECORD_STRUCT_2;
+
+typedef union {
+ struct {
+ UINT8 Reserved1 : 1;
+ UINT8 ControllerSlaveAddress : 7;
+ UINT8 FruDeviceId;
+ UINT8 BusId : 3;
+ UINT8 Lun : 2;
+ UINT8 Reserved2 : 2;
+ UINT8 LogicalFruDevice : 1;
+ UINT8 Reserved3 : 4;
+ UINT8 ChannelNumber : 4;
+ } Bits;
+ UINT32 Uint32;
+} IPMI_FRU_DATA_INFO;
+
+typedef union {
+ struct {
+ UINT8 Length : 4;
+ UINT8 Reserved : 1;
+ UINT8 StringType : 3;
+ } Bits;
+ UINT8 Uint8;
+} IPMI_SDR_RECORD_DEV_ID_STR_TYPE_LENGTH;
+
+typedef struct {
+ UINT16 RecordId; // 1
+ UINT8 Version; // 3
+ UINT8 RecordType; // 4
+ UINT8 RecordLength; // 5
+ IPMI_FRU_DATA_INFO FruDeviceData; // 6
+ UINT8 Reserved; // 10
+ UINT8 DeviceType; // 11
+ UINT8 DeviceTypeModifier; // 12
+ UINT8 FruEntityId; // 13
+ UINT8 FruEntityInstance; // 14
+ UINT8 OemReserved; // 15
+ IPMI_SDR_RECORD_DEV_ID_STR_TYPE_LENGTH StringTypeLength; // 16
+ UINT8 String[16]; // 17
+} IPMI_SDR_RECORD_STRUCT_11;
+
+typedef struct {
+ UINT16 RecordId; // 1
+ UINT8 Version; // 3
+ UINT8 RecordType; // 4
+ UINT8 RecordLength; // 5
+ UINT8 ManufacturerId[3]; // 6
+ UINT8 StringChars[20];
+} IPMI_SDR_RECORD_STRUCT_C0;
+
+typedef struct {
+ UINT16 RecordId; // 1
+ UINT8 Version; // 3
+ UINT8 RecordType; // 4
+ UINT8 RecordLength; // 5
+} IPMI_SDR_RECORD_STRUCT_HEADER;
+
+typedef union {
+ IPMI_SDR_RECORD_STRUCT_1 SensorType1;
+ IPMI_SDR_RECORD_STRUCT_2 SensorType2;
+ IPMI_SDR_RECORD_STRUCT_11 SensorType11;
+ IPMI_SDR_RECORD_STRUCT_C0 SensorTypeC0;
+ IPMI_SDR_RECORD_STRUCT_HEADER SensorHeader;
+} IPMI_SENSOR_RECORD_STRUCT;
+
+typedef struct {
+ UINT16 ReservationId;
+ UINT16 RecordId;
+ UINT8 RecordOffset;
+ UINT8 BytesToRead;
+} IPMI_GET_SDR_REQUEST;
+
+typedef struct {
+ UINT8 CompletionCode;
+ UINT16 NextRecordId;
+ IPMI_SENSOR_RECORD_STRUCT RecordData;
+} IPMI_GET_SDR_RESPONSE;
+
+//
+// Definitions for Add SDR command
+//
+#define IPMI_STORAGE_ADD_SDR 0x24
+
+//
+// Constants and Structure definitions for "Add SDR" command to follow here
+//
+
+//
+// Definitions for Partial Add SDR command
+//
+#define IPMI_STORAGE_PARTIAL_ADD_SDR 0x25
+
+//
+// Constants and Structure definitions for "Partial Add SDR" command to follow here
+//
+
+//
+// Definitions for Delete SDR command
+//
+#define IPMI_STORAGE_DELETE_SDR 0x26
+
+//
+// Constants and Structure definitions for "Delete SDR" command to follow here
+//
+
+//
+// Definitions for Clear SDR Repository command
+//
+#define IPMI_STORAGE_CLEAR_SDR 0x27
+
+//
+// Constants and Structure definitions for "Clear SDR Repository" command to follow here
+//
+
+//
+// Definitions for Get SDR Repository Time command
+//
+#define IPMI_STORAGE_GET_SDR_REPOSITORY_TIME 0x28
+
+//
+// Constants and Structure definitions for "Get SDR Repository Time" command to follow here
+//
+
+//
+// Definitions for Set SDR Repository Time command
+//
+#define IPMI_STORAGE_SET_SDR_REPOSITORY_TIME 0x29
+
+//
+// Constants and Structure definitions for "Set SDR Repository Time" command to follow here
+//
+
+//
+// Definitions for Enter SDR Repository Update Mode command
+//
+#define IPMI_STORAGE_ENTER_SDR_UPDATE_MODE 0x2A
+
+//
+// Constants and Structure definitions for "Enter SDR Repository Update Mode" command to follow here
+//
+
+//
+// Definitions for Exit SDR Repository Update Mode command
+//
+#define IPMI_STORAGE_EXIT_SDR_UPDATE_MODE 0x2B
+
+//
+// Constants and Structure definitions for "Exit SDR Repository Update Mode" command to follow here
+//
+
+//
+// Definitions for Run Initialize Agent command
+//
+#define IPMI_STORAGE_RUN_INIT_AGENT 0x2C
+
+//
+// Constants and Structure definitions for "Run Initialize Agent" command to follow here
+//
+
+//
+// Below is Definitions for System Event Log(SEL) Commands (Chapter 31)
+//
+
+//
+// Definitions for Get SEL Info command
+//
+#define IPMI_STORAGE_GET_SEL_INFO 0x40
+
+//
+// Constants and Structure definitions for "Get SEL Info" command to follow here
+//
+#define IPMI_GET_SEL_INFO_OPERATION_SUPPORT_GET_SEL_ALLOCATION_INFO_CMD BIT0
+#define IPMI_GET_SEL_INFO_OPERATION_SUPPORT_RESERVE_SEL_CMD BIT1
+#define IPMI_GET_SEL_INFO_OPERATION_SUPPORT_PARTIAL_ADD_SEL_ENTRY_CMD BIT2
+#define IPMI_GET_SEL_INFO_OPERATION_SUPPORT_DELETE_SEL_CMD BIT3
+#define IPMI_GET_SEL_INFO_OPERATION_SUPPORT_OVERFLOW_FLAG BIT7
+
+typedef struct {
+ UINT8 CompletionCode;
+ UINT8 Version; // Version of SEL
+ UINT16 NoOfEntries; // No of Entries in the SEL
+ UINT16 FreeSpace; // Free space in Bytes
+ UINT32 RecentAddTimeStamp; // Most Recent Addition of Time Stamp
+ UINT32 RecentEraseTimeStamp; // Most Recent Erasure of Time Stamp
+ UINT8 OperationSupport; // Operation Support
+} IPMI_GET_SEL_INFO_RESPONSE;
+
+//
+// Definitions for Get SEL Allocation Info command
+//
+#define IPMI_STORAGE_GET_SEL_ALLOCATION_INFO 0x41
+
+//
+// Constants and Structure definitions for "Get SEL Allocation Info" command to follow here
+//
+
+//
+// Definitions for Reserve SEL command
+//
+#define IPMI_STORAGE_RESERVE_SEL 0x42
+
+//
+// Constants and Structure definitions for "Reserve SEL" command to follow here
+//
+typedef struct {
+ UINT8 CompletionCode;
+ UINT8 ReservationId[2]; // Reservation ID. LS byte first.
+} IPMI_RESERVE_SEL_RESPONSE;
+
+//
+// Definitions for Get SEL Entry command
+//
+#define IPMI_STORAGE_GET_SEL_ENTRY 0x43
+
+//
+// Constants and Structure definitions for "Get SEL Entry" command to follow here
+//
+
+//
+// Below is Definitions for SEL Record Formats (Chapter 32)
+//
+typedef struct {
+ UINT16 RecordId;
+ UINT8 RecordType;
+ UINT32 TimeStamp;
+ UINT16 GeneratorId;
+ UINT8 EvMRevision;
+ UINT8 SensorType;
+ UINT8 SensorNumber;
+ UINT8 EventDirType;
+ UINT8 OEMEvData1;
+ UINT8 OEMEvData2;
+ UINT8 OEMEvData3;
+} IPMI_SEL_EVENT_RECORD_DATA;
+
+typedef struct {
+ UINT16 RecordId;
+ UINT8 RecordType; // C0h-DFh = OEM system event record
+ UINT32 TimeStamp;
+ UINT8 ManufacturerId[3];
+ UINT8 OEMDefined[6];
+} IPMI_TIMESTAMPED_OEM_SEL_RECORD_DATA;
+
+typedef struct {
+ UINT16 RecordId;
+ UINT8 RecordType; // E0h-FFh = OEM system event record
+ UINT8 OEMDefined[13];
+} IPMI_NON_TIMESTAMPED_OEM_SEL_RECORD_DATA;
+
+typedef struct {
+ UINT8 ReserveId[2]; // Reservation ID, LS Byte First
+ UINT8 SelRecID[2]; // Sel Record ID, LS Byte First
+ UINT8 Offset; // Offset Into Record
+ UINT8 BytesToRead; // Bytes to be Read, 0xFF for entire record
+} IPMI_GET_SEL_ENTRY_REQUEST;
+
+typedef struct {
+ UINT8 CompletionCode;
+ UINT16 NextSelRecordId; // Next SEL Record ID, LS Byte first
+ IPMI_SEL_EVENT_RECORD_DATA RecordData;
+} IPMI_GET_SEL_ENTRY_RESPONSE;
+
+//
+// Definitions for Add SEL Entry command
+//
+#define IPMI_STORAGE_ADD_SEL_ENTRY 0x44
+
+//
+// Constants and Structure definitions for "Add SEL Entry" command to follow here
+//
+typedef struct {
+ IPMI_SEL_EVENT_RECORD_DATA RecordData;
+} IPMI_ADD_SEL_ENTRY_REQUEST;
+
+typedef struct {
+ UINT8 CompletionCode;
+ UINT16 RecordId; // Record ID for added record, LS Byte first
+} IPMI_ADD_SEL_ENTRY_RESPONSE;
+
+//
+// Definitions for Partial Add SEL Entry command
+//
+#define IPMI_STORAGE_PARTIAL_ADD_SEL_ENTRY 0x45
+
+//
+// Constants and Structure definitions for "Partial Add SEL Entry" command to follow here
+//
+typedef struct {
+ UINT16 ReservationId;
+ UINT16 RecordId;
+ UINT8 OffsetIntoRecord;
+ UINT8 InProgress;
+ UINT8 RecordData[0];
+} IPMI_PARTIAL_ADD_SEL_ENTRY_REQUEST;
+
+typedef struct {
+ UINT8 CompletionCode;
+ UINT16 RecordId;
+} IPMI_PARTIAL_ADD_SEL_ENTRY_RESPONSE;
+
+//
+// Definitions for Delete SEL Entry command
+//
+#define IPMI_STORAGE_DELETE_SEL_ENTRY 0x46
+
+//
+// Constants and Structure definitions for "Delete SEL Entry" command to follow here
+//
+typedef struct {
+ UINT8 ReserveId[2]; // Reservation ID, LS byte first
+ UINT8 RecordToDelete[2]; // Record to Delete, LS Byte First
+} IPMI_DELETE_SEL_ENTRY_REQUEST;
+
+#define IPMI_DELETE_SEL_ENTRY_RESPONSE_TYPE_UNSUPPORTED 0x80
+#define IPMI_DELETE_SEL_ENTRY_RESPONSE_ERASE_IN_PROGRESS 0x81
+
+typedef struct {
+ UINT8 CompletionCode;
+ UINT16 RecordId; // Record ID added. LS byte first
+} IPMI_DELETE_SEL_ENTRY_RESPONSE;
+
+//
+// Definitions for Clear SEL command
+//
+#define IPMI_STORAGE_CLEAR_SEL 0x47
+
+//
+// Constants and Structure definitions for "Clear SEL" command to follow here
+//
+#define IPMI_CLEAR_SEL_REQUEST_C_CHAR_ASCII 0x43
+#define IPMI_CLEAR_SEL_REQUEST_L_CHAR_ASCII 0x4C
+#define IPMI_CLEAR_SEL_REQUEST_R_CHAR_ASCII 0x52
+#define IPMI_CLEAR_SEL_REQUEST_INITIALIZE_ERASE 0xAA
+#define IPMI_CLEAR_SEL_REQUEST_GET_ERASE_STATUS 0x00
+
+typedef struct {
+ UINT8 Reserve[2]; // Reserve ID, LSB first
+ UINT8 AscC; // Ascii for 'C' (0x43)
+ UINT8 AscL; // Ascii for 'L' (0x4c)
+ UINT8 AscR; // Ascii for 'R' (0x52)
+ UINT8 Erase; // 0xAA, Initiate Erase, 0x00 Get Erase Status
+} IPMI_CLEAR_SEL_REQUEST;
+
+#define IPMI_CLEAR_SEL_RESPONSE_ERASURE_IN_PROGRESS 0x00
+#define IPMI_CLEAR_SEL_RESPONSE_ERASURE_COMPLETED 0x01
+
+typedef struct {
+ UINT8 CompletionCode;
+ UINT8 ErasureProgress;
+} IPMI_CLEAR_SEL_RESPONSE;
+
+//
+// Definitions for Get SEL Time command
+//
+#define IPMI_STORAGE_GET_SEL_TIME 0x48
+
+//
+// Constants and Structure definitions for "Get SEL Time" command to follow here
+//
+typedef struct {
+ UINT8 CompletionCode;
+ UINT32 Timestamp; // Present Timestamp clock reading. LS byte first.
+} IPMI_GET_SEL_TIME_RESPONSE;
+
+//
+// Definitions for Set SEL Time command
+//
+#define IPMI_STORAGE_SET_SEL_TIME 0x49
+
+//
+// Constants and Structure definitions for "Set SEL Time" command to follow here
+//
+typedef struct {
+ UINT32 Timestamp;
+} IPMI_SET_SEL_TIME_REQUEST;
+
+//
+// Definitions for Get Auxillary Log Status command
+//
+#define IPMI_STORAGE_GET_AUXILLARY_LOG_STATUS 0x5A
+
+//
+// Constants and Structure definitions for "Get Auxillary Log Status" command to follow here
+//
+
+//
+// Definitions for Set Auxillary Log Status command
+//
+#define IPMI_STORAGE_SET_AUXILLARY_LOG_STATUS 0x5B
+
+//
+// Constants and Structure definitions for "Set Auxillary Log Status" command to follow here
+//
+
+//
+// Definitions for Get SEL Time UTC Offset command
+//
+#define IPMI_STORAGE_GET_SEL_TIME_UTC_OFFSET 0x5C
+
+//
+// Constants and Structure definitions for "Get SEL Time UTC Offset" command to follow here
+//
+typedef struct {
+ UINT8 CompletionCode;
+ //
+ // 16-bit, 2s-complement signed integer for the offset in minutes from UTC to SEL Time.
+ // LS-byte first. (ranges from -1440 to 1440)
+ //
+ INT16 UtcOffset;
+} IPMI_GET_SEL_TIME_UTC_OFFSET_RESPONSE;
+
+//
+// Definitions for Set SEL Time UTC Offset command
+//
+#define IPMI_STORAGE_SET_SEL_TIME_UTC_OFFSET 0x5D
+
+//
+// Constants and Structure definitions for "Set SEL Time UTC Offset" command to follow here
+//
+
+#define IPMI_COMPLETE_SEL_RECORD 0xFF
+
+#define IPMI_SEL_SYSTEM_RECORD 0x02
+#define IPMI_SEL_OEM_TIME_STAMP_RECORD_START 0xC0
+#define IPMI_SEL_OEM_TIME_STAMP_RECORD_END 0xDF
+#define IPMI_SEL_OEM_NO_TIME_STAMP_RECORD_START 0xE0
+#define IPMI_SEL_OEM_NO_TIME_STAMP_RECORD_END 0xFF
+
+#define IPMI_SEL_EVENT_DIR(EventDirType) (EventDirType >> 7)
+#define IPMI_SEL_EVENT_DIR_ASSERTION_EVENT 0x00
+#define IPMI_SEL_EVENT_DIR_DEASSERTION_EVENT 0x01
+
+#define IPMI_SEL_EVENT_TYPE(EventDirType) (EventDirType & 0x7F)
+//
+// Event/Reading Type Code Ranges (Chapter 42)
+//
+#define IPMI_SEL_EVENT_TYPE_UNSPECIFIED 0x00
+#define IPMI_SEL_EVENT_TYPE_THRESHOLD 0x01
+#define IPMI_SEL_EVENT_TYPE_GENERIC_START 0x02
+#define IPMI_SEL_EVENT_TYPE_GENERIC_END 0x0C
+#define IPMI_SEL_EVENT_TYPE_SENSOR_SPECIFIC 0x6F
+#define IPMI_SEL_EVENT_TYPE_OEM_START 0x70
+#define IPMI_SEL_EVENT_TYPE_OEM_END 0x7F
+
+#define SOFTWARE_ID_FROM_GENERATOR_ID(GeneratorId) ((GeneratorId & 0xFF) >> 1)
+//
+// System Software IDs definitions (Section 5.5)
+//
+#define IPMI_SWID_BIOS_RANGE_START 0x00
+#define IPMI_SWID_BIOS_RANGE_END 0x0F
+#define IPMI_SWID_SMI_HANDLER_RANGE_START 0x10
+#define IPMI_SWID_SMI_HANDLER_RANGE_END 0x1F
+#define IPMI_SWID_SMS_RANGE_START 0x20
+#define IPMI_SWID_SMS_RANGE_END 0x2F
+#define IPMI_SWID_OEM_RANGE_START 0x30
+#define IPMI_SWID_OEM_RANGE_END 0x3F
+#define IPMI_SWID_REMOTE_CONSOLE_RANGE_START 0x40
+#define IPMI_SWID_REMOTE_CONSOLE_RANGE_END 0x46
+#define IPMI_SWID_TERMINAL_REMOTE_CONSOLE_ID 0x47
+
+#define SLAVE_ADDRESS_FROM_GENERATOR_ID(GeneratorId) ((GeneratorId & 0xFF) >> 1)
+#define LUN_FROM_GENERATOR_ID(GeneratorId) ((GeneratorId >> 8) & 0x03)
+#define CHANNEL_NUMBER_FROM_GENERATOR_ID(GeneratorId) ((GeneratorId >> 12) & 0x0F)
+
+#define IPMI_EVM_REVISION 0x04
+#define IPMI_BIOS_ID 0x18
+#define IPMI_FORMAT_REV 0x00
+#define IPMI_FORMAT_REV1 0x01
+#define IPMI_SOFTWARE_ID 0x01
+#define IPMI_PLATFORM_VAL_ID 0x01
+#define IPMI_GENERATOR_ID(i, f) ((i << 1) | (f << 1) | IPMI_SOFTWARE_ID)
+
+#define IPMI_SENSOR_TYPE_EVENT_CODE_DISCRETE 0x6F
+
+#define IPMI_OEM_SPECIFIC_DATA 0x02
+#define IPMI_SENSOR_SPECIFIC_DATA 0x03
+
+#pragma pack()
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/IpmiNetFnTransport.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/IpmiNetFnTransport.h
new file mode 100644
index 0000000000..58046432eb
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/IpmiNetFnTransport.h
@@ -0,0 +1,916 @@
+/** @file
+ IPMI 2.0 definitions from the IPMI Specification Version 2.0, Revision 1.1.
+
+ This file contains all NetFn Transport commands, including:
+ IPM LAN Commands (Chapter 23)
+ IPMI Serial/Modem Commands (Chapter 25)
+ SOL Commands (Chapter 26)
+ Command Forwarding Commands (Chapter 35b)
+
+ See IPMI specification, Appendix G, Command Assignments
+ and Appendix H, Sub-function Assignments.
+
+ Copyright (c) 1999 - 2018, Intel Corporation. All rights reserved.
+ Copyright (C) 2023 Advanced Micro Devices, Inc. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _IPMI_NET_FN_TRANSPORT_H_
+#define _IPMI_NET_FN_TRANSPORT_H_
+
+#pragma pack(1)
+//
+// Net function definition for Transport command
+//
+#define IPMI_NETFN_TRANSPORT 0x0C
+
+//
+// Below is Definitions for IPM LAN Commands (Chapter 23)
+//
+
+//
+// Definitions for Set Lan Configuration Parameters command
+//
+#define IPMI_TRANSPORT_SET_LAN_CONFIG_PARAMETERS 0x01
+
+//
+// Constants and Structure definitions for "Set Lan Configuration Parameters" command to follow here
+//
+
+//
+// LAN Management Structure
+//
+typedef enum {
+ IpmiLanReserved1,
+ IpmiLanReserved2,
+ IpmiLanAuthType,
+ IpmiLanIpAddress,
+ IpmiLanIpAddressSource,
+ IpmiLanMacAddress,
+ IpmiLanSubnetMask,
+ IpmiLanIpv4HeaderParam,
+ IpmiLanPrimaryRcmpPort,
+ IpmiLanSecondaryRcmpPort,
+ IpmiLanBmcGeneratedArpCtrl,
+ IpmiLanArpInterval,
+ IpmiLanDefaultGateway,
+ IpmiLanDefaultGatewayMac,
+ IpmiLanBackupGateway,
+ IpmiLanBackupGatewayMac,
+ IpmiLanCommunityString,
+ IpmiLanReserved3,
+ IpmiLanDestinationType,
+ IpmiLanDestinationAddress,
+ IpmiLanVlanId = 0x14,
+ IpmiIpv4OrIpv6Support = 0x32,
+ IpmiIpv4OrIpv6AddressEnable,
+ IpmiIpv6HdrStatTrafficClass,
+ IpmiIpv6HdrStatHopLimit,
+ IpmiIpv6HdrFlowLabel,
+ IpmiIpv6Status,
+ IpmiIpv6StaticAddress,
+ IpmiIpv6DhcpStaticDuidLen,
+ IpmiIpv6DhcpStaticDuid,
+ IpmiIpv6DhcpAddress,
+ IpmiIpv6DhcpDynamicDuidLen,
+ IpmiIpv6DhcpDynamicDuid,
+ IpmiIpv6RouterConfig = 0x40,
+ IpmiIpv6StaticRouter1IpAddr,
+ IpmiIpv6DynamicRouterIpAddr = 0x4a
+} IPMI_LAN_OPTION_TYPE;
+
+//
+// IP Address Source
+//
+typedef enum {
+ IpmiUnspecified,
+ IpmiStaticAddrsss,
+ IpmiDynamicAddressBmcDhcp,
+ IpmiDynamicAddressBiosDhcp,
+ IpmiDynamicAddressBmcNonDhcp
+} IPMI_IP_ADDRESS_SRC;
+
+//
+// Destination Type
+//
+typedef enum {
+ IpmiPetTrapDestination,
+ IpmiDirectedEventDestination,
+ IpmiReserved1,
+ IpmiReserved2,
+ IpmiReserved3,
+ IpmiReserved4,
+ IpmiReserved5,
+ IpmiOem1,
+ IpmiOem2
+} IPMI_LAN_DEST_TYPE_DEST_TYPE;
+
+//
+// Destination address format
+//
+typedef enum {
+ IpmiDestinationAddressVersion4,
+ IpmiDestinationAddressVersion6
+} IPMI_LAN_DEST_ADDRESS_VERSION;
+
+typedef union {
+ struct {
+ UINT8 NoAuth : 1;
+ UINT8 MD2Auth : 1;
+ UINT8 MD5Auth : 1;
+ UINT8 Reserved1 : 1;
+ UINT8 StraightPswd : 1;
+ UINT8 OemType : 1;
+ UINT8 Reserved2 : 2;
+ } Bits;
+ UINT8 Uint8;
+} IPMI_LAN_AUTH_TYPE;
+
+typedef struct {
+ UINT8 IpAddress[4];
+} IPMI_LAN_IP_ADDRESS;
+
+typedef union {
+ struct {
+ UINT8 AddressSrc : 4;
+ UINT8 Reserved : 4;
+ } Bits;
+ UINT8 Uint8;
+} IPMI_LAN_IP_ADDRESS_SRC;
+
+typedef struct {
+ UINT8 MacAddress[6];
+} IPMI_LAN_MAC_ADDRESS;
+
+typedef struct {
+ UINT8 IpAddress[4];
+} IPMI_LAN_SUBNET_MASK;
+
+typedef union {
+ struct {
+ UINT8 IpFlag : 3;
+ UINT8 Reserved : 5;
+ } Bits;
+ UINT8 Uint8;
+} IPMI_LAN_IPV4_HDR_PARAM_DATA_2;
+
+typedef union {
+ struct {
+ UINT8 Precedence : 3;
+ UINT8 Reserved : 1;
+ UINT8 ServiceType : 4;
+ } Bits;
+ UINT8 Uint8;
+} IPMI_LAN_IPV4_HDR_PARAM_DATA_3;
+
+typedef struct {
+ UINT8 TimeToLive;
+ IPMI_LAN_IPV4_HDR_PARAM_DATA_2 Data2;
+ IPMI_LAN_IPV4_HDR_PARAM_DATA_3 Data3;
+} IPMI_LAN_IPV4_HDR_PARAM;
+
+typedef struct {
+ UINT8 RcmpPortMsb;
+ UINT8 RcmpPortLsb;
+} IPMI_LAN_RCMP_PORT;
+
+typedef union {
+ struct {
+ UINT8 EnableBmcArpResponse : 1;
+ UINT8 EnableBmcGratuitousArp : 1;
+ UINT8 Reserved : 6;
+ } Bits;
+ UINT8 Uint8;
+} IPMI_LAN_BMC_GENERATED_ARP_CONTROL;
+
+typedef struct {
+ UINT8 ArpInterval;
+} IPMI_LAN_ARP_INTERVAL;
+
+typedef struct {
+ UINT8 IpAddress[4];
+} IPMI_LAN_DEFAULT_GATEWAY;
+
+typedef struct {
+ UINT8 Data[18];
+} IPMI_LAN_COMMUNITY_STRING;
+
+typedef union {
+ struct {
+ UINT8 DestinationSelector : 4;
+ UINT8 Reserved : 4;
+ } Bits;
+ UINT8 Uint8;
+} IPMI_LAN_SET_SELECTOR;
+
+typedef union {
+ struct {
+ UINT8 DestinationType : 3;
+ UINT8 Reserved : 4;
+ UINT8 AlertAcknowledged : 1;
+ } Bits;
+ UINT8 Uint8;
+} IPMI_LAN_DEST_TYPE_DESTINATION_TYPE;
+
+typedef struct {
+ IPMI_LAN_SET_SELECTOR SetSelector;
+ IPMI_LAN_DEST_TYPE_DESTINATION_TYPE DestinationType;
+} IPMI_LAN_DEST_TYPE;
+
+typedef union {
+ struct {
+ UINT8 AlertingIpAddressSelector : 4;
+ UINT8 AddressFormat : 4;
+ } Bits;
+ UINT8 Uint8;
+} IPMI_LAN_ADDRESS_FORMAT;
+
+typedef union {
+ struct {
+ UINT8 UseDefaultGateway : 1;
+ UINT8 Reserved2 : 7;
+ } Bits;
+ UINT8 Uint8;
+} IPMI_LAN_GATEWAY_SELECTOR;
+
+typedef struct {
+ IPMI_LAN_SET_SELECTOR SetSelector;
+ IPMI_LAN_ADDRESS_FORMAT AddressFormat;
+ IPMI_LAN_GATEWAY_SELECTOR GatewaySelector;
+ IPMI_LAN_IP_ADDRESS AlertingIpAddress;
+ IPMI_LAN_MAC_ADDRESS AlertingMacAddress;
+} IPMI_LAN_DEST_ADDRESS;
+
+typedef struct {
+ UINT8 VanIdLowByte;
+} IPMI_LAN_VLAN_ID_DATA1;
+
+typedef union {
+ struct {
+ UINT8 VanIdHighByte : 4;
+ UINT8 Reserved : 3;
+ UINT8 Enabled : 1;
+ } Bits;
+ UINT8 Uint8;
+} IPMI_LAN_VLAN_ID_DATA2;
+
+typedef struct {
+ IPMI_LAN_VLAN_ID_DATA1 Data1;
+ IPMI_LAN_VLAN_ID_DATA2 Data2;
+} IPMI_LAN_VLAN_ID;
+
+typedef union {
+ IPMI_LAN_AUTH_TYPE IpmiLanAuthType;
+ IPMI_LAN_IP_ADDRESS IpmiLanIpAddress;
+ IPMI_LAN_IP_ADDRESS_SRC IpmiLanIpAddressSrc;
+ IPMI_LAN_MAC_ADDRESS IpmiLanMacAddress;
+ IPMI_LAN_SUBNET_MASK IpmiLanSubnetMask;
+ IPMI_LAN_IPV4_HDR_PARAM IpmiLanIpv4HdrParam;
+ IPMI_LAN_RCMP_PORT IpmiLanPrimaryRcmpPort;
+ IPMI_LAN_BMC_GENERATED_ARP_CONTROL IpmiLanArpControl;
+ IPMI_LAN_ARP_INTERVAL IpmiLanArpInterval;
+ IPMI_LAN_COMMUNITY_STRING IpmiLanCommunityString;
+ IPMI_LAN_DEST_TYPE IpmiLanDestType;
+ IPMI_LAN_DEST_ADDRESS IpmiLanDestAddress;
+} IPMI_LAN_OPTIONS;
+
+typedef union {
+ struct {
+ UINT8 AddressSourceType : 4;
+ UINT8 Reserved : 3;
+ UINT8 EnableStatus : 1;
+ } Bits;
+ UINT8 Uint8;
+} IPMI_LAN_IPV6_ADDRESS_SOURCE_TYPE;
+
+typedef struct {
+ UINT8 SetSelector;
+ IPMI_LAN_IPV6_ADDRESS_SOURCE_TYPE AddressSourceType;
+ UINT8 Ipv6Address[16];
+ UINT8 AddressPrefixLen;
+ UINT8 AddressStatus;
+} IPMI_LAN_IPV6_STATIC_ADDRESS;
+
+//
+// Set in progress parameter
+//
+typedef union {
+ struct {
+ UINT8 SetInProgress : 2;
+ UINT8 Reserved : 6;
+ } Bits;
+ UINT8 Uint8;
+} IPMI_LAN_SET_IN_PROGRESS;
+
+typedef union {
+ struct {
+ UINT8 ChannelNo : 4;
+ UINT8 Reserved : 4;
+ } Bits;
+ UINT8 Uint8;
+} IPMI_SET_LAN_CONFIG_CHANNEL_NUM;
+
+typedef struct {
+ IPMI_SET_LAN_CONFIG_CHANNEL_NUM ChannelNumber;
+ UINT8 ParameterSelector;
+ UINT8 ParameterData[0];
+} IPMI_SET_LAN_CONFIGURATION_PARAMETERS_COMMAND_REQUEST;
+
+//
+// Definitions for Get Lan Configuration Parameters command
+//
+#define IPMI_TRANSPORT_GET_LAN_CONFIG_PARAMETERS 0x02
+
+//
+// Constants and Structure definitions for "Get Lan Configuration Parameters" command to follow here
+//
+typedef union {
+ struct {
+ UINT8 ChannelNo : 4;
+ UINT8 Reserved : 3;
+ UINT8 GetParameter : 1;
+ } Bits;
+ UINT8 Uint8;
+} IPMI_GET_LAN_CONFIG_CHANNEL_NUM;
+
+typedef struct {
+ IPMI_GET_LAN_CONFIG_CHANNEL_NUM ChannelNumber;
+ UINT8 ParameterSelector;
+ UINT8 SetSelector;
+ UINT8 BlockSelector;
+} IPMI_GET_LAN_CONFIGURATION_PARAMETERS_REQUEST;
+
+typedef struct {
+ UINT8 CompletionCode;
+ UINT8 ParameterRevision;
+ UINT8 ParameterData[0];
+} IPMI_GET_LAN_CONFIGURATION_PARAMETERS_RESPONSE;
+
+//
+// Definitions for Suspend BMC ARPs command
+//
+#define IPMI_TRANSPORT_SUSPEND_BMC_ARPS 0x03
+
+//
+// Constants and Structure definitions for "Suspend BMC ARPs" command to follow here
+//
+
+//
+// Definitions for Get IP-UDP-RMCP Statistics command
+//
+#define IPMI_TRANSPORT_GET_PACKET_STATISTICS 0x04
+
+//
+// Constants and Structure definitions for "Get IP-UDP-RMCP Statistics" command to follow here
+//
+
+//
+// Below is Definitions for IPMI Serial/Modem Commands (Chapter 25)
+//
+
+//
+// Definitions for Set Serial/Modem Configuration command
+//
+#define IPMI_TRANSPORT_SET_SERIAL_CONFIGURATION 0x10
+
+//
+// Constants and Structure definitions for "Set Serial/Modem Configuration" command to follow here
+//
+
+//
+// EMP OPTION DATA
+//
+typedef union {
+ struct {
+ UINT8 NoAuthentication : 1;
+ UINT8 MD2Authentication : 1;
+ UINT8 MD5Authentication : 1;
+ UINT8 Reserved1 : 1;
+ UINT8 StraightPassword : 1;
+ UINT8 OemProprietary : 1;
+ UINT8 Reservd2 : 2;
+ } Bits;
+ UINT8 Uint8;
+} IPMI_EMP_AUTH_TYPE;
+
+typedef union {
+ struct {
+ UINT8 EnableBasicMode : 1;
+ UINT8 EnablePPPMode : 1;
+ UINT8 EnableTerminalMode : 1;
+ UINT8 Reserved1 : 2;
+ UINT8 SnoopOsPPPNegotiation : 1;
+ UINT8 Reserved2 : 1;
+ UINT8 DirectConnect : 1;
+ } Bits;
+ UINT8 Uint8;
+} IPMI_EMP_CONNECTION_TYPE;
+
+typedef union {
+ struct {
+ UINT8 InactivityTimeout : 4;
+ UINT8 Reserved : 4;
+ } Bits;
+ UINT8 Uint8;
+} IPMI_EMP_INACTIVITY_TIMEOUT;
+
+typedef union {
+ struct {
+ UINT8 IpmiCallback : 1;
+ UINT8 CBCPCallback : 1;
+ UINT8 Reserved : 6;
+ } Bits;
+ UINT8 Uint8;
+} IPMI_CHANNEL_CALLBACK_CONTROL_ENABLE;
+
+typedef union {
+ struct {
+ UINT8 CbcpEnableNoCallback : 1;
+ UINT8 CbcpEnablePreSpecifiedNumber : 1;
+ UINT8 CbcpEnableUserSpecifiedNumber : 1;
+ UINT8 CbcpEnableCallbackFromList : 1;
+ UINT8 Reserved : 4;
+ } Bits;
+ UINT8 Uint8;
+} IPMI_CHANNEL_CALLBACK_CONTROL_CBCP;
+
+typedef struct {
+ IPMI_CHANNEL_CALLBACK_CONTROL_ENABLE CallbackEnable;
+ IPMI_CHANNEL_CALLBACK_CONTROL_CBCP CBCPNegotiation;
+ UINT8 CallbackDestination1;
+ UINT8 CallbackDestination2;
+ UINT8 CallbackDestination3;
+} IPMI_EMP_CHANNEL_CALLBACK_CONTROL;
+
+typedef union {
+ struct {
+ UINT8 CloseSessionOnDCDLoss : 1;
+ UINT8 EnableSessionInactivityTimeout : 1;
+ UINT8 Reserved : 6;
+ } Bits;
+ UINT8 Uint8;
+} IPMI_EMP_SESSION_TERMINATION;
+
+typedef union {
+ struct {
+ UINT8 Reserved1 : 5;
+ UINT8 EnableDtrHangup : 1;
+ UINT8 FlowControl : 2;
+ UINT8 BitRate : 4;
+ UINT8 Reserved2 : 4;
+ UINT8 SaveSetting : 1;
+ UINT8 SetComPort : 1;
+ UINT8 Reserved3 : 6;
+ } Bits;
+ UINT8 Uint8;
+ UINT16 Uint16;
+} IPMI_EMP_MESSAGING_COM_SETTING;
+
+typedef union {
+ struct {
+ UINT8 RingDurationInterval : 6;
+ UINT8 Reserved1 : 2;
+ UINT8 RingDeadTime : 4;
+ UINT8 Reserved2 : 4;
+ } Bits;
+ UINT8 Uint8;
+} IPMI_EMP_MODEM_RING_TIME;
+
+typedef struct {
+ UINT8 Reserved;
+ UINT8 InitString[48];
+} IPMI_EMP_MODEM_INIT_STRING;
+
+typedef struct {
+ UINT8 EscapeSequence[5];
+} IPMI_EMP_MODEM_ESC_SEQUENCE;
+
+typedef struct {
+ UINT8 HangupSequence[8];
+} IPMI_EMP_MODEM_HANGUP_SEQUENCE;
+
+typedef struct {
+ UINT8 ModelDialCommend[8];
+} IPMI_MODEM_DIALUP_COMMAND;
+
+typedef struct {
+ UINT8 PageBlackoutInterval;
+} IPMI_PAGE_BLACKOUT_INTERVAL;
+
+typedef struct {
+ UINT8 CommunityString[18];
+} IPMI_EMP_COMMUNITY_STRING;
+
+typedef union {
+ struct {
+ UINT8 Reserved : 4;
+ UINT8 DialStringSelector : 4;
+ } Bits;
+ UINT8 Uint8;
+} IPMI_DIAL_PAGE_DESTINATION;
+
+typedef union {
+ struct {
+ UINT8 TapAccountSelector : 4;
+ UINT8 Reserved : 4;
+ } Bits;
+ UINT8 Uint8;
+} IPMI_TAP_PAGE_DESTINATION;
+
+typedef struct {
+ UINT8 PPPAccountSetSelector;
+ UINT8 DialStringSelector;
+} IPMI_PPP_ALERT_DESTINATION;
+
+typedef union {
+ IPMI_DIAL_PAGE_DESTINATION DialPageDestination;
+ IPMI_TAP_PAGE_DESTINATION TapPageDestination;
+ IPMI_PPP_ALERT_DESTINATION PppAlertDestination;
+} IPMI_DEST_TYPE_SPECIFIC;
+
+typedef union {
+ struct {
+ UINT8 DestinationSelector : 4;
+ UINT8 Reserved : 4;
+ } Bits;
+ UINT8 Uint8;
+} IPMI_EMP_DESTINATION_SELECTOR;
+
+typedef union {
+ struct {
+ UINT8 DestinationType : 4;
+ UINT8 Reserved : 3;
+ UINT8 AlertAckRequired : 1;
+ } Bits;
+ UINT8 Uint8;
+} IPMI_EMP_DESTINATION_TYPE;
+
+typedef union {
+ struct {
+ UINT8 NumRetriesCall : 3;
+ UINT8 Reserved1 : 1;
+ UINT8 NumRetryAlert : 3;
+ UINT8 Reserved2 : 1;
+ } Bits;
+ UINT8 Uint8;
+} IPMI_EMP_RETRIES;
+
+typedef struct {
+ IPMI_EMP_DESTINATION_SELECTOR DestinationSelector;
+ IPMI_EMP_DESTINATION_TYPE DestinationType;
+ UINT8 AlertAckTimeoutSeconds;
+ IPMI_EMP_RETRIES Retries;
+ IPMI_DEST_TYPE_SPECIFIC DestinationTypeSpecific;
+} IPMI_EMP_DESTINATION_INFO;
+
+typedef union {
+ struct {
+ UINT8 Parity : 3;
+ UINT8 CharacterSize : 1;
+ UINT8 StopBit : 1;
+ UINT8 DtrHangup : 1;
+ UINT8 FlowControl : 2;
+ } Bits;
+ UINT8 Uint8;
+} IPMI_EMP_DESTINATION_COM_SETTING_DATA_2;
+
+typedef union {
+ struct {
+ UINT8 BitRate : 4;
+ UINT8 Reserved : 4;
+ } Bits;
+ UINT8 Uint8;
+} IPMI_EMP_BIT_RATE;
+
+typedef struct {
+ IPMI_EMP_DESTINATION_SELECTOR DestinationSelector;
+ IPMI_EMP_DESTINATION_COM_SETTING_DATA_2 Data2;
+ IPMI_EMP_BIT_RATE BitRate;
+} IPMI_EMP_DESTINATION_COM_SETTING;
+
+typedef union {
+ struct {
+ UINT8 DialStringSelector : 4;
+ UINT8 Reserved : 4;
+ } Bits;
+ UINT8 Uint8;
+} IPMI_DIAL_STRING_SELECTOR;
+
+typedef struct {
+ IPMI_DIAL_STRING_SELECTOR DestinationSelector;
+ UINT8 Reserved;
+ UINT8 DialString[48];
+} IPMI_DESTINATION_DIAL_STRING;
+
+typedef union {
+ UINT32 IpAddressLong;
+ UINT8 IpAddress[4];
+} IPMI_PPP_IP_ADDRESS;
+
+typedef union {
+ struct {
+ UINT8 IpAddressSelector : 4;
+ UINT8 Reserved : 4;
+ } Bits;
+ UINT8 Uint8;
+} IPMI_DESTINATION_IP_ADDRESS_SELECTOR;
+
+typedef struct {
+ IPMI_DESTINATION_IP_ADDRESS_SELECTOR DestinationSelector;
+ IPMI_PPP_IP_ADDRESS PppIpAddress;
+} IPMI_DESTINATION_IP_ADDRESS;
+
+typedef union {
+ struct {
+ UINT8 TapServiceSelector : 4;
+ UINT8 TapDialStringSelector : 4;
+ } Bits;
+ UINT8 Uint8;
+} IPMI_TAP_DIAL_STRING_SERVICE_SELECTOR;
+
+typedef struct {
+ UINT8 TapSelector;
+ IPMI_TAP_DIAL_STRING_SERVICE_SELECTOR TapDialStringServiceSelector;
+} IPMI_DESTINATION_TAP_ACCOUNT;
+
+typedef struct {
+ UINT8 TapSelector;
+ UINT8 PagerIdString[16];
+} IPMI_TAP_PAGER_ID_STRING;
+
+typedef union {
+ UINT8 OptionData;
+ IPMI_EMP_AUTH_TYPE EmpAuthType;
+ IPMI_EMP_CONNECTION_TYPE EmpConnectionType;
+ IPMI_EMP_INACTIVITY_TIMEOUT EmpInactivityTimeout;
+ IPMI_EMP_CHANNEL_CALLBACK_CONTROL EmpCallbackControl;
+ IPMI_EMP_SESSION_TERMINATION EmpSessionTermination;
+ IPMI_EMP_MESSAGING_COM_SETTING EmpMessagingComSetting;
+ IPMI_EMP_MODEM_RING_TIME EmpModemRingTime;
+ IPMI_EMP_MODEM_INIT_STRING EmpModemInitString;
+ IPMI_EMP_MODEM_ESC_SEQUENCE EmpModemEscSequence;
+ IPMI_EMP_MODEM_HANGUP_SEQUENCE EmpModemHangupSequence;
+ IPMI_MODEM_DIALUP_COMMAND EmpModemDialupCommand;
+ IPMI_PAGE_BLACKOUT_INTERVAL EmpPageBlackoutInterval;
+ IPMI_EMP_COMMUNITY_STRING EmpCommunityString;
+ IPMI_EMP_DESTINATION_INFO EmpDestinationInfo;
+ IPMI_EMP_DESTINATION_COM_SETTING EmpDestinationComSetting;
+ UINT8 CallRetryBusySignalInterval;
+ IPMI_DESTINATION_DIAL_STRING DestinationDialString;
+ IPMI_DESTINATION_IP_ADDRESS DestinationIpAddress;
+ IPMI_DESTINATION_TAP_ACCOUNT DestinationTapAccount;
+ IPMI_TAP_PAGER_ID_STRING TapPagerIdString;
+} IPMI_EMP_OPTIONS;
+
+//
+// Definitions for Get Serial/Modem Configuration command
+//
+#define IPMI_TRANSPORT_GET_SERIAL_CONFIGURATION 0x11
+
+//
+// Constants and Structure definitions for "Get Serial/Modem Configuration" command to follow here
+//
+
+//
+// Definitions for Set Serial/Modem Mux command
+//
+#define IPMI_TRANSPORT_SET_SERIAL_MUX 0x12
+
+//
+// Constants and Structure definitions for "Set Serial/Modem Mux" command to follow here
+//
+
+//
+// Set Serial/Modem Mux command request return status
+//
+#define IPMI_MUX_SETTING_REQUEST_REJECTED 0x00
+#define IPMI_MUX_SETTING_REQUEST_ACCEPTED 0x01
+
+//
+// Definitions for serial multiplex settings
+//
+#define IPMI_MUX_SETTING_GET_MUX_SETTING 0x0
+#define IPMI_MUX_SETTING_REQUEST_MUX_TO_SYSTEM 0x1
+#define IPMI_MUX_SETTING_REQUEST_MUX_TO_BMC 0x2
+#define IPMI_MUX_SETTING_FORCE_MUX_TO_SYSTEM 0x3
+#define IPMI_MUX_SETTING_FORCE_MUX_TO_BMC 0x4
+#define IPMI_MUX_SETTING_BLOCK_REQUEST_MUX_TO_SYSTEM 0x5
+#define IPMI_MUX_SETTING_ALLOW_REQUEST_MUX_TO_SYSTEM 0x6
+#define IPMI_MUX_SETTING_BLOCK_REQUEST_MUX_TO_BMC 0x7
+#define IPMI_MUX_SETTING_ALLOW_REQUEST_MUX_TO_BMC 0x8
+
+typedef union {
+ struct {
+ UINT8 ChannelNo : 4;
+ UINT8 Reserved : 4;
+ } Bits;
+ UINT8 Uint8;
+} IPMI_MUX_CHANNEL_NUM;
+
+typedef union {
+ struct {
+ UINT8 MuxSetting : 4;
+ UINT8 Reserved : 4;
+ } Bits;
+ UINT8 Uint8;
+} IPMI_MUX_SETTING_REQUEST;
+
+typedef struct {
+ IPMI_MUX_CHANNEL_NUM ChannelNumber;
+ IPMI_MUX_SETTING_REQUEST MuxSetting;
+} IPMI_SET_SERIAL_MODEM_MUX_COMMAND_REQUEST;
+
+typedef union {
+ struct {
+ UINT8 MuxSetToBmc : 1;
+ UINT8 CommandStatus : 1;
+ UINT8 MessagingSessionActive : 1;
+ UINT8 AlertInProgress : 1;
+ UINT8 Reserved : 2;
+ UINT8 MuxToBmcAllowed : 1;
+ UINT8 MuxToSystemBlocked : 1;
+ } Bits;
+ UINT8 Uint8;
+} IPMI_MUX_SETTING_PRESENT_STATE;
+
+typedef struct {
+ UINT8 CompletionCode;
+ IPMI_MUX_SETTING_PRESENT_STATE MuxSetting;
+} IPMI_SET_SERIAL_MODEM_MUX_COMMAND_RESPONSE;
+
+//
+// Definitions for Get TAP Response Code command
+//
+#define IPMI_TRANSPORT_GET_TAP_RESPONSE_CODE 0x13
+
+//
+// Constants and Structure definitions for "Get TAP Response Code" command to follow here
+//
+
+//
+// Definitions for Set PPP UDP Proxy Transmit Data command
+//
+#define IPMI_TRANSPORT_SET_PPP_UDP_PROXY_TXDATA 0x14
+
+//
+// Constants and Structure definitions for "Set PPP UDP Proxy Transmit Data" command to follow here
+//
+
+//
+// Definitions for Get PPP UDP Proxy Transmit Data command
+//
+#define IPMI_TRANSPORT_GET_PPP_UDP_PROXY_TXDATA 0x15
+
+//
+// Constants and Structure definitions for "Get PPP UDP Proxy Transmit Data" command to follow here
+//
+
+//
+// Definitions for Send PPP UDP Proxy Packet command
+//
+#define IPMI_TRANSPORT_SEND_PPP_UDP_PROXY_PACKET 0x16
+
+//
+// Constants and Structure definitions for "Send PPP UDP Proxy Packet" command to follow here
+//
+
+//
+// Definitions for Get PPP UDP Proxy Receive Data command
+//
+#define IPMI_TRANSPORT_GET_PPP_UDP_PROXY_RX 0x17
+
+//
+// Constants and Structure definitions for "Get PPP UDP Proxy Receive Data" command to follow here
+//
+
+//
+// Definitions for Serial/Modem connection active command
+//
+#define IPMI_TRANSPORT_SERIAL_CONNECTION_ACTIVE 0x18
+
+//
+// Constants and Structure definitions for "Serial/Modem connection active" command to follow here
+//
+
+//
+// Definitions for Callback command
+//
+#define IPMI_TRANSPORT_CALLBACK 0x19
+
+//
+// Constants and Structure definitions for "Callback" command to follow here
+//
+
+//
+// Definitions for Set user Callback Options command
+//
+#define IPMI_TRANSPORT_SET_USER_CALLBACK_OPTIONS 0x1A
+
+//
+// Constants and Structure definitions for "Set user Callback Options" command to follow here
+//
+
+//
+// Definitions for Get user Callback Options command
+//
+#define IPMI_TRANSPORT_GET_USER_CALLBACK_OPTIONS 0x1B
+
+//
+// Constants and Structure definitions for "Get user Callback Options" command to follow here
+//
+
+//
+// Below is Definitions for SOL Commands (Chapter 26)
+//
+
+//
+// Definitions for SOL activating command
+//
+#define IPMI_TRANSPORT_SOL_ACTIVATING 0x20
+
+//
+// Constants and Structure definitions for "SOL activating" command to follow here
+//
+typedef union {
+ struct {
+ UINT8 SessionState : 4;
+ UINT8 Reserved : 4;
+ } Bits;
+ UINT8 Uint8;
+} IPMI_SOL_SESSION_STATE;
+
+typedef struct {
+ IPMI_SOL_SESSION_STATE SessionState;
+ UINT8 PayloadInstance;
+ UINT8 FormatVersionMajor; // 1
+ UINT8 FormatVersionMinor; // 0
+} IPMI_SOL_ACTIVATING_REQUEST;
+
+//
+// Definitions for Set SOL Configuration Parameters command
+//
+#define IPMI_TRANSPORT_SET_SOL_CONFIG_PARAM 0x21
+
+//
+// Constants and Structure definitions for "Set SOL Configuration Parameters" command to follow here
+//
+
+//
+// SOL Configuration Parameters selector
+//
+#define IPMI_SOL_CONFIGURATION_PARAMETER_SET_IN_PROGRESS 0
+#define IPMI_SOL_CONFIGURATION_PARAMETER_SOL_ENABLE 1
+#define IPMI_SOL_CONFIGURATION_PARAMETER_SOL_AUTHENTICATION 2
+#define IPMI_SOL_CONFIGURATION_PARAMETER_SOL_CHARACTER_PARAM 3
+#define IPMI_SOL_CONFIGURATION_PARAMETER_SOL_RETRY 4
+#define IPMI_SOL_CONFIGURATION_PARAMETER_SOL_NV_BIT_RATE 5
+#define IPMI_SOL_CONFIGURATION_PARAMETER_SOL_VOLATILE_BIT_RATE 6
+#define IPMI_SOL_CONFIGURATION_PARAMETER_SOL_PAYLOAD_CHANNEL 7
+#define IPMI_SOL_CONFIGURATION_PARAMETER_SOL_PAYLOAD_PORT 8
+
+typedef union {
+ struct {
+ UINT8 ChannelNumber : 4;
+ UINT8 Reserved : 4;
+ } Bits;
+ UINT8 Uint8;
+} IPMI_SET_SOL_CONFIG_PARAM_CHANNEL_NUM;
+
+typedef struct {
+ IPMI_SET_SOL_CONFIG_PARAM_CHANNEL_NUM ChannelNumber;
+ UINT8 ParameterSelector;
+ UINT8 ParameterData[0];
+} IPMI_SET_SOL_CONFIGURATION_PARAMETERS_REQUEST;
+
+//
+// Definitions for Get SOL Configuration Parameters command
+//
+#define IPMI_TRANSPORT_GET_SOL_CONFIG_PARAM 0x22
+
+//
+// Constants and Structure definitions for "Get SOL Configuration Parameters" command to follow here
+//
+typedef union {
+ struct {
+ UINT8 ChannelNumber : 4;
+ UINT8 Reserved : 3;
+ UINT8 GetParameter : 1;
+ } Bits;
+ UINT8 Uint8;
+} IPMI_GET_SOL_CONFIG_PARAM_CHANNEL_NUM;
+
+typedef struct {
+ IPMI_GET_SOL_CONFIG_PARAM_CHANNEL_NUM ChannelNumber;
+ UINT8 ParameterSelector;
+ UINT8 SetSelector;
+ UINT8 BlockSelector;
+} IPMI_GET_SOL_CONFIGURATION_PARAMETERS_REQUEST;
+
+typedef struct {
+ UINT8 CompletionCode;
+ UINT8 ParameterRevision;
+ UINT8 ParameterData[0];
+} IPMI_GET_SOL_CONFIGURATION_PARAMETERS_RESPONSE;
+
+#pragma pack()
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/LegacyBiosMpTable.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/LegacyBiosMpTable.h
new file mode 100644
index 0000000000..2d9574a50f
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/LegacyBiosMpTable.h
@@ -0,0 +1,288 @@
+/** @file
+ Defives data structures per MultiProcessor Specification Ver 1.4.
+
+ The MultiProcessor Specification defines an enhancement to the standard
+ to which PC manufacturers design DOS-compatible systems.
+
+Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _LEGACY_BIOS_MPTABLE_H_
+#define _LEGACY_BIOS_MPTABLE_H_
+
+#define EFI_LEGACY_MP_TABLE_REV_1_4 0x04
+
+//
+// Define MP table structures. All are packed.
+//
+#pragma pack(1)
+
+#define EFI_LEGACY_MP_TABLE_FLOATING_POINTER_SIGNATURE SIGNATURE_32 ('_', 'M', 'P', '_')
+typedef struct {
+ UINT32 Reserved1 : 6;
+ UINT32 MutipleClk : 1;
+ UINT32 Imcr : 1;
+ UINT32 Reserved2 : 24;
+} FEATUREBYTE2_5;
+
+typedef struct {
+ UINT32 Signature;
+ UINT32 PhysicalAddress;
+ UINT8 Length;
+ UINT8 SpecRev;
+ UINT8 Checksum;
+ UINT8 FeatureByte1;
+ FEATUREBYTE2_5 FeatureByte2_5;
+} EFI_LEGACY_MP_TABLE_FLOATING_POINTER;
+
+#define EFI_LEGACY_MP_TABLE_HEADER_SIGNATURE SIGNATURE_32 ('P', 'C', 'M', 'P')
+typedef struct {
+ UINT32 Signature;
+ UINT16 BaseTableLength;
+ UINT8 SpecRev;
+ UINT8 Checksum;
+ CHAR8 OemId[8];
+ CHAR8 OemProductId[12];
+ UINT32 OemTablePointer;
+ UINT16 OemTableSize;
+ UINT16 EntryCount;
+ UINT32 LocalApicAddress;
+ UINT16 ExtendedTableLength;
+ UINT8 ExtendedChecksum;
+ UINT8 Reserved;
+} EFI_LEGACY_MP_TABLE_HEADER;
+
+typedef struct {
+ UINT8 EntryType;
+} EFI_LEGACY_MP_TABLE_ENTRY_TYPE;
+
+//
+// Entry Type 0: Processor.
+//
+#define EFI_LEGACY_MP_TABLE_ENTRY_TYPE_PROCESSOR 0x00
+typedef struct {
+ UINT8 Enabled : 1;
+ UINT8 Bsp : 1;
+ UINT8 Reserved : 6;
+} EFI_LEGACY_MP_TABLE_ENTRY_PROCESSOR_FLAGS;
+
+typedef struct {
+ UINT32 Stepping : 4;
+ UINT32 Model : 4;
+ UINT32 Family : 4;
+ UINT32 Reserved : 20;
+} EFI_LEGACY_MP_TABLE_ENTRY_PROCESSOR_SIGNATURE;
+
+typedef struct {
+ UINT32 Fpu : 1;
+ UINT32 Reserved1 : 6;
+ UINT32 Mce : 1;
+ UINT32 Cx8 : 1;
+ UINT32 Apic : 1;
+ UINT32 Reserved2 : 22;
+} EFI_LEGACY_MP_TABLE_ENTRY_PROCESSOR_FEATURES;
+
+typedef struct {
+ UINT8 EntryType;
+ UINT8 Id;
+ UINT8 Ver;
+ EFI_LEGACY_MP_TABLE_ENTRY_PROCESSOR_FLAGS Flags;
+ EFI_LEGACY_MP_TABLE_ENTRY_PROCESSOR_SIGNATURE Signature;
+ EFI_LEGACY_MP_TABLE_ENTRY_PROCESSOR_FEATURES Features;
+ UINT32 Reserved1;
+ UINT32 Reserved2;
+} EFI_LEGACY_MP_TABLE_ENTRY_PROCESSOR;
+
+//
+// Entry Type 1: Bus.
+//
+#define EFI_LEGACY_MP_TABLE_ENTRY_TYPE_BUS 0x01
+typedef struct {
+ UINT8 EntryType;
+ UINT8 Id;
+ CHAR8 TypeString[6];
+} EFI_LEGACY_MP_TABLE_ENTRY_BUS;
+
+#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_CBUS "CBUS " // Corollary CBus
+#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_CBUSII "CBUSII" // Corollary CBUS II
+#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_EISA "EISA " // Extended ISA
+#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_FUTURE "FUTURE" // IEEE FutureBus
+#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_INTERN "INTERN" // Internal bus
+#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_ISA "ISA " // Industry Standard Architecture
+#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_MBI "MBI " // Multibus I
+#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_MBII "MBII " // Multibus II
+#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_MCA "MCA " // Micro Channel Architecture
+#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_MPI "MPI " // MPI
+#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_MPSA "MPSA " // MPSA
+#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_NUBUS "NUBUS " // Apple Macintosh NuBus
+#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_PCI "PCI " // Peripheral Component Interconnect
+#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_PCMCIA "PCMCIA" // PC Memory Card International Assoc.
+#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_TC "TC " // DEC TurboChannel
+#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_VL "VL " // VESA Local Bus
+#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_VME "VME " // VMEbus
+#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_XPRESS "XPRESS" // Express System Bus
+//
+// Entry Type 2: I/O APIC.
+//
+#define EFI_LEGACY_MP_TABLE_ENTRY_TYPE_IOAPIC 0x02
+typedef struct {
+ UINT8 Enabled : 1;
+ UINT8 Reserved : 7;
+} EFI_LEGACY_MP_TABLE_ENTRY_IOAPIC_FLAGS;
+
+typedef struct {
+ UINT8 EntryType;
+ UINT8 Id;
+ UINT8 Ver;
+ EFI_LEGACY_MP_TABLE_ENTRY_IOAPIC_FLAGS Flags;
+ UINT32 Address;
+} EFI_LEGACY_MP_TABLE_ENTRY_IOAPIC;
+
+//
+// Entry Type 3: I/O Interrupt Assignment.
+//
+#define EFI_LEGACY_MP_TABLE_ENTRY_TYPE_IO_INT 0x03
+typedef struct {
+ UINT16 Polarity : 2;
+ UINT16 Trigger : 2;
+ UINT16 Reserved : 12;
+} EFI_LEGACY_MP_TABLE_ENTRY_INT_FLAGS;
+
+typedef struct {
+ UINT8 IntNo : 2;
+ UINT8 Dev : 5;
+ UINT8 Reserved : 1;
+} EFI_LEGACY_MP_TABLE_ENTRY_INT_FIELDS;
+
+typedef union {
+ EFI_LEGACY_MP_TABLE_ENTRY_INT_FIELDS fields;
+ UINT8 byte;
+} EFI_LEGACY_MP_TABLE_ENTRY_INT_SOURCE_BUS_IRQ;
+
+typedef struct {
+ UINT8 EntryType;
+ UINT8 IntType;
+ EFI_LEGACY_MP_TABLE_ENTRY_INT_FLAGS Flags;
+ UINT8 SourceBusId;
+ EFI_LEGACY_MP_TABLE_ENTRY_INT_SOURCE_BUS_IRQ SourceBusIrq;
+ UINT8 DestApicId;
+ UINT8 DestApicIntIn;
+} EFI_LEGACY_MP_TABLE_ENTRY_IO_INT;
+
+typedef enum {
+ EfiLegacyMpTableEntryIoIntTypeInt = 0,
+ EfiLegacyMpTableEntryIoIntTypeNmi = 1,
+ EfiLegacyMpTableEntryIoIntTypeSmi = 2,
+ EfiLegacyMpTableEntryIoIntTypeExtInt = 3,
+} EFI_LEGACY_MP_TABLE_ENTRY_IO_INT_TYPE;
+
+typedef enum {
+ EfiLegacyMpTableEntryIoIntFlagsPolaritySpec = 0x0,
+ EfiLegacyMpTableEntryIoIntFlagsPolarityActiveHigh = 0x1,
+ EfiLegacyMpTableEntryIoIntFlagsPolarityReserved = 0x2,
+ EfiLegacyMpTableEntryIoIntFlagsPolarityActiveLow = 0x3,
+} EFI_LEGACY_MP_TABLE_ENTRY_IO_INT_FLAGS_POLARITY;
+
+typedef enum {
+ EfiLegacyMpTableEntryIoIntFlagsTriggerSpec = 0x0,
+ EfiLegacyMpTableEntryIoIntFlagsTriggerEdge = 0x1,
+ EfiLegacyMpTableEntryIoIntFlagsTriggerReserved = 0x2,
+ EfiLegacyMpTableEntryIoIntFlagsTriggerLevel = 0x3,
+} EFI_LEGACY_MP_TABLE_ENTRY_IO_INT_FLAGS_TRIGGER;
+
+//
+// Entry Type 4: Local Interrupt Assignment.
+//
+#define EFI_LEGACY_MP_TABLE_ENTRY_TYPE_LOCAL_INT 0x04
+typedef struct {
+ UINT8 EntryType;
+ UINT8 IntType;
+ EFI_LEGACY_MP_TABLE_ENTRY_INT_FLAGS Flags;
+ UINT8 SourceBusId;
+ EFI_LEGACY_MP_TABLE_ENTRY_INT_SOURCE_BUS_IRQ SourceBusIrq;
+ UINT8 DestApicId;
+ UINT8 DestApicIntIn;
+} EFI_LEGACY_MP_TABLE_ENTRY_LOCAL_INT;
+
+typedef enum {
+ EfiLegacyMpTableEntryLocalIntTypeInt = 0,
+ EfiLegacyMpTableEntryLocalIntTypeNmi = 1,
+ EfiLegacyMpTableEntryLocalIntTypeSmi = 2,
+ EfiLegacyMpTableEntryLocalIntTypeExtInt = 3,
+} EFI_LEGACY_MP_TABLE_ENTRY_LOCAL_INT_TYPE;
+
+typedef enum {
+ EfiLegacyMpTableEntryLocalIntFlagsPolaritySpec = 0x0,
+ EfiLegacyMpTableEntryLocalIntFlagsPolarityActiveHigh = 0x1,
+ EfiLegacyMpTableEntryLocalIntFlagsPolarityReserved = 0x2,
+ EfiLegacyMpTableEntryLocalIntFlagsPolarityActiveLow = 0x3,
+} EFI_LEGACY_MP_TABLE_ENTRY_LOCAL_INT_FLAGS_POLARITY;
+
+typedef enum {
+ EfiLegacyMpTableEntryLocalIntFlagsTriggerSpec = 0x0,
+ EfiLegacyMpTableEntryLocalIntFlagsTriggerEdge = 0x1,
+ EfiLegacyMpTableEntryLocalIntFlagsTriggerReserved = 0x2,
+ EfiLegacyMpTableEntryLocalIntFlagsTriggerLevel = 0x3,
+} EFI_LEGACY_MP_TABLE_ENTRY_LOCAL_INT_FLAGS_TRIGGER;
+
+//
+// Entry Type 128: System Address Space Mapping.
+//
+#define EFI_LEGACY_MP_TABLE_ENTRY_EXT_TYPE_SYS_ADDR_SPACE_MAPPING 0x80
+typedef struct {
+ UINT8 EntryType;
+ UINT8 Length;
+ UINT8 BusId;
+ UINT8 AddressType;
+ UINT64 AddressBase;
+ UINT64 AddressLength;
+} EFI_LEGACY_MP_TABLE_ENTRY_EXT_SYS_ADDR_SPACE_MAPPING;
+
+typedef enum {
+ EfiLegacyMpTableEntryExtSysAddrSpaceMappingIo = 0,
+ EfiLegacyMpTableEntryExtSysAddrSpaceMappingMemory = 1,
+ EfiLegacyMpTableEntryExtSysAddrSpaceMappingPrefetch = 2,
+} EFI_LEGACY_MP_TABLE_ENTRY_EXT_SYS_ADDR_SPACE_MAPPING_TYPE;
+
+//
+// Entry Type 129: Bus Hierarchy.
+//
+#define EFI_LEGACY_MP_TABLE_ENTRY_EXT_TYPE_BUS_HIERARCHY 0x81
+typedef struct {
+ UINT8 SubtractiveDecode : 1;
+ UINT8 Reserved : 7;
+} EFI_LEGACY_MP_TABLE_ENTRY_EXT_BUS_HIERARCHY_BUSINFO;
+
+typedef struct {
+ UINT8 EntryType;
+ UINT8 Length;
+ UINT8 BusId;
+ EFI_LEGACY_MP_TABLE_ENTRY_EXT_BUS_HIERARCHY_BUSINFO BusInfo;
+ UINT8 ParentBus;
+ UINT8 Reserved1;
+ UINT8 Reserved2;
+ UINT8 Reserved3;
+} EFI_LEGACY_MP_TABLE_ENTRY_EXT_BUS_HIERARCHY;
+
+//
+// Entry Type 130: Compatibility Bus Address Space Modifier.
+//
+#define EFI_LEGACY_MP_TABLE_ENTRY_EXT_TYPE_COMPAT_BUS_ADDR_SPACE_MODIFIER 0x82
+typedef struct {
+ UINT8 RangeMode : 1;
+ UINT8 Reserved : 7;
+} EFI_LEGACY_MP_TABLE_ENTRY_EXT_COMPAT_BUS_ADDR_SPACE_MODIFIER_ADDR_MODE;
+
+typedef struct {
+ UINT8 EntryType;
+ UINT8 Length;
+ UINT8 BusId;
+ EFI_LEGACY_MP_TABLE_ENTRY_EXT_COMPAT_BUS_ADDR_SPACE_MODIFIER_ADDR_MODE AddrMode;
+ UINT32 PredefinedRangeList;
+} EFI_LEGACY_MP_TABLE_ENTRY_EXT_COMPAT_BUS_ADDR_SPACE_MODIFIER;
+
+#pragma pack()
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/LowPowerIdleTable.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/LowPowerIdleTable.h
new file mode 100644
index 0000000000..627c01df71
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/LowPowerIdleTable.h
@@ -0,0 +1,81 @@
+/** @file
+ ACPI Low Power Idle Table (LPIT) definitions
+
+ Copyright (c) 2016, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Revision Reference:
+ - ACPI Low Power Idle Table (LPIT) Revision 001, dated July 2014
+ http://www.uefi.org/sites/default/files/resources/ACPI_Low_Power_Idle_Table.pdf
+
+ @par Glossary:
+ - GAS - Generic Address Structure
+ - LPI - Low Power Idle
+**/
+
+#ifndef _LOW_POWER_IDLE_TABLE_H_
+#define _LOW_POWER_IDLE_TABLE_H_
+
+#include
+
+#pragma pack(1)
+
+///
+/// LPI Structure Types
+///
+#define ACPI_LPI_STRUCTURE_TYPE_NATIVE_CSTATE 0x00
+
+///
+/// Low Power Idle (LPI) State Flags
+///
+typedef union {
+ struct {
+ UINT32 Disabled : 1; ///< If set, LPI state is not used
+
+ /**
+ If set, Residency counter is not available for this LPI state and
+ Residency Counter Frequency is invalid
+ **/
+ UINT32 CounterUnavailable : 1;
+ UINT32 Reserved : 30; ///< Reserved for future use. Must be zero
+ } Bits;
+ UINT32 Data32;
+} ACPI_LPI_STATE_FLAGS;
+
+///
+/// Low Power Idle (LPI) structure with Native C-state instruction entry trigger descriptor
+///
+typedef struct {
+ UINT32 Type; ///< LPI State descriptor Type 0
+ UINT32 Length; ///< Length of LPI state Descriptor Structure
+ ///
+ /// Unique LPI state identifier: zero based, monotonically increasing identifier
+ ///
+ UINT16 UniqueId;
+ UINT8 Reserved[2]; ///< Must be Zero
+ ACPI_LPI_STATE_FLAGS Flags; ///< LPI state flags
+
+ /**
+ The LPI entry trigger, matching an existing _CST.Register object, represented as a
+ Generic Address Structure. All processors must request this state or deeper to trigger.
+ **/
+ EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE EntryTrigger;
+ UINT32 Residency; ///< Minimum residency or break-even in uSec
+ UINT32 Latency; ///< Worst case exit latency in uSec
+
+ /**
+ [optional] Residency counter, represented as a Generic Address Structure.
+ If not present, Flags[1] bit should be set.
+ **/
+ EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE ResidencyCounter;
+
+ /**
+ [optional] Residency counter frequency in cycles per second. Value 0 indicates that
+ counter runs at TSC frequency. Valid only if Residency Counter is present.
+ **/
+ UINT64 ResidencyCounterFrequency;
+} ACPI_LPI_NATIVE_CSTATE_DESCRIPTOR;
+
+#pragma pack()
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/Mbr.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/Mbr.h
new file mode 100644
index 0000000000..8ceef53cc1
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/Mbr.h
@@ -0,0 +1,54 @@
+/** @file
+ Legacy Master Boot Record Format Definition.
+
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _MBR_H_
+#define _MBR_H_
+
+#define MBR_SIGNATURE 0xaa55
+
+#define EXTENDED_DOS_PARTITION 0x05
+#define EXTENDED_WINDOWS_PARTITION 0x0F
+
+#define MAX_MBR_PARTITIONS 4
+
+#define PMBR_GPT_PARTITION 0xEE
+#define EFI_PARTITION 0xEF
+
+#define MBR_SIZE 512
+
+#pragma pack(1)
+///
+/// MBR Partition Entry
+///
+typedef struct {
+ UINT8 BootIndicator;
+ UINT8 StartHead;
+ UINT8 StartSector;
+ UINT8 StartTrack;
+ UINT8 OSIndicator;
+ UINT8 EndHead;
+ UINT8 EndSector;
+ UINT8 EndTrack;
+ UINT8 StartingLBA[4];
+ UINT8 SizeInLBA[4];
+} MBR_PARTITION_RECORD;
+
+///
+/// MBR Partition Table
+///
+typedef struct {
+ UINT8 BootStrapCode[440];
+ UINT8 UniqueMbrSignature[4];
+ UINT8 Unknown[2];
+ MBR_PARTITION_RECORD Partition[MAX_MBR_PARTITIONS];
+ UINT16 Signature;
+} MASTER_BOOT_RECORD;
+
+#pragma pack()
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/MemoryMappedConfigurationSpaceAccessTable.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/MemoryMappedConfigurationSpaceAccessTable.h
new file mode 100644
index 0000000000..d47bf848c5
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/MemoryMappedConfigurationSpaceAccessTable.h
@@ -0,0 +1,49 @@
+/** @file
+ ACPI memory mapped configuration space access table definition, defined at
+ in the PCI Firmware Specification, version 3.0.
+ Specification is available at http://www.pcisig.com.
+
+ Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_TABLE_H_
+#define _MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_TABLE_H_
+
+#include
+
+//
+// Ensure proper structure formats
+//
+#pragma pack(1)
+
+///
+/// Memory Mapped Configuration Space Access Table (MCFG)
+/// This table is a basic description table header followed by
+/// a number of base address allocation structures.
+///
+typedef struct {
+ UINT64 BaseAddress;
+ UINT16 PciSegmentGroupNumber;
+ UINT8 StartBusNumber;
+ UINT8 EndBusNumber;
+ UINT32 Reserved;
+} EFI_ACPI_MEMORY_MAPPED_ENHANCED_CONFIGURATION_SPACE_BASE_ADDRESS_ALLOCATION_STRUCTURE;
+
+///
+/// MCFG Table header definition. The rest of the table
+/// must be defined in a platform specific manner.
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT64 Reserved;
+} EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE_HEADER;
+
+///
+/// MCFG Revision (defined in spec)
+///
+#define EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_TABLE_REVISION 0x01
+
+#pragma pack()
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/MemoryOverwriteRequestControlLock.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/MemoryOverwriteRequestControlLock.h
new file mode 100644
index 0000000000..1303c4c0cd
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/MemoryOverwriteRequestControlLock.h
@@ -0,0 +1,37 @@
+/** @file
+ Support for Microsoft Secure MOR implementation, defined at
+ Microsoft Secure MOR implementation.
+ https://msdn.microsoft.com/en-us/library/windows/hardware/mt270973(v=vs.85).aspx
+
+ Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __MEMORY_OVERWRITE_REQUEST_CONTROL_LOCK_H__
+#define __MEMORY_OVERWRITE_REQUEST_CONTROL_LOCK_H__
+
+#define MEMORY_OVERWRITE_REQUEST_CONTROL_LOCK_GUID \
+ { \
+ 0xBB983CCF, 0x151D, 0x40E1, {0xA0, 0x7B, 0x4A, 0x17, 0xBE, 0x16, 0x82, 0x92} \
+ }
+
+#define MEMORY_OVERWRITE_REQUEST_CONTROL_LOCK_NAME L"MemoryOverwriteRequestControlLock"
+
+//
+// VendorGuid: {BB983CCF-151D-40E1-A07B-4A17BE168292}
+// Name: MemoryOverwriteRequestControlLock
+// Attributes: NV+BS+RT
+// GetVariable value in Data parameter: 0x0 (unlocked); 0x1 (locked without key); 0x2 (locked with key)
+// SetVariable value in Data parameter: 0x0 (unlocked); 0x1 (locked);
+// Revision 2 additionally accepts an 8-byte value that represents a shared secret key.
+//
+
+//
+// Note: Setting MemoryOverwriteRequestControlLock does not commit to flash (just changes the internal lock state).
+// Getting the variable returns the internal state and never exposes the key.
+//
+
+extern EFI_GUID gEfiMemoryOverwriteRequestControlLockGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/Nvme.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/Nvme.h
new file mode 100644
index 0000000000..5313b939c4
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/Nvme.h
@@ -0,0 +1,1067 @@
+/** @file
+ Definitions based on NVMe spec. version 1.1.
+
+ (C) Copyright 2016 Hewlett Packard Enterprise Development LP
+ Copyright (c) 2017 - 2023, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Specification Reference:
+ NVMe Specification 1.1
+ NVMe Specification 1.4
+ NVMe Specification 2.0
+
+**/
+
+#ifndef __NVM_E_H__
+#define __NVM_E_H__
+
+#pragma pack(1)
+
+//
+// controller register offsets
+//
+#define NVME_CAP_OFFSET 0x0000 // Controller Capabilities
+#define NVME_VER_OFFSET 0x0008 // Version
+#define NVME_INTMS_OFFSET 0x000c // Interrupt Mask Set
+#define NVME_INTMC_OFFSET 0x0010 // Interrupt Mask Clear
+#define NVME_CC_OFFSET 0x0014 // Controller Configuration
+#define NVME_CSTS_OFFSET 0x001c // Controller Status
+#define NVME_NSSR_OFFSET 0x0020 // NVM Subsystem Reset
+#define NVME_AQA_OFFSET 0x0024 // Admin Queue Attributes
+#define NVME_ASQ_OFFSET 0x0028 // Admin Submission Queue Base Address
+#define NVME_ACQ_OFFSET 0x0030 // Admin Completion Queue Base Address
+#define NVME_BPINFO_OFFSET 0x0040 // Boot Partition Information
+#define NVME_BPRSEL_OFFSET 0x0044 // Boot Partition Read Select
+#define NVME_BPMBL_OFFSET 0x0048 // Boot Partition Memory Buffer Location
+#define NVME_SQ0_OFFSET 0x1000 // Submission Queue 0 (admin) Tail Doorbell
+#define NVME_CQ0_OFFSET 0x1004 // Completion Queue 0 (admin) Head Doorbell
+
+//
+// These register offsets are defined as 0x1000 + (N * (4 << CAP.DSTRD))
+// Get the doorbell stride bit shift value from the controller capabilities.
+//
+#define NVME_SQTDBL_OFFSET(QID, DSTRD) 0x1000 + ((2 * (QID)) * (4 << (DSTRD))) // Submission Queue y (NVM) Tail Doorbell
+#define NVME_CQHDBL_OFFSET(QID, DSTRD) 0x1000 + (((2 * (QID)) + 1) * (4 << (DSTRD))) // Completion Queue y (NVM) Head Doorbell
+
+#pragma pack(1)
+
+//
+// 3.1.1 Offset 00h: CAP - Controller Capabilities
+//
+typedef struct {
+ UINT16 Mqes; // Maximum Queue Entries Supported
+ UINT8 Cqr : 1; // Contiguous Queues Required
+ UINT8 Ams : 2; // Arbitration Mechanism Supported
+ UINT8 Rsvd1 : 5;
+ UINT8 To; // Timeout
+ UINT16 Dstrd : 4;
+ UINT16 Nssrs : 1; // NVM Subsystem Reset Supported NSSRS
+ UINT16 Css : 8; // Command Sets Supported - Bit 37
+ UINT16 Bps : 1; // Boot Partition Support - Bit 45 in NVMe1.4
+ UINT16 Rsvd3 : 2;
+ UINT8 Mpsmin : 4;
+ UINT8 Mpsmax : 4;
+ UINT8 Pmrs : 1;
+ UINT8 Cmbs : 1;
+ UINT8 Rsvd4 : 6;
+} NVME_CAP;
+
+//
+// 3.1.2 Offset 08h: VS - Version
+//
+typedef struct {
+ UINT16 Mnr; // Minor version number
+ UINT16 Mjr; // Major version number
+} NVME_VER;
+
+//
+// 3.1.5 Offset 14h: CC - Controller Configuration
+//
+typedef struct {
+ UINT16 En : 1; // Enable
+ UINT16 Rsvd1 : 3;
+ UINT16 Css : 3; // I/O Command Set Selected
+ UINT16 Mps : 4; // Memory Page Size
+ UINT16 Ams : 3; // Arbitration Mechanism Selected
+ UINT16 Shn : 2; // Shutdown Notification
+ UINT8 Iosqes : 4; // I/O Submission Queue Entry Size
+ UINT8 Iocqes : 4; // I/O Completion Queue Entry Size
+ UINT8 Rsvd2;
+} NVME_CC;
+#define NVME_CC_SHN_NORMAL_SHUTDOWN 1
+#define NVME_CC_SHN_ABRUPT_SHUTDOWN 2
+
+//
+// 3.1.6 Offset 1Ch: CSTS - Controller Status
+//
+typedef struct {
+ UINT32 Rdy : 1; // Ready
+ UINT32 Cfs : 1; // Controller Fatal Status
+ UINT32 Shst : 2; // Shutdown Status
+ UINT32 Nssro : 1; // NVM Subsystem Reset Occurred
+ UINT32 Rsvd1 : 27;
+} NVME_CSTS;
+#define NVME_CSTS_SHST_SHUTDOWN_OCCURRING 1
+#define NVME_CSTS_SHST_SHUTDOWN_COMPLETED 2
+//
+// 3.1.8 Offset 24h: AQA - Admin Queue Attributes
+//
+typedef struct {
+ UINT16 Asqs : 12; // Submission Queue Size
+ UINT16 Rsvd1 : 4;
+ UINT16 Acqs : 12; // Completion Queue Size
+ UINT16 Rsvd2 : 4;
+} NVME_AQA;
+
+//
+// 3.1.9 Offset 28h: ASQ - Admin Submission Queue Base Address
+//
+#define NVME_ASQ UINT64
+//
+// 3.1.10 Offset 30h: ACQ - Admin Completion Queue Base Address
+//
+#define NVME_ACQ UINT64
+
+//
+// 3.1.13 Offset 40h: BPINFO - Boot Partition Information
+//
+typedef struct {
+ UINT32 Bpsz : 15; // Boot Partition Size
+ UINT32 Rsvd1 : 9;
+ UINT32 Brs : 2; // Boot Read Status
+ UINT32 Rsvd2 : 5;
+ UINT32 Abpid : 1; // Active Boot Partition ID
+} NVME_BPINFO;
+
+//
+// 3.1.14 Offset 44h: BPRSEL - Boot Partition Read Select
+//
+typedef struct {
+ UINT32 Bprsz : 10; // Boot Partition Read Size
+ UINT32 Bprof : 20; // Boot Partition Read Offset
+ UINT32 Rsvd1 : 1;
+ UINT32 Bpid : 1; // Boot Partition Identifier
+} NVME_BPRSEL;
+
+//
+// 3.1.15 Offset 48h: BPMBL - Boot Partition Memory Buffer Location (Optional)
+//
+typedef struct {
+ UINT64 Rsvd1 : 12;
+ UINT64 Bmbba : 52; // Boot Partition Memory Buffer Base Address
+} NVME_BPMBL;
+
+//
+// 3.1.25 Offset (1000h + ((2y) * (4 << CAP.DSTRD))): SQyTDBL - Submission Queue y Tail Doorbell
+//
+typedef struct {
+ UINT16 Sqt;
+ UINT16 Rsvd1;
+} NVME_SQTDBL;
+
+//
+// 3.1.12 Offset (1000h + ((2y + 1) * (4 << CAP.DSTRD))): CQyHDBL - Completion Queue y Head Doorbell
+//
+typedef struct {
+ UINT16 Cqh;
+ UINT16 Rsvd1;
+} NVME_CQHDBL;
+
+//
+// NVM command set structures
+//
+// Read Command
+//
+typedef struct {
+ //
+ // CDW 10, 11
+ //
+ UINT64 Slba; /* Starting Sector Address */
+ //
+ // CDW 12
+ //
+ UINT16 Nlb; /* Number of Sectors */
+ UINT16 Rsvd1 : 10;
+ UINT16 Prinfo : 4; /* Protection Info Check */
+ UINT16 Fua : 1; /* Force Unit Access */
+ UINT16 Lr : 1; /* Limited Retry */
+ //
+ // CDW 13
+ //
+ UINT32 Af : 4; /* Access Frequency */
+ UINT32 Al : 2; /* Access Latency */
+ UINT32 Sr : 1; /* Sequential Request */
+ UINT32 In : 1; /* Incompressible */
+ UINT32 Rsvd2 : 24;
+ //
+ // CDW 14
+ //
+ UINT32 Eilbrt; /* Expected Initial Logical Block Reference Tag */
+ //
+ // CDW 15
+ //
+ UINT16 Elbat; /* Expected Logical Block Application Tag */
+ UINT16 Elbatm; /* Expected Logical Block Application Tag Mask */
+} NVME_READ;
+
+//
+// Write Command
+//
+typedef struct {
+ //
+ // CDW 10, 11
+ //
+ UINT64 Slba; /* Starting Sector Address */
+ //
+ // CDW 12
+ //
+ UINT16 Nlb; /* Number of Sectors */
+ UINT16 Rsvd1 : 10;
+ UINT16 Prinfo : 4; /* Protection Info Check */
+ UINT16 Fua : 1; /* Force Unit Access */
+ UINT16 Lr : 1; /* Limited Retry */
+ //
+ // CDW 13
+ //
+ UINT32 Af : 4; /* Access Frequency */
+ UINT32 Al : 2; /* Access Latency */
+ UINT32 Sr : 1; /* Sequential Request */
+ UINT32 In : 1; /* Incompressible */
+ UINT32 Rsvd2 : 24;
+ //
+ // CDW 14
+ //
+ UINT32 Ilbrt; /* Initial Logical Block Reference Tag */
+ //
+ // CDW 15
+ //
+ UINT16 Lbat; /* Logical Block Application Tag */
+ UINT16 Lbatm; /* Logical Block Application Tag Mask */
+} NVME_WRITE;
+
+//
+// Flush
+//
+typedef struct {
+ //
+ // CDW 10
+ //
+ UINT32 Flush; /* Flush */
+} NVME_FLUSH;
+
+//
+// Write Uncorrectable command
+//
+typedef struct {
+ //
+ // CDW 10, 11
+ //
+ UINT64 Slba; /* Starting LBA */
+ //
+ // CDW 12
+ //
+ UINT32 Nlb : 16; /* Number of Logical Blocks */
+ UINT32 Rsvd1 : 16;
+} NVME_WRITE_UNCORRECTABLE;
+
+//
+// Write Zeroes command
+//
+typedef struct {
+ //
+ // CDW 10, 11
+ //
+ UINT64 Slba; /* Starting LBA */
+ //
+ // CDW 12
+ //
+ UINT16 Nlb; /* Number of Logical Blocks */
+ UINT16 Rsvd1 : 10;
+ UINT16 Prinfo : 4; /* Protection Info Check */
+ UINT16 Fua : 1; /* Force Unit Access */
+ UINT16 Lr : 1; /* Limited Retry */
+ //
+ // CDW 13
+ //
+ UINT32 Rsvd2;
+ //
+ // CDW 14
+ //
+ UINT32 Ilbrt; /* Initial Logical Block Reference Tag */
+ //
+ // CDW 15
+ //
+ UINT16 Lbat; /* Logical Block Application Tag */
+ UINT16 Lbatm; /* Logical Block Application Tag Mask */
+} NVME_WRITE_ZEROES;
+
+//
+// Compare command
+//
+typedef struct {
+ //
+ // CDW 10, 11
+ //
+ UINT64 Slba; /* Starting LBA */
+ //
+ // CDW 12
+ //
+ UINT16 Nlb; /* Number of Logical Blocks */
+ UINT16 Rsvd1 : 10;
+ UINT16 Prinfo : 4; /* Protection Info Check */
+ UINT16 Fua : 1; /* Force Unit Access */
+ UINT16 Lr : 1; /* Limited Retry */
+ //
+ // CDW 13
+ //
+ UINT32 Rsvd2;
+ //
+ // CDW 14
+ //
+ UINT32 Eilbrt; /* Expected Initial Logical Block Reference Tag */
+ //
+ // CDW 15
+ //
+ UINT16 Elbat; /* Expected Logical Block Application Tag */
+ UINT16 Elbatm; /* Expected Logical Block Application Tag Mask */
+} NVME_COMPARE;
+
+typedef union {
+ NVME_READ Read;
+ NVME_WRITE Write;
+ NVME_FLUSH Flush;
+ NVME_WRITE_UNCORRECTABLE WriteUncorrectable;
+ NVME_WRITE_ZEROES WriteZeros;
+ NVME_COMPARE Compare;
+} NVME_CMD;
+
+typedef struct {
+ UINT16 Mp; /* Maximum Power */
+ UINT8 Rsvd1; /* Reserved as of Nvm Express 1.1 Spec */
+ UINT8 Mps : 1; /* Max Power Scale */
+ UINT8 Nops : 1; /* Non-Operational State */
+ UINT8 Rsvd2 : 6; /* Reserved as of Nvm Express 1.1 Spec */
+ UINT32 Enlat; /* Entry Latency */
+ UINT32 Exlat; /* Exit Latency */
+ UINT8 Rrt : 5; /* Relative Read Throughput */
+ UINT8 Rsvd3 : 3; /* Reserved as of Nvm Express 1.1 Spec */
+ UINT8 Rrl : 5; /* Relative Read Latency */
+ UINT8 Rsvd4 : 3; /* Reserved as of Nvm Express 1.1 Spec */
+ UINT8 Rwt : 5; /* Relative Write Throughput */
+ UINT8 Rsvd5 : 3; /* Reserved as of Nvm Express 1.1 Spec */
+ UINT8 Rwl : 5; /* Relative Write Latency */
+ UINT8 Rsvd6 : 3; /* Reserved as of Nvm Express 1.1 Spec */
+ UINT8 Rsvd7[16]; /* Reserved as of Nvm Express 1.1 Spec */
+} NVME_PSDESCRIPTOR;
+
+//
+// Identify Controller Data
+//
+typedef struct {
+ //
+ // Controller Capabilities and Features 0-255
+ //
+ UINT16 Vid; /* PCI Vendor ID */
+ UINT16 Ssvid; /* PCI sub-system vendor ID */
+ UINT8 Sn[20]; /* Product serial number */
+
+ UINT8 Mn[40]; /* Product model number */
+ UINT8 Fr[8]; /* Firmware Revision */
+ UINT8 Rab; /* Recommended Arbitration Burst */
+ UINT8 Ieee_oui[3]; /* Organization Unique Identifier */
+ UINT8 Cmic; /* Multi-interface Capabilities */
+ UINT8 Mdts; /* Maximum Data Transfer Size */
+ UINT8 Cntlid[2]; /* Controller ID */
+ UINT8 Rsvd1[176]; /* Reserved as of Nvm Express 1.1 Spec */
+ //
+ // Admin Command Set Attributes
+ //
+ UINT16 Oacs; /* Optional Admin Command Support */
+ #define NAMESPACE_MANAGEMENT_SUPPORTED BIT3
+ #define FW_DOWNLOAD_ACTIVATE_SUPPORTED BIT2
+ #define FORMAT_NVM_SUPPORTED BIT1
+ #define SECURITY_SEND_RECEIVE_SUPPORTED BIT0
+ UINT8 Acl; /* Abort Command Limit */
+ UINT8 Aerl; /* Async Event Request Limit */
+ UINT8 Frmw; /* Firmware updates */
+ UINT8 Lpa; /* Log Page Attributes */
+ UINT8 Elpe; /* Error Log Page Entries */
+ UINT8 Npss; /* Number of Power States Support */
+ UINT8 Avscc; /* Admin Vendor Specific Command Configuration */
+ UINT8 Apsta; /* Autonomous Power State Transition Attributes */
+ //
+ // Below fields before Rsvd2 are defined in NVM Express 1.4 Spec
+ //
+ UINT16 Wctemp; /* Warning Composite Temperature Threshold */
+ UINT16 Cctemp; /* Critical Composite Temperature Threshold */
+ UINT16 Mtfa; /* Maximum Time for Firmware Activation */
+ UINT32 Hmpre; /* Host Memory Buffer Preferred Size */
+ UINT32 Hmmin; /* Host Memory Buffer Minimum Size */
+ UINT8 Tnvmcap[16]; /* Total NVM Capacity */
+ UINT8 Unvmcap[16]; /* Unallocated NVM Capacity */
+ UINT32 Rpmbs; /* Replay Protected Memory Block Support */
+ UINT16 Edstt; /* Extended Device Self-test Time */
+ UINT8 Dsto; /* Device Self-test Options */
+ UINT8 Fwug; /* Firmware Update Granularity */
+ UINT8 Rsvd2[192]; /* Reserved as of Nvm Express 1.4 Spec */
+ //
+ // NVM Command Set Attributes
+ //
+ UINT8 Sqes; /* Submission Queue Entry Size */
+ UINT8 Cqes; /* Completion Queue Entry Size */
+ UINT16 Rsvd3; /* Reserved as of Nvm Express 1.1 Spec */
+ UINT32 Nn; /* Number of Namespaces */
+ UINT16 Oncs; /* Optional NVM Command Support */
+ UINT16 Fuses; /* Fused Operation Support */
+ UINT8 Fna; /* Format NVM Attributes */
+ UINT8 Vwc; /* Volatile Write Cache */
+ UINT16 Awun; /* Atomic Write Unit Normal */
+ UINT16 Awupf; /* Atomic Write Unit Power Fail */
+ UINT8 Nvscc; /* NVM Vendor Specific Command Configuration */
+ UINT8 Rsvd4; /* Reserved as of Nvm Express 1.1 Spec */
+ UINT16 Acwu; /* Atomic Compare & Write Unit */
+ UINT16 Rsvd5; /* Reserved as of Nvm Express 1.1 Spec */
+ UINT32 Sgls; /* SGL Support */
+ UINT8 Rsvd6[164]; /* Reserved as of Nvm Express 1.1 Spec */
+ //
+ // I/O Command set Attributes
+ //
+ UINT8 Rsvd7[1344]; /* Reserved as of Nvm Express 1.1 Spec */
+ //
+ // Power State Descriptors
+ //
+ NVME_PSDESCRIPTOR PsDescriptor[32];
+
+ UINT8 VendorData[1024]; /* Vendor specific data */
+} NVME_ADMIN_CONTROLLER_DATA;
+
+typedef struct {
+ UINT16 Ms; /* Metadata Size */
+ UINT8 Lbads; /* LBA Data Size */
+ UINT8 Rp : 2; /* Relative Performance */
+ #define LBAF_RP_BEST 00b
+ #define LBAF_RP_BETTER 01b
+ #define LBAF_RP_GOOD 10b
+ #define LBAF_RP_DEGRADED 11b
+ UINT8 Rsvd1 : 6; /* Reserved as of Nvm Express 1.1 Spec */
+} NVME_LBAFORMAT;
+
+//
+// Identify Namespace Data
+//
+typedef struct {
+ //
+ // NVM Command Set Specific
+ //
+ UINT64 Nsze; /* Namespace Size (total number of blocks in formatted namespace) */
+ UINT64 Ncap; /* Namespace Capacity (max number of logical blocks) */
+ UINT64 Nuse; /* Namespace Utilization */
+ UINT8 Nsfeat; /* Namespace Features */
+ UINT8 Nlbaf; /* Number of LBA Formats */
+ UINT8 Flbas; /* Formatted LBA size */
+ UINT8 Mc; /* Metadata Capabilities */
+ UINT8 Dpc; /* End-to-end Data Protection capabilities */
+ UINT8 Dps; /* End-to-end Data Protection Type Settings */
+ UINT8 Nmic; /* Namespace Multi-path I/O and Namespace Sharing Capabilities */
+ UINT8 Rescap; /* Reservation Capabilities */
+ UINT8 Rsvd1[88]; /* Reserved as of Nvm Express 1.1 Spec */
+ UINT64 Eui64; /* IEEE Extended Unique Identifier */
+ //
+ // LBA Format
+ //
+ NVME_LBAFORMAT LbaFormat[16];
+
+ UINT8 Rsvd2[192]; /* Reserved as of Nvm Express 1.1 Spec */
+ UINT8 VendorData[3712]; /* Vendor specific data */
+} NVME_ADMIN_NAMESPACE_DATA;
+
+//
+// RPMB Device Configuration Block Data Structure as of Nvm Express 1.4 Spec
+//
+typedef struct {
+ UINT8 Bppe; /* Boot Partition Protection Enable */
+ UINT8 Bpl; /* Boot Partition Lock */
+ UINT8 Nwpac; /* Namespace Write Protection Authentication Control */
+ UINT8 Rsvd1[509]; /* Reserved as of Nvm Express 1.4 Spec */
+} NVME_RPMB_CONFIGURATION_DATA;
+
+#define RPMB_FRAME_STUFF_BYTES 223
+
+//
+// RPMB Data Frame as of Nvm Express 1.4 Spec
+//
+typedef struct {
+ UINT8 Sbakamc[RPMB_FRAME_STUFF_BYTES]; /* [222-N:00] Stuff Bytes */
+ /* [222:222-(N-1)] Authentication Key or Message Authentication Code (MAC) */
+ UINT8 Rpmbt; /* RPMB Target */
+ UINT64 Nonce[2];
+ UINT32 Wcounter; /* Write Counter */
+ UINT32 Address; /* Starting address of data to be programmed to or read from the RPMB. */
+ UINT32 Scount; /* Sector Count */
+ UINT16 Result;
+ UINT16 Rpmessage; /* Request/Response Message */
+ // UINT8 *Data; /* Data to be written or read by signed access where M = 512 * Sector Count. */
+} NVME_RPMB_DATA_FRAME;
+
+//
+// RPMB Device Configuration Block Data Structure.
+// (ref. NVMe Base spec. v2.0 Figure 460).
+//
+typedef struct {
+ UINT8 BPPEnable; /* Boot Partition Protection Enabled */
+ UINT8 BPLock; /* Boot Partition Lock */
+ UINT8 NameSpaceWrP; /* Namespace Write Protection */
+ UINT8 Rsvd1[509]; /* Reserved as of Nvm Express 2.0 Spec */
+} NVME_RPMB_DCB;
+
+//
+// RPMB Request and Response Message Types.
+// (ref. NVMe Base spec. v2.0 Figure 461).
+//
+#define NVME_RPMB_AUTHKEY_PROGRAM 0x0001
+#define NVME_RPMB_COUNTER_READ 0x0002
+#define NVME_RPMB_AUTHDATA_WRITE 0x0003
+#define NVME_RPMB_AUTHDATA_READ 0x0004
+#define NVME_RPMB_RESULT_READ 0x0005
+#define NVME_RPMB_DCB_WRITE 0x0006
+#define NVME_RPMB_DCB_READ 0x0007
+#define NVME_RPMB_AUTHKEY_PROGRAM_RESPONSE 0x0100
+#define NVME_RPMB_COUNTER_READ_RESPONSE 0x0200
+#define NVME_RPMB_AUTHDATA_WRITE_RESPONSE 0x0300
+#define NVME_RPMB_AUTHDATA_READ_RESPONSE 0x0400
+#define NVME_RPMB_DCB_WRITE_RESPONSE 0x0600
+#define NVME_RPMB_DCB_READ_RESPONSE 0x0700
+
+//
+// RPMB Operation Result.
+// (ref. NVMe Base spec. v2.0 Figure 462).
+//
+#define NVME_RPMB_RESULT_SUCCESS 0x00
+#define NVME_RPMB_RESULT_GENERAL_FAILURE 0x01
+#define NVME_RPMB_RESULT_AHTHENTICATION_FAILURE 0x02
+#define NVME_RPMB_RESULT_COUNTER_FAILURE 0x03
+#define NVME_RPMB_RESULT_ADDRESS_FAILURE 0x04
+#define NVME_RPMB_RESULT_WRITE_FAILURE 0x05
+#define NVME_RPMB_RESULT_READ_FAILURE 0x06
+#define NVME_RPMB_RESULT_AUTHKEY_NOT_PROGRAMMED 0x07
+#define NVME_RPMB_RESULT_INVALID_DCB 0x08
+
+//
+// Get Log Page - Boot Partition Log Header.
+// (ref. NVMe Base spec. v2.0 Figure 262).
+//
+typedef struct {
+ UINT8 LogIdentifier; /* Log Identifier, shall be set to 15h */
+ UINT8 Rsvd1[3];
+ UINT32 Bpsz : 15; /* Boot Partition Size */
+ UINT32 Rsvd2 : 16;
+ UINT32 Abpid : 1; /* Active Boot Partition ID */
+ UINT8 Rsvd3[8];
+} NVME_BOOT_PARTITION_HEADER;
+
+//
+// NvmExpress Admin Identify Cmd
+//
+typedef struct {
+ //
+ // CDW 10
+ //
+ UINT32 Cns : 2;
+ UINT32 Rsvd1 : 30;
+} NVME_ADMIN_IDENTIFY;
+
+//
+// NvmExpress Admin Create I/O Completion Queue
+//
+typedef struct {
+ //
+ // CDW 10
+ //
+ UINT32 Qid : 16; /* Queue Identifier */
+ UINT32 Qsize : 16; /* Queue Size */
+
+ //
+ // CDW 11
+ //
+ UINT32 Pc : 1; /* Physically Contiguous */
+ UINT32 Ien : 1; /* Interrupts Enabled */
+ UINT32 Rsvd1 : 14; /* reserved as of Nvm Express 1.1 Spec */
+ UINT32 Iv : 16; /* Interrupt Vector for MSI-X or MSI*/
+} NVME_ADMIN_CRIOCQ;
+
+//
+// NvmExpress Admin Create I/O Submission Queue
+//
+typedef struct {
+ //
+ // CDW 10
+ //
+ UINT32 Qid : 16; /* Queue Identifier */
+ UINT32 Qsize : 16; /* Queue Size */
+
+ //
+ // CDW 11
+ //
+ UINT32 Pc : 1; /* Physically Contiguous */
+ UINT32 Qprio : 2; /* Queue Priority */
+ UINT32 Rsvd1 : 13; /* Reserved as of Nvm Express 1.1 Spec */
+ UINT32 Cqid : 16; /* Completion Queue ID */
+} NVME_ADMIN_CRIOSQ;
+
+//
+// NvmExpress Admin Delete I/O Completion Queue
+//
+typedef struct {
+ //
+ // CDW 10
+ //
+ UINT16 Qid;
+ UINT16 Rsvd1;
+} NVME_ADMIN_DEIOCQ;
+
+//
+// NvmExpress Admin Delete I/O Submission Queue
+//
+typedef struct {
+ //
+ // CDW 10
+ //
+ UINT16 Qid;
+ UINT16 Rsvd1;
+} NVME_ADMIN_DEIOSQ;
+
+//
+// NvmExpress Admin Abort Command
+//
+typedef struct {
+ //
+ // CDW 10
+ //
+ UINT32 Sqid : 16; /* Submission Queue identifier */
+ UINT32 Cid : 16; /* Command Identifier */
+} NVME_ADMIN_ABORT;
+
+//
+// NvmExpress Admin Firmware Activate Command
+//
+typedef struct {
+ //
+ // CDW 10
+ //
+ UINT32 Fs : 3; /* Submission Queue identifier */
+ UINT32 Aa : 2; /* Command Identifier */
+ UINT32 Rsvd1 : 27;
+} NVME_ADMIN_FIRMWARE_ACTIVATE;
+
+//
+// NvmExpress Admin Firmware Image Download Command
+//
+typedef struct {
+ //
+ // CDW 10
+ //
+ UINT32 Numd; /* Number of Dwords */
+ //
+ // CDW 11
+ //
+ UINT32 Ofst; /* Offset */
+} NVME_ADMIN_FIRMWARE_IMAGE_DOWNLOAD;
+
+//
+// NvmExpress Admin Get Features Command
+//
+typedef struct {
+ //
+ // CDW 10
+ //
+ UINT32 Fid : 8; /* Feature Identifier */
+ UINT32 Sel : 3; /* Select */
+ UINT32 Rsvd1 : 21;
+} NVME_ADMIN_GET_FEATURES;
+
+//
+// NvmExpress Admin Get Log Page Command
+//
+typedef struct {
+ //
+ // CDW 10
+ //
+ UINT32 Lid : 8; /* Log Page Identifier */
+ #define LID_ERROR_INFO 0x1
+ #define LID_SMART_INFO 0x2
+ #define LID_FW_SLOT_INFO 0x3
+ #define LID_BP_INFO 0x15
+ UINT32 Rsvd1 : 8;
+ UINT32 Numd : 12; /* Number of Dwords */
+ UINT32 Rsvd2 : 4; /* Reserved as of Nvm Express 1.1 Spec */
+} NVME_ADMIN_GET_LOG_PAGE;
+
+//
+// NvmExpress Admin Set Features Command
+//
+typedef struct {
+ //
+ // CDW 10
+ //
+ UINT32 Fid : 8; /* Feature Identifier */
+ UINT32 Rsvd1 : 23;
+ UINT32 Sv : 1; /* Save */
+} NVME_ADMIN_SET_FEATURES;
+
+//
+// NvmExpress Admin Format NVM Command
+//
+typedef struct {
+ //
+ // CDW 10
+ //
+ UINT32 Lbaf : 4; /* LBA Format */
+ UINT32 Ms : 1; /* Metadata Settings */
+ UINT32 Pi : 3; /* Protection Information */
+ UINT32 Pil : 1; /* Protection Information Location */
+ UINT32 Ses : 3; /* Secure Erase Settings */
+ UINT32 Rsvd1 : 20;
+} NVME_ADMIN_FORMAT_NVM;
+
+//
+// NvmExpress Admin Security Receive Command
+//
+typedef struct {
+ //
+ // CDW 10
+ //
+ UINT32 Rsvd1 : 8;
+ UINT32 Spsp : 16; /* SP Specific */
+ UINT32 Secp : 8; /* Security Protocol */
+ //
+ // CDW 11
+ //
+ UINT32 Al; /* Allocation Length */
+} NVME_ADMIN_SECURITY_RECEIVE;
+
+//
+// NvmExpress Admin Security Send Command
+//
+typedef struct {
+ //
+ // CDW 10
+ //
+ UINT32 Rsvd1 : 8;
+ UINT32 Spsp : 16; /* SP Specific */
+ UINT32 Secp : 8; /* Security Protocol */
+ //
+ // CDW 11
+ //
+ UINT32 Tl; /* Transfer Length */
+} NVME_ADMIN_SECURITY_SEND;
+
+typedef union {
+ NVME_ADMIN_IDENTIFY Identify;
+ NVME_ADMIN_CRIOCQ CrIoCq;
+ NVME_ADMIN_CRIOSQ CrIoSq;
+ NVME_ADMIN_DEIOCQ DeIoCq;
+ NVME_ADMIN_DEIOSQ DeIoSq;
+ NVME_ADMIN_ABORT Abort;
+ NVME_ADMIN_FIRMWARE_ACTIVATE Activate;
+ NVME_ADMIN_FIRMWARE_IMAGE_DOWNLOAD FirmwareImageDownload;
+ NVME_ADMIN_GET_FEATURES GetFeatures;
+ NVME_ADMIN_GET_LOG_PAGE GetLogPage;
+ NVME_ADMIN_SET_FEATURES SetFeatures;
+ NVME_ADMIN_FORMAT_NVM FormatNvm;
+ NVME_ADMIN_SECURITY_RECEIVE SecurityReceive;
+ NVME_ADMIN_SECURITY_SEND SecuritySend;
+} NVME_ADMIN_CMD;
+
+typedef struct {
+ UINT32 Cdw10;
+ UINT32 Cdw11;
+ UINT32 Cdw12;
+ UINT32 Cdw13;
+ UINT32 Cdw14;
+ UINT32 Cdw15;
+} NVME_RAW;
+
+typedef union {
+ NVME_ADMIN_CMD Admin; // Union of Admin commands
+ NVME_CMD Nvm; // Union of Nvm commands
+ NVME_RAW Raw;
+} NVME_PAYLOAD;
+
+//
+// Submission Queue
+//
+typedef struct {
+ //
+ // CDW 0, Common to all commands
+ //
+ UINT8 Opc; // Opcode
+ UINT8 Fuse : 2; // Fused Operation
+ UINT8 Rsvd1 : 5;
+ UINT8 Psdt : 1; // PRP or SGL for Data Transfer
+ UINT16 Cid; // Command Identifier
+
+ //
+ // CDW 1
+ //
+ UINT32 Nsid; // Namespace Identifier
+
+ //
+ // CDW 2,3
+ //
+ UINT64 Rsvd2;
+
+ //
+ // CDW 4,5
+ //
+ UINT64 Mptr; // Metadata Pointer
+
+ //
+ // CDW 6-9
+ //
+ UINT64 Prp[2]; // First and second PRP entries
+
+ NVME_PAYLOAD Payload;
+} NVME_SQ;
+
+//
+// Completion Queue
+//
+typedef struct {
+ //
+ // CDW 0
+ //
+ UINT32 Dword0;
+ //
+ // CDW 1
+ //
+ UINT32 Rsvd1;
+ //
+ // CDW 2
+ //
+ UINT16 Sqhd; // Submission Queue Head Pointer
+ UINT16 Sqid; // Submission Queue Identifier
+ //
+ // CDW 3
+ //
+ UINT16 Cid; // Command Identifier
+ UINT16 Pt : 1; // Phase Tag
+ UINT16 Sc : 8; // Status Code
+ UINT16 Sct : 3; // Status Code Type
+ UINT16 Rsvd2 : 2;
+ UINT16 Mo : 1; // More
+ UINT16 Dnr : 1; // Do Not Retry
+} NVME_CQ;
+
+//
+// Nvm Express Admin cmd opcodes
+//
+#define NVME_ADMIN_DEIOSQ_CMD 0x00
+#define NVME_ADMIN_CRIOSQ_CMD 0x01
+#define NVME_ADMIN_GET_LOG_PAGE_CMD 0x02
+#define NVME_ADMIN_DEIOCQ_CMD 0x04
+#define NVME_ADMIN_CRIOCQ_CMD 0x05
+#define NVME_ADMIN_IDENTIFY_CMD 0x06
+#define NVME_ADMIN_ABORT_CMD 0x08
+#define NVME_ADMIN_SET_FEATURES_CMD 0x09
+#define NVME_ADMIN_GET_FEATURES_CMD 0x0A
+#define NVME_ADMIN_ASYNC_EVENT_REQUEST_CMD 0x0C
+#define NVME_ADMIN_NAMESACE_MANAGEMENT_CMD 0x0D
+#define NVME_ADMIN_FW_COMMIT_CMD 0x10
+#define NVME_ADMIN_FW_IAMGE_DOWNLOAD_CMD 0x11
+#define NVME_ADMIN_NAMESACE_ATTACHMENT_CMD 0x15
+#define NVME_ADMIN_FORMAT_NVM_CMD 0x80
+#define NVME_ADMIN_SECURITY_SEND_CMD 0x81
+#define NVME_ADMIN_SECURITY_RECEIVE_CMD 0x82
+
+#define NVME_IO_FLUSH_OPC 0
+#define NVME_IO_WRITE_OPC 1
+#define NVME_IO_READ_OPC 2
+
+typedef enum {
+ DeleteIOSubmissionQueueOpcode = NVME_ADMIN_DEIOSQ_CMD,
+ CreateIOSubmissionQueueOpcode = NVME_ADMIN_CRIOSQ_CMD,
+ GetLogPageOpcode = NVME_ADMIN_GET_LOG_PAGE_CMD,
+ DeleteIOCompletionQueueOpcode = NVME_ADMIN_DEIOCQ_CMD,
+ CreateIOCompletionQueueOpcode = NVME_ADMIN_CRIOCQ_CMD,
+ IdentifyOpcode = NVME_ADMIN_IDENTIFY_CMD,
+ AbortOpcode = NVME_ADMIN_ABORT_CMD,
+ SetFeaturesOpcode = NVME_ADMIN_SET_FEATURES_CMD,
+ GetFeaturesOpcode = NVME_ADMIN_GET_FEATURES_CMD,
+ AsyncEventRequestOpcode = NVME_ADMIN_ASYNC_EVENT_REQUEST_CMD,
+ NamespaceManagementOpcode = NVME_ADMIN_NAMESACE_MANAGEMENT_CMD,
+ FirmwareCommitOpcode = NVME_ADMIN_FW_COMMIT_CMD,
+ FirmwareImageDownloadOpcode = NVME_ADMIN_FW_IAMGE_DOWNLOAD_CMD,
+ NamespaceAttachmentOpcode = NVME_ADMIN_NAMESACE_ATTACHMENT_CMD,
+ FormatNvmOpcode = NVME_ADMIN_FORMAT_NVM_CMD,
+ SecuritySendOpcode = NVME_ADMIN_SECURITY_SEND_CMD,
+ SecurityReceiveOpcode = NVME_ADMIN_SECURITY_RECEIVE_CMD
+} NVME_ADMIN_COMMAND_OPCODE;
+
+//
+// Controller or Namespace Structure (CNS) field
+// (ref. spec. v1.1 figure 82).
+//
+typedef enum {
+ IdentifyNamespaceCns = 0x0,
+ IdentifyControllerCns = 0x1,
+ IdentifyActiveNsListCns = 0x2
+} NVME_ADMIN_IDENTIFY_CNS;
+
+//
+// Commit Action
+// (ref. spec. 1.1 figure 60).
+//
+typedef enum {
+ ActivateActionReplace = 0x0,
+ ActivateActionReplaceActivate = 0x1,
+ ActivateActionActivate = 0x2
+} NVME_FW_ACTIVATE_ACTION;
+
+//
+// Firmware Slot
+// (ref. spec. 1.1 Figure 60).
+//
+typedef enum {
+ FirmwareSlotCtrlChooses = 0x0,
+ FirmwareSlot1 = 0x1,
+ FirmwareSlot2 = 0x2,
+ FirmwareSlot3 = 0x3,
+ FirmwareSlot4 = 0x4,
+ FirmwareSlot5 = 0x5,
+ FirmwareSlot6 = 0x6,
+ FirmwareSlot7 = 0x7
+} NVME_FW_ACTIVATE_SLOT;
+
+//
+// Get Log Page ? Log Page Identifiers
+// (ref. spec. v1.1 Figure 73).
+//
+typedef enum {
+ ErrorInfoLogID = LID_ERROR_INFO,
+ SmartHealthInfoLogID = LID_SMART_INFO,
+ FirmwareSlotInfoLogID = LID_FW_SLOT_INFO
+} NVME_LOG_ID;
+
+//
+// Get Log Page ? Firmware Slot Information Log
+// (ref. spec. v1.1 Figure 77).
+//
+typedef struct {
+ //
+ // Indicates the firmware slot from which the actively running firmware revision was loaded.
+ //
+ UINT8 ActivelyRunningFwSlot : 3;
+ UINT8 : 1;
+ //
+ // Indicates the firmware slot that is going to be activated at the next controller reset. If this field is 0h, then the controller does not indicate the firmware slot that is going to be activated at the next controller reset.
+ //
+ UINT8 NextActiveFwSlot : 3;
+ UINT8 : 1;
+} NVME_ACTIVE_FW_INFO;
+
+//
+// Get Log Page ? Firmware Slot Information Log
+// (ref. spec. v1.1 Figure 77).
+//
+typedef struct {
+ //
+ // Specifies information about the active firmware revision.
+ // s
+ NVME_ACTIVE_FW_INFO ActiveFwInfo;
+ UINT8 Reserved1[7];
+ //
+ // Contains the revision of the firmware downloaded to firmware slot 1/7. If no valid firmware revision is present or if this slot is unsupported, all zeros shall be returned.
+ //
+ CHAR8 FwRevisionSlot[7][8];
+ UINT8 Reserved2[448];
+} NVME_FW_SLOT_INFO_LOG;
+
+//
+// SMART / Health Information (Log Identifier 02h)
+// (ref. spec. v1.1 5.10.1.2)
+//
+typedef struct {
+ //
+ // This field indicates critical warnings for the state of the controller.
+ //
+ UINT8 CriticalWarningAvailableSpare : 1;
+ UINT8 CriticalWarningTemperature : 1;
+ UINT8 CriticalWarningReliability : 1;
+ UINT8 CriticalWarningMediaReadOnly : 1;
+ UINT8 CriticalWarningVolatileBackup : 1;
+ UINT8 CriticalWarningReserved : 3;
+ //
+ // Contains a value corresponding to a temperature in degrees Kelvin that represents the current composite temperature of the controller and namespace(s) associated with that controller. The manner in which this value is computed is implementation specific and may not represent the actual temperature of any physical point in the NVM subsystem.
+ //
+ UINT16 CompositeTemp;
+ //
+ // Contains a normalized percentage (0 to 100%) of the remaining spare capacity available.
+ //
+ UINT8 AvailableSpare;
+ //
+ // When the Available Spare falls below the threshold indicated in this field, an asynchronous event completion may occur. The value is indicated as a normalized percentage (0 to 100%).
+ //
+ UINT8 AvailableSpareThreshold;
+ //
+ // Contains a vendor specific estimate of the percentage of NVM subsystem life used based on the actual usage and the manufacturer's prediction of NVM life. A value of 100 indicates that the estimated endurance of the NVM in the NVM subsystem has been consumed, but may not indicate an NVM subsystem failure. The value is allowed to exceed 100. Percentages greater than 254 shall be represented as 255. This value shall be updated once per power-on hour (when the controller is not in a sleep state).
+ //
+ UINT8 PercentageUsed;
+ UINT8 Reserved1[26];
+ //
+ // Contains the number of 512 byte data units the host has read from the controller; this value does not include metadata.
+ //
+ UINT8 DataUnitsRead[16];
+ //
+ // Contains the number of 512 byte data units the host has written to the controller; this value does not include metadata.
+ //
+ UINT8 DataUnitsWritten[16];
+ //
+ // Contains the number of read commands completed by the controller.
+ //
+ UINT8 HostReadCommands[16];
+ //
+ // Contains the number of write commands completed by the controller.
+ //
+ UINT8 HostWriteCommands[16];
+ //
+ // Contains the amount of time the controller is busy with I/O commands. This value is reported in minutes.
+ //
+ UINT8 ControllerBusyTime[16];
+ //
+ // Contains the number of power cycles.
+ //
+ UINT8 PowerCycles[16];
+ //
+ // Contains the number of power-on hours.
+ //
+ UINT8 PowerOnHours[16];
+ //
+ // Contains the number of unsafe shutdowns.
+ //
+ UINT8 UnsafeShutdowns[16];
+ //
+ // Contains the number of occurrences where the controller detected an unrecovered data integrity error.
+ //
+ UINT8 MediaAndDataIntegrityErrors[16];
+ //
+ // Contains the number of Error Information log entries over the life of the controller.
+ //
+ UINT8 NumberErrorInformationLogEntries[16];
+ //
+ // Contains the amount of time in minutes that the controller is operational and the Composite Temperature is greater than or equal to the Warning Composite Temperature Threshold (WCTEMP) field and less than the Critical Composite Temperature Threshold (CCTEMP) field in the Identify Controller data structure in Figure 90.
+ //
+ UINT32 WarningCompositeTemperatureTime;
+ //
+ // Contains the amount of time in minutes that the controller is operational and the Composite Temperature is greater the Critical Composite Temperature Threshold (CCTEMP) field in the Identify Controller data structure in Figure 90.
+ //
+ UINT32 CriticalCompositeTemperatureTime;
+ //
+ // Contains the current temperature in degrees Kelvin reported by the temperature sensor. An implementation that does not implement the temperature sensor reports a temperature of zero degrees Kelvin.
+ //
+ UINT16 TemperatureSensor[8];
+ UINT8 Reserved2[296];
+} NVME_SMART_HEALTH_INFO_LOG;
+
+#pragma pack()
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/Pci.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/Pci.h
new file mode 100644
index 0000000000..2cd95d75a2
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/Pci.h
@@ -0,0 +1,15 @@
+/** @file
+ Support for the latest PCI standard.
+
+Copyright (c) 2006 - 2020, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _PCI_H_
+#define _PCI_H_
+
+#include
+#include
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/Pci22.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/Pci22.h
new file mode 100644
index 0000000000..1d95e71c76
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/Pci22.h
@@ -0,0 +1,878 @@
+/** @file
+ Support for PCI 2.2 standard.
+
+ This file includes the definitions in the following specifications,
+ PCI Local Bus Specification, 2.2
+ PCI-to-PCI Bridge Architecture Specification, Revision 1.2
+ PC Card Standard, 8.0
+ PCI Power Management Interface Specification, Revision 1.2
+
+ Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ Copyright (c) 2014 - 2015, Hewlett-Packard Development Company, L.P.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _PCI22_H_
+#define _PCI22_H_
+
+#define PCI_MAX_BUS 255
+#define PCI_MAX_DEVICE 31
+#define PCI_MAX_FUNC 7
+
+#pragma pack(1)
+
+///
+/// Common header region in PCI Configuration Space
+/// Section 6.1, PCI Local Bus Specification, 2.2
+///
+typedef struct {
+ UINT16 VendorId;
+ UINT16 DeviceId;
+ UINT16 Command;
+ UINT16 Status;
+ UINT8 RevisionID;
+ UINT8 ClassCode[3];
+ UINT8 CacheLineSize;
+ UINT8 LatencyTimer;
+ UINT8 HeaderType;
+ UINT8 BIST;
+} PCI_DEVICE_INDEPENDENT_REGION;
+
+///
+/// PCI Device header region in PCI Configuration Space
+/// Section 6.1, PCI Local Bus Specification, 2.2
+///
+typedef struct {
+ UINT32 Bar[6];
+ UINT32 CISPtr;
+ UINT16 SubsystemVendorID;
+ UINT16 SubsystemID;
+ UINT32 ExpansionRomBar;
+ UINT8 CapabilityPtr;
+ UINT8 Reserved1[3];
+ UINT32 Reserved2;
+ UINT8 InterruptLine;
+ UINT8 InterruptPin;
+ UINT8 MinGnt;
+ UINT8 MaxLat;
+} PCI_DEVICE_HEADER_TYPE_REGION;
+
+///
+/// PCI Device Configuration Space
+/// Section 6.1, PCI Local Bus Specification, 2.2
+///
+typedef struct {
+ PCI_DEVICE_INDEPENDENT_REGION Hdr;
+ PCI_DEVICE_HEADER_TYPE_REGION Device;
+} PCI_TYPE00;
+
+///
+/// PCI-PCI Bridge header region in PCI Configuration Space
+/// Section 3.2, PCI-PCI Bridge Architecture, Version 1.2
+///
+typedef struct {
+ UINT32 Bar[2];
+ UINT8 PrimaryBus;
+ UINT8 SecondaryBus;
+ UINT8 SubordinateBus;
+ UINT8 SecondaryLatencyTimer;
+ UINT8 IoBase;
+ UINT8 IoLimit;
+ UINT16 SecondaryStatus;
+ UINT16 MemoryBase;
+ UINT16 MemoryLimit;
+ UINT16 PrefetchableMemoryBase;
+ UINT16 PrefetchableMemoryLimit;
+ UINT32 PrefetchableBaseUpper32;
+ UINT32 PrefetchableLimitUpper32;
+ UINT16 IoBaseUpper16;
+ UINT16 IoLimitUpper16;
+ UINT8 CapabilityPtr;
+ UINT8 Reserved[3];
+ UINT32 ExpansionRomBAR;
+ UINT8 InterruptLine;
+ UINT8 InterruptPin;
+ UINT16 BridgeControl;
+} PCI_BRIDGE_CONTROL_REGISTER;
+
+///
+/// PCI-to-PCI Bridge Configuration Space
+/// Section 3.2, PCI-PCI Bridge Architecture, Version 1.2
+///
+typedef struct {
+ PCI_DEVICE_INDEPENDENT_REGION Hdr;
+ PCI_BRIDGE_CONTROL_REGISTER Bridge;
+} PCI_TYPE01;
+
+typedef union {
+ PCI_TYPE00 Device;
+ PCI_TYPE01 Bridge;
+} PCI_TYPE_GENERIC;
+
+///
+/// CardBus Controller Configuration Space,
+/// Section 4.5.1, PC Card Standard. 8.0
+///
+typedef struct {
+ UINT32 CardBusSocketReg; ///< Cardbus Socket/ExCA Base
+ UINT8 Cap_Ptr;
+ UINT8 Reserved;
+ UINT16 SecondaryStatus; ///< Secondary Status
+ UINT8 PciBusNumber; ///< PCI Bus Number
+ UINT8 CardBusBusNumber; ///< CardBus Bus Number
+ UINT8 SubordinateBusNumber; ///< Subordinate Bus Number
+ UINT8 CardBusLatencyTimer; ///< CardBus Latency Timer
+ UINT32 MemoryBase0; ///< Memory Base Register 0
+ UINT32 MemoryLimit0; ///< Memory Limit Register 0
+ UINT32 MemoryBase1;
+ UINT32 MemoryLimit1;
+ UINT32 IoBase0;
+ UINT32 IoLimit0; ///< I/O Base Register 0
+ UINT32 IoBase1; ///< I/O Limit Register 0
+ UINT32 IoLimit1;
+ UINT8 InterruptLine; ///< Interrupt Line
+ UINT8 InterruptPin; ///< Interrupt Pin
+ UINT16 BridgeControl; ///< Bridge Control
+} PCI_CARDBUS_CONTROL_REGISTER;
+
+//
+// Definitions of PCI class bytes and manipulation macros.
+//
+#define PCI_CLASS_OLD 0x00
+#define PCI_CLASS_OLD_OTHER 0x00
+#define PCI_CLASS_OLD_VGA 0x01
+
+#define PCI_CLASS_MASS_STORAGE 0x01
+#define PCI_CLASS_MASS_STORAGE_SCSI 0x00
+#define PCI_CLASS_MASS_STORAGE_IDE 0x01
+#define PCI_CLASS_MASS_STORAGE_FLOPPY 0x02
+#define PCI_CLASS_MASS_STORAGE_IPI 0x03
+#define PCI_CLASS_MASS_STORAGE_RAID 0x04
+#define PCI_CLASS_MASS_STORAGE_OTHER 0x80
+
+#define PCI_CLASS_NETWORK 0x02
+#define PCI_CLASS_NETWORK_ETHERNET 0x00
+#define PCI_CLASS_NETWORK_TOKENRING 0x01
+#define PCI_CLASS_NETWORK_FDDI 0x02
+#define PCI_CLASS_NETWORK_ATM 0x03
+#define PCI_CLASS_NETWORK_ISDN 0x04
+#define PCI_CLASS_NETWORK_OTHER 0x80
+
+#define PCI_CLASS_DISPLAY 0x03
+#define PCI_CLASS_DISPLAY_VGA 0x00
+#define PCI_IF_VGA_VGA 0x00
+#define PCI_IF_VGA_8514 0x01
+#define PCI_CLASS_DISPLAY_XGA 0x01
+#define PCI_CLASS_DISPLAY_3D 0x02
+#define PCI_CLASS_DISPLAY_OTHER 0x80
+
+#define PCI_CLASS_MEDIA 0x04
+#define PCI_CLASS_MEDIA_VIDEO 0x00
+#define PCI_CLASS_MEDIA_AUDIO 0x01
+#define PCI_CLASS_MEDIA_TELEPHONE 0x02
+#define PCI_CLASS_MEDIA_OTHER 0x80
+
+#define PCI_CLASS_MEMORY_CONTROLLER 0x05
+#define PCI_CLASS_MEMORY_RAM 0x00
+#define PCI_CLASS_MEMORY_FLASH 0x01
+#define PCI_CLASS_MEMORY_OTHER 0x80
+
+#define PCI_CLASS_BRIDGE 0x06
+#define PCI_CLASS_BRIDGE_HOST 0x00
+#define PCI_CLASS_BRIDGE_ISA 0x01
+#define PCI_CLASS_BRIDGE_EISA 0x02
+#define PCI_CLASS_BRIDGE_MCA 0x03
+#define PCI_CLASS_BRIDGE_P2P 0x04
+#define PCI_IF_BRIDGE_P2P 0x00
+#define PCI_IF_BRIDGE_P2P_SUBTRACTIVE 0x01
+#define PCI_CLASS_BRIDGE_PCMCIA 0x05
+#define PCI_CLASS_BRIDGE_NUBUS 0x06
+#define PCI_CLASS_BRIDGE_CARDBUS 0x07
+#define PCI_CLASS_BRIDGE_RACEWAY 0x08
+#define PCI_CLASS_BRIDGE_OTHER 0x80
+#define PCI_CLASS_BRIDGE_ISA_PDECODE 0x80
+
+#define PCI_CLASS_SCC 0x07///< Simple communications controllers
+#define PCI_SUBCLASS_SERIAL 0x00
+#define PCI_IF_GENERIC_XT 0x00
+#define PCI_IF_16450 0x01
+#define PCI_IF_16550 0x02
+#define PCI_IF_16650 0x03
+#define PCI_IF_16750 0x04
+#define PCI_IF_16850 0x05
+#define PCI_IF_16950 0x06
+#define PCI_SUBCLASS_PARALLEL 0x01
+#define PCI_IF_PARALLEL_PORT 0x00
+#define PCI_IF_BI_DIR_PARALLEL_PORT 0x01
+#define PCI_IF_ECP_PARALLEL_PORT 0x02
+#define PCI_IF_1284_CONTROLLER 0x03
+#define PCI_IF_1284_DEVICE 0xFE
+#define PCI_SUBCLASS_MULTIPORT_SERIAL 0x02
+#define PCI_SUBCLASS_MODEM 0x03
+#define PCI_IF_GENERIC_MODEM 0x00
+#define PCI_IF_16450_MODEM 0x01
+#define PCI_IF_16550_MODEM 0x02
+#define PCI_IF_16650_MODEM 0x03
+#define PCI_IF_16750_MODEM 0x04
+#define PCI_SUBCLASS_SCC_OTHER 0x80
+
+#define PCI_CLASS_SYSTEM_PERIPHERAL 0x08
+#define PCI_SUBCLASS_PIC 0x00
+#define PCI_IF_8259_PIC 0x00
+#define PCI_IF_ISA_PIC 0x01
+#define PCI_IF_EISA_PIC 0x02
+#define PCI_IF_APIC_CONTROLLER 0x10 ///< I/O APIC interrupt controller , 32 byte none-prefetchable memory.
+#define PCI_IF_APIC_CONTROLLER2 0x20
+#define PCI_SUBCLASS_DMA 0x01
+#define PCI_IF_8237_DMA 0x00
+#define PCI_IF_ISA_DMA 0x01
+#define PCI_IF_EISA_DMA 0x02
+#define PCI_SUBCLASS_TIMER 0x02
+#define PCI_IF_8254_TIMER 0x00
+#define PCI_IF_ISA_TIMER 0x01
+#define PCI_IF_EISA_TIMER 0x02
+#define PCI_SUBCLASS_RTC 0x03
+#define PCI_IF_GENERIC_RTC 0x00
+#define PCI_IF_ISA_RTC 0x01
+#define PCI_SUBCLASS_PNP_CONTROLLER 0x04 ///< HotPlug Controller
+#define PCI_SUBCLASS_PERIPHERAL_OTHER 0x80
+
+#define PCI_CLASS_INPUT_DEVICE 0x09
+#define PCI_SUBCLASS_KEYBOARD 0x00
+#define PCI_SUBCLASS_PEN 0x01
+#define PCI_SUBCLASS_MOUSE_CONTROLLER 0x02
+#define PCI_SUBCLASS_SCAN_CONTROLLER 0x03
+#define PCI_SUBCLASS_GAMEPORT 0x04
+#define PCI_IF_GAMEPORT 0x00
+#define PCI_IF_GAMEPORT1 0x10
+#define PCI_SUBCLASS_INPUT_OTHER 0x80
+
+#define PCI_CLASS_DOCKING_STATION 0x0A
+#define PCI_SUBCLASS_DOCKING_GENERIC 0x00
+#define PCI_SUBCLASS_DOCKING_OTHER 0x80
+
+#define PCI_CLASS_PROCESSOR 0x0B
+#define PCI_SUBCLASS_PROC_386 0x00
+#define PCI_SUBCLASS_PROC_486 0x01
+#define PCI_SUBCLASS_PROC_PENTIUM 0x02
+#define PCI_SUBCLASS_PROC_ALPHA 0x10
+#define PCI_SUBCLASS_PROC_POWERPC 0x20
+#define PCI_SUBCLASS_PROC_MIPS 0x30
+#define PCI_SUBCLASS_PROC_CO_PORC 0x40 ///< Co-Processor
+
+#define PCI_CLASS_SERIAL 0x0C
+#define PCI_CLASS_SERIAL_FIREWIRE 0x00
+#define PCI_IF_1394 0x00
+#define PCI_IF_1394_OPEN_HCI 0x10
+#define PCI_CLASS_SERIAL_ACCESS_BUS 0x01
+#define PCI_CLASS_SERIAL_SSA 0x02
+#define PCI_CLASS_SERIAL_USB 0x03
+#define PCI_IF_UHCI 0x00
+#define PCI_IF_OHCI 0x10
+#define PCI_IF_USB_OTHER 0x80
+#define PCI_IF_USB_DEVICE 0xFE
+#define PCI_CLASS_SERIAL_FIBRECHANNEL 0x04
+#define PCI_CLASS_SERIAL_SMB 0x05
+
+#define PCI_CLASS_WIRELESS 0x0D
+#define PCI_SUBCLASS_IRDA 0x00
+#define PCI_SUBCLASS_IR 0x01
+#define PCI_SUBCLASS_RF 0x10
+#define PCI_SUBCLASS_WIRELESS_OTHER 0x80
+
+#define PCI_CLASS_INTELLIGENT_IO 0x0E
+
+#define PCI_CLASS_SATELLITE 0x0F
+#define PCI_SUBCLASS_TV 0x01
+#define PCI_SUBCLASS_AUDIO 0x02
+#define PCI_SUBCLASS_VOICE 0x03
+#define PCI_SUBCLASS_DATA 0x04
+
+#define PCI_SECURITY_CONTROLLER 0x10 ///< Encryption and decryption controller
+#define PCI_SUBCLASS_NET_COMPUT 0x00
+#define PCI_SUBCLASS_ENTERTAINMENT 0x10
+#define PCI_SUBCLASS_SECURITY_OTHER 0x80
+
+#define PCI_CLASS_DPIO 0x11
+#define PCI_SUBCLASS_DPIO 0x00
+#define PCI_SUBCLASS_DPIO_OTHER 0x80
+
+/**
+ Macro that checks whether the Base Class code of device matched.
+
+ @param _p Specified device.
+ @param c Base Class code needs matching.
+
+ @retval TRUE Base Class code matches the specified device.
+ @retval FALSE Base Class code doesn't match the specified device.
+
+**/
+#define IS_CLASS1(_p, c) ((_p)->Hdr.ClassCode[2] == (c))
+
+/**
+ Macro that checks whether the Base Class code and Sub-Class code of device matched.
+
+ @param _p Specified device.
+ @param c Base Class code needs matching.
+ @param s Sub-Class code needs matching.
+
+ @retval TRUE Base Class code and Sub-Class code match the specified device.
+ @retval FALSE Base Class code and Sub-Class code don't match the specified device.
+
+**/
+#define IS_CLASS2(_p, c, s) (IS_CLASS1 (_p, c) && ((_p)->Hdr.ClassCode[1] == (s)))
+
+/**
+ Macro that checks whether the Base Class code, Sub-Class code and Interface code of device matched.
+
+ @param _p Specified device.
+ @param c Base Class code needs matching.
+ @param s Sub-Class code needs matching.
+ @param p Interface code needs matching.
+
+ @retval TRUE Base Class code, Sub-Class code and Interface code match the specified device.
+ @retval FALSE Base Class code, Sub-Class code and Interface code don't match the specified device.
+
+**/
+#define IS_CLASS3(_p, c, s, p) (IS_CLASS2 (_p, c, s) && ((_p)->Hdr.ClassCode[0] == (p)))
+
+/**
+ Macro that checks whether device is a display controller.
+
+ @param _p Specified device.
+
+ @retval TRUE Device is a display controller.
+ @retval FALSE Device is not a display controller.
+
+**/
+#define IS_PCI_DISPLAY(_p) IS_CLASS1 (_p, PCI_CLASS_DISPLAY)
+
+/**
+ Macro that checks whether device is a VGA-compatible controller.
+
+ @param _p Specified device.
+
+ @retval TRUE Device is a VGA-compatible controller.
+ @retval FALSE Device is not a VGA-compatible controller.
+
+**/
+#define IS_PCI_VGA(_p) IS_CLASS3 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_VGA, PCI_IF_VGA_VGA)
+
+/**
+ Macro that checks whether device is an 8514-compatible controller.
+
+ @param _p Specified device.
+
+ @retval TRUE Device is an 8514-compatible controller.
+ @retval FALSE Device is not an 8514-compatible controller.
+
+**/
+#define IS_PCI_8514(_p) IS_CLASS3 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_VGA, PCI_IF_VGA_8514)
+
+/**
+ Macro that checks whether device is built before the Class Code field was defined.
+
+ @param _p Specified device.
+
+ @retval TRUE Device is an old device.
+ @retval FALSE Device is not an old device.
+
+**/
+#define IS_PCI_OLD(_p) IS_CLASS1 (_p, PCI_CLASS_OLD)
+
+/**
+ Macro that checks whether device is a VGA-compatible device built before the Class Code field was defined.
+
+ @param _p Specified device.
+
+ @retval TRUE Device is an old VGA-compatible device.
+ @retval FALSE Device is not an old VGA-compatible device.
+
+**/
+#define IS_PCI_OLD_VGA(_p) IS_CLASS2 (_p, PCI_CLASS_OLD, PCI_CLASS_OLD_VGA)
+
+/**
+ Macro that checks whether device is an IDE controller.
+
+ @param _p Specified device.
+
+ @retval TRUE Device is an IDE controller.
+ @retval FALSE Device is not an IDE controller.
+
+**/
+#define IS_PCI_IDE(_p) IS_CLASS2 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_IDE)
+
+/**
+ Macro that checks whether device is a SCSI bus controller.
+
+ @param _p Specified device.
+
+ @retval TRUE Device is a SCSI bus controller.
+ @retval FALSE Device is not a SCSI bus controller.
+
+**/
+#define IS_PCI_SCSI(_p) IS_CLASS2 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_SCSI)
+
+/**
+ Macro that checks whether device is a RAID controller.
+
+ @param _p Specified device.
+
+ @retval TRUE Device is a RAID controller.
+ @retval FALSE Device is not a RAID controller.
+
+**/
+#define IS_PCI_RAID(_p) IS_CLASS2 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_RAID)
+
+/**
+ Macro that checks whether device is an ISA bridge.
+
+ @param _p Specified device.
+
+ @retval TRUE Device is an ISA bridge.
+ @retval FALSE Device is not an ISA bridge.
+
+**/
+#define IS_PCI_LPC(_p) IS_CLASS2 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_ISA)
+
+/**
+ Macro that checks whether device is a PCI-to-PCI bridge.
+
+ @param _p Specified device.
+
+ @retval TRUE Device is a PCI-to-PCI bridge.
+ @retval FALSE Device is not a PCI-to-PCI bridge.
+
+**/
+#define IS_PCI_P2P(_p) IS_CLASS3 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_P2P, PCI_IF_BRIDGE_P2P)
+
+/**
+ Macro that checks whether device is a Subtractive Decode PCI-to-PCI bridge.
+
+ @param _p Specified device.
+
+ @retval TRUE Device is a Subtractive Decode PCI-to-PCI bridge.
+ @retval FALSE Device is not a Subtractive Decode PCI-to-PCI bridge.
+
+**/
+#define IS_PCI_P2P_SUB(_p) IS_CLASS3 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_P2P, PCI_IF_BRIDGE_P2P_SUBTRACTIVE)
+
+/**
+ Macro that checks whether device is a 16550-compatible serial controller.
+
+ @param _p Specified device.
+
+ @retval TRUE Device is a 16550-compatible serial controller.
+ @retval FALSE Device is not a 16550-compatible serial controller.
+
+**/
+#define IS_PCI_16550_SERIAL(_p) IS_CLASS3 (_p, PCI_CLASS_SCC, PCI_SUBCLASS_SERIAL, PCI_IF_16550)
+
+/**
+ Macro that checks whether device is a Universal Serial Bus controller.
+
+ @param _p Specified device.
+
+ @retval TRUE Device is a Universal Serial Bus controller.
+ @retval FALSE Device is not a Universal Serial Bus controller.
+
+**/
+#define IS_PCI_USB(_p) IS_CLASS2 (_p, PCI_CLASS_SERIAL, PCI_CLASS_SERIAL_USB)
+
+//
+// the definition of Header Type
+//
+#define HEADER_TYPE_DEVICE 0x00
+#define HEADER_TYPE_PCI_TO_PCI_BRIDGE 0x01
+#define HEADER_TYPE_CARDBUS_BRIDGE 0x02
+#define HEADER_TYPE_MULTI_FUNCTION 0x80
+//
+// Mask of Header type
+//
+#define HEADER_LAYOUT_CODE 0x7f
+
+/**
+ Macro that checks whether device is a PCI-PCI bridge.
+
+ @param _p Specified device.
+
+ @retval TRUE Device is a PCI-PCI bridge.
+ @retval FALSE Device is not a PCI-PCI bridge.
+
+**/
+#define IS_PCI_BRIDGE(_p) (((_p)->Hdr.HeaderType & HEADER_LAYOUT_CODE) == (HEADER_TYPE_PCI_TO_PCI_BRIDGE))
+
+/**
+ Macro that checks whether device is a CardBus bridge.
+
+ @param _p Specified device.
+
+ @retval TRUE Device is a CardBus bridge.
+ @retval FALSE Device is not a CardBus bridge.
+
+**/
+#define IS_CARDBUS_BRIDGE(_p) (((_p)->Hdr.HeaderType & HEADER_LAYOUT_CODE) == (HEADER_TYPE_CARDBUS_BRIDGE))
+
+/**
+ Macro that checks whether device is a multiple functions device.
+
+ @param _p Specified device.
+
+ @retval TRUE Device is a multiple functions device.
+ @retval FALSE Device is not a multiple functions device.
+
+**/
+#define IS_PCI_MULTI_FUNC(_p) ((_p)->Hdr.HeaderType & HEADER_TYPE_MULTI_FUNCTION)
+
+///
+/// Rom Base Address in Bridge, defined in PCI-to-PCI Bridge Architecture Specification,
+///
+#define PCI_BRIDGE_ROMBAR 0x38
+
+#define PCI_MAX_BAR 0x0006
+#define PCI_MAX_CONFIG_OFFSET 0x0100
+
+#define PCI_VENDOR_ID_OFFSET 0x00
+#define PCI_DEVICE_ID_OFFSET 0x02
+#define PCI_COMMAND_OFFSET 0x04
+#define PCI_PRIMARY_STATUS_OFFSET 0x06
+#define PCI_REVISION_ID_OFFSET 0x08
+#define PCI_CLASSCODE_OFFSET 0x09
+#define PCI_CACHELINE_SIZE_OFFSET 0x0C
+#define PCI_LATENCY_TIMER_OFFSET 0x0D
+#define PCI_HEADER_TYPE_OFFSET 0x0E
+#define PCI_BIST_OFFSET 0x0F
+#define PCI_BASE_ADDRESSREG_OFFSET 0x10
+#define PCI_CARDBUS_CIS_OFFSET 0x28
+#define PCI_SVID_OFFSET 0x2C ///< SubSystem Vendor id
+#define PCI_SUBSYSTEM_VENDOR_ID_OFFSET 0x2C
+#define PCI_SID_OFFSET 0x2E ///< SubSystem ID
+#define PCI_SUBSYSTEM_ID_OFFSET 0x2E
+#define PCI_EXPANSION_ROM_BASE 0x30
+#define PCI_CAPBILITY_POINTER_OFFSET 0x34
+#define PCI_INT_LINE_OFFSET 0x3C ///< Interrupt Line Register
+#define PCI_INT_PIN_OFFSET 0x3D ///< Interrupt Pin Register
+#define PCI_MAXGNT_OFFSET 0x3E ///< Max Grant Register
+#define PCI_MAXLAT_OFFSET 0x3F ///< Max Latency Register
+
+//
+// defined in PCI-to-PCI Bridge Architecture Specification
+//
+#define PCI_BRIDGE_PRIMARY_BUS_REGISTER_OFFSET 0x18
+#define PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET 0x19
+#define PCI_BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET 0x1a
+#define PCI_BRIDGE_SECONDARY_LATENCY_TIMER_OFFSET 0x1b
+#define PCI_BRIDGE_STATUS_REGISTER_OFFSET 0x1E
+#define PCI_BRIDGE_CONTROL_REGISTER_OFFSET 0x3E
+
+///
+/// Interrupt Line "Unknown" or "No connection" value defined for x86 based system
+///
+#define PCI_INT_LINE_UNKNOWN 0xFF
+
+///
+/// PCI Access Data Format
+///
+typedef union {
+ struct {
+ UINT32 Reg : 8;
+ UINT32 Func : 3;
+ UINT32 Dev : 5;
+ UINT32 Bus : 8;
+ UINT32 Reserved : 7;
+ UINT32 Enable : 1;
+ } Bits;
+ UINT32 Uint32;
+} PCI_CONFIG_ACCESS_CF8;
+
+#pragma pack()
+
+#define EFI_PCI_COMMAND_IO_SPACE BIT0 ///< 0x0001
+#define EFI_PCI_COMMAND_MEMORY_SPACE BIT1 ///< 0x0002
+#define EFI_PCI_COMMAND_BUS_MASTER BIT2 ///< 0x0004
+#define EFI_PCI_COMMAND_SPECIAL_CYCLE BIT3 ///< 0x0008
+#define EFI_PCI_COMMAND_MEMORY_WRITE_AND_INVALIDATE BIT4 ///< 0x0010
+#define EFI_PCI_COMMAND_VGA_PALETTE_SNOOP BIT5 ///< 0x0020
+#define EFI_PCI_COMMAND_PARITY_ERROR_RESPOND BIT6 ///< 0x0040
+#define EFI_PCI_COMMAND_STEPPING_CONTROL BIT7 ///< 0x0080
+#define EFI_PCI_COMMAND_SERR BIT8 ///< 0x0100
+#define EFI_PCI_COMMAND_FAST_BACK_TO_BACK BIT9 ///< 0x0200
+
+//
+// defined in PCI-to-PCI Bridge Architecture Specification
+//
+#define EFI_PCI_BRIDGE_CONTROL_PARITY_ERROR_RESPONSE BIT0 ///< 0x0001
+#define EFI_PCI_BRIDGE_CONTROL_SERR BIT1 ///< 0x0002
+#define EFI_PCI_BRIDGE_CONTROL_ISA BIT2 ///< 0x0004
+#define EFI_PCI_BRIDGE_CONTROL_VGA BIT3 ///< 0x0008
+#define EFI_PCI_BRIDGE_CONTROL_VGA_16 BIT4 ///< 0x0010
+#define EFI_PCI_BRIDGE_CONTROL_MASTER_ABORT BIT5 ///< 0x0020
+#define EFI_PCI_BRIDGE_CONTROL_RESET_SECONDARY_BUS BIT6 ///< 0x0040
+#define EFI_PCI_BRIDGE_CONTROL_FAST_BACK_TO_BACK BIT7 ///< 0x0080
+#define EFI_PCI_BRIDGE_CONTROL_PRIMARY_DISCARD_TIMER BIT8 ///< 0x0100
+#define EFI_PCI_BRIDGE_CONTROL_SECONDARY_DISCARD_TIMER BIT9 ///< 0x0200
+#define EFI_PCI_BRIDGE_CONTROL_TIMER_STATUS BIT10 ///< 0x0400
+#define EFI_PCI_BRIDGE_CONTROL_DISCARD_TIMER_SERR BIT11 ///< 0x0800
+
+//
+// Following are the PCI-CARDBUS bridge control bit, defined in PC Card Standard
+//
+#define EFI_PCI_BRIDGE_CONTROL_IREQINT_ENABLE BIT7 ///< 0x0080
+#define EFI_PCI_BRIDGE_CONTROL_RANGE0_MEMORY_TYPE BIT8 ///< 0x0100
+#define EFI_PCI_BRIDGE_CONTROL_RANGE1_MEMORY_TYPE BIT9 ///< 0x0200
+#define EFI_PCI_BRIDGE_CONTROL_WRITE_POSTING_ENABLE BIT10 ///< 0x0400
+
+//
+// Following are the PCI status control bit
+//
+#define EFI_PCI_STATUS_CAPABILITY BIT4 ///< 0x0010
+#define EFI_PCI_STATUS_66MZ_CAPABLE BIT5 ///< 0x0020
+#define EFI_PCI_FAST_BACK_TO_BACK_CAPABLE BIT7 ///< 0x0080
+#define EFI_PCI_MASTER_DATA_PARITY_ERROR BIT8 ///< 0x0100
+
+///
+/// defined in PC Card Standard
+///
+#define EFI_PCI_CARDBUS_BRIDGE_CAPABILITY_PTR 0x14
+
+#pragma pack(1)
+//
+// PCI Capability List IDs and records
+//
+#define EFI_PCI_CAPABILITY_ID_PMI 0x01
+#define EFI_PCI_CAPABILITY_ID_AGP 0x02
+#define EFI_PCI_CAPABILITY_ID_VPD 0x03
+#define EFI_PCI_CAPABILITY_ID_SLOTID 0x04
+#define EFI_PCI_CAPABILITY_ID_MSI 0x05
+#define EFI_PCI_CAPABILITY_ID_HOTPLUG 0x06
+#define EFI_PCI_CAPABILITY_ID_SHPC 0x0C
+
+///
+/// Capabilities List Header
+/// Section 6.7, PCI Local Bus Specification, 2.2
+///
+typedef struct {
+ UINT8 CapabilityID;
+ UINT8 NextItemPtr;
+} EFI_PCI_CAPABILITY_HDR;
+
+///
+/// PMC - Power Management Capabilities
+/// Section 3.2.3, PCI Power Management Interface Specification, Revision 1.2
+///
+typedef union {
+ struct {
+ UINT16 Version : 3;
+ UINT16 PmeClock : 1;
+ UINT16 Reserved : 1;
+ UINT16 DeviceSpecificInitialization : 1;
+ UINT16 AuxCurrent : 3;
+ UINT16 D1Support : 1;
+ UINT16 D2Support : 1;
+ UINT16 PmeSupport : 5;
+ } Bits;
+ UINT16 Data;
+} EFI_PCI_PMC;
+
+#define EFI_PCI_PMC_D3_COLD_MASK (BIT15)
+
+///
+/// PMCSR - Power Management Control/Status
+/// Section 3.2.4, PCI Power Management Interface Specification, Revision 1.2
+///
+typedef union {
+ struct {
+ UINT16 PowerState : 2;
+ UINT16 ReservedForPciExpress : 1;
+ UINT16 NoSoftReset : 1;
+ UINT16 Reserved : 4;
+ UINT16 PmeEnable : 1;
+ UINT16 DataSelect : 4;
+ UINT16 DataScale : 2;
+ UINT16 PmeStatus : 1;
+ } Bits;
+ UINT16 Data;
+} EFI_PCI_PMCSR;
+
+#define PCI_POWER_STATE_D0 0
+#define PCI_POWER_STATE_D1 1
+#define PCI_POWER_STATE_D2 2
+#define PCI_POWER_STATE_D3_HOT 3
+
+///
+/// PMCSR_BSE - PMCSR PCI-to-PCI Bridge Support Extensions
+/// Section 3.2.5, PCI Power Management Interface Specification, Revision 1.2
+///
+typedef union {
+ struct {
+ UINT8 Reserved : 6;
+ UINT8 B2B3 : 1;
+ UINT8 BusPowerClockControl : 1;
+ } Bits;
+ UINT8 Uint8;
+} EFI_PCI_PMCSR_BSE;
+
+///
+/// Power Management Register Block Definition
+/// Section 3.2, PCI Power Management Interface Specification, Revision 1.2
+///
+typedef struct {
+ EFI_PCI_CAPABILITY_HDR Hdr;
+ EFI_PCI_PMC PMC;
+ EFI_PCI_PMCSR PMCSR;
+ EFI_PCI_PMCSR_BSE BridgeExtention;
+ UINT8 Data;
+} EFI_PCI_CAPABILITY_PMI;
+
+///
+/// A.G.P Capability
+/// Section 6.1.4, Accelerated Graphics Port Interface Specification, Revision 1.0
+///
+typedef struct {
+ EFI_PCI_CAPABILITY_HDR Hdr;
+ UINT8 Rev;
+ UINT8 Reserved;
+ UINT32 Status;
+ UINT32 Command;
+} EFI_PCI_CAPABILITY_AGP;
+
+///
+/// VPD Capability Structure
+/// Appendix I, PCI Local Bus Specification, 2.2
+///
+typedef struct {
+ EFI_PCI_CAPABILITY_HDR Hdr;
+ UINT16 AddrReg;
+ UINT32 DataReg;
+} EFI_PCI_CAPABILITY_VPD;
+
+///
+/// Slot Numbering Capabilities Register
+/// Section 3.2.6, PCI-to-PCI Bridge Architecture Specification, Revision 1.2
+///
+typedef struct {
+ EFI_PCI_CAPABILITY_HDR Hdr;
+ UINT8 ExpnsSlotReg;
+ UINT8 ChassisNo;
+} EFI_PCI_CAPABILITY_SLOTID;
+
+///
+/// Message Capability Structure for 32-bit Message Address
+/// Section 6.8.1, PCI Local Bus Specification, 2.2
+///
+typedef struct {
+ EFI_PCI_CAPABILITY_HDR Hdr;
+ UINT16 MsgCtrlReg;
+ UINT32 MsgAddrReg;
+ UINT16 MsgDataReg;
+} EFI_PCI_CAPABILITY_MSI32;
+
+///
+/// Message Capability Structure for 64-bit Message Address
+/// Section 6.8.1, PCI Local Bus Specification, 2.2
+///
+typedef struct {
+ EFI_PCI_CAPABILITY_HDR Hdr;
+ UINT16 MsgCtrlReg;
+ UINT32 MsgAddrRegLsdw;
+ UINT32 MsgAddrRegMsdw;
+ UINT16 MsgDataReg;
+} EFI_PCI_CAPABILITY_MSI64;
+
+///
+/// Capability EFI_PCI_CAPABILITY_ID_HOTPLUG,
+/// CompactPCI Hot Swap Specification PICMG 2.1, R1.0
+///
+typedef struct {
+ EFI_PCI_CAPABILITY_HDR Hdr;
+ ///
+ /// not finished - fields need to go here
+ ///
+} EFI_PCI_CAPABILITY_HOTPLUG;
+
+#define PCI_BAR_IDX0 0x00
+#define PCI_BAR_IDX1 0x01
+#define PCI_BAR_IDX2 0x02
+#define PCI_BAR_IDX3 0x03
+#define PCI_BAR_IDX4 0x04
+#define PCI_BAR_IDX5 0x05
+
+///
+/// EFI PCI Option ROM definitions
+///
+#define EFI_ROOT_BRIDGE_LIST 'eprb'
+#define EFI_PCI_EXPANSION_ROM_HEADER_EFISIGNATURE 0x0EF1 ///< defined in UEFI Spec.
+
+#define PCI_EXPANSION_ROM_HEADER_SIGNATURE 0xaa55
+#define PCI_DATA_STRUCTURE_SIGNATURE SIGNATURE_32 ('P', 'C', 'I', 'R')
+#define PCI_CODE_TYPE_PCAT_IMAGE 0x00
+#define EFI_PCI_EXPANSION_ROM_HEADER_COMPRESSED 0x0001 ///< defined in UEFI spec.
+
+///
+/// Standard PCI Expansion ROM Header
+/// Section 13.4.2, Unified Extensible Firmware Interface Specification, Version 2.1
+///
+typedef struct {
+ UINT16 Signature; ///< 0xaa55
+ UINT8 Reserved[0x16];
+ UINT16 PcirOffset;
+} PCI_EXPANSION_ROM_HEADER;
+
+///
+/// Legacy ROM Header Extensions
+/// Section 6.3.3.1, PCI Local Bus Specification, 2.2
+///
+typedef struct {
+ UINT16 Signature; ///< 0xaa55
+ UINT8 Size512;
+ UINT8 InitEntryPoint[3];
+ UINT8 Reserved[0x12];
+ UINT16 PcirOffset;
+} EFI_LEGACY_EXPANSION_ROM_HEADER;
+
+///
+/// PCI Data Structure Format
+/// Section 6.3.1.2, PCI Local Bus Specification, 2.2
+///
+typedef struct {
+ UINT32 Signature; ///< "PCIR"
+ UINT16 VendorId;
+ UINT16 DeviceId;
+ UINT16 Reserved0;
+ UINT16 Length;
+ UINT8 Revision;
+ UINT8 ClassCode[3];
+ UINT16 ImageLength;
+ UINT16 CodeRevision;
+ UINT8 CodeType;
+ UINT8 Indicator;
+ UINT16 Reserved1;
+} PCI_DATA_STRUCTURE;
+
+///
+/// EFI PCI Expansion ROM Header
+/// Section 13.4.2, Unified Extensible Firmware Interface Specification, Version 2.1
+///
+typedef struct {
+ UINT16 Signature; ///< 0xaa55
+ UINT16 InitializationSize;
+ UINT32 EfiSignature; ///< 0x0EF1
+ UINT16 EfiSubsystem;
+ UINT16 EfiMachineType;
+ UINT16 CompressionType;
+ UINT8 Reserved[8];
+ UINT16 EfiImageHeaderOffset;
+ UINT16 PcirOffset;
+} EFI_PCI_EXPANSION_ROM_HEADER;
+
+typedef union {
+ UINT8 *Raw;
+ PCI_EXPANSION_ROM_HEADER *Generic;
+ EFI_PCI_EXPANSION_ROM_HEADER *Efi;
+ EFI_LEGACY_EXPANSION_ROM_HEADER *PcAt;
+} EFI_PCI_ROM_HEADER;
+
+#pragma pack()
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/Pci23.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/Pci23.h
new file mode 100644
index 0000000000..bce5cd67ea
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/Pci23.h
@@ -0,0 +1,127 @@
+/** @file
+ Support for PCI 2.3 standard.
+
+ Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _PCI23_H_
+#define _PCI23_H_
+
+#include
+
+///
+/// PCI_CLASS_MASS_STORAGE, Base Class 01h.
+///
+///@{
+#define PCI_CLASS_MASS_STORAGE_ATA 0x05
+#define PCI_IF_MASS_STORAGE_SINGLE_DMA 0x20
+#define PCI_IF_MASS_STORAGE_CHAINED_DMA 0x30
+///@}
+
+///
+/// PCI_CLASS_NETWORK, Base Class 02h.
+///
+///@{
+#define PCI_CLASS_NETWORK_WORLDFIP 0x05
+#define PCI_CLASS_NETWORK_PICMG_MULTI_COMPUTING 0x06
+///@}
+
+///
+/// PCI_CLASS_BRIDGE, Base Class 06h.
+///
+///@{
+#define PCI_CLASS_BRIDGE_SEMI_TRANSPARENT_P2P 0x09
+#define PCI_IF_BRIDGE_SEMI_TRANSPARENT_P2P_PRIMARY 0x40
+#define PCI_IF_BRIDGE_SEMI_TRANSPARENT_P2P_SECONDARY 0x80
+#define PCI_CLASS_BRIDGE_INFINIBAND_TO_PCI 0x0A
+///@}
+
+///
+/// PCI_CLASS_SCC, Base Class 07h.
+///
+///@{
+#define PCI_SUBCLASS_GPIB 0x04
+#define PCI_SUBCLASS_SMART_CARD 0x05
+///@}
+
+///
+/// PCI_CLASS_SERIAL, Base Class 0Ch.
+///
+///@{
+#define PCI_IF_EHCI 0x20
+#define PCI_CLASS_SERIAL_IB 0x06
+#define PCI_CLASS_SERIAL_IPMI 0x07
+#define PCI_IF_IPMI_SMIC 0x00
+#define PCI_IF_IPMI_KCS 0x01 ///< Keyboard Controller Style
+#define PCI_IF_IPMI_BT 0x02 ///< Block Transfer
+#define PCI_CLASS_SERIAL_SERCOS 0x08
+#define PCI_CLASS_SERIAL_CANBUS 0x09
+///@}
+
+///
+/// PCI_CLASS_WIRELESS, Base Class 0Dh.
+///
+///@{
+#define PCI_SUBCLASS_BLUETOOTH 0x11
+#define PCI_SUBCLASS_BROADBAND 0x12
+///@}
+
+///
+/// PCI_CLASS_DPIO, Base Class 11h.
+///
+///@{
+#define PCI_SUBCLASS_PERFORMANCE_COUNTERS 0x01
+#define PCI_SUBCLASS_COMMUNICATION_SYNCHRONIZATION 0x10
+#define PCI_SUBCLASS_MANAGEMENT_CARD 0x20
+///@}
+
+///
+/// defined in PCI Express Spec.
+///
+#define PCI_EXP_MAX_CONFIG_OFFSET 0x1000
+
+///
+/// PCI Capability List IDs and records.
+///
+#define EFI_PCI_CAPABILITY_ID_PCIX 0x07
+#define EFI_PCI_CAPABILITY_ID_VENDOR 0x09
+
+#pragma pack(1)
+///
+/// PCI-X Capabilities List,
+/// Section 7.2, PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0b.
+///
+typedef struct {
+ EFI_PCI_CAPABILITY_HDR Hdr;
+ UINT16 CommandReg;
+ UINT32 StatusReg;
+} EFI_PCI_CAPABILITY_PCIX;
+
+///
+/// PCI-X Bridge Capabilities List,
+/// Section 8.6.2, PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0b.
+///
+typedef struct {
+ EFI_PCI_CAPABILITY_HDR Hdr;
+ UINT16 SecStatusReg;
+ UINT32 StatusReg;
+ UINT32 SplitTransCtrlRegUp;
+ UINT32 SplitTransCtrlRegDn;
+} EFI_PCI_CAPABILITY_PCIX_BRDG;
+
+///
+/// Vendor Specific Capability Header
+/// Table H-1: Capability IDs, PCI Local Bus Specification, 2.3
+///
+typedef struct {
+ EFI_PCI_CAPABILITY_HDR Hdr;
+ UINT8 Length;
+} EFI_PCI_CAPABILITY_VENDOR_HDR;
+
+#pragma pack()
+
+#define PCI_CODE_TYPE_EFI_IMAGE 0x03
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/Pci30.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/Pci30.h
new file mode 100644
index 0000000000..d25ac292db
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/Pci30.h
@@ -0,0 +1,72 @@
+/** @file
+ Support for PCI 3.0 standard.
+
+ Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __PCI30_H__
+#define __PCI30_H__
+
+#include
+
+///
+/// PCI_CLASS_MASS_STORAGE, Base Class 01h.
+///
+///@{
+#define PCI_CLASS_MASS_STORAGE_SATADPA 0x06
+#define PCI_IF_MASS_STORAGE_SATA 0x00
+#define PCI_IF_MASS_STORAGE_AHCI 0x01
+///@}
+
+///
+/// PCI_CLASS_WIRELESS, Base Class 0Dh.
+///
+///@{
+#define PCI_SUBCLASS_ETHERNET_80211A 0x20
+#define PCI_SUBCLASS_ETHERNET_80211B 0x21
+///@}
+
+/**
+ Macro that checks whether device is a SATA controller.
+
+ @param _p Specified device.
+
+ @retval TRUE Device is a SATA controller.
+ @retval FALSE Device is not a SATA controller.
+
+**/
+#define IS_PCI_SATADPA(_p) IS_CLASS2 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_SATADPA)
+
+///
+/// PCI Capability List IDs and records
+///
+#define EFI_PCI_CAPABILITY_ID_PCIEXP 0x10
+
+#pragma pack(1)
+
+///
+/// PCI Data Structure Format
+/// Section 5.1.2, PCI Firmware Specification, Revision 3.0
+///
+typedef struct {
+ UINT32 Signature; ///< "PCIR"
+ UINT16 VendorId;
+ UINT16 DeviceId;
+ UINT16 DeviceListOffset;
+ UINT16 Length;
+ UINT8 Revision;
+ UINT8 ClassCode[3];
+ UINT16 ImageLength;
+ UINT16 CodeRevision;
+ UINT8 CodeType;
+ UINT8 Indicator;
+ UINT16 MaxRuntimeImageLength;
+ UINT16 ConfigUtilityCodeHeaderOffset;
+ UINT16 DMTFCLPEntryPointOffset;
+} PCI_3_0_DATA_STRUCTURE;
+
+#pragma pack()
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/PciCodeId.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/PciCodeId.h
new file mode 100644
index 0000000000..e7f0cfa3dc
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/PciCodeId.h
@@ -0,0 +1,93 @@
+/** @file
+ The file lists the PCI class codes only defined in PCI code and ID assignment specification
+ revision 1.3.
+
+ Copyright (c) 2012 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __PCI_CODE_ID_H__
+#define __PCI_CODE_ID_H__
+
+///
+/// PCI_CLASS_MASS_STORAGE, Base Class 01h.
+///
+///@{
+#define PCI_IF_MASS_STORAGE_SCSI_VENDOR_SPECIFIC 0x00
+#define PCI_IF_MASS_STORAGE_SCSI_DEVICE_PQI 0x11
+#define PCI_IF_MASS_STORAGE_SCSI_CONTROLLER_PQI 0x12
+#define PCI_IF_MASS_STORAGE_SCSI_DEVICE_CONTROLLER_PQI 0x13
+#define PCI_IF_MASS_STORAGE_SCSI_DEVICE_NVM_EXPRESS 0x21
+#define PCI_IF_MASS_STORAGE_SATA_SERIAL_BUS 0x02
+#define PCI_CLASS_MASS_STORAGE_SAS 0x07
+#define PCI_IF_MASS_STORAGE_SAS 0x00
+#define PCI_IF_MASS_STORAGE_SAS_SERIAL_BUS 0x01
+#define PCI_CLASS_MASS_STORAGE_SOLID_STATE 0x08
+#define PCI_IF_MASS_STORAGE_SOLID_STATE 0x00
+#define PCI_IF_MASS_STORAGE_SOLID_STATE_NVMHCI 0x01
+#define PCI_IF_MASS_STORAGE_SOLID_STATE_ENTERPRISE_NVMHCI 0x02
+///@}
+
+///
+/// PCI_CLASS_NETWORK, Base Class 02h.
+///
+///@{
+#define PCI_CLASS_NETWORK_INFINIBAND 0x07
+///@}
+
+///
+/// PCI_CLASS_MEDIA, Base Class 04h.
+///
+///@{
+#define PCI_CLASS_MEDIA_MIXED_MODE 0x03
+///@}
+
+///
+/// PCI_CLASS_BRIDGE, Base Class 06h.
+///
+///@{
+#define PCI_CLASS_BRIDGE_ADVANCED_SWITCHING_TO_PCI 0x0B
+#define PCI_IF_BRIDGE_ADVANCED_SWITCHING_TO_PCI_CUSTOM 0x00
+#define PCI_IF_BRIDGE_ADVANCED_SWITCHING_TO_PCI_ASI_SIG 0x01
+///@}
+
+///
+/// PCI_CLASS_SYSTEM_PERIPHERAL, Base Class 08h.
+///
+///@{
+#define PCI_IF_HPET 0x03
+#define PCI_SUBCLASS_SD_HOST_CONTROLLER 0x05
+#define PCI_SUBCLASS_IOMMU 0x06
+///@}
+
+///
+/// PCI_CLASS_PROCESSOR, Base Class 0Bh.
+///
+///@{
+#define PCI_SUBCLASS_PROC_OTHER 0x80
+///@}
+
+///
+/// PCI_CLASS_SERIAL, Base Class 0Ch.
+///
+///@{
+#define PCI_IF_XHCI 0x30
+#define PCI_CLASS_SERIAL_OTHER 0x80
+///@}
+
+///
+/// PCI_CLASS_SATELLITE, Base Class 0Fh.
+///
+///@{
+#define PCI_SUBCLASS_SATELLITE_OTHER 0x80
+///@}
+
+///
+/// PCI_CLASS_PROCESSING_ACCELERATOR, Base Class 12h.
+///
+///@{
+#define PCI_CLASS_PROCESSING_ACCELERATOR 0x12
+///@}
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/PciExpress21.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/PciExpress21.h
new file mode 100644
index 0000000000..7b611c6839
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/PciExpress21.h
@@ -0,0 +1,713 @@
+/** @file
+ Support for the latest PCI standard.
+
+ Copyright (c) 2006 - 2021, Intel Corporation. All rights reserved.
+ (C) Copyright 2016 Hewlett Packard Enterprise Development LP
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _PCIEXPRESS21_H_
+#define _PCIEXPRESS21_H_
+
+#include
+
+/**
+ Macro that converts PCI Bus, PCI Device, PCI Function and PCI Register to an
+ ECAM (Enhanced Configuration Access Mechanism) address. The unused upper bits
+ of Bus, Device, Function and Register are stripped prior to the generation of
+ the address.
+
+ @param Bus PCI Bus number. Range 0..255.
+ @param Device PCI Device number. Range 0..31.
+ @param Function PCI Function number. Range 0..7.
+ @param Register PCI Register number. Range 0..4095.
+
+ @return The encode ECAM address.
+
+**/
+#define PCI_ECAM_ADDRESS(Bus, Device, Function, Offset) \
+ (((Offset) & 0xfff) | (((Function) & 0x07) << 12) | (((Device) & 0x1f) << 15) | (((Bus) & 0xff) << 20))
+
+#pragma pack(1)
+///
+/// PCI Express Capability Structure
+///
+typedef union {
+ struct {
+ UINT16 Version : 4;
+ UINT16 DevicePortType : 4;
+ UINT16 SlotImplemented : 1;
+ UINT16 InterruptMessageNumber : 5;
+ UINT16 Undefined : 1;
+ UINT16 Reserved : 1;
+ } Bits;
+ UINT16 Uint16;
+} PCI_REG_PCIE_CAPABILITY;
+
+#define PCIE_DEVICE_PORT_TYPE_PCIE_ENDPOINT 0
+#define PCIE_DEVICE_PORT_TYPE_LEGACY_PCIE_ENDPOINT 1
+#define PCIE_DEVICE_PORT_TYPE_ROOT_PORT 4
+#define PCIE_DEVICE_PORT_TYPE_UPSTREAM_PORT 5
+#define PCIE_DEVICE_PORT_TYPE_DOWNSTREAM_PORT 6
+#define PCIE_DEVICE_PORT_TYPE_PCIE_TO_PCI_BRIDGE 7
+#define PCIE_DEVICE_PORT_TYPE_PCI_TO_PCIE_BRIDGE 8
+#define PCIE_DEVICE_PORT_TYPE_ROOT_COMPLEX_INTEGRATED_ENDPOINT 9
+#define PCIE_DEVICE_PORT_TYPE_ROOT_COMPLEX_EVENT_COLLECTOR 10
+
+typedef union {
+ struct {
+ UINT32 MaxPayloadSize : 3;
+ UINT32 PhantomFunctions : 2;
+ UINT32 ExtendedTagField : 1;
+ UINT32 EndpointL0sAcceptableLatency : 3;
+ UINT32 EndpointL1AcceptableLatency : 3;
+ UINT32 Undefined : 3;
+ UINT32 RoleBasedErrorReporting : 1;
+ UINT32 Reserved : 2;
+ UINT32 CapturedSlotPowerLimitValue : 8;
+ UINT32 CapturedSlotPowerLimitScale : 2;
+ UINT32 FunctionLevelReset : 1;
+ UINT32 Reserved2 : 3;
+ } Bits;
+ UINT32 Uint32;
+} PCI_REG_PCIE_DEVICE_CAPABILITY;
+
+typedef union {
+ struct {
+ UINT16 CorrectableError : 1;
+ UINT16 NonFatalError : 1;
+ UINT16 FatalError : 1;
+ UINT16 UnsupportedRequest : 1;
+ UINT16 RelaxedOrdering : 1;
+ UINT16 MaxPayloadSize : 3;
+ UINT16 ExtendedTagField : 1;
+ UINT16 PhantomFunctions : 1;
+ UINT16 AuxPower : 1;
+ UINT16 NoSnoop : 1;
+ UINT16 MaxReadRequestSize : 3;
+ UINT16 BridgeConfigurationRetryOrFunctionLevelReset : 1;
+ } Bits;
+ UINT16 Uint16;
+} PCI_REG_PCIE_DEVICE_CONTROL;
+
+#define PCIE_MAX_PAYLOAD_SIZE_128B 0
+#define PCIE_MAX_PAYLOAD_SIZE_256B 1
+#define PCIE_MAX_PAYLOAD_SIZE_512B 2
+#define PCIE_MAX_PAYLOAD_SIZE_1024B 3
+#define PCIE_MAX_PAYLOAD_SIZE_2048B 4
+#define PCIE_MAX_PAYLOAD_SIZE_4096B 5
+#define PCIE_MAX_PAYLOAD_SIZE_RVSD1 6
+#define PCIE_MAX_PAYLOAD_SIZE_RVSD2 7
+
+#define PCIE_MAX_READ_REQ_SIZE_128B 0
+#define PCIE_MAX_READ_REQ_SIZE_256B 1
+#define PCIE_MAX_READ_REQ_SIZE_512B 2
+#define PCIE_MAX_READ_REQ_SIZE_1024B 3
+#define PCIE_MAX_READ_REQ_SIZE_2048B 4
+#define PCIE_MAX_READ_REQ_SIZE_4096B 5
+#define PCIE_MAX_READ_REQ_SIZE_RVSD1 6
+#define PCIE_MAX_READ_REQ_SIZE_RVSD2 7
+
+typedef union {
+ struct {
+ UINT16 CorrectableError : 1;
+ UINT16 NonFatalError : 1;
+ UINT16 FatalError : 1;
+ UINT16 UnsupportedRequest : 1;
+ UINT16 AuxPower : 1;
+ UINT16 TransactionsPending : 1;
+ UINT16 Reserved : 10;
+ } Bits;
+ UINT16 Uint16;
+} PCI_REG_PCIE_DEVICE_STATUS;
+
+typedef union {
+ struct {
+ UINT32 MaxLinkSpeed : 4;
+ UINT32 MaxLinkWidth : 6;
+ UINT32 Aspm : 2;
+ UINT32 L0sExitLatency : 3;
+ UINT32 L1ExitLatency : 3;
+ UINT32 ClockPowerManagement : 1;
+ UINT32 SurpriseDownError : 1;
+ UINT32 DataLinkLayerLinkActive : 1;
+ UINT32 LinkBandwidthNotification : 1;
+ UINT32 AspmOptionalityCompliance : 1;
+ UINT32 Reserved : 1;
+ UINT32 PortNumber : 8;
+ } Bits;
+ UINT32 Uint32;
+} PCI_REG_PCIE_LINK_CAPABILITY;
+
+#define PCIE_LINK_ASPM_L0S BIT0
+#define PCIE_LINK_ASPM_L1 BIT1
+
+typedef union {
+ struct {
+ UINT16 AspmControl : 2;
+ UINT16 Reserved : 1;
+ UINT16 ReadCompletionBoundary : 1;
+ UINT16 LinkDisable : 1;
+ UINT16 RetrainLink : 1;
+ UINT16 CommonClockConfiguration : 1;
+ UINT16 ExtendedSynch : 1;
+ UINT16 ClockPowerManagement : 1;
+ UINT16 HardwareAutonomousWidthDisable : 1;
+ UINT16 LinkBandwidthManagementInterrupt : 1;
+ UINT16 LinkAutonomousBandwidthInterrupt : 1;
+ } Bits;
+ UINT16 Uint16;
+} PCI_REG_PCIE_LINK_CONTROL;
+
+typedef union {
+ struct {
+ UINT16 CurrentLinkSpeed : 4;
+ UINT16 NegotiatedLinkWidth : 6;
+ UINT16 Undefined : 1;
+ UINT16 LinkTraining : 1;
+ UINT16 SlotClockConfiguration : 1;
+ UINT16 DataLinkLayerLinkActive : 1;
+ UINT16 LinkBandwidthManagement : 1;
+ UINT16 LinkAutonomousBandwidth : 1;
+ } Bits;
+ UINT16 Uint16;
+} PCI_REG_PCIE_LINK_STATUS;
+
+typedef union {
+ struct {
+ UINT32 AttentionButton : 1;
+ UINT32 PowerController : 1;
+ UINT32 MrlSensor : 1;
+ UINT32 AttentionIndicator : 1;
+ UINT32 PowerIndicator : 1;
+ UINT32 HotPlugSurprise : 1;
+ UINT32 HotPlugCapable : 1;
+ UINT32 SlotPowerLimitValue : 8;
+ UINT32 SlotPowerLimitScale : 2;
+ UINT32 ElectromechanicalInterlock : 1;
+ UINT32 NoCommandCompleted : 1;
+ UINT32 PhysicalSlotNumber : 13;
+ } Bits;
+ UINT32 Uint32;
+} PCI_REG_PCIE_SLOT_CAPABILITY;
+
+typedef union {
+ struct {
+ UINT16 AttentionButtonPressed : 1;
+ UINT16 PowerFaultDetected : 1;
+ UINT16 MrlSensorChanged : 1;
+ UINT16 PresenceDetectChanged : 1;
+ UINT16 CommandCompletedInterrupt : 1;
+ UINT16 HotPlugInterrupt : 1;
+ UINT16 AttentionIndicator : 2;
+ UINT16 PowerIndicator : 2;
+ UINT16 PowerController : 1;
+ UINT16 ElectromechanicalInterlock : 1;
+ UINT16 DataLinkLayerStateChanged : 1;
+ UINT16 Reserved : 3;
+ } Bits;
+ UINT16 Uint16;
+} PCI_REG_PCIE_SLOT_CONTROL;
+
+typedef union {
+ struct {
+ UINT16 AttentionButtonPressed : 1;
+ UINT16 PowerFaultDetected : 1;
+ UINT16 MrlSensorChanged : 1;
+ UINT16 PresenceDetectChanged : 1;
+ UINT16 CommandCompleted : 1;
+ UINT16 MrlSensor : 1;
+ UINT16 PresenceDetect : 1;
+ UINT16 ElectromechanicalInterlock : 1;
+ UINT16 DataLinkLayerStateChanged : 1;
+ UINT16 Reserved : 7;
+ } Bits;
+ UINT16 Uint16;
+} PCI_REG_PCIE_SLOT_STATUS;
+
+typedef union {
+ struct {
+ UINT16 SystemErrorOnCorrectableError : 1;
+ UINT16 SystemErrorOnNonFatalError : 1;
+ UINT16 SystemErrorOnFatalError : 1;
+ UINT16 PmeInterrupt : 1;
+ UINT16 CrsSoftwareVisibility : 1;
+ UINT16 Reserved : 11;
+ } Bits;
+ UINT16 Uint16;
+} PCI_REG_PCIE_ROOT_CONTROL;
+
+typedef union {
+ struct {
+ UINT16 CrsSoftwareVisibility : 1;
+ UINT16 Reserved : 15;
+ } Bits;
+ UINT16 Uint16;
+} PCI_REG_PCIE_ROOT_CAPABILITY;
+
+typedef union {
+ struct {
+ UINT32 PmeRequesterId : 16;
+ UINT32 PmeStatus : 1;
+ UINT32 PmePending : 1;
+ UINT32 Reserved : 14;
+ } Bits;
+ UINT32 Uint32;
+} PCI_REG_PCIE_ROOT_STATUS;
+
+typedef union {
+ struct {
+ UINT32 CompletionTimeoutRanges : 4;
+ UINT32 CompletionTimeoutDisable : 1;
+ UINT32 AriForwarding : 1;
+ UINT32 AtomicOpRouting : 1;
+ UINT32 AtomicOp32Completer : 1;
+ UINT32 AtomicOp64Completer : 1;
+ UINT32 Cas128Completer : 1;
+ UINT32 NoRoEnabledPrPrPassing : 1;
+ UINT32 LtrMechanism : 1;
+ UINT32 TphCompleter : 2;
+ UINT32 LnSystemCLS : 2;
+ UINT32 TenBitTagCompleterSupported : 1;
+ UINT32 TenBitTagRequesterSupported : 1;
+ UINT32 Obff : 2;
+ UINT32 ExtendedFmtField : 1;
+ UINT32 EndEndTlpPrefix : 1;
+ UINT32 MaxEndEndTlpPrefixes : 2;
+ UINT32 EmergencyPowerReductionSupported : 2;
+ UINT32 EmergencyPowerReductionInitializationRequired : 1;
+ UINT32 Reserved3 : 4;
+ UINT32 FrsSupported : 1;
+ } Bits;
+ UINT32 Uint32;
+} PCI_REG_PCIE_DEVICE_CAPABILITY2;
+
+#define PCIE_COMPLETION_TIMEOUT_NOT_SUPPORTED 0
+#define PCIE_COMPLETION_TIMEOUT_RANGE_A_SUPPORTED 1
+#define PCIE_COMPLETION_TIMEOUT_RANGE_B_SUPPORTED 2
+#define PCIE_COMPLETION_TIMEOUT_RANGE_A_B_SUPPORTED 3
+#define PCIE_COMPLETION_TIMEOUT_RANGE_B_C_SUPPORTED 6
+#define PCIE_COMPLETION_TIMEOUT_RANGE_A_B_C_SUPPORTED 7
+#define PCIE_COMPLETION_TIMEOUT_RANGE_B_C_D_SUPPORTED 14
+#define PCIE_COMPLETION_TIMEOUT_RANGE_A_B_C_D_SUPPORTED 15
+
+#define PCIE_DEVICE_CAPABILITY_OBFF_MESSAGE BIT0
+#define PCIE_DEVICE_CAPABILITY_OBFF_WAKE BIT1
+
+typedef union {
+ struct {
+ UINT16 CompletionTimeoutValue : 4;
+ UINT16 CompletionTimeoutDisable : 1;
+ UINT16 AriForwarding : 1;
+ UINT16 AtomicOpRequester : 1;
+ UINT16 AtomicOpEgressBlocking : 1;
+ UINT16 IdoRequest : 1;
+ UINT16 IdoCompletion : 1;
+ UINT16 LtrMechanism : 1;
+ UINT16 EmergencyPowerReductionRequest : 1;
+ UINT16 TenBitTagRequesterEnable : 1;
+ UINT16 Obff : 2;
+ UINT16 EndEndTlpPrefixBlocking : 1;
+ } Bits;
+ UINT16 Uint16;
+} PCI_REG_PCIE_DEVICE_CONTROL2;
+
+#define PCIE_COMPLETION_TIMEOUT_50US_50MS 0
+#define PCIE_COMPLETION_TIMEOUT_50US_100US 1
+#define PCIE_COMPLETION_TIMEOUT_1MS_10MS 2
+#define PCIE_COMPLETION_TIMEOUT_16MS_55MS 5
+#define PCIE_COMPLETION_TIMEOUT_65MS_210MS 6
+#define PCIE_COMPLETION_TIMEOUT_260MS_900MS 9
+#define PCIE_COMPLETION_TIMEOUT_1S_3_5S 10
+#define PCIE_COMPLETION_TIMEOUT_4S_13S 13
+#define PCIE_COMPLETION_TIMEOUT_17S_64S 14
+
+#define PCIE_DEVICE_CONTROL_OBFF_DISABLED 0
+#define PCIE_DEVICE_CONTROL_OBFF_MESSAGE_A 1
+#define PCIE_DEVICE_CONTROL_OBFF_MESSAGE_B 2
+#define PCIE_DEVICE_CONTROL_OBFF_WAKE 3
+
+typedef union {
+ struct {
+ UINT32 Reserved : 1;
+ UINT32 LinkSpeedsVector : 7;
+ UINT32 Crosslink : 1;
+ UINT32 Reserved2 : 23;
+ } Bits;
+ UINT32 Uint32;
+} PCI_REG_PCIE_LINK_CAPABILITY2;
+
+typedef union {
+ struct {
+ UINT16 TargetLinkSpeed : 4;
+ UINT16 EnterCompliance : 1;
+ UINT16 HardwareAutonomousSpeedDisable : 1;
+ UINT16 SelectableDeemphasis : 1;
+ UINT16 TransmitMargin : 3;
+ UINT16 EnterModifiedCompliance : 1;
+ UINT16 ComplianceSos : 1;
+ UINT16 CompliancePresetDeemphasis : 4;
+ } Bits;
+ UINT16 Uint16;
+} PCI_REG_PCIE_LINK_CONTROL2;
+
+typedef union {
+ struct {
+ UINT16 CurrentDeemphasisLevel : 1;
+ UINT16 EqualizationComplete : 1;
+ UINT16 EqualizationPhase1Successful : 1;
+ UINT16 EqualizationPhase2Successful : 1;
+ UINT16 EqualizationPhase3Successful : 1;
+ UINT16 LinkEqualizationRequest : 1;
+ UINT16 Reserved : 10;
+ } Bits;
+ UINT16 Uint16;
+} PCI_REG_PCIE_LINK_STATUS2;
+
+typedef struct {
+ EFI_PCI_CAPABILITY_HDR Hdr;
+ PCI_REG_PCIE_CAPABILITY Capability;
+ PCI_REG_PCIE_DEVICE_CAPABILITY DeviceCapability;
+ PCI_REG_PCIE_DEVICE_CONTROL DeviceControl;
+ PCI_REG_PCIE_DEVICE_STATUS DeviceStatus;
+ PCI_REG_PCIE_LINK_CAPABILITY LinkCapability;
+ PCI_REG_PCIE_LINK_CONTROL LinkControl;
+ PCI_REG_PCIE_LINK_STATUS LinkStatus;
+ PCI_REG_PCIE_SLOT_CAPABILITY SlotCapability;
+ PCI_REG_PCIE_SLOT_CONTROL SlotControl;
+ PCI_REG_PCIE_SLOT_STATUS SlotStatus;
+ PCI_REG_PCIE_ROOT_CONTROL RootControl;
+ PCI_REG_PCIE_ROOT_CAPABILITY RootCapability;
+ PCI_REG_PCIE_ROOT_STATUS RootStatus;
+ PCI_REG_PCIE_DEVICE_CAPABILITY2 DeviceCapability2;
+ PCI_REG_PCIE_DEVICE_CONTROL2 DeviceControl2;
+ UINT16 DeviceStatus2;
+ PCI_REG_PCIE_LINK_CAPABILITY2 LinkCapability2;
+ PCI_REG_PCIE_LINK_CONTROL2 LinkControl2;
+ PCI_REG_PCIE_LINK_STATUS2 LinkStatus2;
+ UINT32 SlotCapability2;
+ UINT16 SlotControl2;
+ UINT16 SlotStatus2;
+} PCI_CAPABILITY_PCIEXP;
+
+#define EFI_PCIE_CAPABILITY_BASE_OFFSET 0x100
+#define EFI_PCIE_CAPABILITY_ID_SRIOV_CONTROL_ARI_HIERARCHY 0x10
+#define EFI_PCIE_CAPABILITY_DEVICE_CAPABILITIES_2_OFFSET 0x24
+#define EFI_PCIE_CAPABILITY_DEVICE_CAPABILITIES_2_ARI_FORWARDING 0x20
+#define EFI_PCIE_CAPABILITY_DEVICE_CONTROL_2_OFFSET 0x28
+#define EFI_PCIE_CAPABILITY_DEVICE_CONTROL_2_ARI_FORWARDING 0x20
+
+//
+// for SR-IOV
+//
+#define EFI_PCIE_CAPABILITY_ID_ARI 0x0E
+#define EFI_PCIE_CAPABILITY_ID_ATS 0x0F
+#define EFI_PCIE_CAPABILITY_ID_SRIOV 0x10
+#define EFI_PCIE_CAPABILITY_ID_MRIOV 0x11
+
+typedef struct {
+ UINT32 CapabilityHeader;
+ UINT32 Capability;
+ UINT16 Control;
+ UINT16 Status;
+ UINT16 InitialVFs;
+ UINT16 TotalVFs;
+ UINT16 NumVFs;
+ UINT8 FunctionDependencyLink;
+ UINT8 Reserved0;
+ UINT16 FirstVFOffset;
+ UINT16 VFStride;
+ UINT16 Reserved1;
+ UINT16 VFDeviceID;
+ UINT32 SupportedPageSize;
+ UINT32 SystemPageSize;
+ UINT32 VFBar[6];
+ UINT32 VFMigrationStateArrayOffset;
+} SR_IOV_CAPABILITY_REGISTER;
+
+#define EFI_PCIE_CAPABILITY_ID_SRIOV_CAPABILITIES 0x04
+#define EFI_PCIE_CAPABILITY_ID_SRIOV_CONTROL 0x08
+#define EFI_PCIE_CAPABILITY_ID_SRIOV_STATUS 0x0A
+#define EFI_PCIE_CAPABILITY_ID_SRIOV_INITIALVFS 0x0C
+#define EFI_PCIE_CAPABILITY_ID_SRIOV_TOTALVFS 0x0E
+#define EFI_PCIE_CAPABILITY_ID_SRIOV_NUMVFS 0x10
+#define EFI_PCIE_CAPABILITY_ID_SRIOV_FUNCTION_DEPENDENCY_LINK 0x12
+#define EFI_PCIE_CAPABILITY_ID_SRIOV_FIRSTVF 0x14
+#define EFI_PCIE_CAPABILITY_ID_SRIOV_VFSTRIDE 0x16
+#define EFI_PCIE_CAPABILITY_ID_SRIOV_VFDEVICEID 0x1A
+#define EFI_PCIE_CAPABILITY_ID_SRIOV_SUPPORTED_PAGE_SIZE 0x1C
+#define EFI_PCIE_CAPABILITY_ID_SRIOV_SYSTEM_PAGE_SIZE 0x20
+#define EFI_PCIE_CAPABILITY_ID_SRIOV_BAR0 0x24
+#define EFI_PCIE_CAPABILITY_ID_SRIOV_BAR1 0x28
+#define EFI_PCIE_CAPABILITY_ID_SRIOV_BAR2 0x2C
+#define EFI_PCIE_CAPABILITY_ID_SRIOV_BAR3 0x30
+#define EFI_PCIE_CAPABILITY_ID_SRIOV_BAR4 0x34
+#define EFI_PCIE_CAPABILITY_ID_SRIOV_BAR5 0x38
+#define EFI_PCIE_CAPABILITY_ID_SRIOV_VF_MIGRATION_STATE 0x3C
+
+typedef struct {
+ UINT32 CapabilityId : 16;
+ UINT32 CapabilityVersion : 4;
+ UINT32 NextCapabilityOffset : 12;
+} PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER;
+
+#define PCI_EXP_EXT_HDR PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER
+
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_ADVANCED_ERROR_REPORTING_ID 0x0001
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_ADVANCED_ERROR_REPORTING_VER1 0x1
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_ADVANCED_ERROR_REPORTING_VER2 0x2
+
+typedef union {
+ struct {
+ UINT32 Undefined : 1;
+ UINT32 Reserved : 3;
+ UINT32 DataLinkProtocolError : 1;
+ UINT32 SurpriseDownError : 1;
+ UINT32 Reserved2 : 6;
+ UINT32 PoisonedTlp : 1;
+ UINT32 FlowControlProtocolError : 1;
+ UINT32 CompletionTimeout : 1;
+ UINT32 CompleterAbort : 1;
+ UINT32 UnexpectedCompletion : 1;
+ UINT32 ReceiverOverflow : 1;
+ UINT32 MalformedTlp : 1;
+ UINT32 EcrcError : 1;
+ UINT32 UnsupportedRequestError : 1;
+ UINT32 AcsVoilation : 1;
+ UINT32 UncorrectableInternalError : 1;
+ UINT32 McBlockedTlp : 1;
+ UINT32 AtomicOpEgressBlocked : 1;
+ UINT32 TlpPrefixBlockedError : 1;
+ UINT32 Reserved3 : 6;
+ } Bits;
+ UINT32 Uint32;
+} PCI_EXPRESS_REG_UNCORRECTABLE_ERROR;
+
+typedef struct {
+ PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;
+ PCI_EXPRESS_REG_UNCORRECTABLE_ERROR UncorrectableErrorStatus;
+ PCI_EXPRESS_REG_UNCORRECTABLE_ERROR UncorrectableErrorMask;
+ PCI_EXPRESS_REG_UNCORRECTABLE_ERROR UncorrectableErrorSeverity;
+ UINT32 CorrectableErrorStatus;
+ UINT32 CorrectableErrorMask;
+ UINT32 AdvancedErrorCapabilitiesAndControl;
+ UINT32 HeaderLog[4];
+ UINT32 RootErrorCommand;
+ UINT32 RootErrorStatus;
+ UINT16 ErrorSourceIdentification;
+ UINT16 CorrectableErrorSourceIdentification;
+ UINT32 TlpPrefixLog[4];
+} PCI_EXPRESS_EXTENDED_CAPABILITIES_ADVANCED_ERROR_REPORTING;
+
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_VIRTUAL_CHANNEL_ID 0x0002
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_VIRTUAL_CHANNEL_MFVC 0x0009
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_VIRTUAL_CHANNEL_VER1 0x1
+
+typedef struct {
+ UINT32 VcResourceCapability : 24;
+ UINT32 PortArbTableOffset : 8;
+ UINT32 VcResourceControl;
+ UINT16 Reserved1;
+ UINT16 VcResourceStatus;
+} PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_VC;
+
+typedef struct {
+ PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;
+ UINT32 ExtendedVcCount : 3;
+ UINT32 PortVcCapability1 : 29;
+ UINT32 PortVcCapability2 : 24;
+ UINT32 VcArbTableOffset : 8;
+ UINT16 PortVcControl;
+ UINT16 PortVcStatus;
+ PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_VC Capability[1];
+} PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_CAPABILITY;
+
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_SERIAL_NUMBER_ID 0x0003
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_SERIAL_NUMBER_VER1 0x1
+
+typedef struct {
+ PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;
+ UINT64 SerialNumber;
+} PCI_EXPRESS_EXTENDED_CAPABILITIES_SERIAL_NUMBER;
+
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_DECLARATION_ID 0x0005
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_DECLARATION_VER1 0x1
+
+typedef struct {
+ PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;
+ UINT32 ElementSelfDescription;
+ UINT32 Reserved;
+ UINT32 LinkEntry[1];
+} PCI_EXPRESS_EXTENDED_CAPABILITIES_LINK_DECLARATION;
+
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_DECLARATION_GET_LINK_COUNT(LINK_DECLARATION) (UINT8)(((LINK_DECLARATION->ElementSelfDescription)&0x0000ff00)>>8)
+
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_CONTROL_ID 0x0006
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_CONTROL_VER1 0x1
+
+typedef struct {
+ PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;
+ UINT32 RootComplexLinkCapabilities;
+ UINT16 RootComplexLinkControl;
+ UINT16 RootComplexLinkStatus;
+} PCI_EXPRESS_EXTENDED_CAPABILITIES_INTERNAL_LINK_CONTROL;
+
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_POWER_BUDGETING_ID 0x0004
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_POWER_BUDGETING_VER1 0x1
+
+typedef struct {
+ PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;
+ UINT32 DataSelect : 8;
+ UINT32 Reserved : 24;
+ UINT32 Data;
+ UINT32 PowerBudgetCapability : 1;
+ UINT32 Reserved2 : 7;
+ UINT32 Reserved3 : 24;
+} PCI_EXPRESS_EXTENDED_CAPABILITIES_POWER_BUDGETING;
+
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_ID 0x000D
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_VER1 0x1
+
+typedef struct {
+ PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;
+ UINT16 AcsCapability;
+ UINT16 AcsControl;
+ UINT8 EgressControlVectorArray[1];
+} PCI_EXPRESS_EXTENDED_CAPABILITIES_ACS_EXTENDED;
+
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_GET_EGRES_CONTROL(ACS_EXTENDED) (UINT8)(((ACS_EXTENDED->AcsCapability)&0x00000020))
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_GET_EGRES_VECTOR_SIZE(ACS_EXTENDED) (UINT8)(((ACS_EXTENDED->AcsCapability)&0x0000FF00))
+
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_EVENT_COLLECTOR_ENDPOINT_ASSOCIATION_ID 0x0007
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_EVENT_COLLECTOR_ENDPOINT_ASSOCIATION_VER1 0x1
+
+typedef struct {
+ PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;
+ UINT32 AssociationBitmap;
+} PCI_EXPRESS_EXTENDED_CAPABILITIES_EVENT_COLLECTOR_ENDPOINT_ASSOCIATION;
+
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_MULTI_FUNCTION_VIRTUAL_CHANNEL_ID 0x0008
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_MULTI_FUNCTION_VIRTUAL_CHANNEL_VER1 0x1
+
+typedef PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_CAPABILITY PCI_EXPRESS_EXTENDED_CAPABILITIES_MULTI_FUNCTION_VIRTUAL_CHANNEL_CAPABILITY;
+
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_VENDOR_SPECIFIC_ID 0x000B
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_VENDOR_SPECIFIC_VER1 0x1
+
+typedef struct {
+ PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;
+ UINT32 VendorSpecificHeader;
+ UINT8 VendorSpecific[1];
+} PCI_EXPRESS_EXTENDED_CAPABILITIES_VENDOR_SPECIFIC;
+
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_VENDOR_SPECIFIC_GET_SIZE(VENDOR) (UINT16)(((VENDOR->VendorSpecificHeader)&0xFFF00000)>>20)
+
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_RCRB_HEADER_ID 0x000A
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_RCRB_HEADER_VER1 0x1
+
+typedef struct {
+ PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;
+ UINT16 VendorId;
+ UINT16 DeviceId;
+ UINT32 RcrbCapabilities;
+ UINT32 RcrbControl;
+ UINT32 Reserved;
+} PCI_EXPRESS_EXTENDED_CAPABILITIES_RCRB_HEADER;
+
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_MULTICAST_ID 0x0012
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_MULTICAST_VER1 0x1
+
+typedef struct {
+ PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;
+ UINT16 MultiCastCapability;
+ UINT16 MulticastControl;
+ UINT64 McBaseAddress;
+ UINT64 McReceiveAddress;
+ UINT64 McBlockAll;
+ UINT64 McBlockUntranslated;
+ UINT64 McOverlayBar;
+} PCI_EXPRESS_EXTENDED_CAPABILITIES_MULTICAST;
+
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_RESIZABLE_BAR_ID 0x0015
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_RESIZABLE_BAR_VER1 0x1
+
+typedef union {
+ struct {
+ UINT32 Reserved : 4;
+ UINT32 BarSizeCapability : 28;
+ } Bits;
+ UINT32 Uint32;
+} PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_CAPABILITY;
+
+typedef union {
+ struct {
+ UINT32 BarIndex : 3;
+ UINT32 Reserved : 2;
+ UINT32 ResizableBarNumber : 3;
+ UINT32 BarSize : 6;
+ UINT32 Reserved2 : 2;
+ UINT32 BarSizeCapability : 16;
+ } Bits;
+ UINT32 Uint32;
+} PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_CONTROL;
+
+typedef struct {
+ PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_CAPABILITY ResizableBarCapability;
+ PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_CONTROL ResizableBarControl;
+} PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_ENTRY;
+
+typedef struct {
+ PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;
+ PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_ENTRY Capability[1];
+} PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR;
+
+#define GET_NUMBER_RESIZABLE_BARS(x) (x->Capability[0].ResizableBarControl.Bits.ResizableBarNumber)
+
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_ARI_CAPABILITY_ID 0x000E
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_ARI_CAPABILITY_VER1 0x1
+
+typedef struct {
+ PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;
+ UINT16 AriCapability;
+ UINT16 AriControl;
+} PCI_EXPRESS_EXTENDED_CAPABILITIES_ARI_CAPABILITY;
+
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_DYNAMIC_POWER_ALLOCATION_ID 0x0016
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_DYNAMIC_POWER_ALLOCATION_VER1 0x1
+
+typedef struct {
+ PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;
+ UINT32 DpaCapability;
+ UINT32 DpaLatencyIndicator;
+ UINT16 DpaStatus;
+ UINT16 DpaControl;
+ UINT8 DpaPowerAllocationArray[1];
+} PCI_EXPRESS_EXTENDED_CAPABILITIES_DYNAMIC_POWER_ALLOCATION;
+
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_DYNAMIC_POWER_ALLOCATION_GET_SUBSTATE_MAX(POWER) (UINT16)(((POWER->DpaCapability)&0x0000000F))
+
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_LATENCE_TOLERANCE_REPORTING_ID 0x0018
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_LATENCE_TOLERANCE_REPORTING_VER1 0x1
+
+typedef struct {
+ PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;
+ UINT16 MaxSnoopLatency;
+ UINT16 MaxNoSnoopLatency;
+} PCI_EXPRESS_EXTENDED_CAPABILITIES_LATENCE_TOLERANCE_REPORTING;
+
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_TPH_ID 0x0017
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_TPH_VER1 0x1
+
+typedef struct {
+ PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;
+ UINT32 TphRequesterCapability;
+ UINT32 TphRequesterControl;
+ UINT16 TphStTable[1];
+} PCI_EXPRESS_EXTENDED_CAPABILITIES_TPH;
+
+#define GET_TPH_TABLE_SIZE(x) ((x->TphRequesterCapability & 0x7FF0000)>>16) * sizeof(UINT16)
+
+#pragma pack()
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/PciExpress30.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/PciExpress30.h
new file mode 100644
index 0000000000..5db3b66804
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/PciExpress30.h
@@ -0,0 +1,51 @@
+/** @file
+ Support for the PCI Express 3.0 standard.
+
+ This header file may not define all structures. Please extend as required.
+
+ Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _PCIEXPRESS30_H_
+#define _PCIEXPRESS30_H_
+
+#include
+
+#pragma pack(1)
+
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_SECONDARY_PCIE_ID 0x0019
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_SECONDARY_PCIE_VER1 0x1
+
+typedef union {
+ struct {
+ UINT32 PerformEqualization : 1;
+ UINT32 LinkEqualizationRequestInterruptEnable : 1;
+ UINT32 Reserved : 30;
+ } Bits;
+ UINT32 Uint32;
+} PCI_EXPRESS_REG_LINK_CONTROL3;
+
+typedef union {
+ struct {
+ UINT16 DownstreamPortTransmitterPreset : 4;
+ UINT16 DownstreamPortReceiverPresetHint : 3;
+ UINT16 Reserved : 1;
+ UINT16 UpstreamPortTransmitterPreset : 4;
+ UINT16 UpstreamPortReceiverPresetHint : 3;
+ UINT16 Reserved2 : 1;
+ } Bits;
+ UINT16 Uint16;
+} PCI_EXPRESS_REG_LANE_EQUALIZATION_CONTROL;
+
+typedef struct {
+ PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;
+ PCI_EXPRESS_REG_LINK_CONTROL3 LinkControl3;
+ UINT32 LaneErrorStatus;
+ PCI_EXPRESS_REG_LANE_EQUALIZATION_CONTROL EqualizationControl[2];
+} PCI_EXPRESS_EXTENDED_CAPABILITIES_SECONDARY_PCIE;
+
+#pragma pack()
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/PciExpress31.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/PciExpress31.h
new file mode 100644
index 0000000000..2bc468dc07
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/PciExpress31.h
@@ -0,0 +1,72 @@
+/** @file
+Support for the PCI Express 3.1 standard.
+
+This header file may not define all structures. Please extend as required.
+
+Copyright (c) 2016, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _PCIEXPRESS31_H_
+#define _PCIEXPRESS31_H_
+
+#include
+
+#pragma pack(1)
+
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_L1_PM_SUBSTATES_ID 0x001E
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_L1_PM_SUBSTATES_VER1 0x1
+
+typedef union {
+ struct {
+ UINT32 PciPmL12 : 1;
+ UINT32 PciPmL11 : 1;
+ UINT32 AspmL12 : 1;
+ UINT32 AspmL11 : 1;
+ UINT32 L1PmSubstates : 1;
+ UINT32 Reserved : 3;
+ UINT32 CommonModeRestoreTime : 8;
+ UINT32 TPowerOnScale : 2;
+ UINT32 Reserved2 : 1;
+ UINT32 TPowerOnValue : 5;
+ UINT32 Reserved3 : 8;
+ } Bits;
+ UINT32 Uint32;
+} PCI_EXPRESS_REG_L1_PM_SUBSTATES_CAPABILITY;
+
+typedef union {
+ struct {
+ UINT32 PciPmL12 : 1;
+ UINT32 PciPmL11 : 1;
+ UINT32 AspmL12 : 1;
+ UINT32 AspmL11 : 1;
+ UINT32 Reserved : 4;
+ UINT32 CommonModeRestoreTime : 8;
+ UINT32 LtrL12ThresholdValue : 10;
+ UINT32 Reserved2 : 3;
+ UINT32 LtrL12ThresholdScale : 3;
+ } Bits;
+ UINT32 Uint32;
+} PCI_EXPRESS_REG_L1_PM_SUBSTATES_CONTROL1;
+
+typedef union {
+ struct {
+ UINT32 TPowerOnScale : 2;
+ UINT32 Reserved : 1;
+ UINT32 TPowerOnValue : 5;
+ UINT32 Reserved2 : 24;
+ } Bits;
+ UINT32 Uint32;
+} PCI_EXPRESS_REG_L1_PM_SUBSTATES_CONTROL2;
+
+typedef struct {
+ PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;
+ PCI_EXPRESS_REG_L1_PM_SUBSTATES_CAPABILITY Capability;
+ PCI_EXPRESS_REG_L1_PM_SUBSTATES_CONTROL1 Control1;
+ PCI_EXPRESS_REG_L1_PM_SUBSTATES_CONTROL2 Control2;
+} PCI_EXPRESS_EXTENDED_CAPABILITIES_L1_PM_SUBSTATES;
+
+#pragma pack()
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/PciExpress40.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/PciExpress40.h
new file mode 100644
index 0000000000..70ee5503b4
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/PciExpress40.h
@@ -0,0 +1,111 @@
+/** @file
+Support for the PCI Express 4.0 standard.
+
+This header file may not define all structures. Please extend as required.
+
+Copyright (c) 2018, American Megatrends, Inc. All rights reserved.
+Copyright (c) 2020, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _PCIEXPRESS40_H_
+#define _PCIEXPRESS40_H_
+
+#include
+
+#pragma pack(1)
+
+/// The Physical Layer PCI Express Extended Capability definitions.
+///
+/// Based on section 7.7.5 of PCI Express Base Specification 4.0.
+///@{
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_PHYSICAL_LAYER_16_0_ID 0x0026
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_PHYSICAL_LAYER_16_0_VER1 0x1
+
+// Register offsets from Physical Layer PCI-E Ext Cap Header
+#define PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_CAPABILITIES_OFFSET 0x04
+#define PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_CONTROL_OFFSET 0x08
+#define PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_STATUS_OFFSET 0x0C
+#define PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_LOCAL_DATA_PARITY_STATUS_OFFSET 0x10
+#define PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_FIRST_RETIMER_DATA_PARITY_STATUS_OFFSET 0x14
+#define PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_SECOND_RETIMER_DATA_PARITY_STATUS_OFFSET 0x18
+#define PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_LANE_EQUALIZATION_CONTROL_OFFSET 0x20
+
+typedef union {
+ struct {
+ UINT32 Reserved : 32; // Reserved bit 0:31
+ } Bits;
+ UINT32 Uint32;
+} PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_CAPABILITIES;
+
+typedef union {
+ struct {
+ UINT32 Reserved : 32; // Reserved bit 0:31
+ } Bits;
+ UINT32 Uint32;
+} PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_CONTROL;
+
+typedef union {
+ struct {
+ UINT32 EqualizationComplete : 1; // bit 0
+ UINT32 EqualizationPhase1Success : 1; // bit 1
+ UINT32 EqualizationPhase2Success : 1; // bit 2
+ UINT32 EqualizationPhase3Success : 1; // bit 3
+ UINT32 LinkEqualizationRequest : 1; // bit 4
+ UINT32 Reserved : 27; // Reserved bit 5:31
+ } Bits;
+ UINT32 Uint32;
+} PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_STATUS;
+
+typedef union {
+ struct {
+ UINT8 DownstreamPortTransmitterPreset : 4; // bit 0..3
+ UINT8 UpstreamPortTransmitterPreset : 4; // bit 4..7
+ } Bits;
+ UINT8 Uint8;
+} PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_LANE_EQUALIZATION_CONTROL;
+
+typedef struct {
+ PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;
+ PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_CAPABILITIES Capablities;
+ PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_CONTROL Control;
+ PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_STATUS Status;
+ UINT32 LocalDataParityMismatchStatus;
+ UINT32 FirstRetimerDataParityMismatchStatus;
+ UINT32 SecondRetimerDataParityMismatchStatus;
+ UINT32 Reserved;
+ PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_LANE_EQUALIZATION_CONTROL LaneEqualizationControl[1];
+} PCI_EXPRESS_EXTENDED_CAPABILITIES_PHYSICAL_LAYER_16_0;
+///@}
+
+/// The Designated Vendor Specific Capability definitions
+/// Based on section 7.9.6 of PCI Express Base Specification 4.0.
+///@{
+typedef union {
+ struct {
+ UINT32 DvsecVendorId : 16; // bit 0..15
+ UINT32 DvsecRevision : 4; // bit 16..19
+ UINT32 DvsecLength : 12; // bit 20..31
+ } Bits;
+ UINT32 Uint32;
+} PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_1;
+
+typedef union {
+ struct {
+ UINT16 DvsecId : 16; // bit 0..15
+ } Bits;
+ UINT16 Uint16;
+} PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_2;
+
+typedef struct {
+ PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;
+ PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_1 DesignatedVendorSpecificHeader1;
+ PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_2 DesignatedVendorSpecificHeader2;
+ UINT8 DesignatedVendorSpecific[1];
+} PCI_EXPRESS_EXTENDED_CAPABILITIES_DESIGNATED_VENDOR_SPECIFIC;
+///@}
+
+#pragma pack()
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/PciExpress50.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/PciExpress50.h
new file mode 100644
index 0000000000..fcfa564c4c
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/PciExpress50.h
@@ -0,0 +1,136 @@
+/** @file
+Support for the PCI Express 5.0 standard.
+
+This header file may not define all structures. Please extend as required.
+
+Copyright (c) 2020, American Megatrends International LLC. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _PCIEXPRESS50_H_
+#define _PCIEXPRESS50_H_
+
+#include
+
+#pragma pack(1)
+
+/// The Physical Layer PCI Express Extended Capability definitions.
+///
+/// Based on section 7.7.6 of PCI Express Base Specification 5.0.
+///@{
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_PHYSICAL_LAYER_32_0_ID 0x002A
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_PHYSICAL_LAYER_32_0_VER1 0x1
+
+// Register offsets from Physical Layer PCI-E Ext Cap Header
+#define PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_CAPABILITIES_OFFSET 0x04
+#define PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_CONTROL_OFFSET 0x08
+#define PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_STATUS_OFFSET 0x0C
+#define PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_RCVD_MODIFIED_TS_DATA1_OFFSET 0x10
+#define PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_RCVD_MODIFIED_TS_DATA2_OFFSET 0x14
+#define PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_TRANS_MODIFIED_TS_DATA1_OFFSET 0x18
+#define PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_TRANS_MODIFIED_TS_DATA2_OFFSET 0x1C
+#define PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_LANE_EQUALIZATION_CONTROL_OFFSET 0x20
+
+typedef union {
+ struct {
+ UINT32 EqualizationByPassToHighestRateSupport : 1; // bit 0
+ UINT32 NoEqualizationNeededSupport : 1; // bit 1
+ UINT32 Reserved1 : 6; // Reserved bit 2:7
+ UINT32 ModifiedTSUsageMode0Support : 1; // bit 8
+ UINT32 ModifiedTSUsageMode1Support : 1; // bit 9
+ UINT32 ModifiedTSUsageMode2Support : 1; // bit 10
+ UINT32 ModifiedTSReservedUsageModes : 5; // bit 11:15
+ UINT32 Reserved2 : 16; // Reserved bit 16:31
+ } Bits;
+ UINT32 Uint32;
+} PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_CAPABILITIES;
+
+typedef union {
+ struct {
+ UINT32 EqualizationByPassToHighestRateDisable : 1; // bit 0
+ UINT32 NoEqualizationNeededDisable : 1; // bit 1
+ UINT32 Reserved1 : 6; // Reserved bit 2:7
+ UINT32 ModifiedTSUsageModeSelected : 3; // bit 8:10
+ UINT32 Reserved2 : 21; // Reserved bit 11:31
+ } Bits;
+ UINT32 Uint32;
+} PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_CONTROL;
+
+typedef union {
+ struct {
+ UINT32 EqualizationComplete : 1; // bit 0
+ UINT32 EqualizationPhase1Success : 1; // bit 1
+ UINT32 EqualizationPhase2Success : 1; // bit 2
+ UINT32 EqualizationPhase3Success : 1; // bit 3
+ UINT32 LinkEqualizationRequest : 1; // bit 4
+ UINT32 ModifiedTSRcvd : 1; // bit 5
+ UINT32 RcvdEnhancedLinkControl : 2; // bit 6:7
+ UINT32 TransmitterPrecodingOn : 1; // bit 8
+ UINT32 TransmitterPrecodeRequest : 1; // bit 9
+ UINT32 NoEqualizationNeededRcvd : 1; // bit 10
+ UINT32 Reserved : 21; // Reserved bit 11:31
+ } Bits;
+ UINT32 Uint32;
+} PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_STATUS;
+
+typedef union {
+ struct {
+ UINT32 RcvdModifiedTSUsageMode : 3; // bit 0:2
+ UINT32 RcvdModifiedTSUsageInfo1 : 13; // bit 3:15
+ UINT32 RcvdModifiedTSVendorId : 16; // bit 16:31
+ } Bits;
+ UINT32 Uint32;
+} PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_RCVD_MODIFIED_TS_DATA1;
+
+typedef union {
+ struct {
+ UINT32 RcvdModifiedTSUsageInfo2 : 24; // bit 0:23
+ UINT32 AltProtocolNegotiationStatus : 2; // bit 24:25
+ UINT32 Reserved : 6; // Reserved bit 26:31
+ } Bits;
+ UINT32 Uint32;
+} PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_RCVD_MODIFIED_TS_DATA2;
+
+typedef union {
+ struct {
+ UINT32 TransModifiedTSUsageMode : 3; // bit 0:2
+ UINT32 TransModifiedTSUsageInfo1 : 13; // bit 3:15
+ UINT32 TransModifiedTSVendorId : 16; // bit 16:31
+ } Bits;
+ UINT32 Uint32;
+} PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_TRANS_MODIFIED_TS_DATA1;
+
+typedef union {
+ struct {
+ UINT32 TransModifiedTSUsageInfo2 : 24; // bit 0:23
+ UINT32 AltProtocolNegotiationStatus : 2; // bit 24:25
+ UINT32 Reserved : 6; // Reserved bit 26:31
+ } Bits;
+ UINT32 Uint32;
+} PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_TRANS_MODIFIED_TS_DATA2;
+
+typedef union {
+ struct {
+ UINT8 DownstreamPortTransmitterPreset : 4; // bit 0..3
+ UINT8 UpstreamPortTransmitterPreset : 4; // bit 4..7
+ } Bits;
+ UINT8 Uint8;
+} PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_LANE_EQUALIZATION_CONTROL;
+
+typedef struct {
+ PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;
+ PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_CAPABILITIES Capablities;
+ PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_CONTROL Control;
+ PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_STATUS Status;
+ PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_RCVD_MODIFIED_TS_DATA1 RcvdModifiedTs1Data;
+ PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_RCVD_MODIFIED_TS_DATA2 RcvdModifiedTs2Data;
+ PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_TRANS_MODIFIED_TS_DATA1 TransModifiedTs1Data;
+ PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_TRANS_MODIFIED_TS_DATA2 TransModifiedTs2Data;
+ PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_LANE_EQUALIZATION_CONTROL LaneEqualizationControl[1];
+} PCI_EXPRESS_EXTENDED_CAPABILITIES_PHYSICAL_LAYER_32_0;
+///@}
+
+#pragma pack()
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/PeImage.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/PeImage.h
new file mode 100644
index 0000000000..749a28ed70
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/PeImage.h
@@ -0,0 +1,764 @@
+/** @file
+ EFI image format for PE32, PE32+ and TE. Please note some data structures are
+ different for PE32 and PE32+. EFI_IMAGE_NT_HEADERS32 is for PE32 and
+ EFI_IMAGE_NT_HEADERS64 is for PE32+.
+
+ This file is coded to the Visual Studio, Microsoft Portable Executable and
+ Common Object File Format Specification, Revision 8.3 - February 6, 2013.
+ This file also includes some definitions in PI Specification, Revision 1.0.
+
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
+Portions Copyright (c) 2016 - 2020, Hewlett Packard Enterprise Development LP. All rights reserved.
+Portions Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved.
+
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __PE_IMAGE_H__
+#define __PE_IMAGE_H__
+
+//
+// PE32+ Subsystem type for EFI images
+//
+#define EFI_IMAGE_SUBSYSTEM_EFI_APPLICATION 10
+#define EFI_IMAGE_SUBSYSTEM_EFI_BOOT_SERVICE_DRIVER 11
+#define EFI_IMAGE_SUBSYSTEM_EFI_RUNTIME_DRIVER 12
+#define EFI_IMAGE_SUBSYSTEM_SAL_RUNTIME_DRIVER 13///< defined PI Specification, 1.0
+
+//
+// PE32+ Machine type for EFI images
+//
+#define IMAGE_FILE_MACHINE_I386 0x014c
+#define IMAGE_FILE_MACHINE_IA64 0x0200
+#define IMAGE_FILE_MACHINE_EBC 0x0EBC
+#define IMAGE_FILE_MACHINE_X64 0x8664
+#define IMAGE_FILE_MACHINE_ARMTHUMB_MIXED 0x01c2
+#define IMAGE_FILE_MACHINE_ARM64 0xAA64
+#define IMAGE_FILE_MACHINE_RISCV32 0x5032
+#define IMAGE_FILE_MACHINE_RISCV64 0x5064
+#define IMAGE_FILE_MACHINE_RISCV128 0x5128
+#define IMAGE_FILE_MACHINE_LOONGARCH32 0x6232
+#define IMAGE_FILE_MACHINE_LOONGARCH64 0x6264
+
+//
+// EXE file formats
+//
+#define EFI_IMAGE_DOS_SIGNATURE SIGNATURE_16('M', 'Z')
+#define EFI_IMAGE_OS2_SIGNATURE SIGNATURE_16('N', 'E')
+#define EFI_IMAGE_OS2_SIGNATURE_LE SIGNATURE_16('L', 'E')
+#define EFI_IMAGE_NT_SIGNATURE SIGNATURE_32('P', 'E', '\0', '\0')
+
+///
+/// PE images can start with an optional DOS header, so if an image is run
+/// under DOS it can print an error message.
+///
+typedef struct {
+ UINT16 e_magic; ///< Magic number.
+ UINT16 e_cblp; ///< Bytes on last page of file.
+ UINT16 e_cp; ///< Pages in file.
+ UINT16 e_crlc; ///< Relocations.
+ UINT16 e_cparhdr; ///< Size of header in paragraphs.
+ UINT16 e_minalloc; ///< Minimum extra paragraphs needed.
+ UINT16 e_maxalloc; ///< Maximum extra paragraphs needed.
+ UINT16 e_ss; ///< Initial (relative) SS value.
+ UINT16 e_sp; ///< Initial SP value.
+ UINT16 e_csum; ///< Checksum.
+ UINT16 e_ip; ///< Initial IP value.
+ UINT16 e_cs; ///< Initial (relative) CS value.
+ UINT16 e_lfarlc; ///< File address of relocation table.
+ UINT16 e_ovno; ///< Overlay number.
+ UINT16 e_res[4]; ///< Reserved words.
+ UINT16 e_oemid; ///< OEM identifier (for e_oeminfo).
+ UINT16 e_oeminfo; ///< OEM information; e_oemid specific.
+ UINT16 e_res2[10]; ///< Reserved words.
+ UINT32 e_lfanew; ///< File address of new exe header.
+} EFI_IMAGE_DOS_HEADER;
+
+///
+/// COFF File Header (Object and Image).
+///
+typedef struct {
+ UINT16 Machine;
+ UINT16 NumberOfSections;
+ UINT32 TimeDateStamp;
+ UINT32 PointerToSymbolTable;
+ UINT32 NumberOfSymbols;
+ UINT16 SizeOfOptionalHeader;
+ UINT16 Characteristics;
+} EFI_IMAGE_FILE_HEADER;
+
+///
+/// Size of EFI_IMAGE_FILE_HEADER.
+///
+#define EFI_IMAGE_SIZEOF_FILE_HEADER 20
+
+//
+// Characteristics
+//
+#define EFI_IMAGE_FILE_RELOCS_STRIPPED BIT0 ///< 0x0001 Relocation info stripped from file.
+#define EFI_IMAGE_FILE_EXECUTABLE_IMAGE BIT1 ///< 0x0002 File is executable (i.e. no unresolved externel references).
+#define EFI_IMAGE_FILE_LINE_NUMS_STRIPPED BIT2 ///< 0x0004 Line numbers stripped from file.
+#define EFI_IMAGE_FILE_LOCAL_SYMS_STRIPPED BIT3 ///< 0x0008 Local symbols stripped from file.
+#define EFI_IMAGE_FILE_BYTES_REVERSED_LO BIT7 ///< 0x0080 Bytes of machine word are reversed.
+#define EFI_IMAGE_FILE_32BIT_MACHINE BIT8 ///< 0x0100 32 bit word machine.
+#define EFI_IMAGE_FILE_DEBUG_STRIPPED BIT9 ///< 0x0200 Debugging info stripped from file in .DBG file.
+#define EFI_IMAGE_FILE_SYSTEM BIT12 ///< 0x1000 System File.
+#define EFI_IMAGE_FILE_DLL BIT13 ///< 0x2000 File is a DLL.
+#define EFI_IMAGE_FILE_BYTES_REVERSED_HI BIT15 ///< 0x8000 Bytes of machine word are reversed.
+
+///
+/// Header Data Directories.
+///
+typedef struct {
+ UINT32 VirtualAddress;
+ UINT32 Size;
+} EFI_IMAGE_DATA_DIRECTORY;
+
+//
+// Directory Entries
+//
+#define EFI_IMAGE_DIRECTORY_ENTRY_EXPORT 0
+#define EFI_IMAGE_DIRECTORY_ENTRY_IMPORT 1
+#define EFI_IMAGE_DIRECTORY_ENTRY_RESOURCE 2
+#define EFI_IMAGE_DIRECTORY_ENTRY_EXCEPTION 3
+#define EFI_IMAGE_DIRECTORY_ENTRY_SECURITY 4
+#define EFI_IMAGE_DIRECTORY_ENTRY_BASERELOC 5
+#define EFI_IMAGE_DIRECTORY_ENTRY_DEBUG 6
+#define EFI_IMAGE_DIRECTORY_ENTRY_COPYRIGHT 7
+#define EFI_IMAGE_DIRECTORY_ENTRY_GLOBALPTR 8
+#define EFI_IMAGE_DIRECTORY_ENTRY_TLS 9
+#define EFI_IMAGE_DIRECTORY_ENTRY_LOAD_CONFIG 10
+
+#define EFI_IMAGE_NUMBER_OF_DIRECTORY_ENTRIES 16
+
+///
+/// @attention
+/// EFI_IMAGE_NT_OPTIONAL_HDR32_MAGIC means PE32 and
+/// EFI_IMAGE_OPTIONAL_HEADER32 must be used. The data structures only vary
+/// after NT additional fields.
+///
+#define EFI_IMAGE_NT_OPTIONAL_HDR32_MAGIC 0x10b
+
+///
+/// Optional Header Standard Fields for PE32.
+///
+typedef struct {
+ ///
+ /// Standard fields.
+ ///
+ UINT16 Magic;
+ UINT8 MajorLinkerVersion;
+ UINT8 MinorLinkerVersion;
+ UINT32 SizeOfCode;
+ UINT32 SizeOfInitializedData;
+ UINT32 SizeOfUninitializedData;
+ UINT32 AddressOfEntryPoint;
+ UINT32 BaseOfCode;
+ UINT32 BaseOfData; ///< PE32 contains this additional field, which is absent in PE32+.
+ ///
+ /// Optional Header Windows-Specific Fields.
+ ///
+ UINT32 ImageBase;
+ UINT32 SectionAlignment;
+ UINT32 FileAlignment;
+ UINT16 MajorOperatingSystemVersion;
+ UINT16 MinorOperatingSystemVersion;
+ UINT16 MajorImageVersion;
+ UINT16 MinorImageVersion;
+ UINT16 MajorSubsystemVersion;
+ UINT16 MinorSubsystemVersion;
+ UINT32 Win32VersionValue;
+ UINT32 SizeOfImage;
+ UINT32 SizeOfHeaders;
+ UINT32 CheckSum;
+ UINT16 Subsystem;
+ UINT16 DllCharacteristics;
+ UINT32 SizeOfStackReserve;
+ UINT32 SizeOfStackCommit;
+ UINT32 SizeOfHeapReserve;
+ UINT32 SizeOfHeapCommit;
+ UINT32 LoaderFlags;
+ UINT32 NumberOfRvaAndSizes;
+ EFI_IMAGE_DATA_DIRECTORY DataDirectory[EFI_IMAGE_NUMBER_OF_DIRECTORY_ENTRIES];
+} EFI_IMAGE_OPTIONAL_HEADER32;
+
+///
+/// @attention
+/// EFI_IMAGE_NT_OPTIONAL_HDR64_MAGIC means PE32+ and
+/// EFI_IMAGE_OPTIONAL_HEADER64 must be used. The data structures only vary
+/// after NT additional fields.
+///
+#define EFI_IMAGE_NT_OPTIONAL_HDR64_MAGIC 0x20b
+
+///
+/// Optional Header Standard Fields for PE32+.
+///
+typedef struct {
+ ///
+ /// Standard fields.
+ ///
+ UINT16 Magic;
+ UINT8 MajorLinkerVersion;
+ UINT8 MinorLinkerVersion;
+ UINT32 SizeOfCode;
+ UINT32 SizeOfInitializedData;
+ UINT32 SizeOfUninitializedData;
+ UINT32 AddressOfEntryPoint;
+ UINT32 BaseOfCode;
+ ///
+ /// Optional Header Windows-Specific Fields.
+ ///
+ UINT64 ImageBase;
+ UINT32 SectionAlignment;
+ UINT32 FileAlignment;
+ UINT16 MajorOperatingSystemVersion;
+ UINT16 MinorOperatingSystemVersion;
+ UINT16 MajorImageVersion;
+ UINT16 MinorImageVersion;
+ UINT16 MajorSubsystemVersion;
+ UINT16 MinorSubsystemVersion;
+ UINT32 Win32VersionValue;
+ UINT32 SizeOfImage;
+ UINT32 SizeOfHeaders;
+ UINT32 CheckSum;
+ UINT16 Subsystem;
+ UINT16 DllCharacteristics;
+ UINT64 SizeOfStackReserve;
+ UINT64 SizeOfStackCommit;
+ UINT64 SizeOfHeapReserve;
+ UINT64 SizeOfHeapCommit;
+ UINT32 LoaderFlags;
+ UINT32 NumberOfRvaAndSizes;
+ EFI_IMAGE_DATA_DIRECTORY DataDirectory[EFI_IMAGE_NUMBER_OF_DIRECTORY_ENTRIES];
+} EFI_IMAGE_OPTIONAL_HEADER64;
+
+///
+/// @attention
+/// EFI_IMAGE_NT_HEADERS32 is for use ONLY by tools.
+///
+typedef struct {
+ UINT32 Signature;
+ EFI_IMAGE_FILE_HEADER FileHeader;
+ EFI_IMAGE_OPTIONAL_HEADER32 OptionalHeader;
+} EFI_IMAGE_NT_HEADERS32;
+
+#define EFI_IMAGE_SIZEOF_NT_OPTIONAL32_HEADER sizeof (EFI_IMAGE_NT_HEADERS32)
+
+///
+/// @attention
+/// EFI_IMAGE_HEADERS64 is for use ONLY by tools.
+///
+typedef struct {
+ UINT32 Signature;
+ EFI_IMAGE_FILE_HEADER FileHeader;
+ EFI_IMAGE_OPTIONAL_HEADER64 OptionalHeader;
+} EFI_IMAGE_NT_HEADERS64;
+
+#define EFI_IMAGE_SIZEOF_NT_OPTIONAL64_HEADER sizeof (EFI_IMAGE_NT_HEADERS64)
+
+//
+// Other Windows Subsystem Values
+//
+#define EFI_IMAGE_SUBSYSTEM_UNKNOWN 0
+#define EFI_IMAGE_SUBSYSTEM_NATIVE 1
+#define EFI_IMAGE_SUBSYSTEM_WINDOWS_GUI 2
+#define EFI_IMAGE_SUBSYSTEM_WINDOWS_CUI 3
+#define EFI_IMAGE_SUBSYSTEM_OS2_CUI 5
+#define EFI_IMAGE_SUBSYSTEM_POSIX_CUI 7
+
+///
+/// Length of ShortName.
+///
+#define EFI_IMAGE_SIZEOF_SHORT_NAME 8
+
+///
+/// Section Table. This table immediately follows the optional header.
+///
+typedef struct {
+ UINT8 Name[EFI_IMAGE_SIZEOF_SHORT_NAME];
+ union {
+ UINT32 PhysicalAddress;
+ UINT32 VirtualSize;
+ } Misc;
+ UINT32 VirtualAddress;
+ UINT32 SizeOfRawData;
+ UINT32 PointerToRawData;
+ UINT32 PointerToRelocations;
+ UINT32 PointerToLinenumbers;
+ UINT16 NumberOfRelocations;
+ UINT16 NumberOfLinenumbers;
+ UINT32 Characteristics;
+} EFI_IMAGE_SECTION_HEADER;
+
+///
+/// Size of EFI_IMAGE_SECTION_HEADER.
+///
+#define EFI_IMAGE_SIZEOF_SECTION_HEADER 40
+
+//
+// Section Flags Values
+//
+#define EFI_IMAGE_SCN_TYPE_NO_PAD BIT3 ///< 0x00000008 ///< Reserved.
+#define EFI_IMAGE_SCN_CNT_CODE BIT5 ///< 0x00000020
+#define EFI_IMAGE_SCN_CNT_INITIALIZED_DATA BIT6 ///< 0x00000040
+#define EFI_IMAGE_SCN_CNT_UNINITIALIZED_DATA BIT7 ///< 0x00000080
+
+#define EFI_IMAGE_SCN_LNK_OTHER BIT8 ///< 0x00000100 ///< Reserved.
+#define EFI_IMAGE_SCN_LNK_INFO BIT9 ///< 0x00000200 ///< Section contains comments or some other type of information.
+#define EFI_IMAGE_SCN_LNK_REMOVE BIT11 ///< 0x00000800 ///< Section contents will not become part of image.
+#define EFI_IMAGE_SCN_LNK_COMDAT BIT12 ///< 0x00001000
+
+#define EFI_IMAGE_SCN_ALIGN_1BYTES BIT20 ///< 0x00100000
+#define EFI_IMAGE_SCN_ALIGN_2BYTES BIT21 ///< 0x00200000
+#define EFI_IMAGE_SCN_ALIGN_4BYTES (BIT20|BIT21) ///< 0x00300000
+#define EFI_IMAGE_SCN_ALIGN_8BYTES BIT22 ///< 0x00400000
+#define EFI_IMAGE_SCN_ALIGN_16BYTES (BIT20|BIT22) ///< 0x00500000
+#define EFI_IMAGE_SCN_ALIGN_32BYTES (BIT21|BIT22) ///< 0x00600000
+#define EFI_IMAGE_SCN_ALIGN_64BYTES (BIT20|BIT21|BIT22) ///< 0x00700000
+
+#define EFI_IMAGE_SCN_MEM_DISCARDABLE BIT25 ///< 0x02000000
+#define EFI_IMAGE_SCN_MEM_NOT_CACHED BIT26 ///< 0x04000000
+#define EFI_IMAGE_SCN_MEM_NOT_PAGED BIT27 ///< 0x08000000
+#define EFI_IMAGE_SCN_MEM_SHARED BIT28 ///< 0x10000000
+#define EFI_IMAGE_SCN_MEM_EXECUTE BIT29 ///< 0x20000000
+#define EFI_IMAGE_SCN_MEM_READ BIT30 ///< 0x40000000
+#define EFI_IMAGE_SCN_MEM_WRITE BIT31 ///< 0x80000000
+
+///
+/// Size of a Symbol Table Record.
+///
+#define EFI_IMAGE_SIZEOF_SYMBOL 18
+
+//
+// Symbols have a section number of the section in which they are
+// defined. Otherwise, section numbers have the following meanings:
+//
+#define EFI_IMAGE_SYM_UNDEFINED (UINT16) 0 ///< Symbol is undefined or is common.
+#define EFI_IMAGE_SYM_ABSOLUTE (UINT16) -1 ///< Symbol is an absolute value.
+#define EFI_IMAGE_SYM_DEBUG (UINT16) -2 ///< Symbol is a special debug item.
+
+//
+// Symbol Type (fundamental) values.
+//
+#define EFI_IMAGE_SYM_TYPE_NULL 0 ///< no type.
+#define EFI_IMAGE_SYM_TYPE_VOID 1 ///< no valid type.
+#define EFI_IMAGE_SYM_TYPE_CHAR 2 ///< type character.
+#define EFI_IMAGE_SYM_TYPE_SHORT 3 ///< type short integer.
+#define EFI_IMAGE_SYM_TYPE_INT 4
+#define EFI_IMAGE_SYM_TYPE_LONG 5
+#define EFI_IMAGE_SYM_TYPE_FLOAT 6
+#define EFI_IMAGE_SYM_TYPE_DOUBLE 7
+#define EFI_IMAGE_SYM_TYPE_STRUCT 8
+#define EFI_IMAGE_SYM_TYPE_UNION 9
+#define EFI_IMAGE_SYM_TYPE_ENUM 10 ///< enumeration.
+#define EFI_IMAGE_SYM_TYPE_MOE 11 ///< member of enumeration.
+#define EFI_IMAGE_SYM_TYPE_BYTE 12
+#define EFI_IMAGE_SYM_TYPE_WORD 13
+#define EFI_IMAGE_SYM_TYPE_UINT 14
+#define EFI_IMAGE_SYM_TYPE_DWORD 15
+
+//
+// Symbol Type (derived) values.
+//
+#define EFI_IMAGE_SYM_DTYPE_NULL 0 ///< no derived type.
+#define EFI_IMAGE_SYM_DTYPE_POINTER 1
+#define EFI_IMAGE_SYM_DTYPE_FUNCTION 2
+#define EFI_IMAGE_SYM_DTYPE_ARRAY 3
+
+//
+// Storage classes.
+//
+#define EFI_IMAGE_SYM_CLASS_END_OF_FUNCTION ((UINT8) -1)
+#define EFI_IMAGE_SYM_CLASS_NULL 0
+#define EFI_IMAGE_SYM_CLASS_AUTOMATIC 1
+#define EFI_IMAGE_SYM_CLASS_EXTERNAL 2
+#define EFI_IMAGE_SYM_CLASS_STATIC 3
+#define EFI_IMAGE_SYM_CLASS_REGISTER 4
+#define EFI_IMAGE_SYM_CLASS_EXTERNAL_DEF 5
+#define EFI_IMAGE_SYM_CLASS_LABEL 6
+#define EFI_IMAGE_SYM_CLASS_UNDEFINED_LABEL 7
+#define EFI_IMAGE_SYM_CLASS_MEMBER_OF_STRUCT 8
+#define EFI_IMAGE_SYM_CLASS_ARGUMENT 9
+#define EFI_IMAGE_SYM_CLASS_STRUCT_TAG 10
+#define EFI_IMAGE_SYM_CLASS_MEMBER_OF_UNION 11
+#define EFI_IMAGE_SYM_CLASS_UNION_TAG 12
+#define EFI_IMAGE_SYM_CLASS_TYPE_DEFINITION 13
+#define EFI_IMAGE_SYM_CLASS_UNDEFINED_STATIC 14
+#define EFI_IMAGE_SYM_CLASS_ENUM_TAG 15
+#define EFI_IMAGE_SYM_CLASS_MEMBER_OF_ENUM 16
+#define EFI_IMAGE_SYM_CLASS_REGISTER_PARAM 17
+#define EFI_IMAGE_SYM_CLASS_BIT_FIELD 18
+#define EFI_IMAGE_SYM_CLASS_BLOCK 100
+#define EFI_IMAGE_SYM_CLASS_FUNCTION 101
+#define EFI_IMAGE_SYM_CLASS_END_OF_STRUCT 102
+#define EFI_IMAGE_SYM_CLASS_FILE 103
+#define EFI_IMAGE_SYM_CLASS_SECTION 104
+#define EFI_IMAGE_SYM_CLASS_WEAK_EXTERNAL 105
+
+//
+// type packing constants
+//
+#define EFI_IMAGE_N_BTMASK 017
+#define EFI_IMAGE_N_TMASK 060
+#define EFI_IMAGE_N_TMASK1 0300
+#define EFI_IMAGE_N_TMASK2 0360
+#define EFI_IMAGE_N_BTSHFT 4
+#define EFI_IMAGE_N_TSHIFT 2
+
+//
+// Communal selection types.
+//
+#define EFI_IMAGE_COMDAT_SELECT_NODUPLICATES 1
+#define EFI_IMAGE_COMDAT_SELECT_ANY 2
+#define EFI_IMAGE_COMDAT_SELECT_SAME_SIZE 3
+#define EFI_IMAGE_COMDAT_SELECT_EXACT_MATCH 4
+#define EFI_IMAGE_COMDAT_SELECT_ASSOCIATIVE 5
+
+//
+// the following values only be referred in PeCoff, not defined in PECOFF.
+//
+#define EFI_IMAGE_WEAK_EXTERN_SEARCH_NOLIBRARY 1
+#define EFI_IMAGE_WEAK_EXTERN_SEARCH_LIBRARY 2
+#define EFI_IMAGE_WEAK_EXTERN_SEARCH_ALIAS 3
+
+///
+/// Relocation format.
+///
+typedef struct {
+ UINT32 VirtualAddress;
+ UINT32 SymbolTableIndex;
+ UINT16 Type;
+} EFI_IMAGE_RELOCATION;
+
+///
+/// Size of EFI_IMAGE_RELOCATION
+///
+#define EFI_IMAGE_SIZEOF_RELOCATION 10
+
+//
+// I386 relocation types.
+//
+#define EFI_IMAGE_REL_I386_ABSOLUTE 0x0000 ///< Reference is absolute, no relocation is necessary.
+#define EFI_IMAGE_REL_I386_DIR16 0x0001 ///< Direct 16-bit reference to the symbols virtual address.
+#define EFI_IMAGE_REL_I386_REL16 0x0002 ///< PC-relative 16-bit reference to the symbols virtual address.
+#define EFI_IMAGE_REL_I386_DIR32 0x0006 ///< Direct 32-bit reference to the symbols virtual address.
+#define EFI_IMAGE_REL_I386_DIR32NB 0x0007 ///< Direct 32-bit reference to the symbols virtual address, base not included.
+#define EFI_IMAGE_REL_I386_SEG12 0x0009 ///< Direct 16-bit reference to the segment-selector bits of a 32-bit virtual address.
+#define EFI_IMAGE_REL_I386_SECTION 0x000A
+#define EFI_IMAGE_REL_I386_SECREL 0x000B
+#define EFI_IMAGE_REL_I386_REL32 0x0014 ///< PC-relative 32-bit reference to the symbols virtual address.
+
+//
+// x64 processor relocation types.
+//
+#define IMAGE_REL_AMD64_ABSOLUTE 0x0000
+#define IMAGE_REL_AMD64_ADDR64 0x0001
+#define IMAGE_REL_AMD64_ADDR32 0x0002
+#define IMAGE_REL_AMD64_ADDR32NB 0x0003
+#define IMAGE_REL_AMD64_REL32 0x0004
+#define IMAGE_REL_AMD64_REL32_1 0x0005
+#define IMAGE_REL_AMD64_REL32_2 0x0006
+#define IMAGE_REL_AMD64_REL32_3 0x0007
+#define IMAGE_REL_AMD64_REL32_4 0x0008
+#define IMAGE_REL_AMD64_REL32_5 0x0009
+#define IMAGE_REL_AMD64_SECTION 0x000A
+#define IMAGE_REL_AMD64_SECREL 0x000B
+#define IMAGE_REL_AMD64_SECREL7 0x000C
+#define IMAGE_REL_AMD64_TOKEN 0x000D
+#define IMAGE_REL_AMD64_SREL32 0x000E
+#define IMAGE_REL_AMD64_PAIR 0x000F
+#define IMAGE_REL_AMD64_SSPAN32 0x0010
+
+///
+/// Based relocation format.
+///
+typedef struct {
+ UINT32 VirtualAddress;
+ UINT32 SizeOfBlock;
+} EFI_IMAGE_BASE_RELOCATION;
+
+///
+/// Size of EFI_IMAGE_BASE_RELOCATION.
+///
+#define EFI_IMAGE_SIZEOF_BASE_RELOCATION 8
+
+//
+// Based relocation types.
+//
+#define EFI_IMAGE_REL_BASED_ABSOLUTE 0
+#define EFI_IMAGE_REL_BASED_HIGH 1
+#define EFI_IMAGE_REL_BASED_LOW 2
+#define EFI_IMAGE_REL_BASED_HIGHLOW 3
+#define EFI_IMAGE_REL_BASED_HIGHADJ 4
+#define EFI_IMAGE_REL_BASED_MIPS_JMPADDR 5
+#define EFI_IMAGE_REL_BASED_ARM_MOV32A 5
+#define EFI_IMAGE_REL_BASED_ARM_MOV32T 7
+#define EFI_IMAGE_REL_BASED_IA64_IMM64 9
+#define EFI_IMAGE_REL_BASED_MIPS_JMPADDR16 9
+#define EFI_IMAGE_REL_BASED_DIR64 10
+
+///
+/// Relocation types of RISC-V processor.
+///
+#define EFI_IMAGE_REL_BASED_RISCV_HI20 5
+#define EFI_IMAGE_REL_BASED_RISCV_LOW12I 7
+#define EFI_IMAGE_REL_BASED_RISCV_LOW12S 8
+
+//
+// Relocation types of LoongArch processor.
+//
+#define EFI_IMAGE_REL_BASED_LOONGARCH32_MARK_LA 8
+#define EFI_IMAGE_REL_BASED_LOONGARCH64_MARK_LA 8
+
+///
+/// Line number format.
+///
+typedef struct {
+ union {
+ UINT32 SymbolTableIndex; ///< Symbol table index of function name if Linenumber is 0.
+ UINT32 VirtualAddress; ///< Virtual address of line number.
+ } Type;
+ UINT16 Linenumber; ///< Line number.
+} EFI_IMAGE_LINENUMBER;
+
+///
+/// Size of EFI_IMAGE_LINENUMBER.
+///
+#define EFI_IMAGE_SIZEOF_LINENUMBER 6
+
+//
+// Archive format.
+//
+#define EFI_IMAGE_ARCHIVE_START_SIZE 8
+#define EFI_IMAGE_ARCHIVE_START "!\n"
+#define EFI_IMAGE_ARCHIVE_END "`\n"
+#define EFI_IMAGE_ARCHIVE_PAD "\n"
+#define EFI_IMAGE_ARCHIVE_LINKER_MEMBER "/ "
+#define EFI_IMAGE_ARCHIVE_LONGNAMES_MEMBER "// "
+
+///
+/// Archive Member Headers
+///
+typedef struct {
+ UINT8 Name[16]; ///< File member name - `/' terminated.
+ UINT8 Date[12]; ///< File member date - decimal.
+ UINT8 UserID[6]; ///< File member user id - decimal.
+ UINT8 GroupID[6]; ///< File member group id - decimal.
+ UINT8 Mode[8]; ///< File member mode - octal.
+ UINT8 Size[10]; ///< File member size - decimal.
+ UINT8 EndHeader[2]; ///< String to end header. (0x60 0x0A).
+} EFI_IMAGE_ARCHIVE_MEMBER_HEADER;
+
+///
+/// Size of EFI_IMAGE_ARCHIVE_MEMBER_HEADER.
+///
+#define EFI_IMAGE_SIZEOF_ARCHIVE_MEMBER_HDR 60
+
+//
+// DLL Support
+//
+
+///
+/// Export Directory Table.
+///
+typedef struct {
+ UINT32 Characteristics;
+ UINT32 TimeDateStamp;
+ UINT16 MajorVersion;
+ UINT16 MinorVersion;
+ UINT32 Name;
+ UINT32 Base;
+ UINT32 NumberOfFunctions;
+ UINT32 NumberOfNames;
+ UINT32 AddressOfFunctions;
+ UINT32 AddressOfNames;
+ UINT32 AddressOfNameOrdinals;
+} EFI_IMAGE_EXPORT_DIRECTORY;
+
+///
+/// Hint/Name Table.
+///
+typedef struct {
+ UINT16 Hint;
+ UINT8 Name[1];
+} EFI_IMAGE_IMPORT_BY_NAME;
+
+///
+/// Import Address Table RVA (Thunk Table).
+///
+typedef struct {
+ union {
+ UINT32 Function;
+ UINT32 Ordinal;
+ EFI_IMAGE_IMPORT_BY_NAME *AddressOfData;
+ } u1;
+} EFI_IMAGE_THUNK_DATA;
+
+#define EFI_IMAGE_ORDINAL_FLAG BIT31 ///< Flag for PE32.
+#define EFI_IMAGE_SNAP_BY_ORDINAL(Ordinal) ((Ordinal & EFI_IMAGE_ORDINAL_FLAG) != 0)
+#define EFI_IMAGE_ORDINAL(Ordinal) (Ordinal & 0xffff)
+
+///
+/// Import Directory Table
+///
+typedef struct {
+ UINT32 Characteristics;
+ UINT32 TimeDateStamp;
+ UINT32 ForwarderChain;
+ UINT32 Name;
+ EFI_IMAGE_THUNK_DATA *FirstThunk;
+} EFI_IMAGE_IMPORT_DESCRIPTOR;
+
+///
+/// Debug Directory Format.
+///
+typedef struct {
+ UINT32 Characteristics;
+ UINT32 TimeDateStamp;
+ UINT16 MajorVersion;
+ UINT16 MinorVersion;
+ UINT32 Type;
+ UINT32 SizeOfData;
+ UINT32 RVA; ///< The address of the debug data when loaded, relative to the image base.
+ UINT32 FileOffset; ///< The file pointer to the debug data.
+} EFI_IMAGE_DEBUG_DIRECTORY_ENTRY;
+
+#define EFI_IMAGE_DEBUG_TYPE_CODEVIEW 2 ///< The Visual C++ debug information.
+
+///
+/// Debug Data Structure defined in Microsoft C++.
+///
+#define CODEVIEW_SIGNATURE_NB10 SIGNATURE_32('N', 'B', '1', '0')
+typedef struct {
+ UINT32 Signature; ///< "NB10"
+ UINT32 Unknown;
+ UINT32 Unknown2;
+ UINT32 Unknown3;
+ //
+ // Filename of .PDB goes here
+ //
+} EFI_IMAGE_DEBUG_CODEVIEW_NB10_ENTRY;
+
+///
+/// Debug Data Structure defined in Microsoft C++.
+///
+#define CODEVIEW_SIGNATURE_RSDS SIGNATURE_32('R', 'S', 'D', 'S')
+typedef struct {
+ UINT32 Signature; ///< "RSDS".
+ UINT32 Unknown;
+ UINT32 Unknown2;
+ UINT32 Unknown3;
+ UINT32 Unknown4;
+ UINT32 Unknown5;
+ //
+ // Filename of .PDB goes here
+ //
+} EFI_IMAGE_DEBUG_CODEVIEW_RSDS_ENTRY;
+
+///
+/// Debug Data Structure defined by Apple Mach-O to Coff utility.
+///
+#define CODEVIEW_SIGNATURE_MTOC SIGNATURE_32('M', 'T', 'O', 'C')
+typedef struct {
+ UINT32 Signature; ///< "MTOC".
+ GUID MachOUuid;
+ //
+ // Filename of .DLL (Mach-O with debug info) goes here
+ //
+} EFI_IMAGE_DEBUG_CODEVIEW_MTOC_ENTRY;
+
+///
+/// Resource format.
+///
+typedef struct {
+ UINT32 Characteristics;
+ UINT32 TimeDateStamp;
+ UINT16 MajorVersion;
+ UINT16 MinorVersion;
+ UINT16 NumberOfNamedEntries;
+ UINT16 NumberOfIdEntries;
+ //
+ // Array of EFI_IMAGE_RESOURCE_DIRECTORY_ENTRY entries goes here.
+ //
+} EFI_IMAGE_RESOURCE_DIRECTORY;
+
+///
+/// Resource directory entry format.
+///
+typedef struct {
+ union {
+ struct {
+ UINT32 NameOffset : 31;
+ UINT32 NameIsString : 1;
+ } s;
+ UINT32 Id;
+ } u1;
+ union {
+ UINT32 OffsetToData;
+ struct {
+ UINT32 OffsetToDirectory : 31;
+ UINT32 DataIsDirectory : 1;
+ } s;
+ } u2;
+} EFI_IMAGE_RESOURCE_DIRECTORY_ENTRY;
+
+///
+/// Resource directory entry for string.
+///
+typedef struct {
+ UINT16 Length;
+ CHAR16 String[1];
+} EFI_IMAGE_RESOURCE_DIRECTORY_STRING;
+
+///
+/// Resource directory entry for data array.
+///
+typedef struct {
+ UINT32 OffsetToData;
+ UINT32 Size;
+ UINT32 CodePage;
+ UINT32 Reserved;
+} EFI_IMAGE_RESOURCE_DATA_ENTRY;
+
+///
+/// Header format for TE images, defined in the PI Specification, 1.0.
+///
+typedef struct {
+ UINT16 Signature; ///< The signature for TE format = "VZ".
+ UINT16 Machine; ///< From the original file header.
+ UINT8 NumberOfSections; ///< From the original file header.
+ UINT8 Subsystem; ///< From original optional header.
+ UINT16 StrippedSize; ///< Number of bytes we removed from the header.
+ UINT32 AddressOfEntryPoint; ///< Offset to entry point -- from original optional header.
+ UINT32 BaseOfCode; ///< From original image -- required for ITP debug.
+ UINT64 ImageBase; ///< From original file header.
+ EFI_IMAGE_DATA_DIRECTORY DataDirectory[2]; ///< Only base relocation and debug directory.
+} EFI_TE_IMAGE_HEADER;
+
+#define EFI_TE_IMAGE_HEADER_SIGNATURE SIGNATURE_16('V', 'Z')
+
+//
+// Data directory indexes in our TE image header
+//
+#define EFI_TE_IMAGE_DIRECTORY_ENTRY_BASERELOC 0
+#define EFI_TE_IMAGE_DIRECTORY_ENTRY_DEBUG 1
+
+///
+/// Union of PE32, PE32+, and TE headers.
+///
+typedef union {
+ EFI_IMAGE_NT_HEADERS32 Pe32;
+ EFI_IMAGE_NT_HEADERS64 Pe32Plus;
+ EFI_TE_IMAGE_HEADER Te;
+} EFI_IMAGE_OPTIONAL_HEADER_UNION;
+
+typedef union {
+ EFI_IMAGE_NT_HEADERS32 *Pe32;
+ EFI_IMAGE_NT_HEADERS64 *Pe32Plus;
+ EFI_TE_IMAGE_HEADER *Te;
+ EFI_IMAGE_OPTIONAL_HEADER_UNION *Union;
+} EFI_IMAGE_OPTIONAL_HEADER_PTR_UNION;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/Scsi.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/Scsi.h
new file mode 100644
index 0000000000..2ce3722e75
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/Scsi.h
@@ -0,0 +1,425 @@
+/** @file
+ Support for SCSI-2 standard
+
+ Copyright (c) 2006 - 2020, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __SCSI_H__
+#define __SCSI_H__
+
+//
+// SCSI command OP Code
+//
+//
+// Commands for all device types
+//
+#define EFI_SCSI_OP_CHANGE_DEFINITION 0x40
+#define EFI_SCSI_OP_COMPARE 0x39
+#define EFI_SCSI_OP_COPY 0x18
+#define EFI_SCSI_OP_COPY_VERIFY 0x3a
+#define EFI_SCSI_OP_INQUIRY 0x12
+#define EFI_SCSI_OP_LOG_SELECT 0x4c
+#define EFI_SCSI_OP_LOG_SENSE 0x4d
+#define EFI_SCSI_OP_MODE_SEL6 0x15
+#define EFI_SCSI_OP_MODE_SEL10 0x55
+#define EFI_SCSI_OP_MODE_SEN6 0x1a
+#define EFI_SCSI_OP_MODE_SEN10 0x5a
+#define EFI_SCSI_OP_READ_BUFFER 0x3c
+#define EFI_SCSI_OP_RECEIVE_DIAG 0x1c
+#define EFI_SCSI_OP_REQUEST_SENSE 0x03
+#define EFI_SCSI_OP_SEND_DIAG 0x1d
+#define EFI_SCSI_OP_TEST_UNIT_READY 0x00
+#define EFI_SCSI_OP_WRITE_BUFF 0x3b
+
+//
+// Additional commands for Direct Access Devices
+//
+#define EFI_SCSI_OP_FORMAT 0x04
+#define EFI_SCSI_OP_LOCK_UN_CACHE 0x36
+#define EFI_SCSI_OP_PREFETCH 0x34
+#define EFI_SCSI_OP_MEDIA_REMOVAL 0x1e
+#define EFI_SCSI_OP_READ6 0x08
+#define EFI_SCSI_OP_READ10 0x28
+#define EFI_SCSI_OP_READ16 0x88
+#define EFI_SCSI_OP_READ_CAPACITY 0x25
+#define EFI_SCSI_OP_READ_CAPACITY16 0x9e
+#define EFI_SCSI_OP_READ_DEFECT 0x37
+#define EFI_SCSI_OP_READ_LONG 0x3e
+#define EFI_SCSI_OP_REASSIGN_BLK 0x07
+#define EFI_SCSI_OP_RELEASE 0x17
+#define EFI_SCSI_OP_REZERO 0x01
+#define EFI_SCSI_OP_SEARCH_DATA_E 0x31
+#define EFI_SCSI_OP_SEARCH_DATA_H 0x30
+#define EFI_SCSI_OP_SEARCH_DATA_L 0x32
+#define EFI_SCSI_OP_SEEK6 0x0b
+#define EFI_SCSI_OP_SEEK10 0x2b
+#define EFI_SCSI_OP_SEND_DIAG 0x1d
+#define EFI_SCSI_OP_SET_LIMIT 0x33
+#define EFI_SCSI_OP_START_STOP_UNIT 0x1b
+#define EFI_SCSI_OP_SYNC_CACHE 0x35
+#define EFI_SCSI_OP_VERIFY 0x2f
+#define EFI_SCSI_OP_WRITE6 0x0a
+#define EFI_SCSI_OP_WRITE10 0x2a
+#define EFI_SCSI_OP_WRITE16 0x8a
+#define EFI_SCSI_OP_WRITE_VERIFY 0x2e
+#define EFI_SCSI_OP_WRITE_LONG 0x3f
+#define EFI_SCSI_OP_WRITE_SAME 0x41
+#define EFI_SCSI_OP_UNMAP 0x42
+
+//
+// Additional commands for Sequential Access Devices
+//
+#define EFI_SCSI_OP_ERASE 0x19
+#define EFI_SCSI_OP_LOAD_UNLOAD 0x1b
+#define EFI_SCSI_OP_LOCATE 0x2b
+#define EFI_SCSI_OP_READ_BLOCK_LIMIT 0x05
+#define EFI_SCSI_OP_READ_POS 0x34
+#define EFI_SCSI_OP_READ_REVERSE 0x0f
+#define EFI_SCSI_OP_RECOVER_BUF_DATA 0x14
+#define EFI_SCSI_OP_RESERVE_UNIT 0x16
+#define EFI_SCSI_OP_REWIND 0x01
+#define EFI_SCSI_OP_SPACE 0x11
+#define EFI_SCSI_OP_VERIFY_TAPE 0x13
+#define EFI_SCSI_OP_WRITE_FILEMARK 0x10
+
+//
+// Additional commands for Printer Devices
+//
+#define EFI_SCSI_OP_PRINT 0x0a
+#define EFI_SCSI_OP_SLEW_PRINT 0x0b
+#define EFI_SCSI_OP_STOP_PRINT 0x1b
+#define EFI_SCSI_OP_SYNC_BUFF 0x10
+
+//
+// Additional commands for Processor Devices
+//
+#define EFI_SCSI_OP_RECEIVE 0x08
+#define EFI_SCSI_OP_SEND 0x0a
+
+//
+// Additional commands for Write-Once Devices
+//
+#define EFI_SCSI_OP_MEDIUM_SCAN 0x38
+#define EFI_SCSI_OP_SEARCH_DAT_E10 0x31
+#define EFI_SCSI_OP_SEARCH_DAT_E12 0xb1
+#define EFI_SCSI_OP_SEARCH_DAT_H10 0x30
+#define EFI_SCSI_OP_SEARCH_DAT_H12 0xb0
+#define EFI_SCSI_OP_SEARCH_DAT_L10 0x32
+#define EFI_SCSI_OP_SEARCH_DAT_L12 0xb2
+#define EFI_SCSI_OP_SET_LIMIT10 0x33
+#define EFI_SCSI_OP_SET_LIMIT12 0xb3
+#define EFI_SCSI_OP_VERIFY10 0x2f
+#define EFI_SCSI_OP_VERIFY12 0xaf
+#define EFI_SCSI_OP_WRITE12 0xaa
+#define EFI_SCSI_OP_WRITE_VERIFY10 0x2e
+#define EFI_SCSI_OP_WRITE_VERIFY12 0xae
+
+//
+// Additional commands for CD-ROM Devices
+//
+#define EFI_SCSI_OP_PLAY_AUD_10 0x45
+#define EFI_SCSI_OP_PLAY_AUD_12 0xa5
+#define EFI_SCSI_OP_PLAY_AUD_MSF 0x47
+#define EFI_SCSI_OP_PLAY_AUD_TKIN 0x48
+#define EFI_SCSI_OP_PLAY_TK_REL10 0x49
+#define EFI_SCSI_OP_PLAY_TK_REL12 0xa9
+#define EFI_SCSI_OP_READ_CD_CAPACITY 0x25
+#define EFI_SCSI_OP_READ_HEADER 0x44
+#define EFI_SCSI_OP_READ_SUB_CHANNEL 0x42
+#define EFI_SCSI_OP_READ_TOC 0x43
+
+//
+// Additional commands for Scanner Devices
+//
+#define EFI_SCSI_OP_GET_DATABUFF_STAT 0x34
+#define EFI_SCSI_OP_GET_WINDOW 0x25
+#define EFI_SCSI_OP_OBJECT_POS 0x31
+#define EFI_SCSI_OP_SCAN 0x1b
+#define EFI_SCSI_OP_SET_WINDOW 0x24
+
+//
+// Additional commands for Optical Memory Devices
+//
+#define EFI_SCSI_OP_UPDATE_BLOCK 0x3d
+
+//
+// Additional commands for Medium Changer Devices
+//
+#define EFI_SCSI_OP_EXCHANGE_MEDIUM 0xa6
+#define EFI_SCSI_OP_INIT_ELEMENT_STAT 0x07
+#define EFI_SCSI_OP_POS_TO_ELEMENT 0x2b
+#define EFI_SCSI_OP_REQUEST_VE_ADDR 0xb5
+#define EFI_SCSI_OP_SEND_VOL_TAG 0xb6
+
+//
+// Additional commands for Communication Devices
+//
+#define EFI_SCSI_OP_GET_MESSAGE6 0x08
+#define EFI_SCSI_OP_GET_MESSAGE10 0x28
+#define EFI_SCSI_OP_GET_MESSAGE12 0xa8
+#define EFI_SCSI_OP_SEND_MESSAGE6 0x0a
+#define EFI_SCSI_OP_SEND_MESSAGE10 0x2a
+#define EFI_SCSI_OP_SEND_MESSAGE12 0xaa
+
+//
+// Additional commands for Secure Transactions
+//
+#define EFI_SCSI_OP_SECURITY_PROTOCOL_IN 0xa2
+#define EFI_SCSI_OP_SECURITY_PROTOCOL_OUT 0xb5
+
+//
+// SCSI Data Transfer Direction
+//
+#define EFI_SCSI_DATA_IN 0
+#define EFI_SCSI_DATA_OUT 1
+
+//
+// SCSI Block Command Cache Control Parameters
+//
+#define EFI_SCSI_BLOCK_FUA BIT3 ///< Force Unit Access
+#define EFI_SCSI_BLOCK_DPO BIT4 ///< Disable Page Out
+
+//
+// Peripheral Device Type Definitions
+//
+#define EFI_SCSI_TYPE_DISK 0x00 ///< Direct-access device (e.g. magnetic disk)
+#define EFI_SCSI_TYPE_TAPE 0x01 ///< Sequential-access device (e.g. magnetic tape)
+#define EFI_SCSI_TYPE_PRINTER 0x02 ///< Printer device
+#define EFI_SCSI_TYPE_PROCESSOR 0x03 ///< Processor device
+#define EFI_SCSI_TYPE_WORM 0x04 ///< Write-once device (e.g. some optical disks)
+#define EFI_SCSI_TYPE_CDROM 0x05 ///< CD/DVD device
+#define EFI_SCSI_TYPE_SCANNER 0x06 ///< Scanner device (obsolete)
+#define EFI_SCSI_TYPE_OPTICAL 0x07 ///< Optical memory device (e.g. some optical disks)
+#define EFI_SCSI_TYPE_MEDIUMCHANGER 0x08 ///< Medium changer device (e.g. jukeboxes)
+#define EFI_SCSI_TYPE_COMMUNICATION 0x09 ///< Communications device (obsolete)
+#define EFI_SCSI_TYPE_ASCIT8_1 0x0A ///< Defined by ASC IT8 (Graphic arts pre-press devices)
+#define EFI_SCSI_TYPE_ASCIT8_2 0x0B ///< Defined by ASC IT8 (Graphic arts pre-press devices)
+#define EFI_SCSI_TYPE_RAID 0x0C ///< Storage array controller device (e.g., RAID)
+#define EFI_SCSI_TYPE_SES 0x0D ///< Enclosure services device
+#define EFI_SCSI_TYPE_RBC 0x0E ///< Simplified direct-access device (e.g., magnetic disk)
+#define EFI_SCSI_TYPE_OCRW 0x0F ///< Optical card reader/writer device
+#define EFI_SCSI_TYPE_BRIDGE 0x10 ///< Bridge Controller Commands
+#define EFI_SCSI_TYPE_OSD 0x11 ///< Object-based Storage Device
+#define EFI_SCSI_TYPE_AUTOMATION 0x12 ///< Automation/Drive Interface
+#define EFI_SCSI_TYPE_SECURITYMANAGER 0x13 ///< Security manager device
+#define EFI_SCSI_TYPE_RESERVED_LOW 0x14 ///< Reserved (low)
+#define EFI_SCSI_TYPE_RESERVED_HIGH 0x1D ///< Reserved (high)
+#define EFI_SCSI_TYPE_WLUN 0x1E ///< Well known logical unit
+#define EFI_SCSI_TYPE_UNKNOWN 0x1F ///< Unknown or no device type
+
+//
+// Page Codes for INQUIRY command
+//
+#define EFI_SCSI_PAGE_CODE_SUPPORTED_VPD 0x00
+#define EFI_SCSI_PAGE_CODE_BLOCK_LIMITS_VPD 0xB0
+
+#pragma pack(1)
+///
+/// Standard INQUIRY data format
+///
+typedef struct {
+ UINT8 Peripheral_Type : 5;
+ UINT8 Peripheral_Qualifier : 3;
+ UINT8 DeviceType_Modifier : 7;
+ UINT8 Rmb : 1;
+ UINT8 Version;
+ UINT8 Response_Data_Format;
+ UINT8 Addnl_Length;
+ UINT8 Reserved_5_95[95 - 5 + 1];
+} EFI_SCSI_INQUIRY_DATA;
+
+///
+/// Supported VPD Pages VPD page
+///
+typedef struct {
+ UINT8 Peripheral_Type : 5;
+ UINT8 Peripheral_Qualifier : 3;
+ UINT8 PageCode;
+ UINT8 PageLength2;
+ UINT8 PageLength1;
+ UINT8 SupportedVpdPageList[0x100];
+} EFI_SCSI_SUPPORTED_VPD_PAGES_VPD_PAGE;
+
+///
+/// Block Limits VPD page
+///
+typedef struct {
+ UINT8 Peripheral_Type : 5;
+ UINT8 Peripheral_Qualifier : 3;
+ UINT8 PageCode;
+ UINT8 PageLength2;
+ UINT8 PageLength1;
+ UINT8 WriteSameNonZero : 1;
+ UINT8 Reserved_4 : 7;
+ UINT8 MaximumCompareAndWriteLength;
+ UINT8 OptimalTransferLengthGranularity2;
+ UINT8 OptimalTransferLengthGranularity1;
+ UINT8 MaximumTransferLength4;
+ UINT8 MaximumTransferLength3;
+ UINT8 MaximumTransferLength2;
+ UINT8 MaximumTransferLength1;
+ UINT8 OptimalTransferLength4;
+ UINT8 OptimalTransferLength3;
+ UINT8 OptimalTransferLength2;
+ UINT8 OptimalTransferLength1;
+ UINT8 MaximumPrefetchXdreadXdwriteTransferLength4;
+ UINT8 MaximumPrefetchXdreadXdwriteTransferLength3;
+ UINT8 MaximumPrefetchXdreadXdwriteTransferLength2;
+ UINT8 MaximumPrefetchXdreadXdwriteTransferLength1;
+ UINT8 MaximumUnmapLbaCount4;
+ UINT8 MaximumUnmapLbaCount3;
+ UINT8 MaximumUnmapLbaCount2;
+ UINT8 MaximumUnmapLbaCount1;
+ UINT8 MaximumUnmapBlockDescriptorCount4;
+ UINT8 MaximumUnmapBlockDescriptorCount3;
+ UINT8 MaximumUnmapBlockDescriptorCount2;
+ UINT8 MaximumUnmapBlockDescriptorCount1;
+ UINT8 OptimalUnmapGranularity4;
+ UINT8 OptimalUnmapGranularity3;
+ UINT8 OptimalUnmapGranularity2;
+ UINT8 OptimalUnmapGranularity1;
+ UINT8 UnmapGranularityAlignment4 : 7;
+ UINT8 UnmapGranularityAlignmentValid : 1;
+ UINT8 UnmapGranularityAlignment3;
+ UINT8 UnmapGranularityAlignment2;
+ UINT8 UnmapGranularityAlignment1;
+ UINT8 MaximumWriteSameLength4;
+ UINT8 MaximumWriteSameLength3;
+ UINT8 MaximumWriteSameLength2;
+ UINT8 MaximumWriteSameLength1;
+ UINT8 MaximumAtomicTransferLength4;
+ UINT8 MaximumAtomicTransferLength3;
+ UINT8 MaximumAtomicTransferLength2;
+ UINT8 MaximumAtomicTransferLength1;
+ UINT8 AtomicAlignment4;
+ UINT8 AtomicAlignment3;
+ UINT8 AtomicAlignment2;
+ UINT8 AtomicAlignment1;
+ UINT8 AtomicTransferLengthGranularity4;
+ UINT8 AtomicTransferLengthGranularity3;
+ UINT8 AtomicTransferLengthGranularity2;
+ UINT8 AtomicTransferLengthGranularity1;
+ UINT8 MaximumAtomicTransferLengthWithAtomicBoundary4;
+ UINT8 MaximumAtomicTransferLengthWithAtomicBoundary3;
+ UINT8 MaximumAtomicTransferLengthWithAtomicBoundary2;
+ UINT8 MaximumAtomicTransferLengthWithAtomicBoundary1;
+ UINT8 MaximumAtomicBoundarySize4;
+ UINT8 MaximumAtomicBoundarySize3;
+ UINT8 MaximumAtomicBoundarySize2;
+ UINT8 MaximumAtomicBoundarySize1;
+} EFI_SCSI_BLOCK_LIMITS_VPD_PAGE;
+
+///
+/// Error codes 70h and 71h sense data format
+///
+typedef struct {
+ UINT8 Error_Code : 7;
+ UINT8 Valid : 1;
+ UINT8 Segment_Number;
+ UINT8 Sense_Key : 4;
+ UINT8 Reserved_21 : 1;
+ UINT8 Ili : 1;
+ UINT8 Reserved_22 : 2;
+ UINT8 Information_3_6[4];
+ UINT8 Addnl_Sense_Length; ///< Additional sense length (n-7)
+ UINT8 Vendor_Specific_8_11[4];
+ UINT8 Addnl_Sense_Code; ///< Additional sense code
+ UINT8 Addnl_Sense_Code_Qualifier; ///< Additional sense code qualifier
+ UINT8 Field_Replaceable_Unit_Code; ///< Field replaceable unit code
+ UINT8 Reserved_15_17[3];
+} EFI_SCSI_SENSE_DATA;
+
+///
+/// SCSI Disk READ CAPACITY Data
+///
+typedef struct {
+ UINT8 LastLba3;
+ UINT8 LastLba2;
+ UINT8 LastLba1;
+ UINT8 LastLba0;
+ UINT8 BlockSize3;
+ UINT8 BlockSize2;
+ UINT8 BlockSize1;
+ UINT8 BlockSize0;
+} EFI_SCSI_DISK_CAPACITY_DATA;
+
+typedef struct {
+ UINT8 LastLba7;
+ UINT8 LastLba6;
+ UINT8 LastLba5;
+ UINT8 LastLba4;
+ UINT8 LastLba3;
+ UINT8 LastLba2;
+ UINT8 LastLba1;
+ UINT8 LastLba0;
+ UINT8 BlockSize3;
+ UINT8 BlockSize2;
+ UINT8 BlockSize1;
+ UINT8 BlockSize0;
+ UINT8 Protection;
+ UINT8 LogicPerPhysical;
+ UINT8 LowestAlignLogic2;
+ UINT8 LowestAlignLogic1;
+ UINT8 Reserved[16];
+} EFI_SCSI_DISK_CAPACITY_DATA16;
+
+typedef struct {
+ UINT16 DataLen;
+ UINT16 BlkDespDataLen;
+ UINT8 Reserved[4];
+} EFI_SCSI_DISK_UNMAP_PARAM_LIST_HEADER;
+
+typedef struct {
+ UINT64 Lba;
+ UINT32 BlockNum;
+ UINT8 Reserved[4];
+} EFI_SCSI_DISK_UNMAP_BLOCK_DESP;
+
+#pragma pack()
+
+//
+// Sense Key
+//
+#define EFI_SCSI_SK_NO_SENSE (0x0)
+#define EFI_SCSI_SK_RECOVERY_ERROR (0x1)
+#define EFI_SCSI_SK_NOT_READY (0x2)
+#define EFI_SCSI_SK_MEDIUM_ERROR (0x3)
+#define EFI_SCSI_SK_HARDWARE_ERROR (0x4)
+#define EFI_SCSI_SK_ILLEGAL_REQUEST (0x5)
+#define EFI_SCSI_SK_UNIT_ATTENTION (0x6)
+#define EFI_SCSI_SK_DATA_PROTECT (0x7)
+#define EFI_SCSI_SK_BLANK_CHECK (0x8)
+#define EFI_SCSI_SK_VENDOR_SPECIFIC (0x9)
+#define EFI_SCSI_SK_RESERVED_A (0xA)
+#define EFI_SCSI_SK_ABORT (0xB)
+#define EFI_SCSI_SK_RESERVED_C (0xC)
+#define EFI_SCSI_SK_OVERFLOW (0xD)
+#define EFI_SCSI_SK_MISCOMPARE (0xE)
+#define EFI_SCSI_SK_RESERVED_F (0xF)
+
+//
+// Additional Sense Codes and Sense Code Qualifiers.
+// Only some frequently used additional sense codes and qualifiers are
+// defined here. Please refer to SCSI standard for full value definition.
+//
+#define EFI_SCSI_ASC_NOT_READY (0x04)
+#define EFI_SCSI_ASCQ_IN_PROGRESS (0x01)
+
+#define EFI_SCSI_ASC_MEDIA_ERR1 (0x10)
+#define EFI_SCSI_ASC_MEDIA_ERR2 (0x11)
+#define EFI_SCSI_ASC_MEDIA_ERR3 (0x14)
+#define EFI_SCSI_ASC_MEDIA_ERR4 (0x30)
+#define EFI_SCSI_ASC_MEDIA_UPSIDE_DOWN (0x06)
+#define EFI_SCSI_ASC_INVALID_CMD (0x20)
+#define EFI_SCSI_ASC_LBA_OUT_OF_RANGE (0x21)
+#define EFI_SCSI_ASC_INVALID_FIELD (0x24)
+#define EFI_SCSI_ASC_WRITE_PROTECTED (0x27)
+#define EFI_SCSI_ASC_MEDIA_CHANGE (0x28)
+#define EFI_SCSI_ASC_RESET (0x29) ///< Power On Reset or Bus Reset occurred
+#define EFI_SCSI_ASC_ILLEGAL_FIELD (0x26)
+#define EFI_SCSI_ASC_NO_MEDIA (0x3A)
+#define EFI_SCSI_ASC_ILLEGAL_MODE_FOR_THIS_TRACK (0x64)
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/Sd.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/Sd.h
new file mode 100644
index 0000000000..3cfdad21a1
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/Sd.h
@@ -0,0 +1,175 @@
+/** @file
+ Header file for SD memory card support.
+
+ This header file contains some definitions defined in SD Physical Layer Simplified
+ Specification Version 4.10 spec.
+
+ Copyright (c) 2015, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __SD_H__
+#define __SD_H__
+
+//
+// SD command index
+//
+#define SD_GO_IDLE_STATE 0
+#define SD_ALL_SEND_CID 2
+#define SD_SET_RELATIVE_ADDR 3
+#define SD_SET_DSR 4
+#define SDIO_SEND_OP_COND 5
+#define SD_SWITCH_FUNC 6
+#define SD_SELECT_DESELECT_CARD 7
+#define SD_SEND_IF_COND 8
+#define SD_SEND_CSD 9
+#define SD_SEND_CID 10
+#define SD_VOLTAGE_SWITCH 11
+#define SD_STOP_TRANSMISSION 12
+#define SD_SEND_STATUS 13
+#define SD_GO_INACTIVE_STATE 15
+#define SD_SET_BLOCKLEN 16
+#define SD_READ_SINGLE_BLOCK 17
+#define SD_READ_MULTIPLE_BLOCK 18
+#define SD_SEND_TUNING_BLOCK 19
+#define SD_SPEED_CLASS_CONTROL 20
+#define SD_SET_BLOCK_COUNT 23
+#define SD_WRITE_SINGLE_BLOCK 24
+#define SD_WRITE_MULTIPLE_BLOCK 25
+#define SD_PROGRAM_CSD 27
+#define SD_SET_WRITE_PROT 28
+#define SD_CLR_WRITE_PROT 29
+#define SD_SEND_WRITE_PROT 30
+#define SD_ERASE_WR_BLK_START 32
+#define SD_ERASE_WR_BLK_END 33
+#define SD_ERASE 38
+#define SD_LOCK_UNLOCK 42
+#define SD_READ_EXTR_SINGLE 48
+#define SD_WRITE_EXTR_SINGLE 49
+#define SDIO_RW_DIRECT 52
+#define SDIO_RW_EXTENDED 53
+#define SD_APP_CMD 55
+#define SD_GEN_CMD 56
+#define SD_READ_EXTR_MULTI 58
+#define SD_WRITE_EXTR_MULTI 59
+
+#define SD_SET_BUS_WIDTH 6 // ACMD6
+#define SD_STATUS 13 // ACMD13
+#define SD_SEND_NUM_WR_BLOCKS 22 // ACMD22
+#define SD_SET_WR_BLK_ERASE_COUNT 23 // ACMD23
+#define SD_SEND_OP_COND 41 // ACMD41
+#define SD_SET_CLR_CARD_DETECT 42 // ACMD42
+#define SD_SEND_SCR 51 // ACMD51
+
+#pragma pack(1)
+typedef struct {
+ UINT8 NotUsed : 1; // Not used [0:0]
+ UINT8 Crc : 7; // CRC [7:1]
+ UINT16 ManufacturingDate : 12; // Manufacturing date [19:8]
+ UINT16 Reserved : 4; // Reserved [23:20]
+ UINT8 ProductSerialNumber[4]; // Product serial number [55:24]
+ UINT8 ProductRevision; // Product revision [63:56]
+ UINT8 ProductName[5]; // Product name [103:64]
+ UINT8 OemId[2]; // OEM/Application ID [119:104]
+ UINT8 ManufacturerId; // Manufacturer ID [127:120]
+} SD_CID;
+
+typedef struct {
+ UINT32 NotUsed : 1; // Not used [0:0]
+ UINT32 Crc : 7; // CRC [7:1]
+ UINT32 Reserved : 2; // Reserved [9:8]
+ UINT32 FileFormat : 2; // File format [11:10]
+ UINT32 TmpWriteProtect : 1; // Temporary write protection [12:12]
+ UINT32 PermWriteProtect : 1; // Permanent write protection [13:13]
+ UINT32 Copy : 1; // Copy flag (OTP) [14:14]
+ UINT32 FileFormatGrp : 1; // File format group [15:15]
+ UINT32 Reserved1 : 5; // Reserved [20:16]
+ UINT32 WriteBlPartial : 1; // Partial blocks for write allowed [21:21]
+ UINT32 WriteBlLen : 4; // Max. write data block length [25:22]
+ UINT32 R2WFactor : 3; // Write speed factor [28:26]
+ UINT32 Reserved2 : 2; // Manufacturer default ECC [30:29]
+ UINT32 WpGrpEnable : 1; // Write protect group enable [31:31]
+
+ UINT32 WpGrpSize : 7; // Write protect group size [38:32]
+ UINT32 SectorSize : 7; // Erase sector size [45:39]
+ UINT32 EraseBlkEn : 1; // Erase single block enable [46:46]
+ UINT32 CSizeMul : 3; // device size multiplier [49:47]
+ UINT32 VddWCurrMax : 3; // max. write current @VDD max [52:50]
+ UINT32 VddWCurrMin : 3; // max. write current @VDD min [55:53]
+ UINT32 VddRCurrMax : 3; // max. read current @VDD max [58:56]
+ UINT32 VddRCurrMin : 3; // max. read current @VDD min [61:59]
+ UINT32 CSizeLow : 2; // Device size low 2 bits [63:62]
+
+ UINT32 CSizeHigh : 10; // Device size high 10 bits [73:64]
+ UINT32 Reserved4 : 2; // Reserved [75:74]
+ UINT32 DsrImp : 1; // DSR implemented [76:76]
+ UINT32 ReadBlkMisalign : 1; // Read block misalignment [77:77]
+ UINT32 WriteBlkMisalign : 1; // Write block misalignment [78:78]
+ UINT32 ReadBlPartial : 1; // Partial blocks for read allowed [79:79]
+ UINT32 ReadBlLen : 4; // Max. read data block length [83:80]
+ UINT32 Ccc : 12; // Card command classes [95:84]
+
+ UINT32 TranSpeed : 8; // Max. data transfer rate [103:96]
+ UINT32 Nsac : 8; // Data read access-time in CLK cycles (NSAC*100) [111:104]
+ UINT32 Taac : 8; // Data read access-time [119:112]
+ UINT32 Reserved5 : 6; // Reserved [125:120]
+ UINT32 CsdStructure : 2; // CSD structure [127:126]
+} SD_CSD;
+
+typedef struct {
+ UINT32 NotUsed : 1; // Not used [0:0]
+ UINT32 Crc : 7; // CRC [7:1]
+ UINT32 Reserved : 2; // Reserved [9:8]
+ UINT32 FileFormat : 2; // File format [11:10]
+ UINT32 TmpWriteProtect : 1; // Temporary write protection [12:12]
+ UINT32 PermWriteProtect : 1; // Permanent write protection [13:13]
+ UINT32 Copy : 1; // Copy flag (OTP) [14:14]
+ UINT32 FileFormatGrp : 1; // File format group [15:15]
+ UINT32 Reserved1 : 5; // Reserved [20:16]
+ UINT32 WriteBlPartial : 1; // Partial blocks for write allowed [21:21]
+ UINT32 WriteBlLen : 4; // Max. write data block length [25:22]
+ UINT32 R2WFactor : 3; // Write speed factor [28:26]
+ UINT32 Reserved2 : 2; // Manufacturer default ECC [30:29]
+ UINT32 WpGrpEnable : 1; // Write protect group enable [31:31]
+
+ UINT32 WpGrpSize : 7; // Write protect group size [38:32]
+ UINT32 SectorSize : 7; // Erase sector size [45:39]
+ UINT32 EraseBlkEn : 1; // Erase single block enable [46:46]
+ UINT32 Reserved3 : 1; // Reserved [47:47]
+ UINT32 CSizeLow : 16; // Device size low 16 bits [63:48]
+
+ UINT32 CSizeHigh : 6; // Device size high 6 bits [69:64]
+ UINT32 Reserved4 : 6; // Reserved [75:70]
+ UINT32 DsrImp : 1; // DSR implemented [76:76]
+ UINT32 ReadBlkMisalign : 1; // Read block misalignment [77:77]
+ UINT32 WriteBlkMisalign : 1; // Write block misalignment [78:78]
+ UINT32 ReadBlPartial : 1; // Partial blocks for read allowed [79:79]
+ UINT32 ReadBlLen : 4; // Max. read data block length [83:80]
+ UINT32 Ccc : 12; // Card command classes [95:84]
+
+ UINT32 TranSpeed : 8; // Max. data transfer rate [103:96]
+ UINT32 Nsac : 8; // Data read access-time in CLK cycles (NSAC*100) [111:104]
+ UINT32 Taac : 8; // Data read access-time [119:112]
+ UINT32 Reserved5 : 6; // Reserved [125:120]
+ UINT32 CsdStructure : 2; // CSD structure [127:126]
+} SD_CSD2;
+
+typedef struct {
+ UINT32 Reserved; // Reserved [31:0]
+
+ UINT32 CmdSupport : 4; // Command Support bits [35:32]
+ UINT32 Reserved1 : 6; // Reserved [41:36]
+ UINT32 SdSpec4 : 1; // Spec. Version 4.00 or higher [42:42]
+ UINT32 ExSecurity : 4; // Extended Security Support [46:43]
+ UINT32 SdSpec3 : 1; // Spec. Version 3.00 or higher [47:47]
+ UINT32 SdBusWidths : 4; // DAT Bus widths supported [51:48]
+ UINT32 SdSecurity : 3; // CPRM security support [54:52]
+ UINT32 DataStatAfterErase : 1; // Data status after erases [55]
+ UINT32 SdSpec : 4; // SD Memory Card Spec. Version [59:56]
+ UINT32 ScrStructure : 4; // SCR Structure [63:60]
+} SD_SCR;
+
+#pragma pack()
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/SdramSpd.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/SdramSpd.h
new file mode 100644
index 0000000000..390a0d03e2
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/SdramSpd.h
@@ -0,0 +1,68 @@
+/** @file
+ This file contains definitions for the SPD fields on an SDRAM.
+
+ Copyright (c) 2007 - 2016, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _SDRAM_SPD_H_
+#define _SDRAM_SPD_H_
+
+#include
+#include
+#include
+
+//
+// SDRAM SPD field definitions
+//
+#define SPD_MEMORY_TYPE 2
+#define SPD_SDRAM_ROW_ADDR 3
+#define SPD_SDRAM_COL_ADDR 4
+#define SPD_SDRAM_MODULE_ROWS 5
+#define SPD_SDRAM_MODULE_DATA_WIDTH_LSB 6
+#define SPD_SDRAM_MODULE_DATA_WIDTH_MSB 7
+#define SPD_SDRAM_ECC_SUPPORT 11
+#define SPD_SDRAM_REFRESH 12
+#define SPD_SDRAM_WIDTH 13
+#define SPD_SDRAM_ERROR_WIDTH 14
+#define SPD_SDRAM_BURST_LENGTH 16
+#define SPD_SDRAM_NO_OF_BANKS 17
+#define SPD_SDRAM_CAS_LATENCY 18
+#define SPD_SDRAM_MODULE_ATTR 21
+
+#define SPD_SDRAM_TCLK1_PULSE 9 ///< cycle time for highest cas latency
+#define SPD_SDRAM_TAC1_PULSE 10 ///< access time for highest cas latency
+#define SPD_SDRAM_TCLK2_PULSE 23 ///< cycle time for 2nd highest cas latency
+#define SPD_SDRAM_TAC2_PULSE 24 ///< access time for 2nd highest cas latency
+#define SPD_SDRAM_TCLK3_PULSE 25 ///< cycle time for 3rd highest cas latency
+#define SPD_SDRAM_TAC3_PULSE 26 ///< access time for 3rd highest cas latency
+#define SPD_SDRAM_MIN_PRECHARGE 27
+#define SPD_SDRAM_ACTIVE_MIN 28
+#define SPD_SDRAM_RAS_CAS 29
+#define SPD_SDRAM_RAS_PULSE 30
+#define SPD_SDRAM_DENSITY 31
+
+//
+// Memory Type Definitions
+//
+#define SPD_VAL_SDR_TYPE 4 ///< SDR SDRAM memory
+#define SPD_VAL_DDR_TYPE 7 ///< DDR SDRAM memory
+#define SPD_VAL_DDR2_TYPE 8 ///< DDR2 SDRAM memory
+#define SPD_VAL_DDR3_TYPE 11 ///< DDR3 SDRAM memory
+#define SPD_VAL_DDR4_TYPE 12 ///< DDR4 SDRAM memory
+#define SPD_VAL_LPDDR3_TYPE 15 ///< LPDDR3 SDRAM memory
+#define SPD_VAL_LPDDR4_TYPE 16 ///< LPDDR4 SDRAM memory
+
+//
+// ECC Type Definitions
+//
+#define SPD_ECC_TYPE_NONE 0x00 ///< No error checking
+#define SPD_ECC_TYPE_PARITY 0x01 ///< No error checking
+#define SPD_ECC_TYPE_ECC 0x02 ///< Error checking only
+//
+// Module Attributes (Bit positions)
+//
+#define SPD_BUFFERED 0x01
+#define SPD_REGISTERED 0x02
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/SdramSpdDdr3.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/SdramSpdDdr3.h
new file mode 100644
index 0000000000..960c1f4485
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/SdramSpdDdr3.h
@@ -0,0 +1,763 @@
+/** @file
+ This file contains definitions for SPD DDR3.
+
+ Copyright (c) 2016, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Revision Reference:
+ - Serial Presence Detect (SPD) for DDR3 SDRAM Modules Document Release 6
+ http://www.jedec.org/sites/default/files/docs/4_01_02_11R21A.pdf
+**/
+
+#ifndef _SDRAM_SPD_DDR3_H_
+#define _SDRAM_SPD_DDR3_H_
+
+#pragma pack (push, 1)
+
+typedef union {
+ struct {
+ UINT8 BytesUsed : 4; ///< Bits 3:0
+ UINT8 BytesTotal : 3; ///< Bits 6:4
+ UINT8 CrcCoverage : 1; ///< Bits 7:7
+ } Bits;
+ UINT8 Data;
+} SPD3_DEVICE_DESCRIPTION_STRUCT;
+
+typedef union {
+ struct {
+ UINT8 Minor : 4; ///< Bits 3:0
+ UINT8 Major : 4; ///< Bits 7:4
+ } Bits;
+ UINT8 Data;
+} SPD3_REVISION_STRUCT;
+
+typedef union {
+ struct {
+ UINT8 Type : 8; ///< Bits 7:0
+ } Bits;
+ UINT8 Data;
+} SPD3_DRAM_DEVICE_TYPE_STRUCT;
+
+typedef union {
+ struct {
+ UINT8 ModuleType : 4; ///< Bits 3:0
+ UINT8 Reserved : 4; ///< Bits 7:4
+ } Bits;
+ UINT8 Data;
+} SPD3_MODULE_TYPE_STRUCT;
+
+typedef union {
+ struct {
+ UINT8 Density : 4; ///< Bits 3:0
+ UINT8 BankAddress : 3; ///< Bits 6:4
+ UINT8 Reserved : 1; ///< Bits 7:7
+ } Bits;
+ UINT8 Data;
+} SPD3_SDRAM_DENSITY_BANKS_STRUCT;
+
+typedef union {
+ struct {
+ UINT8 ColumnAddress : 3; ///< Bits 2:0
+ UINT8 RowAddress : 3; ///< Bits 5:3
+ UINT8 Reserved : 2; ///< Bits 7:6
+ } Bits;
+ UINT8 Data;
+} SPD3_SDRAM_ADDRESSING_STRUCT;
+
+typedef union {
+ struct {
+ UINT8 OperationAt1_50 : 1; ///< Bits 0:0
+ UINT8 OperationAt1_35 : 1; ///< Bits 1:1
+ UINT8 OperationAt1_25 : 1; ///< Bits 2:2
+ UINT8 Reserved : 5; ///< Bits 7:3
+ } Bits;
+ UINT8 Data;
+} SPD3_MODULE_NOMINAL_VOLTAGE_STRUCT;
+
+typedef union {
+ struct {
+ UINT8 SdramDeviceWidth : 3; ///< Bits 2:0
+ UINT8 RankCount : 3; ///< Bits 5:3
+ UINT8 Reserved : 2; ///< Bits 7:6
+ } Bits;
+ UINT8 Data;
+} SPD3_MODULE_ORGANIZATION_STRUCT;
+
+typedef union {
+ struct {
+ UINT8 PrimaryBusWidth : 3; ///< Bits 2:0
+ UINT8 BusWidthExtension : 2; ///< Bits 4:3
+ UINT8 Reserved : 3; ///< Bits 7:5
+ } Bits;
+ UINT8 Data;
+} SPD3_MODULE_MEMORY_BUS_WIDTH_STRUCT;
+
+typedef union {
+ struct {
+ UINT8 Divisor : 4; ///< Bits 3:0
+ UINT8 Dividend : 4; ///< Bits 7:4
+ } Bits;
+ UINT8 Data;
+} SPD3_FINE_TIMEBASE_STRUCT;
+
+typedef union {
+ struct {
+ UINT8 Dividend : 8; ///< Bits 7:0
+ } Bits;
+ UINT8 Data;
+} SPD3_MEDIUM_TIMEBASE_DIVIDEND_STRUCT;
+
+typedef union {
+ struct {
+ UINT8 Divisor : 8; ///< Bits 7:0
+ } Bits;
+ UINT8 Data;
+} SPD3_MEDIUM_TIMEBASE_DIVISOR_STRUCT;
+
+typedef struct {
+ SPD3_MEDIUM_TIMEBASE_DIVIDEND_STRUCT Dividend; ///< Medium Timebase (MTB) Dividend
+ SPD3_MEDIUM_TIMEBASE_DIVISOR_STRUCT Divisor; ///< Medium Timebase (MTB) Divisor
+} SPD3_MEDIUM_TIMEBASE;
+
+typedef union {
+ struct {
+ UINT8 tCKmin : 8; ///< Bits 7:0
+ } Bits;
+ UINT8 Data;
+} SPD3_TCK_MIN_MTB_STRUCT;
+
+typedef union {
+ struct {
+ UINT16 Cl4 : 1; ///< Bits 0:0
+ UINT16 Cl5 : 1; ///< Bits 1:1
+ UINT16 Cl6 : 1; ///< Bits 2:2
+ UINT16 Cl7 : 1; ///< Bits 3:3
+ UINT16 Cl8 : 1; ///< Bits 4:4
+ UINT16 Cl9 : 1; ///< Bits 5:5
+ UINT16 Cl10 : 1; ///< Bits 6:6
+ UINT16 Cl11 : 1; ///< Bits 7:7
+ UINT16 Cl12 : 1; ///< Bits 8:8
+ UINT16 Cl13 : 1; ///< Bits 9:9
+ UINT16 Cl14 : 1; ///< Bits 10:10
+ UINT16 Cl15 : 1; ///< Bits 11:11
+ UINT16 Cl16 : 1; ///< Bits 12:12
+ UINT16 Cl17 : 1; ///< Bits 13:13
+ UINT16 Cl18 : 1; ///< Bits 14:14
+ UINT16 Reserved : 1; ///< Bits 15:15
+ } Bits;
+ UINT16 Data;
+ UINT8 Data8[2];
+} SPD3_CAS_LATENCIES_SUPPORTED_STRUCT;
+
+typedef union {
+ struct {
+ UINT8 tAAmin : 8; ///< Bits 7:0
+ } Bits;
+ UINT8 Data;
+} SPD3_TAA_MIN_MTB_STRUCT;
+
+typedef union {
+ struct {
+ UINT8 tWRmin : 8; ///< Bits 7:0
+ } Bits;
+ UINT8 Data;
+} SPD3_TWR_MIN_MTB_STRUCT;
+
+typedef union {
+ struct {
+ UINT8 tRCDmin : 8; ///< Bits 7:0
+ } Bits;
+ UINT8 Data;
+} SPD3_TRCD_MIN_MTB_STRUCT;
+
+typedef union {
+ struct {
+ UINT8 tRRDmin : 8; ///< Bits 7:0
+ } Bits;
+ UINT8 Data;
+} SPD3_TRRD_MIN_MTB_STRUCT;
+
+typedef union {
+ struct {
+ UINT8 tRPmin : 8; ///< Bits 7:0
+ } Bits;
+ UINT8 Data;
+} SPD3_TRP_MIN_MTB_STRUCT;
+
+typedef union {
+ struct {
+ UINT8 tRASminUpper : 4; ///< Bits 3:0
+ UINT8 tRCminUpper : 4; ///< Bits 7:4
+ } Bits;
+ UINT8 Data;
+} SPD3_TRAS_TRC_MIN_MTB_STRUCT;
+
+typedef union {
+ struct {
+ UINT8 tRASmin : 8; ///< Bits 7:0
+ } Bits;
+ UINT8 Data;
+} SPD3_TRAS_MIN_MTB_STRUCT;
+
+typedef union {
+ struct {
+ UINT8 tRCmin : 8; ///< Bits 7:0
+ } Bits;
+ UINT8 Data;
+} SPD3_TRC_MIN_MTB_STRUCT;
+
+typedef union {
+ struct {
+ UINT16 tRFCmin : 16; ///< Bits 15:0
+ } Bits;
+ UINT16 Data;
+ UINT8 Data8[2];
+} SPD3_TRFC_MIN_MTB_STRUCT;
+
+typedef union {
+ struct {
+ UINT8 tWTRmin : 8; ///< Bits 7:0
+ } Bits;
+ UINT8 Data;
+} SPD3_TWTR_MIN_MTB_STRUCT;
+
+typedef union {
+ struct {
+ UINT8 tRTPmin : 8; ///< Bits 7:0
+ } Bits;
+ UINT8 Data;
+} SPD3_TRTP_MIN_MTB_STRUCT;
+
+typedef union {
+ struct {
+ UINT8 tFAWminUpper : 4; ///< Bits 3:0
+ UINT8 Reserved : 4; ///< Bits 7:4
+ } Bits;
+ UINT8 Data;
+} SPD3_TFAW_MIN_MTB_UPPER_STRUCT;
+
+typedef union {
+ struct {
+ UINT8 tFAWmin : 8; ///< Bits 7:0
+ } Bits;
+ UINT8 Data;
+} SPD3_TFAW_MIN_MTB_STRUCT;
+
+typedef union {
+ struct {
+ UINT8 Rzq6 : 1; ///< Bits 0:0
+ UINT8 Rzq7 : 1; ///< Bits 1:1
+ UINT8 Reserved : 5; ///< Bits 6:2
+ UINT8 DllOff : 1; ///< Bits 7:7
+ } Bits;
+ UINT8 Data;
+} SPD3_SDRAM_OPTIONAL_FEATURES_STRUCT;
+
+typedef union {
+ struct {
+ UINT8 ExtendedTemperatureRange : 1; ///< Bits 0:0
+ UINT8 ExtendedTemperatureRefreshRate : 1; ///< Bits 1:1
+ UINT8 AutoSelfRefresh : 1; ///< Bits 2:2
+ UINT8 OnDieThermalSensor : 1; ///< Bits 3:3
+ UINT8 Reserved : 3; ///< Bits 6:4
+ UINT8 PartialArraySelfRefresh : 1; ///< Bits 7:7
+ } Bits;
+ UINT8 Data;
+} SPD3_SDRAM_THERMAL_REFRESH_STRUCT;
+
+typedef union {
+ struct {
+ UINT8 ThermalSensorAccuracy : 7; ///< Bits 6:0
+ UINT8 ThermalSensorPresence : 1; ///< Bits 7:7
+ } Bits;
+ UINT8 Data;
+} SPD3_MODULE_THERMAL_SENSOR_STRUCT;
+
+typedef union {
+ struct {
+ UINT8 SignalLoading : 2; ///< Bits 1:0
+ UINT8 Reserved : 2; ///< Bits 3:2
+ UINT8 DieCount : 3; ///< Bits 6:4
+ UINT8 SdramDeviceType : 1; ///< Bits 7:7
+ } Bits;
+ UINT8 Data;
+} SPD3_SDRAM_DEVICE_TYPE_STRUCT;
+
+typedef union {
+ struct {
+ INT8 tCKminFine : 8; ///< Bits 7:0
+ } Bits;
+ INT8 Data;
+} SPD3_TCK_MIN_FTB_STRUCT;
+
+typedef union {
+ struct {
+ INT8 tAAminFine : 8; ///< Bits 7:0
+ } Bits;
+ INT8 Data;
+} SPD3_TAA_MIN_FTB_STRUCT;
+
+typedef union {
+ struct {
+ INT8 tRCDminFine : 8; ///< Bits 7:0
+ } Bits;
+ INT8 Data;
+} SPD3_TRCD_MIN_FTB_STRUCT;
+
+typedef union {
+ struct {
+ INT8 tRPminFine : 8; ///< Bits 7:0
+ } Bits;
+ INT8 Data;
+} SPD3_TRP_MIN_FTB_STRUCT;
+
+typedef union {
+ struct {
+ INT8 tRCminFine : 8; ///< Bits 7:0
+ } Bits;
+ INT8 Data;
+} SPD3_TRC_MIN_FTB_STRUCT;
+
+typedef union {
+ struct {
+ UINT8 MaximumActivateCount : 4; ///< Bits 3:0
+ UINT8 MaximumActivateWindow : 2; ///< Bits 5:4
+ UINT8 VendorSpecific : 2; ///< Bits 7:6
+ } Bits;
+ UINT8 Data;
+} SPD3_MAXIMUM_ACTIVE_COUNT_STRUCT;
+
+typedef union {
+ struct {
+ UINT8 Height : 5; ///< Bits 4:0
+ UINT8 RawCardExtension : 3; ///< Bits 7:5
+ } Bits;
+ UINT8 Data;
+} SPD3_UNBUF_MODULE_NOMINAL_HEIGHT;
+
+typedef union {
+ struct {
+ UINT8 FrontThickness : 4; ///< Bits 3:0
+ UINT8 BackThickness : 4; ///< Bits 7:4
+ } Bits;
+ UINT8 Data;
+} SPD3_UNBUF_MODULE_NOMINAL_THICKNESS;
+
+typedef union {
+ struct {
+ UINT8 Card : 5; ///< Bits 4:0
+ UINT8 Revision : 2; ///< Bits 6:5
+ UINT8 Extension : 1; ///< Bits 7:7
+ } Bits;
+ UINT8 Data;
+} SPD3_UNBUF_REFERENCE_RAW_CARD;
+
+typedef union {
+ struct {
+ UINT8 MappingRank1 : 1; ///< Bits 0:0
+ UINT8 Reserved : 7; ///< Bits 7:1
+ } Bits;
+ UINT8 Data;
+} SPD3_UNBUF_ADDRESS_MAPPING;
+
+typedef union {
+ struct {
+ UINT8 Height : 5; ///< Bits 4:0
+ UINT8 Reserved : 3; ///< Bits 7:5
+ } Bits;
+ UINT8 Data;
+} SPD3_RDIMM_MODULE_NOMINAL_HEIGHT;
+
+typedef union {
+ struct {
+ UINT8 FrontThickness : 4; ///< Bits 3:0
+ UINT8 BackThickness : 4; ///< Bits 7:4
+ } Bits;
+ UINT8 Data;
+} SPD3_RDIMM_MODULE_NOMINAL_THICKNESS;
+
+typedef union {
+ struct {
+ UINT8 Card : 5; ///< Bits 4:0
+ UINT8 Revision : 2; ///< Bits 6:5
+ UINT8 Extension : 1; ///< Bits 7:7
+ } Bits;
+ UINT8 Data;
+} SPD3_RDIMM_REFERENCE_RAW_CARD;
+
+typedef union {
+ struct {
+ UINT8 RegisterCount : 2; ///< Bits 1:0
+ UINT8 DramRowCount : 2; ///< Bits 3:2
+ UINT8 RegisterType : 4; ///< Bits 7:4
+ } Bits;
+ UINT8 Data;
+} SPD3_RDIMM_MODULE_ATTRIBUTES;
+
+typedef union {
+ struct {
+ UINT8 HeatSpreaderThermalCharacteristics : 7; ///< Bits 6:0
+ UINT8 HeatSpreaderSolution : 1; ///< Bits 7:7
+ } Bits;
+ UINT8 Data;
+} SPD3_RDIMM_THERMAL_HEAT_SPREADER_SOLUTION;
+
+typedef union {
+ struct {
+ UINT16 ContinuationCount : 7; ///< Bits 6:0
+ UINT16 ContinuationParity : 1; ///< Bits 7:7
+ UINT16 LastNonZeroByte : 8; ///< Bits 15:8
+ } Bits;
+ UINT16 Data;
+ UINT8 Data8[2];
+} SPD3_MANUFACTURER_ID_CODE;
+
+typedef union {
+ struct {
+ UINT8 RegisterRevisionNumber; ///< Bits 7:0
+ } Bits;
+ UINT8 Data;
+} SPD3_RDIMM_REGISTER_REVISION_NUMBER;
+
+typedef union {
+ struct {
+ UINT8 Bit0 : 1; ///< Bits 0:0
+ UINT8 Bit1 : 1; ///< Bits 1:1
+ UINT8 Bit2 : 1; ///< Bits 2:2
+ UINT8 Reserved : 5; ///< Bits 7:3
+ } Bits;
+ UINT8 Data;
+} SPD3_RDIMM_REGISTER_TYPE;
+
+typedef union {
+ struct {
+ UINT8 Reserved : 4; ///< Bits 0:3
+ UINT8 CommandAddressAOutputs : 2; ///< Bits 5:4
+ UINT8 CommandAddressBOutputs : 2; ///< Bits 7:6
+ } Bits;
+ UINT8 Data;
+} SPD3_RDIMM_REGISTER_CONTROL_COMMAND_ADDRESS;
+
+typedef union {
+ struct {
+ UINT8 ControlSignalsAOutputs : 2; ///< Bits 0:1
+ UINT8 ControlSignalsBOutputs : 2; ///< Bits 3:2
+ UINT8 Y1Y3ClockOutputs : 2; ///< Bits 5:4
+ UINT8 Y0Y2ClockOutputs : 2; ///< Bits 7:6
+ } Bits;
+ UINT8 Data;
+} SPD3_RDIMM_REGISTER_CONTROL_CONTROL_CLOCK;
+
+typedef union {
+ struct {
+ UINT8 Reserved0 : 4; ///< Bits 0:3
+ UINT8 Reserved1 : 4; ///< Bits 7:4
+ } Bits;
+ UINT8 Data;
+} SPD3_RDIMM_REGISTER_CONTROL_RESERVED;
+
+typedef union {
+ struct {
+ UINT8 Height : 5; ///< Bits 4:0
+ UINT8 Reserved : 3; ///< Bits 7:5
+ } Bits;
+ UINT8 Data;
+} SPD3_LRDIMM_MODULE_NOMINAL_HEIGHT;
+
+typedef union {
+ struct {
+ UINT8 FrontThickness : 4; ///< Bits 3:0
+ UINT8 BackThickness : 4; ///< Bits 7:4
+ } Bits;
+ UINT8 Data;
+} SPD3_LRDIMM_MODULE_NOMINAL_THICKNESS;
+
+typedef union {
+ struct {
+ UINT8 Card : 5; ///< Bits 4:0
+ UINT8 Revision : 2; ///< Bits 6:5
+ UINT8 Extension : 1; ///< Bits 7:7
+ } Bits;
+ UINT8 Data;
+} SPD3_LRDIMM_REFERENCE_RAW_CARD;
+
+typedef union {
+ struct {
+ UINT8 RegisterCount : 2; ///< Bits 1:0
+ UINT8 DramRowCount : 2; ///< Bits 3:2
+ UINT8 RegisterType : 4; ///< Bits 7:4
+ } Bits;
+ UINT8 Data;
+} SPD3_LRDIMM_MODULE_ATTRIBUTES;
+
+typedef union {
+ struct {
+ UINT8 AddressCommandPrelaunch : 1; ///< Bits 0:0
+ UINT8 Rank1Rank5Swap : 1; ///< Bits 1:1
+ UINT8 Reserved0 : 1; ///< Bits 2:2
+ UINT8 Reserved1 : 1; ///< Bits 3:3
+ UINT8 AddressCommandOutputs : 2; ///< Bits 5:4
+ UINT8 QxCS_nOutputs : 2; ///< Bits 7:6
+ } Bits;
+ UINT8 Data;
+} SPD3_LRDIMM_TIMING_CONTROL_DRIVE_STRENGTH;
+
+typedef union {
+ struct {
+ UINT8 QxOdtOutputs : 2; ///< Bits 1:0
+ UINT8 QxCkeOutputs : 2; ///< Bits 3:2
+ UINT8 Y1Y3ClockOutputs : 2; ///< Bits 5:4
+ UINT8 Y0Y2ClockOutputs : 2; ///< Bits 7:6
+ } Bits;
+ UINT8 Data;
+} SPD3_LRDIMM_TIMING_DRIVE_STRENGTH;
+
+typedef union {
+ struct {
+ UINT8 YExtendedDelay : 2; ///< Bits 1:0
+ UINT8 QxCS_n : 2; ///< Bits 3:2
+ UINT8 QxOdt : 2; ///< Bits 5:4
+ UINT8 QxCke : 2; ///< Bits 7:6
+ } Bits;
+ UINT8 Data;
+} SPD3_LRDIMM_EXTENDED_DELAY;
+
+typedef union {
+ struct {
+ UINT8 DelayY : 3; ///< Bits 2:0
+ UINT8 Reserved : 1; ///< Bits 3:3
+ UINT8 QxCS_n : 4; ///< Bits 7:4
+ } Bits;
+ UINT8 Data;
+} SPD3_LRDIMM_ADDITIVE_DELAY_FOR_QXCS_N_QXCA;
+
+typedef union {
+ struct {
+ UINT8 QxCS_n : 4; ///< Bits 3:0
+ UINT8 QxOdt : 4; ///< Bits 7:4
+ } Bits;
+ UINT8 Data;
+} SPD3_LRDIMM_ADDITIVE_DELAY_FOR_QXODT_QXCKE;
+
+typedef union {
+ struct {
+ UINT8 RC8MdqOdtStrength : 3; ///< Bits 2:0
+ UINT8 RC8Reserved : 1; ///< Bits 3:3
+ UINT8 RC9MdqOdtStrength : 3; ///< Bits 6:4
+ UINT8 RC9Reserved : 1; ///< Bits 7:7
+ } Bits;
+ UINT8 Data;
+} SPD3_LRDIMM_MDQ_TERMINATION_DRIVE_STRENGTH;
+
+typedef union {
+ struct {
+ UINT8 RC10DA3ValueR0 : 1; ///< Bits 0:0
+ UINT8 RC10DA4ValueR0 : 1; ///< Bits 1:1
+ UINT8 RC10DA3ValueR1 : 1; ///< Bits 2:2
+ UINT8 RC10DA4ValueR1 : 1; ///< Bits 3:3
+ UINT8 RC11DA3ValueR0 : 1; ///< Bits 4:4
+ UINT8 RC11DA4ValueR0 : 1; ///< Bits 5:5
+ UINT8 RC11DA3ValueR1 : 1; ///< Bits 6:6
+ UINT8 RC11DA4ValueR1 : 1; ///< Bits 7:7
+ } Bits;
+ UINT8 Data;
+} SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL;
+
+typedef union {
+ struct {
+ UINT8 Driver_Impedance : 2; ///< Bits 1:0
+ UINT8 Rtt_Nom : 3; ///< Bits 4:2
+ UINT8 Reserved : 1; ///< Bits 5:5
+ UINT8 Rtt_WR : 2; ///< Bits 7:6
+ } Bits;
+ UINT8 Data;
+} SPD3_LRDIMM_MR_1_2;
+
+typedef union {
+ struct {
+ UINT8 MinimumDelayTime : 7; ///< Bits 0:6
+ UINT8 Reserved : 1; ///< Bits 7:7
+ } Bits;
+ UINT8 Data;
+} SPD3_LRDIMM_MODULE_DELAY_TIME;
+
+typedef struct {
+ UINT8 Year; ///< Year represented in BCD (00h = 2000)
+ UINT8 Week; ///< Year represented in BCD (47h = week 47)
+} SPD3_MANUFACTURING_DATE;
+
+typedef union {
+ UINT32 Data;
+ UINT16 SerialNumber16[2];
+ UINT8 SerialNumber8[4];
+} SPD3_MANUFACTURER_SERIAL_NUMBER;
+
+typedef struct {
+ UINT8 Location; ///< Module Manufacturing Location
+} SPD3_MANUFACTURING_LOCATION;
+
+typedef struct {
+ SPD3_MANUFACTURER_ID_CODE IdCode; ///< Module Manufacturer ID Code
+ SPD3_MANUFACTURING_LOCATION Location; ///< Module Manufacturing Location
+ SPD3_MANUFACTURING_DATE Date; ///< Module Manufacturing Year, in BCD (range: 2000-2255)
+ SPD3_MANUFACTURER_SERIAL_NUMBER SerialNumber; ///< Module Serial Number
+} SPD3_UNIQUE_MODULE_ID;
+
+typedef union {
+ UINT16 Crc[1];
+ UINT8 Data8[2];
+} SPD3_CYCLIC_REDUNDANCY_CODE;
+
+typedef struct {
+ SPD3_DEVICE_DESCRIPTION_STRUCT Description; ///< 0 Number of Serial PD Bytes Written / SPD Device Size / CRC Coverage 1, 2
+ SPD3_REVISION_STRUCT Revision; ///< 1 SPD Revision
+ SPD3_DRAM_DEVICE_TYPE_STRUCT DramDeviceType; ///< 2 DRAM Device Type
+ SPD3_MODULE_TYPE_STRUCT ModuleType; ///< 3 Module Type
+ SPD3_SDRAM_DENSITY_BANKS_STRUCT SdramDensityAndBanks; ///< 4 SDRAM Density and Banks
+ SPD3_SDRAM_ADDRESSING_STRUCT SdramAddressing; ///< 5 SDRAM Addressing
+ SPD3_MODULE_NOMINAL_VOLTAGE_STRUCT ModuleNominalVoltage; ///< 6 Module Nominal Voltage, VDD
+ SPD3_MODULE_ORGANIZATION_STRUCT ModuleOrganization; ///< 7 Module Organization
+ SPD3_MODULE_MEMORY_BUS_WIDTH_STRUCT ModuleMemoryBusWidth; ///< 8 Module Memory Bus Width
+ SPD3_FINE_TIMEBASE_STRUCT FineTimebase; ///< 9 Fine Timebase (FTB) Dividend / Divisor
+ SPD3_MEDIUM_TIMEBASE MediumTimebase; ///< 10-11 Medium Timebase (MTB) Dividend
+ SPD3_TCK_MIN_MTB_STRUCT tCKmin; ///< 12 SDRAM Minimum Cycle Time (tCKmin)
+ UINT8 Reserved0; ///< 13 Reserved
+ SPD3_CAS_LATENCIES_SUPPORTED_STRUCT CasLatencies; ///< 14-15 CAS Latencies Supported
+ SPD3_TAA_MIN_MTB_STRUCT tAAmin; ///< 16 Minimum CAS Latency Time (tAAmin)
+ SPD3_TWR_MIN_MTB_STRUCT tWRmin; ///< 17 Minimum Write Recovery Time (tWRmin)
+ SPD3_TRCD_MIN_MTB_STRUCT tRCDmin; ///< 18 Minimum RAS# to CAS# Delay Time (tRCDmin)
+ SPD3_TRRD_MIN_MTB_STRUCT tRRDmin; ///< 19 Minimum Row Active to Row Active Delay Time (tRRDmin)
+ SPD3_TRP_MIN_MTB_STRUCT tRPmin; ///< 20 Minimum Row Precharge Delay Time (tRPmin)
+ SPD3_TRAS_TRC_MIN_MTB_STRUCT tRASMintRCMinUpper; ///< 21 Upper Nibbles for tRAS and tRC
+ SPD3_TRAS_MIN_MTB_STRUCT tRASmin; ///< 22 Minimum Active to Precharge Delay Time (tRASmin), Least Significant Byte
+ SPD3_TRC_MIN_MTB_STRUCT tRCmin; ///< 23 Minimum Active to Active/Refresh Delay Time (tRCmin), Least Significant Byte
+ SPD3_TRFC_MIN_MTB_STRUCT tRFCmin; ///< 24-25 Minimum Refresh Recovery Delay Time (tRFCmin)
+ SPD3_TWTR_MIN_MTB_STRUCT tWTRmin; ///< 26 Minimum Internal Write to Read Command Delay Time (tWTRmin)
+ SPD3_TRTP_MIN_MTB_STRUCT tRTPmin; ///< 27 Minimum Internal Read to Precharge Command Delay Time (tRTPmin)
+ SPD3_TFAW_MIN_MTB_UPPER_STRUCT tFAWMinUpper; ///< 28 Upper Nibble for tFAW
+ SPD3_TFAW_MIN_MTB_STRUCT tFAWmin; ///< 29 Minimum Four Activate Window Delay Time (tFAWmin)
+ SPD3_SDRAM_OPTIONAL_FEATURES_STRUCT SdramOptionalFeatures; ///< 30 SDRAM Optional Features
+ SPD3_SDRAM_THERMAL_REFRESH_STRUCT ThermalAndRefreshOptions; ///< 31 SDRAM Thermal And Refresh Options
+ SPD3_MODULE_THERMAL_SENSOR_STRUCT ModuleThermalSensor; ///< 32 Module Thermal Sensor
+ SPD3_SDRAM_DEVICE_TYPE_STRUCT SdramDeviceType; ///< 33 SDRAM Device Type
+ SPD3_TCK_MIN_FTB_STRUCT tCKminFine; ///< 34 Fine Offset for SDRAM Minimum Cycle Time (tCKmin)
+ SPD3_TAA_MIN_FTB_STRUCT tAAminFine; ///< 35 Fine Offset for Minimum CAS Latency Time (tAAmin)
+ SPD3_TRCD_MIN_FTB_STRUCT tRCDminFine; ///< 36 Fine Offset for Minimum RAS# to CAS# Delay Time (tRCDmin)
+ SPD3_TRP_MIN_FTB_STRUCT tRPminFine; ///< 37 Minimum Row Precharge Delay Time (tRPmin)
+ SPD3_TRC_MIN_FTB_STRUCT tRCminFine; ///< 38 Fine Offset for Minimum Active to Active/Refresh Delay Time (tRCmin)
+ UINT8 Reserved1[40 - 39 + 1]; ///< 39 - 40 Reserved
+ SPD3_MAXIMUM_ACTIVE_COUNT_STRUCT MacValue; ///< 41 SDRAM Maximum Active Count (MAC) Value
+ UINT8 Reserved2[59 - 42 + 1]; ///< 42 - 59 Reserved
+} SPD3_BASE_SECTION;
+
+typedef struct {
+ SPD3_UNBUF_MODULE_NOMINAL_HEIGHT ModuleNominalHeight; ///< 60 Module Nominal Height
+ SPD3_UNBUF_MODULE_NOMINAL_THICKNESS ModuleMaximumThickness; ///< 61 Module Maximum Thickness
+ SPD3_UNBUF_REFERENCE_RAW_CARD ReferenceRawCardUsed; ///< 62 Reference Raw Card Used
+ SPD3_UNBUF_ADDRESS_MAPPING AddressMappingEdgeConn; ///< 63 Address Mapping from Edge Connector to DRAM
+ UINT8 Reserved[116 - 64 + 1]; ///< 64-116 Reserved
+} SPD3_MODULE_UNBUFFERED;
+
+typedef struct {
+ SPD3_RDIMM_MODULE_NOMINAL_HEIGHT ModuleNominalHeight; ///< 60 Module Nominal Height
+ SPD3_RDIMM_MODULE_NOMINAL_THICKNESS ModuleMaximumThickness; ///< 61 Module Maximum Thickness
+ SPD3_RDIMM_REFERENCE_RAW_CARD ReferenceRawCardUsed; ///< 62 Reference Raw Card Used
+ SPD3_RDIMM_MODULE_ATTRIBUTES DimmModuleAttributes; ///< 63 DIMM Module Attributes
+ SPD3_RDIMM_THERMAL_HEAT_SPREADER_SOLUTION ThermalHeatSpreaderSolution; ///< 64 RDIMM Thermal Heat Spreader Solution
+ SPD3_MANUFACTURER_ID_CODE RegisterManufacturerIdCode; ///< 65-66 Register Manufacturer ID Code
+ SPD3_RDIMM_REGISTER_REVISION_NUMBER RegisterRevisionNumber; ///< 67 Register Revision Number
+ SPD3_RDIMM_REGISTER_TYPE RegisterType; ///< 68 Register Type
+ SPD3_RDIMM_REGISTER_CONTROL_RESERVED Rc1Rc0; ///< 69 RC1 (MS Nibble) / RC0 (LS Nibble) - Reserved
+ SPD3_RDIMM_REGISTER_CONTROL_COMMAND_ADDRESS Rc3Rc2; ///< 70 RC3 (MS Nibble) / RC2 (LS Nibble) - Drive Strength, Command/Address
+ SPD3_RDIMM_REGISTER_CONTROL_CONTROL_CLOCK Rc5Rc4; ///< 71 RC5 (MS Nibble) / RC4 (LS Nibble) - Drive Strength, Control and Clock
+ SPD3_RDIMM_REGISTER_CONTROL_RESERVED Rc7Rc6; ///< 72 RC7 (MS Nibble) / RC6 (LS Nibble) - Reserved for Register Vendor
+ SPD3_RDIMM_REGISTER_CONTROL_RESERVED Rc9Rc8; ///< 73 RC9 (MS Nibble) / RC8 (LS Nibble) - Reserved
+ SPD3_RDIMM_REGISTER_CONTROL_RESERVED Rc11Rc10; ///< 74 RC11 (MS Nibble) / RC10 (LS Nibble) - Reserved
+ SPD3_RDIMM_REGISTER_CONTROL_RESERVED Rc13Rc12; ///< 75 RC12 (MS Nibble) / RC12 (LS Nibble) - Reserved
+ SPD3_RDIMM_REGISTER_CONTROL_RESERVED Rc15Rc14; ///< 76 RC15 (MS Nibble) / RC14 (LS Nibble) - Reserved
+ UINT8 Reserved[116 - 77 + 1]; ///< 77-116 Reserved
+} SPD3_MODULE_REGISTERED;
+
+typedef struct {
+ SPD3_UNBUF_MODULE_NOMINAL_HEIGHT ModuleNominalHeight; ///< 60 Module Nominal Height
+ SPD3_UNBUF_MODULE_NOMINAL_THICKNESS ModuleMaximumThickness; ///< 61 Module Maximum Thickness
+ SPD3_UNBUF_REFERENCE_RAW_CARD ReferenceRawCardUsed; ///< 62 Reference Raw Card Used
+ UINT8 Reserved[116 - 63 + 1]; ///< 63-116 Reserved
+} SPD3_MODULE_CLOCKED;
+
+typedef struct {
+ SPD3_LRDIMM_MODULE_NOMINAL_HEIGHT ModuleNominalHeight; ///< 60 Module Nominal Height
+ SPD3_LRDIMM_MODULE_NOMINAL_THICKNESS ModuleMaximumThickness; ///< 61 Module Maximum Thickness
+ SPD3_LRDIMM_REFERENCE_RAW_CARD ReferenceRawCardUsed; ///< 62 Reference Raw Card Used
+ SPD3_LRDIMM_MODULE_ATTRIBUTES DimmModuleAttributes; ///< 63 Module Attributes
+ UINT8 MemoryBufferRevisionNumber; ///< 64 Memory Buffer Revision Number
+ SPD3_MANUFACTURER_ID_CODE ManufacturerIdCode; ///< 65-66 Memory Buffer Manufacturer ID Code
+ SPD3_LRDIMM_TIMING_CONTROL_DRIVE_STRENGTH TimingControlDriveStrengthCaCs; ///< 67 F0RC3 / F0RC2 - Timing Control & Drive Strength, CA & CS
+ SPD3_LRDIMM_TIMING_DRIVE_STRENGTH DriveStrength; ///< 68 F0RC5 / F0RC4 - Drive Strength, ODT & CKE and Y
+ SPD3_LRDIMM_EXTENDED_DELAY ExtendedDelay; ///< 69 F1RC11 / F1RC8 - Extended Delay for Y, CS and ODT & CKE
+ SPD3_LRDIMM_ADDITIVE_DELAY_FOR_QXCS_N_QXCA AdditiveDelayForCsCa; ///< 70 F1RC13 / F1RC12 - Additive Delay for CS and CA
+ SPD3_LRDIMM_ADDITIVE_DELAY_FOR_QXODT_QXCKE AdditiveDelayForOdtCke; ///< 71 F1RC15 / F1RC14 - Additive Delay for ODT & CKE
+ SPD3_LRDIMM_MDQ_TERMINATION_DRIVE_STRENGTH MdqTerminationDriveStrengthFor800_1066; ///< 72 F1RC15 / F1RC14 - Additive Delay for ODT & CKE
+ SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL Rank_0_1QxOdtControlFor800_1066; ///< 73 F[3,4]RC11 / F[3,4]RC10 - Rank 0 & 1 RD & WR QxODT Control for 800 & 1066
+ SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL Rank_2_3QxOdtControlFor800_1066; ///< 74 F[5,6]RC11 / F[5,6]RC10 - Rank 2 & 3 RD & WR QxODT Control for 800 & 1066
+ SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL Rank_4_5QxOdtControlFor800_1066; ///< 75 F[7,8]RC11 / F[7,8]RC10 - Rank 4 & 5 RD & WR QxODT Control for 800 & 1066
+ SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL Rank_6_7QxOdtControlFor800_1066; ///< 76 F[9,10]RC11 / F[9,10]RC10 - Rank 6 & 7 RD & WR QxODT Control for 800 & 1066
+ SPD3_LRDIMM_MR_1_2 MR_1_2RegistersFor800_1066; ///< 77 MR1,2 Registers for 800 & 1066
+ SPD3_LRDIMM_MDQ_TERMINATION_DRIVE_STRENGTH MdqTerminationDriveStrengthFor1333_1600; ///< 78 F1RC15 / F1RC14 - Additive Delay for ODT & CKE
+ SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL Rank_0_1QxOdtControlFor1333_1600; ///< 79 F[3,4]RC11 / F[3,4]RC10 - Rank 0 & 1 RD & WR QxODT Control for 800 & 1066
+ SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL Rank_2_3QxOdtControlFor1333_1600; ///< 80 F[5,6]RC11 / F[5,6]RC10 - Rank 2 & 3 RD & WR QxODT Control for 800 & 1066
+ SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL Rank_4_5QxOdtControlFor1333_1600; ///< 81 F[7,8]RC11 / F[7,8]RC10 - Rank 4 & 5 RD & WR QxODT Control for 800 & 1066
+ SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL Rank_6_7QxOdtControlFor1333_1600; ///< 82 F[9,10]RC11 / F[9,10]RC10 - Rank 6 & 7 RD & WR QxODT Control for 800 & 1066
+ SPD3_LRDIMM_MR_1_2 MR_1_2RegistersFor1333_1600; ///< 83 MR1,2 Registers for 800 & 1066
+ SPD3_LRDIMM_MDQ_TERMINATION_DRIVE_STRENGTH MdqTerminationDriveStrengthFor1866_2133; ///< 84 F1RC15 / F1RC14 - Additive Delay for ODT & CKE
+ SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL Rank_0_1QxOdtControlFor1866_2133; ///< 85 F[3,4]RC11 / F[3,4]RC10 - Rank 0 & 1 RD & WR QxODT Control for 800 & 1066
+ SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL Rank_2_3QxOdtControlFor1866_2133; ///< 86 F[5,6]RC11 / F[5,6]RC10 - Rank 2 & 3 RD & WR QxODT Control for 800 & 1066
+ SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL Rank_4_5QxOdtControlFor1866_2133; ///< 87 F[7,8]RC11 / F[7,8]RC10 - Rank 4 & 5 RD & WR QxODT Control for 800 & 1066
+ SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL Rank_6_7QxOdtControlFor1866_2133; ///< 88 F[9,10]RC11 / F[9,10]RC10 - Rank 6 & 7 RD & WR QxODT Control for 800 & 1066
+ SPD3_LRDIMM_MR_1_2 MR_1_2RegistersFor1866_2133; ///< 89 MR1,2 Registers for 800 & 1066
+ SPD3_LRDIMM_MODULE_DELAY_TIME MinimumModuleDelayTimeFor1_5V; ///< 90 Minimum Module Delay Time for 1.5 V
+ SPD3_LRDIMM_MODULE_DELAY_TIME MaximumModuleDelayTimeFor1_5V; ///< 91 Maximum Module Delay Time for 1.5 V
+ SPD3_LRDIMM_MODULE_DELAY_TIME MinimumModuleDelayTimeFor1_35V; ///< 92 Minimum Module Delay Time for 1.35 V
+ SPD3_LRDIMM_MODULE_DELAY_TIME MaximumModuleDelayTimeFor1_35V; ///< 93 Maximum Module Delay Time for 1.35 V
+ SPD3_LRDIMM_MODULE_DELAY_TIME MinimumModuleDelayTimeFor1_25V; ///< 94 Minimum Module Delay Time for 1.25 V
+ SPD3_LRDIMM_MODULE_DELAY_TIME MaximumModuleDelayTimeFor1_25V; ///< 95 Maximum Module Delay Time for 1.25 V
+ UINT8 Reserved[101 - 96 + 1]; ///< 96-101 Reserved
+ UINT8 PersonalityByte[116 - 102 + 1]; ///< 102-116 Memory Buffer Personality Bytes
+} SPD3_MODULE_LOADREDUCED;
+
+typedef union {
+ SPD3_MODULE_UNBUFFERED Unbuffered; ///< 128-255 Unbuffered Memory Module Types
+ SPD3_MODULE_REGISTERED Registered; ///< 128-255 Registered Memory Module Types
+ SPD3_MODULE_CLOCKED Clocked; ///< 128-255 Registered Memory Module Types
+ SPD3_MODULE_LOADREDUCED LoadReduced; ///< 128-255 Load Reduced Memory Module Types
+} SPD3_MODULE_SPECIFIC;
+
+typedef struct {
+ UINT8 ModulePartNumber[145 - 128 + 1]; ///< 128-145 Module Part Number
+} SPD3_MODULE_PART_NUMBER;
+
+typedef struct {
+ UINT8 ModuleRevisionCode[147 - 146 + 1]; ///< 146-147 Module Revision Code
+} SPD3_MODULE_REVISION_CODE;
+
+typedef struct {
+ UINT8 ManufacturerSpecificData[175 - 150 + 1]; ///< 150-175 Manufacturer's Specific Data
+} SPD3_MANUFACTURER_SPECIFIC;
+
+///
+/// DDR3 Serial Presence Detect structure
+///
+typedef struct {
+ SPD3_BASE_SECTION General; ///< 0-59 General Section
+ SPD3_MODULE_SPECIFIC Module; ///< 60-116 Module-Specific Section
+ SPD3_UNIQUE_MODULE_ID ModuleId; ///< 117-125 Unique Module ID
+ SPD3_CYCLIC_REDUNDANCY_CODE Crc; ///< 126-127 Cyclical Redundancy Code (CRC)
+ SPD3_MODULE_PART_NUMBER ModulePartNumber; ///< 128-145 Module Part Number
+ SPD3_MODULE_REVISION_CODE ModuleRevisionCode; ///< 146-147 Module Revision Code
+ SPD3_MANUFACTURER_ID_CODE DramIdCode; ///< 148-149 Dram Manufacturer ID Code
+ SPD3_MANUFACTURER_SPECIFIC ManufacturerSpecificData; ///< 150-175 Manufacturer's Specific Data
+ UINT8 Reserved[255 - 176 + 1]; ///< 176-255 Open for Customer Use
+} SPD_DDR3;
+
+#pragma pack (pop)
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/SdramSpdDdr4.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/SdramSpdDdr4.h
new file mode 100644
index 0000000000..33b6950bdd
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/SdramSpdDdr4.h
@@ -0,0 +1,952 @@
+/** @file
+ This file contains definitions for SPD DDR4.
+
+ Copyright (c) 2016, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Revision Reference:
+ - Serial Presence Detect (SPD) for DDR4 SDRAM Modules Document Release 4
+ http://www.jedec.org/standards-documents/docs/spd412l-4
+**/
+
+#ifndef _SDRAM_SPD_DDR4_H_
+#define _SDRAM_SPD_DDR4_H_
+
+#pragma pack (push, 1)
+
+typedef union {
+ struct {
+ UINT8 BytesUsed : 4; ///< Bits 3:0
+ UINT8 BytesTotal : 3; ///< Bits 6:4
+ UINT8 CrcCoverage : 1; ///< Bits 7:7
+ } Bits;
+ UINT8 Data;
+} SPD4_DEVICE_DESCRIPTION_STRUCT;
+
+typedef union {
+ struct {
+ UINT8 Minor : 4; ///< Bits 3:0
+ UINT8 Major : 4; ///< Bits 7:4
+ } Bits;
+ UINT8 Data;
+} SPD4_REVISION_STRUCT;
+
+typedef union {
+ struct {
+ UINT8 Type : 8; ///< Bits 7:0
+ } Bits;
+ UINT8 Data;
+} SPD4_DRAM_DEVICE_TYPE_STRUCT;
+
+typedef union {
+ struct {
+ UINT8 ModuleType : 4; ///< Bits 3:0
+ UINT8 HybridMedia : 3; ///< Bits 6:4
+ UINT8 Hybrid : 1; ///< Bits 7:7
+ } Bits;
+ UINT8 Data;
+} SPD4_MODULE_TYPE_STRUCT;
+
+typedef union {
+ struct {
+ UINT8 Density : 4; ///< Bits 3:0
+ UINT8 BankAddress : 2; ///< Bits 5:4
+ UINT8 BankGroup : 2; ///< Bits 7:6
+ } Bits;
+ UINT8 Data;
+} SPD4_SDRAM_DENSITY_BANKS_STRUCT;
+
+typedef union {
+ struct {
+ UINT8 ColumnAddress : 3; ///< Bits 2:0
+ UINT8 RowAddress : 3; ///< Bits 5:3
+ UINT8 Reserved : 2; ///< Bits 7:6
+ } Bits;
+ UINT8 Data;
+} SPD4_SDRAM_ADDRESSING_STRUCT;
+
+typedef union {
+ struct {
+ UINT8 SignalLoading : 2; ///< Bits 1:0
+ UINT8 Reserved : 2; ///< Bits 3:2
+ UINT8 DieCount : 3; ///< Bits 6:4
+ UINT8 SdramPackageType : 1; ///< Bits 7:7
+ } Bits;
+ UINT8 Data;
+} SPD4_PRIMARY_SDRAM_PACKAGE_TYPE_STRUCT;
+
+typedef union {
+ struct {
+ UINT8 MaximumActivateCount : 4; ///< Bits 3:0
+ UINT8 MaximumActivateWindow : 2; ///< Bits 5:4
+ UINT8 Reserved : 2; ///< Bits 7:6
+ } Bits;
+ UINT8 Data;
+} SPD4_SDRAM_OPTIONAL_FEATURES_STRUCT;
+
+typedef union {
+ struct {
+ UINT8 Reserved : 8; ///< Bits 7:0
+ } Bits;
+ UINT8 Data;
+} SPD4_SDRAM_THERMAL_REFRESH_STRUCT;
+
+typedef union {
+ struct {
+ UINT8 Reserved : 5; ///< Bits 4:0
+ UINT8 SoftPPR : 1; ///< Bits 5:5
+ UINT8 PostPackageRepair : 2; ///< Bits 7:6
+ } Bits;
+ UINT8 Data;
+} SPD4_OTHER_SDRAM_OPTIONAL_FEATURES_STRUCT;
+
+typedef union {
+ struct {
+ UINT8 SignalLoading : 2; ///< Bits 1:0
+ UINT8 DRAMDensityRatio : 2; ///< Bits 3:2
+ UINT8 DieCount : 3; ///< Bits 6:4
+ UINT8 SdramPackageType : 1; ///< Bits 7:7
+ } Bits;
+ UINT8 Data;
+} SPD4_SECONDARY_SDRAM_PACKAGE_TYPE_STRUCT;
+
+typedef union {
+ struct {
+ UINT8 OperationAt1_20 : 1; ///< Bits 0:0
+ UINT8 EndurantAt1_20 : 1; ///< Bits 1:1
+ UINT8 Reserved : 6; ///< Bits 7:2
+ } Bits;
+ UINT8 Data;
+} SPD4_MODULE_NOMINAL_VOLTAGE_STRUCT;
+
+typedef union {
+ struct {
+ UINT8 SdramDeviceWidth : 3; ///< Bits 2:0
+ UINT8 RankCount : 3; ///< Bits 5:3
+ UINT8 RankMix : 1; ///< Bits 6:6
+ UINT8 Reserved : 1; ///< Bits 7:7
+ } Bits;
+ UINT8 Data;
+} SPD4_MODULE_ORGANIZATION_STRUCT;
+
+typedef union {
+ struct {
+ UINT8 PrimaryBusWidth : 3; ///< Bits 2:0
+ UINT8 BusWidthExtension : 2; ///< Bits 4:3
+ UINT8 Reserved : 3; ///< Bits 7:5
+ } Bits;
+ UINT8 Data;
+} SPD4_MODULE_MEMORY_BUS_WIDTH_STRUCT;
+
+typedef union {
+ struct {
+ UINT8 Reserved : 7; ///< Bits 6:0
+ UINT8 ThermalSensorPresence : 1; ///< Bits 7:7
+ } Bits;
+ UINT8 Data;
+} SPD4_MODULE_THERMAL_SENSOR_STRUCT;
+
+typedef union {
+ struct {
+ UINT8 ExtendedBaseModuleType : 4; ///< Bits 3:0
+ UINT8 Reserved : 4; ///< Bits 7:4
+ } Bits;
+ UINT8 Data;
+} SPD4_EXTENDED_MODULE_TYPE_STRUCT;
+
+typedef union {
+ struct {
+ UINT8 Fine : 2; ///< Bits 1:0
+ UINT8 Medium : 2; ///< Bits 3:2
+ UINT8 Reserved : 4; ///< Bits 7:4
+ } Bits;
+ UINT8 Data;
+} SPD4_TIMEBASE_STRUCT;
+
+typedef union {
+ struct {
+ UINT8 tCKmin : 8; ///< Bits 7:0
+ } Bits;
+ UINT8 Data;
+} SPD4_TCK_MIN_MTB_STRUCT;
+
+typedef union {
+ struct {
+ UINT8 tCKmax : 8; ///< Bits 7:0
+ } Bits;
+ UINT8 Data;
+} SPD4_TCK_MAX_MTB_STRUCT;
+
+typedef union {
+ struct {
+ UINT32 Cl7 : 1; ///< Bits 0:0
+ UINT32 Cl8 : 1; ///< Bits 1:1
+ UINT32 Cl9 : 1; ///< Bits 2:2
+ UINT32 Cl10 : 1; ///< Bits 3:3
+ UINT32 Cl11 : 1; ///< Bits 4:4
+ UINT32 Cl12 : 1; ///< Bits 5:5
+ UINT32 Cl13 : 1; ///< Bits 6:6
+ UINT32 Cl14 : 1; ///< Bits 7:7
+ UINT32 Cl15 : 1; ///< Bits 8:8
+ UINT32 Cl16 : 1; ///< Bits 9:9
+ UINT32 Cl17 : 1; ///< Bits 10:10
+ UINT32 Cl18 : 1; ///< Bits 11:11
+ UINT32 Cl19 : 1; ///< Bits 12:12
+ UINT32 Cl20 : 1; ///< Bits 13:13
+ UINT32 Cl21 : 1; ///< Bits 14:14
+ UINT32 Cl22 : 1; ///< Bits 15:15
+ UINT32 Cl23 : 1; ///< Bits 16:16
+ UINT32 Cl24 : 1; ///< Bits 17:17
+ UINT32 Cl25 : 1; ///< Bits 18:18
+ UINT32 Cl26 : 1; ///< Bits 19:19
+ UINT32 Cl27 : 1; ///< Bits 20:20
+ UINT32 Cl28 : 1; ///< Bits 21:21
+ UINT32 Cl29 : 1; ///< Bits 22:22
+ UINT32 Cl30 : 1; ///< Bits 23:23
+ UINT32 Cl31 : 1; ///< Bits 24:24
+ UINT32 Cl32 : 1; ///< Bits 25:25
+ UINT32 Cl33 : 1; ///< Bits 26:26
+ UINT32 Cl34 : 1; ///< Bits 27:27
+ UINT32 Cl35 : 1; ///< Bits 28:28
+ UINT32 Cl36 : 1; ///< Bits 29:29
+ UINT32 Reserved : 1; ///< Bits 30:30
+ UINT32 ClRange : 1; ///< Bits 31:31
+ } Bits;
+ struct {
+ UINT32 Cl23 : 1; ///< Bits 0:0
+ UINT32 Cl24 : 1; ///< Bits 1:1
+ UINT32 Cl25 : 1; ///< Bits 2:2
+ UINT32 Cl26 : 1; ///< Bits 3:3
+ UINT32 Cl27 : 1; ///< Bits 4:4
+ UINT32 Cl28 : 1; ///< Bits 5:5
+ UINT32 Cl29 : 1; ///< Bits 6:6
+ UINT32 Cl30 : 1; ///< Bits 7:7
+ UINT32 Cl31 : 1; ///< Bits 8:8
+ UINT32 Cl32 : 1; ///< Bits 9:9
+ UINT32 Cl33 : 1; ///< Bits 10:10
+ UINT32 Cl34 : 1; ///< Bits 11:11
+ UINT32 Cl35 : 1; ///< Bits 12:12
+ UINT32 Cl36 : 1; ///< Bits 13:13
+ UINT32 Cl37 : 1; ///< Bits 14:14
+ UINT32 Cl38 : 1; ///< Bits 15:15
+ UINT32 Cl39 : 1; ///< Bits 16:16
+ UINT32 Cl40 : 1; ///< Bits 17:17
+ UINT32 Cl41 : 1; ///< Bits 18:18
+ UINT32 Cl42 : 1; ///< Bits 19:19
+ UINT32 Cl43 : 1; ///< Bits 20:20
+ UINT32 Cl44 : 1; ///< Bits 21:21
+ UINT32 Cl45 : 1; ///< Bits 22:22
+ UINT32 Cl46 : 1; ///< Bits 23:23
+ UINT32 Cl47 : 1; ///< Bits 24:24
+ UINT32 Cl48 : 1; ///< Bits 25:25
+ UINT32 Cl49 : 1; ///< Bits 26:26
+ UINT32 Cl50 : 1; ///< Bits 27:27
+ UINT32 Cl51 : 1; ///< Bits 28:28
+ UINT32 Cl52 : 1; ///< Bits 29:29
+ UINT32 Reserved : 1; ///< Bits 30:30
+ UINT32 ClRange : 1; ///< Bits 31:31
+ } HighRangeBits;
+ UINT32 Data;
+ UINT16 Data16[2];
+ UINT8 Data8[4];
+} SPD4_CAS_LATENCIES_SUPPORTED_STRUCT;
+
+typedef union {
+ struct {
+ UINT8 tAAmin : 8; ///< Bits 7:0
+ } Bits;
+ UINT8 Data;
+} SPD4_TAA_MIN_MTB_STRUCT;
+
+typedef union {
+ struct {
+ UINT8 tRCDmin : 8; ///< Bits 7:0
+ } Bits;
+ UINT8 Data;
+} SPD4_TRCD_MIN_MTB_STRUCT;
+
+typedef union {
+ struct {
+ UINT8 tRPmin : 8; ///< Bits 7:0
+ } Bits;
+ UINT8 Data;
+} SPD4_TRP_MIN_MTB_STRUCT;
+
+typedef union {
+ struct {
+ UINT8 tRASminUpper : 4; ///< Bits 3:0
+ UINT8 tRCminUpper : 4; ///< Bits 7:4
+ } Bits;
+ UINT8 Data;
+} SPD4_TRAS_TRC_MIN_MTB_STRUCT;
+
+typedef union {
+ struct {
+ UINT8 tRASmin : 8; ///< Bits 7:0
+ } Bits;
+ UINT8 Data;
+} SPD4_TRAS_MIN_MTB_STRUCT;
+
+typedef union {
+ struct {
+ UINT8 tRCmin : 8; ///< Bits 7:0
+ } Bits;
+ UINT8 Data;
+} SPD4_TRC_MIN_MTB_STRUCT;
+
+typedef union {
+ struct {
+ UINT16 tRFCmin : 16; ///< Bits 15:0
+ } Bits;
+ UINT16 Data;
+ UINT8 Data8[2];
+} SPD4_TRFC_MIN_MTB_STRUCT;
+
+typedef union {
+ struct {
+ UINT8 tFAWminUpper : 4; ///< Bits 3:0
+ UINT8 Reserved : 4; ///< Bits 7:4
+ } Bits;
+ UINT8 Data;
+} SPD4_TFAW_MIN_MTB_UPPER_STRUCT;
+
+typedef union {
+ struct {
+ UINT8 tFAWmin : 8; ///< Bits 7:0
+ } Bits;
+ UINT8 Data;
+} SPD4_TFAW_MIN_MTB_STRUCT;
+
+typedef union {
+ struct {
+ UINT8 tRRDmin : 8; ///< Bits 7:0
+ } Bits;
+ UINT8 Data;
+} SPD4_TRRD_MIN_MTB_STRUCT;
+
+typedef union {
+ struct {
+ UINT8 tCCDmin : 8; ///< Bits 7:0
+ } Bits;
+ UINT8 Data;
+} SPD4_TCCD_MIN_MTB_STRUCT;
+
+typedef union {
+ struct {
+ UINT8 tWRminMostSignificantNibble : 4; ///< Bits 3:0
+ UINT8 Reserved : 4; ///< Bits 7:4
+ } Bits;
+ UINT8 Data;
+} SPD4_TWR_UPPER_NIBBLE_STRUCT;
+
+typedef union {
+ struct {
+ UINT8 tWRmin : 8; ///< Bits 7:0
+ } Bits;
+ UINT8 Data;
+} SPD4_TWR_MIN_MTB_STRUCT;
+
+typedef union {
+ struct {
+ UINT8 tWTR_SminMostSignificantNibble : 4; ///< Bits 3:0
+ UINT8 tWTR_LminMostSignificantNibble : 4; ///< Bits 7:4
+ } Bits;
+ UINT8 Data;
+} SPD4_TWTR_UPPER_NIBBLE_STRUCT;
+
+typedef union {
+ struct {
+ UINT8 tWTRmin : 8; ///< Bits 7:0
+ } Bits;
+ UINT8 Data;
+} SPD4_TWTR_MIN_MTB_STRUCT;
+
+typedef union {
+ struct {
+ UINT8 BitOrderatSDRAM : 5; ///< Bits 4:0
+ UINT8 WiredtoUpperLowerNibble : 1; ///< Bits 5:5
+ UINT8 PackageRankMap : 2; ///< Bits 7:6
+ } Bits;
+ UINT8 Data;
+} SPD4_CONNECTOR_BIT_MAPPING_BYTE_STRUCT;
+
+typedef union {
+ struct {
+ INT8 tCCDminFine : 8; ///< Bits 7:0
+ } Bits;
+ INT8 Data;
+} SPD4_TCCD_MIN_FTB_STRUCT;
+
+typedef union {
+ struct {
+ INT8 tRRDminFine : 8; ///< Bits 7:0
+ } Bits;
+ INT8 Data;
+} SPD4_TRRD_MIN_FTB_STRUCT;
+
+typedef union {
+ struct {
+ INT8 tRCminFine : 8; ///< Bits 7:0
+ } Bits;
+ INT8 Data;
+} SPD4_TRC_MIN_FTB_STRUCT;
+
+typedef union {
+ struct {
+ INT8 tRPminFine : 8; ///< Bits 7:0
+ } Bits;
+ INT8 Data;
+} SPD4_TRP_MIN_FTB_STRUCT;
+
+typedef union {
+ struct {
+ INT8 tRCDminFine : 8; ///< Bits 7:0
+ } Bits;
+ INT8 Data;
+} SPD4_TRCD_MIN_FTB_STRUCT;
+
+typedef union {
+ struct {
+ INT8 tAAminFine : 8; ///< Bits 7:0
+ } Bits;
+ INT8 Data;
+} SPD4_TAA_MIN_FTB_STRUCT;
+
+typedef union {
+ struct {
+ INT8 tCKmaxFine : 8; ///< Bits 7:0
+ } Bits;
+ INT8 Data;
+} SPD4_TCK_MAX_FTB_STRUCT;
+
+typedef union {
+ struct {
+ INT8 tCKminFine : 8; ///< Bits 7:0
+ } Bits;
+ INT8 Data;
+} SPD4_TCK_MIN_FTB_STRUCT;
+
+typedef union {
+ struct {
+ UINT8 Height : 5; ///< Bits 4:0
+ UINT8 RawCardExtension : 3; ///< Bits 7:5
+ } Bits;
+ UINT8 Data;
+} SPD4_UNBUF_MODULE_NOMINAL_HEIGHT;
+
+typedef union {
+ struct {
+ UINT8 FrontThickness : 4; ///< Bits 3:0
+ UINT8 BackThickness : 4; ///< Bits 7:4
+ } Bits;
+ UINT8 Data;
+} SPD4_UNBUF_MODULE_NOMINAL_THICKNESS;
+
+typedef union {
+ struct {
+ UINT8 Card : 5; ///< Bits 4:0
+ UINT8 Revision : 2; ///< Bits 6:5
+ UINT8 Extension : 1; ///< Bits 7:7
+ } Bits;
+ UINT8 Data;
+} SPD4_UNBUF_REFERENCE_RAW_CARD;
+
+typedef union {
+ struct {
+ UINT8 MappingRank1 : 1; ///< Bits 0:0
+ UINT8 Reserved : 7; ///< Bits 7:1
+ } Bits;
+ UINT8 Data;
+} SPD4_UNBUF_ADDRESS_MAPPING;
+
+typedef union {
+ struct {
+ UINT8 Height : 5; ///< Bits 4:0
+ UINT8 Reserved : 3; ///< Bits 7:5
+ } Bits;
+ UINT8 Data;
+} SPD4_RDIMM_MODULE_NOMINAL_HEIGHT;
+
+typedef union {
+ struct {
+ UINT8 FrontThickness : 4; ///< Bits 3:0
+ UINT8 BackThickness : 4; ///< Bits 7:4
+ } Bits;
+ UINT8 Data;
+} SPD4_RDIMM_MODULE_NOMINAL_THICKNESS;
+
+typedef union {
+ struct {
+ UINT8 Card : 5; ///< Bits 4:0
+ UINT8 Revision : 2; ///< Bits 6:5
+ UINT8 Extension : 1; ///< Bits 7:7
+ } Bits;
+ UINT8 Data;
+} SPD4_RDIMM_REFERENCE_RAW_CARD;
+
+typedef union {
+ struct {
+ UINT8 RegisterCount : 2; ///< Bits 1:0
+ UINT8 DramRowCount : 2; ///< Bits 3:2
+ UINT8 RegisterType : 4; ///< Bits 7:4
+ } Bits;
+ UINT8 Data;
+} SPD4_RDIMM_MODULE_ATTRIBUTES;
+
+typedef union {
+ struct {
+ UINT8 HeatSpreaderThermalCharacteristics : 7; ///< Bits 6:0
+ UINT8 HeatSpreaderSolution : 1; ///< Bits 7:7
+ } Bits;
+ UINT8 Data;
+} SPD4_RDIMM_THERMAL_HEAT_SPREADER_SOLUTION;
+
+typedef union {
+ struct {
+ UINT16 ContinuationCount : 7; ///< Bits 6:0
+ UINT16 ContinuationParity : 1; ///< Bits 7:7
+ UINT16 LastNonZeroByte : 8; ///< Bits 15:8
+ } Bits;
+ UINT16 Data;
+ UINT8 Data8[2];
+} SPD4_MANUFACTURER_ID_CODE;
+
+typedef union {
+ struct {
+ UINT8 RegisterRevisionNumber; ///< Bits 7:0
+ } Bits;
+ UINT8 Data;
+} SPD4_RDIMM_REGISTER_REVISION_NUMBER;
+
+typedef union {
+ struct {
+ UINT8 Rank1Mapping : 1; ///< Bits 0:0
+ UINT8 Reserved : 7; ///< Bits 7:1
+ } Bits;
+ UINT8 Data;
+} SPD4_RDIMM_ADDRESS_MAPPING_FROM_REGISTER_TO_DRAM;
+
+typedef union {
+ struct {
+ UINT8 Cke : 2; ///< Bits 1:0
+ UINT8 Odt : 2; ///< Bits 3:2
+ UINT8 CommandAddress : 2; ///< Bits 5:4
+ UINT8 ChipSelect : 2; ///< Bits 7:6
+ } Bits;
+ UINT8 Data;
+} SPD4_RDIMM_REGISTER_OUTPUT_DRIVE_STRENGTH_FOR_CONTROL_COMMAND_ADDRESS;
+
+typedef union {
+ struct {
+ UINT8 Y0Y2 : 2; ///< Bits 1:0
+ UINT8 Y1Y3 : 2; ///< Bits 3:2
+ UINT8 Reserved0 : 2; ///< Bits 5:4
+ UINT8 RcdOutputSlewRateControl : 1; ///< Bits 6:6
+ UINT8 Reserved1 : 1; ///< Bits 7:7
+ } Bits;
+ UINT8 Data;
+} SPD4_RDIMM_REGISTER_OUTPUT_DRIVE_STRENGTH_FOR_CLOCK;
+
+typedef union {
+ struct {
+ UINT8 Height : 5; ///< Bits 4:0
+ UINT8 Reserved : 3; ///< Bits 7:5
+ } Bits;
+ UINT8 Data;
+} SPD4_LRDIMM_MODULE_NOMINAL_HEIGHT;
+
+typedef union {
+ struct {
+ UINT8 FrontThickness : 4; ///< Bits 3:0
+ UINT8 BackThickness : 4; ///< Bits 7:4
+ } Bits;
+ UINT8 Data;
+} SPD4_LRDIMM_MODULE_NOMINAL_THICKNESS;
+
+typedef union {
+ struct {
+ UINT8 Card : 5; ///< Bits 4:0
+ UINT8 Revision : 2; ///< Bits 6:5
+ UINT8 Extension : 1; ///< Bits 7:7
+ } Bits;
+ UINT8 Data;
+} SPD4_LRDIMM_REFERENCE_RAW_CARD;
+
+typedef union {
+ struct {
+ UINT8 RegisterCount : 2; ///< Bits 1:0
+ UINT8 DramRowCount : 2; ///< Bits 3:2
+ UINT8 RegisterType : 4; ///< Bits 7:4
+ } Bits;
+ UINT8 Data;
+} SPD4_LRDIMM_MODULE_ATTRIBUTES;
+
+typedef union {
+ struct {
+ UINT8 HeatSpreaderThermalCharacteristics : 7; ///< Bits 6:0
+ UINT8 HeatSpreaderSolution : 1; ///< Bits 7:7
+ } Bits;
+ UINT8 Data;
+} SPD4_LRDIMM_THERMAL_HEAT_SPREADER_SOLUTION;
+
+typedef union {
+ struct {
+ UINT8 RegisterRevisionNumber; ///< Bits 7:0
+ } Bits;
+ UINT8 Data;
+} SPD4_LRDIMM_REGISTER_REVISION_NUMBER;
+
+typedef union {
+ struct {
+ UINT8 Rank1Mapping : 1; ///< Bits 0:0
+ UINT8 Reserved : 7; ///< Bits 7:1
+ } Bits;
+ UINT8 Data;
+} SPD4_LRDIMM_ADDRESS_MAPPING_FROM_REGISTER_TO_DRAM;
+
+typedef union {
+ struct {
+ UINT8 Cke : 2; ///< Bits 1:0
+ UINT8 Odt : 2; ///< Bits 3:2
+ UINT8 CommandAddress : 2; ///< Bits 5:4
+ UINT8 ChipSelect : 2; ///< Bits 7:6
+ } Bits;
+ UINT8 Data;
+} SPD4_LRDIMM_REGISTER_OUTPUT_DRIVE_STRENGTH_FOR_CONTROL_COMMAND_ADDRESS;
+
+typedef union {
+ struct {
+ UINT8 Y0Y2 : 2; ///< Bits 1:0
+ UINT8 Y1Y3 : 2; ///< Bits 3:2
+ UINT8 Reserved0 : 2; ///< Bits 5:4
+ UINT8 RcdOutputSlewRateControl : 1; ///< Bits 6:6
+ UINT8 Reserved1 : 1; ///< Bits 7:7
+ } Bits;
+ UINT8 Data;
+} SPD4_LRDIMM_REGISTER_OUTPUT_DRIVE_STRENGTH_FOR_CLOCK;
+
+typedef struct {
+ UINT8 DataBufferRevisionNumber;
+} SPD4_LRDIMM_DATA_BUFFER_REVISION_NUMBER;
+
+typedef union {
+ struct {
+ UINT8 DramVrefDQForPackageRank0 : 6; ///< Bits 5:0
+ UINT8 Reserved : 2; ///< Bits 7:6
+ } Bits;
+ UINT8 Data;
+} SPD4_LRDIMM_DRAM_VREFDQ_FOR_PACKAGE_RANK;
+
+typedef struct {
+ UINT8 DataBufferVrefDQforDramInterface;
+} SPD4_LRDIMM_DATA_BUFFER_VREFDQ_FOR_DRAM_INTERFACE;
+
+typedef union {
+ struct {
+ UINT8 DramInterfaceMdqDriveStrength : 4; ///< Bits 3:0
+ UINT8 DramInterfaceMdqReadTerminationStrength : 4; ///< Bits 7:4
+ } Bits;
+ UINT8 Data;
+} SPD4_LRDIMM_DATA_BUFFER_MDQ_DRIVE_STRENGTH_RTT_FOR_DATA_RATE;
+
+typedef union {
+ struct {
+ UINT8 DataRateLe1866 : 2; ///< Bits 1:0
+ UINT8 DataRateLe2400 : 2; ///< Bits 3:2
+ UINT8 DataRateLe3200 : 2; ///< Bits 5:4
+ UINT8 Reserved : 2; ///< Bits 7:6
+ } Bits;
+ UINT8 Data;
+} SPD4_LRDIMM_DRAM_DRIVE_STRENGTH;
+
+typedef union {
+ struct {
+ UINT8 Rtt_Nom : 3; ///< Bits 2:0
+ UINT8 Rtt_WR : 3; ///< Bits 5:3
+ UINT8 Reserved : 2; ///< Bits 7:6
+ } Bits;
+ UINT8 Data;
+} SPD4_LRDIMM_DRAM_ODT_RTT_WR_RTT_NOM_FOR_DATA_RATE;
+
+typedef union {
+ struct {
+ UINT8 PackageRanks0_1 : 3; ///< Bits 2:0
+ UINT8 PackageRanks2_3 : 3; ///< Bits 5:3
+ UINT8 Reserved : 2; ///< Bits 7:6
+ } Bits;
+ UINT8 Data;
+} SPD4_LRDIMM_DRAM_ODT_RTT_PARK_FOR_DATA_RATE;
+
+typedef union {
+ struct {
+ UINT8 Rank0 : 1; ///< Bits 0:0
+ UINT8 Rank1 : 1; ///< Bits 1:1
+ UINT8 Rank2 : 1; ///< Bits 2:2
+ UINT8 Rank3 : 1; ///< Bits 3:3
+ UINT8 DataBuffer : 1; ///< Bits 4:4
+ UINT8 Reserved : 3; ///< Bits 7:5
+ } Bits;
+ UINT8 Data;
+} SPD4_LRDIMM_DATA_BUFFER_VREFDQ_FOR_DRAM_INTERFACE_RANGE;
+
+typedef union {
+ struct {
+ UINT8 DataBufferGainAdjustment : 1; ///< Bits 0:0
+ UINT8 DataBufferDfe : 1; ///< Bits 1:1
+ UINT8 Reserved : 6; ///< Bits 7:2
+ } Bits;
+ UINT8 Data;
+} SPD4_LRDIMM_DATA_BUFFER_DQ_DECISION_FEEDBACK_EQUALIZATION;
+
+typedef UINT16 SPD4_NVDIMM_MODULE_PRODUCT_IDENTIFIER;
+
+typedef union {
+ struct {
+ UINT16 ContinuationCount : 7; ///< Bits 6:0
+ UINT16 ContinuationParity : 1; ///< Bits 7:7
+ UINT16 LastNonZeroByte : 8; ///< Bits 15:8
+ } Bits;
+ UINT16 Data;
+ UINT8 Data8[2];
+} SPD4_NVDIMM_SUBSYSTEM_CONTROLLER_MANUFACTURER_ID_CODE;
+
+typedef UINT16 SPD4_NVDIMM_SUBSYSTEM_CONTROLLER_IDENTIFIER;
+
+typedef UINT8 SPD4_NVDIMM_SUBSYSTEM_CONTROLLER_REVISION_CODE;
+
+typedef union {
+ struct {
+ UINT8 Card : 5; ///< Bits 4:0
+ UINT8 Revision : 2; ///< Bits 6:5
+ UINT8 Extension : 1; ///< Bits 7:7
+ } Bits;
+ UINT8 Data;
+} SPD4_NVDIMM_REFERENCE_RAW_CARD;
+
+typedef union {
+ struct {
+ UINT8 Reserved : 4; ///< Bits 3:0
+ UINT8 Extension : 4; ///< Bits 7:4
+ } Bits;
+ UINT8 Data;
+} SPD4_NVDIMM_MODULE_CHARACTERISTICS;
+
+typedef struct {
+ UINT8 Reserved;
+ UINT8 MediaType;
+} SPD4_NVDIMM_HYBRID_MODULE_MEDIA_TYPES;
+
+typedef UINT8 SPD4_NVDIMM_MAXIMUM_NONVOLATILE_MEMORY_INITIALIZATION_TIME;
+
+typedef union {
+ struct {
+ UINT16 FunctionInterface : 5; ///< Bits 4:0
+ UINT16 FunctionClass : 5; ///< Bits 9:5
+ UINT16 BlockOffset : 4; ///< Bits 13:10
+ UINT16 Reserved : 1; ///< Bits 14:14
+ UINT16 Implemented : 1; ///< Bits 15:15
+ } Bits;
+ UINT16 Data;
+ UINT8 Data8[2];
+} SPD4_NVDIMM_FUNCTION_INTERFACE_DESCRIPTOR;
+
+typedef struct {
+ UINT8 Year; ///< Year represented in BCD (00h = 2000)
+ UINT8 Week; ///< Year represented in BCD (47h = week 47)
+} SPD4_MANUFACTURING_DATE;
+
+typedef union {
+ UINT32 Data;
+ UINT16 SerialNumber16[2];
+ UINT8 SerialNumber8[4];
+} SPD4_MANUFACTURER_SERIAL_NUMBER;
+
+typedef struct {
+ UINT8 Location; ///< Module Manufacturing Location
+} SPD4_MANUFACTURING_LOCATION;
+
+typedef struct {
+ SPD4_MANUFACTURER_ID_CODE IdCode; ///< Module Manufacturer ID Code
+ SPD4_MANUFACTURING_LOCATION Location; ///< Module Manufacturing Location
+ SPD4_MANUFACTURING_DATE Date; ///< Module Manufacturing Year, in BCD (range: 2000-2255)
+ SPD4_MANUFACTURER_SERIAL_NUMBER SerialNumber; ///< Module Serial Number
+} SPD4_UNIQUE_MODULE_ID;
+
+typedef union {
+ UINT16 Crc[1];
+ UINT8 Data8[2];
+} SPD4_CYCLIC_REDUNDANCY_CODE;
+
+typedef struct {
+ SPD4_DEVICE_DESCRIPTION_STRUCT Description; ///< 0 Number of Serial PD Bytes Written / SPD Device Size / CRC Coverage 1, 2
+ SPD4_REVISION_STRUCT Revision; ///< 1 SPD Revision
+ SPD4_DRAM_DEVICE_TYPE_STRUCT DramDeviceType; ///< 2 DRAM Device Type
+ SPD4_MODULE_TYPE_STRUCT ModuleType; ///< 3 Module Type
+ SPD4_SDRAM_DENSITY_BANKS_STRUCT SdramDensityAndBanks; ///< 4 SDRAM Density and Banks
+ SPD4_SDRAM_ADDRESSING_STRUCT SdramAddressing; ///< 5 SDRAM Addressing
+ SPD4_PRIMARY_SDRAM_PACKAGE_TYPE_STRUCT PrimarySdramPackageType; ///< 6 Primary SDRAM Package Type
+ SPD4_SDRAM_OPTIONAL_FEATURES_STRUCT SdramOptionalFeatures; ///< 7 SDRAM Optional Features
+ SPD4_SDRAM_THERMAL_REFRESH_STRUCT ThermalAndRefreshOptions; ///< 8 SDRAM Thermal and Refresh Options
+ SPD4_OTHER_SDRAM_OPTIONAL_FEATURES_STRUCT OtherOptionalFeatures; ///< 9 Other SDRAM Optional Features
+ SPD4_SECONDARY_SDRAM_PACKAGE_TYPE_STRUCT SecondarySdramPackageType; ///< 10 Secondary SDRAM Package Type
+ SPD4_MODULE_NOMINAL_VOLTAGE_STRUCT ModuleNominalVoltage; ///< 11 Module Nominal Voltage, VDD
+ SPD4_MODULE_ORGANIZATION_STRUCT ModuleOrganization; ///< 12 Module Organization
+ SPD4_MODULE_MEMORY_BUS_WIDTH_STRUCT ModuleMemoryBusWidth; ///< 13 Module Memory Bus Width
+ SPD4_MODULE_THERMAL_SENSOR_STRUCT ModuleThermalSensor; ///< 14 Module Thermal Sensor
+ SPD4_EXTENDED_MODULE_TYPE_STRUCT ExtendedModuleType; ///< 15 Extended Module Type
+ UINT8 Reserved0; ///< 16 Reserved
+ SPD4_TIMEBASE_STRUCT Timebase; ///< 17 Timebases
+ SPD4_TCK_MIN_MTB_STRUCT tCKmin; ///< 18 SDRAM Minimum Cycle Time (tCKmin)
+ SPD4_TCK_MAX_MTB_STRUCT tCKmax; ///< 19 SDRAM Maximum Cycle Time (tCKmax)
+ SPD4_CAS_LATENCIES_SUPPORTED_STRUCT CasLatencies; ///< 20-23 CAS Latencies Supported
+ SPD4_TAA_MIN_MTB_STRUCT tAAmin; ///< 24 Minimum CAS Latency Time (tAAmin)
+ SPD4_TRCD_MIN_MTB_STRUCT tRCDmin; ///< 25 Minimum RAS# to CAS# Delay Time (tRCDmin)
+ SPD4_TRP_MIN_MTB_STRUCT tRPmin; ///< 26 Minimum Row Precharge Delay Time (tRPmin)
+ SPD4_TRAS_TRC_MIN_MTB_STRUCT tRASMintRCMinUpper; ///< 27 Upper Nibbles for tRAS and tRC
+ SPD4_TRAS_MIN_MTB_STRUCT tRASmin; ///< 28 Minimum Active to Precharge Delay Time (tRASmin), Least Significant Byte
+ SPD4_TRC_MIN_MTB_STRUCT tRCmin; ///< 29 Minimum Active to Active/Refresh Delay Time (tRCmin), Least Significant Byte
+ SPD4_TRFC_MIN_MTB_STRUCT tRFC1min; ///< 30-31 Minimum Refresh Recovery Delay Time (tRFC1min)
+ SPD4_TRFC_MIN_MTB_STRUCT tRFC2min; ///< 32-33 Minimum Refresh Recovery Delay Time (tRFC2min)
+ SPD4_TRFC_MIN_MTB_STRUCT tRFC4min; ///< 34-35 Minimum Refresh Recovery Delay Time (tRFC4min)
+ SPD4_TFAW_MIN_MTB_UPPER_STRUCT tFAWMinUpper; ///< 36 Upper Nibble for tFAW
+ SPD4_TFAW_MIN_MTB_STRUCT tFAWmin; ///< 37 Minimum Four Activate Window Delay Time (tFAWmin)
+ SPD4_TRRD_MIN_MTB_STRUCT tRRD_Smin; ///< 38 Minimum Activate to Activate Delay Time (tRRD_Smin), different bank group
+ SPD4_TRRD_MIN_MTB_STRUCT tRRD_Lmin; ///< 39 Minimum Activate to Activate Delay Time (tRRD_Lmin), same bank group
+ SPD4_TCCD_MIN_MTB_STRUCT tCCD_Lmin; ///< 40 Minimum CAS to CAS Delay Time (tCCD_Lmin), Same Bank Group
+ SPD4_TWR_UPPER_NIBBLE_STRUCT tWRUpperNibble; ///< 41 Upper Nibble for tWRmin
+ SPD4_TWR_MIN_MTB_STRUCT tWRmin; ///< 42 Minimum Write Recovery Time (tWRmin)
+ SPD4_TWTR_UPPER_NIBBLE_STRUCT tWTRUpperNibble; ///< 43 Upper Nibbles for tWTRmin
+ SPD4_TWTR_MIN_MTB_STRUCT tWTR_Smin; ///< 44 Minimum Write to Read Time (tWTR_Smin), Different Bank Group
+ SPD4_TWTR_MIN_MTB_STRUCT tWTR_Lmin; ///< 45 Minimum Write to Read Time (tWTR_Lmin), Same Bank Group
+ UINT8 Reserved1[59 - 46 + 1]; ///< 46-59 Reserved
+ SPD4_CONNECTOR_BIT_MAPPING_BYTE_STRUCT BitMapping[77 - 60 + 1]; ///< 60-77 Connector to SDRAM Bit Mapping
+ UINT8 Reserved2[116 - 78 + 1]; ///< 78-116 Reserved
+ SPD4_TCCD_MIN_FTB_STRUCT tCCD_LminFine; ///< 117 Fine Offset for Minimum CAS to CAS Delay Time (tCCD_Lmin), same bank group
+ SPD4_TRRD_MIN_FTB_STRUCT tRRD_LminFine; ///< 118 Fine Offset for Minimum Activate to Activate Delay Time (tRRD_Lmin), different bank group
+ SPD4_TRRD_MIN_FTB_STRUCT tRRD_SminFine; ///< 119 Fine Offset for Minimum Activate to Activate Delay Time (tRRD_Smin), same bank group
+ SPD4_TRC_MIN_FTB_STRUCT tRCminFine; ///< 120 Fine Offset for Minimum Active to Active/Refresh Delay Time (tRCmin)
+ SPD4_TRP_MIN_FTB_STRUCT tRPminFine; ///< 121 Fine Offset for Minimum Row Precharge Delay Time (tRPabmin)
+ SPD4_TRCD_MIN_FTB_STRUCT tRCDminFine; ///< 122 Fine Offset for Minimum RAS# to CAS# Delay Time (tRCDmin)
+ SPD4_TAA_MIN_FTB_STRUCT tAAminFine; ///< 123 Fine Offset for Minimum CAS Latency Time (tAAmin)
+ SPD4_TCK_MAX_FTB_STRUCT tCKmaxFine; ///< 124 Fine Offset for SDRAM Minimum Cycle Time (tCKmax)
+ SPD4_TCK_MIN_FTB_STRUCT tCKminFine; ///< 125 Fine Offset for SDRAM Maximum Cycle Time (tCKmin)
+ SPD4_CYCLIC_REDUNDANCY_CODE Crc; ///< 126-127 Cyclical Redundancy Code (CRC)
+} SPD4_BASE_SECTION;
+
+typedef struct {
+ SPD4_UNBUF_MODULE_NOMINAL_HEIGHT ModuleNominalHeight; ///< 128 Module Nominal Height
+ SPD4_UNBUF_MODULE_NOMINAL_THICKNESS ModuleMaximumThickness; ///< 129 Module Maximum Thickness
+ SPD4_UNBUF_REFERENCE_RAW_CARD ReferenceRawCardUsed; ///< 130 Reference Raw Card Used
+ SPD4_UNBUF_ADDRESS_MAPPING AddressMappingEdgeConn; ///< 131 Address Mapping from Edge Connector to DRAM
+ UINT8 Reserved[253 - 132 + 1]; ///< 132-253 Reserved
+ SPD4_CYCLIC_REDUNDANCY_CODE Crc; ///< 254-255 Cyclical Redundancy Code (CRC)
+} SPD4_MODULE_UNBUFFERED;
+
+typedef struct {
+ SPD4_RDIMM_MODULE_NOMINAL_HEIGHT ModuleNominalHeight; ///< 128 Module Nominal Height
+ SPD4_RDIMM_MODULE_NOMINAL_THICKNESS ModuleMaximumThickness; ///< 129 Module Maximum Thickness
+ SPD4_RDIMM_REFERENCE_RAW_CARD ReferenceRawCardUsed; ///< 130 Reference Raw Card Used
+ SPD4_RDIMM_MODULE_ATTRIBUTES DimmModuleAttributes; ///< 131 DIMM Module Attributes
+ SPD4_RDIMM_THERMAL_HEAT_SPREADER_SOLUTION DimmThermalHeatSpreaderSolution; ///< 132 RDIMM Thermal Heat Spreader Solution
+ SPD4_MANUFACTURER_ID_CODE RegisterManufacturerIdCode; ///< 133-134 Register Manufacturer ID Code
+ SPD4_RDIMM_REGISTER_REVISION_NUMBER RegisterRevisionNumber; ///< 135 Register Revision Number
+ SPD4_RDIMM_ADDRESS_MAPPING_FROM_REGISTER_TO_DRAM AddressMappingFromRegisterToDRAM; ///< 136 Address Mapping from Register to DRAM
+ SPD4_RDIMM_REGISTER_OUTPUT_DRIVE_STRENGTH_FOR_CONTROL_COMMAND_ADDRESS RegisterOutputDriveStrengthForControlCommandAddress; ///< 137 Register Output Drive Strength for Control and Command Address
+ SPD4_RDIMM_REGISTER_OUTPUT_DRIVE_STRENGTH_FOR_CLOCK RegisterOutputDriveStrengthForClock; ///< 138 Register Output Drive Strength for Clock
+ UINT8 Reserved[253 - 139 + 1]; ///< 253-139 Reserved
+ SPD4_CYCLIC_REDUNDANCY_CODE Crc; ///< 254-255 Cyclical Redundancy Code (CRC)
+} SPD4_MODULE_REGISTERED;
+
+typedef struct {
+ SPD4_LRDIMM_MODULE_NOMINAL_HEIGHT ModuleNominalHeight; ///< 128 Module Nominal Height
+ SPD4_LRDIMM_MODULE_NOMINAL_THICKNESS ModuleMaximumThickness; ///< 129 Module Maximum Thickness
+ SPD4_LRDIMM_REFERENCE_RAW_CARD ReferenceRawCardUsed; ///< 130 Reference Raw Card Used
+ SPD4_LRDIMM_MODULE_ATTRIBUTES DimmModuleAttributes; ///< 131 DIMM Module Attributes
+ SPD4_LRDIMM_THERMAL_HEAT_SPREADER_SOLUTION ThermalHeatSpreaderSolution; ///< 132 RDIMM Thermal Heat Spreader Solution
+ SPD4_MANUFACTURER_ID_CODE RegisterManufacturerIdCode; ///< 133-134 Register Manufacturer ID Code
+ SPD4_LRDIMM_REGISTER_REVISION_NUMBER RegisterRevisionNumber; ///< 135 Register Revision Number
+ SPD4_LRDIMM_ADDRESS_MAPPING_FROM_REGISTER_TO_DRAM AddressMappingFromRegisterToDram; ///< 136 Address Mapping from Register to DRAM
+ SPD4_LRDIMM_REGISTER_OUTPUT_DRIVE_STRENGTH_FOR_CONTROL_COMMAND_ADDRESS RegisterOutputDriveStrengthForControlCommandAddress; ///< 137 Register Output Drive Strength for Control and Command Address
+ SPD4_LRDIMM_REGISTER_OUTPUT_DRIVE_STRENGTH_FOR_CLOCK RegisterOutputDriveStrengthForClock; ///< 138 Register Output Drive Strength for Clock
+ SPD4_LRDIMM_DATA_BUFFER_REVISION_NUMBER DataBufferRevisionNumber; ///< 139 Data Buffer Revision Number
+ SPD4_LRDIMM_DRAM_VREFDQ_FOR_PACKAGE_RANK DramVrefDQForPackageRank0; ///< 140 DRAM VrefDQ for Package Rank 0
+ SPD4_LRDIMM_DRAM_VREFDQ_FOR_PACKAGE_RANK DramVrefDQForPackageRank1; ///< 141 DRAM VrefDQ for Package Rank 1
+ SPD4_LRDIMM_DRAM_VREFDQ_FOR_PACKAGE_RANK DramVrefDQForPackageRank2; ///< 142 DRAM VrefDQ for Package Rank 2
+ SPD4_LRDIMM_DRAM_VREFDQ_FOR_PACKAGE_RANK DramVrefDQForPackageRank3; ///< 143 DRAM VrefDQ for Package Rank 3
+ SPD4_LRDIMM_DATA_BUFFER_VREFDQ_FOR_DRAM_INTERFACE DataBufferVrefDQForDramInterface; ///< 144 Data Buffer VrefDQ for DRAM Interface
+ SPD4_LRDIMM_DATA_BUFFER_MDQ_DRIVE_STRENGTH_RTT_FOR_DATA_RATE DataBufferMdqDriveStrengthRttForDataRateLe1866; ///< 145 Data Buffer MDQ Drive Strength and RTT for data rate <= 1866
+ SPD4_LRDIMM_DATA_BUFFER_MDQ_DRIVE_STRENGTH_RTT_FOR_DATA_RATE DataBufferMdqDriveStrengthRttForDataRateLe2400; ///< 146 Data Buffer MDQ Drive Strength and RTT for data rate <=2400
+ SPD4_LRDIMM_DATA_BUFFER_MDQ_DRIVE_STRENGTH_RTT_FOR_DATA_RATE DataBufferMdqDriveStrengthRttForDataRateLe3200; ///< 147 Data Buffer MDQ Drive Strength and RTT for data rate <=3200
+ SPD4_LRDIMM_DRAM_DRIVE_STRENGTH DramDriveStrength; ///< 148 DRAM Drive Strength
+ SPD4_LRDIMM_DRAM_ODT_RTT_WR_RTT_NOM_FOR_DATA_RATE DramOdtRttWrRttNomForDataRateLe1866; ///< 149 DRAM ODT (RTT_WR and RTT_NOM) for data rate <= 1866
+ SPD4_LRDIMM_DRAM_ODT_RTT_WR_RTT_NOM_FOR_DATA_RATE DramOdtRttWrRttNomForDataRateLe2400; ///< 150 DRAM ODT (RTT_WR and RTT_NOM) for data rate <= 2400
+ SPD4_LRDIMM_DRAM_ODT_RTT_WR_RTT_NOM_FOR_DATA_RATE DramOdtRttWrRttNomForDataRateLe3200; ///< 151 DRAM ODT (RTT_WR and RTT_NOM) for data rate <= 3200
+ SPD4_LRDIMM_DRAM_ODT_RTT_PARK_FOR_DATA_RATE DramOdtRttParkForDataRateLe1866; ///< 152 DRAM ODT (RTT_PARK) for data rate <= 1866
+ SPD4_LRDIMM_DRAM_ODT_RTT_PARK_FOR_DATA_RATE DramOdtRttParkForDataRateLe2400; ///< 153 DRAM ODT (RTT_PARK) for data rate <= 2400
+ SPD4_LRDIMM_DRAM_ODT_RTT_PARK_FOR_DATA_RATE DramOdtRttParkForDataRateLe3200; ///< 154 DRAM ODT (RTT_PARK) for data rate <= 3200
+ SPD4_LRDIMM_DATA_BUFFER_VREFDQ_FOR_DRAM_INTERFACE_RANGE DataBufferVrefDQForDramInterfaceRange; ///< 155 Data Buffer VrefDQ for DRAM Interface Range
+ SPD4_LRDIMM_DATA_BUFFER_DQ_DECISION_FEEDBACK_EQUALIZATION DataBufferDqDecisionFeedbackEqualization; ///< 156 Data Buffer DQ Decision Feedback Equalization
+ UINT8 Reserved[253 - 157 + 1]; ///< 253-132 Reserved
+ SPD4_CYCLIC_REDUNDANCY_CODE Crc; ///< 254-255 Cyclical Redundancy Code (CRC)
+} SPD4_MODULE_LOADREDUCED;
+
+typedef struct {
+ UINT8 Reserved0[191 - 128 + 1]; ///< 128-191 Reserved
+ SPD4_NVDIMM_MODULE_PRODUCT_IDENTIFIER ModuleProductIdentifier; ///< 192-193 Module Product Identifier
+ SPD4_NVDIMM_SUBSYSTEM_CONTROLLER_MANUFACTURER_ID_CODE SubsystemControllerManufacturerIdCode; ///< 194-195 Subsystem Controller Manufacturer's ID Code
+ SPD4_NVDIMM_SUBSYSTEM_CONTROLLER_IDENTIFIER SubsystemControllerIdentifier; ///< 196-197 Subsystem Controller Identifier
+ SPD4_NVDIMM_SUBSYSTEM_CONTROLLER_REVISION_CODE SubsystemControllerRevisionCode; ///< 198 Subsystem Controller Revision Code
+ SPD4_NVDIMM_REFERENCE_RAW_CARD ReferenceRawCardUsed; ///< 199 Reference Raw Card Used
+ SPD4_NVDIMM_MODULE_CHARACTERISTICS ModuleCharacteristics; ///< 200 Module Characteristics
+ SPD4_NVDIMM_HYBRID_MODULE_MEDIA_TYPES HybridModuleMediaTypes; ///< 201-202 Hybrid Module Media Types
+ SPD4_NVDIMM_MAXIMUM_NONVOLATILE_MEMORY_INITIALIZATION_TIME MaximumNonVolatileMemoryInitializationTime; ///< 203 Maximum Non-Volatile Memory Initialization Time
+ SPD4_NVDIMM_FUNCTION_INTERFACE_DESCRIPTOR FunctionInterfaceDescriptors[8]; ///< 204-219 Function Interface Descriptors
+ UINT8 Reserved[253 - 220 + 1]; ///< 220-253 Reserved
+ SPD4_CYCLIC_REDUNDANCY_CODE Crc; ///< 254-255 Cyclical Redundancy Code (CRC)
+} SPD4_MODULE_NVDIMM;
+
+typedef union {
+ SPD4_MODULE_UNBUFFERED Unbuffered; ///< 128-255 Unbuffered Memory Module Types
+ SPD4_MODULE_REGISTERED Registered; ///< 128-255 Registered Memory Module Types
+ SPD4_MODULE_LOADREDUCED LoadReduced; ///< 128-255 Load Reduced Memory Module Types
+ SPD4_MODULE_NVDIMM NonVolatile; ///< 128-255 Non-Volatile (NVDIMM-N) Hybrid Memory Parameters
+} SPD4_MODULE_SPECIFIC;
+
+typedef struct {
+ UINT8 ModulePartNumber[348 - 329 + 1]; ///< 329-348 Module Part Number
+} SPD4_MODULE_PART_NUMBER;
+
+typedef struct {
+ UINT8 ManufacturerSpecificData[381 - 353 + 1]; ///< 353-381 Manufacturer's Specific Data
+} SPD4_MANUFACTURER_SPECIFIC;
+
+typedef UINT8 SPD4_MODULE_REVISION_CODE; ///< 349 Module Revision Code
+typedef UINT8 SPD4_DRAM_STEPPING; ///< 352 Dram Stepping
+
+typedef struct {
+ SPD4_UNIQUE_MODULE_ID ModuleId; ///< 320-328 Unique Module ID
+ SPD4_MODULE_PART_NUMBER ModulePartNumber; ///< 329-348 Module Part Number
+ SPD4_MODULE_REVISION_CODE ModuleRevisionCode; ///< 349 Module Revision Code
+ SPD4_MANUFACTURER_ID_CODE DramIdCode; ///< 350-351 Dram Manufacturer ID Code
+ SPD4_DRAM_STEPPING DramStepping; ///< 352 Dram Stepping
+ SPD4_MANUFACTURER_SPECIFIC ManufacturerSpecificData; ///< 353-381 Manufacturer's Specific Data
+ UINT8 Reserved[2]; ///< 382-383 Reserved
+} SPD4_MANUFACTURING_DATA;
+
+typedef struct {
+ UINT8 Reserved[511 - 384 + 1]; ///< 384-511 Unbuffered Memory Module Types
+} SPD4_END_USER_SECTION;
+
+///
+/// DDR4 Serial Presence Detect structure
+///
+typedef struct {
+ SPD4_BASE_SECTION Base; ///< 0-127 Base Configuration and DRAM Parameters
+ SPD4_MODULE_SPECIFIC Module; ///< 128-255 Module-Specific Section
+ UINT8 Reserved[319 - 256 + 1]; ///< 256-319 Reserved
+ SPD4_MANUFACTURING_DATA ManufactureInfo; ///< 320-383 Manufacturing Information
+ SPD4_END_USER_SECTION EndUser; ///< 384-511 End User Programmable
+} SPD_DDR4;
+
+#pragma pack (pop)
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/SdramSpdLpDdr.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/SdramSpdLpDdr.h
new file mode 100644
index 0000000000..1fb73e4a00
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/SdramSpdLpDdr.h
@@ -0,0 +1,468 @@
+/** @file
+ This file contains definitions for SPD LPDDR.
+
+ Copyright (c) 2016, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Revision Reference:
+ - Serial Presence Detect (SPD) for LPDDR3 and LPDDR4 SDRAM Modules Document Release 2
+ http://www.jedec.org/standards-documents/docs/spd412m-2
+**/
+
+#ifndef _SDRAM_SPD_LPDDR_H_
+#define _SDRAM_SPD_LPDDR_H_
+
+#pragma pack (push, 1)
+
+typedef union {
+ struct {
+ UINT8 BytesUsed : 4; ///< Bits 3:0
+ UINT8 BytesTotal : 3; ///< Bits 6:4
+ UINT8 CrcCoverage : 1; ///< Bits 7:7
+ } Bits;
+ UINT8 Data;
+} SPD_LPDDR_DEVICE_DESCRIPTION_STRUCT;
+
+typedef union {
+ struct {
+ UINT8 Minor : 4; ///< Bits 3:0
+ UINT8 Major : 4; ///< Bits 7:4
+ } Bits;
+ UINT8 Data;
+} SPD_LPDDR_REVISION_STRUCT;
+
+typedef union {
+ struct {
+ UINT8 Type : 8; ///< Bits 7:0
+ } Bits;
+ UINT8 Data;
+} SPD_LPDDR_DRAM_DEVICE_TYPE_STRUCT;
+
+typedef union {
+ struct {
+ UINT8 ModuleType : 4; ///< Bits 3:0
+ UINT8 HybridMedia : 3; ///< Bits 6:4
+ UINT8 Hybrid : 1; ///< Bits 7:7
+ } Bits;
+ UINT8 Data;
+} SPD_LPDDR_MODULE_TYPE_STRUCT;
+
+typedef union {
+ struct {
+ UINT8 Density : 4; ///< Bits 3:0
+ UINT8 BankAddress : 2; ///< Bits 5:4
+ UINT8 BankGroup : 2; ///< Bits 7:6
+ } Bits;
+ UINT8 Data;
+} SPD_LPDDR_SDRAM_DENSITY_BANKS_STRUCT;
+
+typedef union {
+ struct {
+ UINT8 ColumnAddress : 3; ///< Bits 2:0
+ UINT8 RowAddress : 3; ///< Bits 5:3
+ UINT8 Reserved : 2; ///< Bits 7:6
+ } Bits;
+ UINT8 Data;
+} SPD_LPDDR_SDRAM_ADDRESSING_STRUCT;
+
+typedef union {
+ struct {
+ UINT8 SignalLoading : 2; ///< Bits 1:0
+ UINT8 ChannelsPerDie : 2; ///< Bits 3:2
+ UINT8 DieCount : 3; ///< Bits 6:4
+ UINT8 SdramPackageType : 1; ///< Bits 7:7
+ } Bits;
+ UINT8 Data;
+} SPD_LPDDR_SDRAM_PACKAGE_TYPE_STRUCT;
+
+typedef union {
+ struct {
+ UINT8 MaximumActivateCount : 4; ///< Bits 3:0
+ UINT8 MaximumActivateWindow : 2; ///< Bits 5:4
+ UINT8 Reserved : 2; ///< Bits 7:6
+ } Bits;
+ UINT8 Data;
+} SPD_LPDDR_SDRAM_OPTIONAL_FEATURES_STRUCT;
+
+typedef union {
+ struct {
+ UINT8 Reserved : 8; ///< Bits 7:0
+ } Bits;
+ UINT8 Data;
+} SPD_LPDDR_SDRAM_THERMAL_REFRESH_STRUCT;
+
+typedef union {
+ struct {
+ UINT8 Reserved : 5; ///< Bits 4:0
+ UINT8 SoftPPR : 1; ///< Bits 5:5
+ UINT8 PostPackageRepair : 2; ///< Bits 7:6
+ } Bits;
+ UINT8 Data;
+} SPD_LPDDR_OTHER_SDRAM_OPTIONAL_FEATURES_STRUCT;
+
+typedef union {
+ struct {
+ UINT8 OperationAt1_20 : 1; ///< Bits 0:0
+ UINT8 EndurantAt1_20 : 1; ///< Bits 1:1
+ UINT8 OperationAt1_10 : 1; ///< Bits 2:2
+ UINT8 EndurantAt1_10 : 1; ///< Bits 3:3
+ UINT8 OperationAtTBD2V : 1; ///< Bits 4:4
+ UINT8 EndurantAtTBD2V : 1; ///< Bits 5:5
+ UINT8 Reserved : 2; ///< Bits 7:6
+ } Bits;
+ UINT8 Data;
+} SPD_LPDDR_MODULE_NOMINAL_VOLTAGE_STRUCT;
+
+typedef union {
+ struct {
+ UINT8 SdramDeviceWidth : 3; ///< Bits 2:0
+ UINT8 RankCount : 3; ///< Bits 5:3
+ UINT8 Reserved : 2; ///< Bits 7:6
+ } Bits;
+ UINT8 Data;
+} SPD_LPDDR_MODULE_ORGANIZATION_STRUCT;
+
+typedef union {
+ struct {
+ UINT8 PrimaryBusWidth : 3; ///< Bits 2:0
+ UINT8 BusWidthExtension : 2; ///< Bits 4:3
+ UINT8 NumberofChannels : 3; ///< Bits 7:5
+ } Bits;
+ UINT8 Data;
+} SPD_LPDDR_MODULE_MEMORY_BUS_WIDTH_STRUCT;
+
+typedef union {
+ struct {
+ UINT8 Reserved : 7; ///< Bits 6:0
+ UINT8 ThermalSensorPresence : 1; ///< Bits 7:7
+ } Bits;
+ UINT8 Data;
+} SPD_LPDDR_MODULE_THERMAL_SENSOR_STRUCT;
+
+typedef union {
+ struct {
+ UINT8 ExtendedBaseModuleType : 4; ///< Bits 3:0
+ UINT8 Reserved : 4; ///< Bits 7:4
+ } Bits;
+ UINT8 Data;
+} SPD_LPDDR_EXTENDED_MODULE_TYPE_STRUCT;
+
+typedef union {
+ struct {
+ UINT8 ChipSelectLoading : 3; ///< Bits 2:0
+ UINT8 CommandAddressControlClockLoading : 3; ///< Bits 5:3
+ UINT8 DataStrobeMaskLoading : 2; ///< Bits 7:6
+ } Bits;
+ UINT8 Data;
+} SPD_LPDDR_SIGNAL_LOADING_STRUCT;
+
+typedef union {
+ struct {
+ UINT8 Fine : 2; ///< Bits 1:0
+ UINT8 Medium : 2; ///< Bits 3:2
+ UINT8 Reserved : 4; ///< Bits 7:4
+ } Bits;
+ UINT8 Data;
+} SPD_LPDDR_TIMEBASE_STRUCT;
+
+typedef union {
+ struct {
+ UINT8 tCKmin : 8; ///< Bits 7:0
+ } Bits;
+ UINT8 Data;
+} SPD_LPDDR_TCK_MIN_MTB_STRUCT;
+
+typedef union {
+ struct {
+ UINT8 tCKmax : 8; ///< Bits 7:0
+ } Bits;
+ UINT8 Data;
+} SPD_LPDDR_TCK_MAX_MTB_STRUCT;
+
+typedef union {
+ struct {
+ UINT32 Cl3 : 1; ///< Bits 0:0
+ UINT32 Cl6 : 1; ///< Bits 1:1
+ UINT32 Cl8 : 1; ///< Bits 2:2
+ UINT32 Cl9 : 1; ///< Bits 3:3
+ UINT32 Cl10 : 1; ///< Bits 4:4
+ UINT32 Cl11 : 1; ///< Bits 5:5
+ UINT32 Cl12 : 1; ///< Bits 6:6
+ UINT32 Cl14 : 1; ///< Bits 7:7
+ UINT32 Cl16 : 1; ///< Bits 8:8
+ UINT32 Reserved0 : 1; ///< Bits 9:9
+ UINT32 Cl20 : 1; ///< Bits 10:10
+ UINT32 Cl22 : 1; ///< Bits 11:11
+ UINT32 Cl24 : 1; ///< Bits 12:12
+ UINT32 Reserved1 : 1; ///< Bits 13:13
+ UINT32 Cl28 : 1; ///< Bits 14:14
+ UINT32 Reserved2 : 1; ///< Bits 15:15
+ UINT32 Cl32 : 1; ///< Bits 16:16
+ UINT32 Reserved3 : 1; ///< Bits 17:17
+ UINT32 Cl36 : 1; ///< Bits 18:18
+ UINT32 Reserved4 : 1; ///< Bits 19:19
+ UINT32 Cl40 : 1; ///< Bits 20:20
+ UINT32 Reserved5 : 11; ///< Bits 31:21
+ } Bits;
+ UINT32 Data;
+ UINT16 Data16[2];
+ UINT8 Data8[4];
+} SPD_LPDDR_CAS_LATENCIES_SUPPORTED_STRUCT;
+
+typedef union {
+ struct {
+ UINT8 tAAmin : 8; ///< Bits 7:0
+ } Bits;
+ UINT8 Data;
+} SPD_LPDDR_TAA_MIN_MTB_STRUCT;
+
+typedef union {
+ struct {
+ UINT8 ReadLatencyMode : 2; ///< Bits 1:0
+ UINT8 WriteLatencySet : 2; ///< Bits 3:2
+ UINT8 Reserved : 4; ///< Bits 7:4
+ } Bits;
+ UINT8 Data;
+} SPD_LPDDR_RW_LATENCY_OPTION_STRUCT;
+
+typedef union {
+ struct {
+ UINT8 tRCDmin : 8; ///< Bits 7:0
+ } Bits;
+ UINT8 Data;
+} SPD_LPDDR_TRCD_MIN_MTB_STRUCT;
+
+typedef union {
+ struct {
+ UINT8 tRPab : 8; ///< Bits 7:0
+ } Bits;
+ UINT8 Data;
+} SPD_LPDDR_TRP_AB_MTB_STRUCT;
+
+typedef union {
+ struct {
+ UINT8 tRPpb : 8; ///< Bits 7:0
+ } Bits;
+ UINT8 Data;
+} SPD_LPDDR_TRP_PB_MTB_STRUCT;
+
+typedef union {
+ struct {
+ UINT16 tRFCab : 16; ///< Bits 15:0
+ } Bits;
+ UINT16 Data;
+ UINT8 Data8[2];
+} SPD_LPDDR_TRFC_AB_MTB_STRUCT;
+
+typedef union {
+ struct {
+ UINT16 tRFCpb : 16; ///< Bits 15:0
+ } Bits;
+ UINT16 Data;
+ UINT8 Data8[2];
+} SPD_LPDDR_TRFC_PB_MTB_STRUCT;
+
+typedef union {
+ struct {
+ UINT8 BitOrderatSDRAM : 5; ///< Bits 4:0
+ UINT8 WiredtoUpperLowerNibble : 1; ///< Bits 5:5
+ UINT8 PackageRankMap : 2; ///< Bits 7:6
+ } Bits;
+ UINT8 Data;
+} SPD_LPDDR_CONNECTOR_BIT_MAPPING_BYTE_STRUCT;
+
+typedef union {
+ struct {
+ INT8 tRPpbFine : 8; ///< Bits 7:0
+ } Bits;
+ INT8 Data;
+} SPD_LPDDR_TRP_PB_FTB_STRUCT;
+
+typedef union {
+ struct {
+ INT8 tRPabFine : 8; ///< Bits 7:0
+ } Bits;
+ INT8 Data;
+} SPD_LPDDR_TRP_AB_FTB_STRUCT;
+
+typedef union {
+ struct {
+ INT8 tRCDminFine : 8; ///< Bits 7:0
+ } Bits;
+ INT8 Data;
+} SPD_LPDDR_TRCD_MIN_FTB_STRUCT;
+
+typedef union {
+ struct {
+ INT8 tAAminFine : 8; ///< Bits 7:0
+ } Bits;
+ INT8 Data;
+} SPD_LPDDR_TAA_MIN_FTB_STRUCT;
+
+typedef union {
+ struct {
+ INT8 tCKmaxFine : 8; ///< Bits 7:0
+ } Bits;
+ INT8 Data;
+} SPD_LPDDR_TCK_MAX_FTB_STRUCT;
+
+typedef union {
+ struct {
+ INT8 tCKminFine : 8; ///< Bits 7:0
+ } Bits;
+ INT8 Data;
+} SPD_LPDDR_TCK_MIN_FTB_STRUCT;
+
+typedef union {
+ struct {
+ UINT16 ContinuationCount : 7; ///< Bits 6:0
+ UINT16 ContinuationParity : 1; ///< Bits 7:7
+ UINT16 LastNonZeroByte : 8; ///< Bits 15:8
+ } Bits;
+ UINT16 Data;
+ UINT8 Data8[2];
+} SPD_LPDDR_MANUFACTURER_ID_CODE;
+
+typedef struct {
+ UINT8 Location; ///< Module Manufacturing Location
+} SPD_LPDDR_MANUFACTURING_LOCATION;
+
+typedef struct {
+ UINT8 Year; ///< Year represented in BCD (00h = 2000)
+ UINT8 Week; ///< Year represented in BCD (47h = week 47)
+} SPD_LPDDR_MANUFACTURING_DATE;
+
+typedef union {
+ UINT32 Data;
+ UINT16 SerialNumber16[2];
+ UINT8 SerialNumber8[4];
+} SPD_LPDDR_MANUFACTURER_SERIAL_NUMBER;
+
+typedef struct {
+ SPD_LPDDR_MANUFACTURER_ID_CODE IdCode; ///< Module Manufacturer ID Code
+ SPD_LPDDR_MANUFACTURING_LOCATION Location; ///< Module Manufacturing Location
+ SPD_LPDDR_MANUFACTURING_DATE Date; ///< Module Manufacturing Year, in BCD (range: 2000-2255)
+ SPD_LPDDR_MANUFACTURER_SERIAL_NUMBER SerialNumber; ///< Module Serial Number
+} SPD_LPDDR_UNIQUE_MODULE_ID;
+
+typedef union {
+ struct {
+ UINT8 FrontThickness : 4; ///< Bits 3:0
+ UINT8 BackThickness : 4; ///< Bits 7:4
+ } Bits;
+ UINT8 Data;
+} SPD_LPDDR_MODULE_MAXIMUM_THICKNESS;
+
+typedef union {
+ struct {
+ UINT8 Height : 5; ///< Bits 4:0
+ UINT8 RawCardExtension : 3; ///< Bits 7:5
+ } Bits;
+ UINT8 Data;
+} SPD_LPDDR_MODULE_NOMINAL_HEIGHT;
+
+typedef union {
+ struct {
+ UINT8 Card : 5; ///< Bits 4:0
+ UINT8 Revision : 2; ///< Bits 6:5
+ UINT8 Extension : 1; ///< Bits 7:7
+ } Bits;
+ UINT8 Data;
+} SPD_LPDDR_REFERENCE_RAW_CARD;
+
+typedef union {
+ UINT16 Crc[1];
+ UINT8 Data8[2];
+} SPD_LPDDR_CYCLIC_REDUNDANCY_CODE;
+
+typedef struct {
+ SPD_LPDDR_DEVICE_DESCRIPTION_STRUCT Description; ///< 0 Number of Serial PD Bytes Written / SPD Device Size / CRC Coverage 1, 2
+ SPD_LPDDR_REVISION_STRUCT Revision; ///< 1 SPD Revision
+ SPD_LPDDR_DRAM_DEVICE_TYPE_STRUCT DramDeviceType; ///< 2 DRAM Device Type
+ SPD_LPDDR_MODULE_TYPE_STRUCT ModuleType; ///< 3 Module Type
+ SPD_LPDDR_SDRAM_DENSITY_BANKS_STRUCT SdramDensityAndBanks; ///< 4 SDRAM Density and Banks
+ SPD_LPDDR_SDRAM_ADDRESSING_STRUCT SdramAddressing; ///< 5 SDRAM Addressing
+ SPD_LPDDR_SDRAM_PACKAGE_TYPE_STRUCT SdramPackageType; ///< 6 SDRAM Package Type
+ SPD_LPDDR_SDRAM_OPTIONAL_FEATURES_STRUCT SdramOptionalFeatures; ///< 7 SDRAM Optional Features
+ SPD_LPDDR_SDRAM_THERMAL_REFRESH_STRUCT ThermalAndRefreshOptions; ///< 8 SDRAM Thermal and Refresh Options
+ SPD_LPDDR_OTHER_SDRAM_OPTIONAL_FEATURES_STRUCT OtherOptionalFeatures; ///< 9 Other SDRAM Optional Features
+ UINT8 Reserved0; ///< 10 Reserved
+ SPD_LPDDR_MODULE_NOMINAL_VOLTAGE_STRUCT ModuleNominalVoltage; ///< 11 Module Nominal Voltage, VDD
+ SPD_LPDDR_MODULE_ORGANIZATION_STRUCT ModuleOrganization; ///< 12 Module Organization
+ SPD_LPDDR_MODULE_MEMORY_BUS_WIDTH_STRUCT ModuleMemoryBusWidth; ///< 13 Module Memory Bus Width
+ SPD_LPDDR_MODULE_THERMAL_SENSOR_STRUCT ModuleThermalSensor; ///< 14 Module Thermal Sensor
+ SPD_LPDDR_EXTENDED_MODULE_TYPE_STRUCT ExtendedModuleType; ///< 15 Extended Module Type
+ SPD_LPDDR_SIGNAL_LOADING_STRUCT SignalLoading; ///< 16 Signal Loading
+ SPD_LPDDR_TIMEBASE_STRUCT Timebase; ///< 17 Timebases
+ SPD_LPDDR_TCK_MIN_MTB_STRUCT tCKmin; ///< 18 SDRAM Minimum Cycle Time (tCKmin)
+ SPD_LPDDR_TCK_MAX_MTB_STRUCT tCKmax; ///< 19 SDRAM Maximum Cycle Time (tCKmax)
+ SPD_LPDDR_CAS_LATENCIES_SUPPORTED_STRUCT CasLatencies; ///< 20-23 CAS Latencies Supported
+ SPD_LPDDR_TAA_MIN_MTB_STRUCT tAAmin; ///< 24 Minimum CAS Latency Time (tAAmin)
+ SPD_LPDDR_RW_LATENCY_OPTION_STRUCT LatencySetOptions; ///< 25 Read and Write Latency Set Options
+ SPD_LPDDR_TRCD_MIN_MTB_STRUCT tRCDmin; ///< 26 Minimum RAS# to CAS# Delay Time (tRCDmin)
+ SPD_LPDDR_TRP_AB_MTB_STRUCT tRPab; ///< 27 Minimum Row Precharge Delay Time (tRPab), all banks
+ SPD_LPDDR_TRP_PB_MTB_STRUCT tRPpb; ///< 28 Minimum Row Precharge Delay Time (tRPpb), per bank
+ SPD_LPDDR_TRFC_AB_MTB_STRUCT tRFCab; ///< 29-30 Minimum Refresh Recovery Delay Time (tRFCab), all banks
+ SPD_LPDDR_TRFC_PB_MTB_STRUCT tRFCpb; ///< 31-32 Minimum Refresh Recovery Delay Time (tRFCpb), per bank
+ UINT8 Reserved1[59 - 33 + 1]; ///< 33-59 Reserved
+ SPD_LPDDR_CONNECTOR_BIT_MAPPING_BYTE_STRUCT BitMapping[77 - 60 + 1]; ///< 60-77 Connector to SDRAM Bit Mapping
+ UINT8 Reserved2[119 - 78 + 1]; ///< 78-119 Reserved
+ SPD_LPDDR_TRP_PB_FTB_STRUCT tRPpbFine; ///< 120 Fine Offset for Minimum Row Precharge Delay Time (tRPpbFine), per bank
+ SPD_LPDDR_TRP_AB_FTB_STRUCT tRPabFine; ///< 121 Fine Offset for Minimum Row Precharge Delay Time (tRPabFine), all ranks
+ SPD_LPDDR_TRCD_MIN_FTB_STRUCT tRCDminFine; ///< 122 Fine Offset for Minimum RAS# to CAS# Delay Time (tRCDmin)
+ SPD_LPDDR_TAA_MIN_FTB_STRUCT tAAminFine; ///< 123 Fine Offset for Minimum CAS Latency Time (tAAmin)
+ SPD_LPDDR_TCK_MAX_FTB_STRUCT tCKmaxFine; ///< 124 Fine Offset for SDRAM Maximum Cycle Time (tCKmax)
+ SPD_LPDDR_TCK_MIN_FTB_STRUCT tCKminFine; ///< 125 Fine Offset for SDRAM Minimum Cycle Time (tCKmin)
+ SPD_LPDDR_CYCLIC_REDUNDANCY_CODE Crc; ///< 126-127 Cyclical Redundancy Code (CRC)
+} SPD_LPDDR_BASE_SECTION;
+
+typedef struct {
+ SPD_LPDDR_MODULE_NOMINAL_HEIGHT ModuleNominalHeight; ///< 128 Module Nominal Height
+ SPD_LPDDR_MODULE_MAXIMUM_THICKNESS ModuleMaximumThickness; ///< 129 Module Maximum Thickness
+ SPD_LPDDR_REFERENCE_RAW_CARD ReferenceRawCardUsed; ///< 130 Reference Raw Card Used
+ UINT8 Reserved[253 - 131 + 1]; ///< 131-253 Reserved
+ SPD_LPDDR_CYCLIC_REDUNDANCY_CODE Crc; ///< 254-255 Cyclical Redundancy Code (CRC)
+} SPD_LPDDR_MODULE_LPDIMM;
+
+typedef struct {
+ SPD_LPDDR_MODULE_LPDIMM LpDimm; ///< 128-255 Unbuffered Memory Module Types
+} SPD_LPDDR_MODULE_SPECIFIC;
+
+typedef struct {
+ UINT8 ModulePartNumber[348 - 329 + 1]; ///< 329-348 Module Part Number
+} SPD_LPDDR_MODULE_PART_NUMBER;
+
+typedef struct {
+ UINT8 ManufacturerSpecificData[381 - 353 + 1]; ///< 353-381 Manufacturer's Specific Data
+} SPD_LPDDR_MANUFACTURER_SPECIFIC;
+
+typedef UINT8 SPD_LPDDR_MODULE_REVISION_CODE; ///< 349 Module Revision Code
+typedef UINT8 SPD_LPDDR_DRAM_STEPPING; ///< 352 Dram Stepping
+
+typedef struct {
+ SPD_LPDDR_UNIQUE_MODULE_ID ModuleId; ///< 320-328 Unique Module ID
+ SPD_LPDDR_MODULE_PART_NUMBER ModulePartNumber; ///< 329-348 Module Part Number
+ SPD_LPDDR_MODULE_REVISION_CODE ModuleRevisionCode; ///< 349 Module Revision Code
+ SPD_LPDDR_MANUFACTURER_ID_CODE DramIdCode; ///< 350-351 Dram Manufacturer ID Code
+ SPD_LPDDR_DRAM_STEPPING DramStepping; ///< 352 Dram Stepping
+ SPD_LPDDR_MANUFACTURER_SPECIFIC ManufacturerSpecificData; ///< 353-381 Manufacturer's Specific Data
+ UINT8 Reserved[383 - 382 + 1]; ///< 382-383 Reserved
+} SPD_LPDDR_MANUFACTURING_DATA;
+
+typedef struct {
+ UINT8 Reserved[511 - 384 + 1]; ///< 384-511 End User Programmable
+} SPD_LPDDR_END_USER_SECTION;
+
+///
+/// LPDDR Serial Presence Detect structure
+///
+typedef struct {
+ SPD_LPDDR_BASE_SECTION Base; ///< 0-127 Base Configuration and DRAM Parameters
+ SPD_LPDDR_MODULE_SPECIFIC Module; ///< 128-255 Module-Specific Section
+ UINT8 Reserved[319 - 256 + 1]; ///< 256-319 Hybrid Memory Parameters
+ SPD_LPDDR_MANUFACTURING_DATA ManufactureInfo; ///< 320-383 Manufacturing Information
+ SPD_LPDDR_END_USER_SECTION EndUser; ///< 384-511 End User Programmable
+} SPD_LPDDR;
+
+#pragma pack (pop)
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/SerialPortConsoleRedirectionTable.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/SerialPortConsoleRedirectionTable.h
new file mode 100644
index 0000000000..b17500d876
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/SerialPortConsoleRedirectionTable.h
@@ -0,0 +1,175 @@
+/** @file
+ ACPI Serial Port Console Redirection Table as defined by Microsoft in
+ http://www.microsoft.com/whdc/system/platform/server/spcr.mspx
+
+ Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.
+ (C) Copyright 2015 Hewlett Packard Enterprise Development LP
+ Copyright (c) 2014 - 2016, ARM Limited. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_H_
+#define _SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_H_
+
+#include
+
+//
+// Ensure proper structure formats
+//
+#pragma pack(1)
+
+///
+/// SPCR Revision (defined in spec)
+///
+#define EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_REVISION 0x02
+
+///
+/// Serial Port Console Redirection Table Format
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT8 InterfaceType;
+ UINT8 Reserved1[3];
+ EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE BaseAddress;
+ UINT8 InterruptType;
+ UINT8 Irq;
+ UINT32 GlobalSystemInterrupt;
+ UINT8 BaudRate;
+ UINT8 Parity;
+ UINT8 StopBits;
+ UINT8 FlowControl;
+ UINT8 TerminalType;
+ UINT8 Reserved2;
+ UINT16 PciDeviceId;
+ UINT16 PciVendorId;
+ UINT8 PciBusNumber;
+ UINT8 PciDeviceNumber;
+ UINT8 PciFunctionNumber;
+ UINT32 PciFlags;
+ UINT8 PciSegment;
+ UINT32 Reserved3;
+} EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE;
+
+#pragma pack()
+
+//
+// SPCR Definitions
+//
+
+//
+// Interface Type
+//
+
+///
+/// Full 16550 interface
+///
+#define EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERFACE_TYPE_16550 0
+///
+/// Full 16450 interface
+///
+#define EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERFACE_TYPE_16450 1
+
+//
+// The Serial Port Subtypes for ARM are documented in Table 3 of the DBG2 Specification
+//
+
+///
+/// ARM PL011 UART
+///
+#define EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERFACE_TYPE_ARM_PL011_UART 0x03
+
+///
+/// NVIDIA 16550 UART
+///
+#define EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERFACE_TYPE_NVIDIA_16550_UART 0x05
+
+///
+/// ARM SBSA Generic UART (2.x) supporting 32-bit only accesses [deprecated]
+///
+#define EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERFACE_TYPE_ARM_SBSA_GENERIC_UART_2X 0x0d
+
+///
+/// ARM SBSA Generic UART
+///
+#define EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERFACE_TYPE_ARM_SBSA_GENERIC_UART 0x0e
+
+///
+/// ARM DCC
+///
+#define EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERFACE_TYPE_DCC 0x0f
+
+///
+/// BCM2835 UART
+///
+#define EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERFACE_TYPE_BCM2835_UART 0x10
+
+///
+/// 16550-compatible with parameters defined in Generic Address Structure
+///
+#define EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERFACE_TYPE_16550_WITH_GAS 0x12
+
+//
+// Interrupt Type
+//
+
+///
+/// PC-AT-compatible dual-8259 IRQ interrupt
+///
+#define EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERRUPT_TYPE_8259 0x1
+///
+/// I/O APIC interrupt (Global System Interrupt)
+///
+#define EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERRUPT_TYPE_APIC 0x2
+///
+/// I/O SAPIC interrupt (Global System Interrupt)
+///
+#define EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERRUPT_TYPE_SAPIC 0x4
+///
+/// ARMH GIC interrupt (Global System Interrupt)
+///
+#define EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERRUPT_TYPE_GIC 0x8
+
+//
+// Baud Rate
+//
+#define EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_BAUD_RATE_9600 3
+#define EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_BAUD_RATE_19200 4
+#define EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_BAUD_RATE_57600 6
+#define EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_BAUD_RATE_115200 7
+
+//
+// Parity
+//
+#define EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_PARITY_NO_PARITY 0
+
+//
+// Stop Bits
+//
+#define EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_STOP_BITS_1 1
+
+//
+// Flow Control
+//
+
+///
+/// DCD required for transmit
+///
+#define EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_FLOW_CONTROL_DCD 0x1
+///
+/// RTS/CTS hardware flow control
+///
+#define EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_FLOW_CONTROL_RTS_CTS 0x2
+///
+/// XON/XOFF software control
+///
+#define EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_FLOW_CONTROL_XON_XOFF 0x4
+
+//
+// Terminal Type
+//
+#define EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_TERMINAL_TYPE_VT100 0
+#define EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_TERMINAL_TYPE_VT100_PLUS 1
+#define EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_TERMINAL_TYPE_VT_UTF8 2
+#define EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_TERMINAL_TYPE_ANSI 3
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/ServiceProcessorManagementInterfaceTable.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/ServiceProcessorManagementInterfaceTable.h
new file mode 100644
index 0000000000..37a0ecf366
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/ServiceProcessorManagementInterfaceTable.h
@@ -0,0 +1,98 @@
+/** @file
+ Service Processor Management Interface (SPMI) ACPI table definition from
+ Intelligent Platform Management Interface Specification Second Generation.
+
+ Copyright (c) 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Revision Reference:
+ - Intelligent Platform Management Interface Specification Second Generation
+ v2.0 Revision 1.1, Dated October 2013.
+ https://www.intel.com/content/dam/www/public/us/en/documents/specification-updates/ipmi-intelligent-platform-mgt-interface-spec-2nd-gen-v2-0-spec-update.pdf
+**/
+
+#ifndef _SERVICE_PROCESSOR_MANAGEMENT_INTERFACE_TABLE_H_
+#define _SERVICE_PROCESSOR_MANAGEMENT_INTERFACE_TABLE_H_
+
+#include
+
+#pragma pack(1)
+
+///
+/// Definition for the device identification information used by the Service
+/// Processor Management Interface Description Table
+///
+typedef union {
+ ///
+ /// For PCI IPMI device
+ ///
+ struct {
+ UINT8 SegmentGroup;
+ UINT8 Bus;
+ UINT8 Device;
+ UINT8 Function;
+ } Pci;
+ ///
+ /// For non-PCI IPMI device, the ACPI _UID value of the device
+ ///
+ UINT32 Uid;
+} EFI_ACPI_SERVICE_PROCESSOR_MANAGEMENT_INTERFACE_TABLE_DEVICE_ID;
+
+///
+/// Definition for Service Processor Management Interface Description Table
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ ///
+ /// Indicates the type of IPMI interface.
+ ///
+ UINT8 InterfaceType;
+ ///
+ /// This field must always be 01h to be compatible with any software that
+ /// implements previous versions of this spec.
+ ///
+ UINT8 Reserved1;
+ ///
+ /// Identifies the IPMI specification revision, in BCD format.
+ ///
+ UINT16 SpecificationRevision;
+ ///
+ /// Interrupt type(s) used by the interface.
+ ///
+ UINT8 InterruptType;
+ ///
+ /// The bit assignment of the SCI interrupt within the GPEx_STS register of a
+ /// GPE described if the FADT that the interface triggers.
+ ///
+ UINT8 Gpe;
+ ///
+ /// Reserved, must be 00h.
+ ///
+ UINT8 Reserved2;
+ ///
+ /// PCI Device Flag.
+ ///
+ UINT8 PciDeviceFlag;
+ ///
+ /// The I/O APIC or I/O SAPIC Global System Interrupt used by the interface.
+ ///
+ UINT32 GlobalSystemInterrupt;
+ ///
+ /// The base address of the interface register set described using the
+ /// Generic Address Structure (GAS, See [ACPI 2.0] for the definition).
+ ///
+ EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE BaseAddress;
+ ///
+ /// Device identification information.
+ ///
+ EFI_ACPI_SERVICE_PROCESSOR_MANAGEMENT_INTERFACE_TABLE_DEVICE_ID DeviceId;
+ ///
+ /// This field must always be null (0x00) to be compatible with any software
+ /// that implements previous versions of this spec.
+ ///
+ UINT8 Reserved3;
+} EFI_ACPI_SERVICE_PROCESSOR_MANAGEMENT_INTERFACE_TABLE;
+
+#pragma pack()
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/SmBios.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/SmBios.h
new file mode 100644
index 0000000000..f63a575ef9
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/SmBios.h
@@ -0,0 +1,2949 @@
+/** @file
+ Industry Standard Definitions of SMBIOS Table Specification v3.6.0.
+
+Copyright (c) 2006 - 2021, Intel Corporation. All rights reserved.
+(C) Copyright 2015-2017 Hewlett Packard Enterprise Development LP
+(C) Copyright 2015 - 2019 Hewlett Packard Enterprise Development LP
+Copyright (c) 2022, AMD Incorporated. All rights reserved.
+Copyright (c) 1985 - 2022, American Megatrends International LLC.
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __SMBIOS_STANDARD_H__
+#define __SMBIOS_STANDARD_H__
+
+///
+/// Reference SMBIOS 2.6, chapter 3.1.2.
+/// For v2.1 and later, handle values in the range 0FF00h to 0FFFFh are reserved for
+/// use by this specification.
+///
+#define SMBIOS_HANDLE_RESERVED_BEGIN 0xFF00
+
+///
+/// Reference SMBIOS 2.7, chapter 6.1.2.
+/// The UEFI Platform Initialization Specification reserves handle number FFFEh for its
+/// EFI_SMBIOS_PROTOCOL.Add() function to mean "assign an unused handle number automatically."
+/// This number is not used for any other purpose by the SMBIOS specification.
+///
+#define SMBIOS_HANDLE_PI_RESERVED 0xFFFE
+
+///
+/// Reference SMBIOS 2.6, chapter 3.1.3.
+/// Each text string is limited to 64 significant characters due to system MIF limitations.
+/// Reference SMBIOS 2.7, chapter 6.1.3.
+/// It will have no limit on the length of each individual text string.
+///
+#define SMBIOS_STRING_MAX_LENGTH 64
+
+//
+// The length of the entire structure table (including all strings) must be reported
+// in the Structure Table Length field of the SMBIOS Structure Table Entry Point,
+// which is a WORD field limited to 65,535 bytes.
+//
+#define SMBIOS_TABLE_MAX_LENGTH 0xFFFF
+
+//
+// For SMBIOS 3.0, Structure table maximum size in Entry Point structure is DWORD field limited to 0xFFFFFFFF bytes.
+//
+#define SMBIOS_3_0_TABLE_MAX_LENGTH 0xFFFFFFFF
+
+//
+// SMBIOS type macros which is according to SMBIOS 3.3.0 specification.
+//
+#define SMBIOS_TYPE_BIOS_INFORMATION 0
+#define SMBIOS_TYPE_SYSTEM_INFORMATION 1
+#define SMBIOS_TYPE_BASEBOARD_INFORMATION 2
+#define SMBIOS_TYPE_SYSTEM_ENCLOSURE 3
+#define SMBIOS_TYPE_PROCESSOR_INFORMATION 4
+#define SMBIOS_TYPE_MEMORY_CONTROLLER_INFORMATION 5
+#define SMBIOS_TYPE_MEMORY_MODULE_INFORMATON 6
+#define SMBIOS_TYPE_CACHE_INFORMATION 7
+#define SMBIOS_TYPE_PORT_CONNECTOR_INFORMATION 8
+#define SMBIOS_TYPE_SYSTEM_SLOTS 9
+#define SMBIOS_TYPE_ONBOARD_DEVICE_INFORMATION 10
+#define SMBIOS_TYPE_OEM_STRINGS 11
+#define SMBIOS_TYPE_SYSTEM_CONFIGURATION_OPTIONS 12
+#define SMBIOS_TYPE_BIOS_LANGUAGE_INFORMATION 13
+#define SMBIOS_TYPE_GROUP_ASSOCIATIONS 14
+#define SMBIOS_TYPE_SYSTEM_EVENT_LOG 15
+#define SMBIOS_TYPE_PHYSICAL_MEMORY_ARRAY 16
+#define SMBIOS_TYPE_MEMORY_DEVICE 17
+#define SMBIOS_TYPE_32BIT_MEMORY_ERROR_INFORMATION 18
+#define SMBIOS_TYPE_MEMORY_ARRAY_MAPPED_ADDRESS 19
+#define SMBIOS_TYPE_MEMORY_DEVICE_MAPPED_ADDRESS 20
+#define SMBIOS_TYPE_BUILT_IN_POINTING_DEVICE 21
+#define SMBIOS_TYPE_PORTABLE_BATTERY 22
+#define SMBIOS_TYPE_SYSTEM_RESET 23
+#define SMBIOS_TYPE_HARDWARE_SECURITY 24
+#define SMBIOS_TYPE_SYSTEM_POWER_CONTROLS 25
+#define SMBIOS_TYPE_VOLTAGE_PROBE 26
+#define SMBIOS_TYPE_COOLING_DEVICE 27
+#define SMBIOS_TYPE_TEMPERATURE_PROBE 28
+#define SMBIOS_TYPE_ELECTRICAL_CURRENT_PROBE 29
+#define SMBIOS_TYPE_OUT_OF_BAND_REMOTE_ACCESS 30
+#define SMBIOS_TYPE_BOOT_INTEGRITY_SERVICE 31
+#define SMBIOS_TYPE_SYSTEM_BOOT_INFORMATION 32
+#define SMBIOS_TYPE_64BIT_MEMORY_ERROR_INFORMATION 33
+#define SMBIOS_TYPE_MANAGEMENT_DEVICE 34
+#define SMBIOS_TYPE_MANAGEMENT_DEVICE_COMPONENT 35
+#define SMBIOS_TYPE_MANAGEMENT_DEVICE_THRESHOLD_DATA 36
+#define SMBIOS_TYPE_MEMORY_CHANNEL 37
+#define SMBIOS_TYPE_IPMI_DEVICE_INFORMATION 38
+#define SMBIOS_TYPE_SYSTEM_POWER_SUPPLY 39
+#define SMBIOS_TYPE_ADDITIONAL_INFORMATION 40
+#define SMBIOS_TYPE_ONBOARD_DEVICES_EXTENDED_INFORMATION 41
+#define SMBIOS_TYPE_MANAGEMENT_CONTROLLER_HOST_INTERFACE 42
+#define SMBIOS_TYPE_TPM_DEVICE 43
+#define SMBIOS_TYPE_PROCESSOR_ADDITIONAL_INFORMATION 44
+#define SMBIOS_TYPE_FIRMWARE_INVENTORY_INFORMATION 45
+#define SMBIOS_TYPE_STRING_PROPERTY_INFORMATION 46
+
+///
+/// Inactive type is added from SMBIOS 2.2. Reference SMBIOS 2.6, chapter 3.3.43.
+/// Upper-level software that interprets the SMBIOS structure-table should bypass an
+/// Inactive structure just like a structure type that the software does not recognize.
+///
+#define SMBIOS_TYPE_INACTIVE 0x007E
+
+///
+/// End-of-table type is added from SMBIOS 2.2. Reference SMBIOS 2.6, chapter 3.3.44.
+/// The end-of-table indicator is used in the last physical structure in a table
+///
+#define SMBIOS_TYPE_END_OF_TABLE 0x007F
+
+#define SMBIOS_OEM_BEGIN 128
+#define SMBIOS_OEM_END 255
+
+///
+/// Types 0 through 127 (7Fh) are reserved for and defined by this
+/// specification. Types 128 through 256 (80h to FFh) are available for system- and OEM-specific information.
+///
+typedef UINT8 SMBIOS_TYPE;
+
+///
+/// Specifies the structure's handle, a unique 16-bit number in the range 0 to 0FFFEh (for version
+/// 2.0) or 0 to 0FEFFh (for version 2.1 and later). The handle can be used with the Get SMBIOS
+/// Structure function to retrieve a specific structure; the handle numbers are not required to be
+/// contiguous. For v2.1 and later, handle values in the range 0FF00h to 0FFFFh are reserved for
+/// use by this specification.
+/// If the system configuration changes, a previously assigned handle might no longer exist.
+/// However once a handle has been assigned by the BIOS, the BIOS cannot re-assign that handle
+/// number to another structure.
+///
+typedef UINT16 SMBIOS_HANDLE;
+
+///
+/// Smbios Table Entry Point Structure.
+///
+#pragma pack(1)
+typedef struct {
+ UINT8 AnchorString[4];
+ UINT8 EntryPointStructureChecksum;
+ UINT8 EntryPointLength;
+ UINT8 MajorVersion;
+ UINT8 MinorVersion;
+ UINT16 MaxStructureSize;
+ UINT8 EntryPointRevision;
+ UINT8 FormattedArea[5];
+ UINT8 IntermediateAnchorString[5];
+ UINT8 IntermediateChecksum;
+ UINT16 TableLength;
+ UINT32 TableAddress;
+ UINT16 NumberOfSmbiosStructures;
+ UINT8 SmbiosBcdRevision;
+} SMBIOS_TABLE_ENTRY_POINT;
+
+typedef struct {
+ UINT8 AnchorString[5];
+ UINT8 EntryPointStructureChecksum;
+ UINT8 EntryPointLength;
+ UINT8 MajorVersion;
+ UINT8 MinorVersion;
+ UINT8 DocRev;
+ UINT8 EntryPointRevision;
+ UINT8 Reserved;
+ UINT32 TableMaximumSize;
+ UINT64 TableAddress;
+} SMBIOS_TABLE_3_0_ENTRY_POINT;
+
+///
+/// The Smbios structure header.
+///
+typedef struct {
+ SMBIOS_TYPE Type;
+ UINT8 Length;
+ SMBIOS_HANDLE Handle;
+} SMBIOS_STRUCTURE;
+
+///
+/// Text strings associated with a given SMBIOS structure are returned in the dmiStrucBuffer, appended directly after
+/// the formatted portion of the structure. This method of returning string information eliminates the need for
+/// application software to deal with pointers embedded in the SMBIOS structure. Each string is terminated with a null
+/// (00h) BYTE and the set of strings is terminated with an additional null (00h) BYTE. When the formatted portion of
+/// a SMBIOS structure references a string, it does so by specifying a non-zero string number within the structure's
+/// string-set. For example, if a string field contains 02h, it references the second string following the formatted portion
+/// of the SMBIOS structure. If a string field references no string, a null (0) is placed in that string field. If the
+/// formatted portion of the structure contains string-reference fields and all the string fields are set to 0 (no string
+/// references), the formatted section of the structure is followed by two null (00h) BYTES.
+///
+typedef UINT8 SMBIOS_TABLE_STRING;
+
+///
+/// BIOS Characteristics
+/// Defines which functions the BIOS supports. PCI, PCMCIA, Flash, etc.
+///
+typedef struct {
+ UINT32 Reserved : 2; ///< Bits 0-1.
+ UINT32 Unknown : 1;
+ UINT32 BiosCharacteristicsNotSupported : 1;
+ UINT32 IsaIsSupported : 1;
+ UINT32 McaIsSupported : 1;
+ UINT32 EisaIsSupported : 1;
+ UINT32 PciIsSupported : 1;
+ UINT32 PcmciaIsSupported : 1;
+ UINT32 PlugAndPlayIsSupported : 1;
+ UINT32 ApmIsSupported : 1;
+ UINT32 BiosIsUpgradable : 1;
+ UINT32 BiosShadowingAllowed : 1;
+ UINT32 VlVesaIsSupported : 1;
+ UINT32 EscdSupportIsAvailable : 1;
+ UINT32 BootFromCdIsSupported : 1;
+ UINT32 SelectableBootIsSupported : 1;
+ UINT32 RomBiosIsSocketed : 1;
+ UINT32 BootFromPcmciaIsSupported : 1;
+ UINT32 EDDSpecificationIsSupported : 1;
+ UINT32 JapaneseNecFloppyIsSupported : 1;
+ UINT32 JapaneseToshibaFloppyIsSupported : 1;
+ UINT32 Floppy525_360IsSupported : 1;
+ UINT32 Floppy525_12IsSupported : 1;
+ UINT32 Floppy35_720IsSupported : 1;
+ UINT32 Floppy35_288IsSupported : 1;
+ UINT32 PrintScreenIsSupported : 1;
+ UINT32 Keyboard8042IsSupported : 1;
+ UINT32 SerialIsSupported : 1;
+ UINT32 PrinterIsSupported : 1;
+ UINT32 CgaMonoIsSupported : 1;
+ UINT32 NecPc98 : 1;
+ UINT32 ReservedForVendor : 32; ///< Bits 32-63. Bits 32-47 reserved for BIOS vendor
+ ///< and bits 48-63 reserved for System Vendor.
+} MISC_BIOS_CHARACTERISTICS;
+
+///
+/// BIOS Characteristics Extension Byte 1.
+/// This information, available for SMBIOS version 2.1 and later, appears at offset 12h
+/// within the BIOS Information structure.
+///
+typedef struct {
+ UINT8 AcpiIsSupported : 1;
+ UINT8 UsbLegacyIsSupported : 1;
+ UINT8 AgpIsSupported : 1;
+ UINT8 I2OBootIsSupported : 1;
+ UINT8 Ls120BootIsSupported : 1;
+ UINT8 AtapiZipDriveBootIsSupported : 1;
+ UINT8 Boot1394IsSupported : 1;
+ UINT8 SmartBatteryIsSupported : 1;
+} MBCE_BIOS_RESERVED;
+
+///
+/// BIOS Characteristics Extension Byte 2.
+/// This information, available for SMBIOS version 2.3 and later, appears at offset 13h
+/// within the BIOS Information structure.
+///
+typedef struct {
+ UINT8 BiosBootSpecIsSupported : 1;
+ UINT8 FunctionKeyNetworkBootIsSupported : 1;
+ UINT8 TargetContentDistributionEnabled : 1;
+ UINT8 UefiSpecificationSupported : 1;
+ UINT8 VirtualMachineSupported : 1;
+ UINT8 ManufacturingModeSupported : 1;
+ UINT8 ManufacturingModeEnabled : 1;
+ UINT8 ExtensionByte2Reserved : 1;
+} MBCE_SYSTEM_RESERVED;
+
+///
+/// BIOS Characteristics Extension Bytes.
+///
+typedef struct {
+ MBCE_BIOS_RESERVED BiosReserved;
+ MBCE_SYSTEM_RESERVED SystemReserved;
+} MISC_BIOS_CHARACTERISTICS_EXTENSION;
+
+///
+/// Extended BIOS ROM size.
+///
+typedef struct {
+ UINT16 Size : 14;
+ UINT16 Unit : 2;
+} EXTENDED_BIOS_ROM_SIZE;
+
+///
+/// BIOS Information (Type 0).
+///
+typedef struct {
+ SMBIOS_STRUCTURE Hdr;
+ SMBIOS_TABLE_STRING Vendor;
+ SMBIOS_TABLE_STRING BiosVersion;
+ UINT16 BiosSegment;
+ SMBIOS_TABLE_STRING BiosReleaseDate;
+ UINT8 BiosSize;
+ MISC_BIOS_CHARACTERISTICS BiosCharacteristics;
+ UINT8 BIOSCharacteristicsExtensionBytes[2];
+ UINT8 SystemBiosMajorRelease;
+ UINT8 SystemBiosMinorRelease;
+ UINT8 EmbeddedControllerFirmwareMajorRelease;
+ UINT8 EmbeddedControllerFirmwareMinorRelease;
+ //
+ // Add for smbios 3.1.0
+ //
+ EXTENDED_BIOS_ROM_SIZE ExtendedBiosSize;
+} SMBIOS_TABLE_TYPE0;
+
+///
+/// System Wake-up Type.
+///
+typedef enum {
+ SystemWakeupTypeReserved = 0x00,
+ SystemWakeupTypeOther = 0x01,
+ SystemWakeupTypeUnknown = 0x02,
+ SystemWakeupTypeApmTimer = 0x03,
+ SystemWakeupTypeModemRing = 0x04,
+ SystemWakeupTypeLanRemote = 0x05,
+ SystemWakeupTypePowerSwitch = 0x06,
+ SystemWakeupTypePciPme = 0x07,
+ SystemWakeupTypeAcPowerRestored = 0x08
+} MISC_SYSTEM_WAKEUP_TYPE;
+
+///
+/// System Information (Type 1).
+///
+/// The information in this structure defines attributes of the overall system and is
+/// intended to be associated with the Component ID group of the system's MIF.
+/// An SMBIOS implementation is associated with a single system instance and contains
+/// one and only one System Information (Type 1) structure.
+///
+typedef struct {
+ SMBIOS_STRUCTURE Hdr;
+ SMBIOS_TABLE_STRING Manufacturer;
+ SMBIOS_TABLE_STRING ProductName;
+ SMBIOS_TABLE_STRING Version;
+ SMBIOS_TABLE_STRING SerialNumber;
+ GUID Uuid;
+ UINT8 WakeUpType; ///< The enumeration value from MISC_SYSTEM_WAKEUP_TYPE.
+ SMBIOS_TABLE_STRING SKUNumber;
+ SMBIOS_TABLE_STRING Family;
+} SMBIOS_TABLE_TYPE1;
+
+///
+/// Base Board - Feature Flags.
+///
+typedef struct {
+ UINT8 Motherboard : 1;
+ UINT8 RequiresDaughterCard : 1;
+ UINT8 Removable : 1;
+ UINT8 Replaceable : 1;
+ UINT8 HotSwappable : 1;
+ UINT8 Reserved : 3;
+} BASE_BOARD_FEATURE_FLAGS;
+
+///
+/// Base Board - Board Type.
+///
+typedef enum {
+ BaseBoardTypeUnknown = 0x1,
+ BaseBoardTypeOther = 0x2,
+ BaseBoardTypeServerBlade = 0x3,
+ BaseBoardTypeConnectivitySwitch = 0x4,
+ BaseBoardTypeSystemManagementModule = 0x5,
+ BaseBoardTypeProcessorModule = 0x6,
+ BaseBoardTypeIOModule = 0x7,
+ BaseBoardTypeMemoryModule = 0x8,
+ BaseBoardTypeDaughterBoard = 0x9,
+ BaseBoardTypeMotherBoard = 0xA,
+ BaseBoardTypeProcessorMemoryModule = 0xB,
+ BaseBoardTypeProcessorIOModule = 0xC,
+ BaseBoardTypeInterconnectBoard = 0xD
+} BASE_BOARD_TYPE;
+
+///
+/// Base Board (or Module) Information (Type 2).
+///
+/// The information in this structure defines attributes of a system baseboard -
+/// for example a motherboard, planar, or server blade or other standard system module.
+///
+typedef struct {
+ SMBIOS_STRUCTURE Hdr;
+ SMBIOS_TABLE_STRING Manufacturer;
+ SMBIOS_TABLE_STRING ProductName;
+ SMBIOS_TABLE_STRING Version;
+ SMBIOS_TABLE_STRING SerialNumber;
+ SMBIOS_TABLE_STRING AssetTag;
+ BASE_BOARD_FEATURE_FLAGS FeatureFlag;
+ SMBIOS_TABLE_STRING LocationInChassis;
+ UINT16 ChassisHandle;
+ UINT8 BoardType; ///< The enumeration value from BASE_BOARD_TYPE.
+ UINT8 NumberOfContainedObjectHandles;
+ UINT16 ContainedObjectHandles[1];
+} SMBIOS_TABLE_TYPE2;
+
+///
+/// System Enclosure or Chassis Types
+///
+typedef enum {
+ MiscChassisTypeOther = 0x01,
+ MiscChassisTypeUnknown = 0x02,
+ MiscChassisTypeDeskTop = 0x03,
+ MiscChassisTypeLowProfileDesktop = 0x04,
+ MiscChassisTypePizzaBox = 0x05,
+ MiscChassisTypeMiniTower = 0x06,
+ MiscChassisTypeTower = 0x07,
+ MiscChassisTypePortable = 0x08,
+ MiscChassisTypeLapTop = 0x09,
+ MiscChassisTypeNotebook = 0x0A,
+ MiscChassisTypeHandHeld = 0x0B,
+ MiscChassisTypeDockingStation = 0x0C,
+ MiscChassisTypeAllInOne = 0x0D,
+ MiscChassisTypeSubNotebook = 0x0E,
+ MiscChassisTypeSpaceSaving = 0x0F,
+ MiscChassisTypeLunchBox = 0x10,
+ MiscChassisTypeMainServerChassis = 0x11,
+ MiscChassisTypeExpansionChassis = 0x12,
+ MiscChassisTypeSubChassis = 0x13,
+ MiscChassisTypeBusExpansionChassis = 0x14,
+ MiscChassisTypePeripheralChassis = 0x15,
+ MiscChassisTypeRaidChassis = 0x16,
+ MiscChassisTypeRackMountChassis = 0x17,
+ MiscChassisTypeSealedCasePc = 0x18,
+ MiscChassisMultiSystemChassis = 0x19,
+ MiscChassisCompactPCI = 0x1A,
+ MiscChassisAdvancedTCA = 0x1B,
+ MiscChassisBlade = 0x1C,
+ MiscChassisBladeEnclosure = 0x1D,
+ MiscChassisTablet = 0x1E,
+ MiscChassisConvertible = 0x1F,
+ MiscChassisDetachable = 0x20,
+ MiscChassisIoTGateway = 0x21,
+ MiscChassisEmbeddedPc = 0x22,
+ MiscChassisMiniPc = 0x23,
+ MiscChassisStickPc = 0x24
+} MISC_CHASSIS_TYPE;
+
+///
+/// System Enclosure or Chassis States .
+///
+typedef enum {
+ ChassisStateOther = 0x01,
+ ChassisStateUnknown = 0x02,
+ ChassisStateSafe = 0x03,
+ ChassisStateWarning = 0x04,
+ ChassisStateCritical = 0x05,
+ ChassisStateNonRecoverable = 0x06
+} MISC_CHASSIS_STATE;
+
+///
+/// System Enclosure or Chassis Security Status.
+///
+typedef enum {
+ ChassisSecurityStatusOther = 0x01,
+ ChassisSecurityStatusUnknown = 0x02,
+ ChassisSecurityStatusNone = 0x03,
+ ChassisSecurityStatusExternalInterfaceLockedOut = 0x04,
+ ChassisSecurityStatusExternalInterfaceLockedEnabled = 0x05
+} MISC_CHASSIS_SECURITY_STATE;
+
+///
+/// Contained Element record
+///
+typedef struct {
+ UINT8 ContainedElementType;
+ UINT8 ContainedElementMinimum;
+ UINT8 ContainedElementMaximum;
+} CONTAINED_ELEMENT;
+
+///
+/// System Enclosure or Chassis (Type 3).
+///
+/// The information in this structure defines attributes of the system's mechanical enclosure(s).
+/// For example, if a system included a separate enclosure for its peripheral devices,
+/// two structures would be returned: one for the main, system enclosure and the second for
+/// the peripheral device enclosure. The additions to this structure in v2.1 of this specification
+/// support the population of the CIM_Chassis class.
+///
+typedef struct {
+ SMBIOS_STRUCTURE Hdr;
+ SMBIOS_TABLE_STRING Manufacturer;
+ UINT8 Type;
+ SMBIOS_TABLE_STRING Version;
+ SMBIOS_TABLE_STRING SerialNumber;
+ SMBIOS_TABLE_STRING AssetTag;
+ UINT8 BootupState; ///< The enumeration value from MISC_CHASSIS_STATE.
+ UINT8 PowerSupplyState; ///< The enumeration value from MISC_CHASSIS_STATE.
+ UINT8 ThermalState; ///< The enumeration value from MISC_CHASSIS_STATE.
+ UINT8 SecurityStatus; ///< The enumeration value from MISC_CHASSIS_SECURITY_STATE.
+ UINT8 OemDefined[4];
+ UINT8 Height;
+ UINT8 NumberofPowerCords;
+ UINT8 ContainedElementCount;
+ UINT8 ContainedElementRecordLength;
+ //
+ // Can have 0 to (ContainedElementCount * ContainedElementRecordLength) contained elements
+ //
+ CONTAINED_ELEMENT ContainedElements[1];
+ //
+ // Add for smbios 2.7
+ //
+ // Since ContainedElements has a variable number of entries, must not define SKUNumber in
+ // the structure. Need to reference it by starting at offset 0x15 and adding
+ // (ContainedElementCount * ContainedElementRecordLength) bytes.
+ //
+ // SMBIOS_TABLE_STRING SKUNumber;
+} SMBIOS_TABLE_TYPE3;
+
+///
+/// Processor Information - Processor Type.
+///
+typedef enum {
+ ProcessorOther = 0x01,
+ ProcessorUnknown = 0x02,
+ CentralProcessor = 0x03,
+ MathProcessor = 0x04,
+ DspProcessor = 0x05,
+ VideoProcessor = 0x06
+} PROCESSOR_TYPE_DATA;
+
+///
+/// Processor Information - Processor Family.
+///
+typedef enum {
+ ProcessorFamilyOther = 0x01,
+ ProcessorFamilyUnknown = 0x02,
+ ProcessorFamily8086 = 0x03,
+ ProcessorFamily80286 = 0x04,
+ ProcessorFamilyIntel386 = 0x05,
+ ProcessorFamilyIntel486 = 0x06,
+ ProcessorFamily8087 = 0x07,
+ ProcessorFamily80287 = 0x08,
+ ProcessorFamily80387 = 0x09,
+ ProcessorFamily80487 = 0x0A,
+ ProcessorFamilyPentium = 0x0B,
+ ProcessorFamilyPentiumPro = 0x0C,
+ ProcessorFamilyPentiumII = 0x0D,
+ ProcessorFamilyPentiumMMX = 0x0E,
+ ProcessorFamilyCeleron = 0x0F,
+ ProcessorFamilyPentiumIIXeon = 0x10,
+ ProcessorFamilyPentiumIII = 0x11,
+ ProcessorFamilyM1 = 0x12,
+ ProcessorFamilyM2 = 0x13,
+ ProcessorFamilyIntelCeleronM = 0x14,
+ ProcessorFamilyIntelPentium4Ht = 0x15,
+ ProcessorFamilyAmdDuron = 0x18,
+ ProcessorFamilyK5 = 0x19,
+ ProcessorFamilyK6 = 0x1A,
+ ProcessorFamilyK6_2 = 0x1B,
+ ProcessorFamilyK6_3 = 0x1C,
+ ProcessorFamilyAmdAthlon = 0x1D,
+ ProcessorFamilyAmd29000 = 0x1E,
+ ProcessorFamilyK6_2Plus = 0x1F,
+ ProcessorFamilyPowerPC = 0x20,
+ ProcessorFamilyPowerPC601 = 0x21,
+ ProcessorFamilyPowerPC603 = 0x22,
+ ProcessorFamilyPowerPC603Plus = 0x23,
+ ProcessorFamilyPowerPC604 = 0x24,
+ ProcessorFamilyPowerPC620 = 0x25,
+ ProcessorFamilyPowerPCx704 = 0x26,
+ ProcessorFamilyPowerPC750 = 0x27,
+ ProcessorFamilyIntelCoreDuo = 0x28,
+ ProcessorFamilyIntelCoreDuoMobile = 0x29,
+ ProcessorFamilyIntelCoreSoloMobile = 0x2A,
+ ProcessorFamilyIntelAtom = 0x2B,
+ ProcessorFamilyIntelCoreM = 0x2C,
+ ProcessorFamilyIntelCorem3 = 0x2D,
+ ProcessorFamilyIntelCorem5 = 0x2E,
+ ProcessorFamilyIntelCorem7 = 0x2F,
+ ProcessorFamilyAlpha = 0x30,
+ ProcessorFamilyAlpha21064 = 0x31,
+ ProcessorFamilyAlpha21066 = 0x32,
+ ProcessorFamilyAlpha21164 = 0x33,
+ ProcessorFamilyAlpha21164PC = 0x34,
+ ProcessorFamilyAlpha21164a = 0x35,
+ ProcessorFamilyAlpha21264 = 0x36,
+ ProcessorFamilyAlpha21364 = 0x37,
+ ProcessorFamilyAmdTurionIIUltraDualCoreMobileM = 0x38,
+ ProcessorFamilyAmdTurionIIDualCoreMobileM = 0x39,
+ ProcessorFamilyAmdAthlonIIDualCoreM = 0x3A,
+ ProcessorFamilyAmdOpteron6100Series = 0x3B,
+ ProcessorFamilyAmdOpteron4100Series = 0x3C,
+ ProcessorFamilyAmdOpteron6200Series = 0x3D,
+ ProcessorFamilyAmdOpteron4200Series = 0x3E,
+ ProcessorFamilyAmdFxSeries = 0x3F,
+ ProcessorFamilyMips = 0x40,
+ ProcessorFamilyMIPSR4000 = 0x41,
+ ProcessorFamilyMIPSR4200 = 0x42,
+ ProcessorFamilyMIPSR4400 = 0x43,
+ ProcessorFamilyMIPSR4600 = 0x44,
+ ProcessorFamilyMIPSR10000 = 0x45,
+ ProcessorFamilyAmdCSeries = 0x46,
+ ProcessorFamilyAmdESeries = 0x47,
+ ProcessorFamilyAmdASeries = 0x48, ///< SMBIOS spec 2.8.0 updated the name
+ ProcessorFamilyAmdGSeries = 0x49,
+ ProcessorFamilyAmdZSeries = 0x4A,
+ ProcessorFamilyAmdRSeries = 0x4B,
+ ProcessorFamilyAmdOpteron4300 = 0x4C,
+ ProcessorFamilyAmdOpteron6300 = 0x4D,
+ ProcessorFamilyAmdOpteron3300 = 0x4E,
+ ProcessorFamilyAmdFireProSeries = 0x4F,
+ ProcessorFamilySparc = 0x50,
+ ProcessorFamilySuperSparc = 0x51,
+ ProcessorFamilymicroSparcII = 0x52,
+ ProcessorFamilymicroSparcIIep = 0x53,
+ ProcessorFamilyUltraSparc = 0x54,
+ ProcessorFamilyUltraSparcII = 0x55,
+ ProcessorFamilyUltraSparcIii = 0x56,
+ ProcessorFamilyUltraSparcIII = 0x57,
+ ProcessorFamilyUltraSparcIIIi = 0x58,
+ ProcessorFamily68040 = 0x60,
+ ProcessorFamily68xxx = 0x61,
+ ProcessorFamily68000 = 0x62,
+ ProcessorFamily68010 = 0x63,
+ ProcessorFamily68020 = 0x64,
+ ProcessorFamily68030 = 0x65,
+ ProcessorFamilyAmdAthlonX4QuadCore = 0x66,
+ ProcessorFamilyAmdOpteronX1000Series = 0x67,
+ ProcessorFamilyAmdOpteronX2000Series = 0x68,
+ ProcessorFamilyAmdOpteronASeries = 0x69,
+ ProcessorFamilyAmdOpteronX3000Series = 0x6A,
+ ProcessorFamilyAmdZen = 0x6B,
+ ProcessorFamilyHobbit = 0x70,
+ ProcessorFamilyCrusoeTM5000 = 0x78,
+ ProcessorFamilyCrusoeTM3000 = 0x79,
+ ProcessorFamilyEfficeonTM8000 = 0x7A,
+ ProcessorFamilyWeitek = 0x80,
+ ProcessorFamilyItanium = 0x82,
+ ProcessorFamilyAmdAthlon64 = 0x83,
+ ProcessorFamilyAmdOpteron = 0x84,
+ ProcessorFamilyAmdSempron = 0x85,
+ ProcessorFamilyAmdTurion64Mobile = 0x86,
+ ProcessorFamilyDualCoreAmdOpteron = 0x87,
+ ProcessorFamilyAmdAthlon64X2DualCore = 0x88,
+ ProcessorFamilyAmdTurion64X2Mobile = 0x89,
+ ProcessorFamilyQuadCoreAmdOpteron = 0x8A,
+ ProcessorFamilyThirdGenerationAmdOpteron = 0x8B,
+ ProcessorFamilyAmdPhenomFxQuadCore = 0x8C,
+ ProcessorFamilyAmdPhenomX4QuadCore = 0x8D,
+ ProcessorFamilyAmdPhenomX2DualCore = 0x8E,
+ ProcessorFamilyAmdAthlonX2DualCore = 0x8F,
+ ProcessorFamilyPARISC = 0x90,
+ ProcessorFamilyPaRisc8500 = 0x91,
+ ProcessorFamilyPaRisc8000 = 0x92,
+ ProcessorFamilyPaRisc7300LC = 0x93,
+ ProcessorFamilyPaRisc7200 = 0x94,
+ ProcessorFamilyPaRisc7100LC = 0x95,
+ ProcessorFamilyPaRisc7100 = 0x96,
+ ProcessorFamilyV30 = 0xA0,
+ ProcessorFamilyQuadCoreIntelXeon3200Series = 0xA1,
+ ProcessorFamilyDualCoreIntelXeon3000Series = 0xA2,
+ ProcessorFamilyQuadCoreIntelXeon5300Series = 0xA3,
+ ProcessorFamilyDualCoreIntelXeon5100Series = 0xA4,
+ ProcessorFamilyDualCoreIntelXeon5000Series = 0xA5,
+ ProcessorFamilyDualCoreIntelXeonLV = 0xA6,
+ ProcessorFamilyDualCoreIntelXeonULV = 0xA7,
+ ProcessorFamilyDualCoreIntelXeon7100Series = 0xA8,
+ ProcessorFamilyQuadCoreIntelXeon5400Series = 0xA9,
+ ProcessorFamilyQuadCoreIntelXeon = 0xAA,
+ ProcessorFamilyDualCoreIntelXeon5200Series = 0xAB,
+ ProcessorFamilyDualCoreIntelXeon7200Series = 0xAC,
+ ProcessorFamilyQuadCoreIntelXeon7300Series = 0xAD,
+ ProcessorFamilyQuadCoreIntelXeon7400Series = 0xAE,
+ ProcessorFamilyMultiCoreIntelXeon7400Series = 0xAF,
+ ProcessorFamilyPentiumIIIXeon = 0xB0,
+ ProcessorFamilyPentiumIIISpeedStep = 0xB1,
+ ProcessorFamilyPentium4 = 0xB2,
+ ProcessorFamilyIntelXeon = 0xB3,
+ ProcessorFamilyAS400 = 0xB4,
+ ProcessorFamilyIntelXeonMP = 0xB5,
+ ProcessorFamilyAMDAthlonXP = 0xB6,
+ ProcessorFamilyAMDAthlonMP = 0xB7,
+ ProcessorFamilyIntelItanium2 = 0xB8,
+ ProcessorFamilyIntelPentiumM = 0xB9,
+ ProcessorFamilyIntelCeleronD = 0xBA,
+ ProcessorFamilyIntelPentiumD = 0xBB,
+ ProcessorFamilyIntelPentiumEx = 0xBC,
+ ProcessorFamilyIntelCoreSolo = 0xBD, ///< SMBIOS spec 2.6 updated this value
+ ProcessorFamilyReserved = 0xBE,
+ ProcessorFamilyIntelCore2 = 0xBF,
+ ProcessorFamilyIntelCore2Solo = 0xC0,
+ ProcessorFamilyIntelCore2Extreme = 0xC1,
+ ProcessorFamilyIntelCore2Quad = 0xC2,
+ ProcessorFamilyIntelCore2ExtremeMobile = 0xC3,
+ ProcessorFamilyIntelCore2DuoMobile = 0xC4,
+ ProcessorFamilyIntelCore2SoloMobile = 0xC5,
+ ProcessorFamilyIntelCoreI7 = 0xC6,
+ ProcessorFamilyDualCoreIntelCeleron = 0xC7,
+ ProcessorFamilyIBM390 = 0xC8,
+ ProcessorFamilyG4 = 0xC9,
+ ProcessorFamilyG5 = 0xCA,
+ ProcessorFamilyG6 = 0xCB,
+ ProcessorFamilyzArchitecture = 0xCC,
+ ProcessorFamilyIntelCoreI5 = 0xCD,
+ ProcessorFamilyIntelCoreI3 = 0xCE,
+ ProcessorFamilyIntelCoreI9 = 0xCF,
+ ProcessorFamilyViaC7M = 0xD2,
+ ProcessorFamilyViaC7D = 0xD3,
+ ProcessorFamilyViaC7 = 0xD4,
+ ProcessorFamilyViaEden = 0xD5,
+ ProcessorFamilyMultiCoreIntelXeon = 0xD6,
+ ProcessorFamilyDualCoreIntelXeon3Series = 0xD7,
+ ProcessorFamilyQuadCoreIntelXeon3Series = 0xD8,
+ ProcessorFamilyViaNano = 0xD9,
+ ProcessorFamilyDualCoreIntelXeon5Series = 0xDA,
+ ProcessorFamilyQuadCoreIntelXeon5Series = 0xDB,
+ ProcessorFamilyDualCoreIntelXeon7Series = 0xDD,
+ ProcessorFamilyQuadCoreIntelXeon7Series = 0xDE,
+ ProcessorFamilyMultiCoreIntelXeon7Series = 0xDF,
+ ProcessorFamilyMultiCoreIntelXeon3400Series = 0xE0,
+ ProcessorFamilyAmdOpteron3000Series = 0xE4,
+ ProcessorFamilyAmdSempronII = 0xE5,
+ ProcessorFamilyEmbeddedAmdOpteronQuadCore = 0xE6,
+ ProcessorFamilyAmdPhenomTripleCore = 0xE7,
+ ProcessorFamilyAmdTurionUltraDualCoreMobile = 0xE8,
+ ProcessorFamilyAmdTurionDualCoreMobile = 0xE9,
+ ProcessorFamilyAmdAthlonDualCore = 0xEA,
+ ProcessorFamilyAmdSempronSI = 0xEB,
+ ProcessorFamilyAmdPhenomII = 0xEC,
+ ProcessorFamilyAmdAthlonII = 0xED,
+ ProcessorFamilySixCoreAmdOpteron = 0xEE,
+ ProcessorFamilyAmdSempronM = 0xEF,
+ ProcessorFamilyi860 = 0xFA,
+ ProcessorFamilyi960 = 0xFB,
+ ProcessorFamilyIndicatorFamily2 = 0xFE,
+ ProcessorFamilyReserved1 = 0xFF
+} PROCESSOR_FAMILY_DATA;
+
+///
+/// Processor Information2 - Processor Family2.
+///
+typedef enum {
+ ProcessorFamilyARMv7 = 0x0100,
+ ProcessorFamilyARMv8 = 0x0101,
+ ProcessorFamilyARMv9 = 0x0102,
+ ProcessorFamilySH3 = 0x0104,
+ ProcessorFamilySH4 = 0x0105,
+ ProcessorFamilyARM = 0x0118,
+ ProcessorFamilyStrongARM = 0x0119,
+ ProcessorFamily6x86 = 0x012C,
+ ProcessorFamilyMediaGX = 0x012D,
+ ProcessorFamilyMII = 0x012E,
+ ProcessorFamilyWinChip = 0x0140,
+ ProcessorFamilyDSP = 0x015E,
+ ProcessorFamilyVideoProcessor = 0x01F4,
+ ProcessorFamilyRiscvRV32 = 0x0200,
+ ProcessorFamilyRiscVRV64 = 0x0201,
+ ProcessorFamilyRiscVRV128 = 0x0202,
+ ProcessorFamilyLoongArch = 0x0258,
+ ProcessorFamilyLoongson1 = 0x0259,
+ ProcessorFamilyLoongson2 = 0x025A,
+ ProcessorFamilyLoongson3 = 0x025B,
+ ProcessorFamilyLoongson2K = 0x025C,
+ ProcessorFamilyLoongson3A = 0x025D,
+ ProcessorFamilyLoongson3B = 0x025E,
+ ProcessorFamilyLoongson3C = 0x025F,
+ ProcessorFamilyLoongson3D = 0x0260,
+ ProcessorFamilyLoongson3E = 0x0261,
+ ProcessorFamilyDualCoreLoongson2K = 0x0262,
+ ProcessorFamilyQuadCoreLoongson3A = 0x026C,
+ ProcessorFamilyMultiCoreLoongson3A = 0x026D,
+ ProcessorFamilyQuadCoreLoongson3B = 0x026E,
+ ProcessorFamilyMultiCoreLoongson3B = 0x026F,
+ ProcessorFamilyMultiCoreLoongson3C = 0x0270,
+ ProcessorFamilyMultiCoreLoongson3D = 0x0271
+} PROCESSOR_FAMILY2_DATA;
+
+///
+/// Processor Information - Voltage.
+///
+typedef struct {
+ UINT8 ProcessorVoltageCapability5V : 1;
+ UINT8 ProcessorVoltageCapability3_3V : 1;
+ UINT8 ProcessorVoltageCapability2_9V : 1;
+ UINT8 ProcessorVoltageCapabilityReserved : 1; ///< Bit 3, must be zero.
+ UINT8 ProcessorVoltageReserved : 3; ///< Bits 4-6, must be zero.
+ UINT8 ProcessorVoltageIndicateLegacy : 1;
+} PROCESSOR_VOLTAGE;
+
+///
+/// Processor Information - Processor Upgrade.
+///
+typedef enum {
+ ProcessorUpgradeOther = 0x01,
+ ProcessorUpgradeUnknown = 0x02,
+ ProcessorUpgradeDaughterBoard = 0x03,
+ ProcessorUpgradeZIFSocket = 0x04,
+ ProcessorUpgradePiggyBack = 0x05, ///< Replaceable.
+ ProcessorUpgradeNone = 0x06,
+ ProcessorUpgradeLIFSocket = 0x07,
+ ProcessorUpgradeSlot1 = 0x08,
+ ProcessorUpgradeSlot2 = 0x09,
+ ProcessorUpgrade370PinSocket = 0x0A,
+ ProcessorUpgradeSlotA = 0x0B,
+ ProcessorUpgradeSlotM = 0x0C,
+ ProcessorUpgradeSocket423 = 0x0D,
+ ProcessorUpgradeSocketA = 0x0E, ///< Socket 462.
+ ProcessorUpgradeSocket478 = 0x0F,
+ ProcessorUpgradeSocket754 = 0x10,
+ ProcessorUpgradeSocket940 = 0x11,
+ ProcessorUpgradeSocket939 = 0x12,
+ ProcessorUpgradeSocketmPGA604 = 0x13,
+ ProcessorUpgradeSocketLGA771 = 0x14,
+ ProcessorUpgradeSocketLGA775 = 0x15,
+ ProcessorUpgradeSocketS1 = 0x16,
+ ProcessorUpgradeAM2 = 0x17,
+ ProcessorUpgradeF1207 = 0x18,
+ ProcessorSocketLGA1366 = 0x19,
+ ProcessorUpgradeSocketG34 = 0x1A,
+ ProcessorUpgradeSocketAM3 = 0x1B,
+ ProcessorUpgradeSocketC32 = 0x1C,
+ ProcessorUpgradeSocketLGA1156 = 0x1D,
+ ProcessorUpgradeSocketLGA1567 = 0x1E,
+ ProcessorUpgradeSocketPGA988A = 0x1F,
+ ProcessorUpgradeSocketBGA1288 = 0x20,
+ ProcessorUpgradeSocketrPGA988B = 0x21,
+ ProcessorUpgradeSocketBGA1023 = 0x22,
+ ProcessorUpgradeSocketBGA1224 = 0x23,
+ ProcessorUpgradeSocketLGA1155 = 0x24, ///< SMBIOS spec 2.8.0 updated the name
+ ProcessorUpgradeSocketLGA1356 = 0x25,
+ ProcessorUpgradeSocketLGA2011 = 0x26,
+ ProcessorUpgradeSocketFS1 = 0x27,
+ ProcessorUpgradeSocketFS2 = 0x28,
+ ProcessorUpgradeSocketFM1 = 0x29,
+ ProcessorUpgradeSocketFM2 = 0x2A,
+ ProcessorUpgradeSocketLGA2011_3 = 0x2B,
+ ProcessorUpgradeSocketLGA1356_3 = 0x2C,
+ ProcessorUpgradeSocketLGA1150 = 0x2D,
+ ProcessorUpgradeSocketBGA1168 = 0x2E,
+ ProcessorUpgradeSocketBGA1234 = 0x2F,
+ ProcessorUpgradeSocketBGA1364 = 0x30,
+ ProcessorUpgradeSocketAM4 = 0x31,
+ ProcessorUpgradeSocketLGA1151 = 0x32,
+ ProcessorUpgradeSocketBGA1356 = 0x33,
+ ProcessorUpgradeSocketBGA1440 = 0x34,
+ ProcessorUpgradeSocketBGA1515 = 0x35,
+ ProcessorUpgradeSocketLGA3647_1 = 0x36,
+ ProcessorUpgradeSocketSP3 = 0x37,
+ ProcessorUpgradeSocketSP3r2 = 0x38,
+ ProcessorUpgradeSocketLGA2066 = 0x39,
+ ProcessorUpgradeSocketBGA1392 = 0x3A,
+ ProcessorUpgradeSocketBGA1510 = 0x3B,
+ ProcessorUpgradeSocketBGA1528 = 0x3C,
+ ProcessorUpgradeSocketLGA4189 = 0x3D,
+ ProcessorUpgradeSocketLGA1200 = 0x3E,
+ ProcessorUpgradeSocketLGA4677 = 0x3F,
+ ProcessorUpgradeSocketLGA1700 = 0x40,
+ ProcessorUpgradeSocketBGA1744 = 0x41,
+ ProcessorUpgradeSocketBGA1781 = 0x42,
+ ProcessorUpgradeSocketBGA1211 = 0x43,
+ ProcessorUpgradeSocketBGA2422 = 0x44,
+ ProcessorUpgradeSocketLGA1211 = 0x45,
+ ProcessorUpgradeSocketLGA2422 = 0x46,
+ ProcessorUpgradeSocketLGA5773 = 0x47,
+ ProcessorUpgradeSocketBGA5773 = 0x48
+} PROCESSOR_UPGRADE;
+
+///
+/// Processor ID Field Description
+///
+typedef struct {
+ UINT32 ProcessorSteppingId : 4;
+ UINT32 ProcessorModel : 4;
+ UINT32 ProcessorFamily : 4;
+ UINT32 ProcessorType : 2;
+ UINT32 ProcessorReserved1 : 2;
+ UINT32 ProcessorXModel : 4;
+ UINT32 ProcessorXFamily : 8;
+ UINT32 ProcessorReserved2 : 4;
+} PROCESSOR_SIGNATURE;
+
+typedef struct {
+ UINT32 ProcessorFpu : 1;
+ UINT32 ProcessorVme : 1;
+ UINT32 ProcessorDe : 1;
+ UINT32 ProcessorPse : 1;
+ UINT32 ProcessorTsc : 1;
+ UINT32 ProcessorMsr : 1;
+ UINT32 ProcessorPae : 1;
+ UINT32 ProcessorMce : 1;
+ UINT32 ProcessorCx8 : 1;
+ UINT32 ProcessorApic : 1;
+ UINT32 ProcessorReserved1 : 1;
+ UINT32 ProcessorSep : 1;
+ UINT32 ProcessorMtrr : 1;
+ UINT32 ProcessorPge : 1;
+ UINT32 ProcessorMca : 1;
+ UINT32 ProcessorCmov : 1;
+ UINT32 ProcessorPat : 1;
+ UINT32 ProcessorPse36 : 1;
+ UINT32 ProcessorPsn : 1;
+ UINT32 ProcessorClfsh : 1;
+ UINT32 ProcessorReserved2 : 1;
+ UINT32 ProcessorDs : 1;
+ UINT32 ProcessorAcpi : 1;
+ UINT32 ProcessorMmx : 1;
+ UINT32 ProcessorFxsr : 1;
+ UINT32 ProcessorSse : 1;
+ UINT32 ProcessorSse2 : 1;
+ UINT32 ProcessorSs : 1;
+ UINT32 ProcessorReserved3 : 1;
+ UINT32 ProcessorTm : 1;
+ UINT32 ProcessorReserved4 : 2;
+} PROCESSOR_FEATURE_FLAGS;
+
+typedef struct {
+ UINT16 ProcessorReserved1 : 1;
+ UINT16 ProcessorUnknown : 1;
+ UINT16 Processor64BitCapable : 1;
+ UINT16 ProcessorMultiCore : 1;
+ UINT16 ProcessorHardwareThread : 1;
+ UINT16 ProcessorExecuteProtection : 1;
+ UINT16 ProcessorEnhancedVirtualization : 1;
+ UINT16 ProcessorPowerPerformanceCtrl : 1;
+ UINT16 Processor128BitCapable : 1;
+ UINT16 ProcessorArm64SocId : 1;
+ UINT16 ProcessorReserved2 : 6;
+} PROCESSOR_CHARACTERISTIC_FLAGS;
+
+///
+/// Processor Information - Status
+///
+typedef union {
+ struct {
+ UINT8 CpuStatus : 3; ///< Indicates the status of the processor.
+ UINT8 Reserved1 : 3; ///< Reserved for future use. Must be set to zero.
+ UINT8 SocketPopulated : 1; ///< Indicates if the processor socket is populated or not.
+ UINT8 Reserved2 : 1; ///< Reserved for future use. Must be set to zero.
+ } Bits;
+ UINT8 Data;
+} PROCESSOR_STATUS_DATA;
+
+typedef struct {
+ PROCESSOR_SIGNATURE Signature;
+ PROCESSOR_FEATURE_FLAGS FeatureFlags;
+} PROCESSOR_ID_DATA;
+
+///
+/// Processor Information (Type 4).
+///
+/// The information in this structure defines the attributes of a single processor;
+/// a separate structure instance is provided for each system processor socket/slot.
+/// For example, a system with an IntelDX2 processor would have a single
+/// structure instance, while a system with an IntelSX2 processor would have a structure
+/// to describe the main CPU, and a second structure to describe the 80487 co-processor.
+///
+typedef struct {
+ SMBIOS_STRUCTURE Hdr;
+ SMBIOS_TABLE_STRING Socket;
+ UINT8 ProcessorType; ///< The enumeration value from PROCESSOR_TYPE_DATA.
+ UINT8 ProcessorFamily; ///< The enumeration value from PROCESSOR_FAMILY_DATA.
+ SMBIOS_TABLE_STRING ProcessorManufacturer;
+ PROCESSOR_ID_DATA ProcessorId;
+ SMBIOS_TABLE_STRING ProcessorVersion;
+ PROCESSOR_VOLTAGE Voltage;
+ UINT16 ExternalClock;
+ UINT16 MaxSpeed;
+ UINT16 CurrentSpeed;
+ UINT8 Status;
+ UINT8 ProcessorUpgrade; ///< The enumeration value from PROCESSOR_UPGRADE.
+ UINT16 L1CacheHandle;
+ UINT16 L2CacheHandle;
+ UINT16 L3CacheHandle;
+ SMBIOS_TABLE_STRING SerialNumber;
+ SMBIOS_TABLE_STRING AssetTag;
+ SMBIOS_TABLE_STRING PartNumber;
+ //
+ // Add for smbios 2.5
+ //
+ UINT8 CoreCount;
+ UINT8 EnabledCoreCount;
+ UINT8 ThreadCount;
+ UINT16 ProcessorCharacteristics;
+ //
+ // Add for smbios 2.6
+ //
+ UINT16 ProcessorFamily2;
+ //
+ // Add for smbios 3.0
+ //
+ UINT16 CoreCount2;
+ UINT16 EnabledCoreCount2;
+ UINT16 ThreadCount2;
+ //
+ // Add for smbios 3.6
+ //
+ UINT16 ThreadEnabled;
+} SMBIOS_TABLE_TYPE4;
+
+///
+/// Memory Controller Error Detecting Method.
+///
+typedef enum {
+ ErrorDetectingMethodOther = 0x01,
+ ErrorDetectingMethodUnknown = 0x02,
+ ErrorDetectingMethodNone = 0x03,
+ ErrorDetectingMethodParity = 0x04,
+ ErrorDetectingMethod32Ecc = 0x05,
+ ErrorDetectingMethod64Ecc = 0x06,
+ ErrorDetectingMethod128Ecc = 0x07,
+ ErrorDetectingMethodCrc = 0x08
+} MEMORY_ERROR_DETECT_METHOD;
+
+///
+/// Memory Controller Error Correcting Capability.
+///
+typedef struct {
+ UINT8 Other : 1;
+ UINT8 Unknown : 1;
+ UINT8 None : 1;
+ UINT8 SingleBitErrorCorrect : 1;
+ UINT8 DoubleBitErrorCorrect : 1;
+ UINT8 ErrorScrubbing : 1;
+ UINT8 Reserved : 2;
+} MEMORY_ERROR_CORRECT_CAPABILITY;
+
+///
+/// Memory Controller Information - Interleave Support.
+///
+typedef enum {
+ MemoryInterleaveOther = 0x01,
+ MemoryInterleaveUnknown = 0x02,
+ MemoryInterleaveOneWay = 0x03,
+ MemoryInterleaveTwoWay = 0x04,
+ MemoryInterleaveFourWay = 0x05,
+ MemoryInterleaveEightWay = 0x06,
+ MemoryInterleaveSixteenWay = 0x07
+} MEMORY_SUPPORT_INTERLEAVE_TYPE;
+
+///
+/// Memory Controller Information - Memory Speeds.
+///
+typedef struct {
+ UINT16 Other : 1;
+ UINT16 Unknown : 1;
+ UINT16 SeventyNs : 1;
+ UINT16 SixtyNs : 1;
+ UINT16 FiftyNs : 1;
+ UINT16 Reserved : 11;
+} MEMORY_SPEED_TYPE;
+
+///
+/// Memory Controller Information (Type 5, Obsolete).
+///
+/// The information in this structure defines the attributes of the system's memory controller(s)
+/// and the supported attributes of any memory-modules present in the sockets controlled by
+/// this controller.
+/// Note: This structure, and its companion Memory Module Information (Type 6, Obsolete),
+/// are obsolete starting with version 2.1 of this specification. The Physical Memory Array (Type 16)
+/// and Memory Device (Type 17) structures should be used instead. BIOS providers might
+/// choose to implement both memory description types to allow existing DMI browsers
+/// to properly display the system's memory attributes.
+///
+typedef struct {
+ SMBIOS_STRUCTURE Hdr;
+ UINT8 ErrDetectMethod; ///< The enumeration value from MEMORY_ERROR_DETECT_METHOD.
+ MEMORY_ERROR_CORRECT_CAPABILITY ErrCorrectCapability;
+ UINT8 SupportInterleave; ///< The enumeration value from MEMORY_SUPPORT_INTERLEAVE_TYPE.
+ UINT8 CurrentInterleave; ///< The enumeration value from MEMORY_SUPPORT_INTERLEAVE_TYPE .
+ UINT8 MaxMemoryModuleSize;
+ MEMORY_SPEED_TYPE SupportSpeed;
+ UINT16 SupportMemoryType;
+ UINT8 MemoryModuleVoltage;
+ UINT8 AssociatedMemorySlotNum;
+ UINT16 MemoryModuleConfigHandles[1];
+} SMBIOS_TABLE_TYPE5;
+
+///
+/// Memory Module Information - Memory Types
+///
+typedef struct {
+ UINT16 Other : 1;
+ UINT16 Unknown : 1;
+ UINT16 Standard : 1;
+ UINT16 FastPageMode : 1;
+ UINT16 Edo : 1;
+ UINT16 Parity : 1;
+ UINT16 Ecc : 1;
+ UINT16 Simm : 1;
+ UINT16 Dimm : 1;
+ UINT16 BurstEdo : 1;
+ UINT16 Sdram : 1;
+ UINT16 Reserved : 5;
+} MEMORY_CURRENT_TYPE;
+
+///
+/// Memory Module Information - Memory Size.
+///
+typedef struct {
+ UINT8 InstalledOrEnabledSize : 7; ///< Size (n), where 2**n is the size in MB.
+ UINT8 SingleOrDoubleBank : 1;
+} MEMORY_INSTALLED_ENABLED_SIZE;
+
+///
+/// Memory Module Information (Type 6, Obsolete)
+///
+/// One Memory Module Information structure is included for each memory-module socket
+/// in the system. The structure describes the speed, type, size, and error status
+/// of each system memory module. The supported attributes of each module are described
+/// by the "owning" Memory Controller Information structure.
+/// Note: This structure, and its companion Memory Controller Information (Type 5, Obsolete),
+/// are obsolete starting with version 2.1 of this specification. The Physical Memory Array (Type 16)
+/// and Memory Device (Type 17) structures should be used instead.
+///
+typedef struct {
+ SMBIOS_STRUCTURE Hdr;
+ SMBIOS_TABLE_STRING SocketDesignation;
+ UINT8 BankConnections;
+ UINT8 CurrentSpeed;
+ MEMORY_CURRENT_TYPE CurrentMemoryType;
+ MEMORY_INSTALLED_ENABLED_SIZE InstalledSize;
+ MEMORY_INSTALLED_ENABLED_SIZE EnabledSize;
+ UINT8 ErrorStatus;
+} SMBIOS_TABLE_TYPE6;
+
+///
+/// Cache Information - SRAM Type.
+///
+typedef struct {
+ UINT16 Other : 1;
+ UINT16 Unknown : 1;
+ UINT16 NonBurst : 1;
+ UINT16 Burst : 1;
+ UINT16 PipelineBurst : 1;
+ UINT16 Synchronous : 1;
+ UINT16 Asynchronous : 1;
+ UINT16 Reserved : 9;
+} CACHE_SRAM_TYPE_DATA;
+
+///
+/// Cache Information - Error Correction Type.
+///
+typedef enum {
+ CacheErrorOther = 0x01,
+ CacheErrorUnknown = 0x02,
+ CacheErrorNone = 0x03,
+ CacheErrorParity = 0x04,
+ CacheErrorSingleBit = 0x05, ///< ECC
+ CacheErrorMultiBit = 0x06 ///< ECC
+} CACHE_ERROR_TYPE_DATA;
+
+///
+/// Cache Information - System Cache Type.
+///
+typedef enum {
+ CacheTypeOther = 0x01,
+ CacheTypeUnknown = 0x02,
+ CacheTypeInstruction = 0x03,
+ CacheTypeData = 0x04,
+ CacheTypeUnified = 0x05
+} CACHE_TYPE_DATA;
+
+///
+/// Cache Information - Associativity.
+///
+typedef enum {
+ CacheAssociativityOther = 0x01,
+ CacheAssociativityUnknown = 0x02,
+ CacheAssociativityDirectMapped = 0x03,
+ CacheAssociativity2Way = 0x04,
+ CacheAssociativity4Way = 0x05,
+ CacheAssociativityFully = 0x06,
+ CacheAssociativity8Way = 0x07,
+ CacheAssociativity16Way = 0x08,
+ CacheAssociativity12Way = 0x09,
+ CacheAssociativity24Way = 0x0A,
+ CacheAssociativity32Way = 0x0B,
+ CacheAssociativity48Way = 0x0C,
+ CacheAssociativity64Way = 0x0D,
+ CacheAssociativity20Way = 0x0E
+} CACHE_ASSOCIATIVITY_DATA;
+
+///
+/// Cache Information (Type 7).
+///
+/// The information in this structure defines the attributes of CPU cache device in the system.
+/// One structure is specified for each such device, whether the device is internal to
+/// or external to the CPU module. Cache modules can be associated with a processor structure
+/// in one or two ways, depending on the SMBIOS version.
+///
+typedef struct {
+ SMBIOS_STRUCTURE Hdr;
+ SMBIOS_TABLE_STRING SocketDesignation;
+ UINT16 CacheConfiguration;
+ UINT16 MaximumCacheSize;
+ UINT16 InstalledSize;
+ CACHE_SRAM_TYPE_DATA SupportedSRAMType;
+ CACHE_SRAM_TYPE_DATA CurrentSRAMType;
+ UINT8 CacheSpeed;
+ UINT8 ErrorCorrectionType; ///< The enumeration value from CACHE_ERROR_TYPE_DATA.
+ UINT8 SystemCacheType; ///< The enumeration value from CACHE_TYPE_DATA.
+ UINT8 Associativity; ///< The enumeration value from CACHE_ASSOCIATIVITY_DATA.
+ //
+ // Add for smbios 3.1.0
+ //
+ UINT32 MaximumCacheSize2;
+ UINT32 InstalledSize2;
+} SMBIOS_TABLE_TYPE7;
+
+///
+/// Port Connector Information - Connector Types.
+///
+typedef enum {
+ PortConnectorTypeNone = 0x00,
+ PortConnectorTypeCentronics = 0x01,
+ PortConnectorTypeMiniCentronics = 0x02,
+ PortConnectorTypeProprietary = 0x03,
+ PortConnectorTypeDB25Male = 0x04,
+ PortConnectorTypeDB25Female = 0x05,
+ PortConnectorTypeDB15Male = 0x06,
+ PortConnectorTypeDB15Female = 0x07,
+ PortConnectorTypeDB9Male = 0x08,
+ PortConnectorTypeDB9Female = 0x09,
+ PortConnectorTypeRJ11 = 0x0A,
+ PortConnectorTypeRJ45 = 0x0B,
+ PortConnectorType50PinMiniScsi = 0x0C,
+ PortConnectorTypeMiniDin = 0x0D,
+ PortConnectorTypeMicroDin = 0x0E,
+ PortConnectorTypePS2 = 0x0F,
+ PortConnectorTypeInfrared = 0x10,
+ PortConnectorTypeHpHil = 0x11,
+ PortConnectorTypeUsb = 0x12,
+ PortConnectorTypeSsaScsi = 0x13,
+ PortConnectorTypeCircularDin8Male = 0x14,
+ PortConnectorTypeCircularDin8Female = 0x15,
+ PortConnectorTypeOnboardIde = 0x16,
+ PortConnectorTypeOnboardFloppy = 0x17,
+ PortConnectorType9PinDualInline = 0x18,
+ PortConnectorType25PinDualInline = 0x19,
+ PortConnectorType50PinDualInline = 0x1A,
+ PortConnectorType68PinDualInline = 0x1B,
+ PortConnectorTypeOnboardSoundInput = 0x1C,
+ PortConnectorTypeMiniCentronicsType14 = 0x1D,
+ PortConnectorTypeMiniCentronicsType26 = 0x1E,
+ PortConnectorTypeHeadPhoneMiniJack = 0x1F,
+ PortConnectorTypeBNC = 0x20,
+ PortConnectorType1394 = 0x21,
+ PortConnectorTypeSasSata = 0x22,
+ PortConnectorTypeUsbTypeC = 0x23,
+ PortConnectorTypePC98 = 0xA0,
+ PortConnectorTypePC98Hireso = 0xA1,
+ PortConnectorTypePCH98 = 0xA2,
+ PortConnectorTypePC98Note = 0xA3,
+ PortConnectorTypePC98Full = 0xA4,
+ PortConnectorTypeOther = 0xFF
+} MISC_PORT_CONNECTOR_TYPE;
+
+///
+/// Port Connector Information - Port Types
+///
+typedef enum {
+ PortTypeNone = 0x00,
+ PortTypeParallelXtAtCompatible = 0x01,
+ PortTypeParallelPortPs2 = 0x02,
+ PortTypeParallelPortEcp = 0x03,
+ PortTypeParallelPortEpp = 0x04,
+ PortTypeParallelPortEcpEpp = 0x05,
+ PortTypeSerialXtAtCompatible = 0x06,
+ PortTypeSerial16450Compatible = 0x07,
+ PortTypeSerial16550Compatible = 0x08,
+ PortTypeSerial16550ACompatible = 0x09,
+ PortTypeScsi = 0x0A,
+ PortTypeMidi = 0x0B,
+ PortTypeJoyStick = 0x0C,
+ PortTypeKeyboard = 0x0D,
+ PortTypeMouse = 0x0E,
+ PortTypeSsaScsi = 0x0F,
+ PortTypeUsb = 0x10,
+ PortTypeFireWire = 0x11,
+ PortTypePcmciaTypeI = 0x12,
+ PortTypePcmciaTypeII = 0x13,
+ PortTypePcmciaTypeIII = 0x14,
+ PortTypeCardBus = 0x15,
+ PortTypeAccessBusPort = 0x16,
+ PortTypeScsiII = 0x17,
+ PortTypeScsiWide = 0x18,
+ PortTypePC98 = 0x19,
+ PortTypePC98Hireso = 0x1A,
+ PortTypePCH98 = 0x1B,
+ PortTypeVideoPort = 0x1C,
+ PortTypeAudioPort = 0x1D,
+ PortTypeModemPort = 0x1E,
+ PortTypeNetworkPort = 0x1F,
+ PortTypeSata = 0x20,
+ PortTypeSas = 0x21,
+ PortTypeMfdp = 0x22, ///< Multi-Function Display Port
+ PortTypeThunderbolt = 0x23,
+ PortType8251Compatible = 0xA0,
+ PortType8251FifoCompatible = 0xA1,
+ PortTypeOther = 0xFF
+} MISC_PORT_TYPE;
+
+///
+/// Port Connector Information (Type 8).
+///
+/// The information in this structure defines the attributes of a system port connector,
+/// e.g. parallel, serial, keyboard, or mouse ports. The port's type and connector information
+/// are provided. One structure is present for each port provided by the system.
+///
+typedef struct {
+ SMBIOS_STRUCTURE Hdr;
+ SMBIOS_TABLE_STRING InternalReferenceDesignator;
+ UINT8 InternalConnectorType; ///< The enumeration value from MISC_PORT_CONNECTOR_TYPE.
+ SMBIOS_TABLE_STRING ExternalReferenceDesignator;
+ UINT8 ExternalConnectorType; ///< The enumeration value from MISC_PORT_CONNECTOR_TYPE.
+ UINT8 PortType; ///< The enumeration value from MISC_PORT_TYPE.
+} SMBIOS_TABLE_TYPE8;
+
+#if !CONFIG(DISPLAY_FSP_VERSION_INFO_2)
+
+///
+/// System Slots - Slot Type
+///
+typedef enum {
+ SlotTypeOther = 0x01,
+ SlotTypeUnknown = 0x02,
+ SlotTypeIsa = 0x03,
+ SlotTypeMca = 0x04,
+ SlotTypeEisa = 0x05,
+ SlotTypePci = 0x06,
+ SlotTypePcmcia = 0x07,
+ SlotTypeVlVesa = 0x08,
+ SlotTypeProprietary = 0x09,
+ SlotTypeProcessorCardSlot = 0x0A,
+ SlotTypeProprietaryMemoryCardSlot = 0x0B,
+ SlotTypeIORiserCardSlot = 0x0C,
+ SlotTypeNuBus = 0x0D,
+ SlotTypePci66MhzCapable = 0x0E,
+ SlotTypeAgp = 0x0F,
+ SlotTypeApg2X = 0x10,
+ SlotTypeAgp4X = 0x11,
+ SlotTypePciX = 0x12,
+ SlotTypeAgp8X = 0x13,
+ SlotTypeM2Socket1_DP = 0x14,
+ SlotTypeM2Socket1_SD = 0x15,
+ SlotTypeM2Socket2 = 0x16,
+ SlotTypeM2Socket3 = 0x17,
+ SlotTypeMxmTypeI = 0x18,
+ SlotTypeMxmTypeII = 0x19,
+ SlotTypeMxmTypeIIIStandard = 0x1A,
+ SlotTypeMxmTypeIIIHe = 0x1B,
+ SlotTypeMxmTypeIV = 0x1C,
+ SlotTypeMxm30TypeA = 0x1D,
+ SlotTypeMxm30TypeB = 0x1E,
+ SlotTypePciExpressGen2Sff_8639 = 0x1F,
+ SlotTypePciExpressGen3Sff_8639 = 0x20,
+ SlotTypePciExpressMini52pinWithBSKO = 0x21, ///< PCI Express Mini 52-pin (CEM spec. 2.0) with bottom-side keep-outs.
+ SlotTypePciExpressMini52pinWithoutBSKO = 0x22, ///< PCI Express Mini 52-pin (CEM spec. 2.0) without bottom-side keep-outs.
+ SlotTypePciExpressMini76pin = 0x23, ///< PCI Express Mini 76-pin (CEM spec. 2.0) Corresponds to Display-Mini card.
+ SlotTypePCIExpressGen4SFF_8639 = 0x24, ///< U.2
+ SlotTypePCIExpressGen5SFF_8639 = 0x25, ///< U.2
+ SlotTypeOCPNIC30SmallFormFactor = 0x26, ///< SFF
+ SlotTypeOCPNIC30LargeFormFactor = 0x27, ///< LFF
+ SlotTypeOCPNICPriorto30 = 0x28,
+ SlotTypeCXLFlexbus10 = 0x30,
+ SlotTypePC98C20 = 0xA0,
+ SlotTypePC98C24 = 0xA1,
+ SlotTypePC98E = 0xA2,
+ SlotTypePC98LocalBus = 0xA3,
+ SlotTypePC98Card = 0xA4,
+ SlotTypePciExpress = 0xA5,
+ SlotTypePciExpressX1 = 0xA6,
+ SlotTypePciExpressX2 = 0xA7,
+ SlotTypePciExpressX4 = 0xA8,
+ SlotTypePciExpressX8 = 0xA9,
+ SlotTypePciExpressX16 = 0xAA,
+ SlotTypePciExpressGen2 = 0xAB,
+ SlotTypePciExpressGen2X1 = 0xAC,
+ SlotTypePciExpressGen2X2 = 0xAD,
+ SlotTypePciExpressGen2X4 = 0xAE,
+ SlotTypePciExpressGen2X8 = 0xAF,
+ SlotTypePciExpressGen2X16 = 0xB0,
+ SlotTypePciExpressGen3 = 0xB1,
+ SlotTypePciExpressGen3X1 = 0xB2,
+ SlotTypePciExpressGen3X2 = 0xB3,
+ SlotTypePciExpressGen3X4 = 0xB4,
+ SlotTypePciExpressGen3X8 = 0xB5,
+ SlotTypePciExpressGen3X16 = 0xB6,
+ SlotTypePciExpressGen4 = 0xB8,
+ SlotTypePciExpressGen4X1 = 0xB9,
+ SlotTypePciExpressGen4X2 = 0xBA,
+ SlotTypePciExpressGen4X4 = 0xBB,
+ SlotTypePciExpressGen4X8 = 0xBC,
+ SlotTypePciExpressGen4X16 = 0xBD,
+ SlotTypePCIExpressGen5 = 0xBE,
+ SlotTypePCIExpressGen5X1 = 0xBF,
+ SlotTypePCIExpressGen5X2 = 0xC0,
+ SlotTypePCIExpressGen5X4 = 0xC1,
+ SlotTypePCIExpressGen5X8 = 0xC2,
+ SlotTypePCIExpressGen5X16 = 0xC3,
+ SlotTypePCIExpressGen6andBeyond = 0xC4,
+ SlotTypeEnterpriseandDatacenter1UE1FormFactorSlot = 0xC5,
+ SlotTypeEnterpriseandDatacenter3E3FormFactorSlot = 0xC6
+} MISC_SLOT_TYPE;
+
+///
+/// System Slots - Slot Data Bus Width.
+///
+typedef enum {
+ SlotDataBusWidthOther = 0x01,
+ SlotDataBusWidthUnknown = 0x02,
+ SlotDataBusWidth8Bit = 0x03,
+ SlotDataBusWidth16Bit = 0x04,
+ SlotDataBusWidth32Bit = 0x05,
+ SlotDataBusWidth64Bit = 0x06,
+ SlotDataBusWidth128Bit = 0x07,
+ SlotDataBusWidth1X = 0x08, ///< Or X1
+ SlotDataBusWidth2X = 0x09, ///< Or X2
+ SlotDataBusWidth4X = 0x0A, ///< Or X4
+ SlotDataBusWidth8X = 0x0B, ///< Or X8
+ SlotDataBusWidth12X = 0x0C, ///< Or X12
+ SlotDataBusWidth16X = 0x0D, ///< Or X16
+ SlotDataBusWidth32X = 0x0E ///< Or X32
+} MISC_SLOT_DATA_BUS_WIDTH;
+
+///
+/// System Slots - Slot Physical Width.
+///
+typedef enum {
+ SlotPhysicalWidthOther = 0x01,
+ SlotPhysicalWidthUnknown = 0x02,
+ SlotPhysicalWidth8Bit = 0x03,
+ SlotPhysicalWidth16Bit = 0x04,
+ SlotPhysicalWidth32Bit = 0x05,
+ SlotPhysicalWidth64Bit = 0x06,
+ SlotPhysicalWidth128Bit = 0x07,
+ SlotPhysicalWidth1X = 0x08, ///< Or X1
+ SlotPhysicalWidth2X = 0x09, ///< Or X2
+ SlotPhysicalWidth4X = 0x0A, ///< Or X4
+ SlotPhysicalWidth8X = 0x0B, ///< Or X8
+ SlotPhysicalWidth12X = 0x0C, ///< Or X12
+ SlotPhysicalWidth16X = 0x0D, ///< Or X16
+ SlotPhysicalWidth32X = 0x0E ///< Or X32
+} MISC_SLOT_PHYSICAL_WIDTH;
+
+///
+/// System Slots - Slot Information.
+///
+typedef enum {
+ Others = 0x00,
+ Gen1 = 0x01,
+ Gen2 = 0x01,
+ Gen3 = 0x03,
+ Gen4 = 0x04,
+ Gen5 = 0x05,
+ Gen6 = 0x06
+} MISC_SLOT_INFORMATION;
+
+///
+/// System Slots - Current Usage.
+///
+typedef enum {
+ SlotUsageOther = 0x01,
+ SlotUsageUnknown = 0x02,
+ SlotUsageAvailable = 0x03,
+ SlotUsageInUse = 0x04,
+ SlotUsageUnavailable = 0x05
+} MISC_SLOT_USAGE;
+
+///
+/// System Slots - Slot Length.
+///
+typedef enum {
+ SlotLengthOther = 0x01,
+ SlotLengthUnknown = 0x02,
+ SlotLengthShort = 0x03,
+ SlotLengthLong = 0x04
+} MISC_SLOT_LENGTH;
+
+#endif
+///
+/// System Slots - Slot Characteristics 1.
+///
+typedef struct {
+ UINT8 CharacteristicsUnknown : 1;
+ UINT8 Provides50Volts : 1;
+ UINT8 Provides33Volts : 1;
+ UINT8 SharedSlot : 1;
+ UINT8 PcCard16Supported : 1;
+ UINT8 CardBusSupported : 1;
+ UINT8 ZoomVideoSupported : 1;
+ UINT8 ModemRingResumeSupported : 1;
+} MISC_SLOT_CHARACTERISTICS1;
+///
+/// System Slots - Slot Characteristics 2.
+///
+typedef struct {
+ UINT8 PmeSignalSupported : 1;
+ UINT8 HotPlugDevicesSupported : 1;
+ UINT8 SmbusSignalSupported : 1;
+ UINT8 BifurcationSupported : 1;
+ UINT8 AsyncSurpriseRemoval : 1;
+ UINT8 FlexbusSlotCxl10Capable : 1;
+ UINT8 FlexbusSlotCxl20Capable : 1;
+ UINT8 Reserved : 1; ///< Set to 0.
+} MISC_SLOT_CHARACTERISTICS2;
+
+///
+/// System Slots - Slot Height
+///
+typedef enum {
+ SlotHeightNone = 0x00,
+ SlotHeightOther = 0x01,
+ SlotHeightUnknown = 0x02,
+ SlotHeightFullHeight = 0x03,
+ SlotHeightLowProfile = 0x04
+} MISC_SLOT_HEIGHT;
+
+///
+/// System Slots - Peer Segment/Bus/Device/Function/Width Groups
+///
+typedef struct {
+ UINT16 SegmentGroupNum;
+ UINT8 BusNum;
+ UINT8 DevFuncNum;
+ UINT8 DataBusWidth;
+} MISC_SLOT_PEER_GROUP;
+
+///
+/// System Slots (Type 9)
+///
+/// The information in this structure defines the attributes of a system slot.
+/// One structure is provided for each slot in the system.
+///
+///
+typedef struct {
+ SMBIOS_STRUCTURE Hdr;
+ SMBIOS_TABLE_STRING SlotDesignation;
+ UINT8 SlotType; ///< The enumeration value from MISC_SLOT_TYPE.
+ UINT8 SlotDataBusWidth; ///< The enumeration value from MISC_SLOT_DATA_BUS_WIDTH.
+ UINT8 CurrentUsage; ///< The enumeration value from MISC_SLOT_USAGE.
+ UINT8 SlotLength; ///< The enumeration value from MISC_SLOT_LENGTH.
+ UINT16 SlotID;
+ MISC_SLOT_CHARACTERISTICS1 SlotCharacteristics1;
+ MISC_SLOT_CHARACTERISTICS2 SlotCharacteristics2;
+ //
+ // Add for smbios 2.6
+ //
+ UINT16 SegmentGroupNum;
+ UINT8 BusNum;
+ UINT8 DevFuncNum;
+ //
+ // Add for smbios 3.2
+ //
+ UINT8 DataBusWidth;
+ UINT8 PeerGroupingCount;
+ MISC_SLOT_PEER_GROUP PeerGroups[1];
+ //
+ // Since PeerGroups has a variable number of entries, must not define new
+ // fields in the structure. Remaining fields can be referenced using
+ // SMBIOS_TABLE_TYPE9_EXTENDED structure
+ //
+} SMBIOS_TABLE_TYPE9;
+
+///
+/// Extended structure for System Slots (Type 9)
+///
+typedef struct {
+ //
+ // Add for smbios 3.4
+ //
+ UINT8 SlotInformation;
+ UINT8 SlotPhysicalWidth;
+ UINT16 SlotPitch;
+ //
+ // Add for smbios 3.5
+ //
+ UINT8 SlotHeight; ///< The enumeration value from MISC_SLOT_HEIGHT.
+} SMBIOS_TABLE_TYPE9_EXTENDED;
+
+///
+/// On Board Devices Information - Device Types.
+///
+typedef enum {
+ OnBoardDeviceTypeOther = 0x01,
+ OnBoardDeviceTypeUnknown = 0x02,
+ OnBoardDeviceTypeVideo = 0x03,
+ OnBoardDeviceTypeScsiController = 0x04,
+ OnBoardDeviceTypeEthernet = 0x05,
+ OnBoardDeviceTypeTokenRing = 0x06,
+ OnBoardDeviceTypeSound = 0x07,
+ OnBoardDeviceTypePATAController = 0x08,
+ OnBoardDeviceTypeSATAController = 0x09,
+ OnBoardDeviceTypeSASController = 0x0A
+} MISC_ONBOARD_DEVICE_TYPE;
+
+///
+/// Device Item Entry
+///
+typedef struct {
+ UINT8 DeviceType; ///< Bit [6:0] - enumeration type of device from MISC_ONBOARD_DEVICE_TYPE.
+ ///< Bit 7 - 1 : device enabled, 0 : device disabled.
+ SMBIOS_TABLE_STRING DescriptionString;
+} DEVICE_STRUCT;
+
+///
+/// On Board Devices Information (Type 10, obsolete).
+///
+/// Note: This structure is obsolete starting with version 2.6 specification; the Onboard Devices Extended
+/// Information (Type 41) structure should be used instead . BIOS providers can choose to implement both
+/// types to allow existing SMBIOS browsers to properly display the system's onboard devices information.
+/// The information in this structure defines the attributes of devices that are onboard (soldered onto)
+/// a system element, usually the baseboard. In general, an entry in this table implies that the BIOS
+/// has some level of control over the enabling of the associated device for use by the system.
+///
+typedef struct {
+ SMBIOS_STRUCTURE Hdr;
+ DEVICE_STRUCT Device[1];
+} SMBIOS_TABLE_TYPE10;
+
+///
+/// OEM Strings (Type 11).
+/// This structure contains free form strings defined by the OEM. Examples of this are:
+/// Part Numbers for Reference Documents for the system, contact information for the manufacturer, etc.
+///
+typedef struct {
+ SMBIOS_STRUCTURE Hdr;
+ UINT8 StringCount;
+} SMBIOS_TABLE_TYPE11;
+
+///
+/// System Configuration Options (Type 12).
+///
+/// This structure contains information required to configure the base board's Jumpers and Switches.
+///
+typedef struct {
+ SMBIOS_STRUCTURE Hdr;
+ UINT8 StringCount;
+} SMBIOS_TABLE_TYPE12;
+
+///
+/// BIOS Language Information (Type 13).
+///
+/// The information in this structure defines the installable language attributes of the BIOS.
+///
+typedef struct {
+ SMBIOS_STRUCTURE Hdr;
+ UINT8 InstallableLanguages;
+ UINT8 Flags;
+ UINT8 Reserved[15];
+ SMBIOS_TABLE_STRING CurrentLanguages;
+} SMBIOS_TABLE_TYPE13;
+
+///
+/// Group Item Entry
+///
+typedef struct {
+ UINT8 ItemType;
+ UINT16 ItemHandle;
+} GROUP_STRUCT;
+
+///
+/// Group Associations (Type 14).
+///
+/// The Group Associations structure is provided for OEMs who want to specify
+/// the arrangement or hierarchy of certain components (including other Group Associations)
+/// within the system.
+///
+typedef struct {
+ SMBIOS_STRUCTURE Hdr;
+ SMBIOS_TABLE_STRING GroupName;
+ GROUP_STRUCT Group[1];
+} SMBIOS_TABLE_TYPE14;
+
+///
+/// System Event Log - Event Log Types.
+///
+typedef enum {
+ EventLogTypeReserved = 0x00,
+ EventLogTypeSingleBitECC = 0x01,
+ EventLogTypeMultiBitECC = 0x02,
+ EventLogTypeParityMemErr = 0x03,
+ EventLogTypeBusTimeOut = 0x04,
+ EventLogTypeIOChannelCheck = 0x05,
+ EventLogTypeSoftwareNMI = 0x06,
+ EventLogTypePOSTMemResize = 0x07,
+ EventLogTypePOSTErr = 0x08,
+ EventLogTypePCIParityErr = 0x09,
+ EventLogTypePCISystemErr = 0x0A,
+ EventLogTypeCPUFailure = 0x0B,
+ EventLogTypeEISATimeOut = 0x0C,
+ EventLogTypeMemLogDisabled = 0x0D,
+ EventLogTypeLoggingDisabled = 0x0E,
+ EventLogTypeSysLimitExce = 0x10,
+ EventLogTypeAsyncHWTimer = 0x11,
+ EventLogTypeSysConfigInfo = 0x12,
+ EventLogTypeHDInfo = 0x13,
+ EventLogTypeSysReconfig = 0x14,
+ EventLogTypeUncorrectCPUErr = 0x15,
+ EventLogTypeAreaResetAndClr = 0x16,
+ EventLogTypeSystemBoot = 0x17,
+ EventLogTypeUnused = 0x18, ///< 0x18 - 0x7F
+ EventLogTypeAvailForSys = 0x80, ///< 0x80 - 0xFE
+ EventLogTypeEndOfLog = 0xFF
+} EVENT_LOG_TYPE_DATA;
+
+///
+/// System Event Log - Variable Data Format Types.
+///
+typedef enum {
+ EventLogVariableNone = 0x00,
+ EventLogVariableHandle = 0x01,
+ EventLogVariableMutilEvent = 0x02,
+ EventLogVariableMutilEventHandle = 0x03,
+ EventLogVariablePOSTResultBitmap = 0x04,
+ EventLogVariableSysManagementType = 0x05,
+ EventLogVariableMutliEventSysManagmentType = 0x06,
+ EventLogVariableUnused = 0x07,
+ EventLogVariableOEMAssigned = 0x80
+} EVENT_LOG_VARIABLE_DATA;
+
+///
+/// Event Log Type Descriptors
+///
+typedef struct {
+ UINT8 LogType; ///< The enumeration value from EVENT_LOG_TYPE_DATA.
+ UINT8 DataFormatType;
+} EVENT_LOG_TYPE;
+
+///
+/// System Event Log (Type 15).
+///
+/// The presence of this structure within the SMBIOS data returned for a system indicates
+/// that the system supports an event log. An event log is a fixed-length area within a
+/// non-volatile storage element, starting with a fixed-length (and vendor-specific) header
+/// record, followed by one or more variable-length log records.
+///
+typedef struct {
+ SMBIOS_STRUCTURE Hdr;
+ UINT16 LogAreaLength;
+ UINT16 LogHeaderStartOffset;
+ UINT16 LogDataStartOffset;
+ UINT8 AccessMethod;
+ UINT8 LogStatus;
+ UINT32 LogChangeToken;
+ UINT32 AccessMethodAddress;
+ UINT8 LogHeaderFormat;
+ UINT8 NumberOfSupportedLogTypeDescriptors;
+ UINT8 LengthOfLogTypeDescriptor;
+ EVENT_LOG_TYPE EventLogTypeDescriptors[1];
+} SMBIOS_TABLE_TYPE15;
+
+///
+/// Physical Memory Array - Location.
+///
+typedef enum {
+ MemoryArrayLocationOther = 0x01,
+ MemoryArrayLocationUnknown = 0x02,
+ MemoryArrayLocationSystemBoard = 0x03,
+ MemoryArrayLocationIsaAddonCard = 0x04,
+ MemoryArrayLocationEisaAddonCard = 0x05,
+ MemoryArrayLocationPciAddonCard = 0x06,
+ MemoryArrayLocationMcaAddonCard = 0x07,
+ MemoryArrayLocationPcmciaAddonCard = 0x08,
+ MemoryArrayLocationProprietaryAddonCard = 0x09,
+ MemoryArrayLocationNuBus = 0x0A,
+ MemoryArrayLocationPc98C20AddonCard = 0xA0,
+ MemoryArrayLocationPc98C24AddonCard = 0xA1,
+ MemoryArrayLocationPc98EAddonCard = 0xA2,
+ MemoryArrayLocationPc98LocalBusAddonCard = 0xA3,
+ MemoryArrayLocationCXLAddonCard = 0xA4
+} MEMORY_ARRAY_LOCATION;
+
+///
+/// Physical Memory Array - Use.
+///
+typedef enum {
+ MemoryArrayUseOther = 0x01,
+ MemoryArrayUseUnknown = 0x02,
+ MemoryArrayUseSystemMemory = 0x03,
+ MemoryArrayUseVideoMemory = 0x04,
+ MemoryArrayUseFlashMemory = 0x05,
+ MemoryArrayUseNonVolatileRam = 0x06,
+ MemoryArrayUseCacheMemory = 0x07
+} MEMORY_ARRAY_USE;
+
+///
+/// Physical Memory Array - Error Correction Types.
+///
+typedef enum {
+ MemoryErrorCorrectionOther = 0x01,
+ MemoryErrorCorrectionUnknown = 0x02,
+ MemoryErrorCorrectionNone = 0x03,
+ MemoryErrorCorrectionParity = 0x04,
+ MemoryErrorCorrectionSingleBitEcc = 0x05,
+ MemoryErrorCorrectionMultiBitEcc = 0x06,
+ MemoryErrorCorrectionCrc = 0x07
+} MEMORY_ERROR_CORRECTION;
+
+///
+/// Physical Memory Array (Type 16).
+///
+/// This structure describes a collection of memory devices that operate
+/// together to form a memory address space.
+///
+typedef struct {
+ SMBIOS_STRUCTURE Hdr;
+ UINT8 Location; ///< The enumeration value from MEMORY_ARRAY_LOCATION.
+ UINT8 Use; ///< The enumeration value from MEMORY_ARRAY_USE.
+ UINT8 MemoryErrorCorrection; ///< The enumeration value from MEMORY_ERROR_CORRECTION.
+ UINT32 MaximumCapacity;
+ UINT16 MemoryErrorInformationHandle;
+ UINT16 NumberOfMemoryDevices;
+ //
+ // Add for smbios 2.7
+ //
+ UINT64 ExtendedMaximumCapacity;
+} SMBIOS_TABLE_TYPE16;
+
+///
+/// Memory Device - Form Factor.
+///
+typedef enum {
+ MemoryFormFactorOther = 0x01,
+ MemoryFormFactorUnknown = 0x02,
+ MemoryFormFactorSimm = 0x03,
+ MemoryFormFactorSip = 0x04,
+ MemoryFormFactorChip = 0x05,
+ MemoryFormFactorDip = 0x06,
+ MemoryFormFactorZip = 0x07,
+ MemoryFormFactorProprietaryCard = 0x08,
+ MemoryFormFactorDimm = 0x09,
+ MemoryFormFactorTsop = 0x0A,
+ MemoryFormFactorRowOfChips = 0x0B,
+ MemoryFormFactorRimm = 0x0C,
+ MemoryFormFactorSodimm = 0x0D,
+ MemoryFormFactorSrimm = 0x0E,
+ MemoryFormFactorFbDimm = 0x0F,
+ MemoryFormFactorDie = 0x10
+} MEMORY_FORM_FACTOR;
+
+///
+/// Memory Device - Type
+///
+typedef enum {
+ MemoryTypeOther = 0x01,
+ MemoryTypeUnknown = 0x02,
+ MemoryTypeDram = 0x03,
+ MemoryTypeEdram = 0x04,
+ MemoryTypeVram = 0x05,
+ MemoryTypeSram = 0x06,
+ MemoryTypeRam = 0x07,
+ MemoryTypeRom = 0x08,
+ MemoryTypeFlash = 0x09,
+ MemoryTypeEeprom = 0x0A,
+ MemoryTypeFeprom = 0x0B,
+ MemoryTypeEprom = 0x0C,
+ MemoryTypeCdram = 0x0D,
+ MemoryType3Dram = 0x0E,
+ MemoryTypeSdram = 0x0F,
+ MemoryTypeSgram = 0x10,
+ MemoryTypeRdram = 0x11,
+ MemoryTypeDdr = 0x12,
+ MemoryTypeDdr2 = 0x13,
+ MemoryTypeDdr2FbDimm = 0x14,
+ MemoryTypeDdr3 = 0x18,
+ MemoryTypeFbd2 = 0x19,
+ MemoryTypeDdr4 = 0x1A,
+ MemoryTypeLpddr = 0x1B,
+ MemoryTypeLpddr2 = 0x1C,
+ MemoryTypeLpddr3 = 0x1D,
+ MemoryTypeLpddr4 = 0x1E,
+ MemoryTypeLogicalNonVolatileDevice = 0x1F,
+ MemoryTypeHBM = 0x20,
+ MemoryTypeHBM2 = 0x21,
+ MemoryTypeDdr5 = 0x22,
+ MemoryTypeLpddr5 = 0x23,
+ MemoryTypeHBM3 = 0x24
+} MEMORY_DEVICE_TYPE;
+
+///
+/// Memory Device - Type Detail
+///
+typedef struct {
+ UINT16 Reserved : 1;
+ UINT16 Other : 1;
+ UINT16 Unknown : 1;
+ UINT16 FastPaged : 1;
+ UINT16 StaticColumn : 1;
+ UINT16 PseudoStatic : 1;
+ UINT16 Rambus : 1;
+ UINT16 Synchronous : 1;
+ UINT16 Cmos : 1;
+ UINT16 Edo : 1;
+ UINT16 WindowDram : 1;
+ UINT16 CacheDram : 1;
+ UINT16 Nonvolatile : 1;
+ UINT16 Registered : 1;
+ UINT16 Unbuffered : 1;
+ UINT16 LrDimm : 1;
+} MEMORY_DEVICE_TYPE_DETAIL;
+
+///
+/// Memory Device - Memory Technology
+///
+typedef enum {
+ MemoryTechnologyOther = 0x01,
+ MemoryTechnologyUnknown = 0x02,
+ MemoryTechnologyDram = 0x03,
+ MemoryTechnologyNvdimmN = 0x04,
+ MemoryTechnologyNvdimmF = 0x05,
+ MemoryTechnologyNvdimmP = 0x06,
+ //
+ // This definition is updated to represent Intel
+ // Optane DC Persistent Memory in SMBIOS spec 3.4.0
+ //
+ MemoryTechnologyIntelOptanePersistentMemory = 0x07
+} MEMORY_DEVICE_TECHNOLOGY;
+
+///
+/// Memory Device - Memory Operating Mode Capability
+///
+typedef union {
+ ///
+ /// Individual bit fields
+ ///
+ struct {
+ UINT16 Reserved : 1; ///< Set to 0.
+ UINT16 Other : 1;
+ UINT16 Unknown : 1;
+ UINT16 VolatileMemory : 1;
+ UINT16 ByteAccessiblePersistentMemory : 1;
+ UINT16 BlockAccessiblePersistentMemory : 1;
+ UINT16 Reserved2 : 10; ///< Set to 0.
+ } Bits;
+ ///
+ /// All bit fields as a 16-bit value
+ ///
+ UINT16 Uint16;
+} MEMORY_DEVICE_OPERATING_MODE_CAPABILITY;
+
+///
+/// Memory Device (Type 17).
+///
+/// This structure describes a single memory device that is part of
+/// a larger Physical Memory Array (Type 16).
+/// Note: If a system includes memory-device sockets, the SMBIOS implementation
+/// includes a Memory Device structure instance for each slot, whether or not the
+/// socket is currently populated.
+///
+typedef struct {
+ SMBIOS_STRUCTURE Hdr;
+ UINT16 MemoryArrayHandle;
+ UINT16 MemoryErrorInformationHandle;
+ UINT16 TotalWidth;
+ UINT16 DataWidth;
+ UINT16 Size;
+ UINT8 FormFactor; ///< The enumeration value from MEMORY_FORM_FACTOR.
+ UINT8 DeviceSet;
+ SMBIOS_TABLE_STRING DeviceLocator;
+ SMBIOS_TABLE_STRING BankLocator;
+ UINT8 MemoryType; ///< The enumeration value from MEMORY_DEVICE_TYPE.
+ MEMORY_DEVICE_TYPE_DETAIL TypeDetail;
+ UINT16 Speed;
+ SMBIOS_TABLE_STRING Manufacturer;
+ SMBIOS_TABLE_STRING SerialNumber;
+ SMBIOS_TABLE_STRING AssetTag;
+ SMBIOS_TABLE_STRING PartNumber;
+ //
+ // Add for smbios 2.6
+ //
+ UINT8 Attributes;
+ //
+ // Add for smbios 2.7
+ //
+ UINT32 ExtendedSize;
+ //
+ // Keep using name "ConfiguredMemoryClockSpeed" for compatibility
+ // although this field is renamed from "Configured Memory Clock Speed"
+ // to "Configured Memory Speed" in smbios 3.2.0.
+ //
+ UINT16 ConfiguredMemoryClockSpeed;
+ //
+ // Add for smbios 2.8.0
+ //
+ UINT16 MinimumVoltage;
+ UINT16 MaximumVoltage;
+ UINT16 ConfiguredVoltage;
+ //
+ // Add for smbios 3.2.0
+ //
+ UINT8 MemoryTechnology; ///< The enumeration value from MEMORY_DEVICE_TECHNOLOGY
+ MEMORY_DEVICE_OPERATING_MODE_CAPABILITY MemoryOperatingModeCapability;
+ SMBIOS_TABLE_STRING FirmwareVersion;
+ UINT16 ModuleManufacturerID;
+ UINT16 ModuleProductID;
+ UINT16 MemorySubsystemControllerManufacturerID;
+ UINT16 MemorySubsystemControllerProductID;
+ UINT64 NonVolatileSize;
+ UINT64 VolatileSize;
+ UINT64 CacheSize;
+ UINT64 LogicalSize;
+ //
+ // Add for smbios 3.3.0
+ //
+ UINT32 ExtendedSpeed;
+ UINT32 ExtendedConfiguredMemorySpeed;
+} SMBIOS_TABLE_TYPE17;
+
+///
+/// 32-bit Memory Error Information - Error Type.
+///
+typedef enum {
+ MemoryErrorOther = 0x01,
+ MemoryErrorUnknown = 0x02,
+ MemoryErrorOk = 0x03,
+ MemoryErrorBadRead = 0x04,
+ MemoryErrorParity = 0x05,
+ MemoryErrorSigleBit = 0x06,
+ MemoryErrorDoubleBit = 0x07,
+ MemoryErrorMultiBit = 0x08,
+ MemoryErrorNibble = 0x09,
+ MemoryErrorChecksum = 0x0A,
+ MemoryErrorCrc = 0x0B,
+ MemoryErrorCorrectSingleBit = 0x0C,
+ MemoryErrorCorrected = 0x0D,
+ MemoryErrorUnCorrectable = 0x0E
+} MEMORY_ERROR_TYPE;
+
+///
+/// 32-bit Memory Error Information - Error Granularity.
+///
+typedef enum {
+ MemoryGranularityOther = 0x01,
+ MemoryGranularityOtherUnknown = 0x02,
+ MemoryGranularityDeviceLevel = 0x03,
+ MemoryGranularityMemPartitionLevel = 0x04
+} MEMORY_ERROR_GRANULARITY;
+
+///
+/// 32-bit Memory Error Information - Error Operation.
+///
+typedef enum {
+ MemoryErrorOperationOther = 0x01,
+ MemoryErrorOperationUnknown = 0x02,
+ MemoryErrorOperationRead = 0x03,
+ MemoryErrorOperationWrite = 0x04,
+ MemoryErrorOperationPartialWrite = 0x05
+} MEMORY_ERROR_OPERATION;
+
+///
+/// 32-bit Memory Error Information (Type 18).
+///
+/// This structure identifies the specifics of an error that might be detected
+/// within a Physical Memory Array.
+///
+typedef struct {
+ SMBIOS_STRUCTURE Hdr;
+ UINT8 ErrorType; ///< The enumeration value from MEMORY_ERROR_TYPE.
+ UINT8 ErrorGranularity; ///< The enumeration value from MEMORY_ERROR_GRANULARITY.
+ UINT8 ErrorOperation; ///< The enumeration value from MEMORY_ERROR_OPERATION.
+ UINT32 VendorSyndrome;
+ UINT32 MemoryArrayErrorAddress;
+ UINT32 DeviceErrorAddress;
+ UINT32 ErrorResolution;
+} SMBIOS_TABLE_TYPE18;
+
+///
+/// Memory Array Mapped Address (Type 19).
+///
+/// This structure provides the address mapping for a Physical Memory Array.
+/// One structure is present for each contiguous address range described.
+///
+typedef struct {
+ SMBIOS_STRUCTURE Hdr;
+ UINT32 StartingAddress;
+ UINT32 EndingAddress;
+ UINT16 MemoryArrayHandle;
+ UINT8 PartitionWidth;
+ //
+ // Add for smbios 2.7
+ //
+ UINT64 ExtendedStartingAddress;
+ UINT64 ExtendedEndingAddress;
+} SMBIOS_TABLE_TYPE19;
+
+///
+/// Memory Device Mapped Address (Type 20).
+///
+/// This structure maps memory address space usually to a device-level granularity.
+/// One structure is present for each contiguous address range described.
+///
+typedef struct {
+ SMBIOS_STRUCTURE Hdr;
+ UINT32 StartingAddress;
+ UINT32 EndingAddress;
+ UINT16 MemoryDeviceHandle;
+ UINT16 MemoryArrayMappedAddressHandle;
+ UINT8 PartitionRowPosition;
+ UINT8 InterleavePosition;
+ UINT8 InterleavedDataDepth;
+ //
+ // Add for smbios 2.7
+ //
+ UINT64 ExtendedStartingAddress;
+ UINT64 ExtendedEndingAddress;
+} SMBIOS_TABLE_TYPE20;
+
+///
+/// Built-in Pointing Device - Type
+///
+typedef enum {
+ PointingDeviceTypeOther = 0x01,
+ PointingDeviceTypeUnknown = 0x02,
+ PointingDeviceTypeMouse = 0x03,
+ PointingDeviceTypeTrackBall = 0x04,
+ PointingDeviceTypeTrackPoint = 0x05,
+ PointingDeviceTypeGlidePoint = 0x06,
+ PointingDeviceTouchPad = 0x07,
+ PointingDeviceTouchScreen = 0x08,
+ PointingDeviceOpticalSensor = 0x09
+} BUILTIN_POINTING_DEVICE_TYPE;
+
+///
+/// Built-in Pointing Device - Interface.
+///
+typedef enum {
+ PointingDeviceInterfaceOther = 0x01,
+ PointingDeviceInterfaceUnknown = 0x02,
+ PointingDeviceInterfaceSerial = 0x03,
+ PointingDeviceInterfacePs2 = 0x04,
+ PointingDeviceInterfaceInfrared = 0x05,
+ PointingDeviceInterfaceHpHil = 0x06,
+ PointingDeviceInterfaceBusMouse = 0x07,
+ PointingDeviceInterfaceADB = 0x08,
+ PointingDeviceInterfaceBusMouseDB9 = 0xA0,
+ PointingDeviceInterfaceBusMouseMicroDin = 0xA1,
+ PointingDeviceInterfaceUsb = 0xA2,
+ PointingDeviceInterfaceI2c = 0xA3,
+ PointingDeviceInterfaceSpi = 0xA4
+} BUILTIN_POINTING_DEVICE_INTERFACE;
+
+///
+/// Built-in Pointing Device (Type 21).
+///
+/// This structure describes the attributes of the built-in pointing device for the
+/// system. The presence of this structure does not imply that the built-in
+/// pointing device is active for the system's use!
+///
+typedef struct {
+ SMBIOS_STRUCTURE Hdr;
+ UINT8 Type; ///< The enumeration value from BUILTIN_POINTING_DEVICE_TYPE.
+ UINT8 Interface; ///< The enumeration value from BUILTIN_POINTING_DEVICE_INTERFACE.
+ UINT8 NumberOfButtons;
+} SMBIOS_TABLE_TYPE21;
+
+///
+/// Portable Battery - Device Chemistry
+///
+typedef enum {
+ PortableBatteryDeviceChemistryOther = 0x01,
+ PortableBatteryDeviceChemistryUnknown = 0x02,
+ PortableBatteryDeviceChemistryLeadAcid = 0x03,
+ PortableBatteryDeviceChemistryNickelCadmium = 0x04,
+ PortableBatteryDeviceChemistryNickelMetalHydride = 0x05,
+ PortableBatteryDeviceChemistryLithiumIon = 0x06,
+ PortableBatteryDeviceChemistryZincAir = 0x07,
+ PortableBatteryDeviceChemistryLithiumPolymer = 0x08
+} PORTABLE_BATTERY_DEVICE_CHEMISTRY;
+
+///
+/// Portable Battery (Type 22).
+///
+/// This structure describes the attributes of the portable battery(s) for the system.
+/// The structure contains the static attributes for the group. Each structure describes
+/// a single battery pack's attributes.
+///
+typedef struct {
+ SMBIOS_STRUCTURE Hdr;
+ SMBIOS_TABLE_STRING Location;
+ SMBIOS_TABLE_STRING Manufacturer;
+ SMBIOS_TABLE_STRING ManufactureDate;
+ SMBIOS_TABLE_STRING SerialNumber;
+ SMBIOS_TABLE_STRING DeviceName;
+ UINT8 DeviceChemistry; ///< The enumeration value from PORTABLE_BATTERY_DEVICE_CHEMISTRY.
+ UINT16 DeviceCapacity;
+ UINT16 DesignVoltage;
+ SMBIOS_TABLE_STRING SBDSVersionNumber;
+ UINT8 MaximumErrorInBatteryData;
+ UINT16 SBDSSerialNumber;
+ UINT16 SBDSManufactureDate;
+ SMBIOS_TABLE_STRING SBDSDeviceChemistry;
+ UINT8 DesignCapacityMultiplier;
+ UINT32 OEMSpecific;
+} SMBIOS_TABLE_TYPE22;
+
+///
+/// System Reset (Type 23)
+///
+/// This structure describes whether Automatic System Reset functions enabled (Status).
+/// If the system has a watchdog Timer and the timer is not reset (Timer Reset)
+/// before the Interval elapses, an automatic system reset will occur. The system will re-boot
+/// according to the Boot Option. This function may repeat until the Limit is reached, at which time
+/// the system will re-boot according to the Boot Option at Limit.
+///
+typedef struct {
+ SMBIOS_STRUCTURE Hdr;
+ UINT8 Capabilities;
+ UINT16 ResetCount;
+ UINT16 ResetLimit;
+ UINT16 TimerInterval;
+ UINT16 Timeout;
+} SMBIOS_TABLE_TYPE23;
+
+///
+/// Hardware Security (Type 24).
+///
+/// This structure describes the system-wide hardware security settings.
+///
+typedef struct {
+ SMBIOS_STRUCTURE Hdr;
+ UINT8 HardwareSecuritySettings;
+} SMBIOS_TABLE_TYPE24;
+
+///
+/// System Power Controls (Type 25).
+///
+/// This structure describes the attributes for controlling the main power supply to the system.
+/// Software that interprets this structure uses the month, day, hour, minute, and second values
+/// to determine the number of seconds until the next power-on of the system. The presence of
+/// this structure implies that a timed power-on facility is available for the system.
+///
+typedef struct {
+ SMBIOS_STRUCTURE Hdr;
+ UINT8 NextScheduledPowerOnMonth;
+ UINT8 NextScheduledPowerOnDayOfMonth;
+ UINT8 NextScheduledPowerOnHour;
+ UINT8 NextScheduledPowerOnMinute;
+ UINT8 NextScheduledPowerOnSecond;
+} SMBIOS_TABLE_TYPE25;
+
+///
+/// Voltage Probe - Location and Status.
+///
+typedef struct {
+ UINT8 VoltageProbeSite : 5;
+ UINT8 VoltageProbeStatus : 3;
+} MISC_VOLTAGE_PROBE_LOCATION;
+
+///
+/// Voltage Probe (Type 26)
+///
+/// This describes the attributes for a voltage probe in the system.
+/// Each structure describes a single voltage probe.
+///
+typedef struct {
+ SMBIOS_STRUCTURE Hdr;
+ SMBIOS_TABLE_STRING Description;
+ MISC_VOLTAGE_PROBE_LOCATION LocationAndStatus;
+ UINT16 MaximumValue;
+ UINT16 MinimumValue;
+ UINT16 Resolution;
+ UINT16 Tolerance;
+ UINT16 Accuracy;
+ UINT32 OEMDefined;
+ UINT16 NominalValue;
+} SMBIOS_TABLE_TYPE26;
+
+///
+/// Cooling Device - Device Type and Status.
+///
+typedef struct {
+ UINT8 CoolingDevice : 5;
+ UINT8 CoolingDeviceStatus : 3;
+} MISC_COOLING_DEVICE_TYPE;
+
+///
+/// Cooling Device (Type 27)
+///
+/// This structure describes the attributes for a cooling device in the system.
+/// Each structure describes a single cooling device.
+///
+typedef struct {
+ SMBIOS_STRUCTURE Hdr;
+ UINT16 TemperatureProbeHandle;
+ MISC_COOLING_DEVICE_TYPE DeviceTypeAndStatus;
+ UINT8 CoolingUnitGroup;
+ UINT32 OEMDefined;
+ UINT16 NominalSpeed;
+ //
+ // Add for smbios 2.7
+ //
+ SMBIOS_TABLE_STRING Description;
+} SMBIOS_TABLE_TYPE27;
+
+///
+/// Temperature Probe - Location and Status.
+///
+typedef struct {
+ UINT8 TemperatureProbeSite : 5;
+ UINT8 TemperatureProbeStatus : 3;
+} MISC_TEMPERATURE_PROBE_LOCATION;
+
+///
+/// Temperature Probe (Type 28).
+///
+/// This structure describes the attributes for a temperature probe in the system.
+/// Each structure describes a single temperature probe.
+///
+typedef struct {
+ SMBIOS_STRUCTURE Hdr;
+ SMBIOS_TABLE_STRING Description;
+ MISC_TEMPERATURE_PROBE_LOCATION LocationAndStatus;
+ UINT16 MaximumValue;
+ UINT16 MinimumValue;
+ UINT16 Resolution;
+ UINT16 Tolerance;
+ UINT16 Accuracy;
+ UINT32 OEMDefined;
+ UINT16 NominalValue;
+} SMBIOS_TABLE_TYPE28;
+
+///
+/// Electrical Current Probe - Location and Status.
+///
+typedef struct {
+ UINT8 ElectricalCurrentProbeSite : 5;
+ UINT8 ElectricalCurrentProbeStatus : 3;
+} MISC_ELECTRICAL_CURRENT_PROBE_LOCATION;
+
+///
+/// Electrical Current Probe (Type 29).
+///
+/// This structure describes the attributes for an electrical current probe in the system.
+/// Each structure describes a single electrical current probe.
+///
+typedef struct {
+ SMBIOS_STRUCTURE Hdr;
+ SMBIOS_TABLE_STRING Description;
+ MISC_ELECTRICAL_CURRENT_PROBE_LOCATION LocationAndStatus;
+ UINT16 MaximumValue;
+ UINT16 MinimumValue;
+ UINT16 Resolution;
+ UINT16 Tolerance;
+ UINT16 Accuracy;
+ UINT32 OEMDefined;
+ UINT16 NominalValue;
+} SMBIOS_TABLE_TYPE29;
+
+///
+/// Out-of-Band Remote Access (Type 30).
+///
+/// This structure describes the attributes and policy settings of a hardware facility
+/// that may be used to gain remote access to a hardware system when the operating system
+/// is not available due to power-down status, hardware failures, or boot failures.
+///
+typedef struct {
+ SMBIOS_STRUCTURE Hdr;
+ SMBIOS_TABLE_STRING ManufacturerName;
+ UINT8 Connections;
+} SMBIOS_TABLE_TYPE30;
+
+///
+/// Boot Integrity Services (BIS) Entry Point (Type 31).
+///
+/// Structure type 31 (decimal) is reserved for use by the Boot Integrity Services (BIS).
+///
+typedef struct {
+ SMBIOS_STRUCTURE Hdr;
+ UINT8 Checksum;
+ UINT8 Reserved1;
+ UINT16 Reserved2;
+ UINT32 BisEntry16;
+ UINT32 BisEntry32;
+ UINT64 Reserved3;
+ UINT32 Reserved4;
+} SMBIOS_TABLE_TYPE31;
+
+///
+/// System Boot Information - System Boot Status.
+///
+typedef enum {
+ BootInformationStatusNoError = 0x00,
+ BootInformationStatusNoBootableMedia = 0x01,
+ BootInformationStatusNormalOSFailedLoading = 0x02,
+ BootInformationStatusFirmwareDetectedFailure = 0x03,
+ BootInformationStatusOSDetectedFailure = 0x04,
+ BootInformationStatusUserRequestedBoot = 0x05,
+ BootInformationStatusSystemSecurityViolation = 0x06,
+ BootInformationStatusPreviousRequestedImage = 0x07,
+ BootInformationStatusWatchdogTimerExpired = 0x08,
+ BootInformationStatusStartReserved = 0x09,
+ BootInformationStatusStartOemSpecific = 0x80,
+ BootInformationStatusStartProductSpecific = 0xC0
+} MISC_BOOT_INFORMATION_STATUS_DATA_TYPE;
+
+///
+/// System Boot Information (Type 32).
+///
+/// The client system firmware, e.g. BIOS, communicates the System Boot Status to the
+/// client's Pre-boot Execution Environment (PXE) boot image or OS-present management
+/// application via this structure. When used in the PXE environment, for example,
+/// this code identifies the reason the PXE was initiated and can be used by boot-image
+/// software to further automate an enterprise's PXE sessions. For example, an enterprise
+/// could choose to automatically download a hardware-diagnostic image to a client whose
+/// reason code indicated either a firmware- or operating system-detected hardware failure.
+///
+typedef struct {
+ SMBIOS_STRUCTURE Hdr;
+ UINT8 Reserved[6];
+ UINT8 BootStatus; ///< The enumeration value from MISC_BOOT_INFORMATION_STATUS_DATA_TYPE.
+} SMBIOS_TABLE_TYPE32;
+
+///
+/// 64-bit Memory Error Information (Type 33).
+///
+/// This structure describes an error within a Physical Memory Array,
+/// when the error address is above 4G (0xFFFFFFFF).
+///
+typedef struct {
+ SMBIOS_STRUCTURE Hdr;
+ UINT8 ErrorType; ///< The enumeration value from MEMORY_ERROR_TYPE.
+ UINT8 ErrorGranularity; ///< The enumeration value from MEMORY_ERROR_GRANULARITY.
+ UINT8 ErrorOperation; ///< The enumeration value from MEMORY_ERROR_OPERATION.
+ UINT32 VendorSyndrome;
+ UINT64 MemoryArrayErrorAddress;
+ UINT64 DeviceErrorAddress;
+ UINT32 ErrorResolution;
+} SMBIOS_TABLE_TYPE33;
+
+///
+/// Management Device - Type.
+///
+typedef enum {
+ ManagementDeviceTypeOther = 0x01,
+ ManagementDeviceTypeUnknown = 0x02,
+ ManagementDeviceTypeLm75 = 0x03,
+ ManagementDeviceTypeLm78 = 0x04,
+ ManagementDeviceTypeLm79 = 0x05,
+ ManagementDeviceTypeLm80 = 0x06,
+ ManagementDeviceTypeLm81 = 0x07,
+ ManagementDeviceTypeAdm9240 = 0x08,
+ ManagementDeviceTypeDs1780 = 0x09,
+ ManagementDeviceTypeMaxim1617 = 0x0A,
+ ManagementDeviceTypeGl518Sm = 0x0B,
+ ManagementDeviceTypeW83781D = 0x0C,
+ ManagementDeviceTypeHt82H791 = 0x0D
+} MISC_MANAGEMENT_DEVICE_TYPE;
+
+///
+/// Management Device - Address Type.
+///
+typedef enum {
+ ManagementDeviceAddressTypeOther = 0x01,
+ ManagementDeviceAddressTypeUnknown = 0x02,
+ ManagementDeviceAddressTypeIOPort = 0x03,
+ ManagementDeviceAddressTypeMemory = 0x04,
+ ManagementDeviceAddressTypeSmbus = 0x05
+} MISC_MANAGEMENT_DEVICE_ADDRESS_TYPE;
+
+///
+/// Management Device (Type 34).
+///
+/// The information in this structure defines the attributes of a Management Device.
+/// A Management Device might control one or more fans or voltage, current, or temperature
+/// probes as defined by one or more Management Device Component structures.
+///
+typedef struct {
+ SMBIOS_STRUCTURE Hdr;
+ SMBIOS_TABLE_STRING Description;
+ UINT8 Type; ///< The enumeration value from MISC_MANAGEMENT_DEVICE_TYPE.
+ UINT32 Address;
+ UINT8 AddressType; ///< The enumeration value from MISC_MANAGEMENT_DEVICE_ADDRESS_TYPE.
+} SMBIOS_TABLE_TYPE34;
+
+///
+/// Management Device Component (Type 35)
+///
+/// This structure associates a cooling device or environmental probe with structures
+/// that define the controlling hardware device and (optionally) the component's thresholds.
+///
+typedef struct {
+ SMBIOS_STRUCTURE Hdr;
+ SMBIOS_TABLE_STRING Description;
+ UINT16 ManagementDeviceHandle;
+ UINT16 ComponentHandle;
+ UINT16 ThresholdHandle;
+} SMBIOS_TABLE_TYPE35;
+
+///
+/// Management Device Threshold Data (Type 36).
+///
+/// The information in this structure defines threshold information for
+/// a component (probe or cooling-unit) contained within a Management Device.
+///
+typedef struct {
+ SMBIOS_STRUCTURE Hdr;
+ UINT16 LowerThresholdNonCritical;
+ UINT16 UpperThresholdNonCritical;
+ UINT16 LowerThresholdCritical;
+ UINT16 UpperThresholdCritical;
+ UINT16 LowerThresholdNonRecoverable;
+ UINT16 UpperThresholdNonRecoverable;
+} SMBIOS_TABLE_TYPE36;
+
+///
+/// Memory Channel Entry.
+///
+typedef struct {
+ UINT8 DeviceLoad;
+ UINT16 DeviceHandle;
+} MEMORY_DEVICE;
+
+///
+/// Memory Channel - Channel Type.
+///
+typedef enum {
+ MemoryChannelTypeOther = 0x01,
+ MemoryChannelTypeUnknown = 0x02,
+ MemoryChannelTypeRambus = 0x03,
+ MemoryChannelTypeSyncLink = 0x04
+} MEMORY_CHANNEL_TYPE;
+
+///
+/// Memory Channel (Type 37)
+///
+/// The information in this structure provides the correlation between a Memory Channel
+/// and its associated Memory Devices. Each device presents one or more loads to the channel.
+/// The sum of all device loads cannot exceed the channel's defined maximum.
+///
+typedef struct {
+ SMBIOS_STRUCTURE Hdr;
+ UINT8 ChannelType;
+ UINT8 MaximumChannelLoad;
+ UINT8 MemoryDeviceCount;
+ MEMORY_DEVICE MemoryDevice[1];
+} SMBIOS_TABLE_TYPE37;
+
+///
+/// IPMI Device Information - BMC Interface Type
+///
+typedef enum {
+ IPMIDeviceInfoInterfaceTypeUnknown = 0x00,
+ IPMIDeviceInfoInterfaceTypeKCS = 0x01, ///< The Keyboard Controller Style.
+ IPMIDeviceInfoInterfaceTypeSMIC = 0x02, ///< The Server Management Interface Chip.
+ IPMIDeviceInfoInterfaceTypeBT = 0x03, ///< The Block Transfer
+ IPMIDeviceInfoInterfaceTypeSSIF = 0x04 ///< SMBus System Interface
+} BMC_INTERFACE_TYPE;
+
+///
+/// IPMI Device Information (Type 38).
+///
+/// The information in this structure defines the attributes of an
+/// Intelligent Platform Management Interface (IPMI) Baseboard Management Controller (BMC).
+///
+/// The Type 42 structure can also be used to describe a physical management controller
+/// host interface and one or more protocols that share that interface. If IPMI is not
+/// shared with other protocols, either the Type 38 or Type 42 structures can be used.
+/// Providing Type 38 is recommended for backward compatibility.
+///
+typedef struct {
+ SMBIOS_STRUCTURE Hdr;
+ UINT8 InterfaceType; ///< The enumeration value from BMC_INTERFACE_TYPE.
+ UINT8 IPMISpecificationRevision;
+ UINT8 I2CSlaveAddress;
+ UINT8 NVStorageDeviceAddress;
+ UINT64 BaseAddress;
+ UINT8 BaseAddressModifier_InterruptInfo;
+ UINT8 InterruptNumber;
+} SMBIOS_TABLE_TYPE38;
+
+///
+/// System Power Supply - Power Supply Characteristics.
+///
+typedef struct {
+ UINT16 PowerSupplyHotReplaceable : 1;
+ UINT16 PowerSupplyPresent : 1;
+ UINT16 PowerSupplyUnplugged : 1;
+ UINT16 InputVoltageRangeSwitch : 4;
+ UINT16 PowerSupplyStatus : 3;
+ UINT16 PowerSupplyType : 4;
+ UINT16 Reserved : 2;
+} SYS_POWER_SUPPLY_CHARACTERISTICS;
+
+///
+/// System Power Supply (Type 39).
+///
+/// This structure identifies attributes of a system power supply. One instance
+/// of this record is present for each possible power supply in a system.
+///
+typedef struct {
+ SMBIOS_STRUCTURE Hdr;
+ UINT8 PowerUnitGroup;
+ SMBIOS_TABLE_STRING Location;
+ SMBIOS_TABLE_STRING DeviceName;
+ SMBIOS_TABLE_STRING Manufacturer;
+ SMBIOS_TABLE_STRING SerialNumber;
+ SMBIOS_TABLE_STRING AssetTagNumber;
+ SMBIOS_TABLE_STRING ModelPartNumber;
+ SMBIOS_TABLE_STRING RevisionLevel;
+ UINT16 MaxPowerCapacity;
+ SYS_POWER_SUPPLY_CHARACTERISTICS PowerSupplyCharacteristics;
+ UINT16 InputVoltageProbeHandle;
+ UINT16 CoolingDeviceHandle;
+ UINT16 InputCurrentProbeHandle;
+} SMBIOS_TABLE_TYPE39;
+
+///
+/// Additional Information Entry Format.
+///
+typedef struct {
+ UINT8 EntryLength;
+ UINT16 ReferencedHandle;
+ UINT8 ReferencedOffset;
+ SMBIOS_TABLE_STRING EntryString;
+ UINT8 Value[1];
+} ADDITIONAL_INFORMATION_ENTRY;
+
+///
+/// Additional Information (Type 40).
+///
+/// This structure is intended to provide additional information for handling unspecified
+/// enumerated values and interim field updates in another structure.
+///
+typedef struct {
+ SMBIOS_STRUCTURE Hdr;
+ UINT8 NumberOfAdditionalInformationEntries;
+ ADDITIONAL_INFORMATION_ENTRY AdditionalInfoEntries[1];
+} SMBIOS_TABLE_TYPE40;
+
+///
+/// Onboard Devices Extended Information - Onboard Device Types.
+///
+typedef enum {
+ OnBoardDeviceExtendedTypeOther = 0x01,
+ OnBoardDeviceExtendedTypeUnknown = 0x02,
+ OnBoardDeviceExtendedTypeVideo = 0x03,
+ OnBoardDeviceExtendedTypeScsiController = 0x04,
+ OnBoardDeviceExtendedTypeEthernet = 0x05,
+ OnBoardDeviceExtendedTypeTokenRing = 0x06,
+ OnBoardDeviceExtendedTypeSound = 0x07,
+ OnBoardDeviceExtendedTypePATAController = 0x08,
+ OnBoardDeviceExtendedTypeSATAController = 0x09,
+ OnBoardDeviceExtendedTypeSASController = 0x0A,
+ OnBoardDeviceExtendedTypeWirelessLAN = 0x0B,
+ OnBoardDeviceExtendedTypeBluetooth = 0x0C,
+ OnBoardDeviceExtendedTypeWWAN = 0x0D,
+ OnBoardDeviceExtendedTypeeMMC = 0x0E,
+ OnBoardDeviceExtendedTypeNvme = 0x0F,
+ OnBoardDeviceExtendedTypeUfc = 0x10
+} ONBOARD_DEVICE_EXTENDED_INFO_TYPE;
+
+///
+/// Onboard Devices Extended Information (Type 41).
+///
+/// The information in this structure defines the attributes of devices that
+/// are onboard (soldered onto) a system element, usually the baseboard.
+/// In general, an entry in this table implies that the BIOS has some level of
+/// control over the enabling of the associated device for use by the system.
+///
+typedef struct {
+ SMBIOS_STRUCTURE Hdr;
+ SMBIOS_TABLE_STRING ReferenceDesignation;
+ UINT8 DeviceType; ///< The enumeration value from ONBOARD_DEVICE_EXTENDED_INFO_TYPE
+ UINT8 DeviceTypeInstance;
+ UINT16 SegmentGroupNum;
+ UINT8 BusNum;
+ UINT8 DevFuncNum;
+} SMBIOS_TABLE_TYPE41;
+
+///
+/// Management Controller Host Interface - Protocol Record Data Format.
+///
+typedef struct {
+ UINT8 ProtocolType;
+ UINT8 ProtocolTypeDataLen;
+ UINT8 ProtocolTypeData[1];
+} MC_HOST_INTERFACE_PROTOCOL_RECORD;
+
+///
+/// Management Controller Host Interface - Interface Types.
+/// 00h - 3Fh: MCTP Host Interfaces
+///
+typedef enum {
+ MCHostInterfaceTypeNetworkHostInterface = 0x40,
+ MCHostInterfaceTypeOemDefined = 0xF0
+} MC_HOST_INTERFACE_TYPE;
+
+///
+/// Management Controller Host Interface - Protocol Types.
+///
+typedef enum {
+ MCHostInterfaceProtocolTypeIPMI = 0x02,
+ MCHostInterfaceProtocolTypeMCTP = 0x03,
+ MCHostInterfaceProtocolTypeRedfishOverIP = 0x04,
+ MCHostInterfaceProtocolTypeOemDefined = 0xF0
+} MC_HOST_INTERFACE_PROTOCOL_TYPE;
+
+///
+/// Management Controller Host Interface (Type 42).
+///
+/// The information in this structure defines the attributes of a Management
+/// Controller Host Interface that is not discoverable by "Plug and Play" mechanisms.
+///
+/// Type 42 should be used for management controller host interfaces that use protocols
+/// other than IPMI or that use multiple protocols on a single host interface type.
+///
+/// This structure should also be provided if IPMI is shared with other protocols
+/// over the same interface hardware. If IPMI is not shared with other protocols,
+/// either the Type 38 or Type 42 structures can be used. Providing Type 38 is
+/// recommended for backward compatibility. The structures are not required to
+/// be mutually exclusive. Type 38 and Type 42 structures may be implemented
+/// simultaneously to provide backward compatibility with IPMI applications or drivers
+/// that do not yet recognize the Type 42 structure.
+///
+typedef struct {
+ SMBIOS_STRUCTURE Hdr;
+ UINT8 InterfaceType; ///< The enumeration value from MC_HOST_INTERFACE_TYPE
+ UINT8 InterfaceTypeSpecificDataLength;
+ UINT8 InterfaceTypeSpecificData[4]; ///< This field has a minimum of four bytes
+} SMBIOS_TABLE_TYPE42;
+
+///
+/// Processor Specific Block - Processor Architecture Type
+///
+typedef enum {
+ ProcessorSpecificBlockArchTypeReserved = 0x00,
+ ProcessorSpecificBlockArchTypeIa32 = 0x01,
+ ProcessorSpecificBlockArchTypeX64 = 0x02,
+ ProcessorSpecificBlockArchTypeItanium = 0x03,
+ ProcessorSpecificBlockArchTypeAarch32 = 0x04,
+ ProcessorSpecificBlockArchTypeAarch64 = 0x05,
+ ProcessorSpecificBlockArchTypeRiscVRV32 = 0x06,
+ ProcessorSpecificBlockArchTypeRiscVRV64 = 0x07,
+ ProcessorSpecificBlockArchTypeRiscVRV128 = 0x08,
+ ProcessorSpecificBlockArchTypeLoongArch32 = 0x09,
+ ProcessorSpecificBlockArchTypeLoongArch64 = 0x0A
+} PROCESSOR_SPECIFIC_BLOCK_ARCH_TYPE;
+
+///
+/// Processor Specific Block is the standard container of processor-specific data.
+///
+typedef struct {
+ UINT8 Length;
+ UINT8 ProcessorArchType;
+ ///
+ /// Below followed by Processor-specific data
+ ///
+ ///
+} PROCESSOR_SPECIFIC_BLOCK;
+
+///
+/// Processor Additional Information(Type 44).
+///
+/// The information in this structure defines the processor additional information in case
+/// SMBIOS type 4 is not sufficient to describe processor characteristics.
+/// The SMBIOS type 44 structure has a reference handle field to link back to the related
+/// SMBIOS type 4 structure. There may be multiple SMBIOS type 44 structures linked to the
+/// same SMBIOS type 4 structure. For example, when cores are not identical in a processor,
+/// SMBIOS type 44 structures describe different core-specific information.
+///
+/// SMBIOS type 44 defines the standard header for the processor-specific block, while the
+/// contents of processor-specific data are maintained by processor
+/// architecture workgroups or vendors in separate documents.
+///
+typedef struct {
+ SMBIOS_STRUCTURE Hdr;
+ SMBIOS_HANDLE RefHandle; ///< This field refer to associated SMBIOS type 4
+ ///
+ /// Below followed by Processor-specific block
+ ///
+ PROCESSOR_SPECIFIC_BLOCK ProcessorSpecificBlock;
+} SMBIOS_TABLE_TYPE44;
+
+///
+/// TPM Device (Type 43).
+///
+typedef struct {
+ SMBIOS_STRUCTURE Hdr;
+ UINT8 VendorID[4];
+ UINT8 MajorSpecVersion;
+ UINT8 MinorSpecVersion;
+ UINT32 FirmwareVersion1;
+ UINT32 FirmwareVersion2;
+ SMBIOS_TABLE_STRING Description;
+ UINT64 Characteristics;
+ UINT32 OemDefined;
+} SMBIOS_TABLE_TYPE43;
+
+///
+/// Firmware Inventory Version Format Type (Type 45).
+///
+typedef enum {
+ VersionFormatTypeFreeForm = 0x00,
+ VersionFormatTypeMajorMinor = 0x01,
+ VersionFormatType32BitHex = 0x02,
+ VersionFormatType64BitHex = 0x03,
+ VersionFormatTypeReserved = 0x04, /// 0x04 - 0x7F are reserved
+ VersionFormatTypeOem = 0x80 /// 0x80 - 0xFF are BIOS Vendor/OEM-specific
+} FIRMWARE_INVENTORY_VERSION_FORMAT_TYPE;
+
+///
+/// Firmware Inventory Firmware Id Format Type (Type 45).
+///
+typedef enum {
+ FirmwareIdFormatTypeFreeForm = 0x00,
+ FirmwareIdFormatTypeUuid = 0x01,
+ FirmwareIdFormatTypeReserved = 0x04, /// 0x04 - 0x7F are reserved
+ InventoryFirmwareIdFormatTypeOem = 0x80 /// 0x80 - 0xFF are BIOS Vendor/OEM-specific
+} FIRMWARE_INVENTORY_FIRMWARE_ID_FORMAT_TYPE;
+
+///
+/// Firmware Inventory Firmware Characteristics (Type 45).
+///
+typedef struct {
+ UINT16 Updatable : 1;
+ UINT16 WriteProtected : 1;
+ UINT16 Reserved : 14;
+} FIRMWARE_CHARACTERISTICS;
+
+///
+/// Firmware Inventory State Information (Type 45).
+///
+typedef enum {
+ FirmwareInventoryStateOther = 0x01,
+ FirmwareInventoryStateUnknown = 0x02,
+ FirmwareInventoryStateDisabled = 0x03,
+ FirmwareInventoryStateEnabled = 0x04,
+ FirmwareInventoryStateAbsent = 0x05,
+ FirmwareInventoryStateStandbyOffline = 0x06,
+ FirmwareInventoryStateStandbySpare = 0x07,
+ FirmwareInventoryStateUnavailableOffline = 0x08
+} FIRMWARE_INVENTORY_STATE;
+
+///
+/// Firmware Inventory Information (Type 45)
+///
+/// The information in this structure defines an inventory of firmware
+/// components in the system. This can include firmware components such as
+/// BIOS, BMC, as well as firmware for other devices in the system.
+/// The information can be used by software to display the firmware inventory
+/// in a uniform manner. It can also be used by a management controller,
+/// such as a BMC, for remote system management.
+/// This structure is not intended to replace other standard programmatic
+/// interfaces for firmware updates.
+/// One Type 45 structure is provided for each firmware component.
+///
+typedef struct {
+ SMBIOS_STRUCTURE Hdr;
+ SMBIOS_TABLE_STRING FirmwareComponentName;
+ SMBIOS_TABLE_STRING FirmwareVersion;
+ UINT8 FirmwareVersionFormat; ///< The enumeration value from FIRMWARE_INVENTORY_VERSION_FORMAT_TYPE
+ SMBIOS_TABLE_STRING FirmwareId;
+ UINT8 FirmwareIdFormat; ///< The enumeration value from FIRMWARE_INVENTORY_FIRMWARE_ID_FORMAT_TYPE.
+ SMBIOS_TABLE_STRING ReleaseDate;
+ SMBIOS_TABLE_STRING Manufacturer;
+ SMBIOS_TABLE_STRING LowestSupportedVersion;
+ UINT64 ImageSize;
+ FIRMWARE_CHARACTERISTICS Characteristics;
+ UINT8 State; ///< The enumeration value from FIRMWARE_INVENTORY_STATE.
+ UINT8 AssociatedComponentCount;
+ ///
+ /// zero or n-number of handles depends on AssociatedComponentCount
+ /// handles are of type SMBIOS_HANDLE
+ ///
+} SMBIOS_TABLE_TYPE45;
+
+///
+/// String Property IDs (Type 46).
+///
+typedef enum {
+ StringPropertyIdNone = 0x0000,
+ StringPropertyIdDevicePath = 0x0001,
+ StringPropertyIdReserved = 0x0002, /// Reserved 0x0002 - 0x7FFF
+ StringPropertyIdBiosVendor = 0x8000, /// BIOS vendor 0x8000 - 0xBFFF
+ StringPropertyIdOem = 0xC000 /// OEM range 0xC000 - 0xFFFF
+} STRING_PROPERTY_ID;
+
+///
+/// This structure defines a string property for another structure.
+/// This allows adding string properties that are common to several structures
+/// without having to modify the definitions of these structures.
+/// Multiple type 46 structures can add string properties to the same
+/// parent structure.
+///
+typedef struct {
+ SMBIOS_STRUCTURE Hdr;
+ UINT16 StringPropertyId; ///< The enumeration value from STRING_PROPERTY_ID.
+ SMBIOS_TABLE_STRING StringPropertyValue;
+ SMBIOS_HANDLE ParentHandle;
+} SMBIOS_TABLE_TYPE46;
+
+///
+/// Inactive (Type 126)
+///
+typedef struct {
+ SMBIOS_STRUCTURE Hdr;
+} SMBIOS_TABLE_TYPE126;
+
+///
+/// End-of-Table (Type 127)
+///
+typedef struct {
+ SMBIOS_STRUCTURE Hdr;
+} SMBIOS_TABLE_TYPE127;
+
+///
+/// Union of all the possible SMBIOS record types.
+///
+typedef union {
+ SMBIOS_STRUCTURE *Hdr;
+ SMBIOS_TABLE_TYPE0 *Type0;
+ SMBIOS_TABLE_TYPE1 *Type1;
+ SMBIOS_TABLE_TYPE2 *Type2;
+ SMBIOS_TABLE_TYPE3 *Type3;
+ SMBIOS_TABLE_TYPE4 *Type4;
+ SMBIOS_TABLE_TYPE5 *Type5;
+ SMBIOS_TABLE_TYPE6 *Type6;
+ SMBIOS_TABLE_TYPE7 *Type7;
+ SMBIOS_TABLE_TYPE8 *Type8;
+ SMBIOS_TABLE_TYPE9 *Type9;
+ SMBIOS_TABLE_TYPE10 *Type10;
+ SMBIOS_TABLE_TYPE11 *Type11;
+ SMBIOS_TABLE_TYPE12 *Type12;
+ SMBIOS_TABLE_TYPE13 *Type13;
+ SMBIOS_TABLE_TYPE14 *Type14;
+ SMBIOS_TABLE_TYPE15 *Type15;
+ SMBIOS_TABLE_TYPE16 *Type16;
+ SMBIOS_TABLE_TYPE17 *Type17;
+ SMBIOS_TABLE_TYPE18 *Type18;
+ SMBIOS_TABLE_TYPE19 *Type19;
+ SMBIOS_TABLE_TYPE20 *Type20;
+ SMBIOS_TABLE_TYPE21 *Type21;
+ SMBIOS_TABLE_TYPE22 *Type22;
+ SMBIOS_TABLE_TYPE23 *Type23;
+ SMBIOS_TABLE_TYPE24 *Type24;
+ SMBIOS_TABLE_TYPE25 *Type25;
+ SMBIOS_TABLE_TYPE26 *Type26;
+ SMBIOS_TABLE_TYPE27 *Type27;
+ SMBIOS_TABLE_TYPE28 *Type28;
+ SMBIOS_TABLE_TYPE29 *Type29;
+ SMBIOS_TABLE_TYPE30 *Type30;
+ SMBIOS_TABLE_TYPE31 *Type31;
+ SMBIOS_TABLE_TYPE32 *Type32;
+ SMBIOS_TABLE_TYPE33 *Type33;
+ SMBIOS_TABLE_TYPE34 *Type34;
+ SMBIOS_TABLE_TYPE35 *Type35;
+ SMBIOS_TABLE_TYPE36 *Type36;
+ SMBIOS_TABLE_TYPE37 *Type37;
+ SMBIOS_TABLE_TYPE38 *Type38;
+ SMBIOS_TABLE_TYPE39 *Type39;
+ SMBIOS_TABLE_TYPE40 *Type40;
+ SMBIOS_TABLE_TYPE41 *Type41;
+ SMBIOS_TABLE_TYPE42 *Type42;
+ SMBIOS_TABLE_TYPE43 *Type43;
+ SMBIOS_TABLE_TYPE44 *Type44;
+ SMBIOS_TABLE_TYPE45 *Type45;
+ SMBIOS_TABLE_TYPE46 *Type46;
+ SMBIOS_TABLE_TYPE126 *Type126;
+ SMBIOS_TABLE_TYPE127 *Type127;
+ UINT8 *Raw;
+} SMBIOS_STRUCTURE_POINTER;
+
+#pragma pack()
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/SmBus.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/SmBus.h
new file mode 100644
index 0000000000..ad0d8b0e8f
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/SmBus.h
@@ -0,0 +1,73 @@
+/** @file
+ This file declares the SMBus definitions defined in SmBus Specification V2.0
+ and defined in PI1.0 specification volume 5.
+
+ Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _SMBUS_H_
+#define _SMBUS_H_
+
+///
+/// UDID of SMBUS device.
+///
+typedef struct {
+ UINT32 VendorSpecificId;
+ UINT16 SubsystemDeviceId;
+ UINT16 SubsystemVendorId;
+ UINT16 Interface;
+ UINT16 DeviceId;
+ UINT16 VendorId;
+ UINT8 VendorRevision;
+ UINT8 DeviceCapabilities;
+} EFI_SMBUS_UDID;
+
+///
+/// Smbus Device Address
+///
+typedef struct {
+ ///
+ /// The SMBUS hardware address to which the SMBUS device is preassigned or allocated.
+ ///
+ UINTN SmbusDeviceAddress : 7;
+} EFI_SMBUS_DEVICE_ADDRESS;
+
+typedef struct {
+ ///
+ /// The SMBUS hardware address to which the SMBUS device is preassigned or
+ /// allocated. Type EFI_SMBUS_DEVICE_ADDRESS is defined in EFI_PEI_SMBUS2_PPI.Execute().
+ ///
+ EFI_SMBUS_DEVICE_ADDRESS SmbusDeviceAddress;
+ ///
+ /// The SMBUS Unique Device Identifier (UDID) as defined in EFI_SMBUS_UDID.
+ /// Type EFI_SMBUS_UDID is defined in EFI_PEI_SMBUS2_PPI.ArpDevice().
+ ///
+ EFI_SMBUS_UDID SmbusDeviceUdid;
+} EFI_SMBUS_DEVICE_MAP;
+
+///
+/// Smbus Operations
+///
+typedef enum _EFI_SMBUS_OPERATION {
+ EfiSmbusQuickRead,
+ EfiSmbusQuickWrite,
+ EfiSmbusReceiveByte,
+ EfiSmbusSendByte,
+ EfiSmbusReadByte,
+ EfiSmbusWriteByte,
+ EfiSmbusReadWord,
+ EfiSmbusWriteWord,
+ EfiSmbusReadBlock,
+ EfiSmbusWriteBlock,
+ EfiSmbusProcessCall,
+ EfiSmbusBWBRProcessCall
+} EFI_SMBUS_OPERATION;
+
+///
+/// EFI_SMBUS_DEVICE_COMMAND
+///
+typedef UINTN EFI_SMBUS_DEVICE_COMMAND;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/Spdm.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/Spdm.h
new file mode 100644
index 0000000000..24be328a42
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/Spdm.h
@@ -0,0 +1,318 @@
+/** @file
+ Definitions of Security Protocol & Data Model Specification (SPDM)
+ version 1.0.0 in Distributed Management Task Force (DMTF).
+
+Copyright (c) 2019, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __SPDM_H__
+#define __SPDM_H__
+
+#pragma pack(1)
+
+///
+/// SPDM response code
+///
+#define SPDM_DIGESTS 0x01
+#define SPDM_CERTIFICATE 0x02
+#define SPDM_CHALLENGE_AUTH 0x03
+#define SPDM_VERSION 0x04
+#define SPDM_MEASUREMENTS 0x60
+#define SPDM_CAPABILITIES 0x61
+#define SPDM_SET_CERT_RESPONSE 0x62
+#define SPDM_ALGORITHMS 0x63
+#define SPDM_ERROR 0x7F
+///
+/// SPDM request code
+///
+#define SPDM_GET_DIGESTS 0x81
+#define SPDM_GET_CERTIFICATE 0x82
+#define SPDM_CHALLENGE 0x83
+#define SPDM_GET_VERSION 0x84
+#define SPDM_GET_MEASUREMENTS 0xE0
+#define SPDM_GET_CAPABILITIES 0xE1
+#define SPDM_NEGOTIATE_ALGORITHMS 0xE3
+#define SPDM_RESPOND_IF_READY 0xFF
+
+///
+/// SPDM message header
+///
+typedef struct {
+ UINT8 SPDMVersion;
+ UINT8 RequestResponseCode;
+ UINT8 Param1;
+ UINT8 Param2;
+} SPDM_MESSAGE_HEADER;
+
+#define SPDM_MESSAGE_VERSION 0x10
+
+///
+/// SPDM GET_VERSION request
+///
+typedef struct {
+ SPDM_MESSAGE_HEADER Header;
+} SPDM_GET_VERSION_REQUEST;
+
+///
+/// SPDM GET_VERSION response
+///
+typedef struct {
+ SPDM_MESSAGE_HEADER Header;
+ UINT8 Reserved;
+ UINT8 VersionNumberEntryCount;
+ // SPDM_VERSION_NUMBER VersionNumberEntry[VersionNumberEntryCount];
+} SPDM_VERSION_RESPONSE;
+
+///
+/// SPDM VERSION structure
+///
+typedef struct {
+ UINT16 Alpha : 4;
+ UINT16 UpdateVersionNumber : 4;
+ UINT16 MinorVersion : 4;
+ UINT16 MajorVersion : 4;
+} SPDM_VERSION_NUMBER;
+
+///
+/// SPDM GET_CAPABILITIES request
+///
+typedef struct {
+ SPDM_MESSAGE_HEADER Header;
+} SPDM_GET_CAPABILITIES_REQUEST;
+
+///
+/// SPDM GET_CAPABILITIES response
+///
+typedef struct {
+ SPDM_MESSAGE_HEADER Header;
+ UINT8 Reserved;
+ UINT8 CTExponent;
+ UINT16 Reserved2;
+ UINT32 Flags;
+} SPDM_CAPABILITIES_RESPONSE;
+
+///
+/// SPDM GET_CAPABILITIES response Flags
+///
+#define SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_CACHE_CAP BIT0
+#define SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_CERT_CAP BIT1
+#define SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_CHAL_CAP BIT2
+#define SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_MEAS_CAP (BIT3 | BIT4)
+#define SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_MEAS_CAP_NO_SIG BIT3
+#define SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_MEAS_CAP_SIG BIT4
+#define SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_MEAS_FRESH_CAP BIT5
+
+///
+/// SPDM NEGOTIATE_ALGORITHMS request
+///
+typedef struct {
+ SPDM_MESSAGE_HEADER Header;
+ UINT16 Length;
+ UINT8 MeasurementSpecification;
+ UINT8 Reserved;
+ UINT32 BaseAsymAlgo;
+ UINT32 BaseHashAlgo;
+ UINT8 Reserved2[12];
+ UINT8 ExtAsymCount;
+ UINT8 ExtHashCount;
+ UINT16 Reserved3;
+ // UINT32 ExtAsym[ExtAsymCount];
+ // UINT32 ExtHash[ExtHashCount];
+} SPDM_NEGOTIATE_ALGORITHMS_REQUEST;
+
+///
+/// SPDM NEGOTIATE_ALGORITHMS request BaseAsymAlgo
+///
+#define SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSASSA_2048 BIT0
+#define SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSAPSS_2048 BIT1
+#define SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSASSA_3072 BIT2
+#define SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSAPSS_3072 BIT3
+#define SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_ECDSA_ECC_NIST_P256 BIT4
+#define SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSASSA_4096 BIT5
+#define SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSAPSS_4096 BIT6
+#define SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_ECDSA_ECC_NIST_P384 BIT7
+#define SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_ECDSA_ECC_NIST_P521 BIT8
+
+///
+/// SPDM NEGOTIATE_ALGORITHMS request BaseHashAlgo
+///
+#define SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA_256 BIT0
+#define SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA_384 BIT1
+#define SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA_512 BIT2
+#define SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA3_256 BIT3
+#define SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA3_384 BIT4
+#define SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA3_512 BIT5
+
+///
+/// SPDM NEGOTIATE_ALGORITHMS response
+///
+typedef struct {
+ SPDM_MESSAGE_HEADER Header;
+ UINT16 Length;
+ UINT8 MeasurementSpecificationSel;
+ UINT8 Reserved;
+ UINT32 MeasurementHashAlgo;
+ UINT32 BaseAsymSel;
+ UINT32 BaseHashSel;
+ UINT8 Reserved2[12];
+ UINT8 ExtAsymSelCount;
+ UINT8 ExtHashSelCount;
+ UINT16 Reserved3;
+ // UINT32 ExtAsymSel[ExtAsymSelCount];
+ // UINT32 ExtHashSel[ExtHashSelCount];
+} SPDM_ALGORITHMS_RESPONSE;
+
+///
+/// SPDM NEGOTIATE_ALGORITHMS response MeasurementHashAlgo
+///
+#define SPDM_ALGORITHMS_MEASUREMENT_HASH_ALGO_RAW_BIT_STREAM_ONLY BIT0
+#define SPDM_ALGORITHMS_MEASUREMENT_HASH_ALGO_TPM_ALG_SHA_256 BIT1
+#define SPDM_ALGORITHMS_MEASUREMENT_HASH_ALGO_TPM_ALG_SHA_384 BIT2
+#define SPDM_ALGORITHMS_MEASUREMENT_HASH_ALGO_TPM_ALG_SHA_512 BIT3
+#define SPDM_ALGORITHMS_MEASUREMENT_HASH_ALGO_TPM_ALG_SHA3_256 BIT4
+#define SPDM_ALGORITHMS_MEASUREMENT_HASH_ALGO_TPM_ALG_SHA3_384 BIT5
+#define SPDM_ALGORITHMS_MEASUREMENT_HASH_ALGO_TPM_ALG_SHA3_512 BIT6
+
+///
+/// SPDM GET_DIGESTS request
+///
+typedef struct {
+ SPDM_MESSAGE_HEADER Header;
+} SPDM_GET_DIGESTS_REQUEST;
+
+///
+/// SPDM GET_DIGESTS response
+///
+typedef struct {
+ SPDM_MESSAGE_HEADER Header;
+ // UINT8 Digest[DigestSize];
+} SPDM_DIGESTS_RESPONSE;
+
+///
+/// SPDM GET_DIGESTS request
+///
+typedef struct {
+ SPDM_MESSAGE_HEADER Header;
+ UINT16 Offset;
+ UINT16 Length;
+} SPDM_GET_CERTIFICATE_REQUEST;
+
+///
+/// SPDM GET_DIGESTS response
+///
+typedef struct {
+ SPDM_MESSAGE_HEADER Header;
+ UINT16 PortionLength;
+ UINT16 RemainderLength;
+ // UINT8 CertChain[CertChainSize];
+} SPDM_CERTIFICATE_RESPONSE;
+
+///
+/// SPDM CHALLENGE request
+///
+typedef struct {
+ SPDM_MESSAGE_HEADER Header;
+ UINT8 Nonce[32];
+} SPDM_CHALLENGE_REQUEST;
+
+///
+/// SPDM CHALLENGE response
+///
+typedef struct {
+ SPDM_MESSAGE_HEADER Header;
+ // UINT8 CertChainHash[DigestSize];
+ // UINT8 Nonce[32];
+ // UINT8 MeasurementSummaryHash[DigestSize];
+ // UINT16 OpaqueLength;
+ // UINT8 OpaqueData[OpaqueLength];
+ // UINT8 Signature[KeySize];
+} SPDM_CHALLENGE_AUTH_RESPONSE;
+
+///
+/// SPDM GET_MEASUREMENTS request
+///
+typedef struct {
+ SPDM_MESSAGE_HEADER Header;
+ UINT8 Nonce[32];
+} SPDM_GET_MEASUREMENTS_REQUEST;
+
+///
+/// SPDM MEASUREMENTS block common header
+///
+typedef struct {
+ UINT8 Index;
+ UINT8 MeasurementSpecification;
+ UINT16 MeasurementSize;
+ // UINT8 Measurement[MeasurementSize];
+} SPDM_MEASUREMENT_BLOCK_COMMON_HEADER;
+
+#define SPDM_MEASUREMENT_BLOCK_HEADER_SPECIFICATION_DMTF BIT0
+
+///
+/// SPDM MEASUREMENTS block DMTF header
+///
+typedef struct {
+ UINT8 DMTFSpecMeasurementValueType;
+ UINT16 DMTFSpecMeasurementValueSize;
+ // UINT8 DMTFSpecMeasurementValue[DMTFSpecMeasurementValueSize];
+} SPDM_MEASUREMENT_BLOCK_DMTF_HEADER;
+
+///
+/// SPDM MEASUREMENTS block MeasurementValueType
+///
+#define SPDM_MEASUREMENT_BLOCK_MEASUREMENT_TYPE_IMMUTABLE_ROM 0
+#define SPDM_MEASUREMENT_BLOCK_MEASUREMENT_TYPE_MUTABLE_FIRMWARE 1
+#define SPDM_MEASUREMENT_BLOCK_MEASUREMENT_TYPE_HARDWARE_CONFIGURATION 2
+#define SPDM_MEASUREMENT_BLOCK_MEASUREMENT_TYPE_FIRMWARE_CONFIGURATION 3
+#define SPDM_MEASUREMENT_BLOCK_MEASUREMENT_TYPE_RAW_BIT_STREAM BIT7
+
+///
+/// SPDM GET_MEASUREMENTS response
+///
+typedef struct {
+ SPDM_MESSAGE_HEADER Header;
+ UINT8 NumberOfBlocks;
+ UINT8 MeasurementRecordLength[3];
+ // UINT8 MeasurementRecord[MeasurementRecordLength];
+ // UINT8 Nonce[32];
+ // UINT16 OpaqueLength;
+ // UINT8 OpaqueData[OpaqueLength];
+ // UINT8 Signature[KeySize];
+} SPDM_MEASUREMENTS_RESPONSE;
+
+///
+/// SPDM ERROR response
+///
+typedef struct {
+ SPDM_MESSAGE_HEADER Header;
+ // Param1 == Error Code
+ // Param2 == Error Data
+ // UINT8 ExtendedErrorData[];
+} SPDM_ERROR_RESPONSE;
+
+///
+/// SPDM error code
+///
+#define SPDM_ERROR_CODE_INVALID_REQUEST 0x01
+#define SPDM_ERROR_CODE_BUSY 0x03
+#define SPDM_ERROR_CODE_UNEXPECTED_REQUEST 0x04
+#define SPDM_ERROR_CODE_UNSPECIFIED 0x05
+#define SPDM_ERROR_CODE_UNSUPPORTED_REQUEST 0x07
+#define SPDM_ERROR_CODE_MAJOR_VERSION_MISMATCH 0x41
+#define SPDM_ERROR_CODE_RESPONSE_NOT_READY 0x42
+#define SPDM_ERROR_CODE_REQUEST_RESYNCH 0x43
+
+///
+/// SPDM RESPONSE_IF_READY request
+///
+typedef struct {
+ SPDM_MESSAGE_HEADER Header;
+ // Param1 == RequestCode
+ // Param2 == Token
+} SPDM_RESPONSE_IF_READY_REQUEST;
+
+#pragma pack()
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/TcgPhysicalPresence.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/TcgPhysicalPresence.h
new file mode 100644
index 0000000000..721e699245
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/TcgPhysicalPresence.h
@@ -0,0 +1,123 @@
+/** @file
+ TCG Physical Presence definition.
+
+Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _TCG_PHYSICAL_PRESENCE_H_
+#define _TCG_PHYSICAL_PRESENCE_H_
+
+//
+// TCG PP definition for physical presence ACPI function
+//
+#define TCG_ACPI_FUNCTION_GET_PHYSICAL_PRESENCE_INTERFACE_VERSION 1
+#define TCG_ACPI_FUNCTION_SUBMIT_REQUEST_TO_BIOS 2
+#define TCG_ACPI_FUNCTION_GET_PENDING_REQUEST_BY_OS 3
+#define TCG_ACPI_FUNCTION_GET_PLATFORM_ACTION_TO_TRANSITION_TO_BIOS 4
+#define TCG_ACPI_FUNCTION_RETURN_REQUEST_RESPONSE_TO_OS 5
+#define TCG_ACPI_FUNCTION_SUBMIT_PREFERRED_USER_LANGUAGE 6
+#define TCG_ACPI_FUNCTION_SUBMIT_REQUEST_TO_BIOS_2 7
+#define TCG_ACPI_FUNCTION_GET_USER_CONFIRMATION_STATUS_FOR_REQUEST 8
+
+//
+// TCG PP definition for TPM Operation Response to OS Environment
+//
+#define TCG_PP_OPERATION_RESPONSE_SUCCESS 0x0
+#define TCG_PP_OPERATION_RESPONSE_USER_ABORT 0xFFFFFFF0
+#define TCG_PP_OPERATION_RESPONSE_BIOS_FAILURE 0xFFFFFFF1
+
+//
+// TCG PP definition of return code for Return TPM Operation Response to OS Environment
+//
+#define TCG_PP_RETURN_TPM_OPERATION_RESPONSE_SUCCESS 0
+#define TCG_PP_RETURN_TPM_OPERATION_RESPONSE_FAILURE 1
+
+//
+// TCG PP definition of return code for Submit TPM Request to Pre-OS Environment
+// and Submit TPM Request to Pre-OS Environment 2
+//
+#define TCG_PP_SUBMIT_REQUEST_TO_PREOS_SUCCESS 0
+#define TCG_PP_SUBMIT_REQUEST_TO_PREOS_NOT_IMPLEMENTED 1
+#define TCG_PP_SUBMIT_REQUEST_TO_PREOS_GENERAL_FAILURE 2
+#define TCG_PP_SUBMIT_REQUEST_TO_PREOS_BLOCKED_BY_BIOS_SETTINGS 3
+
+//
+// TCG PP definition of return code for Get User Confirmation Status for Operation
+//
+#define TCG_PP_GET_USER_CONFIRMATION_NOT_IMPLEMENTED 0
+#define TCG_PP_GET_USER_CONFIRMATION_BIOS_ONLY 1
+#define TCG_PP_GET_USER_CONFIRMATION_BLOCKED_BY_BIOS_CONFIGURATION 2
+#define TCG_PP_GET_USER_CONFIRMATION_ALLOWED_AND_PPUSER_REQUIRED 3
+#define TCG_PP_GET_USER_CONFIRMATION_ALLOWED_AND_PPUSER_NOT_REQUIRED 4
+
+//
+// TCG PP definition of physical presence operation actions for TPM12
+//
+#define TCG_PHYSICAL_PRESENCE_NO_ACTION 0
+#define TCG_PHYSICAL_PRESENCE_ENABLE 1
+#define TCG_PHYSICAL_PRESENCE_DISABLE 2
+#define TCG_PHYSICAL_PRESENCE_ACTIVATE 3
+#define TCG_PHYSICAL_PRESENCE_DEACTIVATE 4
+#define TCG_PHYSICAL_PRESENCE_CLEAR 5
+#define TCG_PHYSICAL_PRESENCE_ENABLE_ACTIVATE 6
+#define TCG_PHYSICAL_PRESENCE_DEACTIVATE_DISABLE 7
+#define TCG_PHYSICAL_PRESENCE_SET_OWNER_INSTALL_TRUE 8
+#define TCG_PHYSICAL_PRESENCE_SET_OWNER_INSTALL_FALSE 9
+#define TCG_PHYSICAL_PRESENCE_ENABLE_ACTIVATE_OWNER_TRUE 10
+#define TCG_PHYSICAL_PRESENCE_DEACTIVATE_DISABLE_OWNER_FALSE 11
+#define TCG_PHYSICAL_PRESENCE_DEFERRED_PP_UNOWNERED_FIELD_UPGRADE 12
+#define TCG_PHYSICAL_PRESENCE_SET_OPERATOR_AUTH 13
+#define TCG_PHYSICAL_PRESENCE_CLEAR_ENABLE_ACTIVATE 14
+#define TCG_PHYSICAL_PRESENCE_SET_NO_PPI_PROVISION_FALSE 15
+#define TCG_PHYSICAL_PRESENCE_SET_NO_PPI_PROVISION_TRUE 16
+#define TCG_PHYSICAL_PRESENCE_SET_NO_PPI_CLEAR_FALSE 17
+#define TCG_PHYSICAL_PRESENCE_SET_NO_PPI_CLEAR_TRUE 18
+#define TCG_PHYSICAL_PRESENCE_SET_NO_PPI_MAINTENANCE_FALSE 19
+#define TCG_PHYSICAL_PRESENCE_SET_NO_PPI_MAINTENANCE_TRUE 20
+#define TCG_PHYSICAL_PRESENCE_ENABLE_ACTIVATE_CLEAR 21
+#define TCG_PHYSICAL_PRESENCE_ENABLE_ACTIVATE_CLEAR_ENABLE_ACTIVATE 22
+
+#define TCG_PHYSICAL_PRESENCE_VENDOR_SPECIFIC_OPERATION 128
+
+//
+// TCG PP definition of physical presence operation actions for TPM2
+//
+#define TCG2_PHYSICAL_PRESENCE_NO_ACTION 0
+#define TCG2_PHYSICAL_PRESENCE_ENABLE 1
+#define TCG2_PHYSICAL_PRESENCE_DISABLE 2
+#define TCG2_PHYSICAL_PRESENCE_CLEAR 5
+#define TCG2_PHYSICAL_PRESENCE_ENABLE_CLEAR 14
+#define TCG2_PHYSICAL_PRESENCE_SET_PP_REQUIRED_FOR_CLEAR_TRUE 17
+#define TCG2_PHYSICAL_PRESENCE_SET_PP_REQUIRED_FOR_CLEAR_FALSE 18
+#define TCG2_PHYSICAL_PRESENCE_ENABLE_CLEAR_2 21
+#define TCG2_PHYSICAL_PRESENCE_ENABLE_CLEAR_3 22
+#define TCG2_PHYSICAL_PRESENCE_SET_PCR_BANKS 23
+#define TCG2_PHYSICAL_PRESENCE_CHANGE_EPS 24
+#define TCG2_PHYSICAL_PRESENCE_SET_PP_REQUIRED_FOR_CHANGE_PCRS_FALSE 25
+#define TCG2_PHYSICAL_PRESENCE_SET_PP_REQUIRED_FOR_CHANGE_PCRS_TRUE 26
+#define TCG2_PHYSICAL_PRESENCE_SET_PP_REQUIRED_FOR_TURN_ON_FALSE 27
+#define TCG2_PHYSICAL_PRESENCE_SET_PP_REQUIRED_FOR_TURN_ON_TRUE 28
+#define TCG2_PHYSICAL_PRESENCE_SET_PP_REQUIRED_FOR_TURN_OFF_FALSE 29
+#define TCG2_PHYSICAL_PRESENCE_SET_PP_REQUIRED_FOR_TURN_OFF_TRUE 30
+#define TCG2_PHYSICAL_PRESENCE_SET_PP_REQUIRED_FOR_CHANGE_EPS_FALSE 31
+#define TCG2_PHYSICAL_PRESENCE_SET_PP_REQUIRED_FOR_CHANGE_EPS_TRUE 32
+#define TCG2_PHYSICAL_PRESENCE_LOG_ALL_DIGESTS 33
+#define TCG2_PHYSICAL_PRESENCE_DISABLE_ENDORSEMENT_ENABLE_STORAGE_HIERARCHY 34
+#define TCG2_PHYSICAL_PRESENCE_NO_ACTION_MAX 34
+
+//
+// TCG PP definition of physical presence operation actions for storage management
+//
+#define TCG2_PHYSICAL_PRESENCE_STORAGE_MANAGEMENT_BEGIN 96
+#define TCG2_PHYSICAL_PRESENCE_ENABLE_BLOCK_SID 96
+#define TCG2_PHYSICAL_PRESENCE_DISABLE_BLOCK_SID 97
+#define TCG2_PHYSICAL_PRESENCE_SET_PP_REQUIRED_FOR_ENABLE_BLOCK_SID_FUNC_TRUE 98
+#define TCG2_PHYSICAL_PRESENCE_SET_PP_REQUIRED_FOR_ENABLE_BLOCK_SID_FUNC_FALSE 99
+#define TCG2_PHYSICAL_PRESENCE_SET_PP_REQUIRED_FOR_DISABLE_BLOCK_SID_FUNC_TRUE 100
+#define TCG2_PHYSICAL_PRESENCE_SET_PP_REQUIRED_FOR_DISABLE_BLOCK_SID_FUNC_FALSE 101
+
+#define TCG2_PHYSICAL_PRESENCE_VENDOR_SPECIFIC_OPERATION 128
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/TcgStorageCore.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/TcgStorageCore.h
new file mode 100644
index 0000000000..9253049c47
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/TcgStorageCore.h
@@ -0,0 +1,387 @@
+/** @file
+ TCG defined values and structures.
+
+ (TCG Storage Architecture Core Specification, Version 2.01, Revision 1.00,
+ https://trustedcomputinggroup.org/tcg-storage-architecture-core-specification/)
+
+ Check http://trustedcomputinggroup.org for latest specification updates.
+
+Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _TCG_STORAGE_CORE_H_
+#define _TCG_STORAGE_CORE_H_
+
+#include
+
+#pragma pack(1)
+
+/// UID in host native byte order
+typedef UINT64 TCG_UID;
+
+#define TCG_TO_UID(b0, b1, b2, b3, b4, b5, b6, b7) (TCG_UID)(\
+ (UINT64)(b0) | \
+ ((UINT64)(b1) << 8) | \
+ ((UINT64)(b2) << 16) | \
+ ((UINT64)(b3) << 24) | \
+ ((UINT64)(b4) << 32) | \
+ ((UINT64)(b5) << 40) | \
+ ((UINT64)(b6) << 48) | \
+ ((UINT64)(b7) << 56))
+
+typedef struct {
+ UINT32 ReservedBE;
+ UINT16 ComIDBE;
+ UINT16 ComIDExtensionBE;
+ UINT32 OutstandingDataBE;
+ UINT32 MinTransferBE;
+ UINT32 LengthBE;
+ UINT8 Payload[0];
+} TCG_COM_PACKET;
+
+typedef struct {
+ UINT32 TperSessionNumberBE;
+ UINT32 HostSessionNumberBE;
+ UINT32 SequenceNumberBE;
+ UINT16 ReservedBE;
+ UINT16 AckTypeBE;
+ UINT32 AcknowledgementBE;
+ UINT32 LengthBE;
+ UINT8 Payload[0];
+} TCG_PACKET;
+
+#define TCG_SUBPACKET_ALIGNMENT 4// 4-byte alignment per spec
+
+typedef struct {
+ UINT8 ReservedBE[6];
+ UINT16 KindBE;
+ UINT32 LengthBE;
+ UINT8 Payload[0];
+} TCG_SUB_PACKET;
+
+#define SUBPACKET_KIND_DATA 0x0000
+#define SUBPACKET_KIND_CREDIT_CONTROL 0x8001
+
+#define TCG_ATOM_TYPE_INTEGER 0x0
+#define TCG_ATOM_TYPE_BYTE 0x1
+typedef struct {
+ UINT8 Data : 6;
+ UINT8 Sign : 1;
+ UINT8 IsZero : 1;
+} TCG_TINY_ATOM_BITS;
+
+typedef union {
+ UINT8 Raw;
+ TCG_TINY_ATOM_BITS TinyAtomBits;
+} TCG_SIMPLE_TOKEN_TINY_ATOM;
+
+typedef struct {
+ UINT8 Length : 4;
+ UINT8 SignOrCont : 1;
+ UINT8 ByteOrInt : 1;
+ UINT8 IsZero : 1;
+ UINT8 IsOne : 1;
+} TCG_SHORT_ATOM_BITS;
+
+typedef union {
+ UINT8 RawHeader;
+ TCG_SHORT_ATOM_BITS ShortAtomBits;
+} TCG_SIMPLE_TOKEN_SHORT_ATOM;
+
+#define TCG_MEDIUM_ATOM_LENGTH_HIGH_SHIFT 0x8
+#define TCG_MEDIUM_ATOM_LENGTH_HIGH_MASK 0x7
+
+typedef struct {
+ UINT8 LengthHigh : 3;
+ UINT8 SignOrCont : 1;
+ UINT8 ByteOrInt : 1;
+ UINT8 IsZero : 1;
+ UINT8 IsOne1 : 1;
+ UINT8 IsOne2 : 1;
+ UINT8 LengthLow;
+} TCG_MEDIUM_ATOM_BITS;
+
+typedef union {
+ UINT16 RawHeader;
+ TCG_MEDIUM_ATOM_BITS MediumAtomBits;
+} TCG_SIMPLE_TOKEN_MEDIUM_ATOM;
+
+#define TCG_LONG_ATOM_LENGTH_HIGH_SHIFT 16
+#define TCG_LONG_ATOM_LENGTH_MID_SHIFT 8
+
+typedef struct {
+ UINT8 SignOrCont : 1;
+ UINT8 ByteOrInt : 1;
+ UINT8 Reserved : 2;
+ UINT8 IsZero : 1;
+ UINT8 IsOne1 : 1;
+ UINT8 IsOne2 : 1;
+ UINT8 IsOne3 : 1;
+ UINT8 LengthHigh;
+ UINT8 LengthMid;
+ UINT8 LengthLow;
+} TCG_LONG_ATOM_BITS;
+
+typedef union {
+ UINT32 RawHeader;
+ TCG_LONG_ATOM_BITS LongAtomBits;
+} TCG_SIMPLE_TOKEN_LONG_ATOM;
+
+// TCG Core Spec v2 - Table 04 - Token Types
+typedef enum {
+ TcgTokenTypeReserved,
+ TcgTokenTypeTinyAtom,
+ TcgTokenTypeShortAtom,
+ TcgTokenTypeMediumAtom,
+ TcgTokenTypeLongAtom,
+ TcgTokenTypeStartList,
+ TcgTokenTypeEndList,
+ TcgTokenTypeStartName,
+ TcgTokenTypeEndName,
+ TcgTokenTypeCall,
+ TcgTokenTypeEndOfData,
+ TcgTokenTypeEndOfSession,
+ TcgTokenTypeStartTransaction,
+ TcgTokenTypeEndTransaction,
+ TcgTokenTypeEmptyAtom,
+} TCG_TOKEN_TYPE;
+
+#pragma pack()
+
+#define TCG_TOKEN_SHORTATOM_MAX_BYTE_SIZE 0x0F
+#define TCG_TOKEN_MEDIUMATOM_MAX_BYTE_SIZE 0x7FF
+#define TCG_TOKEN_LONGATOM_MAX_BYTE_SIZE 0xFFFFFF
+
+#define TCG_TOKEN_TINYATOM_UNSIGNED_MAX_VALUE 0x3F
+#define TCG_TOKEN_TINYATOM_SIGNED_MAX_VALUE 0x1F
+#define TCG_TOKEN_TINYATOM_SIGNED_MIN_VALUE -32
+
+// TOKEN TYPES
+#define TCG_TOKEN_TINYATOM 0x00
+#define TCG_TOKEN_TINYSIGNEDATOM 0x40
+#define TCG_TOKEN_SHORTATOM 0x80
+#define TCG_TOKEN_SHORTSIGNEDATOM 0x90
+#define TCG_TOKEN_SHORTBYTESATOM 0xA0
+#define TCG_TOKEN_MEDIUMATOM 0xC0
+#define TCG_TOKEN_MEDIUMSIGNEDATOM 0xC8
+#define TCG_TOKEN_MEDIUMBYTESATOM 0xD0
+#define TCG_TOKEN_LONGATOM 0xE0
+#define TCG_TOKEN_LONGSIGNEDATOM 0xE1
+#define TCG_TOKEN_LONGBYTESATOM 0xE2
+#define TCG_TOKEN_STARTLIST 0xF0
+#define TCG_TOKEN_ENDLIST 0xF1
+#define TCG_TOKEN_STARTNAME 0xF2
+#define TCG_TOKEN_ENDNAME 0xF3
+// 0xF4 - 0xF7 TCG Reserved
+#define TCG_TOKEN_CALL 0xF8
+#define TCG_TOKEN_ENDDATA 0xF9
+#define TCG_TOKEN_ENDSESSION 0xFA
+#define TCG_TOKEN_STARTTRANSACTION 0xFB
+#define TCG_TOKEN_ENDTRANSACTION 0xFC
+// 0xFD - 0xFE TCG Reserved
+#define TCG_TOKEN_EMPTY 0xFF
+
+// CELLBLOCK reserved Names
+#define TCG_CELL_BLOCK_TABLE_NAME (UINT8)0x00
+#define TCG_CELL_BLOCK_START_ROW_NAME (UINT8)0x01
+#define TCG_CELL_BLOCK_END_ROW_NAME (UINT8)0x02
+#define TCG_CELL_BLOCK_START_COLUMN_NAME (UINT8)0x03
+#define TCG_CELL_BLOCK_END_COLUMN_NAME (UINT8)0x04
+
+// METHOD STATUS CODES
+#define TCG_METHOD_STATUS_CODE_SUCCESS 0x00
+#define TCG_METHOD_STATUS_CODE_NOT_AUTHORIZED 0x01
+#define TCG_METHOD_STATUS_CODE_OBSOLETE 0x02
+#define TCG_METHOD_STATUS_CODE_SP_BUSY 0x03
+#define TCG_METHOD_STATUS_CODE_SP_FAILED 0x04
+#define TCG_METHOD_STATUS_CODE_SP_DISABLED 0x05
+#define TCG_METHOD_STATUS_CODE_SP_FROZEN 0x06
+#define TCG_METHOD_STATUS_CODE_NO_SESSIONS_AVAILABLE 0x07
+#define TCG_METHOD_STATUS_CODE_UNIQUENESS_CONFLICT 0x08
+#define TCG_METHOD_STATUS_CODE_INSUFFICIENT_SPACE 0x09
+#define TCG_METHOD_STATUS_CODE_INSUFFICIENT_ROWS 0x0A
+#define TCG_METHOD_STATUS_CODE_INVALID_PARAMETER 0x0C
+#define TCG_METHOD_STATUS_CODE_OBSOLETE2 0x0D
+#define TCG_METHOD_STATUS_CODE_OBSOLETE3 0x0E
+#define TCG_METHOD_STATUS_CODE_TPER_MALFUNCTION 0x0F
+#define TCG_METHOD_STATUS_CODE_TRANSACTION_FAILURE 0x10
+#define TCG_METHOD_STATUS_CODE_RESPONSE_OVERFLOW 0x11
+#define TCG_METHOD_STATUS_CODE_AUTHORITY_LOCKED_OUT 0x12
+#define TCG_METHOD_STATUS_CODE_FAIL 0x3F
+
+// Feature Codes
+#define TCG_FEATURE_INVALID (UINT16)0x0000
+#define TCG_FEATURE_TPER (UINT16)0x0001
+#define TCG_FEATURE_LOCKING (UINT16)0x0002
+#define TCG_FEATURE_GEOMETRY_REPORTING (UINT16)0x0003
+#define TCG_FEATURE_SINGLE_USER_MODE (UINT16)0x0201
+#define TCG_FEATURE_DATASTORE_TABLE (UINT16)0x0202
+#define TCG_FEATURE_OPAL_SSC_V1_0_0 (UINT16)0x0200
+#define TCG_FEATURE_OPAL_SSC_V2_0_0 (UINT16)0x0203
+#define TCG_FEATURE_OPAL_SSC_LITE (UINT16)0x0301
+#define TCG_FEATURE_PYRITE_SSC (UINT16)0x0302
+#define TCG_FEATURE_PYRITE_SSC_V2_0_0 (UINT16)0x0303
+#define TCG_FEATURE_BLOCK_SID (UINT16)0x0402
+#define TCG_FEATURE_DATA_REMOVAL (UINT16)0x0404
+
+// ACE Expression values
+#define TCG_ACE_EXPRESSION_AND 0x0
+#define TCG_ACE_EXPRESSION_OR 0x1
+
+/****************************************************************************
+TRUSTED RECEIVE - supported security protocols list (SP_Specific = 0000h)
+ATA 8 Rev6a Table 68 7.57.6.2
+****************************************************************************/
+// Security Protocol IDs
+#define TCG_SECURITY_PROTOCOL_INFO 0x00
+#define TCG_OPAL_SECURITY_PROTOCOL_1 0x01
+#define TCG_OPAL_SECURITY_PROTOCOL_2 0x02
+#define TCG_SECURITY_PROTOCOL_TCG3 0x03
+#define TCG_SECURITY_PROTOCOL_TCG4 0x04
+#define TCG_SECURITY_PROTOCOL_TCG5 0x05
+#define TCG_SECURITY_PROTOCOL_TCG6 0x06
+#define TCG_SECURITY_PROTOCOL_CBCS 0x07
+#define TCG_SECURITY_PROTOCOL_TAPE_DATA 0x20
+#define TCG_SECURITY_PROTOCOL_DATA_ENCRYPT_CONFIG 0x21
+#define TCG_SECURITY_PROTOCOL_SA_CREATION_CAPS 0x40
+#define TCG_SECURITY_PROTOCOL_IKEV2_SCSI 0x41
+#define TCG_SECURITY_PROTOCOL_JEDEC_UFS 0xEC
+#define TCG_SECURITY_PROTOCOL_SDCARD_SECURITY 0xED
+#define TCG_SECURITY_PROTOCOL_IEEE_1667 0xEE
+#define TCG_SECURITY_PROTOCOL_ATA_DEVICE_SERVER_PASS 0xEF
+
+// Security Protocol Specific IDs
+#define TCG_SP_SPECIFIC_PROTOCOL_LIST 0x0000
+#define TCG_SP_SPECIFIC_PROTOCOL_LEVEL0_DISCOVERY 0x0001
+
+#define TCG_RESERVED_COMID 0x0000
+
+// Defined in TCG Storage Feature Set:Block SID Authentication spec,
+// ComId used for BlockSid command is hardcode 0x0005.
+#define TCG_BLOCKSID_COMID 0x0005
+
+#pragma pack(1)
+typedef struct {
+ UINT8 Reserved[6];
+ UINT16 ListLength_BE; // 6 - 7
+ UINT8 List[504]; // 8...
+} TCG_SUPPORTED_SECURITY_PROTOCOLS;
+
+// Level 0 Discovery
+typedef struct {
+ UINT32 LengthBE; // number of valid bytes in discovery response, not including length field
+ UINT16 VerMajorBE;
+ UINT16 VerMinorBE;
+ UINT8 Reserved[8];
+ UINT8 VendorUnique[32];
+} TCG_LEVEL0_DISCOVERY_HEADER;
+
+typedef struct _TCG_LEVEL0_FEATURE_DESCRIPTOR_HEADER {
+ UINT16 FeatureCode_BE;
+ UINT8 Reserved : 4;
+ UINT8 Version : 4;
+ UINT8 Length; // length of feature dependent data in bytes
+} TCG_LEVEL0_FEATURE_DESCRIPTOR_HEADER;
+
+typedef struct {
+ TCG_LEVEL0_FEATURE_DESCRIPTOR_HEADER Header;
+ UINT8 LockingSupported : 1;
+ UINT8 LockingEnabled : 1; // means the locking security provider (SP) is enabled
+ UINT8 Locked : 1; // means at least 1 locking range is enabled
+ UINT8 MediaEncryption : 1;
+ UINT8 MbrEnabled : 1;
+ UINT8 MbrDone : 1;
+ UINT8 Reserved : 2;
+ UINT8 Reserved515[11];
+} TCG_LOCKING_FEATURE_DESCRIPTOR;
+
+typedef struct {
+ TCG_LEVEL0_FEATURE_DESCRIPTOR_HEADER Header;
+ UINT8 SIDValueState : 1;
+ UINT8 SIDBlockedState : 1;
+ UINT8 Reserved4 : 6;
+ UINT8 HardwareReset : 1;
+ UINT8 Reserved5 : 7;
+ UINT8 Reserved615[10];
+} TCG_BLOCK_SID_FEATURE_DESCRIPTOR;
+
+typedef struct {
+ TCG_LEVEL0_FEATURE_DESCRIPTOR_HEADER Header;
+ UINT8 SyncSupported : 1;
+ UINT8 AsyncSupported : 1;
+ UINT8 AckNakSupported : 1;
+ UINT8 BufferMgmtSupported : 1;
+ UINT8 StreamingSupported : 1;
+ UINT8 Reserved4b5 : 1;
+ UINT8 ComIdMgmtSupported : 1;
+ UINT8 Reserved4b7 : 1;
+ UINT8 Reserved515[11];
+} TCG_TPER_FEATURE_DESCRIPTOR;
+
+#pragma pack()
+
+// Special Purpose UIDs
+#define TCG_UID_NULL TCG_TO_UID(0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00)
+#define TCG_UID_THIS_SP TCG_TO_UID(0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01)
+#define TCG_UID_SMUID TCG_TO_UID(0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF)
+
+// Session Manager Method UIDS
+#define TCG_UID_SM_PROPERTIES TCG_TO_UID(0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x01)
+#define TCG_UID_SM_START_SESSION TCG_TO_UID(0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x02)
+#define TCG_UID_SM_SYNC_SESSION TCG_TO_UID(0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x03)
+#define TCG_UID_SM_START_TRUSTED_SESSION TCG_TO_UID(0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x04)
+#define TCG_UID_SM_SYNC_TRUSTED_SESSION TCG_TO_UID(0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x05)
+#define TCG_UID_SM_CLOSE_SESSION TCG_TO_UID(0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x06)
+
+// MethodID UIDs
+#define TCG_UID_METHOD_DELETE_SP TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x01)
+#define TCG_UID_METHOD_CREATE_TABLE TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x02)
+#define TCG_UID_METHOD_DELETE TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x03)
+#define TCG_UID_METHOD_CREATE_ROW TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x04)
+#define TCG_UID_METHOD_DELETE_ROW TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x05)
+#define TCG_UID_METHOD_NEXT TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x08)
+#define TCG_UID_METHOD_GET_FREE_SPACE TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x09)
+#define TCG_UID_METHOD_GET_FREE_ROWS TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x0A)
+#define TCG_UID_METHOD_DELETE_METHOD TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x0B)
+#define TCG_UID_METHOD_GET_ACL TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x0D)
+#define TCG_UID_METHOD_ADD_ACE TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x0E)
+#define TCG_UID_METHOD_REMOVE_ACE TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x0F)
+#define TCG_UID_METHOD_GEN_KEY TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x10)
+#define TCG_UID_METHOD_GET_PACKAGE TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x12)
+#define TCG_UID_METHOD_SET_PACKAGE TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x13)
+#define TCG_UID_METHOD_GET TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x16)
+#define TCG_UID_METHOD_SET TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x17)
+#define TCG_UID_METHOD_AUTHENTICATE TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x1C)
+#define TCG_UID_METHOD_ISSUE_SP TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x02, 0x01)
+#define TCG_UID_METHOD_GET_CLOCK TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x04, 0x01)
+#define TCG_UID_METHOD_RESET_CLOCK TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x04, 0x02)
+#define TCG_UID_METHOD_SET_CLOCK_HIGH TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x04, 0x03)
+#define TCG_UID_METHOD_SET_LAG_HIGH TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x04, 0x04)
+#define TCG_UID_METHOD_SET_CLOCK_LOW TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x04, 0x05)
+#define TCG_UID_METHOD_SET_LAG_LOW TCG_TO_UID(0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x06)
+#define TCG_UID_METHOD_INCREMENT_COUNTER TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x04, 0x07)
+#define TCG_UID_METHOD_RANDOM TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x06, 0x01)
+#define TCG_UID_METHOD_SALT TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x06, 0x02)
+#define TCG_UID_METHOD_DECRYPT_INIT TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x06, 0x03)
+#define TCG_UID_METHOD_DECRYPT TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x06, 0x04)
+#define TCG_UID_METHOD_DECRYPT_FINALIZE TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x06, 0x05)
+#define TCG_UID_METHOD_ENCRYPT_INIT TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x06, 0x06)
+#define TCG_UID_METHOD_ENCRYPT TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x06, 0x07)
+#define TCG_UID_METHOD_ENCRYPT_FINALIZE TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x06, 0x08)
+#define TCG_UID_METHOD_HMAC_INIT TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x06, 0x09)
+#define TCG_UID_METHOD_HMAC TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x06, 0x0A)
+#define TCG_UID_METHOD_HMAC_FINALIZE TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x06, 0x0B)
+#define TCG_UID_METHOD_HASH_INIT TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x06, 0x0C)
+#define TCG_UID_METHOD_HASH TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x06, 0x0D)
+#define TCG_UID_METHOD_HASH_FINALIZE TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x06, 0x0E)
+#define TCG_UID_METHOD_SIGN TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x06, 0x0F)
+#define TCG_UID_METHOD_VERIFY TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x06, 0x10)
+#define TCG_UID_METHOD_XOR TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x06, 0x11)
+#define TCG_UID_METHOD_ADD_LOG TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x0A, 0x01)
+#define TCG_UID_METHOD_CREATE_LOG TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x0A, 0x02)
+#define TCG_UID_METHOD_CLEAR_LOG TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x0A, 0x03)
+#define TCG_UID_METHOD_FLUSH_LOG TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x0A, 0x04)
+
+#endif // TCG_H_
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/TcgStorageOpal.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/TcgStorageOpal.h
new file mode 100644
index 0000000000..0a145b1933
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/TcgStorageOpal.h
@@ -0,0 +1,241 @@
+/** @file
+ Opal Specification defined values and structures.
+
+ (TCG Storage Architecture Core Specification, Version 2.01, Revision 1.00,
+ https://trustedcomputinggroup.org/tcg-storage-architecture-core-specification/
+
+ Storage Work Group Storage Security Subsystem Class: Pyrite, Version 1.00 Final, Revision 1.00,
+ https://trustedcomputinggroup.org/tcg-storage-security-subsystem-class-pyrite/
+
+ Storage Work Group Storage Security Subsystem Class: Opal, Version 2.01 Final, Revision 1.00,
+ https://trustedcomputinggroup.org/storage-work-group-storage-security-subsystem-class-opal/
+
+ TCG Storage Security Subsystem Class: Opalite Version 1.00 Revision 1.00,
+ https://trustedcomputinggroup.org/tcg-storage-security-subsystem-class-opalite/)
+
+ Check http://trustedcomputinggroup.org for latest specification updates.
+
+Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _TCG_STORAGE_OPAL_H_
+#define _TCG_STORAGE_OPAL_H_
+
+#include
+
+#define OPAL_UID_ADMIN_SP TCG_TO_UID(0x00, 0x00, 0x02, 0x05, 0x00, 0x00, 0x00, 0x01)
+#define OPAL_UID_ADMIN_SP_C_PIN_MSID TCG_TO_UID(0x00, 0x00, 0x00, 0x0B, 0x00, 0x00, 0x84, 0x02)
+#define OPAL_UID_ADMIN_SP_C_PIN_SID TCG_TO_UID(0x00, 0x00, 0x00, 0x0B, 0x00, 0x00, 0x00, 0x01)
+#define OPAL_UID_LOCKING_SP TCG_TO_UID(0x00, 0x00, 0x02, 0x05, 0x00, 0x00, 0x00, 0x02)
+
+// ADMIN_SP
+// Authorities
+#define OPAL_ADMIN_SP_ANYBODY_AUTHORITY TCG_TO_UID(0x00, 0x00, 0x00, 0x09, 0x00, 0x00, 0x00, 0x01)
+#define OPAL_ADMIN_SP_ADMINS_AUTHORITY TCG_TO_UID(0x00, 0x00, 0x00, 0x09, 0x00, 0x00, 0x00, 0x02)
+#define OPAL_ADMIN_SP_MAKERS_AUTHORITY TCG_TO_UID(0x00, 0x00, 0x00, 0x09, 0x00, 0x00, 0x00, 0x03)
+#define OPAL_ADMIN_SP_SID_AUTHORITY TCG_TO_UID(0x00, 0x00, 0x00, 0x09, 0x00, 0x00, 0x00, 0x06)
+#define OPAL_ADMIN_SP_ADMIN1_AUTHORITY TCG_TO_UID(0x00, 0x00, 0x00, 0x09, 0x00, 0x00, 0x02, 0x01)
+#define OPAL_ADMIN_SP_PSID_AUTHORITY TCG_TO_UID(0x00, 0x00, 0x00, 0x09, 0x00, 0x01, 0xFF, 0x01)
+
+#define OPAL_ADMIN_SP_ACTIVATE_METHOD TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x02, 0x03)
+#define OPAL_ADMIN_SP_REVERT_METHOD TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x02, 0x02)
+
+// ADMIN_SP
+// Data Removal mechanism
+#define OPAL_UID_ADMIN_SP_DATA_REMOVAL_MECHANISM TCG_TO_UID(0x00, 0x00, 0x11, 0x01, 0x00, 0x00, 0x00, 0x01)
+
+// LOCKING SP
+// Authorities
+#define OPAL_LOCKING_SP_ANYBODY_AUTHORITY TCG_TO_UID(0x00, 0x00, 0x00, 0x09, 0x00, 0x00, 0x00, 0x01)
+#define OPAL_LOCKING_SP_ADMINS_AUTHORITY TCG_TO_UID(0x00, 0x00, 0x00, 0x09, 0x00, 0x00, 0x00, 0x02)
+#define OPAL_LOCKING_SP_ADMIN1_AUTHORITY TCG_TO_UID(0x00, 0x00, 0x00, 0x09, 0x00, 0x01, 0x00, 0x01)
+#define OPAL_LOCKING_SP_USERS_AUTHORITY TCG_TO_UID(0x00, 0x00, 0x00, 0x09, 0x00, 0x03, 0x00, 0x00)
+#define OPAL_LOCKING_SP_USER1_AUTHORITY TCG_TO_UID(0x00, 0x00, 0x00, 0x09, 0x00, 0x03, 0x00, 0x01)
+
+#define OPAL_LOCKING_SP_REVERTSP_METHOD TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x11)
+
+// C_PIN Table Rows
+#define OPAL_LOCKING_SP_C_PIN_ADMIN1 TCG_TO_UID( 0x00, 0x00, 0x00, 0x0B, 0x00, 0x01, 0x00, 0x01 )
+#define OPAL_LOCKING_SP_C_PIN_USER1 TCG_TO_UID( 0x00, 0x00, 0x00, 0x0B, 0x00, 0x03, 0x00, 0x01 )
+
+// Locking Table
+#define OPAL_LOCKING_SP_LOCKING_GLOBALRANGE TCG_TO_UID( 0x00, 0x00, 0x08, 0x02, 0x00, 0x00, 0x00, 0x01 )
+#define OPAL_LOCKING_SP_LOCKING_RANGE1 TCG_TO_UID( 0x00, 0x00, 0x08, 0x02, 0x00, 0x03, 0x00, 0x01 )
+
+// LOCKING SP ACE Table Preconfiguration
+#define OPAL_LOCKING_SP_ACE_LOCKING_GLOBALRANGE_GET_ALL TCG_TO_UID( 0x00, 0x00, 0x00, 0x08, 0x00, 0x03, 0xD0, 0x00 )
+#define OPAL_LOCKING_SP_ACE_LOCKING_GLOBALRANGE_SET_RDLOCKED TCG_TO_UID( 0x00, 0x00, 0x00, 0x08, 0x00, 0x03, 0xE0, 0x00 )
+#define OPAL_LOCKING_SP_ACE_LOCKING_GLOBALRANGE_SET_WRLOCKED TCG_TO_UID( 0x00, 0x00, 0x00, 0x08, 0x00, 0x03, 0xE8, 0x00 )
+
+#define OPAL_LOCKING_SP_ACE_K_AES_256_GLOBALRANGE_GENKEY TCG_TO_UID( 0x00, 0x00, 0x00, 0x08, 0x00, 0x03, 0xB8, 0x00 )
+#define OPAL_LOCKING_SP_ACE_K_AES_128_GLOBALRANGE_GENKEY TCG_TO_UID( 0x00, 0x00, 0x00, 0x08, 0x00, 0x03, 0xB0, 0x00 )
+
+// LOCKING SP LockingInfo Table Preconfiguration
+#define OPAL_LOCKING_SP_LOCKING_INFO TCG_TO_UID( 0x00, 0x00, 0x08, 0x01, 0x00, 0x00, 0x00, 0x01 )
+
+#define OPAL_LOCKING_SP_LOCKINGINFO_ALIGNMENTREQUIRED_COL 0x7
+#define OPAL_LOCKING_SP_LOCKINGINFO_LOGICALBLOCKSIZE_COL 0x8
+#define OPAL_LOCKING_SP_LOCKINGINFO_ALIGNMENTGRANULARITY_COL 0x9
+#define OPAL_LOCKING_SP_LOCKINGINFO_LOWESTALIGNEDLBA_COL 0xA
+
+// K_AES_256 Table Preconfiguration
+#define OPAL_LOCKING_SP_K_AES_256_GLOBALRANGE_KEY TCG_TO_UID( 0x00, 0x00, 0x08, 0x06, 0x00, 0x00, 0x00, 0x01 )
+
+// K_AES_128 Table Preconfiguration
+#define OPAL_LOCKING_SP_K_AES_128_GLOBALRANGE_KEY TCG_TO_UID( 0x00, 0x00, 0x08, 0x05, 0x00, 0x00, 0x00, 0x01 )
+
+// Minimum Properties that an Opal Compliant SD Shall support
+#define OPAL_MIN_MAX_COM_PACKET_SIZE 2048
+#define OPAL_MIN_MAX_REPONSE_COM_PACKET_SIZE 2048
+#define OPAL_MIN_MAX_PACKET_SIZE 2028
+#define OPAL_MIN_MAX_IND_TOKEN_SIZE 1992
+#define OPAL_MIN_MAX_PACKETS 1
+#define OPAL_MIN_MAX_SUBPACKETS 1
+#define OPAL_MIN_MAX_METHODS 1
+#define OPAL_MIN_MAX_SESSIONS 1
+#define OPAL_MIN_MAX_AUTHENTICATIONS 2
+#define OPAL_MIN_MAX_TRANSACTION_LIMIT 1
+
+#define OPAL_ADMIN_SP_PIN_COL 3
+#define OPAL_LOCKING_SP_C_PIN_TRYLIMIT_COL 5
+#define OPAL_RANDOM_METHOD_MAX_COUNT_SIZE 32
+
+// Data Removal Mechanism column.
+#define OPAL_ADMIN_SP_ACTIVE_DATA_REMOVAL_MECHANISM_COL 1
+
+//
+// Supported Data Removal Mechanism.
+// Detail see Pyrite SSC v2 spec.
+//
+typedef enum {
+ OverwriteDataErase = 0,
+ BlockErase,
+ CryptoErase,
+ Unmap,
+ ResetWritePointers,
+ VendorSpecificErase,
+ ResearvedMechanism
+} SUPPORTED_DATA_REMOVAL_MECHANISM;
+
+#pragma pack(1)
+
+typedef struct _OPAL_GEOMETRY_REPORTING_FEATURE {
+ TCG_LEVEL0_FEATURE_DESCRIPTOR_HEADER Header;
+ UINT8 Reserved[8];
+ UINT32 LogicalBlockSizeBE;
+ UINT64 AlignmentGranularityBE;
+ UINT64 LowestAlignedLBABE;
+} OPAL_GEOMETRY_REPORTING_FEATURE;
+
+typedef struct _OPAL_SINGLE_USER_MODE_FEATURE {
+ TCG_LEVEL0_FEATURE_DESCRIPTOR_HEADER Header;
+ UINT32 NumLockingObjectsSupportedBE;
+ UINT8 Any : 1;
+ UINT8 All : 1;
+ UINT8 Policy : 1;
+ UINT8 Reserved : 5;
+ UINT8 Reserved2[7];
+} OPAL_SINGLE_USER_MODE_FEATURE;
+
+typedef struct _OPAL_DATASTORE_TABLE_FEATURE {
+ TCG_LEVEL0_FEATURE_DESCRIPTOR_HEADER Header;
+ UINT16 Reserved;
+ UINT16 MaxNumTablesBE;
+ UINT32 MaxTotalSizeBE;
+ UINT32 SizeAlignmentBE;
+} OPAL_DATASTORE_TABLE_FEATURE;
+
+typedef struct _OPAL_SSCV1_FEATURE_DESCRIPTOR {
+ TCG_LEVEL0_FEATURE_DESCRIPTOR_HEADER Header;
+ UINT16 BaseComdIdBE;
+ UINT16 NumComIdsBE;
+ UINT8 RangeCrossing : 1;
+ UINT8 Reserved : 7;
+ UINT8 Future[11];
+} OPAL_SSCV1_FEATURE_DESCRIPTOR;
+
+typedef struct _OPAL_SSCV2_FEATURE_DESCRIPTOR {
+ TCG_LEVEL0_FEATURE_DESCRIPTOR_HEADER Header;
+ UINT16 BaseComdIdBE;
+ UINT16 NumComIdsBE;
+ UINT8 Reserved;
+ UINT16 NumLockingSpAdminAuthoritiesSupportedBE;
+ UINT16 NumLockingSpUserAuthoritiesSupportedBE;
+ UINT8 InitialCPINSIDPIN;
+ UINT8 CPINSIDPINRevertBehavior;
+ UINT8 Future[5];
+} OPAL_SSCV2_FEATURE_DESCRIPTOR;
+
+typedef struct _OPAL_SSCLITE_FEATURE_DESCRIPTOR {
+ TCG_LEVEL0_FEATURE_DESCRIPTOR_HEADER Header;
+ UINT16 BaseComdIdBE;
+ UINT16 NumComIdsBE;
+ UINT8 Reserved[5];
+ UINT8 InitialCPINSIDPIN;
+ UINT8 CPINSIDPINRevertBehavior;
+ UINT8 Future[5];
+} OPAL_SSCLITE_FEATURE_DESCRIPTOR;
+
+typedef struct _PYRITE_SSC_FEATURE_DESCRIPTOR {
+ TCG_LEVEL0_FEATURE_DESCRIPTOR_HEADER Header;
+ UINT16 BaseComdIdBE;
+ UINT16 NumComIdsBE;
+ UINT8 Reserved[5];
+ UINT8 InitialCPINSIDPIN;
+ UINT8 CPINSIDPINRevertBehavior;
+ UINT8 Future[5];
+} PYRITE_SSC_FEATURE_DESCRIPTOR;
+
+typedef struct _PYRITE_SSCV2_FEATURE_DESCRIPTOR {
+ TCG_LEVEL0_FEATURE_DESCRIPTOR_HEADER Header;
+ UINT16 BaseComdIdBE;
+ UINT16 NumComIdsBE;
+ UINT8 Reserved[5];
+ UINT8 InitialCPINSIDPIN;
+ UINT8 CPINSIDPINRevertBehavior;
+ UINT8 Future[5];
+} PYRITE_SSCV2_FEATURE_DESCRIPTOR;
+
+typedef struct _DATA_REMOVAL_FEATURE_DESCRIPTOR {
+ TCG_LEVEL0_FEATURE_DESCRIPTOR_HEADER Header;
+ UINT8 Reserved;
+ UINT8 OperationProcessing : 1;
+ UINT8 Reserved2 : 7;
+ UINT8 RemovalMechanism;
+ UINT8 FormatBit0 : 1; // Data Removal Time Format for Bit 0
+ UINT8 FormatBit1 : 1; // Data Removal Time Format for Bit 1
+ UINT8 FormatBit2 : 1; // Data Removal Time Format for Bit 2
+ UINT8 FormatBit3 : 1; // Data Removal Time Format for Bit 3
+ UINT8 FormatBit4 : 1; // Data Removal Time Format for Bit 4
+ UINT8 FormatBit5 : 1; // Data Removal Time Format for Bit 5
+ UINT8 Reserved3 : 2;
+ UINT16 TimeBit0; // Data Removal Time for Supported Data Removal Mechanism Bit 0
+ UINT16 TimeBit1; // Data Removal Time for Supported Data Removal Mechanism Bit 1
+ UINT16 TimeBit2; // Data Removal Time for Supported Data Removal Mechanism Bit 2
+ UINT16 TimeBit3; // Data Removal Time for Supported Data Removal Mechanism Bit 3
+ UINT16 TimeBit4; // Data Removal Time for Supported Data Removal Mechanism Bit 4
+ UINT16 TimeBit5; // Data Removal Time for Supported Data Removal Mechanism Bit 5
+ UINT8 Future[16];
+} DATA_REMOVAL_FEATURE_DESCRIPTOR;
+
+typedef union {
+ TCG_LEVEL0_FEATURE_DESCRIPTOR_HEADER CommonHeader;
+ TCG_TPER_FEATURE_DESCRIPTOR Tper;
+ TCG_LOCKING_FEATURE_DESCRIPTOR Locking;
+ OPAL_GEOMETRY_REPORTING_FEATURE Geometry;
+ OPAL_SINGLE_USER_MODE_FEATURE SingleUser;
+ OPAL_DATASTORE_TABLE_FEATURE DataStore;
+ OPAL_SSCV1_FEATURE_DESCRIPTOR OpalSscV1;
+ OPAL_SSCV2_FEATURE_DESCRIPTOR OpalSscV2;
+ OPAL_SSCLITE_FEATURE_DESCRIPTOR OpalSscLite;
+ PYRITE_SSC_FEATURE_DESCRIPTOR PyriteSsc;
+ PYRITE_SSCV2_FEATURE_DESCRIPTOR PyriteSscV2;
+ TCG_BLOCK_SID_FEATURE_DESCRIPTOR BlockSid;
+ DATA_REMOVAL_FEATURE_DESCRIPTOR DataRemoval;
+} OPAL_LEVEL0_FEATURE_DESCRIPTOR;
+
+#pragma pack()
+
+#endif // _OPAL_H_
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/TcpaAcpi.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/TcpaAcpi.h
new file mode 100644
index 0000000000..ce4c8dd01e
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/TcpaAcpi.h
@@ -0,0 +1,52 @@
+/** @file
+ TCPA ACPI table definition.
+
+Copyright (c) 2013, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _TCPA_ACPI_H_
+#define _TCPA_ACPI_H_
+
+#include
+
+#pragma pack (1)
+
+typedef struct _EFI_TCG_CLIENT_ACPI_TABLE {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT16 PlatformClass;
+ UINT32 Laml;
+ UINT64 Lasa;
+} EFI_TCG_CLIENT_ACPI_TABLE;
+
+typedef struct _EFI_TCG_SERVER_ACPI_TABLE {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT16 PlatformClass;
+ UINT16 Reserved0;
+ UINT64 Laml;
+ UINT64 Lasa;
+ UINT16 SpecRev;
+ UINT8 DeviceFlags;
+ UINT8 InterruptFlags;
+ UINT8 Gpe;
+ UINT8 Reserved1[3];
+ UINT32 GlobalSysInt;
+ EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE BaseAddress;
+ UINT32 Reserved2;
+ EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE ConfigAddress;
+ UINT8 PciSegNum;
+ UINT8 PciBusNum;
+ UINT8 PciDevNum;
+ UINT8 PciFuncNum;
+} EFI_TCG_SERVER_ACPI_TABLE;
+
+//
+// TCG Platform Type based on TCG ACPI Specification Version 1.00
+//
+#define TCG_PLATFORM_TYPE_CLIENT 0
+#define TCG_PLATFORM_TYPE_SERVER 1
+
+#pragma pack ()
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/Tdx.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/Tdx.h
new file mode 100644
index 0000000000..3b5a1a4250
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/Tdx.h
@@ -0,0 +1,203 @@
+/** @file
+ Intel Trust Domain Extension definitions
+ Detailed information is in below document:
+ https://software.intel.com/content/dam/develop/external/us/en/documents
+ /tdx-module-1eas-v0.85.039.pdf
+
+ Copyright (c) 2020 - 2021, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef MDE_PKG_TDX_H_
+#define MDE_PKG_TDX_H_
+
+#define EXIT_REASON_EXTERNAL_INTERRUPT 1
+#define EXIT_REASON_TRIPLE_FAULT 2
+
+#define EXIT_REASON_PENDING_INTERRUPT 7
+#define EXIT_REASON_NMI_WINDOW 8
+#define EXIT_REASON_TASK_SWITCH 9
+#define EXIT_REASON_CPUID 10
+#define EXIT_REASON_HLT 12
+#define EXIT_REASON_INVD 13
+#define EXIT_REASON_INVLPG 14
+#define EXIT_REASON_RDPMC 15
+#define EXIT_REASON_RDTSC 16
+#define EXIT_REASON_VMCALL 18
+#define EXIT_REASON_VMCLEAR 19
+#define EXIT_REASON_VMLAUNCH 20
+#define EXIT_REASON_VMPTRLD 21
+#define EXIT_REASON_VMPTRST 22
+#define EXIT_REASON_VMREAD 23
+#define EXIT_REASON_VMRESUME 24
+#define EXIT_REASON_VMWRITE 25
+#define EXIT_REASON_VMOFF 26
+#define EXIT_REASON_VMON 27
+#define EXIT_REASON_CR_ACCESS 28
+#define EXIT_REASON_DR_ACCESS 29
+#define EXIT_REASON_IO_INSTRUCTION 30
+#define EXIT_REASON_MSR_READ 31
+#define EXIT_REASON_MSR_WRITE 32
+#define EXIT_REASON_INVALID_STATE 33
+#define EXIT_REASON_MSR_LOAD_FAIL 34
+#define EXIT_REASON_MWAIT_INSTRUCTION 36
+#define EXIT_REASON_MONITOR_TRAP_FLAG 37
+#define EXIT_REASON_MONITOR_INSTRUCTION 39
+#define EXIT_REASON_PAUSE_INSTRUCTION 40
+#define EXIT_REASON_MCE_DURING_VMENTRY 41
+#define EXIT_REASON_TPR_BELOW_THRESHOLD 43
+#define EXIT_REASON_APIC_ACCESS 44
+#define EXIT_REASON_EOI_INDUCED 45
+#define EXIT_REASON_GDTR_IDTR 46
+#define EXIT_REASON_LDTR_TR 47
+#define EXIT_REASON_EPT_VIOLATION 48
+#define EXIT_REASON_EPT_MISCONFIG 49
+#define EXIT_REASON_INVEPT 50
+#define EXIT_REASON_RDTSCP 51
+#define EXIT_REASON_PREEMPTION_TIMER 52
+#define EXIT_REASON_INVVPID 53
+#define EXIT_REASON_WBINVD 54
+#define EXIT_REASON_XSETBV 55
+#define EXIT_REASON_APIC_WRITE 56
+#define EXIT_REASON_RDRAND 57
+#define EXIT_REASON_INVPCID 58
+#define EXIT_REASON_VMFUNC 59
+#define EXIT_REASON_ENCLS 60
+#define EXIT_REASON_RDSEED 61
+#define EXIT_REASON_PML_FULL 62
+#define EXIT_REASON_XSAVES 63
+#define EXIT_REASON_XRSTORS 64
+
+// TDCALL API Function Completion Status Codes
+#define TDX_EXIT_REASON_SUCCESS 0x0000000000000000
+#define TDX_EXIT_REASON_PAGE_ALREADY_ACCEPTED 0x00000B0A00000000
+#define TDX_EXIT_REASON_PAGE_SIZE_MISMATCH 0xC0000B0B00000000
+#define TDX_EXIT_REASON_OPERAND_INVALID 0xC000010000000000
+#define TDX_EXIT_REASON_OPERAND_BUSY 0x8000020000000000
+
+// TDCALL [TDG.MEM.PAGE.ACCEPT] page size
+#define TDCALL_ACCEPT_PAGE_SIZE_4K 0
+#define TDCALL_ACCEPT_PAGE_SIZE_2M 1
+#define TDCALL_ACCEPT_PAGE_SIZE_1G 2
+
+#define TDCALL_TDVMCALL 0
+#define TDCALL_TDINFO 1
+#define TDCALL_TDEXTENDRTMR 2
+#define TDCALL_TDGETVEINFO 3
+#define TDCALL_TDREPORT 4
+#define TDCALL_TDSETCPUIDVE 5
+#define TDCALL_TDACCEPTPAGE 6
+
+#define TDVMCALL_CPUID 0x0000a
+#define TDVMCALL_HALT 0x0000c
+#define TDVMCALL_IO 0x0001e
+#define TDVMCALL_RDMSR 0x0001f
+#define TDVMCALL_WRMSR 0x00020
+#define TDVMCALL_MMIO 0x00030
+#define TDVMCALL_PCONFIG 0x00041
+
+#define TDVMCALL_GET_TDVMCALL_INFO 0x10000
+#define TDVMCALL_MAPGPA 0x10001
+#define TDVMCALL_GET_QUOTE 0x10002
+#define TDVMCALL_REPORT_FATAL_ERR 0x10003
+#define TDVMCALL_SETUP_EVENT_NOTIFY 0x10004
+
+#pragma pack(1)
+typedef struct {
+ UINT64 Data[6];
+} TDCALL_GENERIC_RETURN_DATA;
+
+typedef struct {
+ UINT64 Gpaw;
+ UINT64 Attributes;
+ UINT32 MaxVcpus;
+ UINT32 NumVcpus;
+ UINT64 Resv[3];
+} TDCALL_INFO_RETURN_DATA;
+
+typedef union {
+ UINT64 Val;
+ struct {
+ UINT32 Size : 3;
+ UINT32 Direction : 1;
+ UINT32 String : 1;
+ UINT32 Rep : 1;
+ UINT32 Encoding : 1;
+ UINT32 Resv : 9;
+ UINT32 Port : 16;
+ UINT32 Resv2;
+ } Io;
+} VMX_EXIT_QUALIFICATION;
+
+typedef struct {
+ UINT32 ExitReason;
+ UINT32 Resv;
+ VMX_EXIT_QUALIFICATION ExitQualification;
+ UINT64 GuestLA;
+ UINT64 GuestPA;
+ UINT32 ExitInstructionLength;
+ UINT32 ExitInstructionInfo;
+ UINT32 Resv1;
+} TDCALL_VEINFO_RETURN_DATA;
+
+typedef union {
+ TDCALL_GENERIC_RETURN_DATA Generic;
+ TDCALL_INFO_RETURN_DATA TdInfo;
+ TDCALL_VEINFO_RETURN_DATA VeInfo;
+} TD_RETURN_DATA;
+
+/* data structure used in TDREPORT_STRUCT */
+typedef struct {
+ UINT8 Type;
+ UINT8 Subtype;
+ UINT8 Version;
+ UINT8 Rsvd;
+} TD_REPORT_TYPE;
+
+typedef struct {
+ TD_REPORT_TYPE ReportType;
+ UINT8 Rsvd1[12];
+ UINT8 CpuSvn[16];
+ UINT8 TeeTcbInfoHash[48];
+ UINT8 TeeInfoHash[48];
+ UINT8 ReportData[64];
+ UINT8 Rsvd2[32];
+ UINT8 Mac[32];
+} REPORTMACSTRUCT;
+
+typedef struct {
+ UINT8 Seam[2];
+ UINT8 Rsvd[14];
+} TEE_TCB_SVN;
+
+typedef struct {
+ UINT8 Valid[8];
+ TEE_TCB_SVN TeeTcbSvn;
+ UINT8 Mrseam[48];
+ UINT8 Mrsignerseam[48];
+ UINT8 Attributes[8];
+ UINT8 Rsvd[111];
+} TEE_TCB_INFO;
+
+typedef struct {
+ UINT8 Attributes[8];
+ UINT8 Xfam[8];
+ UINT8 Mrtd[48];
+ UINT8 Mrconfigid[48];
+ UINT8 Mrowner[48];
+ UINT8 Mrownerconfig[48];
+ UINT8 Rtmrs[4][48];
+ UINT8 Rsvd[112];
+} TDINFO;
+
+typedef struct {
+ REPORTMACSTRUCT ReportMacStruct;
+ TEE_TCB_INFO TeeTcbInfo;
+ UINT8 Rsvd[17];
+ TDINFO Tdinfo;
+} TDREPORT_STRUCT;
+
+#pragma pack()
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/Tls1.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/Tls1.h
new file mode 100644
index 0000000000..8e5c6b6597
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/Tls1.h
@@ -0,0 +1,138 @@
+/** @file
+ Transport Layer Security -- TLS 1.0/1.1/1.2 Standard definitions, from RFC 2246/4346/5246
+
+ This file contains common TLS 1.0/1.1/1.2 definitions from RFC 2246/4346/5246
+
+ Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef __TLS_1_H__
+#define __TLS_1_H__
+
+#pragma pack(1)
+
+///
+/// TLS Cipher Suite, refers to A.5 of rfc-2246, rfc-4346, rfc-5246, rfc-5288 and rfc-5289.
+///
+#define TLS_RSA_WITH_NULL_MD5 {0x00, 0x01}
+#define TLS_RSA_WITH_NULL_SHA {0x00, 0x02}
+#define TLS_RSA_WITH_RC4_128_MD5 {0x00, 0x04}
+#define TLS_RSA_WITH_RC4_128_SHA {0x00, 0x05}
+#define TLS_RSA_WITH_IDEA_CBC_SHA {0x00, 0x07}
+#define TLS_RSA_WITH_DES_CBC_SHA {0x00, 0x09}
+#define TLS_RSA_WITH_3DES_EDE_CBC_SHA {0x00, 0x0A}
+#define TLS_DH_DSS_WITH_DES_CBC_SHA {0x00, 0x0C}
+#define TLS_DH_DSS_WITH_3DES_EDE_CBC_SHA {0x00, 0x0D}
+#define TLS_DH_RSA_WITH_DES_CBC_SHA {0x00, 0x0F}
+#define TLS_DH_RSA_WITH_3DES_EDE_CBC_SHA {0x00, 0x10}
+#define TLS_DHE_DSS_WITH_DES_CBC_SHA {0x00, 0x12}
+#define TLS_DHE_DSS_WITH_3DES_EDE_CBC_SHA {0x00, 0x13}
+#define TLS_DHE_RSA_WITH_DES_CBC_SHA {0x00, 0x15}
+#define TLS_DHE_RSA_WITH_3DES_EDE_CBC_SHA {0x00, 0x16}
+#define TLS_RSA_WITH_AES_128_CBC_SHA {0x00, 0x2F}
+#define TLS_DH_DSS_WITH_AES_128_CBC_SHA {0x00, 0x30}
+#define TLS_DH_RSA_WITH_AES_128_CBC_SHA {0x00, 0x31}
+#define TLS_DHE_DSS_WITH_AES_128_CBC_SHA {0x00, 0x32}
+#define TLS_DHE_RSA_WITH_AES_128_CBC_SHA {0x00, 0x33}
+#define TLS_RSA_WITH_AES_256_CBC_SHA {0x00, 0x35}
+#define TLS_DH_DSS_WITH_AES_256_CBC_SHA {0x00, 0x36}
+#define TLS_DH_RSA_WITH_AES_256_CBC_SHA {0x00, 0x37}
+#define TLS_DHE_DSS_WITH_AES_256_CBC_SHA {0x00, 0x38}
+#define TLS_DHE_RSA_WITH_AES_256_CBC_SHA {0x00, 0x39}
+#define TLS_RSA_WITH_NULL_SHA256 {0x00, 0x3B}
+#define TLS_RSA_WITH_AES_128_CBC_SHA256 {0x00, 0x3C}
+#define TLS_RSA_WITH_AES_256_CBC_SHA256 {0x00, 0x3D}
+#define TLS_DH_DSS_WITH_AES_128_CBC_SHA256 {0x00, 0x3E}
+#define TLS_DH_RSA_WITH_AES_128_CBC_SHA256 {0x00, 0x3F}
+#define TLS_DHE_DSS_WITH_AES_128_CBC_SHA256 {0x00, 0x40}
+#define TLS_DHE_RSA_WITH_AES_128_CBC_SHA256 {0x00, 0x67}
+#define TLS_DH_DSS_WITH_AES_256_CBC_SHA256 {0x00, 0x68}
+#define TLS_DH_RSA_WITH_AES_256_CBC_SHA256 {0x00, 0x69}
+#define TLS_DHE_DSS_WITH_AES_256_CBC_SHA256 {0x00, 0x6A}
+#define TLS_DHE_RSA_WITH_AES_256_CBC_SHA256 {0x00, 0x6B}
+#define TLS_DHE_RSA_WITH_AES_256_GCM_SHA384 {0x00, 0x9F}
+#define TLS_ECDHE_ECDSA_WITH_AES_128_GCM_SHA256 {0xC0, 0x2B}
+#define TLS_ECDHE_ECDSA_WITH_AES_256_GCM_SHA384 {0xC0, 0x2C}
+#define TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 {0xC0, 0x30}
+
+///
+/// TLS Version, refers to A.1 of rfc-2246, rfc-4346 and rfc-5246.
+///
+#define TLS10_PROTOCOL_VERSION_MAJOR 0x03
+#define TLS10_PROTOCOL_VERSION_MINOR 0x01
+#define TLS11_PROTOCOL_VERSION_MAJOR 0x03
+#define TLS11_PROTOCOL_VERSION_MINOR 0x02
+#define TLS12_PROTOCOL_VERSION_MAJOR 0x03
+#define TLS12_PROTOCOL_VERSION_MINOR 0x03
+
+///
+/// TLS Content Type, refers to A.1 of rfc-2246, rfc-4346 and rfc-5246.
+///
+typedef enum {
+ TlsContentTypeChangeCipherSpec = 20,
+ TlsContentTypeAlert = 21,
+ TlsContentTypeHandshake = 22,
+ TlsContentTypeApplicationData = 23,
+} TLS_CONTENT_TYPE;
+
+///
+/// TLS Record Header, refers to A.1 of rfc-2246, rfc-4346 and rfc-5246.
+///
+typedef struct {
+ UINT8 ContentType;
+ EFI_TLS_VERSION Version;
+ UINT16 Length;
+} TLS_RECORD_HEADER;
+
+#define TLS_RECORD_HEADER_LENGTH 5
+
+//
+// The length (in bytes) of the TLSPlaintext records payload MUST NOT exceed 2^14.
+// Refers to section 6.2 of RFC5246.
+//
+#define TLS_PLAINTEXT_RECORD_MAX_PAYLOAD_LENGTH 16384
+
+//
+// The length (in bytes) of the TLSCiphertext records payload MUST NOT exceed 2^14 + 2048.
+// Refers to section 6.2 of RFC5246.
+//
+#define TLS_CIPHERTEXT_RECORD_MAX_PAYLOAD_LENGTH 18432
+
+///
+/// TLS Hash algorithm, refers to section 7.4.1.4.1. of rfc-5246.
+///
+typedef enum {
+ TlsHashAlgoNone = 0,
+ TlsHashAlgoMd5 = 1,
+ TlsHashAlgoSha1 = 2,
+ TlsHashAlgoSha224 = 3,
+ TlsHashAlgoSha256 = 4,
+ TlsHashAlgoSha384 = 5,
+ TlsHashAlgoSha512 = 6,
+} TLS_HASH_ALGO;
+
+///
+/// TLS Signature algorithm, refers to section 7.4.1.4.1. of rfc-5246.
+///
+typedef enum {
+ TlsSignatureAlgoAnonymous = 0,
+ TlsSignatureAlgoRsa = 1,
+ TlsSignatureAlgoDsa = 2,
+ TlsSignatureAlgoEcdsa = 3,
+} TLS_SIGNATURE_ALGO;
+
+///
+/// TLS Supported Elliptic Curves Extensions, refers to section 5.1.1 of rfc-8422.
+///
+typedef enum {
+ TlsEcNamedCurveSecp256r1 = 23,
+ TlsEcNamedCurveSecp384r1 = 24,
+ TlsEcNamedCurveSecp521r1 = 25,
+ TlsEcNamedCurveX25519 = 29,
+ TlsEcNamedCurveX448 = 30,
+} TLS_EC_NAMED_CURVE;
+
+#pragma pack()
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/Tpm12.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/Tpm12.h
new file mode 100644
index 0000000000..031b206740
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/Tpm12.h
@@ -0,0 +1,2165 @@
+/** @file
+ TPM Specification data structures (TCG TPM Specification Version 1.2 Revision 103)
+ See http://trustedcomputinggroup.org for latest specification updates
+
+ Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _TPM12_H_
+#define _TPM12_H_
+
+///
+/// The start of TPM return codes
+///
+#define TPM_BASE 0
+
+//
+// All structures MUST be packed on a byte boundary.
+//
+
+#pragma pack (1)
+
+//
+// Part 2, section 2.2.3: Helper redefinitions
+//
+///
+/// Indicates the conditions where it is required that authorization be presented
+///
+typedef UINT8 TPM_AUTH_DATA_USAGE;
+///
+/// The information as to what the payload is in an encrypted structure
+///
+typedef UINT8 TPM_PAYLOAD_TYPE;
+///
+/// The version info breakdown
+///
+typedef UINT8 TPM_VERSION_BYTE;
+///
+/// The state of the dictionary attack mitigation logic
+///
+typedef UINT8 TPM_DA_STATE;
+///
+/// The request or response authorization type
+///
+typedef UINT16 TPM_TAG;
+///
+/// The protocol in use
+///
+typedef UINT16 TPM_PROTOCOL_ID;
+///
+/// Indicates the start state
+///
+typedef UINT16 TPM_STARTUP_TYPE;
+///
+/// The definition of the encryption scheme
+///
+typedef UINT16 TPM_ENC_SCHEME;
+///
+/// The definition of the signature scheme
+///
+typedef UINT16 TPM_SIG_SCHEME;
+///
+/// The definition of the migration scheme
+///
+typedef UINT16 TPM_MIGRATE_SCHEME;
+///
+/// Sets the state of the physical presence mechanism
+///
+typedef UINT16 TPM_PHYSICAL_PRESENCE;
+///
+/// Indicates the types of entity that are supported by the TPM
+///
+typedef UINT16 TPM_ENTITY_TYPE;
+///
+/// Indicates the permitted usage of the key
+///
+typedef UINT16 TPM_KEY_USAGE;
+///
+/// The type of asymmetric encrypted structure in use by the endorsement key
+///
+typedef UINT16 TPM_EK_TYPE;
+///
+/// The tag for the structure
+///
+typedef UINT16 TPM_STRUCTURE_TAG;
+///
+/// The platform specific spec to which the information relates to
+///
+typedef UINT16 TPM_PLATFORM_SPECIFIC;
+///
+/// The command ordinal
+///
+typedef UINT32 TPM_COMMAND_CODE;
+///
+/// Identifies a TPM capability area
+///
+typedef UINT32 TPM_CAPABILITY_AREA;
+///
+/// Indicates information regarding a key
+///
+typedef UINT32 TPM_KEY_FLAGS;
+///
+/// Indicates the type of algorithm
+///
+typedef UINT32 TPM_ALGORITHM_ID;
+///
+/// The locality modifier
+///
+typedef UINT32 TPM_MODIFIER_INDICATOR;
+///
+/// The actual number of a counter
+///
+typedef UINT32 TPM_ACTUAL_COUNT;
+///
+/// Attributes that define what options are in use for a transport session
+///
+typedef UINT32 TPM_TRANSPORT_ATTRIBUTES;
+///
+/// Handle to an authorization session
+///
+typedef UINT32 TPM_AUTHHANDLE;
+///
+/// Index to a DIR register
+///
+typedef UINT32 TPM_DIRINDEX;
+///
+/// The area where a key is held assigned by the TPM
+///
+typedef UINT32 TPM_KEY_HANDLE;
+///
+/// Index to a PCR register
+///
+typedef UINT32 TPM_PCRINDEX;
+///
+/// The return code from a function
+///
+typedef UINT32 TPM_RESULT;
+///
+/// The types of resources that a TPM may have using internal resources
+///
+typedef UINT32 TPM_RESOURCE_TYPE;
+///
+/// Allows for controlling of the key when loaded and how to handle TPM_Startup issues
+///
+typedef UINT32 TPM_KEY_CONTROL;
+///
+/// The index into the NV storage area
+///
+typedef UINT32 TPM_NV_INDEX;
+///
+/// The family ID. Family IDs are automatically assigned a sequence number by the TPM.
+/// A trusted process can set the FamilyID value in an individual row to NULL, which
+/// invalidates that row. The family ID resets to NULL on each change of TPM Owner.
+///
+typedef UINT32 TPM_FAMILY_ID;
+///
+/// IA value used as a label for the most recent verification of this family. Set to zero when not in use.
+///
+typedef UINT32 TPM_FAMILY_VERIFICATION;
+///
+/// How the TPM handles var
+///
+typedef UINT32 TPM_STARTUP_EFFECTS;
+///
+/// The mode of a symmetric encryption
+///
+typedef UINT32 TPM_SYM_MODE;
+///
+/// The family flags
+///
+typedef UINT32 TPM_FAMILY_FLAGS;
+///
+/// The index value for the delegate NV table
+///
+typedef UINT32 TPM_DELEGATE_INDEX;
+///
+/// The restrictions placed on delegation of CMK commands
+///
+typedef UINT32 TPM_CMK_DELEGATE;
+///
+/// The ID value of a monotonic counter
+///
+typedef UINT32 TPM_COUNT_ID;
+///
+/// A command to execute
+///
+typedef UINT32 TPM_REDIT_COMMAND;
+///
+/// A transport session handle
+///
+typedef UINT32 TPM_TRANSHANDLE;
+///
+/// A generic handle could be key, transport etc
+///
+typedef UINT32 TPM_HANDLE;
+///
+/// What operation is happening
+///
+typedef UINT32 TPM_FAMILY_OPERATION;
+
+//
+// Part 2, section 2.2.4: Vendor specific
+// The following defines allow for the quick specification of a
+// vendor specific item.
+//
+#define TPM_Vendor_Specific32 ((UINT32) 0x00000400)
+#define TPM_Vendor_Specific8 ((UINT8) 0x80)
+
+//
+// Part 2, section 3.1: TPM_STRUCTURE_TAG
+//
+#define TPM_TAG_CONTEXTBLOB ((TPM_STRUCTURE_TAG) 0x0001)
+#define TPM_TAG_CONTEXT_SENSITIVE ((TPM_STRUCTURE_TAG) 0x0002)
+#define TPM_TAG_CONTEXTPOINTER ((TPM_STRUCTURE_TAG) 0x0003)
+#define TPM_TAG_CONTEXTLIST ((TPM_STRUCTURE_TAG) 0x0004)
+#define TPM_TAG_SIGNINFO ((TPM_STRUCTURE_TAG) 0x0005)
+#define TPM_TAG_PCR_INFO_LONG ((TPM_STRUCTURE_TAG) 0x0006)
+#define TPM_TAG_PERSISTENT_FLAGS ((TPM_STRUCTURE_TAG) 0x0007)
+#define TPM_TAG_VOLATILE_FLAGS ((TPM_STRUCTURE_TAG) 0x0008)
+#define TPM_TAG_PERSISTENT_DATA ((TPM_STRUCTURE_TAG) 0x0009)
+#define TPM_TAG_VOLATILE_DATA ((TPM_STRUCTURE_TAG) 0x000A)
+#define TPM_TAG_SV_DATA ((TPM_STRUCTURE_TAG) 0x000B)
+#define TPM_TAG_EK_BLOB ((TPM_STRUCTURE_TAG) 0x000C)
+#define TPM_TAG_EK_BLOB_AUTH ((TPM_STRUCTURE_TAG) 0x000D)
+#define TPM_TAG_COUNTER_VALUE ((TPM_STRUCTURE_TAG) 0x000E)
+#define TPM_TAG_TRANSPORT_INTERNAL ((TPM_STRUCTURE_TAG) 0x000F)
+#define TPM_TAG_TRANSPORT_LOG_IN ((TPM_STRUCTURE_TAG) 0x0010)
+#define TPM_TAG_TRANSPORT_LOG_OUT ((TPM_STRUCTURE_TAG) 0x0011)
+#define TPM_TAG_AUDIT_EVENT_IN ((TPM_STRUCTURE_TAG) 0x0012)
+#define TPM_TAG_AUDIT_EVENT_OUT ((TPM_STRUCTURE_TAG) 0x0013)
+#define TPM_TAG_CURRENT_TICKS ((TPM_STRUCTURE_TAG) 0x0014)
+#define TPM_TAG_KEY ((TPM_STRUCTURE_TAG) 0x0015)
+#define TPM_TAG_STORED_DATA12 ((TPM_STRUCTURE_TAG) 0x0016)
+#define TPM_TAG_NV_ATTRIBUTES ((TPM_STRUCTURE_TAG) 0x0017)
+#define TPM_TAG_NV_DATA_PUBLIC ((TPM_STRUCTURE_TAG) 0x0018)
+#define TPM_TAG_NV_DATA_SENSITIVE ((TPM_STRUCTURE_TAG) 0x0019)
+#define TPM_TAG_DELEGATIONS ((TPM_STRUCTURE_TAG) 0x001A)
+#define TPM_TAG_DELEGATE_PUBLIC ((TPM_STRUCTURE_TAG) 0x001B)
+#define TPM_TAG_DELEGATE_TABLE_ROW ((TPM_STRUCTURE_TAG) 0x001C)
+#define TPM_TAG_TRANSPORT_AUTH ((TPM_STRUCTURE_TAG) 0x001D)
+#define TPM_TAG_TRANSPORT_PUBLIC ((TPM_STRUCTURE_TAG) 0x001E)
+#define TPM_TAG_PERMANENT_FLAGS ((TPM_STRUCTURE_TAG) 0x001F)
+#define TPM_TAG_STCLEAR_FLAGS ((TPM_STRUCTURE_TAG) 0x0020)
+#define TPM_TAG_STANY_FLAGS ((TPM_STRUCTURE_TAG) 0x0021)
+#define TPM_TAG_PERMANENT_DATA ((TPM_STRUCTURE_TAG) 0x0022)
+#define TPM_TAG_STCLEAR_DATA ((TPM_STRUCTURE_TAG) 0x0023)
+#define TPM_TAG_STANY_DATA ((TPM_STRUCTURE_TAG) 0x0024)
+#define TPM_TAG_FAMILY_TABLE_ENTRY ((TPM_STRUCTURE_TAG) 0x0025)
+#define TPM_TAG_DELEGATE_SENSITIVE ((TPM_STRUCTURE_TAG) 0x0026)
+#define TPM_TAG_DELG_KEY_BLOB ((TPM_STRUCTURE_TAG) 0x0027)
+#define TPM_TAG_KEY12 ((TPM_STRUCTURE_TAG) 0x0028)
+#define TPM_TAG_CERTIFY_INFO2 ((TPM_STRUCTURE_TAG) 0x0029)
+#define TPM_TAG_DELEGATE_OWNER_BLOB ((TPM_STRUCTURE_TAG) 0x002A)
+#define TPM_TAG_EK_BLOB_ACTIVATE ((TPM_STRUCTURE_TAG) 0x002B)
+#define TPM_TAG_DAA_BLOB ((TPM_STRUCTURE_TAG) 0x002C)
+#define TPM_TAG_DAA_CONTEXT ((TPM_STRUCTURE_TAG) 0x002D)
+#define TPM_TAG_DAA_ENFORCE ((TPM_STRUCTURE_TAG) 0x002E)
+#define TPM_TAG_DAA_ISSUER ((TPM_STRUCTURE_TAG) 0x002F)
+#define TPM_TAG_CAP_VERSION_INFO ((TPM_STRUCTURE_TAG) 0x0030)
+#define TPM_TAG_DAA_SENSITIVE ((TPM_STRUCTURE_TAG) 0x0031)
+#define TPM_TAG_DAA_TPM ((TPM_STRUCTURE_TAG) 0x0032)
+#define TPM_TAG_CMK_MIGAUTH ((TPM_STRUCTURE_TAG) 0x0033)
+#define TPM_TAG_CMK_SIGTICKET ((TPM_STRUCTURE_TAG) 0x0034)
+#define TPM_TAG_CMK_MA_APPROVAL ((TPM_STRUCTURE_TAG) 0x0035)
+#define TPM_TAG_QUOTE_INFO2 ((TPM_STRUCTURE_TAG) 0x0036)
+#define TPM_TAG_DA_INFO ((TPM_STRUCTURE_TAG) 0x0037)
+#define TPM_TAG_DA_LIMITED ((TPM_STRUCTURE_TAG) 0x0038)
+#define TPM_TAG_DA_ACTION_TYPE ((TPM_STRUCTURE_TAG) 0x0039)
+
+//
+// Part 2, section 4: TPM Types
+//
+
+//
+// Part 2, section 4.1: TPM_RESOURCE_TYPE
+//
+#define TPM_RT_KEY ((TPM_RESOURCE_TYPE) 0x00000001) ///< The handle is a key handle and is the result of a LoadKey type operation
+#define TPM_RT_AUTH ((TPM_RESOURCE_TYPE) 0x00000002) ///< The handle is an authorization handle. Auth handles come from TPM_OIAP, TPM_OSAP and TPM_DSAP
+#define TPM_RT_HASH ((TPM_RESOURCE_TYPE) 0x00000003) ///< Reserved for hashes
+#define TPM_RT_TRANS ((TPM_RESOURCE_TYPE) 0x00000004) ///< The handle is for a transport session. Transport handles come from TPM_EstablishTransport
+#define TPM_RT_CONTEXT ((TPM_RESOURCE_TYPE) 0x00000005) ///< Resource wrapped and held outside the TPM using the context save/restore commands
+#define TPM_RT_COUNTER ((TPM_RESOURCE_TYPE) 0x00000006) ///< Reserved for counters
+#define TPM_RT_DELEGATE ((TPM_RESOURCE_TYPE) 0x00000007) ///< The handle is for a delegate row. These are the internal rows held in NV storage by the TPM
+#define TPM_RT_DAA_TPM ((TPM_RESOURCE_TYPE) 0x00000008) ///< The value is a DAA TPM specific blob
+#define TPM_RT_DAA_V0 ((TPM_RESOURCE_TYPE) 0x00000009) ///< The value is a DAA V0 parameter
+#define TPM_RT_DAA_V1 ((TPM_RESOURCE_TYPE) 0x0000000A) ///< The value is a DAA V1 parameter
+
+//
+// Part 2, section 4.2: TPM_PAYLOAD_TYPE
+//
+#define TPM_PT_ASYM ((TPM_PAYLOAD_TYPE) 0x01) ///< The entity is an asymmetric key
+#define TPM_PT_BIND ((TPM_PAYLOAD_TYPE) 0x02) ///< The entity is bound data
+#define TPM_PT_MIGRATE ((TPM_PAYLOAD_TYPE) 0x03) ///< The entity is a migration blob
+#define TPM_PT_MAINT ((TPM_PAYLOAD_TYPE) 0x04) ///< The entity is a maintenance blob
+#define TPM_PT_SEAL ((TPM_PAYLOAD_TYPE) 0x05) ///< The entity is sealed data
+#define TPM_PT_MIGRATE_RESTRICTED ((TPM_PAYLOAD_TYPE) 0x06) ///< The entity is a restricted-migration asymmetric key
+#define TPM_PT_MIGRATE_EXTERNAL ((TPM_PAYLOAD_TYPE) 0x07) ///< The entity is a external migratable key
+#define TPM_PT_CMK_MIGRATE ((TPM_PAYLOAD_TYPE) 0x08) ///< The entity is a CMK migratable blob
+#define TPM_PT_VENDOR_SPECIFIC ((TPM_PAYLOAD_TYPE) 0x80) ///< 0x80 - 0xFF Vendor specific payloads
+
+//
+// Part 2, section 4.3: TPM_ENTITY_TYPE
+//
+#define TPM_ET_KEYHANDLE ((UINT16) 0x0001) ///< The entity is a keyHandle or key
+#define TPM_ET_OWNER ((UINT16) 0x0002) ///< The entity is the TPM Owner
+#define TPM_ET_DATA ((UINT16) 0x0003) ///< The entity is some data
+#define TPM_ET_SRK ((UINT16) 0x0004) ///< The entity is the SRK
+#define TPM_ET_KEY ((UINT16) 0x0005) ///< The entity is a key or keyHandle
+#define TPM_ET_REVOKE ((UINT16) 0x0006) ///< The entity is the RevokeTrust value
+#define TPM_ET_DEL_OWNER_BLOB ((UINT16) 0x0007) ///< The entity is a delegate owner blob
+#define TPM_ET_DEL_ROW ((UINT16) 0x0008) ///< The entity is a delegate row
+#define TPM_ET_DEL_KEY_BLOB ((UINT16) 0x0009) ///< The entity is a delegate key blob
+#define TPM_ET_COUNTER ((UINT16) 0x000A) ///< The entity is a counter
+#define TPM_ET_NV ((UINT16) 0x000B) ///< The entity is a NV index
+#define TPM_ET_OPERATOR ((UINT16) 0x000C) ///< The entity is the operator
+#define TPM_ET_RESERVED_HANDLE ((UINT16) 0x0040) ///< Reserved. This value avoids collisions with the handle MSB setting.
+//
+// TPM_ENTITY_TYPE MSB Values: The MSB is used to indicate the ADIP encryption sheme when applicable
+//
+#define TPM_ET_XOR ((UINT16) 0x0000) ///< ADIP encryption scheme: XOR
+#define TPM_ET_AES128 ((UINT16) 0x0006) ///< ADIP encryption scheme: AES 128 bits
+
+//
+// Part 2, section 4.4.1: Reserved Key Handles
+//
+#define TPM_KH_SRK ((TPM_KEY_HANDLE) 0x40000000) ///< The handle points to the SRK
+#define TPM_KH_OWNER ((TPM_KEY_HANDLE) 0x40000001) ///< The handle points to the TPM Owner
+#define TPM_KH_REVOKE ((TPM_KEY_HANDLE) 0x40000002) ///< The handle points to the RevokeTrust value
+#define TPM_KH_TRANSPORT ((TPM_KEY_HANDLE) 0x40000003) ///< The handle points to the EstablishTransport static authorization
+#define TPM_KH_OPERATOR ((TPM_KEY_HANDLE) 0x40000004) ///< The handle points to the Operator auth
+#define TPM_KH_ADMIN ((TPM_KEY_HANDLE) 0x40000005) ///< The handle points to the delegation administration auth
+#define TPM_KH_EK ((TPM_KEY_HANDLE) 0x40000006) ///< The handle points to the PUBEK, only usable with TPM_OwnerReadInternalPub
+
+//
+// Part 2, section 4.5: TPM_STARTUP_TYPE
+//
+#define TPM_ST_CLEAR ((TPM_STARTUP_TYPE) 0x0001) ///< The TPM is starting up from a clean state
+#define TPM_ST_STATE ((TPM_STARTUP_TYPE) 0x0002) ///< The TPM is starting up from a saved state
+#define TPM_ST_DEACTIVATED ((TPM_STARTUP_TYPE) 0x0003) ///< The TPM is to startup and set the deactivated flag to TRUE
+
+//
+// Part 2, section 4.6: TPM_STATUP_EFFECTS
+// The table makeup is still an open issue.
+//
+
+//
+// Part 2, section 4.7: TPM_PROTOCOL_ID
+//
+#define TPM_PID_OIAP ((TPM_PROTOCOL_ID) 0x0001) ///< The OIAP protocol.
+#define TPM_PID_OSAP ((TPM_PROTOCOL_ID) 0x0002) ///< The OSAP protocol.
+#define TPM_PID_ADIP ((TPM_PROTOCOL_ID) 0x0003) ///< The ADIP protocol.
+#define TPM_PID_ADCP ((TPM_PROTOCOL_ID) 0x0004) ///< The ADCP protocol.
+#define TPM_PID_OWNER ((TPM_PROTOCOL_ID) 0x0005) ///< The protocol for taking ownership of a TPM.
+#define TPM_PID_DSAP ((TPM_PROTOCOL_ID) 0x0006) ///< The DSAP protocol
+#define TPM_PID_TRANSPORT ((TPM_PROTOCOL_ID) 0x0007) ///< The transport protocol
+
+//
+// Part 2, section 4.8: TPM_ALGORITHM_ID
+// The TPM MUST support the algorithms TPM_ALG_RSA, TPM_ALG_SHA, TPM_ALG_HMAC,
+// TPM_ALG_MGF1
+//
+#define TPM_ALG_RSA ((TPM_ALGORITHM_ID) 0x00000001) ///< The RSA algorithm.
+#define TPM_ALG_DES ((TPM_ALGORITHM_ID) 0x00000002) ///< The DES algorithm
+#define TPM_ALG_3DES ((TPM_ALGORITHM_ID) 0x00000003) ///< The 3DES algorithm in EDE mode
+#define TPM_ALG_SHA ((TPM_ALGORITHM_ID) 0x00000004) ///< The SHA1 algorithm
+#define TPM_ALG_HMAC ((TPM_ALGORITHM_ID) 0x00000005) ///< The RFC 2104 HMAC algorithm
+#define TPM_ALG_AES128 ((TPM_ALGORITHM_ID) 0x00000006) ///< The AES algorithm, key size 128
+#define TPM_ALG_MGF1 ((TPM_ALGORITHM_ID) 0x00000007) ///< The XOR algorithm using MGF1 to create a string the size of the encrypted block
+#define TPM_ALG_AES192 ((TPM_ALGORITHM_ID) 0x00000008) ///< AES, key size 192
+#define TPM_ALG_AES256 ((TPM_ALGORITHM_ID) 0x00000009) ///< AES, key size 256
+#define TPM_ALG_XOR ((TPM_ALGORITHM_ID) 0x0000000A) ///< XOR using the rolling nonces
+
+//
+// Part 2, section 4.9: TPM_PHYSICAL_PRESENCE
+//
+#define TPM_PHYSICAL_PRESENCE_HW_DISABLE ((TPM_PHYSICAL_PRESENCE) 0x0200) ///< Sets the physicalPresenceHWEnable to FALSE
+#define TPM_PHYSICAL_PRESENCE_CMD_DISABLE ((TPM_PHYSICAL_PRESENCE) 0x0100) ///< Sets the physicalPresenceCMDEnable to FALSE
+#define TPM_PHYSICAL_PRESENCE_LIFETIME_LOCK ((TPM_PHYSICAL_PRESENCE) 0x0080) ///< Sets the physicalPresenceLifetimeLock to TRUE
+#define TPM_PHYSICAL_PRESENCE_HW_ENABLE ((TPM_PHYSICAL_PRESENCE) 0x0040) ///< Sets the physicalPresenceHWEnable to TRUE
+#define TPM_PHYSICAL_PRESENCE_CMD_ENABLE ((TPM_PHYSICAL_PRESENCE) 0x0020) ///< Sets the physicalPresenceCMDEnable to TRUE
+#define TPM_PHYSICAL_PRESENCE_NOTPRESENT ((TPM_PHYSICAL_PRESENCE) 0x0010) ///< Sets PhysicalPresence = FALSE
+#define TPM_PHYSICAL_PRESENCE_PRESENT ((TPM_PHYSICAL_PRESENCE) 0x0008) ///< Sets PhysicalPresence = TRUE
+#define TPM_PHYSICAL_PRESENCE_LOCK ((TPM_PHYSICAL_PRESENCE) 0x0004) ///< Sets PhysicalPresenceLock = TRUE
+
+//
+// Part 2, section 4.10: TPM_MIGRATE_SCHEME
+//
+#define TPM_MS_MIGRATE ((TPM_MIGRATE_SCHEME) 0x0001) ///< A public key that can be used with all TPM migration commands other than 'ReWrap' mode.
+#define TPM_MS_REWRAP ((TPM_MIGRATE_SCHEME) 0x0002) ///< A public key that can be used for the ReWrap mode of TPM_CreateMigrationBlob.
+#define TPM_MS_MAINT ((TPM_MIGRATE_SCHEME) 0x0003) ///< A public key that can be used for the Maintenance commands
+#define TPM_MS_RESTRICT_MIGRATE ((TPM_MIGRATE_SCHEME) 0x0004) ///< The key is to be migrated to a Migration Authority.
+#define TPM_MS_RESTRICT_APPROVE_DOUBLE ((TPM_MIGRATE_SCHEME) 0x0005) ///< The key is to be migrated to an entity approved by a Migration Authority using double wrapping
+
+//
+// Part 2, section 4.11: TPM_EK_TYPE
+//
+#define TPM_EK_TYPE_ACTIVATE ((TPM_EK_TYPE) 0x0001) ///< The blob MUST be TPM_EK_BLOB_ACTIVATE
+#define TPM_EK_TYPE_AUTH ((TPM_EK_TYPE) 0x0002) ///< The blob MUST be TPM_EK_BLOB_AUTH
+
+//
+// Part 2, section 4.12: TPM_PLATFORM_SPECIFIC
+//
+#define TPM_PS_PC_11 ((TPM_PLATFORM_SPECIFIC) 0x0001) ///< PC Specific version 1.1
+#define TPM_PS_PC_12 ((TPM_PLATFORM_SPECIFIC) 0x0002) ///< PC Specific version 1.2
+#define TPM_PS_PDA_12 ((TPM_PLATFORM_SPECIFIC) 0x0003) ///< PDA Specific version 1.2
+#define TPM_PS_Server_12 ((TPM_PLATFORM_SPECIFIC) 0x0004) ///< Server Specific version 1.2
+#define TPM_PS_Mobile_12 ((TPM_PLATFORM_SPECIFIC) 0x0005) ///< Mobil Specific version 1.2
+
+//
+// Part 2, section 5: Basic Structures
+//
+
+///
+/// Part 2, section 5.1: TPM_STRUCT_VER
+///
+typedef struct tdTPM_STRUCT_VER {
+ UINT8 major;
+ UINT8 minor;
+ UINT8 revMajor;
+ UINT8 revMinor;
+} TPM_STRUCT_VER;
+
+///
+/// Part 2, section 5.3: TPM_VERSION
+///
+typedef struct tdTPM_VERSION {
+ TPM_VERSION_BYTE major;
+ TPM_VERSION_BYTE minor;
+ UINT8 revMajor;
+ UINT8 revMinor;
+} TPM_VERSION;
+
+#define TPM_SHA1_160_HASH_LEN 0x14
+#define TPM_SHA1BASED_NONCE_LEN TPM_SHA1_160_HASH_LEN
+
+///
+/// Part 2, section 5.4: TPM_DIGEST
+///
+typedef struct tdTPM_DIGEST {
+ UINT8 digest[TPM_SHA1_160_HASH_LEN];
+} TPM_DIGEST;
+
+///
+/// This SHALL be the digest of the chosen identityLabel and privacyCA for a new TPM identity
+///
+typedef TPM_DIGEST TPM_CHOSENID_HASH;
+///
+/// This SHALL be the hash of a list of PCR indexes and PCR values that a key or data is bound to
+///
+typedef TPM_DIGEST TPM_COMPOSITE_HASH;
+///
+/// This SHALL be the value of a DIR register
+///
+typedef TPM_DIGEST TPM_DIRVALUE;
+
+typedef TPM_DIGEST TPM_HMAC;
+///
+/// The value inside of the PCR
+///
+typedef TPM_DIGEST TPM_PCRVALUE;
+///
+/// This SHALL be the value of the current internal audit state
+///
+typedef TPM_DIGEST TPM_AUDITDIGEST;
+
+///
+/// Part 2, section 5.5: TPM_NONCE
+///
+typedef struct tdTPM_NONCE {
+ UINT8 nonce[20];
+} TPM_NONCE;
+
+///
+/// This SHALL be a random value generated by a TPM immediately after the EK is installed
+/// in that TPM, whenever an EK is installed in that TPM
+///
+typedef TPM_NONCE TPM_DAA_TPM_SEED;
+///
+/// This SHALL be a random value
+///
+typedef TPM_NONCE TPM_DAA_CONTEXT_SEED;
+
+//
+// Part 2, section 5.6: TPM_AUTHDATA
+//
+///
+/// The AuthData data is the information that is saved or passed to provide proof of ownership
+/// 296 of an entity
+///
+typedef UINT8 tdTPM_AUTHDATA[20];
+
+typedef tdTPM_AUTHDATA TPM_AUTHDATA;
+///
+/// A secret plaintext value used in the authorization process
+///
+typedef TPM_AUTHDATA TPM_SECRET;
+///
+/// A ciphertext (encrypted) version of AuthData data. The encryption mechanism depends on the context
+///
+typedef TPM_AUTHDATA TPM_ENCAUTH;
+
+///
+/// Part 2, section 5.7: TPM_KEY_HANDLE_LIST
+/// Size of handle is loaded * sizeof(TPM_KEY_HANDLE)
+///
+typedef struct tdTPM_KEY_HANDLE_LIST {
+ UINT16 loaded;
+ TPM_KEY_HANDLE handle[1];
+} TPM_KEY_HANDLE_LIST;
+
+//
+// Part 2, section 5.8: TPM_KEY_USAGE values
+//
+///
+/// TPM_KEY_SIGNING SHALL indicate a signing key. The [private] key SHALL be
+/// used for signing operations, only. This means that it MUST be a leaf of the
+/// Protected Storage key hierarchy.
+///
+#define TPM_KEY_SIGNING ((UINT16) 0x0010)
+///
+/// TPM_KEY_STORAGE SHALL indicate a storage key. The key SHALL be used to wrap
+/// and unwrap other keys in the Protected Storage hierarchy
+///
+#define TPM_KEY_STORAGE ((UINT16) 0x0011)
+///
+/// TPM_KEY_IDENTITY SHALL indicate an identity key. The key SHALL be used for
+/// operations that require a TPM identity, only.
+///
+#define TPM_KEY_IDENTITY ((UINT16) 0x0012)
+///
+/// TPM_KEY_AUTHCHANGE SHALL indicate an ephemeral key that is in use during
+/// the ChangeAuthAsym process, only.
+///
+#define TPM_KEY_AUTHCHANGE ((UINT16) 0x0013)
+///
+/// TPM_KEY_BIND SHALL indicate a key that can be used for TPM_Bind and
+/// TPM_Unbind operations only.
+///
+#define TPM_KEY_BIND ((UINT16) 0x0014)
+///
+/// TPM_KEY_LEGACY SHALL indicate a key that can perform signing and binding
+/// operations. The key MAY be used for both signing and binding operations.
+/// The TPM_KEY_LEGACY key type is to allow for use by applications where both
+/// signing and encryption operations occur with the same key. The use of this
+/// key type is not recommended TPM_KEY_MIGRATE 0x0016 This SHALL indicate a
+/// key in use for TPM_MigrateKey
+///
+#define TPM_KEY_LEGACY ((UINT16) 0x0015)
+///
+/// TPM_KEY_MIGRAGE SHALL indicate a key in use for TPM_MigrateKey
+///
+#define TPM_KEY_MIGRATE ((UINT16) 0x0016)
+
+//
+// Part 2, section 5.8.1: Mandatory Key Usage Schemes
+//
+
+#define TPM_ES_NONE ((TPM_ENC_SCHEME) 0x0001)
+#define TPM_ES_RSAESPKCSv15 ((TPM_ENC_SCHEME) 0x0002)
+#define TPM_ES_RSAESOAEP_SHA1_MGF1 ((TPM_ENC_SCHEME) 0x0003)
+#define TPM_ES_SYM_CNT ((TPM_ENC_SCHEME) 0x0004) ///< rev94 defined
+#define TPM_ES_SYM_CTR ((TPM_ENC_SCHEME) 0x0004)
+#define TPM_ES_SYM_OFB ((TPM_ENC_SCHEME) 0x0005)
+
+#define TPM_SS_NONE ((TPM_SIG_SCHEME) 0x0001)
+#define TPM_SS_RSASSAPKCS1v15_SHA1 ((TPM_SIG_SCHEME) 0x0002)
+#define TPM_SS_RSASSAPKCS1v15_DER ((TPM_SIG_SCHEME) 0x0003)
+#define TPM_SS_RSASSAPKCS1v15_INFO ((TPM_SIG_SCHEME) 0x0004)
+
+//
+// Part 2, section 5.9: TPM_AUTH_DATA_USAGE values
+//
+#define TPM_AUTH_NEVER ((TPM_AUTH_DATA_USAGE) 0x00)
+#define TPM_AUTH_ALWAYS ((TPM_AUTH_DATA_USAGE) 0x01)
+#define TPM_AUTH_PRIV_USE_ONLY ((TPM_AUTH_DATA_USAGE) 0x03)
+
+///
+/// Part 2, section 5.10: TPM_KEY_FLAGS
+///
+typedef enum tdTPM_KEY_FLAGS {
+ redirection = 0x00000001,
+ migratable = 0x00000002,
+ isVolatile = 0x00000004,
+ pcrIgnoredOnRead = 0x00000008,
+ migrateAuthority = 0x00000010
+} TPM_KEY_FLAGS_BITS;
+
+///
+/// Part 2, section 5.11: TPM_CHANGEAUTH_VALIDATE
+///
+typedef struct tdTPM_CHANGEAUTH_VALIDATE {
+ TPM_SECRET newAuthSecret;
+ TPM_NONCE n1;
+} TPM_CHANGEAUTH_VALIDATE;
+
+///
+/// Part 2, section 5.12: TPM_MIGRATIONKEYAUTH
+/// declared after section 10 to catch declaration of TPM_PUBKEY
+///
+/// Part 2 section 10.1: TPM_KEY_PARMS
+/// [size_is(parmSize)] BYTE* parms;
+///
+typedef struct tdTPM_KEY_PARMS {
+ TPM_ALGORITHM_ID algorithmID;
+ TPM_ENC_SCHEME encScheme;
+ TPM_SIG_SCHEME sigScheme;
+ UINT32 parmSize;
+ UINT8 *parms;
+} TPM_KEY_PARMS;
+
+///
+/// Part 2, section 10.4: TPM_STORE_PUBKEY
+///
+typedef struct tdTPM_STORE_PUBKEY {
+ UINT32 keyLength;
+ UINT8 key[1];
+} TPM_STORE_PUBKEY;
+
+///
+/// Part 2, section 10.5: TPM_PUBKEY
+///
+typedef struct tdTPM_PUBKEY {
+ TPM_KEY_PARMS algorithmParms;
+ TPM_STORE_PUBKEY pubKey;
+} TPM_PUBKEY;
+
+///
+/// Part 2, section 5.12: TPM_MIGRATIONKEYAUTH
+///
+typedef struct tdTPM_MIGRATIONKEYAUTH {
+ TPM_PUBKEY migrationKey;
+ TPM_MIGRATE_SCHEME migrationScheme;
+ TPM_DIGEST digest;
+} TPM_MIGRATIONKEYAUTH;
+
+///
+/// Part 2, section 5.13: TPM_COUNTER_VALUE
+///
+typedef struct tdTPM_COUNTER_VALUE {
+ TPM_STRUCTURE_TAG tag;
+ UINT8 label[4];
+ TPM_ACTUAL_COUNT counter;
+} TPM_COUNTER_VALUE;
+
+///
+/// Part 2, section 5.14: TPM_SIGN_INFO
+/// Size of data indicated by dataLen
+///
+typedef struct tdTPM_SIGN_INFO {
+ TPM_STRUCTURE_TAG tag;
+ UINT8 fixed[4];
+ TPM_NONCE replay;
+ UINT32 dataLen;
+ UINT8 *data;
+} TPM_SIGN_INFO;
+
+///
+/// Part 2, section 5.15: TPM_MSA_COMPOSITE
+/// Number of migAuthDigest indicated by MSAlist
+///
+typedef struct tdTPM_MSA_COMPOSITE {
+ UINT32 MSAlist;
+ TPM_DIGEST migAuthDigest[1];
+} TPM_MSA_COMPOSITE;
+
+///
+/// Part 2, section 5.16: TPM_CMK_AUTH
+///
+typedef struct tdTPM_CMK_AUTH {
+ TPM_DIGEST migrationAuthorityDigest;
+ TPM_DIGEST destinationKeyDigest;
+ TPM_DIGEST sourceKeyDigest;
+} TPM_CMK_AUTH;
+
+//
+// Part 2, section 5.17: TPM_CMK_DELEGATE
+//
+#define TPM_CMK_DELEGATE_SIGNING ((TPM_CMK_DELEGATE) BIT31)
+#define TPM_CMK_DELEGATE_STORAGE ((TPM_CMK_DELEGATE) BIT30)
+#define TPM_CMK_DELEGATE_BIND ((TPM_CMK_DELEGATE) BIT29)
+#define TPM_CMK_DELEGATE_LEGACY ((TPM_CMK_DELEGATE) BIT28)
+#define TPM_CMK_DELEGATE_MIGRATE ((TPM_CMK_DELEGATE) BIT27)
+
+///
+/// Part 2, section 5.18: TPM_SELECT_SIZE
+///
+typedef struct tdTPM_SELECT_SIZE {
+ UINT8 major;
+ UINT8 minor;
+ UINT16 reqSize;
+} TPM_SELECT_SIZE;
+
+///
+/// Part 2, section 5,19: TPM_CMK_MIGAUTH
+///
+typedef struct tdTPM_CMK_MIGAUTH {
+ TPM_STRUCTURE_TAG tag;
+ TPM_DIGEST msaDigest;
+ TPM_DIGEST pubKeyDigest;
+} TPM_CMK_MIGAUTH;
+
+///
+/// Part 2, section 5.20: TPM_CMK_SIGTICKET
+///
+typedef struct tdTPM_CMK_SIGTICKET {
+ TPM_STRUCTURE_TAG tag;
+ TPM_DIGEST verKeyDigest;
+ TPM_DIGEST signedData;
+} TPM_CMK_SIGTICKET;
+
+///
+/// Part 2, section 5.21: TPM_CMK_MA_APPROVAL
+///
+typedef struct tdTPM_CMK_MA_APPROVAL {
+ TPM_STRUCTURE_TAG tag;
+ TPM_DIGEST migrationAuthorityDigest;
+} TPM_CMK_MA_APPROVAL;
+
+//
+// Part 2, section 6: Command Tags
+//
+#define TPM_TAG_RQU_COMMAND ((TPM_STRUCTURE_TAG) 0x00C1)
+#define TPM_TAG_RQU_AUTH1_COMMAND ((TPM_STRUCTURE_TAG) 0x00C2)
+#define TPM_TAG_RQU_AUTH2_COMMAND ((TPM_STRUCTURE_TAG) 0x00C3)
+#define TPM_TAG_RSP_COMMAND ((TPM_STRUCTURE_TAG) 0x00C4)
+#define TPM_TAG_RSP_AUTH1_COMMAND ((TPM_STRUCTURE_TAG) 0x00C5)
+#define TPM_TAG_RSP_AUTH2_COMMAND ((TPM_STRUCTURE_TAG) 0x00C6)
+
+///
+/// Part 2, section 7.1: TPM_PERMANENT_FLAGS
+///
+typedef struct tdTPM_PERMANENT_FLAGS {
+ TPM_STRUCTURE_TAG tag;
+ BOOLEAN disable;
+ BOOLEAN ownership;
+ BOOLEAN deactivated;
+ BOOLEAN readPubek;
+ BOOLEAN disableOwnerClear;
+ BOOLEAN allowMaintenance;
+ BOOLEAN physicalPresenceLifetimeLock;
+ BOOLEAN physicalPresenceHWEnable;
+ BOOLEAN physicalPresenceCMDEnable;
+ BOOLEAN CEKPUsed;
+ BOOLEAN TPMpost;
+ BOOLEAN TPMpostLock;
+ BOOLEAN FIPS;
+ BOOLEAN operator;
+ BOOLEAN enableRevokeEK;
+ BOOLEAN nvLocked;
+ BOOLEAN readSRKPub;
+ BOOLEAN tpmEstablished;
+ BOOLEAN maintenanceDone;
+ BOOLEAN disableFullDALogicInfo;
+} TPM_PERMANENT_FLAGS;
+
+//
+// Part 2, section 7.1.1: Flag Restrictions (of TPM_PERMANENT_FLAGS)
+//
+#define TPM_PF_DISABLE ((TPM_CAPABILITY_AREA) 1)
+#define TPM_PF_OWNERSHIP ((TPM_CAPABILITY_AREA) 2)
+#define TPM_PF_DEACTIVATED ((TPM_CAPABILITY_AREA) 3)
+#define TPM_PF_READPUBEK ((TPM_CAPABILITY_AREA) 4)
+#define TPM_PF_DISABLEOWNERCLEAR ((TPM_CAPABILITY_AREA) 5)
+#define TPM_PF_ALLOWMAINTENANCE ((TPM_CAPABILITY_AREA) 6)
+#define TPM_PF_PHYSICALPRESENCELIFETIMELOCK ((TPM_CAPABILITY_AREA) 7)
+#define TPM_PF_PHYSICALPRESENCEHWENABLE ((TPM_CAPABILITY_AREA) 8)
+#define TPM_PF_PHYSICALPRESENCECMDENABLE ((TPM_CAPABILITY_AREA) 9)
+#define TPM_PF_CEKPUSED ((TPM_CAPABILITY_AREA) 10)
+#define TPM_PF_TPMPOST ((TPM_CAPABILITY_AREA) 11)
+#define TPM_PF_TPMPOSTLOCK ((TPM_CAPABILITY_AREA) 12)
+#define TPM_PF_FIPS ((TPM_CAPABILITY_AREA) 13)
+#define TPM_PF_OPERATOR ((TPM_CAPABILITY_AREA) 14)
+#define TPM_PF_ENABLEREVOKEEK ((TPM_CAPABILITY_AREA) 15)
+#define TPM_PF_NV_LOCKED ((TPM_CAPABILITY_AREA) 16)
+#define TPM_PF_READSRKPUB ((TPM_CAPABILITY_AREA) 17)
+#define TPM_PF_TPMESTABLISHED ((TPM_CAPABILITY_AREA) 18)
+#define TPM_PF_MAINTENANCEDONE ((TPM_CAPABILITY_AREA) 19)
+#define TPM_PF_DISABLEFULLDALOGICINFO ((TPM_CAPABILITY_AREA) 20)
+
+///
+/// Part 2, section 7.2: TPM_STCLEAR_FLAGS
+///
+typedef struct tdTPM_STCLEAR_FLAGS {
+ TPM_STRUCTURE_TAG tag;
+ BOOLEAN deactivated;
+ BOOLEAN disableForceClear;
+ BOOLEAN physicalPresence;
+ BOOLEAN physicalPresenceLock;
+ BOOLEAN bGlobalLock;
+} TPM_STCLEAR_FLAGS;
+
+//
+// Part 2, section 7.2.1: Flag Restrictions (of TPM_STCLEAR_FLAGS)
+//
+#define TPM_SF_DEACTIVATED ((TPM_CAPABILITY_AREA) 1)
+#define TPM_SF_DISABLEFORCECLEAR ((TPM_CAPABILITY_AREA) 2)
+#define TPM_SF_PHYSICALPRESENCE ((TPM_CAPABILITY_AREA) 3)
+#define TPM_SF_PHYSICALPRESENCELOCK ((TPM_CAPABILITY_AREA) 4)
+#define TPM_SF_BGLOBALLOCK ((TPM_CAPABILITY_AREA) 5)
+
+///
+/// Part 2, section 7.3: TPM_STANY_FLAGS
+///
+typedef struct tdTPM_STANY_FLAGS {
+ TPM_STRUCTURE_TAG tag;
+ BOOLEAN postInitialise;
+ TPM_MODIFIER_INDICATOR localityModifier;
+ BOOLEAN transportExclusive;
+ BOOLEAN TOSPresent;
+} TPM_STANY_FLAGS;
+
+//
+// Part 2, section 7.3.1: Flag Restrictions (of TPM_STANY_FLAGS)
+//
+#define TPM_AF_POSTINITIALISE ((TPM_CAPABILITY_AREA) 1)
+#define TPM_AF_LOCALITYMODIFIER ((TPM_CAPABILITY_AREA) 2)
+#define TPM_AF_TRANSPORTEXCLUSIVE ((TPM_CAPABILITY_AREA) 3)
+#define TPM_AF_TOSPRESENT ((TPM_CAPABILITY_AREA) 4)
+
+//
+// All those structures defined in section 7.4, 7.5, 7.6 are not normative and
+// thus no definitions here
+//
+// Part 2, section 7.4: TPM_PERMANENT_DATA
+//
+#define TPM_MIN_COUNTERS 4 ///< the minimum number of counters is 4
+#define TPM_DELEGATE_KEY TPM_KEY
+#define TPM_NUM_PCR 16
+#define TPM_MAX_NV_WRITE_NOOWNER 64
+
+//
+// Part 2, section 7.4.1: PERMANENT_DATA Subcap for SetCapability
+//
+#define TPM_PD_REVMAJOR ((TPM_CAPABILITY_AREA) 1)
+#define TPM_PD_REVMINOR ((TPM_CAPABILITY_AREA) 2)
+#define TPM_PD_TPMPROOF ((TPM_CAPABILITY_AREA) 3)
+#define TPM_PD_OWNERAUTH ((TPM_CAPABILITY_AREA) 4)
+#define TPM_PD_OPERATORAUTH ((TPM_CAPABILITY_AREA) 5)
+#define TPM_PD_MANUMAINTPUB ((TPM_CAPABILITY_AREA) 6)
+#define TPM_PD_ENDORSEMENTKEY ((TPM_CAPABILITY_AREA) 7)
+#define TPM_PD_SRK ((TPM_CAPABILITY_AREA) 8)
+#define TPM_PD_DELEGATEKEY ((TPM_CAPABILITY_AREA) 9)
+#define TPM_PD_CONTEXTKEY ((TPM_CAPABILITY_AREA) 10)
+#define TPM_PD_AUDITMONOTONICCOUNTER ((TPM_CAPABILITY_AREA) 11)
+#define TPM_PD_MONOTONICCOUNTER ((TPM_CAPABILITY_AREA) 12)
+#define TPM_PD_PCRATTRIB ((TPM_CAPABILITY_AREA) 13)
+#define TPM_PD_ORDINALAUDITSTATUS ((TPM_CAPABILITY_AREA) 14)
+#define TPM_PD_AUTHDIR ((TPM_CAPABILITY_AREA) 15)
+#define TPM_PD_RNGSTATE ((TPM_CAPABILITY_AREA) 16)
+#define TPM_PD_FAMILYTABLE ((TPM_CAPABILITY_AREA) 17)
+#define TPM_DELEGATETABLE ((TPM_CAPABILITY_AREA) 18)
+#define TPM_PD_EKRESET ((TPM_CAPABILITY_AREA) 19)
+#define TPM_PD_MAXNVBUFSIZE ((TPM_CAPABILITY_AREA) 20)
+#define TPM_PD_LASTFAMILYID ((TPM_CAPABILITY_AREA) 21)
+#define TPM_PD_NOOWNERNVWRITE ((TPM_CAPABILITY_AREA) 22)
+#define TPM_PD_RESTRICTDELEGATE ((TPM_CAPABILITY_AREA) 23)
+#define TPM_PD_TPMDAASEED ((TPM_CAPABILITY_AREA) 24)
+#define TPM_PD_DAAPROOF ((TPM_CAPABILITY_AREA) 25)
+
+///
+/// Part 2, section 7.5: TPM_STCLEAR_DATA
+/// available inside TPM only
+///
+typedef struct tdTPM_STCLEAR_DATA {
+ TPM_STRUCTURE_TAG tag;
+ TPM_NONCE contextNonceKey;
+ TPM_COUNT_ID countID;
+ UINT32 ownerReference;
+ BOOLEAN disableResetLock;
+ TPM_PCRVALUE PCR[TPM_NUM_PCR];
+ UINT32 deferredPhysicalPresence;
+} TPM_STCLEAR_DATA;
+
+//
+// Part 2, section 7.5.1: STCLEAR_DATA Subcap for SetCapability
+//
+#define TPM_SD_CONTEXTNONCEKEY ((TPM_CAPABILITY_AREA)0x00000001)
+#define TPM_SD_COUNTID ((TPM_CAPABILITY_AREA)0x00000002)
+#define TPM_SD_OWNERREFERENCE ((TPM_CAPABILITY_AREA)0x00000003)
+#define TPM_SD_DISABLERESETLOCK ((TPM_CAPABILITY_AREA)0x00000004)
+#define TPM_SD_PCR ((TPM_CAPABILITY_AREA)0x00000005)
+#define TPM_SD_DEFERREDPHYSICALPRESENCE ((TPM_CAPABILITY_AREA)0x00000006)
+
+//
+// Part 2, section 7.6.1: STANY_DATA Subcap for SetCapability
+//
+#define TPM_AD_CONTEXTNONCESESSION ((TPM_CAPABILITY_AREA) 1)
+#define TPM_AD_AUDITDIGEST ((TPM_CAPABILITY_AREA) 2)
+#define TPM_AD_CURRENTTICKS ((TPM_CAPABILITY_AREA) 3)
+#define TPM_AD_CONTEXTCOUNT ((TPM_CAPABILITY_AREA) 4)
+#define TPM_AD_CONTEXTLIST ((TPM_CAPABILITY_AREA) 5)
+#define TPM_AD_SESSIONS ((TPM_CAPABILITY_AREA) 6)
+
+//
+// Part 2, section 8: PCR Structures
+//
+
+///
+/// Part 2, section 8.1: TPM_PCR_SELECTION
+/// Size of pcrSelect[] indicated by sizeOfSelect
+///
+typedef struct tdTPM_PCR_SELECTION {
+ UINT16 sizeOfSelect;
+ UINT8 pcrSelect[1];
+} TPM_PCR_SELECTION;
+
+///
+/// Part 2, section 8.2: TPM_PCR_COMPOSITE
+/// Size of pcrValue[] indicated by valueSize
+///
+typedef struct tdTPM_PCR_COMPOSITE {
+ TPM_PCR_SELECTION select;
+ UINT32 valueSize;
+ TPM_PCRVALUE pcrValue[1];
+} TPM_PCR_COMPOSITE;
+
+///
+/// Part 2, section 8.3: TPM_PCR_INFO
+///
+typedef struct tdTPM_PCR_INFO {
+ TPM_PCR_SELECTION pcrSelection;
+ TPM_COMPOSITE_HASH digestAtRelease;
+ TPM_COMPOSITE_HASH digestAtCreation;
+} TPM_PCR_INFO;
+
+///
+/// Part 2, section 8.6: TPM_LOCALITY_SELECTION
+///
+typedef UINT8 TPM_LOCALITY_SELECTION;
+
+#define TPM_LOC_FOUR ((UINT8) 0x10)
+#define TPM_LOC_THREE ((UINT8) 0x08)
+#define TPM_LOC_TWO ((UINT8) 0x04)
+#define TPM_LOC_ONE ((UINT8) 0x02)
+#define TPM_LOC_ZERO ((UINT8) 0x01)
+
+///
+/// Part 2, section 8.4: TPM_PCR_INFO_LONG
+///
+typedef struct tdTPM_PCR_INFO_LONG {
+ TPM_STRUCTURE_TAG tag;
+ TPM_LOCALITY_SELECTION localityAtCreation;
+ TPM_LOCALITY_SELECTION localityAtRelease;
+ TPM_PCR_SELECTION creationPCRSelection;
+ TPM_PCR_SELECTION releasePCRSelection;
+ TPM_COMPOSITE_HASH digestAtCreation;
+ TPM_COMPOSITE_HASH digestAtRelease;
+} TPM_PCR_INFO_LONG;
+
+///
+/// Part 2, section 8.5: TPM_PCR_INFO_SHORT
+///
+typedef struct tdTPM_PCR_INFO_SHORT {
+ TPM_PCR_SELECTION pcrSelection;
+ TPM_LOCALITY_SELECTION localityAtRelease;
+ TPM_COMPOSITE_HASH digestAtRelease;
+} TPM_PCR_INFO_SHORT;
+
+///
+/// Part 2, section 8.8: TPM_PCR_ATTRIBUTES
+///
+typedef struct tdTPM_PCR_ATTRIBUTES {
+ BOOLEAN pcrReset;
+ TPM_LOCALITY_SELECTION pcrExtendLocal;
+ TPM_LOCALITY_SELECTION pcrResetLocal;
+} TPM_PCR_ATTRIBUTES;
+
+//
+// Part 2, section 9: Storage Structures
+//
+
+///
+/// Part 2, section 9.1: TPM_STORED_DATA
+/// [size_is(sealInfoSize)] BYTE* sealInfo;
+/// [size_is(encDataSize)] BYTE* encData;
+///
+typedef struct tdTPM_STORED_DATA {
+ TPM_STRUCT_VER ver;
+ UINT32 sealInfoSize;
+ UINT8 *sealInfo;
+ UINT32 encDataSize;
+ UINT8 *encData;
+} TPM_STORED_DATA;
+
+///
+/// Part 2, section 9.2: TPM_STORED_DATA12
+/// [size_is(sealInfoSize)] BYTE* sealInfo;
+/// [size_is(encDataSize)] BYTE* encData;
+///
+typedef struct tdTPM_STORED_DATA12 {
+ TPM_STRUCTURE_TAG tag;
+ TPM_ENTITY_TYPE et;
+ UINT32 sealInfoSize;
+ UINT8 *sealInfo;
+ UINT32 encDataSize;
+ UINT8 *encData;
+} TPM_STORED_DATA12;
+
+///
+/// Part 2, section 9.3: TPM_SEALED_DATA
+/// [size_is(dataSize)] BYTE* data;
+///
+typedef struct tdTPM_SEALED_DATA {
+ TPM_PAYLOAD_TYPE payload;
+ TPM_SECRET authData;
+ TPM_NONCE tpmProof;
+ TPM_DIGEST storedDigest;
+ UINT32 dataSize;
+ UINT8 *data;
+} TPM_SEALED_DATA;
+
+///
+/// Part 2, section 9.4: TPM_SYMMETRIC_KEY
+/// [size_is(size)] BYTE* data;
+///
+typedef struct tdTPM_SYMMETRIC_KEY {
+ TPM_ALGORITHM_ID algId;
+ TPM_ENC_SCHEME encScheme;
+ UINT16 dataSize;
+ UINT8 *data;
+} TPM_SYMMETRIC_KEY;
+
+///
+/// Part 2, section 9.5: TPM_BOUND_DATA
+///
+typedef struct tdTPM_BOUND_DATA {
+ TPM_STRUCT_VER ver;
+ TPM_PAYLOAD_TYPE payload;
+ UINT8 payloadData[1];
+} TPM_BOUND_DATA;
+
+//
+// Part 2 section 10: TPM_KEY complex
+//
+
+//
+// Section 10.1, 10.4, and 10.5 have been defined previously
+//
+
+///
+/// Part 2, section 10.2: TPM_KEY
+/// [size_is(encDataSize)] BYTE* encData;
+///
+typedef struct tdTPM_KEY {
+ TPM_STRUCT_VER ver;
+ TPM_KEY_USAGE keyUsage;
+ TPM_KEY_FLAGS keyFlags;
+ TPM_AUTH_DATA_USAGE authDataUsage;
+ TPM_KEY_PARMS algorithmParms;
+ UINT32 PCRInfoSize;
+ UINT8 *PCRInfo;
+ TPM_STORE_PUBKEY pubKey;
+ UINT32 encDataSize;
+ UINT8 *encData;
+} TPM_KEY;
+
+///
+/// Part 2, section 10.3: TPM_KEY12
+/// [size_is(encDataSize)] BYTE* encData;
+///
+typedef struct tdTPM_KEY12 {
+ TPM_STRUCTURE_TAG tag;
+ UINT16 fill;
+ TPM_KEY_USAGE keyUsage;
+ TPM_KEY_FLAGS keyFlags;
+ TPM_AUTH_DATA_USAGE authDataUsage;
+ TPM_KEY_PARMS algorithmParms;
+ UINT32 PCRInfoSize;
+ UINT8 *PCRInfo;
+ TPM_STORE_PUBKEY pubKey;
+ UINT32 encDataSize;
+ UINT8 *encData;
+} TPM_KEY12;
+
+///
+/// Part 2, section 10.7: TPM_STORE_PRIVKEY
+/// [size_is(keyLength)] BYTE* key;
+///
+typedef struct tdTPM_STORE_PRIVKEY {
+ UINT32 keyLength;
+ UINT8 *key;
+} TPM_STORE_PRIVKEY;
+
+///
+/// Part 2, section 10.6: TPM_STORE_ASYMKEY
+///
+typedef struct tdTPM_STORE_ASYMKEY {
+ // pos len total
+ TPM_PAYLOAD_TYPE payload; // 0 1 1
+ TPM_SECRET usageAuth; // 1 20 21
+ TPM_SECRET migrationAuth; // 21 20 41
+ TPM_DIGEST pubDataDigest; // 41 20 61
+ TPM_STORE_PRIVKEY privKey; // 61 132-151 193-214
+} TPM_STORE_ASYMKEY;
+
+///
+/// Part 2, section 10.8: TPM_MIGRATE_ASYMKEY
+/// [size_is(partPrivKeyLen)] BYTE* partPrivKey;
+///
+typedef struct tdTPM_MIGRATE_ASYMKEY {
+ // pos len total
+ TPM_PAYLOAD_TYPE payload; // 0 1 1
+ TPM_SECRET usageAuth; // 1 20 21
+ TPM_DIGEST pubDataDigest; // 21 20 41
+ UINT32 partPrivKeyLen; // 41 4 45
+ UINT8 *partPrivKey; // 45 112-127 157-172
+} TPM_MIGRATE_ASYMKEY;
+
+///
+/// Part 2, section 10.9: TPM_KEY_CONTROL
+///
+#define TPM_KEY_CONTROL_OWNER_EVICT ((UINT32) 0x00000001)
+
+//
+// Part 2, section 11: Signed Structures
+//
+
+///
+/// Part 2, section 11.1: TPM_CERTIFY_INFO Structure
+///
+typedef struct tdTPM_CERTIFY_INFO {
+ TPM_STRUCT_VER version;
+ TPM_KEY_USAGE keyUsage;
+ TPM_KEY_FLAGS keyFlags;
+ TPM_AUTH_DATA_USAGE authDataUsage;
+ TPM_KEY_PARMS algorithmParms;
+ TPM_DIGEST pubkeyDigest;
+ TPM_NONCE data;
+ BOOLEAN parentPCRStatus;
+ UINT32 PCRInfoSize;
+ UINT8 *PCRInfo;
+} TPM_CERTIFY_INFO;
+
+///
+/// Part 2, section 11.2: TPM_CERTIFY_INFO2 Structure
+///
+typedef struct tdTPM_CERTIFY_INFO2 {
+ TPM_STRUCTURE_TAG tag;
+ UINT8 fill;
+ TPM_PAYLOAD_TYPE payloadType;
+ TPM_KEY_USAGE keyUsage;
+ TPM_KEY_FLAGS keyFlags;
+ TPM_AUTH_DATA_USAGE authDataUsage;
+ TPM_KEY_PARMS algorithmParms;
+ TPM_DIGEST pubkeyDigest;
+ TPM_NONCE data;
+ BOOLEAN parentPCRStatus;
+ UINT32 PCRInfoSize;
+ UINT8 *PCRInfo;
+ UINT32 migrationAuthoritySize;
+ UINT8 *migrationAuthority;
+} TPM_CERTIFY_INFO2;
+
+///
+/// Part 2, section 11.3 TPM_QUOTE_INFO Structure
+///
+typedef struct tdTPM_QUOTE_INFO {
+ TPM_STRUCT_VER version;
+ UINT8 fixed[4];
+ TPM_COMPOSITE_HASH digestValue;
+ TPM_NONCE externalData;
+} TPM_QUOTE_INFO;
+
+///
+/// Part 2, section 11.4 TPM_QUOTE_INFO2 Structure
+///
+typedef struct tdTPM_QUOTE_INFO2 {
+ TPM_STRUCTURE_TAG tag;
+ UINT8 fixed[4];
+ TPM_NONCE externalData;
+ TPM_PCR_INFO_SHORT infoShort;
+} TPM_QUOTE_INFO2;
+
+//
+// Part 2, section 12: Identity Structures
+//
+
+///
+/// Part 2, section 12.1 TPM_EK_BLOB
+///
+typedef struct tdTPM_EK_BLOB {
+ TPM_STRUCTURE_TAG tag;
+ TPM_EK_TYPE ekType;
+ UINT32 blobSize;
+ UINT8 *blob;
+} TPM_EK_BLOB;
+
+///
+/// Part 2, section 12.2 TPM_EK_BLOB_ACTIVATE
+///
+typedef struct tdTPM_EK_BLOB_ACTIVATE {
+ TPM_STRUCTURE_TAG tag;
+ TPM_SYMMETRIC_KEY sessionKey;
+ TPM_DIGEST idDigest;
+ TPM_PCR_INFO_SHORT pcrInfo;
+} TPM_EK_BLOB_ACTIVATE;
+
+///
+/// Part 2, section 12.3 TPM_EK_BLOB_AUTH
+///
+typedef struct tdTPM_EK_BLOB_AUTH {
+ TPM_STRUCTURE_TAG tag;
+ TPM_SECRET authValue;
+} TPM_EK_BLOB_AUTH;
+
+///
+/// Part 2, section 12.5 TPM_IDENTITY_CONTENTS
+///
+typedef struct tdTPM_IDENTITY_CONTENTS {
+ TPM_STRUCT_VER ver;
+ UINT32 ordinal;
+ TPM_CHOSENID_HASH labelPrivCADigest;
+ TPM_PUBKEY identityPubKey;
+} TPM_IDENTITY_CONTENTS;
+
+///
+/// Part 2, section 12.6 TPM_IDENTITY_REQ
+///
+typedef struct tdTPM_IDENTITY_REQ {
+ UINT32 asymSize;
+ UINT32 symSize;
+ TPM_KEY_PARMS asymAlgorithm;
+ TPM_KEY_PARMS symAlgorithm;
+ UINT8 *asymBlob;
+ UINT8 *symBlob;
+} TPM_IDENTITY_REQ;
+
+///
+/// Part 2, section 12.7 TPM_IDENTITY_PROOF
+///
+typedef struct tdTPM_IDENTITY_PROOF {
+ TPM_STRUCT_VER ver;
+ UINT32 labelSize;
+ UINT32 identityBindingSize;
+ UINT32 endorsementSize;
+ UINT32 platformSize;
+ UINT32 conformanceSize;
+ TPM_PUBKEY identityKey;
+ UINT8 *labelArea;
+ UINT8 *identityBinding;
+ UINT8 *endorsementCredential;
+ UINT8 *platformCredential;
+ UINT8 *conformanceCredential;
+} TPM_IDENTITY_PROOF;
+
+///
+/// Part 2, section 12.8 TPM_ASYM_CA_CONTENTS
+///
+typedef struct tdTPM_ASYM_CA_CONTENTS {
+ TPM_SYMMETRIC_KEY sessionKey;
+ TPM_DIGEST idDigest;
+} TPM_ASYM_CA_CONTENTS;
+
+///
+/// Part 2, section 12.9 TPM_SYM_CA_ATTESTATION
+///
+typedef struct tdTPM_SYM_CA_ATTESTATION {
+ UINT32 credSize;
+ TPM_KEY_PARMS algorithm;
+ UINT8 *credential;
+} TPM_SYM_CA_ATTESTATION;
+
+///
+/// Part 2, section 15: Tick Structures
+/// Placed here out of order because definitions are used in section 13.
+///
+typedef struct tdTPM_CURRENT_TICKS {
+ TPM_STRUCTURE_TAG tag;
+ UINT64 currentTicks;
+ UINT16 tickRate;
+ TPM_NONCE tickNonce;
+} TPM_CURRENT_TICKS;
+
+///
+/// Part 2, section 13: Transport structures
+///
+
+///
+/// Part 2, section 13.1: TPM _TRANSPORT_PUBLIC
+///
+typedef struct tdTPM_TRANSPORT_PUBLIC {
+ TPM_STRUCTURE_TAG tag;
+ TPM_TRANSPORT_ATTRIBUTES transAttributes;
+ TPM_ALGORITHM_ID algId;
+ TPM_ENC_SCHEME encScheme;
+} TPM_TRANSPORT_PUBLIC;
+
+//
+// Part 2, section 13.1.1 TPM_TRANSPORT_ATTRIBUTES Definitions
+//
+#define TPM_TRANSPORT_ENCRYPT ((UINT32)BIT0)
+#define TPM_TRANSPORT_LOG ((UINT32)BIT1)
+#define TPM_TRANSPORT_EXCLUSIVE ((UINT32)BIT2)
+
+///
+/// Part 2, section 13.2 TPM_TRANSPORT_INTERNAL
+///
+typedef struct tdTPM_TRANSPORT_INTERNAL {
+ TPM_STRUCTURE_TAG tag;
+ TPM_AUTHDATA authData;
+ TPM_TRANSPORT_PUBLIC transPublic;
+ TPM_TRANSHANDLE transHandle;
+ TPM_NONCE transNonceEven;
+ TPM_DIGEST transDigest;
+} TPM_TRANSPORT_INTERNAL;
+
+///
+/// Part 2, section 13.3 TPM_TRANSPORT_LOG_IN structure
+///
+typedef struct tdTPM_TRANSPORT_LOG_IN {
+ TPM_STRUCTURE_TAG tag;
+ TPM_DIGEST parameters;
+ TPM_DIGEST pubKeyHash;
+} TPM_TRANSPORT_LOG_IN;
+
+///
+/// Part 2, section 13.4 TPM_TRANSPORT_LOG_OUT structure
+///
+typedef struct tdTPM_TRANSPORT_LOG_OUT {
+ TPM_STRUCTURE_TAG tag;
+ TPM_CURRENT_TICKS currentTicks;
+ TPM_DIGEST parameters;
+ TPM_MODIFIER_INDICATOR locality;
+} TPM_TRANSPORT_LOG_OUT;
+
+///
+/// Part 2, section 13.5 TPM_TRANSPORT_AUTH structure
+///
+typedef struct tdTPM_TRANSPORT_AUTH {
+ TPM_STRUCTURE_TAG tag;
+ TPM_AUTHDATA authData;
+} TPM_TRANSPORT_AUTH;
+
+//
+// Part 2, section 14: Audit Structures
+//
+
+///
+/// Part 2, section 14.1 TPM_AUDIT_EVENT_IN structure
+///
+typedef struct tdTPM_AUDIT_EVENT_IN {
+ TPM_STRUCTURE_TAG tag;
+ TPM_DIGEST inputParms;
+ TPM_COUNTER_VALUE auditCount;
+} TPM_AUDIT_EVENT_IN;
+
+///
+/// Part 2, section 14.2 TPM_AUDIT_EVENT_OUT structure
+///
+typedef struct tdTPM_AUDIT_EVENT_OUT {
+ TPM_STRUCTURE_TAG tag;
+ TPM_COMMAND_CODE ordinal;
+ TPM_DIGEST outputParms;
+ TPM_COUNTER_VALUE auditCount;
+ TPM_RESULT returnCode;
+} TPM_AUDIT_EVENT_OUT;
+
+//
+// Part 2, section 16: Return Codes
+//
+
+#define TPM_VENDOR_ERROR TPM_Vendor_Specific32
+#define TPM_NON_FATAL 0x00000800
+
+#define TPM_SUCCESS ((TPM_RESULT) TPM_BASE)
+#define TPM_AUTHFAIL ((TPM_RESULT) (TPM_BASE + 1))
+#define TPM_BADINDEX ((TPM_RESULT) (TPM_BASE + 2))
+#define TPM_BAD_PARAMETER ((TPM_RESULT) (TPM_BASE + 3))
+#define TPM_AUDITFAILURE ((TPM_RESULT) (TPM_BASE + 4))
+#define TPM_CLEAR_DISABLED ((TPM_RESULT) (TPM_BASE + 5))
+#define TPM_DEACTIVATED ((TPM_RESULT) (TPM_BASE + 6))
+#define TPM_DISABLED ((TPM_RESULT) (TPM_BASE + 7))
+#define TPM_DISABLED_CMD ((TPM_RESULT) (TPM_BASE + 8))
+#define TPM_FAIL ((TPM_RESULT) (TPM_BASE + 9))
+#define TPM_BAD_ORDINAL ((TPM_RESULT) (TPM_BASE + 10))
+#define TPM_INSTALL_DISABLED ((TPM_RESULT) (TPM_BASE + 11))
+#define TPM_INVALID_KEYHANDLE ((TPM_RESULT) (TPM_BASE + 12))
+#define TPM_KEYNOTFOUND ((TPM_RESULT) (TPM_BASE + 13))
+#define TPM_INAPPROPRIATE_ENC ((TPM_RESULT) (TPM_BASE + 14))
+#define TPM_MIGRATEFAIL ((TPM_RESULT) (TPM_BASE + 15))
+#define TPM_INVALID_PCR_INFO ((TPM_RESULT) (TPM_BASE + 16))
+#define TPM_NOSPACE ((TPM_RESULT) (TPM_BASE + 17))
+#define TPM_NOSRK ((TPM_RESULT) (TPM_BASE + 18))
+#define TPM_NOTSEALED_BLOB ((TPM_RESULT) (TPM_BASE + 19))
+#define TPM_OWNER_SET ((TPM_RESULT) (TPM_BASE + 20))
+#define TPM_RESOURCES ((TPM_RESULT) (TPM_BASE + 21))
+#define TPM_SHORTRANDOM ((TPM_RESULT) (TPM_BASE + 22))
+#define TPM_SIZE ((TPM_RESULT) (TPM_BASE + 23))
+#define TPM_WRONGPCRVAL ((TPM_RESULT) (TPM_BASE + 24))
+#define TPM_BAD_PARAM_SIZE ((TPM_RESULT) (TPM_BASE + 25))
+#define TPM_SHA_THREAD ((TPM_RESULT) (TPM_BASE + 26))
+#define TPM_SHA_ERROR ((TPM_RESULT) (TPM_BASE + 27))
+#define TPM_FAILEDSELFTEST ((TPM_RESULT) (TPM_BASE + 28))
+#define TPM_AUTH2FAIL ((TPM_RESULT) (TPM_BASE + 29))
+#define TPM_BADTAG ((TPM_RESULT) (TPM_BASE + 30))
+#define TPM_IOERROR ((TPM_RESULT) (TPM_BASE + 31))
+#define TPM_ENCRYPT_ERROR ((TPM_RESULT) (TPM_BASE + 32))
+#define TPM_DECRYPT_ERROR ((TPM_RESULT) (TPM_BASE + 33))
+#define TPM_INVALID_AUTHHANDLE ((TPM_RESULT) (TPM_BASE + 34))
+#define TPM_NO_ENDORSEMENT ((TPM_RESULT) (TPM_BASE + 35))
+#define TPM_INVALID_KEYUSAGE ((TPM_RESULT) (TPM_BASE + 36))
+#define TPM_WRONG_ENTITYTYPE ((TPM_RESULT) (TPM_BASE + 37))
+#define TPM_INVALID_POSTINIT ((TPM_RESULT) (TPM_BASE + 38))
+#define TPM_INAPPROPRIATE_SIG ((TPM_RESULT) (TPM_BASE + 39))
+#define TPM_BAD_KEY_PROPERTY ((TPM_RESULT) (TPM_BASE + 40))
+#define TPM_BAD_MIGRATION ((TPM_RESULT) (TPM_BASE + 41))
+#define TPM_BAD_SCHEME ((TPM_RESULT) (TPM_BASE + 42))
+#define TPM_BAD_DATASIZE ((TPM_RESULT) (TPM_BASE + 43))
+#define TPM_BAD_MODE ((TPM_RESULT) (TPM_BASE + 44))
+#define TPM_BAD_PRESENCE ((TPM_RESULT) (TPM_BASE + 45))
+#define TPM_BAD_VERSION ((TPM_RESULT) (TPM_BASE + 46))
+#define TPM_NO_WRAP_TRANSPORT ((TPM_RESULT) (TPM_BASE + 47))
+#define TPM_AUDITFAIL_UNSUCCESSFUL ((TPM_RESULT) (TPM_BASE + 48))
+#define TPM_AUDITFAIL_SUCCESSFUL ((TPM_RESULT) (TPM_BASE + 49))
+#define TPM_NOTRESETABLE ((TPM_RESULT) (TPM_BASE + 50))
+#define TPM_NOTLOCAL ((TPM_RESULT) (TPM_BASE + 51))
+#define TPM_BAD_TYPE ((TPM_RESULT) (TPM_BASE + 52))
+#define TPM_INVALID_RESOURCE ((TPM_RESULT) (TPM_BASE + 53))
+#define TPM_NOTFIPS ((TPM_RESULT) (TPM_BASE + 54))
+#define TPM_INVALID_FAMILY ((TPM_RESULT) (TPM_BASE + 55))
+#define TPM_NO_NV_PERMISSION ((TPM_RESULT) (TPM_BASE + 56))
+#define TPM_REQUIRES_SIGN ((TPM_RESULT) (TPM_BASE + 57))
+#define TPM_KEY_NOTSUPPORTED ((TPM_RESULT) (TPM_BASE + 58))
+#define TPM_AUTH_CONFLICT ((TPM_RESULT) (TPM_BASE + 59))
+#define TPM_AREA_LOCKED ((TPM_RESULT) (TPM_BASE + 60))
+#define TPM_BAD_LOCALITY ((TPM_RESULT) (TPM_BASE + 61))
+#define TPM_READ_ONLY ((TPM_RESULT) (TPM_BASE + 62))
+#define TPM_PER_NOWRITE ((TPM_RESULT) (TPM_BASE + 63))
+#define TPM_FAMILYCOUNT ((TPM_RESULT) (TPM_BASE + 64))
+#define TPM_WRITE_LOCKED ((TPM_RESULT) (TPM_BASE + 65))
+#define TPM_BAD_ATTRIBUTES ((TPM_RESULT) (TPM_BASE + 66))
+#define TPM_INVALID_STRUCTURE ((TPM_RESULT) (TPM_BASE + 67))
+#define TPM_KEY_OWNER_CONTROL ((TPM_RESULT) (TPM_BASE + 68))
+#define TPM_BAD_COUNTER ((TPM_RESULT) (TPM_BASE + 69))
+#define TPM_NOT_FULLWRITE ((TPM_RESULT) (TPM_BASE + 70))
+#define TPM_CONTEXT_GAP ((TPM_RESULT) (TPM_BASE + 71))
+#define TPM_MAXNVWRITES ((TPM_RESULT) (TPM_BASE + 72))
+#define TPM_NOOPERATOR ((TPM_RESULT) (TPM_BASE + 73))
+#define TPM_RESOURCEMISSING ((TPM_RESULT) (TPM_BASE + 74))
+#define TPM_DELEGATE_LOCK ((TPM_RESULT) (TPM_BASE + 75))
+#define TPM_DELEGATE_FAMILY ((TPM_RESULT) (TPM_BASE + 76))
+#define TPM_DELEGATE_ADMIN ((TPM_RESULT) (TPM_BASE + 77))
+#define TPM_TRANSPORT_NOTEXCLUSIVE ((TPM_RESULT) (TPM_BASE + 78))
+#define TPM_OWNER_CONTROL ((TPM_RESULT) (TPM_BASE + 79))
+#define TPM_DAA_RESOURCES ((TPM_RESULT) (TPM_BASE + 80))
+#define TPM_DAA_INPUT_DATA0 ((TPM_RESULT) (TPM_BASE + 81))
+#define TPM_DAA_INPUT_DATA1 ((TPM_RESULT) (TPM_BASE + 82))
+#define TPM_DAA_ISSUER_SETTINGS ((TPM_RESULT) (TPM_BASE + 83))
+#define TPM_DAA_TPM_SETTINGS ((TPM_RESULT) (TPM_BASE + 84))
+#define TPM_DAA_STAGE ((TPM_RESULT) (TPM_BASE + 85))
+#define TPM_DAA_ISSUER_VALIDITY ((TPM_RESULT) (TPM_BASE + 86))
+#define TPM_DAA_WRONG_W ((TPM_RESULT) (TPM_BASE + 87))
+#define TPM_BAD_HANDLE ((TPM_RESULT) (TPM_BASE + 88))
+#define TPM_BAD_DELEGATE ((TPM_RESULT) (TPM_BASE + 89))
+#define TPM_BADCONTEXT ((TPM_RESULT) (TPM_BASE + 90))
+#define TPM_TOOMANYCONTEXTS ((TPM_RESULT) (TPM_BASE + 91))
+#define TPM_MA_TICKET_SIGNATURE ((TPM_RESULT) (TPM_BASE + 92))
+#define TPM_MA_DESTINATION ((TPM_RESULT) (TPM_BASE + 93))
+#define TPM_MA_SOURCE ((TPM_RESULT) (TPM_BASE + 94))
+#define TPM_MA_AUTHORITY ((TPM_RESULT) (TPM_BASE + 95))
+#define TPM_PERMANENTEK ((TPM_RESULT) (TPM_BASE + 97))
+#define TPM_BAD_SIGNATURE ((TPM_RESULT) (TPM_BASE + 98))
+#define TPM_NOCONTEXTSPACE ((TPM_RESULT) (TPM_BASE + 99))
+
+#define TPM_RETRY ((TPM_RESULT) (TPM_BASE + TPM_NON_FATAL))
+#define TPM_NEEDS_SELFTEST ((TPM_RESULT) (TPM_BASE + TPM_NON_FATAL + 1))
+#define TPM_DOING_SELFTEST ((TPM_RESULT) (TPM_BASE + TPM_NON_FATAL + 2))
+#define TPM_DEFEND_LOCK_RUNNING ((TPM_RESULT) (TPM_BASE + TPM_NON_FATAL + 3))
+
+//
+// Part 2, section 17: Ordinals
+//
+// Ordinals are 32 bit values. The upper byte contains values that serve as
+// flag indicators, the next byte contains values indicating what committee
+// designated the ordinal, and the final two bytes contain the Command
+// Ordinal Index.
+// 3 2 1
+// 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+// +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+// |P|C|V| Reserved| Purview | Command Ordinal Index |
+// +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+//
+// Where:
+//
+// * P is Protected/Unprotected command. When 0 the command is a Protected
+// command, when 1 the command is an Unprotected command.
+//
+// * C is Non-Connection/Connection related command. When 0 this command
+// passes through to either the protected (TPM) or unprotected (TSS)
+// components.
+//
+// * V is TPM/Vendor command. When 0 the command is TPM defined, when 1 the
+// command is vendor defined.
+//
+// * All reserved area bits are set to 0.
+//
+
+#define TPM_ORD_ActivateIdentity ((TPM_COMMAND_CODE) 0x0000007A)
+#define TPM_ORD_AuthorizeMigrationKey ((TPM_COMMAND_CODE) 0x0000002B)
+#define TPM_ORD_CertifyKey ((TPM_COMMAND_CODE) 0x00000032)
+#define TPM_ORD_CertifyKey2 ((TPM_COMMAND_CODE) 0x00000033)
+#define TPM_ORD_CertifySelfTest ((TPM_COMMAND_CODE) 0x00000052)
+#define TPM_ORD_ChangeAuth ((TPM_COMMAND_CODE) 0x0000000C)
+#define TPM_ORD_ChangeAuthAsymFinish ((TPM_COMMAND_CODE) 0x0000000F)
+#define TPM_ORD_ChangeAuthAsymStart ((TPM_COMMAND_CODE) 0x0000000E)
+#define TPM_ORD_ChangeAuthOwner ((TPM_COMMAND_CODE) 0x00000010)
+#define TPM_ORD_CMK_ApproveMA ((TPM_COMMAND_CODE) 0x0000001D)
+#define TPM_ORD_CMK_ConvertMigration ((TPM_COMMAND_CODE) 0x00000024)
+#define TPM_ORD_CMK_CreateBlob ((TPM_COMMAND_CODE) 0x0000001B)
+#define TPM_ORD_CMK_CreateKey ((TPM_COMMAND_CODE) 0x00000013)
+#define TPM_ORD_CMK_CreateTicket ((TPM_COMMAND_CODE) 0x00000012)
+#define TPM_ORD_CMK_SetRestrictions ((TPM_COMMAND_CODE) 0x0000001C)
+#define TPM_ORD_ContinueSelfTest ((TPM_COMMAND_CODE) 0x00000053)
+#define TPM_ORD_ConvertMigrationBlob ((TPM_COMMAND_CODE) 0x0000002A)
+#define TPM_ORD_CreateCounter ((TPM_COMMAND_CODE) 0x000000DC)
+#define TPM_ORD_CreateEndorsementKeyPair ((TPM_COMMAND_CODE) 0x00000078)
+#define TPM_ORD_CreateMaintenanceArchive ((TPM_COMMAND_CODE) 0x0000002C)
+#define TPM_ORD_CreateMigrationBlob ((TPM_COMMAND_CODE) 0x00000028)
+#define TPM_ORD_CreateRevocableEK ((TPM_COMMAND_CODE) 0x0000007F)
+#define TPM_ORD_CreateWrapKey ((TPM_COMMAND_CODE) 0x0000001F)
+#define TPM_ORD_DAA_JOIN ((TPM_COMMAND_CODE) 0x00000029)
+#define TPM_ORD_DAA_SIGN ((TPM_COMMAND_CODE) 0x00000031)
+#define TPM_ORD_Delegate_CreateKeyDelegation ((TPM_COMMAND_CODE) 0x000000D4)
+#define TPM_ORD_Delegate_CreateOwnerDelegation ((TPM_COMMAND_CODE) 0x000000D5)
+#define TPM_ORD_Delegate_LoadOwnerDelegation ((TPM_COMMAND_CODE) 0x000000D8)
+#define TPM_ORD_Delegate_Manage ((TPM_COMMAND_CODE) 0x000000D2)
+#define TPM_ORD_Delegate_ReadTable ((TPM_COMMAND_CODE) 0x000000DB)
+#define TPM_ORD_Delegate_UpdateVerification ((TPM_COMMAND_CODE) 0x000000D1)
+#define TPM_ORD_Delegate_VerifyDelegation ((TPM_COMMAND_CODE) 0x000000D6)
+#define TPM_ORD_DirRead ((TPM_COMMAND_CODE) 0x0000001A)
+#define TPM_ORD_DirWriteAuth ((TPM_COMMAND_CODE) 0x00000019)
+#define TPM_ORD_DisableForceClear ((TPM_COMMAND_CODE) 0x0000005E)
+#define TPM_ORD_DisableOwnerClear ((TPM_COMMAND_CODE) 0x0000005C)
+#define TPM_ORD_DisablePubekRead ((TPM_COMMAND_CODE) 0x0000007E)
+#define TPM_ORD_DSAP ((TPM_COMMAND_CODE) 0x00000011)
+#define TPM_ORD_EstablishTransport ((TPM_COMMAND_CODE) 0x000000E6)
+#define TPM_ORD_EvictKey ((TPM_COMMAND_CODE) 0x00000022)
+#define TPM_ORD_ExecuteTransport ((TPM_COMMAND_CODE) 0x000000E7)
+#define TPM_ORD_Extend ((TPM_COMMAND_CODE) 0x00000014)
+#define TPM_ORD_FieldUpgrade ((TPM_COMMAND_CODE) 0x000000AA)
+#define TPM_ORD_FlushSpecific ((TPM_COMMAND_CODE) 0x000000BA)
+#define TPM_ORD_ForceClear ((TPM_COMMAND_CODE) 0x0000005D)
+#define TPM_ORD_GetAuditDigest ((TPM_COMMAND_CODE) 0x00000085)
+#define TPM_ORD_GetAuditDigestSigned ((TPM_COMMAND_CODE) 0x00000086)
+#define TPM_ORD_GetAuditEvent ((TPM_COMMAND_CODE) 0x00000082)
+#define TPM_ORD_GetAuditEventSigned ((TPM_COMMAND_CODE) 0x00000083)
+#define TPM_ORD_GetCapability ((TPM_COMMAND_CODE) 0x00000065)
+#define TPM_ORD_GetCapabilityOwner ((TPM_COMMAND_CODE) 0x00000066)
+#define TPM_ORD_GetCapabilitySigned ((TPM_COMMAND_CODE) 0x00000064)
+#define TPM_ORD_GetOrdinalAuditStatus ((TPM_COMMAND_CODE) 0x0000008C)
+#define TPM_ORD_GetPubKey ((TPM_COMMAND_CODE) 0x00000021)
+#define TPM_ORD_GetRandom ((TPM_COMMAND_CODE) 0x00000046)
+#define TPM_ORD_GetTestResult ((TPM_COMMAND_CODE) 0x00000054)
+#define TPM_ORD_GetTicks ((TPM_COMMAND_CODE) 0x000000F1)
+#define TPM_ORD_IncrementCounter ((TPM_COMMAND_CODE) 0x000000DD)
+#define TPM_ORD_Init ((TPM_COMMAND_CODE) 0x00000097)
+#define TPM_ORD_KeyControlOwner ((TPM_COMMAND_CODE) 0x00000023)
+#define TPM_ORD_KillMaintenanceFeature ((TPM_COMMAND_CODE) 0x0000002E)
+#define TPM_ORD_LoadAuthContext ((TPM_COMMAND_CODE) 0x000000B7)
+#define TPM_ORD_LoadContext ((TPM_COMMAND_CODE) 0x000000B9)
+#define TPM_ORD_LoadKey ((TPM_COMMAND_CODE) 0x00000020)
+#define TPM_ORD_LoadKey2 ((TPM_COMMAND_CODE) 0x00000041)
+#define TPM_ORD_LoadKeyContext ((TPM_COMMAND_CODE) 0x000000B5)
+#define TPM_ORD_LoadMaintenanceArchive ((TPM_COMMAND_CODE) 0x0000002D)
+#define TPM_ORD_LoadManuMaintPub ((TPM_COMMAND_CODE) 0x0000002F)
+#define TPM_ORD_MakeIdentity ((TPM_COMMAND_CODE) 0x00000079)
+#define TPM_ORD_MigrateKey ((TPM_COMMAND_CODE) 0x00000025)
+#define TPM_ORD_NV_DefineSpace ((TPM_COMMAND_CODE) 0x000000CC)
+#define TPM_ORD_NV_ReadValue ((TPM_COMMAND_CODE) 0x000000CF)
+#define TPM_ORD_NV_ReadValueAuth ((TPM_COMMAND_CODE) 0x000000D0)
+#define TPM_ORD_NV_WriteValue ((TPM_COMMAND_CODE) 0x000000CD)
+#define TPM_ORD_NV_WriteValueAuth ((TPM_COMMAND_CODE) 0x000000CE)
+#define TPM_ORD_OIAP ((TPM_COMMAND_CODE) 0x0000000A)
+#define TPM_ORD_OSAP ((TPM_COMMAND_CODE) 0x0000000B)
+#define TPM_ORD_OwnerClear ((TPM_COMMAND_CODE) 0x0000005B)
+#define TPM_ORD_OwnerReadInternalPub ((TPM_COMMAND_CODE) 0x00000081)
+#define TPM_ORD_OwnerReadPubek ((TPM_COMMAND_CODE) 0x0000007D)
+#define TPM_ORD_OwnerSetDisable ((TPM_COMMAND_CODE) 0x0000006E)
+#define TPM_ORD_PCR_Reset ((TPM_COMMAND_CODE) 0x000000C8)
+#define TPM_ORD_PcrRead ((TPM_COMMAND_CODE) 0x00000015)
+#define TPM_ORD_PhysicalDisable ((TPM_COMMAND_CODE) 0x00000070)
+#define TPM_ORD_PhysicalEnable ((TPM_COMMAND_CODE) 0x0000006F)
+#define TPM_ORD_PhysicalSetDeactivated ((TPM_COMMAND_CODE) 0x00000072)
+#define TPM_ORD_Quote ((TPM_COMMAND_CODE) 0x00000016)
+#define TPM_ORD_Quote2 ((TPM_COMMAND_CODE) 0x0000003E)
+#define TPM_ORD_ReadCounter ((TPM_COMMAND_CODE) 0x000000DE)
+#define TPM_ORD_ReadManuMaintPub ((TPM_COMMAND_CODE) 0x00000030)
+#define TPM_ORD_ReadPubek ((TPM_COMMAND_CODE) 0x0000007C)
+#define TPM_ORD_ReleaseCounter ((TPM_COMMAND_CODE) 0x000000DF)
+#define TPM_ORD_ReleaseCounterOwner ((TPM_COMMAND_CODE) 0x000000E0)
+#define TPM_ORD_ReleaseTransportSigned ((TPM_COMMAND_CODE) 0x000000E8)
+#define TPM_ORD_Reset ((TPM_COMMAND_CODE) 0x0000005A)
+#define TPM_ORD_ResetLockValue ((TPM_COMMAND_CODE) 0x00000040)
+#define TPM_ORD_RevokeTrust ((TPM_COMMAND_CODE) 0x00000080)
+#define TPM_ORD_SaveAuthContext ((TPM_COMMAND_CODE) 0x000000B6)
+#define TPM_ORD_SaveContext ((TPM_COMMAND_CODE) 0x000000B8)
+#define TPM_ORD_SaveKeyContext ((TPM_COMMAND_CODE) 0x000000B4)
+#define TPM_ORD_SaveState ((TPM_COMMAND_CODE) 0x00000098)
+#define TPM_ORD_Seal ((TPM_COMMAND_CODE) 0x00000017)
+#define TPM_ORD_Sealx ((TPM_COMMAND_CODE) 0x0000003D)
+#define TPM_ORD_SelfTestFull ((TPM_COMMAND_CODE) 0x00000050)
+#define TPM_ORD_SetCapability ((TPM_COMMAND_CODE) 0x0000003F)
+#define TPM_ORD_SetOperatorAuth ((TPM_COMMAND_CODE) 0x00000074)
+#define TPM_ORD_SetOrdinalAuditStatus ((TPM_COMMAND_CODE) 0x0000008D)
+#define TPM_ORD_SetOwnerInstall ((TPM_COMMAND_CODE) 0x00000071)
+#define TPM_ORD_SetOwnerPointer ((TPM_COMMAND_CODE) 0x00000075)
+#define TPM_ORD_SetRedirection ((TPM_COMMAND_CODE) 0x0000009A)
+#define TPM_ORD_SetTempDeactivated ((TPM_COMMAND_CODE) 0x00000073)
+#define TPM_ORD_SHA1Complete ((TPM_COMMAND_CODE) 0x000000A2)
+#define TPM_ORD_SHA1CompleteExtend ((TPM_COMMAND_CODE) 0x000000A3)
+#define TPM_ORD_SHA1Start ((TPM_COMMAND_CODE) 0x000000A0)
+#define TPM_ORD_SHA1Update ((TPM_COMMAND_CODE) 0x000000A1)
+#define TPM_ORD_Sign ((TPM_COMMAND_CODE) 0x0000003C)
+#define TPM_ORD_Startup ((TPM_COMMAND_CODE) 0x00000099)
+#define TPM_ORD_StirRandom ((TPM_COMMAND_CODE) 0x00000047)
+#define TPM_ORD_TakeOwnership ((TPM_COMMAND_CODE) 0x0000000D)
+#define TPM_ORD_Terminate_Handle ((TPM_COMMAND_CODE) 0x00000096)
+#define TPM_ORD_TickStampBlob ((TPM_COMMAND_CODE) 0x000000F2)
+#define TPM_ORD_UnBind ((TPM_COMMAND_CODE) 0x0000001E)
+#define TPM_ORD_Unseal ((TPM_COMMAND_CODE) 0x00000018)
+#define TSC_ORD_PhysicalPresence ((TPM_COMMAND_CODE) 0x4000000A)
+#define TSC_ORD_ResetEstablishmentBit ((TPM_COMMAND_CODE) 0x4000000B)
+
+//
+// Part 2, section 18: Context structures
+//
+
+///
+/// Part 2, section 18.1: TPM_CONTEXT_BLOB
+///
+typedef struct tdTPM_CONTEXT_BLOB {
+ TPM_STRUCTURE_TAG tag;
+ TPM_RESOURCE_TYPE resourceType;
+ TPM_HANDLE handle;
+ UINT8 label[16];
+ UINT32 contextCount;
+ TPM_DIGEST integrityDigest;
+ UINT32 additionalSize;
+ UINT8 *additionalData;
+ UINT32 sensitiveSize;
+ UINT8 *sensitiveData;
+} TPM_CONTEXT_BLOB;
+
+///
+/// Part 2, section 18.2 TPM_CONTEXT_SENSITIVE
+///
+typedef struct tdTPM_CONTEXT_SENSITIVE {
+ TPM_STRUCTURE_TAG tag;
+ TPM_NONCE contextNonce;
+ UINT32 internalSize;
+ UINT8 *internalData;
+} TPM_CONTEXT_SENSITIVE;
+
+//
+// Part 2, section 19: NV Structures
+//
+
+//
+// Part 2, section 19.1.1: Required TPM_NV_INDEX values
+//
+#define TPM_NV_INDEX_LOCK ((UINT32)0xffffffff)
+#define TPM_NV_INDEX0 ((UINT32)0x00000000)
+#define TPM_NV_INDEX_DIR ((UINT32)0x10000001)
+#define TPM_NV_INDEX_EKCert ((UINT32)0x0000f000)
+#define TPM_NV_INDEX_TPM_CC ((UINT32)0x0000f001)
+#define TPM_NV_INDEX_PlatformCert ((UINT32)0x0000f002)
+#define TPM_NV_INDEX_Platform_CC ((UINT32)0x0000f003)
+//
+// Part 2, section 19.1.2: Reserved Index values
+//
+#define TPM_NV_INDEX_TSS_BASE ((UINT32)0x00011100)
+#define TPM_NV_INDEX_PC_BASE ((UINT32)0x00011200)
+#define TPM_NV_INDEX_SERVER_BASE ((UINT32)0x00011300)
+#define TPM_NV_INDEX_MOBILE_BASE ((UINT32)0x00011400)
+#define TPM_NV_INDEX_PERIPHERAL_BASE ((UINT32)0x00011500)
+#define TPM_NV_INDEX_GROUP_RESV_BASE ((UINT32)0x00010000)
+
+///
+/// Part 2, section 19.2: TPM_NV_ATTRIBUTES
+///
+typedef struct tdTPM_NV_ATTRIBUTES {
+ TPM_STRUCTURE_TAG tag;
+ UINT32 attributes;
+} TPM_NV_ATTRIBUTES;
+
+#define TPM_NV_PER_READ_STCLEAR (BIT31)
+#define TPM_NV_PER_AUTHREAD (BIT18)
+#define TPM_NV_PER_OWNERREAD (BIT17)
+#define TPM_NV_PER_PPREAD (BIT16)
+#define TPM_NV_PER_GLOBALLOCK (BIT15)
+#define TPM_NV_PER_WRITE_STCLEAR (BIT14)
+#define TPM_NV_PER_WRITEDEFINE (BIT13)
+#define TPM_NV_PER_WRITEALL (BIT12)
+#define TPM_NV_PER_AUTHWRITE (BIT2)
+#define TPM_NV_PER_OWNERWRITE (BIT1)
+#define TPM_NV_PER_PPWRITE (BIT0)
+
+///
+/// Part 2, section 19.3: TPM_NV_DATA_PUBLIC
+///
+typedef struct tdTPM_NV_DATA_PUBLIC {
+ TPM_STRUCTURE_TAG tag;
+ TPM_NV_INDEX nvIndex;
+ TPM_PCR_INFO_SHORT pcrInfoRead;
+ TPM_PCR_INFO_SHORT pcrInfoWrite;
+ TPM_NV_ATTRIBUTES permission;
+ BOOLEAN bReadSTClear;
+ BOOLEAN bWriteSTClear;
+ BOOLEAN bWriteDefine;
+ UINT32 dataSize;
+} TPM_NV_DATA_PUBLIC;
+
+//
+// Part 2, section 20: Delegate Structures
+//
+
+#define TPM_DEL_OWNER_BITS ((UINT32)0x00000001)
+#define TPM_DEL_KEY_BITS ((UINT32)0x00000002)
+///
+/// Part 2, section 20.2: Delegate Definitions
+///
+typedef struct tdTPM_DELEGATIONS {
+ TPM_STRUCTURE_TAG tag;
+ UINT32 delegateType;
+ UINT32 per1;
+ UINT32 per2;
+} TPM_DELEGATIONS;
+
+//
+// Part 2, section 20.2.1: Owner Permission Settings
+//
+#define TPM_DELEGATE_SetOrdinalAuditStatus (BIT30)
+#define TPM_DELEGATE_DirWriteAuth (BIT29)
+#define TPM_DELEGATE_CMK_ApproveMA (BIT28)
+#define TPM_DELEGATE_NV_WriteValue (BIT27)
+#define TPM_DELEGATE_CMK_CreateTicket (BIT26)
+#define TPM_DELEGATE_NV_ReadValue (BIT25)
+#define TPM_DELEGATE_Delegate_LoadOwnerDelegation (BIT24)
+#define TPM_DELEGATE_DAA_Join (BIT23)
+#define TPM_DELEGATE_AuthorizeMigrationKey (BIT22)
+#define TPM_DELEGATE_CreateMaintenanceArchive (BIT21)
+#define TPM_DELEGATE_LoadMaintenanceArchive (BIT20)
+#define TPM_DELEGATE_KillMaintenanceFeature (BIT19)
+#define TPM_DELEGATE_OwnerReadInteralPub (BIT18)
+#define TPM_DELEGATE_ResetLockValue (BIT17)
+#define TPM_DELEGATE_OwnerClear (BIT16)
+#define TPM_DELEGATE_DisableOwnerClear (BIT15)
+#define TPM_DELEGATE_NV_DefineSpace (BIT14)
+#define TPM_DELEGATE_OwnerSetDisable (BIT13)
+#define TPM_DELEGATE_SetCapability (BIT12)
+#define TPM_DELEGATE_MakeIdentity (BIT11)
+#define TPM_DELEGATE_ActivateIdentity (BIT10)
+#define TPM_DELEGATE_OwnerReadPubek (BIT9)
+#define TPM_DELEGATE_DisablePubekRead (BIT8)
+#define TPM_DELEGATE_SetRedirection (BIT7)
+#define TPM_DELEGATE_FieldUpgrade (BIT6)
+#define TPM_DELEGATE_Delegate_UpdateVerification (BIT5)
+#define TPM_DELEGATE_CreateCounter (BIT4)
+#define TPM_DELEGATE_ReleaseCounterOwner (BIT3)
+#define TPM_DELEGATE_DelegateManage (BIT2)
+#define TPM_DELEGATE_Delegate_CreateOwnerDelegation (BIT1)
+#define TPM_DELEGATE_DAA_Sign (BIT0)
+
+//
+// Part 2, section 20.2.3: Key Permission settings
+//
+#define TPM_KEY_DELEGATE_CMK_ConvertMigration (BIT28)
+#define TPM_KEY_DELEGATE_TickStampBlob (BIT27)
+#define TPM_KEY_DELEGATE_ChangeAuthAsymStart (BIT26)
+#define TPM_KEY_DELEGATE_ChangeAuthAsymFinish (BIT25)
+#define TPM_KEY_DELEGATE_CMK_CreateKey (BIT24)
+#define TPM_KEY_DELEGATE_MigrateKey (BIT23)
+#define TPM_KEY_DELEGATE_LoadKey2 (BIT22)
+#define TPM_KEY_DELEGATE_EstablishTransport (BIT21)
+#define TPM_KEY_DELEGATE_ReleaseTransportSigned (BIT20)
+#define TPM_KEY_DELEGATE_Quote2 (BIT19)
+#define TPM_KEY_DELEGATE_Sealx (BIT18)
+#define TPM_KEY_DELEGATE_MakeIdentity (BIT17)
+#define TPM_KEY_DELEGATE_ActivateIdentity (BIT16)
+#define TPM_KEY_DELEGATE_GetAuditDigestSigned (BIT15)
+#define TPM_KEY_DELEGATE_Sign (BIT14)
+#define TPM_KEY_DELEGATE_CertifyKey2 (BIT13)
+#define TPM_KEY_DELEGATE_CertifyKey (BIT12)
+#define TPM_KEY_DELEGATE_CreateWrapKey (BIT11)
+#define TPM_KEY_DELEGATE_CMK_CreateBlob (BIT10)
+#define TPM_KEY_DELEGATE_CreateMigrationBlob (BIT9)
+#define TPM_KEY_DELEGATE_ConvertMigrationBlob (BIT8)
+#define TPM_KEY_DELEGATE_CreateKeyDelegation (BIT7)
+#define TPM_KEY_DELEGATE_ChangeAuth (BIT6)
+#define TPM_KEY_DELEGATE_GetPubKey (BIT5)
+#define TPM_KEY_DELEGATE_UnBind (BIT4)
+#define TPM_KEY_DELEGATE_Quote (BIT3)
+#define TPM_KEY_DELEGATE_Unseal (BIT2)
+#define TPM_KEY_DELEGATE_Seal (BIT1)
+#define TPM_KEY_DELEGATE_LoadKey (BIT0)
+
+//
+// Part 2, section 20.3: TPM_FAMILY_FLAGS
+//
+#define TPM_DELEGATE_ADMIN_LOCK (BIT1)
+#define TPM_FAMFLAG_ENABLE (BIT0)
+
+///
+/// Part 2, section 20.4: TPM_FAMILY_LABEL
+///
+typedef struct tdTPM_FAMILY_LABEL {
+ UINT8 label;
+} TPM_FAMILY_LABEL;
+
+///
+/// Part 2, section 20.5: TPM_FAMILY_TABLE_ENTRY
+///
+typedef struct tdTPM_FAMILY_TABLE_ENTRY {
+ TPM_STRUCTURE_TAG tag;
+ TPM_FAMILY_LABEL label;
+ TPM_FAMILY_ID familyID;
+ TPM_FAMILY_VERIFICATION verificationCount;
+ TPM_FAMILY_FLAGS flags;
+} TPM_FAMILY_TABLE_ENTRY;
+
+//
+// Part 2, section 20.6: TPM_FAMILY_TABLE
+//
+#define TPM_NUM_FAMILY_TABLE_ENTRY_MIN 8
+
+typedef struct tdTPM_FAMILY_TABLE {
+ TPM_FAMILY_TABLE_ENTRY famTableRow[TPM_NUM_FAMILY_TABLE_ENTRY_MIN];
+} TPM_FAMILY_TABLE;
+
+///
+/// Part 2, section 20.7: TPM_DELEGATE_LABEL
+///
+typedef struct tdTPM_DELEGATE_LABEL {
+ UINT8 label;
+} TPM_DELEGATE_LABEL;
+
+///
+/// Part 2, section 20.8: TPM_DELEGATE_PUBLIC
+///
+typedef struct tdTPM_DELEGATE_PUBLIC {
+ TPM_STRUCTURE_TAG tag;
+ TPM_DELEGATE_LABEL label;
+ TPM_PCR_INFO_SHORT pcrInfo;
+ TPM_DELEGATIONS permissions;
+ TPM_FAMILY_ID familyID;
+ TPM_FAMILY_VERIFICATION verificationCount;
+} TPM_DELEGATE_PUBLIC;
+
+///
+/// Part 2, section 20.9: TPM_DELEGATE_TABLE_ROW
+///
+typedef struct tdTPM_DELEGATE_TABLE_ROW {
+ TPM_STRUCTURE_TAG tag;
+ TPM_DELEGATE_PUBLIC pub;
+ TPM_SECRET authValue;
+} TPM_DELEGATE_TABLE_ROW;
+
+//
+// Part 2, section 20.10: TPM_DELEGATE_TABLE
+//
+#define TPM_NUM_DELEGATE_TABLE_ENTRY_MIN 2
+
+typedef struct tdTPM_DELEGATE_TABLE {
+ TPM_DELEGATE_TABLE_ROW delRow[TPM_NUM_DELEGATE_TABLE_ENTRY_MIN];
+} TPM_DELEGATE_TABLE;
+
+///
+/// Part 2, section 20.11: TPM_DELEGATE_SENSITIVE
+///
+typedef struct tdTPM_DELEGATE_SENSITIVE {
+ TPM_STRUCTURE_TAG tag;
+ TPM_SECRET authValue;
+} TPM_DELEGATE_SENSITIVE;
+
+///
+/// Part 2, section 20.12: TPM_DELEGATE_OWNER_BLOB
+///
+typedef struct tdTPM_DELEGATE_OWNER_BLOB {
+ TPM_STRUCTURE_TAG tag;
+ TPM_DELEGATE_PUBLIC pub;
+ TPM_DIGEST integrityDigest;
+ UINT32 additionalSize;
+ UINT8 *additionalArea;
+ UINT32 sensitiveSize;
+ UINT8 *sensitiveArea;
+} TPM_DELEGATE_OWNER_BLOB;
+
+///
+/// Part 2, section 20.13: TTPM_DELEGATE_KEY_BLOB
+///
+typedef struct tdTPM_DELEGATE_KEY_BLOB {
+ TPM_STRUCTURE_TAG tag;
+ TPM_DELEGATE_PUBLIC pub;
+ TPM_DIGEST integrityDigest;
+ TPM_DIGEST pubKeyDigest;
+ UINT32 additionalSize;
+ UINT8 *additionalArea;
+ UINT32 sensitiveSize;
+ UINT8 *sensitiveArea;
+} TPM_DELEGATE_KEY_BLOB;
+
+//
+// Part 2, section 20.14: TPM_FAMILY_OPERATION Values
+//
+#define TPM_FAMILY_CREATE ((UINT32)0x00000001)
+#define TPM_FAMILY_ENABLE ((UINT32)0x00000002)
+#define TPM_FAMILY_ADMIN ((UINT32)0x00000003)
+#define TPM_FAMILY_INVALIDATE ((UINT32)0x00000004)
+
+//
+// Part 2, section 21.1: TPM_CAPABILITY_AREA for GetCapability
+//
+#define TPM_CAP_ORD ((TPM_CAPABILITY_AREA) 0x00000001)
+#define TPM_CAP_ALG ((TPM_CAPABILITY_AREA) 0x00000002)
+#define TPM_CAP_PID ((TPM_CAPABILITY_AREA) 0x00000003)
+#define TPM_CAP_FLAG ((TPM_CAPABILITY_AREA) 0x00000004)
+#define TPM_CAP_PROPERTY ((TPM_CAPABILITY_AREA) 0x00000005)
+#define TPM_CAP_VERSION ((TPM_CAPABILITY_AREA) 0x00000006)
+#define TPM_CAP_KEY_HANDLE ((TPM_CAPABILITY_AREA) 0x00000007)
+#define TPM_CAP_CHECK_LOADED ((TPM_CAPABILITY_AREA) 0x00000008)
+#define TPM_CAP_SYM_MODE ((TPM_CAPABILITY_AREA) 0x00000009)
+#define TPM_CAP_KEY_STATUS ((TPM_CAPABILITY_AREA) 0x0000000C)
+#define TPM_CAP_NV_LIST ((TPM_CAPABILITY_AREA) 0x0000000D)
+#define TPM_CAP_MFR ((TPM_CAPABILITY_AREA) 0x00000010)
+#define TPM_CAP_NV_INDEX ((TPM_CAPABILITY_AREA) 0x00000011)
+#define TPM_CAP_TRANS_ALG ((TPM_CAPABILITY_AREA) 0x00000012)
+#define TPM_CAP_HANDLE ((TPM_CAPABILITY_AREA) 0x00000014)
+#define TPM_CAP_TRANS_ES ((TPM_CAPABILITY_AREA) 0x00000015)
+#define TPM_CAP_AUTH_ENCRYPT ((TPM_CAPABILITY_AREA) 0x00000017)
+#define TPM_CAP_SELECT_SIZE ((TPM_CAPABILITY_AREA) 0x00000018)
+#define TPM_CAP_VERSION_VAL ((TPM_CAPABILITY_AREA) 0x0000001A)
+
+#define TPM_CAP_FLAG_PERMANENT ((TPM_CAPABILITY_AREA) 0x00000108)
+#define TPM_CAP_FLAG_VOLATILE ((TPM_CAPABILITY_AREA) 0x00000109)
+
+//
+// Part 2, section 21.2: CAP_PROPERTY Subcap values for GetCapability
+//
+#define TPM_CAP_PROP_PCR ((TPM_CAPABILITY_AREA) 0x00000101)
+#define TPM_CAP_PROP_DIR ((TPM_CAPABILITY_AREA) 0x00000102)
+#define TPM_CAP_PROP_MANUFACTURER ((TPM_CAPABILITY_AREA) 0x00000103)
+#define TPM_CAP_PROP_KEYS ((TPM_CAPABILITY_AREA) 0x00000104)
+#define TPM_CAP_PROP_MIN_COUNTER ((TPM_CAPABILITY_AREA) 0x00000107)
+#define TPM_CAP_PROP_AUTHSESS ((TPM_CAPABILITY_AREA) 0x0000010A)
+#define TPM_CAP_PROP_TRANSESS ((TPM_CAPABILITY_AREA) 0x0000010B)
+#define TPM_CAP_PROP_COUNTERS ((TPM_CAPABILITY_AREA) 0x0000010C)
+#define TPM_CAP_PROP_MAX_AUTHSESS ((TPM_CAPABILITY_AREA) 0x0000010D)
+#define TPM_CAP_PROP_MAX_TRANSESS ((TPM_CAPABILITY_AREA) 0x0000010E)
+#define TPM_CAP_PROP_MAX_COUNTERS ((TPM_CAPABILITY_AREA) 0x0000010F)
+#define TPM_CAP_PROP_MAX_KEYS ((TPM_CAPABILITY_AREA) 0x00000110)
+#define TPM_CAP_PROP_OWNER ((TPM_CAPABILITY_AREA) 0x00000111)
+#define TPM_CAP_PROP_CONTEXT ((TPM_CAPABILITY_AREA) 0x00000112)
+#define TPM_CAP_PROP_MAX_CONTEXT ((TPM_CAPABILITY_AREA) 0x00000113)
+#define TPM_CAP_PROP_FAMILYROWS ((TPM_CAPABILITY_AREA) 0x00000114)
+#define TPM_CAP_PROP_TIS_TIMEOUT ((TPM_CAPABILITY_AREA) 0x00000115)
+#define TPM_CAP_PROP_STARTUP_EFFECT ((TPM_CAPABILITY_AREA) 0x00000116)
+#define TPM_CAP_PROP_DELEGATE_ROW ((TPM_CAPABILITY_AREA) 0x00000117)
+#define TPM_CAP_PROP_DAA_MAX ((TPM_CAPABILITY_AREA) 0x00000119)
+#define CAP_PROP_SESSION_DAA ((TPM_CAPABILITY_AREA) 0x0000011A)
+#define TPM_CAP_PROP_CONTEXT_DIST ((TPM_CAPABILITY_AREA) 0x0000011B)
+#define TPM_CAP_PROP_DAA_INTERRUPT ((TPM_CAPABILITY_AREA) 0x0000011C)
+#define TPM_CAP_PROP_SESSIONS ((TPM_CAPABILITY_AREA) 0x0000011D)
+#define TPM_CAP_PROP_MAX_SESSIONS ((TPM_CAPABILITY_AREA) 0x0000011E)
+#define TPM_CAP_PROP_CMK_RESTRICTION ((TPM_CAPABILITY_AREA) 0x0000011F)
+#define TPM_CAP_PROP_DURATION ((TPM_CAPABILITY_AREA) 0x00000120)
+#define TPM_CAP_PROP_ACTIVE_COUNTER ((TPM_CAPABILITY_AREA) 0x00000122)
+#define TPM_CAP_PROP_MAX_NV_AVAILABLE ((TPM_CAPABILITY_AREA) 0x00000123)
+#define TPM_CAP_PROP_INPUT_BUFFER ((TPM_CAPABILITY_AREA) 0x00000124)
+
+//
+// Part 2, section 21.4: TPM_CAPABILITY_AREA for SetCapability
+//
+#define TPM_SET_PERM_FLAGS ((TPM_CAPABILITY_AREA) 0x00000001)
+#define TPM_SET_PERM_DATA ((TPM_CAPABILITY_AREA) 0x00000002)
+#define TPM_SET_STCLEAR_FLAGS ((TPM_CAPABILITY_AREA) 0x00000003)
+#define TPM_SET_STCLEAR_DATA ((TPM_CAPABILITY_AREA) 0x00000004)
+#define TPM_SET_STANY_FLAGS ((TPM_CAPABILITY_AREA) 0x00000005)
+#define TPM_SET_STANY_DATA ((TPM_CAPABILITY_AREA) 0x00000006)
+
+///
+/// Part 2, section 21.6: TPM_CAP_VERSION_INFO
+/// [size_is(vendorSpecificSize)] BYTE* vendorSpecific;
+///
+typedef struct tdTPM_CAP_VERSION_INFO {
+ TPM_STRUCTURE_TAG tag;
+ TPM_VERSION version;
+ UINT16 specLevel;
+ UINT8 errataRev;
+ UINT8 tpmVendorID[4];
+ UINT16 vendorSpecificSize;
+ UINT8 *vendorSpecific;
+} TPM_CAP_VERSION_INFO;
+
+///
+/// Part 2, section 21.10: TPM_DA_ACTION_TYPE
+///
+typedef struct tdTPM_DA_ACTION_TYPE {
+ TPM_STRUCTURE_TAG tag;
+ UINT32 actions;
+} TPM_DA_ACTION_TYPE;
+
+#define TPM_DA_ACTION_FAILURE_MODE (((UINT32)1)<<3)
+#define TPM_DA_ACTION_DEACTIVATE (((UINT32)1)<<2)
+#define TPM_DA_ACTION_DISABLE (((UINT32)1)<<1)
+#define TPM_DA_ACTION_TIMEOUT (((UINT32)1)<<0)
+
+///
+/// Part 2, section 21.7: TPM_DA_INFO
+///
+typedef struct tdTPM_DA_INFO {
+ TPM_STRUCTURE_TAG tag;
+ TPM_DA_STATE state;
+ UINT16 currentCount;
+ UINT16 thresholdCount;
+ TPM_DA_ACTION_TYPE actionAtThreshold;
+ UINT32 actionDependValue;
+ UINT32 vendorDataSize;
+ UINT8 *vendorData;
+} TPM_DA_INFO;
+
+///
+/// Part 2, section 21.8: TPM_DA_INFO_LIMITED
+///
+typedef struct tdTPM_DA_INFO_LIMITED {
+ TPM_STRUCTURE_TAG tag;
+ TPM_DA_STATE state;
+ TPM_DA_ACTION_TYPE actionAtThreshold;
+ UINT32 vendorDataSize;
+ UINT8 *vendorData;
+} TPM_DA_INFO_LIMITED;
+
+//
+// Part 2, section 21.9: CAP_PROPERTY Subcap values for GetCapability
+//
+#define TPM_DA_STATE_INACTIVE ((UINT8)0x00)
+#define TPM_DA_STATE_ACTIVE ((UINT8)0x01)
+
+//
+// Part 2, section 22: DAA Structures
+//
+
+//
+// Part 2, section 22.1: Size definitions
+//
+#define TPM_DAA_SIZE_r0 (43)
+#define TPM_DAA_SIZE_r1 (43)
+#define TPM_DAA_SIZE_r2 (128)
+#define TPM_DAA_SIZE_r3 (168)
+#define TPM_DAA_SIZE_r4 (219)
+#define TPM_DAA_SIZE_NT (20)
+#define TPM_DAA_SIZE_v0 (128)
+#define TPM_DAA_SIZE_v1 (192)
+#define TPM_DAA_SIZE_NE (256)
+#define TPM_DAA_SIZE_w (256)
+#define TPM_DAA_SIZE_issuerModulus (256)
+//
+// Part 2, section 22.2: Constant definitions
+//
+#define TPM_DAA_power0 (104)
+#define TPM_DAA_power1 (1024)
+
+///
+/// Part 2, section 22.3: TPM_DAA_ISSUER
+///
+typedef struct tdTPM_DAA_ISSUER {
+ TPM_STRUCTURE_TAG tag;
+ TPM_DIGEST DAA_digest_R0;
+ TPM_DIGEST DAA_digest_R1;
+ TPM_DIGEST DAA_digest_S0;
+ TPM_DIGEST DAA_digest_S1;
+ TPM_DIGEST DAA_digest_n;
+ TPM_DIGEST DAA_digest_gamma;
+ UINT8 DAA_generic_q[26];
+} TPM_DAA_ISSUER;
+
+///
+/// Part 2, section 22.4: TPM_DAA_TPM
+///
+typedef struct tdTPM_DAA_TPM {
+ TPM_STRUCTURE_TAG tag;
+ TPM_DIGEST DAA_digestIssuer;
+ TPM_DIGEST DAA_digest_v0;
+ TPM_DIGEST DAA_digest_v1;
+ TPM_DIGEST DAA_rekey;
+ UINT32 DAA_count;
+} TPM_DAA_TPM;
+
+///
+/// Part 2, section 22.5: TPM_DAA_CONTEXT
+///
+typedef struct tdTPM_DAA_CONTEXT {
+ TPM_STRUCTURE_TAG tag;
+ TPM_DIGEST DAA_digestContext;
+ TPM_DIGEST DAA_digest;
+ TPM_DAA_CONTEXT_SEED DAA_contextSeed;
+ UINT8 DAA_scratch[256];
+ UINT8 DAA_stage;
+} TPM_DAA_CONTEXT;
+
+///
+/// Part 2, section 22.6: TPM_DAA_JOINDATA
+///
+typedef struct tdTPM_DAA_JOINDATA {
+ UINT8 DAA_join_u0[128];
+ UINT8 DAA_join_u1[138];
+ TPM_DIGEST DAA_digest_n0;
+} TPM_DAA_JOINDATA;
+
+///
+/// Part 2, section 22.8: TPM_DAA_BLOB
+///
+typedef struct tdTPM_DAA_BLOB {
+ TPM_STRUCTURE_TAG tag;
+ TPM_RESOURCE_TYPE resourceType;
+ UINT8 label[16];
+ TPM_DIGEST blobIntegrity;
+ UINT32 additionalSize;
+ UINT8 *additionalData;
+ UINT32 sensitiveSize;
+ UINT8 *sensitiveData;
+} TPM_DAA_BLOB;
+
+///
+/// Part 2, section 22.9: TPM_DAA_SENSITIVE
+///
+typedef struct tdTPM_DAA_SENSITIVE {
+ TPM_STRUCTURE_TAG tag;
+ UINT32 internalSize;
+ UINT8 *internalData;
+} TPM_DAA_SENSITIVE;
+
+//
+// Part 2, section 23: Redirection
+//
+
+///
+/// Part 2 section 23.1: TPM_REDIR_COMMAND
+/// This section defines exactly one value but does not
+/// give it a name. The definition of TPM_SetRedirection in Part3
+/// refers to exactly one name but does not give its value. We join
+/// them here.
+///
+#define TPM_REDIR_GPIO (0x00000001)
+
+///
+/// TPM Command Headers defined in Part 3
+///
+typedef struct tdTPM_RQU_COMMAND_HDR {
+ TPM_STRUCTURE_TAG tag;
+ UINT32 paramSize;
+ TPM_COMMAND_CODE ordinal;
+} TPM_RQU_COMMAND_HDR;
+
+///
+/// TPM Response Headers defined in Part 3
+///
+typedef struct tdTPM_RSP_COMMAND_HDR {
+ TPM_STRUCTURE_TAG tag;
+ UINT32 paramSize;
+ TPM_RESULT returnCode;
+} TPM_RSP_COMMAND_HDR;
+
+#pragma pack ()
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/Tpm20.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/Tpm20.h
new file mode 100644
index 0000000000..5c3e76b0f6
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/Tpm20.h
@@ -0,0 +1,1812 @@
+/** @file
+ TPM2.0 Specification data structures
+ (Trusted Platform Module Library Specification, Family "2.0", Level 00, Revision 00.96,
+ @http://www.trustedcomputinggroup.org/resources/tpm_library_specification)
+
+ Check http://trustedcomputinggroup.org for latest specification updates.
+
+Copyright (c) 2013 - 2015, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _TPM20_H_
+#define _TPM20_H_
+
+#include
+
+#pragma pack (1)
+
+// Annex A Algorithm Constants
+
+// Table 205 - Defines for SHA1 Hash Values
+#define SHA1_DIGEST_SIZE 20
+#define SHA1_BLOCK_SIZE 64
+
+// Table 206 - Defines for SHA256 Hash Values
+#define SHA256_DIGEST_SIZE 32
+#define SHA256_BLOCK_SIZE 64
+
+// Table 207 - Defines for SHA384 Hash Values
+#define SHA384_DIGEST_SIZE 48
+#define SHA384_BLOCK_SIZE 128
+
+// Table 208 - Defines for SHA512 Hash Values
+#define SHA512_DIGEST_SIZE 64
+#define SHA512_BLOCK_SIZE 128
+
+// Table 209 - Defines for SM3_256 Hash Values
+#define SM3_256_DIGEST_SIZE 32
+#define SM3_256_BLOCK_SIZE 64
+
+// Table 210 - Defines for Architectural Limits Values
+#define MAX_SESSION_NUMBER 3
+
+// Annex B Implementation Definitions
+
+// Table 211 - Defines for Logic Values
+#define YES 1
+#define NO 0
+#define SET 1
+#define CLEAR 0
+
+// Table 215 - Defines for RSA Algorithm Constants
+#define MAX_RSA_KEY_BITS 2048
+#define MAX_RSA_KEY_BYTES ((MAX_RSA_KEY_BITS + 7) / 8)
+
+// Table 216 - Defines for ECC Algorithm Constants
+#define MAX_ECC_KEY_BITS 256
+#define MAX_ECC_KEY_BYTES ((MAX_ECC_KEY_BITS + 7) / 8)
+
+// Table 217 - Defines for AES Algorithm Constants
+#define MAX_AES_KEY_BITS 128
+#define MAX_AES_BLOCK_SIZE_BYTES 16
+#define MAX_AES_KEY_BYTES ((MAX_AES_KEY_BITS + 7) / 8)
+
+// Table 218 - Defines for SM4 Algorithm Constants
+#define MAX_SM4_KEY_BITS 128
+#define MAX_SM4_BLOCK_SIZE_BYTES 16
+#define MAX_SM4_KEY_BYTES ((MAX_SM4_KEY_BITS + 7) / 8)
+
+// Table 219 - Defines for Symmetric Algorithm Constants
+#define MAX_SYM_KEY_BITS MAX_AES_KEY_BITS
+#define MAX_SYM_KEY_BYTES MAX_AES_KEY_BYTES
+#define MAX_SYM_BLOCK_SIZE MAX_AES_BLOCK_SIZE_BYTES
+
+// Table 220 - Defines for Implementation Values
+typedef UINT16 BSIZE;
+#define BUFFER_ALIGNMENT 4
+#define IMPLEMENTATION_PCR 24
+#define PLATFORM_PCR 24
+#define DRTM_PCR 17
+#define NUM_LOCALITIES 5
+#define MAX_HANDLE_NUM 3
+#define MAX_ACTIVE_SESSIONS 64
+typedef UINT16 CONTEXT_SLOT;
+typedef UINT64 CONTEXT_COUNTER;
+#define MAX_LOADED_SESSIONS 3
+#define MAX_SESSION_NUM 3
+#define MAX_LOADED_OBJECTS 3
+#define MIN_EVICT_OBJECTS 2
+#define PCR_SELECT_MIN ((PLATFORM_PCR + 7) / 8)
+#define PCR_SELECT_MAX ((IMPLEMENTATION_PCR + 7) / 8)
+#define NUM_POLICY_PCR_GROUP 1
+#define NUM_AUTHVALUE_PCR_GROUP 1
+#define MAX_CONTEXT_SIZE 4000
+#define MAX_DIGEST_BUFFER 1024
+#define MAX_NV_INDEX_SIZE 1024
+#define MAX_CAP_BUFFER 1024
+#define NV_MEMORY_SIZE 16384
+#define NUM_STATIC_PCR 16
+#define MAX_ALG_LIST_SIZE 64
+#define TIMER_PRESCALE 100000
+#define PRIMARY_SEED_SIZE 32
+#define CONTEXT_ENCRYPT_ALG TPM_ALG_AES
+#define CONTEXT_ENCRYPT_KEY_BITS MAX_SYM_KEY_BITS
+#define CONTEXT_ENCRYPT_KEY_BYTES ((CONTEXT_ENCRYPT_KEY_BITS + 7) / 8)
+#define CONTEXT_INTEGRITY_HASH_ALG TPM_ALG_SHA256
+#define CONTEXT_INTEGRITY_HASH_SIZE SHA256_DIGEST_SIZE
+#define PROOF_SIZE CONTEXT_INTEGRITY_HASH_SIZE
+#define NV_CLOCK_UPDATE_INTERVAL 12
+#define NUM_POLICY_PCR 1
+#define MAX_COMMAND_SIZE 4096
+#define MAX_RESPONSE_SIZE 4096
+#define ORDERLY_BITS 8
+#define MAX_ORDERLY_COUNT ((1 << ORDERLY_BITS) - 1)
+#define ALG_ID_FIRST TPM_ALG_FIRST
+#define ALG_ID_LAST TPM_ALG_LAST
+#define MAX_SYM_DATA 128
+#define MAX_RNG_ENTROPY_SIZE 64
+#define RAM_INDEX_SPACE 512
+#define RSA_DEFAULT_PUBLIC_EXPONENT 0x00010001
+#define CRT_FORMAT_RSA YES
+#define PRIVATE_VENDOR_SPECIFIC_BYTES ((MAX_RSA_KEY_BYTES / 2) * ( 3 + CRT_FORMAT_RSA * 2))
+
+// Capability related MAX_ value
+#define MAX_CAP_DATA (MAX_CAP_BUFFER - sizeof(TPM_CAP) - sizeof(UINT32))
+#define MAX_CAP_ALGS (MAX_CAP_DATA / sizeof(TPMS_ALG_PROPERTY))
+#define MAX_CAP_HANDLES (MAX_CAP_DATA / sizeof(TPM_HANDLE))
+#define MAX_CAP_CC (MAX_CAP_DATA / sizeof(TPM_CC))
+#define MAX_TPM_PROPERTIES (MAX_CAP_DATA / sizeof(TPMS_TAGGED_PROPERTY))
+#define MAX_PCR_PROPERTIES (MAX_CAP_DATA / sizeof(TPMS_TAGGED_PCR_SELECT))
+#define MAX_ECC_CURVES (MAX_CAP_DATA / sizeof(TPM_ECC_CURVE))
+
+//
+// Always set 5 here, because we want to support all hash algo in BIOS.
+//
+#define HASH_COUNT 5
+
+// 5 Base Types
+
+// Table 3 - Definition of Base Types
+typedef UINT8 BYTE;
+
+// Table 4 - Definition of Types for Documentation Clarity
+//
+// NOTE: Comment because it has same name as TPM1.2 (value is same, so not runtime issue)
+//
+// typedef UINT32 TPM_ALGORITHM_ID;
+// typedef UINT32 TPM_MODIFIER_INDICATOR;
+typedef UINT32 TPM_AUTHORIZATION_SIZE;
+typedef UINT32 TPM_PARAMETER_SIZE;
+typedef UINT16 TPM_KEY_SIZE;
+typedef UINT16 TPM_KEY_BITS;
+
+// 6 Constants
+
+// Table 6 - TPM_GENERATED Constants
+typedef UINT32 TPM_GENERATED;
+#define TPM_GENERATED_VALUE (TPM_GENERATED)(0xff544347)
+
+// Table 7 - TPM_ALG_ID Constants
+typedef UINT16 TPM_ALG_ID;
+//
+// NOTE: Comment some algo which has same name as TPM1.2 (value is same, so not runtime issue)
+//
+#define TPM_ALG_ERROR (TPM_ALG_ID)(0x0000)
+#define TPM_ALG_FIRST (TPM_ALG_ID)(0x0001)
+// #define TPM_ALG_RSA (TPM_ALG_ID)(0x0001)
+// #define TPM_ALG_SHA (TPM_ALG_ID)(0x0004)
+#define TPM_ALG_SHA1 (TPM_ALG_ID)(0x0004)
+// #define TPM_ALG_HMAC (TPM_ALG_ID)(0x0005)
+#define TPM_ALG_AES (TPM_ALG_ID)(0x0006)
+// #define TPM_ALG_MGF1 (TPM_ALG_ID)(0x0007)
+#define TPM_ALG_KEYEDHASH (TPM_ALG_ID)(0x0008)
+// #define TPM_ALG_XOR (TPM_ALG_ID)(0x000A)
+#define TPM_ALG_SHA256 (TPM_ALG_ID)(0x000B)
+#define TPM_ALG_SHA384 (TPM_ALG_ID)(0x000C)
+#define TPM_ALG_SHA512 (TPM_ALG_ID)(0x000D)
+#define TPM_ALG_NULL (TPM_ALG_ID)(0x0010)
+#define TPM_ALG_SM3_256 (TPM_ALG_ID)(0x0012)
+#define TPM_ALG_SM4 (TPM_ALG_ID)(0x0013)
+#define TPM_ALG_RSASSA (TPM_ALG_ID)(0x0014)
+#define TPM_ALG_RSAES (TPM_ALG_ID)(0x0015)
+#define TPM_ALG_RSAPSS (TPM_ALG_ID)(0x0016)
+#define TPM_ALG_OAEP (TPM_ALG_ID)(0x0017)
+#define TPM_ALG_ECDSA (TPM_ALG_ID)(0x0018)
+#define TPM_ALG_ECDH (TPM_ALG_ID)(0x0019)
+#define TPM_ALG_ECDAA (TPM_ALG_ID)(0x001A)
+#define TPM_ALG_SM2 (TPM_ALG_ID)(0x001B)
+#define TPM_ALG_ECSCHNORR (TPM_ALG_ID)(0x001C)
+#define TPM_ALG_ECMQV (TPM_ALG_ID)(0x001D)
+#define TPM_ALG_KDF1_SP800_56a (TPM_ALG_ID)(0x0020)
+#define TPM_ALG_KDF2 (TPM_ALG_ID)(0x0021)
+#define TPM_ALG_KDF1_SP800_108 (TPM_ALG_ID)(0x0022)
+#define TPM_ALG_ECC (TPM_ALG_ID)(0x0023)
+#define TPM_ALG_SYMCIPHER (TPM_ALG_ID)(0x0025)
+#define TPM_ALG_CTR (TPM_ALG_ID)(0x0040)
+#define TPM_ALG_OFB (TPM_ALG_ID)(0x0041)
+#define TPM_ALG_CBC (TPM_ALG_ID)(0x0042)
+#define TPM_ALG_CFB (TPM_ALG_ID)(0x0043)
+#define TPM_ALG_ECB (TPM_ALG_ID)(0x0044)
+#define TPM_ALG_LAST (TPM_ALG_ID)(0x0044)
+
+// Table 8 - TPM_ECC_CURVE Constants
+typedef UINT16 TPM_ECC_CURVE;
+#define TPM_ECC_NONE (TPM_ECC_CURVE)(0x0000)
+#define TPM_ECC_NIST_P192 (TPM_ECC_CURVE)(0x0001)
+#define TPM_ECC_NIST_P224 (TPM_ECC_CURVE)(0x0002)
+#define TPM_ECC_NIST_P256 (TPM_ECC_CURVE)(0x0003)
+#define TPM_ECC_NIST_P384 (TPM_ECC_CURVE)(0x0004)
+#define TPM_ECC_NIST_P521 (TPM_ECC_CURVE)(0x0005)
+#define TPM_ECC_BN_P256 (TPM_ECC_CURVE)(0x0010)
+#define TPM_ECC_BN_P638 (TPM_ECC_CURVE)(0x0011)
+#define TPM_ECC_SM2_P256 (TPM_ECC_CURVE)(0x0020)
+
+// Table 11 - TPM_CC Constants (Numeric Order)
+typedef UINT32 TPM_CC;
+#define TPM_CC_FIRST (TPM_CC)(0x0000011F)
+#define TPM_CC_PP_FIRST (TPM_CC)(0x0000011F)
+#define TPM_CC_NV_UndefineSpaceSpecial (TPM_CC)(0x0000011F)
+#define TPM_CC_EvictControl (TPM_CC)(0x00000120)
+#define TPM_CC_HierarchyControl (TPM_CC)(0x00000121)
+#define TPM_CC_NV_UndefineSpace (TPM_CC)(0x00000122)
+#define TPM_CC_ChangeEPS (TPM_CC)(0x00000124)
+#define TPM_CC_ChangePPS (TPM_CC)(0x00000125)
+#define TPM_CC_Clear (TPM_CC)(0x00000126)
+#define TPM_CC_ClearControl (TPM_CC)(0x00000127)
+#define TPM_CC_ClockSet (TPM_CC)(0x00000128)
+#define TPM_CC_HierarchyChangeAuth (TPM_CC)(0x00000129)
+#define TPM_CC_NV_DefineSpace (TPM_CC)(0x0000012A)
+#define TPM_CC_PCR_Allocate (TPM_CC)(0x0000012B)
+#define TPM_CC_PCR_SetAuthPolicy (TPM_CC)(0x0000012C)
+#define TPM_CC_PP_Commands (TPM_CC)(0x0000012D)
+#define TPM_CC_SetPrimaryPolicy (TPM_CC)(0x0000012E)
+#define TPM_CC_FieldUpgradeStart (TPM_CC)(0x0000012F)
+#define TPM_CC_ClockRateAdjust (TPM_CC)(0x00000130)
+#define TPM_CC_CreatePrimary (TPM_CC)(0x00000131)
+#define TPM_CC_NV_GlobalWriteLock (TPM_CC)(0x00000132)
+#define TPM_CC_PP_LAST (TPM_CC)(0x00000132)
+#define TPM_CC_GetCommandAuditDigest (TPM_CC)(0x00000133)
+#define TPM_CC_NV_Increment (TPM_CC)(0x00000134)
+#define TPM_CC_NV_SetBits (TPM_CC)(0x00000135)
+#define TPM_CC_NV_Extend (TPM_CC)(0x00000136)
+#define TPM_CC_NV_Write (TPM_CC)(0x00000137)
+#define TPM_CC_NV_WriteLock (TPM_CC)(0x00000138)
+#define TPM_CC_DictionaryAttackLockReset (TPM_CC)(0x00000139)
+#define TPM_CC_DictionaryAttackParameters (TPM_CC)(0x0000013A)
+#define TPM_CC_NV_ChangeAuth (TPM_CC)(0x0000013B)
+#define TPM_CC_PCR_Event (TPM_CC)(0x0000013C)
+#define TPM_CC_PCR_Reset (TPM_CC)(0x0000013D)
+#define TPM_CC_SequenceComplete (TPM_CC)(0x0000013E)
+#define TPM_CC_SetAlgorithmSet (TPM_CC)(0x0000013F)
+#define TPM_CC_SetCommandCodeAuditStatus (TPM_CC)(0x00000140)
+#define TPM_CC_FieldUpgradeData (TPM_CC)(0x00000141)
+#define TPM_CC_IncrementalSelfTest (TPM_CC)(0x00000142)
+#define TPM_CC_SelfTest (TPM_CC)(0x00000143)
+#define TPM_CC_Startup (TPM_CC)(0x00000144)
+#define TPM_CC_Shutdown (TPM_CC)(0x00000145)
+#define TPM_CC_StirRandom (TPM_CC)(0x00000146)
+#define TPM_CC_ActivateCredential (TPM_CC)(0x00000147)
+#define TPM_CC_Certify (TPM_CC)(0x00000148)
+#define TPM_CC_PolicyNV (TPM_CC)(0x00000149)
+#define TPM_CC_CertifyCreation (TPM_CC)(0x0000014A)
+#define TPM_CC_Duplicate (TPM_CC)(0x0000014B)
+#define TPM_CC_GetTime (TPM_CC)(0x0000014C)
+#define TPM_CC_GetSessionAuditDigest (TPM_CC)(0x0000014D)
+#define TPM_CC_NV_Read (TPM_CC)(0x0000014E)
+#define TPM_CC_NV_ReadLock (TPM_CC)(0x0000014F)
+#define TPM_CC_ObjectChangeAuth (TPM_CC)(0x00000150)
+#define TPM_CC_PolicySecret (TPM_CC)(0x00000151)
+#define TPM_CC_Rewrap (TPM_CC)(0x00000152)
+#define TPM_CC_Create (TPM_CC)(0x00000153)
+#define TPM_CC_ECDH_ZGen (TPM_CC)(0x00000154)
+#define TPM_CC_HMAC (TPM_CC)(0x00000155)
+#define TPM_CC_Import (TPM_CC)(0x00000156)
+#define TPM_CC_Load (TPM_CC)(0x00000157)
+#define TPM_CC_Quote (TPM_CC)(0x00000158)
+#define TPM_CC_RSA_Decrypt (TPM_CC)(0x00000159)
+#define TPM_CC_HMAC_Start (TPM_CC)(0x0000015B)
+#define TPM_CC_SequenceUpdate (TPM_CC)(0x0000015C)
+#define TPM_CC_Sign (TPM_CC)(0x0000015D)
+#define TPM_CC_Unseal (TPM_CC)(0x0000015E)
+#define TPM_CC_PolicySigned (TPM_CC)(0x00000160)
+#define TPM_CC_ContextLoad (TPM_CC)(0x00000161)
+#define TPM_CC_ContextSave (TPM_CC)(0x00000162)
+#define TPM_CC_ECDH_KeyGen (TPM_CC)(0x00000163)
+#define TPM_CC_EncryptDecrypt (TPM_CC)(0x00000164)
+#define TPM_CC_FlushContext (TPM_CC)(0x00000165)
+#define TPM_CC_LoadExternal (TPM_CC)(0x00000167)
+#define TPM_CC_MakeCredential (TPM_CC)(0x00000168)
+#define TPM_CC_NV_ReadPublic (TPM_CC)(0x00000169)
+#define TPM_CC_PolicyAuthorize (TPM_CC)(0x0000016A)
+#define TPM_CC_PolicyAuthValue (TPM_CC)(0x0000016B)
+#define TPM_CC_PolicyCommandCode (TPM_CC)(0x0000016C)
+#define TPM_CC_PolicyCounterTimer (TPM_CC)(0x0000016D)
+#define TPM_CC_PolicyCpHash (TPM_CC)(0x0000016E)
+#define TPM_CC_PolicyLocality (TPM_CC)(0x0000016F)
+#define TPM_CC_PolicyNameHash (TPM_CC)(0x00000170)
+#define TPM_CC_PolicyOR (TPM_CC)(0x00000171)
+#define TPM_CC_PolicyTicket (TPM_CC)(0x00000172)
+#define TPM_CC_ReadPublic (TPM_CC)(0x00000173)
+#define TPM_CC_RSA_Encrypt (TPM_CC)(0x00000174)
+#define TPM_CC_StartAuthSession (TPM_CC)(0x00000176)
+#define TPM_CC_VerifySignature (TPM_CC)(0x00000177)
+#define TPM_CC_ECC_Parameters (TPM_CC)(0x00000178)
+#define TPM_CC_FirmwareRead (TPM_CC)(0x00000179)
+#define TPM_CC_GetCapability (TPM_CC)(0x0000017A)
+#define TPM_CC_GetRandom (TPM_CC)(0x0000017B)
+#define TPM_CC_GetTestResult (TPM_CC)(0x0000017C)
+#define TPM_CC_Hash (TPM_CC)(0x0000017D)
+#define TPM_CC_PCR_Read (TPM_CC)(0x0000017E)
+#define TPM_CC_PolicyPCR (TPM_CC)(0x0000017F)
+#define TPM_CC_PolicyRestart (TPM_CC)(0x00000180)
+#define TPM_CC_ReadClock (TPM_CC)(0x00000181)
+#define TPM_CC_PCR_Extend (TPM_CC)(0x00000182)
+#define TPM_CC_PCR_SetAuthValue (TPM_CC)(0x00000183)
+#define TPM_CC_NV_Certify (TPM_CC)(0x00000184)
+#define TPM_CC_EventSequenceComplete (TPM_CC)(0x00000185)
+#define TPM_CC_HashSequenceStart (TPM_CC)(0x00000186)
+#define TPM_CC_PolicyPhysicalPresence (TPM_CC)(0x00000187)
+#define TPM_CC_PolicyDuplicationSelect (TPM_CC)(0x00000188)
+#define TPM_CC_PolicyGetDigest (TPM_CC)(0x00000189)
+#define TPM_CC_TestParms (TPM_CC)(0x0000018A)
+#define TPM_CC_Commit (TPM_CC)(0x0000018B)
+#define TPM_CC_PolicyPassword (TPM_CC)(0x0000018C)
+#define TPM_CC_ZGen_2Phase (TPM_CC)(0x0000018D)
+#define TPM_CC_EC_Ephemeral (TPM_CC)(0x0000018E)
+#define TPM_CC_LAST (TPM_CC)(0x0000018E)
+
+// Table 15 - TPM_RC Constants (Actions)
+typedef UINT32 TPM_RC;
+#define TPM_RC_SUCCESS (TPM_RC)(0x000)
+#define TPM_RC_BAD_TAG (TPM_RC)(0x030)
+#define RC_VER1 (TPM_RC)(0x100)
+#define TPM_RC_INITIALIZE (TPM_RC)(RC_VER1 + 0x000)
+#define TPM_RC_FAILURE (TPM_RC)(RC_VER1 + 0x001)
+#define TPM_RC_SEQUENCE (TPM_RC)(RC_VER1 + 0x003)
+#define TPM_RC_PRIVATE (TPM_RC)(RC_VER1 + 0x00B)
+#define TPM_RC_HMAC (TPM_RC)(RC_VER1 + 0x019)
+#define TPM_RC_DISABLED (TPM_RC)(RC_VER1 + 0x020)
+#define TPM_RC_EXCLUSIVE (TPM_RC)(RC_VER1 + 0x021)
+#define TPM_RC_AUTH_TYPE (TPM_RC)(RC_VER1 + 0x024)
+#define TPM_RC_AUTH_MISSING (TPM_RC)(RC_VER1 + 0x025)
+#define TPM_RC_POLICY (TPM_RC)(RC_VER1 + 0x026)
+#define TPM_RC_PCR (TPM_RC)(RC_VER1 + 0x027)
+#define TPM_RC_PCR_CHANGED (TPM_RC)(RC_VER1 + 0x028)
+#define TPM_RC_UPGRADE (TPM_RC)(RC_VER1 + 0x02D)
+#define TPM_RC_TOO_MANY_CONTEXTS (TPM_RC)(RC_VER1 + 0x02E)
+#define TPM_RC_AUTH_UNAVAILABLE (TPM_RC)(RC_VER1 + 0x02F)
+#define TPM_RC_REBOOT (TPM_RC)(RC_VER1 + 0x030)
+#define TPM_RC_UNBALANCED (TPM_RC)(RC_VER1 + 0x031)
+#define TPM_RC_COMMAND_SIZE (TPM_RC)(RC_VER1 + 0x042)
+#define TPM_RC_COMMAND_CODE (TPM_RC)(RC_VER1 + 0x043)
+#define TPM_RC_AUTHSIZE (TPM_RC)(RC_VER1 + 0x044)
+#define TPM_RC_AUTH_CONTEXT (TPM_RC)(RC_VER1 + 0x045)
+#define TPM_RC_NV_RANGE (TPM_RC)(RC_VER1 + 0x046)
+#define TPM_RC_NV_SIZE (TPM_RC)(RC_VER1 + 0x047)
+#define TPM_RC_NV_LOCKED (TPM_RC)(RC_VER1 + 0x048)
+#define TPM_RC_NV_AUTHORIZATION (TPM_RC)(RC_VER1 + 0x049)
+#define TPM_RC_NV_UNINITIALIZED (TPM_RC)(RC_VER1 + 0x04A)
+#define TPM_RC_NV_SPACE (TPM_RC)(RC_VER1 + 0x04B)
+#define TPM_RC_NV_DEFINED (TPM_RC)(RC_VER1 + 0x04C)
+#define TPM_RC_BAD_CONTEXT (TPM_RC)(RC_VER1 + 0x050)
+#define TPM_RC_CPHASH (TPM_RC)(RC_VER1 + 0x051)
+#define TPM_RC_PARENT (TPM_RC)(RC_VER1 + 0x052)
+#define TPM_RC_NEEDS_TEST (TPM_RC)(RC_VER1 + 0x053)
+#define TPM_RC_NO_RESULT (TPM_RC)(RC_VER1 + 0x054)
+#define TPM_RC_SENSITIVE (TPM_RC)(RC_VER1 + 0x055)
+#define RC_MAX_FM0 (TPM_RC)(RC_VER1 + 0x07F)
+#define RC_FMT1 (TPM_RC)(0x080)
+#define TPM_RC_ASYMMETRIC (TPM_RC)(RC_FMT1 + 0x001)
+#define TPM_RC_ATTRIBUTES (TPM_RC)(RC_FMT1 + 0x002)
+#define TPM_RC_HASH (TPM_RC)(RC_FMT1 + 0x003)
+#define TPM_RC_VALUE (TPM_RC)(RC_FMT1 + 0x004)
+#define TPM_RC_HIERARCHY (TPM_RC)(RC_FMT1 + 0x005)
+#define TPM_RC_KEY_SIZE (TPM_RC)(RC_FMT1 + 0x007)
+#define TPM_RC_MGF (TPM_RC)(RC_FMT1 + 0x008)
+#define TPM_RC_MODE (TPM_RC)(RC_FMT1 + 0x009)
+#define TPM_RC_TYPE (TPM_RC)(RC_FMT1 + 0x00A)
+#define TPM_RC_HANDLE (TPM_RC)(RC_FMT1 + 0x00B)
+#define TPM_RC_KDF (TPM_RC)(RC_FMT1 + 0x00C)
+#define TPM_RC_RANGE (TPM_RC)(RC_FMT1 + 0x00D)
+#define TPM_RC_AUTH_FAIL (TPM_RC)(RC_FMT1 + 0x00E)
+#define TPM_RC_NONCE (TPM_RC)(RC_FMT1 + 0x00F)
+#define TPM_RC_PP (TPM_RC)(RC_FMT1 + 0x010)
+#define TPM_RC_SCHEME (TPM_RC)(RC_FMT1 + 0x012)
+#define TPM_RC_SIZE (TPM_RC)(RC_FMT1 + 0x015)
+#define TPM_RC_SYMMETRIC (TPM_RC)(RC_FMT1 + 0x016)
+#define TPM_RC_TAG (TPM_RC)(RC_FMT1 + 0x017)
+#define TPM_RC_SELECTOR (TPM_RC)(RC_FMT1 + 0x018)
+#define TPM_RC_INSUFFICIENT (TPM_RC)(RC_FMT1 + 0x01A)
+#define TPM_RC_SIGNATURE (TPM_RC)(RC_FMT1 + 0x01B)
+#define TPM_RC_KEY (TPM_RC)(RC_FMT1 + 0x01C)
+#define TPM_RC_POLICY_FAIL (TPM_RC)(RC_FMT1 + 0x01D)
+#define TPM_RC_INTEGRITY (TPM_RC)(RC_FMT1 + 0x01F)
+#define TPM_RC_TICKET (TPM_RC)(RC_FMT1 + 0x020)
+#define TPM_RC_RESERVED_BITS (TPM_RC)(RC_FMT1 + 0x021)
+#define TPM_RC_BAD_AUTH (TPM_RC)(RC_FMT1 + 0x022)
+#define TPM_RC_EXPIRED (TPM_RC)(RC_FMT1 + 0x023)
+#define TPM_RC_POLICY_CC (TPM_RC)(RC_FMT1 + 0x024 )
+#define TPM_RC_BINDING (TPM_RC)(RC_FMT1 + 0x025)
+#define TPM_RC_CURVE (TPM_RC)(RC_FMT1 + 0x026)
+#define TPM_RC_ECC_POINT (TPM_RC)(RC_FMT1 + 0x027)
+#define RC_WARN (TPM_RC)(0x900)
+#define TPM_RC_CONTEXT_GAP (TPM_RC)(RC_WARN + 0x001)
+#define TPM_RC_OBJECT_MEMORY (TPM_RC)(RC_WARN + 0x002)
+#define TPM_RC_SESSION_MEMORY (TPM_RC)(RC_WARN + 0x003)
+#define TPM_RC_MEMORY (TPM_RC)(RC_WARN + 0x004)
+#define TPM_RC_SESSION_HANDLES (TPM_RC)(RC_WARN + 0x005)
+#define TPM_RC_OBJECT_HANDLES (TPM_RC)(RC_WARN + 0x006)
+#define TPM_RC_LOCALITY (TPM_RC)(RC_WARN + 0x007)
+#define TPM_RC_YIELDED (TPM_RC)(RC_WARN + 0x008)
+#define TPM_RC_CANCELED (TPM_RC)(RC_WARN + 0x009)
+#define TPM_RC_TESTING (TPM_RC)(RC_WARN + 0x00A)
+#define TPM_RC_REFERENCE_H0 (TPM_RC)(RC_WARN + 0x010)
+#define TPM_RC_REFERENCE_H1 (TPM_RC)(RC_WARN + 0x011)
+#define TPM_RC_REFERENCE_H2 (TPM_RC)(RC_WARN + 0x012)
+#define TPM_RC_REFERENCE_H3 (TPM_RC)(RC_WARN + 0x013)
+#define TPM_RC_REFERENCE_H4 (TPM_RC)(RC_WARN + 0x014)
+#define TPM_RC_REFERENCE_H5 (TPM_RC)(RC_WARN + 0x015)
+#define TPM_RC_REFERENCE_H6 (TPM_RC)(RC_WARN + 0x016)
+#define TPM_RC_REFERENCE_S0 (TPM_RC)(RC_WARN + 0x018)
+#define TPM_RC_REFERENCE_S1 (TPM_RC)(RC_WARN + 0x019)
+#define TPM_RC_REFERENCE_S2 (TPM_RC)(RC_WARN + 0x01A)
+#define TPM_RC_REFERENCE_S3 (TPM_RC)(RC_WARN + 0x01B)
+#define TPM_RC_REFERENCE_S4 (TPM_RC)(RC_WARN + 0x01C)
+#define TPM_RC_REFERENCE_S5 (TPM_RC)(RC_WARN + 0x01D)
+#define TPM_RC_REFERENCE_S6 (TPM_RC)(RC_WARN + 0x01E)
+#define TPM_RC_NV_RATE (TPM_RC)(RC_WARN + 0x020)
+#define TPM_RC_LOCKOUT (TPM_RC)(RC_WARN + 0x021)
+#define TPM_RC_RETRY (TPM_RC)(RC_WARN + 0x022)
+#define TPM_RC_NV_UNAVAILABLE (TPM_RC)(RC_WARN + 0x023)
+#define TPM_RC_NOT_USED (TPM_RC)(RC_WARN + 0x7F)
+#define TPM_RC_H (TPM_RC)(0x000)
+#define TPM_RC_P (TPM_RC)(0x040)
+#define TPM_RC_S (TPM_RC)(0x800)
+#define TPM_RC_1 (TPM_RC)(0x100)
+#define TPM_RC_2 (TPM_RC)(0x200)
+#define TPM_RC_3 (TPM_RC)(0x300)
+#define TPM_RC_4 (TPM_RC)(0x400)
+#define TPM_RC_5 (TPM_RC)(0x500)
+#define TPM_RC_6 (TPM_RC)(0x600)
+#define TPM_RC_7 (TPM_RC)(0x700)
+#define TPM_RC_8 (TPM_RC)(0x800)
+#define TPM_RC_9 (TPM_RC)(0x900)
+#define TPM_RC_A (TPM_RC)(0xA00)
+#define TPM_RC_B (TPM_RC)(0xB00)
+#define TPM_RC_C (TPM_RC)(0xC00)
+#define TPM_RC_D (TPM_RC)(0xD00)
+#define TPM_RC_E (TPM_RC)(0xE00)
+#define TPM_RC_F (TPM_RC)(0xF00)
+#define TPM_RC_N_MASK (TPM_RC)(0xF00)
+
+// Table 16 - TPM_CLOCK_ADJUST Constants
+typedef INT8 TPM_CLOCK_ADJUST;
+#define TPM_CLOCK_COARSE_SLOWER (TPM_CLOCK_ADJUST)(-3)
+#define TPM_CLOCK_MEDIUM_SLOWER (TPM_CLOCK_ADJUST)(-2)
+#define TPM_CLOCK_FINE_SLOWER (TPM_CLOCK_ADJUST)(-1)
+#define TPM_CLOCK_NO_CHANGE (TPM_CLOCK_ADJUST)(0)
+#define TPM_CLOCK_FINE_FASTER (TPM_CLOCK_ADJUST)(1)
+#define TPM_CLOCK_MEDIUM_FASTER (TPM_CLOCK_ADJUST)(2)
+#define TPM_CLOCK_COARSE_FASTER (TPM_CLOCK_ADJUST)(3)
+
+// Table 17 - TPM_EO Constants
+typedef UINT16 TPM_EO;
+#define TPM_EO_EQ (TPM_EO)(0x0000)
+#define TPM_EO_NEQ (TPM_EO)(0x0001)
+#define TPM_EO_SIGNED_GT (TPM_EO)(0x0002)
+#define TPM_EO_UNSIGNED_GT (TPM_EO)(0x0003)
+#define TPM_EO_SIGNED_LT (TPM_EO)(0x0004)
+#define TPM_EO_UNSIGNED_LT (TPM_EO)(0x0005)
+#define TPM_EO_SIGNED_GE (TPM_EO)(0x0006)
+#define TPM_EO_UNSIGNED_GE (TPM_EO)(0x0007)
+#define TPM_EO_SIGNED_LE (TPM_EO)(0x0008)
+#define TPM_EO_UNSIGNED_LE (TPM_EO)(0x0009)
+#define TPM_EO_BITSET (TPM_EO)(0x000A)
+#define TPM_EO_BITCLEAR (TPM_EO)(0x000B)
+
+// Table 18 - TPM_ST Constants
+typedef UINT16 TPM_ST;
+#define TPM_ST_RSP_COMMAND (TPM_ST)(0x00C4)
+#define TPM_ST_NULL (TPM_ST)(0X8000)
+#define TPM_ST_NO_SESSIONS (TPM_ST)(0x8001)
+#define TPM_ST_SESSIONS (TPM_ST)(0x8002)
+#define TPM_ST_ATTEST_NV (TPM_ST)(0x8014)
+#define TPM_ST_ATTEST_COMMAND_AUDIT (TPM_ST)(0x8015)
+#define TPM_ST_ATTEST_SESSION_AUDIT (TPM_ST)(0x8016)
+#define TPM_ST_ATTEST_CERTIFY (TPM_ST)(0x8017)
+#define TPM_ST_ATTEST_QUOTE (TPM_ST)(0x8018)
+#define TPM_ST_ATTEST_TIME (TPM_ST)(0x8019)
+#define TPM_ST_ATTEST_CREATION (TPM_ST)(0x801A)
+#define TPM_ST_CREATION (TPM_ST)(0x8021)
+#define TPM_ST_VERIFIED (TPM_ST)(0x8022)
+#define TPM_ST_AUTH_SECRET (TPM_ST)(0x8023)
+#define TPM_ST_HASHCHECK (TPM_ST)(0x8024)
+#define TPM_ST_AUTH_SIGNED (TPM_ST)(0x8025)
+#define TPM_ST_FU_MANIFEST (TPM_ST)(0x8029)
+
+// Table 19 - TPM_SU Constants
+typedef UINT16 TPM_SU;
+#define TPM_SU_CLEAR (TPM_SU)(0x0000)
+#define TPM_SU_STATE (TPM_SU)(0x0001)
+
+// Table 20 - TPM_SE Constants
+typedef UINT8 TPM_SE;
+#define TPM_SE_HMAC (TPM_SE)(0x00)
+#define TPM_SE_POLICY (TPM_SE)(0x01)
+#define TPM_SE_TRIAL (TPM_SE)(0x03)
+
+// Table 21 - TPM_CAP Constants
+typedef UINT32 TPM_CAP;
+#define TPM_CAP_FIRST (TPM_CAP)(0x00000000)
+#define TPM_CAP_ALGS (TPM_CAP)(0x00000000)
+#define TPM_CAP_HANDLES (TPM_CAP)(0x00000001)
+#define TPM_CAP_COMMANDS (TPM_CAP)(0x00000002)
+#define TPM_CAP_PP_COMMANDS (TPM_CAP)(0x00000003)
+#define TPM_CAP_AUDIT_COMMANDS (TPM_CAP)(0x00000004)
+#define TPM_CAP_PCRS (TPM_CAP)(0x00000005)
+#define TPM_CAP_TPM_PROPERTIES (TPM_CAP)(0x00000006)
+#define TPM_CAP_PCR_PROPERTIES (TPM_CAP)(0x00000007)
+#define TPM_CAP_ECC_CURVES (TPM_CAP)(0x00000008)
+#define TPM_CAP_LAST (TPM_CAP)(0x00000008)
+#define TPM_CAP_VENDOR_PROPERTY (TPM_CAP)(0x00000100)
+
+// Table 22 - TPM_PT Constants
+typedef UINT32 TPM_PT;
+#define TPM_PT_NONE (TPM_PT)(0x00000000)
+#define PT_GROUP (TPM_PT)(0x00000100)
+#define PT_FIXED (TPM_PT)(PT_GROUP * 1)
+#define TPM_PT_FAMILY_INDICATOR (TPM_PT)(PT_FIXED + 0)
+#define TPM_PT_LEVEL (TPM_PT)(PT_FIXED + 1)
+#define TPM_PT_REVISION (TPM_PT)(PT_FIXED + 2)
+#define TPM_PT_DAY_OF_YEAR (TPM_PT)(PT_FIXED + 3)
+#define TPM_PT_YEAR (TPM_PT)(PT_FIXED + 4)
+#define TPM_PT_MANUFACTURER (TPM_PT)(PT_FIXED + 5)
+#define TPM_PT_VENDOR_STRING_1 (TPM_PT)(PT_FIXED + 6)
+#define TPM_PT_VENDOR_STRING_2 (TPM_PT)(PT_FIXED + 7)
+#define TPM_PT_VENDOR_STRING_3 (TPM_PT)(PT_FIXED + 8)
+#define TPM_PT_VENDOR_STRING_4 (TPM_PT)(PT_FIXED + 9)
+#define TPM_PT_VENDOR_TPM_TYPE (TPM_PT)(PT_FIXED + 10)
+#define TPM_PT_FIRMWARE_VERSION_1 (TPM_PT)(PT_FIXED + 11)
+#define TPM_PT_FIRMWARE_VERSION_2 (TPM_PT)(PT_FIXED + 12)
+#define TPM_PT_INPUT_BUFFER (TPM_PT)(PT_FIXED + 13)
+#define TPM_PT_HR_TRANSIENT_MIN (TPM_PT)(PT_FIXED + 14)
+#define TPM_PT_HR_PERSISTENT_MIN (TPM_PT)(PT_FIXED + 15)
+#define TPM_PT_HR_LOADED_MIN (TPM_PT)(PT_FIXED + 16)
+#define TPM_PT_ACTIVE_SESSIONS_MAX (TPM_PT)(PT_FIXED + 17)
+#define TPM_PT_PCR_COUNT (TPM_PT)(PT_FIXED + 18)
+#define TPM_PT_PCR_SELECT_MIN (TPM_PT)(PT_FIXED + 19)
+#define TPM_PT_CONTEXT_GAP_MAX (TPM_PT)(PT_FIXED + 20)
+#define TPM_PT_NV_COUNTERS_MAX (TPM_PT)(PT_FIXED + 22)
+#define TPM_PT_NV_INDEX_MAX (TPM_PT)(PT_FIXED + 23)
+#define TPM_PT_MEMORY (TPM_PT)(PT_FIXED + 24)
+#define TPM_PT_CLOCK_UPDATE (TPM_PT)(PT_FIXED + 25)
+#define TPM_PT_CONTEXT_HASH (TPM_PT)(PT_FIXED + 26)
+#define TPM_PT_CONTEXT_SYM (TPM_PT)(PT_FIXED + 27)
+#define TPM_PT_CONTEXT_SYM_SIZE (TPM_PT)(PT_FIXED + 28)
+#define TPM_PT_ORDERLY_COUNT (TPM_PT)(PT_FIXED + 29)
+#define TPM_PT_MAX_COMMAND_SIZE (TPM_PT)(PT_FIXED + 30)
+#define TPM_PT_MAX_RESPONSE_SIZE (TPM_PT)(PT_FIXED + 31)
+#define TPM_PT_MAX_DIGEST (TPM_PT)(PT_FIXED + 32)
+#define TPM_PT_MAX_OBJECT_CONTEXT (TPM_PT)(PT_FIXED + 33)
+#define TPM_PT_MAX_SESSION_CONTEXT (TPM_PT)(PT_FIXED + 34)
+#define TPM_PT_PS_FAMILY_INDICATOR (TPM_PT)(PT_FIXED + 35)
+#define TPM_PT_PS_LEVEL (TPM_PT)(PT_FIXED + 36)
+#define TPM_PT_PS_REVISION (TPM_PT)(PT_FIXED + 37)
+#define TPM_PT_PS_DAY_OF_YEAR (TPM_PT)(PT_FIXED + 38)
+#define TPM_PT_PS_YEAR (TPM_PT)(PT_FIXED + 39)
+#define TPM_PT_SPLIT_MAX (TPM_PT)(PT_FIXED + 40)
+#define TPM_PT_TOTAL_COMMANDS (TPM_PT)(PT_FIXED + 41)
+#define TPM_PT_LIBRARY_COMMANDS (TPM_PT)(PT_FIXED + 42)
+#define TPM_PT_VENDOR_COMMANDS (TPM_PT)(PT_FIXED + 43)
+#define PT_VAR (TPM_PT)(PT_GROUP * 2)
+#define TPM_PT_PERMANENT (TPM_PT)(PT_VAR + 0)
+#define TPM_PT_STARTUP_CLEAR (TPM_PT)(PT_VAR + 1)
+#define TPM_PT_HR_NV_INDEX (TPM_PT)(PT_VAR + 2)
+#define TPM_PT_HR_LOADED (TPM_PT)(PT_VAR + 3)
+#define TPM_PT_HR_LOADED_AVAIL (TPM_PT)(PT_VAR + 4)
+#define TPM_PT_HR_ACTIVE (TPM_PT)(PT_VAR + 5)
+#define TPM_PT_HR_ACTIVE_AVAIL (TPM_PT)(PT_VAR + 6)
+#define TPM_PT_HR_TRANSIENT_AVAIL (TPM_PT)(PT_VAR + 7)
+#define TPM_PT_HR_PERSISTENT (TPM_PT)(PT_VAR + 8)
+#define TPM_PT_HR_PERSISTENT_AVAIL (TPM_PT)(PT_VAR + 9)
+#define TPM_PT_NV_COUNTERS (TPM_PT)(PT_VAR + 10)
+#define TPM_PT_NV_COUNTERS_AVAIL (TPM_PT)(PT_VAR + 11)
+#define TPM_PT_ALGORITHM_SET (TPM_PT)(PT_VAR + 12)
+#define TPM_PT_LOADED_CURVES (TPM_PT)(PT_VAR + 13)
+#define TPM_PT_LOCKOUT_COUNTER (TPM_PT)(PT_VAR + 14)
+#define TPM_PT_MAX_AUTH_FAIL (TPM_PT)(PT_VAR + 15)
+#define TPM_PT_LOCKOUT_INTERVAL (TPM_PT)(PT_VAR + 16)
+#define TPM_PT_LOCKOUT_RECOVERY (TPM_PT)(PT_VAR + 17)
+#define TPM_PT_NV_WRITE_RECOVERY (TPM_PT)(PT_VAR + 18)
+#define TPM_PT_AUDIT_COUNTER_0 (TPM_PT)(PT_VAR + 19)
+#define TPM_PT_AUDIT_COUNTER_1 (TPM_PT)(PT_VAR + 20)
+
+// Table 23 - TPM_PT_PCR Constants
+typedef UINT32 TPM_PT_PCR;
+#define TPM_PT_PCR_FIRST (TPM_PT_PCR)(0x00000000)
+#define TPM_PT_PCR_SAVE (TPM_PT_PCR)(0x00000000)
+#define TPM_PT_PCR_EXTEND_L0 (TPM_PT_PCR)(0x00000001)
+#define TPM_PT_PCR_RESET_L0 (TPM_PT_PCR)(0x00000002)
+#define TPM_PT_PCR_EXTEND_L1 (TPM_PT_PCR)(0x00000003)
+#define TPM_PT_PCR_RESET_L1 (TPM_PT_PCR)(0x00000004)
+#define TPM_PT_PCR_EXTEND_L2 (TPM_PT_PCR)(0x00000005)
+#define TPM_PT_PCR_RESET_L2 (TPM_PT_PCR)(0x00000006)
+#define TPM_PT_PCR_EXTEND_L3 (TPM_PT_PCR)(0x00000007)
+#define TPM_PT_PCR_RESET_L3 (TPM_PT_PCR)(0x00000008)
+#define TPM_PT_PCR_EXTEND_L4 (TPM_PT_PCR)(0x00000009)
+#define TPM_PT_PCR_RESET_L4 (TPM_PT_PCR)(0x0000000A)
+#define TPM_PT_PCR_NO_INCREMENT (TPM_PT_PCR)(0x00000011)
+#define TPM_PT_PCR_DRTM_RESET (TPM_PT_PCR)(0x00000012)
+#define TPM_PT_PCR_POLICY (TPM_PT_PCR)(0x00000013)
+#define TPM_PT_PCR_AUTH (TPM_PT_PCR)(0x00000014)
+#define TPM_PT_PCR_LAST (TPM_PT_PCR)(0x00000014)
+
+// Table 24 - TPM_PS Constants
+typedef UINT32 TPM_PS;
+#define TPM_PS_MAIN (TPM_PS)(0x00000000)
+#define TPM_PS_PC (TPM_PS)(0x00000001)
+#define TPM_PS_PDA (TPM_PS)(0x00000002)
+#define TPM_PS_CELL_PHONE (TPM_PS)(0x00000003)
+#define TPM_PS_SERVER (TPM_PS)(0x00000004)
+#define TPM_PS_PERIPHERAL (TPM_PS)(0x00000005)
+#define TPM_PS_TSS (TPM_PS)(0x00000006)
+#define TPM_PS_STORAGE (TPM_PS)(0x00000007)
+#define TPM_PS_AUTHENTICATION (TPM_PS)(0x00000008)
+#define TPM_PS_EMBEDDED (TPM_PS)(0x00000009)
+#define TPM_PS_HARDCOPY (TPM_PS)(0x0000000A)
+#define TPM_PS_INFRASTRUCTURE (TPM_PS)(0x0000000B)
+#define TPM_PS_VIRTUALIZATION (TPM_PS)(0x0000000C)
+#define TPM_PS_TNC (TPM_PS)(0x0000000D)
+#define TPM_PS_MULTI_TENANT (TPM_PS)(0x0000000E)
+#define TPM_PS_TC (TPM_PS)(0x0000000F)
+
+// 7 Handles
+
+// Table 25 - Handles Types
+//
+// NOTE: Comment because it has same name as TPM1.2 (value is same, so not runtime issue)
+//
+// typedef UINT32 TPM_HANDLE;
+
+// Table 26 - TPM_HT Constants
+typedef UINT8 TPM_HT;
+#define TPM_HT_PCR (TPM_HT)(0x00)
+#define TPM_HT_NV_INDEX (TPM_HT)(0x01)
+#define TPM_HT_HMAC_SESSION (TPM_HT)(0x02)
+#define TPM_HT_LOADED_SESSION (TPM_HT)(0x02)
+#define TPM_HT_POLICY_SESSION (TPM_HT)(0x03)
+#define TPM_HT_ACTIVE_SESSION (TPM_HT)(0x03)
+#define TPM_HT_PERMANENT (TPM_HT)(0x40)
+#define TPM_HT_TRANSIENT (TPM_HT)(0x80)
+#define TPM_HT_PERSISTENT (TPM_HT)(0x81)
+
+// Table 27 - TPM_RH Constants
+typedef UINT32 TPM_RH;
+#define TPM_RH_FIRST (TPM_RH)(0x40000000)
+#define TPM_RH_SRK (TPM_RH)(0x40000000)
+#define TPM_RH_OWNER (TPM_RH)(0x40000001)
+#define TPM_RH_REVOKE (TPM_RH)(0x40000002)
+#define TPM_RH_TRANSPORT (TPM_RH)(0x40000003)
+#define TPM_RH_OPERATOR (TPM_RH)(0x40000004)
+#define TPM_RH_ADMIN (TPM_RH)(0x40000005)
+#define TPM_RH_EK (TPM_RH)(0x40000006)
+#define TPM_RH_NULL (TPM_RH)(0x40000007)
+#define TPM_RH_UNASSIGNED (TPM_RH)(0x40000008)
+#define TPM_RS_PW (TPM_RH)(0x40000009)
+#define TPM_RH_LOCKOUT (TPM_RH)(0x4000000A)
+#define TPM_RH_ENDORSEMENT (TPM_RH)(0x4000000B)
+#define TPM_RH_PLATFORM (TPM_RH)(0x4000000C)
+#define TPM_RH_PLATFORM_NV (TPM_RH)(0x4000000D)
+#define TPM_RH_AUTH_00 (TPM_RH)(0x40000010)
+#define TPM_RH_AUTH_FF (TPM_RH)(0x4000010F)
+#define TPM_RH_LAST (TPM_RH)(0x4000010F)
+
+// Table 28 - TPM_HC Constants
+typedef TPM_HANDLE TPM_HC;
+#define HR_HANDLE_MASK (TPM_HC)(0x00FFFFFF)
+#define HR_RANGE_MASK (TPM_HC)(0xFF000000)
+#define HR_SHIFT (TPM_HC)(24)
+#define HR_PCR (TPM_HC)((TPM_HC)TPM_HT_PCR << HR_SHIFT)
+#define HR_HMAC_SESSION (TPM_HC)((TPM_HC)TPM_HT_HMAC_SESSION << HR_SHIFT)
+#define HR_POLICY_SESSION (TPM_HC)((TPM_HC)TPM_HT_POLICY_SESSION << HR_SHIFT)
+#define HR_TRANSIENT (TPM_HC)((TPM_HC)TPM_HT_TRANSIENT << HR_SHIFT)
+#define HR_PERSISTENT (TPM_HC)((TPM_HC)TPM_HT_PERSISTENT << HR_SHIFT)
+#define HR_NV_INDEX (TPM_HC)((TPM_HC)TPM_HT_NV_INDEX << HR_SHIFT)
+#define HR_PERMANENT (TPM_HC)((TPM_HC)TPM_HT_PERMANENT << HR_SHIFT)
+#define PCR_FIRST (TPM_HC)(HR_PCR + 0)
+#define PCR_LAST (TPM_HC)(PCR_FIRST + IMPLEMENTATION_PCR - 1)
+#define HMAC_SESSION_FIRST (TPM_HC)(HR_HMAC_SESSION + 0)
+#define HMAC_SESSION_LAST (TPM_HC)(HMAC_SESSION_FIRST + MAX_ACTIVE_SESSIONS - 1)
+#define LOADED_SESSION_FIRST (TPM_HC)(HMAC_SESSION_FIRST)
+#define LOADED_SESSION_LAST (TPM_HC)(HMAC_SESSION_LAST)
+#define POLICY_SESSION_FIRST (TPM_HC)(HR_POLICY_SESSION + 0)
+#define POLICY_SESSION_LAST (TPM_HC)(POLICY_SESSION_FIRST + MAX_ACTIVE_SESSIONS - 1)
+#define TRANSIENT_FIRST (TPM_HC)(HR_TRANSIENT + 0)
+#define ACTIVE_SESSION_FIRST (TPM_HC)(POLICY_SESSION_FIRST)
+#define ACTIVE_SESSION_LAST (TPM_HC)(POLICY_SESSION_LAST)
+#define TRANSIENT_LAST (TPM_HC)(TRANSIENT_FIRST+MAX_LOADED_OBJECTS - 1)
+#define PERSISTENT_FIRST (TPM_HC)(HR_PERSISTENT + 0)
+#define PERSISTENT_LAST (TPM_HC)(PERSISTENT_FIRST + 0x00FFFFFF)
+#define PLATFORM_PERSISTENT (TPM_HC)(PERSISTENT_FIRST + 0x00800000)
+#define NV_INDEX_FIRST (TPM_HC)(HR_NV_INDEX + 0)
+#define NV_INDEX_LAST (TPM_HC)(NV_INDEX_FIRST + 0x00FFFFFF)
+#define PERMANENT_FIRST (TPM_HC)(TPM_RH_FIRST)
+#define PERMANENT_LAST (TPM_HC)(TPM_RH_LAST)
+
+// 8 Attribute Structures
+
+// Table 29 - TPMA_ALGORITHM Bits
+typedef struct {
+ UINT32 asymmetric : 1;
+ UINT32 symmetric : 1;
+ UINT32 hash : 1;
+ UINT32 object : 1;
+ UINT32 reserved4_7 : 4;
+ UINT32 signing : 1;
+ UINT32 encrypting : 1;
+ UINT32 method : 1;
+ UINT32 reserved11_31 : 21;
+} TPMA_ALGORITHM;
+
+// Table 30 - TPMA_OBJECT Bits
+typedef struct {
+ UINT32 reserved1 : 1;
+ UINT32 fixedTPM : 1;
+ UINT32 stClear : 1;
+ UINT32 reserved4 : 1;
+ UINT32 fixedParent : 1;
+ UINT32 sensitiveDataOrigin : 1;
+ UINT32 userWithAuth : 1;
+ UINT32 adminWithPolicy : 1;
+ UINT32 reserved8_9 : 2;
+ UINT32 noDA : 1;
+ UINT32 encryptedDuplication : 1;
+ UINT32 reserved12_15 : 4;
+ UINT32 restricted : 1;
+ UINT32 decrypt : 1;
+ UINT32 sign : 1;
+ UINT32 reserved19_31 : 13;
+} TPMA_OBJECT;
+
+// Table 31 - TPMA_SESSION Bits
+typedef struct {
+ UINT8 continueSession : 1;
+ UINT8 auditExclusive : 1;
+ UINT8 auditReset : 1;
+ UINT8 reserved3_4 : 2;
+ UINT8 decrypt : 1;
+ UINT8 encrypt : 1;
+ UINT8 audit : 1;
+} TPMA_SESSION;
+
+// Table 32 - TPMA_LOCALITY Bits
+//
+// NOTE: Use low case here to resolve conflict
+//
+typedef struct {
+ UINT8 locZero : 1;
+ UINT8 locOne : 1;
+ UINT8 locTwo : 1;
+ UINT8 locThree : 1;
+ UINT8 locFour : 1;
+ UINT8 Extended : 3;
+} TPMA_LOCALITY;
+
+// Table 33 - TPMA_PERMANENT Bits
+typedef struct {
+ UINT32 ownerAuthSet : 1;
+ UINT32 endorsementAuthSet : 1;
+ UINT32 lockoutAuthSet : 1;
+ UINT32 reserved3_7 : 5;
+ UINT32 disableClear : 1;
+ UINT32 inLockout : 1;
+ UINT32 tpmGeneratedEPS : 1;
+ UINT32 reserved11_31 : 21;
+} TPMA_PERMANENT;
+
+// Table 34 - TPMA_STARTUP_CLEAR Bits
+typedef struct {
+ UINT32 phEnable : 1;
+ UINT32 shEnable : 1;
+ UINT32 ehEnable : 1;
+ UINT32 reserved3_30 : 28;
+ UINT32 orderly : 1;
+} TPMA_STARTUP_CLEAR;
+
+// Table 35 - TPMA_MEMORY Bits
+typedef struct {
+ UINT32 sharedRAM : 1;
+ UINT32 sharedNV : 1;
+ UINT32 objectCopiedToRam : 1;
+ UINT32 reserved3_31 : 29;
+} TPMA_MEMORY;
+
+// Table 36 - TPMA_CC Bits
+typedef struct {
+ UINT32 commandIndex : 16;
+ UINT32 reserved16_21 : 6;
+ UINT32 nv : 1;
+ UINT32 extensive : 1;
+ UINT32 flushed : 1;
+ UINT32 cHandles : 3;
+ UINT32 rHandle : 1;
+ UINT32 V : 1;
+ UINT32 Res : 2;
+} TPMA_CC;
+
+// 9 Interface Types
+
+// Table 37 - TPMI_YES_NO Type
+typedef BYTE TPMI_YES_NO;
+
+// Table 38 - TPMI_DH_OBJECT Type
+typedef TPM_HANDLE TPMI_DH_OBJECT;
+
+// Table 39 - TPMI_DH_PERSISTENT Type
+typedef TPM_HANDLE TPMI_DH_PERSISTENT;
+
+// Table 40 - TPMI_DH_ENTITY Type
+typedef TPM_HANDLE TPMI_DH_ENTITY;
+
+// Table 41 - TPMI_DH_PCR Type
+typedef TPM_HANDLE TPMI_DH_PCR;
+
+// Table 42 - TPMI_SH_AUTH_SESSION Type
+typedef TPM_HANDLE TPMI_SH_AUTH_SESSION;
+
+// Table 43 - TPMI_SH_HMAC Type
+typedef TPM_HANDLE TPMI_SH_HMAC;
+
+// Table 44 - TPMI_SH_POLICY Type
+typedef TPM_HANDLE TPMI_SH_POLICY;
+
+// Table 45 - TPMI_DH_CONTEXT Type
+typedef TPM_HANDLE TPMI_DH_CONTEXT;
+
+// Table 46 - TPMI_RH_HIERARCHY Type
+typedef TPM_HANDLE TPMI_RH_HIERARCHY;
+
+// Table 47 - TPMI_RH_HIERARCHY_AUTH Type
+typedef TPM_HANDLE TPMI_RH_HIERARCHY_AUTH;
+
+// Table 48 - TPMI_RH_PLATFORM Type
+typedef TPM_HANDLE TPMI_RH_PLATFORM;
+
+// Table 49 - TPMI_RH_OWNER Type
+typedef TPM_HANDLE TPMI_RH_OWNER;
+
+// Table 50 - TPMI_RH_ENDORSEMENT Type
+typedef TPM_HANDLE TPMI_RH_ENDORSEMENT;
+
+// Table 51 - TPMI_RH_PROVISION Type
+typedef TPM_HANDLE TPMI_RH_PROVISION;
+
+// Table 52 - TPMI_RH_CLEAR Type
+typedef TPM_HANDLE TPMI_RH_CLEAR;
+
+// Table 53 - TPMI_RH_NV_AUTH Type
+typedef TPM_HANDLE TPMI_RH_NV_AUTH;
+
+// Table 54 - TPMI_RH_LOCKOUT Type
+typedef TPM_HANDLE TPMI_RH_LOCKOUT;
+
+// Table 55 - TPMI_RH_NV_INDEX Type
+typedef TPM_HANDLE TPMI_RH_NV_INDEX;
+
+// Table 56 - TPMI_ALG_HASH Type
+typedef TPM_ALG_ID TPMI_ALG_HASH;
+
+// Table 57 - TPMI_ALG_ASYM Type
+typedef TPM_ALG_ID TPMI_ALG_ASYM;
+
+// Table 58 - TPMI_ALG_SYM Type
+typedef TPM_ALG_ID TPMI_ALG_SYM;
+
+// Table 59 - TPMI_ALG_SYM_OBJECT Type
+typedef TPM_ALG_ID TPMI_ALG_SYM_OBJECT;
+
+// Table 60 - TPMI_ALG_SYM_MODE Type
+typedef TPM_ALG_ID TPMI_ALG_SYM_MODE;
+
+// Table 61 - TPMI_ALG_KDF Type
+typedef TPM_ALG_ID TPMI_ALG_KDF;
+
+// Table 62 - TPMI_ALG_SIG_SCHEME Type
+typedef TPM_ALG_ID TPMI_ALG_SIG_SCHEME;
+
+// Table 63 - TPMI_ECC_KEY_EXCHANGE Type
+typedef TPM_ALG_ID TPMI_ECC_KEY_EXCHANGE;
+
+// Table 64 - TPMI_ST_COMMAND_TAG Type
+typedef TPM_ST TPMI_ST_COMMAND_TAG;
+
+// 10 Structure Definitions
+
+// Table 65 - TPMS_ALGORITHM_DESCRIPTION Structure
+typedef struct {
+ TPM_ALG_ID alg;
+ TPMA_ALGORITHM attributes;
+} TPMS_ALGORITHM_DESCRIPTION;
+
+// Table 66 - TPMU_HA Union
+typedef union {
+ BYTE sha1[SHA1_DIGEST_SIZE];
+ BYTE sha256[SHA256_DIGEST_SIZE];
+ BYTE sm3_256[SM3_256_DIGEST_SIZE];
+ BYTE sha384[SHA384_DIGEST_SIZE];
+ BYTE sha512[SHA512_DIGEST_SIZE];
+} TPMU_HA;
+
+// Table 67 - TPMT_HA Structure
+typedef struct {
+ TPMI_ALG_HASH hashAlg;
+ TPMU_HA digest;
+} TPMT_HA;
+
+// Table 68 - TPM2B_DIGEST Structure
+typedef struct {
+ UINT16 size;
+ BYTE buffer[sizeof (TPMU_HA)];
+} TPM2B_DIGEST;
+
+// Table 69 - TPM2B_DATA Structure
+typedef struct {
+ UINT16 size;
+ BYTE buffer[sizeof (TPMT_HA)];
+} TPM2B_DATA;
+
+// Table 70 - TPM2B_NONCE Types
+typedef TPM2B_DIGEST TPM2B_NONCE;
+
+// Table 71 - TPM2B_AUTH Types
+typedef TPM2B_DIGEST TPM2B_AUTH;
+
+// Table 72 - TPM2B_OPERAND Types
+typedef TPM2B_DIGEST TPM2B_OPERAND;
+
+// Table 73 - TPM2B_EVENT Structure
+typedef struct {
+ UINT16 size;
+ BYTE buffer[1024];
+} TPM2B_EVENT;
+
+// Table 74 - TPM2B_MAX_BUFFER Structure
+typedef struct {
+ UINT16 size;
+ BYTE buffer[MAX_DIGEST_BUFFER];
+} TPM2B_MAX_BUFFER;
+
+// Table 75 - TPM2B_MAX_NV_BUFFER Structure
+typedef struct {
+ UINT16 size;
+ BYTE buffer[MAX_NV_INDEX_SIZE];
+} TPM2B_MAX_NV_BUFFER;
+
+// Table 76 - TPM2B_TIMEOUT Structure
+typedef struct {
+ UINT16 size;
+ BYTE buffer[sizeof (UINT64)];
+} TPM2B_TIMEOUT;
+
+// Table 77 -- TPM2B_IV Structure
+typedef struct {
+ UINT16 size;
+ BYTE buffer[MAX_SYM_BLOCK_SIZE];
+} TPM2B_IV;
+
+// Table 78 - TPMU_NAME Union
+typedef union {
+ TPMT_HA digest;
+ TPM_HANDLE handle;
+} TPMU_NAME;
+
+// Table 79 - TPM2B_NAME Structure
+typedef struct {
+ UINT16 size;
+ BYTE name[sizeof (TPMU_NAME)];
+} TPM2B_NAME;
+
+// Table 80 - TPMS_PCR_SELECT Structure
+typedef struct {
+ UINT8 sizeofSelect;
+ BYTE pcrSelect[PCR_SELECT_MAX];
+} TPMS_PCR_SELECT;
+
+// Table 81 - TPMS_PCR_SELECTION Structure
+typedef struct {
+ TPMI_ALG_HASH hash;
+ UINT8 sizeofSelect;
+ BYTE pcrSelect[PCR_SELECT_MAX];
+} TPMS_PCR_SELECTION;
+
+// Table 84 - TPMT_TK_CREATION Structure
+typedef struct {
+ TPM_ST tag;
+ TPMI_RH_HIERARCHY hierarchy;
+ TPM2B_DIGEST digest;
+} TPMT_TK_CREATION;
+
+// Table 85 - TPMT_TK_VERIFIED Structure
+typedef struct {
+ TPM_ST tag;
+ TPMI_RH_HIERARCHY hierarchy;
+ TPM2B_DIGEST digest;
+} TPMT_TK_VERIFIED;
+
+// Table 86 - TPMT_TK_AUTH Structure
+typedef struct {
+ TPM_ST tag;
+ TPMI_RH_HIERARCHY hierarchy;
+ TPM2B_DIGEST digest;
+} TPMT_TK_AUTH;
+
+// Table 87 - TPMT_TK_HASHCHECK Structure
+typedef struct {
+ TPM_ST tag;
+ TPMI_RH_HIERARCHY hierarchy;
+ TPM2B_DIGEST digest;
+} TPMT_TK_HASHCHECK;
+
+// Table 88 - TPMS_ALG_PROPERTY Structure
+typedef struct {
+ TPM_ALG_ID alg;
+ TPMA_ALGORITHM algProperties;
+} TPMS_ALG_PROPERTY;
+
+// Table 89 - TPMS_TAGGED_PROPERTY Structure
+typedef struct {
+ TPM_PT property;
+ UINT32 value;
+} TPMS_TAGGED_PROPERTY;
+
+// Table 90 - TPMS_TAGGED_PCR_SELECT Structure
+typedef struct {
+ TPM_PT tag;
+ UINT8 sizeofSelect;
+ BYTE pcrSelect[PCR_SELECT_MAX];
+} TPMS_TAGGED_PCR_SELECT;
+
+// Table 91 - TPML_CC Structure
+typedef struct {
+ UINT32 count;
+ TPM_CC commandCodes[MAX_CAP_CC];
+} TPML_CC;
+
+// Table 92 - TPML_CCA Structure
+typedef struct {
+ UINT32 count;
+ TPMA_CC commandAttributes[MAX_CAP_CC];
+} TPML_CCA;
+
+// Table 93 - TPML_ALG Structure
+typedef struct {
+ UINT32 count;
+ TPM_ALG_ID algorithms[MAX_ALG_LIST_SIZE];
+} TPML_ALG;
+
+// Table 94 - TPML_HANDLE Structure
+typedef struct {
+ UINT32 count;
+ TPM_HANDLE handle[MAX_CAP_HANDLES];
+} TPML_HANDLE;
+
+// Table 95 - TPML_DIGEST Structure
+typedef struct {
+ UINT32 count;
+ TPM2B_DIGEST digests[8];
+} TPML_DIGEST;
+
+// Table 96 -- TPML_DIGEST_VALUES Structure
+typedef struct {
+ UINT32 count;
+ TPMT_HA digests[HASH_COUNT];
+} TPML_DIGEST_VALUES;
+
+// Table 97 - TPM2B_DIGEST_VALUES Structure
+typedef struct {
+ UINT16 size;
+ BYTE buffer[sizeof (TPML_DIGEST_VALUES)];
+} TPM2B_DIGEST_VALUES;
+
+// Table 98 - TPML_PCR_SELECTION Structure
+typedef struct {
+ UINT32 count;
+ TPMS_PCR_SELECTION pcrSelections[HASH_COUNT];
+} TPML_PCR_SELECTION;
+
+// Table 99 - TPML_ALG_PROPERTY Structure
+typedef struct {
+ UINT32 count;
+ TPMS_ALG_PROPERTY algProperties[MAX_CAP_ALGS];
+} TPML_ALG_PROPERTY;
+
+// Table 100 - TPML_TAGGED_TPM_PROPERTY Structure
+typedef struct {
+ UINT32 count;
+ TPMS_TAGGED_PROPERTY tpmProperty[MAX_TPM_PROPERTIES];
+} TPML_TAGGED_TPM_PROPERTY;
+
+// Table 101 - TPML_TAGGED_PCR_PROPERTY Structure
+typedef struct {
+ UINT32 count;
+ TPMS_TAGGED_PCR_SELECT pcrProperty[MAX_PCR_PROPERTIES];
+} TPML_TAGGED_PCR_PROPERTY;
+
+// Table 102 - TPML_ECC_CURVE Structure
+typedef struct {
+ UINT32 count;
+ TPM_ECC_CURVE eccCurves[MAX_ECC_CURVES];
+} TPML_ECC_CURVE;
+
+// Table 103 - TPMU_CAPABILITIES Union
+typedef union {
+ TPML_ALG_PROPERTY algorithms;
+ TPML_HANDLE handles;
+ TPML_CCA command;
+ TPML_CC ppCommands;
+ TPML_CC auditCommands;
+ TPML_PCR_SELECTION assignedPCR;
+ TPML_TAGGED_TPM_PROPERTY tpmProperties;
+ TPML_TAGGED_PCR_PROPERTY pcrProperties;
+ TPML_ECC_CURVE eccCurves;
+} TPMU_CAPABILITIES;
+
+// Table 104 - TPMS_CAPABILITY_DATA Structure
+typedef struct {
+ TPM_CAP capability;
+ TPMU_CAPABILITIES data;
+} TPMS_CAPABILITY_DATA;
+
+// Table 105 - TPMS_CLOCK_INFO Structure
+typedef struct {
+ UINT64 clock;
+ UINT32 resetCount;
+ UINT32 restartCount;
+ TPMI_YES_NO safe;
+} TPMS_CLOCK_INFO;
+
+// Table 106 - TPMS_TIME_INFO Structure
+typedef struct {
+ UINT64 time;
+ TPMS_CLOCK_INFO clockInfo;
+} TPMS_TIME_INFO;
+
+// Table 107 - TPMS_TIME_ATTEST_INFO Structure
+typedef struct {
+ TPMS_TIME_INFO time;
+ UINT64 firmwareVersion;
+} TPMS_TIME_ATTEST_INFO;
+
+// Table 108 - TPMS_CERTIFY_INFO Structure
+typedef struct {
+ TPM2B_NAME name;
+ TPM2B_NAME qualifiedName;
+} TPMS_CERTIFY_INFO;
+
+// Table 109 - TPMS_QUOTE_INFO Structure
+typedef struct {
+ TPML_PCR_SELECTION pcrSelect;
+ TPM2B_DIGEST pcrDigest;
+} TPMS_QUOTE_INFO;
+
+// Table 110 - TPMS_COMMAND_AUDIT_INFO Structure
+typedef struct {
+ UINT64 auditCounter;
+ TPM_ALG_ID digestAlg;
+ TPM2B_DIGEST auditDigest;
+ TPM2B_DIGEST commandDigest;
+} TPMS_COMMAND_AUDIT_INFO;
+
+// Table 111 - TPMS_SESSION_AUDIT_INFO Structure
+typedef struct {
+ TPMI_YES_NO exclusiveSession;
+ TPM2B_DIGEST sessionDigest;
+} TPMS_SESSION_AUDIT_INFO;
+
+// Table 112 - TPMS_CREATION_INFO Structure
+typedef struct {
+ TPM2B_NAME objectName;
+ TPM2B_DIGEST creationHash;
+} TPMS_CREATION_INFO;
+
+// Table 113 - TPMS_NV_CERTIFY_INFO Structure
+typedef struct {
+ TPM2B_NAME indexName;
+ UINT16 offset;
+ TPM2B_MAX_NV_BUFFER nvContents;
+} TPMS_NV_CERTIFY_INFO;
+
+// Table 114 - TPMI_ST_ATTEST Type
+typedef TPM_ST TPMI_ST_ATTEST;
+
+// Table 115 - TPMU_ATTEST Union
+typedef union {
+ TPMS_CERTIFY_INFO certify;
+ TPMS_CREATION_INFO creation;
+ TPMS_QUOTE_INFO quote;
+ TPMS_COMMAND_AUDIT_INFO commandAudit;
+ TPMS_SESSION_AUDIT_INFO sessionAudit;
+ TPMS_TIME_ATTEST_INFO time;
+ TPMS_NV_CERTIFY_INFO nv;
+} TPMU_ATTEST;
+
+// Table 116 - TPMS_ATTEST Structure
+typedef struct {
+ TPM_GENERATED magic;
+ TPMI_ST_ATTEST type;
+ TPM2B_NAME qualifiedSigner;
+ TPM2B_DATA extraData;
+ TPMS_CLOCK_INFO clockInfo;
+ UINT64 firmwareVersion;
+ TPMU_ATTEST attested;
+} TPMS_ATTEST;
+
+// Table 117 - TPM2B_ATTEST Structure
+typedef struct {
+ UINT16 size;
+ BYTE attestationData[sizeof (TPMS_ATTEST)];
+} TPM2B_ATTEST;
+
+// Table 118 - TPMS_AUTH_COMMAND Structure
+typedef struct {
+ TPMI_SH_AUTH_SESSION sessionHandle;
+ TPM2B_NONCE nonce;
+ TPMA_SESSION sessionAttributes;
+ TPM2B_AUTH hmac;
+} TPMS_AUTH_COMMAND;
+
+// Table 119 - TPMS_AUTH_RESPONSE Structure
+typedef struct {
+ TPM2B_NONCE nonce;
+ TPMA_SESSION sessionAttributes;
+ TPM2B_AUTH hmac;
+} TPMS_AUTH_RESPONSE;
+
+// 11 Algorithm Parameters and Structures
+
+// Table 120 - TPMI_AES_KEY_BITS Type
+typedef TPM_KEY_BITS TPMI_AES_KEY_BITS;
+
+// Table 121 - TPMI_SM4_KEY_BITS Type
+typedef TPM_KEY_BITS TPMI_SM4_KEY_BITS;
+
+// Table 122 - TPMU_SYM_KEY_BITS Union
+typedef union {
+ TPMI_AES_KEY_BITS aes;
+ TPMI_SM4_KEY_BITS SM4;
+ TPM_KEY_BITS sym;
+ TPMI_ALG_HASH xor;
+} TPMU_SYM_KEY_BITS;
+
+// Table 123 - TPMU_SYM_MODE Union
+typedef union {
+ TPMI_ALG_SYM_MODE aes;
+ TPMI_ALG_SYM_MODE SM4;
+ TPMI_ALG_SYM_MODE sym;
+} TPMU_SYM_MODE;
+
+// Table 125 - TPMT_SYM_DEF Structure
+typedef struct {
+ TPMI_ALG_SYM algorithm;
+ TPMU_SYM_KEY_BITS keyBits;
+ TPMU_SYM_MODE mode;
+} TPMT_SYM_DEF;
+
+// Table 126 - TPMT_SYM_DEF_OBJECT Structure
+typedef struct {
+ TPMI_ALG_SYM_OBJECT algorithm;
+ TPMU_SYM_KEY_BITS keyBits;
+ TPMU_SYM_MODE mode;
+} TPMT_SYM_DEF_OBJECT;
+
+// Table 127 - TPM2B_SYM_KEY Structure
+typedef struct {
+ UINT16 size;
+ BYTE buffer[MAX_SYM_KEY_BYTES];
+} TPM2B_SYM_KEY;
+
+// Table 128 - TPMS_SYMCIPHER_PARMS Structure
+typedef struct {
+ TPMT_SYM_DEF_OBJECT sym;
+} TPMS_SYMCIPHER_PARMS;
+
+// Table 129 - TPM2B_SENSITIVE_DATA Structure
+typedef struct {
+ UINT16 size;
+ BYTE buffer[MAX_SYM_DATA];
+} TPM2B_SENSITIVE_DATA;
+
+// Table 130 - TPMS_SENSITIVE_CREATE Structure
+typedef struct {
+ TPM2B_AUTH userAuth;
+ TPM2B_SENSITIVE_DATA data;
+} TPMS_SENSITIVE_CREATE;
+
+// Table 131 - TPM2B_SENSITIVE_CREATE Structure
+typedef struct {
+ UINT16 size;
+ TPMS_SENSITIVE_CREATE sensitive;
+} TPM2B_SENSITIVE_CREATE;
+
+// Table 132 - TPMS_SCHEME_SIGHASH Structure
+typedef struct {
+ TPMI_ALG_HASH hashAlg;
+} TPMS_SCHEME_SIGHASH;
+
+// Table 133 - TPMI_ALG_KEYEDHASH_SCHEME Type
+typedef TPM_ALG_ID TPMI_ALG_KEYEDHASH_SCHEME;
+
+// Table 134 - HMAC_SIG_SCHEME Types
+typedef TPMS_SCHEME_SIGHASH TPMS_SCHEME_HMAC;
+
+// Table 135 - TPMS_SCHEME_XOR Structure
+typedef struct {
+ TPMI_ALG_HASH hashAlg;
+ TPMI_ALG_KDF kdf;
+} TPMS_SCHEME_XOR;
+
+// Table 136 - TPMU_SCHEME_KEYEDHASH Union
+typedef union {
+ TPMS_SCHEME_HMAC hmac;
+ TPMS_SCHEME_XOR xor;
+} TPMU_SCHEME_KEYEDHASH;
+
+// Table 137 - TPMT_KEYEDHASH_SCHEME Structure
+typedef struct {
+ TPMI_ALG_KEYEDHASH_SCHEME scheme;
+ TPMU_SCHEME_KEYEDHASH details;
+} TPMT_KEYEDHASH_SCHEME;
+
+// Table 138 - RSA_SIG_SCHEMES Types
+typedef TPMS_SCHEME_SIGHASH TPMS_SCHEME_RSASSA;
+typedef TPMS_SCHEME_SIGHASH TPMS_SCHEME_RSAPSS;
+
+// Table 139 - ECC_SIG_SCHEMES Types
+typedef TPMS_SCHEME_SIGHASH TPMS_SCHEME_ECDSA;
+typedef TPMS_SCHEME_SIGHASH TPMS_SCHEME_SM2;
+typedef TPMS_SCHEME_SIGHASH TPMS_SCHEME_ECSCHNORR;
+
+// Table 140 - TPMS_SCHEME_ECDAA Structure
+typedef struct {
+ TPMI_ALG_HASH hashAlg;
+ UINT16 count;
+} TPMS_SCHEME_ECDAA;
+
+// Table 141 - TPMU_SIG_SCHEME Union
+typedef union {
+ TPMS_SCHEME_RSASSA rsassa;
+ TPMS_SCHEME_RSAPSS rsapss;
+ TPMS_SCHEME_ECDSA ecdsa;
+ TPMS_SCHEME_ECDAA ecdaa;
+ TPMS_SCHEME_ECSCHNORR ecSchnorr;
+ TPMS_SCHEME_HMAC hmac;
+ TPMS_SCHEME_SIGHASH any;
+} TPMU_SIG_SCHEME;
+
+// Table 142 - TPMT_SIG_SCHEME Structure
+typedef struct {
+ TPMI_ALG_SIG_SCHEME scheme;
+ TPMU_SIG_SCHEME details;
+} TPMT_SIG_SCHEME;
+
+// Table 143 - TPMS_SCHEME_OAEP Structure
+typedef struct {
+ TPMI_ALG_HASH hashAlg;
+} TPMS_SCHEME_OAEP;
+
+// Table 144 - TPMS_SCHEME_ECDH Structure
+typedef struct {
+ TPMI_ALG_HASH hashAlg;
+} TPMS_SCHEME_ECDH;
+
+// Table 145 - TPMS_SCHEME_MGF1 Structure
+typedef struct {
+ TPMI_ALG_HASH hashAlg;
+} TPMS_SCHEME_MGF1;
+
+// Table 146 - TPMS_SCHEME_KDF1_SP800_56a Structure
+typedef struct {
+ TPMI_ALG_HASH hashAlg;
+} TPMS_SCHEME_KDF1_SP800_56a;
+
+// Table 147 - TPMS_SCHEME_KDF2 Structure
+typedef struct {
+ TPMI_ALG_HASH hashAlg;
+} TPMS_SCHEME_KDF2;
+
+// Table 148 - TPMS_SCHEME_KDF1_SP800_108 Structure
+typedef struct {
+ TPMI_ALG_HASH hashAlg;
+} TPMS_SCHEME_KDF1_SP800_108;
+
+// Table 149 - TPMU_KDF_SCHEME Union
+typedef union {
+ TPMS_SCHEME_MGF1 mgf1;
+ TPMS_SCHEME_KDF1_SP800_56a kdf1_SP800_56a;
+ TPMS_SCHEME_KDF2 kdf2;
+ TPMS_SCHEME_KDF1_SP800_108 kdf1_sp800_108;
+} TPMU_KDF_SCHEME;
+
+// Table 150 - TPMT_KDF_SCHEME Structure
+typedef struct {
+ TPMI_ALG_KDF scheme;
+ TPMU_KDF_SCHEME details;
+} TPMT_KDF_SCHEME;
+
+// Table 151 - TPMI_ALG_ASYM_SCHEME Type
+typedef TPM_ALG_ID TPMI_ALG_ASYM_SCHEME;
+
+// Table 152 - TPMU_ASYM_SCHEME Union
+typedef union {
+ TPMS_SCHEME_RSASSA rsassa;
+ TPMS_SCHEME_RSAPSS rsapss;
+ TPMS_SCHEME_OAEP oaep;
+ TPMS_SCHEME_ECDSA ecdsa;
+ TPMS_SCHEME_ECDAA ecdaa;
+ TPMS_SCHEME_ECSCHNORR ecSchnorr;
+ TPMS_SCHEME_SIGHASH anySig;
+} TPMU_ASYM_SCHEME;
+
+// Table 153 - TPMT_ASYM_SCHEME Structure
+typedef struct {
+ TPMI_ALG_ASYM_SCHEME scheme;
+ TPMU_ASYM_SCHEME details;
+} TPMT_ASYM_SCHEME;
+
+// Table 154 - TPMI_ALG_RSA_SCHEME Type
+typedef TPM_ALG_ID TPMI_ALG_RSA_SCHEME;
+
+// Table 155 - TPMT_RSA_SCHEME Structure
+typedef struct {
+ TPMI_ALG_RSA_SCHEME scheme;
+ TPMU_ASYM_SCHEME details;
+} TPMT_RSA_SCHEME;
+
+// Table 156 - TPMI_ALG_RSA_DECRYPT Type
+typedef TPM_ALG_ID TPMI_ALG_RSA_DECRYPT;
+
+// Table 157 - TPMT_RSA_DECRYPT Structure
+typedef struct {
+ TPMI_ALG_RSA_DECRYPT scheme;
+ TPMU_ASYM_SCHEME details;
+} TPMT_RSA_DECRYPT;
+
+// Table 158 - TPM2B_PUBLIC_KEY_RSA Structure
+typedef struct {
+ UINT16 size;
+ BYTE buffer[MAX_RSA_KEY_BYTES];
+} TPM2B_PUBLIC_KEY_RSA;
+
+// Table 159 - TPMI_RSA_KEY_BITS Type
+typedef TPM_KEY_BITS TPMI_RSA_KEY_BITS;
+
+// Table 160 - TPM2B_PRIVATE_KEY_RSA Structure
+typedef struct {
+ UINT16 size;
+ BYTE buffer[MAX_RSA_KEY_BYTES/2];
+} TPM2B_PRIVATE_KEY_RSA;
+
+// Table 161 - TPM2B_ECC_PARAMETER Structure
+typedef struct {
+ UINT16 size;
+ BYTE buffer[MAX_ECC_KEY_BYTES];
+} TPM2B_ECC_PARAMETER;
+
+// Table 162 - TPMS_ECC_POINT Structure
+typedef struct {
+ TPM2B_ECC_PARAMETER x;
+ TPM2B_ECC_PARAMETER y;
+} TPMS_ECC_POINT;
+
+// Table 163 -- TPM2B_ECC_POINT Structure
+typedef struct {
+ UINT16 size;
+ TPMS_ECC_POINT point;
+} TPM2B_ECC_POINT;
+
+// Table 164 - TPMI_ALG_ECC_SCHEME Type
+typedef TPM_ALG_ID TPMI_ALG_ECC_SCHEME;
+
+// Table 165 - TPMI_ECC_CURVE Type
+typedef TPM_ECC_CURVE TPMI_ECC_CURVE;
+
+// Table 166 - TPMT_ECC_SCHEME Structure
+typedef struct {
+ TPMI_ALG_ECC_SCHEME scheme;
+ TPMU_SIG_SCHEME details;
+} TPMT_ECC_SCHEME;
+
+// Table 167 - TPMS_ALGORITHM_DETAIL_ECC Structure
+typedef struct {
+ TPM_ECC_CURVE curveID;
+ UINT16 keySize;
+ TPMT_KDF_SCHEME kdf;
+ TPMT_ECC_SCHEME sign;
+ TPM2B_ECC_PARAMETER p;
+ TPM2B_ECC_PARAMETER a;
+ TPM2B_ECC_PARAMETER b;
+ TPM2B_ECC_PARAMETER gX;
+ TPM2B_ECC_PARAMETER gY;
+ TPM2B_ECC_PARAMETER n;
+ TPM2B_ECC_PARAMETER h;
+} TPMS_ALGORITHM_DETAIL_ECC;
+
+// Table 168 - TPMS_SIGNATURE_RSASSA Structure
+typedef struct {
+ TPMI_ALG_HASH hash;
+ TPM2B_PUBLIC_KEY_RSA sig;
+} TPMS_SIGNATURE_RSASSA;
+
+// Table 169 - TPMS_SIGNATURE_RSAPSS Structure
+typedef struct {
+ TPMI_ALG_HASH hash;
+ TPM2B_PUBLIC_KEY_RSA sig;
+} TPMS_SIGNATURE_RSAPSS;
+
+// Table 170 - TPMS_SIGNATURE_ECDSA Structure
+typedef struct {
+ TPMI_ALG_HASH hash;
+ TPM2B_ECC_PARAMETER signatureR;
+ TPM2B_ECC_PARAMETER signatureS;
+} TPMS_SIGNATURE_ECDSA;
+
+// Table 171 - TPMU_SIGNATURE Union
+typedef union {
+ TPMS_SIGNATURE_RSASSA rsassa;
+ TPMS_SIGNATURE_RSAPSS rsapss;
+ TPMS_SIGNATURE_ECDSA ecdsa;
+ TPMS_SIGNATURE_ECDSA sm2;
+ TPMS_SIGNATURE_ECDSA ecdaa;
+ TPMS_SIGNATURE_ECDSA ecschnorr;
+ TPMT_HA hmac;
+ TPMS_SCHEME_SIGHASH any;
+} TPMU_SIGNATURE;
+
+// Table 172 - TPMT_SIGNATURE Structure
+typedef struct {
+ TPMI_ALG_SIG_SCHEME sigAlg;
+ TPMU_SIGNATURE signature;
+} TPMT_SIGNATURE;
+
+// Table 173 - TPMU_ENCRYPTED_SECRET Union
+typedef union {
+ BYTE ecc[sizeof (TPMS_ECC_POINT)];
+ BYTE rsa[MAX_RSA_KEY_BYTES];
+ BYTE symmetric[sizeof (TPM2B_DIGEST)];
+ BYTE keyedHash[sizeof (TPM2B_DIGEST)];
+} TPMU_ENCRYPTED_SECRET;
+
+// Table 174 - TPM2B_ENCRYPTED_SECRET Structure
+typedef struct {
+ UINT16 size;
+ BYTE secret[sizeof (TPMU_ENCRYPTED_SECRET)];
+} TPM2B_ENCRYPTED_SECRET;
+
+// 12 Key/Object Complex
+
+// Table 175 - TPMI_ALG_PUBLIC Type
+typedef TPM_ALG_ID TPMI_ALG_PUBLIC;
+
+// Table 176 - TPMU_PUBLIC_ID Union
+typedef union {
+ TPM2B_DIGEST keyedHash;
+ TPM2B_DIGEST sym;
+ TPM2B_PUBLIC_KEY_RSA rsa;
+ TPMS_ECC_POINT ecc;
+} TPMU_PUBLIC_ID;
+
+// Table 177 - TPMS_KEYEDHASH_PARMS Structure
+typedef struct {
+ TPMT_KEYEDHASH_SCHEME scheme;
+} TPMS_KEYEDHASH_PARMS;
+
+// Table 178 - TPMS_ASYM_PARMS Structure
+typedef struct {
+ TPMT_SYM_DEF_OBJECT symmetric;
+ TPMT_ASYM_SCHEME scheme;
+} TPMS_ASYM_PARMS;
+
+// Table 179 - TPMS_RSA_PARMS Structure
+typedef struct {
+ TPMT_SYM_DEF_OBJECT symmetric;
+ TPMT_RSA_SCHEME scheme;
+ TPMI_RSA_KEY_BITS keyBits;
+ UINT32 exponent;
+} TPMS_RSA_PARMS;
+
+// Table 180 - TPMS_ECC_PARMS Structure
+typedef struct {
+ TPMT_SYM_DEF_OBJECT symmetric;
+ TPMT_ECC_SCHEME scheme;
+ TPMI_ECC_CURVE curveID;
+ TPMT_KDF_SCHEME kdf;
+} TPMS_ECC_PARMS;
+
+// Table 181 - TPMU_PUBLIC_PARMS Union
+typedef union {
+ TPMS_KEYEDHASH_PARMS keyedHashDetail;
+ TPMT_SYM_DEF_OBJECT symDetail;
+ TPMS_RSA_PARMS rsaDetail;
+ TPMS_ECC_PARMS eccDetail;
+ TPMS_ASYM_PARMS asymDetail;
+} TPMU_PUBLIC_PARMS;
+
+// Table 182 - TPMT_PUBLIC_PARMS Structure
+typedef struct {
+ TPMI_ALG_PUBLIC type;
+ TPMU_PUBLIC_PARMS parameters;
+} TPMT_PUBLIC_PARMS;
+
+// Table 183 - TPMT_PUBLIC Structure
+typedef struct {
+ TPMI_ALG_PUBLIC type;
+ TPMI_ALG_HASH nameAlg;
+ TPMA_OBJECT objectAttributes;
+ TPM2B_DIGEST authPolicy;
+ TPMU_PUBLIC_PARMS parameters;
+ TPMU_PUBLIC_ID unique;
+} TPMT_PUBLIC;
+
+// Table 184 - TPM2B_PUBLIC Structure
+typedef struct {
+ UINT16 size;
+ TPMT_PUBLIC publicArea;
+} TPM2B_PUBLIC;
+
+// Table 185 - TPM2B_PRIVATE_VENDOR_SPECIFIC Structure
+typedef struct {
+ UINT16 size;
+ BYTE buffer[PRIVATE_VENDOR_SPECIFIC_BYTES];
+} TPM2B_PRIVATE_VENDOR_SPECIFIC;
+
+// Table 186 - TPMU_SENSITIVE_COMPOSITE Union
+typedef union {
+ TPM2B_PRIVATE_KEY_RSA rsa;
+ TPM2B_ECC_PARAMETER ecc;
+ TPM2B_SENSITIVE_DATA bits;
+ TPM2B_SYM_KEY sym;
+ TPM2B_PRIVATE_VENDOR_SPECIFIC any;
+} TPMU_SENSITIVE_COMPOSITE;
+
+// Table 187 - TPMT_SENSITIVE Structure
+typedef struct {
+ TPMI_ALG_PUBLIC sensitiveType;
+ TPM2B_AUTH authValue;
+ TPM2B_DIGEST seedValue;
+ TPMU_SENSITIVE_COMPOSITE sensitive;
+} TPMT_SENSITIVE;
+
+// Table 188 - TPM2B_SENSITIVE Structure
+typedef struct {
+ UINT16 size;
+ TPMT_SENSITIVE sensitiveArea;
+} TPM2B_SENSITIVE;
+
+// Table 189 - _PRIVATE Structure
+typedef struct {
+ TPM2B_DIGEST integrityOuter;
+ TPM2B_DIGEST integrityInner;
+ TPMT_SENSITIVE sensitive;
+} _PRIVATE;
+
+// Table 190 - TPM2B_PRIVATE Structure
+typedef struct {
+ UINT16 size;
+ BYTE buffer[sizeof (_PRIVATE)];
+} TPM2B_PRIVATE;
+
+// Table 191 - _ID_OBJECT Structure
+typedef struct {
+ TPM2B_DIGEST integrityHMAC;
+ TPM2B_DIGEST encIdentity;
+} _ID_OBJECT;
+
+// Table 192 - TPM2B_ID_OBJECT Structure
+typedef struct {
+ UINT16 size;
+ BYTE credential[sizeof (_ID_OBJECT)];
+} TPM2B_ID_OBJECT;
+
+// 13 NV Storage Structures
+
+// Table 193 - TPM_NV_INDEX Bits
+//
+// NOTE: Comment here to resolve conflict
+//
+// typedef struct {
+// UINT32 index : 22;
+// UINT32 space : 2;
+// UINT32 RH_NV : 8;
+// } TPM_NV_INDEX;
+
+// Table 195 - TPMA_NV Bits
+typedef struct {
+ UINT32 TPMA_NV_PPWRITE : 1;
+ UINT32 TPMA_NV_OWNERWRITE : 1;
+ UINT32 TPMA_NV_AUTHWRITE : 1;
+ UINT32 TPMA_NV_POLICYWRITE : 1;
+ UINT32 TPMA_NV_COUNTER : 1;
+ UINT32 TPMA_NV_BITS : 1;
+ UINT32 TPMA_NV_EXTEND : 1;
+ UINT32 reserved7_9 : 3;
+ UINT32 TPMA_NV_POLICY_DELETE : 1;
+ UINT32 TPMA_NV_WRITELOCKED : 1;
+ UINT32 TPMA_NV_WRITEALL : 1;
+ UINT32 TPMA_NV_WRITEDEFINE : 1;
+ UINT32 TPMA_NV_WRITE_STCLEAR : 1;
+ UINT32 TPMA_NV_GLOBALLOCK : 1;
+ UINT32 TPMA_NV_PPREAD : 1;
+ UINT32 TPMA_NV_OWNERREAD : 1;
+ UINT32 TPMA_NV_AUTHREAD : 1;
+ UINT32 TPMA_NV_POLICYREAD : 1;
+ UINT32 reserved20_24 : 5;
+ UINT32 TPMA_NV_NO_DA : 1;
+ UINT32 TPMA_NV_ORDERLY : 1;
+ UINT32 TPMA_NV_CLEAR_STCLEAR : 1;
+ UINT32 TPMA_NV_READLOCKED : 1;
+ UINT32 TPMA_NV_WRITTEN : 1;
+ UINT32 TPMA_NV_PLATFORMCREATE : 1;
+ UINT32 TPMA_NV_READ_STCLEAR : 1;
+} TPMA_NV;
+
+// Table 196 - TPMS_NV_PUBLIC Structure
+typedef struct {
+ TPMI_RH_NV_INDEX nvIndex;
+ TPMI_ALG_HASH nameAlg;
+ TPMA_NV attributes;
+ TPM2B_DIGEST authPolicy;
+ UINT16 dataSize;
+} TPMS_NV_PUBLIC;
+
+// Table 197 - TPM2B_NV_PUBLIC Structure
+typedef struct {
+ UINT16 size;
+ TPMS_NV_PUBLIC nvPublic;
+} TPM2B_NV_PUBLIC;
+
+// 14 Context Data
+
+// Table 198 - TPM2B_CONTEXT_SENSITIVE Structure
+typedef struct {
+ UINT16 size;
+ BYTE buffer[MAX_CONTEXT_SIZE];
+} TPM2B_CONTEXT_SENSITIVE;
+
+// Table 199 - TPMS_CONTEXT_DATA Structure
+typedef struct {
+ TPM2B_DIGEST integrity;
+ TPM2B_CONTEXT_SENSITIVE encrypted;
+} TPMS_CONTEXT_DATA;
+
+// Table 200 - TPM2B_CONTEXT_DATA Structure
+typedef struct {
+ UINT16 size;
+ BYTE buffer[sizeof (TPMS_CONTEXT_DATA)];
+} TPM2B_CONTEXT_DATA;
+
+// Table 201 - TPMS_CONTEXT Structure
+typedef struct {
+ UINT64 sequence;
+ TPMI_DH_CONTEXT savedHandle;
+ TPMI_RH_HIERARCHY hierarchy;
+ TPM2B_CONTEXT_DATA contextBlob;
+} TPMS_CONTEXT;
+
+// 15 Creation Data
+
+// Table 203 - TPMS_CREATION_DATA Structure
+typedef struct {
+ TPML_PCR_SELECTION pcrSelect;
+ TPM2B_DIGEST pcrDigest;
+ TPMA_LOCALITY locality;
+ TPM_ALG_ID parentNameAlg;
+ TPM2B_NAME parentName;
+ TPM2B_NAME parentQualifiedName;
+ TPM2B_DATA outsideInfo;
+} TPMS_CREATION_DATA;
+
+// Table 204 - TPM2B_CREATION_DATA Structure
+typedef struct {
+ UINT16 size;
+ TPMS_CREATION_DATA creationData;
+} TPM2B_CREATION_DATA;
+
+//
+// Command Header
+//
+typedef struct {
+ TPM_ST tag;
+ UINT32 paramSize;
+ TPM_CC commandCode;
+} TPM2_COMMAND_HEADER;
+
+typedef struct {
+ TPM_ST tag;
+ UINT32 paramSize;
+ TPM_RC responseCode;
+} TPM2_RESPONSE_HEADER;
+
+#pragma pack ()
+
+//
+// TCG Algorithm Registry
+//
+#define HASH_ALG_SHA1 0x00000001
+#define HASH_ALG_SHA256 0x00000002
+#define HASH_ALG_SHA384 0x00000004
+#define HASH_ALG_SHA512 0x00000008
+#define HASH_ALG_SM3_256 0x00000010
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/Tpm2Acpi.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/Tpm2Acpi.h
new file mode 100644
index 0000000000..63d4133dee
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/Tpm2Acpi.h
@@ -0,0 +1,66 @@
+/** @file
+ TPM2 ACPI table definition.
+
+Copyright (c) 2013 - 2019, Intel Corporation. All rights reserved.
+Copyright (c) 2021, Ampere Computing LLC. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _TPM2_ACPI_H_
+#define _TPM2_ACPI_H_
+
+#include
+
+#pragma pack (1)
+
+#define EFI_TPM2_ACPI_TABLE_REVISION_3 3
+#define EFI_TPM2_ACPI_TABLE_REVISION_4 4
+#define EFI_TPM2_ACPI_TABLE_REVISION EFI_TPM2_ACPI_TABLE_REVISION_4
+
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ // Flags field is replaced in version 4 and above
+ // BIT0~15: PlatformClass This field is only valid for version 4 and above
+ // BIT16~31: Reserved
+ UINT32 Flags;
+ UINT64 AddressOfControlArea;
+ UINT32 StartMethod;
+ // UINT8 PlatformSpecificParameters[]; // size up to 12
+ // UINT32 Laml; // Optional
+ // UINT64 Lasa; // Optional
+} EFI_TPM2_ACPI_TABLE;
+
+#define EFI_TPM2_ACPI_TABLE_START_METHOD_ACPI 2
+#define EFI_TPM2_ACPI_TABLE_START_METHOD_TIS 6
+#define EFI_TPM2_ACPI_TABLE_START_METHOD_COMMAND_RESPONSE_BUFFER_INTERFACE 7
+#define EFI_TPM2_ACPI_TABLE_START_METHOD_COMMAND_RESPONSE_BUFFER_INTERFACE_WITH_ACPI 8
+#define EFI_TPM2_ACPI_TABLE_START_METHOD_COMMAND_RESPONSE_BUFFER_INTERFACE_WITH_SMC 11
+
+typedef struct {
+ UINT32 Reserved;
+ UINT32 Error;
+ UINT32 Cancel;
+ UINT32 Start;
+ UINT64 InterruptControl;
+ UINT32 CommandSize;
+ UINT64 Command;
+ UINT32 ResponseSize;
+ UINT64 Response;
+} EFI_TPM2_ACPI_CONTROL_AREA;
+
+//
+// Start Method Specific Parameters for ARM SMC Start Method (11)
+// Refer to Table 9: Start Method Specific Parameters for ARM SMC
+//
+typedef struct {
+ UINT32 Interrupt;
+ UINT8 Flags;
+ UINT8 OperationFlags;
+ UINT8 Reserved[2];
+ UINT32 SmcFunctionId;
+} EFI_TPM2_ACPI_START_METHOD_SPECIFIC_PARAMETERS_ARM_SMC;
+
+#pragma pack ()
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/TpmPtp.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/TpmPtp.h
new file mode 100644
index 0000000000..1846b8c591
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/TpmPtp.h
@@ -0,0 +1,515 @@
+/** @file
+ Platform TPM Profile Specification definition for TPM2.0.
+ It covers both FIFO and CRB interface.
+
+Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _TPM_PTP_H_
+#define _TPM_PTP_H_
+
+//
+// PTP FIFO definition
+//
+
+//
+// Set structure alignment to 1-byte
+//
+#pragma pack (1)
+
+//
+// Register set map as specified in PTP specification Chapter 5
+//
+typedef struct {
+ ///
+ /// Used to gain ownership for this particular port.
+ ///
+ UINT8 Access; // 0
+ UINT8 Reserved1[7]; // 1
+ ///
+ /// Controls interrupts.
+ ///
+ UINT32 IntEnable; // 8
+ ///
+ /// SIRQ vector to be used by the TPM.
+ ///
+ UINT8 IntVector; // 0ch
+ UINT8 Reserved2[3]; // 0dh
+ ///
+ /// What caused interrupt.
+ ///
+ UINT32 IntSts; // 10h
+ ///
+ /// Shows which interrupts are supported by that particular TPM.
+ ///
+ UINT32 InterfaceCapability; // 14h
+ ///
+ /// Status Register. Provides status of the TPM.
+ ///
+ UINT8 Status; // 18h
+ ///
+ /// Number of consecutive writes that can be done to the TPM.
+ ///
+ UINT16 BurstCount; // 19h
+ ///
+ /// Additional Status Register.
+ ///
+ UINT8 StatusEx; // 1Bh
+ UINT8 Reserved3[8];
+ ///
+ /// Read or write FIFO, depending on transaction.
+ ///
+ UINT32 DataFifo; // 24h
+ UINT8 Reserved4[8]; // 28h
+ ///
+ /// Used to identify the Interface types supported by the TPM.
+ ///
+ UINT32 InterfaceId; // 30h
+ UINT8 Reserved5[0x4c]; // 34h
+ ///
+ /// Extended ReadFIFO or WriteFIFO, depending on the current bus cycle (read or write)
+ ///
+ UINT32 XDataFifo; // 80h
+ UINT8 Reserved6[0xe7c]; // 84h
+ ///
+ /// Vendor ID
+ ///
+ UINT16 Vid; // 0f00h
+ ///
+ /// Device ID
+ ///
+ UINT16 Did; // 0f02h
+ ///
+ /// Revision ID
+ ///
+ UINT8 Rid; // 0f04h
+ UINT8 Reserved[0xfb]; // 0f05h
+} PTP_FIFO_REGISTERS;
+
+//
+// Restore original structure alignment
+//
+#pragma pack ()
+
+//
+// Define pointer types used to access TIS registers on PC
+//
+typedef PTP_FIFO_REGISTERS *PTP_FIFO_REGISTERS_PTR;
+
+//
+// Define bits of FIFO Interface Identifier Register
+//
+typedef union {
+ struct {
+ UINT32 InterfaceType : 4;
+ UINT32 InterfaceVersion : 4;
+ UINT32 CapLocality : 1;
+ UINT32 Reserved1 : 2;
+ UINT32 CapDataXferSizeSupport : 2;
+ UINT32 CapFIFO : 1;
+ UINT32 CapCRB : 1;
+ UINT32 CapIFRes : 2;
+ UINT32 InterfaceSelector : 2;
+ UINT32 IntfSelLock : 1;
+ UINT32 Reserved2 : 4;
+ UINT32 Reserved3 : 8;
+ } Bits;
+ UINT32 Uint32;
+} PTP_FIFO_INTERFACE_IDENTIFIER;
+
+//
+// Define bits of FIFO Interface Capability Register
+//
+typedef union {
+ struct {
+ UINT32 DataAvailIntSupport : 1;
+ UINT32 StsValidIntSupport : 1;
+ UINT32 LocalityChangeIntSupport : 1;
+ UINT32 InterruptLevelHigh : 1;
+ UINT32 InterruptLevelLow : 1;
+ UINT32 InterruptEdgeRising : 1;
+ UINT32 InterruptEdgeFalling : 1;
+ UINT32 CommandReadyIntSupport : 1;
+ UINT32 BurstCountStatic : 1;
+ UINT32 DataTransferSizeSupport : 2;
+ UINT32 Reserved : 17;
+ UINT32 InterfaceVersion : 3;
+ UINT32 Reserved2 : 1;
+ } Bits;
+ UINT32 Uint32;
+} PTP_FIFO_INTERFACE_CAPABILITY;
+
+///
+/// InterfaceVersion
+///
+#define INTERFACE_CAPABILITY_INTERFACE_VERSION_TIS_12 0x0
+#define INTERFACE_CAPABILITY_INTERFACE_VERSION_TIS_13 0x2
+#define INTERFACE_CAPABILITY_INTERFACE_VERSION_PTP 0x3
+
+//
+// Define bits of ACCESS and STATUS registers
+//
+
+///
+/// This bit is a 1 to indicate that the other bits in this register are valid.
+///
+#define PTP_FIFO_VALID BIT7
+///
+/// Indicate that this locality is active.
+///
+#define PTP_FIFO_ACC_ACTIVE BIT5
+///
+/// Set to 1 to indicate that this locality had the TPM taken away while
+/// this locality had the TIS_PC_ACC_ACTIVE bit set.
+///
+#define PTP_FIFO_ACC_SEIZED BIT4
+///
+/// Set to 1 to indicate that TPM MUST reset the
+/// TIS_PC_ACC_ACTIVE bit and remove ownership for localities less than the
+/// locality that is writing this bit.
+///
+#define PTP_FIFO_ACC_SEIZE BIT3
+///
+/// When this bit is 1, another locality is requesting usage of the TPM.
+///
+#define PTP_FIFO_ACC_PENDIND BIT2
+///
+/// Set to 1 to indicate that this locality is requesting to use TPM.
+///
+#define PTP_FIFO_ACC_RQUUSE BIT1
+///
+/// A value of 1 indicates that a T/OS has not been established on the platform
+///
+#define PTP_FIFO_ACC_ESTABLISH BIT0
+
+///
+/// This field indicates that STS_DATA and STS_EXPECT are valid
+///
+#define PTP_FIFO_STS_VALID BIT7
+///
+/// When this bit is 1, TPM is in the Ready state,
+/// indicating it is ready to receive a new command.
+///
+#define PTP_FIFO_STS_READY BIT6
+///
+/// Write a 1 to this bit to cause the TPM to execute that command.
+///
+#define PTP_FIFO_STS_GO BIT5
+///
+/// This bit indicates that the TPM has data available as a response.
+///
+#define PTP_FIFO_STS_DATA BIT4
+///
+/// The TPM sets this bit to a value of 1 when it expects another byte of data for a command.
+///
+#define PTP_FIFO_STS_EXPECT BIT3
+///
+/// Indicates that the TPM has completed all self-test actions following a TPM_ContinueSelfTest command.
+///
+#define PTP_FIFO_STS_SELFTEST_DONE BIT2
+///
+/// Writes a 1 to this bit to force the TPM to re-send the response.
+///
+#define PTP_FIFO_STS_RETRY BIT1
+
+///
+/// TPM Family Identifier.
+/// 00: TPM 1.2 Family
+/// 01: TPM 2.0 Family
+///
+#define PTP_FIFO_STS_EX_TPM_FAMILY (BIT2 | BIT3)
+#define PTP_FIFO_STS_EX_TPM_FAMILY_OFFSET (2)
+#define PTP_FIFO_STS_EX_TPM_FAMILY_TPM12 (0)
+#define PTP_FIFO_STS_EX_TPM_FAMILY_TPM20 (BIT2)
+///
+/// A write of 1 after tpmGo and before dataAvail aborts the currently executing command, resulting in a response of TPM_RC_CANCELLED.
+/// A write of 1 after dataAvail and before tpmGo is ignored by the TPM.
+///
+#define PTP_FIFO_STS_EX_CANCEL BIT0
+
+//
+// PTP CRB definition
+//
+
+//
+// Set structure alignment to 1-byte
+//
+#pragma pack (1)
+
+//
+// Register set map as specified in PTP specification Chapter 5
+//
+typedef struct {
+ ///
+ /// Used to determine current state of Locality of the TPM.
+ ///
+ UINT32 LocalityState; // 0
+ UINT8 Reserved1[4]; // 4
+ ///
+ /// Used to gain control of the TPM by this Locality.
+ ///
+ UINT32 LocalityControl; // 8
+ ///
+ /// Used to determine whether Locality has been granted or Seized.
+ ///
+ UINT32 LocalityStatus; // 0ch
+ UINT8 Reserved2[0x20]; // 10h
+ ///
+ /// Used to identify the Interface types supported by the TPM.
+ ///
+ UINT32 InterfaceId; // 30h
+ ///
+ /// Vendor ID
+ ///
+ UINT16 Vid; // 34h
+ ///
+ /// Device ID
+ ///
+ UINT16 Did; // 36h
+ ///
+ /// Optional Register used in low memory environments prior to CRB_DATA_BUFFER availability.
+ ///
+ UINT64 CrbControlExtension; // 38h
+ ///
+ /// Register used to initiate transactions for the CRB interface.
+ ///
+ UINT32 CrbControlRequest; // 40h
+ ///
+ /// Register used by the TPM to provide status of the CRB interface.
+ ///
+ UINT32 CrbControlStatus; // 44h
+ ///
+ /// Register used by software to cancel command processing.
+ ///
+ UINT32 CrbControlCancel; // 48h
+ ///
+ /// Register used to indicate presence of command or response data in the CRB buffer.
+ ///
+ UINT32 CrbControlStart; // 4Ch
+ ///
+ /// Register used to configure and respond to interrupts.
+ ///
+ UINT32 CrbInterruptEnable; // 50h
+ UINT32 CrbInterruptStatus; // 54h
+ ///
+ /// Size of the Command buffer.
+ ///
+ UINT32 CrbControlCommandSize; // 58h
+ ///
+ /// Command buffer start address
+ ///
+ UINT32 CrbControlCommandAddressLow; // 5Ch
+ UINT32 CrbControlCommandAddressHigh; // 60h
+ ///
+ /// Size of the Response buffer
+ ///
+ UINT32 CrbControlResponseSize; // 64h
+ ///
+ /// Address of the start of the Response buffer
+ ///
+ UINT64 CrbControlResponseAddrss; // 68h
+ UINT8 Reserved4[0x10]; // 70h
+ ///
+ /// Command/Response Data may be defined as large as 3968 (0xF80).
+ ///
+ UINT8 CrbDataBuffer[0xF80]; // 80h
+} PTP_CRB_REGISTERS;
+
+//
+// Define pointer types used to access CRB registers on PTP
+//
+typedef PTP_CRB_REGISTERS *PTP_CRB_REGISTERS_PTR;
+
+//
+// Define bits of CRB Interface Identifier Register
+//
+typedef union {
+ struct {
+ UINT32 InterfaceType : 4;
+ UINT32 InterfaceVersion : 4;
+ UINT32 CapLocality : 1;
+ UINT32 CapCRBIdleBypass : 1;
+ UINT32 Reserved1 : 1;
+ UINT32 CapDataXferSizeSupport : 2;
+ UINT32 CapFIFO : 1;
+ UINT32 CapCRB : 1;
+ UINT32 CapIFRes : 2;
+ UINT32 InterfaceSelector : 2;
+ UINT32 IntfSelLock : 1;
+ UINT32 Reserved2 : 4;
+ UINT32 Rid : 8;
+ } Bits;
+ UINT32 Uint32;
+} PTP_CRB_INTERFACE_IDENTIFIER;
+
+///
+/// InterfaceType
+///
+#define PTP_INTERFACE_IDENTIFIER_INTERFACE_TYPE_FIFO 0x0
+#define PTP_INTERFACE_IDENTIFIER_INTERFACE_TYPE_CRB 0x1
+#define PTP_INTERFACE_IDENTIFIER_INTERFACE_TYPE_TIS 0xF
+
+///
+/// InterfaceVersion
+///
+#define PTP_INTERFACE_IDENTIFIER_INTERFACE_VERSION_FIFO 0x0
+#define PTP_INTERFACE_IDENTIFIER_INTERFACE_VERSION_CRB 0x1
+
+///
+/// InterfaceSelector
+///
+#define PTP_INTERFACE_IDENTIFIER_INTERFACE_SELECTOR_FIFO 0x0
+#define PTP_INTERFACE_IDENTIFIER_INTERFACE_SELECTOR_CRB 0x1
+
+//
+// Define bits of Locality State Register
+//
+
+///
+/// This bit indicates whether all other bits of this register contain valid values, if it is a 1.
+///
+#define PTP_CRB_LOCALITY_STATE_TPM_REG_VALID_STATUS BIT7
+
+///
+/// 000 - Locality 0
+/// 001 - Locality 1
+/// 010 - Locality 2
+/// 011 - Locality 3
+/// 100 - Locality 4
+///
+#define PTP_CRB_LOCALITY_STATE_ACTIVE_LOCALITY_MASK (BIT2 | BIT3 | BIT4)
+#define PTP_CRB_LOCALITY_STATE_ACTIVE_LOCALITY_0 (0)
+#define PTP_CRB_LOCALITY_STATE_ACTIVE_LOCALITY_1 (BIT2)
+#define PTP_CRB_LOCALITY_STATE_ACTIVE_LOCALITY_2 (BIT3)
+#define PTP_CRB_LOCALITY_STATE_ACTIVE_LOCALITY_3 (BIT2 | BIT3)
+#define PTP_CRB_LOCALITY_STATE_ACTIVE_LOCALITY_4 (BIT4)
+
+///
+/// A 0 indicates to the host that no locality is assigned.
+/// A 1 indicates a locality has been assigned.
+///
+#define PTP_CRB_LOCALITY_STATE_LOCALITY_ASSIGNED BIT1
+
+///
+/// The TPM clears this bit to 0 upon receipt of _TPM_Hash_End
+/// The TPM sets this bit to a 1 when the TPM_LOC_CTRL_x.resetEstablishment field is set to 1.
+///
+#define PTP_CRB_LOCALITY_STATE_TPM_ESTABLISHED BIT0
+
+//
+// Define bits of Locality Control Register
+//
+
+///
+/// Writes (1): Reset TPM_LOC_STATE_x.tpmEstablished bit if the write occurs from Locality 3 or 4.
+///
+#define PTP_CRB_LOCALITY_CONTROL_RESET_ESTABLISHMENT_BIT BIT3
+
+///
+/// Writes (1): The TPM gives control of the TPM to the locality setting this bit if it is the higher priority locality.
+///
+#define PTP_CRB_LOCALITY_CONTROL_SEIZE BIT2
+
+///
+/// Writes (1): The active Locality is done with the TPM.
+///
+#define PTP_CRB_LOCALITY_CONTROL_RELINQUISH BIT1
+
+///
+/// Writes (1): Interrupt the TPM and generate a locality arbitration algorithm.
+///
+#define PTP_CRB_LOCALITY_CONTROL_REQUEST_ACCESS BIT0
+
+//
+// Define bits of Locality Status Register
+//
+
+///
+/// 0: A higher locality has not initiated a Seize arbitration process.
+/// 1: A higher locality has Seized the TPM from this locality.
+///
+#define PTP_CRB_LOCALITY_STATUS_BEEN_SEIZED BIT1
+
+///
+/// 0: Locality has not been granted to the TPM.
+/// 1: Locality has been granted access to the TPM
+///
+#define PTP_CRB_LOCALITY_STATUS_GRANTED BIT0
+
+//
+// Define bits of CRB Control Area Request Register
+//
+
+///
+/// Used by Software to indicate transition the TPM to and from the Idle state
+/// 1: Set by Software to indicate response has been read from the response buffer and TPM can transition to Idle
+/// 0: Cleared to 0 by TPM to acknowledge the request when TPM enters Idle state.
+/// TPM SHALL complete this transition within TIMEOUT_C.
+///
+#define PTP_CRB_CONTROL_AREA_REQUEST_GO_IDLE BIT1
+
+///
+/// Used by Software to request the TPM transition to the Ready State.
+/// 1: Set to 1 by Software to indicate the TPM should be ready to receive a command.
+/// 0: Cleared to 0 by TPM to acknowledge the request.
+/// TPM SHALL complete this transition within TIMEOUT_C.
+///
+#define PTP_CRB_CONTROL_AREA_REQUEST_COMMAND_READY BIT0
+
+//
+// Define bits of CRB Control Area Status Register
+//
+
+///
+/// Used by TPM to indicate it is in the Idle State
+/// 1: Set by TPM when in the Idle State
+/// 0: Cleared by TPM on receipt of TPM_CRB_CTRL_REQ_x.cmdReady when TPM transitions to the Ready State.
+/// SHALL be cleared by TIMEOUT_C.
+///
+#define PTP_CRB_CONTROL_AREA_STATUS_TPM_IDLE BIT1
+
+///
+/// Used by the TPM to indicate current status.
+/// 1: Set by TPM to indicate a FATAL Error
+/// 0: Indicates TPM is operational
+///
+#define PTP_CRB_CONTROL_AREA_STATUS_TPM_STATUS BIT0
+
+//
+// Define bits of CRB Control Cancel Register
+//
+
+///
+/// Used by software to cancel command processing Reads return correct value
+/// Writes (0000 0001h): Cancel a command
+/// Writes (0000 0000h): Clears field when command has been cancelled
+///
+#define PTP_CRB_CONTROL_CANCEL BIT0
+
+//
+// Define bits of CRB Control Start Register
+//
+
+///
+/// When set by software, indicates a command is ready for processing.
+/// Writes (0000 0001h): TPM transitions to Command Execution
+/// Writes (0000 0000h): TPM clears this field and transitions to Command Completion
+///
+#define PTP_CRB_CONTROL_START BIT0
+
+//
+// Restore original structure alignment
+//
+#pragma pack ()
+
+//
+// Default TimeOut value
+//
+#define PTP_TIMEOUT_A (750 * 1000) // 750ms
+#define PTP_TIMEOUT_B (2000 * 1000) // 2s
+#define PTP_TIMEOUT_C (200 * 1000) // 200ms
+#define PTP_TIMEOUT_D (30 * 1000) // 30ms
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/TpmTis.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/TpmTis.h
new file mode 100644
index 0000000000..cf98268f81
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/TpmTis.h
@@ -0,0 +1,181 @@
+/** @file
+ TPM Interface Specification definition.
+ It covers both TPM1.2 and TPM2.0.
+
+Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _TPM_TIS_H_
+#define _TPM_TIS_H_
+
+//
+// Set structure alignment to 1-byte
+//
+#pragma pack (1)
+
+//
+// Register set map as specified in TIS specification Chapter 10
+//
+typedef struct {
+ ///
+ /// Used to gain ownership for this particular port.
+ ///
+ UINT8 Access; // 0
+ UINT8 Reserved1[7]; // 1
+ ///
+ /// Controls interrupts.
+ ///
+ UINT32 IntEnable; // 8
+ ///
+ /// SIRQ vector to be used by the TPM.
+ ///
+ UINT8 IntVector; // 0ch
+ UINT8 Reserved2[3]; // 0dh
+ ///
+ /// What caused interrupt.
+ ///
+ UINT32 IntSts; // 10h
+ ///
+ /// Shows which interrupts are supported by that particular TPM.
+ ///
+ UINT32 IntfCapability; // 14h
+ ///
+ /// Status Register. Provides status of the TPM.
+ ///
+ UINT8 Status; // 18h
+ ///
+ /// Number of consecutive writes that can be done to the TPM.
+ ///
+ UINT16 BurstCount; // 19h
+ UINT8 Reserved3[9];
+ ///
+ /// Read or write FIFO, depending on transaction.
+ ///
+ UINT32 DataFifo; // 24h
+ UINT8 Reserved4[0xed8]; // 28h
+ ///
+ /// Vendor ID
+ ///
+ UINT16 Vid; // 0f00h
+ ///
+ /// Device ID
+ ///
+ UINT16 Did; // 0f02h
+ ///
+ /// Revision ID
+ ///
+ UINT8 Rid; // 0f04h
+ UINT8 Reserved[0x7b]; // 0f05h
+ ///
+ /// Alias to I/O legacy space.
+ ///
+ UINT32 LegacyAddress1; // 0f80h
+ ///
+ /// Additional 8 bits for I/O legacy space extension.
+ ///
+ UINT32 LegacyAddress1Ex; // 0f84h
+ ///
+ /// Alias to second I/O legacy space.
+ ///
+ UINT32 LegacyAddress2; // 0f88h
+ ///
+ /// Additional 8 bits for second I/O legacy space extension.
+ ///
+ UINT32 LegacyAddress2Ex; // 0f8ch
+ ///
+ /// Vendor-defined configuration registers.
+ ///
+ UINT8 VendorDefined[0x70]; // 0f90h
+} TIS_PC_REGISTERS;
+
+//
+// Restore original structure alignment
+//
+#pragma pack ()
+
+//
+// Define pointer types used to access TIS registers on PC
+//
+typedef TIS_PC_REGISTERS *TIS_PC_REGISTERS_PTR;
+
+//
+// Define bits of ACCESS and STATUS registers
+//
+
+///
+/// This bit is a 1 to indicate that the other bits in this register are valid.
+///
+#define TIS_PC_VALID BIT7
+///
+/// Indicate that this locality is active.
+///
+#define TIS_PC_ACC_ACTIVE BIT5
+///
+/// Set to 1 to indicate that this locality had the TPM taken away while
+/// this locality had the TIS_PC_ACC_ACTIVE bit set.
+///
+#define TIS_PC_ACC_SEIZED BIT4
+///
+/// Set to 1 to indicate that TPM MUST reset the
+/// TIS_PC_ACC_ACTIVE bit and remove ownership for localities less than the
+/// locality that is writing this bit.
+///
+#define TIS_PC_ACC_SEIZE BIT3
+///
+/// When this bit is 1, another locality is requesting usage of the TPM.
+///
+#define TIS_PC_ACC_PENDIND BIT2
+///
+/// Set to 1 to indicate that this locality is requesting to use TPM.
+///
+#define TIS_PC_ACC_RQUUSE BIT1
+///
+/// A value of 1 indicates that a T/OS has not been established on the platform
+///
+#define TIS_PC_ACC_ESTABLISH BIT0
+
+///
+/// Write a 1 to this bit to notify TPM to cancel currently executing command
+///
+#define TIS_PC_STS_CANCEL BIT24
+///
+/// This field indicates that STS_DATA and STS_EXPECT are valid
+///
+#define TIS_PC_STS_VALID BIT7
+///
+/// When this bit is 1, TPM is in the Ready state,
+/// indicating it is ready to receive a new command.
+///
+#define TIS_PC_STS_READY BIT6
+///
+/// Write a 1 to this bit to cause the TPM to execute that command.
+///
+#define TIS_PC_STS_GO BIT5
+///
+/// This bit indicates that the TPM has data available as a response.
+///
+#define TIS_PC_STS_DATA BIT4
+///
+/// The TPM sets this bit to a value of 1 when it expects another byte of data for a command.
+///
+#define TIS_PC_STS_EXPECT BIT3
+///
+/// Indicates that the TPM has completed all self-test actions following a TPM_ContinueSelfTest command.
+///
+#define TIS_PC_STS_SELFTEST_DONE BIT2
+///
+/// Writes a 1 to this bit to force the TPM to re-send the response.
+///
+#define TIS_PC_STS_RETRY BIT1
+
+//
+// Default TimeOut value
+//
+#define TIS_TIMEOUT_A (750 * 1000) // 750ms
+#define TIS_TIMEOUT_B (2000 * 1000) // 2s
+#define TIS_TIMEOUT_C (750 * 1000) // 750ms
+#define TIS_TIMEOUT_D (750 * 1000) // 750ms
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/Udf.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/Udf.h
new file mode 100644
index 0000000000..105b3f87d9
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/Udf.h
@@ -0,0 +1,141 @@
+/** @file
+ OSTA Universal Disk Format (UDF) definitions.
+
+ Copyright (C) 2014-2017 Paulo Alcantara
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef __UDF_H__
+#define __UDF_H__
+
+#define UDF_BEA_IDENTIFIER "BEA01"
+#define UDF_NSR2_IDENTIFIER "NSR02"
+#define UDF_NSR3_IDENTIFIER "NSR03"
+#define UDF_TEA_IDENTIFIER "TEA01"
+
+#define UDF_LOGICAL_SECTOR_SHIFT 11
+#define UDF_LOGICAL_SECTOR_SIZE ((UINT64)(1ULL << UDF_LOGICAL_SECTOR_SHIFT))
+#define UDF_VRS_START_OFFSET ((UINT64)(16ULL << UDF_LOGICAL_SECTOR_SHIFT))
+
+typedef enum {
+ UdfPrimaryVolumeDescriptor = 1,
+ UdfAnchorVolumeDescriptorPointer = 2,
+ UdfVolumeDescriptorPointer = 3,
+ UdfImplemenationUseVolumeDescriptor = 4,
+ UdfPartitionDescriptor = 5,
+ UdfLogicalVolumeDescriptor = 6,
+ UdfUnallocatedSpaceDescriptor = 7,
+ UdfTerminatingDescriptor = 8,
+ UdfLogicalVolumeIntegrityDescriptor = 9,
+ UdfFileSetDescriptor = 256,
+ UdfFileIdentifierDescriptor = 257,
+ UdfAllocationExtentDescriptor = 258,
+ UdfFileEntry = 261,
+ UdfExtendedFileEntry = 266,
+} UDF_VOLUME_DESCRIPTOR_ID;
+
+#pragma pack(1)
+
+typedef struct {
+ UINT16 TagIdentifier;
+ UINT16 DescriptorVersion;
+ UINT8 TagChecksum;
+ UINT8 Reserved;
+ UINT16 TagSerialNumber;
+ UINT16 DescriptorCRC;
+ UINT16 DescriptorCRCLength;
+ UINT32 TagLocation;
+} UDF_DESCRIPTOR_TAG;
+
+typedef struct {
+ UINT32 ExtentLength;
+ UINT32 ExtentLocation;
+} UDF_EXTENT_AD;
+
+typedef struct {
+ UINT8 CharacterSetType;
+ UINT8 CharacterSetInfo[63];
+} UDF_CHAR_SPEC;
+
+typedef struct {
+ UINT8 Flags;
+ UINT8 Identifier[23];
+ union {
+ //
+ // Domain Entity Identifier
+ //
+ struct {
+ UINT16 UdfRevision;
+ UINT8 DomainFlags;
+ UINT8 Reserved[5];
+ } Domain;
+ //
+ // UDF Entity Identifier
+ //
+ struct {
+ UINT16 UdfRevision;
+ UINT8 OSClass;
+ UINT8 OSIdentifier;
+ UINT8 Reserved[4];
+ } Entity;
+ //
+ // Implementation Entity Identifier
+ //
+ struct {
+ UINT8 OSClass;
+ UINT8 OSIdentifier;
+ UINT8 ImplementationUseArea[6];
+ } ImplementationEntity;
+ //
+ // Application Entity Identifier
+ //
+ struct {
+ UINT8 ApplicationUseArea[8];
+ } ApplicationEntity;
+ //
+ // Raw Identifier Suffix
+ //
+ struct {
+ UINT8 Data[8];
+ } Raw;
+ } Suffix;
+} UDF_ENTITY_ID;
+
+typedef struct {
+ UINT32 LogicalBlockNumber;
+ UINT16 PartitionReferenceNumber;
+} UDF_LB_ADDR;
+
+typedef struct {
+ UINT32 ExtentLength;
+ UDF_LB_ADDR ExtentLocation;
+ UINT8 ImplementationUse[6];
+} UDF_LONG_ALLOCATION_DESCRIPTOR;
+
+typedef struct {
+ UDF_DESCRIPTOR_TAG DescriptorTag;
+ UDF_EXTENT_AD MainVolumeDescriptorSequenceExtent;
+ UDF_EXTENT_AD ReserveVolumeDescriptorSequenceExtent;
+ UINT8 Reserved[480];
+} UDF_ANCHOR_VOLUME_DESCRIPTOR_POINTER;
+
+typedef struct {
+ UDF_DESCRIPTOR_TAG DescriptorTag;
+ UINT32 VolumeDescriptorSequenceNumber;
+ UDF_CHAR_SPEC DescriptorCharacterSet;
+ UINT8 LogicalVolumeIdentifier[128];
+ UINT32 LogicalBlockSize;
+ UDF_ENTITY_ID DomainIdentifier;
+ UDF_LONG_ALLOCATION_DESCRIPTOR LogicalVolumeContentsUse;
+ UINT32 MapTableLength;
+ UINT32 NumberOfPartitionMaps;
+ UDF_ENTITY_ID ImplementationIdentifier;
+ UINT8 ImplementationUse[128];
+ UDF_EXTENT_AD IntegritySequenceExtent;
+ UINT8 PartitionMaps[6];
+} UDF_LOGICAL_VOLUME_DESCRIPTOR;
+
+#pragma pack()
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/UefiTcgPlatform.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/UefiTcgPlatform.h
new file mode 100644
index 0000000000..77866bb2df
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/UefiTcgPlatform.h
@@ -0,0 +1,495 @@
+/** @file
+ TCG EFI Platform Definition in TCG_EFI_Platform_1_20_Final and
+ TCG PC Client Platform Firmware Profile Specification, Revision 1.05
+
+ Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __UEFI_TCG_PLATFORM_H__
+#define __UEFI_TCG_PLATFORM_H__
+
+#include
+#include
+#include
+
+//
+// Standard event types
+//
+#define EV_PREBOOT_CERT ((TCG_EVENTTYPE) 0x00000000)
+#define EV_POST_CODE ((TCG_EVENTTYPE) 0x00000001)
+#define EV_NO_ACTION ((TCG_EVENTTYPE) 0x00000003)
+#define EV_SEPARATOR ((TCG_EVENTTYPE) 0x00000004)
+#define EV_ACTION ((TCG_EVENTTYPE) 0x00000005)
+#define EV_EVENT_TAG ((TCG_EVENTTYPE) 0x00000006)
+#define EV_S_CRTM_CONTENTS ((TCG_EVENTTYPE) 0x00000007)
+#define EV_S_CRTM_VERSION ((TCG_EVENTTYPE) 0x00000008)
+#define EV_CPU_MICROCODE ((TCG_EVENTTYPE) 0x00000009)
+#define EV_PLATFORM_CONFIG_FLAGS ((TCG_EVENTTYPE) 0x0000000A)
+#define EV_TABLE_OF_DEVICES ((TCG_EVENTTYPE) 0x0000000B)
+#define EV_COMPACT_HASH ((TCG_EVENTTYPE) 0x0000000C)
+#define EV_NONHOST_CODE ((TCG_EVENTTYPE) 0x0000000F)
+#define EV_NONHOST_CONFIG ((TCG_EVENTTYPE) 0x00000010)
+#define EV_NONHOST_INFO ((TCG_EVENTTYPE) 0x00000011)
+#define EV_OMIT_BOOT_DEVICE_EVENTS ((TCG_EVENTTYPE) 0x00000012)
+
+//
+// EFI specific event types
+//
+#define EV_EFI_EVENT_BASE ((TCG_EVENTTYPE) 0x80000000)
+#define EV_EFI_VARIABLE_DRIVER_CONFIG (EV_EFI_EVENT_BASE + 1)
+#define EV_EFI_VARIABLE_BOOT (EV_EFI_EVENT_BASE + 2)
+#define EV_EFI_BOOT_SERVICES_APPLICATION (EV_EFI_EVENT_BASE + 3)
+#define EV_EFI_BOOT_SERVICES_DRIVER (EV_EFI_EVENT_BASE + 4)
+#define EV_EFI_RUNTIME_SERVICES_DRIVER (EV_EFI_EVENT_BASE + 5)
+#define EV_EFI_GPT_EVENT (EV_EFI_EVENT_BASE + 6)
+#define EV_EFI_ACTION (EV_EFI_EVENT_BASE + 7)
+#define EV_EFI_PLATFORM_FIRMWARE_BLOB (EV_EFI_EVENT_BASE + 8)
+#define EV_EFI_HANDOFF_TABLES (EV_EFI_EVENT_BASE + 9)
+#define EV_EFI_PLATFORM_FIRMWARE_BLOB2 (EV_EFI_EVENT_BASE + 0xA)
+#define EV_EFI_HANDOFF_TABLES2 (EV_EFI_EVENT_BASE + 0xB)
+#define EV_EFI_HCRTM_EVENT (EV_EFI_EVENT_BASE + 0x10)
+#define EV_EFI_VARIABLE_AUTHORITY (EV_EFI_EVENT_BASE + 0xE0)
+#define EV_EFI_SPDM_FIRMWARE_BLOB (EV_EFI_EVENT_BASE + 0xE1)
+#define EV_EFI_SPDM_FIRMWARE_CONFIG (EV_EFI_EVENT_BASE + 0xE2)
+
+#define EFI_CALLING_EFI_APPLICATION \
+ "Calling EFI Application from Boot Option"
+#define EFI_RETURNING_FROM_EFI_APPLICATION \
+ "Returning from EFI Application from Boot Option"
+#define EFI_EXIT_BOOT_SERVICES_INVOCATION \
+ "Exit Boot Services Invocation"
+#define EFI_EXIT_BOOT_SERVICES_FAILED \
+ "Exit Boot Services Returned with Failure"
+#define EFI_EXIT_BOOT_SERVICES_SUCCEEDED \
+ "Exit Boot Services Returned with Success"
+
+#define EV_POSTCODE_INFO_POST_CODE "POST CODE"
+#define POST_CODE_STR_LEN (sizeof(EV_POSTCODE_INFO_POST_CODE) - 1)
+
+#define EV_POSTCODE_INFO_SMM_CODE "SMM CODE"
+#define SMM_CODE_STR_LEN (sizeof(EV_POSTCODE_INFO_SMM_CODE) - 1)
+
+#define EV_POSTCODE_INFO_ACPI_DATA "ACPI DATA"
+#define ACPI_DATA_LEN (sizeof(EV_POSTCODE_INFO_ACPI_DATA) - 1)
+
+#define EV_POSTCODE_INFO_BIS_CODE "BIS CODE"
+#define BIS_CODE_LEN (sizeof(EV_POSTCODE_INFO_BIS_CODE) - 1)
+
+#define EV_POSTCODE_INFO_UEFI_PI "UEFI PI"
+#define UEFI_PI_LEN (sizeof(EV_POSTCODE_INFO_UEFI_PI) - 1)
+
+#define EV_POSTCODE_INFO_OPROM "Embedded Option ROM"
+#define OPROM_LEN (sizeof(EV_POSTCODE_INFO_OPROM) - 1)
+
+#define EV_POSTCODE_INFO_EMBEDDED_UEFI_DRIVER "Embedded UEFI Driver"
+#define EMBEDDED_UEFI_DRIVER_LEN (sizeof(EV_POSTCODE_INFO_EMBEDDED_UEFI_DRIVER) - 1)
+
+#define FIRMWARE_DEBUGGER_EVENT_STRING "UEFI Debug Mode"
+#define FIRMWARE_DEBUGGER_EVENT_STRING_LEN (sizeof(FIRMWARE_DEBUGGER_EVENT_STRING) - 1)
+
+//
+// Set structure alignment to 1-byte
+//
+#pragma pack (1)
+
+typedef UINT32 TCG_EVENTTYPE;
+typedef TPM_PCRINDEX TCG_PCRINDEX;
+typedef TPM_DIGEST TCG_DIGEST;
+///
+/// Event Log Entry Structure Definition
+///
+typedef struct tdTCG_PCR_EVENT {
+ TCG_PCRINDEX PCRIndex; ///< PCRIndex event extended to
+ TCG_EVENTTYPE EventType; ///< TCG EFI event type
+ TCG_DIGEST Digest; ///< Value extended into PCRIndex
+ UINT32 EventSize; ///< Size of the event data
+ UINT8 Event[1]; ///< The event data
+} TCG_PCR_EVENT;
+
+#define TSS_EVENT_DATA_MAX_SIZE 256
+
+///
+/// TCG_PCR_EVENT_HDR
+///
+typedef struct tdTCG_PCR_EVENT_HDR {
+ TCG_PCRINDEX PCRIndex;
+ TCG_EVENTTYPE EventType;
+ TCG_DIGEST Digest;
+ UINT32 EventSize;
+} TCG_PCR_EVENT_HDR;
+
+///
+/// EFI_PLATFORM_FIRMWARE_BLOB
+///
+/// BlobLength should be of type UINTN but we use UINT64 here
+/// because PEI is 32-bit while DXE is 64-bit on x64 platforms
+///
+typedef struct tdEFI_PLATFORM_FIRMWARE_BLOB {
+ EFI_PHYSICAL_ADDRESS BlobBase;
+ UINT64 BlobLength;
+} EFI_PLATFORM_FIRMWARE_BLOB;
+
+///
+/// UEFI_PLATFORM_FIRMWARE_BLOB
+///
+/// This structure is used in EV_EFI_PLATFORM_FIRMWARE_BLOB
+/// event to facilitate the measurement of firmware volume.
+///
+typedef struct tdUEFI_PLATFORM_FIRMWARE_BLOB {
+ EFI_PHYSICAL_ADDRESS BlobBase;
+ UINT64 BlobLength;
+} UEFI_PLATFORM_FIRMWARE_BLOB;
+
+///
+/// UEFI_PLATFORM_FIRMWARE_BLOB2
+///
+/// This structure is used in EV_EFI_PLATFORM_FIRMWARE_BLOB2
+/// event to facilitate the measurement of firmware volume.
+///
+typedef struct tdUEFI_PLATFORM_FIRMWARE_BLOB2 {
+ UINT8 BlobDescriptionSize;
+ // UINT8 BlobDescription[BlobDescriptionSize];
+ // EFI_PHYSICAL_ADDRESS BlobBase;
+ // UINT64 BlobLength;
+} UEFI_PLATFORM_FIRMWARE_BLOB2;
+
+///
+/// EFI_IMAGE_LOAD_EVENT
+///
+/// This structure is used in EV_EFI_BOOT_SERVICES_APPLICATION,
+/// EV_EFI_BOOT_SERVICES_DRIVER and EV_EFI_RUNTIME_SERVICES_DRIVER
+///
+typedef struct tdEFI_IMAGE_LOAD_EVENT {
+ EFI_PHYSICAL_ADDRESS ImageLocationInMemory;
+ UINTN ImageLengthInMemory;
+ UINTN ImageLinkTimeAddress;
+ UINTN LengthOfDevicePath;
+ EFI_DEVICE_PATH_PROTOCOL DevicePath[1];
+} EFI_IMAGE_LOAD_EVENT;
+
+///
+/// UEFI_IMAGE_LOAD_EVENT
+///
+/// This structure is used in EV_EFI_BOOT_SERVICES_APPLICATION,
+/// EV_EFI_BOOT_SERVICES_DRIVER and EV_EFI_RUNTIME_SERVICES_DRIVER
+///
+typedef struct tdUEFI_IMAGE_LOAD_EVENT {
+ EFI_PHYSICAL_ADDRESS ImageLocationInMemory;
+ UINT64 ImageLengthInMemory;
+ UINT64 ImageLinkTimeAddress;
+ UINT64 LengthOfDevicePath;
+ EFI_DEVICE_PATH_PROTOCOL DevicePath[1];
+} UEFI_IMAGE_LOAD_EVENT;
+
+///
+/// EFI_HANDOFF_TABLE_POINTERS
+///
+/// This structure is used in EV_EFI_HANDOFF_TABLES event to facilitate
+/// the measurement of given configuration tables.
+///
+typedef struct tdEFI_HANDOFF_TABLE_POINTERS {
+ UINTN NumberOfTables;
+ EFI_CONFIGURATION_TABLE TableEntry[1];
+} EFI_HANDOFF_TABLE_POINTERS;
+
+///
+/// UEFI_HANDOFF_TABLE_POINTERS
+///
+/// This structure is used in EV_EFI_HANDOFF_TABLES event to facilitate
+/// the measurement of given configuration tables.
+///
+typedef struct tdUEFI_HANDOFF_TABLE_POINTERS {
+ UINT64 NumberOfTables;
+ EFI_CONFIGURATION_TABLE TableEntry[1];
+} UEFI_HANDOFF_TABLE_POINTERS;
+
+///
+/// UEFI_HANDOFF_TABLE_POINTERS2
+///
+/// This structure is used in EV_EFI_HANDOFF_TABLES2 event to facilitate
+/// the measurement of given configuration tables.
+///
+typedef struct tdUEFI_HANDOFF_TABLE_POINTERS2 {
+ UINT8 TableDescriptionSize;
+ // UINT8 TableDescription[TableDescriptionSize];
+ // UINT64 NumberOfTables;
+ // EFI_CONFIGURATION_TABLE TableEntry[1];
+} UEFI_HANDOFF_TABLE_POINTERS2;
+
+///
+/// EFI_VARIABLE_DATA
+///
+/// This structure serves as the header for measuring variables. The name of the
+/// variable (in Unicode format) should immediately follow, then the variable
+/// data.
+/// This is defined in TCG EFI Platform Spec for TPM1.1 or 1.2 V1.22
+///
+typedef struct tdEFI_VARIABLE_DATA {
+ EFI_GUID VariableName;
+ UINTN UnicodeNameLength;
+ UINTN VariableDataLength;
+ CHAR16 UnicodeName[1];
+ INT8 VariableData[1]; ///< Driver or platform-specific data
+} EFI_VARIABLE_DATA;
+
+///
+/// UEFI_VARIABLE_DATA
+///
+/// This structure serves as the header for measuring variables. The name of the
+/// variable (in Unicode format) should immediately follow, then the variable
+/// data.
+/// This is defined in TCG PC Client Firmware Profile Spec 00.21
+///
+typedef struct tdUEFI_VARIABLE_DATA {
+ EFI_GUID VariableName;
+ UINT64 UnicodeNameLength;
+ UINT64 VariableDataLength;
+ CHAR16 UnicodeName[1];
+ INT8 VariableData[1]; ///< Driver or platform-specific data
+} UEFI_VARIABLE_DATA;
+
+//
+// For TrEE1.0 compatibility
+//
+typedef struct {
+ EFI_GUID VariableName;
+ UINT64 UnicodeNameLength; // The TCG Definition used UINTN
+ UINT64 VariableDataLength; // The TCG Definition used UINTN
+ CHAR16 UnicodeName[1];
+ INT8 VariableData[1];
+} EFI_VARIABLE_DATA_TREE;
+
+typedef struct tdEFI_GPT_DATA {
+ EFI_PARTITION_TABLE_HEADER EfiPartitionHeader;
+ UINTN NumberOfPartitions;
+ EFI_PARTITION_ENTRY Partitions[1];
+} EFI_GPT_DATA;
+
+typedef struct tdUEFI_GPT_DATA {
+ EFI_PARTITION_TABLE_HEADER EfiPartitionHeader;
+ UINT64 NumberOfPartitions;
+ EFI_PARTITION_ENTRY Partitions[1];
+} UEFI_GPT_DATA;
+
+#define TCG_DEVICE_SECURITY_EVENT_DATA_SIGNATURE "SPDM Device Sec"
+#define TCG_DEVICE_SECURITY_EVENT_DATA_VERSION 1
+
+#define TCG_DEVICE_SECURITY_EVENT_DATA_DEVICE_TYPE_NULL 0
+#define TCG_DEVICE_SECURITY_EVENT_DATA_DEVICE_TYPE_PCI 1
+#define TCG_DEVICE_SECURITY_EVENT_DATA_DEVICE_TYPE_USB 2
+
+///
+/// TCG_DEVICE_SECURITY_EVENT_DATA_HEADER
+/// This is the header of TCG_DEVICE_SECURITY_EVENT_DATA, which is
+/// used in EV_EFI_SPDM_FIRMWARE_BLOB and EV_EFI_SPDM_FIRMWARE_CONFIG.
+///
+typedef struct {
+ UINT8 Signature[16];
+ UINT16 Version;
+ UINT16 Length;
+ UINT32 SpdmHashAlgo;
+ UINT32 DeviceType;
+ // SPDM_MEASUREMENT_BLOCK SpdmMeasurementBlock;
+} TCG_DEVICE_SECURITY_EVENT_DATA_HEADER;
+
+#define TCG_DEVICE_SECURITY_EVENT_DATA_PCI_CONTEXT_VERSION 0
+
+///
+/// TCG_DEVICE_SECURITY_EVENT_DATA_PCI_CONTEXT
+/// This is the PCI context data of TCG_DEVICE_SECURITY_EVENT_DATA, which is
+/// used in EV_EFI_SPDM_FIRMWARE_BLOB and EV_EFI_SPDM_FIRMWARE_CONFIG.
+///
+typedef struct {
+ UINT16 Version;
+ UINT16 Length;
+ UINT16 VendorId;
+ UINT16 DeviceId;
+ UINT8 RevisionID;
+ UINT8 ClassCode[3];
+ UINT16 SubsystemVendorID;
+ UINT16 SubsystemID;
+} TCG_DEVICE_SECURITY_EVENT_DATA_PCI_CONTEXT;
+
+#define TCG_DEVICE_SECURITY_EVENT_DATA_USB_CONTEXT_VERSION 0
+
+///
+/// TCG_DEVICE_SECURITY_EVENT_DATA_USB_CONTEXT
+/// This is the USB context data of TCG_DEVICE_SECURITY_EVENT_DATA, which is
+/// used in EV_EFI_SPDM_FIRMWARE_BLOB and EV_EFI_SPDM_FIRMWARE_CONFIG.
+///
+typedef struct {
+ UINT16 Version;
+ UINT16 Length;
+ // UINT8 DeviceDescriptor[DescLen];
+ // UINT8 BodDescriptor[DescLen];
+ // UINT8 ConfigurationDescriptor[DescLen][NumOfConfiguration];
+} TCG_DEVICE_SECURITY_EVENT_DATA_USB_CONTEXT;
+
+//
+// Crypto Agile Log Entry Format
+//
+typedef struct tdTCG_PCR_EVENT2 {
+ TCG_PCRINDEX PCRIndex;
+ TCG_EVENTTYPE EventType;
+ TPML_DIGEST_VALUES Digest;
+ UINT32 EventSize;
+ UINT8 Event[1];
+} TCG_PCR_EVENT2;
+
+//
+// TCG PCR Event2 Header
+// Follow TCG EFI Protocol Spec 5.2 Crypto Agile Log Entry Format
+//
+typedef struct tdTCG_PCR_EVENT2_HDR {
+ TCG_PCRINDEX PCRIndex;
+ TCG_EVENTTYPE EventType;
+ TPML_DIGEST_VALUES Digests;
+ UINT32 EventSize;
+} TCG_PCR_EVENT2_HDR;
+
+//
+// Log Header Entry Data
+//
+typedef struct {
+ //
+ // TCG defined hashing algorithm ID.
+ //
+ UINT16 algorithmId;
+ //
+ // The size of the digest for the respective hashing algorithm.
+ //
+ UINT16 digestSize;
+} TCG_EfiSpecIdEventAlgorithmSize;
+
+#define TCG_EfiSpecIDEventStruct_SIGNATURE_02 "Spec ID Event02"
+#define TCG_EfiSpecIDEventStruct_SIGNATURE_03 "Spec ID Event03"
+
+#define TCG_EfiSpecIDEventStruct_SPEC_VERSION_MAJOR_TPM12 1
+#define TCG_EfiSpecIDEventStruct_SPEC_VERSION_MINOR_TPM12 2
+#define TCG_EfiSpecIDEventStruct_SPEC_ERRATA_TPM12 2
+
+#define TCG_EfiSpecIDEventStruct_SPEC_VERSION_MAJOR_TPM2 2
+#define TCG_EfiSpecIDEventStruct_SPEC_VERSION_MINOR_TPM2 0
+#define TCG_EfiSpecIDEventStruct_SPEC_ERRATA_TPM2 0
+#define TCG_EfiSpecIDEventStruct_SPEC_ERRATA_TPM2_REV_105 105
+
+typedef struct {
+ UINT8 signature[16];
+ //
+ // The value for the Platform Class.
+ // The enumeration is defined in the TCG ACPI Specification Client Common Header.
+ //
+ UINT32 platformClass;
+ //
+ // The TCG EFI Platform Specification minor version number this BIOS supports.
+ // Any BIOS supporting version (1.22) MUST set this value to 02h.
+ // Any BIOS supporting version (2.0) SHALL set this value to 0x00.
+ //
+ UINT8 specVersionMinor;
+ //
+ // The TCG EFI Platform Specification major version number this BIOS supports.
+ // Any BIOS supporting version (1.22) MUST set this value to 01h.
+ // Any BIOS supporting version (2.0) SHALL set this value to 0x02.
+ //
+ UINT8 specVersionMajor;
+ //
+ // The TCG EFI Platform Specification errata for this specification this BIOS supports.
+ // Any BIOS supporting version and errata (1.22) MUST set this value to 02h.
+ // Any BIOS supporting version and errata (2.0) SHALL set this value to 0x00.
+ //
+ UINT8 specErrata;
+ //
+ // Specifies the size of the UINTN fields used in various data structures used in this specification.
+ // 0x01 indicates UINT32 and 0x02 indicates UINT64.
+ //
+ UINT8 uintnSize;
+ //
+ // This field is added in "Spec ID Event03".
+ // The number of hashing algorithms used in this event log (except the first event).
+ // All events in this event log use all hashing algorithms defined here.
+ //
+ // UINT32 numberOfAlgorithms;
+ //
+ // This field is added in "Spec ID Event03".
+ // An array of size numberOfAlgorithms of value pairs.
+ //
+ // TCG_EfiSpecIdEventAlgorithmSize digestSize[numberOfAlgorithms];
+ //
+ // Size in bytes of the VendorInfo field.
+ // Maximum value SHALL be FFh bytes.
+ //
+ // UINT8 vendorInfoSize;
+ //
+ // Provided for use by the BIOS implementer.
+ // The value might be used, for example, to provide more detailed information about the specific BIOS such as BIOS revision numbers, etc.
+ // The values within this field are not standardized and are implementer-specific.
+ // Platform-specific or -unique information SHALL NOT be provided in this field.
+ //
+ // UINT8 vendorInfo[vendorInfoSize];
+} TCG_EfiSpecIDEventStruct;
+
+typedef struct tdTCG_PCClientTaggedEvent {
+ UINT32 taggedEventID;
+ UINT32 taggedEventDataSize;
+ // UINT8 taggedEventData[taggedEventDataSize];
+} TCG_PCClientTaggedEvent;
+
+#define TCG_Sp800_155_PlatformId_Event_SIGNATURE "SP800-155 Event"
+#define TCG_Sp800_155_PlatformId_Event2_SIGNATURE "SP800-155 Event2"
+
+typedef struct tdTCG_Sp800_155_PlatformId_Event2 {
+ UINT8 Signature[16];
+ //
+ // Where Vendor ID is an integer defined
+ // at http://www.iana.org/assignments/enterprisenumbers
+ //
+ UINT32 VendorId;
+ //
+ // 16-byte identifier of a given platform's static configuration of code
+ //
+ EFI_GUID ReferenceManifestGuid;
+ //
+ // Below structure is newly added in TCG_Sp800_155_PlatformId_Event2.
+ //
+ // UINT8 PlatformManufacturerStrSize;
+ // UINT8 PlatformManufacturerStr[PlatformManufacturerStrSize];
+ // UINT8 PlatformModelSize;
+ // UINT8 PlatformModel[PlatformModelSize];
+ // UINT8 PlatformVersionSize;
+ // UINT8 PlatformVersion[PlatformVersionSize];
+ // UINT8 PlatformModelSize;
+ // UINT8 PlatformModel[PlatformModelSize];
+ // UINT8 FirmwareManufacturerStrSize;
+ // UINT8 FirmwareManufacturerStr[FirmwareManufacturerStrSize];
+ // UINT32 FirmwareManufacturerId;
+ // UINT8 FirmwareVersion;
+ // UINT8 FirmwareVersion[FirmwareVersionSize]];
+} TCG_Sp800_155_PlatformId_Event2;
+
+#define TCG_EfiStartupLocalityEvent_SIGNATURE "StartupLocality"
+
+//
+// The Locality Indicator which sent the TPM2_Startup command
+//
+#define LOCALITY_0_INDICATOR 0x00
+#define LOCALITY_3_INDICATOR 0x03
+
+//
+// Startup Locality Event
+//
+typedef struct tdTCG_EfiStartupLocalityEvent {
+ UINT8 Signature[16];
+ //
+ // The Locality Indicator which sent the TPM2_Startup command
+ //
+ UINT8 StartupLocality;
+} TCG_EfiStartupLocalityEvent;
+
+//
+// Restore original structure alignment
+//
+#pragma pack ()
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/Usb.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/Usb.h
new file mode 100644
index 0000000000..3a096d91b4
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/Usb.h
@@ -0,0 +1,377 @@
+/** @file
+ Support for USB 2.0 standard.
+
+ Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __USB_H__
+#define __USB_H__
+
+//
+// Subset of Class and Subclass definitions from USB Specs
+//
+
+//
+// Usb mass storage class code
+//
+#define USB_MASS_STORE_CLASS 0x08
+
+//
+// Usb mass storage subclass code, specify the command set used.
+//
+#define USB_MASS_STORE_RBC 0x01 ///< Reduced Block Commands
+#define USB_MASS_STORE_8020I 0x02 ///< SFF-8020i, typically a CD/DVD device
+#define USB_MASS_STORE_QIC 0x03 ///< Typically a tape device
+#define USB_MASS_STORE_UFI 0x04 ///< Typically a floppy disk driver device
+#define USB_MASS_STORE_8070I 0x05 ///< SFF-8070i, typically a floppy disk driver device.
+#define USB_MASS_STORE_SCSI 0x06 ///< SCSI transparent command set
+
+//
+// Usb mass storage protocol code, specify the transport protocol
+//
+#define USB_MASS_STORE_CBI0 0x00 ///< CBI protocol with command completion interrupt
+#define USB_MASS_STORE_CBI1 0x01 ///< CBI protocol without command completion interrupt
+#define USB_MASS_STORE_BOT 0x50 ///< Bulk-Only Transport
+
+//
+// Standard device request and request type
+// USB 2.0 spec, Section 9.4
+//
+#define USB_DEV_GET_STATUS 0x00
+#define USB_DEV_GET_STATUS_REQ_TYPE_D 0x80 // Receiver : Device
+#define USB_DEV_GET_STATUS_REQ_TYPE_I 0x81 // Receiver : Interface
+#define USB_DEV_GET_STATUS_REQ_TYPE_E 0x82 // Receiver : Endpoint
+
+#define USB_DEV_CLEAR_FEATURE 0x01
+#define USB_DEV_CLEAR_FEATURE_REQ_TYPE_D 0x00 // Receiver : Device
+#define USB_DEV_CLEAR_FEATURE_REQ_TYPE_I 0x01 // Receiver : Interface
+#define USB_DEV_CLEAR_FEATURE_REQ_TYPE_E 0x02 // Receiver : Endpoint
+
+#define USB_DEV_SET_FEATURE 0x03
+#define USB_DEV_SET_FEATURE_REQ_TYPE_D 0x00 // Receiver : Device
+#define USB_DEV_SET_FEATURE_REQ_TYPE_I 0x01 // Receiver : Interface
+#define USB_DEV_SET_FEATURE_REQ_TYPE_E 0x02 // Receiver : Endpoint
+
+#define USB_DEV_SET_ADDRESS 0x05
+#define USB_DEV_SET_ADDRESS_REQ_TYPE 0x00
+
+#define USB_DEV_GET_DESCRIPTOR 0x06
+#define USB_DEV_GET_DESCRIPTOR_REQ_TYPE 0x80
+
+#define USB_DEV_SET_DESCRIPTOR 0x07
+#define USB_DEV_SET_DESCRIPTOR_REQ_TYPE 0x00
+
+#define USB_DEV_GET_CONFIGURATION 0x08
+#define USB_DEV_GET_CONFIGURATION_REQ_TYPE 0x80
+
+#define USB_DEV_SET_CONFIGURATION 0x09
+#define USB_DEV_SET_CONFIGURATION_REQ_TYPE 0x00
+
+#define USB_DEV_GET_INTERFACE 0x0A
+#define USB_DEV_GET_INTERFACE_REQ_TYPE 0x81
+
+#define USB_DEV_SET_INTERFACE 0x0B
+#define USB_DEV_SET_INTERFACE_REQ_TYPE 0x01
+
+#define USB_DEV_SYNCH_FRAME 0x0C
+#define USB_DEV_SYNCH_FRAME_REQ_TYPE 0x82
+
+//
+// USB standard descriptors and reqeust
+//
+#pragma pack(1)
+
+///
+/// Format of Setup Data for USB Device Requests
+/// USB 2.0 spec, Section 9.3
+///
+typedef struct {
+ UINT8 RequestType;
+ UINT8 Request;
+ UINT16 Value;
+ UINT16 Index;
+ UINT16 Length;
+} USB_DEVICE_REQUEST;
+
+///
+/// Standard Device Descriptor
+/// USB 2.0 spec, Section 9.6.1
+///
+typedef struct {
+ UINT8 Length;
+ UINT8 DescriptorType;
+ UINT16 BcdUSB;
+ UINT8 DeviceClass;
+ UINT8 DeviceSubClass;
+ UINT8 DeviceProtocol;
+ UINT8 MaxPacketSize0;
+ UINT16 IdVendor;
+ UINT16 IdProduct;
+ UINT16 BcdDevice;
+ UINT8 StrManufacturer;
+ UINT8 StrProduct;
+ UINT8 StrSerialNumber;
+ UINT8 NumConfigurations;
+} USB_DEVICE_DESCRIPTOR;
+
+///
+/// Standard Configuration Descriptor
+/// USB 2.0 spec, Section 9.6.3
+///
+typedef struct {
+ UINT8 Length;
+ UINT8 DescriptorType;
+ UINT16 TotalLength;
+ UINT8 NumInterfaces;
+ UINT8 ConfigurationValue;
+ UINT8 Configuration;
+ UINT8 Attributes;
+ UINT8 MaxPower;
+} USB_CONFIG_DESCRIPTOR;
+
+///
+/// Standard Interface Descriptor
+/// USB 2.0 spec, Section 9.6.5
+///
+typedef struct {
+ UINT8 Length;
+ UINT8 DescriptorType;
+ UINT8 InterfaceNumber;
+ UINT8 AlternateSetting;
+ UINT8 NumEndpoints;
+ UINT8 InterfaceClass;
+ UINT8 InterfaceSubClass;
+ UINT8 InterfaceProtocol;
+ UINT8 Interface;
+} USB_INTERFACE_DESCRIPTOR;
+
+///
+/// Standard Endpoint Descriptor
+/// USB 2.0 spec, Section 9.6.6
+///
+typedef struct {
+ UINT8 Length;
+ UINT8 DescriptorType;
+ UINT8 EndpointAddress;
+ UINT8 Attributes;
+ UINT16 MaxPacketSize;
+ UINT8 Interval;
+} USB_ENDPOINT_DESCRIPTOR;
+
+///
+/// UNICODE String Descriptor
+/// USB 2.0 spec, Section 9.6.7
+///
+typedef struct {
+ UINT8 Length;
+ UINT8 DescriptorType;
+ CHAR16 String[1];
+} EFI_USB_STRING_DESCRIPTOR;
+
+#pragma pack()
+
+typedef enum {
+ //
+ // USB request type
+ //
+ USB_REQ_TYPE_STANDARD = (0x00 << 5),
+ USB_REQ_TYPE_CLASS = (0x01 << 5),
+ USB_REQ_TYPE_VENDOR = (0x02 << 5),
+
+ //
+ // Standard control transfer request type, or the value
+ // to fill in EFI_USB_DEVICE_REQUEST.Request
+ //
+ USB_REQ_GET_STATUS = 0x00,
+ USB_REQ_CLEAR_FEATURE = 0x01,
+ USB_REQ_SET_FEATURE = 0x03,
+ USB_REQ_SET_ADDRESS = 0x05,
+ USB_REQ_GET_DESCRIPTOR = 0x06,
+ USB_REQ_SET_DESCRIPTOR = 0x07,
+ USB_REQ_GET_CONFIG = 0x08,
+ USB_REQ_SET_CONFIG = 0x09,
+ USB_REQ_GET_INTERFACE = 0x0A,
+ USB_REQ_SET_INTERFACE = 0x0B,
+ USB_REQ_SYNCH_FRAME = 0x0C,
+
+ //
+ // Usb control transfer target
+ //
+ USB_TARGET_DEVICE = 0,
+ USB_TARGET_INTERFACE = 0x01,
+ USB_TARGET_ENDPOINT = 0x02,
+ USB_TARGET_OTHER = 0x03,
+
+ //
+ // USB Descriptor types
+ //
+ USB_DESC_TYPE_DEVICE = 0x01,
+ USB_DESC_TYPE_CONFIG = 0x02,
+ USB_DESC_TYPE_STRING = 0x03,
+ USB_DESC_TYPE_INTERFACE = 0x04,
+ USB_DESC_TYPE_ENDPOINT = 0x05,
+ USB_DESC_TYPE_HID = 0x21,
+ USB_DESC_TYPE_REPORT = 0x22,
+
+ //
+ // Features to be cleared by CLEAR_FEATURE requests
+ //
+ USB_FEATURE_ENDPOINT_HALT = 0,
+
+ //
+ // USB endpoint types: 00: control, 01: isochronous, 10: bulk, 11: interrupt
+ //
+ USB_ENDPOINT_CONTROL = 0x00,
+ USB_ENDPOINT_ISO = 0x01,
+ USB_ENDPOINT_BULK = 0x02,
+ USB_ENDPOINT_INTERRUPT = 0x03,
+
+ USB_ENDPOINT_TYPE_MASK = 0x03,
+ USB_ENDPOINT_DIR_IN = 0x80,
+
+ //
+ // Use 200 ms to increase the error handling response time
+ //
+ EFI_USB_INTERRUPT_DELAY = 2000000
+} USB_TYPES_DEFINITION;
+
+//
+// HID constants definition, see Device Class Definition
+// for Human Interface Devices (HID) rev1.11
+//
+
+//
+// HID standard GET_DESCRIPTOR request.
+//
+#define USB_HID_GET_DESCRIPTOR_REQ_TYPE 0x81
+
+//
+// HID specific requests.
+//
+#define USB_HID_CLASS_GET_REQ_TYPE 0xa1
+#define USB_HID_CLASS_SET_REQ_TYPE 0x21
+
+//
+// HID report item format
+//
+#define HID_ITEM_FORMAT_SHORT 0
+#define HID_ITEM_FORMAT_LONG 1
+
+//
+// Special tag indicating long items
+//
+#define HID_ITEM_TAG_LONG 15
+
+//
+// HID report descriptor item type (prefix bit 2,3)
+//
+#define HID_ITEM_TYPE_MAIN 0
+#define HID_ITEM_TYPE_GLOBAL 1
+#define HID_ITEM_TYPE_LOCAL 2
+#define HID_ITEM_TYPE_RESERVED 3
+
+//
+// HID report descriptor main item tags
+//
+#define HID_MAIN_ITEM_TAG_INPUT 8
+#define HID_MAIN_ITEM_TAG_OUTPUT 9
+#define HID_MAIN_ITEM_TAG_FEATURE 11
+#define HID_MAIN_ITEM_TAG_BEGIN_COLLECTION 10
+#define HID_MAIN_ITEM_TAG_END_COLLECTION 12
+
+//
+// HID report descriptor main item contents
+//
+#define HID_MAIN_ITEM_CONSTANT 0x001
+#define HID_MAIN_ITEM_VARIABLE 0x002
+#define HID_MAIN_ITEM_RELATIVE 0x004
+#define HID_MAIN_ITEM_WRAP 0x008
+#define HID_MAIN_ITEM_NONLINEAR 0x010
+#define HID_MAIN_ITEM_NO_PREFERRED 0x020
+#define HID_MAIN_ITEM_NULL_STATE 0x040
+#define HID_MAIN_ITEM_VOLATILE 0x080
+#define HID_MAIN_ITEM_BUFFERED_BYTE 0x100
+
+//
+// HID report descriptor collection item types
+//
+#define HID_COLLECTION_PHYSICAL 0
+#define HID_COLLECTION_APPLICATION 1
+#define HID_COLLECTION_LOGICAL 2
+
+//
+// HID report descriptor global item tags
+//
+#define HID_GLOBAL_ITEM_TAG_USAGE_PAGE 0
+#define HID_GLOBAL_ITEM_TAG_LOGICAL_MINIMUM 1
+#define HID_GLOBAL_ITEM_TAG_LOGICAL_MAXIMUM 2
+#define HID_GLOBAL_ITEM_TAG_PHYSICAL_MINIMUM 3
+#define HID_GLOBAL_ITEM_TAG_PHYSICAL_MAXIMUM 4
+#define HID_GLOBAL_ITEM_TAG_UNIT_EXPONENT 5
+#define HID_GLOBAL_ITEM_TAG_UNIT 6
+#define HID_GLOBAL_ITEM_TAG_REPORT_SIZE 7
+#define HID_GLOBAL_ITEM_TAG_REPORT_ID 8
+#define HID_GLOBAL_ITEM_TAG_REPORT_COUNT 9
+#define HID_GLOBAL_ITEM_TAG_PUSH 10
+#define HID_GLOBAL_ITEM_TAG_POP 11
+
+//
+// HID report descriptor local item tags
+//
+#define HID_LOCAL_ITEM_TAG_USAGE 0
+#define HID_LOCAL_ITEM_TAG_USAGE_MINIMUM 1
+#define HID_LOCAL_ITEM_TAG_USAGE_MAXIMUM 2
+#define HID_LOCAL_ITEM_TAG_DESIGNATOR_INDEX 3
+#define HID_LOCAL_ITEM_TAG_DESIGNATOR_MINIMUM 4
+#define HID_LOCAL_ITEM_TAG_DESIGNATOR_MAXIMUM 5
+#define HID_LOCAL_ITEM_TAG_STRING_INDEX 7
+#define HID_LOCAL_ITEM_TAG_STRING_MINIMUM 8
+#define HID_LOCAL_ITEM_TAG_STRING_MAXIMUM 9
+#define HID_LOCAL_ITEM_TAG_DELIMITER 10
+
+//
+// HID report types
+//
+#define HID_INPUT_REPORT 1
+#define HID_OUTPUT_REPORT 2
+#define HID_FEATURE_REPORT 3
+
+//
+// HID class protocol request
+//
+#define EFI_USB_GET_REPORT_REQUEST 0x01
+#define EFI_USB_GET_IDLE_REQUEST 0x02
+#define EFI_USB_GET_PROTOCOL_REQUEST 0x03
+#define EFI_USB_SET_REPORT_REQUEST 0x09
+#define EFI_USB_SET_IDLE_REQUEST 0x0a
+#define EFI_USB_SET_PROTOCOL_REQUEST 0x0b
+
+#pragma pack(1)
+///
+/// Descriptor header for Report/Physical Descriptors
+/// HID 1.1, section 6.2.1
+///
+typedef struct hid_class_descriptor {
+ UINT8 DescriptorType;
+ UINT16 DescriptorLength;
+} EFI_USB_HID_CLASS_DESCRIPTOR;
+
+///
+/// The HID descriptor identifies the length and type
+/// of subordinate descriptors for a device.
+/// HID 1.1, section 6.2.1
+///
+typedef struct hid_descriptor {
+ UINT8 Length;
+ UINT8 DescriptorType;
+ UINT16 BcdHID;
+ UINT8 CountryCode;
+ UINT8 NumDescriptors;
+ EFI_USB_HID_CLASS_DESCRIPTOR HidClassDesc[1];
+} EFI_USB_HID_DESCRIPTOR;
+
+#pragma pack()
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/WatchdogActionTable.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/WatchdogActionTable.h
new file mode 100644
index 0000000000..bc9dddfd71
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/WatchdogActionTable.h
@@ -0,0 +1,89 @@
+/** @file
+ ACPI Watchdog Action Table (WADT) as defined at
+ Microsoft Hardware Watchdog Timers Design Specification.
+
+ Copyright (c) 2008 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _WATCHDOG_ACTION_TABLE_H_
+#define _WATCHDOG_ACTION_TABLE_H_
+
+#include
+
+//
+// Ensure proper structure formats
+//
+#pragma pack(1)
+///
+/// Watchdog Action Table definition.
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 WatchdogHeaderLength;
+ UINT16 PCISegment;
+ UINT8 PCIBusNumber;
+ UINT8 PCIDeviceNumber;
+ UINT8 PCIFunctionNumber;
+ UINT8 Reserved_45[3];
+ UINT32 TimerPeriod;
+ UINT32 MaxCount;
+ UINT32 MinCount;
+ UINT8 WatchdogFlags;
+ UINT8 Reserved_61[3];
+ UINT32 NumberWatchdogInstructionEntries;
+} EFI_ACPI_WATCHDOG_ACTION_1_0_TABLE;
+
+///
+/// Watchdog Instruction Entries
+///
+typedef struct {
+ UINT8 WatchdogAction;
+ UINT8 InstructionFlags;
+ UINT8 Reserved_2[2];
+ EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE RegisterRegion;
+ UINT32 Value;
+ UINT32 Mask;
+} EFI_ACPI_WATCHDOG_ACTION_1_0_WATCHDOG_ACTION_INSTRUCTION_ENTRY;
+
+#pragma pack()
+
+///
+/// WDAT Revision (defined in spec)
+///
+#define EFI_ACPI_WATCHDOG_ACTION_1_0_TABLE_REVISION 0x01
+
+//
+// WDAT 1.0 Flags
+//
+#define EFI_ACPI_WDAT_1_0_WATCHDOG_ENABLED 0x1
+#define EFI_ACPI_WDAT_1_0_WATCHDOG_STOPPED_IN_SLEEP_STATE 0x80
+
+//
+// WDAT 1.0 Watchdog Actions
+//
+#define EFI_ACPI_WDAT_1_0_WATCHDOG_ACTION_RESET 0x1
+#define EFI_ACPI_WDAT_1_0_WATCHDOG_ACTION_QUERY_CURRENT_COUNTDOWN_PERIOD 0x4
+#define EFI_ACPI_WDAT_1_0_WATCHDOG_ACTION_QUERY_COUNTDOWN_PERIOD 0x5
+#define EFI_ACPI_WDAT_1_0_WATCHDOG_ACTION_SET_COUNTDOWN_PERIOD 0x6
+#define EFI_ACPI_WDAT_1_0_WATCHDOG_ACTION_QUERY_RUNNING_STATE 0x8
+#define EFI_ACPI_WDAT_1_0_WATCHDOG_ACTION_SET_RUNNING_STATE 0x9
+#define EFI_ACPI_WDAT_1_0_WATCHDOG_ACTION_QUERY_STOPPED_STATE 0xA
+#define EFI_ACPI_WDAT_1_0_WATCHDOG_ACTION_SET_STOPPED_STATE 0xB
+#define EFI_ACPI_WDAT_1_0_WATCHDOG_ACTION_QUERY_REBOOT 0x10
+#define EFI_ACPI_WDAT_1_0_WATCHDOG_ACTION_SET_REBOOT 0x11
+#define EFI_ACPI_WDAT_1_0_WATCHDOG_ACTION_QUERY_SHUTDOWN 0x12
+#define EFI_ACPI_WDAT_1_0_WATCHDOG_ACTION_SET_SHUTDOWN 0x13
+#define EFI_ACPI_WDAT_1_0_WATCHDOG_ACTION_QUERY_WATCHDOG_STATUS 0x20
+#define EFI_ACPI_WDAT_1_0_WATCHDOG_ACTION_SET_WATCHDOG_STATUS 0x21
+
+//
+// WDAT 1.0 Watchdog Action Entry Instruction Flags
+//
+#define EFI_ACPI_WDAT_1_0_WATCHDOG_INSTRUCTION_READ_VALUE 0x0
+#define EFI_ACPI_WDAT_1_0_WATCHDOG_INSTRUCTION_READ_COUNTDOWN 0x1
+#define EFI_ACPI_WDAT_1_0_WATCHDOG_INSTRUCTION_WRITE_VALUE 0x2
+#define EFI_ACPI_WDAT_1_0_WATCHDOG_INSTRUCTION_WRITE_COUNTDOWN 0x3
+#define EFI_ACPI_WDAT_1_0_WATCHDOG_INSTRUCTION_PRESERVE_REGISTER 0x80
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/WatchdogResourceTable.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/WatchdogResourceTable.h
new file mode 100644
index 0000000000..63cf3f9974
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/WatchdogResourceTable.h
@@ -0,0 +1,50 @@
+/** @file
+ ACPI Watchdog Resource Table (WDRT) as defined at
+ Microsoft Windows Hardware Developer Central.
+
+ Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _WATCHDOG_RESOURCE_TABLE_H_
+#define _WATCHDOG_RESOURCE_TABLE_H_
+
+#include
+
+//
+// Ensure proper structure formats
+//
+#pragma pack(1)
+
+///
+/// Watchdog Resource Table definition.
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE ControlRegisterAddress;
+ EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE CountRegisterAddress;
+ UINT16 PCIDeviceID;
+ UINT16 PCIVendorID;
+ UINT8 PCIBusNumber;
+ UINT8 PCIDeviceNumber;
+ UINT8 PCIFunctionNumber;
+ UINT8 PCISegment;
+ UINT16 MaxCount;
+ UINT8 Units;
+} EFI_ACPI_WATCHDOG_RESOURCE_1_0_TABLE;
+
+#pragma pack()
+
+//
+// WDRT Revision (defined in spec)
+//
+#define EFI_ACPI_WATCHDOG_RESOURCE_1_0_TABLE_REVISION 0x01
+
+//
+// WDRT 1.0 Count Unit
+//
+#define EFI_ACPI_WDRT_1_0_COUNT_UNIT_1_SEC_PER_COUNT 1
+#define EFI_ACPI_WDRT_1_0_COUNT_UNIT_100_MILLISEC_PER_COUNT 2
+#define EFI_ACPI_WDRT_1_0_COUNT_UNIT_10_MILLISEC_PER_COUNT 3
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/WindowsSmmSecurityMitigationTable.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/WindowsSmmSecurityMitigationTable.h
new file mode 100644
index 0000000000..74be417a29
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/WindowsSmmSecurityMitigationTable.h
@@ -0,0 +1,32 @@
+/** @file
+ Defines Windows SMM Security Mitigation Table
+ @ https://msdn.microsoft.com/windows/hardware/drivers/bringup/acpi-system-description-tables#wsmt
+
+ Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _WINDOWS_SMM_SECURITY_MITIGATION_TABLE_H_
+#define _WINDOWS_SMM_SECURITY_MITIGATION_TABLE_H_
+
+#include
+
+#define EFI_ACPI_WINDOWS_SMM_SECURITY_MITIGATION_TABLE_SIGNATURE SIGNATURE_32('W', 'S', 'M', 'T')
+
+#pragma pack(1)
+
+#define EFI_WSMT_TABLE_REVISION 1
+
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 ProtectionFlags;
+} EFI_ACPI_WSMT_TABLE;
+
+#define EFI_WSMT_PROTECTION_FLAGS_FIXED_COMM_BUFFERS 0x1
+#define EFI_WSMT_PROTECTION_FLAGS_COMM_BUFFER_NESTED_PTR_PROTECTION 0x2
+#define EFI_WSMT_PROTECTION_FLAGS_SYSTEM_RESOURCE_PROTECTION 0x4
+
+#pragma pack()
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/WindowsUxCapsule.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/WindowsUxCapsule.h
new file mode 100644
index 0000000000..0a53be639e
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/IndustryStandard/WindowsUxCapsule.h
@@ -0,0 +1,40 @@
+/** @file
+ Defines Windows UX Capsule GUID and layout defined at Microsoft
+ Windows UEFI Firmware Update Platform specification
+
+ Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _WINDOWS_UX_CAPSULE_GUID_H_
+#define _WINDOWS_UX_CAPSULE_GUID_H_
+
+#pragma pack(1)
+
+typedef struct {
+ UINT8 Version;
+ UINT8 Checksum;
+ UINT8 ImageType;
+ UINT8 Reserved;
+ UINT32 Mode;
+ UINT32 OffsetX;
+ UINT32 OffsetY;
+ // UINT8 Image[];
+} DISPLAY_DISPLAY_PAYLOAD;
+
+typedef struct {
+ EFI_CAPSULE_HEADER CapsuleHeader;
+ DISPLAY_DISPLAY_PAYLOAD ImagePayload;
+} EFI_DISPLAY_CAPSULE;
+
+#pragma pack()
+
+#define WINDOWS_UX_CAPSULE_GUID \
+ { \
+ 0x3b8c8162, 0x188c, 0x46a4, { 0xae, 0xc9, 0xbe, 0x43, 0xf1, 0xd6, 0x56, 0x97} \
+ }
+
+extern EFI_GUID gWindowsUxCapsuleGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/ArmTrngLib.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/ArmTrngLib.h
new file mode 100644
index 0000000000..9fc9fd0bb8
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/ArmTrngLib.h
@@ -0,0 +1,106 @@
+/** @file
+ Arm TRNG interface library definitions (Cf. [1]).
+
+ Copyright (c) 2021 - 2022, Arm Limited. All rights reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Reference(s):
+ - [1] Arm True Random Number Generator Firmware, Interface 1.0,
+ Platform Design Document.
+ (https://developer.arm.com/documentation/den0098/latest/)
+ - [2] NIST Special Publication 800-90B, Recommendation for the Entropy
+ Sources Used for Random Bit Generation.
+ (https://csrc.nist.gov/publications/detail/sp/800-90b/final)
+
+ @par Glossary:
+ - TRNG - True Random Number Generator
+**/
+
+#ifndef ARM_TRNG_LIB_H_
+#define ARM_TRNG_LIB_H_
+
+/** Get the version of the Arm TRNG backend.
+
+ A TRNG may be implemented by the system firmware, in which case this
+ function shall return the version of the Arm TRNG backend.
+ The implementation must return NOT_SUPPORTED if a Back end is not present.
+
+ @param [out] MajorRevision Major revision.
+ @param [out] MinorRevision Minor revision.
+
+ @retval RETURN_SUCCESS The function completed successfully.
+ @retval RETURN_INVALID_PARAMETER Invalid parameter.
+ @retval RETURN_UNSUPPORTED Backend not present.
+**/
+RETURN_STATUS
+EFIAPI
+GetArmTrngVersion (
+ OUT UINT16 *MajorRevision,
+ OUT UINT16 *MinorRevision
+ );
+
+/** Get the UUID of the Arm TRNG backend.
+
+ A TRNG may be implemented by the system firmware, in which case this
+ function shall return the UUID of the TRNG backend.
+ Returning the Arm TRNG UUID is optional and if not implemented,
+ RETURN_UNSUPPORTED shall be returned.
+
+ Note: The caller must not rely on the returned UUID as a trustworthy Arm TRNG
+ Back end identity
+
+ @param [out] Guid UUID of the Arm TRNG backend.
+
+ @retval RETURN_SUCCESS The function completed successfully.
+ @retval RETURN_INVALID_PARAMETER Invalid parameter.
+ @retval RETURN_UNSUPPORTED Function not implemented.
+**/
+RETURN_STATUS
+EFIAPI
+GetArmTrngUuid (
+ OUT GUID *Guid
+ );
+
+/** Returns maximum number of entropy bits that can be returned in a single
+ call.
+
+ @return Returns the maximum number of Entropy bits that can be returned
+ in a single call to GetArmTrngEntropy().
+**/
+UINTN
+EFIAPI
+GetArmTrngMaxSupportedEntropyBits (
+ VOID
+ );
+
+/** Returns N bits of conditioned entropy.
+
+ See [2] Section 2.3.1 GetEntropy: An Interface to the Entropy Source
+ GetEntropy
+ Input:
+ bits_of_entropy: the requested amount of entropy
+ Output:
+ entropy_bitstring: The string that provides the requested entropy.
+ status: A Boolean value that is TRUE if the request has been satisfied,
+ and is FALSE otherwise.
+
+ @param [in] EntropyBits Number of entropy bits requested.
+ @param [in] BufferSize Size of the Buffer in bytes.
+ @param [out] Buffer Buffer to return the entropy bits.
+
+ @retval RETURN_SUCCESS The function completed successfully.
+ @retval RETURN_INVALID_PARAMETER Invalid parameter.
+ @retval RETURN_UNSUPPORTED Function not implemented.
+ @retval RETURN_BAD_BUFFER_SIZE Buffer size is too small.
+ @retval RETURN_NOT_READY No Entropy available.
+**/
+RETURN_STATUS
+EFIAPI
+GetArmTrngEntropy (
+ IN UINTN EntropyBits,
+ IN UINTN BufferSize,
+ OUT UINT8 *Buffer
+ );
+
+#endif // ARM_TRNG_LIB_H_
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/BaseLib.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/BaseLib.h
new file mode 100644
index 0000000000..8d8c9564cf
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/BaseLib.h
@@ -0,0 +1,7633 @@
+/** @file
+ Provides string functions, linked list functions, math functions, synchronization
+ functions, file path functions, and CPU architecture-specific functions.
+
+Copyright (c) 2006 - 2021, Intel Corporation. All rights reserved.
+Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
+Copyright (c) Microsoft Corporation.
+Portions Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.
+Portions Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved.
+
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __BASE_LIB__
+#define __BASE_LIB__
+
+//
+// Definitions for architecture-specific types
+//
+#if defined (MDE_CPU_IA32)
+///
+/// The IA-32 architecture context buffer used by SetJump() and LongJump().
+///
+typedef struct {
+ UINT32 Ebx;
+ UINT32 Esi;
+ UINT32 Edi;
+ UINT32 Ebp;
+ UINT32 Esp;
+ UINT32 Eip;
+ UINT32 Ssp;
+} BASE_LIBRARY_JUMP_BUFFER;
+
+#define BASE_LIBRARY_JUMP_BUFFER_ALIGNMENT 4
+
+#endif // defined (MDE_CPU_IA32)
+
+#if defined (MDE_CPU_X64)
+///
+/// The x64 architecture context buffer used by SetJump() and LongJump().
+///
+typedef struct {
+ UINT64 Rbx;
+ UINT64 Rsp;
+ UINT64 Rbp;
+ UINT64 Rdi;
+ UINT64 Rsi;
+ UINT64 R12;
+ UINT64 R13;
+ UINT64 R14;
+ UINT64 R15;
+ UINT64 Rip;
+ UINT64 MxCsr;
+ UINT8 XmmBuffer[160]; ///< XMM6-XMM15.
+ UINT64 Ssp;
+} BASE_LIBRARY_JUMP_BUFFER;
+
+#define BASE_LIBRARY_JUMP_BUFFER_ALIGNMENT 8
+
+#endif // defined (MDE_CPU_X64)
+
+#if defined (MDE_CPU_EBC)
+///
+/// The EBC context buffer used by SetJump() and LongJump().
+///
+typedef struct {
+ UINT64 R0;
+ UINT64 R1;
+ UINT64 R2;
+ UINT64 R3;
+ UINT64 IP;
+} BASE_LIBRARY_JUMP_BUFFER;
+
+#define BASE_LIBRARY_JUMP_BUFFER_ALIGNMENT 8
+
+#endif // defined (MDE_CPU_EBC)
+
+#if defined (MDE_CPU_ARM)
+
+typedef struct {
+ UINT32 R3; ///< A copy of R13.
+ UINT32 R4;
+ UINT32 R5;
+ UINT32 R6;
+ UINT32 R7;
+ UINT32 R8;
+ UINT32 R9;
+ UINT32 R10;
+ UINT32 R11;
+ UINT32 R12;
+ UINT32 R14;
+} BASE_LIBRARY_JUMP_BUFFER;
+
+#define BASE_LIBRARY_JUMP_BUFFER_ALIGNMENT 4
+
+#endif // defined (MDE_CPU_ARM)
+
+#if defined (MDE_CPU_AARCH64)
+typedef struct {
+ // GP regs
+ UINT64 X19;
+ UINT64 X20;
+ UINT64 X21;
+ UINT64 X22;
+ UINT64 X23;
+ UINT64 X24;
+ UINT64 X25;
+ UINT64 X26;
+ UINT64 X27;
+ UINT64 X28;
+ UINT64 FP;
+ UINT64 LR;
+ UINT64 IP0;
+
+ // FP regs
+ UINT64 D8;
+ UINT64 D9;
+ UINT64 D10;
+ UINT64 D11;
+ UINT64 D12;
+ UINT64 D13;
+ UINT64 D14;
+ UINT64 D15;
+} BASE_LIBRARY_JUMP_BUFFER;
+
+#define BASE_LIBRARY_JUMP_BUFFER_ALIGNMENT 8
+
+#endif // defined (MDE_CPU_AARCH64)
+
+#if defined (MDE_CPU_RISCV64)
+///
+/// The RISC-V architecture context buffer used by SetJump() and LongJump().
+///
+typedef struct {
+ UINT64 RA;
+ UINT64 S0;
+ UINT64 S1;
+ UINT64 S2;
+ UINT64 S3;
+ UINT64 S4;
+ UINT64 S5;
+ UINT64 S6;
+ UINT64 S7;
+ UINT64 S8;
+ UINT64 S9;
+ UINT64 S10;
+ UINT64 S11;
+ UINT64 SP;
+} BASE_LIBRARY_JUMP_BUFFER;
+
+#define BASE_LIBRARY_JUMP_BUFFER_ALIGNMENT 8
+
+VOID
+RiscVSetSupervisorScratch (
+ IN UINT64
+ );
+
+UINT64
+RiscVGetSupervisorScratch (
+ VOID
+ );
+
+VOID
+RiscVSetSupervisorStvec (
+ IN UINT64
+ );
+
+UINT64
+RiscVGetSupervisorStvec (
+ VOID
+ );
+
+UINT64
+RiscVGetSupervisorTrapCause (
+ VOID
+ );
+
+VOID
+RiscVSetSupervisorAddressTranslationRegister (
+ IN UINT64
+ );
+
+UINT64
+RiscVReadTimer (
+ VOID
+ );
+
+VOID
+RiscVEnableTimerInterrupt (
+ VOID
+ );
+
+VOID
+RiscVDisableTimerInterrupt (
+ VOID
+ );
+
+VOID
+RiscVClearPendingTimerInterrupt (
+ VOID
+ );
+
+#endif // defined (MDE_CPU_RISCV64)
+
+#if defined (MDE_CPU_LOONGARCH64)
+///
+/// The LoongArch architecture context buffer used by SetJump() and LongJump()
+///
+typedef struct {
+ UINT64 S0;
+ UINT64 S1;
+ UINT64 S2;
+ UINT64 S3;
+ UINT64 S4;
+ UINT64 S5;
+ UINT64 S6;
+ UINT64 S7;
+ UINT64 S8;
+ UINT64 SP;
+ UINT64 FP;
+ UINT64 RA;
+} BASE_LIBRARY_JUMP_BUFFER;
+
+#define BASE_LIBRARY_JUMP_BUFFER_ALIGNMENT 8
+
+#endif // defined (MDE_CPU_LOONGARCH64)
+
+//
+// String Services
+//
+
+/**
+ Returns the length of a Null-terminated Unicode string.
+
+ This function is similar as strlen_s defined in C11.
+
+ If String is not aligned on a 16-bit boundary, then ASSERT().
+
+ @param String A pointer to a Null-terminated Unicode string.
+ @param MaxSize The maximum number of Destination Unicode
+ char, including terminating null char.
+
+ @retval 0 If String is NULL.
+ @retval MaxSize If there is no null character in the first MaxSize characters of String.
+ @return The number of characters that percede the terminating null character.
+
+**/
+UINTN
+EFIAPI
+StrnLenS (
+ IN CONST CHAR16 *String,
+ IN UINTN MaxSize
+ );
+
+/**
+ Returns the size of a Null-terminated Unicode string in bytes, including the
+ Null terminator.
+
+ This function returns the size of the Null-terminated Unicode string
+ specified by String in bytes, including the Null terminator.
+
+ If String is not aligned on a 16-bit boundary, then ASSERT().
+
+ @param String A pointer to a Null-terminated Unicode string.
+ @param MaxSize The maximum number of Destination Unicode
+ char, including the Null terminator.
+
+ @retval 0 If String is NULL.
+ @retval (sizeof (CHAR16) * (MaxSize + 1))
+ If there is no Null terminator in the first MaxSize characters of
+ String.
+ @return The size of the Null-terminated Unicode string in bytes, including
+ the Null terminator.
+
+**/
+UINTN
+EFIAPI
+StrnSizeS (
+ IN CONST CHAR16 *String,
+ IN UINTN MaxSize
+ );
+
+/**
+ Copies the string pointed to by Source (including the terminating null char)
+ to the array pointed to by Destination.
+
+ This function is similar as strcpy_s defined in C11.
+
+ If Destination is not aligned on a 16-bit boundary, then ASSERT().
+ If Source is not aligned on a 16-bit boundary, then ASSERT().
+
+ If an error is returned, then the Destination is unmodified.
+
+ @param Destination A pointer to a Null-terminated Unicode string.
+ @param DestMax The maximum number of Destination Unicode
+ char, including terminating null char.
+ @param Source A pointer to a Null-terminated Unicode string.
+
+ @retval RETURN_SUCCESS String is copied.
+ @retval RETURN_BUFFER_TOO_SMALL If DestMax is NOT greater than StrLen(Source).
+ @retval RETURN_INVALID_PARAMETER If Destination is NULL.
+ If Source is NULL.
+ If PcdMaximumUnicodeStringLength is not zero,
+ and DestMax is greater than
+ PcdMaximumUnicodeStringLength.
+ If DestMax is 0.
+ @retval RETURN_ACCESS_DENIED If Source and Destination overlap.
+**/
+RETURN_STATUS
+EFIAPI
+StrCpyS (
+ OUT CHAR16 *Destination,
+ IN UINTN DestMax,
+ IN CONST CHAR16 *Source
+ );
+
+/**
+ Copies not more than Length successive char from the string pointed to by
+ Source to the array pointed to by Destination. If no null char is copied from
+ Source, then Destination[Length] is always set to null.
+
+ This function is similar as strncpy_s defined in C11.
+
+ If Length > 0 and Destination is not aligned on a 16-bit boundary, then ASSERT().
+ If Length > 0 and Source is not aligned on a 16-bit boundary, then ASSERT().
+
+ If an error is returned, then the Destination is unmodified.
+
+ @param Destination A pointer to a Null-terminated Unicode string.
+ @param DestMax The maximum number of Destination Unicode
+ char, including terminating null char.
+ @param Source A pointer to a Null-terminated Unicode string.
+ @param Length The maximum number of Unicode characters to copy.
+
+ @retval RETURN_SUCCESS String is copied.
+ @retval RETURN_BUFFER_TOO_SMALL If DestMax is NOT greater than
+ MIN(StrLen(Source), Length).
+ @retval RETURN_INVALID_PARAMETER If Destination is NULL.
+ If Source is NULL.
+ If PcdMaximumUnicodeStringLength is not zero,
+ and DestMax is greater than
+ PcdMaximumUnicodeStringLength.
+ If DestMax is 0.
+ @retval RETURN_ACCESS_DENIED If Source and Destination overlap.
+**/
+RETURN_STATUS
+EFIAPI
+StrnCpyS (
+ OUT CHAR16 *Destination,
+ IN UINTN DestMax,
+ IN CONST CHAR16 *Source,
+ IN UINTN Length
+ );
+
+/**
+ Appends a copy of the string pointed to by Source (including the terminating
+ null char) to the end of the string pointed to by Destination.
+
+ This function is similar as strcat_s defined in C11.
+
+ If Destination is not aligned on a 16-bit boundary, then ASSERT().
+ If Source is not aligned on a 16-bit boundary, then ASSERT().
+
+ If an error is returned, then the Destination is unmodified.
+
+ @param Destination A pointer to a Null-terminated Unicode string.
+ @param DestMax The maximum number of Destination Unicode
+ char, including terminating null char.
+ @param Source A pointer to a Null-terminated Unicode string.
+
+ @retval RETURN_SUCCESS String is appended.
+ @retval RETURN_BAD_BUFFER_SIZE If DestMax is NOT greater than
+ StrLen(Destination).
+ @retval RETURN_BUFFER_TOO_SMALL If (DestMax - StrLen(Destination)) is NOT
+ greater than StrLen(Source).
+ @retval RETURN_INVALID_PARAMETER If Destination is NULL.
+ If Source is NULL.
+ If PcdMaximumUnicodeStringLength is not zero,
+ and DestMax is greater than
+ PcdMaximumUnicodeStringLength.
+ If DestMax is 0.
+ @retval RETURN_ACCESS_DENIED If Source and Destination overlap.
+**/
+RETURN_STATUS
+EFIAPI
+StrCatS (
+ IN OUT CHAR16 *Destination,
+ IN UINTN DestMax,
+ IN CONST CHAR16 *Source
+ );
+
+/**
+ Appends not more than Length successive char from the string pointed to by
+ Source to the end of the string pointed to by Destination. If no null char is
+ copied from Source, then Destination[StrLen(Destination) + Length] is always
+ set to null.
+
+ This function is similar as strncat_s defined in C11.
+
+ If Destination is not aligned on a 16-bit boundary, then ASSERT().
+ If Source is not aligned on a 16-bit boundary, then ASSERT().
+
+ If an error is returned, then the Destination is unmodified.
+
+ @param Destination A pointer to a Null-terminated Unicode string.
+ @param DestMax The maximum number of Destination Unicode
+ char, including terminating null char.
+ @param Source A pointer to a Null-terminated Unicode string.
+ @param Length The maximum number of Unicode characters to copy.
+
+ @retval RETURN_SUCCESS String is appended.
+ @retval RETURN_BAD_BUFFER_SIZE If DestMax is NOT greater than
+ StrLen(Destination).
+ @retval RETURN_BUFFER_TOO_SMALL If (DestMax - StrLen(Destination)) is NOT
+ greater than MIN(StrLen(Source), Length).
+ @retval RETURN_INVALID_PARAMETER If Destination is NULL.
+ If Source is NULL.
+ If PcdMaximumUnicodeStringLength is not zero,
+ and DestMax is greater than
+ PcdMaximumUnicodeStringLength.
+ If DestMax is 0.
+ @retval RETURN_ACCESS_DENIED If Source and Destination overlap.
+**/
+RETURN_STATUS
+EFIAPI
+StrnCatS (
+ IN OUT CHAR16 *Destination,
+ IN UINTN DestMax,
+ IN CONST CHAR16 *Source,
+ IN UINTN Length
+ );
+
+/**
+ Convert a Null-terminated Unicode decimal string to a value of type UINTN.
+
+ This function outputs a value of type UINTN by interpreting the contents of
+ the Unicode string specified by String as a decimal number. The format of the
+ input Unicode string String is:
+
+ [spaces] [decimal digits].
+
+ The valid decimal digit character is in the range [0-9]. The function will
+ ignore the pad space, which includes spaces or tab characters, before
+ [decimal digits]. The running zero in the beginning of [decimal digits] will
+ be ignored. Then, the function stops at the first character that is a not a
+ valid decimal character or a Null-terminator, whichever one comes first.
+
+ If String is not aligned in a 16-bit boundary, then ASSERT().
+
+ If String has no valid decimal digits in the above format, then 0 is stored
+ at the location pointed to by Data.
+ If the number represented by String exceeds the range defined by UINTN, then
+ MAX_UINTN is stored at the location pointed to by Data.
+
+ If EndPointer is not NULL, a pointer to the character that stopped the scan
+ is stored at the location pointed to by EndPointer. If String has no valid
+ decimal digits right after the optional pad spaces, the value of String is
+ stored at the location pointed to by EndPointer.
+
+ @param String Pointer to a Null-terminated Unicode string.
+ @param EndPointer Pointer to character that stops scan.
+ @param Data Pointer to the converted value.
+
+ @retval RETURN_SUCCESS Value is translated from String.
+ @retval RETURN_INVALID_PARAMETER If String is NULL.
+ If Data is NULL.
+ If PcdMaximumUnicodeStringLength is not
+ zero, and String contains more than
+ PcdMaximumUnicodeStringLength Unicode
+ characters, not including the
+ Null-terminator.
+ @retval RETURN_UNSUPPORTED If the number represented by String exceeds
+ the range defined by UINTN.
+
+**/
+RETURN_STATUS
+EFIAPI
+StrDecimalToUintnS (
+ IN CONST CHAR16 *String,
+ OUT CHAR16 **EndPointer OPTIONAL,
+ OUT UINTN *Data
+ );
+
+/**
+ Convert a Null-terminated Unicode decimal string to a value of type UINT64.
+
+ This function outputs a value of type UINT64 by interpreting the contents of
+ the Unicode string specified by String as a decimal number. The format of the
+ input Unicode string String is:
+
+ [spaces] [decimal digits].
+
+ The valid decimal digit character is in the range [0-9]. The function will
+ ignore the pad space, which includes spaces or tab characters, before
+ [decimal digits]. The running zero in the beginning of [decimal digits] will
+ be ignored. Then, the function stops at the first character that is a not a
+ valid decimal character or a Null-terminator, whichever one comes first.
+
+ If String is not aligned in a 16-bit boundary, then ASSERT().
+
+ If String has no valid decimal digits in the above format, then 0 is stored
+ at the location pointed to by Data.
+ If the number represented by String exceeds the range defined by UINT64, then
+ MAX_UINT64 is stored at the location pointed to by Data.
+
+ If EndPointer is not NULL, a pointer to the character that stopped the scan
+ is stored at the location pointed to by EndPointer. If String has no valid
+ decimal digits right after the optional pad spaces, the value of String is
+ stored at the location pointed to by EndPointer.
+
+ @param String Pointer to a Null-terminated Unicode string.
+ @param EndPointer Pointer to character that stops scan.
+ @param Data Pointer to the converted value.
+
+ @retval RETURN_SUCCESS Value is translated from String.
+ @retval RETURN_INVALID_PARAMETER If String is NULL.
+ If Data is NULL.
+ If PcdMaximumUnicodeStringLength is not
+ zero, and String contains more than
+ PcdMaximumUnicodeStringLength Unicode
+ characters, not including the
+ Null-terminator.
+ @retval RETURN_UNSUPPORTED If the number represented by String exceeds
+ the range defined by UINT64.
+
+**/
+RETURN_STATUS
+EFIAPI
+StrDecimalToUint64S (
+ IN CONST CHAR16 *String,
+ OUT CHAR16 **EndPointer OPTIONAL,
+ OUT UINT64 *Data
+ );
+
+/**
+ Convert a Null-terminated Unicode hexadecimal string to a value of type
+ UINTN.
+
+ This function outputs a value of type UINTN by interpreting the contents of
+ the Unicode string specified by String as a hexadecimal number. The format of
+ the input Unicode string String is:
+
+ [spaces][zeros][x][hexadecimal digits].
+
+ The valid hexadecimal digit character is in the range [0-9], [a-f] and [A-F].
+ The prefix "0x" is optional. Both "x" and "X" is allowed in "0x" prefix.
+ If "x" appears in the input string, it must be prefixed with at least one 0.
+ The function will ignore the pad space, which includes spaces or tab
+ characters, before [zeros], [x] or [hexadecimal digit]. The running zero
+ before [x] or [hexadecimal digit] will be ignored. Then, the decoding starts
+ after [x] or the first valid hexadecimal digit. Then, the function stops at
+ the first character that is a not a valid hexadecimal character or NULL,
+ whichever one comes first.
+
+ If String is not aligned in a 16-bit boundary, then ASSERT().
+
+ If String has no valid hexadecimal digits in the above format, then 0 is
+ stored at the location pointed to by Data.
+ If the number represented by String exceeds the range defined by UINTN, then
+ MAX_UINTN is stored at the location pointed to by Data.
+
+ If EndPointer is not NULL, a pointer to the character that stopped the scan
+ is stored at the location pointed to by EndPointer. If String has no valid
+ hexadecimal digits right after the optional pad spaces, the value of String
+ is stored at the location pointed to by EndPointer.
+
+ @param String Pointer to a Null-terminated Unicode string.
+ @param EndPointer Pointer to character that stops scan.
+ @param Data Pointer to the converted value.
+
+ @retval RETURN_SUCCESS Value is translated from String.
+ @retval RETURN_INVALID_PARAMETER If String is NULL.
+ If Data is NULL.
+ If PcdMaximumUnicodeStringLength is not
+ zero, and String contains more than
+ PcdMaximumUnicodeStringLength Unicode
+ characters, not including the
+ Null-terminator.
+ @retval RETURN_UNSUPPORTED If the number represented by String exceeds
+ the range defined by UINTN.
+
+**/
+RETURN_STATUS
+EFIAPI
+StrHexToUintnS (
+ IN CONST CHAR16 *String,
+ OUT CHAR16 **EndPointer OPTIONAL,
+ OUT UINTN *Data
+ );
+
+/**
+ Convert a Null-terminated Unicode hexadecimal string to a value of type
+ UINT64.
+
+ This function outputs a value of type UINT64 by interpreting the contents of
+ the Unicode string specified by String as a hexadecimal number. The format of
+ the input Unicode string String is:
+
+ [spaces][zeros][x][hexadecimal digits].
+
+ The valid hexadecimal digit character is in the range [0-9], [a-f] and [A-F].
+ The prefix "0x" is optional. Both "x" and "X" is allowed in "0x" prefix.
+ If "x" appears in the input string, it must be prefixed with at least one 0.
+ The function will ignore the pad space, which includes spaces or tab
+ characters, before [zeros], [x] or [hexadecimal digit]. The running zero
+ before [x] or [hexadecimal digit] will be ignored. Then, the decoding starts
+ after [x] or the first valid hexadecimal digit. Then, the function stops at
+ the first character that is a not a valid hexadecimal character or NULL,
+ whichever one comes first.
+
+ If String is not aligned in a 16-bit boundary, then ASSERT().
+
+ If String has no valid hexadecimal digits in the above format, then 0 is
+ stored at the location pointed to by Data.
+ If the number represented by String exceeds the range defined by UINT64, then
+ MAX_UINT64 is stored at the location pointed to by Data.
+
+ If EndPointer is not NULL, a pointer to the character that stopped the scan
+ is stored at the location pointed to by EndPointer. If String has no valid
+ hexadecimal digits right after the optional pad spaces, the value of String
+ is stored at the location pointed to by EndPointer.
+
+ @param String Pointer to a Null-terminated Unicode string.
+ @param EndPointer Pointer to character that stops scan.
+ @param Data Pointer to the converted value.
+
+ @retval RETURN_SUCCESS Value is translated from String.
+ @retval RETURN_INVALID_PARAMETER If String is NULL.
+ If Data is NULL.
+ If PcdMaximumUnicodeStringLength is not
+ zero, and String contains more than
+ PcdMaximumUnicodeStringLength Unicode
+ characters, not including the
+ Null-terminator.
+ @retval RETURN_UNSUPPORTED If the number represented by String exceeds
+ the range defined by UINT64.
+
+**/
+RETURN_STATUS
+EFIAPI
+StrHexToUint64S (
+ IN CONST CHAR16 *String,
+ OUT CHAR16 **EndPointer OPTIONAL,
+ OUT UINT64 *Data
+ );
+
+/**
+ Returns the length of a Null-terminated Ascii string.
+
+ This function is similar as strlen_s defined in C11.
+
+ @param String A pointer to a Null-terminated Ascii string.
+ @param MaxSize The maximum number of Destination Ascii
+ char, including terminating null char.
+
+ @retval 0 If String is NULL.
+ @retval MaxSize If there is no null character in the first MaxSize characters of String.
+ @return The number of characters that percede the terminating null character.
+
+**/
+UINTN
+EFIAPI
+AsciiStrnLenS (
+ IN CONST CHAR8 *String,
+ IN UINTN MaxSize
+ );
+
+/**
+ Returns the size of a Null-terminated Ascii string in bytes, including the
+ Null terminator.
+
+ This function returns the size of the Null-terminated Ascii string specified
+ by String in bytes, including the Null terminator.
+
+ @param String A pointer to a Null-terminated Ascii string.
+ @param MaxSize The maximum number of Destination Ascii
+ char, including the Null terminator.
+
+ @retval 0 If String is NULL.
+ @retval (sizeof (CHAR8) * (MaxSize + 1))
+ If there is no Null terminator in the first MaxSize characters of
+ String.
+ @return The size of the Null-terminated Ascii string in bytes, including the
+ Null terminator.
+
+**/
+UINTN
+EFIAPI
+AsciiStrnSizeS (
+ IN CONST CHAR8 *String,
+ IN UINTN MaxSize
+ );
+
+/**
+ Copies the string pointed to by Source (including the terminating null char)
+ to the array pointed to by Destination.
+
+ This function is similar as strcpy_s defined in C11.
+
+ If an error is returned, then the Destination is unmodified.
+
+ @param Destination A pointer to a Null-terminated Ascii string.
+ @param DestMax The maximum number of Destination Ascii
+ char, including terminating null char.
+ @param Source A pointer to a Null-terminated Ascii string.
+
+ @retval RETURN_SUCCESS String is copied.
+ @retval RETURN_BUFFER_TOO_SMALL If DestMax is NOT greater than StrLen(Source).
+ @retval RETURN_INVALID_PARAMETER If Destination is NULL.
+ If Source is NULL.
+ If PcdMaximumAsciiStringLength is not zero,
+ and DestMax is greater than
+ PcdMaximumAsciiStringLength.
+ If DestMax is 0.
+ @retval RETURN_ACCESS_DENIED If Source and Destination overlap.
+**/
+RETURN_STATUS
+EFIAPI
+AsciiStrCpyS (
+ OUT CHAR8 *Destination,
+ IN UINTN DestMax,
+ IN CONST CHAR8 *Source
+ );
+
+/**
+ Copies not more than Length successive char from the string pointed to by
+ Source to the array pointed to by Destination. If no null char is copied from
+ Source, then Destination[Length] is always set to null.
+
+ This function is similar as strncpy_s defined in C11.
+
+ If an error is returned, then the Destination is unmodified.
+
+ @param Destination A pointer to a Null-terminated Ascii string.
+ @param DestMax The maximum number of Destination Ascii
+ char, including terminating null char.
+ @param Source A pointer to a Null-terminated Ascii string.
+ @param Length The maximum number of Ascii characters to copy.
+
+ @retval RETURN_SUCCESS String is copied.
+ @retval RETURN_BUFFER_TOO_SMALL If DestMax is NOT greater than
+ MIN(StrLen(Source), Length).
+ @retval RETURN_INVALID_PARAMETER If Destination is NULL.
+ If Source is NULL.
+ If PcdMaximumAsciiStringLength is not zero,
+ and DestMax is greater than
+ PcdMaximumAsciiStringLength.
+ If DestMax is 0.
+ @retval RETURN_ACCESS_DENIED If Source and Destination overlap.
+**/
+RETURN_STATUS
+EFIAPI
+AsciiStrnCpyS (
+ OUT CHAR8 *Destination,
+ IN UINTN DestMax,
+ IN CONST CHAR8 *Source,
+ IN UINTN Length
+ );
+
+/**
+ Appends a copy of the string pointed to by Source (including the terminating
+ null char) to the end of the string pointed to by Destination.
+
+ This function is similar as strcat_s defined in C11.
+
+ If an error is returned, then the Destination is unmodified.
+
+ @param Destination A pointer to a Null-terminated Ascii string.
+ @param DestMax The maximum number of Destination Ascii
+ char, including terminating null char.
+ @param Source A pointer to a Null-terminated Ascii string.
+
+ @retval RETURN_SUCCESS String is appended.
+ @retval RETURN_BAD_BUFFER_SIZE If DestMax is NOT greater than
+ StrLen(Destination).
+ @retval RETURN_BUFFER_TOO_SMALL If (DestMax - StrLen(Destination)) is NOT
+ greater than StrLen(Source).
+ @retval RETURN_INVALID_PARAMETER If Destination is NULL.
+ If Source is NULL.
+ If PcdMaximumAsciiStringLength is not zero,
+ and DestMax is greater than
+ PcdMaximumAsciiStringLength.
+ If DestMax is 0.
+ @retval RETURN_ACCESS_DENIED If Source and Destination overlap.
+**/
+RETURN_STATUS
+EFIAPI
+AsciiStrCatS (
+ IN OUT CHAR8 *Destination,
+ IN UINTN DestMax,
+ IN CONST CHAR8 *Source
+ );
+
+/**
+ Appends not more than Length successive char from the string pointed to by
+ Source to the end of the string pointed to by Destination. If no null char is
+ copied from Source, then Destination[StrLen(Destination) + Length] is always
+ set to null.
+
+ This function is similar as strncat_s defined in C11.
+
+ If an error is returned, then the Destination is unmodified.
+
+ @param Destination A pointer to a Null-terminated Ascii string.
+ @param DestMax The maximum number of Destination Ascii
+ char, including terminating null char.
+ @param Source A pointer to a Null-terminated Ascii string.
+ @param Length The maximum number of Ascii characters to copy.
+
+ @retval RETURN_SUCCESS String is appended.
+ @retval RETURN_BAD_BUFFER_SIZE If DestMax is NOT greater than
+ StrLen(Destination).
+ @retval RETURN_BUFFER_TOO_SMALL If (DestMax - StrLen(Destination)) is NOT
+ greater than MIN(StrLen(Source), Length).
+ @retval RETURN_INVALID_PARAMETER If Destination is NULL.
+ If Source is NULL.
+ If PcdMaximumAsciiStringLength is not zero,
+ and DestMax is greater than
+ PcdMaximumAsciiStringLength.
+ If DestMax is 0.
+ @retval RETURN_ACCESS_DENIED If Source and Destination overlap.
+**/
+RETURN_STATUS
+EFIAPI
+AsciiStrnCatS (
+ IN OUT CHAR8 *Destination,
+ IN UINTN DestMax,
+ IN CONST CHAR8 *Source,
+ IN UINTN Length
+ );
+
+/**
+ Convert a Null-terminated Ascii decimal string to a value of type UINTN.
+
+ This function outputs a value of type UINTN by interpreting the contents of
+ the Ascii string specified by String as a decimal number. The format of the
+ input Ascii string String is:
+
+ [spaces] [decimal digits].
+
+ The valid decimal digit character is in the range [0-9]. The function will
+ ignore the pad space, which includes spaces or tab characters, before
+ [decimal digits]. The running zero in the beginning of [decimal digits] will
+ be ignored. Then, the function stops at the first character that is a not a
+ valid decimal character or a Null-terminator, whichever one comes first.
+
+ If String has no valid decimal digits in the above format, then 0 is stored
+ at the location pointed to by Data.
+ If the number represented by String exceeds the range defined by UINTN, then
+ MAX_UINTN is stored at the location pointed to by Data.
+
+ If EndPointer is not NULL, a pointer to the character that stopped the scan
+ is stored at the location pointed to by EndPointer. If String has no valid
+ decimal digits right after the optional pad spaces, the value of String is
+ stored at the location pointed to by EndPointer.
+
+ @param String Pointer to a Null-terminated Ascii string.
+ @param EndPointer Pointer to character that stops scan.
+ @param Data Pointer to the converted value.
+
+ @retval RETURN_SUCCESS Value is translated from String.
+ @retval RETURN_INVALID_PARAMETER If String is NULL.
+ If Data is NULL.
+ If PcdMaximumAsciiStringLength is not zero,
+ and String contains more than
+ PcdMaximumAsciiStringLength Ascii
+ characters, not including the
+ Null-terminator.
+ @retval RETURN_UNSUPPORTED If the number represented by String exceeds
+ the range defined by UINTN.
+
+**/
+RETURN_STATUS
+EFIAPI
+AsciiStrDecimalToUintnS (
+ IN CONST CHAR8 *String,
+ OUT CHAR8 **EndPointer OPTIONAL,
+ OUT UINTN *Data
+ );
+
+/**
+ Convert a Null-terminated Ascii decimal string to a value of type UINT64.
+
+ This function outputs a value of type UINT64 by interpreting the contents of
+ the Ascii string specified by String as a decimal number. The format of the
+ input Ascii string String is:
+
+ [spaces] [decimal digits].
+
+ The valid decimal digit character is in the range [0-9]. The function will
+ ignore the pad space, which includes spaces or tab characters, before
+ [decimal digits]. The running zero in the beginning of [decimal digits] will
+ be ignored. Then, the function stops at the first character that is a not a
+ valid decimal character or a Null-terminator, whichever one comes first.
+
+ If String has no valid decimal digits in the above format, then 0 is stored
+ at the location pointed to by Data.
+ If the number represented by String exceeds the range defined by UINT64, then
+ MAX_UINT64 is stored at the location pointed to by Data.
+
+ If EndPointer is not NULL, a pointer to the character that stopped the scan
+ is stored at the location pointed to by EndPointer. If String has no valid
+ decimal digits right after the optional pad spaces, the value of String is
+ stored at the location pointed to by EndPointer.
+
+ @param String Pointer to a Null-terminated Ascii string.
+ @param EndPointer Pointer to character that stops scan.
+ @param Data Pointer to the converted value.
+
+ @retval RETURN_SUCCESS Value is translated from String.
+ @retval RETURN_INVALID_PARAMETER If String is NULL.
+ If Data is NULL.
+ If PcdMaximumAsciiStringLength is not zero,
+ and String contains more than
+ PcdMaximumAsciiStringLength Ascii
+ characters, not including the
+ Null-terminator.
+ @retval RETURN_UNSUPPORTED If the number represented by String exceeds
+ the range defined by UINT64.
+
+**/
+RETURN_STATUS
+EFIAPI
+AsciiStrDecimalToUint64S (
+ IN CONST CHAR8 *String,
+ OUT CHAR8 **EndPointer OPTIONAL,
+ OUT UINT64 *Data
+ );
+
+/**
+ Convert a Null-terminated Ascii hexadecimal string to a value of type UINTN.
+
+ This function outputs a value of type UINTN by interpreting the contents of
+ the Ascii string specified by String as a hexadecimal number. The format of
+ the input Ascii string String is:
+
+ [spaces][zeros][x][hexadecimal digits].
+
+ The valid hexadecimal digit character is in the range [0-9], [a-f] and [A-F].
+ The prefix "0x" is optional. Both "x" and "X" is allowed in "0x" prefix. If
+ "x" appears in the input string, it must be prefixed with at least one 0. The
+ function will ignore the pad space, which includes spaces or tab characters,
+ before [zeros], [x] or [hexadecimal digits]. The running zero before [x] or
+ [hexadecimal digits] will be ignored. Then, the decoding starts after [x] or
+ the first valid hexadecimal digit. Then, the function stops at the first
+ character that is a not a valid hexadecimal character or Null-terminator,
+ whichever on comes first.
+
+ If String has no valid hexadecimal digits in the above format, then 0 is
+ stored at the location pointed to by Data.
+ If the number represented by String exceeds the range defined by UINTN, then
+ MAX_UINTN is stored at the location pointed to by Data.
+
+ If EndPointer is not NULL, a pointer to the character that stopped the scan
+ is stored at the location pointed to by EndPointer. If String has no valid
+ hexadecimal digits right after the optional pad spaces, the value of String
+ is stored at the location pointed to by EndPointer.
+
+ @param String Pointer to a Null-terminated Ascii string.
+ @param EndPointer Pointer to character that stops scan.
+ @param Data Pointer to the converted value.
+
+ @retval RETURN_SUCCESS Value is translated from String.
+ @retval RETURN_INVALID_PARAMETER If String is NULL.
+ If Data is NULL.
+ If PcdMaximumAsciiStringLength is not zero,
+ and String contains more than
+ PcdMaximumAsciiStringLength Ascii
+ characters, not including the
+ Null-terminator.
+ @retval RETURN_UNSUPPORTED If the number represented by String exceeds
+ the range defined by UINTN.
+
+**/
+RETURN_STATUS
+EFIAPI
+AsciiStrHexToUintnS (
+ IN CONST CHAR8 *String,
+ OUT CHAR8 **EndPointer OPTIONAL,
+ OUT UINTN *Data
+ );
+
+/**
+ Convert a Null-terminated Ascii hexadecimal string to a value of type UINT64.
+
+ This function outputs a value of type UINT64 by interpreting the contents of
+ the Ascii string specified by String as a hexadecimal number. The format of
+ the input Ascii string String is:
+
+ [spaces][zeros][x][hexadecimal digits].
+
+ The valid hexadecimal digit character is in the range [0-9], [a-f] and [A-F].
+ The prefix "0x" is optional. Both "x" and "X" is allowed in "0x" prefix. If
+ "x" appears in the input string, it must be prefixed with at least one 0. The
+ function will ignore the pad space, which includes spaces or tab characters,
+ before [zeros], [x] or [hexadecimal digits]. The running zero before [x] or
+ [hexadecimal digits] will be ignored. Then, the decoding starts after [x] or
+ the first valid hexadecimal digit. Then, the function stops at the first
+ character that is a not a valid hexadecimal character or Null-terminator,
+ whichever on comes first.
+
+ If String has no valid hexadecimal digits in the above format, then 0 is
+ stored at the location pointed to by Data.
+ If the number represented by String exceeds the range defined by UINT64, then
+ MAX_UINT64 is stored at the location pointed to by Data.
+
+ If EndPointer is not NULL, a pointer to the character that stopped the scan
+ is stored at the location pointed to by EndPointer. If String has no valid
+ hexadecimal digits right after the optional pad spaces, the value of String
+ is stored at the location pointed to by EndPointer.
+
+ @param String Pointer to a Null-terminated Ascii string.
+ @param EndPointer Pointer to character that stops scan.
+ @param Data Pointer to the converted value.
+
+ @retval RETURN_SUCCESS Value is translated from String.
+ @retval RETURN_INVALID_PARAMETER If String is NULL.
+ If Data is NULL.
+ If PcdMaximumAsciiStringLength is not zero,
+ and String contains more than
+ PcdMaximumAsciiStringLength Ascii
+ characters, not including the
+ Null-terminator.
+ @retval RETURN_UNSUPPORTED If the number represented by String exceeds
+ the range defined by UINT64.
+
+**/
+RETURN_STATUS
+EFIAPI
+AsciiStrHexToUint64S (
+ IN CONST CHAR8 *String,
+ OUT CHAR8 **EndPointer OPTIONAL,
+ OUT UINT64 *Data
+ );
+
+/**
+ Returns the length of a Null-terminated Unicode string.
+
+ This function returns the number of Unicode characters in the Null-terminated
+ Unicode string specified by String.
+
+ If String is NULL, then ASSERT().
+ If String is not aligned on a 16-bit boundary, then ASSERT().
+ If PcdMaximumUnicodeStringLength is not zero, and String contains more than
+ PcdMaximumUnicodeStringLength Unicode characters not including the
+ Null-terminator, then ASSERT().
+
+ @param String Pointer to a Null-terminated Unicode string.
+
+ @return The length of String.
+
+**/
+UINTN
+EFIAPI
+StrLen (
+ IN CONST CHAR16 *String
+ );
+
+/**
+ Returns the size of a Null-terminated Unicode string in bytes, including the
+ Null terminator.
+
+ This function returns the size, in bytes, of the Null-terminated Unicode string
+ specified by String.
+
+ If String is NULL, then ASSERT().
+ If String is not aligned on a 16-bit boundary, then ASSERT().
+ If PcdMaximumUnicodeStringLength is not zero, and String contains more than
+ PcdMaximumUnicodeStringLength Unicode characters not including the
+ Null-terminator, then ASSERT().
+
+ @param String The pointer to a Null-terminated Unicode string.
+
+ @return The size of String.
+
+**/
+UINTN
+EFIAPI
+StrSize (
+ IN CONST CHAR16 *String
+ );
+
+/**
+ Compares two Null-terminated Unicode strings, and returns the difference
+ between the first mismatched Unicode characters.
+
+ This function compares the Null-terminated Unicode string FirstString to the
+ Null-terminated Unicode string SecondString. If FirstString is identical to
+ SecondString, then 0 is returned. Otherwise, the value returned is the first
+ mismatched Unicode character in SecondString subtracted from the first
+ mismatched Unicode character in FirstString.
+
+ If FirstString is NULL, then ASSERT().
+ If FirstString is not aligned on a 16-bit boundary, then ASSERT().
+ If SecondString is NULL, then ASSERT().
+ If SecondString is not aligned on a 16-bit boundary, then ASSERT().
+ If PcdMaximumUnicodeStringLength is not zero, and FirstString contains more
+ than PcdMaximumUnicodeStringLength Unicode characters not including the
+ Null-terminator, then ASSERT().
+ If PcdMaximumUnicodeStringLength is not zero, and SecondString contains more
+ than PcdMaximumUnicodeStringLength Unicode characters, not including the
+ Null-terminator, then ASSERT().
+
+ @param FirstString The pointer to a Null-terminated Unicode string.
+ @param SecondString The pointer to a Null-terminated Unicode string.
+
+ @retval 0 FirstString is identical to SecondString.
+ @return others FirstString is not identical to SecondString.
+
+**/
+INTN
+EFIAPI
+StrCmp (
+ IN CONST CHAR16 *FirstString,
+ IN CONST CHAR16 *SecondString
+ );
+
+/**
+ Compares up to a specified length the contents of two Null-terminated Unicode strings,
+ and returns the difference between the first mismatched Unicode characters.
+
+ This function compares the Null-terminated Unicode string FirstString to the
+ Null-terminated Unicode string SecondString. At most, Length Unicode
+ characters will be compared. If Length is 0, then 0 is returned. If
+ FirstString is identical to SecondString, then 0 is returned. Otherwise, the
+ value returned is the first mismatched Unicode character in SecondString
+ subtracted from the first mismatched Unicode character in FirstString.
+
+ If Length > 0 and FirstString is NULL, then ASSERT().
+ If Length > 0 and FirstString is not aligned on a 16-bit boundary, then ASSERT().
+ If Length > 0 and SecondString is NULL, then ASSERT().
+ If Length > 0 and SecondString is not aligned on a 16-bit boundary, then ASSERT().
+ If PcdMaximumUnicodeStringLength is not zero, and Length is greater than
+ PcdMaximumUnicodeStringLength, then ASSERT().
+ If PcdMaximumUnicodeStringLength is not zero, and FirstString contains more than
+ PcdMaximumUnicodeStringLength Unicode characters, not including the Null-terminator,
+ then ASSERT().
+ If PcdMaximumUnicodeStringLength is not zero, and SecondString contains more than
+ PcdMaximumUnicodeStringLength Unicode characters, not including the Null-terminator,
+ then ASSERT().
+
+ @param FirstString The pointer to a Null-terminated Unicode string.
+ @param SecondString The pointer to a Null-terminated Unicode string.
+ @param Length The maximum number of Unicode characters to compare.
+
+ @retval 0 FirstString is identical to SecondString.
+ @return others FirstString is not identical to SecondString.
+
+**/
+INTN
+EFIAPI
+StrnCmp (
+ IN CONST CHAR16 *FirstString,
+ IN CONST CHAR16 *SecondString,
+ IN UINTN Length
+ );
+
+/**
+ Returns the first occurrence of a Null-terminated Unicode sub-string
+ in a Null-terminated Unicode string.
+
+ This function scans the contents of the Null-terminated Unicode string
+ specified by String and returns the first occurrence of SearchString.
+ If SearchString is not found in String, then NULL is returned. If
+ the length of SearchString is zero, then String is returned.
+
+ If String is NULL, then ASSERT().
+ If String is not aligned on a 16-bit boundary, then ASSERT().
+ If SearchString is NULL, then ASSERT().
+ If SearchString is not aligned on a 16-bit boundary, then ASSERT().
+
+ If PcdMaximumUnicodeStringLength is not zero, and SearchString
+ or String contains more than PcdMaximumUnicodeStringLength Unicode
+ characters, not including the Null-terminator, then ASSERT().
+
+ @param String The pointer to a Null-terminated Unicode string.
+ @param SearchString The pointer to a Null-terminated Unicode string to search for.
+
+ @retval NULL If the SearchString does not appear in String.
+ @return others If there is a match.
+
+**/
+CHAR16 *
+EFIAPI
+StrStr (
+ IN CONST CHAR16 *String,
+ IN CONST CHAR16 *SearchString
+ );
+
+/**
+ Convert a Null-terminated Unicode decimal string to a value of
+ type UINTN.
+
+ This function returns a value of type UINTN by interpreting the contents
+ of the Unicode string specified by String as a decimal number. The format
+ of the input Unicode string String is:
+
+ [spaces] [decimal digits].
+
+ The valid decimal digit character is in the range [0-9]. The
+ function will ignore the pad space, which includes spaces or
+ tab characters, before [decimal digits]. The running zero in the
+ beginning of [decimal digits] will be ignored. Then, the function
+ stops at the first character that is a not a valid decimal character
+ or a Null-terminator, whichever one comes first.
+
+ If String is NULL, then ASSERT().
+ If String is not aligned in a 16-bit boundary, then ASSERT().
+ If String has only pad spaces, then 0 is returned.
+ If String has no pad spaces or valid decimal digits,
+ then 0 is returned.
+ If the number represented by String overflows according
+ to the range defined by UINTN, then MAX_UINTN is returned.
+
+ If PcdMaximumUnicodeStringLength is not zero, and String contains
+ more than PcdMaximumUnicodeStringLength Unicode characters not including
+ the Null-terminator, then ASSERT().
+
+ @param String The pointer to a Null-terminated Unicode string.
+
+ @retval Value translated from String.
+
+**/
+UINTN
+EFIAPI
+StrDecimalToUintn (
+ IN CONST CHAR16 *String
+ );
+
+/**
+ Convert a Null-terminated Unicode decimal string to a value of
+ type UINT64.
+
+ This function returns a value of type UINT64 by interpreting the contents
+ of the Unicode string specified by String as a decimal number. The format
+ of the input Unicode string String is:
+
+ [spaces] [decimal digits].
+
+ The valid decimal digit character is in the range [0-9]. The
+ function will ignore the pad space, which includes spaces or
+ tab characters, before [decimal digits]. The running zero in the
+ beginning of [decimal digits] will be ignored. Then, the function
+ stops at the first character that is a not a valid decimal character
+ or a Null-terminator, whichever one comes first.
+
+ If String is NULL, then ASSERT().
+ If String is not aligned in a 16-bit boundary, then ASSERT().
+ If String has only pad spaces, then 0 is returned.
+ If String has no pad spaces or valid decimal digits,
+ then 0 is returned.
+ If the number represented by String overflows according
+ to the range defined by UINT64, then MAX_UINT64 is returned.
+
+ If PcdMaximumUnicodeStringLength is not zero, and String contains
+ more than PcdMaximumUnicodeStringLength Unicode characters not including
+ the Null-terminator, then ASSERT().
+
+ @param String The pointer to a Null-terminated Unicode string.
+
+ @retval Value translated from String.
+
+**/
+UINT64
+EFIAPI
+StrDecimalToUint64 (
+ IN CONST CHAR16 *String
+ );
+
+/**
+ Convert a Null-terminated Unicode hexadecimal string to a value of type UINTN.
+
+ This function returns a value of type UINTN by interpreting the contents
+ of the Unicode string specified by String as a hexadecimal number.
+ The format of the input Unicode string String is:
+
+ [spaces][zeros][x][hexadecimal digits].
+
+ The valid hexadecimal digit character is in the range [0-9], [a-f] and [A-F].
+ The prefix "0x" is optional. Both "x" and "X" is allowed in "0x" prefix.
+ If "x" appears in the input string, it must be prefixed with at least one 0.
+ The function will ignore the pad space, which includes spaces or tab characters,
+ before [zeros], [x] or [hexadecimal digit]. The running zero before [x] or
+ [hexadecimal digit] will be ignored. Then, the decoding starts after [x] or the
+ first valid hexadecimal digit. Then, the function stops at the first character
+ that is a not a valid hexadecimal character or NULL, whichever one comes first.
+
+ If String is NULL, then ASSERT().
+ If String is not aligned in a 16-bit boundary, then ASSERT().
+ If String has only pad spaces, then zero is returned.
+ If String has no leading pad spaces, leading zeros or valid hexadecimal digits,
+ then zero is returned.
+ If the number represented by String overflows according to the range defined by
+ UINTN, then MAX_UINTN is returned.
+
+ If PcdMaximumUnicodeStringLength is not zero, and String contains more than
+ PcdMaximumUnicodeStringLength Unicode characters not including the Null-terminator,
+ then ASSERT().
+
+ @param String The pointer to a Null-terminated Unicode string.
+
+ @retval Value translated from String.
+
+**/
+UINTN
+EFIAPI
+StrHexToUintn (
+ IN CONST CHAR16 *String
+ );
+
+/**
+ Convert a Null-terminated Unicode hexadecimal string to a value of type UINT64.
+
+ This function returns a value of type UINT64 by interpreting the contents
+ of the Unicode string specified by String as a hexadecimal number.
+ The format of the input Unicode string String is
+
+ [spaces][zeros][x][hexadecimal digits].
+
+ The valid hexadecimal digit character is in the range [0-9], [a-f] and [A-F].
+ The prefix "0x" is optional. Both "x" and "X" is allowed in "0x" prefix.
+ If "x" appears in the input string, it must be prefixed with at least one 0.
+ The function will ignore the pad space, which includes spaces or tab characters,
+ before [zeros], [x] or [hexadecimal digit]. The running zero before [x] or
+ [hexadecimal digit] will be ignored. Then, the decoding starts after [x] or the
+ first valid hexadecimal digit. Then, the function stops at the first character that is
+ a not a valid hexadecimal character or NULL, whichever one comes first.
+
+ If String is NULL, then ASSERT().
+ If String is not aligned in a 16-bit boundary, then ASSERT().
+ If String has only pad spaces, then zero is returned.
+ If String has no leading pad spaces, leading zeros or valid hexadecimal digits,
+ then zero is returned.
+ If the number represented by String overflows according to the range defined by
+ UINT64, then MAX_UINT64 is returned.
+
+ If PcdMaximumUnicodeStringLength is not zero, and String contains more than
+ PcdMaximumUnicodeStringLength Unicode characters not including the Null-terminator,
+ then ASSERT().
+
+ @param String The pointer to a Null-terminated Unicode string.
+
+ @retval Value translated from String.
+
+**/
+UINT64
+EFIAPI
+StrHexToUint64 (
+ IN CONST CHAR16 *String
+ );
+
+/**
+ Convert a Null-terminated Unicode string to IPv6 address and prefix length.
+
+ This function outputs a value of type IPv6_ADDRESS and may output a value
+ of type UINT8 by interpreting the contents of the Unicode string specified
+ by String. The format of the input Unicode string String is as follows:
+
+ X:X:X:X:X:X:X:X[/P]
+
+ X contains one to four hexadecimal digit characters in the range [0-9], [a-f] and
+ [A-F]. X is converted to a value of type UINT16, whose low byte is stored in low
+ memory address and high byte is stored in high memory address. P contains decimal
+ digit characters in the range [0-9]. The running zero in the beginning of P will
+ be ignored. /P is optional.
+
+ When /P is not in the String, the function stops at the first character that is
+ not a valid hexadecimal digit character after eight X's are converted.
+
+ When /P is in the String, the function stops at the first character that is not
+ a valid decimal digit character after P is converted.
+
+ "::" can be used to compress one or more groups of X when X contains only 0.
+ The "::" can only appear once in the String.
+
+ If String is not aligned in a 16-bit boundary, then ASSERT().
+
+ If EndPointer is not NULL and Address is translated from String, a pointer
+ to the character that stopped the scan is stored at the location pointed to
+ by EndPointer.
+
+ @param String Pointer to a Null-terminated Unicode string.
+ @param EndPointer Pointer to character that stops scan.
+ @param Address Pointer to the converted IPv6 address.
+ @param PrefixLength Pointer to the converted IPv6 address prefix
+ length. MAX_UINT8 is returned when /P is
+ not in the String.
+
+ @retval RETURN_SUCCESS Address is translated from String.
+ @retval RETURN_INVALID_PARAMETER If String is NULL.
+ If Data is NULL.
+ @retval RETURN_UNSUPPORTED If X contains more than four hexadecimal
+ digit characters.
+ If String contains "::" and number of X
+ is not less than 8.
+ If P starts with character that is not a
+ valid decimal digit character.
+ If the decimal number converted from P
+ exceeds 128.
+
+**/
+RETURN_STATUS
+EFIAPI
+StrToIpv6Address (
+ IN CONST CHAR16 *String,
+ OUT CHAR16 **EndPointer OPTIONAL,
+ OUT IPv6_ADDRESS *Address,
+ OUT UINT8 *PrefixLength OPTIONAL
+ );
+
+/**
+ Convert a Null-terminated Unicode string to IPv4 address and prefix length.
+
+ This function outputs a value of type IPv4_ADDRESS and may output a value
+ of type UINT8 by interpreting the contents of the Unicode string specified
+ by String. The format of the input Unicode string String is as follows:
+
+ D.D.D.D[/P]
+
+ D and P are decimal digit characters in the range [0-9]. The running zero in
+ the beginning of D and P will be ignored. /P is optional.
+
+ When /P is not in the String, the function stops at the first character that is
+ not a valid decimal digit character after four D's are converted.
+
+ When /P is in the String, the function stops at the first character that is not
+ a valid decimal digit character after P is converted.
+
+ If String is not aligned in a 16-bit boundary, then ASSERT().
+
+ If EndPointer is not NULL and Address is translated from String, a pointer
+ to the character that stopped the scan is stored at the location pointed to
+ by EndPointer.
+
+ @param String Pointer to a Null-terminated Unicode string.
+ @param EndPointer Pointer to character that stops scan.
+ @param Address Pointer to the converted IPv4 address.
+ @param PrefixLength Pointer to the converted IPv4 address prefix
+ length. MAX_UINT8 is returned when /P is
+ not in the String.
+
+ @retval RETURN_SUCCESS Address is translated from String.
+ @retval RETURN_INVALID_PARAMETER If String is NULL.
+ If Data is NULL.
+ @retval RETURN_UNSUPPORTED If String is not in the correct format.
+ If any decimal number converted from D
+ exceeds 255.
+ If the decimal number converted from P
+ exceeds 32.
+
+**/
+RETURN_STATUS
+EFIAPI
+StrToIpv4Address (
+ IN CONST CHAR16 *String,
+ OUT CHAR16 **EndPointer OPTIONAL,
+ OUT IPv4_ADDRESS *Address,
+ OUT UINT8 *PrefixLength OPTIONAL
+ );
+
+#define GUID_STRING_LENGTH 36
+
+/**
+ Convert a Null-terminated Unicode GUID string to a value of type
+ EFI_GUID.
+
+ This function outputs a GUID value by interpreting the contents of
+ the Unicode string specified by String. The format of the input
+ Unicode string String consists of 36 characters, as follows:
+
+ aabbccdd-eeff-gghh-iijj-kkllmmnnoopp
+
+ The pairs aa - pp are two characters in the range [0-9], [a-f] and
+ [A-F], with each pair representing a single byte hexadecimal value.
+
+ The mapping between String and the EFI_GUID structure is as follows:
+ aa Data1[24:31]
+ bb Data1[16:23]
+ cc Data1[8:15]
+ dd Data1[0:7]
+ ee Data2[8:15]
+ ff Data2[0:7]
+ gg Data3[8:15]
+ hh Data3[0:7]
+ ii Data4[0:7]
+ jj Data4[8:15]
+ kk Data4[16:23]
+ ll Data4[24:31]
+ mm Data4[32:39]
+ nn Data4[40:47]
+ oo Data4[48:55]
+ pp Data4[56:63]
+
+ If String is not aligned in a 16-bit boundary, then ASSERT().
+
+ @param String Pointer to a Null-terminated Unicode string.
+ @param Guid Pointer to the converted GUID.
+
+ @retval RETURN_SUCCESS Guid is translated from String.
+ @retval RETURN_INVALID_PARAMETER If String is NULL.
+ If Data is NULL.
+ @retval RETURN_UNSUPPORTED If String is not as the above format.
+
+**/
+RETURN_STATUS
+EFIAPI
+StrToGuid (
+ IN CONST CHAR16 *String,
+ OUT GUID *Guid
+ );
+
+/**
+ Convert a Null-terminated Unicode hexadecimal string to a byte array.
+
+ This function outputs a byte array by interpreting the contents of
+ the Unicode string specified by String in hexadecimal format. The format of
+ the input Unicode string String is:
+
+ [XX]*
+
+ X is a hexadecimal digit character in the range [0-9], [a-f] and [A-F].
+ The function decodes every two hexadecimal digit characters as one byte. The
+ decoding stops after Length of characters and outputs Buffer containing
+ (Length / 2) bytes.
+
+ If String is not aligned in a 16-bit boundary, then ASSERT().
+
+ @param String Pointer to a Null-terminated Unicode string.
+ @param Length The number of Unicode characters to decode.
+ @param Buffer Pointer to the converted bytes array.
+ @param MaxBufferSize The maximum size of Buffer.
+
+ @retval RETURN_SUCCESS Buffer is translated from String.
+ @retval RETURN_INVALID_PARAMETER If String is NULL.
+ If Data is NULL.
+ If Length is not multiple of 2.
+ If PcdMaximumUnicodeStringLength is not zero,
+ and Length is greater than
+ PcdMaximumUnicodeStringLength.
+ @retval RETURN_UNSUPPORTED If Length of characters from String contain
+ a character that is not valid hexadecimal
+ digit characters, or a Null-terminator.
+ @retval RETURN_BUFFER_TOO_SMALL If MaxBufferSize is less than (Length / 2).
+**/
+RETURN_STATUS
+EFIAPI
+StrHexToBytes (
+ IN CONST CHAR16 *String,
+ IN UINTN Length,
+ OUT UINT8 *Buffer,
+ IN UINTN MaxBufferSize
+ );
+
+/**
+ Convert a Null-terminated Unicode string to a Null-terminated
+ ASCII string.
+
+ This function is similar to AsciiStrCpyS.
+
+ This function converts the content of the Unicode string Source
+ to the ASCII string Destination by copying the lower 8 bits of
+ each Unicode character. The function terminates the ASCII string
+ Destination by appending a Null-terminator character at the end.
+
+ The caller is responsible to make sure Destination points to a buffer with size
+ equal or greater than ((StrLen (Source) + 1) * sizeof (CHAR8)) in bytes.
+
+ If any Unicode characters in Source contain non-zero value in
+ the upper 8 bits, then ASSERT().
+
+ If Source is not aligned on a 16-bit boundary, then ASSERT().
+
+ If an error is returned, then the Destination is unmodified.
+
+ @param Source The pointer to a Null-terminated Unicode string.
+ @param Destination The pointer to a Null-terminated ASCII string.
+ @param DestMax The maximum number of Destination Ascii
+ char, including terminating null char.
+
+ @retval RETURN_SUCCESS String is converted.
+ @retval RETURN_BUFFER_TOO_SMALL If DestMax is NOT greater than StrLen(Source).
+ @retval RETURN_INVALID_PARAMETER If Destination is NULL.
+ If Source is NULL.
+ If PcdMaximumAsciiStringLength is not zero,
+ and DestMax is greater than
+ PcdMaximumAsciiStringLength.
+ If PcdMaximumUnicodeStringLength is not zero,
+ and DestMax is greater than
+ PcdMaximumUnicodeStringLength.
+ If DestMax is 0.
+ @retval RETURN_ACCESS_DENIED If Source and Destination overlap.
+
+**/
+RETURN_STATUS
+EFIAPI
+UnicodeStrToAsciiStrS (
+ IN CONST CHAR16 *Source,
+ OUT CHAR8 *Destination,
+ IN UINTN DestMax
+ );
+
+/**
+ Convert not more than Length successive characters from a Null-terminated
+ Unicode string to a Null-terminated Ascii string. If no null char is copied
+ from Source, then Destination[Length] is always set to null.
+
+ This function converts not more than Length successive characters from the
+ Unicode string Source to the Ascii string Destination by copying the lower 8
+ bits of each Unicode character. The function terminates the Ascii string
+ Destination by appending a Null-terminator character at the end.
+
+ The caller is responsible to make sure Destination points to a buffer with size
+ equal or greater than ((StrLen (Source) + 1) * sizeof (CHAR8)) in bytes.
+
+ If any Unicode characters in Source contain non-zero value in the upper 8
+ bits, then ASSERT().
+ If Source is not aligned on a 16-bit boundary, then ASSERT().
+
+ If an error is returned, then the Destination is unmodified.
+
+ @param Source The pointer to a Null-terminated Unicode string.
+ @param Length The maximum number of Unicode characters to
+ convert.
+ @param Destination The pointer to a Null-terminated Ascii string.
+ @param DestMax The maximum number of Destination Ascii
+ char, including terminating null char.
+ @param DestinationLength The number of Unicode characters converted.
+
+ @retval RETURN_SUCCESS String is converted.
+ @retval RETURN_INVALID_PARAMETER If Destination is NULL.
+ If Source is NULL.
+ If DestinationLength is NULL.
+ If PcdMaximumAsciiStringLength is not zero,
+ and Length or DestMax is greater than
+ PcdMaximumAsciiStringLength.
+ If PcdMaximumUnicodeStringLength is not
+ zero, and Length or DestMax is greater than
+ PcdMaximumUnicodeStringLength.
+ If DestMax is 0.
+ @retval RETURN_BUFFER_TOO_SMALL If DestMax is NOT greater than
+ MIN(StrLen(Source), Length).
+ @retval RETURN_ACCESS_DENIED If Source and Destination overlap.
+
+**/
+RETURN_STATUS
+EFIAPI
+UnicodeStrnToAsciiStrS (
+ IN CONST CHAR16 *Source,
+ IN UINTN Length,
+ OUT CHAR8 *Destination,
+ IN UINTN DestMax,
+ OUT UINTN *DestinationLength
+ );
+
+/**
+ Returns the length of a Null-terminated ASCII string.
+
+ This function returns the number of ASCII characters in the Null-terminated
+ ASCII string specified by String.
+
+ If Length > 0 and Destination is NULL, then ASSERT().
+ If Length > 0 and Source is NULL, then ASSERT().
+ If PcdMaximumAsciiStringLength is not zero and String contains more than
+ PcdMaximumAsciiStringLength ASCII characters not including the Null-terminator,
+ then ASSERT().
+
+ @param String The pointer to a Null-terminated ASCII string.
+
+ @return The length of String.
+
+**/
+UINTN
+EFIAPI
+AsciiStrLen (
+ IN CONST CHAR8 *String
+ );
+
+/**
+ Returns the size of a Null-terminated ASCII string in bytes, including the
+ Null terminator.
+
+ This function returns the size, in bytes, of the Null-terminated ASCII string
+ specified by String.
+
+ If String is NULL, then ASSERT().
+ If PcdMaximumAsciiStringLength is not zero and String contains more than
+ PcdMaximumAsciiStringLength ASCII characters not including the Null-terminator,
+ then ASSERT().
+
+ @param String The pointer to a Null-terminated ASCII string.
+
+ @return The size of String.
+
+**/
+UINTN
+EFIAPI
+AsciiStrSize (
+ IN CONST CHAR8 *String
+ );
+
+/**
+ Compares two Null-terminated ASCII strings, and returns the difference
+ between the first mismatched ASCII characters.
+
+ This function compares the Null-terminated ASCII string FirstString to the
+ Null-terminated ASCII string SecondString. If FirstString is identical to
+ SecondString, then 0 is returned. Otherwise, the value returned is the first
+ mismatched ASCII character in SecondString subtracted from the first
+ mismatched ASCII character in FirstString.
+
+ If FirstString is NULL, then ASSERT().
+ If SecondString is NULL, then ASSERT().
+ If PcdMaximumAsciiStringLength is not zero and FirstString contains more than
+ PcdMaximumAsciiStringLength ASCII characters not including the Null-terminator,
+ then ASSERT().
+ If PcdMaximumAsciiStringLength is not zero and SecondString contains more
+ than PcdMaximumAsciiStringLength ASCII characters not including the
+ Null-terminator, then ASSERT().
+
+ @param FirstString The pointer to a Null-terminated ASCII string.
+ @param SecondString The pointer to a Null-terminated ASCII string.
+
+ @retval ==0 FirstString is identical to SecondString.
+ @retval !=0 FirstString is not identical to SecondString.
+
+**/
+INTN
+EFIAPI
+AsciiStrCmp (
+ IN CONST CHAR8 *FirstString,
+ IN CONST CHAR8 *SecondString
+ );
+
+/**
+ Performs a case insensitive comparison of two Null-terminated ASCII strings,
+ and returns the difference between the first mismatched ASCII characters.
+
+ This function performs a case insensitive comparison of the Null-terminated
+ ASCII string FirstString to the Null-terminated ASCII string SecondString. If
+ FirstString is identical to SecondString, then 0 is returned. Otherwise, the
+ value returned is the first mismatched lower case ASCII character in
+ SecondString subtracted from the first mismatched lower case ASCII character
+ in FirstString.
+
+ If FirstString is NULL, then ASSERT().
+ If SecondString is NULL, then ASSERT().
+ If PcdMaximumAsciiStringLength is not zero and FirstString contains more than
+ PcdMaximumAsciiStringLength ASCII characters not including the Null-terminator,
+ then ASSERT().
+ If PcdMaximumAsciiStringLength is not zero and SecondString contains more
+ than PcdMaximumAsciiStringLength ASCII characters not including the
+ Null-terminator, then ASSERT().
+
+ @param FirstString The pointer to a Null-terminated ASCII string.
+ @param SecondString The pointer to a Null-terminated ASCII string.
+
+ @retval ==0 FirstString is identical to SecondString using case insensitive
+ comparisons.
+ @retval !=0 FirstString is not identical to SecondString using case
+ insensitive comparisons.
+
+**/
+INTN
+EFIAPI
+AsciiStriCmp (
+ IN CONST CHAR8 *FirstString,
+ IN CONST CHAR8 *SecondString
+ );
+
+/**
+ Compares two Null-terminated ASCII strings with maximum lengths, and returns
+ the difference between the first mismatched ASCII characters.
+
+ This function compares the Null-terminated ASCII string FirstString to the
+ Null-terminated ASCII string SecondString. At most, Length ASCII characters
+ will be compared. If Length is 0, then 0 is returned. If FirstString is
+ identical to SecondString, then 0 is returned. Otherwise, the value returned
+ is the first mismatched ASCII character in SecondString subtracted from the
+ first mismatched ASCII character in FirstString.
+
+ If Length > 0 and FirstString is NULL, then ASSERT().
+ If Length > 0 and SecondString is NULL, then ASSERT().
+ If PcdMaximumAsciiStringLength is not zero, and Length is greater than
+ PcdMaximumAsciiStringLength, then ASSERT().
+ If PcdMaximumAsciiStringLength is not zero, and FirstString contains more than
+ PcdMaximumAsciiStringLength ASCII characters, not including the Null-terminator,
+ then ASSERT().
+ If PcdMaximumAsciiStringLength is not zero, and SecondString contains more than
+ PcdMaximumAsciiStringLength ASCII characters, not including the Null-terminator,
+ then ASSERT().
+
+ @param FirstString The pointer to a Null-terminated ASCII string.
+ @param SecondString The pointer to a Null-terminated ASCII string.
+ @param Length The maximum number of ASCII characters for compare.
+
+ @retval ==0 FirstString is identical to SecondString.
+ @retval !=0 FirstString is not identical to SecondString.
+
+**/
+INTN
+EFIAPI
+AsciiStrnCmp (
+ IN CONST CHAR8 *FirstString,
+ IN CONST CHAR8 *SecondString,
+ IN UINTN Length
+ );
+
+/**
+ Returns the first occurrence of a Null-terminated ASCII sub-string
+ in a Null-terminated ASCII string.
+
+ This function scans the contents of the ASCII string specified by String
+ and returns the first occurrence of SearchString. If SearchString is not
+ found in String, then NULL is returned. If the length of SearchString is zero,
+ then String is returned.
+
+ If String is NULL, then ASSERT().
+ If SearchString is NULL, then ASSERT().
+
+ If PcdMaximumAsciiStringLength is not zero, and SearchString or
+ String contains more than PcdMaximumAsciiStringLength Unicode characters
+ not including the Null-terminator, then ASSERT().
+
+ @param String The pointer to a Null-terminated ASCII string.
+ @param SearchString The pointer to a Null-terminated ASCII string to search for.
+
+ @retval NULL If the SearchString does not appear in String.
+ @retval others If there is a match return the first occurrence of SearchingString.
+ If the length of SearchString is zero,return String.
+
+**/
+CHAR8 *
+EFIAPI
+AsciiStrStr (
+ IN CONST CHAR8 *String,
+ IN CONST CHAR8 *SearchString
+ );
+
+/**
+ Convert a Null-terminated ASCII decimal string to a value of type
+ UINTN.
+
+ This function returns a value of type UINTN by interpreting the contents
+ of the ASCII string String as a decimal number. The format of the input
+ ASCII string String is:
+
+ [spaces] [decimal digits].
+
+ The valid decimal digit character is in the range [0-9]. The function will
+ ignore the pad space, which includes spaces or tab characters, before the digits.
+ The running zero in the beginning of [decimal digits] will be ignored. Then, the
+ function stops at the first character that is a not a valid decimal character or
+ Null-terminator, whichever on comes first.
+
+ If String has only pad spaces, then 0 is returned.
+ If String has no pad spaces or valid decimal digits, then 0 is returned.
+ If the number represented by String overflows according to the range defined by
+ UINTN, then MAX_UINTN is returned.
+ If String is NULL, then ASSERT().
+ If PcdMaximumAsciiStringLength is not zero, and String contains more than
+ PcdMaximumAsciiStringLength ASCII characters not including the Null-terminator,
+ then ASSERT().
+
+ @param String The pointer to a Null-terminated ASCII string.
+
+ @retval The value translated from String.
+
+**/
+UINTN
+EFIAPI
+AsciiStrDecimalToUintn (
+ IN CONST CHAR8 *String
+ );
+
+/**
+ Convert a Null-terminated ASCII decimal string to a value of type
+ UINT64.
+
+ This function returns a value of type UINT64 by interpreting the contents
+ of the ASCII string String as a decimal number. The format of the input
+ ASCII string String is:
+
+ [spaces] [decimal digits].
+
+ The valid decimal digit character is in the range [0-9]. The function will
+ ignore the pad space, which includes spaces or tab characters, before the digits.
+ The running zero in the beginning of [decimal digits] will be ignored. Then, the
+ function stops at the first character that is a not a valid decimal character or
+ Null-terminator, whichever on comes first.
+
+ If String has only pad spaces, then 0 is returned.
+ If String has no pad spaces or valid decimal digits, then 0 is returned.
+ If the number represented by String overflows according to the range defined by
+ UINT64, then MAX_UINT64 is returned.
+ If String is NULL, then ASSERT().
+ If PcdMaximumAsciiStringLength is not zero, and String contains more than
+ PcdMaximumAsciiStringLength ASCII characters not including the Null-terminator,
+ then ASSERT().
+
+ @param String The pointer to a Null-terminated ASCII string.
+
+ @retval Value translated from String.
+
+**/
+UINT64
+EFIAPI
+AsciiStrDecimalToUint64 (
+ IN CONST CHAR8 *String
+ );
+
+/**
+ Convert a Null-terminated ASCII hexadecimal string to a value of type UINTN.
+
+ This function returns a value of type UINTN by interpreting the contents of
+ the ASCII string String as a hexadecimal number. The format of the input ASCII
+ string String is:
+
+ [spaces][zeros][x][hexadecimal digits].
+
+ The valid hexadecimal digit character is in the range [0-9], [a-f] and [A-F].
+ The prefix "0x" is optional. Both "x" and "X" is allowed in "0x" prefix. If "x"
+ appears in the input string, it must be prefixed with at least one 0. The function
+ will ignore the pad space, which includes spaces or tab characters, before [zeros],
+ [x] or [hexadecimal digits]. The running zero before [x] or [hexadecimal digits]
+ will be ignored. Then, the decoding starts after [x] or the first valid hexadecimal
+ digit. Then, the function stops at the first character that is a not a valid
+ hexadecimal character or Null-terminator, whichever on comes first.
+
+ If String has only pad spaces, then 0 is returned.
+ If String has no leading pad spaces, leading zeros or valid hexadecimal digits, then
+ 0 is returned.
+
+ If the number represented by String overflows according to the range defined by UINTN,
+ then MAX_UINTN is returned.
+ If String is NULL, then ASSERT().
+ If PcdMaximumAsciiStringLength is not zero,
+ and String contains more than PcdMaximumAsciiStringLength ASCII characters not including
+ the Null-terminator, then ASSERT().
+
+ @param String The pointer to a Null-terminated ASCII string.
+
+ @retval Value translated from String.
+
+**/
+UINTN
+EFIAPI
+AsciiStrHexToUintn (
+ IN CONST CHAR8 *String
+ );
+
+/**
+ Convert a Null-terminated ASCII hexadecimal string to a value of type UINT64.
+
+ This function returns a value of type UINT64 by interpreting the contents of
+ the ASCII string String as a hexadecimal number. The format of the input ASCII
+ string String is:
+
+ [spaces][zeros][x][hexadecimal digits].
+
+ The valid hexadecimal digit character is in the range [0-9], [a-f] and [A-F].
+ The prefix "0x" is optional. Both "x" and "X" is allowed in "0x" prefix. If "x"
+ appears in the input string, it must be prefixed with at least one 0. The function
+ will ignore the pad space, which includes spaces or tab characters, before [zeros],
+ [x] or [hexadecimal digits]. The running zero before [x] or [hexadecimal digits]
+ will be ignored. Then, the decoding starts after [x] or the first valid hexadecimal
+ digit. Then, the function stops at the first character that is a not a valid
+ hexadecimal character or Null-terminator, whichever on comes first.
+
+ If String has only pad spaces, then 0 is returned.
+ If String has no leading pad spaces, leading zeros or valid hexadecimal digits, then
+ 0 is returned.
+
+ If the number represented by String overflows according to the range defined by UINT64,
+ then MAX_UINT64 is returned.
+ If String is NULL, then ASSERT().
+ If PcdMaximumAsciiStringLength is not zero,
+ and String contains more than PcdMaximumAsciiStringLength ASCII characters not including
+ the Null-terminator, then ASSERT().
+
+ @param String The pointer to a Null-terminated ASCII string.
+
+ @retval Value translated from String.
+
+**/
+UINT64
+EFIAPI
+AsciiStrHexToUint64 (
+ IN CONST CHAR8 *String
+ );
+
+/**
+ Convert a Null-terminated ASCII string to IPv6 address and prefix length.
+
+ This function outputs a value of type IPv6_ADDRESS and may output a value
+ of type UINT8 by interpreting the contents of the ASCII string specified
+ by String. The format of the input ASCII string String is as follows:
+
+ X:X:X:X:X:X:X:X[/P]
+
+ X contains one to four hexadecimal digit characters in the range [0-9], [a-f] and
+ [A-F]. X is converted to a value of type UINT16, whose low byte is stored in low
+ memory address and high byte is stored in high memory address. P contains decimal
+ digit characters in the range [0-9]. The running zero in the beginning of P will
+ be ignored. /P is optional.
+
+ When /P is not in the String, the function stops at the first character that is
+ not a valid hexadecimal digit character after eight X's are converted.
+
+ When /P is in the String, the function stops at the first character that is not
+ a valid decimal digit character after P is converted.
+
+ "::" can be used to compress one or more groups of X when X contains only 0.
+ The "::" can only appear once in the String.
+
+ If EndPointer is not NULL and Address is translated from String, a pointer
+ to the character that stopped the scan is stored at the location pointed to
+ by EndPointer.
+
+ @param String Pointer to a Null-terminated ASCII string.
+ @param EndPointer Pointer to character that stops scan.
+ @param Address Pointer to the converted IPv6 address.
+ @param PrefixLength Pointer to the converted IPv6 address prefix
+ length. MAX_UINT8 is returned when /P is
+ not in the String.
+
+ @retval RETURN_SUCCESS Address is translated from String.
+ @retval RETURN_INVALID_PARAMETER If String is NULL.
+ If Data is NULL.
+ @retval RETURN_UNSUPPORTED If X contains more than four hexadecimal
+ digit characters.
+ If String contains "::" and number of X
+ is not less than 8.
+ If P starts with character that is not a
+ valid decimal digit character.
+ If the decimal number converted from P
+ exceeds 128.
+
+**/
+RETURN_STATUS
+EFIAPI
+AsciiStrToIpv6Address (
+ IN CONST CHAR8 *String,
+ OUT CHAR8 **EndPointer OPTIONAL,
+ OUT IPv6_ADDRESS *Address,
+ OUT UINT8 *PrefixLength OPTIONAL
+ );
+
+/**
+ Convert a Null-terminated ASCII string to IPv4 address and prefix length.
+
+ This function outputs a value of type IPv4_ADDRESS and may output a value
+ of type UINT8 by interpreting the contents of the ASCII string specified
+ by String. The format of the input ASCII string String is as follows:
+
+ D.D.D.D[/P]
+
+ D and P are decimal digit characters in the range [0-9]. The running zero in
+ the beginning of D and P will be ignored. /P is optional.
+
+ When /P is not in the String, the function stops at the first character that is
+ not a valid decimal digit character after four D's are converted.
+
+ When /P is in the String, the function stops at the first character that is not
+ a valid decimal digit character after P is converted.
+
+ If EndPointer is not NULL and Address is translated from String, a pointer
+ to the character that stopped the scan is stored at the location pointed to
+ by EndPointer.
+
+ @param String Pointer to a Null-terminated ASCII string.
+ @param EndPointer Pointer to character that stops scan.
+ @param Address Pointer to the converted IPv4 address.
+ @param PrefixLength Pointer to the converted IPv4 address prefix
+ length. MAX_UINT8 is returned when /P is
+ not in the String.
+
+ @retval RETURN_SUCCESS Address is translated from String.
+ @retval RETURN_INVALID_PARAMETER If String is NULL.
+ If Data is NULL.
+ @retval RETURN_UNSUPPORTED If String is not in the correct format.
+ If any decimal number converted from D
+ exceeds 255.
+ If the decimal number converted from P
+ exceeds 32.
+
+**/
+RETURN_STATUS
+EFIAPI
+AsciiStrToIpv4Address (
+ IN CONST CHAR8 *String,
+ OUT CHAR8 **EndPointer OPTIONAL,
+ OUT IPv4_ADDRESS *Address,
+ OUT UINT8 *PrefixLength OPTIONAL
+ );
+
+/**
+ Convert a Null-terminated ASCII GUID string to a value of type
+ EFI_GUID.
+
+ This function outputs a GUID value by interpreting the contents of
+ the ASCII string specified by String. The format of the input
+ ASCII string String consists of 36 characters, as follows:
+
+ aabbccdd-eeff-gghh-iijj-kkllmmnnoopp
+
+ The pairs aa - pp are two characters in the range [0-9], [a-f] and
+ [A-F], with each pair representing a single byte hexadecimal value.
+
+ The mapping between String and the EFI_GUID structure is as follows:
+ aa Data1[24:31]
+ bb Data1[16:23]
+ cc Data1[8:15]
+ dd Data1[0:7]
+ ee Data2[8:15]
+ ff Data2[0:7]
+ gg Data3[8:15]
+ hh Data3[0:7]
+ ii Data4[0:7]
+ jj Data4[8:15]
+ kk Data4[16:23]
+ ll Data4[24:31]
+ mm Data4[32:39]
+ nn Data4[40:47]
+ oo Data4[48:55]
+ pp Data4[56:63]
+
+ @param String Pointer to a Null-terminated ASCII string.
+ @param Guid Pointer to the converted GUID.
+
+ @retval RETURN_SUCCESS Guid is translated from String.
+ @retval RETURN_INVALID_PARAMETER If String is NULL.
+ If Data is NULL.
+ @retval RETURN_UNSUPPORTED If String is not as the above format.
+
+**/
+RETURN_STATUS
+EFIAPI
+AsciiStrToGuid (
+ IN CONST CHAR8 *String,
+ OUT GUID *Guid
+ );
+
+/**
+ Convert a Null-terminated ASCII hexadecimal string to a byte array.
+
+ This function outputs a byte array by interpreting the contents of
+ the ASCII string specified by String in hexadecimal format. The format of
+ the input ASCII string String is:
+
+ [XX]*
+
+ X is a hexadecimal digit character in the range [0-9], [a-f] and [A-F].
+ The function decodes every two hexadecimal digit characters as one byte. The
+ decoding stops after Length of characters and outputs Buffer containing
+ (Length / 2) bytes.
+
+ @param String Pointer to a Null-terminated ASCII string.
+ @param Length The number of ASCII characters to decode.
+ @param Buffer Pointer to the converted bytes array.
+ @param MaxBufferSize The maximum size of Buffer.
+
+ @retval RETURN_SUCCESS Buffer is translated from String.
+ @retval RETURN_INVALID_PARAMETER If String is NULL.
+ If Data is NULL.
+ If Length is not multiple of 2.
+ If PcdMaximumAsciiStringLength is not zero,
+ and Length is greater than
+ PcdMaximumAsciiStringLength.
+ @retval RETURN_UNSUPPORTED If Length of characters from String contain
+ a character that is not valid hexadecimal
+ digit characters, or a Null-terminator.
+ @retval RETURN_BUFFER_TOO_SMALL If MaxBufferSize is less than (Length / 2).
+**/
+RETURN_STATUS
+EFIAPI
+AsciiStrHexToBytes (
+ IN CONST CHAR8 *String,
+ IN UINTN Length,
+ OUT UINT8 *Buffer,
+ IN UINTN MaxBufferSize
+ );
+
+/**
+ Convert one Null-terminated ASCII string to a Null-terminated
+ Unicode string.
+
+ This function is similar to StrCpyS.
+
+ This function converts the contents of the ASCII string Source to the Unicode
+ string Destination. The function terminates the Unicode string Destination by
+ appending a Null-terminator character at the end.
+
+ The caller is responsible to make sure Destination points to a buffer with size
+ equal or greater than ((AsciiStrLen (Source) + 1) * sizeof (CHAR16)) in bytes.
+
+ If Destination is not aligned on a 16-bit boundary, then ASSERT().
+
+ If an error is returned, then the Destination is unmodified.
+
+ @param Source The pointer to a Null-terminated ASCII string.
+ @param Destination The pointer to a Null-terminated Unicode string.
+ @param DestMax The maximum number of Destination Unicode
+ char, including terminating null char.
+
+ @retval RETURN_SUCCESS String is converted.
+ @retval RETURN_BUFFER_TOO_SMALL If DestMax is NOT greater than StrLen(Source).
+ @retval RETURN_INVALID_PARAMETER If Destination is NULL.
+ If Source is NULL.
+ If PcdMaximumUnicodeStringLength is not zero,
+ and DestMax is greater than
+ PcdMaximumUnicodeStringLength.
+ If PcdMaximumAsciiStringLength is not zero,
+ and DestMax is greater than
+ PcdMaximumAsciiStringLength.
+ If DestMax is 0.
+ @retval RETURN_ACCESS_DENIED If Source and Destination overlap.
+
+**/
+RETURN_STATUS
+EFIAPI
+AsciiStrToUnicodeStrS (
+ IN CONST CHAR8 *Source,
+ OUT CHAR16 *Destination,
+ IN UINTN DestMax
+ );
+
+/**
+ Convert not more than Length successive characters from a Null-terminated
+ Ascii string to a Null-terminated Unicode string. If no null char is copied
+ from Source, then Destination[Length] is always set to null.
+
+ This function converts not more than Length successive characters from the
+ Ascii string Source to the Unicode string Destination. The function
+ terminates the Unicode string Destination by appending a Null-terminator
+ character at the end.
+
+ The caller is responsible to make sure Destination points to a buffer with
+ size not smaller than
+ ((MIN(AsciiStrLen(Source), Length) + 1) * sizeof (CHAR8)) in bytes.
+
+ If Destination is not aligned on a 16-bit boundary, then ASSERT().
+
+ If an error is returned, then Destination and DestinationLength are
+ unmodified.
+
+ @param Source The pointer to a Null-terminated Ascii string.
+ @param Length The maximum number of Ascii characters to convert.
+ @param Destination The pointer to a Null-terminated Unicode string.
+ @param DestMax The maximum number of Destination Unicode char,
+ including terminating null char.
+ @param DestinationLength The number of Ascii characters converted.
+
+ @retval RETURN_SUCCESS String is converted.
+ @retval RETURN_INVALID_PARAMETER If Destination is NULL.
+ If Source is NULL.
+ If DestinationLength is NULL.
+ If PcdMaximumUnicodeStringLength is not
+ zero, and Length or DestMax is greater than
+ PcdMaximumUnicodeStringLength.
+ If PcdMaximumAsciiStringLength is not zero,
+ and Length or DestMax is greater than
+ PcdMaximumAsciiStringLength.
+ If DestMax is 0.
+ @retval RETURN_BUFFER_TOO_SMALL If DestMax is NOT greater than
+ MIN(AsciiStrLen(Source), Length).
+ @retval RETURN_ACCESS_DENIED If Source and Destination overlap.
+
+**/
+RETURN_STATUS
+EFIAPI
+AsciiStrnToUnicodeStrS (
+ IN CONST CHAR8 *Source,
+ IN UINTN Length,
+ OUT CHAR16 *Destination,
+ IN UINTN DestMax,
+ OUT UINTN *DestinationLength
+ );
+
+/**
+ Convert a Unicode character to upper case only if
+ it maps to a valid small-case ASCII character.
+
+ This internal function only deal with Unicode character
+ which maps to a valid small-case ASCII character, i.e.
+ L'a' to L'z'. For other Unicode character, the input character
+ is returned directly.
+
+ @param Char The character to convert.
+
+ @retval LowerCharacter If the Char is with range L'a' to L'z'.
+ @retval Unchanged Otherwise.
+
+**/
+CHAR16
+EFIAPI
+CharToUpper (
+ IN CHAR16 Char
+ );
+
+/**
+ Converts a lowercase Ascii character to upper one.
+
+ If Chr is lowercase Ascii character, then converts it to upper one.
+
+ If Value >= 0xA0, then ASSERT().
+ If (Value & 0x0F) >= 0x0A, then ASSERT().
+
+ @param Chr one Ascii character
+
+ @return The uppercase value of Ascii character
+
+**/
+CHAR8
+EFIAPI
+AsciiCharToUpper (
+ IN CHAR8 Chr
+ );
+
+/**
+ Convert binary data to a Base64 encoded ascii string based on RFC4648.
+
+ Produce a Null-terminated Ascii string in the output buffer specified by Destination and DestinationSize.
+ The Ascii string is produced by converting the data string specified by Source and SourceLength.
+
+ @param Source Input UINT8 data
+ @param SourceLength Number of UINT8 bytes of data
+ @param Destination Pointer to output string buffer
+ @param DestinationSize Size of ascii buffer. Set to 0 to get the size needed.
+ Caller is responsible for passing in buffer of DestinationSize
+
+ @retval RETURN_SUCCESS When ascii buffer is filled in.
+ @retval RETURN_INVALID_PARAMETER If Source is NULL or DestinationSize is NULL.
+ @retval RETURN_INVALID_PARAMETER If SourceLength or DestinationSize is bigger than (MAX_ADDRESS - (UINTN)Destination).
+ @retval RETURN_BUFFER_TOO_SMALL If SourceLength is 0 and DestinationSize is <1.
+ @retval RETURN_BUFFER_TOO_SMALL If Destination is NULL or DestinationSize is smaller than required buffersize.
+
+**/
+RETURN_STATUS
+EFIAPI
+Base64Encode (
+ IN CONST UINT8 *Source,
+ IN UINTN SourceLength,
+ OUT CHAR8 *Destination OPTIONAL,
+ IN OUT UINTN *DestinationSize
+ );
+
+/**
+ Decode Base64 ASCII encoded data to 8-bit binary representation, based on
+ RFC4648.
+
+ Decoding occurs according to "Table 1: The Base 64 Alphabet" in RFC4648.
+
+ Whitespace is ignored at all positions:
+ - 0x09 ('\t') horizontal tab
+ - 0x0A ('\n') new line
+ - 0x0B ('\v') vertical tab
+ - 0x0C ('\f') form feed
+ - 0x0D ('\r') carriage return
+ - 0x20 (' ') space
+
+ The minimum amount of required padding (with ASCII 0x3D, '=') is tolerated
+ and enforced at the end of the Base64 ASCII encoded data, and only there.
+
+ Other characters outside of the encoding alphabet cause the function to
+ reject the Base64 ASCII encoded data.
+
+ @param[in] Source Array of CHAR8 elements containing the Base64
+ ASCII encoding. May be NULL if SourceSize is
+ zero.
+
+ @param[in] SourceSize Number of CHAR8 elements in Source.
+
+ @param[out] Destination Array of UINT8 elements receiving the decoded
+ 8-bit binary representation. Allocated by the
+ caller. May be NULL if DestinationSize is
+ zero on input. If NULL, decoding is
+ performed, but the 8-bit binary
+ representation is not stored. If non-NULL and
+ the function returns an error, the contents
+ of Destination are indeterminate.
+
+ @param[in,out] DestinationSize On input, the number of UINT8 elements that
+ the caller allocated for Destination. On
+ output, if the function returns
+ RETURN_SUCCESS or RETURN_BUFFER_TOO_SMALL,
+ the number of UINT8 elements that are
+ required for decoding the Base64 ASCII
+ representation. If the function returns a
+ value different from both RETURN_SUCCESS and
+ RETURN_BUFFER_TOO_SMALL, then DestinationSize
+ is indeterminate on output.
+
+ @retval RETURN_SUCCESS SourceSize CHAR8 elements at Source have
+ been decoded to on-output DestinationSize
+ UINT8 elements at Destination. Note that
+ RETURN_SUCCESS covers the case when
+ DestinationSize is zero on input, and
+ Source decodes to zero bytes (due to
+ containing at most ignored whitespace).
+
+ @retval RETURN_BUFFER_TOO_SMALL The input value of DestinationSize is not
+ large enough for decoding SourceSize CHAR8
+ elements at Source. The required number of
+ UINT8 elements has been stored to
+ DestinationSize.
+
+ @retval RETURN_INVALID_PARAMETER DestinationSize is NULL.
+
+ @retval RETURN_INVALID_PARAMETER Source is NULL, but SourceSize is not zero.
+
+ @retval RETURN_INVALID_PARAMETER Destination is NULL, but DestinationSize is
+ not zero on input.
+
+ @retval RETURN_INVALID_PARAMETER Source is non-NULL, and (Source +
+ SourceSize) would wrap around MAX_ADDRESS.
+
+ @retval RETURN_INVALID_PARAMETER Destination is non-NULL, and (Destination +
+ DestinationSize) would wrap around
+ MAX_ADDRESS, as specified on input.
+
+ @retval RETURN_INVALID_PARAMETER None of Source and Destination are NULL,
+ and CHAR8[SourceSize] at Source overlaps
+ UINT8[DestinationSize] at Destination, as
+ specified on input.
+
+ @retval RETURN_INVALID_PARAMETER Invalid CHAR8 element encountered in
+ Source.
+**/
+RETURN_STATUS
+EFIAPI
+Base64Decode (
+ IN CONST CHAR8 *Source OPTIONAL,
+ IN UINTN SourceSize,
+ OUT UINT8 *Destination OPTIONAL,
+ IN OUT UINTN *DestinationSize
+ );
+
+/**
+ Converts an 8-bit value to an 8-bit BCD value.
+
+ Converts the 8-bit value specified by Value to BCD. The BCD value is
+ returned.
+
+ If Value >= 100, then ASSERT().
+
+ @param Value The 8-bit value to convert to BCD. Range 0..99.
+
+ @return The BCD value.
+
+**/
+UINT8
+EFIAPI
+DecimalToBcd8 (
+ IN UINT8 Value
+ );
+
+/**
+ Converts an 8-bit BCD value to an 8-bit value.
+
+ Converts the 8-bit BCD value specified by Value to an 8-bit value. The 8-bit
+ value is returned.
+
+ If Value >= 0xA0, then ASSERT().
+ If (Value & 0x0F) >= 0x0A, then ASSERT().
+
+ @param Value The 8-bit BCD value to convert to an 8-bit value.
+
+ @return The 8-bit value is returned.
+
+**/
+UINT8
+EFIAPI
+BcdToDecimal8 (
+ IN UINT8 Value
+ );
+
+//
+// File Path Manipulation Functions
+//
+
+/**
+ Removes the last directory or file entry in a path.
+
+ @param[in, out] Path The pointer to the path to modify.
+
+ @retval FALSE Nothing was found to remove.
+ @retval TRUE A directory or file was removed.
+**/
+BOOLEAN
+EFIAPI
+PathRemoveLastItem (
+ IN OUT CHAR16 *Path
+ );
+
+/**
+ Function to clean up paths.
+ - Single periods in the path are removed.
+ - Double periods in the path are removed along with a single parent directory.
+ - Forward slashes L'/' are converted to backward slashes L'\'.
+
+ This will be done inline and the existing buffer may be larger than required
+ upon completion.
+
+ @param[in] Path The pointer to the string containing the path.
+
+ @return Returns Path, otherwise returns NULL to indicate that an error has occurred.
+**/
+CHAR16 *
+EFIAPI
+PathCleanUpDirectories (
+ IN CHAR16 *Path
+ );
+
+//
+// Linked List Functions and Macros
+//
+
+/**
+ Initializes the head node of a doubly linked list that is declared as a
+ global variable in a module.
+
+ Initializes the forward and backward links of a new linked list. After
+ initializing a linked list with this macro, the other linked list functions
+ may be used to add and remove nodes from the linked list. This macro results
+ in smaller executables by initializing the linked list in the data section,
+ instead if calling the InitializeListHead() function to perform the
+ equivalent operation.
+
+ @param ListHead The head note of a list to initialize.
+
+**/
+#define INITIALIZE_LIST_HEAD_VARIABLE(ListHead) {&(ListHead), &(ListHead)}
+
+/**
+ Iterates over each node in a doubly linked list using each node's forward link.
+
+ @param Entry A pointer to a list node used as a loop cursor during iteration
+ @param ListHead The head node of the doubly linked list
+
+**/
+#define BASE_LIST_FOR_EACH(Entry, ListHead) \
+ for(Entry = (ListHead)->ForwardLink; Entry != (ListHead); Entry = Entry->ForwardLink)
+
+/**
+ Iterates over each node in a doubly linked list using each node's forward link
+ with safety against node removal.
+
+ This macro uses NextEntry to temporarily store the next list node so the node
+ pointed to by Entry may be deleted in the current loop iteration step and
+ iteration can continue from the node pointed to by NextEntry.
+
+ @param Entry A pointer to a list node used as a loop cursor during iteration
+ @param NextEntry A pointer to a list node used to temporarily store the next node
+ @param ListHead The head node of the doubly linked list
+
+**/
+#define BASE_LIST_FOR_EACH_SAFE(Entry, NextEntry, ListHead) \
+ for(Entry = (ListHead)->ForwardLink, NextEntry = Entry->ForwardLink;\
+ Entry != (ListHead); Entry = NextEntry, NextEntry = Entry->ForwardLink)
+
+/**
+ Checks whether FirstEntry and SecondEntry are part of the same doubly-linked
+ list.
+
+ If FirstEntry is NULL, then ASSERT().
+ If FirstEntry->ForwardLink is NULL, then ASSERT().
+ If FirstEntry->BackLink is NULL, then ASSERT().
+ If SecondEntry is NULL, then ASSERT();
+ If PcdMaximumLinkedListLength is not zero, and List contains more than
+ PcdMaximumLinkedListLength nodes, then ASSERT().
+
+ @param FirstEntry A pointer to a node in a linked list.
+ @param SecondEntry A pointer to the node to locate.
+
+ @retval TRUE SecondEntry is in the same doubly-linked list as FirstEntry.
+ @retval FALSE SecondEntry isn't in the same doubly-linked list as FirstEntry,
+ or FirstEntry is invalid.
+
+**/
+BOOLEAN
+EFIAPI
+IsNodeInList (
+ IN CONST LIST_ENTRY *FirstEntry,
+ IN CONST LIST_ENTRY *SecondEntry
+ );
+
+/**
+ Initializes the head node of a doubly linked list, and returns the pointer to
+ the head node of the doubly linked list.
+
+ Initializes the forward and backward links of a new linked list. After
+ initializing a linked list with this function, the other linked list
+ functions may be used to add and remove nodes from the linked list. It is up
+ to the caller of this function to allocate the memory for ListHead.
+
+ If ListHead is NULL, then ASSERT().
+
+ @param ListHead A pointer to the head node of a new doubly linked list.
+
+ @return ListHead
+
+**/
+LIST_ENTRY *
+EFIAPI
+InitializeListHead (
+ IN OUT LIST_ENTRY *ListHead
+ );
+
+/**
+ Adds a node to the beginning of a doubly linked list, and returns the pointer
+ to the head node of the doubly linked list.
+
+ Adds the node Entry at the beginning of the doubly linked list denoted by
+ ListHead, and returns ListHead.
+
+ If ListHead is NULL, then ASSERT().
+ If Entry is NULL, then ASSERT().
+ If ListHead was not initialized with INTIALIZE_LIST_HEAD_VARIABLE() or
+ InitializeListHead(), then ASSERT().
+ If PcdMaximumLinkedListLength is not zero, and prior to insertion the number
+ of nodes in ListHead, including the ListHead node, is greater than or
+ equal to PcdMaximumLinkedListLength, then ASSERT().
+
+ @param ListHead A pointer to the head node of a doubly linked list.
+ @param Entry A pointer to a node that is to be inserted at the beginning
+ of a doubly linked list.
+
+ @return ListHead
+
+**/
+LIST_ENTRY *
+EFIAPI
+InsertHeadList (
+ IN OUT LIST_ENTRY *ListHead,
+ IN OUT LIST_ENTRY *Entry
+ );
+
+/**
+ Adds a node to the end of a doubly linked list, and returns the pointer to
+ the head node of the doubly linked list.
+
+ Adds the node Entry to the end of the doubly linked list denoted by ListHead,
+ and returns ListHead.
+
+ If ListHead is NULL, then ASSERT().
+ If Entry is NULL, then ASSERT().
+ If ListHead was not initialized with INTIALIZE_LIST_HEAD_VARIABLE() or
+ InitializeListHead(), then ASSERT().
+ If PcdMaximumLinkedListLength is not zero, and prior to insertion the number
+ of nodes in ListHead, including the ListHead node, is greater than or
+ equal to PcdMaximumLinkedListLength, then ASSERT().
+
+ @param ListHead A pointer to the head node of a doubly linked list.
+ @param Entry A pointer to a node that is to be added at the end of the
+ doubly linked list.
+
+ @return ListHead
+
+**/
+LIST_ENTRY *
+EFIAPI
+InsertTailList (
+ IN OUT LIST_ENTRY *ListHead,
+ IN OUT LIST_ENTRY *Entry
+ );
+
+/**
+ Retrieves the first node of a doubly linked list.
+
+ Returns the first node of a doubly linked list. List must have been
+ initialized with INTIALIZE_LIST_HEAD_VARIABLE() or InitializeListHead().
+ If List is empty, then List is returned.
+
+ If List is NULL, then ASSERT().
+ If List was not initialized with INTIALIZE_LIST_HEAD_VARIABLE() or
+ InitializeListHead(), then ASSERT().
+ If PcdMaximumLinkedListLength is not zero, and the number of nodes
+ in List, including the List node, is greater than or equal to
+ PcdMaximumLinkedListLength, then ASSERT().
+
+ @param List A pointer to the head node of a doubly linked list.
+
+ @return The first node of a doubly linked list.
+ @retval List The list is empty.
+
+**/
+LIST_ENTRY *
+EFIAPI
+GetFirstNode (
+ IN CONST LIST_ENTRY *List
+ );
+
+/**
+ Retrieves the next node of a doubly linked list.
+
+ Returns the node of a doubly linked list that follows Node.
+ List must have been initialized with INTIALIZE_LIST_HEAD_VARIABLE()
+ or InitializeListHead(). If List is empty, then List is returned.
+
+ If List is NULL, then ASSERT().
+ If Node is NULL, then ASSERT().
+ If List was not initialized with INTIALIZE_LIST_HEAD_VARIABLE() or
+ InitializeListHead(), then ASSERT().
+ If PcdMaximumLinkedListLength is not zero, and List contains more than
+ PcdMaximumLinkedListLength nodes, then ASSERT().
+ If PcdVerifyNodeInList is TRUE and Node is not a node in List, then ASSERT().
+
+ @param List A pointer to the head node of a doubly linked list.
+ @param Node A pointer to a node in the doubly linked list.
+
+ @return The pointer to the next node if one exists. Otherwise List is returned.
+
+**/
+LIST_ENTRY *
+EFIAPI
+GetNextNode (
+ IN CONST LIST_ENTRY *List,
+ IN CONST LIST_ENTRY *Node
+ );
+
+/**
+ Retrieves the previous node of a doubly linked list.
+
+ Returns the node of a doubly linked list that precedes Node.
+ List must have been initialized with INTIALIZE_LIST_HEAD_VARIABLE()
+ or InitializeListHead(). If List is empty, then List is returned.
+
+ If List is NULL, then ASSERT().
+ If Node is NULL, then ASSERT().
+ If List was not initialized with INTIALIZE_LIST_HEAD_VARIABLE() or
+ InitializeListHead(), then ASSERT().
+ If PcdMaximumLinkedListLength is not zero, and List contains more than
+ PcdMaximumLinkedListLength nodes, then ASSERT().
+ If PcdVerifyNodeInList is TRUE and Node is not a node in List, then ASSERT().
+
+ @param List A pointer to the head node of a doubly linked list.
+ @param Node A pointer to a node in the doubly linked list.
+
+ @return The pointer to the previous node if one exists. Otherwise List is returned.
+
+**/
+LIST_ENTRY *
+EFIAPI
+GetPreviousNode (
+ IN CONST LIST_ENTRY *List,
+ IN CONST LIST_ENTRY *Node
+ );
+
+/**
+ Checks to see if a doubly linked list is empty or not.
+
+ Checks to see if the doubly linked list is empty. If the linked list contains
+ zero nodes, this function returns TRUE. Otherwise, it returns FALSE.
+
+ If ListHead is NULL, then ASSERT().
+ If ListHead was not initialized with INTIALIZE_LIST_HEAD_VARIABLE() or
+ InitializeListHead(), then ASSERT().
+ If PcdMaximumLinkedListLength is not zero, and the number of nodes
+ in List, including the List node, is greater than or equal to
+ PcdMaximumLinkedListLength, then ASSERT().
+
+ @param ListHead A pointer to the head node of a doubly linked list.
+
+ @retval TRUE The linked list is empty.
+ @retval FALSE The linked list is not empty.
+
+**/
+BOOLEAN
+EFIAPI
+IsListEmpty (
+ IN CONST LIST_ENTRY *ListHead
+ );
+
+/**
+ Determines if a node in a doubly linked list is the head node of a the same
+ doubly linked list. This function is typically used to terminate a loop that
+ traverses all the nodes in a doubly linked list starting with the head node.
+
+ Returns TRUE if Node is equal to List. Returns FALSE if Node is one of the
+ nodes in the doubly linked list specified by List. List must have been
+ initialized with INTIALIZE_LIST_HEAD_VARIABLE() or InitializeListHead().
+
+ If List is NULL, then ASSERT().
+ If Node is NULL, then ASSERT().
+ If List was not initialized with INTIALIZE_LIST_HEAD_VARIABLE() or InitializeListHead(),
+ then ASSERT().
+ If PcdMaximumLinkedListLength is not zero, and the number of nodes
+ in List, including the List node, is greater than or equal to
+ PcdMaximumLinkedListLength, then ASSERT().
+ If PcdVerifyNodeInList is TRUE and Node is not a node in List the and Node is not equal
+ to List, then ASSERT().
+
+ @param List A pointer to the head node of a doubly linked list.
+ @param Node A pointer to a node in the doubly linked list.
+
+ @retval TRUE Node is the head of the doubly-linked list pointed by List.
+ @retval FALSE Node is not the head of the doubly-linked list pointed by List.
+
+**/
+BOOLEAN
+EFIAPI
+IsNull (
+ IN CONST LIST_ENTRY *List,
+ IN CONST LIST_ENTRY *Node
+ );
+
+/**
+ Determines if a node the last node in a doubly linked list.
+
+ Returns TRUE if Node is the last node in the doubly linked list specified by
+ List. Otherwise, FALSE is returned. List must have been initialized with
+ INTIALIZE_LIST_HEAD_VARIABLE() or InitializeListHead().
+
+ If List is NULL, then ASSERT().
+ If Node is NULL, then ASSERT().
+ If List was not initialized with INTIALIZE_LIST_HEAD_VARIABLE() or
+ InitializeListHead(), then ASSERT().
+ If PcdMaximumLinkedListLength is not zero, and the number of nodes
+ in List, including the List node, is greater than or equal to
+ PcdMaximumLinkedListLength, then ASSERT().
+ If PcdVerifyNodeInList is TRUE and Node is not a node in List, then ASSERT().
+
+ @param List A pointer to the head node of a doubly linked list.
+ @param Node A pointer to a node in the doubly linked list.
+
+ @retval TRUE Node is the last node in the linked list.
+ @retval FALSE Node is not the last node in the linked list.
+
+**/
+BOOLEAN
+EFIAPI
+IsNodeAtEnd (
+ IN CONST LIST_ENTRY *List,
+ IN CONST LIST_ENTRY *Node
+ );
+
+/**
+ Swaps the location of two nodes in a doubly linked list, and returns the
+ first node after the swap.
+
+ If FirstEntry is identical to SecondEntry, then SecondEntry is returned.
+ Otherwise, the location of the FirstEntry node is swapped with the location
+ of the SecondEntry node in a doubly linked list. SecondEntry must be in the
+ same double linked list as FirstEntry and that double linked list must have
+ been initialized with INTIALIZE_LIST_HEAD_VARIABLE() or InitializeListHead().
+ SecondEntry is returned after the nodes are swapped.
+
+ If FirstEntry is NULL, then ASSERT().
+ If SecondEntry is NULL, then ASSERT().
+ If PcdVerifyNodeInList is TRUE and SecondEntry and FirstEntry are not in the
+ same linked list, then ASSERT().
+ If PcdMaximumLinkedListLength is not zero, and the number of nodes in the
+ linked list containing the FirstEntry and SecondEntry nodes, including
+ the FirstEntry and SecondEntry nodes, is greater than or equal to
+ PcdMaximumLinkedListLength, then ASSERT().
+
+ @param FirstEntry A pointer to a node in a linked list.
+ @param SecondEntry A pointer to another node in the same linked list.
+
+ @return SecondEntry.
+
+**/
+LIST_ENTRY *
+EFIAPI
+SwapListEntries (
+ IN OUT LIST_ENTRY *FirstEntry,
+ IN OUT LIST_ENTRY *SecondEntry
+ );
+
+/**
+ Removes a node from a doubly linked list, and returns the node that follows
+ the removed node.
+
+ Removes the node Entry from a doubly linked list. It is up to the caller of
+ this function to release the memory used by this node if that is required. On
+ exit, the node following Entry in the doubly linked list is returned. If
+ Entry is the only node in the linked list, then the head node of the linked
+ list is returned.
+
+ If Entry is NULL, then ASSERT().
+ If Entry is the head node of an empty list, then ASSERT().
+ If PcdMaximumLinkedListLength is not zero, and the number of nodes in the
+ linked list containing Entry, including the Entry node, is greater than
+ or equal to PcdMaximumLinkedListLength, then ASSERT().
+
+ @param Entry A pointer to a node in a linked list.
+
+ @return Entry.
+
+**/
+LIST_ENTRY *
+EFIAPI
+RemoveEntryList (
+ IN CONST LIST_ENTRY *Entry
+ );
+
+//
+// Math Services
+//
+
+/**
+ Prototype for comparison function for any two element types.
+
+ @param[in] Buffer1 The pointer to first buffer.
+ @param[in] Buffer2 The pointer to second buffer.
+
+ @retval 0 Buffer1 equal to Buffer2.
+ @return <0 Buffer1 is less than Buffer2.
+ @return >0 Buffer1 is greater than Buffer2.
+**/
+typedef
+INTN
+(EFIAPI *BASE_SORT_COMPARE)(
+ IN CONST VOID *Buffer1,
+ IN CONST VOID *Buffer2
+ );
+
+/**
+ This function is identical to perform QuickSort,
+ except that is uses the pre-allocated buffer so the in place sorting does not need to
+ allocate and free buffers constantly.
+
+ Each element must be equal sized.
+
+ if BufferToSort is NULL, then ASSERT.
+ if CompareFunction is NULL, then ASSERT.
+ if BufferOneElement is NULL, then ASSERT.
+ if ElementSize is < 1, then ASSERT.
+
+ if Count is < 2 then perform no action.
+
+ @param[in, out] BufferToSort on call a Buffer of (possibly sorted) elements
+ on return a buffer of sorted elements
+ @param[in] Count the number of elements in the buffer to sort
+ @param[in] ElementSize Size of an element in bytes
+ @param[in] CompareFunction The function to call to perform the comparison
+ of any 2 elements
+ @param[out] BufferOneElement Caller provided buffer whose size equals to ElementSize.
+ It's used by QuickSort() for swapping in sorting.
+**/
+VOID
+EFIAPI
+QuickSort (
+ IN OUT VOID *BufferToSort,
+ IN CONST UINTN Count,
+ IN CONST UINTN ElementSize,
+ IN BASE_SORT_COMPARE CompareFunction,
+ OUT VOID *BufferOneElement
+ );
+
+/**
+ Shifts a 64-bit integer left between 0 and 63 bits. The low bits are filled
+ with zeros. The shifted value is returned.
+
+ This function shifts the 64-bit value Operand to the left by Count bits. The
+ low Count bits are set to zero. The shifted value is returned.
+
+ If Count is greater than 63, then ASSERT().
+
+ @param Operand The 64-bit operand to shift left.
+ @param Count The number of bits to shift left.
+
+ @return Operand << Count.
+
+**/
+UINT64
+EFIAPI
+LShiftU64 (
+ IN UINT64 Operand,
+ IN UINTN Count
+ );
+
+/**
+ Shifts a 64-bit integer right between 0 and 63 bits. This high bits are
+ filled with zeros. The shifted value is returned.
+
+ This function shifts the 64-bit value Operand to the right by Count bits. The
+ high Count bits are set to zero. The shifted value is returned.
+
+ If Count is greater than 63, then ASSERT().
+
+ @param Operand The 64-bit operand to shift right.
+ @param Count The number of bits to shift right.
+
+ @return Operand >> Count
+
+**/
+UINT64
+EFIAPI
+RShiftU64 (
+ IN UINT64 Operand,
+ IN UINTN Count
+ );
+
+/**
+ Shifts a 64-bit integer right between 0 and 63 bits. The high bits are filled
+ with original integer's bit 63. The shifted value is returned.
+
+ This function shifts the 64-bit value Operand to the right by Count bits. The
+ high Count bits are set to bit 63 of Operand. The shifted value is returned.
+
+ If Count is greater than 63, then ASSERT().
+
+ @param Operand The 64-bit operand to shift right.
+ @param Count The number of bits to shift right.
+
+ @return Operand >> Count
+
+**/
+UINT64
+EFIAPI
+ARShiftU64 (
+ IN UINT64 Operand,
+ IN UINTN Count
+ );
+
+/**
+ Rotates a 32-bit integer left between 0 and 31 bits, filling the low bits
+ with the high bits that were rotated.
+
+ This function rotates the 32-bit value Operand to the left by Count bits. The
+ low Count bits are fill with the high Count bits of Operand. The rotated
+ value is returned.
+
+ If Count is greater than 31, then ASSERT().
+
+ @param Operand The 32-bit operand to rotate left.
+ @param Count The number of bits to rotate left.
+
+ @return Operand << Count
+
+**/
+UINT32
+EFIAPI
+LRotU32 (
+ IN UINT32 Operand,
+ IN UINTN Count
+ );
+
+/**
+ Rotates a 32-bit integer right between 0 and 31 bits, filling the high bits
+ with the low bits that were rotated.
+
+ This function rotates the 32-bit value Operand to the right by Count bits.
+ The high Count bits are fill with the low Count bits of Operand. The rotated
+ value is returned.
+
+ If Count is greater than 31, then ASSERT().
+
+ @param Operand The 32-bit operand to rotate right.
+ @param Count The number of bits to rotate right.
+
+ @return Operand >> Count
+
+**/
+UINT32
+EFIAPI
+RRotU32 (
+ IN UINT32 Operand,
+ IN UINTN Count
+ );
+
+/**
+ Rotates a 64-bit integer left between 0 and 63 bits, filling the low bits
+ with the high bits that were rotated.
+
+ This function rotates the 64-bit value Operand to the left by Count bits. The
+ low Count bits are fill with the high Count bits of Operand. The rotated
+ value is returned.
+
+ If Count is greater than 63, then ASSERT().
+
+ @param Operand The 64-bit operand to rotate left.
+ @param Count The number of bits to rotate left.
+
+ @return Operand << Count
+
+**/
+UINT64
+EFIAPI
+LRotU64 (
+ IN UINT64 Operand,
+ IN UINTN Count
+ );
+
+/**
+ Rotates a 64-bit integer right between 0 and 63 bits, filling the high bits
+ with the high low bits that were rotated.
+
+ This function rotates the 64-bit value Operand to the right by Count bits.
+ The high Count bits are fill with the low Count bits of Operand. The rotated
+ value is returned.
+
+ If Count is greater than 63, then ASSERT().
+
+ @param Operand The 64-bit operand to rotate right.
+ @param Count The number of bits to rotate right.
+
+ @return Operand >> Count
+
+**/
+UINT64
+EFIAPI
+RRotU64 (
+ IN UINT64 Operand,
+ IN UINTN Count
+ );
+
+/**
+ Returns the bit position of the lowest bit set in a 32-bit value.
+
+ This function computes the bit position of the lowest bit set in the 32-bit
+ value specified by Operand. If Operand is zero, then -1 is returned.
+ Otherwise, a value between 0 and 31 is returned.
+
+ @param Operand The 32-bit operand to evaluate.
+
+ @retval 0..31 The lowest bit set in Operand was found.
+ @retval -1 Operand is zero.
+
+**/
+INTN
+EFIAPI
+LowBitSet32 (
+ IN UINT32 Operand
+ );
+
+/**
+ Returns the bit position of the lowest bit set in a 64-bit value.
+
+ This function computes the bit position of the lowest bit set in the 64-bit
+ value specified by Operand. If Operand is zero, then -1 is returned.
+ Otherwise, a value between 0 and 63 is returned.
+
+ @param Operand The 64-bit operand to evaluate.
+
+ @retval 0..63 The lowest bit set in Operand was found.
+ @retval -1 Operand is zero.
+
+
+**/
+INTN
+EFIAPI
+LowBitSet64 (
+ IN UINT64 Operand
+ );
+
+/**
+ Returns the bit position of the highest bit set in a 32-bit value. Equivalent
+ to log2(x).
+
+ This function computes the bit position of the highest bit set in the 32-bit
+ value specified by Operand. If Operand is zero, then -1 is returned.
+ Otherwise, a value between 0 and 31 is returned.
+
+ @param Operand The 32-bit operand to evaluate.
+
+ @retval 0..31 Position of the highest bit set in Operand if found.
+ @retval -1 Operand is zero.
+
+**/
+INTN
+EFIAPI
+HighBitSet32 (
+ IN UINT32 Operand
+ );
+
+/**
+ Returns the bit position of the highest bit set in a 64-bit value. Equivalent
+ to log2(x).
+
+ This function computes the bit position of the highest bit set in the 64-bit
+ value specified by Operand. If Operand is zero, then -1 is returned.
+ Otherwise, a value between 0 and 63 is returned.
+
+ @param Operand The 64-bit operand to evaluate.
+
+ @retval 0..63 Position of the highest bit set in Operand if found.
+ @retval -1 Operand is zero.
+
+**/
+INTN
+EFIAPI
+HighBitSet64 (
+ IN UINT64 Operand
+ );
+
+/**
+ Returns the value of the highest bit set in a 32-bit value. Equivalent to
+ 1 << log2(x).
+
+ This function computes the value of the highest bit set in the 32-bit value
+ specified by Operand. If Operand is zero, then zero is returned.
+
+ @param Operand The 32-bit operand to evaluate.
+
+ @return 1 << HighBitSet32(Operand)
+ @retval 0 Operand is zero.
+
+**/
+UINT32
+EFIAPI
+GetPowerOfTwo32 (
+ IN UINT32 Operand
+ );
+
+/**
+ Returns the value of the highest bit set in a 64-bit value. Equivalent to
+ 1 << log2(x).
+
+ This function computes the value of the highest bit set in the 64-bit value
+ specified by Operand. If Operand is zero, then zero is returned.
+
+ @param Operand The 64-bit operand to evaluate.
+
+ @return 1 << HighBitSet64(Operand)
+ @retval 0 Operand is zero.
+
+**/
+UINT64
+EFIAPI
+GetPowerOfTwo64 (
+ IN UINT64 Operand
+ );
+
+/**
+ Switches the endianness of a 16-bit integer.
+
+ This function swaps the bytes in a 16-bit unsigned value to switch the value
+ from little endian to big endian or vice versa. The byte swapped value is
+ returned.
+
+ @param Value A 16-bit unsigned value.
+
+ @return The byte swapped Value.
+
+**/
+UINT16
+EFIAPI
+SwapBytes16 (
+ IN UINT16 Value
+ );
+
+/**
+ Switches the endianness of a 32-bit integer.
+
+ This function swaps the bytes in a 32-bit unsigned value to switch the value
+ from little endian to big endian or vice versa. The byte swapped value is
+ returned.
+
+ @param Value A 32-bit unsigned value.
+
+ @return The byte swapped Value.
+
+**/
+UINT32
+EFIAPI
+SwapBytes32 (
+ IN UINT32 Value
+ );
+
+/**
+ Switches the endianness of a 64-bit integer.
+
+ This function swaps the bytes in a 64-bit unsigned value to switch the value
+ from little endian to big endian or vice versa. The byte swapped value is
+ returned.
+
+ @param Value A 64-bit unsigned value.
+
+ @return The byte swapped Value.
+
+**/
+UINT64
+EFIAPI
+SwapBytes64 (
+ IN UINT64 Value
+ );
+
+/**
+ Multiples a 64-bit unsigned integer by a 32-bit unsigned integer and
+ generates a 64-bit unsigned result.
+
+ This function multiples the 64-bit unsigned value Multiplicand by the 32-bit
+ unsigned value Multiplier and generates a 64-bit unsigned result. This 64-
+ bit unsigned result is returned.
+
+ @param Multiplicand A 64-bit unsigned value.
+ @param Multiplier A 32-bit unsigned value.
+
+ @return Multiplicand * Multiplier
+
+**/
+UINT64
+EFIAPI
+MultU64x32 (
+ IN UINT64 Multiplicand,
+ IN UINT32 Multiplier
+ );
+
+/**
+ Multiples a 64-bit unsigned integer by a 64-bit unsigned integer and
+ generates a 64-bit unsigned result.
+
+ This function multiples the 64-bit unsigned value Multiplicand by the 64-bit
+ unsigned value Multiplier and generates a 64-bit unsigned result. This 64-
+ bit unsigned result is returned.
+
+ @param Multiplicand A 64-bit unsigned value.
+ @param Multiplier A 64-bit unsigned value.
+
+ @return Multiplicand * Multiplier.
+
+**/
+UINT64
+EFIAPI
+MultU64x64 (
+ IN UINT64 Multiplicand,
+ IN UINT64 Multiplier
+ );
+
+/**
+ Multiples a 64-bit signed integer by a 64-bit signed integer and generates a
+ 64-bit signed result.
+
+ This function multiples the 64-bit signed value Multiplicand by the 64-bit
+ signed value Multiplier and generates a 64-bit signed result. This 64-bit
+ signed result is returned.
+
+ @param Multiplicand A 64-bit signed value.
+ @param Multiplier A 64-bit signed value.
+
+ @return Multiplicand * Multiplier
+
+**/
+INT64
+EFIAPI
+MultS64x64 (
+ IN INT64 Multiplicand,
+ IN INT64 Multiplier
+ );
+
+/**
+ Divides a 64-bit unsigned integer by a 32-bit unsigned integer and generates
+ a 64-bit unsigned result.
+
+ This function divides the 64-bit unsigned value Dividend by the 32-bit
+ unsigned value Divisor and generates a 64-bit unsigned quotient. This
+ function returns the 64-bit unsigned quotient.
+
+ If Divisor is 0, then ASSERT().
+
+ @param Dividend A 64-bit unsigned value.
+ @param Divisor A 32-bit unsigned value.
+
+ @return Dividend / Divisor.
+
+**/
+UINT64
+EFIAPI
+DivU64x32 (
+ IN UINT64 Dividend,
+ IN UINT32 Divisor
+ );
+
+/**
+ Divides a 64-bit unsigned integer by a 32-bit unsigned integer and generates
+ a 32-bit unsigned remainder.
+
+ This function divides the 64-bit unsigned value Dividend by the 32-bit
+ unsigned value Divisor and generates a 32-bit remainder. This function
+ returns the 32-bit unsigned remainder.
+
+ If Divisor is 0, then ASSERT().
+
+ @param Dividend A 64-bit unsigned value.
+ @param Divisor A 32-bit unsigned value.
+
+ @return Dividend % Divisor.
+
+**/
+UINT32
+EFIAPI
+ModU64x32 (
+ IN UINT64 Dividend,
+ IN UINT32 Divisor
+ );
+
+/**
+ Divides a 64-bit unsigned integer by a 32-bit unsigned integer and generates
+ a 64-bit unsigned result and an optional 32-bit unsigned remainder.
+
+ This function divides the 64-bit unsigned value Dividend by the 32-bit
+ unsigned value Divisor and generates a 64-bit unsigned quotient. If Remainder
+ is not NULL, then the 32-bit unsigned remainder is returned in Remainder.
+ This function returns the 64-bit unsigned quotient.
+
+ If Divisor is 0, then ASSERT().
+
+ @param Dividend A 64-bit unsigned value.
+ @param Divisor A 32-bit unsigned value.
+ @param Remainder A pointer to a 32-bit unsigned value. This parameter is
+ optional and may be NULL.
+
+ @return Dividend / Divisor.
+
+**/
+UINT64
+EFIAPI
+DivU64x32Remainder (
+ IN UINT64 Dividend,
+ IN UINT32 Divisor,
+ OUT UINT32 *Remainder OPTIONAL
+ );
+
+/**
+ Divides a 64-bit unsigned integer by a 64-bit unsigned integer and generates
+ a 64-bit unsigned result and an optional 64-bit unsigned remainder.
+
+ This function divides the 64-bit unsigned value Dividend by the 64-bit
+ unsigned value Divisor and generates a 64-bit unsigned quotient. If Remainder
+ is not NULL, then the 64-bit unsigned remainder is returned in Remainder.
+ This function returns the 64-bit unsigned quotient.
+
+ If Divisor is 0, then ASSERT().
+
+ @param Dividend A 64-bit unsigned value.
+ @param Divisor A 64-bit unsigned value.
+ @param Remainder A pointer to a 64-bit unsigned value. This parameter is
+ optional and may be NULL.
+
+ @return Dividend / Divisor.
+
+**/
+UINT64
+EFIAPI
+DivU64x64Remainder (
+ IN UINT64 Dividend,
+ IN UINT64 Divisor,
+ OUT UINT64 *Remainder OPTIONAL
+ );
+
+/**
+ Divides a 64-bit signed integer by a 64-bit signed integer and generates a
+ 64-bit signed result and a optional 64-bit signed remainder.
+
+ This function divides the 64-bit signed value Dividend by the 64-bit signed
+ value Divisor and generates a 64-bit signed quotient. If Remainder is not
+ NULL, then the 64-bit signed remainder is returned in Remainder. This
+ function returns the 64-bit signed quotient.
+
+ It is the caller's responsibility to not call this function with a Divisor of 0.
+ If Divisor is 0, then the quotient and remainder should be assumed to be
+ the largest negative integer.
+
+ If Divisor is 0, then ASSERT().
+
+ @param Dividend A 64-bit signed value.
+ @param Divisor A 64-bit signed value.
+ @param Remainder A pointer to a 64-bit signed value. This parameter is
+ optional and may be NULL.
+
+ @return Dividend / Divisor.
+
+**/
+INT64
+EFIAPI
+DivS64x64Remainder (
+ IN INT64 Dividend,
+ IN INT64 Divisor,
+ OUT INT64 *Remainder OPTIONAL
+ );
+
+/**
+ Reads a 16-bit value from memory that may be unaligned.
+
+ This function returns the 16-bit value pointed to by Buffer. The function
+ guarantees that the read operation does not produce an alignment fault.
+
+ If the Buffer is NULL, then ASSERT().
+
+ @param Buffer The pointer to a 16-bit value that may be unaligned.
+
+ @return The 16-bit value read from Buffer.
+
+**/
+UINT16
+EFIAPI
+ReadUnaligned16 (
+ IN CONST UINT16 *Buffer
+ );
+
+/**
+ Writes a 16-bit value to memory that may be unaligned.
+
+ This function writes the 16-bit value specified by Value to Buffer. Value is
+ returned. The function guarantees that the write operation does not produce
+ an alignment fault.
+
+ If the Buffer is NULL, then ASSERT().
+
+ @param Buffer The pointer to a 16-bit value that may be unaligned.
+ @param Value 16-bit value to write to Buffer.
+
+ @return The 16-bit value to write to Buffer.
+
+**/
+UINT16
+EFIAPI
+WriteUnaligned16 (
+ OUT UINT16 *Buffer,
+ IN UINT16 Value
+ );
+
+/**
+ Reads a 24-bit value from memory that may be unaligned.
+
+ This function returns the 24-bit value pointed to by Buffer. The function
+ guarantees that the read operation does not produce an alignment fault.
+
+ If the Buffer is NULL, then ASSERT().
+
+ @param Buffer The pointer to a 24-bit value that may be unaligned.
+
+ @return The 24-bit value read from Buffer.
+
+**/
+UINT32
+EFIAPI
+ReadUnaligned24 (
+ IN CONST UINT32 *Buffer
+ );
+
+/**
+ Writes a 24-bit value to memory that may be unaligned.
+
+ This function writes the 24-bit value specified by Value to Buffer. Value is
+ returned. The function guarantees that the write operation does not produce
+ an alignment fault.
+
+ If the Buffer is NULL, then ASSERT().
+
+ @param Buffer The pointer to a 24-bit value that may be unaligned.
+ @param Value 24-bit value to write to Buffer.
+
+ @return The 24-bit value to write to Buffer.
+
+**/
+UINT32
+EFIAPI
+WriteUnaligned24 (
+ OUT UINT32 *Buffer,
+ IN UINT32 Value
+ );
+
+/**
+ Reads a 32-bit value from memory that may be unaligned.
+
+ This function returns the 32-bit value pointed to by Buffer. The function
+ guarantees that the read operation does not produce an alignment fault.
+
+ If the Buffer is NULL, then ASSERT().
+
+ @param Buffer The pointer to a 32-bit value that may be unaligned.
+
+ @return The 32-bit value read from Buffer.
+
+**/
+UINT32
+EFIAPI
+ReadUnaligned32 (
+ IN CONST UINT32 *Buffer
+ );
+
+/**
+ Writes a 32-bit value to memory that may be unaligned.
+
+ This function writes the 32-bit value specified by Value to Buffer. Value is
+ returned. The function guarantees that the write operation does not produce
+ an alignment fault.
+
+ If the Buffer is NULL, then ASSERT().
+
+ @param Buffer The pointer to a 32-bit value that may be unaligned.
+ @param Value 32-bit value to write to Buffer.
+
+ @return The 32-bit value to write to Buffer.
+
+**/
+UINT32
+EFIAPI
+WriteUnaligned32 (
+ OUT UINT32 *Buffer,
+ IN UINT32 Value
+ );
+
+/**
+ Reads a 64-bit value from memory that may be unaligned.
+
+ This function returns the 64-bit value pointed to by Buffer. The function
+ guarantees that the read operation does not produce an alignment fault.
+
+ If the Buffer is NULL, then ASSERT().
+
+ @param Buffer The pointer to a 64-bit value that may be unaligned.
+
+ @return The 64-bit value read from Buffer.
+
+**/
+UINT64
+EFIAPI
+ReadUnaligned64 (
+ IN CONST UINT64 *Buffer
+ );
+
+/**
+ Writes a 64-bit value to memory that may be unaligned.
+
+ This function writes the 64-bit value specified by Value to Buffer. Value is
+ returned. The function guarantees that the write operation does not produce
+ an alignment fault.
+
+ If the Buffer is NULL, then ASSERT().
+
+ @param Buffer The pointer to a 64-bit value that may be unaligned.
+ @param Value 64-bit value to write to Buffer.
+
+ @return The 64-bit value to write to Buffer.
+
+**/
+UINT64
+EFIAPI
+WriteUnaligned64 (
+ OUT UINT64 *Buffer,
+ IN UINT64 Value
+ );
+
+//
+// Bit Field Functions
+//
+
+/**
+ Returns a bit field from an 8-bit value.
+
+ Returns the bitfield specified by the StartBit and the EndBit from Operand.
+
+ If 8-bit operations are not supported, then ASSERT().
+ If StartBit is greater than 7, then ASSERT().
+ If EndBit is greater than 7, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+
+ @param Operand Operand on which to perform the bitfield operation.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..7.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..7.
+
+ @return The bit field read.
+
+**/
+UINT8
+EFIAPI
+BitFieldRead8 (
+ IN UINT8 Operand,
+ IN UINTN StartBit,
+ IN UINTN EndBit
+ );
+
+/**
+ Writes a bit field to an 8-bit value, and returns the result.
+
+ Writes Value to the bit field specified by the StartBit and the EndBit in
+ Operand. All other bits in Operand are preserved. The new 8-bit value is
+ returned.
+
+ If 8-bit operations are not supported, then ASSERT().
+ If StartBit is greater than 7, then ASSERT().
+ If EndBit is greater than 7, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Operand Operand on which to perform the bitfield operation.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..7.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..7.
+ @param Value New value of the bit field.
+
+ @return The new 8-bit value.
+
+**/
+UINT8
+EFIAPI
+BitFieldWrite8 (
+ IN UINT8 Operand,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT8 Value
+ );
+
+/**
+ Reads a bit field from an 8-bit value, performs a bitwise OR, and returns the
+ result.
+
+ Performs a bitwise OR between the bit field specified by StartBit
+ and EndBit in Operand and the value specified by OrData. All other bits in
+ Operand are preserved. The new 8-bit value is returned.
+
+ If 8-bit operations are not supported, then ASSERT().
+ If StartBit is greater than 7, then ASSERT().
+ If EndBit is greater than 7, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Operand Operand on which to perform the bitfield operation.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..7.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..7.
+ @param OrData The value to OR with the read value from the value
+
+ @return The new 8-bit value.
+
+**/
+UINT8
+EFIAPI
+BitFieldOr8 (
+ IN UINT8 Operand,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT8 OrData
+ );
+
+/**
+ Reads a bit field from an 8-bit value, performs a bitwise AND, and returns
+ the result.
+
+ Performs a bitwise AND between the bit field specified by StartBit and EndBit
+ in Operand and the value specified by AndData. All other bits in Operand are
+ preserved. The new 8-bit value is returned.
+
+ If 8-bit operations are not supported, then ASSERT().
+ If StartBit is greater than 7, then ASSERT().
+ If EndBit is greater than 7, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Operand Operand on which to perform the bitfield operation.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..7.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..7.
+ @param AndData The value to AND with the read value from the value.
+
+ @return The new 8-bit value.
+
+**/
+UINT8
+EFIAPI
+BitFieldAnd8 (
+ IN UINT8 Operand,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT8 AndData
+ );
+
+/**
+ Reads a bit field from an 8-bit value, performs a bitwise AND followed by a
+ bitwise OR, and returns the result.
+
+ Performs a bitwise AND between the bit field specified by StartBit and EndBit
+ in Operand and the value specified by AndData, followed by a bitwise
+ OR with value specified by OrData. All other bits in Operand are
+ preserved. The new 8-bit value is returned.
+
+ If 8-bit operations are not supported, then ASSERT().
+ If StartBit is greater than 7, then ASSERT().
+ If EndBit is greater than 7, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Operand Operand on which to perform the bitfield operation.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..7.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..7.
+ @param AndData The value to AND with the read value from the value.
+ @param OrData The value to OR with the result of the AND operation.
+
+ @return The new 8-bit value.
+
+**/
+UINT8
+EFIAPI
+BitFieldAndThenOr8 (
+ IN UINT8 Operand,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT8 AndData,
+ IN UINT8 OrData
+ );
+
+/**
+ Returns a bit field from a 16-bit value.
+
+ Returns the bitfield specified by the StartBit and the EndBit from Operand.
+
+ If 16-bit operations are not supported, then ASSERT().
+ If StartBit is greater than 15, then ASSERT().
+ If EndBit is greater than 15, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+
+ @param Operand Operand on which to perform the bitfield operation.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..15.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..15.
+
+ @return The bit field read.
+
+**/
+UINT16
+EFIAPI
+BitFieldRead16 (
+ IN UINT16 Operand,
+ IN UINTN StartBit,
+ IN UINTN EndBit
+ );
+
+/**
+ Writes a bit field to a 16-bit value, and returns the result.
+
+ Writes Value to the bit field specified by the StartBit and the EndBit in
+ Operand. All other bits in Operand are preserved. The new 16-bit value is
+ returned.
+
+ If 16-bit operations are not supported, then ASSERT().
+ If StartBit is greater than 15, then ASSERT().
+ If EndBit is greater than 15, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Operand Operand on which to perform the bitfield operation.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..15.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..15.
+ @param Value New value of the bit field.
+
+ @return The new 16-bit value.
+
+**/
+UINT16
+EFIAPI
+BitFieldWrite16 (
+ IN UINT16 Operand,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT16 Value
+ );
+
+/**
+ Reads a bit field from a 16-bit value, performs a bitwise OR, and returns the
+ result.
+
+ Performs a bitwise OR between the bit field specified by StartBit
+ and EndBit in Operand and the value specified by OrData. All other bits in
+ Operand are preserved. The new 16-bit value is returned.
+
+ If 16-bit operations are not supported, then ASSERT().
+ If StartBit is greater than 15, then ASSERT().
+ If EndBit is greater than 15, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Operand Operand on which to perform the bitfield operation.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..15.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..15.
+ @param OrData The value to OR with the read value from the value
+
+ @return The new 16-bit value.
+
+**/
+UINT16
+EFIAPI
+BitFieldOr16 (
+ IN UINT16 Operand,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT16 OrData
+ );
+
+/**
+ Reads a bit field from a 16-bit value, performs a bitwise AND, and returns
+ the result.
+
+ Performs a bitwise AND between the bit field specified by StartBit and EndBit
+ in Operand and the value specified by AndData. All other bits in Operand are
+ preserved. The new 16-bit value is returned.
+
+ If 16-bit operations are not supported, then ASSERT().
+ If StartBit is greater than 15, then ASSERT().
+ If EndBit is greater than 15, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Operand Operand on which to perform the bitfield operation.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..15.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..15.
+ @param AndData The value to AND with the read value from the value
+
+ @return The new 16-bit value.
+
+**/
+UINT16
+EFIAPI
+BitFieldAnd16 (
+ IN UINT16 Operand,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT16 AndData
+ );
+
+/**
+ Reads a bit field from a 16-bit value, performs a bitwise AND followed by a
+ bitwise OR, and returns the result.
+
+ Performs a bitwise AND between the bit field specified by StartBit and EndBit
+ in Operand and the value specified by AndData, followed by a bitwise
+ OR with value specified by OrData. All other bits in Operand are
+ preserved. The new 16-bit value is returned.
+
+ If 16-bit operations are not supported, then ASSERT().
+ If StartBit is greater than 15, then ASSERT().
+ If EndBit is greater than 15, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Operand Operand on which to perform the bitfield operation.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..15.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..15.
+ @param AndData The value to AND with the read value from the value.
+ @param OrData The value to OR with the result of the AND operation.
+
+ @return The new 16-bit value.
+
+**/
+UINT16
+EFIAPI
+BitFieldAndThenOr16 (
+ IN UINT16 Operand,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT16 AndData,
+ IN UINT16 OrData
+ );
+
+/**
+ Returns a bit field from a 32-bit value.
+
+ Returns the bitfield specified by the StartBit and the EndBit from Operand.
+
+ If 32-bit operations are not supported, then ASSERT().
+ If StartBit is greater than 31, then ASSERT().
+ If EndBit is greater than 31, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+
+ @param Operand Operand on which to perform the bitfield operation.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..31.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..31.
+
+ @return The bit field read.
+
+**/
+UINT32
+EFIAPI
+BitFieldRead32 (
+ IN UINT32 Operand,
+ IN UINTN StartBit,
+ IN UINTN EndBit
+ );
+
+/**
+ Writes a bit field to a 32-bit value, and returns the result.
+
+ Writes Value to the bit field specified by the StartBit and the EndBit in
+ Operand. All other bits in Operand are preserved. The new 32-bit value is
+ returned.
+
+ If 32-bit operations are not supported, then ASSERT().
+ If StartBit is greater than 31, then ASSERT().
+ If EndBit is greater than 31, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Operand Operand on which to perform the bitfield operation.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..31.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..31.
+ @param Value New value of the bit field.
+
+ @return The new 32-bit value.
+
+**/
+UINT32
+EFIAPI
+BitFieldWrite32 (
+ IN UINT32 Operand,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 Value
+ );
+
+/**
+ Reads a bit field from a 32-bit value, performs a bitwise OR, and returns the
+ result.
+
+ Performs a bitwise OR between the bit field specified by StartBit
+ and EndBit in Operand and the value specified by OrData. All other bits in
+ Operand are preserved. The new 32-bit value is returned.
+
+ If 32-bit operations are not supported, then ASSERT().
+ If StartBit is greater than 31, then ASSERT().
+ If EndBit is greater than 31, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Operand Operand on which to perform the bitfield operation.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..31.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..31.
+ @param OrData The value to OR with the read value from the value.
+
+ @return The new 32-bit value.
+
+**/
+UINT32
+EFIAPI
+BitFieldOr32 (
+ IN UINT32 Operand,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 OrData
+ );
+
+/**
+ Reads a bit field from a 32-bit value, performs a bitwise AND, and returns
+ the result.
+
+ Performs a bitwise AND between the bit field specified by StartBit and EndBit
+ in Operand and the value specified by AndData. All other bits in Operand are
+ preserved. The new 32-bit value is returned.
+
+ If 32-bit operations are not supported, then ASSERT().
+ If StartBit is greater than 31, then ASSERT().
+ If EndBit is greater than 31, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Operand Operand on which to perform the bitfield operation.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..31.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..31.
+ @param AndData The value to AND with the read value from the value
+
+ @return The new 32-bit value.
+
+**/
+UINT32
+EFIAPI
+BitFieldAnd32 (
+ IN UINT32 Operand,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 AndData
+ );
+
+/**
+ Reads a bit field from a 32-bit value, performs a bitwise AND followed by a
+ bitwise OR, and returns the result.
+
+ Performs a bitwise AND between the bit field specified by StartBit and EndBit
+ in Operand and the value specified by AndData, followed by a bitwise
+ OR with value specified by OrData. All other bits in Operand are
+ preserved. The new 32-bit value is returned.
+
+ If 32-bit operations are not supported, then ASSERT().
+ If StartBit is greater than 31, then ASSERT().
+ If EndBit is greater than 31, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Operand Operand on which to perform the bitfield operation.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..31.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..31.
+ @param AndData The value to AND with the read value from the value.
+ @param OrData The value to OR with the result of the AND operation.
+
+ @return The new 32-bit value.
+
+**/
+UINT32
+EFIAPI
+BitFieldAndThenOr32 (
+ IN UINT32 Operand,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 AndData,
+ IN UINT32 OrData
+ );
+
+/**
+ Returns a bit field from a 64-bit value.
+
+ Returns the bitfield specified by the StartBit and the EndBit from Operand.
+
+ If 64-bit operations are not supported, then ASSERT().
+ If StartBit is greater than 63, then ASSERT().
+ If EndBit is greater than 63, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+
+ @param Operand Operand on which to perform the bitfield operation.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..63.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..63.
+
+ @return The bit field read.
+
+**/
+UINT64
+EFIAPI
+BitFieldRead64 (
+ IN UINT64 Operand,
+ IN UINTN StartBit,
+ IN UINTN EndBit
+ );
+
+/**
+ Writes a bit field to a 64-bit value, and returns the result.
+
+ Writes Value to the bit field specified by the StartBit and the EndBit in
+ Operand. All other bits in Operand are preserved. The new 64-bit value is
+ returned.
+
+ If 64-bit operations are not supported, then ASSERT().
+ If StartBit is greater than 63, then ASSERT().
+ If EndBit is greater than 63, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Operand Operand on which to perform the bitfield operation.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..63.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..63.
+ @param Value New value of the bit field.
+
+ @return The new 64-bit value.
+
+**/
+UINT64
+EFIAPI
+BitFieldWrite64 (
+ IN UINT64 Operand,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT64 Value
+ );
+
+/**
+ Reads a bit field from a 64-bit value, performs a bitwise OR, and returns the
+ result.
+
+ Performs a bitwise OR between the bit field specified by StartBit
+ and EndBit in Operand and the value specified by OrData. All other bits in
+ Operand are preserved. The new 64-bit value is returned.
+
+ If 64-bit operations are not supported, then ASSERT().
+ If StartBit is greater than 63, then ASSERT().
+ If EndBit is greater than 63, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Operand Operand on which to perform the bitfield operation.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..63.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..63.
+ @param OrData The value to OR with the read value from the value
+
+ @return The new 64-bit value.
+
+**/
+UINT64
+EFIAPI
+BitFieldOr64 (
+ IN UINT64 Operand,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT64 OrData
+ );
+
+/**
+ Reads a bit field from a 64-bit value, performs a bitwise AND, and returns
+ the result.
+
+ Performs a bitwise AND between the bit field specified by StartBit and EndBit
+ in Operand and the value specified by AndData. All other bits in Operand are
+ preserved. The new 64-bit value is returned.
+
+ If 64-bit operations are not supported, then ASSERT().
+ If StartBit is greater than 63, then ASSERT().
+ If EndBit is greater than 63, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Operand Operand on which to perform the bitfield operation.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..63.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..63.
+ @param AndData The value to AND with the read value from the value
+
+ @return The new 64-bit value.
+
+**/
+UINT64
+EFIAPI
+BitFieldAnd64 (
+ IN UINT64 Operand,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT64 AndData
+ );
+
+/**
+ Reads a bit field from a 64-bit value, performs a bitwise AND followed by a
+ bitwise OR, and returns the result.
+
+ Performs a bitwise AND between the bit field specified by StartBit and EndBit
+ in Operand and the value specified by AndData, followed by a bitwise
+ OR with value specified by OrData. All other bits in Operand are
+ preserved. The new 64-bit value is returned.
+
+ If 64-bit operations are not supported, then ASSERT().
+ If StartBit is greater than 63, then ASSERT().
+ If EndBit is greater than 63, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Operand Operand on which to perform the bitfield operation.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..63.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..63.
+ @param AndData The value to AND with the read value from the value.
+ @param OrData The value to OR with the result of the AND operation.
+
+ @return The new 64-bit value.
+
+**/
+UINT64
+EFIAPI
+BitFieldAndThenOr64 (
+ IN UINT64 Operand,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT64 AndData,
+ IN UINT64 OrData
+ );
+
+/**
+ Reads a bit field from a 32-bit value, counts and returns
+ the number of set bits.
+
+ Counts the number of set bits in the bit field specified by
+ StartBit and EndBit in Operand. The count is returned.
+
+ If StartBit is greater than 31, then ASSERT().
+ If EndBit is greater than 31, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+
+ @param Operand Operand on which to perform the bitfield operation.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..31.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..31.
+
+ @return The number of bits set between StartBit and EndBit.
+
+**/
+UINT8
+EFIAPI
+BitFieldCountOnes32 (
+ IN UINT32 Operand,
+ IN UINTN StartBit,
+ IN UINTN EndBit
+ );
+
+/**
+ Reads a bit field from a 64-bit value, counts and returns
+ the number of set bits.
+
+ Counts the number of set bits in the bit field specified by
+ StartBit and EndBit in Operand. The count is returned.
+
+ If StartBit is greater than 63, then ASSERT().
+ If EndBit is greater than 63, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+
+ @param Operand Operand on which to perform the bitfield operation.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..63.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..63.
+
+ @return The number of bits set between StartBit and EndBit.
+
+**/
+UINT8
+EFIAPI
+BitFieldCountOnes64 (
+ IN UINT64 Operand,
+ IN UINTN StartBit,
+ IN UINTN EndBit
+ );
+
+//
+// Base Library Checksum Functions
+//
+
+/**
+ Returns the sum of all elements in a buffer in unit of UINT8.
+ During calculation, the carry bits are dropped.
+
+ This function calculates the sum of all elements in a buffer
+ in unit of UINT8. The carry bits in result of addition are dropped.
+ The result is returned as UINT8. If Length is Zero, then Zero is
+ returned.
+
+ If Buffer is NULL, then ASSERT().
+ If Length is greater than (MAX_ADDRESS - Buffer + 1), then ASSERT().
+
+ @param Buffer The pointer to the buffer to carry out the sum operation.
+ @param Length The size, in bytes, of Buffer.
+
+ @return Sum The sum of Buffer with carry bits dropped during additions.
+
+**/
+UINT8
+EFIAPI
+CalculateSum8 (
+ IN CONST UINT8 *Buffer,
+ IN UINTN Length
+ );
+
+/**
+ Returns the two's complement checksum of all elements in a buffer
+ of 8-bit values.
+
+ This function first calculates the sum of the 8-bit values in the
+ buffer specified by Buffer and Length. The carry bits in the result
+ of addition are dropped. Then, the two's complement of the sum is
+ returned. If Length is 0, then 0 is returned.
+
+ If Buffer is NULL, then ASSERT().
+ If Length is greater than (MAX_ADDRESS - Buffer + 1), then ASSERT().
+
+ @param Buffer The pointer to the buffer to carry out the checksum operation.
+ @param Length The size, in bytes, of Buffer.
+
+ @return Checksum The two's complement checksum of Buffer.
+
+**/
+UINT8
+EFIAPI
+CalculateCheckSum8 (
+ IN CONST UINT8 *Buffer,
+ IN UINTN Length
+ );
+
+/**
+ Returns the sum of all elements in a buffer of 16-bit values. During
+ calculation, the carry bits are dropped.
+
+ This function calculates the sum of the 16-bit values in the buffer
+ specified by Buffer and Length. The carry bits in result of addition are dropped.
+ The 16-bit result is returned. If Length is 0, then 0 is returned.
+
+ If Buffer is NULL, then ASSERT().
+ If Buffer is not aligned on a 16-bit boundary, then ASSERT().
+ If Length is not aligned on a 16-bit boundary, then ASSERT().
+ If Length is greater than (MAX_ADDRESS - Buffer + 1), then ASSERT().
+
+ @param Buffer The pointer to the buffer to carry out the sum operation.
+ @param Length The size, in bytes, of Buffer.
+
+ @return Sum The sum of Buffer with carry bits dropped during additions.
+
+**/
+UINT16
+EFIAPI
+CalculateSum16 (
+ IN CONST UINT16 *Buffer,
+ IN UINTN Length
+ );
+
+/**
+ Returns the two's complement checksum of all elements in a buffer of
+ 16-bit values.
+
+ This function first calculates the sum of the 16-bit values in the buffer
+ specified by Buffer and Length. The carry bits in the result of addition
+ are dropped. Then, the two's complement of the sum is returned. If Length
+ is 0, then 0 is returned.
+
+ If Buffer is NULL, then ASSERT().
+ If Buffer is not aligned on a 16-bit boundary, then ASSERT().
+ If Length is not aligned on a 16-bit boundary, then ASSERT().
+ If Length is greater than (MAX_ADDRESS - Buffer + 1), then ASSERT().
+
+ @param Buffer The pointer to the buffer to carry out the checksum operation.
+ @param Length The size, in bytes, of Buffer.
+
+ @return Checksum The two's complement checksum of Buffer.
+
+**/
+UINT16
+EFIAPI
+CalculateCheckSum16 (
+ IN CONST UINT16 *Buffer,
+ IN UINTN Length
+ );
+
+/**
+ Returns the sum of all elements in a buffer of 32-bit values. During
+ calculation, the carry bits are dropped.
+
+ This function calculates the sum of the 32-bit values in the buffer
+ specified by Buffer and Length. The carry bits in result of addition are dropped.
+ The 32-bit result is returned. If Length is 0, then 0 is returned.
+
+ If Buffer is NULL, then ASSERT().
+ If Buffer is not aligned on a 32-bit boundary, then ASSERT().
+ If Length is not aligned on a 32-bit boundary, then ASSERT().
+ If Length is greater than (MAX_ADDRESS - Buffer + 1), then ASSERT().
+
+ @param Buffer The pointer to the buffer to carry out the sum operation.
+ @param Length The size, in bytes, of Buffer.
+
+ @return Sum The sum of Buffer with carry bits dropped during additions.
+
+**/
+UINT32
+EFIAPI
+CalculateSum32 (
+ IN CONST UINT32 *Buffer,
+ IN UINTN Length
+ );
+
+/**
+ Returns the two's complement checksum of all elements in a buffer of
+ 32-bit values.
+
+ This function first calculates the sum of the 32-bit values in the buffer
+ specified by Buffer and Length. The carry bits in the result of addition
+ are dropped. Then, the two's complement of the sum is returned. If Length
+ is 0, then 0 is returned.
+
+ If Buffer is NULL, then ASSERT().
+ If Buffer is not aligned on a 32-bit boundary, then ASSERT().
+ If Length is not aligned on a 32-bit boundary, then ASSERT().
+ If Length is greater than (MAX_ADDRESS - Buffer + 1), then ASSERT().
+
+ @param Buffer The pointer to the buffer to carry out the checksum operation.
+ @param Length The size, in bytes, of Buffer.
+
+ @return Checksum The two's complement checksum of Buffer.
+
+**/
+UINT32
+EFIAPI
+CalculateCheckSum32 (
+ IN CONST UINT32 *Buffer,
+ IN UINTN Length
+ );
+
+/**
+ Returns the sum of all elements in a buffer of 64-bit values. During
+ calculation, the carry bits are dropped.
+
+ This function calculates the sum of the 64-bit values in the buffer
+ specified by Buffer and Length. The carry bits in result of addition are dropped.
+ The 64-bit result is returned. If Length is 0, then 0 is returned.
+
+ If Buffer is NULL, then ASSERT().
+ If Buffer is not aligned on a 64-bit boundary, then ASSERT().
+ If Length is not aligned on a 64-bit boundary, then ASSERT().
+ If Length is greater than (MAX_ADDRESS - Buffer + 1), then ASSERT().
+
+ @param Buffer The pointer to the buffer to carry out the sum operation.
+ @param Length The size, in bytes, of Buffer.
+
+ @return Sum The sum of Buffer with carry bits dropped during additions.
+
+**/
+UINT64
+EFIAPI
+CalculateSum64 (
+ IN CONST UINT64 *Buffer,
+ IN UINTN Length
+ );
+
+/**
+ Returns the two's complement checksum of all elements in a buffer of
+ 64-bit values.
+
+ This function first calculates the sum of the 64-bit values in the buffer
+ specified by Buffer and Length. The carry bits in the result of addition
+ are dropped. Then, the two's complement of the sum is returned. If Length
+ is 0, then 0 is returned.
+
+ If Buffer is NULL, then ASSERT().
+ If Buffer is not aligned on a 64-bit boundary, then ASSERT().
+ If Length is not aligned on a 64-bit boundary, then ASSERT().
+ If Length is greater than (MAX_ADDRESS - Buffer + 1), then ASSERT().
+
+ @param Buffer The pointer to the buffer to carry out the checksum operation.
+ @param Length The size, in bytes, of Buffer.
+
+ @return Checksum The two's complement checksum of Buffer.
+
+**/
+UINT64
+EFIAPI
+CalculateCheckSum64 (
+ IN CONST UINT64 *Buffer,
+ IN UINTN Length
+ );
+
+/**
+ Computes and returns a 32-bit CRC for a data buffer.
+ CRC32 value bases on ITU-T V.42.
+
+ If Buffer is NULL, then ASSERT().
+ If Length is greater than (MAX_ADDRESS - Buffer + 1), then ASSERT().
+
+ @param[in] Buffer A pointer to the buffer on which the 32-bit CRC is to be computed.
+ @param[in] Length The number of bytes in the buffer Data.
+
+ @retval Crc32 The 32-bit CRC was computed for the data buffer.
+
+**/
+UINT32
+EFIAPI
+CalculateCrc32 (
+ IN VOID *Buffer,
+ IN UINTN Length
+ );
+
+/**
+ Calculates the CRC16-ANSI checksum of the given buffer.
+
+ @param[in] Buffer Pointer to the buffer.
+ @param[in] Length Length of the buffer, in bytes.
+ @param[in] InitialValue Initial value of the CRC.
+
+ @return The CRC16-ANSI checksum.
+**/
+UINT16
+EFIAPI
+CalculateCrc16Ansi (
+ IN CONST VOID *Buffer,
+ IN UINTN Length,
+ IN UINT16 InitialValue
+ );
+
+/**
+ Calculates the CRC32c checksum of the given buffer.
+
+ @param[in] Buffer Pointer to the buffer.
+ @param[in] Length Length of the buffer, in bytes.
+ @param[in] InitialValue Initial value of the CRC.
+
+ @return The CRC32c checksum.
+**/
+UINT32
+EFIAPI
+CalculateCrc32c (
+ IN CONST VOID *Buffer,
+ IN UINTN Length,
+ IN UINT32 InitialValue
+ );
+
+//
+// Base Library CPU Functions
+//
+
+/**
+ Function entry point used when a stack switch is requested with SwitchStack()
+
+ @param Context1 Context1 parameter passed into SwitchStack().
+ @param Context2 Context2 parameter passed into SwitchStack().
+**/
+typedef
+VOID
+(EFIAPI *SWITCH_STACK_ENTRY_POINT)(
+ IN VOID *Context1 OPTIONAL,
+ IN VOID *Context2 OPTIONAL
+ );
+
+/**
+ Used to serialize load and store operations.
+
+ All loads and stores that proceed calls to this function are guaranteed to be
+ globally visible when this function returns.
+
+**/
+VOID
+EFIAPI
+MemoryFence (
+ VOID
+ );
+
+/**
+ Saves the current CPU context that can be restored with a call to LongJump()
+ and returns 0.
+
+ Saves the current CPU context in the buffer specified by JumpBuffer and
+ returns 0. The initial call to SetJump() must always return 0. Subsequent
+ calls to LongJump() cause a non-zero value to be returned by SetJump().
+
+ If JumpBuffer is NULL, then ASSERT().
+ For Itanium processors, if JumpBuffer is not aligned on a 16-byte boundary, then ASSERT().
+
+ NOTE: The structure BASE_LIBRARY_JUMP_BUFFER is CPU architecture specific.
+ The same structure must never be used for more than one CPU architecture context.
+ For example, a BASE_LIBRARY_JUMP_BUFFER allocated by an IA-32 module must never be used from an x64 module.
+ SetJump()/LongJump() is not currently supported for the EBC processor type.
+
+ @param JumpBuffer A pointer to CPU context buffer.
+
+ @retval 0 Indicates a return from SetJump().
+
+**/
+RETURNS_TWICE
+UINTN
+EFIAPI
+SetJump (
+ OUT BASE_LIBRARY_JUMP_BUFFER *JumpBuffer
+ );
+
+/**
+ Restores the CPU context that was saved with SetJump().
+
+ Restores the CPU context from the buffer specified by JumpBuffer. This
+ function never returns to the caller. Instead is resumes execution based on
+ the state of JumpBuffer.
+
+ If JumpBuffer is NULL, then ASSERT().
+ For Itanium processors, if JumpBuffer is not aligned on a 16-byte boundary, then ASSERT().
+ If Value is 0, then ASSERT().
+
+ @param JumpBuffer A pointer to CPU context buffer.
+ @param Value The value to return when the SetJump() context is
+ restored and must be non-zero.
+
+**/
+VOID
+EFIAPI
+LongJump (
+ IN BASE_LIBRARY_JUMP_BUFFER *JumpBuffer,
+ IN UINTN Value
+ );
+
+/**
+ Enables CPU interrupts.
+
+**/
+VOID
+EFIAPI
+EnableInterrupts (
+ VOID
+ );
+
+/**
+ Disables CPU interrupts.
+
+**/
+VOID
+EFIAPI
+DisableInterrupts (
+ VOID
+ );
+
+/**
+ Disables CPU interrupts and returns the interrupt state prior to the disable
+ operation.
+
+ @retval TRUE CPU interrupts were enabled on entry to this call.
+ @retval FALSE CPU interrupts were disabled on entry to this call.
+
+**/
+BOOLEAN
+EFIAPI
+SaveAndDisableInterrupts (
+ VOID
+ );
+
+/**
+ Enables CPU interrupts for the smallest window required to capture any
+ pending interrupts.
+
+**/
+VOID
+EFIAPI
+EnableDisableInterrupts (
+ VOID
+ );
+
+/**
+ Retrieves the current CPU interrupt state.
+
+ Returns TRUE if interrupts are currently enabled. Otherwise
+ returns FALSE.
+
+ @retval TRUE CPU interrupts are enabled.
+ @retval FALSE CPU interrupts are disabled.
+
+**/
+BOOLEAN
+EFIAPI
+GetInterruptState (
+ VOID
+ );
+
+/**
+ Set the current CPU interrupt state.
+
+ Sets the current CPU interrupt state to the state specified by
+ InterruptState. If InterruptState is TRUE, then interrupts are enabled. If
+ InterruptState is FALSE, then interrupts are disabled. InterruptState is
+ returned.
+
+ @param InterruptState TRUE if interrupts should enabled. FALSE if
+ interrupts should be disabled.
+
+ @return InterruptState
+
+**/
+BOOLEAN
+EFIAPI
+SetInterruptState (
+ IN BOOLEAN InterruptState
+ );
+
+/**
+ Requests CPU to pause for a short period of time.
+
+ Requests CPU to pause for a short period of time. Typically used in MP
+ systems to prevent memory starvation while waiting for a spin lock.
+
+**/
+VOID
+EFIAPI
+CpuPause (
+ VOID
+ );
+
+/**
+ Transfers control to a function starting with a new stack.
+
+ Transfers control to the function specified by EntryPoint using the
+ new stack specified by NewStack and passing in the parameters specified
+ by Context1 and Context2. Context1 and Context2 are optional and may
+ be NULL. The function EntryPoint must never return. This function
+ supports a variable number of arguments following the NewStack parameter.
+ These additional arguments are ignored on IA-32, x64, and EBC architectures.
+ Itanium processors expect one additional parameter of type VOID * that specifies
+ the new backing store pointer.
+
+ If EntryPoint is NULL, then ASSERT().
+ If NewStack is NULL, then ASSERT().
+
+ @param EntryPoint A pointer to function to call with the new stack.
+ @param Context1 A pointer to the context to pass into the EntryPoint
+ function.
+ @param Context2 A pointer to the context to pass into the EntryPoint
+ function.
+ @param NewStack A pointer to the new stack to use for the EntryPoint
+ function.
+ @param ... This variable argument list is ignored for IA-32, x64, and
+ EBC architectures. For Itanium processors, this variable
+ argument list is expected to contain a single parameter of
+ type VOID * that specifies the new backing store pointer.
+
+
+**/
+VOID
+EFIAPI
+SwitchStack (
+ IN SWITCH_STACK_ENTRY_POINT EntryPoint,
+ IN VOID *Context1 OPTIONAL,
+ IN VOID *Context2 OPTIONAL,
+ IN VOID *NewStack,
+ ...
+ );
+
+/**
+ Generates a breakpoint on the CPU.
+
+ Generates a breakpoint on the CPU. The breakpoint must be implemented such
+ that code can resume normal execution after the breakpoint.
+
+**/
+VOID
+EFIAPI
+CpuBreakpoint (
+ VOID
+ );
+
+/**
+ Executes an infinite loop.
+
+ Forces the CPU to execute an infinite loop. A debugger may be used to skip
+ past the loop and the code that follows the loop must execute properly. This
+ implies that the infinite loop must not cause the code that follow it to be
+ optimized away.
+
+**/
+VOID
+EFIAPI
+CpuDeadLoop (
+ VOID
+ );
+
+/**
+ Uses as a barrier to stop speculative execution.
+
+ Ensures that no later instruction will execute speculatively, until all prior
+ instructions have completed.
+
+**/
+VOID
+EFIAPI
+SpeculationBarrier (
+ VOID
+ );
+
+#if defined (MDE_CPU_X64) || defined (MDE_CPU_IA32)
+
+/**
+ The TDCALL instruction causes a VM exit to the Intel TDX module. It is
+ used to call guest-side Intel TDX functions, either local or a TD exit
+ to the host VMM, as selected by Leaf.
+
+ @param[in] Leaf Leaf number of TDCALL instruction
+ @param[in] Arg1 Arg1
+ @param[in] Arg2 Arg2
+ @param[in] Arg3 Arg3
+ @param[in,out] Results Returned result of the Leaf function
+
+ @return 0 A successful call
+ @return Other See individual leaf functions
+**/
+UINTN
+EFIAPI
+TdCall (
+ IN UINT64 Leaf,
+ IN UINT64 Arg1,
+ IN UINT64 Arg2,
+ IN UINT64 Arg3,
+ IN OUT VOID *Results
+ );
+
+/**
+ TDVMALL is a leaf function 0 for TDCALL. It helps invoke services from the
+ host VMM to pass/receive information.
+
+ @param[in] Leaf Number of sub-functions
+ @param[in] Arg1 Arg1
+ @param[in] Arg2 Arg2
+ @param[in] Arg3 Arg3
+ @param[in] Arg4 Arg4
+ @param[in,out] Results Returned result of the sub-function
+
+ @return 0 A successful call
+ @return Other See individual sub-functions
+
+**/
+UINTN
+EFIAPI
+TdVmCall (
+ IN UINT64 Leaf,
+ IN UINT64 Arg1,
+ IN UINT64 Arg2,
+ IN UINT64 Arg3,
+ IN UINT64 Arg4,
+ IN OUT VOID *Results
+ );
+
+/**
+ Probe if TD is enabled.
+
+ @return TRUE TD is enabled.
+ @return FALSE TD is not enabled.
+**/
+BOOLEAN
+EFIAPI
+TdIsEnabled (
+ VOID
+ );
+
+#endif
+
+#if defined (MDE_CPU_X64)
+//
+// The page size for the PVALIDATE instruction
+//
+typedef enum {
+ PvalidatePageSize4K = 0,
+ PvalidatePageSize2MB,
+} PVALIDATE_PAGE_SIZE;
+
+//
+// PVALIDATE Return Code.
+//
+#define PVALIDATE_RET_SUCCESS 0
+#define PVALIDATE_RET_FAIL_INPUT 1
+#define PVALIDATE_RET_SIZE_MISMATCH 6
+
+//
+// The PVALIDATE instruction did not make any changes to the RMP entry.
+//
+#define PVALIDATE_RET_NO_RMPUPDATE 255
+
+/**
+ Execute a PVALIDATE instruction to validate or to rescinds validation of a guest
+ page's RMP entry.
+
+ The instruction is available only when CPUID Fn8000_001F_EAX[SNP]=1.
+
+ The function is available on X64.
+
+ @param[in] PageSize The page size to use.
+ @param[in] Validate If TRUE, validate the guest virtual address
+ otherwise invalidate the guest virtual address.
+ @param[in] Address The guest virtual address.
+
+ @retval PVALIDATE_RET_SUCCESS The PVALIDATE instruction succeeded, and
+ updated the RMP entry.
+ @retval PVALIDATE_RET_NO_RMPUPDATE The PVALIDATE instruction succeeded, but
+ did not update the RMP entry.
+ @return Failure code from the PVALIDATE
+ instruction.
+**/
+UINT32
+EFIAPI
+AsmPvalidate (
+ IN PVALIDATE_PAGE_SIZE PageSize,
+ IN BOOLEAN Validate,
+ IN PHYSICAL_ADDRESS Address
+ );
+
+//
+// RDX settings for RMPADJUST
+//
+#define RMPADJUST_VMPL_MAX 3
+#define RMPADJUST_VMPL_MASK 0xFF
+#define RMPADJUST_VMPL_SHIFT 0
+#define RMPADJUST_PERMISSION_MASK_MASK 0xFF
+#define RMPADJUST_PERMISSION_MASK_SHIFT 8
+#define RMPADJUST_VMSA_PAGE_BIT BIT16
+
+/**
+ Adjusts the permissions of an SEV-SNP guest page.
+
+ Executes a RMPADJUST instruction with the register state specified by Rax,
+ Rcx, and Rdx. Returns Eax. This function is only available on X64.
+
+ The instruction is available only when CPUID Fn8000_001F_EAX[SNP]=1.
+
+ @param[in] Rax The value to load into RAX before executing the RMPADJUST
+ instruction.
+ @param[in] Rcx The value to load into RCX before executing the RMPADJUST
+ instruction.
+ @param[in] Rdx The value to load into RDX before executing the RMPADJUST
+ instruction.
+
+ @return Eax
+**/
+UINT32
+EFIAPI
+AsmRmpAdjust (
+ IN UINT64 Rax,
+ IN UINT64 Rcx,
+ IN UINT64 Rdx
+ );
+
+#endif
+
+#if defined (MDE_CPU_IA32) || defined (MDE_CPU_X64)
+///
+/// IA32 and x64 Specific Functions.
+/// Byte packed structure for 16-bit Real Mode EFLAGS.
+///
+typedef union {
+ struct {
+ UINT32 CF : 1; ///< Carry Flag.
+ UINT32 Reserved_0 : 1; ///< Reserved.
+ UINT32 PF : 1; ///< Parity Flag.
+ UINT32 Reserved_1 : 1; ///< Reserved.
+ UINT32 AF : 1; ///< Auxiliary Carry Flag.
+ UINT32 Reserved_2 : 1; ///< Reserved.
+ UINT32 ZF : 1; ///< Zero Flag.
+ UINT32 SF : 1; ///< Sign Flag.
+ UINT32 TF : 1; ///< Trap Flag.
+ UINT32 IF : 1; ///< Interrupt Enable Flag.
+ UINT32 DF : 1; ///< Direction Flag.
+ UINT32 OF : 1; ///< Overflow Flag.
+ UINT32 IOPL : 2; ///< I/O Privilege Level.
+ UINT32 NT : 1; ///< Nested Task.
+ UINT32 Reserved_3 : 1; ///< Reserved.
+ } Bits;
+ UINT16 Uint16;
+} IA32_FLAGS16;
+
+///
+/// Byte packed structure for EFLAGS/RFLAGS.
+/// 32-bits on IA-32.
+/// 64-bits on x64. The upper 32-bits on x64 are reserved.
+///
+typedef union {
+ struct {
+ UINT32 CF : 1; ///< Carry Flag.
+ UINT32 Reserved_0 : 1; ///< Reserved.
+ UINT32 PF : 1; ///< Parity Flag.
+ UINT32 Reserved_1 : 1; ///< Reserved.
+ UINT32 AF : 1; ///< Auxiliary Carry Flag.
+ UINT32 Reserved_2 : 1; ///< Reserved.
+ UINT32 ZF : 1; ///< Zero Flag.
+ UINT32 SF : 1; ///< Sign Flag.
+ UINT32 TF : 1; ///< Trap Flag.
+ UINT32 IF : 1; ///< Interrupt Enable Flag.
+ UINT32 DF : 1; ///< Direction Flag.
+ UINT32 OF : 1; ///< Overflow Flag.
+ UINT32 IOPL : 2; ///< I/O Privilege Level.
+ UINT32 NT : 1; ///< Nested Task.
+ UINT32 Reserved_3 : 1; ///< Reserved.
+ UINT32 RF : 1; ///< Resume Flag.
+ UINT32 VM : 1; ///< Virtual 8086 Mode.
+ UINT32 AC : 1; ///< Alignment Check.
+ UINT32 VIF : 1; ///< Virtual Interrupt Flag.
+ UINT32 VIP : 1; ///< Virtual Interrupt Pending.
+ UINT32 ID : 1; ///< ID Flag.
+ UINT32 Reserved_4 : 10; ///< Reserved.
+ } Bits;
+ UINTN UintN;
+} IA32_EFLAGS32;
+
+///
+/// Byte packed structure for Control Register 0 (CR0).
+/// 32-bits on IA-32.
+/// 64-bits on x64. The upper 32-bits on x64 are reserved.
+///
+typedef union {
+ struct {
+ UINT32 PE : 1; ///< Protection Enable.
+ UINT32 MP : 1; ///< Monitor Coprocessor.
+ UINT32 EM : 1; ///< Emulation.
+ UINT32 TS : 1; ///< Task Switched.
+ UINT32 ET : 1; ///< Extension Type.
+ UINT32 NE : 1; ///< Numeric Error.
+ UINT32 Reserved_0 : 10; ///< Reserved.
+ UINT32 WP : 1; ///< Write Protect.
+ UINT32 Reserved_1 : 1; ///< Reserved.
+ UINT32 AM : 1; ///< Alignment Mask.
+ UINT32 Reserved_2 : 10; ///< Reserved.
+ UINT32 NW : 1; ///< Mot Write-through.
+ UINT32 CD : 1; ///< Cache Disable.
+ UINT32 PG : 1; ///< Paging.
+ } Bits;
+ UINTN UintN;
+} IA32_CR0;
+
+///
+/// Byte packed structure for Control Register 4 (CR4).
+/// 32-bits on IA-32.
+/// 64-bits on x64. The upper 32-bits on x64 are reserved.
+///
+typedef union {
+ struct {
+ UINT32 VME : 1; ///< Virtual-8086 Mode Extensions.
+ UINT32 PVI : 1; ///< Protected-Mode Virtual Interrupts.
+ UINT32 TSD : 1; ///< Time Stamp Disable.
+ UINT32 DE : 1; ///< Debugging Extensions.
+ UINT32 PSE : 1; ///< Page Size Extensions.
+ UINT32 PAE : 1; ///< Physical Address Extension.
+ UINT32 MCE : 1; ///< Machine Check Enable.
+ UINT32 PGE : 1; ///< Page Global Enable.
+ UINT32 PCE : 1; ///< Performance Monitoring Counter
+ ///< Enable.
+ UINT32 OSFXSR : 1; ///< Operating System Support for
+ ///< FXSAVE and FXRSTOR instructions
+ UINT32 OSXMMEXCPT : 1; ///< Operating System Support for
+ ///< Unmasked SIMD Floating Point
+ ///< Exceptions.
+ UINT32 UMIP : 1; ///< User-Mode Instruction Prevention.
+ UINT32 LA57 : 1; ///< Linear Address 57bit.
+ UINT32 VMXE : 1; ///< VMX Enable.
+ UINT32 SMXE : 1; ///< SMX Enable.
+ UINT32 Reserved_3 : 1; ///< Reserved.
+ UINT32 FSGSBASE : 1; ///< FSGSBASE Enable.
+ UINT32 PCIDE : 1; ///< PCID Enable.
+ UINT32 OSXSAVE : 1; ///< XSAVE and Processor Extended States Enable.
+ UINT32 Reserved_4 : 1; ///< Reserved.
+ UINT32 SMEP : 1; ///< SMEP Enable.
+ UINT32 SMAP : 1; ///< SMAP Enable.
+ UINT32 PKE : 1; ///< Protection-Key Enable.
+ UINT32 Reserved_5 : 9; ///< Reserved.
+ } Bits;
+ UINTN UintN;
+} IA32_CR4;
+
+///
+/// Byte packed structure for a segment descriptor in a GDT/LDT.
+///
+typedef union {
+ struct {
+ UINT32 LimitLow : 16;
+ UINT32 BaseLow : 16;
+ UINT32 BaseMid : 8;
+ UINT32 Type : 4;
+ UINT32 S : 1;
+ UINT32 DPL : 2;
+ UINT32 P : 1;
+ UINT32 LimitHigh : 4;
+ UINT32 AVL : 1;
+ UINT32 L : 1;
+ UINT32 DB : 1;
+ UINT32 G : 1;
+ UINT32 BaseHigh : 8;
+ } Bits;
+ UINT64 Uint64;
+} IA32_SEGMENT_DESCRIPTOR;
+
+///
+/// Byte packed structure for an IDTR, GDTR, LDTR descriptor.
+///
+ #pragma pack (1)
+typedef struct {
+ UINT16 Limit;
+ UINTN Base;
+} IA32_DESCRIPTOR;
+ #pragma pack ()
+
+#define IA32_IDT_GATE_TYPE_TASK 0x85
+#define IA32_IDT_GATE_TYPE_INTERRUPT_16 0x86
+#define IA32_IDT_GATE_TYPE_TRAP_16 0x87
+#define IA32_IDT_GATE_TYPE_INTERRUPT_32 0x8E
+#define IA32_IDT_GATE_TYPE_TRAP_32 0x8F
+
+#define IA32_GDT_TYPE_TSS 0x9
+#define IA32_GDT_ALIGNMENT 8
+
+ #if defined (MDE_CPU_IA32)
+///
+/// Byte packed structure for an IA-32 Interrupt Gate Descriptor.
+///
+typedef union {
+ struct {
+ UINT32 OffsetLow : 16; ///< Offset bits 15..0.
+ UINT32 Selector : 16; ///< Selector.
+ UINT32 Reserved_0 : 8; ///< Reserved.
+ UINT32 GateType : 8; ///< Gate Type. See #defines above.
+ UINT32 OffsetHigh : 16; ///< Offset bits 31..16.
+ } Bits;
+ UINT64 Uint64;
+} IA32_IDT_GATE_DESCRIPTOR;
+
+ #pragma pack (1)
+//
+// IA32 Task-State Segment Definition
+//
+typedef struct {
+ UINT16 PreviousTaskLink;
+ UINT16 Reserved_2;
+ UINT32 ESP0;
+ UINT16 SS0;
+ UINT16 Reserved_10;
+ UINT32 ESP1;
+ UINT16 SS1;
+ UINT16 Reserved_18;
+ UINT32 ESP2;
+ UINT16 SS2;
+ UINT16 Reserved_26;
+ UINT32 CR3;
+ UINT32 EIP;
+ UINT32 EFLAGS;
+ UINT32 EAX;
+ UINT32 ECX;
+ UINT32 EDX;
+ UINT32 EBX;
+ UINT32 ESP;
+ UINT32 EBP;
+ UINT32 ESI;
+ UINT32 EDI;
+ UINT16 ES;
+ UINT16 Reserved_74;
+ UINT16 CS;
+ UINT16 Reserved_78;
+ UINT16 SS;
+ UINT16 Reserved_82;
+ UINT16 DS;
+ UINT16 Reserved_86;
+ UINT16 FS;
+ UINT16 Reserved_90;
+ UINT16 GS;
+ UINT16 Reserved_94;
+ UINT16 LDTSegmentSelector;
+ UINT16 Reserved_98;
+ UINT16 T;
+ UINT16 IOMapBaseAddress;
+} IA32_TASK_STATE_SEGMENT;
+
+typedef union {
+ struct {
+ UINT32 LimitLow : 16; ///< Segment Limit 15..00
+ UINT32 BaseLow : 16; ///< Base Address 15..00
+ UINT32 BaseMid : 8; ///< Base Address 23..16
+ UINT32 Type : 4; ///< Type (1 0 B 1)
+ UINT32 Reserved_43 : 1; ///< 0
+ UINT32 DPL : 2; ///< Descriptor Privilege Level
+ UINT32 P : 1; ///< Segment Present
+ UINT32 LimitHigh : 4; ///< Segment Limit 19..16
+ UINT32 AVL : 1; ///< Available for use by system software
+ UINT32 Reserved_52 : 2; ///< 0 0
+ UINT32 G : 1; ///< Granularity
+ UINT32 BaseHigh : 8; ///< Base Address 31..24
+ } Bits;
+ UINT64 Uint64;
+} IA32_TSS_DESCRIPTOR;
+ #pragma pack ()
+
+ #endif // defined (MDE_CPU_IA32)
+
+ #if defined (MDE_CPU_X64)
+///
+/// Byte packed structure for an x64 Interrupt Gate Descriptor.
+///
+typedef union {
+ struct {
+ UINT32 OffsetLow : 16; ///< Offset bits 15..0.
+ UINT32 Selector : 16; ///< Selector.
+ UINT32 Reserved_0 : 8; ///< Reserved.
+ UINT32 GateType : 8; ///< Gate Type. See #defines above.
+ UINT32 OffsetHigh : 16; ///< Offset bits 31..16.
+ UINT32 OffsetUpper : 32; ///< Offset bits 63..32.
+ UINT32 Reserved_1 : 32; ///< Reserved.
+ } Bits;
+ struct {
+ UINT64 Uint64;
+ UINT64 Uint64_1;
+ } Uint128;
+} IA32_IDT_GATE_DESCRIPTOR;
+
+ #pragma pack (1)
+//
+// IA32 Task-State Segment Definition
+//
+typedef struct {
+ UINT32 Reserved_0;
+ UINT64 RSP0;
+ UINT64 RSP1;
+ UINT64 RSP2;
+ UINT64 Reserved_28;
+ UINT64 IST[7];
+ UINT64 Reserved_92;
+ UINT16 Reserved_100;
+ UINT16 IOMapBaseAddress;
+} IA32_TASK_STATE_SEGMENT;
+
+typedef union {
+ struct {
+ UINT32 LimitLow : 16; ///< Segment Limit 15..00
+ UINT32 BaseLow : 16; ///< Base Address 15..00
+ UINT32 BaseMidl : 8; ///< Base Address 23..16
+ UINT32 Type : 4; ///< Type (1 0 B 1)
+ UINT32 Reserved_43 : 1; ///< 0
+ UINT32 DPL : 2; ///< Descriptor Privilege Level
+ UINT32 P : 1; ///< Segment Present
+ UINT32 LimitHigh : 4; ///< Segment Limit 19..16
+ UINT32 AVL : 1; ///< Available for use by system software
+ UINT32 Reserved_52 : 2; ///< 0 0
+ UINT32 G : 1; ///< Granularity
+ UINT32 BaseMidh : 8; ///< Base Address 31..24
+ UINT32 BaseHigh : 32; ///< Base Address 63..32
+ UINT32 Reserved_96 : 32; ///< Reserved
+ } Bits;
+ struct {
+ UINT64 Uint64;
+ UINT64 Uint64_1;
+ } Uint128;
+} IA32_TSS_DESCRIPTOR;
+ #pragma pack ()
+
+ #endif // defined (MDE_CPU_X64)
+
+///
+/// Byte packed structure for an FP/SSE/SSE2 context.
+///
+typedef struct {
+ UINT8 Buffer[512];
+} IA32_FX_BUFFER;
+
+///
+/// Structures for the 16-bit real mode thunks.
+///
+typedef struct {
+ UINT32 Reserved1;
+ UINT32 Reserved2;
+ UINT32 Reserved3;
+ UINT32 Reserved4;
+ UINT8 BL;
+ UINT8 BH;
+ UINT16 Reserved5;
+ UINT8 DL;
+ UINT8 DH;
+ UINT16 Reserved6;
+ UINT8 CL;
+ UINT8 CH;
+ UINT16 Reserved7;
+ UINT8 AL;
+ UINT8 AH;
+ UINT16 Reserved8;
+} IA32_BYTE_REGS;
+
+typedef struct {
+ UINT16 DI;
+ UINT16 Reserved1;
+ UINT16 SI;
+ UINT16 Reserved2;
+ UINT16 BP;
+ UINT16 Reserved3;
+ UINT16 SP;
+ UINT16 Reserved4;
+ UINT16 BX;
+ UINT16 Reserved5;
+ UINT16 DX;
+ UINT16 Reserved6;
+ UINT16 CX;
+ UINT16 Reserved7;
+ UINT16 AX;
+ UINT16 Reserved8;
+} IA32_WORD_REGS;
+
+typedef struct {
+ UINT32 EDI;
+ UINT32 ESI;
+ UINT32 EBP;
+ UINT32 ESP;
+ UINT32 EBX;
+ UINT32 EDX;
+ UINT32 ECX;
+ UINT32 EAX;
+ UINT16 DS;
+ UINT16 ES;
+ UINT16 FS;
+ UINT16 GS;
+ IA32_EFLAGS32 EFLAGS;
+ UINT32 Eip;
+ UINT16 CS;
+ UINT16 SS;
+} IA32_DWORD_REGS;
+
+typedef union {
+ IA32_DWORD_REGS E;
+ IA32_WORD_REGS X;
+ IA32_BYTE_REGS H;
+} IA32_REGISTER_SET;
+
+///
+/// Byte packed structure for an 16-bit real mode thunks.
+///
+typedef struct {
+ IA32_REGISTER_SET *RealModeState;
+ VOID *RealModeBuffer;
+ UINT32 RealModeBufferSize;
+ UINT32 ThunkAttributes;
+} THUNK_CONTEXT;
+
+#define THUNK_ATTRIBUTE_BIG_REAL_MODE 0x00000001
+#define THUNK_ATTRIBUTE_DISABLE_A20_MASK_INT_15 0x00000002
+#define THUNK_ATTRIBUTE_DISABLE_A20_MASK_KBD_CTRL 0x00000004
+
+///
+/// Type definition for representing labels in NASM source code that allow for
+/// the patching of immediate operands of IA32 and X64 instructions.
+///
+/// While the type is technically defined as a function type (note: not a
+/// pointer-to-function type), such labels in NASM source code never stand for
+/// actual functions, and identifiers declared with this function type should
+/// never be called. This is also why the EFIAPI calling convention specifier
+/// is missing from the typedef, and why the typedef does not follow the usual
+/// edk2 coding style for function (or pointer-to-function) typedefs. The VOID
+/// return type and the VOID argument list are merely artifacts.
+///
+typedef VOID (X86_ASSEMBLY_PATCH_LABEL) (
+ VOID
+ );
+
+/**
+ Retrieves CPUID information.
+
+ Executes the CPUID instruction with EAX set to the value specified by Index.
+ This function always returns Index.
+ If Eax is not NULL, then the value of EAX after CPUID is returned in Eax.
+ If Ebx is not NULL, then the value of EBX after CPUID is returned in Ebx.
+ If Ecx is not NULL, then the value of ECX after CPUID is returned in Ecx.
+ If Edx is not NULL, then the value of EDX after CPUID is returned in Edx.
+ This function is only available on IA-32 and x64.
+
+ @param Index The 32-bit value to load into EAX prior to invoking the CPUID
+ instruction.
+ @param Eax The pointer to the 32-bit EAX value returned by the CPUID
+ instruction. This is an optional parameter that may be NULL.
+ @param Ebx The pointer to the 32-bit EBX value returned by the CPUID
+ instruction. This is an optional parameter that may be NULL.
+ @param Ecx The pointer to the 32-bit ECX value returned by the CPUID
+ instruction. This is an optional parameter that may be NULL.
+ @param Edx The pointer to the 32-bit EDX value returned by the CPUID
+ instruction. This is an optional parameter that may be NULL.
+
+ @return Index.
+
+**/
+UINT32
+EFIAPI
+AsmCpuid (
+ IN UINT32 Index,
+ OUT UINT32 *Eax OPTIONAL,
+ OUT UINT32 *Ebx OPTIONAL,
+ OUT UINT32 *Ecx OPTIONAL,
+ OUT UINT32 *Edx OPTIONAL
+ );
+
+/**
+ Retrieves CPUID information using an extended leaf identifier.
+
+ Executes the CPUID instruction with EAX set to the value specified by Index
+ and ECX set to the value specified by SubIndex. This function always returns
+ Index. This function is only available on IA-32 and x64.
+
+ If Eax is not NULL, then the value of EAX after CPUID is returned in Eax.
+ If Ebx is not NULL, then the value of EBX after CPUID is returned in Ebx.
+ If Ecx is not NULL, then the value of ECX after CPUID is returned in Ecx.
+ If Edx is not NULL, then the value of EDX after CPUID is returned in Edx.
+
+ @param Index The 32-bit value to load into EAX prior to invoking the
+ CPUID instruction.
+ @param SubIndex The 32-bit value to load into ECX prior to invoking the
+ CPUID instruction.
+ @param Eax The pointer to the 32-bit EAX value returned by the CPUID
+ instruction. This is an optional parameter that may be
+ NULL.
+ @param Ebx The pointer to the 32-bit EBX value returned by the CPUID
+ instruction. This is an optional parameter that may be
+ NULL.
+ @param Ecx The pointer to the 32-bit ECX value returned by the CPUID
+ instruction. This is an optional parameter that may be
+ NULL.
+ @param Edx The pointer to the 32-bit EDX value returned by the CPUID
+ instruction. This is an optional parameter that may be
+ NULL.
+
+ @return Index.
+
+**/
+UINT32
+EFIAPI
+AsmCpuidEx (
+ IN UINT32 Index,
+ IN UINT32 SubIndex,
+ OUT UINT32 *Eax OPTIONAL,
+ OUT UINT32 *Ebx OPTIONAL,
+ OUT UINT32 *Ecx OPTIONAL,
+ OUT UINT32 *Edx OPTIONAL
+ );
+
+/**
+ Set CD bit and clear NW bit of CR0 followed by a WBINVD.
+
+ Disables the caches by setting the CD bit of CR0 to 1, clearing the NW bit of CR0 to 0,
+ and executing a WBINVD instruction. This function is only available on IA-32 and x64.
+
+**/
+VOID
+EFIAPI
+AsmDisableCache (
+ VOID
+ );
+
+/**
+ Perform a WBINVD and clear both the CD and NW bits of CR0.
+
+ Enables the caches by executing a WBINVD instruction and then clear both the CD and NW
+ bits of CR0 to 0. This function is only available on IA-32 and x64.
+
+**/
+VOID
+EFIAPI
+AsmEnableCache (
+ VOID
+ );
+
+/**
+ Returns the lower 32-bits of a Machine Specific Register(MSR).
+
+ Reads and returns the lower 32-bits of the MSR specified by Index.
+ No parameter checking is performed on Index, and some Index values may cause
+ CPU exceptions. The caller must either guarantee that Index is valid, or the
+ caller must set up exception handlers to catch the exceptions. This function
+ is only available on IA-32 and x64.
+
+ @param Index The 32-bit MSR index to read.
+
+ @return The lower 32 bits of the MSR identified by Index.
+
+**/
+UINT32
+EFIAPI
+AsmReadMsr32 (
+ IN UINT32 Index
+ );
+
+/**
+ Writes a 32-bit value to a Machine Specific Register(MSR), and returns the value.
+ The upper 32-bits of the MSR are set to zero.
+
+ Writes the 32-bit value specified by Value to the MSR specified by Index. The
+ upper 32-bits of the MSR write are set to zero. The 32-bit value written to
+ the MSR is returned. No parameter checking is performed on Index or Value,
+ and some of these may cause CPU exceptions. The caller must either guarantee
+ that Index and Value are valid, or the caller must establish proper exception
+ handlers. This function is only available on IA-32 and x64.
+
+ @param Index The 32-bit MSR index to write.
+ @param Value The 32-bit value to write to the MSR.
+
+ @return Value
+
+**/
+UINT32
+EFIAPI
+AsmWriteMsr32 (
+ IN UINT32 Index,
+ IN UINT32 Value
+ );
+
+/**
+ Reads a 64-bit MSR, performs a bitwise OR on the lower 32-bits, and
+ writes the result back to the 64-bit MSR.
+
+ Reads the 64-bit MSR specified by Index, performs a bitwise OR
+ between the lower 32-bits of the read result and the value specified by
+ OrData, and writes the result to the 64-bit MSR specified by Index. The lower
+ 32-bits of the value written to the MSR is returned. No parameter checking is
+ performed on Index or OrData, and some of these may cause CPU exceptions. The
+ caller must either guarantee that Index and OrData are valid, or the caller
+ must establish proper exception handlers. This function is only available on
+ IA-32 and x64.
+
+ @param Index The 32-bit MSR index to write.
+ @param OrData The value to OR with the read value from the MSR.
+
+ @return The lower 32-bit value written to the MSR.
+
+**/
+UINT32
+EFIAPI
+AsmMsrOr32 (
+ IN UINT32 Index,
+ IN UINT32 OrData
+ );
+
+/**
+ Reads a 64-bit MSR, performs a bitwise AND on the lower 32-bits, and writes
+ the result back to the 64-bit MSR.
+
+ Reads the 64-bit MSR specified by Index, performs a bitwise AND between the
+ lower 32-bits of the read result and the value specified by AndData, and
+ writes the result to the 64-bit MSR specified by Index. The lower 32-bits of
+ the value written to the MSR is returned. No parameter checking is performed
+ on Index or AndData, and some of these may cause CPU exceptions. The caller
+ must either guarantee that Index and AndData are valid, or the caller must
+ establish proper exception handlers. This function is only available on IA-32
+ and x64.
+
+ @param Index The 32-bit MSR index to write.
+ @param AndData The value to AND with the read value from the MSR.
+
+ @return The lower 32-bit value written to the MSR.
+
+**/
+UINT32
+EFIAPI
+AsmMsrAnd32 (
+ IN UINT32 Index,
+ IN UINT32 AndData
+ );
+
+/**
+ Reads a 64-bit MSR, performs a bitwise AND followed by a bitwise OR
+ on the lower 32-bits, and writes the result back to the 64-bit MSR.
+
+ Reads the 64-bit MSR specified by Index, performs a bitwise AND between the
+ lower 32-bits of the read result and the value specified by AndData
+ preserving the upper 32-bits, performs a bitwise OR between the
+ result of the AND operation and the value specified by OrData, and writes the
+ result to the 64-bit MSR specified by Address. The lower 32-bits of the value
+ written to the MSR is returned. No parameter checking is performed on Index,
+ AndData, or OrData, and some of these may cause CPU exceptions. The caller
+ must either guarantee that Index, AndData, and OrData are valid, or the
+ caller must establish proper exception handlers. This function is only
+ available on IA-32 and x64.
+
+ @param Index The 32-bit MSR index to write.
+ @param AndData The value to AND with the read value from the MSR.
+ @param OrData The value to OR with the result of the AND operation.
+
+ @return The lower 32-bit value written to the MSR.
+
+**/
+UINT32
+EFIAPI
+AsmMsrAndThenOr32 (
+ IN UINT32 Index,
+ IN UINT32 AndData,
+ IN UINT32 OrData
+ );
+
+/**
+ Reads a bit field of an MSR.
+
+ Reads the bit field in the lower 32-bits of a 64-bit MSR. The bit field is
+ specified by the StartBit and the EndBit. The value of the bit field is
+ returned. The caller must either guarantee that Index is valid, or the caller
+ must set up exception handlers to catch the exceptions. This function is only
+ available on IA-32 and x64.
+
+ If StartBit is greater than 31, then ASSERT().
+ If EndBit is greater than 31, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+
+ @param Index The 32-bit MSR index to read.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..31.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..31.
+
+ @return The bit field read from the MSR.
+
+**/
+UINT32
+EFIAPI
+AsmMsrBitFieldRead32 (
+ IN UINT32 Index,
+ IN UINTN StartBit,
+ IN UINTN EndBit
+ );
+
+/**
+ Writes a bit field to an MSR.
+
+ Writes Value to a bit field in the lower 32-bits of a 64-bit MSR. The bit
+ field is specified by the StartBit and the EndBit. All other bits in the
+ destination MSR are preserved. The lower 32-bits of the MSR written is
+ returned. The caller must either guarantee that Index and the data written
+ is valid, or the caller must set up exception handlers to catch the exceptions.
+ This function is only available on IA-32 and x64.
+
+ If StartBit is greater than 31, then ASSERT().
+ If EndBit is greater than 31, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Index The 32-bit MSR index to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..31.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..31.
+ @param Value New value of the bit field.
+
+ @return The lower 32-bit of the value written to the MSR.
+
+**/
+UINT32
+EFIAPI
+AsmMsrBitFieldWrite32 (
+ IN UINT32 Index,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 Value
+ );
+
+/**
+ Reads a bit field in a 64-bit MSR, performs a bitwise OR, and writes the
+ result back to the bit field in the 64-bit MSR.
+
+ Reads the 64-bit MSR specified by Index, performs a bitwise OR
+ between the read result and the value specified by OrData, and writes the
+ result to the 64-bit MSR specified by Index. The lower 32-bits of the value
+ written to the MSR are returned. Extra left bits in OrData are stripped. The
+ caller must either guarantee that Index and the data written is valid, or
+ the caller must set up exception handlers to catch the exceptions. This
+ function is only available on IA-32 and x64.
+
+ If StartBit is greater than 31, then ASSERT().
+ If EndBit is greater than 31, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Index The 32-bit MSR index to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..31.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..31.
+ @param OrData The value to OR with the read value from the MSR.
+
+ @return The lower 32-bit of the value written to the MSR.
+
+**/
+UINT32
+EFIAPI
+AsmMsrBitFieldOr32 (
+ IN UINT32 Index,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 OrData
+ );
+
+/**
+ Reads a bit field in a 64-bit MSR, performs a bitwise AND, and writes the
+ result back to the bit field in the 64-bit MSR.
+
+ Reads the 64-bit MSR specified by Index, performs a bitwise AND between the
+ read result and the value specified by AndData, and writes the result to the
+ 64-bit MSR specified by Index. The lower 32-bits of the value written to the
+ MSR are returned. Extra left bits in AndData are stripped. The caller must
+ either guarantee that Index and the data written is valid, or the caller must
+ set up exception handlers to catch the exceptions. This function is only
+ available on IA-32 and x64.
+
+ If StartBit is greater than 31, then ASSERT().
+ If EndBit is greater than 31, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Index The 32-bit MSR index to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..31.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..31.
+ @param AndData The value to AND with the read value from the MSR.
+
+ @return The lower 32-bit of the value written to the MSR.
+
+**/
+UINT32
+EFIAPI
+AsmMsrBitFieldAnd32 (
+ IN UINT32 Index,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 AndData
+ );
+
+/**
+ Reads a bit field in a 64-bit MSR, performs a bitwise AND followed by a
+ bitwise OR, and writes the result back to the bit field in the
+ 64-bit MSR.
+
+ Reads the 64-bit MSR specified by Index, performs a bitwise AND followed by a
+ bitwise OR between the read result and the value specified by
+ AndData, and writes the result to the 64-bit MSR specified by Index. The
+ lower 32-bits of the value written to the MSR are returned. Extra left bits
+ in both AndData and OrData are stripped. The caller must either guarantee
+ that Index and the data written is valid, or the caller must set up exception
+ handlers to catch the exceptions. This function is only available on IA-32
+ and x64.
+
+ If StartBit is greater than 31, then ASSERT().
+ If EndBit is greater than 31, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Index The 32-bit MSR index to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..31.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..31.
+ @param AndData The value to AND with the read value from the MSR.
+ @param OrData The value to OR with the result of the AND operation.
+
+ @return The lower 32-bit of the value written to the MSR.
+
+**/
+UINT32
+EFIAPI
+AsmMsrBitFieldAndThenOr32 (
+ IN UINT32 Index,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 AndData,
+ IN UINT32 OrData
+ );
+
+/**
+ Returns a 64-bit Machine Specific Register(MSR).
+
+ Reads and returns the 64-bit MSR specified by Index. No parameter checking is
+ performed on Index, and some Index values may cause CPU exceptions. The
+ caller must either guarantee that Index is valid, or the caller must set up
+ exception handlers to catch the exceptions. This function is only available
+ on IA-32 and x64.
+
+ @param Index The 32-bit MSR index to read.
+
+ @return The value of the MSR identified by Index.
+
+**/
+UINT64
+EFIAPI
+AsmReadMsr64 (
+ IN UINT32 Index
+ );
+
+/**
+ Writes a 64-bit value to a Machine Specific Register(MSR), and returns the
+ value.
+
+ Writes the 64-bit value specified by Value to the MSR specified by Index. The
+ 64-bit value written to the MSR is returned. No parameter checking is
+ performed on Index or Value, and some of these may cause CPU exceptions. The
+ caller must either guarantee that Index and Value are valid, or the caller
+ must establish proper exception handlers. This function is only available on
+ IA-32 and x64.
+
+ @param Index The 32-bit MSR index to write.
+ @param Value The 64-bit value to write to the MSR.
+
+ @return Value
+
+**/
+UINT64
+EFIAPI
+AsmWriteMsr64 (
+ IN UINT32 Index,
+ IN UINT64 Value
+ );
+
+/**
+ Reads a 64-bit MSR, performs a bitwise OR, and writes the result
+ back to the 64-bit MSR.
+
+ Reads the 64-bit MSR specified by Index, performs a bitwise OR
+ between the read result and the value specified by OrData, and writes the
+ result to the 64-bit MSR specified by Index. The value written to the MSR is
+ returned. No parameter checking is performed on Index or OrData, and some of
+ these may cause CPU exceptions. The caller must either guarantee that Index
+ and OrData are valid, or the caller must establish proper exception handlers.
+ This function is only available on IA-32 and x64.
+
+ @param Index The 32-bit MSR index to write.
+ @param OrData The value to OR with the read value from the MSR.
+
+ @return The value written back to the MSR.
+
+**/
+UINT64
+EFIAPI
+AsmMsrOr64 (
+ IN UINT32 Index,
+ IN UINT64 OrData
+ );
+
+/**
+ Reads a 64-bit MSR, performs a bitwise AND, and writes the result back to the
+ 64-bit MSR.
+
+ Reads the 64-bit MSR specified by Index, performs a bitwise AND between the
+ read result and the value specified by OrData, and writes the result to the
+ 64-bit MSR specified by Index. The value written to the MSR is returned. No
+ parameter checking is performed on Index or OrData, and some of these may
+ cause CPU exceptions. The caller must either guarantee that Index and OrData
+ are valid, or the caller must establish proper exception handlers. This
+ function is only available on IA-32 and x64.
+
+ @param Index The 32-bit MSR index to write.
+ @param AndData The value to AND with the read value from the MSR.
+
+ @return The value written back to the MSR.
+
+**/
+UINT64
+EFIAPI
+AsmMsrAnd64 (
+ IN UINT32 Index,
+ IN UINT64 AndData
+ );
+
+/**
+ Reads a 64-bit MSR, performs a bitwise AND followed by a bitwise
+ OR, and writes the result back to the 64-bit MSR.
+
+ Reads the 64-bit MSR specified by Index, performs a bitwise AND between read
+ result and the value specified by AndData, performs a bitwise OR
+ between the result of the AND operation and the value specified by OrData,
+ and writes the result to the 64-bit MSR specified by Index. The value written
+ to the MSR is returned. No parameter checking is performed on Index, AndData,
+ or OrData, and some of these may cause CPU exceptions. The caller must either
+ guarantee that Index, AndData, and OrData are valid, or the caller must
+ establish proper exception handlers. This function is only available on IA-32
+ and x64.
+
+ @param Index The 32-bit MSR index to write.
+ @param AndData The value to AND with the read value from the MSR.
+ @param OrData The value to OR with the result of the AND operation.
+
+ @return The value written back to the MSR.
+
+**/
+UINT64
+EFIAPI
+AsmMsrAndThenOr64 (
+ IN UINT32 Index,
+ IN UINT64 AndData,
+ IN UINT64 OrData
+ );
+
+/**
+ Reads a bit field of an MSR.
+
+ Reads the bit field in the 64-bit MSR. The bit field is specified by the
+ StartBit and the EndBit. The value of the bit field is returned. The caller
+ must either guarantee that Index is valid, or the caller must set up
+ exception handlers to catch the exceptions. This function is only available
+ on IA-32 and x64.
+
+ If StartBit is greater than 63, then ASSERT().
+ If EndBit is greater than 63, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+
+ @param Index The 32-bit MSR index to read.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..63.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..63.
+
+ @return The value read from the MSR.
+
+**/
+UINT64
+EFIAPI
+AsmMsrBitFieldRead64 (
+ IN UINT32 Index,
+ IN UINTN StartBit,
+ IN UINTN EndBit
+ );
+
+/**
+ Writes a bit field to an MSR.
+
+ Writes Value to a bit field in a 64-bit MSR. The bit field is specified by
+ the StartBit and the EndBit. All other bits in the destination MSR are
+ preserved. The MSR written is returned. The caller must either guarantee
+ that Index and the data written is valid, or the caller must set up exception
+ handlers to catch the exceptions. This function is only available on IA-32 and x64.
+
+ If StartBit is greater than 63, then ASSERT().
+ If EndBit is greater than 63, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Index The 32-bit MSR index to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..63.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..63.
+ @param Value New value of the bit field.
+
+ @return The value written back to the MSR.
+
+**/
+UINT64
+EFIAPI
+AsmMsrBitFieldWrite64 (
+ IN UINT32 Index,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT64 Value
+ );
+
+/**
+ Reads a bit field in a 64-bit MSR, performs a bitwise OR, and
+ writes the result back to the bit field in the 64-bit MSR.
+
+ Reads the 64-bit MSR specified by Index, performs a bitwise OR
+ between the read result and the value specified by OrData, and writes the
+ result to the 64-bit MSR specified by Index. The value written to the MSR is
+ returned. Extra left bits in OrData are stripped. The caller must either
+ guarantee that Index and the data written is valid, or the caller must set up
+ exception handlers to catch the exceptions. This function is only available
+ on IA-32 and x64.
+
+ If StartBit is greater than 63, then ASSERT().
+ If EndBit is greater than 63, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Index The 32-bit MSR index to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..63.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..63.
+ @param OrData The value to OR with the read value from the bit field.
+
+ @return The value written back to the MSR.
+
+**/
+UINT64
+EFIAPI
+AsmMsrBitFieldOr64 (
+ IN UINT32 Index,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT64 OrData
+ );
+
+/**
+ Reads a bit field in a 64-bit MSR, performs a bitwise AND, and writes the
+ result back to the bit field in the 64-bit MSR.
+
+ Reads the 64-bit MSR specified by Index, performs a bitwise AND between the
+ read result and the value specified by AndData, and writes the result to the
+ 64-bit MSR specified by Index. The value written to the MSR is returned.
+ Extra left bits in AndData are stripped. The caller must either guarantee
+ that Index and the data written is valid, or the caller must set up exception
+ handlers to catch the exceptions. This function is only available on IA-32
+ and x64.
+
+ If StartBit is greater than 63, then ASSERT().
+ If EndBit is greater than 63, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Index The 32-bit MSR index to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..63.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..63.
+ @param AndData The value to AND with the read value from the bit field.
+
+ @return The value written back to the MSR.
+
+**/
+UINT64
+EFIAPI
+AsmMsrBitFieldAnd64 (
+ IN UINT32 Index,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT64 AndData
+ );
+
+/**
+ Reads a bit field in a 64-bit MSR, performs a bitwise AND followed by a
+ bitwise OR, and writes the result back to the bit field in the
+ 64-bit MSR.
+
+ Reads the 64-bit MSR specified by Index, performs a bitwise AND followed by
+ a bitwise OR between the read result and the value specified by
+ AndData, and writes the result to the 64-bit MSR specified by Index. The
+ value written to the MSR is returned. Extra left bits in both AndData and
+ OrData are stripped. The caller must either guarantee that Index and the data
+ written is valid, or the caller must set up exception handlers to catch the
+ exceptions. This function is only available on IA-32 and x64.
+
+ If StartBit is greater than 63, then ASSERT().
+ If EndBit is greater than 63, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Index The 32-bit MSR index to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..63.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..63.
+ @param AndData The value to AND with the read value from the bit field.
+ @param OrData The value to OR with the result of the AND operation.
+
+ @return The value written back to the MSR.
+
+**/
+UINT64
+EFIAPI
+AsmMsrBitFieldAndThenOr64 (
+ IN UINT32 Index,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT64 AndData,
+ IN UINT64 OrData
+ );
+
+/**
+ Reads the current value of the EFLAGS register.
+
+ Reads and returns the current value of the EFLAGS register. This function is
+ only available on IA-32 and x64. This returns a 32-bit value on IA-32 and a
+ 64-bit value on x64.
+
+ @return EFLAGS on IA-32 or RFLAGS on x64.
+
+**/
+UINTN
+EFIAPI
+AsmReadEflags (
+ VOID
+ );
+
+/**
+ Reads the current value of the Control Register 0 (CR0).
+
+ Reads and returns the current value of CR0. This function is only available
+ on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on
+ x64.
+
+ @return The value of the Control Register 0 (CR0).
+
+**/
+UINTN
+EFIAPI
+AsmReadCr0 (
+ VOID
+ );
+
+/**
+ Reads the current value of the Control Register 2 (CR2).
+
+ Reads and returns the current value of CR2. This function is only available
+ on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on
+ x64.
+
+ @return The value of the Control Register 2 (CR2).
+
+**/
+UINTN
+EFIAPI
+AsmReadCr2 (
+ VOID
+ );
+
+/**
+ Reads the current value of the Control Register 3 (CR3).
+
+ Reads and returns the current value of CR3. This function is only available
+ on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on
+ x64.
+
+ @return The value of the Control Register 3 (CR3).
+
+**/
+UINTN
+EFIAPI
+AsmReadCr3 (
+ VOID
+ );
+
+/**
+ Reads the current value of the Control Register 4 (CR4).
+
+ Reads and returns the current value of CR4. This function is only available
+ on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on
+ x64.
+
+ @return The value of the Control Register 4 (CR4).
+
+**/
+UINTN
+EFIAPI
+AsmReadCr4 (
+ VOID
+ );
+
+/**
+ Writes a value to Control Register 0 (CR0).
+
+ Writes and returns a new value to CR0. This function is only available on
+ IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.
+
+ @param Cr0 The value to write to CR0.
+
+ @return The value written to CR0.
+
+**/
+UINTN
+EFIAPI
+AsmWriteCr0 (
+ UINTN Cr0
+ );
+
+/**
+ Writes a value to Control Register 2 (CR2).
+
+ Writes and returns a new value to CR2. This function is only available on
+ IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.
+
+ @param Cr2 The value to write to CR2.
+
+ @return The value written to CR2.
+
+**/
+UINTN
+EFIAPI
+AsmWriteCr2 (
+ UINTN Cr2
+ );
+
+/**
+ Writes a value to Control Register 3 (CR3).
+
+ Writes and returns a new value to CR3. This function is only available on
+ IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.
+
+ @param Cr3 The value to write to CR3.
+
+ @return The value written to CR3.
+
+**/
+UINTN
+EFIAPI
+AsmWriteCr3 (
+ UINTN Cr3
+ );
+
+/**
+ Writes a value to Control Register 4 (CR4).
+
+ Writes and returns a new value to CR4. This function is only available on
+ IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.
+
+ @param Cr4 The value to write to CR4.
+
+ @return The value written to CR4.
+
+**/
+UINTN
+EFIAPI
+AsmWriteCr4 (
+ UINTN Cr4
+ );
+
+/**
+ Reads the current value of Debug Register 0 (DR0).
+
+ Reads and returns the current value of DR0. This function is only available
+ on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on
+ x64.
+
+ @return The value of Debug Register 0 (DR0).
+
+**/
+UINTN
+EFIAPI
+AsmReadDr0 (
+ VOID
+ );
+
+/**
+ Reads the current value of Debug Register 1 (DR1).
+
+ Reads and returns the current value of DR1. This function is only available
+ on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on
+ x64.
+
+ @return The value of Debug Register 1 (DR1).
+
+**/
+UINTN
+EFIAPI
+AsmReadDr1 (
+ VOID
+ );
+
+/**
+ Reads the current value of Debug Register 2 (DR2).
+
+ Reads and returns the current value of DR2. This function is only available
+ on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on
+ x64.
+
+ @return The value of Debug Register 2 (DR2).
+
+**/
+UINTN
+EFIAPI
+AsmReadDr2 (
+ VOID
+ );
+
+/**
+ Reads the current value of Debug Register 3 (DR3).
+
+ Reads and returns the current value of DR3. This function is only available
+ on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on
+ x64.
+
+ @return The value of Debug Register 3 (DR3).
+
+**/
+UINTN
+EFIAPI
+AsmReadDr3 (
+ VOID
+ );
+
+/**
+ Reads the current value of Debug Register 4 (DR4).
+
+ Reads and returns the current value of DR4. This function is only available
+ on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on
+ x64.
+
+ @return The value of Debug Register 4 (DR4).
+
+**/
+UINTN
+EFIAPI
+AsmReadDr4 (
+ VOID
+ );
+
+/**
+ Reads the current value of Debug Register 5 (DR5).
+
+ Reads and returns the current value of DR5. This function is only available
+ on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on
+ x64.
+
+ @return The value of Debug Register 5 (DR5).
+
+**/
+UINTN
+EFIAPI
+AsmReadDr5 (
+ VOID
+ );
+
+/**
+ Reads the current value of Debug Register 6 (DR6).
+
+ Reads and returns the current value of DR6. This function is only available
+ on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on
+ x64.
+
+ @return The value of Debug Register 6 (DR6).
+
+**/
+UINTN
+EFIAPI
+AsmReadDr6 (
+ VOID
+ );
+
+/**
+ Reads the current value of Debug Register 7 (DR7).
+
+ Reads and returns the current value of DR7. This function is only available
+ on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on
+ x64.
+
+ @return The value of Debug Register 7 (DR7).
+
+**/
+UINTN
+EFIAPI
+AsmReadDr7 (
+ VOID
+ );
+
+/**
+ Writes a value to Debug Register 0 (DR0).
+
+ Writes and returns a new value to DR0. This function is only available on
+ IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.
+
+ @param Dr0 The value to write to Dr0.
+
+ @return The value written to Debug Register 0 (DR0).
+
+**/
+UINTN
+EFIAPI
+AsmWriteDr0 (
+ UINTN Dr0
+ );
+
+/**
+ Writes a value to Debug Register 1 (DR1).
+
+ Writes and returns a new value to DR1. This function is only available on
+ IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.
+
+ @param Dr1 The value to write to Dr1.
+
+ @return The value written to Debug Register 1 (DR1).
+
+**/
+UINTN
+EFIAPI
+AsmWriteDr1 (
+ UINTN Dr1
+ );
+
+/**
+ Writes a value to Debug Register 2 (DR2).
+
+ Writes and returns a new value to DR2. This function is only available on
+ IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.
+
+ @param Dr2 The value to write to Dr2.
+
+ @return The value written to Debug Register 2 (DR2).
+
+**/
+UINTN
+EFIAPI
+AsmWriteDr2 (
+ UINTN Dr2
+ );
+
+/**
+ Writes a value to Debug Register 3 (DR3).
+
+ Writes and returns a new value to DR3. This function is only available on
+ IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.
+
+ @param Dr3 The value to write to Dr3.
+
+ @return The value written to Debug Register 3 (DR3).
+
+**/
+UINTN
+EFIAPI
+AsmWriteDr3 (
+ UINTN Dr3
+ );
+
+/**
+ Writes a value to Debug Register 4 (DR4).
+
+ Writes and returns a new value to DR4. This function is only available on
+ IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.
+
+ @param Dr4 The value to write to Dr4.
+
+ @return The value written to Debug Register 4 (DR4).
+
+**/
+UINTN
+EFIAPI
+AsmWriteDr4 (
+ UINTN Dr4
+ );
+
+/**
+ Writes a value to Debug Register 5 (DR5).
+
+ Writes and returns a new value to DR5. This function is only available on
+ IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.
+
+ @param Dr5 The value to write to Dr5.
+
+ @return The value written to Debug Register 5 (DR5).
+
+**/
+UINTN
+EFIAPI
+AsmWriteDr5 (
+ UINTN Dr5
+ );
+
+/**
+ Writes a value to Debug Register 6 (DR6).
+
+ Writes and returns a new value to DR6. This function is only available on
+ IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.
+
+ @param Dr6 The value to write to Dr6.
+
+ @return The value written to Debug Register 6 (DR6).
+
+**/
+UINTN
+EFIAPI
+AsmWriteDr6 (
+ UINTN Dr6
+ );
+
+/**
+ Writes a value to Debug Register 7 (DR7).
+
+ Writes and returns a new value to DR7. This function is only available on
+ IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.
+
+ @param Dr7 The value to write to Dr7.
+
+ @return The value written to Debug Register 7 (DR7).
+
+**/
+UINTN
+EFIAPI
+AsmWriteDr7 (
+ UINTN Dr7
+ );
+
+/**
+ Reads the current value of Code Segment Register (CS).
+
+ Reads and returns the current value of CS. This function is only available on
+ IA-32 and x64.
+
+ @return The current value of CS.
+
+**/
+UINT16
+EFIAPI
+AsmReadCs (
+ VOID
+ );
+
+/**
+ Reads the current value of Data Segment Register (DS).
+
+ Reads and returns the current value of DS. This function is only available on
+ IA-32 and x64.
+
+ @return The current value of DS.
+
+**/
+UINT16
+EFIAPI
+AsmReadDs (
+ VOID
+ );
+
+/**
+ Reads the current value of Extra Segment Register (ES).
+
+ Reads and returns the current value of ES. This function is only available on
+ IA-32 and x64.
+
+ @return The current value of ES.
+
+**/
+UINT16
+EFIAPI
+AsmReadEs (
+ VOID
+ );
+
+/**
+ Reads the current value of FS Data Segment Register (FS).
+
+ Reads and returns the current value of FS. This function is only available on
+ IA-32 and x64.
+
+ @return The current value of FS.
+
+**/
+UINT16
+EFIAPI
+AsmReadFs (
+ VOID
+ );
+
+/**
+ Reads the current value of GS Data Segment Register (GS).
+
+ Reads and returns the current value of GS. This function is only available on
+ IA-32 and x64.
+
+ @return The current value of GS.
+
+**/
+UINT16
+EFIAPI
+AsmReadGs (
+ VOID
+ );
+
+/**
+ Reads the current value of Stack Segment Register (SS).
+
+ Reads and returns the current value of SS. This function is only available on
+ IA-32 and x64.
+
+ @return The current value of SS.
+
+**/
+UINT16
+EFIAPI
+AsmReadSs (
+ VOID
+ );
+
+/**
+ Reads the current value of Task Register (TR).
+
+ Reads and returns the current value of TR. This function is only available on
+ IA-32 and x64.
+
+ @return The current value of TR.
+
+**/
+UINT16
+EFIAPI
+AsmReadTr (
+ VOID
+ );
+
+/**
+ Reads the current Global Descriptor Table Register(GDTR) descriptor.
+
+ Reads and returns the current GDTR descriptor and returns it in Gdtr. This
+ function is only available on IA-32 and x64.
+
+ If Gdtr is NULL, then ASSERT().
+
+ @param Gdtr The pointer to a GDTR descriptor.
+
+**/
+VOID
+EFIAPI
+AsmReadGdtr (
+ OUT IA32_DESCRIPTOR *Gdtr
+ );
+
+/**
+ Writes the current Global Descriptor Table Register (GDTR) descriptor.
+
+ Writes and the current GDTR descriptor specified by Gdtr. This function is
+ only available on IA-32 and x64.
+
+ If Gdtr is NULL, then ASSERT().
+
+ @param Gdtr The pointer to a GDTR descriptor.
+
+**/
+VOID
+EFIAPI
+AsmWriteGdtr (
+ IN CONST IA32_DESCRIPTOR *Gdtr
+ );
+
+/**
+ Reads the current Interrupt Descriptor Table Register(IDTR) descriptor.
+
+ Reads and returns the current IDTR descriptor and returns it in Idtr. This
+ function is only available on IA-32 and x64.
+
+ If Idtr is NULL, then ASSERT().
+
+ @param Idtr The pointer to a IDTR descriptor.
+
+**/
+VOID
+EFIAPI
+AsmReadIdtr (
+ OUT IA32_DESCRIPTOR *Idtr
+ );
+
+/**
+ Writes the current Interrupt Descriptor Table Register(IDTR) descriptor.
+
+ Writes the current IDTR descriptor and returns it in Idtr. This function is
+ only available on IA-32 and x64.
+
+ If Idtr is NULL, then ASSERT().
+
+ @param Idtr The pointer to a IDTR descriptor.
+
+**/
+VOID
+EFIAPI
+AsmWriteIdtr (
+ IN CONST IA32_DESCRIPTOR *Idtr
+ );
+
+/**
+ Reads the current Local Descriptor Table Register(LDTR) selector.
+
+ Reads and returns the current 16-bit LDTR descriptor value. This function is
+ only available on IA-32 and x64.
+
+ @return The current selector of LDT.
+
+**/
+UINT16
+EFIAPI
+AsmReadLdtr (
+ VOID
+ );
+
+/**
+ Writes the current Local Descriptor Table Register (LDTR) selector.
+
+ Writes and the current LDTR descriptor specified by Ldtr. This function is
+ only available on IA-32 and x64.
+
+ @param Ldtr 16-bit LDTR selector value.
+
+**/
+VOID
+EFIAPI
+AsmWriteLdtr (
+ IN UINT16 Ldtr
+ );
+
+/**
+ Save the current floating point/SSE/SSE2 context to a buffer.
+
+ Saves the current floating point/SSE/SSE2 state to the buffer specified by
+ Buffer. Buffer must be aligned on a 16-byte boundary. This function is only
+ available on IA-32 and x64.
+
+ If Buffer is NULL, then ASSERT().
+ If Buffer is not aligned on a 16-byte boundary, then ASSERT().
+
+ @param Buffer The pointer to a buffer to save the floating point/SSE/SSE2 context.
+
+**/
+VOID
+EFIAPI
+AsmFxSave (
+ OUT IA32_FX_BUFFER *Buffer
+ );
+
+/**
+ Restores the current floating point/SSE/SSE2 context from a buffer.
+
+ Restores the current floating point/SSE/SSE2 state from the buffer specified
+ by Buffer. Buffer must be aligned on a 16-byte boundary. This function is
+ only available on IA-32 and x64.
+
+ If Buffer is NULL, then ASSERT().
+ If Buffer is not aligned on a 16-byte boundary, then ASSERT().
+ If Buffer was not saved with AsmFxSave(), then ASSERT().
+
+ @param Buffer The pointer to a buffer to save the floating point/SSE/SSE2 context.
+
+**/
+VOID
+EFIAPI
+AsmFxRestore (
+ IN CONST IA32_FX_BUFFER *Buffer
+ );
+
+/**
+ Reads the current value of 64-bit MMX Register #0 (MM0).
+
+ Reads and returns the current value of MM0. This function is only available
+ on IA-32 and x64.
+
+ @return The current value of MM0.
+
+**/
+UINT64
+EFIAPI
+AsmReadMm0 (
+ VOID
+ );
+
+/**
+ Reads the current value of 64-bit MMX Register #1 (MM1).
+
+ Reads and returns the current value of MM1. This function is only available
+ on IA-32 and x64.
+
+ @return The current value of MM1.
+
+**/
+UINT64
+EFIAPI
+AsmReadMm1 (
+ VOID
+ );
+
+/**
+ Reads the current value of 64-bit MMX Register #2 (MM2).
+
+ Reads and returns the current value of MM2. This function is only available
+ on IA-32 and x64.
+
+ @return The current value of MM2.
+
+**/
+UINT64
+EFIAPI
+AsmReadMm2 (
+ VOID
+ );
+
+/**
+ Reads the current value of 64-bit MMX Register #3 (MM3).
+
+ Reads and returns the current value of MM3. This function is only available
+ on IA-32 and x64.
+
+ @return The current value of MM3.
+
+**/
+UINT64
+EFIAPI
+AsmReadMm3 (
+ VOID
+ );
+
+/**
+ Reads the current value of 64-bit MMX Register #4 (MM4).
+
+ Reads and returns the current value of MM4. This function is only available
+ on IA-32 and x64.
+
+ @return The current value of MM4.
+
+**/
+UINT64
+EFIAPI
+AsmReadMm4 (
+ VOID
+ );
+
+/**
+ Reads the current value of 64-bit MMX Register #5 (MM5).
+
+ Reads and returns the current value of MM5. This function is only available
+ on IA-32 and x64.
+
+ @return The current value of MM5.
+
+**/
+UINT64
+EFIAPI
+AsmReadMm5 (
+ VOID
+ );
+
+/**
+ Reads the current value of 64-bit MMX Register #6 (MM6).
+
+ Reads and returns the current value of MM6. This function is only available
+ on IA-32 and x64.
+
+ @return The current value of MM6.
+
+**/
+UINT64
+EFIAPI
+AsmReadMm6 (
+ VOID
+ );
+
+/**
+ Reads the current value of 64-bit MMX Register #7 (MM7).
+
+ Reads and returns the current value of MM7. This function is only available
+ on IA-32 and x64.
+
+ @return The current value of MM7.
+
+**/
+UINT64
+EFIAPI
+AsmReadMm7 (
+ VOID
+ );
+
+/**
+ Writes the current value of 64-bit MMX Register #0 (MM0).
+
+ Writes the current value of MM0. This function is only available on IA32 and
+ x64.
+
+ @param Value The 64-bit value to write to MM0.
+
+**/
+VOID
+EFIAPI
+AsmWriteMm0 (
+ IN UINT64 Value
+ );
+
+/**
+ Writes the current value of 64-bit MMX Register #1 (MM1).
+
+ Writes the current value of MM1. This function is only available on IA32 and
+ x64.
+
+ @param Value The 64-bit value to write to MM1.
+
+**/
+VOID
+EFIAPI
+AsmWriteMm1 (
+ IN UINT64 Value
+ );
+
+/**
+ Writes the current value of 64-bit MMX Register #2 (MM2).
+
+ Writes the current value of MM2. This function is only available on IA32 and
+ x64.
+
+ @param Value The 64-bit value to write to MM2.
+
+**/
+VOID
+EFIAPI
+AsmWriteMm2 (
+ IN UINT64 Value
+ );
+
+/**
+ Writes the current value of 64-bit MMX Register #3 (MM3).
+
+ Writes the current value of MM3. This function is only available on IA32 and
+ x64.
+
+ @param Value The 64-bit value to write to MM3.
+
+**/
+VOID
+EFIAPI
+AsmWriteMm3 (
+ IN UINT64 Value
+ );
+
+/**
+ Writes the current value of 64-bit MMX Register #4 (MM4).
+
+ Writes the current value of MM4. This function is only available on IA32 and
+ x64.
+
+ @param Value The 64-bit value to write to MM4.
+
+**/
+VOID
+EFIAPI
+AsmWriteMm4 (
+ IN UINT64 Value
+ );
+
+/**
+ Writes the current value of 64-bit MMX Register #5 (MM5).
+
+ Writes the current value of MM5. This function is only available on IA32 and
+ x64.
+
+ @param Value The 64-bit value to write to MM5.
+
+**/
+VOID
+EFIAPI
+AsmWriteMm5 (
+ IN UINT64 Value
+ );
+
+/**
+ Writes the current value of 64-bit MMX Register #6 (MM6).
+
+ Writes the current value of MM6. This function is only available on IA32 and
+ x64.
+
+ @param Value The 64-bit value to write to MM6.
+
+**/
+VOID
+EFIAPI
+AsmWriteMm6 (
+ IN UINT64 Value
+ );
+
+/**
+ Writes the current value of 64-bit MMX Register #7 (MM7).
+
+ Writes the current value of MM7. This function is only available on IA32 and
+ x64.
+
+ @param Value The 64-bit value to write to MM7.
+
+**/
+VOID
+EFIAPI
+AsmWriteMm7 (
+ IN UINT64 Value
+ );
+
+/**
+ Reads the current value of Time Stamp Counter (TSC).
+
+ Reads and returns the current value of TSC. This function is only available
+ on IA-32 and x64.
+
+ @return The current value of TSC
+
+**/
+UINT64
+EFIAPI
+AsmReadTsc (
+ VOID
+ );
+
+/**
+ Reads the current value of a Performance Counter (PMC).
+
+ Reads and returns the current value of performance counter specified by
+ Index. This function is only available on IA-32 and x64.
+
+ @param Index The 32-bit Performance Counter index to read.
+
+ @return The value of the PMC specified by Index.
+
+**/
+UINT64
+EFIAPI
+AsmReadPmc (
+ IN UINT32 Index
+ );
+
+/**
+ Sets up a monitor buffer that is used by AsmMwait().
+
+ Executes a MONITOR instruction with the register state specified by Eax, Ecx
+ and Edx. Returns Eax. This function is only available on IA-32 and x64.
+
+ @param Eax The value to load into EAX or RAX before executing the MONITOR
+ instruction.
+ @param Ecx The value to load into ECX or RCX before executing the MONITOR
+ instruction.
+ @param Edx The value to load into EDX or RDX before executing the MONITOR
+ instruction.
+
+ @return Eax
+
+**/
+UINTN
+EFIAPI
+AsmMonitor (
+ IN UINTN Eax,
+ IN UINTN Ecx,
+ IN UINTN Edx
+ );
+
+/**
+ Executes an MWAIT instruction.
+
+ Executes an MWAIT instruction with the register state specified by Eax and
+ Ecx. Returns Eax. This function is only available on IA-32 and x64.
+
+ @param Eax The value to load into EAX or RAX before executing the MONITOR
+ instruction.
+ @param Ecx The value to load into ECX or RCX before executing the MONITOR
+ instruction.
+
+ @return Eax
+
+**/
+UINTN
+EFIAPI
+AsmMwait (
+ IN UINTN Eax,
+ IN UINTN Ecx
+ );
+
+/**
+ Executes a WBINVD instruction.
+
+ Executes a WBINVD instruction. This function is only available on IA-32 and
+ x64.
+
+**/
+VOID
+EFIAPI
+AsmWbinvd (
+ VOID
+ );
+
+/**
+ Executes a INVD instruction.
+
+ Executes a INVD instruction. This function is only available on IA-32 and
+ x64.
+
+**/
+VOID
+EFIAPI
+AsmInvd (
+ VOID
+ );
+
+/**
+ Flushes a cache line from all the instruction and data caches within the
+ coherency domain of the CPU.
+
+ Flushed the cache line specified by LinearAddress, and returns LinearAddress.
+ This function is only available on IA-32 and x64.
+
+ @param LinearAddress The address of the cache line to flush. If the CPU is
+ in a physical addressing mode, then LinearAddress is a
+ physical address. If the CPU is in a virtual
+ addressing mode, then LinearAddress is a virtual
+ address.
+
+ @return LinearAddress.
+**/
+VOID *
+EFIAPI
+AsmFlushCacheLine (
+ IN VOID *LinearAddress
+ );
+
+/**
+ Enables the 32-bit paging mode on the CPU.
+
+ Enables the 32-bit paging mode on the CPU. CR0, CR3, CR4, and the page tables
+ must be properly initialized prior to calling this service. This function
+ assumes the current execution mode is 32-bit protected mode. This function is
+ only available on IA-32. After the 32-bit paging mode is enabled, control is
+ transferred to the function specified by EntryPoint using the new stack
+ specified by NewStack and passing in the parameters specified by Context1 and
+ Context2. Context1 and Context2 are optional and may be NULL. The function
+ EntryPoint must never return.
+
+ If the current execution mode is not 32-bit protected mode, then ASSERT().
+ If EntryPoint is NULL, then ASSERT().
+ If NewStack is NULL, then ASSERT().
+
+ There are a number of constraints that must be followed before calling this
+ function:
+ 1) Interrupts must be disabled.
+ 2) The caller must be in 32-bit protected mode with flat descriptors. This
+ means all descriptors must have a base of 0 and a limit of 4GB.
+ 3) CR0 and CR4 must be compatible with 32-bit protected mode with flat
+ descriptors.
+ 4) CR3 must point to valid page tables that will be used once the transition
+ is complete, and those page tables must guarantee that the pages for this
+ function and the stack are identity mapped.
+
+ @param EntryPoint A pointer to function to call with the new stack after
+ paging is enabled.
+ @param Context1 A pointer to the context to pass into the EntryPoint
+ function as the first parameter after paging is enabled.
+ @param Context2 A pointer to the context to pass into the EntryPoint
+ function as the second parameter after paging is enabled.
+ @param NewStack A pointer to the new stack to use for the EntryPoint
+ function after paging is enabled.
+
+**/
+VOID
+EFIAPI
+AsmEnablePaging32 (
+ IN SWITCH_STACK_ENTRY_POINT EntryPoint,
+ IN VOID *Context1 OPTIONAL,
+ IN VOID *Context2 OPTIONAL,
+ IN VOID *NewStack
+ );
+
+/**
+ Disables the 32-bit paging mode on the CPU.
+
+ Disables the 32-bit paging mode on the CPU and returns to 32-bit protected
+ mode. This function assumes the current execution mode is 32-paged protected
+ mode. This function is only available on IA-32. After the 32-bit paging mode
+ is disabled, control is transferred to the function specified by EntryPoint
+ using the new stack specified by NewStack and passing in the parameters
+ specified by Context1 and Context2. Context1 and Context2 are optional and
+ may be NULL. The function EntryPoint must never return.
+
+ If the current execution mode is not 32-bit paged mode, then ASSERT().
+ If EntryPoint is NULL, then ASSERT().
+ If NewStack is NULL, then ASSERT().
+
+ There are a number of constraints that must be followed before calling this
+ function:
+ 1) Interrupts must be disabled.
+ 2) The caller must be in 32-bit paged mode.
+ 3) CR0, CR3, and CR4 must be compatible with 32-bit paged mode.
+ 4) CR3 must point to valid page tables that guarantee that the pages for
+ this function and the stack are identity mapped.
+
+ @param EntryPoint A pointer to function to call with the new stack after
+ paging is disabled.
+ @param Context1 A pointer to the context to pass into the EntryPoint
+ function as the first parameter after paging is disabled.
+ @param Context2 A pointer to the context to pass into the EntryPoint
+ function as the second parameter after paging is
+ disabled.
+ @param NewStack A pointer to the new stack to use for the EntryPoint
+ function after paging is disabled.
+
+**/
+VOID
+EFIAPI
+AsmDisablePaging32 (
+ IN SWITCH_STACK_ENTRY_POINT EntryPoint,
+ IN VOID *Context1 OPTIONAL,
+ IN VOID *Context2 OPTIONAL,
+ IN VOID *NewStack
+ );
+
+/**
+ Enables the 64-bit paging mode on the CPU.
+
+ Enables the 64-bit paging mode on the CPU. CR0, CR3, CR4, and the page tables
+ must be properly initialized prior to calling this service. This function
+ assumes the current execution mode is 32-bit protected mode with flat
+ descriptors. This function is only available on IA-32. After the 64-bit
+ paging mode is enabled, control is transferred to the function specified by
+ EntryPoint using the new stack specified by NewStack and passing in the
+ parameters specified by Context1 and Context2. Context1 and Context2 are
+ optional and may be 0. The function EntryPoint must never return.
+
+ If the current execution mode is not 32-bit protected mode with flat
+ descriptors, then ASSERT().
+ If EntryPoint is 0, then ASSERT().
+ If NewStack is 0, then ASSERT().
+
+ @param Cs The 16-bit selector to load in the CS before EntryPoint
+ is called. The descriptor in the GDT that this selector
+ references must be setup for long mode.
+ @param EntryPoint The 64-bit virtual address of the function to call with
+ the new stack after paging is enabled.
+ @param Context1 The 64-bit virtual address of the context to pass into
+ the EntryPoint function as the first parameter after
+ paging is enabled.
+ @param Context2 The 64-bit virtual address of the context to pass into
+ the EntryPoint function as the second parameter after
+ paging is enabled.
+ @param NewStack The 64-bit virtual address of the new stack to use for
+ the EntryPoint function after paging is enabled.
+
+**/
+VOID
+EFIAPI
+AsmEnablePaging64 (
+ IN UINT16 Cs,
+ IN UINT64 EntryPoint,
+ IN UINT64 Context1 OPTIONAL,
+ IN UINT64 Context2 OPTIONAL,
+ IN UINT64 NewStack
+ );
+
+/**
+ Disables the 64-bit paging mode on the CPU.
+
+ Disables the 64-bit paging mode on the CPU and returns to 32-bit protected
+ mode. This function assumes the current execution mode is 64-paging mode.
+ This function is only available on x64. After the 64-bit paging mode is
+ disabled, control is transferred to the function specified by EntryPoint
+ using the new stack specified by NewStack and passing in the parameters
+ specified by Context1 and Context2. Context1 and Context2 are optional and
+ may be 0. The function EntryPoint must never return.
+
+ If the current execution mode is not 64-bit paged mode, then ASSERT().
+ If EntryPoint is 0, then ASSERT().
+ If NewStack is 0, then ASSERT().
+
+ @param Cs The 16-bit selector to load in the CS before EntryPoint
+ is called. The descriptor in the GDT that this selector
+ references must be setup for 32-bit protected mode.
+ @param EntryPoint The 64-bit virtual address of the function to call with
+ the new stack after paging is disabled.
+ @param Context1 The 64-bit virtual address of the context to pass into
+ the EntryPoint function as the first parameter after
+ paging is disabled.
+ @param Context2 The 64-bit virtual address of the context to pass into
+ the EntryPoint function as the second parameter after
+ paging is disabled.
+ @param NewStack The 64-bit virtual address of the new stack to use for
+ the EntryPoint function after paging is disabled.
+
+**/
+VOID
+EFIAPI
+AsmDisablePaging64 (
+ IN UINT16 Cs,
+ IN UINT32 EntryPoint,
+ IN UINT32 Context1 OPTIONAL,
+ IN UINT32 Context2 OPTIONAL,
+ IN UINT32 NewStack
+ );
+
+//
+// 16-bit thunking services
+//
+
+/**
+ Retrieves the properties for 16-bit thunk functions.
+
+ Computes the size of the buffer and stack below 1MB required to use the
+ AsmPrepareThunk16(), AsmThunk16() and AsmPrepareAndThunk16() functions. This
+ buffer size is returned in RealModeBufferSize, and the stack size is returned
+ in ExtraStackSize. If parameters are passed to the 16-bit real mode code,
+ then the actual minimum stack size is ExtraStackSize plus the maximum number
+ of bytes that need to be passed to the 16-bit real mode code.
+
+ If RealModeBufferSize is NULL, then ASSERT().
+ If ExtraStackSize is NULL, then ASSERT().
+
+ @param RealModeBufferSize A pointer to the size of the buffer below 1MB
+ required to use the 16-bit thunk functions.
+ @param ExtraStackSize A pointer to the extra size of stack below 1MB
+ that the 16-bit thunk functions require for
+ temporary storage in the transition to and from
+ 16-bit real mode.
+
+**/
+VOID
+EFIAPI
+AsmGetThunk16Properties (
+ OUT UINT32 *RealModeBufferSize,
+ OUT UINT32 *ExtraStackSize
+ );
+
+/**
+ Prepares all structures a code required to use AsmThunk16().
+
+ Prepares all structures and code required to use AsmThunk16().
+
+ This interface is limited to be used in either physical mode or virtual modes with paging enabled where the
+ virtual to physical mappings for ThunkContext.RealModeBuffer is mapped 1:1.
+
+ If ThunkContext is NULL, then ASSERT().
+
+ @param ThunkContext A pointer to the context structure that describes the
+ 16-bit real mode code to call.
+
+**/
+VOID
+EFIAPI
+AsmPrepareThunk16 (
+ IN OUT THUNK_CONTEXT *ThunkContext
+ );
+
+/**
+ Transfers control to a 16-bit real mode entry point and returns the results.
+
+ Transfers control to a 16-bit real mode entry point and returns the results.
+ AsmPrepareThunk16() must be called with ThunkContext before this function is used.
+ This function must be called with interrupts disabled.
+
+ The register state from the RealModeState field of ThunkContext is restored just prior
+ to calling the 16-bit real mode entry point. This includes the EFLAGS field of RealModeState,
+ which is used to set the interrupt state when a 16-bit real mode entry point is called.
+ Control is transferred to the 16-bit real mode entry point specified by the CS and Eip fields of RealModeState.
+ The stack is initialized to the SS and ESP fields of RealModeState. Any parameters passed to
+ the 16-bit real mode code must be populated by the caller at SS:ESP prior to calling this function.
+ The 16-bit real mode entry point is invoked with a 16-bit CALL FAR instruction,
+ so when accessing stack contents, the 16-bit real mode code must account for the 16-bit segment
+ and 16-bit offset of the return address that were pushed onto the stack. The 16-bit real mode entry
+ point must exit with a RETF instruction. The register state is captured into RealModeState immediately
+ after the RETF instruction is executed.
+
+ If EFLAGS specifies interrupts enabled, or any of the 16-bit real mode code enables interrupts,
+ or any of the 16-bit real mode code makes a SW interrupt, then the caller is responsible for making sure
+ the IDT at address 0 is initialized to handle any HW or SW interrupts that may occur while in 16-bit real mode.
+
+ If EFLAGS specifies interrupts enabled, or any of the 16-bit real mode code enables interrupts,
+ then the caller is responsible for making sure the 8259 PIC is in a state compatible with 16-bit real mode.
+ This includes the base vectors, the interrupt masks, and the edge/level trigger mode.
+
+ If THUNK_ATTRIBUTE_BIG_REAL_MODE is set in the ThunkAttributes field of ThunkContext, then the user code
+ is invoked in big real mode. Otherwise, the user code is invoked in 16-bit real mode with 64KB segment limits.
+
+ If neither THUNK_ATTRIBUTE_DISABLE_A20_MASK_INT_15 nor THUNK_ATTRIBUTE_DISABLE_A20_MASK_KBD_CTRL are set in
+ ThunkAttributes, then it is assumed that the user code did not enable the A20 mask, and no attempt is made to
+ disable the A20 mask.
+
+ If THUNK_ATTRIBUTE_DISABLE_A20_MASK_INT_15 is set and THUNK_ATTRIBUTE_DISABLE_A20_MASK_KBD_CTRL is clear in
+ ThunkAttributes, then attempt to use the INT 15 service to disable the A20 mask. If this INT 15 call fails,
+ then attempt to disable the A20 mask by directly accessing the 8042 keyboard controller I/O ports.
+
+ If THUNK_ATTRIBUTE_DISABLE_A20_MASK_INT_15 is clear and THUNK_ATTRIBUTE_DISABLE_A20_MASK_KBD_CTRL is set in
+ ThunkAttributes, then attempt to disable the A20 mask by directly accessing the 8042 keyboard controller I/O ports.
+
+ If ThunkContext is NULL, then ASSERT().
+ If AsmPrepareThunk16() was not previously called with ThunkContext, then ASSERT().
+ If both THUNK_ATTRIBUTE_DISABLE_A20_MASK_INT_15 and THUNK_ATTRIBUTE_DISABLE_A20_MASK_KBD_CTRL are set in
+ ThunkAttributes, then ASSERT().
+
+ This interface is limited to be used in either physical mode or virtual modes with paging enabled where the
+ virtual to physical mappings for ThunkContext.RealModeBuffer are mapped 1:1.
+
+ @param ThunkContext A pointer to the context structure that describes the
+ 16-bit real mode code to call.
+
+**/
+VOID
+EFIAPI
+AsmThunk16 (
+ IN OUT THUNK_CONTEXT *ThunkContext
+ );
+
+/**
+ Prepares all structures and code for a 16-bit real mode thunk, transfers
+ control to a 16-bit real mode entry point, and returns the results.
+
+ Prepares all structures and code for a 16-bit real mode thunk, transfers
+ control to a 16-bit real mode entry point, and returns the results. If the
+ caller only need to perform a single 16-bit real mode thunk, then this
+ service should be used. If the caller intends to make more than one 16-bit
+ real mode thunk, then it is more efficient if AsmPrepareThunk16() is called
+ once and AsmThunk16() can be called for each 16-bit real mode thunk.
+
+ This interface is limited to be used in either physical mode or virtual modes with paging enabled where the
+ virtual to physical mappings for ThunkContext.RealModeBuffer is mapped 1:1.
+
+ See AsmPrepareThunk16() and AsmThunk16() for the detailed description and ASSERT() conditions.
+
+ @param ThunkContext A pointer to the context structure that describes the
+ 16-bit real mode code to call.
+
+**/
+VOID
+EFIAPI
+AsmPrepareAndThunk16 (
+ IN OUT THUNK_CONTEXT *ThunkContext
+ );
+
+/**
+ Generates a 16-bit random number through RDRAND instruction.
+
+ if Rand is NULL, then ASSERT().
+
+ @param[out] Rand Buffer pointer to store the random result.
+
+ @retval TRUE RDRAND call was successful.
+ @retval FALSE Failed attempts to call RDRAND.
+
+ **/
+BOOLEAN
+EFIAPI
+AsmRdRand16 (
+ OUT UINT16 *Rand
+ );
+
+/**
+ Generates a 32-bit random number through RDRAND instruction.
+
+ if Rand is NULL, then ASSERT().
+
+ @param[out] Rand Buffer pointer to store the random result.
+
+ @retval TRUE RDRAND call was successful.
+ @retval FALSE Failed attempts to call RDRAND.
+
+**/
+BOOLEAN
+EFIAPI
+AsmRdRand32 (
+ OUT UINT32 *Rand
+ );
+
+/**
+ Generates a 64-bit random number through RDRAND instruction.
+
+ if Rand is NULL, then ASSERT().
+
+ @param[out] Rand Buffer pointer to store the random result.
+
+ @retval TRUE RDRAND call was successful.
+ @retval FALSE Failed attempts to call RDRAND.
+
+**/
+BOOLEAN
+EFIAPI
+AsmRdRand64 (
+ OUT UINT64 *Rand
+ );
+
+/**
+ Load given selector into TR register.
+
+ @param[in] Selector Task segment selector
+**/
+VOID
+EFIAPI
+AsmWriteTr (
+ IN UINT16 Selector
+ );
+
+/**
+ Performs a serializing operation on all load-from-memory instructions that
+ were issued prior the AsmLfence function.
+
+ Executes a LFENCE instruction. This function is only available on IA-32 and x64.
+
+**/
+VOID
+EFIAPI
+AsmLfence (
+ VOID
+ );
+
+/**
+ Executes a XGETBV instruction
+
+ Executes a XGETBV instruction. This function is only available on IA-32 and
+ x64.
+
+ @param[in] Index Extended control register index
+
+ @return The current value of the extended control register
+**/
+UINT64
+EFIAPI
+AsmXGetBv (
+ IN UINT32 Index
+ );
+
+/**
+ Executes a XSETBV instruction to write a 64-bit value to a Extended Control
+ Register(XCR), and returns the value.
+
+ Writes the 64-bit value specified by Value to the XCR specified by Index. The
+ 64-bit value written to the XCR is returned. No parameter checking is
+ performed on Index or Value, and some of these may cause CPU exceptions. The
+ caller must either guarantee that Index and Value are valid, or the caller
+ must establish proper exception handlers. This function is only available on
+ IA-32 and x64.
+
+ @param Index The 32-bit XCR index to write.
+ @param Value The 64-bit value to write to the XCR.
+
+ @return Value
+
+**/
+UINT64
+EFIAPI
+AsmXSetBv (
+ IN UINT32 Index,
+ IN UINT64 Value
+ );
+
+/**
+ Executes a VMGEXIT instruction (VMMCALL with a REP prefix)
+
+ Executes a VMGEXIT instruction. This function is only available on IA-32 and
+ x64.
+
+**/
+VOID
+EFIAPI
+AsmVmgExit (
+ VOID
+ );
+
+/**
+ Patch the immediate operand of an IA32 or X64 instruction such that the byte,
+ word, dword or qword operand is encoded at the end of the instruction's
+ binary representation.
+
+ This function should be used to update object code that was compiled with
+ NASM from assembly source code. Example:
+
+ NASM source code:
+
+ mov eax, strict dword 0 ; the imm32 zero operand will be patched
+ ASM_PFX(gPatchCr3):
+ mov cr3, eax
+
+ C source code:
+
+ X86_ASSEMBLY_PATCH_LABEL gPatchCr3;
+ PatchInstructionX86 (gPatchCr3, AsmReadCr3 (), 4);
+
+ @param[out] InstructionEnd Pointer right past the instruction to patch. The
+ immediate operand to patch is expected to
+ comprise the trailing bytes of the instruction.
+ If InstructionEnd is closer to address 0 than
+ ValueSize permits, then ASSERT().
+
+ @param[in] PatchValue The constant to write to the immediate operand.
+ The caller is responsible for ensuring that
+ PatchValue can be represented in the byte, word,
+ dword or qword operand (as indicated through
+ ValueSize); otherwise ASSERT().
+
+ @param[in] ValueSize The size of the operand in bytes; must be 1, 2,
+ 4, or 8. ASSERT() otherwise.
+**/
+VOID
+EFIAPI
+PatchInstructionX86 (
+ OUT X86_ASSEMBLY_PATCH_LABEL *InstructionEnd,
+ IN UINT64 PatchValue,
+ IN UINTN ValueSize
+ );
+
+#endif // defined (MDE_CPU_IA32) || defined (MDE_CPU_X64)
+#endif // !defined (__BASE_LIB__)
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/BaseMemoryLib.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/BaseMemoryLib.h
new file mode 100644
index 0000000000..3c764aebc5
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/BaseMemoryLib.h
@@ -0,0 +1,483 @@
+/** @file
+ Provides copy memory, fill memory, zero memory, and GUID functions.
+
+ The Base Memory Library provides optimized implementations for common memory-based operations.
+ These functions should be used in place of coding your own loops to do equivalent common functions.
+ This allows optimized library implementations to help increase performance.
+
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __BASE_MEMORY_LIB__
+#define __BASE_MEMORY_LIB__
+
+/**
+ Copies a source buffer to a destination buffer, and returns the destination buffer.
+
+ This function copies Length bytes from SourceBuffer to DestinationBuffer, and returns
+ DestinationBuffer. The implementation must be reentrant, and it must handle the case
+ where SourceBuffer overlaps DestinationBuffer.
+
+ If Length is greater than (MAX_ADDRESS - DestinationBuffer + 1), then ASSERT().
+ If Length is greater than (MAX_ADDRESS - SourceBuffer + 1), then ASSERT().
+
+ @param DestinationBuffer The pointer to the destination buffer of the memory copy.
+ @param SourceBuffer The pointer to the source buffer of the memory copy.
+ @param Length The number of bytes to copy from SourceBuffer to DestinationBuffer.
+
+ @return DestinationBuffer.
+
+**/
+VOID *
+EFIAPI
+CopyMem (
+ OUT VOID *DestinationBuffer,
+ IN CONST VOID *SourceBuffer,
+ IN UINTN Length
+ );
+
+/**
+ Fills a target buffer with a byte value, and returns the target buffer.
+
+ This function fills Length bytes of Buffer with Value, and returns Buffer.
+
+ If Length is greater than (MAX_ADDRESS - Buffer + 1), then ASSERT().
+
+ @param Buffer The memory to set.
+ @param Length The number of bytes to set.
+ @param Value The value with which to fill Length bytes of Buffer.
+
+ @return Buffer.
+
+**/
+VOID *
+EFIAPI
+SetMem (
+ OUT VOID *Buffer,
+ IN UINTN Length,
+ IN UINT8 Value
+ );
+
+/**
+ Fills a target buffer with a 16-bit value, and returns the target buffer.
+
+ This function fills Length bytes of Buffer with the 16-bit value specified by
+ Value, and returns Buffer. Value is repeated every 16-bits in for Length
+ bytes of Buffer.
+
+ If Length > 0 and Buffer is NULL, then ASSERT().
+ If Length is greater than (MAX_ADDRESS - Buffer + 1), then ASSERT().
+ If Buffer is not aligned on a 16-bit boundary, then ASSERT().
+ If Length is not aligned on a 16-bit boundary, then ASSERT().
+
+ @param Buffer The pointer to the target buffer to fill.
+ @param Length The number of bytes in Buffer to fill.
+ @param Value The value with which to fill Length bytes of Buffer.
+
+ @return Buffer.
+
+**/
+VOID *
+EFIAPI
+SetMem16 (
+ OUT VOID *Buffer,
+ IN UINTN Length,
+ IN UINT16 Value
+ );
+
+/**
+ Fills a target buffer with a 32-bit value, and returns the target buffer.
+
+ This function fills Length bytes of Buffer with the 32-bit value specified by
+ Value, and returns Buffer. Value is repeated every 32-bits in for Length
+ bytes of Buffer.
+
+ If Length > 0 and Buffer is NULL, then ASSERT().
+ If Length is greater than (MAX_ADDRESS - Buffer + 1), then ASSERT().
+ If Buffer is not aligned on a 32-bit boundary, then ASSERT().
+ If Length is not aligned on a 32-bit boundary, then ASSERT().
+
+ @param Buffer The pointer to the target buffer to fill.
+ @param Length The number of bytes in Buffer to fill.
+ @param Value The value with which to fill Length bytes of Buffer.
+
+ @return Buffer.
+
+**/
+VOID *
+EFIAPI
+SetMem32 (
+ OUT VOID *Buffer,
+ IN UINTN Length,
+ IN UINT32 Value
+ );
+
+/**
+ Fills a target buffer with a 64-bit value, and returns the target buffer.
+
+ This function fills Length bytes of Buffer with the 64-bit value specified by
+ Value, and returns Buffer. Value is repeated every 64-bits in for Length
+ bytes of Buffer.
+
+ If Length > 0 and Buffer is NULL, then ASSERT().
+ If Length is greater than (MAX_ADDRESS - Buffer + 1), then ASSERT().
+ If Buffer is not aligned on a 64-bit boundary, then ASSERT().
+ If Length is not aligned on a 64-bit boundary, then ASSERT().
+
+ @param Buffer The pointer to the target buffer to fill.
+ @param Length The number of bytes in Buffer to fill.
+ @param Value The value with which to fill Length bytes of Buffer.
+
+ @return Buffer.
+
+**/
+VOID *
+EFIAPI
+SetMem64 (
+ OUT VOID *Buffer,
+ IN UINTN Length,
+ IN UINT64 Value
+ );
+
+/**
+ Fills a target buffer with a value that is size UINTN, and returns the target buffer.
+
+ This function fills Length bytes of Buffer with the UINTN sized value specified by
+ Value, and returns Buffer. Value is repeated every sizeof(UINTN) bytes for Length
+ bytes of Buffer.
+
+ If Length > 0 and Buffer is NULL, then ASSERT().
+ If Length is greater than (MAX_ADDRESS - Buffer + 1), then ASSERT().
+ If Buffer is not aligned on a UINTN boundary, then ASSERT().
+ If Length is not aligned on a UINTN boundary, then ASSERT().
+
+ @param Buffer The pointer to the target buffer to fill.
+ @param Length The number of bytes in Buffer to fill.
+ @param Value The value with which to fill Length bytes of Buffer.
+
+ @return Buffer.
+
+**/
+VOID *
+EFIAPI
+SetMemN (
+ OUT VOID *Buffer,
+ IN UINTN Length,
+ IN UINTN Value
+ );
+
+/**
+ Fills a target buffer with zeros, and returns the target buffer.
+
+ This function fills Length bytes of Buffer with zeros, and returns Buffer.
+
+ If Length > 0 and Buffer is NULL, then ASSERT().
+ If Length is greater than (MAX_ADDRESS - Buffer + 1), then ASSERT().
+
+ @param Buffer The pointer to the target buffer to fill with zeros.
+ @param Length The number of bytes in Buffer to fill with zeros.
+
+ @return Buffer.
+
+**/
+VOID *
+EFIAPI
+ZeroMem (
+ OUT VOID *Buffer,
+ IN UINTN Length
+ );
+
+/**
+ Compares the contents of two buffers.
+
+ This function compares Length bytes of SourceBuffer to Length bytes of DestinationBuffer.
+ If all Length bytes of the two buffers are identical, then 0 is returned. Otherwise, the
+ value returned is the first mismatched byte in SourceBuffer subtracted from the first
+ mismatched byte in DestinationBuffer.
+
+ If Length > 0 and DestinationBuffer is NULL, then ASSERT().
+ If Length > 0 and SourceBuffer is NULL, then ASSERT().
+ If Length is greater than (MAX_ADDRESS - DestinationBuffer + 1), then ASSERT().
+ If Length is greater than (MAX_ADDRESS - SourceBuffer + 1), then ASSERT().
+
+ @param DestinationBuffer The pointer to the destination buffer to compare.
+ @param SourceBuffer The pointer to the source buffer to compare.
+ @param Length The number of bytes to compare.
+
+ @return 0 All Length bytes of the two buffers are identical.
+ @retval Non-zero The first mismatched byte in SourceBuffer subtracted from the first
+ mismatched byte in DestinationBuffer.
+
+**/
+INTN
+EFIAPI
+CompareMem (
+ IN CONST VOID *DestinationBuffer,
+ IN CONST VOID *SourceBuffer,
+ IN UINTN Length
+ );
+
+/**
+ Scans a target buffer for an 8-bit value, and returns a pointer to the matching 8-bit value
+ in the target buffer.
+
+ This function searches target the buffer specified by Buffer and Length from the lowest
+ address to the highest address for an 8-bit value that matches Value. If a match is found,
+ then a pointer to the matching byte in the target buffer is returned. If no match is found,
+ then NULL is returned. If Length is 0, then NULL is returned.
+
+ If Length > 0 and Buffer is NULL, then ASSERT().
+ If Length is greater than (MAX_ADDRESS - Buffer + 1), then ASSERT().
+
+ @param Buffer The pointer to the target buffer to scan.
+ @param Length The number of bytes in Buffer to scan.
+ @param Value The value to search for in the target buffer.
+
+ @return A pointer to the matching byte in the target buffer, otherwise NULL.
+
+**/
+VOID *
+EFIAPI
+ScanMem8 (
+ IN CONST VOID *Buffer,
+ IN UINTN Length,
+ IN UINT8 Value
+ );
+
+/**
+ Scans a target buffer for a 16-bit value, and returns a pointer to the matching 16-bit value
+ in the target buffer.
+
+ This function searches target the buffer specified by Buffer and Length from the lowest
+ address to the highest address for a 16-bit value that matches Value. If a match is found,
+ then a pointer to the matching byte in the target buffer is returned. If no match is found,
+ then NULL is returned. If Length is 0, then NULL is returned.
+
+ If Length > 0 and Buffer is NULL, then ASSERT().
+ If Buffer is not aligned on a 16-bit boundary, then ASSERT().
+ If Length is not aligned on a 16-bit boundary, then ASSERT().
+ If Length is greater than (MAX_ADDRESS - Buffer + 1), then ASSERT().
+
+ @param Buffer The pointer to the target buffer to scan.
+ @param Length The number of bytes in Buffer to scan.
+ @param Value The value to search for in the target buffer.
+
+ @return A pointer to the matching byte in the target buffer, otherwise NULL.
+
+**/
+VOID *
+EFIAPI
+ScanMem16 (
+ IN CONST VOID *Buffer,
+ IN UINTN Length,
+ IN UINT16 Value
+ );
+
+/**
+ Scans a target buffer for a 32-bit value, and returns a pointer to the matching 32-bit value
+ in the target buffer.
+
+ This function searches target the buffer specified by Buffer and Length from the lowest
+ address to the highest address for a 32-bit value that matches Value. If a match is found,
+ then a pointer to the matching byte in the target buffer is returned. If no match is found,
+ then NULL is returned. If Length is 0, then NULL is returned.
+
+ If Length > 0 and Buffer is NULL, then ASSERT().
+ If Buffer is not aligned on a 32-bit boundary, then ASSERT().
+ If Length is not aligned on a 32-bit boundary, then ASSERT().
+ If Length is greater than (MAX_ADDRESS - Buffer + 1), then ASSERT().
+
+ @param Buffer The pointer to the target buffer to scan.
+ @param Length The number of bytes in Buffer to scan.
+ @param Value The value to search for in the target buffer.
+
+ @return A pointer to the matching byte in the target buffer, otherwise NULL.
+
+**/
+VOID *
+EFIAPI
+ScanMem32 (
+ IN CONST VOID *Buffer,
+ IN UINTN Length,
+ IN UINT32 Value
+ );
+
+/**
+ Scans a target buffer for a 64-bit value, and returns a pointer to the matching 64-bit value
+ in the target buffer.
+
+ This function searches target the buffer specified by Buffer and Length from the lowest
+ address to the highest address for a 64-bit value that matches Value. If a match is found,
+ then a pointer to the matching byte in the target buffer is returned. If no match is found,
+ then NULL is returned. If Length is 0, then NULL is returned.
+
+ If Length > 0 and Buffer is NULL, then ASSERT().
+ If Buffer is not aligned on a 64-bit boundary, then ASSERT().
+ If Length is not aligned on a 64-bit boundary, then ASSERT().
+ If Length is greater than (MAX_ADDRESS - Buffer + 1), then ASSERT().
+
+ @param Buffer The pointer to the target buffer to scan.
+ @param Length The number of bytes in Buffer to scan.
+ @param Value The value to search for in the target buffer.
+
+ @return A pointer to the matching byte in the target buffer, otherwise NULL.
+
+**/
+VOID *
+EFIAPI
+ScanMem64 (
+ IN CONST VOID *Buffer,
+ IN UINTN Length,
+ IN UINT64 Value
+ );
+
+/**
+ Scans a target buffer for a UINTN sized value, and returns a pointer to the matching
+ UINTN sized value in the target buffer.
+
+ This function searches target the buffer specified by Buffer and Length from the lowest
+ address to the highest address for a UINTN sized value that matches Value. If a match is found,
+ then a pointer to the matching byte in the target buffer is returned. If no match is found,
+ then NULL is returned. If Length is 0, then NULL is returned.
+
+ If Length > 0 and Buffer is NULL, then ASSERT().
+ If Buffer is not aligned on a UINTN boundary, then ASSERT().
+ If Length is not aligned on a UINTN boundary, then ASSERT().
+ If Length is greater than (MAX_ADDRESS - Buffer + 1), then ASSERT().
+
+ @param Buffer The pointer to the target buffer to scan.
+ @param Length The number of bytes in Buffer to scan.
+ @param Value The value to search for in the target buffer.
+
+ @return A pointer to the matching byte in the target buffer, otherwise NULL.
+
+**/
+VOID *
+EFIAPI
+ScanMemN (
+ IN CONST VOID *Buffer,
+ IN UINTN Length,
+ IN UINTN Value
+ );
+
+/**
+ Copies a source GUID to a destination GUID.
+
+ This function copies the contents of the 128-bit GUID specified by SourceGuid to
+ DestinationGuid, and returns DestinationGuid.
+
+ If DestinationGuid is NULL, then ASSERT().
+ If SourceGuid is NULL, then ASSERT().
+
+ @param DestinationGuid The pointer to the destination GUID.
+ @param SourceGuid The pointer to the source GUID.
+
+ @return DestinationGuid.
+
+**/
+GUID *
+EFIAPI
+CopyGuid (
+ OUT GUID *DestinationGuid,
+ IN CONST GUID *SourceGuid
+ );
+
+/**
+ Compares two GUIDs.
+
+ This function compares Guid1 to Guid2. If the GUIDs are identical then TRUE is returned.
+ If there are any bit differences in the two GUIDs, then FALSE is returned.
+
+ If Guid1 is NULL, then ASSERT().
+ If Guid2 is NULL, then ASSERT().
+
+ @param Guid1 A pointer to a 128 bit GUID.
+ @param Guid2 A pointer to a 128 bit GUID.
+
+ @retval TRUE Guid1 and Guid2 are identical.
+ @retval FALSE Guid1 and Guid2 are not identical.
+
+**/
+BOOLEAN
+EFIAPI
+CompareGuid (
+ IN CONST GUID *Guid1,
+ IN CONST GUID *Guid2
+ );
+
+/**
+ Scans a target buffer for a GUID, and returns a pointer to the matching GUID
+ in the target buffer.
+
+ This function searches target the buffer specified by Buffer and Length from
+ the lowest address to the highest address at 128-bit increments for the 128-bit
+ GUID value that matches Guid. If a match is found, then a pointer to the matching
+ GUID in the target buffer is returned. If no match is found, then NULL is returned.
+ If Length is 0, then NULL is returned.
+
+ If Length > 0 and Buffer is NULL, then ASSERT().
+ If Buffer is not aligned on a 32-bit boundary, then ASSERT().
+ If Length is not aligned on a 128-bit boundary, then ASSERT().
+ If Length is greater than (MAX_ADDRESS - Buffer + 1), then ASSERT().
+
+ @param Buffer The pointer to the target buffer to scan.
+ @param Length The number of bytes in Buffer to scan.
+ @param Guid The value to search for in the target buffer.
+
+ @return A pointer to the matching Guid in the target buffer, otherwise NULL.
+
+**/
+VOID *
+EFIAPI
+ScanGuid (
+ IN CONST VOID *Buffer,
+ IN UINTN Length,
+ IN CONST GUID *Guid
+ );
+
+/**
+ Checks if the given GUID is a zero GUID.
+
+ This function checks whether the given GUID is a zero GUID. If the GUID is
+ identical to a zero GUID then TRUE is returned. Otherwise, FALSE is returned.
+
+ If Guid is NULL, then ASSERT().
+
+ @param Guid The pointer to a 128 bit GUID.
+
+ @retval TRUE Guid is a zero GUID.
+ @retval FALSE Guid is not a zero GUID.
+
+**/
+BOOLEAN
+EFIAPI
+IsZeroGuid (
+ IN CONST GUID *Guid
+ );
+
+/**
+ Checks if the contents of a buffer are all zeros.
+
+ This function checks whether the contents of a buffer are all zeros. If the
+ contents are all zeros, return TRUE. Otherwise, return FALSE.
+
+ If Length > 0 and Buffer is NULL, then ASSERT().
+ If Length is greater than (MAX_ADDRESS - Buffer + 1), then ASSERT().
+
+ @param Buffer The pointer to the buffer to be checked.
+ @param Length The size of the buffer (in bytes) to be checked.
+
+ @retval TRUE Contents of the buffer are all zeros.
+ @retval FALSE Contents of the buffer are not all zeros.
+
+**/
+BOOLEAN
+EFIAPI
+IsZeroBuffer (
+ IN CONST VOID *Buffer,
+ IN UINTN Length
+ );
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/BaseRiscVSbiLib.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/BaseRiscVSbiLib.h
new file mode 100644
index 0000000000..46fb8c5468
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/BaseRiscVSbiLib.h
@@ -0,0 +1,154 @@
+/** @file
+ Library to call the RISC-V SBI ecalls
+
+ Copyright (c) 2021-2022, Hewlett Packard Development LP. All rights reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Glossary:
+ - Hart - Hardware Thread, similar to a CPU core
+
+ Currently, EDK2 needs to call SBI only to set the time and to do system reset.
+
+**/
+
+#ifndef RISCV_SBI_LIB_H_
+#define RISCV_SBI_LIB_H_
+
+#include
+
+/* SBI Extension IDs */
+#define SBI_EXT_TIME 0x54494D45
+#define SBI_EXT_SRST 0x53525354
+
+/* SBI function IDs for TIME extension*/
+#define SBI_EXT_TIME_SET_TIMER 0x0
+
+/* SBI function IDs for SRST extension */
+#define SBI_EXT_SRST_RESET 0x0
+
+#define SBI_SRST_RESET_TYPE_SHUTDOWN 0x0
+#define SBI_SRST_RESET_TYPE_COLD_REBOOT 0x1
+#define SBI_SRST_RESET_TYPE_WARM_REBOOT 0x2
+
+#define SBI_SRST_RESET_REASON_NONE 0x0
+#define SBI_SRST_RESET_REASON_SYSFAIL 0x1
+
+/* SBI return error codes */
+#define SBI_SUCCESS 0
+#define SBI_ERR_FAILED -1
+#define SBI_ERR_NOT_SUPPORTED -2
+#define SBI_ERR_INVALID_PARAM -3
+#define SBI_ERR_DENIED -4
+#define SBI_ERR_INVALID_ADDRESS -5
+#define SBI_ERR_ALREADY_AVAILABLE -6
+#define SBI_ERR_ALREADY_STARTED -7
+#define SBI_ERR_ALREADY_STOPPED -8
+
+#define SBI_LAST_ERR SBI_ERR_ALREADY_STOPPED
+
+typedef struct {
+ UINT64 BootHartId;
+ VOID *PeiServiceTable; // PEI Service table
+ VOID *PrePiHobList; // Pre PI Hob List
+ UINT64 FlattenedDeviceTree; // Pointer to Flattened Device tree
+} EFI_RISCV_FIRMWARE_CONTEXT;
+
+//
+// EDK2 OpenSBI firmware extension return status.
+//
+typedef struct {
+ UINTN Error; ///< SBI status code
+ UINTN Value; ///< Value returned
+} SBI_RET;
+
+VOID
+EFIAPI
+SbiSetTimer (
+ IN UINT64 Time
+ );
+
+EFI_STATUS
+EFIAPI
+SbiSystemReset (
+ IN UINTN ResetType,
+ IN UINTN ResetReason
+ );
+
+/**
+ Get firmware context of the calling hart.
+
+ @param[out] FirmwareContext The firmware context pointer.
+**/
+VOID
+EFIAPI
+GetFirmwareContext (
+ OUT EFI_RISCV_FIRMWARE_CONTEXT **FirmwareContext
+ );
+
+/**
+ Set firmware context of the calling hart.
+
+ @param[in] FirmwareContext The firmware context pointer.
+**/
+VOID
+EFIAPI
+SetFirmwareContext (
+ IN EFI_RISCV_FIRMWARE_CONTEXT *FirmwareContext
+ );
+
+/**
+ Get pointer to OpenSBI Firmware Context
+
+ Get the pointer of firmware context.
+
+ @param FirmwareContextPtr Pointer to retrieve pointer to the
+ Firmware Context.
+**/
+VOID
+EFIAPI
+GetFirmwareContextPointer (
+ IN OUT EFI_RISCV_FIRMWARE_CONTEXT **FirmwareContextPtr
+ );
+
+/**
+ Set pointer to OpenSBI Firmware Context
+
+ Set the pointer of firmware context.
+
+ @param FirmwareContextPtr Pointer to Firmware Context.
+**/
+VOID
+EFIAPI
+SetFirmwareContextPointer (
+ IN EFI_RISCV_FIRMWARE_CONTEXT *FirmwareContextPtr
+ );
+
+/**
+ Make ECALL in assembly
+
+ Switch to M-mode
+
+ @param[in,out] Arg0
+ @param[in,out] Arg1
+ @param[in] Arg2
+ @param[in] Arg3
+ @param[in] Arg4
+ @param[in] Arg5
+ @param[in] FID
+ @param[in] EXT
+**/
+VOID
+EFIAPI
+RiscVSbiEcall (
+ IN OUT UINTN *Arg0,
+ IN OUT UINTN *Arg1,
+ IN UINTN Arg2,
+ IN UINTN Arg3,
+ IN UINTN Arg4,
+ IN UINTN Arg5,
+ IN UINTN Fid,
+ IN UINTN Ext
+ );
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/CacheMaintenanceLib.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/CacheMaintenanceLib.h
new file mode 100644
index 0000000000..8976940bbf
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/CacheMaintenanceLib.h
@@ -0,0 +1,206 @@
+/** @file
+ Provides services to maintain instruction and data caches.
+
+ The Cache Maintenance Library provides abstractions for basic processor cache operations.
+ It removes the need to use assembly in C code.
+
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __CACHE_MAINTENANCE_LIB__
+#define __CACHE_MAINTENANCE_LIB__
+
+/**
+ Invalidates the entire instruction cache in cache coherency domain of the
+ calling CPU.
+
+**/
+VOID
+EFIAPI
+InvalidateInstructionCache (
+ VOID
+ );
+
+/**
+ Invalidates a range of instruction cache lines in the cache coherency domain
+ of the calling CPU.
+
+ Invalidates the instruction cache lines specified by Address and Length. If
+ Address is not aligned on a cache line boundary, then entire instruction
+ cache line containing Address is invalidated. If Address + Length is not
+ aligned on a cache line boundary, then the entire instruction cache line
+ containing Address + Length -1 is invalidated. This function may choose to
+ invalidate the entire instruction cache if that is more efficient than
+ invalidating the specified range. If Length is 0, then no instruction cache
+ lines are invalidated. Address is returned.
+
+ If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
+
+ @param Address The base address of the instruction cache lines to
+ invalidate. If the CPU is in a physical addressing mode, then
+ Address is a physical address. If the CPU is in a virtual
+ addressing mode, then Address is a virtual address.
+
+ @param Length The number of bytes to invalidate from the instruction cache.
+
+ @return Address.
+
+**/
+VOID *
+EFIAPI
+InvalidateInstructionCacheRange (
+ IN VOID *Address,
+ IN UINTN Length
+ );
+
+/**
+ Writes Back and Invalidates the entire data cache in cache coherency domain
+ of the calling CPU.
+
+ Writes Back and Invalidates the entire data cache in cache coherency domain
+ of the calling CPU. This function guarantees that all dirty cache lines are
+ written back to system memory, and also invalidates all the data cache lines
+ in the cache coherency domain of the calling CPU.
+
+**/
+VOID
+EFIAPI
+WriteBackInvalidateDataCache (
+ VOID
+ );
+
+/**
+ Writes Back and Invalidates a range of data cache lines in the cache
+ coherency domain of the calling CPU.
+
+ Writes Back and Invalidate the data cache lines specified by Address and
+ Length. If Address is not aligned on a cache line boundary, then entire data
+ cache line containing Address is written back and invalidated. If Address +
+ Length is not aligned on a cache line boundary, then the entire data cache
+ line containing Address + Length -1 is written back and invalidated. This
+ function may choose to write back and invalidate the entire data cache if
+ that is more efficient than writing back and invalidating the specified
+ range. If Length is 0, then no data cache lines are written back and
+ invalidated. Address is returned.
+
+ If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
+
+ @param Address The base address of the data cache lines to write back and
+ invalidate. If the CPU is in a physical addressing mode, then
+ Address is a physical address. If the CPU is in a virtual
+ addressing mode, then Address is a virtual address.
+ @param Length The number of bytes to write back and invalidate from the
+ data cache.
+
+ @return Address of cache invalidation.
+
+**/
+VOID *
+EFIAPI
+WriteBackInvalidateDataCacheRange (
+ IN VOID *Address,
+ IN UINTN Length
+ );
+
+/**
+ Writes Back the entire data cache in cache coherency domain of the calling
+ CPU.
+
+ Writes Back the entire data cache in cache coherency domain of the calling
+ CPU. This function guarantees that all dirty cache lines are written back to
+ system memory. This function may also invalidate all the data cache lines in
+ the cache coherency domain of the calling CPU.
+
+**/
+VOID
+EFIAPI
+WriteBackDataCache (
+ VOID
+ );
+
+/**
+ Writes Back a range of data cache lines in the cache coherency domain of the
+ calling CPU.
+
+ Writes Back the data cache lines specified by Address and Length. If Address
+ is not aligned on a cache line boundary, then entire data cache line
+ containing Address is written back. If Address + Length is not aligned on a
+ cache line boundary, then the entire data cache line containing Address +
+ Length -1 is written back. This function may choose to write back the entire
+ data cache if that is more efficient than writing back the specified range.
+ If Length is 0, then no data cache lines are written back. This function may
+ also invalidate all the data cache lines in the specified range of the cache
+ coherency domain of the calling CPU. Address is returned.
+
+ If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
+
+ @param Address The base address of the data cache lines to write back. If
+ the CPU is in a physical addressing mode, then Address is a
+ physical address. If the CPU is in a virtual addressing
+ mode, then Address is a virtual address.
+ @param Length The number of bytes to write back from the data cache.
+
+ @return Address of cache written in main memory.
+
+**/
+VOID *
+EFIAPI
+WriteBackDataCacheRange (
+ IN VOID *Address,
+ IN UINTN Length
+ );
+
+/**
+ Invalidates the entire data cache in cache coherency domain of the calling
+ CPU.
+
+ Invalidates the entire data cache in cache coherency domain of the calling
+ CPU. This function must be used with care because dirty cache lines are not
+ written back to system memory. It is typically used for cache diagnostics. If
+ the CPU does not support invalidation of the entire data cache, then a write
+ back and invalidate operation should be performed on the entire data cache.
+
+**/
+VOID
+EFIAPI
+InvalidateDataCache (
+ VOID
+ );
+
+/**
+ Invalidates a range of data cache lines in the cache coherency domain of the
+ calling CPU.
+
+ Invalidates the data cache lines specified by Address and Length. If Address
+ is not aligned on a cache line boundary, then entire data cache line
+ containing Address is invalidated. If Address + Length is not aligned on a
+ cache line boundary, then the entire data cache line containing Address +
+ Length -1 is invalidated. This function must never invalidate any cache lines
+ outside the specified range. If Length is 0, the no data cache lines are
+ invalidated. Address is returned. This function must be used with care
+ because dirty cache lines are not written back to system memory. It is
+ typically used for cache diagnostics. If the CPU does not support
+ invalidation of a data cache range, then a write back and invalidate
+ operation should be performed on the data cache range.
+
+ If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
+
+ @param Address The base address of the data cache lines to invalidate. If
+ the CPU is in a physical addressing mode, then Address is a
+ physical address. If the CPU is in a virtual addressing mode,
+ then Address is a virtual address.
+ @param Length The number of bytes to invalidate from the data cache.
+
+ @return Address.
+
+**/
+VOID *
+EFIAPI
+InvalidateDataCacheRange (
+ IN VOID *Address,
+ IN UINTN Length
+ );
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/CcProbeLib.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/CcProbeLib.h
new file mode 100644
index 0000000000..4aec444496
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/CcProbeLib.h
@@ -0,0 +1,26 @@
+/** @file
+
+Copyright (c) 2022, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef CC_PROBE_LIB_H_
+#define CC_PROBE_LIB_H_
+
+#include
+
+/**
+ Probe the ConfidentialComputing Guest type. See defition of
+ CC_GUEST_TYPE in .
+
+ @return The guest type
+
+**/
+UINT8
+EFIAPI
+CcProbe (
+ VOID
+ );
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/CpuLib.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/CpuLib.h
new file mode 100644
index 0000000000..3a5c8dc750
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/CpuLib.h
@@ -0,0 +1,44 @@
+/** @file
+ Provides CPU architecture specific functions that can not be defined
+ in the Base Library due to dependencies on the PAL Library
+
+ The CPU Library provides services to flush CPU TLBs and place the CPU in a sleep state.
+ The implementation of these services on Itanium processors requires the use of PAL Calls.
+ PAL Calls require PEI and DXE specific mechanisms to look up PAL Entry Point.
+ As a result, these services could not be defined in the Base Library.
+
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __CPU_LIB_H__
+#define __CPU_LIB_H__
+
+/**
+ Places the CPU in a sleep state until an interrupt is received.
+
+ Places the CPU in a sleep state until an interrupt is received. If interrupts
+ are disabled prior to calling this function, then the CPU will be placed in a
+ sleep state indefinitely.
+
+**/
+VOID
+EFIAPI
+CpuSleep (
+ VOID
+ );
+
+/**
+ Flushes all the Translation Lookaside Buffers(TLB) entries in a CPU.
+
+ Flushes all the Translation Lookaside Buffers(TLB) entries in a CPU.
+
+**/
+VOID
+EFIAPI
+CpuFlushTlb (
+ VOID
+ );
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/DebugLib.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/DebugLib.h
new file mode 100644
index 0000000000..5e65eca505
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/DebugLib.h
@@ -0,0 +1,630 @@
+/** @file
+ Provides services to print debug and assert messages to a debug output device.
+
+ The Debug library supports debug print and asserts based on a combination of macros and code.
+ The debug library can be turned on and off so that the debug code does not increase the size of an image.
+
+ Note that a reserved macro named MDEPKG_NDEBUG is introduced for the intention
+ of size reduction when compiler optimization is disabled. If MDEPKG_NDEBUG is
+ defined, then debug and assert related macros wrapped by it are the NULL implementations.
+
+Copyright (c) 2006 - 2020, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __DEBUG_LIB_H__
+#define __DEBUG_LIB_H__
+
+//
+// Declare bits for PcdDebugPropertyMask
+//
+#define DEBUG_PROPERTY_DEBUG_ASSERT_ENABLED 0x01
+#define DEBUG_PROPERTY_DEBUG_PRINT_ENABLED 0x02
+#define DEBUG_PROPERTY_DEBUG_CODE_ENABLED 0x04
+#define DEBUG_PROPERTY_CLEAR_MEMORY_ENABLED 0x08
+#define DEBUG_PROPERTY_ASSERT_BREAKPOINT_ENABLED 0x10
+#define DEBUG_PROPERTY_ASSERT_DEADLOOP_ENABLED 0x20
+
+//
+// Declare bits for PcdDebugPrintErrorLevel and the ErrorLevel parameter of DebugPrint()
+//
+#define DEBUG_INIT 0x00000001 // Initialization
+#define DEBUG_WARN 0x00000002 // Warnings
+#define DEBUG_LOAD 0x00000004 // Load events
+#define DEBUG_FS 0x00000008 // EFI File system
+#define DEBUG_POOL 0x00000010 // Alloc & Free (pool)
+#define DEBUG_PAGE 0x00000020 // Alloc & Free (page)
+#define DEBUG_INFO 0x00000040 // Informational debug messages
+#define DEBUG_DISPATCH 0x00000080 // PEI/DXE/SMM Dispatchers
+#define DEBUG_VARIABLE 0x00000100 // Variable
+#define DEBUG_BM 0x00000400 // Boot Manager
+#define DEBUG_BLKIO 0x00001000 // BlkIo Driver
+#define DEBUG_NET 0x00004000 // Network Io Driver
+#define DEBUG_UNDI 0x00010000 // UNDI Driver
+#define DEBUG_LOADFILE 0x00020000 // LoadFile
+#define DEBUG_EVENT 0x00080000 // Event messages
+#define DEBUG_GCD 0x00100000 // Global Coherency Database changes
+#define DEBUG_CACHE 0x00200000 // Memory range cachability changes
+#define DEBUG_VERBOSE 0x00400000 // Detailed debug messages that may
+ // significantly impact boot performance
+#define DEBUG_ERROR 0x80000000 // Error
+
+//
+// Aliases of debug message mask bits
+//
+#define EFI_D_INIT DEBUG_INIT
+#define EFI_D_WARN DEBUG_WARN
+#define EFI_D_LOAD DEBUG_LOAD
+#define EFI_D_FS DEBUG_FS
+#define EFI_D_POOL DEBUG_POOL
+#define EFI_D_PAGE DEBUG_PAGE
+#define EFI_D_INFO DEBUG_INFO
+#define EFI_D_DISPATCH DEBUG_DISPATCH
+#define EFI_D_VARIABLE DEBUG_VARIABLE
+#define EFI_D_BM DEBUG_BM
+#define EFI_D_BLKIO DEBUG_BLKIO
+#define EFI_D_NET DEBUG_NET
+#define EFI_D_UNDI DEBUG_UNDI
+#define EFI_D_LOADFILE DEBUG_LOADFILE
+#define EFI_D_EVENT DEBUG_EVENT
+#define EFI_D_VERBOSE DEBUG_VERBOSE
+#define EFI_D_ERROR DEBUG_ERROR
+
+//
+// Source file line number.
+// Default is use the to compiler provided __LINE__ macro value. The __LINE__
+// mapping can be overriden by predefining DEBUG_LINE_NUMBER
+//
+// Defining DEBUG_LINE_NUMBER to a fixed value is useful when comparing builds
+// across source code formatting changes that may add/remove lines in a source
+// file.
+//
+#ifdef DEBUG_LINE_NUMBER
+#else
+#define DEBUG_LINE_NUMBER __LINE__
+#endif
+
+/**
+ Macro that converts a Boolean expression to a Null-terminated ASCII string.
+
+ The default is to use the C pre-processor stringizing operator '#' to add
+ quotes around the C expression. If DEBUG_EXPRESSION_STRING_VALUE is defined
+ then the C expression is converted to the fixed string value.
+
+ Defining DEBUG_EXPRESSION_STRING_VALUE to a fixed value is useful when
+ comparing builds across source code formatting changes that may make
+ changes to spaces or parenthesis in a Boolean expression.
+
+ @param Expression Boolean expression.
+
+**/
+
+#ifdef DEBUG_EXPRESSION_STRING_VALUE
+#define DEBUG_EXPRESSION_STRING(Expression) DEBUG_EXPRESSION_STRING_VALUE
+#else
+#define DEBUG_EXPRESSION_STRING(Expression) #Expression
+#endif
+
+/**
+ Prints a debug message to the debug output device if the specified error level is enabled.
+
+ If any bit in ErrorLevel is also set in DebugPrintErrorLevelLib function
+ GetDebugPrintErrorLevel (), then print the message specified by Format and the
+ associated variable argument list to the debug output device.
+
+ If Format is NULL, then ASSERT().
+
+ @param ErrorLevel The error level of the debug message.
+ @param Format The format string for the debug message to print.
+ @param ... The variable argument list whose contents are accessed
+ based on the format string specified by Format.
+
+**/
+VOID
+EFIAPI
+DebugPrint (
+ IN UINTN ErrorLevel,
+ IN CONST CHAR8 *Format,
+ ...
+ );
+
+/**
+ Prints a debug message to the debug output device if the specified
+ error level is enabled.
+
+ If any bit in ErrorLevel is also set in DebugPrintErrorLevelLib function
+ GetDebugPrintErrorLevel (), then print the message specified by Format and
+ the associated variable argument list to the debug output device.
+
+ If Format is NULL, then ASSERT().
+
+ @param ErrorLevel The error level of the debug message.
+ @param Format Format string for the debug message to print.
+ @param VaListMarker VA_LIST marker for the variable argument list.
+
+**/
+VOID
+EFIAPI
+DebugVPrint (
+ IN UINTN ErrorLevel,
+ IN CONST CHAR8 *Format,
+ IN VA_LIST VaListMarker
+ );
+
+/**
+ Prints a debug message to the debug output device if the specified
+ error level is enabled.
+ This function use BASE_LIST which would provide a more compatible
+ service than VA_LIST.
+
+ If any bit in ErrorLevel is also set in DebugPrintErrorLevelLib function
+ GetDebugPrintErrorLevel (), then print the message specified by Format and
+ the associated variable argument list to the debug output device.
+
+ If Format is NULL, then ASSERT().
+
+ @param ErrorLevel The error level of the debug message.
+ @param Format Format string for the debug message to print.
+ @param BaseListMarker BASE_LIST marker for the variable argument list.
+
+**/
+VOID
+EFIAPI
+DebugBPrint (
+ IN UINTN ErrorLevel,
+ IN CONST CHAR8 *Format,
+ IN BASE_LIST BaseListMarker
+ );
+
+/**
+ Prints an assert message containing a filename, line number, and description.
+ This may be followed by a breakpoint or a dead loop.
+
+ Print a message of the form "ASSERT (): \n"
+ to the debug output device. If DEBUG_PROPERTY_ASSERT_BREAKPOINT_ENABLED bit of
+ PcdDebugProperyMask is set then CpuBreakpoint() is called. Otherwise, if
+ DEBUG_PROPERTY_ASSERT_DEADLOOP_ENABLED bit of PcdDebugProperyMask is set then
+ CpuDeadLoop() is called. If neither of these bits are set, then this function
+ returns immediately after the message is printed to the debug output device.
+ DebugAssert() must actively prevent recursion. If DebugAssert() is called while
+ processing another DebugAssert(), then DebugAssert() must return immediately.
+
+ If FileName is NULL, then a string of "(NULL) Filename" is printed.
+ If Description is NULL, then a string of "(NULL) Description" is printed.
+
+ @param FileName The pointer to the name of the source file that generated the assert condition.
+ @param LineNumber The line number in the source file that generated the assert condition
+ @param Description The pointer to the description of the assert condition.
+
+**/
+VOID
+EFIAPI
+DebugAssert (
+ IN CONST CHAR8 *FileName,
+ IN UINTN LineNumber,
+ IN CONST CHAR8 *Description
+ );
+
+/**
+ Fills a target buffer with PcdDebugClearMemoryValue, and returns the target buffer.
+
+ This function fills Length bytes of Buffer with the value specified by
+ PcdDebugClearMemoryValue, and returns Buffer.
+
+ If Buffer is NULL, then ASSERT().
+ If Length is greater than (MAX_ADDRESS - Buffer + 1), then ASSERT().
+
+ @param Buffer The pointer to the target buffer to be filled with PcdDebugClearMemoryValue.
+ @param Length The number of bytes in Buffer to fill with zeros PcdDebugClearMemoryValue.
+
+ @return Buffer The pointer to the target buffer filled with PcdDebugClearMemoryValue.
+
+**/
+VOID *
+EFIAPI
+DebugClearMemory (
+ OUT VOID *Buffer,
+ IN UINTN Length
+ );
+
+/**
+ Returns TRUE if ASSERT() macros are enabled.
+
+ This function returns TRUE if the DEBUG_PROPERTY_DEBUG_ASSERT_ENABLED bit of
+ PcdDebugProperyMask is set. Otherwise, FALSE is returned.
+
+ @retval TRUE The DEBUG_PROPERTY_DEBUG_ASSERT_ENABLED bit of PcdDebugProperyMask is set.
+ @retval FALSE The DEBUG_PROPERTY_DEBUG_ASSERT_ENABLED bit of PcdDebugProperyMask is clear.
+
+**/
+BOOLEAN
+EFIAPI
+DebugAssertEnabled (
+ VOID
+ );
+
+/**
+ Returns TRUE if DEBUG() macros are enabled.
+
+ This function returns TRUE if the DEBUG_PROPERTY_DEBUG_PRINT_ENABLED bit of
+ PcdDebugProperyMask is set. Otherwise, FALSE is returned.
+
+ @retval TRUE The DEBUG_PROPERTY_DEBUG_PRINT_ENABLED bit of PcdDebugProperyMask is set.
+ @retval FALSE The DEBUG_PROPERTY_DEBUG_PRINT_ENABLED bit of PcdDebugProperyMask is clear.
+
+**/
+BOOLEAN
+EFIAPI
+DebugPrintEnabled (
+ VOID
+ );
+
+/**
+ Returns TRUE if DEBUG_CODE() macros are enabled.
+
+ This function returns TRUE if the DEBUG_PROPERTY_DEBUG_CODE_ENABLED bit of
+ PcdDebugProperyMask is set. Otherwise, FALSE is returned.
+
+ @retval TRUE The DEBUG_PROPERTY_DEBUG_CODE_ENABLED bit of PcdDebugProperyMask is set.
+ @retval FALSE The DEBUG_PROPERTY_DEBUG_CODE_ENABLED bit of PcdDebugProperyMask is clear.
+
+**/
+BOOLEAN
+EFIAPI
+DebugCodeEnabled (
+ VOID
+ );
+
+/**
+ Returns TRUE if DEBUG_CLEAR_MEMORY() macro is enabled.
+
+ This function returns TRUE if the DEBUG_PROPERTY_CLEAR_MEMORY_ENABLED bit of
+ PcdDebugProperyMask is set. Otherwise, FALSE is returned.
+
+ @retval TRUE The DEBUG_PROPERTY_CLEAR_MEMORY_ENABLED bit of PcdDebugProperyMask is set.
+ @retval FALSE The DEBUG_PROPERTY_CLEAR_MEMORY_ENABLED bit of PcdDebugProperyMask is clear.
+
+**/
+BOOLEAN
+EFIAPI
+DebugClearMemoryEnabled (
+ VOID
+ );
+
+/**
+ Returns TRUE if any one of the bit is set both in ErrorLevel and PcdFixedDebugPrintErrorLevel.
+
+ This function compares the bit mask of ErrorLevel and PcdFixedDebugPrintErrorLevel.
+
+ @retval TRUE Current ErrorLevel is supported.
+ @retval FALSE Current ErrorLevel is not supported.
+
+**/
+BOOLEAN
+EFIAPI
+DebugPrintLevelEnabled (
+ IN CONST UINTN ErrorLevel
+ );
+
+/**
+ Internal worker macro that calls DebugAssert().
+
+ This macro calls DebugAssert(), passing in the filename, line number, and an
+ expression that evaluated to FALSE.
+
+ @param Expression Boolean expression that evaluated to FALSE
+
+**/
+#if defined (EDKII_UNIT_TEST_FRAMEWORK_ENABLED)
+
+/**
+ Unit test library replacement for DebugAssert() in DebugLib.
+
+ If FileName is NULL, then a string of "(NULL) Filename" is printed.
+ If Description is NULL, then a string of "(NULL) Description" is printed.
+
+ @param FileName The pointer to the name of the source file that generated the assert condition.
+ @param LineNumber The line number in the source file that generated the assert condition
+ @param Description The pointer to the description of the assert condition.
+
+**/
+VOID
+EFIAPI
+UnitTestDebugAssert (
+ IN CONST CHAR8 *FileName,
+ IN UINTN LineNumber,
+ IN CONST CHAR8 *Description
+ );
+
+ #if defined (_ASSERT)
+ #undef _ASSERT
+ #endif
+ #if defined (__clang__) && defined (__FILE_NAME__)
+#define _ASSERT(Expression) UnitTestDebugAssert (__FILE_NAME__, DEBUG_LINE_NUMBER, DEBUG_EXPRESSION_STRING (Expression))
+ #else
+#define _ASSERT(Expression) UnitTestDebugAssert (__FILE__, DEBUG_LINE_NUMBER, DEBUG_EXPRESSION_STRING (Expression))
+ #endif
+#else
+ #if defined (__clang__) && defined (__FILE_NAME__)
+#define _ASSERT(Expression) DebugAssert (__FILE_NAME__, DEBUG_LINE_NUMBER, DEBUG_EXPRESSION_STRING (Expression))
+ #else
+#define _ASSERT(Expression) DebugAssert (__FILE__, DEBUG_LINE_NUMBER, DEBUG_EXPRESSION_STRING (Expression))
+ #endif
+#endif
+
+/**
+ Internal worker macro that calls DebugPrint().
+
+ This macro calls DebugPrint() passing in the debug error level, a format
+ string, and a variable argument list.
+ __VA_ARGS__ is not supported by EBC compiler, Microsoft Visual Studio .NET 2003
+ and Microsoft Windows Server 2003 Driver Development Kit (Microsoft WINDDK) version 3790.1830.
+
+ @param Expression Expression containing an error level, a format string,
+ and a variable argument list based on the format string.
+
+**/
+
+#if !defined (MDE_CPU_EBC) && (!defined (_MSC_VER) || _MSC_VER > 1400)
+#define _DEBUG_PRINT(PrintLevel, ...) \
+ do { \
+ if (DebugPrintLevelEnabled (PrintLevel)) { \
+ DebugPrint (PrintLevel, ##__VA_ARGS__); \
+ } \
+ } while (FALSE)
+#define _DEBUG(Expression) _DEBUG_PRINT Expression
+#else
+#define _DEBUG(Expression) DebugPrint Expression
+#endif
+
+/**
+ Macro that calls DebugAssert() if an expression evaluates to FALSE.
+
+ If MDEPKG_NDEBUG is not defined and the DEBUG_PROPERTY_DEBUG_ASSERT_ENABLED
+ bit of PcdDebugProperyMask is set, then this macro evaluates the Boolean
+ expression specified by Expression. If Expression evaluates to FALSE, then
+ DebugAssert() is called passing in the source filename, source line number,
+ and Expression.
+
+ @param Expression Boolean expression.
+
+**/
+#if !defined (MDEPKG_NDEBUG)
+#define ASSERT(Expression) \
+ do { \
+ if (DebugAssertEnabled ()) { \
+ if (!(Expression)) { \
+ _ASSERT (Expression); \
+ ANALYZER_UNREACHABLE (); \
+ } \
+ } \
+ } while (FALSE)
+#else
+#define ASSERT(Expression)
+#endif
+
+/**
+ Macro that calls DebugPrint().
+
+ If MDEPKG_NDEBUG is not defined and the DEBUG_PROPERTY_DEBUG_PRINT_ENABLED
+ bit of PcdDebugProperyMask is set, then this macro passes Expression to
+ DebugPrint().
+
+ @param Expression Expression containing an error level, a format string,
+ and a variable argument list based on the format string.
+
+
+**/
+#if !defined (MDEPKG_NDEBUG)
+#define DEBUG(Expression) \
+ do { \
+ if (DebugPrintEnabled ()) { \
+ _DEBUG (Expression); \
+ } \
+ } while (FALSE)
+#else
+#define DEBUG(Expression)
+#endif
+
+/**
+ Macro that calls DebugAssert() if an EFI_STATUS evaluates to an error code.
+
+ If MDEPKG_NDEBUG is not defined and the DEBUG_PROPERTY_DEBUG_ASSERT_ENABLED
+ bit of PcdDebugProperyMask is set, then this macro evaluates the EFI_STATUS
+ value specified by StatusParameter. If StatusParameter is an error code,
+ then DebugAssert() is called passing in the source filename, source line
+ number, and StatusParameter.
+
+ @param StatusParameter EFI_STATUS value to evaluate.
+
+**/
+#if !defined (MDEPKG_NDEBUG)
+#define ASSERT_EFI_ERROR(StatusParameter) \
+ do { \
+ if (DebugAssertEnabled ()) { \
+ if (EFI_ERROR (StatusParameter)) { \
+ DEBUG ((DEBUG_ERROR, "\nASSERT_EFI_ERROR (Status = %r)\n", StatusParameter)); \
+ _ASSERT (!EFI_ERROR (StatusParameter)); \
+ } \
+ } \
+ } while (FALSE)
+#else
+#define ASSERT_EFI_ERROR(StatusParameter)
+#endif
+
+/**
+ Macro that calls DebugAssert() if a RETURN_STATUS evaluates to an error code.
+
+ If MDEPKG_NDEBUG is not defined and the DEBUG_PROPERTY_DEBUG_ASSERT_ENABLED
+ bit of PcdDebugProperyMask is set, then this macro evaluates the
+ RETURN_STATUS value specified by StatusParameter. If StatusParameter is an
+ error code, then DebugAssert() is called passing in the source filename,
+ source line number, and StatusParameter.
+
+ @param StatusParameter RETURN_STATUS value to evaluate.
+
+**/
+#if !defined (MDEPKG_NDEBUG)
+#define ASSERT_RETURN_ERROR(StatusParameter) \
+ do { \
+ if (DebugAssertEnabled ()) { \
+ if (RETURN_ERROR (StatusParameter)) { \
+ DEBUG ((DEBUG_ERROR, "\nASSERT_RETURN_ERROR (Status = %r)\n", \
+ StatusParameter)); \
+ _ASSERT (!RETURN_ERROR (StatusParameter)); \
+ } \
+ } \
+ } while (FALSE)
+#else
+#define ASSERT_RETURN_ERROR(StatusParameter)
+#endif
+
+/**
+ Macro that calls DebugAssert() if a protocol is already installed in the
+ handle database.
+
+ If MDEPKG_NDEBUG is defined or the DEBUG_PROPERTY_DEBUG_ASSERT_ENABLED bit
+ of PcdDebugProperyMask is clear, then return.
+
+ If Handle is NULL, then a check is made to see if the protocol specified by Guid
+ is present on any handle in the handle database. If Handle is not NULL, then
+ a check is made to see if the protocol specified by Guid is present on the
+ handle specified by Handle. If the check finds the protocol, then DebugAssert()
+ is called passing in the source filename, source line number, and Guid.
+
+ If Guid is NULL, then ASSERT().
+
+ @param Handle The handle to check for the protocol. This is an optional
+ parameter that may be NULL. If it is NULL, then the entire
+ handle database is searched.
+
+ @param Guid The pointer to a protocol GUID.
+
+**/
+#if !defined (MDEPKG_NDEBUG)
+#define ASSERT_PROTOCOL_ALREADY_INSTALLED(Handle, Guid) \
+ do { \
+ if (DebugAssertEnabled ()) { \
+ VOID *Instance; \
+ ASSERT (Guid != NULL); \
+ if (Handle == NULL) { \
+ if (!EFI_ERROR (gBS->LocateProtocol ((EFI_GUID *)Guid, NULL, &Instance))) { \
+ _ASSERT (Guid already installed in database); \
+ } \
+ } else { \
+ if (!EFI_ERROR (gBS->HandleProtocol (Handle, (EFI_GUID *)Guid, &Instance))) { \
+ _ASSERT (Guid already installed on Handle); \
+ } \
+ } \
+ } \
+ } while (FALSE)
+#else
+#define ASSERT_PROTOCOL_ALREADY_INSTALLED(Handle, Guid)
+#endif
+
+/**
+ Macro that marks the beginning of debug source code.
+
+ If the DEBUG_PROPERTY_DEBUG_CODE_ENABLED bit of PcdDebugProperyMask is set,
+ then this macro marks the beginning of source code that is included in a module.
+ Otherwise, the source lines between DEBUG_CODE_BEGIN() and DEBUG_CODE_END()
+ are not included in a module.
+
+**/
+#define DEBUG_CODE_BEGIN() do { if (DebugCodeEnabled ()) { UINT8 __DebugCodeLocal
+
+/**
+ The macro that marks the end of debug source code.
+
+ If the DEBUG_PROPERTY_DEBUG_CODE_ENABLED bit of PcdDebugProperyMask is set,
+ then this macro marks the end of source code that is included in a module.
+ Otherwise, the source lines between DEBUG_CODE_BEGIN() and DEBUG_CODE_END()
+ are not included in a module.
+
+**/
+#define DEBUG_CODE_END() __DebugCodeLocal = 0; __DebugCodeLocal++; } } while (FALSE)
+
+/**
+ The macro that declares a section of debug source code.
+
+ If the DEBUG_PROPERTY_DEBUG_CODE_ENABLED bit of PcdDebugProperyMask is set,
+ then the source code specified by Expression is included in a module.
+ Otherwise, the source specified by Expression is not included in a module.
+
+**/
+#define DEBUG_CODE(Expression) \
+ DEBUG_CODE_BEGIN (); \
+ Expression \
+ DEBUG_CODE_END ()
+
+/**
+ The macro that calls DebugClearMemory() to clear a buffer to a default value.
+
+ If the DEBUG_PROPERTY_CLEAR_MEMORY_ENABLED bit of PcdDebugProperyMask is set,
+ then this macro calls DebugClearMemory() passing in Address and Length.
+
+ @param Address The pointer to a buffer.
+ @param Length The number of bytes in the buffer to set.
+
+**/
+#define DEBUG_CLEAR_MEMORY(Address, Length) \
+ do { \
+ if (DebugClearMemoryEnabled ()) { \
+ DebugClearMemory (Address, Length); \
+ } \
+ } while (FALSE)
+
+/**
+ Macro that calls DebugAssert() if the containing record does not have a
+ matching signature. If the signatures matches, then a pointer to the data
+ structure that contains a specified field of that data structure is returned.
+ This is a lightweight method hide information by placing a public data
+ structure inside a larger private data structure and using a pointer to the
+ public data structure to retrieve a pointer to the private data structure.
+
+ If MDEPKG_NDEBUG is defined or the DEBUG_PROPERTY_DEBUG_ASSERT_ENABLED bit
+ of PcdDebugProperyMask is clear, then this macro computes the offset, in bytes,
+ of the field specified by Field from the beginning of the data structure specified
+ by TYPE. This offset is subtracted from Record, and is used to return a pointer
+ to a data structure of the type specified by TYPE.
+
+ If MDEPKG_NDEBUG is not defined and the DEBUG_PROPERTY_DEBUG_ASSERT_ENABLED bit
+ of PcdDebugProperyMask is set, then this macro computes the offset, in bytes,
+ of field specified by Field from the beginning of the data structure specified
+ by TYPE. This offset is subtracted from Record, and is used to compute a pointer
+ to a data structure of the type specified by TYPE. The Signature field of the
+ data structure specified by TYPE is compared to TestSignature. If the signatures
+ match, then a pointer to the pointer to a data structure of the type specified by
+ TYPE is returned. If the signatures do not match, then DebugAssert() is called
+ with a description of "CR has a bad signature" and Record is returned.
+
+ If the data type specified by TYPE does not contain the field specified by Field,
+ then the module will not compile.
+
+ If TYPE does not contain a field called Signature, then the module will not
+ compile.
+
+ @param Record The pointer to the field specified by Field within a data
+ structure of type TYPE.
+
+ @param TYPE The name of the data structure type to return This
+ data structure must contain the field specified by Field.
+
+ @param Field The name of the field in the data structure specified
+ by TYPE to which Record points.
+
+ @param TestSignature The 32-bit signature value to match.
+
+**/
+#if !defined (MDEPKG_NDEBUG)
+#define CR(Record, TYPE, Field, TestSignature) \
+ (DebugAssertEnabled () && (BASE_CR (Record, TYPE, Field)->Signature != TestSignature)) ? \
+ (TYPE *) (_ASSERT (CR has Bad Signature), Record) : \
+ BASE_CR (Record, TYPE, Field)
+#else
+#define CR(Record, TYPE, Field, TestSignature) \
+ BASE_CR (Record, TYPE, Field)
+#endif
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/DebugPrintErrorLevelLib.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/DebugPrintErrorLevelLib.h
new file mode 100644
index 0000000000..bddf2252a5
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/DebugPrintErrorLevelLib.h
@@ -0,0 +1,39 @@
+/** @file
+ Debug Print Error Level Library class
+
+ Copyright (c) 2011 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _DEBUG_PRINT_ERROR_LEVEL_LIB_H_
+#define _DEBUG_PRINT_ERROR_LEVEL_LIB_H_
+
+/**
+ Returns the debug print error level mask for the current module.
+
+ @return Debug print error level mask for the current module.
+
+**/
+UINT32
+EFIAPI
+GetDebugPrintErrorLevel (
+ VOID
+ );
+
+/**
+ Sets the global debug print error level mask fpr the entire platform.
+
+ @param ErrorLevel Global debug print error level
+
+ @retval TRUE The debug print error level mask was successfully set.
+ @retval FALSE The debug print error level mask could not be set.
+
+**/
+BOOLEAN
+EFIAPI
+SetDebugPrintErrorLevel (
+ UINT32 ErrorLevel
+ );
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/DevicePathLib.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/DevicePathLib.h
new file mode 100644
index 0000000000..36469687c7
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/DevicePathLib.h
@@ -0,0 +1,561 @@
+/** @file
+ Provides library functions to construct and parse UEFI Device Paths.
+
+ This library provides defines, macros, and functions to help create and parse
+ EFI_DEVICE_PATH_PROTOCOL structures.
+
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __DEVICE_PATH_LIB_H__
+#define __DEVICE_PATH_LIB_H__
+
+#define END_DEVICE_PATH_LENGTH (sizeof (EFI_DEVICE_PATH_PROTOCOL))
+
+/**
+ Determine whether a given device path is valid.
+
+ @param DevicePath A pointer to a device path data structure.
+ @param MaxSize The maximum size of the device path data structure.
+
+ @retval TRUE DevicePath is valid.
+ @retval FALSE DevicePath is NULL.
+ @retval FALSE Maxsize is less than sizeof(EFI_DEVICE_PATH_PROTOCOL).
+ @retval FALSE The length of any node node in the DevicePath is less
+ than sizeof (EFI_DEVICE_PATH_PROTOCOL).
+ @retval FALSE If MaxSize is not zero, the size of the DevicePath
+ exceeds MaxSize.
+ @retval FALSE If PcdMaximumDevicePathNodeCount is not zero, the node
+ count of the DevicePath exceeds PcdMaximumDevicePathNodeCount.
+**/
+BOOLEAN
+EFIAPI
+IsDevicePathValid (
+ IN CONST EFI_DEVICE_PATH_PROTOCOL *DevicePath,
+ IN UINTN MaxSize
+ );
+
+/**
+ Returns the Type field of a device path node.
+
+ Returns the Type field of the device path node specified by Node.
+
+ If Node is NULL, then ASSERT().
+
+ @param Node A pointer to a device path node data structure.
+
+ @return The Type field of the device path node specified by Node.
+
+**/
+UINT8
+EFIAPI
+DevicePathType (
+ IN CONST VOID *Node
+ );
+
+/**
+ Returns the SubType field of a device path node.
+
+ Returns the SubType field of the device path node specified by Node.
+
+ If Node is NULL, then ASSERT().
+
+ @param Node A pointer to a device path node data structure.
+
+ @return The SubType field of the device path node specified by Node.
+
+**/
+UINT8
+EFIAPI
+DevicePathSubType (
+ IN CONST VOID *Node
+ );
+
+/**
+ Returns the 16-bit Length field of a device path node.
+
+ Returns the 16-bit Length field of the device path node specified by Node.
+ Node is not required to be aligned on a 16-bit boundary, so it is recommended
+ that a function such as ReadUnaligned16() be used to extract the contents of
+ the Length field.
+
+ If Node is NULL, then ASSERT().
+
+ @param Node A pointer to a device path node data structure.
+
+ @return The 16-bit Length field of the device path node specified by Node.
+
+**/
+UINTN
+EFIAPI
+DevicePathNodeLength (
+ IN CONST VOID *Node
+ );
+
+/**
+ Returns a pointer to the next node in a device path.
+
+ Returns a pointer to the device path node that follows the device path node specified by Node.
+
+ If Node is NULL, then ASSERT().
+
+ @param Node A pointer to a device path node data structure.
+
+ @return a pointer to the device path node that follows the device path node specified by Node.
+
+**/
+EFI_DEVICE_PATH_PROTOCOL *
+EFIAPI
+NextDevicePathNode (
+ IN CONST VOID *Node
+ );
+
+/**
+ Determines if a device path node is an end node of a device path.
+ This includes nodes that are the end of a device path instance and nodes that
+ are the end of an entire device path.
+
+ Determines if the device path node specified by Node is an end node of a device path.
+ This includes nodes that are the end of a device path instance and nodes that are the
+ end of an entire device path. If Node represents an end node of a device path,
+ then TRUE is returned. Otherwise, FALSE is returned.
+
+ If Node is NULL, then ASSERT().
+
+ @param Node A pointer to a device path node data structure.
+
+ @retval TRUE The device path node specified by Node is an end node of a device path.
+ @retval FALSE The device path node specified by Node is not an end node of a device path.
+
+**/
+BOOLEAN
+EFIAPI
+IsDevicePathEndType (
+ IN CONST VOID *Node
+ );
+
+/**
+ Determines if a device path node is an end node of an entire device path.
+
+ Determines if a device path node specified by Node is an end node of an entire device path.
+ If Node represents the end of an entire device path, then TRUE is returned.
+ Otherwise, FALSE is returned.
+
+ If Node is NULL, then ASSERT().
+
+ @param Node A pointer to a device path node data structure.
+
+ @retval TRUE The device path node specified by Node is the end of an entire device path.
+ @retval FALSE The device path node specified by Node is not the end of an entire device path.
+
+**/
+BOOLEAN
+EFIAPI
+IsDevicePathEnd (
+ IN CONST VOID *Node
+ );
+
+/**
+ Determines if a device path node is an end node of a device path instance.
+
+ Determines if a device path node specified by Node is an end node of a device path instance.
+ If Node represents the end of a device path instance, then TRUE is returned.
+ Otherwise, FALSE is returned.
+
+ If Node is NULL, then ASSERT().
+
+ @param Node A pointer to a device path node data structure.
+
+ @retval TRUE The device path node specified by Node is the end of a device path instance.
+ @retval FALSE The device path node specified by Node is not the end of a device path instance.
+
+**/
+BOOLEAN
+EFIAPI
+IsDevicePathEndInstance (
+ IN CONST VOID *Node
+ );
+
+/**
+ Sets the length, in bytes, of a device path node.
+
+ Sets the length of the device path node specified by Node to the value specified
+ by NodeLength. NodeLength is returned. Node is not required to be aligned on
+ a 16-bit boundary, so it is recommended that a function such as WriteUnaligned16()
+ be used to set the contents of the Length field.
+
+ If Node is NULL, then ASSERT().
+ If NodeLength >= 0x10000, then ASSERT().
+ If NodeLength < sizeof (EFI_DEVICE_PATH_PROTOCOL), then ASSERT().
+
+ @param Node A pointer to a device path node data structure.
+ @param Length The length, in bytes, of the device path node.
+
+ @return Length
+
+**/
+UINT16
+EFIAPI
+SetDevicePathNodeLength (
+ IN OUT VOID *Node,
+ IN UINTN Length
+ );
+
+/**
+ Fills in all the fields of a device path node that is the end of an entire device path.
+
+ Fills in all the fields of a device path node specified by Node so Node represents
+ the end of an entire device path. The Type field of Node is set to
+ END_DEVICE_PATH_TYPE, the SubType field of Node is set to
+ END_ENTIRE_DEVICE_PATH_SUBTYPE, and the Length field of Node is set to
+ END_DEVICE_PATH_LENGTH. Node is not required to be aligned on a 16-bit boundary,
+ so it is recommended that a function such as WriteUnaligned16() be used to set
+ the contents of the Length field.
+
+ If Node is NULL, then ASSERT().
+
+ @param Node A pointer to a device path node data structure.
+
+**/
+VOID
+EFIAPI
+SetDevicePathEndNode (
+ OUT VOID *Node
+ );
+
+/**
+ Returns the size of a device path in bytes.
+
+ This function returns the size, in bytes, of the device path data structure
+ specified by DevicePath including the end of device path node.
+ If DevicePath is NULL or invalid, then 0 is returned.
+
+ @param DevicePath A pointer to a device path data structure.
+
+ @retval 0 If DevicePath is NULL or invalid.
+ @retval Others The size of a device path in bytes.
+
+**/
+UINTN
+EFIAPI
+GetDevicePathSize (
+ IN CONST EFI_DEVICE_PATH_PROTOCOL *DevicePath
+ );
+
+/**
+ Creates a new copy of an existing device path.
+
+ This function allocates space for a new copy of the device path specified by DevicePath. If
+ DevicePath is NULL, then NULL is returned. If the memory is successfully allocated, then the
+ contents of DevicePath are copied to the newly allocated buffer, and a pointer to that buffer
+ is returned. Otherwise, NULL is returned.
+ The memory for the new device path is allocated from EFI boot services memory.
+ It is the responsibility of the caller to free the memory allocated.
+
+ @param DevicePath A pointer to a device path data structure.
+
+ @retval NULL DevicePath is NULL or invalid.
+ @retval Others A pointer to the duplicated device path.
+
+**/
+EFI_DEVICE_PATH_PROTOCOL *
+EFIAPI
+DuplicateDevicePath (
+ IN CONST EFI_DEVICE_PATH_PROTOCOL *DevicePath
+ );
+
+/**
+ Creates a new device path by appending a second device path to a first device path.
+
+ This function creates a new device path by appending a copy of SecondDevicePath to a copy of
+ FirstDevicePath in a newly allocated buffer. Only the end-of-device-path device node from
+ SecondDevicePath is retained. The newly created device path is returned.
+ If FirstDevicePath is NULL, then it is ignored, and a duplicate of SecondDevicePath is returned.
+ If SecondDevicePath is NULL, then it is ignored, and a duplicate of FirstDevicePath is returned.
+ If both FirstDevicePath and SecondDevicePath are NULL, then a copy of an end-of-device-path is
+ returned.
+ If there is not enough memory for the newly allocated buffer, then NULL is returned.
+ The memory for the new device path is allocated from EFI boot services memory. It is the
+ responsibility of the caller to free the memory allocated.
+
+ @param FirstDevicePath A pointer to a device path data structure.
+ @param SecondDevicePath A pointer to a device path data structure.
+
+ @retval NULL If there is not enough memory for the newly allocated buffer.
+ @retval NULL If FirstDevicePath or SecondDevicePath is invalid.
+ @retval Others A pointer to the new device path if success.
+ Or a copy an end-of-device-path if both FirstDevicePath and SecondDevicePath are NULL.
+
+**/
+EFI_DEVICE_PATH_PROTOCOL *
+EFIAPI
+AppendDevicePath (
+ IN CONST EFI_DEVICE_PATH_PROTOCOL *FirstDevicePath OPTIONAL,
+ IN CONST EFI_DEVICE_PATH_PROTOCOL *SecondDevicePath OPTIONAL
+ );
+
+/**
+ Creates a new path by appending the device node to the device path.
+
+ This function creates a new device path by appending a copy of the device node specified by
+ DevicePathNode to a copy of the device path specified by DevicePath in an allocated buffer.
+ The end-of-device-path device node is moved after the end of the appended device node.
+ If DevicePathNode is NULL then a copy of DevicePath is returned.
+ If DevicePath is NULL then a copy of DevicePathNode, followed by an end-of-device path device
+ node is returned.
+ If both DevicePathNode and DevicePath are NULL then a copy of an end-of-device-path device node
+ is returned.
+ If there is not enough memory to allocate space for the new device path, then NULL is returned.
+ The memory is allocated from EFI boot services memory. It is the responsibility of the caller to
+ free the memory allocated.
+
+ @param DevicePath A pointer to a device path data structure.
+ @param DevicePathNode A pointer to a single device path node.
+
+ @retval NULL There is not enough memory for the new device path.
+ @retval Others A pointer to the new device path if success.
+ A copy of DevicePathNode followed by an end-of-device-path node
+ if both FirstDevicePath and SecondDevicePath are NULL.
+ A copy of an end-of-device-path node if both FirstDevicePath and SecondDevicePath are NULL.
+
+**/
+EFI_DEVICE_PATH_PROTOCOL *
+EFIAPI
+AppendDevicePathNode (
+ IN CONST EFI_DEVICE_PATH_PROTOCOL *DevicePath OPTIONAL,
+ IN CONST EFI_DEVICE_PATH_PROTOCOL *DevicePathNode OPTIONAL
+ );
+
+/**
+ Creates a new device path by appending the specified device path instance to the specified device
+ path.
+
+ This function creates a new device path by appending a copy of the device path instance specified
+ by DevicePathInstance to a copy of the device path secified by DevicePath in a allocated buffer.
+ The end-of-device-path device node is moved after the end of the appended device path instance
+ and a new end-of-device-path-instance node is inserted between.
+ If DevicePath is NULL, then a copy if DevicePathInstance is returned.
+ If DevicePathInstance is NULL, then NULL is returned.
+ If DevicePath or DevicePathInstance is invalid, then NULL is returned.
+ If there is not enough memory to allocate space for the new device path, then NULL is returned.
+ The memory is allocated from EFI boot services memory. It is the responsibility of the caller to
+ free the memory allocated.
+
+ @param DevicePath A pointer to a device path data structure.
+ @param DevicePathInstance A pointer to a device path instance.
+
+ @return A pointer to the new device path.
+
+**/
+EFI_DEVICE_PATH_PROTOCOL *
+EFIAPI
+AppendDevicePathInstance (
+ IN CONST EFI_DEVICE_PATH_PROTOCOL *DevicePath OPTIONAL,
+ IN CONST EFI_DEVICE_PATH_PROTOCOL *DevicePathInstance OPTIONAL
+ );
+
+/**
+ Creates a copy of the current device path instance and returns a pointer to the next device path
+ instance.
+
+ This function creates a copy of the current device path instance. It also updates DevicePath to
+ point to the next device path instance in the device path (or NULL if no more) and updates Size
+ to hold the size of the device path instance copy.
+ If DevicePath is NULL, then NULL is returned.
+ If DevicePath points to a invalid device path, then NULL is returned.
+ If there is not enough memory to allocate space for the new device path, then NULL is returned.
+ The memory is allocated from EFI boot services memory. It is the responsibility of the caller to
+ free the memory allocated.
+ If Size is NULL, then ASSERT().
+
+ @param DevicePath On input, this holds the pointer to the current device path
+ instance. On output, this holds the pointer to the next device
+ path instance or NULL if there are no more device path
+ instances in the device path pointer to a device path data
+ structure.
+ @param Size On output, this holds the size of the device path instance, in
+ bytes or zero, if DevicePath is NULL.
+
+ @return A pointer to the current device path instance.
+
+**/
+EFI_DEVICE_PATH_PROTOCOL *
+EFIAPI
+GetNextDevicePathInstance (
+ IN OUT EFI_DEVICE_PATH_PROTOCOL **DevicePath,
+ OUT UINTN *Size
+ );
+
+/**
+ Creates a device node.
+
+ This function creates a new device node in a newly allocated buffer of size NodeLength and
+ initializes the device path node header with NodeType and NodeSubType. The new device path node
+ is returned.
+ If NodeLength is smaller than a device path header, then NULL is returned.
+ If there is not enough memory to allocate space for the new device path, then NULL is returned.
+ The memory is allocated from EFI boot services memory. It is the responsibility of the caller to
+ free the memory allocated.
+
+ @param NodeType The device node type for the new device node.
+ @param NodeSubType The device node sub-type for the new device node.
+ @param NodeLength The length of the new device node.
+
+ @return The new device path.
+
+**/
+EFI_DEVICE_PATH_PROTOCOL *
+EFIAPI
+CreateDeviceNode (
+ IN UINT8 NodeType,
+ IN UINT8 NodeSubType,
+ IN UINT16 NodeLength
+ );
+
+/**
+ Determines if a device path is single or multi-instance.
+
+ This function returns TRUE if the device path specified by DevicePath is multi-instance.
+ Otherwise, FALSE is returned.
+ If DevicePath is NULL or invalid, then FALSE is returned.
+
+ @param DevicePath A pointer to a device path data structure.
+
+ @retval TRUE DevicePath is multi-instance.
+ @retval FALSE DevicePath is not multi-instance, or DevicePath is NULL or invalid.
+
+**/
+BOOLEAN
+EFIAPI
+IsDevicePathMultiInstance (
+ IN CONST EFI_DEVICE_PATH_PROTOCOL *DevicePath
+ );
+
+/**
+ Retrieves the device path protocol from a handle.
+
+ This function returns the device path protocol from the handle specified by Handle. If Handle is
+ NULL or Handle does not contain a device path protocol, then NULL is returned.
+
+ @param Handle The handle from which to retrieve the device path protocol.
+
+ @return The device path protocol from the handle specified by Handle.
+
+**/
+EFI_DEVICE_PATH_PROTOCOL *
+EFIAPI
+DevicePathFromHandle (
+ IN EFI_HANDLE Handle
+ );
+
+/**
+ Allocates a device path for a file and appends it to an existing device path.
+
+ If Device is a valid device handle that contains a device path protocol, then a device path for
+ the file specified by FileName is allocated and appended to the device path associated with the
+ handle Device. The allocated device path is returned. If Device is NULL or Device is a handle
+ that does not support the device path protocol, then a device path containing a single device
+ path node for the file specified by FileName is allocated and returned.
+ The memory for the new device path is allocated from EFI boot services memory. It is the responsibility
+ of the caller to free the memory allocated.
+
+ If FileName is NULL, then ASSERT().
+ If FileName is not aligned on a 16-bit boundary, then ASSERT().
+
+ @param Device A pointer to a device handle. This parameter is optional and
+ may be NULL.
+ @param FileName A pointer to a Null-terminated Unicode string.
+
+ @return The allocated device path.
+
+**/
+EFI_DEVICE_PATH_PROTOCOL *
+EFIAPI
+FileDevicePath (
+ IN EFI_HANDLE Device OPTIONAL,
+ IN CONST CHAR16 *FileName
+ );
+
+/**
+ Converts a device path to its text representation.
+
+ @param DevicePath A Pointer to the device to be converted.
+ @param DisplayOnly If DisplayOnly is TRUE, then the shorter text representation
+ of the display node is used, where applicable. If DisplayOnly
+ is FALSE, then the longer text representation of the display node
+ is used.
+ @param AllowShortcuts If AllowShortcuts is TRUE, then the shortcut forms of text
+ representation for a device node can be used, where applicable.
+
+ @return A pointer to the allocated text representation of the device path or
+ NULL if DeviceNode is NULL or there was insufficient memory.
+
+**/
+CHAR16 *
+EFIAPI
+ConvertDevicePathToText (
+ IN CONST EFI_DEVICE_PATH_PROTOCOL *DevicePath,
+ IN BOOLEAN DisplayOnly,
+ IN BOOLEAN AllowShortcuts
+ );
+
+/**
+ Converts a device node to its string representation.
+
+ @param DeviceNode A Pointer to the device node to be converted.
+ @param DisplayOnly If DisplayOnly is TRUE, then the shorter text representation
+ of the display node is used, where applicable. If DisplayOnly
+ is FALSE, then the longer text representation of the display node
+ is used.
+ @param AllowShortcuts If AllowShortcuts is TRUE, then the shortcut forms of text
+ representation for a device node can be used, where applicable.
+
+ @return A pointer to the allocated text representation of the device node or NULL if DeviceNode
+ is NULL or there was insufficient memory.
+
+**/
+CHAR16 *
+EFIAPI
+ConvertDeviceNodeToText (
+ IN CONST EFI_DEVICE_PATH_PROTOCOL *DeviceNode,
+ IN BOOLEAN DisplayOnly,
+ IN BOOLEAN AllowShortcuts
+ );
+
+/**
+ Convert text to the binary representation of a device node.
+
+ @param TextDeviceNode TextDeviceNode points to the text representation of a device
+ node. Conversion starts with the first character and continues
+ until the first non-device node character.
+
+ @return A pointer to the EFI device node or NULL if TextDeviceNode is NULL or there was
+ insufficient memory or text unsupported.
+
+**/
+EFI_DEVICE_PATH_PROTOCOL *
+EFIAPI
+ConvertTextToDeviceNode (
+ IN CONST CHAR16 *TextDeviceNode
+ );
+
+/**
+ Convert text to the binary representation of a device path.
+
+ @param TextDevicePath TextDevicePath points to the text representation of a device
+ path. Conversion starts with the first character and continues
+ until the first non-device node character.
+
+ @return A pointer to the allocated device path or NULL if TextDeviceNode is NULL or
+ there was insufficient memory.
+
+**/
+EFI_DEVICE_PATH_PROTOCOL *
+EFIAPI
+ConvertTextToDevicePath (
+ IN CONST CHAR16 *TextDevicePath
+ );
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/DxeCoreEntryPoint.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/DxeCoreEntryPoint.h
new file mode 100644
index 0000000000..d7eba1b843
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/DxeCoreEntryPoint.h
@@ -0,0 +1,89 @@
+/** @file
+ Module entry point library for DXE core.
+
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __MODULE_ENTRY_POINT_H__
+#define __MODULE_ENTRY_POINT_H__
+
+///
+/// Global variable that contains a pointer to the Hob List passed into the DXE Core entry point.
+///
+extern VOID *gHobList;
+
+/**
+ The entry point of PE/COFF Image for the DXE Core.
+
+ This function is the entry point for the DXE Core. This function is required to call
+ ProcessModuleEntryPointList() and ProcessModuleEntryPointList() is never expected to return.
+ The DXE Core is responsible for calling ProcessLibraryConstructorList() as soon as the EFI
+ System Table and the image handle for the DXE Core itself have been established.
+ If ProcessModuleEntryPointList() returns, then ASSERT() and halt the system.
+
+ @param HobStart Pointer to the beginning of the HOB List passed in from the PEI Phase.
+
+**/
+VOID
+EFIAPI
+_ModuleEntryPoint (
+ IN VOID *HobStart
+ );
+
+/**
+ Required by the EBC compiler and identical in functionality to _ModuleEntryPoint().
+
+ This function is required to call _ModuleEntryPoint() passing in HobStart.
+
+ @param HobStart Pointer to the beginning of the HOB List passed in from the PEI Phase.
+
+**/
+VOID
+EFIAPI
+EfiMain (
+ IN VOID *HobStart
+ );
+
+/**
+ Autogenerated function that calls the library constructors for all of the module's dependent libraries.
+
+ This function must be called by _ModuleEntryPoint().
+ This function calls the set of library constructors for the set of library instances
+ that a module depends on. This includes library instances that a module depends on
+ directly and library instances that a module depends on indirectly through other
+ libraries. This function is autogenerated by build tools and those build tools are
+ responsible for collecting the set of library instances, determine which ones have
+ constructors, and calling the library constructors in the proper order based upon
+ each of the library instances own dependencies.
+
+ @param ImageHandle The image handle of the DXE Core.
+ @param SystemTable A pointer to the EFI System Table.
+
+**/
+VOID
+EFIAPI
+ProcessLibraryConstructorList (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ );
+
+/**
+ Autogenerated function that calls a set of module entry points.
+
+ This function must be called by _ModuleEntryPoint().
+ This function calls the set of module entry points.
+ This function is autogenerated by build tools and those build tools are responsible
+ for collecting the module entry points and calling them in a specified order.
+
+ @param HobStart Pointer to the beginning of the HOB List passed in from the PEI Phase.
+
+**/
+VOID
+EFIAPI
+ProcessModuleEntryPointList (
+ IN VOID *HobStart
+ );
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/DxeServicesLib.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/DxeServicesLib.h
new file mode 100644
index 0000000000..c24ec83316
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/DxeServicesLib.h
@@ -0,0 +1,322 @@
+/** @file
+ MDE DXE Services Library provides functions that simplify the development of DXE Drivers.
+ These functions help access data from sections of FFS files or from file path.
+
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+(C) Copyright 2015 Hewlett Packard Enterprise Development LP
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __DXE_SERVICES_LIB_H__
+#define __DXE_SERVICES_LIB_H__
+
+/**
+ Searches all the available firmware volumes and returns the first matching FFS section.
+
+ This function searches all the firmware volumes for FFS files with FV file type specified by FileType
+ The order that the firmware volumes is searched is not deterministic. For each available FV a search
+ is made for FFS file of type FileType. If the FV contains more than one FFS file with the same FileType,
+ the FileInstance instance will be the matched FFS file. For each FFS file found a search
+ is made for FFS sections of type SectionType. If the FFS file contains at least SectionInstance instances
+ of the FFS section specified by SectionType, then the SectionInstance instance is returned in Buffer.
+ Buffer is allocated using AllocatePool(), and the size of the allocated buffer is returned in Size.
+ It is the caller's responsibility to use FreePool() to free the allocated buffer.
+ See EFI_FIRMWARE_VOLUME2_PROTOCOL.ReadSection() for details on how sections
+ are retrieved from an FFS file based on SectionType and SectionInstance.
+
+ If SectionType is EFI_SECTION_TE, and the search with an FFS file fails,
+ the search will be retried with a section type of EFI_SECTION_PE32.
+ This function must be called with a TPL <= TPL_NOTIFY.
+
+ If Buffer is NULL, then ASSERT().
+ If Size is NULL, then ASSERT().
+
+ @param FileType Indicates the FV file type to search for within all available FVs.
+ @param FileInstance Indicates which file instance within all available FVs specified by FileType.
+ FileInstance starts from zero.
+ @param SectionType Indicates the FFS section type to search for within the FFS file
+ specified by FileType with FileInstance.
+ @param SectionInstance Indicates which section instance within the FFS file
+ specified by FileType with FileInstance to retrieve. SectionInstance starts from zero.
+ @param Buffer On output, a pointer to a callee allocated buffer containing the FFS file section that was found.
+ Is it the caller's responsibility to free this buffer using FreePool().
+ @param Size On output, a pointer to the size, in bytes, of Buffer.
+
+ @retval EFI_SUCCESS The specified FFS section was returned.
+ @retval EFI_NOT_FOUND The specified FFS section could not be found.
+ @retval EFI_OUT_OF_RESOURCES There are not enough resources available to retrieve the matching FFS section.
+ @retval EFI_DEVICE_ERROR The FFS section could not be retrieves due to a device error.
+ @retval EFI_ACCESS_DENIED The FFS section could not be retrieves because the firmware volume that
+ contains the matching FFS section does not allow reads.
+**/
+EFI_STATUS
+EFIAPI
+GetSectionFromAnyFvByFileType (
+ IN EFI_FV_FILETYPE FileType,
+ IN UINTN FileInstance,
+ IN EFI_SECTION_TYPE SectionType,
+ IN UINTN SectionInstance,
+ OUT VOID **Buffer,
+ OUT UINTN *Size
+ );
+
+/**
+ Searches all the available firmware volumes and returns the first matching FFS section.
+
+ This function searches all the firmware volumes for FFS files with an FFS filename specified by NameGuid.
+ The order in which the firmware volumes are searched is not deterministic. For each FFS file found, a search
+ is made for FFS sections of type SectionType. If the FFS file contains at least SectionInstance instances
+ of the FFS section specified by SectionType, then the SectionInstance instance is returned in Buffer.
+ Buffer is allocated using AllocatePool(), and the size of the allocated buffer is returned in Size.
+ It is the caller's responsibility to use FreePool() to free the allocated buffer.
+ See EFI_FIRMWARE_VOLUME2_PROTOCOL.ReadSection() for details on how sections
+ are retrieved from an FFS file based on SectionType and SectionInstance.
+
+ If SectionType is EFI_SECTION_TE, and the search with an FFS file fails,
+ the search will be retried with a section type of EFI_SECTION_PE32.
+ This function must be called with a TPL <= TPL_NOTIFY.
+
+ If NameGuid is NULL, then ASSERT().
+ If Buffer is NULL, then ASSERT().
+ If Size is NULL, then ASSERT().
+
+
+ @param NameGuid A pointer to to the FFS filename GUID to search for
+ within any of the firmware volumes in the platform.
+ @param SectionType Indicates the FFS section type to search for within
+ the FFS file specified by NameGuid.
+ @param SectionInstance Indicates which section instance within the FFS file
+ specified by NameGuid to retrieve.
+ @param Buffer On output, a pointer to a callee-allocated buffer
+ containing the FFS file section that was found.
+ It is the caller's responsibility to free this
+ buffer using FreePool().
+ @param Size On output, a pointer to the size, in bytes, of Buffer.
+
+ @retval EFI_SUCCESS The specified FFS section was returned.
+ @retval EFI_NOT_FOUND The specified FFS section could not be found.
+ @retval EFI_OUT_OF_RESOURCES There are not enough resources available to retrieve
+ the matching FFS section.
+ @retval EFI_DEVICE_ERROR The FFS section could not be retrieves due to a
+ device error.
+ @retval EFI_ACCESS_DENIED The FFS section could not be retrieves because the
+ firmware volume that contains the matching FFS
+ section does not allow reads.
+**/
+EFI_STATUS
+EFIAPI
+GetSectionFromAnyFv (
+ IN CONST EFI_GUID *NameGuid,
+ IN EFI_SECTION_TYPE SectionType,
+ IN UINTN SectionInstance,
+ OUT VOID **Buffer,
+ OUT UINTN *Size
+ );
+
+/**
+ Searches the firmware volume that the currently executing module was loaded from and returns the first matching FFS section.
+
+ This function searches the firmware volume that the currently executing module was loaded
+ from for an FFS file with an FFS filename specified by NameGuid. If the FFS file is found, a search
+ is made for FFS sections of type SectionType. If the FFS file contains at least SectionInstance
+ instances of the FFS section specified by SectionType, then the SectionInstance instance is returned in Buffer.
+ Buffer is allocated using AllocatePool(), and the size of the allocated buffer is returned in Size.
+ It is the caller's responsibility to use FreePool() to free the allocated buffer.
+ See EFI_FIRMWARE_VOLUME2_PROTOCOL.ReadSection() for details on how sections are retrieved from
+ an FFS file based on SectionType and SectionInstance.
+
+ If the currently executing module was not loaded from a firmware volume, then EFI_NOT_FOUND is returned.
+ If SectionType is EFI_SECTION_TE, and the search with an FFS file fails,
+ the search will be retried with a section type of EFI_SECTION_PE32.
+
+ This function must be called with a TPL <= TPL_NOTIFY.
+ If NameGuid is NULL, then ASSERT().
+ If Buffer is NULL, then ASSERT().
+ If Size is NULL, then ASSERT().
+
+ @param NameGuid A pointer to to the FFS filename GUID to search for
+ within the firmware volumes that the currently
+ executing module was loaded from.
+ @param SectionType Indicates the FFS section type to search for within
+ the FFS file specified by NameGuid.
+ @param SectionInstance Indicates which section instance within the FFS
+ file specified by NameGuid to retrieve.
+ @param Buffer On output, a pointer to a callee allocated buffer
+ containing the FFS file section that was found.
+ It is the caller's responsibility to free this buffer
+ using FreePool().
+ @param Size On output, a pointer to the size, in bytes, of Buffer.
+
+
+ @retval EFI_SUCCESS The specified FFS section was returned.
+ @retval EFI_NOT_FOUND The specified FFS section could not be found.
+ @retval EFI_OUT_OF_RESOURCES There are not enough resources available to retrieve
+ the matching FFS section.
+ @retval EFI_DEVICE_ERROR The FFS section could not be retrieves due to a
+ device error.
+ @retval EFI_ACCESS_DENIED The FFS section could not be retrieves because the
+ firmware volume that contains the matching FFS
+ section does not allow reads.
+**/
+EFI_STATUS
+EFIAPI
+GetSectionFromFv (
+ IN CONST EFI_GUID *NameGuid,
+ IN EFI_SECTION_TYPE SectionType,
+ IN UINTN SectionInstance,
+ OUT VOID **Buffer,
+ OUT UINTN *Size
+ );
+
+/**
+ Searches the FFS file the currently executing module was loaded from and returns the first matching FFS section.
+
+ This function searches the FFS file that the currently executing module was loaded from for a FFS sections of type SectionType.
+ If the FFS file contains at least SectionInstance instances of the FFS section specified by SectionType,
+ then the SectionInstance instance is returned in Buffer. Buffer is allocated using AllocatePool(),
+ and the size of the allocated buffer is returned in Size. It is the caller's responsibility
+ to use FreePool() to free the allocated buffer. See EFI_FIRMWARE_VOLUME2_PROTOCOL.ReadSection() for
+ details on how sections are retrieved from an FFS file based on SectionType and SectionInstance.
+
+ If the currently executing module was not loaded from an FFS file, then EFI_NOT_FOUND is returned.
+ If SectionType is EFI_SECTION_TE, and the search with an FFS file fails,
+ the search will be retried with a section type of EFI_SECTION_PE32.
+ This function must be called with a TPL <= TPL_NOTIFY.
+
+ If Buffer is NULL, then ASSERT().
+ If Size is NULL, then ASSERT().
+
+
+ @param SectionType Indicates the FFS section type to search for within
+ the FFS file that the currently executing module
+ was loaded from.
+ @param SectionInstance Indicates which section instance to retrieve within
+ the FFS file that the currently executing module
+ was loaded from.
+ @param Buffer On output, a pointer to a callee allocated buffer
+ containing the FFS file section that was found.
+ It is the caller's responsibility to free this buffer
+ using FreePool().
+ @param Size On output, a pointer to the size, in bytes, of Buffer.
+
+ @retval EFI_SUCCESS The specified FFS section was returned.
+ @retval EFI_NOT_FOUND The specified FFS section could not be found.
+ @retval EFI_OUT_OF_RESOURCES There are not enough resources available to retrieve
+ the matching FFS section.
+ @retval EFI_DEVICE_ERROR The FFS section could not be retrieves due to a
+ device error.
+ @retval EFI_ACCESS_DENIED The FFS section could not be retrieves because the
+ firmware volume that contains the matching FFS
+ section does not allow reads.
+
+**/
+EFI_STATUS
+EFIAPI
+GetSectionFromFfs (
+ IN EFI_SECTION_TYPE SectionType,
+ IN UINTN SectionInstance,
+ OUT VOID **Buffer,
+ OUT UINTN *Size
+ );
+
+/**
+ Get the image file buffer data and buffer size by its device path.
+
+ Access the file either from a firmware volume, from a file system interface,
+ or from the load file interface.
+
+ Allocate memory to store the found image. The caller is responsible to free memory.
+
+ If FilePath is NULL, then NULL is returned.
+ If FileSize is NULL, then NULL is returned.
+ If AuthenticationStatus is NULL, then NULL is returned.
+
+ @param[in] BootPolicy The policy for Open Image File.If TRUE,
+ indicates that the request originates from
+ the boot manager, and that the boot manager is
+ attempting to load FilePath as a boot selection.
+ If FALSE, then FilePath must match an exact
+ file to be loaded.
+ @param[in] FilePath Pointer to the device path of the file that is abstracted to
+ the file buffer.
+ @param[out] FileSize Pointer to the size of the abstracted file buffer.
+ @param[out] AuthenticationStatus Pointer to the authentication status.
+
+ @retval NULL FilePath is NULL, or FileSize is NULL, or AuthenticationStatus is NULL, or the file can't be found.
+ @retval other The abstracted file buffer. The caller is responsible to free memory.
+**/
+VOID *
+EFIAPI
+GetFileBufferByFilePath (
+ IN BOOLEAN BootPolicy,
+ IN CONST EFI_DEVICE_PATH_PROTOCOL *FilePath,
+ OUT UINTN *FileSize,
+ OUT UINT32 *AuthenticationStatus
+ );
+
+/**
+ Searches all the available firmware volumes and returns the file device path of first matching
+ FFS section.
+
+ This function searches all the firmware volumes for FFS files with an FFS filename specified by NameGuid.
+ The order that the firmware volumes is searched is not deterministic. For each FFS file found a search
+ is made for FFS sections of type SectionType.
+
+ If SectionType is EFI_SECTION_TE, and the search with an FFS file fails,
+ the search will be retried with a section type of EFI_SECTION_PE32.
+ This function must be called with a TPL <= TPL_NOTIFY.
+
+ If NameGuid is NULL, then ASSERT().
+
+ @param NameGuid A pointer to to the FFS filename GUID to search for
+ within any of the firmware volumes in the platform.
+ @param SectionType Indicates the FFS section type to search for within
+ the FFS file specified by NameGuid.
+ @param SectionInstance Indicates which section instance within the FFS file
+ specified by NameGuid to retrieve.
+ @param FvFileDevicePath Device path for the target FFS
+ file.
+
+ @retval EFI_SUCCESS The specified file device path of FFS section was returned.
+ @retval EFI_NOT_FOUND The specified file device path of FFS section could not be found.
+ @retval EFI_DEVICE_ERROR The FFS section could not be retrieves due to a
+ device error.
+ @retval EFI_ACCESS_DENIED The FFS section could not be retrieves because the
+ firmware volume that contains the matching FFS section does not
+ allow reads.
+ @retval EFI_INVALID_PARAMETER FvFileDevicePath is NULL.
+
+**/
+EFI_STATUS
+EFIAPI
+GetFileDevicePathFromAnyFv (
+ IN CONST EFI_GUID *NameGuid,
+ IN EFI_SECTION_TYPE SectionType,
+ IN UINTN SectionInstance,
+ OUT EFI_DEVICE_PATH_PROTOCOL **FvFileDevicePath
+ );
+
+/**
+ Allocates one or more 4KB pages of a given type from a memory region that is
+ accessible to PEI.
+
+ Allocates the number of 4KB pages of type 'MemoryType' and returns a
+ pointer to the allocated buffer. The buffer returned is aligned on a 4KB
+ boundary. If Pages is 0, then NULL is returned. If there is not enough
+ memory remaining to satisfy the request, then NULL is returned.
+
+ @param[in] MemoryType The memory type to allocate
+ @param[in] Pages The number of 4 KB pages to allocate.
+
+ @return A pointer to the allocated buffer or NULL if allocation fails.
+
+**/
+VOID *
+EFIAPI
+AllocatePeiAccessiblePages (
+ IN EFI_MEMORY_TYPE MemoryType,
+ IN UINTN Pages
+ );
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/DxeServicesTableLib.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/DxeServicesTableLib.h
new file mode 100644
index 0000000000..decd2884fd
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/DxeServicesTableLib.h
@@ -0,0 +1,27 @@
+/** @file
+ Provides a service to retrieve a pointer to the DXE Services Table.
+ Only available to DXE module types.
+
+ This library does not contain any functions or macros. It simply exports a global
+ pointer to the DXE Services Table as defined in the Platform Initialization Driver
+ Execution Environment Core Interface Specification. The library constructor must
+ initialize this global pointer to the DX Services Table, so it is available at the
+ module's entry point. Since there is overhead in looking up the pointer to the DXE
+ Services Table, only those modules that actually require access to the DXE Services
+ Table should use this library. This will typically be DXE Drivers that require GCD
+ or Dispatcher services.
+
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __DXE_SERVICES_TABLE_LIB_H__
+#define __DXE_SERVICES_TABLE_LIB_H__
+
+///
+/// Cache copy of the DXE Services Table
+///
+extern EFI_DXE_SERVICES *gDS;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/ExtractGuidedSectionLib.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/ExtractGuidedSectionLib.h
new file mode 100644
index 0000000000..7f0eedabdb
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/ExtractGuidedSectionLib.h
@@ -0,0 +1,279 @@
+/** @file
+ This library provides common functions to process the different guided section data.
+
+ This library provides functions to process GUIDed sections of FFS files. Handlers may
+ be registered to decode GUIDed sections of FFS files. Services are provided to determine
+ the set of supported section GUIDs, collection information about a specific GUIDed section,
+ and decode a specific GUIDed section.
+
+ A library instance that produces this library class may be used to produce a
+ EFI_PEI_GUIDED_SECTION_EXTRACTION_PPI or a EFI_GUIDED_SECTION_EXTRACTION_PROTOCOL
+ providing a simple method to extend the number of GUIDed sections types a platform supports.
+
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __EXTRACT_GUIDED_SECTION_H__
+#define __EXTRACT_GUIDED_SECTION_H__
+
+/**
+ Examines a GUIDed section and returns the size of the decoded buffer and the
+ size of an optional scratch buffer required to actually decode the data in a GUIDed section.
+
+ Examines a GUIDed section specified by InputSection.
+ If GUID for InputSection does not match the GUID that this handler supports,
+ then RETURN_UNSUPPORTED is returned.
+ If the required information can not be retrieved from InputSection,
+ then RETURN_INVALID_PARAMETER is returned.
+ If the GUID of InputSection does match the GUID that this handler supports,
+ then the size required to hold the decoded buffer is returned in OututBufferSize,
+ the size of an optional scratch buffer is returned in ScratchSize, and the Attributes field
+ from EFI_GUID_DEFINED_SECTION header of InputSection is returned in SectionAttribute.
+
+ If InputSection is NULL, then ASSERT().
+ If OutputBufferSize is NULL, then ASSERT().
+ If ScratchBufferSize is NULL, then ASSERT().
+ If SectionAttribute is NULL, then ASSERT().
+
+
+ @param[in] InputSection A pointer to a GUIDed section of an FFS formatted file.
+ @param[out] OutputBufferSize A pointer to the size, in bytes, of an output buffer required
+ if the buffer specified by InputSection were decoded.
+ @param[out] ScratchBufferSize A pointer to the size, in bytes, required as scratch space
+ if the buffer specified by InputSection were decoded.
+ @param[out] SectionAttribute A pointer to the attributes of the GUIDed section. See the Attributes
+ field of EFI_GUID_DEFINED_SECTION in the PI Specification.
+
+ @retval RETURN_SUCCESS The information about InputSection was returned.
+ @retval RETURN_UNSUPPORTED The section specified by InputSection does not match the GUID this handler supports.
+ @retval RETURN_INVALID_PARAMETER The information can not be retrieved from the section specified by InputSection.
+
+**/
+typedef
+RETURN_STATUS
+(EFIAPI *EXTRACT_GUIDED_SECTION_GET_INFO_HANDLER)(
+ IN CONST VOID *InputSection,
+ OUT UINT32 *OutputBufferSize,
+ OUT UINT32 *ScratchBufferSize,
+ OUT UINT16 *SectionAttribute
+ );
+
+/**
+ Decodes a GUIDed section into a caller allocated output buffer.
+
+ Decodes the GUIDed section specified by InputSection.
+ If GUID for InputSection does not match the GUID that this handler supports, then RETURN_UNSUPPORTED is returned.
+ If the data in InputSection can not be decoded, then RETURN_INVALID_PARAMETER is returned.
+ If the GUID of InputSection does match the GUID that this handler supports, then InputSection
+ is decoded into the buffer specified by OutputBuffer and the authentication status of this
+ decode operation is returned in AuthenticationStatus. If the decoded buffer is identical to the
+ data in InputSection, then OutputBuffer is set to point at the data in InputSection. Otherwise,
+ the decoded data will be placed in caller allocated buffer specified by OutputBuffer.
+
+ If InputSection is NULL, then ASSERT().
+ If OutputBuffer is NULL, then ASSERT().
+ If ScratchBuffer is NULL and this decode operation requires a scratch buffer, then ASSERT().
+ If AuthenticationStatus is NULL, then ASSERT().
+
+
+ @param[in] InputSection A pointer to a GUIDed section of an FFS formatted file.
+ @param[out] OutputBuffer A pointer to a buffer that contains the result of a decode operation.
+ @param[out] ScratchBuffer A caller allocated buffer that may be required by this function
+ as a scratch buffer to perform the decode operation.
+ @param[out] AuthenticationStatus
+ A pointer to the authentication status of the decoded output buffer.
+ See the definition of authentication status in the EFI_PEI_GUIDED_SECTION_EXTRACTION_PPI
+ section of the PI Specification. EFI_AUTH_STATUS_PLATFORM_OVERRIDE must
+ never be set by this handler.
+
+ @retval RETURN_SUCCESS The buffer specified by InputSection was decoded.
+ @retval RETURN_UNSUPPORTED The section specified by InputSection does not match the GUID this handler supports.
+ @retval RETURN_INVALID_PARAMETER The section specified by InputSection can not be decoded.
+
+**/
+typedef
+RETURN_STATUS
+(EFIAPI *EXTRACT_GUIDED_SECTION_DECODE_HANDLER)(
+ IN CONST VOID *InputSection,
+ OUT VOID **OutputBuffer,
+ IN VOID *ScratchBuffer OPTIONAL,
+ OUT UINT32 *AuthenticationStatus
+ );
+
+/**
+ Registers handlers of type EXTRACT_GUIDED_SECTION_GET_INFO_HANDLER and EXTRACT_GUIDED_SECTION_DECODE_HANDLER
+ for a specific GUID section type.
+
+ Registers the handlers specified by GetInfoHandler and DecodeHandler with the GUID specified by SectionGuid.
+ If the GUID value specified by SectionGuid has already been registered, then return RETURN_ALREADY_STARTED.
+ If there are not enough resources available to register the handlers then RETURN_OUT_OF_RESOURCES is returned.
+
+ If SectionGuid is NULL, then ASSERT().
+ If GetInfoHandler is NULL, then ASSERT().
+ If DecodeHandler is NULL, then ASSERT().
+
+ @param[in] SectionGuid A pointer to the GUID associated with the the handlers
+ of the GUIDed section type being registered.
+ @param[in] GetInfoHandler Pointer to a function that examines a GUIDed section and returns the
+ size of the decoded buffer and the size of an optional scratch buffer
+ required to actually decode the data in a GUIDed section.
+ @param[in] DecodeHandler Pointer to a function that decodes a GUIDed section into a caller
+ allocated output buffer.
+
+ @retval RETURN_SUCCESS The handlers were registered.
+ @retval RETURN_OUT_OF_RESOURCES There are not enough resources available to register the handlers.
+
+**/
+RETURN_STATUS
+EFIAPI
+ExtractGuidedSectionRegisterHandlers (
+ IN CONST GUID *SectionGuid,
+ IN EXTRACT_GUIDED_SECTION_GET_INFO_HANDLER GetInfoHandler,
+ IN EXTRACT_GUIDED_SECTION_DECODE_HANDLER DecodeHandler
+ );
+
+/**
+ Retrieve the list GUIDs that have been registered through ExtractGuidedSectionRegisterHandlers().
+
+ Sets ExtractHandlerGuidTable so it points at a callee allocated array of registered GUIDs.
+ The total number of GUIDs in the array are returned. Since the array of GUIDs is callee allocated
+ and caller must treat this array of GUIDs as read-only data.
+ If ExtractHandlerGuidTable is NULL, then ASSERT().
+
+ @param[out] ExtractHandlerGuidTable A pointer to the array of GUIDs that have been registered through
+ ExtractGuidedSectionRegisterHandlers().
+
+ @return the number of the supported extract guided Handler.
+
+**/
+UINTN
+EFIAPI
+ExtractGuidedSectionGetGuidList (
+ OUT GUID **ExtractHandlerGuidTable
+ );
+
+/**
+ Retrieves a GUID from a GUIDed section and uses that GUID to select an associated handler of type
+ EXTRACT_GUIDED_SECTION_GET_INFO_HANDLER that was registered with ExtractGuidedSectionRegisterHandlers().
+ The selected handler is used to retrieve and return the size of the decoded buffer and the size of an
+ optional scratch buffer required to actually decode the data in a GUIDed section.
+
+ Examines a GUIDed section specified by InputSection.
+ If GUID for InputSection does not match any of the GUIDs registered through ExtractGuidedSectionRegisterHandlers(),
+ then RETURN_UNSUPPORTED is returned.
+ If the GUID of InputSection does match the GUID that this handler supports, then the the associated handler
+ of type EXTRACT_GUIDED_SECTION_GET_INFO_HANDLER that was registered with ExtractGuidedSectionRegisterHandlers()
+ is used to retrieve the OututBufferSize, ScratchSize, and Attributes values. The return status from the handler of
+ type EXTRACT_GUIDED_SECTION_GET_INFO_HANDLER is returned.
+
+ If InputSection is NULL, then ASSERT().
+ If OutputBufferSize is NULL, then ASSERT().
+ If ScratchBufferSize is NULL, then ASSERT().
+ If SectionAttribute is NULL, then ASSERT().
+
+ @param[in] InputSection A pointer to a GUIDed section of an FFS formatted file.
+ @param[out] OutputBufferSize A pointer to the size, in bytes, of an output buffer required if the buffer
+ specified by InputSection were decoded.
+ @param[out] ScratchBufferSize A pointer to the size, in bytes, required as scratch space if the buffer specified by
+ InputSection were decoded.
+ @param[out] SectionAttribute A pointer to the attributes of the GUIDed section. See the Attributes field of
+ EFI_GUID_DEFINED_SECTION in the PI Specification.
+
+ @retval RETURN_SUCCESS Get the required information successfully.
+ @retval RETURN_UNSUPPORTED The GUID from the section specified by InputSection does not match any of
+ the GUIDs registered with ExtractGuidedSectionRegisterHandlers().
+ @retval Others The return status from the handler associated with the GUID retrieved from
+ the section specified by InputSection.
+
+**/
+RETURN_STATUS
+EFIAPI
+ExtractGuidedSectionGetInfo (
+ IN CONST VOID *InputSection,
+ OUT UINT32 *OutputBufferSize,
+ OUT UINT32 *ScratchBufferSize,
+ OUT UINT16 *SectionAttribute
+ );
+
+/**
+ Retrieves the GUID from a GUIDed section and uses that GUID to select an associated handler of type
+ EXTRACT_GUIDED_SECTION_DECODE_HANDLER that was registered with ExtractGuidedSectionRegisterHandlers().
+ The selected handler is used to decode the data in a GUIDed section and return the result in a caller
+ allocated output buffer.
+
+ Decodes the GUIDed section specified by InputSection.
+ If GUID for InputSection does not match any of the GUIDs registered through ExtractGuidedSectionRegisterHandlers(),
+ then RETURN_UNSUPPORTED is returned.
+ If the GUID of InputSection does match the GUID that this handler supports, then the the associated handler
+ of type EXTRACT_GUIDED_SECTION_DECODE_HANDLER that was registered with ExtractGuidedSectionRegisterHandlers()
+ is used to decode InputSection into the buffer specified by OutputBuffer and the authentication status of this
+ decode operation is returned in AuthenticationStatus. If the decoded buffer is identical to the data in InputSection,
+ then OutputBuffer is set to point at the data in InputSection. Otherwise, the decoded data will be placed in caller
+ allocated buffer specified by OutputBuffer. This function is responsible for computing the EFI_AUTH_STATUS_PLATFORM_OVERRIDE
+ bit of in AuthenticationStatus. The return status from the handler of type EXTRACT_GUIDED_SECTION_DECODE_HANDLER is returned.
+
+ If InputSection is NULL, then ASSERT().
+ If OutputBuffer is NULL, then ASSERT().
+ If ScratchBuffer is NULL and this decode operation requires a scratch buffer, then ASSERT().
+ If AuthenticationStatus is NULL, then ASSERT().
+
+ @param[in] InputSection A pointer to a GUIDed section of an FFS formatted file.
+ @param[out] OutputBuffer A pointer to a buffer that contains the result of a decode operation.
+ @param[in] ScratchBuffer A caller allocated buffer that may be required by this function as a scratch buffer to perform the decode operation.
+ @param[out] AuthenticationStatus
+ A pointer to the authentication status of the decoded output buffer. See the definition
+ of authentication status in the EFI_PEI_GUIDED_SECTION_EXTRACTION_PPI section of the PI
+ Specification.
+
+ @retval RETURN_SUCCESS The buffer specified by InputSection was decoded.
+ @retval RETURN_UNSUPPORTED The section specified by InputSection does not match the GUID this handler supports.
+ @retval RETURN_INVALID_PARAMETER The section specified by InputSection can not be decoded.
+
+**/
+RETURN_STATUS
+EFIAPI
+ExtractGuidedSectionDecode (
+ IN CONST VOID *InputSection,
+ OUT VOID **OutputBuffer,
+ IN VOID *ScratchBuffer OPTIONAL,
+ OUT UINT32 *AuthenticationStatus
+ );
+
+/**
+ Retrieves handlers of type EXTRACT_GUIDED_SECTION_GET_INFO_HANDLER and
+ EXTRACT_GUIDED_SECTION_DECODE_HANDLER for a specific GUID section type.
+
+ Retrieves the handlers associated with SectionGuid and returns them in
+ GetInfoHandler and DecodeHandler.
+
+ If the GUID value specified by SectionGuid has not been registered, then
+ return RETURN_NOT_FOUND.
+
+ If SectionGuid is NULL, then ASSERT().
+
+ @param[in] SectionGuid A pointer to the GUID associated with the handlersof the GUIDed
+ section type being retrieved.
+ @param[out] GetInfoHandler Pointer to a function that examines a GUIDed section and returns
+ the size of the decoded buffer and the size of an optional scratch
+ buffer required to actually decode the data in a GUIDed section.
+ This is an optional parameter that may be NULL. If it is NULL, then
+ the previously registered handler is not returned.
+ @param[out] DecodeHandler Pointer to a function that decodes a GUIDed section into a caller
+ allocated output buffer. This is an optional parameter that may be NULL.
+ If it is NULL, then the previously registered handler is not returned.
+
+ @retval RETURN_SUCCESS The handlers were retrieved.
+ @retval RETURN_NOT_FOUND No handlers have been registered with the specified GUID.
+
+**/
+RETURN_STATUS
+EFIAPI
+ExtractGuidedSectionGetHandlers (
+ IN CONST GUID *SectionGuid,
+ OUT EXTRACT_GUIDED_SECTION_GET_INFO_HANDLER *GetInfoHandler OPTIONAL,
+ OUT EXTRACT_GUIDED_SECTION_DECODE_HANDLER *DecodeHandler OPTIONAL
+ );
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/FileHandleLib.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/FileHandleLib.h
new file mode 100644
index 0000000000..9a2bedf96a
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/FileHandleLib.h
@@ -0,0 +1,501 @@
+/** @file
+ Provides interface to EFI_FILE_HANDLE functionality.
+
+ Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _FILE_HANDLE_LIBRARY_HEADER_
+#define _FILE_HANDLE_LIBRARY_HEADER_
+
+#include
+#include
+
+/// The tag for use in identifying UNICODE files.
+/// If the file is UNICODE, the first 16 bits of the file will equal this value.
+extern CONST UINT16 gUnicodeFileTag;
+
+/**
+ This function retrieves information about the file for the handle
+ specified and stores it in the allocated pool memory.
+
+ This function allocates a buffer to store the file's information. It is the
+ caller's responsibility to free the buffer.
+
+ @param[in] FileHandle The file handle of the file for which information is
+ being requested.
+
+ @retval NULL Information could not be retrieved.
+ @retval !NULL The information about the file.
+**/
+EFI_FILE_INFO *
+EFIAPI
+FileHandleGetInfo (
+ IN EFI_FILE_HANDLE FileHandle
+ );
+
+/**
+ This function sets the information about the file for the opened handle
+ specified.
+
+ @param[in] FileHandle The file handle of the file for which information
+ is being set.
+
+ @param[in] FileInfo The information to set.
+
+ @retval EFI_SUCCESS The information was set.
+ @retval EFI_INVALID_PARAMETER A parameter was out of range or invalid.
+ @retval EFI_UNSUPPORTED The FileHandle does not support FileInfo.
+ @retval EFI_NO_MEDIA The device has no medium.
+ @retval EFI_DEVICE_ERROR The device reported an error.
+ @retval EFI_VOLUME_CORRUPTED The file system structures are corrupted.
+ @retval EFI_WRITE_PROTECTED The file or medium is write protected.
+ @retval EFI_ACCESS_DENIED The file was opened read only.
+ @retval EFI_VOLUME_FULL The volume is full.
+**/
+EFI_STATUS
+EFIAPI
+FileHandleSetInfo (
+ IN EFI_FILE_HANDLE FileHandle,
+ IN CONST EFI_FILE_INFO *FileInfo
+ );
+
+/**
+ This function reads information from an opened file.
+
+ If FileHandle is not a directory, the function reads the requested number of
+ bytes from the file at the file's current position and returns them in Buffer.
+ If the read goes beyond the end of the file, the read length is truncated to the
+ end of the file. The file's current position is increased by the number of bytes
+ returned. If FileHandle is a directory, the function reads the directory entry
+ at the file's current position and returns the entry in Buffer. If the Buffer
+ is not large enough to hold the current directory entry, then
+ EFI_BUFFER_TOO_SMALL is returned and the current file position is not updated.
+ BufferSize is set to be the size of the buffer needed to read the entry. On
+ success, the current position is updated to the next directory entry. If there
+ are no more directory entries, the read returns a zero-length buffer.
+ EFI_FILE_INFO is the structure returned as the directory entry.
+
+ @param[in] FileHandle The opened file handle.
+ @param[in, out] BufferSize On input, the size of buffer in bytes. On return,
+ the number of bytes written.
+ @param[out] Buffer The buffer to put read data into.
+
+ @retval EFI_SUCCESS Data was read.
+ @retval EFI_NO_MEDIA The device has no media.
+ @retval EFI_DEVICE_ERROR The device reported an error.
+ @retval EFI_VOLUME_CORRUPTED The file system structures are corrupted.
+ @retval EFI_BUFFER_TO_SMALL Buffer is too small. ReadSize contains required
+ size.
+
+**/
+EFI_STATUS
+EFIAPI
+FileHandleRead (
+ IN EFI_FILE_HANDLE FileHandle,
+ IN OUT UINTN *BufferSize,
+ OUT VOID *Buffer
+ );
+
+/**
+ Write data to a file.
+
+ This function writes the specified number of bytes to the file at the current
+ file position. The current file position is advanced the actual number of bytes
+ written, which is returned in BufferSize. Partial writes only occur when there
+ has been a data error during the write attempt (such as "volume space full").
+ The file is automatically grown to hold the data if required. Direct writes to
+ opened directories are not supported.
+
+ @param[in] FileHandle The opened file for writing.
+ @param[in, out] BufferSize On input, the number of bytes in Buffer. On output,
+ the number of bytes written.
+ @param[in] Buffer The buffer containing data to write is stored.
+
+ @retval EFI_SUCCESS Data was written.
+ @retval EFI_UNSUPPORTED Writes to an open directory are not supported.
+ @retval EFI_NO_MEDIA The device has no media.
+ @retval EFI_DEVICE_ERROR The device reported an error.
+ @retval EFI_VOLUME_CORRUPTED The file system structures are corrupted.
+ @retval EFI_WRITE_PROTECTED The device is write-protected.
+ @retval EFI_ACCESS_DENIED The file was opened for read only.
+ @retval EFI_VOLUME_FULL The volume is full.
+**/
+EFI_STATUS
+EFIAPI
+FileHandleWrite (
+ IN EFI_FILE_HANDLE FileHandle,
+ IN OUT UINTN *BufferSize,
+ IN VOID *Buffer
+ );
+
+/**
+ Close an open file handle.
+
+ This function closes a specified file handle. All "dirty" cached file data is
+ flushed to the device, and the file is closed. In all cases the handle is
+ closed.
+
+ @param[in] FileHandle The file handle to close.
+
+ @retval EFI_SUCCESS The file handle was closed successfully.
+**/
+EFI_STATUS
+EFIAPI
+FileHandleClose (
+ IN EFI_FILE_HANDLE FileHandle
+ );
+
+/**
+ Delete a file and close the handle.
+
+ This function closes and deletes a file. In all cases the file handle is closed.
+ If the file cannot be deleted, the warning code EFI_WARN_DELETE_FAILURE is
+ returned, but the handle is still closed.
+
+ @param[in] FileHandle The file handle to delete.
+
+ @retval EFI_SUCCESS The file was closed successfully.
+ @retval EFI_WARN_DELETE_FAILURE The handle was closed, but the file was not
+ deleted.
+ @retval INVALID_PARAMETER One of the parameters has an invalid value.
+**/
+EFI_STATUS
+EFIAPI
+FileHandleDelete (
+ IN EFI_FILE_HANDLE FileHandle
+ );
+
+/**
+ Set the current position in a file.
+
+ This function sets the current file position for the handle to the position
+ supplied. With the exception of moving to position 0xFFFFFFFFFFFFFFFF, only
+ absolute positioning is supported, and moving past the end of the file is
+ allowed (a subsequent write would grow the file). Moving to position
+ 0xFFFFFFFFFFFFFFFF causes the current position to be set to the end of the file.
+ If FileHandle is a directory, the only position that may be set is zero. This
+ has the effect of starting the read process of the directory entries over again.
+
+ @param[in] FileHandle The file handle on which the position is being set.
+ @param[in] Position The byte position from the beginning of the file.
+
+ @retval EFI_SUCCESS The operation completed successfully.
+ @retval EFI_UNSUPPORTED The request for non-zero is not valid on
+ directories.
+ @retval INVALID_PARAMETER One of the parameters has an invalid value.
+**/
+EFI_STATUS
+EFIAPI
+FileHandleSetPosition (
+ IN EFI_FILE_HANDLE FileHandle,
+ IN UINT64 Position
+ );
+
+/**
+ Gets a file's current position.
+
+ This function retrieves the current file position for the file handle. For
+ directories, the current file position has no meaning outside of the file
+ system driver. As such, the operation is not supported. An error is returned
+ if FileHandle is a directory.
+
+ @param[in] FileHandle The open file handle on which to get the position.
+ @param[out] Position The byte position from beginning of file.
+
+ @retval EFI_SUCCESS The operation completed successfully.
+ @retval INVALID_PARAMETER One of the parameters has an invalid value.
+ @retval EFI_UNSUPPORTED The request is not valid on directories.
+**/
+EFI_STATUS
+EFIAPI
+FileHandleGetPosition (
+ IN EFI_FILE_HANDLE FileHandle,
+ OUT UINT64 *Position
+ );
+
+/**
+ Flushes data on a file.
+
+ This function flushes all modified data associated with a file to a device.
+
+ @param[in] FileHandle The file handle on which to flush data.
+
+ @retval EFI_SUCCESS The data was flushed.
+ @retval EFI_NO_MEDIA The device has no media.
+ @retval EFI_DEVICE_ERROR The device reported an error.
+ @retval EFI_VOLUME_CORRUPTED The file system structures are corrupted.
+ @retval EFI_WRITE_PROTECTED The file or medium is write protected.
+ @retval EFI_ACCESS_DENIED The file was opened for read only.
+**/
+EFI_STATUS
+EFIAPI
+FileHandleFlush (
+ IN EFI_FILE_HANDLE FileHandle
+ );
+
+/**
+ Function to determine if a given handle is a directory handle.
+
+ Open the file information on the DirHandle and verify that the Attribute
+ includes EFI_FILE_DIRECTORY bit set.
+
+ @param[in] DirHandle Handle to open file.
+
+ @retval EFI_SUCCESS DirHandle is a directory.
+ @retval EFI_INVALID_PARAMETER DirHandle is NULL.
+ The file information returns from FileHandleGetInfo is NULL.
+ @retval EFI_NOT_FOUND DirHandle is not a directory.
+**/
+EFI_STATUS
+EFIAPI
+FileHandleIsDirectory (
+ IN EFI_FILE_HANDLE DirHandle
+ );
+
+/** Retrieve first entry from a directory.
+
+ This function takes an open directory handle and gets information from the
+ first entry in the directory. A buffer is allocated to contain
+ the information and a pointer to the buffer is returned in *Buffer. The
+ caller can use FileHandleFindNextFile() to get subsequent directory entries.
+
+ The buffer will be freed by FileHandleFindNextFile() when the last directory
+ entry is read. Otherwise, the caller must free the buffer, using FreePool,
+ when finished with it.
+
+ @param[in] DirHandle The file handle of the directory to search.
+ @param[out] Buffer The pointer to pointer to buffer for file's information.
+
+ @retval EFI_SUCCESS Found the first file.
+ @retval EFI_NOT_FOUND Cannot find the directory.
+ @retval EFI_NO_MEDIA The device has no media.
+ @retval EFI_DEVICE_ERROR The device reported an error.
+ @retval EFI_VOLUME_CORRUPTED The file system structures are corrupted.
+ @return Others The status of FileHandleGetInfo, FileHandleSetPosition,
+ or FileHandleRead.
+**/
+EFI_STATUS
+EFIAPI
+FileHandleFindFirstFile (
+ IN EFI_FILE_HANDLE DirHandle,
+ OUT EFI_FILE_INFO **Buffer
+ );
+
+/** Retrieve next entries from a directory.
+
+ To use this function, the caller must first call the FileHandleFindFirstFile()
+ function to get the first directory entry. Subsequent directory entries are
+ retrieved by using the FileHandleFindNextFile() function. This function can
+ be called several times to get each entry from the directory. If the call of
+ FileHandleFindNextFile() retrieved the last directory entry, the next call of
+ this function will set *NoFile to TRUE and free the buffer.
+
+ @param[in] DirHandle The file handle of the directory.
+ @param[out] Buffer The pointer to buffer for file's information.
+ @param[out] NoFile The pointer to boolean when last file is found.
+
+ @retval EFI_SUCCESS Found the next file, or reached last file.
+ @retval EFI_NO_MEDIA The device has no media.
+ @retval EFI_DEVICE_ERROR The device reported an error.
+ @retval EFI_VOLUME_CORRUPTED The file system structures are corrupted.
+**/
+EFI_STATUS
+EFIAPI
+FileHandleFindNextFile (
+ IN EFI_FILE_HANDLE DirHandle,
+ OUT EFI_FILE_INFO *Buffer,
+ OUT BOOLEAN *NoFile
+ );
+
+/**
+ Retrieve the size of a file.
+
+ This function extracts the file size info from the FileHandle's EFI_FILE_INFO
+ data.
+
+ @param[in] FileHandle The file handle from which size is retrieved.
+ @param[out] Size The pointer to size.
+
+ @retval EFI_SUCCESS Operation was completed successfully.
+ @retval EFI_DEVICE_ERROR Cannot access the file.
+ @retval EFI_INVALID_PARAMETER FileHandle is NULL.
+ Size is NULL.
+**/
+EFI_STATUS
+EFIAPI
+FileHandleGetSize (
+ IN EFI_FILE_HANDLE FileHandle,
+ OUT UINT64 *Size
+ );
+
+/**
+ Set the size of a file.
+
+ This function changes the file size info from the FileHandle's EFI_FILE_INFO
+ data.
+
+ @param[in] FileHandle The file handle whose size is to be changed.
+ @param[in] Size The new size.
+
+ @retval EFI_SUCCESS The operation completed successfully.
+ @retval EFI_DEVICE_ERROR Cannot access the file.
+ @retval EFI_INVALID_PARAMETER FileHandle is NULL.
+**/
+EFI_STATUS
+EFIAPI
+FileHandleSetSize (
+ IN EFI_FILE_HANDLE FileHandle,
+ IN UINT64 Size
+ );
+
+/**
+ Function to get a full filename given a EFI_FILE_HANDLE somewhere lower on the
+ directory 'stack'. If the file is a directory, then append the '\' char at the
+ end of name string. If it's not a directory, then the last '\' should not be
+ added.
+
+ @param[in] Handle Handle to the Directory or File to create path to.
+ @param[out] FullFileName Pointer to pointer to generated full file name. It
+ is the responsibility of the caller to free this memory
+ with a call to FreePool().
+ @retval EFI_SUCCESS The operation was successful and FullFileName is valid.
+ @retval EFI_INVALID_PARAMETER Handle was NULL.
+ @retval EFI_INVALID_PARAMETER FullFileName was NULL.
+ @retval EFI_OUT_OF_MEMORY A memory allocation failed.
+**/
+EFI_STATUS
+EFIAPI
+FileHandleGetFileName (
+ IN CONST EFI_FILE_HANDLE Handle,
+ OUT CHAR16 **FullFileName
+ );
+
+/**
+ Function to read a single line (up to but not including the \n) from a file.
+
+ If the position upon start is 0, then the Ascii Boolean will be set. This should be
+ maintained and not changed for all operations with the same file.
+ The function will not return the \r and \n character in buffer. When an empty line is
+ read a CHAR_NULL character will be returned in buffer.
+
+ @param[in] Handle FileHandle to read from.
+ @param[in, out] Buffer The pointer to buffer to read into.
+ @param[in, out] Size The pointer to number of bytes in Buffer.
+ @param[in] Truncate If the buffer is large enough, this has no effect.
+ If the buffer is is too small and Truncate is TRUE,
+ the line will be truncated.
+ If the buffer is is too small and Truncate is FALSE,
+ then no read will occur.
+
+ @param[in, out] Ascii Boolean value for indicating whether the file is
+ Ascii (TRUE) or UCS2 (FALSE).
+
+ @retval EFI_SUCCESS The operation was successful. The line is stored in
+ Buffer.
+ @retval EFI_INVALID_PARAMETER Handle was NULL.
+ @retval EFI_INVALID_PARAMETER Size was NULL.
+ @retval EFI_BUFFER_TOO_SMALL Size was not large enough to store the line.
+ Size was updated to the minimum space required.
+ @sa FileHandleRead
+**/
+EFI_STATUS
+EFIAPI
+FileHandleReadLine (
+ IN EFI_FILE_HANDLE Handle,
+ IN OUT CHAR16 *Buffer,
+ IN OUT UINTN *Size,
+ IN BOOLEAN Truncate,
+ IN OUT BOOLEAN *Ascii
+ );
+
+/**
+ Function to read a single line from a file. The \n is not included in the returned
+ buffer. The returned buffer must be callee freed.
+
+ If the position upon start is 0, then the Ascii Boolean will be set. This should be
+ maintained and not changed for all operations with the same file.
+
+ @param[in] Handle FileHandle to read from.
+ @param[in, out] Ascii Boolean value for indicating whether the file is
+ Ascii (TRUE) or UCS2 (FALSE).
+
+ @return The line of text from the file.
+
+ @sa FileHandleReadLine
+**/
+CHAR16 *
+EFIAPI
+FileHandleReturnLine (
+ IN EFI_FILE_HANDLE Handle,
+ IN OUT BOOLEAN *Ascii
+ );
+
+/**
+ Function to write a line of text to a file.
+
+ If the file is a Unicode file (with UNICODE file tag) then write the unicode
+ text.
+ If the file is an ASCII file then write the ASCII text.
+ If the size of file is zero (without file tag at the beginning) then write
+ ASCII text as default.
+
+ @param[in] Handle FileHandle to write to.
+ @param[in] Buffer Buffer to write, if NULL the function will
+ take no action and return EFI_SUCCESS.
+
+ @retval EFI_SUCCESS The data was written.
+ Buffer is NULL.
+ @retval EFI_INVALID_PARAMETER Handle is NULL.
+ @retval EFI_OUT_OF_RESOURCES Unable to allocate temporary space for ASCII
+ string due to out of resources.
+
+ @sa FileHandleWrite
+**/
+EFI_STATUS
+EFIAPI
+FileHandleWriteLine (
+ IN EFI_FILE_HANDLE Handle,
+ IN CHAR16 *Buffer
+ );
+
+/**
+ Function to take a formatted argument and print it to a file.
+
+ @param[in] Handle The file handle for the file to write to.
+ @param[in] Format The format argument (see printlib for the format specifier).
+ @param[in] ... The variable arguments for the format.
+
+ @retval EFI_SUCCESS The operation was successful.
+ @retval other A return value from FileHandleWriteLine.
+
+ @sa FileHandleWriteLine
+**/
+EFI_STATUS
+EFIAPI
+FileHandlePrintLine (
+ IN EFI_FILE_HANDLE Handle,
+ IN CONST CHAR16 *Format,
+ ...
+ );
+
+/**
+ Function to determine if a FILE_HANDLE is at the end of the file.
+
+ This will NOT work on directories.
+
+ If Handle is NULL, then ASSERT().
+
+ @param[in] Handle The file handle.
+
+ @retval TRUE The position is at the end of the file.
+ @retval FALSE The position is not at the end of the file.
+**/
+BOOLEAN
+EFIAPI
+FileHandleEof (
+ IN EFI_FILE_HANDLE Handle
+ );
+
+#endif //_FILE_HANDLE_LIBRARY_HEADER_
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/HobLib.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/HobLib.h
new file mode 100644
index 0000000000..da8a905d0a
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/HobLib.h
@@ -0,0 +1,560 @@
+/** @file
+ Provides services to create and parse HOBs. Only available for PEI
+ and DXE module types.
+
+ The HOB Library supports the efficient creation and searching of HOBs
+ defined in the PI Specification.
+ A HOB is a Hand-Off Block, defined in the Framework architecture, that
+ allows the PEI phase to pass information to the DXE phase. HOBs are position
+ independent and can be relocated easily to different memory locations.
+
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __HOB_LIB_H__
+#define __HOB_LIB_H__
+
+/**
+ Returns the pointer to the HOB list.
+
+ This function returns the pointer to first HOB in the list.
+ For PEI phase, the PEI service GetHobList() can be used to retrieve the pointer
+ to the HOB list. For the DXE phase, the HOB list pointer can be retrieved through
+ the EFI System Table by looking up theHOB list GUID in the System Configuration Table.
+ Since the System Configuration Table does not exist that the time the DXE Core is
+ launched, the DXE Core uses a global variable from the DXE Core Entry Point Library
+ to manage the pointer to the HOB list.
+
+ If the pointer to the HOB list is NULL, then ASSERT().
+
+ @return The pointer to the HOB list.
+
+**/
+VOID *
+EFIAPI
+GetHobList (
+ VOID
+ );
+
+/**
+ Returns the next instance of a HOB type from the starting HOB.
+
+ This function searches the first instance of a HOB type from the starting HOB pointer.
+ If there does not exist such HOB type from the starting HOB pointer, it will return NULL.
+ In contrast with macro GET_NEXT_HOB(), this function does not skip the starting HOB pointer
+ unconditionally: it returns HobStart back if HobStart itself meets the requirement;
+ caller is required to use GET_NEXT_HOB() if it wishes to skip current HobStart.
+
+ If HobStart is NULL, then ASSERT().
+
+ @param Type The HOB type to return.
+ @param HobStart The starting HOB pointer to search from.
+
+ @return The next instance of a HOB type from the starting HOB.
+
+**/
+VOID *
+EFIAPI
+GetNextHob (
+ IN UINT16 Type,
+ IN CONST VOID *HobStart
+ );
+
+/**
+ Returns the first instance of a HOB type among the whole HOB list.
+
+ This function searches the first instance of a HOB type among the whole HOB list.
+ If there does not exist such HOB type in the HOB list, it will return NULL.
+
+ If the pointer to the HOB list is NULL, then ASSERT().
+
+ @param Type The HOB type to return.
+
+ @return The next instance of a HOB type from the starting HOB.
+
+**/
+VOID *
+EFIAPI
+GetFirstHob (
+ IN UINT16 Type
+ );
+
+/**
+ Returns the next instance of the matched GUID HOB from the starting HOB.
+
+ This function searches the first instance of a HOB from the starting HOB pointer.
+ Such HOB should satisfy two conditions:
+ its HOB type is EFI_HOB_TYPE_GUID_EXTENSION and its GUID Name equals to the input Guid.
+ If there does not exist such HOB from the starting HOB pointer, it will return NULL.
+ Caller is required to apply GET_GUID_HOB_DATA () and GET_GUID_HOB_DATA_SIZE ()
+ to extract the data section and its size info respectively.
+ In contrast with macro GET_NEXT_HOB(), this function does not skip the starting HOB pointer
+ unconditionally: it returns HobStart back if HobStart itself meets the requirement;
+ caller is required to use GET_NEXT_HOB() if it wishes to skip current HobStart.
+
+ If Guid is NULL, then ASSERT().
+ If HobStart is NULL, then ASSERT().
+
+ @param Guid The GUID to match with in the HOB list.
+ @param HobStart A pointer to a Guid.
+
+ @return The next instance of the matched GUID HOB from the starting HOB.
+
+**/
+VOID *
+EFIAPI
+GetNextGuidHob (
+ IN CONST EFI_GUID *Guid,
+ IN CONST VOID *HobStart
+ );
+
+/**
+ Returns the first instance of the matched GUID HOB among the whole HOB list.
+
+ This function searches the first instance of a HOB among the whole HOB list.
+ Such HOB should satisfy two conditions:
+ its HOB type is EFI_HOB_TYPE_GUID_EXTENSION and its GUID Name equals to the input Guid.
+ If there does not exist such HOB from the starting HOB pointer, it will return NULL.
+ Caller is required to apply GET_GUID_HOB_DATA () and GET_GUID_HOB_DATA_SIZE ()
+ to extract the data section and its size info respectively.
+
+ If the pointer to the HOB list is NULL, then ASSERT().
+ If Guid is NULL, then ASSERT().
+
+ @param Guid The GUID to match with in the HOB list.
+
+ @return The first instance of the matched GUID HOB among the whole HOB list.
+
+**/
+VOID *
+EFIAPI
+GetFirstGuidHob (
+ IN CONST EFI_GUID *Guid
+ );
+
+/**
+ Get the system boot mode from the HOB list.
+
+ This function returns the system boot mode information from the
+ PHIT HOB in HOB list.
+
+ If the pointer to the HOB list is NULL, then ASSERT().
+
+ @param VOID
+
+ @return The Boot Mode.
+
+**/
+EFI_BOOT_MODE
+EFIAPI
+GetBootModeHob (
+ VOID
+ );
+
+/**
+ Builds a HOB for a loaded PE32 module.
+
+ This function builds a HOB for a loaded PE32 module.
+ It can only be invoked during PEI phase;
+ for DXE phase, it will ASSERT() since PEI HOB is read-only for DXE phase.
+
+ If ModuleName is NULL, then ASSERT().
+ If there is no additional space for HOB creation, then ASSERT().
+
+ @param ModuleName The GUID File Name of the module.
+ @param MemoryAllocationModule The 64 bit physical address of the module.
+ @param ModuleLength The length of the module in bytes.
+ @param EntryPoint The 64 bit physical address of the module entry point.
+
+**/
+VOID
+EFIAPI
+BuildModuleHob (
+ IN CONST EFI_GUID *ModuleName,
+ IN EFI_PHYSICAL_ADDRESS MemoryAllocationModule,
+ IN UINT64 ModuleLength,
+ IN EFI_PHYSICAL_ADDRESS EntryPoint
+ );
+
+/**
+ Builds a HOB that describes a chunk of system memory with Owner GUID.
+
+ This function builds a HOB that describes a chunk of system memory.
+ It can only be invoked during PEI phase;
+ for DXE phase, it will ASSERT() since PEI HOB is read-only for DXE phase.
+
+ If there is no additional space for HOB creation, then ASSERT().
+
+ @param ResourceType The type of resource described by this HOB.
+ @param ResourceAttribute The resource attributes of the memory described by this HOB.
+ @param PhysicalStart The 64 bit physical address of memory described by this HOB.
+ @param NumberOfBytes The length of the memory described by this HOB in bytes.
+ @param OwnerGUID GUID for the owner of this resource.
+
+**/
+VOID
+EFIAPI
+BuildResourceDescriptorWithOwnerHob (
+ IN EFI_RESOURCE_TYPE ResourceType,
+ IN EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttribute,
+ IN EFI_PHYSICAL_ADDRESS PhysicalStart,
+ IN UINT64 NumberOfBytes,
+ IN EFI_GUID *OwnerGUID
+ );
+
+/**
+ Builds a HOB that describes a chunk of system memory.
+
+ This function builds a HOB that describes a chunk of system memory.
+ It can only be invoked during PEI phase;
+ for DXE phase, it will ASSERT() since PEI HOB is read-only for DXE phase.
+
+ If there is no additional space for HOB creation, then ASSERT().
+
+ @param ResourceType The type of resource described by this HOB.
+ @param ResourceAttribute The resource attributes of the memory described by this HOB.
+ @param PhysicalStart The 64 bit physical address of memory described by this HOB.
+ @param NumberOfBytes The length of the memory described by this HOB in bytes.
+
+**/
+VOID
+EFIAPI
+BuildResourceDescriptorHob (
+ IN EFI_RESOURCE_TYPE ResourceType,
+ IN EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttribute,
+ IN EFI_PHYSICAL_ADDRESS PhysicalStart,
+ IN UINT64 NumberOfBytes
+ );
+
+/**
+ Builds a customized HOB tagged with a GUID for identification and returns
+ the start address of GUID HOB data.
+
+ This function builds a customized HOB tagged with a GUID for identification
+ and returns the start address of GUID HOB data so that caller can fill the customized data.
+ The HOB Header and Name field is already stripped.
+ It can only be invoked during PEI phase;
+ for DXE phase, it will ASSERT() since PEI HOB is read-only for DXE phase.
+
+ If Guid is NULL, then ASSERT().
+ If there is no additional space for HOB creation, then ASSERT().
+ If DataLength > (0xFFF8 - sizeof (EFI_HOB_GUID_TYPE)), then ASSERT().
+ HobLength is UINT16 and multiples of 8 bytes, so the max HobLength is 0xFFF8.
+
+ @param Guid The GUID to tag the customized HOB.
+ @param DataLength The size of the data payload for the GUID HOB.
+
+ @retval NULL The GUID HOB could not be allocated.
+ @retval others The start address of GUID HOB data.
+
+**/
+VOID *
+EFIAPI
+BuildGuidHob (
+ IN CONST EFI_GUID *Guid,
+ IN UINTN DataLength
+ );
+
+/**
+ Builds a customized HOB tagged with a GUID for identification, copies the input data to the HOB
+ data field, and returns the start address of the GUID HOB data.
+
+ This function builds a customized HOB tagged with a GUID for identification and copies the input
+ data to the HOB data field and returns the start address of the GUID HOB data. It can only be
+ invoked during PEI phase; for DXE phase, it will ASSERT() since PEI HOB is read-only for DXE phase.
+ The HOB Header and Name field is already stripped.
+ It can only be invoked during PEI phase;
+ for DXE phase, it will ASSERT() since PEI HOB is read-only for DXE phase.
+
+ If Guid is NULL, then ASSERT().
+ If Data is NULL and DataLength > 0, then ASSERT().
+ If there is no additional space for HOB creation, then ASSERT().
+ If DataLength > (0xFFF8 - sizeof (EFI_HOB_GUID_TYPE)), then ASSERT().
+ HobLength is UINT16 and multiples of 8 bytes, so the max HobLength is 0xFFF8.
+
+ @param Guid The GUID to tag the customized HOB.
+ @param Data The data to be copied into the data field of the GUID HOB.
+ @param DataLength The size of the data payload for the GUID HOB.
+
+ @retval NULL The GUID HOB could not be allocated.
+ @retval others The start address of GUID HOB data.
+
+**/
+VOID *
+EFIAPI
+BuildGuidDataHob (
+ IN CONST EFI_GUID *Guid,
+ IN VOID *Data,
+ IN UINTN DataLength
+ );
+
+/**
+ Builds a Firmware Volume HOB.
+
+ This function builds a Firmware Volume HOB.
+ It can only be invoked during PEI phase;
+ for DXE phase, it will ASSERT() since PEI HOB is read-only for DXE phase.
+
+ If there is no additional space for HOB creation, then ASSERT().
+ If the FvImage buffer is not at its required alignment, then ASSERT().
+
+ @param BaseAddress The base address of the Firmware Volume.
+ @param Length The size of the Firmware Volume in bytes.
+
+**/
+VOID
+EFIAPI
+BuildFvHob (
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,
+ IN UINT64 Length
+ );
+
+/**
+ Builds a EFI_HOB_TYPE_FV2 HOB.
+
+ This function builds a EFI_HOB_TYPE_FV2 HOB.
+ It can only be invoked during PEI phase;
+ for DXE phase, it will ASSERT() since PEI HOB is read-only for DXE phase.
+
+ If there is no additional space for HOB creation, then ASSERT().
+ If the FvImage buffer is not at its required alignment, then ASSERT().
+
+ @param BaseAddress The base address of the Firmware Volume.
+ @param Length The size of the Firmware Volume in bytes.
+ @param FvName The name of the Firmware Volume.
+ @param FileName The name of the file.
+
+**/
+VOID
+EFIAPI
+BuildFv2Hob (
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,
+ IN UINT64 Length,
+ IN CONST EFI_GUID *FvName,
+ IN CONST EFI_GUID *FileName
+ );
+
+/**
+ Builds a EFI_HOB_TYPE_FV3 HOB.
+
+ This function builds a EFI_HOB_TYPE_FV3 HOB.
+ It can only be invoked during PEI phase;
+ for DXE phase, it will ASSERT() since PEI HOB is read-only for DXE phase.
+
+ If there is no additional space for HOB creation, then ASSERT().
+ If the FvImage buffer is not at its required alignment, then ASSERT().
+
+ @param BaseAddress The base address of the Firmware Volume.
+ @param Length The size of the Firmware Volume in bytes.
+ @param AuthenticationStatus The authentication status.
+ @param ExtractedFv TRUE if the FV was extracted as a file within
+ another firmware volume. FALSE otherwise.
+ @param FvName The name of the Firmware Volume.
+ Valid only if IsExtractedFv is TRUE.
+ @param FileName The name of the file.
+ Valid only if IsExtractedFv is TRUE.
+
+**/
+VOID
+EFIAPI
+BuildFv3Hob (
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,
+ IN UINT64 Length,
+ IN UINT32 AuthenticationStatus,
+ IN BOOLEAN ExtractedFv,
+ IN CONST EFI_GUID *FvName OPTIONAL,
+ IN CONST EFI_GUID *FileName OPTIONAL
+ );
+
+/**
+ Builds a Capsule Volume HOB.
+
+ This function builds a Capsule Volume HOB.
+ It can only be invoked during PEI phase;
+ for DXE phase, it will ASSERT() since PEI HOB is read-only for DXE phase.
+
+ If the platform does not support Capsule Volume HOBs, then ASSERT().
+ If there is no additional space for HOB creation, then ASSERT().
+
+ @param BaseAddress The base address of the Capsule Volume.
+ @param Length The size of the Capsule Volume in bytes.
+
+**/
+VOID
+EFIAPI
+BuildCvHob (
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,
+ IN UINT64 Length
+ );
+
+/**
+ Builds a HOB for the CPU.
+
+ This function builds a HOB for the CPU.
+ It can only be invoked during PEI phase;
+ for DXE phase, it will ASSERT() since PEI HOB is read-only for DXE phase.
+
+ If there is no additional space for HOB creation, then ASSERT().
+
+ @param SizeOfMemorySpace The maximum physical memory addressability of the processor.
+ @param SizeOfIoSpace The maximum physical I/O addressability of the processor.
+
+**/
+VOID
+EFIAPI
+BuildCpuHob (
+ IN UINT8 SizeOfMemorySpace,
+ IN UINT8 SizeOfIoSpace
+ );
+
+/**
+ Builds a HOB for the Stack.
+
+ This function builds a HOB for the stack.
+ It can only be invoked during PEI phase;
+ for DXE phase, it will ASSERT() since PEI HOB is read-only for DXE phase.
+
+ If there is no additional space for HOB creation, then ASSERT().
+
+ @param BaseAddress The 64 bit physical address of the Stack.
+ @param Length The length of the stack in bytes.
+
+**/
+VOID
+EFIAPI
+BuildStackHob (
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,
+ IN UINT64 Length
+ );
+
+/**
+ Builds a HOB for the BSP store.
+
+ This function builds a HOB for BSP store.
+ It can only be invoked during PEI phase;
+ for DXE phase, it will ASSERT() since PEI HOB is read-only for DXE phase.
+
+ If there is no additional space for HOB creation, then ASSERT().
+
+ @param BaseAddress The 64 bit physical address of the BSP.
+ @param Length The length of the BSP store in bytes.
+ @param MemoryType Type of memory allocated by this HOB.
+
+**/
+VOID
+EFIAPI
+BuildBspStoreHob (
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,
+ IN UINT64 Length,
+ IN EFI_MEMORY_TYPE MemoryType
+ );
+
+/**
+ Builds a HOB for the memory allocation.
+
+ This function builds a HOB for the memory allocation.
+ It can only be invoked during PEI phase;
+ for DXE phase, it will ASSERT() since PEI HOB is read-only for DXE phase.
+
+ If there is no additional space for HOB creation, then ASSERT().
+
+ @param BaseAddress The 64 bit physical address of the memory.
+ @param Length The length of the memory allocation in bytes.
+ @param MemoryType Type of memory allocated by this HOB.
+
+**/
+VOID
+EFIAPI
+BuildMemoryAllocationHob (
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,
+ IN UINT64 Length,
+ IN EFI_MEMORY_TYPE MemoryType
+ );
+
+/**
+ Returns the type of a HOB.
+
+ This macro returns the HobType field from the HOB header for the
+ HOB specified by HobStart.
+
+ @param HobStart A pointer to a HOB.
+
+ @return HobType.
+
+**/
+#define GET_HOB_TYPE(HobStart) \
+ ((*(EFI_HOB_GENERIC_HEADER **)&(HobStart))->HobType)
+
+/**
+ Returns the length, in bytes, of a HOB.
+
+ This macro returns the HobLength field from the HOB header for the
+ HOB specified by HobStart.
+
+ @param HobStart A pointer to a HOB.
+
+ @return HobLength.
+
+**/
+#define GET_HOB_LENGTH(HobStart) \
+ ((*(EFI_HOB_GENERIC_HEADER **)&(HobStart))->HobLength)
+
+/**
+ Returns a pointer to the next HOB in the HOB list.
+
+ This macro returns a pointer to HOB that follows the
+ HOB specified by HobStart in the HOB List.
+
+ @param HobStart A pointer to a HOB.
+
+ @return A pointer to the next HOB in the HOB list.
+
+**/
+#define GET_NEXT_HOB(HobStart) \
+ (VOID *)(*(UINT8 **)&(HobStart) + GET_HOB_LENGTH (HobStart))
+
+/**
+ Determines if a HOB is the last HOB in the HOB list.
+
+ This macro determine if the HOB specified by HobStart is the
+ last HOB in the HOB list. If HobStart is last HOB in the HOB list,
+ then TRUE is returned. Otherwise, FALSE is returned.
+
+ @param HobStart A pointer to a HOB.
+
+ @retval TRUE The HOB specified by HobStart is the last HOB in the HOB list.
+ @retval FALSE The HOB specified by HobStart is not the last HOB in the HOB list.
+
+**/
+#define END_OF_HOB_LIST(HobStart) (GET_HOB_TYPE (HobStart) == (UINT16)EFI_HOB_TYPE_END_OF_HOB_LIST)
+
+/**
+ Returns a pointer to data buffer from a HOB of type EFI_HOB_TYPE_GUID_EXTENSION.
+
+ This macro returns a pointer to the data buffer in a HOB specified by HobStart.
+ HobStart is assumed to be a HOB of type EFI_HOB_TYPE_GUID_EXTENSION.
+
+ @param GuidHob A pointer to a HOB.
+
+ @return A pointer to the data buffer in a HOB.
+
+**/
+#define GET_GUID_HOB_DATA(HobStart) \
+ (VOID *)(*(UINT8 **)&(HobStart) + sizeof (EFI_HOB_GUID_TYPE))
+
+/**
+ Returns the size of the data buffer from a HOB of type EFI_HOB_TYPE_GUID_EXTENSION.
+
+ This macro returns the size, in bytes, of the data buffer in a HOB specified by HobStart.
+ HobStart is assumed to be a HOB of type EFI_HOB_TYPE_GUID_EXTENSION.
+
+ @param GuidHob A pointer to a HOB.
+
+ @return The size of the data buffer.
+**/
+#define GET_GUID_HOB_DATA_SIZE(HobStart) \
+ (UINT16)(GET_HOB_LENGTH (HobStart) - sizeof (EFI_HOB_GUID_TYPE))
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/HstiLib.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/HstiLib.h
new file mode 100644
index 0000000000..0d0dd8a80b
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/HstiLib.h
@@ -0,0 +1,152 @@
+/** @file
+ Provides services to create, get and update HSTI table in AIP protocol.
+
+ Copyright (c) 2015, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __HSTI_LIB_H__
+#define __HSTI_LIB_H__
+
+/**
+ Publish HSTI table in AIP protocol.
+
+ One system should have only one PLATFORM_SECURITY_ROLE_PLATFORM_REFERENCE.
+
+ If the Role is NOT PLATFORM_SECURITY_ROLE_PLATFORM_REFERENCE,
+ SecurityFeaturesRequired field will be ignored.
+
+ @param Hsti HSTI data
+ @param HstiSize HSTI size
+
+ @retval EFI_SUCCESS The HSTI data is published in AIP protocol.
+ @retval EFI_ALREADY_STARTED There is already HSTI table with Role and ImplementationID published in system.
+ @retval EFI_VOLUME_CORRUPTED The input HSTI data does not follow HSTI specification.
+ @retval EFI_OUT_OF_RESOURCES There is not enough system resource to publish HSTI data in AIP protocol.
+**/
+EFI_STATUS
+EFIAPI
+HstiLibSetTable (
+ IN VOID *Hsti,
+ IN UINTN HstiSize
+ );
+
+/**
+ Search HSTI table in AIP protocol, and return the data.
+ This API will return the HSTI table with indicated Role and ImplementationID,
+ NULL ImplementationID means to find the first HSTI table with indicated Role.
+
+ @param Role Role of HSTI data.
+ @param ImplementationID ImplementationID of HSTI data.
+ NULL means find the first one match Role.
+ @param Hsti HSTI data. This buffer is allocated by callee, and it
+ is the responsibility of the caller to free it after
+ using it.
+ @param HstiSize HSTI size
+
+ @retval EFI_SUCCESS The HSTI data in AIP protocol is returned.
+ @retval EFI_NOT_FOUND There is not HSTI table with the Role and ImplementationID published in system.
+**/
+EFI_STATUS
+EFIAPI
+HstiLibGetTable (
+ IN UINT32 Role,
+ IN CHAR16 *ImplementationID OPTIONAL,
+ OUT VOID **Hsti,
+ OUT UINTN *HstiSize
+ );
+
+/**
+ Set FeaturesVerified in published HSTI table.
+ This API will update the HSTI table with indicated Role and ImplementationID,
+ NULL ImplementationID means to find the first HSTI table with indicated Role.
+
+ @param Role Role of HSTI data.
+ @param ImplementationID ImplementationID of HSTI data.
+ NULL means find the first one match Role.
+ @param ByteIndex Byte index of FeaturesVerified of HSTI data.
+ @param BitMask Bit mask of FeaturesVerified of HSTI data.
+
+ @retval EFI_SUCCESS The FeaturesVerified of HSTI data updated in AIP protocol.
+ @retval EFI_NOT_STARTED There is not HSTI table with the Role and ImplementationID published in system.
+ @retval EFI_UNSUPPORTED The ByteIndex is invalid.
+**/
+EFI_STATUS
+EFIAPI
+HstiLibSetFeaturesVerified (
+ IN UINT32 Role,
+ IN CHAR16 *ImplementationID OPTIONAL,
+ IN UINT32 ByteIndex,
+ IN UINT8 BitMask
+ );
+
+/**
+ Clear FeaturesVerified in published HSTI table.
+ This API will update the HSTI table with indicated Role and ImplementationID,
+ NULL ImplementationID means to find the first HSTI table with indicated Role.
+
+ @param Role Role of HSTI data.
+ @param ImplementationID ImplementationID of HSTI data.
+ NULL means find the first one match Role.
+ @param ByteIndex Byte index of FeaturesVerified of HSTI data.
+ @param BitMask Bit mask of FeaturesVerified of HSTI data.
+
+ @retval EFI_SUCCESS The FeaturesVerified of HSTI data updated in AIP protocol.
+ @retval EFI_NOT_STARTED There is not HSTI table with the Role and ImplementationID published in system.
+ @retval EFI_UNSUPPORTED The ByteIndex is invalid.
+**/
+EFI_STATUS
+EFIAPI
+HstiLibClearFeaturesVerified (
+ IN UINT32 Role,
+ IN CHAR16 *ImplementationID OPTIONAL,
+ IN UINT32 ByteIndex,
+ IN UINT8 BitMask
+ );
+
+/**
+ Append ErrorString in published HSTI table.
+ This API will update the HSTI table with indicated Role and ImplementationID,
+ NULL ImplementationID means to find the first HSTI table with indicated Role.
+
+ @param Role Role of HSTI data.
+ @param ImplementationID ImplementationID of HSTI data.
+ NULL means find the first one match Role.
+ @param ErrorString ErrorString of HSTI data.
+
+ @retval EFI_SUCCESS The ErrorString of HSTI data is updated in AIP protocol.
+ @retval EFI_NOT_STARTED There is not HSTI table with the Role and ImplementationID published in system.
+ @retval EFI_OUT_OF_RESOURCES There is not enough system resource to update ErrorString.
+**/
+EFI_STATUS
+EFIAPI
+HstiLibAppendErrorString (
+ IN UINT32 Role,
+ IN CHAR16 *ImplementationID OPTIONAL,
+ IN CHAR16 *ErrorString
+ );
+
+/**
+ Set a new ErrorString in published HSTI table.
+ This API will update the HSTI table with indicated Role and ImplementationID,
+ NULL ImplementationID means to find the first HSTI table with indicated Role.
+
+ @param Role Role of HSTI data.
+ @param ImplementationID ImplementationID of HSTI data.
+ NULL means find the first one match Role.
+ @param ErrorString ErrorString of HSTI data.
+
+ @retval EFI_SUCCESS The ErrorString of HSTI data is updated in AIP protocol.
+ @retval EFI_NOT_STARTED There is not HSTI table with the Role and ImplementationID published in system.
+ @retval EFI_OUT_OF_RESOURCES There is not enough system resource to update ErrorString.
+**/
+EFI_STATUS
+EFIAPI
+HstiLibSetErrorString (
+ IN UINT32 Role,
+ IN CHAR16 *ImplementationID OPTIONAL,
+ IN CHAR16 *ErrorString
+ );
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/IoLib.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/IoLib.h
new file mode 100644
index 0000000000..18e20df9b0
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/IoLib.h
@@ -0,0 +1,2807 @@
+/** @file
+ Provide services to access I/O Ports and MMIO registers.
+
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+Copyright (c) 2017, AMD Incorporated. All rights reserved.
+
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __IO_LIB_H__
+#define __IO_LIB_H__
+
+/**
+ Macro that converts PCI Segment and I/O Port to an address that can be
+ passed to the I/O Library functions.
+
+ Computes an address that is compatible with the I/O Library functions.
+ The unused upper bits of Segment, and Port are stripped prior to the
+ generation of the address.
+
+ @param Segment PCI Segment number. Range 0..65535.
+ @param Port I/O Port number. Range 0..65535.
+
+ @return An address that the I/o Library functions need.
+
+**/
+
+#define IO_LIB_ADDRESS(Segment, Port) \
+ ( ((Port) & 0xffff) | (((Segment) & 0xffff) << 16) )
+
+/**
+ Reads an 8-bit I/O port.
+
+ Reads the 8-bit I/O port specified by Port. The 8-bit read value is returned.
+ This function must guarantee that all I/O read and write operations are
+ serialized.
+
+ If 8-bit I/O port operations are not supported, then ASSERT().
+
+ @param Port The I/O port to read.
+
+ @return The value read.
+
+**/
+UINT8
+EFIAPI
+IoRead8 (
+ IN UINTN Port
+ );
+
+/**
+ Writes an 8-bit I/O port.
+
+ Writes the 8-bit I/O port specified by Port with the value specified by Value
+ and returns Value. This function must guarantee that all I/O read and write
+ operations are serialized.
+
+ If 8-bit I/O port operations are not supported, then ASSERT().
+
+ @param Port The I/O port to write.
+ @param Value The value to write to the I/O port.
+
+ @return The value written the I/O port.
+
+**/
+UINT8
+EFIAPI
+IoWrite8 (
+ IN UINTN Port,
+ IN UINT8 Value
+ );
+
+/**
+ Reads an 8-bit I/O port fifo into a block of memory.
+
+ Reads the 8-bit I/O fifo port specified by Port.
+ The port is read Count times, and the read data is
+ stored in the provided Buffer.
+
+ This function must guarantee that all I/O read and write operations are
+ serialized.
+
+ If 8-bit I/O port operations are not supported, then ASSERT().
+
+ @param Port The I/O port to read.
+ @param Count The number of times to read I/O port.
+ @param Buffer The buffer to store the read data into.
+
+**/
+VOID
+EFIAPI
+IoReadFifo8 (
+ IN UINTN Port,
+ IN UINTN Count,
+ OUT VOID *Buffer
+ );
+
+/**
+ Writes a block of memory into an 8-bit I/O port fifo.
+
+ Writes the 8-bit I/O fifo port specified by Port.
+ The port is written Count times, and the write data is
+ retrieved from the provided Buffer.
+
+ This function must guarantee that all I/O write and write operations are
+ serialized.
+
+ If 8-bit I/O port operations are not supported, then ASSERT().
+
+ @param Port The I/O port to write.
+ @param Count The number of times to write I/O port.
+ @param Buffer The buffer to retrieve the write data from.
+
+**/
+VOID
+EFIAPI
+IoWriteFifo8 (
+ IN UINTN Port,
+ IN UINTN Count,
+ IN VOID *Buffer
+ );
+
+/**
+ Reads an 8-bit I/O port, performs a bitwise OR, and writes the
+ result back to the 8-bit I/O port.
+
+ Reads the 8-bit I/O port specified by Port, performs a bitwise OR
+ between the read result and the value specified by OrData, and writes the
+ result to the 8-bit I/O port specified by Port. The value written to the I/O
+ port is returned. This function must guarantee that all I/O read and write
+ operations are serialized.
+
+ If 8-bit I/O port operations are not supported, then ASSERT().
+
+ @param Port The I/O port to write.
+ @param OrData The value to OR with the read value from the I/O port.
+
+ @return The value written back to the I/O port.
+
+**/
+UINT8
+EFIAPI
+IoOr8 (
+ IN UINTN Port,
+ IN UINT8 OrData
+ );
+
+/**
+ Reads an 8-bit I/O port, performs a bitwise AND, and writes the result back
+ to the 8-bit I/O port.
+
+ Reads the 8-bit I/O port specified by Port, performs a bitwise AND between
+ the read result and the value specified by AndData, and writes the result to
+ the 8-bit I/O port specified by Port. The value written to the I/O port is
+ returned. This function must guarantee that all I/O read and write operations
+ are serialized.
+
+ If 8-bit I/O port operations are not supported, then ASSERT().
+
+ @param Port The I/O port to write.
+ @param AndData The value to AND with the read value from the I/O port.
+
+ @return The value written back to the I/O port.
+
+**/
+UINT8
+EFIAPI
+IoAnd8 (
+ IN UINTN Port,
+ IN UINT8 AndData
+ );
+
+/**
+ Reads an 8-bit I/O port, performs a bitwise AND followed by a bitwise
+ OR, and writes the result back to the 8-bit I/O port.
+
+ Reads the 8-bit I/O port specified by Port, performs a bitwise AND between
+ the read result and the value specified by AndData, performs a bitwise OR
+ between the result of the AND operation and the value specified by OrData,
+ and writes the result to the 8-bit I/O port specified by Port. The value
+ written to the I/O port is returned. This function must guarantee that all
+ I/O read and write operations are serialized.
+
+ If 8-bit I/O port operations are not supported, then ASSERT().
+
+ @param Port The I/O port to write.
+ @param AndData The value to AND with the read value from the I/O port.
+ @param OrData The value to OR with the result of the AND operation.
+
+ @return The value written back to the I/O port.
+
+**/
+UINT8
+EFIAPI
+IoAndThenOr8 (
+ IN UINTN Port,
+ IN UINT8 AndData,
+ IN UINT8 OrData
+ );
+
+/**
+ Reads a bit field of an I/O register.
+
+ Reads the bit field in an 8-bit I/O register. The bit field is specified by
+ the StartBit and the EndBit. The value of the bit field is returned.
+
+ If 8-bit I/O port operations are not supported, then ASSERT().
+ If StartBit is greater than 7, then ASSERT().
+ If EndBit is greater than 7, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+
+ @param Port The I/O port to read.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..7.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..7.
+
+ @return The value read.
+
+**/
+UINT8
+EFIAPI
+IoBitFieldRead8 (
+ IN UINTN Port,
+ IN UINTN StartBit,
+ IN UINTN EndBit
+ );
+
+/**
+ Writes a bit field to an I/O register.
+
+ Writes Value to the bit field of the I/O register. The bit field is specified
+ by the StartBit and the EndBit. All other bits in the destination I/O
+ register are preserved. The value written to the I/O port is returned.
+
+ If 8-bit I/O port operations are not supported, then ASSERT().
+ If StartBit is greater than 7, then ASSERT().
+ If EndBit is greater than 7, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Port The I/O port to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..7.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..7.
+ @param Value New value of the bit field.
+
+ @return The value written back to the I/O port.
+
+**/
+UINT8
+EFIAPI
+IoBitFieldWrite8 (
+ IN UINTN Port,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT8 Value
+ );
+
+/**
+ Reads a bit field in an 8-bit port, performs a bitwise OR, and writes the
+ result back to the bit field in the 8-bit port.
+
+ Reads the 8-bit I/O port specified by Port, performs a bitwise OR
+ between the read result and the value specified by OrData, and writes the
+ result to the 8-bit I/O port specified by Port. The value written to the I/O
+ port is returned. This function must guarantee that all I/O read and write
+ operations are serialized. Extra left bits in OrData are stripped.
+
+ If 8-bit I/O port operations are not supported, then ASSERT().
+ If StartBit is greater than 7, then ASSERT().
+ If EndBit is greater than 7, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Port The I/O port to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..7.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..7.
+ @param OrData The value to OR with the read value from the I/O port.
+
+ @return The value written back to the I/O port.
+
+**/
+UINT8
+EFIAPI
+IoBitFieldOr8 (
+ IN UINTN Port,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT8 OrData
+ );
+
+/**
+ Reads a bit field in an 8-bit port, performs a bitwise AND, and writes the
+ result back to the bit field in the 8-bit port.
+
+ Reads the 8-bit I/O port specified by Port, performs a bitwise AND between
+ the read result and the value specified by AndData, and writes the result to
+ the 8-bit I/O port specified by Port. The value written to the I/O port is
+ returned. This function must guarantee that all I/O read and write operations
+ are serialized. Extra left bits in AndData are stripped.
+
+ If 8-bit I/O port operations are not supported, then ASSERT().
+ If StartBit is greater than 7, then ASSERT().
+ If EndBit is greater than 7, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Port The I/O port to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..7.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..7.
+ @param AndData The value to AND with the read value from the I/O port.
+
+ @return The value written back to the I/O port.
+
+**/
+UINT8
+EFIAPI
+IoBitFieldAnd8 (
+ IN UINTN Port,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT8 AndData
+ );
+
+/**
+ Reads a bit field in an 8-bit port, performs a bitwise AND followed by a
+ bitwise OR, and writes the result back to the bit field in the
+ 8-bit port.
+
+ Reads the 8-bit I/O port specified by Port, performs a bitwise AND followed
+ by a bitwise OR between the read result and the value specified by
+ AndData, and writes the result to the 8-bit I/O port specified by Port. The
+ value written to the I/O port is returned. This function must guarantee that
+ all I/O read and write operations are serialized. Extra left bits in both
+ AndData and OrData are stripped.
+
+ If 8-bit I/O port operations are not supported, then ASSERT().
+ If StartBit is greater than 7, then ASSERT().
+ If EndBit is greater than 7, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Port The I/O port to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..7.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..7.
+ @param AndData The value to AND with the read value from the I/O port.
+ @param OrData The value to OR with the result of the AND operation.
+
+ @return The value written back to the I/O port.
+
+**/
+UINT8
+EFIAPI
+IoBitFieldAndThenOr8 (
+ IN UINTN Port,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT8 AndData,
+ IN UINT8 OrData
+ );
+
+/**
+ Reads a 16-bit I/O port.
+
+ Reads the 16-bit I/O port specified by Port. The 16-bit read value is returned.
+ This function must guarantee that all I/O read and write operations are
+ serialized.
+
+ If 16-bit I/O port operations are not supported, then ASSERT().
+ If Port is not aligned on a 16-bit boundary, then ASSERT().
+
+ @param Port The I/O port to read.
+
+ @return The value read.
+
+**/
+UINT16
+EFIAPI
+IoRead16 (
+ IN UINTN Port
+ );
+
+/**
+ Writes a 16-bit I/O port.
+
+ Writes the 16-bit I/O port specified by Port with the value specified by Value
+ and returns Value. This function must guarantee that all I/O read and write
+ operations are serialized.
+
+ If 16-bit I/O port operations are not supported, then ASSERT().
+ If Port is not aligned on a 16-bit boundary, then ASSERT().
+
+ @param Port The I/O port to write.
+ @param Value The value to write to the I/O port.
+
+ @return The value written the I/O port.
+
+**/
+UINT16
+EFIAPI
+IoWrite16 (
+ IN UINTN Port,
+ IN UINT16 Value
+ );
+
+/**
+ Reads a 16-bit I/O port fifo into a block of memory.
+
+ Reads the 16-bit I/O fifo port specified by Port.
+ The port is read Count times, and the read data is
+ stored in the provided Buffer.
+
+ This function must guarantee that all I/O read and write operations are
+ serialized.
+
+ If 16-bit I/O port operations are not supported, then ASSERT().
+
+ @param Port The I/O port to read.
+ @param Count The number of times to read I/O port.
+ @param Buffer The buffer to store the read data into.
+
+**/
+VOID
+EFIAPI
+IoReadFifo16 (
+ IN UINTN Port,
+ IN UINTN Count,
+ OUT VOID *Buffer
+ );
+
+/**
+ Writes a block of memory into a 16-bit I/O port fifo.
+
+ Writes the 16-bit I/O fifo port specified by Port.
+ The port is written Count times, and the write data is
+ retrieved from the provided Buffer.
+
+ This function must guarantee that all I/O write and write operations are
+ serialized.
+
+ If 16-bit I/O port operations are not supported, then ASSERT().
+
+ @param Port The I/O port to write.
+ @param Count The number of times to write I/O port.
+ @param Buffer The buffer to retrieve the write data from.
+
+**/
+VOID
+EFIAPI
+IoWriteFifo16 (
+ IN UINTN Port,
+ IN UINTN Count,
+ IN VOID *Buffer
+ );
+
+/**
+ Reads a 16-bit I/O port, performs a bitwise OR, and writes the
+ result back to the 16-bit I/O port.
+
+ Reads the 16-bit I/O port specified by Port, performs a bitwise OR
+ between the read result and the value specified by OrData, and writes the
+ result to the 16-bit I/O port specified by Port. The value written to the I/O
+ port is returned. This function must guarantee that all I/O read and write
+ operations are serialized.
+
+ If 16-bit I/O port operations are not supported, then ASSERT().
+ If Port is not aligned on a 16-bit boundary, then ASSERT().
+
+ @param Port The I/O port to write.
+ @param OrData The value to OR with the read value from the I/O port.
+
+ @return The value written back to the I/O port.
+
+**/
+UINT16
+EFIAPI
+IoOr16 (
+ IN UINTN Port,
+ IN UINT16 OrData
+ );
+
+/**
+ Reads a 16-bit I/O port, performs a bitwise AND, and writes the result back
+ to the 16-bit I/O port.
+
+ Reads the 16-bit I/O port specified by Port, performs a bitwise AND between
+ the read result and the value specified by AndData, and writes the result to
+ the 16-bit I/O port specified by Port. The value written to the I/O port is
+ returned. This function must guarantee that all I/O read and write operations
+ are serialized.
+
+ If 16-bit I/O port operations are not supported, then ASSERT().
+ If Port is not aligned on a 16-bit boundary, then ASSERT().
+
+ @param Port The I/O port to write.
+ @param AndData The value to AND with the read value from the I/O port.
+
+ @return The value written back to the I/O port.
+
+**/
+UINT16
+EFIAPI
+IoAnd16 (
+ IN UINTN Port,
+ IN UINT16 AndData
+ );
+
+/**
+ Reads a 16-bit I/O port, performs a bitwise AND followed by a bitwise
+ OR, and writes the result back to the 16-bit I/O port.
+
+ Reads the 16-bit I/O port specified by Port, performs a bitwise AND between
+ the read result and the value specified by AndData, performs a bitwise OR
+ between the result of the AND operation and the value specified by OrData,
+ and writes the result to the 16-bit I/O port specified by Port. The value
+ written to the I/O port is returned. This function must guarantee that all
+ I/O read and write operations are serialized.
+
+ If 16-bit I/O port operations are not supported, then ASSERT().
+ If Port is not aligned on a 16-bit boundary, then ASSERT().
+
+ @param Port The I/O port to write.
+ @param AndData The value to AND with the read value from the I/O port.
+ @param OrData The value to OR with the result of the AND operation.
+
+ @return The value written back to the I/O port.
+
+**/
+UINT16
+EFIAPI
+IoAndThenOr16 (
+ IN UINTN Port,
+ IN UINT16 AndData,
+ IN UINT16 OrData
+ );
+
+/**
+ Reads a bit field of an I/O register.
+
+ Reads the bit field in a 16-bit I/O register. The bit field is specified by
+ the StartBit and the EndBit. The value of the bit field is returned.
+
+ If 16-bit I/O port operations are not supported, then ASSERT().
+ If Port is not aligned on a 16-bit boundary, then ASSERT().
+ If StartBit is greater than 15, then ASSERT().
+ If EndBit is greater than 15, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+
+ @param Port The I/O port to read.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..15.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..15.
+
+ @return The value read.
+
+**/
+UINT16
+EFIAPI
+IoBitFieldRead16 (
+ IN UINTN Port,
+ IN UINTN StartBit,
+ IN UINTN EndBit
+ );
+
+/**
+ Writes a bit field to an I/O register.
+
+ Writes Value to the bit field of the I/O register. The bit field is specified
+ by the StartBit and the EndBit. All other bits in the destination I/O
+ register are preserved. The value written to the I/O port is returned. Extra
+ left bits in Value are stripped.
+
+ If 16-bit I/O port operations are not supported, then ASSERT().
+ If Port is not aligned on a 16-bit boundary, then ASSERT().
+ If StartBit is greater than 15, then ASSERT().
+ If EndBit is greater than 15, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Port The I/O port to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..15.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..15.
+ @param Value New value of the bit field.
+
+ @return The value written back to the I/O port.
+
+**/
+UINT16
+EFIAPI
+IoBitFieldWrite16 (
+ IN UINTN Port,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT16 Value
+ );
+
+/**
+ Reads a bit field in a 16-bit port, performs a bitwise OR, and writes the
+ result back to the bit field in the 16-bit port.
+
+ Reads the 16-bit I/O port specified by Port, performs a bitwise OR
+ between the read result and the value specified by OrData, and writes the
+ result to the 16-bit I/O port specified by Port. The value written to the I/O
+ port is returned. This function must guarantee that all I/O read and write
+ operations are serialized. Extra left bits in OrData are stripped.
+
+ If 16-bit I/O port operations are not supported, then ASSERT().
+ If Port is not aligned on a 16-bit boundary, then ASSERT().
+ If StartBit is greater than 15, then ASSERT().
+ If EndBit is greater than 15, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Port The I/O port to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..15.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..15.
+ @param OrData The value to OR with the read value from the I/O port.
+
+ @return The value written back to the I/O port.
+
+**/
+UINT16
+EFIAPI
+IoBitFieldOr16 (
+ IN UINTN Port,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT16 OrData
+ );
+
+/**
+ Reads a bit field in a 16-bit port, performs a bitwise AND, and writes the
+ result back to the bit field in the 16-bit port.
+
+ Reads the 16-bit I/O port specified by Port, performs a bitwise AND between
+ the read result and the value specified by AndData, and writes the result to
+ the 16-bit I/O port specified by Port. The value written to the I/O port is
+ returned. This function must guarantee that all I/O read and write operations
+ are serialized. Extra left bits in AndData are stripped.
+
+ If 16-bit I/O port operations are not supported, then ASSERT().
+ If Port is not aligned on a 16-bit boundary, then ASSERT().
+ If StartBit is greater than 15, then ASSERT().
+ If EndBit is greater than 15, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Port The I/O port to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..15.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..15.
+ @param AndData The value to AND with the read value from the I/O port.
+
+ @return The value written back to the I/O port.
+
+**/
+UINT16
+EFIAPI
+IoBitFieldAnd16 (
+ IN UINTN Port,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT16 AndData
+ );
+
+/**
+ Reads a bit field in a 16-bit port, performs a bitwise AND followed by a
+ bitwise OR, and writes the result back to the bit field in the
+ 16-bit port.
+
+ Reads the 16-bit I/O port specified by Port, performs a bitwise AND followed
+ by a bitwise OR between the read result and the value specified by
+ AndData, and writes the result to the 16-bit I/O port specified by Port. The
+ value written to the I/O port is returned. This function must guarantee that
+ all I/O read and write operations are serialized. Extra left bits in both
+ AndData and OrData are stripped.
+
+ If 16-bit I/O port operations are not supported, then ASSERT().
+ If Port is not aligned on a 16-bit boundary, then ASSERT().
+ If StartBit is greater than 15, then ASSERT().
+ If EndBit is greater than 15, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Port The I/O port to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..15.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..15.
+ @param AndData The value to AND with the read value from the I/O port.
+ @param OrData The value to OR with the result of the AND operation.
+
+ @return The value written back to the I/O port.
+
+**/
+UINT16
+EFIAPI
+IoBitFieldAndThenOr16 (
+ IN UINTN Port,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT16 AndData,
+ IN UINT16 OrData
+ );
+
+/**
+ Reads a 32-bit I/O port.
+
+ Reads the 32-bit I/O port specified by Port. The 32-bit read value is returned.
+ This function must guarantee that all I/O read and write operations are
+ serialized.
+
+ If 32-bit I/O port operations are not supported, then ASSERT().
+ If Port is not aligned on a 32-bit boundary, then ASSERT().
+
+ @param Port The I/O port to read.
+
+ @return The value read.
+
+**/
+UINT32
+EFIAPI
+IoRead32 (
+ IN UINTN Port
+ );
+
+/**
+ Writes a 32-bit I/O port.
+
+ Writes the 32-bit I/O port specified by Port with the value specified by Value
+ and returns Value. This function must guarantee that all I/O read and write
+ operations are serialized.
+
+ If 32-bit I/O port operations are not supported, then ASSERT().
+ If Port is not aligned on a 32-bit boundary, then ASSERT().
+
+ @param Port The I/O port to write.
+ @param Value The value to write to the I/O port.
+
+ @return The value written the I/O port.
+
+**/
+UINT32
+EFIAPI
+IoWrite32 (
+ IN UINTN Port,
+ IN UINT32 Value
+ );
+
+/**
+ Reads a 32-bit I/O port fifo into a block of memory.
+
+ Reads the 32-bit I/O fifo port specified by Port.
+ The port is read Count times, and the read data is
+ stored in the provided Buffer.
+
+ This function must guarantee that all I/O read and write operations are
+ serialized.
+
+ If 32-bit I/O port operations are not supported, then ASSERT().
+
+ @param Port The I/O port to read.
+ @param Count The number of times to read I/O port.
+ @param Buffer The buffer to store the read data into.
+
+**/
+VOID
+EFIAPI
+IoReadFifo32 (
+ IN UINTN Port,
+ IN UINTN Count,
+ OUT VOID *Buffer
+ );
+
+/**
+ Writes a block of memory into a 32-bit I/O port fifo.
+
+ Writes the 32-bit I/O fifo port specified by Port.
+ The port is written Count times, and the write data is
+ retrieved from the provided Buffer.
+
+ This function must guarantee that all I/O write and write operations are
+ serialized.
+
+ If 32-bit I/O port operations are not supported, then ASSERT().
+
+ @param Port The I/O port to write.
+ @param Count The number of times to write I/O port.
+ @param Buffer The buffer to retrieve the write data from.
+
+**/
+VOID
+EFIAPI
+IoWriteFifo32 (
+ IN UINTN Port,
+ IN UINTN Count,
+ IN VOID *Buffer
+ );
+
+/**
+ Reads a 32-bit I/O port, performs a bitwise OR, and writes the
+ result back to the 32-bit I/O port.
+
+ Reads the 32-bit I/O port specified by Port, performs a bitwise OR
+ between the read result and the value specified by OrData, and writes the
+ result to the 32-bit I/O port specified by Port. The value written to the I/O
+ port is returned. This function must guarantee that all I/O read and write
+ operations are serialized.
+
+ If 32-bit I/O port operations are not supported, then ASSERT().
+ If Port is not aligned on a 32-bit boundary, then ASSERT().
+
+ @param Port The I/O port to write.
+ @param OrData The value to OR with the read value from the I/O port.
+
+ @return The value written back to the I/O port.
+
+**/
+UINT32
+EFIAPI
+IoOr32 (
+ IN UINTN Port,
+ IN UINT32 OrData
+ );
+
+/**
+ Reads a 32-bit I/O port, performs a bitwise AND, and writes the result back
+ to the 32-bit I/O port.
+
+ Reads the 32-bit I/O port specified by Port, performs a bitwise AND between
+ the read result and the value specified by AndData, and writes the result to
+ the 32-bit I/O port specified by Port. The value written to the I/O port is
+ returned. This function must guarantee that all I/O read and write operations
+ are serialized.
+
+ If 32-bit I/O port operations are not supported, then ASSERT().
+ If Port is not aligned on a 32-bit boundary, then ASSERT().
+
+ @param Port The I/O port to write.
+ @param AndData The value to AND with the read value from the I/O port.
+
+ @return The value written back to the I/O port.
+
+**/
+UINT32
+EFIAPI
+IoAnd32 (
+ IN UINTN Port,
+ IN UINT32 AndData
+ );
+
+/**
+ Reads a 32-bit I/O port, performs a bitwise AND followed by a bitwise
+ OR, and writes the result back to the 32-bit I/O port.
+
+ Reads the 32-bit I/O port specified by Port, performs a bitwise AND between
+ the read result and the value specified by AndData, performs a bitwise OR
+ between the result of the AND operation and the value specified by OrData,
+ and writes the result to the 32-bit I/O port specified by Port. The value
+ written to the I/O port is returned. This function must guarantee that all
+ I/O read and write operations are serialized.
+
+ If 32-bit I/O port operations are not supported, then ASSERT().
+ If Port is not aligned on a 32-bit boundary, then ASSERT().
+
+ @param Port The I/O port to write.
+ @param AndData The value to AND with the read value from the I/O port.
+ @param OrData The value to OR with the result of the AND operation.
+
+ @return The value written back to the I/O port.
+
+**/
+UINT32
+EFIAPI
+IoAndThenOr32 (
+ IN UINTN Port,
+ IN UINT32 AndData,
+ IN UINT32 OrData
+ );
+
+/**
+ Reads a bit field of an I/O register.
+
+ Reads the bit field in a 32-bit I/O register. The bit field is specified by
+ the StartBit and the EndBit. The value of the bit field is returned.
+
+ If 32-bit I/O port operations are not supported, then ASSERT().
+ If Port is not aligned on a 32-bit boundary, then ASSERT().
+ If StartBit is greater than 31, then ASSERT().
+ If EndBit is greater than 31, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+
+ @param Port The I/O port to read.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..31.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..31.
+
+ @return The value read.
+
+**/
+UINT32
+EFIAPI
+IoBitFieldRead32 (
+ IN UINTN Port,
+ IN UINTN StartBit,
+ IN UINTN EndBit
+ );
+
+/**
+ Writes a bit field to an I/O register.
+
+ Writes Value to the bit field of the I/O register. The bit field is specified
+ by the StartBit and the EndBit. All other bits in the destination I/O
+ register are preserved. The value written to the I/O port is returned. Extra
+ left bits in Value are stripped.
+
+ If 32-bit I/O port operations are not supported, then ASSERT().
+ If Port is not aligned on a 32-bit boundary, then ASSERT().
+ If StartBit is greater than 31, then ASSERT().
+ If EndBit is greater than 31, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Port The I/O port to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..31.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..31.
+ @param Value New value of the bit field.
+
+ @return The value written back to the I/O port.
+
+**/
+UINT32
+EFIAPI
+IoBitFieldWrite32 (
+ IN UINTN Port,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 Value
+ );
+
+/**
+ Reads a bit field in a 32-bit port, performs a bitwise OR, and writes the
+ result back to the bit field in the 32-bit port.
+
+ Reads the 32-bit I/O port specified by Port, performs a bitwise OR
+ between the read result and the value specified by OrData, and writes the
+ result to the 32-bit I/O port specified by Port. The value written to the I/O
+ port is returned. This function must guarantee that all I/O read and write
+ operations are serialized. Extra left bits in OrData are stripped.
+
+ If 32-bit I/O port operations are not supported, then ASSERT().
+ If Port is not aligned on a 32-bit boundary, then ASSERT().
+ If StartBit is greater than 31, then ASSERT().
+ If EndBit is greater than 31, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Port The I/O port to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..31.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..31.
+ @param OrData The value to OR with the read value from the I/O port.
+
+ @return The value written back to the I/O port.
+
+**/
+UINT32
+EFIAPI
+IoBitFieldOr32 (
+ IN UINTN Port,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 OrData
+ );
+
+/**
+ Reads a bit field in a 32-bit port, performs a bitwise AND, and writes the
+ result back to the bit field in the 32-bit port.
+
+ Reads the 32-bit I/O port specified by Port, performs a bitwise AND between
+ the read result and the value specified by AndData, and writes the result to
+ the 32-bit I/O port specified by Port. The value written to the I/O port is
+ returned. This function must guarantee that all I/O read and write operations
+ are serialized. Extra left bits in AndData are stripped.
+
+ If 32-bit I/O port operations are not supported, then ASSERT().
+ If Port is not aligned on a 32-bit boundary, then ASSERT().
+ If StartBit is greater than 31, then ASSERT().
+ If EndBit is greater than 31, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Port The I/O port to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..31.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..31.
+ @param AndData The value to AND with the read value from the I/O port.
+
+ @return The value written back to the I/O port.
+
+**/
+UINT32
+EFIAPI
+IoBitFieldAnd32 (
+ IN UINTN Port,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 AndData
+ );
+
+/**
+ Reads a bit field in a 32-bit port, performs a bitwise AND followed by a
+ bitwise OR, and writes the result back to the bit field in the
+ 32-bit port.
+
+ Reads the 32-bit I/O port specified by Port, performs a bitwise AND followed
+ by a bitwise OR between the read result and the value specified by
+ AndData, and writes the result to the 32-bit I/O port specified by Port. The
+ value written to the I/O port is returned. This function must guarantee that
+ all I/O read and write operations are serialized. Extra left bits in both
+ AndData and OrData are stripped.
+
+ If 32-bit I/O port operations are not supported, then ASSERT().
+ If Port is not aligned on a 32-bit boundary, then ASSERT().
+ If StartBit is greater than 31, then ASSERT().
+ If EndBit is greater than 31, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Port The I/O port to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..31.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..31.
+ @param AndData The value to AND with the read value from the I/O port.
+ @param OrData The value to OR with the result of the AND operation.
+
+ @return The value written back to the I/O port.
+
+**/
+UINT32
+EFIAPI
+IoBitFieldAndThenOr32 (
+ IN UINTN Port,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 AndData,
+ IN UINT32 OrData
+ );
+
+/**
+ Reads a 64-bit I/O port.
+
+ Reads the 64-bit I/O port specified by Port. The 64-bit read value is returned.
+ This function must guarantee that all I/O read and write operations are
+ serialized.
+
+ If 64-bit I/O port operations are not supported, then ASSERT().
+ If Port is not aligned on a 64-bit boundary, then ASSERT().
+
+ @param Port The I/O port to read.
+
+ @return The value read.
+
+**/
+UINT64
+EFIAPI
+IoRead64 (
+ IN UINTN Port
+ );
+
+/**
+ Writes a 64-bit I/O port.
+
+ Writes the 64-bit I/O port specified by Port with the value specified by Value
+ and returns Value. This function must guarantee that all I/O read and write
+ operations are serialized.
+
+ If 64-bit I/O port operations are not supported, then ASSERT().
+ If Port is not aligned on a 64-bit boundary, then ASSERT().
+
+ @param Port The I/O port to write.
+ @param Value The value to write to the I/O port.
+
+ @return The value written the I/O port.
+
+**/
+UINT64
+EFIAPI
+IoWrite64 (
+ IN UINTN Port,
+ IN UINT64 Value
+ );
+
+/**
+ Reads a 64-bit I/O port, performs a bitwise OR, and writes the
+ result back to the 64-bit I/O port.
+
+ Reads the 64-bit I/O port specified by Port, performs a bitwise OR
+ between the read result and the value specified by OrData, and writes the
+ result to the 64-bit I/O port specified by Port. The value written to the I/O
+ port is returned. This function must guarantee that all I/O read and write
+ operations are serialized.
+
+ If 64-bit I/O port operations are not supported, then ASSERT().
+ If Port is not aligned on a 64-bit boundary, then ASSERT().
+
+ @param Port The I/O port to write.
+ @param OrData The value to OR with the read value from the I/O port.
+
+ @return The value written back to the I/O port.
+
+**/
+UINT64
+EFIAPI
+IoOr64 (
+ IN UINTN Port,
+ IN UINT64 OrData
+ );
+
+/**
+ Reads a 64-bit I/O port, performs a bitwise AND, and writes the result back
+ to the 64-bit I/O port.
+
+ Reads the 64-bit I/O port specified by Port, performs a bitwise AND between
+ the read result and the value specified by AndData, and writes the result to
+ the 64-bit I/O port specified by Port. The value written to the I/O port is
+ returned. This function must guarantee that all I/O read and write operations
+ are serialized.
+
+ If 64-bit I/O port operations are not supported, then ASSERT().
+ If Port is not aligned on a 64-bit boundary, then ASSERT().
+
+ @param Port The I/O port to write.
+ @param AndData The value to AND with the read value from the I/O port.
+
+ @return The value written back to the I/O port.
+
+**/
+UINT64
+EFIAPI
+IoAnd64 (
+ IN UINTN Port,
+ IN UINT64 AndData
+ );
+
+/**
+ Reads a 64-bit I/O port, performs a bitwise AND followed by a bitwise
+ OR, and writes the result back to the 64-bit I/O port.
+
+ Reads the 64-bit I/O port specified by Port, performs a bitwise AND between
+ the read result and the value specified by AndData, performs a bitwise OR
+ between the result of the AND operation and the value specified by OrData,
+ and writes the result to the 64-bit I/O port specified by Port. The value
+ written to the I/O port is returned. This function must guarantee that all
+ I/O read and write operations are serialized.
+
+ If 64-bit I/O port operations are not supported, then ASSERT().
+ If Port is not aligned on a 64-bit boundary, then ASSERT().
+
+ @param Port The I/O port to write.
+ @param AndData The value to AND with the read value from the I/O port.
+ @param OrData The value to OR with the result of the AND operation.
+
+ @return The value written back to the I/O port.
+
+**/
+UINT64
+EFIAPI
+IoAndThenOr64 (
+ IN UINTN Port,
+ IN UINT64 AndData,
+ IN UINT64 OrData
+ );
+
+/**
+ Reads a bit field of an I/O register.
+
+ Reads the bit field in a 64-bit I/O register. The bit field is specified by
+ the StartBit and the EndBit. The value of the bit field is returned.
+
+ If 64-bit I/O port operations are not supported, then ASSERT().
+ If Port is not aligned on a 64-bit boundary, then ASSERT().
+ If StartBit is greater than 63, then ASSERT().
+ If EndBit is greater than 63, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+
+ @param Port The I/O port to read.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..63.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..63.
+
+ @return The value read.
+
+**/
+UINT64
+EFIAPI
+IoBitFieldRead64 (
+ IN UINTN Port,
+ IN UINTN StartBit,
+ IN UINTN EndBit
+ );
+
+/**
+ Writes a bit field to an I/O register.
+
+ Writes Value to the bit field of the I/O register. The bit field is specified
+ by the StartBit and the EndBit. All other bits in the destination I/O
+ register are preserved. The value written to the I/O port is returned. Extra
+ left bits in Value are stripped.
+
+ If 64-bit I/O port operations are not supported, then ASSERT().
+ If Port is not aligned on a 64-bit boundary, then ASSERT().
+ If StartBit is greater than 63, then ASSERT().
+ If EndBit is greater than 63, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Port The I/O port to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..63.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..63.
+ @param Value New value of the bit field.
+
+ @return The value written back to the I/O port.
+
+**/
+UINT64
+EFIAPI
+IoBitFieldWrite64 (
+ IN UINTN Port,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT64 Value
+ );
+
+/**
+ Reads a bit field in a 64-bit port, performs a bitwise OR, and writes the
+ result back to the bit field in the 64-bit port.
+
+ Reads the 64-bit I/O port specified by Port, performs a bitwise OR
+ between the read result and the value specified by OrData, and writes the
+ result to the 64-bit I/O port specified by Port. The value written to the I/O
+ port is returned. This function must guarantee that all I/O read and write
+ operations are serialized. Extra left bits in OrData are stripped.
+
+ If 64-bit I/O port operations are not supported, then ASSERT().
+ If Port is not aligned on a 64-bit boundary, then ASSERT().
+ If StartBit is greater than 63, then ASSERT().
+ If EndBit is greater than 63, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Port The I/O port to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..63.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..63.
+ @param OrData The value to OR with the read value from the I/O port.
+
+ @return The value written back to the I/O port.
+
+**/
+UINT64
+EFIAPI
+IoBitFieldOr64 (
+ IN UINTN Port,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT64 OrData
+ );
+
+/**
+ Reads a bit field in a 64-bit port, performs a bitwise AND, and writes the
+ result back to the bit field in the 64-bit port.
+
+ Reads the 64-bit I/O port specified by Port, performs a bitwise AND between
+ the read result and the value specified by AndData, and writes the result to
+ the 64-bit I/O port specified by Port. The value written to the I/O port is
+ returned. This function must guarantee that all I/O read and write operations
+ are serialized. Extra left bits in AndData are stripped.
+
+ If 64-bit I/O port operations are not supported, then ASSERT().
+ If Port is not aligned on a 64-bit boundary, then ASSERT().
+ If StartBit is greater than 63, then ASSERT().
+ If EndBit is greater than 63, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Port The I/O port to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..63.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..63.
+ @param AndData The value to AND with the read value from the I/O port.
+
+ @return The value written back to the I/O port.
+
+**/
+UINT64
+EFIAPI
+IoBitFieldAnd64 (
+ IN UINTN Port,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT64 AndData
+ );
+
+/**
+ Reads a bit field in a 64-bit port, performs a bitwise AND followed by a
+ bitwise OR, and writes the result back to the bit field in the
+ 64-bit port.
+
+ Reads the 64-bit I/O port specified by Port, performs a bitwise AND followed
+ by a bitwise OR between the read result and the value specified by
+ AndData, and writes the result to the 64-bit I/O port specified by Port. The
+ value written to the I/O port is returned. This function must guarantee that
+ all I/O read and write operations are serialized. Extra left bits in both
+ AndData and OrData are stripped.
+
+ If 64-bit I/O port operations are not supported, then ASSERT().
+ If Port is not aligned on a 64-bit boundary, then ASSERT().
+ If StartBit is greater than 63, then ASSERT().
+ If EndBit is greater than 63, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Port The I/O port to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..63.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..63.
+ @param AndData The value to AND with the read value from the I/O port.
+ @param OrData The value to OR with the result of the AND operation.
+
+ @return The value written back to the I/O port.
+
+**/
+UINT64
+EFIAPI
+IoBitFieldAndThenOr64 (
+ IN UINTN Port,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT64 AndData,
+ IN UINT64 OrData
+ );
+
+/**
+ Reads an 8-bit MMIO register.
+
+ Reads the 8-bit MMIO register specified by Address. The 8-bit read value is
+ returned. This function must guarantee that all MMIO read and write
+ operations are serialized.
+
+ If 8-bit MMIO register operations are not supported, then ASSERT().
+
+ @param Address The MMIO register to read.
+
+ @return The value read.
+
+**/
+UINT8
+EFIAPI
+MmioRead8 (
+ IN UINTN Address
+ );
+
+/**
+ Writes an 8-bit MMIO register.
+
+ Writes the 8-bit MMIO register specified by Address with the value specified
+ by Value and returns Value. This function must guarantee that all MMIO read
+ and write operations are serialized.
+
+ If 8-bit MMIO register operations are not supported, then ASSERT().
+
+ @param Address The MMIO register to write.
+ @param Value The value to write to the MMIO register.
+
+ @return Value.
+
+**/
+UINT8
+EFIAPI
+MmioWrite8 (
+ IN UINTN Address,
+ IN UINT8 Value
+ );
+
+/**
+ Reads an 8-bit MMIO register, performs a bitwise OR, and writes the
+ result back to the 8-bit MMIO register.
+
+ Reads the 8-bit MMIO register specified by Address, performs a bitwise
+ OR between the read result and the value specified by OrData, and
+ writes the result to the 8-bit MMIO register specified by Address. The value
+ written to the MMIO register is returned. This function must guarantee that
+ all MMIO read and write operations are serialized.
+
+ If 8-bit MMIO register operations are not supported, then ASSERT().
+
+ @param Address The MMIO register to write.
+ @param OrData The value to OR with the read value from the MMIO register.
+
+ @return The value written back to the MMIO register.
+
+**/
+UINT8
+EFIAPI
+MmioOr8 (
+ IN UINTN Address,
+ IN UINT8 OrData
+ );
+
+/**
+ Reads an 8-bit MMIO register, performs a bitwise AND, and writes the result
+ back to the 8-bit MMIO register.
+
+ Reads the 8-bit MMIO register specified by Address, performs a bitwise AND
+ between the read result and the value specified by AndData, and writes the
+ result to the 8-bit MMIO register specified by Address. The value written to
+ the MMIO register is returned. This function must guarantee that all MMIO
+ read and write operations are serialized.
+
+ If 8-bit MMIO register operations are not supported, then ASSERT().
+
+ @param Address The MMIO register to write.
+ @param AndData The value to AND with the read value from the MMIO register.
+
+ @return The value written back to the MMIO register.
+
+**/
+UINT8
+EFIAPI
+MmioAnd8 (
+ IN UINTN Address,
+ IN UINT8 AndData
+ );
+
+/**
+ Reads an 8-bit MMIO register, performs a bitwise AND followed by a bitwise
+ OR, and writes the result back to the 8-bit MMIO register.
+
+ Reads the 8-bit MMIO register specified by Address, performs a bitwise AND
+ between the read result and the value specified by AndData, performs a
+ bitwise OR between the result of the AND operation and the value specified by
+ OrData, and writes the result to the 8-bit MMIO register specified by
+ Address. The value written to the MMIO register is returned. This function
+ must guarantee that all MMIO read and write operations are serialized.
+
+ If 8-bit MMIO register operations are not supported, then ASSERT().
+
+
+ @param Address The MMIO register to write.
+ @param AndData The value to AND with the read value from the MMIO register.
+ @param OrData The value to OR with the result of the AND operation.
+
+ @return The value written back to the MMIO register.
+
+**/
+UINT8
+EFIAPI
+MmioAndThenOr8 (
+ IN UINTN Address,
+ IN UINT8 AndData,
+ IN UINT8 OrData
+ );
+
+/**
+ Reads a bit field of a MMIO register.
+
+ Reads the bit field in an 8-bit MMIO register. The bit field is specified by
+ the StartBit and the EndBit. The value of the bit field is returned.
+
+ If 8-bit MMIO register operations are not supported, then ASSERT().
+ If StartBit is greater than 7, then ASSERT().
+ If EndBit is greater than 7, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+
+ @param Address MMIO register to read.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..7.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..7.
+
+ @return The value read.
+
+**/
+UINT8
+EFIAPI
+MmioBitFieldRead8 (
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit
+ );
+
+/**
+ Writes a bit field to a MMIO register.
+
+ Writes Value to the bit field of the MMIO register. The bit field is
+ specified by the StartBit and the EndBit. All other bits in the destination
+ MMIO register are preserved. The new value of the 8-bit register is returned.
+
+ If 8-bit MMIO register operations are not supported, then ASSERT().
+ If StartBit is greater than 7, then ASSERT().
+ If EndBit is greater than 7, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Address MMIO register to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..7.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..7.
+ @param Value New value of the bit field.
+
+ @return The value written back to the MMIO register.
+
+**/
+UINT8
+EFIAPI
+MmioBitFieldWrite8 (
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT8 Value
+ );
+
+/**
+ Reads a bit field in an 8-bit MMIO register, performs a bitwise OR, and
+ writes the result back to the bit field in the 8-bit MMIO register.
+
+ Reads the 8-bit MMIO register specified by Address, performs a bitwise
+ OR between the read result and the value specified by OrData, and
+ writes the result to the 8-bit MMIO register specified by Address. The value
+ written to the MMIO register is returned. This function must guarantee that
+ all MMIO read and write operations are serialized. Extra left bits in OrData
+ are stripped.
+
+ If 8-bit MMIO register operations are not supported, then ASSERT().
+ If StartBit is greater than 7, then ASSERT().
+ If EndBit is greater than 7, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Address MMIO register to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..7.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..7.
+ @param OrData The value to OR with read value from the MMIO register.
+
+ @return The value written back to the MMIO register.
+
+**/
+UINT8
+EFIAPI
+MmioBitFieldOr8 (
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT8 OrData
+ );
+
+/**
+ Reads a bit field in an 8-bit MMIO register, performs a bitwise AND, and
+ writes the result back to the bit field in the 8-bit MMIO register.
+
+ Reads the 8-bit MMIO register specified by Address, performs a bitwise AND
+ between the read result and the value specified by AndData, and writes the
+ result to the 8-bit MMIO register specified by Address. The value written to
+ the MMIO register is returned. This function must guarantee that all MMIO
+ read and write operations are serialized. Extra left bits in AndData are
+ stripped.
+
+ If 8-bit MMIO register operations are not supported, then ASSERT().
+ If StartBit is greater than 7, then ASSERT().
+ If EndBit is greater than 7, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Address MMIO register to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..7.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..7.
+ @param AndData The value to AND with read value from the MMIO register.
+
+ @return The value written back to the MMIO register.
+
+**/
+UINT8
+EFIAPI
+MmioBitFieldAnd8 (
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT8 AndData
+ );
+
+/**
+ Reads a bit field in an 8-bit MMIO register, performs a bitwise AND followed
+ by a bitwise OR, and writes the result back to the bit field in the
+ 8-bit MMIO register.
+
+ Reads the 8-bit MMIO register specified by Address, performs a bitwise AND
+ followed by a bitwise OR between the read result and the value
+ specified by AndData, and writes the result to the 8-bit MMIO register
+ specified by Address. The value written to the MMIO register is returned.
+ This function must guarantee that all MMIO read and write operations are
+ serialized. Extra left bits in both AndData and OrData are stripped.
+
+ If 8-bit MMIO register operations are not supported, then ASSERT().
+ If StartBit is greater than 7, then ASSERT().
+ If EndBit is greater than 7, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Address MMIO register to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..7.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..7.
+ @param AndData The value to AND with read value from the MMIO register.
+ @param OrData The value to OR with the result of the AND operation.
+
+ @return The value written back to the MMIO register.
+
+**/
+UINT8
+EFIAPI
+MmioBitFieldAndThenOr8 (
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT8 AndData,
+ IN UINT8 OrData
+ );
+
+/**
+ Reads a 16-bit MMIO register.
+
+ Reads the 16-bit MMIO register specified by Address. The 16-bit read value is
+ returned. This function must guarantee that all MMIO read and write
+ operations are serialized.
+
+ If 16-bit MMIO register operations are not supported, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+
+ @param Address The MMIO register to read.
+
+ @return The value read.
+
+**/
+UINT16
+EFIAPI
+MmioRead16 (
+ IN UINTN Address
+ );
+
+/**
+ Writes a 16-bit MMIO register.
+
+ Writes the 16-bit MMIO register specified by Address with the value specified
+ by Value and returns Value. This function must guarantee that all MMIO read
+ and write operations are serialized.
+
+ If 16-bit MMIO register operations are not supported, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+
+ @param Address The MMIO register to write.
+ @param Value The value to write to the MMIO register.
+
+ @return Value.
+
+**/
+UINT16
+EFIAPI
+MmioWrite16 (
+ IN UINTN Address,
+ IN UINT16 Value
+ );
+
+/**
+ Reads a 16-bit MMIO register, performs a bitwise OR, and writes the
+ result back to the 16-bit MMIO register.
+
+ Reads the 16-bit MMIO register specified by Address, performs a bitwise
+ OR between the read result and the value specified by OrData, and
+ writes the result to the 16-bit MMIO register specified by Address. The value
+ written to the MMIO register is returned. This function must guarantee that
+ all MMIO read and write operations are serialized.
+
+ If 16-bit MMIO register operations are not supported, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+
+ @param Address The MMIO register to write.
+ @param OrData The value to OR with the read value from the MMIO register.
+
+ @return The value written back to the MMIO register.
+
+**/
+UINT16
+EFIAPI
+MmioOr16 (
+ IN UINTN Address,
+ IN UINT16 OrData
+ );
+
+/**
+ Reads a 16-bit MMIO register, performs a bitwise AND, and writes the result
+ back to the 16-bit MMIO register.
+
+ Reads the 16-bit MMIO register specified by Address, performs a bitwise AND
+ between the read result and the value specified by AndData, and writes the
+ result to the 16-bit MMIO register specified by Address. The value written to
+ the MMIO register is returned. This function must guarantee that all MMIO
+ read and write operations are serialized.
+
+ If 16-bit MMIO register operations are not supported, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+
+ @param Address The MMIO register to write.
+ @param AndData The value to AND with the read value from the MMIO register.
+
+ @return The value written back to the MMIO register.
+
+**/
+UINT16
+EFIAPI
+MmioAnd16 (
+ IN UINTN Address,
+ IN UINT16 AndData
+ );
+
+/**
+ Reads a 16-bit MMIO register, performs a bitwise AND followed by a bitwise
+ OR, and writes the result back to the 16-bit MMIO register.
+
+ Reads the 16-bit MMIO register specified by Address, performs a bitwise AND
+ between the read result and the value specified by AndData, performs a
+ bitwise OR between the result of the AND operation and the value specified by
+ OrData, and writes the result to the 16-bit MMIO register specified by
+ Address. The value written to the MMIO register is returned. This function
+ must guarantee that all MMIO read and write operations are serialized.
+
+ If 16-bit MMIO register operations are not supported, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+
+ @param Address The MMIO register to write.
+ @param AndData The value to AND with the read value from the MMIO register.
+ @param OrData The value to OR with the result of the AND operation.
+
+ @return The value written back to the MMIO register.
+
+**/
+UINT16
+EFIAPI
+MmioAndThenOr16 (
+ IN UINTN Address,
+ IN UINT16 AndData,
+ IN UINT16 OrData
+ );
+
+/**
+ Reads a bit field of a MMIO register.
+
+ Reads the bit field in a 16-bit MMIO register. The bit field is specified by
+ the StartBit and the EndBit. The value of the bit field is returned.
+
+ If 16-bit MMIO register operations are not supported, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+ If StartBit is greater than 15, then ASSERT().
+ If EndBit is greater than 15, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+
+ @param Address MMIO register to read.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..15.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..15.
+
+ @return The value read.
+
+**/
+UINT16
+EFIAPI
+MmioBitFieldRead16 (
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit
+ );
+
+/**
+ Writes a bit field to a MMIO register.
+
+ Writes Value to the bit field of the MMIO register. The bit field is
+ specified by the StartBit and the EndBit. All other bits in the destination
+ MMIO register are preserved. The new value of the 16-bit register is returned.
+
+ If 16-bit MMIO register operations are not supported, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+ If StartBit is greater than 15, then ASSERT().
+ If EndBit is greater than 15, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Address MMIO register to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..15.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..15.
+ @param Value New value of the bit field.
+
+ @return The value written back to the MMIO register.
+
+**/
+UINT16
+EFIAPI
+MmioBitFieldWrite16 (
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT16 Value
+ );
+
+/**
+ Reads a bit field in a 16-bit MMIO register, performs a bitwise OR, and
+ writes the result back to the bit field in the 16-bit MMIO register.
+
+ Reads the 16-bit MMIO register specified by Address, performs a bitwise
+ OR between the read result and the value specified by OrData, and
+ writes the result to the 16-bit MMIO register specified by Address. The value
+ written to the MMIO register is returned. This function must guarantee that
+ all MMIO read and write operations are serialized. Extra left bits in OrData
+ are stripped.
+
+ If 16-bit MMIO register operations are not supported, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+ If StartBit is greater than 15, then ASSERT().
+ If EndBit is greater than 15, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Address MMIO register to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..15.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..15.
+ @param OrData The value to OR with read value from the MMIO register.
+
+ @return The value written back to the MMIO register.
+
+**/
+UINT16
+EFIAPI
+MmioBitFieldOr16 (
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT16 OrData
+ );
+
+/**
+ Reads a bit field in a 16-bit MMIO register, performs a bitwise AND, and
+ writes the result back to the bit field in the 16-bit MMIO register.
+
+ Reads the 16-bit MMIO register specified by Address, performs a bitwise AND
+ between the read result and the value specified by AndData, and writes the
+ result to the 16-bit MMIO register specified by Address. The value written to
+ the MMIO register is returned. This function must guarantee that all MMIO
+ read and write operations are serialized. Extra left bits in AndData are
+ stripped.
+
+ If 16-bit MMIO register operations are not supported, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+ If StartBit is greater than 15, then ASSERT().
+ If EndBit is greater than 15, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Address MMIO register to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..15.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..15.
+ @param AndData The value to AND with read value from the MMIO register.
+
+ @return The value written back to the MMIO register.
+
+**/
+UINT16
+EFIAPI
+MmioBitFieldAnd16 (
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT16 AndData
+ );
+
+/**
+ Reads a bit field in a 16-bit MMIO register, performs a bitwise AND followed
+ by a bitwise OR, and writes the result back to the bit field in the
+ 16-bit MMIO register.
+
+ Reads the 16-bit MMIO register specified by Address, performs a bitwise AND
+ followed by a bitwise OR between the read result and the value
+ specified by AndData, and writes the result to the 16-bit MMIO register
+ specified by Address. The value written to the MMIO register is returned.
+ This function must guarantee that all MMIO read and write operations are
+ serialized. Extra left bits in both AndData and OrData are stripped.
+
+ If 16-bit MMIO register operations are not supported, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+ If StartBit is greater than 15, then ASSERT().
+ If EndBit is greater than 15, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Address MMIO register to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..15.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..15.
+ @param AndData The value to AND with read value from the MMIO register.
+ @param OrData The value to OR with the result of the AND operation.
+
+ @return The value written back to the MMIO register.
+
+**/
+UINT16
+EFIAPI
+MmioBitFieldAndThenOr16 (
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT16 AndData,
+ IN UINT16 OrData
+ );
+
+/**
+ Reads a 32-bit MMIO register.
+
+ Reads the 32-bit MMIO register specified by Address. The 32-bit read value is
+ returned. This function must guarantee that all MMIO read and write
+ operations are serialized.
+
+ If 32-bit MMIO register operations are not supported, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+
+ @param Address The MMIO register to read.
+
+ @return The value read.
+
+**/
+UINT32
+EFIAPI
+MmioRead32 (
+ IN UINTN Address
+ );
+
+/**
+ Writes a 32-bit MMIO register.
+
+ Writes the 32-bit MMIO register specified by Address with the value specified
+ by Value and returns Value. This function must guarantee that all MMIO read
+ and write operations are serialized.
+
+ If 32-bit MMIO register operations are not supported, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+
+ @param Address The MMIO register to write.
+ @param Value The value to write to the MMIO register.
+
+ @return Value.
+
+**/
+UINT32
+EFIAPI
+MmioWrite32 (
+ IN UINTN Address,
+ IN UINT32 Value
+ );
+
+/**
+ Reads a 32-bit MMIO register, performs a bitwise OR, and writes the
+ result back to the 32-bit MMIO register.
+
+ Reads the 32-bit MMIO register specified by Address, performs a bitwise
+ OR between the read result and the value specified by OrData, and
+ writes the result to the 32-bit MMIO register specified by Address. The value
+ written to the MMIO register is returned. This function must guarantee that
+ all MMIO read and write operations are serialized.
+
+ If 32-bit MMIO register operations are not supported, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+
+ @param Address The MMIO register to write.
+ @param OrData The value to OR with the read value from the MMIO register.
+
+ @return The value written back to the MMIO register.
+
+**/
+UINT32
+EFIAPI
+MmioOr32 (
+ IN UINTN Address,
+ IN UINT32 OrData
+ );
+
+/**
+ Reads a 32-bit MMIO register, performs a bitwise AND, and writes the result
+ back to the 32-bit MMIO register.
+
+ Reads the 32-bit MMIO register specified by Address, performs a bitwise AND
+ between the read result and the value specified by AndData, and writes the
+ result to the 32-bit MMIO register specified by Address. The value written to
+ the MMIO register is returned. This function must guarantee that all MMIO
+ read and write operations are serialized.
+
+ If 32-bit MMIO register operations are not supported, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+
+ @param Address The MMIO register to write.
+ @param AndData The value to AND with the read value from the MMIO register.
+
+ @return The value written back to the MMIO register.
+
+**/
+UINT32
+EFIAPI
+MmioAnd32 (
+ IN UINTN Address,
+ IN UINT32 AndData
+ );
+
+/**
+ Reads a 32-bit MMIO register, performs a bitwise AND followed by a bitwise
+ OR, and writes the result back to the 32-bit MMIO register.
+
+ Reads the 32-bit MMIO register specified by Address, performs a bitwise AND
+ between the read result and the value specified by AndData, performs a
+ bitwise OR between the result of the AND operation and the value specified by
+ OrData, and writes the result to the 32-bit MMIO register specified by
+ Address. The value written to the MMIO register is returned. This function
+ must guarantee that all MMIO read and write operations are serialized.
+
+ If 32-bit MMIO register operations are not supported, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+
+ @param Address The MMIO register to write.
+ @param AndData The value to AND with the read value from the MMIO register.
+ @param OrData The value to OR with the result of the AND operation.
+
+ @return The value written back to the MMIO register.
+
+**/
+UINT32
+EFIAPI
+MmioAndThenOr32 (
+ IN UINTN Address,
+ IN UINT32 AndData,
+ IN UINT32 OrData
+ );
+
+/**
+ Reads a bit field of a MMIO register.
+
+ Reads the bit field in a 32-bit MMIO register. The bit field is specified by
+ the StartBit and the EndBit. The value of the bit field is returned.
+
+ If 32-bit MMIO register operations are not supported, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+ If StartBit is greater than 31, then ASSERT().
+ If EndBit is greater than 31, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+
+ @param Address MMIO register to read.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..31.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..31.
+
+ @return The value read.
+
+**/
+UINT32
+EFIAPI
+MmioBitFieldRead32 (
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit
+ );
+
+/**
+ Writes a bit field to a MMIO register.
+
+ Writes Value to the bit field of the MMIO register. The bit field is
+ specified by the StartBit and the EndBit. All other bits in the destination
+ MMIO register are preserved. The new value of the 32-bit register is returned.
+
+ If 32-bit MMIO register operations are not supported, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+ If StartBit is greater than 31, then ASSERT().
+ If EndBit is greater than 31, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Address MMIO register to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..31.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..31.
+ @param Value New value of the bit field.
+
+ @return The value written back to the MMIO register.
+
+**/
+UINT32
+EFIAPI
+MmioBitFieldWrite32 (
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 Value
+ );
+
+/**
+ Reads a bit field in a 32-bit MMIO register, performs a bitwise OR, and
+ writes the result back to the bit field in the 32-bit MMIO register.
+
+ Reads the 32-bit MMIO register specified by Address, performs a bitwise
+ OR between the read result and the value specified by OrData, and
+ writes the result to the 32-bit MMIO register specified by Address. The value
+ written to the MMIO register is returned. This function must guarantee that
+ all MMIO read and write operations are serialized. Extra left bits in OrData
+ are stripped.
+
+ If 32-bit MMIO register operations are not supported, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+ If StartBit is greater than 31, then ASSERT().
+ If EndBit is greater than 31, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Address MMIO register to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..31.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..31.
+ @param OrData The value to OR with read value from the MMIO register.
+
+ @return The value written back to the MMIO register.
+
+**/
+UINT32
+EFIAPI
+MmioBitFieldOr32 (
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 OrData
+ );
+
+/**
+ Reads a bit field in a 32-bit MMIO register, performs a bitwise AND, and
+ writes the result back to the bit field in the 32-bit MMIO register.
+
+ Reads the 32-bit MMIO register specified by Address, performs a bitwise AND
+ between the read result and the value specified by AndData, and writes the
+ result to the 32-bit MMIO register specified by Address. The value written to
+ the MMIO register is returned. This function must guarantee that all MMIO
+ read and write operations are serialized. Extra left bits in AndData are
+ stripped.
+
+ If 32-bit MMIO register operations are not supported, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+ If StartBit is greater than 31, then ASSERT().
+ If EndBit is greater than 31, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Address MMIO register to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..31.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..31.
+ @param AndData The value to AND with read value from the MMIO register.
+
+ @return The value written back to the MMIO register.
+
+**/
+UINT32
+EFIAPI
+MmioBitFieldAnd32 (
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 AndData
+ );
+
+/**
+ Reads a bit field in a 32-bit MMIO register, performs a bitwise AND followed
+ by a bitwise OR, and writes the result back to the bit field in the
+ 32-bit MMIO register.
+
+ Reads the 32-bit MMIO register specified by Address, performs a bitwise AND
+ followed by a bitwise OR between the read result and the value
+ specified by AndData, and writes the result to the 32-bit MMIO register
+ specified by Address. The value written to the MMIO register is returned.
+ This function must guarantee that all MMIO read and write operations are
+ serialized. Extra left bits in both AndData and OrData are stripped.
+
+ If 32-bit MMIO register operations are not supported, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+ If StartBit is greater than 31, then ASSERT().
+ If EndBit is greater than 31, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Address MMIO register to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..31.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..31.
+ @param AndData The value to AND with read value from the MMIO register.
+ @param OrData The value to OR with the result of the AND operation.
+
+ @return The value written back to the MMIO register.
+
+**/
+UINT32
+EFIAPI
+MmioBitFieldAndThenOr32 (
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 AndData,
+ IN UINT32 OrData
+ );
+
+/**
+ Reads a 64-bit MMIO register.
+
+ Reads the 64-bit MMIO register specified by Address. The 64-bit read value is
+ returned. This function must guarantee that all MMIO read and write
+ operations are serialized.
+
+ If 64-bit MMIO register operations are not supported, then ASSERT().
+ If Address is not aligned on a 64-bit boundary, then ASSERT().
+
+ @param Address The MMIO register to read.
+
+ @return The value read.
+
+**/
+UINT64
+EFIAPI
+MmioRead64 (
+ IN UINTN Address
+ );
+
+/**
+ Writes a 64-bit MMIO register.
+
+ Writes the 64-bit MMIO register specified by Address with the value specified
+ by Value and returns Value. This function must guarantee that all MMIO read
+ and write operations are serialized.
+
+ If 64-bit MMIO register operations are not supported, then ASSERT().
+ If Address is not aligned on a 64-bit boundary, then ASSERT().
+
+ @param Address The MMIO register to write.
+ @param Value The value to write to the MMIO register.
+
+**/
+UINT64
+EFIAPI
+MmioWrite64 (
+ IN UINTN Address,
+ IN UINT64 Value
+ );
+
+/**
+ Reads a 64-bit MMIO register, performs a bitwise OR, and writes the
+ result back to the 64-bit MMIO register.
+
+ Reads the 64-bit MMIO register specified by Address, performs a bitwise
+ OR between the read result and the value specified by OrData, and
+ writes the result to the 64-bit MMIO register specified by Address. The value
+ written to the MMIO register is returned. This function must guarantee that
+ all MMIO read and write operations are serialized.
+
+ If 64-bit MMIO register operations are not supported, then ASSERT().
+ If Address is not aligned on a 64-bit boundary, then ASSERT().
+
+ @param Address The MMIO register to write.
+ @param OrData The value to OR with the read value from the MMIO register.
+
+ @return The value written back to the MMIO register.
+
+**/
+UINT64
+EFIAPI
+MmioOr64 (
+ IN UINTN Address,
+ IN UINT64 OrData
+ );
+
+/**
+ Reads a 64-bit MMIO register, performs a bitwise AND, and writes the result
+ back to the 64-bit MMIO register.
+
+ Reads the 64-bit MMIO register specified by Address, performs a bitwise AND
+ between the read result and the value specified by AndData, and writes the
+ result to the 64-bit MMIO register specified by Address. The value written to
+ the MMIO register is returned. This function must guarantee that all MMIO
+ read and write operations are serialized.
+
+ If 64-bit MMIO register operations are not supported, then ASSERT().
+ If Address is not aligned on a 64-bit boundary, then ASSERT().
+
+ @param Address The MMIO register to write.
+ @param AndData The value to AND with the read value from the MMIO register.
+
+ @return The value written back to the MMIO register.
+
+**/
+UINT64
+EFIAPI
+MmioAnd64 (
+ IN UINTN Address,
+ IN UINT64 AndData
+ );
+
+/**
+ Reads a 64-bit MMIO register, performs a bitwise AND followed by a bitwise
+ OR, and writes the result back to the 64-bit MMIO register.
+
+ Reads the 64-bit MMIO register specified by Address, performs a bitwise AND
+ between the read result and the value specified by AndData, performs a
+ bitwise OR between the result of the AND operation and the value specified by
+ OrData, and writes the result to the 64-bit MMIO register specified by
+ Address. The value written to the MMIO register is returned. This function
+ must guarantee that all MMIO read and write operations are serialized.
+
+ If 64-bit MMIO register operations are not supported, then ASSERT().
+ If Address is not aligned on a 64-bit boundary, then ASSERT().
+
+ @param Address The MMIO register to write.
+ @param AndData The value to AND with the read value from the MMIO register.
+ @param OrData The value to OR with the result of the AND operation.
+
+ @return The value written back to the MMIO register.
+
+**/
+UINT64
+EFIAPI
+MmioAndThenOr64 (
+ IN UINTN Address,
+ IN UINT64 AndData,
+ IN UINT64 OrData
+ );
+
+/**
+ Reads a bit field of a MMIO register.
+
+ Reads the bit field in a 64-bit MMIO register. The bit field is specified by
+ the StartBit and the EndBit. The value of the bit field is returned.
+
+ If 64-bit MMIO register operations are not supported, then ASSERT().
+ If Address is not aligned on a 64-bit boundary, then ASSERT().
+ If StartBit is greater than 63, then ASSERT().
+ If EndBit is greater than 63, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+
+ @param Address MMIO register to read.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..63.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..63.
+
+ @return The value read.
+
+**/
+UINT64
+EFIAPI
+MmioBitFieldRead64 (
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit
+ );
+
+/**
+ Writes a bit field to a MMIO register.
+
+ Writes Value to the bit field of the MMIO register. The bit field is
+ specified by the StartBit and the EndBit. All other bits in the destination
+ MMIO register are preserved. The new value of the 64-bit register is returned.
+
+ If 64-bit MMIO register operations are not supported, then ASSERT().
+ If Address is not aligned on a 64-bit boundary, then ASSERT().
+ If StartBit is greater than 63, then ASSERT().
+ If EndBit is greater than 63, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Address MMIO register to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..63.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..63.
+ @param Value New value of the bit field.
+
+ @return The value written back to the MMIO register.
+
+**/
+UINT64
+EFIAPI
+MmioBitFieldWrite64 (
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT64 Value
+ );
+
+/**
+ Reads a bit field in a 64-bit MMIO register, performs a bitwise OR, and
+ writes the result back to the bit field in the 64-bit MMIO register.
+
+ Reads the 64-bit MMIO register specified by Address, performs a bitwise
+ OR between the read result and the value specified by OrData, and
+ writes the result to the 64-bit MMIO register specified by Address. The value
+ written to the MMIO register is returned. This function must guarantee that
+ all MMIO read and write operations are serialized. Extra left bits in OrData
+ are stripped.
+
+ If 64-bit MMIO register operations are not supported, then ASSERT().
+ If Address is not aligned on a 64-bit boundary, then ASSERT().
+ If StartBit is greater than 63, then ASSERT().
+ If EndBit is greater than 63, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Address MMIO register to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..63.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..63.
+ @param OrData The value to OR with read value from the MMIO register.
+
+ @return The value written back to the MMIO register.
+
+**/
+UINT64
+EFIAPI
+MmioBitFieldOr64 (
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT64 OrData
+ );
+
+/**
+ Reads a bit field in a 64-bit MMIO register, performs a bitwise AND, and
+ writes the result back to the bit field in the 64-bit MMIO register.
+
+ Reads the 64-bit MMIO register specified by Address, performs a bitwise AND
+ between the read result and the value specified by AndData, and writes the
+ result to the 64-bit MMIO register specified by Address. The value written to
+ the MMIO register is returned. This function must guarantee that all MMIO
+ read and write operations are serialized. Extra left bits in AndData are
+ stripped.
+
+ If 64-bit MMIO register operations are not supported, then ASSERT().
+ If Address is not aligned on a 64-bit boundary, then ASSERT().
+ If StartBit is greater than 63, then ASSERT().
+ If EndBit is greater than 63, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Address MMIO register to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..63.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..63.
+ @param AndData The value to AND with read value from the MMIO register.
+
+ @return The value written back to the MMIO register.
+
+**/
+UINT64
+EFIAPI
+MmioBitFieldAnd64 (
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT64 AndData
+ );
+
+/**
+ Reads a bit field in a 64-bit MMIO register, performs a bitwise AND followed
+ by a bitwise OR, and writes the result back to the bit field in the
+ 64-bit MMIO register.
+
+ Reads the 64-bit MMIO register specified by Address, performs a bitwise AND
+ followed by a bitwise OR between the read result and the value
+ specified by AndData, and writes the result to the 64-bit MMIO register
+ specified by Address. The value written to the MMIO register is returned.
+ This function must guarantee that all MMIO read and write operations are
+ serialized. Extra left bits in both AndData and OrData are stripped.
+
+ If 64-bit MMIO register operations are not supported, then ASSERT().
+ If Address is not aligned on a 64-bit boundary, then ASSERT().
+ If StartBit is greater than 63, then ASSERT().
+ If EndBit is greater than 63, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Address MMIO register to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..63.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..63.
+ @param AndData The value to AND with read value from the MMIO register.
+ @param OrData The value to OR with the result of the AND operation.
+
+ @return The value written back to the MMIO register.
+
+**/
+UINT64
+EFIAPI
+MmioBitFieldAndThenOr64 (
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT64 AndData,
+ IN UINT64 OrData
+ );
+
+/**
+ Copy data from MMIO region to system memory by using 8-bit access.
+
+ Copy data from MMIO region specified by starting address StartAddress
+ to system memory specified by Buffer by using 8-bit access. The total
+ number of byte to be copied is specified by Length. Buffer is returned.
+
+ If Length is greater than (MAX_ADDRESS - StartAddress + 1), then ASSERT().
+ If Length is greater than (MAX_ADDRESS - Buffer + 1), then ASSERT().
+
+
+ @param StartAddress Starting address for the MMIO region to be copied from.
+ @param Length The size, in bytes, of Buffer.
+ @param Buffer Pointer to a system memory buffer receiving the data read.
+
+ @return Buffer
+
+**/
+UINT8 *
+EFIAPI
+MmioReadBuffer8 (
+ IN UINTN StartAddress,
+ IN UINTN Length,
+ OUT UINT8 *Buffer
+ );
+
+/**
+ Copy data from MMIO region to system memory by using 16-bit access.
+
+ Copy data from MMIO region specified by starting address StartAddress
+ to system memory specified by Buffer by using 16-bit access. The total
+ number of byte to be copied is specified by Length. Buffer is returned.
+
+ If StartAddress is not aligned on a 16-bit boundary, then ASSERT().
+
+ If Length is greater than (MAX_ADDRESS - StartAddress + 1), then ASSERT().
+ If Length is greater than (MAX_ADDRESS - Buffer + 1), then ASSERT().
+
+ If Length is not aligned on a 16-bit boundary, then ASSERT().
+ If Buffer is not aligned on a 16-bit boundary, then ASSERT().
+
+ @param StartAddress Starting address for the MMIO region to be copied from.
+ @param Length The size, in bytes, of Buffer.
+ @param Buffer Pointer to a system memory buffer receiving the data read.
+
+ @return Buffer
+
+**/
+UINT16 *
+EFIAPI
+MmioReadBuffer16 (
+ IN UINTN StartAddress,
+ IN UINTN Length,
+ OUT UINT16 *Buffer
+ );
+
+/**
+ Copy data from MMIO region to system memory by using 32-bit access.
+
+ Copy data from MMIO region specified by starting address StartAddress
+ to system memory specified by Buffer by using 32-bit access. The total
+ number of byte to be copied is specified by Length. Buffer is returned.
+
+ If StartAddress is not aligned on a 32-bit boundary, then ASSERT().
+
+ If Length is greater than (MAX_ADDRESS - StartAddress + 1), then ASSERT().
+ If Length is greater than (MAX_ADDRESS - Buffer + 1), then ASSERT().
+
+ If Length is not aligned on a 32-bit boundary, then ASSERT().
+ If Buffer is not aligned on a 32-bit boundary, then ASSERT().
+
+ @param StartAddress Starting address for the MMIO region to be copied from.
+ @param Length The size, in bytes, of Buffer.
+ @param Buffer Pointer to a system memory buffer receiving the data read.
+
+ @return Buffer
+
+**/
+UINT32 *
+EFIAPI
+MmioReadBuffer32 (
+ IN UINTN StartAddress,
+ IN UINTN Length,
+ OUT UINT32 *Buffer
+ );
+
+/**
+ Copy data from MMIO region to system memory by using 64-bit access.
+
+ Copy data from MMIO region specified by starting address StartAddress
+ to system memory specified by Buffer by using 64-bit access. The total
+ number of byte to be copied is specified by Length. Buffer is returned.
+
+ If StartAddress is not aligned on a 64-bit boundary, then ASSERT().
+
+ If Length is greater than (MAX_ADDRESS - StartAddress + 1), then ASSERT().
+ If Length is greater than (MAX_ADDRESS - Buffer + 1), then ASSERT().
+
+ If Length is not aligned on a 64-bit boundary, then ASSERT().
+ If Buffer is not aligned on a 64-bit boundary, then ASSERT().
+
+ @param StartAddress Starting address for the MMIO region to be copied from.
+ @param Length The size, in bytes, of Buffer.
+ @param Buffer Pointer to a system memory buffer receiving the data read.
+
+ @return Buffer
+
+**/
+UINT64 *
+EFIAPI
+MmioReadBuffer64 (
+ IN UINTN StartAddress,
+ IN UINTN Length,
+ OUT UINT64 *Buffer
+ );
+
+/**
+ Copy data from system memory to MMIO region by using 8-bit access.
+
+ Copy data from system memory specified by Buffer to MMIO region specified
+ by starting address StartAddress by using 8-bit access. The total number
+ of byte to be copied is specified by Length. Buffer is returned.
+
+ If Length is greater than (MAX_ADDRESS - StartAddress + 1), then ASSERT().
+ If Length is greater than (MAX_ADDRESS -Buffer + 1), then ASSERT().
+
+
+ @param StartAddress Starting address for the MMIO region to be copied to.
+ @param Length The size, in bytes, of Buffer.
+ @param Buffer Pointer to a system memory buffer containing the data to write.
+
+ @return Buffer
+
+**/
+UINT8 *
+EFIAPI
+MmioWriteBuffer8 (
+ IN UINTN StartAddress,
+ IN UINTN Length,
+ IN CONST UINT8 *Buffer
+ );
+
+/**
+ Copy data from system memory to MMIO region by using 16-bit access.
+
+ Copy data from system memory specified by Buffer to MMIO region specified
+ by starting address StartAddress by using 16-bit access. The total number
+ of byte to be copied is specified by Length. Buffer is returned.
+
+ If StartAddress is not aligned on a 16-bit boundary, then ASSERT().
+
+ If Length is greater than (MAX_ADDRESS - StartAddress + 1), then ASSERT().
+ If Length is greater than (MAX_ADDRESS -Buffer + 1), then ASSERT().
+
+ If Length is not aligned on a 16-bit boundary, then ASSERT().
+
+ If Buffer is not aligned on a 16-bit boundary, then ASSERT().
+
+ @param StartAddress Starting address for the MMIO region to be copied to.
+ @param Length The size, in bytes, of Buffer.
+ @param Buffer Pointer to a system memory buffer containing the data to write.
+
+ @return Buffer
+
+**/
+UINT16 *
+EFIAPI
+MmioWriteBuffer16 (
+ IN UINTN StartAddress,
+ IN UINTN Length,
+ IN CONST UINT16 *Buffer
+ );
+
+/**
+ Copy data from system memory to MMIO region by using 32-bit access.
+
+ Copy data from system memory specified by Buffer to MMIO region specified
+ by starting address StartAddress by using 32-bit access. The total number
+ of byte to be copied is specified by Length. Buffer is returned.
+
+ If StartAddress is not aligned on a 32-bit boundary, then ASSERT().
+
+ If Length is greater than (MAX_ADDRESS - StartAddress + 1), then ASSERT().
+ If Length is greater than (MAX_ADDRESS -Buffer + 1), then ASSERT().
+
+ If Length is not aligned on a 32-bit boundary, then ASSERT().
+
+ If Buffer is not aligned on a 32-bit boundary, then ASSERT().
+
+ @param StartAddress Starting address for the MMIO region to be copied to.
+ @param Length The size, in bytes, of Buffer.
+ @param Buffer Pointer to a system memory buffer containing the data to write.
+
+ @return Buffer
+
+**/
+UINT32 *
+EFIAPI
+MmioWriteBuffer32 (
+ IN UINTN StartAddress,
+ IN UINTN Length,
+ IN CONST UINT32 *Buffer
+ );
+
+/**
+ Copy data from system memory to MMIO region by using 64-bit access.
+
+ Copy data from system memory specified by Buffer to MMIO region specified
+ by starting address StartAddress by using 64-bit access. The total number
+ of byte to be copied is specified by Length. Buffer is returned.
+
+ If StartAddress is not aligned on a 64-bit boundary, then ASSERT().
+
+ If Length is greater than (MAX_ADDRESS - StartAddress + 1), then ASSERT().
+ If Length is greater than (MAX_ADDRESS -Buffer + 1), then ASSERT().
+
+ If Length is not aligned on a 64-bit boundary, then ASSERT().
+
+ If Buffer is not aligned on a 64-bit boundary, then ASSERT().
+
+ @param StartAddress Starting address for the MMIO region to be copied to.
+ @param Length The size, in bytes, of Buffer.
+ @param Buffer Pointer to a system memory buffer containing the data to write.
+
+ @return Buffer
+
+**/
+UINT64 *
+EFIAPI
+MmioWriteBuffer64 (
+ IN UINTN StartAddress,
+ IN UINTN Length,
+ IN CONST UINT64 *Buffer
+ );
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/MemoryAllocationLib.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/MemoryAllocationLib.h
new file mode 100644
index 0000000000..fd36433690
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/MemoryAllocationLib.h
@@ -0,0 +1,487 @@
+/** @file
+ Provides services to allocate and free memory buffers of various memory types and alignments.
+
+ The Memory Allocation Library abstracts various common memory allocation operations. This library
+ allows code to be written in a phase-independent manner because the allocation of memory in PEI, DXE,
+ and SMM (for example) is done via a different mechanism. Using a common library interface makes it
+ much easier to port algorithms from phase to phase.
+
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __MEMORY_ALLOCATION_LIB_H__
+#define __MEMORY_ALLOCATION_LIB_H__
+
+/**
+ Allocates one or more 4KB pages of type EfiBootServicesData.
+
+ Allocates the number of 4KB pages of type EfiBootServicesData and returns a pointer to the
+ allocated buffer. The buffer returned is aligned on a 4KB boundary. If Pages is 0, then NULL
+ is returned. If there is not enough memory remaining to satisfy the request, then NULL is
+ returned.
+
+ @param Pages The number of 4 KB pages to allocate.
+
+ @return A pointer to the allocated buffer or NULL if allocation fails.
+
+**/
+VOID *
+EFIAPI
+AllocatePages (
+ IN UINTN Pages
+ );
+
+/**
+ Allocates one or more 4KB pages of type EfiRuntimeServicesData.
+
+ Allocates the number of 4KB pages of type EfiRuntimeServicesData and returns a pointer to the
+ allocated buffer. The buffer returned is aligned on a 4KB boundary. If Pages is 0, then NULL
+ is returned. If there is not enough memory remaining to satisfy the request, then NULL is
+ returned.
+
+ @param Pages The number of 4 KB pages to allocate.
+
+ @return A pointer to the allocated buffer or NULL if allocation fails.
+
+**/
+VOID *
+EFIAPI
+AllocateRuntimePages (
+ IN UINTN Pages
+ );
+
+/**
+ Allocates one or more 4KB pages of type EfiReservedMemoryType.
+
+ Allocates the number of 4KB pages of type EfiReservedMemoryType and returns a pointer to the
+ allocated buffer. The buffer returned is aligned on a 4KB boundary. If Pages is 0, then NULL
+ is returned. If there is not enough memory remaining to satisfy the request, then NULL is
+ returned.
+
+ @param Pages The number of 4 KB pages to allocate.
+
+ @return A pointer to the allocated buffer or NULL if allocation fails.
+
+**/
+VOID *
+EFIAPI
+AllocateReservedPages (
+ IN UINTN Pages
+ );
+
+/**
+ Frees one or more 4KB pages that were previously allocated with one of the page allocation
+ functions in the Memory Allocation Library.
+
+ Frees the number of 4KB pages specified by Pages from the buffer specified by Buffer. Buffer
+ must have been allocated on a previous call to the page allocation services of the Memory
+ Allocation Library. If it is not possible to free allocated pages, then this function will
+ perform no actions.
+
+ If Buffer was not allocated with a page allocation function in the Memory Allocation Library,
+ then ASSERT().
+ If Pages is zero, then ASSERT().
+
+ @param Buffer Pointer to the buffer of pages to free.
+ @param Pages The number of 4 KB pages to free.
+
+**/
+VOID
+EFIAPI
+FreePages (
+ IN VOID *Buffer,
+ IN UINTN Pages
+ );
+
+/**
+ Allocates one or more 4KB pages of type EfiBootServicesData at a specified alignment.
+
+ Allocates the number of 4KB pages specified by Pages of type EfiBootServicesData with an
+ alignment specified by Alignment. The allocated buffer is returned. If Pages is 0, then NULL is
+ returned. If there is not enough memory at the specified alignment remaining to satisfy the
+ request, then NULL is returned.
+
+ If Alignment is not a power of two and Alignment is not zero, then ASSERT().
+ If Pages plus EFI_SIZE_TO_PAGES (Alignment) overflows, then ASSERT().
+
+ @param Pages The number of 4 KB pages to allocate.
+ @param Alignment The requested alignment of the allocation. Must be a power of two.
+ If Alignment is zero, then byte alignment is used.
+
+ @return A pointer to the allocated buffer or NULL if allocation fails.
+
+**/
+VOID *
+EFIAPI
+AllocateAlignedPages (
+ IN UINTN Pages,
+ IN UINTN Alignment
+ );
+
+/**
+ Allocates one or more 4KB pages of type EfiRuntimeServicesData at a specified alignment.
+
+ Allocates the number of 4KB pages specified by Pages of type EfiRuntimeServicesData with an
+ alignment specified by Alignment. The allocated buffer is returned. If Pages is 0, then NULL is
+ returned. If there is not enough memory at the specified alignment remaining to satisfy the
+ request, then NULL is returned.
+
+ If Alignment is not a power of two and Alignment is not zero, then ASSERT().
+ If Pages plus EFI_SIZE_TO_PAGES (Alignment) overflows, then ASSERT().
+
+ @param Pages The number of 4 KB pages to allocate.
+ @param Alignment The requested alignment of the allocation. Must be a power of two.
+ If Alignment is zero, then byte alignment is used.
+
+ @return A pointer to the allocated buffer or NULL if allocation fails.
+
+**/
+VOID *
+EFIAPI
+AllocateAlignedRuntimePages (
+ IN UINTN Pages,
+ IN UINTN Alignment
+ );
+
+/**
+ Allocates one or more 4KB pages of type EfiReservedMemoryType at a specified alignment.
+
+ Allocates the number of 4KB pages specified by Pages of type EfiReservedMemoryType with an
+ alignment specified by Alignment. The allocated buffer is returned. If Pages is 0, then NULL is
+ returned. If there is not enough memory at the specified alignment remaining to satisfy the
+ request, then NULL is returned.
+
+ If Alignment is not a power of two and Alignment is not zero, then ASSERT().
+ If Pages plus EFI_SIZE_TO_PAGES (Alignment) overflows, then ASSERT().
+
+ @param Pages The number of 4 KB pages to allocate.
+ @param Alignment The requested alignment of the allocation. Must be a power of two.
+ If Alignment is zero, then byte alignment is used.
+
+ @return A pointer to the allocated buffer or NULL if allocation fails.
+
+**/
+VOID *
+EFIAPI
+AllocateAlignedReservedPages (
+ IN UINTN Pages,
+ IN UINTN Alignment
+ );
+
+/**
+ Frees one or more 4KB pages that were previously allocated with one of the aligned page
+ allocation functions in the Memory Allocation Library.
+
+ Frees the number of 4KB pages specified by Pages from the buffer specified by Buffer. Buffer
+ must have been allocated on a previous call to the aligned page allocation services of the Memory
+ Allocation Library. If it is not possible to free allocated pages, then this function will
+ perform no actions.
+
+ If Buffer was not allocated with an aligned page allocation function in the Memory Allocation
+ Library, then ASSERT().
+ If Pages is zero, then ASSERT().
+
+ @param Buffer Pointer to the buffer of pages to free.
+ @param Pages The number of 4 KB pages to free.
+
+**/
+VOID
+EFIAPI
+FreeAlignedPages (
+ IN VOID *Buffer,
+ IN UINTN Pages
+ );
+
+/**
+ Allocates a buffer of type EfiBootServicesData.
+
+ Allocates the number bytes specified by AllocationSize of type EfiBootServicesData and returns a
+ pointer to the allocated buffer. If AllocationSize is 0, then a valid buffer of 0 size is
+ returned. If there is not enough memory remaining to satisfy the request, then NULL is returned.
+
+ @param AllocationSize The number of bytes to allocate.
+
+ @return A pointer to the allocated buffer or NULL if allocation fails.
+
+**/
+VOID *
+EFIAPI
+AllocatePool (
+ IN UINTN AllocationSize
+ );
+
+/**
+ Allocates a buffer of type EfiRuntimeServicesData.
+
+ Allocates the number bytes specified by AllocationSize of type EfiRuntimeServicesData and returns
+ a pointer to the allocated buffer. If AllocationSize is 0, then a valid buffer of 0 size is
+ returned. If there is not enough memory remaining to satisfy the request, then NULL is returned.
+
+ @param AllocationSize The number of bytes to allocate.
+
+ @return A pointer to the allocated buffer or NULL if allocation fails.
+
+**/
+VOID *
+EFIAPI
+AllocateRuntimePool (
+ IN UINTN AllocationSize
+ );
+
+/**
+ Allocates a buffer of type EfiReservedMemoryType.
+
+ Allocates the number bytes specified by AllocationSize of type EfiReservedMemoryType and returns
+ a pointer to the allocated buffer. If AllocationSize is 0, then a valid buffer of 0 size is
+ returned. If there is not enough memory remaining to satisfy the request, then NULL is returned.
+
+ @param AllocationSize The number of bytes to allocate.
+
+ @return A pointer to the allocated buffer or NULL if allocation fails.
+
+**/
+VOID *
+EFIAPI
+AllocateReservedPool (
+ IN UINTN AllocationSize
+ );
+
+/**
+ Allocates and zeros a buffer of type EfiBootServicesData.
+
+ Allocates the number bytes specified by AllocationSize of type EfiBootServicesData, clears the
+ buffer with zeros, and returns a pointer to the allocated buffer. If AllocationSize is 0, then a
+ valid buffer of 0 size is returned. If there is not enough memory remaining to satisfy the
+ request, then NULL is returned.
+
+ @param AllocationSize The number of bytes to allocate and zero.
+
+ @return A pointer to the allocated buffer or NULL if allocation fails.
+
+**/
+VOID *
+EFIAPI
+AllocateZeroPool (
+ IN UINTN AllocationSize
+ );
+
+/**
+ Allocates and zeros a buffer of type EfiRuntimeServicesData.
+
+ Allocates the number bytes specified by AllocationSize of type EfiRuntimeServicesData, clears the
+ buffer with zeros, and returns a pointer to the allocated buffer. If AllocationSize is 0, then a
+ valid buffer of 0 size is returned. If there is not enough memory remaining to satisfy the
+ request, then NULL is returned.
+
+ @param AllocationSize The number of bytes to allocate and zero.
+
+ @return A pointer to the allocated buffer or NULL if allocation fails.
+
+**/
+VOID *
+EFIAPI
+AllocateRuntimeZeroPool (
+ IN UINTN AllocationSize
+ );
+
+/**
+ Allocates and zeros a buffer of type EfiReservedMemoryType.
+
+ Allocates the number bytes specified by AllocationSize of type EfiReservedMemoryType, clears the
+ buffer with zeros, and returns a pointer to the allocated buffer. If AllocationSize is 0, then a
+ valid buffer of 0 size is returned. If there is not enough memory remaining to satisfy the
+ request, then NULL is returned.
+
+ @param AllocationSize The number of bytes to allocate and zero.
+
+ @return A pointer to the allocated buffer or NULL if allocation fails.
+
+**/
+VOID *
+EFIAPI
+AllocateReservedZeroPool (
+ IN UINTN AllocationSize
+ );
+
+/**
+ Copies a buffer to an allocated buffer of type EfiBootServicesData.
+
+ Allocates the number bytes specified by AllocationSize of type EfiBootServicesData, copies
+ AllocationSize bytes from Buffer to the newly allocated buffer, and returns a pointer to the
+ allocated buffer. If AllocationSize is 0, then a valid buffer of 0 size is returned. If there
+ is not enough memory remaining to satisfy the request, then NULL is returned.
+
+ If Buffer is NULL, then ASSERT().
+ If AllocationSize is greater than (MAX_ADDRESS - Buffer + 1), then ASSERT().
+
+ @param AllocationSize The number of bytes to allocate and zero.
+ @param Buffer The buffer to copy to the allocated buffer.
+
+ @return A pointer to the allocated buffer or NULL if allocation fails.
+
+**/
+VOID *
+EFIAPI
+AllocateCopyPool (
+ IN UINTN AllocationSize,
+ IN CONST VOID *Buffer
+ );
+
+/**
+ Copies a buffer to an allocated buffer of type EfiRuntimeServicesData.
+
+ Allocates the number bytes specified by AllocationSize of type EfiRuntimeServicesData, copies
+ AllocationSize bytes from Buffer to the newly allocated buffer, and returns a pointer to the
+ allocated buffer. If AllocationSize is 0, then a valid buffer of 0 size is returned. If there
+ is not enough memory remaining to satisfy the request, then NULL is returned.
+
+ If Buffer is NULL, then ASSERT().
+ If AllocationSize is greater than (MAX_ADDRESS - Buffer + 1), then ASSERT().
+
+ @param AllocationSize The number of bytes to allocate and zero.
+ @param Buffer The buffer to copy to the allocated buffer.
+
+ @return A pointer to the allocated buffer or NULL if allocation fails.
+
+**/
+VOID *
+EFIAPI
+AllocateRuntimeCopyPool (
+ IN UINTN AllocationSize,
+ IN CONST VOID *Buffer
+ );
+
+/**
+ Copies a buffer to an allocated buffer of type EfiReservedMemoryType.
+
+ Allocates the number bytes specified by AllocationSize of type EfiReservedMemoryType, copies
+ AllocationSize bytes from Buffer to the newly allocated buffer, and returns a pointer to the
+ allocated buffer. If AllocationSize is 0, then a valid buffer of 0 size is returned. If there
+ is not enough memory remaining to satisfy the request, then NULL is returned.
+
+ If Buffer is NULL, then ASSERT().
+ If AllocationSize is greater than (MAX_ADDRESS - Buffer + 1), then ASSERT().
+
+ @param AllocationSize The number of bytes to allocate and zero.
+ @param Buffer The buffer to copy to the allocated buffer.
+
+ @return A pointer to the allocated buffer or NULL if allocation fails.
+
+**/
+VOID *
+EFIAPI
+AllocateReservedCopyPool (
+ IN UINTN AllocationSize,
+ IN CONST VOID *Buffer
+ );
+
+/**
+ Reallocates a buffer of type EfiBootServicesData.
+
+ Allocates and zeros the number bytes specified by NewSize from memory of type
+ EfiBootServicesData. If OldBuffer is not NULL, then the smaller of OldSize and
+ NewSize bytes are copied from OldBuffer to the newly allocated buffer, and
+ OldBuffer is freed. A pointer to the newly allocated buffer is returned.
+ If NewSize is 0, then a valid buffer of 0 size is returned. If there is not
+ enough memory remaining to satisfy the request, then NULL is returned.
+
+ If the allocation of the new buffer is successful and the smaller of NewSize and OldSize
+ is greater than (MAX_ADDRESS - OldBuffer + 1), then ASSERT().
+
+ @param OldSize The size, in bytes, of OldBuffer.
+ @param NewSize The size, in bytes, of the buffer to reallocate.
+ @param OldBuffer The buffer to copy to the allocated buffer. This is an optional
+ parameter that may be NULL.
+
+ @return A pointer to the allocated buffer or NULL if allocation fails.
+
+**/
+VOID *
+EFIAPI
+ReallocatePool (
+ IN UINTN OldSize,
+ IN UINTN NewSize,
+ IN VOID *OldBuffer OPTIONAL
+ );
+
+/**
+ Reallocates a buffer of type EfiRuntimeServicesData.
+
+ Allocates and zeros the number bytes specified by NewSize from memory of type
+ EfiRuntimeServicesData. If OldBuffer is not NULL, then the smaller of OldSize and
+ NewSize bytes are copied from OldBuffer to the newly allocated buffer, and
+ OldBuffer is freed. A pointer to the newly allocated buffer is returned.
+ If NewSize is 0, then a valid buffer of 0 size is returned. If there is not
+ enough memory remaining to satisfy the request, then NULL is returned.
+
+ If the allocation of the new buffer is successful and the smaller of NewSize and OldSize
+ is greater than (MAX_ADDRESS - OldBuffer + 1), then ASSERT().
+
+ @param OldSize The size, in bytes, of OldBuffer.
+ @param NewSize The size, in bytes, of the buffer to reallocate.
+ @param OldBuffer The buffer to copy to the allocated buffer. This is an optional
+ parameter that may be NULL.
+
+ @return A pointer to the allocated buffer or NULL if allocation fails.
+
+**/
+VOID *
+EFIAPI
+ReallocateRuntimePool (
+ IN UINTN OldSize,
+ IN UINTN NewSize,
+ IN VOID *OldBuffer OPTIONAL
+ );
+
+/**
+ Reallocates a buffer of type EfiReservedMemoryType.
+
+ Allocates and zeros the number bytes specified by NewSize from memory of type
+ EfiReservedMemoryType. If OldBuffer is not NULL, then the smaller of OldSize and
+ NewSize bytes are copied from OldBuffer to the newly allocated buffer, and
+ OldBuffer is freed. A pointer to the newly allocated buffer is returned.
+ If NewSize is 0, then a valid buffer of 0 size is returned. If there is not
+ enough memory remaining to satisfy the request, then NULL is returned.
+
+ If the allocation of the new buffer is successful and the smaller of NewSize and OldSize
+ is greater than (MAX_ADDRESS - OldBuffer + 1), then ASSERT().
+
+ @param OldSize The size, in bytes, of OldBuffer.
+ @param NewSize The size, in bytes, of the buffer to reallocate.
+ @param OldBuffer The buffer to copy to the allocated buffer. This is an optional
+ parameter that may be NULL.
+
+ @return A pointer to the allocated buffer or NULL if allocation fails.
+
+**/
+VOID *
+EFIAPI
+ReallocateReservedPool (
+ IN UINTN OldSize,
+ IN UINTN NewSize,
+ IN VOID *OldBuffer OPTIONAL
+ );
+
+/**
+ Frees a buffer that was previously allocated with one of the pool allocation functions in the
+ Memory Allocation Library.
+
+ Frees the buffer specified by Buffer. Buffer must have been allocated on a previous call to the
+ pool allocation services of the Memory Allocation Library. If it is not possible to free pool
+ resources, then this function will perform no actions.
+
+ If Buffer was not allocated with a pool allocation function in the Memory Allocation Library,
+ then ASSERT().
+
+ @param Buffer Pointer to the buffer to free.
+
+**/
+VOID
+EFIAPI
+FreePool (
+ IN VOID *Buffer
+ );
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/MmServicesTableLib.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/MmServicesTableLib.h
new file mode 100644
index 0000000000..22d888a8a3
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/MmServicesTableLib.h
@@ -0,0 +1,19 @@
+/** @file
+ Provides a service to retrieve a pointer to the Standalone MM Services Table.
+ Only available to MM_STANDALONE, SMM/DXE Combined and SMM module types.
+
+Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.
+Copyright (c) 2016 - 2018, ARM Limited. All rights reserved.
+
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __MM_SERVICES_TABLE_LIB_H__
+#define __MM_SERVICES_TABLE_LIB_H__
+
+#include
+
+extern EFI_MM_SYSTEM_TABLE *gMmst;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/MmUnblockMemoryLib.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/MmUnblockMemoryLib.h
new file mode 100644
index 0000000000..b3ebcac897
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/MmUnblockMemoryLib.h
@@ -0,0 +1,44 @@
+/** @file
+ MM Unblock Memory Library Interface.
+
+ This library provides an interface to request non-MMRAM pages to be mapped/unblocked
+ from inside MM environment.
+
+ For MM modules that need to access regions outside of MMRAMs, the agents that set up
+ these regions are responsible for invoking this API in order for these memory areas
+ to be accessed from inside MM.
+
+ Copyright (c) Microsoft Corporation.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef MM_UNBLOCK_MEMORY_LIB_H_
+#define MM_UNBLOCK_MEMORY_LIB_H_
+
+/**
+ This API provides a way to unblock certain data pages to be accessible inside MM environment.
+
+ @param UnblockAddress The address of buffer caller requests to unblock, the address
+ has to be page aligned.
+ @param NumberOfPages The number of pages requested to be unblocked from MM
+ environment.
+
+ @retval RETURN_SUCCESS The request goes through successfully.
+ @retval RETURN_NOT_AVAILABLE_YET The requested functionality is not produced yet.
+ @retval RETURN_UNSUPPORTED The requested functionality is not supported on current platform.
+ @retval RETURN_SECURITY_VIOLATION The requested address failed to pass security check for
+ unblocking.
+ @retval RETURN_INVALID_PARAMETER Input address either NULL pointer or not page aligned.
+ @retval RETURN_ACCESS_DENIED The request is rejected due to system has passed certain boot
+ phase.
+
+**/
+RETURN_STATUS
+EFIAPI
+MmUnblockMemoryRequest (
+ IN PHYSICAL_ADDRESS UnblockAddress,
+ IN UINT64 NumberOfPages
+ );
+
+#endif // MM_UNBLOCK_MEMORY_LIB_H_
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/OrderedCollectionLib.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/OrderedCollectionLib.h
new file mode 100644
index 0000000000..a1e91a81d2
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/OrderedCollectionLib.h
@@ -0,0 +1,408 @@
+/** @file
+ An ordered collection library interface.
+
+ The library class provides a set of APIs to manage an ordered collection of
+ items.
+
+ Copyright (C) 2014, Red Hat, Inc.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef __ORDERED_COLLECTION_LIB__
+#define __ORDERED_COLLECTION_LIB__
+
+#include
+
+//
+// Opaque structure for a collection.
+//
+typedef struct ORDERED_COLLECTION ORDERED_COLLECTION;
+
+//
+// Opaque structure for collection entries.
+//
+// Collection entries do not take ownership of the associated user structures,
+// they only link them. This makes it easy to link the same user structure into
+// several collections. If reference counting is required, the caller is
+// responsible for implementing it, as part of the user structure.
+//
+// A pointer-to-ORDERED_COLLECTION_ENTRY is considered an "iterator". Multiple,
+// simultaneous iterations are supported.
+//
+typedef struct ORDERED_COLLECTION_ENTRY ORDERED_COLLECTION_ENTRY;
+
+//
+// Altering the key field of an in-collection user structure (ie. the portion
+// of the user structure that ORDERED_COLLECTION_USER_COMPARE and
+// ORDERED_COLLECTION_KEY_COMPARE, below, read) is not allowed in-place. The
+// caller is responsible for bracketing the key change with the deletion and
+// the reinsertion of the user structure, so that the changed key value is
+// reflected in the collection.
+//
+
+/**
+ Comparator function type for two user structures.
+
+ @param[in] UserStruct1 Pointer to the first user structure.
+
+ @param[in] UserStruct2 Pointer to the second user structure.
+
+ @retval <0 If UserStruct1 compares less than UserStruct2.
+
+ @retval 0 If UserStruct1 compares equal to UserStruct2.
+
+ @retval >0 If UserStruct1 compares greater than UserStruct2.
+**/
+typedef
+INTN
+(EFIAPI *ORDERED_COLLECTION_USER_COMPARE)(
+ IN CONST VOID *UserStruct1,
+ IN CONST VOID *UserStruct2
+ );
+
+/**
+ Compare a standalone key against a user structure containing an embedded key.
+
+ @param[in] StandaloneKey Pointer to the bare key.
+
+ @param[in] UserStruct Pointer to the user structure with the embedded
+ key.
+
+ @retval <0 If StandaloneKey compares less than UserStruct's key.
+
+ @retval 0 If StandaloneKey compares equal to UserStruct's key.
+
+ @retval >0 If StandaloneKey compares greater than UserStruct's key.
+**/
+typedef
+INTN
+(EFIAPI *ORDERED_COLLECTION_KEY_COMPARE)(
+ IN CONST VOID *StandaloneKey,
+ IN CONST VOID *UserStruct
+ );
+
+//
+// Some functions below are read-only, while others are read-write. If any
+// write operation is expected to run concurrently with any other operation on
+// the same collection, then the caller is responsible for implementing locking
+// for the whole collection.
+//
+
+/**
+ Retrieve the user structure linked by the specified collection entry.
+
+ Read-only operation.
+
+ @param[in] Entry Pointer to the collection entry whose associated user
+ structure we want to retrieve. The caller is responsible
+ for passing a non-NULL argument.
+
+ @return Pointer to user structure linked by Entry.
+**/
+VOID *
+EFIAPI
+OrderedCollectionUserStruct (
+ IN CONST ORDERED_COLLECTION_ENTRY *Entry
+ );
+
+/**
+ Allocate and initialize the ORDERED_COLLECTION structure.
+
+ @param[in] UserStructCompare This caller-provided function will be used to
+ order two user structures linked into the
+ collection, during the insertion procedure.
+
+ @param[in] KeyCompare This caller-provided function will be used to
+ order the standalone search key against user
+ structures linked into the collection, during
+ the lookup procedure.
+
+ @retval NULL If allocation failed.
+
+ @return Pointer to the allocated, initialized ORDERED_COLLECTION
+ structure, otherwise.
+**/
+ORDERED_COLLECTION *
+EFIAPI
+OrderedCollectionInit (
+ IN ORDERED_COLLECTION_USER_COMPARE UserStructCompare,
+ IN ORDERED_COLLECTION_KEY_COMPARE KeyCompare
+ );
+
+/**
+ Check whether the collection is empty (has no entries).
+
+ Read-only operation.
+
+ @param[in] Collection The collection to check for emptiness.
+
+ @retval TRUE The collection is empty.
+
+ @retval FALSE The collection is not empty.
+**/
+BOOLEAN
+EFIAPI
+OrderedCollectionIsEmpty (
+ IN CONST ORDERED_COLLECTION *Collection
+ );
+
+/**
+ Uninitialize and release an empty ORDERED_COLLECTION structure.
+
+ Read-write operation.
+
+ It is the caller's responsibility to delete all entries from the collection
+ before calling this function.
+
+ @param[in] Collection The empty collection to uninitialize and release.
+**/
+VOID
+EFIAPI
+OrderedCollectionUninit (
+ IN ORDERED_COLLECTION *Collection
+ );
+
+/**
+ Look up the collection entry that links the user structure that matches the
+ specified standalone key.
+
+ Read-only operation.
+
+ @param[in] Collection The collection to search for StandaloneKey.
+
+ @param[in] StandaloneKey The key to locate among the user structures linked
+ into Collection. StandaloneKey will be passed to
+ ORDERED_COLLECTION_KEY_COMPARE.
+
+ @retval NULL StandaloneKey could not be found.
+
+ @return The collection entry that links to the user structure matching
+ StandaloneKey, otherwise.
+**/
+ORDERED_COLLECTION_ENTRY *
+EFIAPI
+OrderedCollectionFind (
+ IN CONST ORDERED_COLLECTION *Collection,
+ IN CONST VOID *StandaloneKey
+ );
+
+/**
+ Find the collection entry of the minimum user structure stored in the
+ collection.
+
+ Read-only operation.
+
+ @param[in] Collection The collection to return the minimum entry of. The
+ user structure linked by the minimum entry compares
+ less than all other user structures in the collection.
+
+ @retval NULL If Collection is empty.
+
+ @return The collection entry that links the minimum user structure,
+ otherwise.
+**/
+ORDERED_COLLECTION_ENTRY *
+EFIAPI
+OrderedCollectionMin (
+ IN CONST ORDERED_COLLECTION *Collection
+ );
+
+/**
+ Find the collection entry of the maximum user structure stored in the
+ collection.
+
+ Read-only operation.
+
+ @param[in] Collection The collection to return the maximum entry of. The
+ user structure linked by the maximum entry compares
+ greater than all other user structures in the
+ collection.
+
+ @retval NULL If Collection is empty.
+
+ @return The collection entry that links the maximum user structure,
+ otherwise.
+**/
+ORDERED_COLLECTION_ENTRY *
+EFIAPI
+OrderedCollectionMax (
+ IN CONST ORDERED_COLLECTION *Collection
+ );
+
+/**
+ Get the collection entry of the least user structure that is greater than the
+ one linked by Entry.
+
+ Read-only operation.
+
+ @param[in] Entry The entry to get the successor entry of.
+
+ @retval NULL If Entry is NULL, or Entry is the maximum entry of its
+ containing collection (ie. Entry has no successor entry).
+
+ @return The collection entry linking the least user structure that is
+ greater than the one linked by Entry, otherwise.
+**/
+ORDERED_COLLECTION_ENTRY *
+EFIAPI
+OrderedCollectionNext (
+ IN CONST ORDERED_COLLECTION_ENTRY *Entry
+ );
+
+/**
+ Get the collection entry of the greatest user structure that is less than the
+ one linked by Entry.
+
+ Read-only operation.
+
+ @param[in] Entry The entry to get the predecessor entry of.
+
+ @retval NULL If Entry is NULL, or Entry is the minimum entry of its
+ containing collection (ie. Entry has no predecessor entry).
+
+ @return The collection entry linking the greatest user structure that
+ is less than the one linked by Entry, otherwise.
+**/
+ORDERED_COLLECTION_ENTRY *
+EFIAPI
+OrderedCollectionPrev (
+ IN CONST ORDERED_COLLECTION_ENTRY *Entry
+ );
+
+/**
+ Insert (link) a user structure into the collection, allocating a new
+ collection entry.
+
+ Read-write operation.
+
+ @param[in,out] Collection The collection to insert UserStruct into.
+
+ @param[out] Entry The meaning of this optional, output-only
+ parameter depends on the return value of the
+ function.
+
+ When insertion is successful (RETURN_SUCCESS),
+ Entry is set on output to the new collection entry
+ that now links UserStruct.
+
+ When insertion fails due to lack of memory
+ (RETURN_OUT_OF_RESOURCES), Entry is not changed.
+
+ When insertion fails due to key collision (ie.
+ another user structure is already in the
+ collection that compares equal to UserStruct),
+ with return value RETURN_ALREADY_STARTED, then
+ Entry is set on output to the entry that links the
+ colliding user structure. This enables
+ "find-or-insert" in one function call, or helps
+ with later removal of the colliding element.
+
+ @param[in] UserStruct The user structure to link into the collection.
+ UserStruct is ordered against in-collection user
+ structures with the
+ ORDERED_COLLECTION_USER_COMPARE function.
+
+ @retval RETURN_SUCCESS Insertion successful. A new collection entry
+ has been allocated, linking UserStruct. The
+ new collection entry is reported back in
+ Entry (if the caller requested it).
+
+ Existing ORDERED_COLLECTION_ENTRY pointers
+ into Collection remain valid. For example,
+ on-going iterations in the caller can
+ continue with OrderedCollectionNext() /
+ OrderedCollectionPrev(), and they will
+ return the new entry at some point if user
+ structure order dictates it.
+
+ @retval RETURN_OUT_OF_RESOURCES The function failed to allocate memory for
+ the new collection entry. The collection has
+ not been changed. Existing
+ ORDERED_COLLECTION_ENTRY pointers into
+ Collection remain valid.
+
+ @retval RETURN_ALREADY_STARTED A user structure has been found in the
+ collection that compares equal to
+ UserStruct. The entry linking the colliding
+ user structure is reported back in Entry (if
+ the caller requested it). The collection has
+ not been changed. Existing
+ ORDERED_COLLECTION_ENTRY pointers into
+ Collection remain valid.
+**/
+RETURN_STATUS
+EFIAPI
+OrderedCollectionInsert (
+ IN OUT ORDERED_COLLECTION *Collection,
+ OUT ORDERED_COLLECTION_ENTRY **Entry OPTIONAL,
+ IN VOID *UserStruct
+ );
+
+/**
+ Delete an entry from the collection, unlinking the associated user structure.
+
+ Read-write operation.
+
+ @param[in,out] Collection The collection to delete Entry from.
+
+ @param[in] Entry The collection entry to delete from Collection.
+ The caller is responsible for ensuring that Entry
+ belongs to Collection, and that Entry is non-NULL
+ and valid. Entry is typically an earlier return
+ value, or output parameter, of:
+
+ - OrderedCollectionFind(), for deleting an entry
+ by user structure key,
+
+ - OrderedCollectionMin() / OrderedCollectionMax(),
+ for deleting the minimum / maximum entry,
+
+ - OrderedCollectionNext() /
+ OrderedCollectionPrev(), for deleting an entry
+ found during an iteration,
+
+ - OrderedCollectionInsert() with return value
+ RETURN_ALREADY_STARTED, for deleting an entry
+ whose linked user structure caused collision
+ during insertion.
+
+ Existing ORDERED_COLLECTION_ENTRY pointers (ie.
+ iterators) *different* from Entry remain valid.
+ For example:
+
+ - OrderedCollectionNext() /
+ OrderedCollectionPrev() iterations in the caller
+ can be continued from Entry, if
+ OrderedCollectionNext() or
+ OrderedCollectionPrev() is called on Entry
+ *before* OrderedCollectionDelete() is. That is,
+ fetch the successor / predecessor entry first,
+ then delete Entry.
+
+ - On-going iterations in the caller that would
+ have otherwise returned Entry at some point, as
+ dictated by user structure order, will correctly
+ reflect the absence of Entry after
+ OrderedCollectionDelete() is called
+ mid-iteration.
+
+ @param[out] UserStruct If the caller provides this optional output-only
+ parameter, then on output it is set to the user
+ structure originally linked by Entry (which is now
+ freed).
+
+ This is a convenience that may save the caller a
+ OrderedCollectionUserStruct() invocation before
+ calling OrderedCollectionDelete(), in order to
+ retrieve the user structure being unlinked.
+**/
+VOID
+EFIAPI
+OrderedCollectionDelete (
+ IN OUT ORDERED_COLLECTION *Collection,
+ IN ORDERED_COLLECTION_ENTRY *Entry,
+ OUT VOID **UserStruct OPTIONAL
+ );
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/PcdLib.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/PcdLib.h
new file mode 100644
index 0000000000..27f2e5a5e5
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/PcdLib.h
@@ -0,0 +1,1676 @@
+/** @file
+ Provides library services to get and set Platform Configuration Database entries.
+
+ PCD Library Class provides a PCD usage macro interface for all PCD types.
+ It should be included in any module that uses PCD. If a module uses dynamic/dynamicex
+ PCD, module should be linked to a PEIM/DXE library instance to access that PCD.
+ If a module uses PatchableInModule type PCD, it also needs the library instance to produce
+ LibPatchPcdSetPtr() interface. For FeatureFlag/Fixed PCD, the macro interface is
+ translated to a variable or macro that is auto-generated by build tool in
+ module's autogen.h/autogen.c.
+ The PcdGetXX(), PcdSetXX(), PcdToken(), and PcdGetNextTokenSpace() operations are
+ only available prior to ExitBootServices(). If access to PCD values are required
+ at runtime, then their values must be collected prior to ExitBootServices().
+ There are no restrictions on the use of FeaturePcd(), FixedPcdGetXX(),
+ PatchPcdGetXX(), and PatchPcdSetXX().
+
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __PCD_LIB_H__
+#define __PCD_LIB_H__
+
+/**
+ Retrieves a token number based on a token name.
+
+ Returns the token number associated with the PCD token specified by TokenName.
+ If TokenName is not a valid token in the token space, then the module will not build.
+
+ @param TokenName The name of the PCD token to retrieve the token number for.
+
+ @return The token number associated with the PCD.
+
+**/
+#define PcdToken(TokenName) _PCD_TOKEN_##TokenName
+
+/**
+ Retrieves a Boolean PCD feature flag based on a token name.
+
+ Returns the Boolean value for the PCD feature flag specified by TokenName.
+ If TokenName is not a valid token in the token space, then the module will not build.
+ If TokenName is not a feature flag PCD, then the module will not build.
+
+ @param TokenName The name of the PCD token to retrieve a current value for.
+
+ @return Boolean value for the PCD feature flag.
+
+**/
+#define FeaturePcdGet(TokenName) _PCD_GET_MODE_BOOL_##TokenName
+
+/**
+ Retrieves an 8-bit fixed PCD token value based on a token name.
+
+ Returns the 8-bit value for the token specified by TokenName.
+ If TokenName is not a valid token in the token space, then the module will not build.
+ If TokenName is not a fixed at build PCD, then the module will not build.
+
+ @param TokenName The name of the PCD token to retrieve a current value for.
+
+ @return 8-bit value for the token specified by TokenName.
+
+**/
+#define FixedPcdGet8(TokenName) _PCD_VALUE_##TokenName
+
+/**
+ Retrieves a 16-bit fixed PCD token value based on a token name.
+
+ Returns the 16-bit value for the token specified by TokenName.
+ If TokenName is not a valid token in the token space, then the module will not build.
+ If TokenName is not a fixed at build PCD, then the module will not build.
+
+ @param TokenName The name of the PCD token to retrieve a current value for.
+
+ @return 16-bit value for the token specified by TokenName.
+
+**/
+#define FixedPcdGet16(TokenName) _PCD_VALUE_##TokenName
+
+/**
+ Retrieves a 32-bit fixed PCD token value based on a token name.
+
+ Returns the 32-bit value for the token specified by TokenName.
+ If TokenName is not a valid token in the token space, then the module will not build.
+ If TokenName is not a fixed at build PCD, then the module will not build.
+
+ @param TokenName The name of the PCD token to retrieve a current value for.
+
+ @return 32-bit value for the token specified by TokenName.
+
+**/
+#define FixedPcdGet32(TokenName) _PCD_VALUE_##TokenName
+
+/**
+ Retrieves a 64-bit fixed PCD token value based on a token name.
+
+ Returns the 64-bit value for the token specified by TokenName.
+ If TokenName is not a valid token in the token space, then the module will not build.
+ If TokenName is not a fixed at build PCD, then the module will not build.
+
+ @param TokenName The name of the PCD token to retrieve a current value for.
+
+ @return 64-bit value for the token specified by TokenName.
+
+**/
+#define FixedPcdGet64(TokenName) _PCD_VALUE_##TokenName
+
+/**
+ Retrieves a Boolean fixed PCD token value based on a token name.
+
+ Returns the Boolean value for the token specified by TokenName.
+ If TokenName is not a valid token in the token space, then the module will not build.
+ If TokenName is not a fixed at build PCD, then the module will not build.
+
+ @param TokenName The name of the PCD token to retrieve a current value for.
+
+ @return The Boolean value for the token.
+
+**/
+#define FixedPcdGetBool(TokenName) _PCD_VALUE_##TokenName
+
+/**
+ Retrieves a pointer to a fixed PCD token buffer based on a token name.
+
+ Returns a pointer to the buffer for the token specified by TokenName.
+ If TokenName is not a valid token in the token space, then the module will not build.
+ If TokenName is not a fixed at build PCD, then the module will not build.
+
+ @param TokenName The name of the PCD token to retrieve a current value for.
+
+ @return A pointer to the buffer.
+
+**/
+#define FixedPcdGetPtr(TokenName) ((VOID *)_PCD_VALUE_##TokenName)
+
+/**
+ Retrieves an 8-bit binary patchable PCD token value based on a token name.
+
+ Returns the 8-bit value for the token specified by TokenName.
+ If TokenName is not a valid token in the token space, then the module will not build.
+ If TokenName is not a patchable in module PCD, then the module will not build.
+
+ @param TokenName The name of the PCD token to retrieve a current value for.
+
+ @return An 8-bit binary patchable PCD token value.
+
+**/
+#define PatchPcdGet8(TokenName) _gPcd_BinaryPatch_##TokenName
+
+/**
+ Retrieves a 16-bit binary patchable PCD token value based on a token name.
+
+ Returns the 16-bit value for the token specified by TokenName.
+ If TokenName is not a valid token in the token space, then the module will not build.
+ If TokenName is not a patchable in module PCD, then the module will not build.
+
+ @param TokenName The name of the PCD token to retrieve a current value for.
+
+ @return A 16-bit binary patchable PCD token value.
+
+**/
+#define PatchPcdGet16(TokenName) _gPcd_BinaryPatch_##TokenName
+
+/**
+ Retrieves a 32-bit binary patchable PCD token value based on a token name.
+
+ Returns the 32-bit value for the token specified by TokenName.
+ If TokenName is not a valid token in the token space, then the module will not build.
+ If TokenName is not a patchable in module PCD, then the module will not build.
+
+ @param TokenName The name of the PCD token to retrieve a current value for.
+
+ @return A 32-bit binary patchable PCD token value.
+
+**/
+#define PatchPcdGet32(TokenName) _gPcd_BinaryPatch_##TokenName
+
+/**
+ Retrieves a 64-bit binary patchable PCD token value based on a token name.
+
+ Returns the 64-bit value for the token specified by TokenName.
+ If TokenName is not a valid token in the token space, then the module will not build.
+ If TokenName is not a patchable in module PCD, then the module will not build.
+
+ @param TokenName The name of the PCD token to retrieve a current value for.
+
+ @return A 64-bit binary patchable PCD token value.
+
+**/
+#define PatchPcdGet64(TokenName) _gPcd_BinaryPatch_##TokenName
+
+/**
+ Retrieves a Boolean binary patchable PCD token value based on a token name.
+
+ Returns the Boolean value for the token specified by TokenName.
+ If TokenName is not a valid token in the token space, then the module will not build.
+ If TokenName is not a patchable in module PCD, then the module will not build.
+
+ @param TokenName The name of the PCD token to retrieve a current value for.
+
+ @return The Boolean value for the token.
+
+**/
+#define PatchPcdGetBool(TokenName) _gPcd_BinaryPatch_##TokenName
+
+/**
+ Retrieves a pointer to a binary patchable PCD token buffer based on a token name.
+
+ Returns a pointer to the buffer for the token specified by TokenName.
+ If TokenName is not a valid token in the token space, then the module will not build.
+ If TokenName is not a patchable in module PCD, then the module will not build.
+
+ @param TokenName The name of the PCD token to retrieve a current value for.
+
+ @return A pointer to the buffer for the token.
+
+**/
+#define PatchPcdGetPtr(TokenName) ((VOID *)_gPcd_BinaryPatch_##TokenName)
+
+/**
+ Sets an 8-bit binary patchable PCD token value based on a token name.
+
+ Sets the 8-bit value for the token specified by TokenName. Value is returned.
+ If TokenName is not a valid token in the token space, then the module will not build.
+ If TokenName is not a patchable in module PCD, then the module will not build.
+
+ @param TokenName The name of the binary patchable PCD token to set the current value for.
+ @param Value The 8-bit value to set.
+
+ @return Return the Value that was set.
+
+**/
+#define PatchPcdSet8(TokenName, Value) (_gPcd_BinaryPatch_##TokenName = (Value))
+
+/**
+ Sets a 16-bit binary patchable PCD token value based on a token name.
+
+ Sets the 16-bit value for the token specified by TokenName. Value is returned.
+ If TokenName is not a valid token in the token space, then the module will not build.
+ If TokenName is not a patchable in module PCD, then the module will not build.
+
+ @param TokenName The name of the binary patchable PCD token to set the current value for.
+ @param Value The 16-bit value to set.
+
+ @return Return the Value that was set.
+
+**/
+#define PatchPcdSet16(TokenName, Value) (_gPcd_BinaryPatch_##TokenName = (Value))
+
+/**
+ Sets a 32-bit binary patchable PCD token value based on a token name.
+
+ Sets the 32-bit value for the token specified by TokenName. Value is returned.
+ If TokenName is not a valid token in the token space, then the module will not build.
+ If TokenName is not a patchable in module PCD, then the module will not build.
+
+ @param TokenName The name of the binary patchable PCD token to set the current value for.
+ @param Value The 32-bit value to set.
+
+ @return Return the Value that was set.
+
+**/
+#define PatchPcdSet32(TokenName, Value) (_gPcd_BinaryPatch_##TokenName = (Value))
+
+/**
+ Sets a 64-bit binary patchable PCD token value based on a token name.
+
+ Sets the 64-bit value for the token specified by TokenName. Value is returned.
+ If TokenName is not a valid token in the token space, then the module will not build.
+ If TokenName is not a patchable in module PCD, then the module will not build.
+
+ @param TokenName The name of the binary patchable PCD token to set the current value for.
+ @param Value The 64-bit value to set.
+
+ @return Return the Value that was set.
+
+**/
+#define PatchPcdSet64(TokenName, Value) (_gPcd_BinaryPatch_##TokenName = (Value))
+
+/**
+ Sets a Boolean binary patchable PCD token value based on a token name.
+
+ Sets the Boolean value for the token specified by TokenName. Value is returned.
+ If TokenName is not a valid token in the token space, then the module will not build.
+ If TokenName is not a patchable in module PCD, then the module will not build.
+
+ @param TokenName The name of the binary patchable PCD token to set the current value for.
+ @param Value The boolean value to set.
+
+ @return Return the Value that was set.
+
+**/
+#define PatchPcdSetBool(TokenName, Value) (_gPcd_BinaryPatch_##TokenName = (Value))
+
+/**
+ Sets a pointer to a binary patchable PCD token buffer based on a token name.
+
+ Sets the buffer for the token specified by TokenName. Buffer is returned.
+ If SizeOfBuffer is greater than the maximum size supported by TokenName, then set SizeOfBuffer
+ to the maximum size supported by TokenName and return NULL to indicate that the set operation
+ was not actually performed. If SizeOfBuffer is set to MAX_ADDRESS, then SizeOfBuffer must be
+ set to the maximum size supported by TokenName and NULL must be returned.
+ If TokenName is not a valid token in the token space, then the module will not build.
+ If TokenName is not a patchable in module PCD, then the module will not build.
+
+ If SizeOfBuffer is NULL, then ASSERT().
+ If SizeOfBuffer > 0 and Buffer is NULL, then ASSERT().
+
+ @param TokenName The name of the binary patchable PCD token to set the current value for.
+ @param SizeOfBuffer A pointer to the size, in bytes, of Buffer.
+ @param Buffer Pointer to the value to set.
+
+ @return Return the pointer to the Buffer that was set.
+
+**/
+#define PatchPcdSetPtr(TokenName, Size, Buffer) \
+ LibPatchPcdSetPtrAndSize ( \
+ (VOID *)_gPcd_BinaryPatch_##TokenName, \
+ &_gPcd_BinaryPatch_Size_##TokenName, \
+ (UINTN)_PCD_PATCHABLE_##TokenName##_SIZE, \
+ (Size), \
+ (Buffer) \
+ )
+
+/**
+ Retrieves an 8-bit PCD token value based on a token name.
+
+ Returns the 8-bit value for the token specified by TokenName.
+ If TokenName is not a valid token in the token space, then the module will not build.
+
+ @param TokenName The name of the PCD token to retrieve a current value for.
+
+ @return 8-bit value for the token specified by TokenName.
+
+**/
+#define PcdGet8(TokenName) _PCD_GET_MODE_8_##TokenName
+
+/**
+ Retrieves a 16-bit PCD token value based on a token name.
+
+ Returns the 16-bit value for the token specified by TokenName.
+ If TokenName is not a valid token in the token space, then the module will not build.
+
+ @param TokenName The name of the PCD token to retrieve a current value for.
+
+ @return 16-bit value for the token specified by TokenName.
+
+**/
+#define PcdGet16(TokenName) _PCD_GET_MODE_16_##TokenName
+
+/**
+ Retrieves a 32-bit PCD token value based on a token name.
+
+ Returns the 32-bit value for the token specified by TokenName.
+ If TokenName is not a valid token in the token space, then the module will not build.
+
+ @param TokenName The name of the PCD token to retrieve a current value for.
+
+ @return 32-bit value for the token specified by TokenName.
+
+**/
+#define PcdGet32(TokenName) _PCD_GET_MODE_32_##TokenName
+
+/**
+ Retrieves a 64-bit PCD token value based on a token name.
+
+ Returns the 64-bit value for the token specified by TokenName.
+ If TokenName is not a valid token in the token space, then the module will not build.
+
+ @param TokenName The name of the PCD token to retrieve a current value for.
+
+ @return 64-bit value for the token specified by TokenName.
+
+**/
+#define PcdGet64(TokenName) _PCD_GET_MODE_64_##TokenName
+
+/**
+ Retrieves a pointer to a PCD token buffer based on a token name.
+
+ Returns a pointer to the buffer for the token specified by TokenName.
+ If TokenName is not a valid token in the token space, then the module will not build.
+
+ @param TokenName The name of the PCD token to retrieve a current value for.
+
+ @return A pointer to the buffer.
+
+**/
+#define PcdGetPtr(TokenName) _PCD_GET_MODE_PTR_##TokenName
+
+/**
+ Retrieves a Boolean PCD token value based on a token name.
+
+ Returns the Boolean value for the token specified by TokenName.
+ If TokenName is not a valid token in the token space, then the module will not build.
+
+ @param TokenName The name of the PCD token to retrieve a current value for.
+
+ @return A Boolean PCD token value.
+
+**/
+#define PcdGetBool(TokenName) _PCD_GET_MODE_BOOL_##TokenName
+
+/**
+ Retrieves the size of a fixed PCD token based on a token name.
+
+ Returns the size of the token specified by TokenName.
+ If TokenName is not a valid token in the token space, then the module will not build.
+
+ @param[in] TokenName The name of the PCD token to retrieve a current value size for.
+
+ @return Return the size
+
+**/
+#define FixedPcdGetSize(TokenName) _PCD_SIZE_##TokenName
+
+/**
+ Retrieves the size of a binary patchable PCD token based on a token name.
+
+ Returns the size of the token specified by TokenName.
+ If TokenName is not a valid token in the token space, then the module will not build.
+
+ @param[in] TokenName The name of the PCD token to retrieve a current value size for.
+
+ @return Return the size
+
+**/
+#define PatchPcdGetSize(TokenName) _gPcd_BinaryPatch_Size_##TokenName
+
+/**
+ Retrieves the size of the PCD token based on a token name.
+
+ Returns the size of the token specified by TokenName.
+ If TokenName is not a valid token in the token space, then the module will not build.
+
+ @param[in] TokenName The name of the PCD token to retrieve a current value size for.
+
+ @return Return the size
+
+**/
+#define PcdGetSize(TokenName) _PCD_GET_MODE_SIZE_##TokenName
+
+/**
+ Retrieve the size of a given PCD token.
+
+ Returns the size of the token specified by TokenNumber and Guid.
+ If Guid is NULL, then ASSERT().
+
+ @param[in] Guid Pointer to a 128-bit unique value that designates
+ which namespace to retrieve a value from.
+ @param[in] TokenNumber The PCD token number to retrieve a current value size for.
+
+ @return Return the size.
+
+**/
+#define PcdGetExSize(Guid, TokenName) LibPcdGetExSize ((Guid), PcdTokenEx(Guid,TokenName))
+
+/**
+ Sets a 8-bit PCD token value based on a token name.
+
+ Sets the 8-bit value for the token specified by TokenName.
+ If TokenName is not a valid token in the token space, then the module will not build.
+
+ @param TokenName The name of the PCD token to retrieve a current value for.
+ @param Value The 8-bit value to set.
+
+ @return The status of the set operation.
+
+**/
+#define PcdSet8S(TokenName, Value) _PCD_SET_MODE_8_S_##TokenName ((Value))
+
+/**
+ Sets a 16-bit PCD token value based on a token name.
+
+ Sets the 16-bit value for the token specified by TokenName.
+ If TokenName is not a valid token in the token space, then the module will not build.
+
+ @param TokenName The name of the PCD token to retrieve a current value for.
+ @param Value The 16-bit value to set.
+
+ @return The status of the set operation.
+
+**/
+#define PcdSet16S(TokenName, Value) _PCD_SET_MODE_16_S_##TokenName ((Value))
+
+/**
+ Sets a 32-bit PCD token value based on a token name.
+
+ Sets the 32-bit value for the token specified by TokenName.
+ If TokenName is not a valid token in the token space, then the module will not build.
+
+ @param TokenName The name of the PCD token to retrieve a current value for.
+ @param Value The 32-bit value to set.
+
+ @return The status of the set operation.
+
+**/
+#define PcdSet32S(TokenName, Value) _PCD_SET_MODE_32_S_##TokenName ((Value))
+
+/**
+ Sets a 64-bit PCD token value based on a token name.
+
+ Sets the 64-bit value for the token specified by TokenName.
+ If TokenName is not a valid token in the token space, then the module will not build.
+
+ @param TokenName The name of the PCD token to retrieve a current value for.
+ @param Value The 64-bit value to set.
+
+ @return The status of the set operation.
+
+**/
+#define PcdSet64S(TokenName, Value) _PCD_SET_MODE_64_S_##TokenName ((Value))
+
+/**
+ Sets a pointer to a PCD token buffer based on a token name.
+
+ Sets the buffer for the token specified by TokenName.
+ If SizeOfBuffer is greater than the maximum size supported by TokenName,
+ then set SizeOfBuffer to the maximum size supported by TokenName and return
+ RETURN_INVALID_PARAMETER to indicate that the set operation was not actually performed.
+ If SizeOfBuffer is set to MAX_ADDRESS, then SizeOfBuffer must be set to the maximum size
+ supported by TokenName and RETURN_INVALID_PARAMETER must be returned.
+ If TokenName is not a valid token in the token space, then the module will not build.
+
+ If SizeOfBuffer is NULL, then ASSERT().
+ If SizeOfBuffer > 0 and Buffer is NULL, then ASSERT().
+
+ @param TokenName The name of the PCD token to set the current value for.
+ @param SizeOfBuffer A pointer to the size, in bytes, of Buffer.
+ @param Buffer A pointer to the buffer to set.
+
+ @return The status of the set operation.
+
+**/
+#define PcdSetPtrS(TokenName, SizeOfBuffer, Buffer) \
+ _PCD_SET_MODE_PTR_S_##TokenName ((SizeOfBuffer), (Buffer))
+
+/**
+ Sets a boolean PCD token value based on a token name.
+
+ Sets the boolean value for the token specified by TokenName.
+ If TokenName is not a valid token in the token space, then the module will not build.
+
+ @param TokenName The name of the PCD token to retrieve a current value for.
+ @param Value The boolean value to set.
+
+ @return The status of the set operation.
+
+**/
+#define PcdSetBoolS(TokenName, Value) _PCD_SET_MODE_BOOL_S_##TokenName ((Value))
+
+/**
+ Retrieves a token number based on a GUID and a token name.
+
+ Returns the token number for the token specified by Guid and TokenName.
+ If TokenName is not a valid token in the token space, then the module will not build.
+
+ @param Guid Pointer to a 128-bit unique value that designates
+ which namespace to retrieve a value from.
+ @param TokenName The name of the PCD token to retrieve a current value for.
+
+ @return Return the token number.
+
+**/
+#define PcdTokenEx(Guid, TokenName) _PCD_TOKEN_EX_##TokenName(Guid)
+
+/**
+ Retrieves an 8-bit PCD token value based on a GUID and a token name.
+
+ Returns the 8-bit value for the token specified by Guid and TokenName.
+ If TokenName is not a valid token in the token space specified by Guid,
+ then the module will not build.
+
+ If Guid is NULL, then ASSERT().
+
+ @param Guid Pointer to a 128-bit unique value that designates
+ which namespace to retrieve a value from.
+ @param TokenName The name of the PCD token to retrieve a current value for.
+
+ @return An 8-bit PCD token value.
+
+**/
+#define PcdGetEx8(Guid, TokenName) LibPcdGetEx8 ((Guid), PcdTokenEx(Guid,TokenName))
+
+/**
+ Retrieves a 16-bit PCD token value based on a GUID and a token name.
+
+ Returns the 16-bit value for the token specified by Guid and TokenName.
+ If TokenName is not a valid token in the token space specified by Guid,
+ then the module will not build.
+
+ If Guid is NULL, then ASSERT().
+
+ @param Guid Pointer to a 128-bit unique value that designates
+ which namespace to retrieve a value from.
+ @param TokenName The name of the PCD token to retrieve a current value for.
+
+ @return A 16-bit PCD token value.
+
+**/
+#define PcdGetEx16(Guid, TokenName) LibPcdGetEx16 ((Guid), PcdTokenEx(Guid,TokenName))
+
+/**
+ Retrieves a 32-bit PCD token value based on a GUID and a token name.
+
+ Returns the 32-bit value for the token specified by Guid and TokenName.
+ If TokenName is not a valid token in the token space specified by Guid,
+ then the module will not build.
+
+ If Guid is NULL, then ASSERT().
+
+ @param Guid Pointer to a 128-bit unique value that designates
+ which namespace to retrieve a value from.
+ @param TokenName The name of the PCD token to retrieve a current value for.
+
+ @return A 32-bit PCD token value.
+
+**/
+#define PcdGetEx32(Guid, TokenName) LibPcdGetEx32 ((Guid), PcdTokenEx(Guid,TokenName))
+
+/**
+ Retrieves a 64-bit PCD token value based on a GUID and a token name.
+
+ Returns the 64-bit value for the token specified by Guid and TokenName.
+ If TokenName is not a valid token in the token space specified by Guid,
+ then the module will not build.
+
+ If Guid is NULL, then ASSERT().
+
+ @param Guid Pointer to a 128-bit unique value that designates
+ which namespace to retrieve a value from.
+ @param TokenName The name of the PCD token to retrieve a current value for.
+
+ @return A 64-bit PCD token value.
+
+**/
+#define PcdGetEx64(Guid, TokenName) LibPcdGetEx64 ((Guid), PcdTokenEx(Guid,TokenName))
+
+/**
+ Retrieves a pointer to a PCD token buffer based on a GUID and a token name.
+
+ Returns a pointer to the buffer for the token specified by Guid and TokenName.
+ If TokenName is not a valid token in the token space specified by Guid,
+ then the module will not build.
+
+ If Guid is NULL, then ASSERT().
+
+ @param Guid Pointer to a 128-bit unique value that designates
+ which namespace to retrieve a value from.
+ @param TokenName The name of the PCD token to retrieve a current value for.
+
+ @return A pointer to a PCD token buffer.
+
+**/
+#define PcdGetExPtr(Guid, TokenName) LibPcdGetExPtr ((Guid), PcdTokenEx(Guid,TokenName))
+
+/**
+ Retrieves a Boolean PCD token value based on a GUID and a token name.
+
+ Returns the Boolean value for the token specified by Guid and TokenName.
+ If TokenName is not a valid token in the token space specified by Guid,
+ then the module will not build.
+
+ If Guid is NULL, then ASSERT().
+
+ @param Guid Pointer to a 128-bit unique value that designates
+ which namespace to retrieve a value from.
+ @param TokenName The name of the PCD token to retrieve a current value for.
+
+ @return A Boolean PCD token value.
+
+**/
+#define PcdGetExBool(Guid, TokenName) LibPcdGetExBool ((Guid), PcdTokenEx(Guid,TokenName))
+
+/**
+ Sets an 8-bit PCD token value based on a GUID and a token name.
+
+ Sets the 8-bit value for the token specified by Guid and TokenName.
+ If TokenName is not a valid token in the token space specified by Guid,
+ then the module will not build.
+
+ If Guid is NULL, then ASSERT().
+
+ @param Guid Pointer to a 128-bit unique value that designates
+ which namespace to retrieve a value from.
+ @param TokenName The name of the PCD token to set the current value for.
+ @param Value The 8-bit value to set.
+
+ @return The status of the set operation.
+
+**/
+#define PcdSetEx8S(Guid, TokenName, Value) LibPcdSetEx8S ((Guid), PcdTokenEx(Guid,TokenName), (Value))
+
+/**
+ Sets an 16-bit PCD token value based on a GUID and a token name.
+
+ Sets the 16-bit value for the token specified by Guid and TokenName.
+ If TokenName is not a valid token in the token space specified by Guid,
+ then the module will not build.
+
+ If Guid is NULL, then ASSERT().
+
+ @param Guid Pointer to a 128-bit unique value that designates
+ which namespace to retrieve a value from.
+ @param TokenName The name of the PCD token to set the current value for.
+ @param Value The 16-bit value to set.
+
+ @return The status of the set operation.
+
+**/
+#define PcdSetEx16S(Guid, TokenName, Value) LibPcdSetEx16S ((Guid), PcdTokenEx(Guid,TokenName), (Value))
+
+/**
+ Sets an 32-bit PCD token value based on a GUID and a token name.
+
+ Sets the 32-bit value for the token specified by Guid and TokenName.
+ If TokenName is not a valid token in the token space specified by Guid,
+ then the module will not build.
+
+ If Guid is NULL, then ASSERT().
+
+ @param Guid Pointer to a 128-bit unique value that designates
+ which namespace to retrieve a value from.
+ @param TokenName The name of the PCD token to set the current value for.
+ @param Value The 32-bit value to set.
+
+ @return The status of the set operation.
+
+**/
+#define PcdSetEx32S(Guid, TokenName, Value) LibPcdSetEx32S ((Guid), PcdTokenEx(Guid,TokenName), (Value))
+
+/**
+ Sets an 64-bit PCD token value based on a GUID and a token name.
+
+ Sets the 64-bit value for the token specified by Guid and TokenName.
+ If TokenName is not a valid token in the token space specified by Guid,
+ then the module will not build.
+
+ If Guid is NULL, then ASSERT().
+
+ @param Guid Pointer to a 128-bit unique value that designates
+ which namespace to retrieve a value from.
+ @param TokenName The name of the PCD token to set the current value for.
+ @param Value The 64-bit value to set.
+
+ @return The status of the set operation.
+
+**/
+#define PcdSetEx64S(Guid, TokenName, Value) LibPcdSetEx64S ((Guid), PcdTokenEx(Guid,TokenName), (Value))
+
+/**
+ Sets a pointer to a PCD token buffer based on a GUID and a token name.
+
+ Sets the buffer for the token specified by Guid and TokenName.
+ If SizeOfBuffer is greater than the maximum size supported by Guid and TokenName,
+ then set SizeOfBuffer to the maximum size supported by Guid and TokenName and return
+ RETURN_INVALID_PARAMETER to indicate that the set operation was not actually performed.
+ If SizeOfBuffer is set to MAX_ADDRESS, then SizeOfBuffer must be set to the maximum size
+ supported by Guid and TokenName and RETURN_INVALID_PARAMETER must be returned.
+ If TokenName is not a valid token in the token space specified by Guid,
+ then the module will not build.
+
+ If Guid is NULL, then ASSERT().
+ If SizeOfBuffer is NULL, then ASSERT().
+ If SizeOfBuffer > 0 and Buffer is NULL, then ASSERT().
+
+ @param Guid Pointer to a 128-bit unique value that designates
+ which namespace to retrieve a value from.
+ @param TokenName The name of the PCD token to set the current value for.
+ @param SizeOfBuffer A pointer to the size, in bytes, of Buffer.
+ @param Buffer Pointer to the buffer to set.
+
+ @return The status of the set operation.
+
+**/
+#define PcdSetExPtrS(Guid, TokenName, SizeOfBuffer, Buffer) \
+ LibPcdSetExPtrS ((Guid), PcdTokenEx(Guid,TokenName), (SizeOfBuffer), (Buffer))
+
+/**
+ Sets an boolean PCD token value based on a GUID and a token name.
+
+ Sets the boolean value for the token specified by Guid and TokenName.
+ If TokenName is not a valid token in the token space specified by Guid,
+ then the module will not build.
+
+ If Guid is NULL, then ASSERT().
+
+ @param Guid Pointer to a 128-bit unique value that designates
+ which namespace to retrieve a value from.
+ @param TokenName The name of the PCD token to set the current value for.
+ @param Value The boolean value to set.
+
+ @return The status of the set operation.
+
+**/
+#define PcdSetExBoolS(Guid, TokenName, Value) \
+ LibPcdSetExBoolS ((Guid), PcdTokenEx(Guid,TokenName), (Value))
+
+/**
+ This function provides a means by which SKU support can be established in the PCD infrastructure.
+
+ Sets the current SKU in the PCD database to the value specified by SkuId. SkuId is returned.
+
+ @param SkuId The SKU value that will be used when the PCD service retrieves and sets values
+ associated with a PCD token.
+
+ @return Return the SKU ID that was set.
+
+**/
+UINTN
+EFIAPI
+LibPcdSetSku (
+ IN UINTN SkuId
+ );
+
+/**
+ This function provides a means by which to retrieve a value for a given PCD token.
+
+ Returns the 8-bit value for the token specified by TokenNumber.
+
+ @param[in] TokenNumber The PCD token number to retrieve a current value for.
+
+ @return Returns the 8-bit value for the token specified by TokenNumber.
+
+**/
+UINT8
+EFIAPI
+LibPcdGet8 (
+ IN UINTN TokenNumber
+ );
+
+/**
+ This function provides a means by which to retrieve a value for a given PCD token.
+
+ Returns the 16-bit value for the token specified by TokenNumber.
+
+ @param[in] TokenNumber The PCD token number to retrieve a current value for.
+
+ @return Returns the 16-bit value for the token specified by TokenNumber.
+
+**/
+UINT16
+EFIAPI
+LibPcdGet16 (
+ IN UINTN TokenNumber
+ );
+
+/**
+ This function provides a means by which to retrieve a value for a given PCD token.
+
+ Returns the 32-bit value for the token specified by TokenNumber.
+
+ @param[in] TokenNumber The PCD token number to retrieve a current value for.
+
+ @return Returns the 32-bit value for the token specified by TokenNumber.
+
+**/
+UINT32
+EFIAPI
+LibPcdGet32 (
+ IN UINTN TokenNumber
+ );
+
+/**
+ This function provides a means by which to retrieve a value for a given PCD token.
+
+ Returns the 64-bit value for the token specified by TokenNumber.
+
+ @param[in] TokenNumber The PCD token number to retrieve a current value for.
+
+ @return Returns the 64-bit value for the token specified by TokenNumber.
+
+**/
+UINT64
+EFIAPI
+LibPcdGet64 (
+ IN UINTN TokenNumber
+ );
+
+/**
+ This function provides a means by which to retrieve a value for a given PCD token.
+
+ Returns the pointer to the buffer of the token specified by TokenNumber.
+
+ @param[in] TokenNumber The PCD token number to retrieve a current value for.
+
+ @return Returns the pointer to the token specified by TokenNumber.
+
+**/
+VOID *
+EFIAPI
+LibPcdGetPtr (
+ IN UINTN TokenNumber
+ );
+
+/**
+ This function provides a means by which to retrieve a value for a given PCD token.
+
+ Returns the Boolean value of the token specified by TokenNumber.
+
+ @param[in] TokenNumber The PCD token number to retrieve a current value for.
+
+ @return Returns the Boolean value of the token specified by TokenNumber.
+
+**/
+BOOLEAN
+EFIAPI
+LibPcdGetBool (
+ IN UINTN TokenNumber
+ );
+
+/**
+ This function provides a means by which to retrieve the size of a given PCD token.
+
+ @param[in] TokenNumber The PCD token number to retrieve a current value for.
+
+ @return Returns the size of the token specified by TokenNumber.
+
+**/
+UINTN
+EFIAPI
+LibPcdGetSize (
+ IN UINTN TokenNumber
+ );
+
+/**
+ This function provides a means by which to retrieve a value for a given PCD token.
+
+ Returns the 8-bit value for the token specified by TokenNumber and Guid.
+
+ If Guid is NULL, then ASSERT().
+
+ @param[in] Guid Pointer to a 128-bit unique value that designates
+ which namespace to retrieve a value from.
+ @param[in] TokenNumber The PCD token number to retrieve a current value for.
+
+ @return Return the UINT8.
+
+**/
+UINT8
+EFIAPI
+LibPcdGetEx8 (
+ IN CONST GUID *Guid,
+ IN UINTN TokenNumber
+ );
+
+/**
+ This function provides a means by which to retrieve a value for a given PCD token.
+
+ Returns the 16-bit value for the token specified by TokenNumber and Guid.
+
+ If Guid is NULL, then ASSERT().
+
+ @param[in] Guid Pointer to a 128-bit unique value that designates
+ which namespace to retrieve a value from.
+ @param[in] TokenNumber The PCD token number to retrieve a current value for.
+
+ @return Return the UINT16.
+
+**/
+UINT16
+EFIAPI
+LibPcdGetEx16 (
+ IN CONST GUID *Guid,
+ IN UINTN TokenNumber
+ );
+
+/**
+ Returns the 32-bit value for the token specified by TokenNumber and Guid.
+ If Guid is NULL, then ASSERT().
+
+ @param[in] Guid Pointer to a 128-bit unique value that designates
+ which namespace to retrieve a value from.
+ @param[in] TokenNumber The PCD token number to retrieve a current value for.
+
+ @return Return the UINT32.
+
+**/
+UINT32
+EFIAPI
+LibPcdGetEx32 (
+ IN CONST GUID *Guid,
+ IN UINTN TokenNumber
+ );
+
+/**
+ This function provides a means by which to retrieve a value for a given PCD token.
+
+ Returns the 64-bit value for the token specified by TokenNumber and Guid.
+
+ If Guid is NULL, then ASSERT().
+
+ @param[in] Guid Pointer to a 128-bit unique value that designates
+ which namespace to retrieve a value from.
+ @param[in] TokenNumber The PCD token number to retrieve a current value for.
+
+ @return Return the UINT64.
+
+**/
+UINT64
+EFIAPI
+LibPcdGetEx64 (
+ IN CONST GUID *Guid,
+ IN UINTN TokenNumber
+ );
+
+/**
+ This function provides a means by which to retrieve a value for a given PCD token.
+
+ Returns the pointer to the buffer of token specified by TokenNumber and Guid.
+
+ If Guid is NULL, then ASSERT().
+
+ @param[in] Guid Pointer to a 128-bit unique value that designates
+ which namespace to retrieve a value from.
+ @param[in] TokenNumber The PCD token number to retrieve a current value for.
+
+ @return Return the VOID* pointer.
+
+**/
+VOID *
+EFIAPI
+LibPcdGetExPtr (
+ IN CONST GUID *Guid,
+ IN UINTN TokenNumber
+ );
+
+/**
+ This function provides a means by which to retrieve a value for a given PCD token.
+
+ Returns the Boolean value of the token specified by TokenNumber and Guid.
+
+ If Guid is NULL, then ASSERT().
+
+ @param[in] Guid Pointer to a 128-bit unique value that designates
+ which namespace to retrieve a value from.
+ @param[in] TokenNumber The PCD token number to retrieve a current value for.
+
+ @return Return the BOOLEAN.
+
+**/
+BOOLEAN
+EFIAPI
+LibPcdGetExBool (
+ IN CONST GUID *Guid,
+ IN UINTN TokenNumber
+ );
+
+/**
+ This function provides a means by which to retrieve the size of a given PCD token.
+
+ Returns the size of the token specified by TokenNumber and Guid.
+
+ If Guid is NULL, then ASSERT().
+
+ @param[in] Guid Pointer to a 128-bit unique value that designates
+ which namespace to retrieve a value from.
+ @param[in] TokenNumber The PCD token number to retrieve a current value for.
+
+ @return Return the size.
+
+**/
+UINTN
+EFIAPI
+LibPcdGetExSize (
+ IN CONST GUID *Guid,
+ IN UINTN TokenNumber
+ );
+
+/**
+ This function provides a means by which to set a value for a given PCD token.
+
+ Sets the 8-bit value for the token specified by TokenNumber
+ to the value specified by Value.
+
+ @param[in] TokenNumber The PCD token number to set a current value for.
+ @param[in] Value The 8-bit value to set.
+
+ @return The status of the set operation.
+
+**/
+RETURN_STATUS
+EFIAPI
+LibPcdSet8S (
+ IN UINTN TokenNumber,
+ IN UINT8 Value
+ );
+
+/**
+ This function provides a means by which to set a value for a given PCD token.
+
+ Sets the 16-bit value for the token specified by TokenNumber
+ to the value specified by Value.
+
+ @param[in] TokenNumber The PCD token number to set a current value for.
+ @param[in] Value The 16-bit value to set.
+
+ @return The status of the set operation.
+
+**/
+RETURN_STATUS
+EFIAPI
+LibPcdSet16S (
+ IN UINTN TokenNumber,
+ IN UINT16 Value
+ );
+
+/**
+ This function provides a means by which to set a value for a given PCD token.
+
+ Sets the 32-bit value for the token specified by TokenNumber
+ to the value specified by Value.
+
+ @param[in] TokenNumber The PCD token number to set a current value for.
+ @param[in] Value The 32-bit value to set.
+
+ @return The status of the set operation.
+
+**/
+RETURN_STATUS
+EFIAPI
+LibPcdSet32S (
+ IN UINTN TokenNumber,
+ IN UINT32 Value
+ );
+
+/**
+ This function provides a means by which to set a value for a given PCD token.
+
+ Sets the 64-bit value for the token specified by TokenNumber
+ to the value specified by Value.
+
+ @param[in] TokenNumber The PCD token number to set a current value for.
+ @param[in] Value The 64-bit value to set.
+
+ @return The status of the set operation.
+
+**/
+RETURN_STATUS
+EFIAPI
+LibPcdSet64S (
+ IN UINTN TokenNumber,
+ IN UINT64 Value
+ );
+
+/**
+ This function provides a means by which to set a value for a given PCD token.
+
+ Sets a buffer for the token specified by TokenNumber to the value specified
+ by Buffer and SizeOfBuffer. If SizeOfBuffer is greater than the maximum size
+ support by TokenNumber, then set SizeOfBuffer to the maximum size supported by
+ TokenNumber and return RETURN_INVALID_PARAMETER to indicate that the set operation
+ was not actually performed.
+
+ If SizeOfBuffer is set to MAX_ADDRESS, then SizeOfBuffer must be set to the
+ maximum size supported by TokenName and RETURN_INVALID_PARAMETER must be returned.
+
+ If SizeOfBuffer is NULL, then ASSERT().
+ If SizeOfBuffer > 0 and Buffer is NULL, then ASSERT().
+
+ @param[in] TokenNumber The PCD token number to set a current value for.
+ @param[in, out] SizeOfBuffer The size, in bytes, of Buffer.
+ @param[in] Buffer A pointer to the buffer to set.
+
+ @return The status of the set operation.
+
+**/
+RETURN_STATUS
+EFIAPI
+LibPcdSetPtrS (
+ IN UINTN TokenNumber,
+ IN OUT UINTN *SizeOfBuffer,
+ IN CONST VOID *Buffer
+ );
+
+/**
+ This function provides a means by which to set a value for a given PCD token.
+
+ Sets the boolean value for the token specified by TokenNumber
+ to the value specified by Value.
+
+ @param[in] TokenNumber The PCD token number to set a current value for.
+ @param[in] Value The boolean value to set.
+
+ @return The status of the set operation.
+
+**/
+RETURN_STATUS
+EFIAPI
+LibPcdSetBoolS (
+ IN UINTN TokenNumber,
+ IN BOOLEAN Value
+ );
+
+/**
+ This function provides a means by which to set a value for a given PCD token.
+
+ Sets the 8-bit value for the token specified by TokenNumber
+ to the value specified by Value.
+
+ If Guid is NULL, then ASSERT().
+
+ @param[in] Guid The pointer to a 128-bit unique value that
+ designates which namespace to set a value from.
+ @param[in] TokenNumber The PCD token number to set a current value for.
+ @param[in] Value The 8-bit value to set.
+
+ @return The status of the set operation.
+
+**/
+RETURN_STATUS
+EFIAPI
+LibPcdSetEx8S (
+ IN CONST GUID *Guid,
+ IN UINTN TokenNumber,
+ IN UINT8 Value
+ );
+
+/**
+ This function provides a means by which to set a value for a given PCD token.
+
+ Sets the 16-bit value for the token specified by TokenNumber
+ to the value specified by Value.
+
+ If Guid is NULL, then ASSERT().
+
+ @param[in] Guid The pointer to a 128-bit unique value that
+ designates which namespace to set a value from.
+ @param[in] TokenNumber The PCD token number to set a current value for.
+ @param[in] Value The 16-bit value to set.
+
+ @return The status of the set operation.
+
+**/
+RETURN_STATUS
+EFIAPI
+LibPcdSetEx16S (
+ IN CONST GUID *Guid,
+ IN UINTN TokenNumber,
+ IN UINT16 Value
+ );
+
+/**
+ This function provides a means by which to set a value for a given PCD token.
+
+ Sets the 32-bit value for the token specified by TokenNumber
+ to the value specified by Value.
+
+ If Guid is NULL, then ASSERT().
+
+ @param[in] Guid The pointer to a 128-bit unique value that
+ designates which namespace to set a value from.
+ @param[in] TokenNumber The PCD token number to set a current value for.
+ @param[in] Value The 32-bit value to set.
+
+ @return The status of the set operation.
+
+**/
+RETURN_STATUS
+EFIAPI
+LibPcdSetEx32S (
+ IN CONST GUID *Guid,
+ IN UINTN TokenNumber,
+ IN UINT32 Value
+ );
+
+/**
+ This function provides a means by which to set a value for a given PCD token.
+
+ Sets the 64-bit value for the token specified by TokenNumber
+ to the value specified by Value.
+
+ If Guid is NULL, then ASSERT().
+
+ @param[in] Guid The pointer to a 128-bit unique value that
+ designates which namespace to set a value from.
+ @param[in] TokenNumber The PCD token number to set a current value for.
+ @param[in] Value The 64-bit value to set.
+
+ @return The status of the set operation.
+
+**/
+RETURN_STATUS
+EFIAPI
+LibPcdSetEx64S (
+ IN CONST GUID *Guid,
+ IN UINTN TokenNumber,
+ IN UINT64 Value
+ );
+
+/**
+ This function provides a means by which to set a value for a given PCD token.
+
+ Sets a buffer for the token specified by TokenNumber to the value specified by
+ Buffer and SizeOfBuffer. If SizeOfBuffer is greater than the maximum size
+ support by TokenNumber, then set SizeOfBuffer to the maximum size supported by
+ TokenNumber and return RETURN_INVALID_PARAMETER to indicate that the set operation
+ was not actually performed.
+
+ If Guid is NULL, then ASSERT().
+ If SizeOfBuffer is NULL, then ASSERT().
+ If SizeOfBuffer > 0 and Buffer is NULL, then ASSERT().
+
+ @param[in] Guid Pointer to a 128-bit unique value that
+ designates which namespace to set a value from.
+ @param[in] TokenNumber The PCD token number to set a current value for.
+ @param[in, out] SizeOfBuffer The size, in bytes, of Buffer.
+ @param[in] Buffer A pointer to the buffer to set.
+
+ @return The status of the set operation.
+
+**/
+RETURN_STATUS
+EFIAPI
+LibPcdSetExPtrS (
+ IN CONST GUID *Guid,
+ IN UINTN TokenNumber,
+ IN OUT UINTN *SizeOfBuffer,
+ IN VOID *Buffer
+ );
+
+/**
+ This function provides a means by which to set a value for a given PCD token.
+
+ Sets the boolean value for the token specified by TokenNumber
+ to the value specified by Value.
+
+ If Guid is NULL, then ASSERT().
+
+ @param[in] Guid The pointer to a 128-bit unique value that
+ designates which namespace to set a value from.
+ @param[in] TokenNumber The PCD token number to set a current value for.
+ @param[in] Value The boolean value to set.
+
+ @return The status of the set operation.
+
+**/
+RETURN_STATUS
+EFIAPI
+LibPcdSetExBoolS (
+ IN CONST GUID *Guid,
+ IN UINTN TokenNumber,
+ IN BOOLEAN Value
+ );
+
+/**
+ This notification function serves two purposes.
+
+ Firstly, it notifies the module that did the registration that the value of this
+ PCD token has been set.
+ Secondly, it provides a mechanism for the module that did the registration to intercept
+ the set operation and override the value been set if necessary. After the invocation of
+ the callback function, TokenData will be used by PCD service PEIM or driver to modify th
+ internal data in PCD database.
+
+ @param[in] CallBackGuid The PCD token GUID being set.
+ @param[in] CallBackToken The PCD token number being set.
+ @param[in, out] TokenData A pointer to the token data being set.
+ @param[in] TokenDataSize The size, in bytes, of the data being set.
+
+**/
+typedef
+VOID
+(EFIAPI *PCD_CALLBACK)(
+ IN CONST GUID *CallBackGuid OPTIONAL,
+ IN UINTN CallBackToken,
+ IN OUT VOID *TokenData,
+ IN UINTN TokenDataSize
+ );
+
+/**
+ Set up a notification function that is called when a specified token is set.
+
+ When the token specified by TokenNumber and Guid is set,
+ then notification function specified by NotificationFunction is called.
+ If Guid is NULL, then the default token space is used.
+ If NotificationFunction is NULL, then ASSERT().
+
+ @param[in] Guid Pointer to a 128-bit unique value that designates which
+ namespace to set a value from. If NULL, then the default
+ token space is used.
+ @param[in] TokenNumber The PCD token number to monitor.
+ @param[in] NotificationFunction The function to call when the token
+ specified by Guid and TokenNumber is set.
+
+**/
+VOID
+EFIAPI
+LibPcdCallbackOnSet (
+ IN CONST GUID *Guid OPTIONAL,
+ IN UINTN TokenNumber,
+ IN PCD_CALLBACK NotificationFunction
+ );
+
+/**
+ Disable a notification function that was established with LibPcdCallbackonSet().
+
+ Disable a notification function that was previously established with LibPcdCallbackOnSet().
+ If NotificationFunction is NULL, then ASSERT().
+ If LibPcdCallbackOnSet() was not previously called with Guid, TokenNumber,
+ and NotificationFunction, then ASSERT().
+
+ @param[in] Guid Specify the GUID token space.
+ @param[in] TokenNumber Specify the token number.
+ @param[in] NotificationFunction The callback function to be unregistered.
+
+**/
+VOID
+EFIAPI
+LibPcdCancelCallback (
+ IN CONST GUID *Guid OPTIONAL,
+ IN UINTN TokenNumber,
+ IN PCD_CALLBACK NotificationFunction
+ );
+
+/**
+ Retrieves the next token in a token space.
+
+ Retrieves the next PCD token number from the token space specified by Guid.
+ If Guid is NULL, then the default token space is used. If TokenNumber is 0,
+ then the first token number is returned. Otherwise, the token number that
+ follows TokenNumber in the token space is returned. If TokenNumber is the last
+ token number in the token space, then 0 is returned.
+
+ If TokenNumber is not 0 and is not in the token space specified by Guid, then ASSERT().
+
+ @param[in] Guid Pointer to a 128-bit unique value that designates which namespace
+ to set a value from. If NULL, then the default token space is used.
+ @param[in] TokenNumber The previous PCD token number. If 0, then retrieves the first PCD
+ token number.
+
+ @return The next valid token number.
+
+**/
+UINTN
+EFIAPI
+LibPcdGetNextToken (
+ IN CONST GUID *Guid OPTIONAL,
+ IN UINTN TokenNumber
+ );
+
+/**
+ Used to retrieve the list of available PCD token space GUIDs.
+
+ Returns the PCD token space GUID that follows TokenSpaceGuid in the list of token spaces
+ in the platform.
+ If TokenSpaceGuid is NULL, then a pointer to the first PCD token spaces returned.
+ If TokenSpaceGuid is the last PCD token space GUID in the list, then NULL is returned.
+
+ @param TokenSpaceGuid Pointer to the a PCD token space GUID
+
+ @return The next valid token namespace.
+
+**/
+GUID *
+EFIAPI
+LibPcdGetNextTokenSpace (
+ IN CONST GUID *TokenSpaceGuid
+ );
+
+/**
+ Sets a value of a patchable PCD entry that is type pointer.
+
+ Sets the PCD entry specified by PatchVariable to the value specified by Buffer
+ and SizeOfBuffer. Buffer is returned. If SizeOfBuffer is greater than
+ MaximumDatumSize, then set SizeOfBuffer to MaximumDatumSize and return
+ NULL to indicate that the set operation was not actually performed.
+ If SizeOfBuffer is set to MAX_ADDRESS, then SizeOfBuffer must be set to
+ MaximumDatumSize and NULL must be returned.
+
+ If PatchVariable is NULL, then ASSERT().
+ If SizeOfBuffer is NULL, then ASSERT().
+ If SizeOfBuffer > 0 and Buffer is NULL, then ASSERT().
+
+ @param[out] PatchVariable A pointer to the global variable in a module that is
+ the target of the set operation.
+ @param[in] MaximumDatumSize The maximum size allowed for the PCD entry specified by PatchVariable.
+ @param[in, out] SizeOfBuffer A pointer to the size, in bytes, of Buffer.
+ @param[in] Buffer A pointer to the buffer to used to set the target variable.
+
+ @return Return the pointer to the Buffer that was set.
+
+**/
+VOID *
+EFIAPI
+LibPatchPcdSetPtr (
+ OUT VOID *PatchVariable,
+ IN UINTN MaximumDatumSize,
+ IN OUT UINTN *SizeOfBuffer,
+ IN CONST VOID *Buffer
+ );
+
+/**
+ Sets a value of a patchable PCD entry that is type pointer.
+
+ Sets the PCD entry specified by PatchVariable to the value specified
+ by Buffer and SizeOfBuffer. If SizeOfBuffer is greater than MaximumDatumSize,
+ then set SizeOfBuffer to MaximumDatumSize and return RETURN_INVALID_PARAMETER
+ to indicate that the set operation was not actually performed.
+ If SizeOfBuffer is set to MAX_ADDRESS, then SizeOfBuffer must be set to
+ MaximumDatumSize and RETURN_INVALID_PARAMETER must be returned.
+
+ If PatchVariable is NULL, then ASSERT().
+ If SizeOfBuffer is NULL, then ASSERT().
+ If SizeOfBuffer > 0 and Buffer is NULL, then ASSERT().
+
+ @param[out] PatchVariable A pointer to the global variable in a module that is
+ the target of the set operation.
+ @param[in] MaximumDatumSize The maximum size allowed for the PCD entry specified by PatchVariable.
+ @param[in, out] SizeOfBuffer A pointer to the size, in bytes, of Buffer.
+ @param[in] Buffer A pointer to the buffer to used to set the target variable.
+
+ @return The status of the set operation.
+
+**/
+RETURN_STATUS
+EFIAPI
+LibPatchPcdSetPtrS (
+ OUT VOID *PatchVariable,
+ IN UINTN MaximumDatumSize,
+ IN OUT UINTN *SizeOfBuffer,
+ IN CONST VOID *Buffer
+ );
+
+/**
+ Sets a value and size of a patchable PCD entry that is type pointer.
+
+ Sets the PCD entry specified by PatchVariable to the value specified by Buffer
+ and SizeOfBuffer. Buffer is returned. If SizeOfBuffer is greater than
+ MaximumDatumSize, then set SizeOfBuffer to MaximumDatumSize and return
+ NULL to indicate that the set operation was not actually performed.
+ If SizeOfBuffer is set to MAX_ADDRESS, then SizeOfBuffer must be set to
+ MaximumDatumSize and NULL must be returned.
+
+ If PatchVariable is NULL, then ASSERT().
+ If SizeOfPatchVariable is NULL, then ASSERT().
+ If SizeOfBuffer is NULL, then ASSERT().
+ If SizeOfBuffer > 0 and Buffer is NULL, then ASSERT().
+
+ @param[out] PatchVariable A pointer to the global variable in a module that is
+ the target of the set operation.
+ @param[out] SizeOfPatchVariable A pointer to the size, in bytes, of PatchVariable.
+ @param[in] MaximumDatumSize The maximum size allowed for the PCD entry specified by PatchVariable.
+ @param[in, out] SizeOfBuffer A pointer to the size, in bytes, of Buffer.
+ @param[in] Buffer A pointer to the buffer to used to set the target variable.
+
+ @return Return the pointer to the Buffer that was set.
+
+**/
+VOID *
+EFIAPI
+LibPatchPcdSetPtrAndSize (
+ OUT VOID *PatchVariable,
+ OUT UINTN *SizeOfPatchVariable,
+ IN UINTN MaximumDatumSize,
+ IN OUT UINTN *SizeOfBuffer,
+ IN CONST VOID *Buffer
+ );
+
+/**
+ Sets a value and size of a patchable PCD entry that is type pointer.
+
+ Sets the PCD entry specified by PatchVariable to the value specified
+ by Buffer and SizeOfBuffer. If SizeOfBuffer is greater than MaximumDatumSize,
+ then set SizeOfBuffer to MaximumDatumSize and return RETURN_INVALID_PARAMETER
+ to indicate that the set operation was not actually performed.
+ If SizeOfBuffer is set to MAX_ADDRESS, then SizeOfBuffer must be set to
+ MaximumDatumSize and RETURN_INVALID_PARAMETER must be returned.
+
+ If PatchVariable is NULL, then ASSERT().
+ If SizeOfPatchVariable is NULL, then ASSERT().
+ If SizeOfBuffer is NULL, then ASSERT().
+ If SizeOfBuffer > 0 and Buffer is NULL, then ASSERT().
+
+ @param[out] PatchVariable A pointer to the global variable in a module that is
+ the target of the set operation.
+ @param[out] SizeOfPatchVariable A pointer to the size, in bytes, of PatchVariable.
+ @param[in] MaximumDatumSize The maximum size allowed for the PCD entry specified by PatchVariable.
+ @param[in, out] SizeOfBuffer A pointer to the size, in bytes, of Buffer.
+ @param[in] Buffer A pointer to the buffer to used to set the target variable.
+
+ @return The status of the set operation.
+
+**/
+RETURN_STATUS
+EFIAPI
+LibPatchPcdSetPtrAndSizeS (
+ OUT VOID *PatchVariable,
+ OUT UINTN *SizeOfPatchVariable,
+ IN UINTN MaximumDatumSize,
+ IN OUT UINTN *SizeOfBuffer,
+ IN CONST VOID *Buffer
+ );
+
+typedef enum {
+ PCD_TYPE_8,
+ PCD_TYPE_16,
+ PCD_TYPE_32,
+ PCD_TYPE_64,
+ PCD_TYPE_BOOL,
+ PCD_TYPE_PTR
+} PCD_TYPE;
+
+typedef struct {
+ ///
+ /// The returned information associated with the requested TokenNumber. If
+ /// TokenNumber is 0, then PcdType is set to PCD_TYPE_8.
+ ///
+ PCD_TYPE PcdType;
+ ///
+ /// The size of the data in bytes associated with the TokenNumber specified. If
+ /// TokenNumber is 0, then PcdSize is set 0.
+ ///
+ UINTN PcdSize;
+ ///
+ /// The null-terminated ASCII string associated with a given token. If the
+ /// TokenNumber specified was 0, then this field corresponds to the null-terminated
+ /// ASCII string associated with the token's namespace Guid. If NULL, there is no
+ /// name associated with this request.
+ ///
+ CHAR8 *PcdName;
+} PCD_INFO;
+
+/**
+ Retrieve additional information associated with a PCD token.
+
+ This includes information such as the type of value the TokenNumber is associated with as well as possible
+ human readable name that is associated with the token.
+
+ If TokenNumber is not in the default token space specified, then ASSERT().
+
+ @param[in] TokenNumber The PCD token number.
+ @param[out] PcdInfo The returned information associated with the requested TokenNumber.
+ The caller is responsible for freeing the buffer that is allocated by callee for PcdInfo->PcdName.
+**/
+VOID
+EFIAPI
+LibPcdGetInfo (
+ IN UINTN TokenNumber,
+ OUT PCD_INFO *PcdInfo
+ );
+
+/**
+ Retrieve additional information associated with a PCD token.
+
+ This includes information such as the type of value the TokenNumber is associated with as well as possible
+ human readable name that is associated with the token.
+
+ If TokenNumber is not in the token space specified by Guid, then ASSERT().
+
+ @param[in] Guid The 128-bit unique value that designates the namespace from which to extract the value.
+ @param[in] TokenNumber The PCD token number.
+ @param[out] PcdInfo The returned information associated with the requested TokenNumber.
+ The caller is responsible for freeing the buffer that is allocated by callee for PcdInfo->PcdName.
+**/
+VOID
+EFIAPI
+LibPcdGetInfoEx (
+ IN CONST GUID *Guid,
+ IN UINTN TokenNumber,
+ OUT PCD_INFO *PcdInfo
+ );
+
+/**
+ Retrieve the currently set SKU Id.
+
+ @return The currently set SKU Id. If the platform has not set at a SKU Id, then the
+ default SKU Id value of 0 is returned. If the platform has set a SKU Id, then the currently set SKU
+ Id is returned.
+**/
+UINTN
+EFIAPI
+LibPcdGetSku (
+ VOID
+ );
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/PciCf8Lib.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/PciCf8Lib.h
new file mode 100644
index 0000000000..e730fe5d1e
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/PciCf8Lib.h
@@ -0,0 +1,1087 @@
+/** @file
+ Provides services to access PCI Configuration Space using the I/O ports 0xCF8 and 0xCFC.
+
+ This library is identical to the PCI Library, except the access method for performing PCI
+ configuration cycles must be through I/O ports 0xCF8 and 0xCFC. This library only allows
+ access to PCI Segment #0.
+
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __PCI_CF8_LIB_H__
+#define __PCI_CF8_LIB_H__
+
+/**
+ Macro that converts PCI Bus, PCI Device, PCI Function and PCI Register to an
+ address that can be passed to the PCI Library functions.
+
+ Computes an address that is compatible with the PCI Library functions. The
+ unused upper bits of Bus, Device, Function and Register are stripped prior to
+ the generation of the address.
+
+ @param Bus PCI Bus number. Range 0..255.
+ @param Device PCI Device number. Range 0..31.
+ @param Function PCI Function number. Range 0..7.
+ @param Register PCI Register number. Range 0..255.
+
+ @return The encode PCI address.
+
+**/
+#define PCI_CF8_LIB_ADDRESS(Bus, Device, Function, Offset) \
+ (((Offset) & 0xfff) | (((Function) & 0x07) << 12) | (((Device) & 0x1f) << 15) | (((Bus) & 0xff) << 20))
+
+/**
+ Registers a PCI device so PCI configuration registers may be accessed after
+ SetVirtualAddressMap().
+
+ Registers the PCI device specified by Address so all the PCI configuration registers
+ associated with that PCI device may be accessed after SetVirtualAddressMap() is called.
+
+ If Address > 0x0FFFFFFF, then ASSERT().
+ If the register specified by Address >= 0x100, then ASSERT().
+
+ @param Address Address that encodes the PCI Bus, Device, Function and
+ Register.
+
+ @retval RETURN_SUCCESS The PCI device was registered for runtime access.
+ @retval RETURN_UNSUPPORTED An attempt was made to call this function
+ after ExitBootServices().
+ @retval RETURN_UNSUPPORTED The resources required to access the PCI device
+ at runtime could not be mapped.
+ @retval RETURN_OUT_OF_RESOURCES There are not enough resources available to
+ complete the registration.
+
+**/
+RETURN_STATUS
+EFIAPI
+PciCf8RegisterForRuntimeAccess (
+ IN UINTN Address
+ );
+
+/**
+ Reads an 8-bit PCI configuration register.
+
+ Reads and returns the 8-bit PCI configuration register specified by Address.
+ This function must guarantee that all PCI read and write operations are
+ serialized.
+
+ If Address > 0x0FFFFFFF, then ASSERT().
+ If the register specified by Address >= 0x100, then ASSERT().
+
+ @param Address Address that encodes the PCI Bus, Device, Function and
+ Register.
+
+ @return The read value from the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+PciCf8Read8 (
+ IN UINTN Address
+ );
+
+/**
+ Writes an 8-bit PCI configuration register.
+
+ Writes the 8-bit PCI configuration register specified by Address with the
+ value specified by Value. Value is returned. This function must guarantee
+ that all PCI read and write operations are serialized.
+
+ If Address > 0x0FFFFFFF, then ASSERT().
+ If the register specified by Address >= 0x100, then ASSERT().
+
+ @param Address Address that encodes the PCI Bus, Device, Function and
+ Register.
+ @param Value The value to write.
+
+ @return The value written to the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+PciCf8Write8 (
+ IN UINTN Address,
+ IN UINT8 Value
+ );
+
+/**
+ Performs a bitwise OR of an 8-bit PCI configuration register with
+ an 8-bit value.
+
+ Reads the 8-bit PCI configuration register specified by Address, performs a
+ bitwise OR between the read result and the value specified by
+ OrData, and writes the result to the 8-bit PCI configuration register
+ specified by Address. The value written to the PCI configuration register is
+ returned. This function must guarantee that all PCI read and write operations
+ are serialized.
+
+ If Address > 0x0FFFFFFF, then ASSERT().
+ If the register specified by Address >= 0x100, then ASSERT().
+
+ @param Address Address that encodes the PCI Bus, Device, Function and
+ Register.
+ @param OrData The value to OR with the PCI configuration register.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+PciCf8Or8 (
+ IN UINTN Address,
+ IN UINT8 OrData
+ );
+
+/**
+ Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
+ value.
+
+ Reads the 8-bit PCI configuration register specified by Address, performs a
+ bitwise AND between the read result and the value specified by AndData, and
+ writes the result to the 8-bit PCI configuration register specified by
+ Address. The value written to the PCI configuration register is returned.
+ This function must guarantee that all PCI read and write operations are
+ serialized.
+
+ If Address > 0x0FFFFFFF, then ASSERT().
+ If the register specified by Address >= 0x100, then ASSERT().
+
+ @param Address Address that encodes the PCI Bus, Device, Function and
+ Register.
+ @param AndData The value to AND with the PCI configuration register.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+PciCf8And8 (
+ IN UINTN Address,
+ IN UINT8 AndData
+ );
+
+/**
+ Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
+ value, followed a bitwise OR with another 8-bit value.
+
+ Reads the 8-bit PCI configuration register specified by Address, performs a
+ bitwise AND between the read result and the value specified by AndData,
+ performs a bitwise OR between the result of the AND operation and
+ the value specified by OrData, and writes the result to the 8-bit PCI
+ configuration register specified by Address. The value written to the PCI
+ configuration register is returned. This function must guarantee that all PCI
+ read and write operations are serialized.
+
+ If Address > 0x0FFFFFFF, then ASSERT().
+ If the register specified by Address >= 0x100, then ASSERT().
+
+ @param Address Address that encodes the PCI Bus, Device, Function and
+ Register.
+ @param AndData The value to AND with the PCI configuration register.
+ @param OrData The value to OR with the result of the AND operation.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+PciCf8AndThenOr8 (
+ IN UINTN Address,
+ IN UINT8 AndData,
+ IN UINT8 OrData
+ );
+
+/**
+ Reads a bit field of a PCI configuration register.
+
+ Reads the bit field in an 8-bit PCI configuration register. The bit field is
+ specified by the StartBit and the EndBit. The value of the bit field is
+ returned.
+
+ If Address > 0x0FFFFFFF, then ASSERT().
+ If the register specified by Address >= 0x100, then ASSERT().
+ If StartBit is greater than 7, then ASSERT().
+ If EndBit is greater than 7, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+
+ @param Address PCI configuration register to read.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..7.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..7.
+
+ @return The value of the bit field read from the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+PciCf8BitFieldRead8 (
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit
+ );
+
+/**
+ Writes a bit field to a PCI configuration register.
+
+ Writes Value to the bit field of the PCI configuration register. The bit
+ field is specified by the StartBit and the EndBit. All other bits in the
+ destination PCI configuration register are preserved. The new value of the
+ 8-bit register is returned.
+
+ If Address > 0x0FFFFFFF, then ASSERT().
+ If the register specified by Address >= 0x100, then ASSERT().
+ If StartBit is greater than 7, then ASSERT().
+ If EndBit is greater than 7, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Address PCI configuration register to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..7.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..7.
+ @param Value New value of the bit field.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+PciCf8BitFieldWrite8 (
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT8 Value
+ );
+
+/**
+ Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and
+ writes the result back to the bit field in the 8-bit port.
+
+ Reads the 8-bit PCI configuration register specified by Address, performs a
+ bitwise OR between the read result and the value specified by
+ OrData, and writes the result to the 8-bit PCI configuration register
+ specified by Address. The value written to the PCI configuration register is
+ returned. This function must guarantee that all PCI read and write operations
+ are serialized. Extra left bits in OrData are stripped.
+
+ If Address > 0x0FFFFFFF, then ASSERT().
+ If the register specified by Address >= 0x100, then ASSERT().
+ If StartBit is greater than 7, then ASSERT().
+ If EndBit is greater than 7, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Address PCI configuration register to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..7.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..7.
+ @param OrData The value to OR with the PCI configuration register.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+PciCf8BitFieldOr8 (
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT8 OrData
+ );
+
+/**
+ Reads a bit field in an 8-bit PCI configuration register, performs a bitwise
+ AND, and writes the result back to the bit field in the 8-bit register.
+
+ Reads the 8-bit PCI configuration register specified by Address, performs a
+ bitwise AND between the read result and the value specified by AndData, and
+ writes the result to the 8-bit PCI configuration register specified by
+ Address. The value written to the PCI configuration register is returned.
+ This function must guarantee that all PCI read and write operations are
+ serialized. Extra left bits in AndData are stripped.
+
+ If Address > 0x0FFFFFFF, then ASSERT().
+ If the register specified by Address >= 0x100, then ASSERT().
+ If StartBit is greater than 7, then ASSERT().
+ If EndBit is greater than 7, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Address PCI configuration register to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..7.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..7.
+ @param AndData The value to AND with the PCI configuration register.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+PciCf8BitFieldAnd8 (
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT8 AndData
+ );
+
+/**
+ Reads a bit field in an 8-bit port, performs a bitwise AND followed by a
+ bitwise OR, and writes the result back to the bit field in the
+ 8-bit port.
+
+ Reads the 8-bit PCI configuration register specified by Address, performs a
+ bitwise AND followed by a bitwise OR between the read result and
+ the value specified by AndData, and writes the result to the 8-bit PCI
+ configuration register specified by Address. The value written to the PCI
+ configuration register is returned. This function must guarantee that all PCI
+ read and write operations are serialized. Extra left bits in both AndData and
+ OrData are stripped.
+
+ If Address > 0x0FFFFFFF, then ASSERT().
+ If the register specified by Address >= 0x100, then ASSERT().
+ If StartBit is greater than 7, then ASSERT().
+ If EndBit is greater than 7, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Address PCI configuration register to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..7.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..7.
+ @param AndData The value to AND with the PCI configuration register.
+ @param OrData The value to OR with the result of the AND operation.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+PciCf8BitFieldAndThenOr8 (
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT8 AndData,
+ IN UINT8 OrData
+ );
+
+/**
+ Reads a 16-bit PCI configuration register.
+
+ Reads and returns the 16-bit PCI configuration register specified by Address.
+ This function must guarantee that all PCI read and write operations are
+ serialized.
+
+ If Address > 0x0FFFFFFF, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+ If the register specified by Address >= 0x100, then ASSERT().
+
+ @param Address Address that encodes the PCI Bus, Device, Function and
+ Register.
+
+ @return The read value from the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+PciCf8Read16 (
+ IN UINTN Address
+ );
+
+/**
+ Writes a 16-bit PCI configuration register.
+
+ Writes the 16-bit PCI configuration register specified by Address with the
+ value specified by Value. Value is returned. This function must guarantee
+ that all PCI read and write operations are serialized.
+
+ If Address > 0x0FFFFFFF, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+ If the register specified by Address >= 0x100, then ASSERT().
+
+ @param Address Address that encodes the PCI Bus, Device, Function and
+ Register.
+ @param Value The value to write.
+
+ @return The value written to the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+PciCf8Write16 (
+ IN UINTN Address,
+ IN UINT16 Value
+ );
+
+/**
+ Performs a bitwise OR of a 16-bit PCI configuration register with
+ a 16-bit value.
+
+ Reads the 16-bit PCI configuration register specified by Address, performs a
+ bitwise OR between the read result and the value specified by
+ OrData, and writes the result to the 16-bit PCI configuration register
+ specified by Address. The value written to the PCI configuration register is
+ returned. This function must guarantee that all PCI read and write operations
+ are serialized.
+
+ If Address > 0x0FFFFFFF, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+ If the register specified by Address >= 0x100, then ASSERT().
+
+ @param Address Address that encodes the PCI Bus, Device, Function and
+ Register.
+ @param OrData The value to OR with the PCI configuration register.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+PciCf8Or16 (
+ IN UINTN Address,
+ IN UINT16 OrData
+ );
+
+/**
+ Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
+ value.
+
+ Reads the 16-bit PCI configuration register specified by Address, performs a
+ bitwise AND between the read result and the value specified by AndData, and
+ writes the result to the 16-bit PCI configuration register specified by
+ Address. The value written to the PCI configuration register is returned.
+ This function must guarantee that all PCI read and write operations are
+ serialized.
+
+ If Address > 0x0FFFFFFF, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+ If the register specified by Address >= 0x100, then ASSERT().
+
+ @param Address Address that encodes the PCI Bus, Device, Function and
+ Register.
+ @param AndData The value to AND with the PCI configuration register.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+PciCf8And16 (
+ IN UINTN Address,
+ IN UINT16 AndData
+ );
+
+/**
+ Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
+ value, followed a bitwise OR with another 16-bit value.
+
+ Reads the 16-bit PCI configuration register specified by Address, performs a
+ bitwise AND between the read result and the value specified by AndData,
+ performs a bitwise OR between the result of the AND operation and
+ the value specified by OrData, and writes the result to the 16-bit PCI
+ configuration register specified by Address. The value written to the PCI
+ configuration register is returned. This function must guarantee that all PCI
+ read and write operations are serialized.
+
+ If Address > 0x0FFFFFFF, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+ If the register specified by Address >= 0x100, then ASSERT().
+
+ @param Address Address that encodes the PCI Bus, Device, Function and
+ Register.
+ @param AndData The value to AND with the PCI configuration register.
+ @param OrData The value to OR with the result of the AND operation.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+PciCf8AndThenOr16 (
+ IN UINTN Address,
+ IN UINT16 AndData,
+ IN UINT16 OrData
+ );
+
+/**
+ Reads a bit field of a PCI configuration register.
+
+ Reads the bit field in a 16-bit PCI configuration register. The bit field is
+ specified by the StartBit and the EndBit. The value of the bit field is
+ returned.
+
+ If Address > 0x0FFFFFFF, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+ If the register specified by Address >= 0x100, then ASSERT().
+ If StartBit is greater than 15, then ASSERT().
+ If EndBit is greater than 15, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+
+ @param Address PCI configuration register to read.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..15.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..15.
+
+ @return The value of the bit field read from the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+PciCf8BitFieldRead16 (
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit
+ );
+
+/**
+ Writes a bit field to a PCI configuration register.
+
+ Writes Value to the bit field of the PCI configuration register. The bit
+ field is specified by the StartBit and the EndBit. All other bits in the
+ destination PCI configuration register are preserved. The new value of the
+ 16-bit register is returned.
+
+ If Address > 0x0FFFFFFF, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+ If the register specified by Address >= 0x100, then ASSERT().
+ If StartBit is greater than 15, then ASSERT().
+ If EndBit is greater than 15, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Address PCI configuration register to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..15.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..15.
+ @param Value New value of the bit field.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+PciCf8BitFieldWrite16 (
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT16 Value
+ );
+
+/**
+ Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and
+ writes the result back to the bit field in the 16-bit port.
+
+ Reads the 16-bit PCI configuration register specified by Address, performs a
+ bitwise OR between the read result and the value specified by
+ OrData, and writes the result to the 16-bit PCI configuration register
+ specified by Address. The value written to the PCI configuration register is
+ returned. This function must guarantee that all PCI read and write operations
+ are serialized. Extra left bits in OrData are stripped.
+
+ If Address > 0x0FFFFFFF, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+ If the register specified by Address >= 0x100, then ASSERT().
+ If StartBit is greater than 15, then ASSERT().
+ If EndBit is greater than 15, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Address PCI configuration register to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..15.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..15.
+ @param OrData The value to OR with the PCI configuration register.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+PciCf8BitFieldOr16 (
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT16 OrData
+ );
+
+/**
+ Reads a bit field in a 16-bit PCI configuration register, performs a bitwise
+ AND, and writes the result back to the bit field in the 16-bit register.
+
+ Reads the 16-bit PCI configuration register specified by Address, performs a
+ bitwise AND between the read result and the value specified by AndData, and
+ writes the result to the 16-bit PCI configuration register specified by
+ Address. The value written to the PCI configuration register is returned.
+ This function must guarantee that all PCI read and write operations are
+ serialized. Extra left bits in AndData are stripped.
+
+ If Address > 0x0FFFFFFF, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+ If the register specified by Address >= 0x100, then ASSERT().
+ If StartBit is greater than 15, then ASSERT().
+ If EndBit is greater than 15, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Address PCI configuration register to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..15.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..15.
+ @param AndData The value to AND with the PCI configuration register.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+PciCf8BitFieldAnd16 (
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT16 AndData
+ );
+
+/**
+ Reads a bit field in a 16-bit port, performs a bitwise AND followed by a
+ bitwise OR, and writes the result back to the bit field in the
+ 16-bit port.
+
+ Reads the 16-bit PCI configuration register specified by Address, performs a
+ bitwise AND followed by a bitwise OR between the read result and
+ the value specified by AndData, and writes the result to the 16-bit PCI
+ configuration register specified by Address. The value written to the PCI
+ configuration register is returned. This function must guarantee that all PCI
+ read and write operations are serialized. Extra left bits in both AndData and
+ OrData are stripped.
+
+ If Address > 0x0FFFFFFF, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+ If the register specified by Address >= 0x100, then ASSERT().
+ If StartBit is greater than 15, then ASSERT().
+ If EndBit is greater than 15, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Address PCI configuration register to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..15.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..15.
+ @param AndData The value to AND with the PCI configuration register.
+ @param OrData The value to OR with the result of the AND operation.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+PciCf8BitFieldAndThenOr16 (
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT16 AndData,
+ IN UINT16 OrData
+ );
+
+/**
+ Reads a 32-bit PCI configuration register.
+
+ Reads and returns the 32-bit PCI configuration register specified by Address.
+ This function must guarantee that all PCI read and write operations are
+ serialized.
+
+ If Address > 0x0FFFFFFF, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+ If the register specified by Address >= 0x100, then ASSERT().
+
+ @param Address Address that encodes the PCI Bus, Device, Function and
+ Register.
+
+ @return The read value from the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+PciCf8Read32 (
+ IN UINTN Address
+ );
+
+/**
+ Writes a 32-bit PCI configuration register.
+
+ Writes the 32-bit PCI configuration register specified by Address with the
+ value specified by Value. Value is returned. This function must guarantee
+ that all PCI read and write operations are serialized.
+
+ If Address > 0x0FFFFFFF, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+ If the register specified by Address >= 0x100, then ASSERT().
+
+ @param Address Address that encodes the PCI Bus, Device, Function and
+ Register.
+ @param Value The value to write.
+
+ @return The value written to the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+PciCf8Write32 (
+ IN UINTN Address,
+ IN UINT32 Value
+ );
+
+/**
+ Performs a bitwise OR of a 32-bit PCI configuration register with
+ a 32-bit value.
+
+ Reads the 32-bit PCI configuration register specified by Address, performs a
+ bitwise OR between the read result and the value specified by
+ OrData, and writes the result to the 32-bit PCI configuration register
+ specified by Address. The value written to the PCI configuration register is
+ returned. This function must guarantee that all PCI read and write operations
+ are serialized.
+
+ If Address > 0x0FFFFFFF, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+ If the register specified by Address >= 0x100, then ASSERT().
+
+ @param Address Address that encodes the PCI Bus, Device, Function and
+ Register.
+ @param OrData The value to OR with the PCI configuration register.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+PciCf8Or32 (
+ IN UINTN Address,
+ IN UINT32 OrData
+ );
+
+/**
+ Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
+ value.
+
+ Reads the 32-bit PCI configuration register specified by Address, performs a
+ bitwise AND between the read result and the value specified by AndData, and
+ writes the result to the 32-bit PCI configuration register specified by
+ Address. The value written to the PCI configuration register is returned.
+ This function must guarantee that all PCI read and write operations are
+ serialized.
+
+ If Address > 0x0FFFFFFF, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+ If the register specified by Address >= 0x100, then ASSERT().
+
+ @param Address Address that encodes the PCI Bus, Device, Function and
+ Register.
+ @param AndData The value to AND with the PCI configuration register.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+PciCf8And32 (
+ IN UINTN Address,
+ IN UINT32 AndData
+ );
+
+/**
+ Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
+ value, followed a bitwise OR with another 32-bit value.
+
+ Reads the 32-bit PCI configuration register specified by Address, performs a
+ bitwise AND between the read result and the value specified by AndData,
+ performs a bitwise OR between the result of the AND operation and
+ the value specified by OrData, and writes the result to the 32-bit PCI
+ configuration register specified by Address. The value written to the PCI
+ configuration register is returned. This function must guarantee that all PCI
+ read and write operations are serialized.
+
+ If Address > 0x0FFFFFFF, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+ If the register specified by Address >= 0x100, then ASSERT().
+
+ @param Address Address that encodes the PCI Bus, Device, Function and
+ Register.
+ @param AndData The value to AND with the PCI configuration register.
+ @param OrData The value to OR with the result of the AND operation.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+PciCf8AndThenOr32 (
+ IN UINTN Address,
+ IN UINT32 AndData,
+ IN UINT32 OrData
+ );
+
+/**
+ Reads a bit field of a PCI configuration register.
+
+ Reads the bit field in a 32-bit PCI configuration register. The bit field is
+ specified by the StartBit and the EndBit. The value of the bit field is
+ returned.
+
+ If Address > 0x0FFFFFFF, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+ If the register specified by Address >= 0x100, then ASSERT().
+ If StartBit is greater than 31, then ASSERT().
+ If EndBit is greater than 31, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+
+ @param Address PCI configuration register to read.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..31.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..31.
+
+ @return The value of the bit field read from the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+PciCf8BitFieldRead32 (
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit
+ );
+
+/**
+ Writes a bit field to a PCI configuration register.
+
+ Writes Value to the bit field of the PCI configuration register. The bit
+ field is specified by the StartBit and the EndBit. All other bits in the
+ destination PCI configuration register are preserved. The new value of the
+ 32-bit register is returned.
+
+ If Address > 0x0FFFFFFF, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+ If the register specified by Address >= 0x100, then ASSERT().
+ If StartBit is greater than 31, then ASSERT().
+ If EndBit is greater than 31, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Address PCI configuration register to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..31.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..31.
+ @param Value New value of the bit field.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+PciCf8BitFieldWrite32 (
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 Value
+ );
+
+/**
+ Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and
+ writes the result back to the bit field in the 32-bit port.
+
+ Reads the 32-bit PCI configuration register specified by Address, performs a
+ bitwise OR between the read result and the value specified by
+ OrData, and writes the result to the 32-bit PCI configuration register
+ specified by Address. The value written to the PCI configuration register is
+ returned. This function must guarantee that all PCI read and write operations
+ are serialized. Extra left bits in OrData are stripped.
+
+ If Address > 0x0FFFFFFF, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+ If the register specified by Address >= 0x100, then ASSERT().
+ If StartBit is greater than 31, then ASSERT().
+ If EndBit is greater than 31, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Address PCI configuration register to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..31.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..31.
+ @param OrData The value to OR with the PCI configuration register.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+PciCf8BitFieldOr32 (
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 OrData
+ );
+
+/**
+ Reads a bit field in a 32-bit PCI configuration register, performs a bitwise
+ AND, and writes the result back to the bit field in the 32-bit register.
+
+ Reads the 32-bit PCI configuration register specified by Address, performs a
+ bitwise AND between the read result and the value specified by AndData, and
+ writes the result to the 32-bit PCI configuration register specified by
+ Address. The value written to the PCI configuration register is returned.
+ This function must guarantee that all PCI read and write operations are
+ serialized. Extra left bits in AndData are stripped.
+
+ If Address > 0x0FFFFFFF, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+ If the register specified by Address >= 0x100, then ASSERT().
+ If StartBit is greater than 31, then ASSERT().
+ If EndBit is greater than 31, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Address PCI configuration register to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..31.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..31.
+ @param AndData The value to AND with the PCI configuration register.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+PciCf8BitFieldAnd32 (
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 AndData
+ );
+
+/**
+ Reads a bit field in a 32-bit port, performs a bitwise AND followed by a
+ bitwise OR, and writes the result back to the bit field in the
+ 32-bit port.
+
+ Reads the 32-bit PCI configuration register specified by Address, performs a
+ bitwise AND followed by a bitwise OR between the read result and
+ the value specified by AndData, and writes the result to the 32-bit PCI
+ configuration register specified by Address. The value written to the PCI
+ configuration register is returned. This function must guarantee that all PCI
+ read and write operations are serialized. Extra left bits in both AndData and
+ OrData are stripped.
+
+ If Address > 0x0FFFFFFF, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+ If the register specified by Address >= 0x100, then ASSERT().
+ If StartBit is greater than 31, then ASSERT().
+ If EndBit is greater than 31, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Address PCI configuration register to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..31.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..31.
+ @param AndData The value to AND with the PCI configuration register.
+ @param OrData The value to OR with the result of the AND operation.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+PciCf8BitFieldAndThenOr32 (
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 AndData,
+ IN UINT32 OrData
+ );
+
+/**
+ Reads a range of PCI configuration registers into a caller supplied buffer.
+
+ Reads the range of PCI configuration registers specified by StartAddress and
+ Size into the buffer specified by Buffer. This function only allows the PCI
+ configuration registers from a single PCI function to be read. Size is
+ returned. When possible 32-bit PCI configuration read cycles are used to read
+ from StartAddress to StartAddress + Size. Due to alignment restrictions, 8-bit
+ and 16-bit PCI configuration read cycles may be used at the beginning and the
+ end of the range.
+
+ If StartAddress > 0x0FFFFFFF, then ASSERT().
+ If the register specified by StartAddress >= 0x100, then ASSERT().
+ If ((StartAddress & 0xFFF) + Size) > 0x100, then ASSERT().
+ If Size > 0 and Buffer is NULL, then ASSERT().
+
+ @param StartAddress Starting address that encodes the PCI Bus, Device,
+ Function and Register.
+ @param Size Size in bytes of the transfer.
+ @param Buffer Pointer to a buffer receiving the data read.
+
+ @return Size read from StartAddress.
+
+**/
+UINTN
+EFIAPI
+PciCf8ReadBuffer (
+ IN UINTN StartAddress,
+ IN UINTN Size,
+ OUT VOID *Buffer
+ );
+
+/**
+ Copies the data in a caller supplied buffer to a specified range of PCI
+ configuration space.
+
+ Writes the range of PCI configuration registers specified by StartAddress and
+ Size from the buffer specified by Buffer. This function only allows the PCI
+ configuration registers from a single PCI function to be written. Size is
+ returned. When possible 32-bit PCI configuration write cycles are used to
+ write from StartAddress to StartAddress + Size. Due to alignment restrictions,
+ 8-bit and 16-bit PCI configuration write cycles may be used at the beginning
+ and the end of the range.
+
+ If StartAddress > 0x0FFFFFFF, then ASSERT().
+ If the register specified by StartAddress >= 0x100, then ASSERT().
+ If ((StartAddress & 0xFFF) + Size) > 0x100, then ASSERT().
+ If Size > 0 and Buffer is NULL, then ASSERT().
+
+ @param StartAddress Starting address that encodes the PCI Bus, Device,
+ Function and Register.
+ @param Size Size in bytes of the transfer.
+ @param Buffer Pointer to a buffer containing the data to write.
+
+ @return Size written to StartAddress.
+
+**/
+UINTN
+EFIAPI
+PciCf8WriteBuffer (
+ IN UINTN StartAddress,
+ IN UINTN Size,
+ IN VOID *Buffer
+ );
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/PciExpressLib.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/PciExpressLib.h
new file mode 100644
index 0000000000..e30f40cb3b
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/PciExpressLib.h
@@ -0,0 +1,1057 @@
+/** @file
+ Provides services to access PCI Configuration Space using the MMIO PCI Express window.
+
+ This library is identical to the PCI Library, except the access method for performing PCI
+ configuration cycles must be through the PCI Express MMIO window whose base address
+ is defined by PcdPciExpressBaseAddress and size defined by PcdPciExpressBaseSize.
+
+
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __PCI_EXPRESS_LIB_H__
+#define __PCI_EXPRESS_LIB_H__
+
+#include
+
+/**
+ Macro that converts PCI Bus, PCI Device, PCI Function and PCI Register to an
+ address that can be passed to the PCI Library functions.
+
+ Computes an address that is compatible with the PCI Library functions. The
+ unused upper bits of Bus, Device, Function and Register are stripped prior to
+ the generation of the address.
+
+ @param Bus PCI Bus number. Range 0..255.
+ @param Device PCI Device number. Range 0..31.
+ @param Function PCI Function number. Range 0..7.
+ @param Register PCI Register number. Range 0..4095.
+
+ @return The encode PCI address.
+
+**/
+#define PCI_EXPRESS_LIB_ADDRESS(Bus, Device, Function, Offset) PCI_ECAM_ADDRESS ((Bus), (Device), (Function), (Offset))
+
+/**
+ Registers a PCI device so PCI configuration registers may be accessed after
+ SetVirtualAddressMap().
+
+ Registers the PCI device specified by Address so all the PCI configuration
+ registers associated with that PCI device may be accessed after SetVirtualAddressMap()
+ is called.
+
+ If Address > 0x0FFFFFFF, then ASSERT().
+
+ @param Address Address that encodes the PCI Bus, Device, Function and
+ Register.
+
+ @retval RETURN_SUCCESS The PCI device was registered for runtime access.
+ @retval RETURN_UNSUPPORTED An attempt was made to call this function
+ after ExitBootServices().
+ @retval RETURN_UNSUPPORTED The resources required to access the PCI device
+ at runtime could not be mapped.
+ @retval RETURN_OUT_OF_RESOURCES There are not enough resources available to
+ complete the registration.
+
+**/
+RETURN_STATUS
+EFIAPI
+PciExpressRegisterForRuntimeAccess (
+ IN UINTN Address
+ );
+
+/**
+ Reads an 8-bit PCI configuration register.
+
+ Reads and returns the 8-bit PCI configuration register specified by Address.
+ This function must guarantee that all PCI read and write operations are
+ serialized.
+
+ If Address > 0x0FFFFFFF, then ASSERT().
+
+ @param Address Address that encodes the PCI Bus, Device, Function and
+ Register.
+
+ @return The read value from the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+PciExpressRead8 (
+ IN UINTN Address
+ );
+
+/**
+ Writes an 8-bit PCI configuration register.
+
+ Writes the 8-bit PCI configuration register specified by Address with the
+ value specified by Value. Value is returned. This function must guarantee
+ that all PCI read and write operations are serialized.
+
+ If Address > 0x0FFFFFFF, then ASSERT().
+
+ @param Address Address that encodes the PCI Bus, Device, Function and
+ Register.
+ @param Value The value to write.
+
+ @return The value written to the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+PciExpressWrite8 (
+ IN UINTN Address,
+ IN UINT8 Value
+ );
+
+/**
+ Performs a bitwise OR of an 8-bit PCI configuration register with
+ an 8-bit value.
+
+ Reads the 8-bit PCI configuration register specified by Address, performs a
+ bitwise OR between the read result and the value specified by
+ OrData, and writes the result to the 8-bit PCI configuration register
+ specified by Address. The value written to the PCI configuration register is
+ returned. This function must guarantee that all PCI read and write operations
+ are serialized.
+
+ If Address > 0x0FFFFFFF, then ASSERT().
+
+ @param Address Address that encodes the PCI Bus, Device, Function and
+ Register.
+ @param OrData The value to OR with the PCI configuration register.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+PciExpressOr8 (
+ IN UINTN Address,
+ IN UINT8 OrData
+ );
+
+/**
+ Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
+ value.
+
+ Reads the 8-bit PCI configuration register specified by Address, performs a
+ bitwise AND between the read result and the value specified by AndData, and
+ writes the result to the 8-bit PCI configuration register specified by
+ Address. The value written to the PCI configuration register is returned.
+ This function must guarantee that all PCI read and write operations are
+ serialized.
+
+ If Address > 0x0FFFFFFF, then ASSERT().
+
+ @param Address Address that encodes the PCI Bus, Device, Function and
+ Register.
+ @param AndData The value to AND with the PCI configuration register.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+PciExpressAnd8 (
+ IN UINTN Address,
+ IN UINT8 AndData
+ );
+
+/**
+ Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
+ value, followed a bitwise OR with another 8-bit value.
+
+ Reads the 8-bit PCI configuration register specified by Address, performs a
+ bitwise AND between the read result and the value specified by AndData,
+ performs a bitwise OR between the result of the AND operation and
+ the value specified by OrData, and writes the result to the 8-bit PCI
+ configuration register specified by Address. The value written to the PCI
+ configuration register is returned. This function must guarantee that all PCI
+ read and write operations are serialized.
+
+ If Address > 0x0FFFFFFF, then ASSERT().
+
+ @param Address Address that encodes the PCI Bus, Device, Function and
+ Register.
+ @param AndData The value to AND with the PCI configuration register.
+ @param OrData The value to OR with the result of the AND operation.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+PciExpressAndThenOr8 (
+ IN UINTN Address,
+ IN UINT8 AndData,
+ IN UINT8 OrData
+ );
+
+/**
+ Reads a bit field of a PCI configuration register.
+
+ Reads the bit field in an 8-bit PCI configuration register. The bit field is
+ specified by the StartBit and the EndBit. The value of the bit field is
+ returned.
+
+ If Address > 0x0FFFFFFF, then ASSERT().
+ If StartBit is greater than 7, then ASSERT().
+ If EndBit is greater than 7, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+
+ @param Address PCI configuration register to read.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..7.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..7.
+
+ @return The value of the bit field read from the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+PciExpressBitFieldRead8 (
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit
+ );
+
+/**
+ Writes a bit field to a PCI configuration register.
+
+ Writes Value to the bit field of the PCI configuration register. The bit
+ field is specified by the StartBit and the EndBit. All other bits in the
+ destination PCI configuration register are preserved. The new value of the
+ 8-bit register is returned.
+
+ If Address > 0x0FFFFFFF, then ASSERT().
+ If StartBit is greater than 7, then ASSERT().
+ If EndBit is greater than 7, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Address PCI configuration register to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..7.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..7.
+ @param Value New value of the bit field.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+PciExpressBitFieldWrite8 (
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT8 Value
+ );
+
+/**
+ Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and
+ writes the result back to the bit field in the 8-bit port.
+
+ Reads the 8-bit PCI configuration register specified by Address, performs a
+ bitwise OR between the read result and the value specified by
+ OrData, and writes the result to the 8-bit PCI configuration register
+ specified by Address. The value written to the PCI configuration register is
+ returned. This function must guarantee that all PCI read and write operations
+ are serialized. Extra left bits in OrData are stripped.
+
+ If Address > 0x0FFFFFFF, then ASSERT().
+ If StartBit is greater than 7, then ASSERT().
+ If EndBit is greater than 7, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Address PCI configuration register to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..7.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..7.
+ @param OrData The value to OR with the PCI configuration register.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+PciExpressBitFieldOr8 (
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT8 OrData
+ );
+
+/**
+ Reads a bit field in an 8-bit PCI configuration register, performs a bitwise
+ AND, and writes the result back to the bit field in the 8-bit register.
+
+ Reads the 8-bit PCI configuration register specified by Address, performs a
+ bitwise AND between the read result and the value specified by AndData, and
+ writes the result to the 8-bit PCI configuration register specified by
+ Address. The value written to the PCI configuration register is returned.
+ This function must guarantee that all PCI read and write operations are
+ serialized. Extra left bits in AndData are stripped.
+
+ If Address > 0x0FFFFFFF, then ASSERT().
+ If StartBit is greater than 7, then ASSERT().
+ If EndBit is greater than 7, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Address PCI configuration register to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..7.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..7.
+ @param AndData The value to AND with the PCI configuration register.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+PciExpressBitFieldAnd8 (
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT8 AndData
+ );
+
+/**
+ Reads a bit field in an 8-bit port, performs a bitwise AND followed by a
+ bitwise OR, and writes the result back to the bit field in the
+ 8-bit port.
+
+ Reads the 8-bit PCI configuration register specified by Address, performs a
+ bitwise AND followed by a bitwise OR between the read result and
+ the value specified by AndData, and writes the result to the 8-bit PCI
+ configuration register specified by Address. The value written to the PCI
+ configuration register is returned. This function must guarantee that all PCI
+ read and write operations are serialized. Extra left bits in both AndData and
+ OrData are stripped.
+
+ If Address > 0x0FFFFFFF, then ASSERT().
+ If StartBit is greater than 7, then ASSERT().
+ If EndBit is greater than 7, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Address PCI configuration register to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..7.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..7.
+ @param AndData The value to AND with the PCI configuration register.
+ @param OrData The value to OR with the result of the AND operation.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+PciExpressBitFieldAndThenOr8 (
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT8 AndData,
+ IN UINT8 OrData
+ );
+
+/**
+ Reads a 16-bit PCI configuration register.
+
+ Reads and returns the 16-bit PCI configuration register specified by Address.
+ This function must guarantee that all PCI read and write operations are
+ serialized.
+
+ If Address > 0x0FFFFFFF, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+
+ @param Address Address that encodes the PCI Bus, Device, Function and
+ Register.
+
+ @return The read value from the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+PciExpressRead16 (
+ IN UINTN Address
+ );
+
+/**
+ Writes a 16-bit PCI configuration register.
+
+ Writes the 16-bit PCI configuration register specified by Address with the
+ value specified by Value. Value is returned. This function must guarantee
+ that all PCI read and write operations are serialized.
+
+ If Address > 0x0FFFFFFF, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+
+ @param Address Address that encodes the PCI Bus, Device, Function and
+ Register.
+ @param Value The value to write.
+
+ @return The value written to the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+PciExpressWrite16 (
+ IN UINTN Address,
+ IN UINT16 Value
+ );
+
+/**
+ Performs a bitwise OR of a 16-bit PCI configuration register with
+ a 16-bit value.
+
+ Reads the 16-bit PCI configuration register specified by Address, performs a
+ bitwise OR between the read result and the value specified by
+ OrData, and writes the result to the 16-bit PCI configuration register
+ specified by Address. The value written to the PCI configuration register is
+ returned. This function must guarantee that all PCI read and write operations
+ are serialized.
+
+ If Address > 0x0FFFFFFF, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+
+ @param Address Address that encodes the PCI Bus, Device, Function and
+ Register.
+ @param OrData The value to OR with the PCI configuration register.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+PciExpressOr16 (
+ IN UINTN Address,
+ IN UINT16 OrData
+ );
+
+/**
+ Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
+ value.
+
+ Reads the 16-bit PCI configuration register specified by Address, performs a
+ bitwise AND between the read result and the value specified by AndData, and
+ writes the result to the 16-bit PCI configuration register specified by
+ Address. The value written to the PCI configuration register is returned.
+ This function must guarantee that all PCI read and write operations are
+ serialized.
+
+ If Address > 0x0FFFFFFF, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+
+ @param Address Address that encodes the PCI Bus, Device, Function and
+ Register.
+ @param AndData The value to AND with the PCI configuration register.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+PciExpressAnd16 (
+ IN UINTN Address,
+ IN UINT16 AndData
+ );
+
+/**
+ Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
+ value, followed a bitwise OR with another 16-bit value.
+
+ Reads the 16-bit PCI configuration register specified by Address, performs a
+ bitwise AND between the read result and the value specified by AndData,
+ performs a bitwise OR between the result of the AND operation and
+ the value specified by OrData, and writes the result to the 16-bit PCI
+ configuration register specified by Address. The value written to the PCI
+ configuration register is returned. This function must guarantee that all PCI
+ read and write operations are serialized.
+
+ If Address > 0x0FFFFFFF, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+
+ @param Address Address that encodes the PCI Bus, Device, Function and
+ Register.
+ @param AndData The value to AND with the PCI configuration register.
+ @param OrData The value to OR with the result of the AND operation.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+PciExpressAndThenOr16 (
+ IN UINTN Address,
+ IN UINT16 AndData,
+ IN UINT16 OrData
+ );
+
+/**
+ Reads a bit field of a PCI configuration register.
+
+ Reads the bit field in a 16-bit PCI configuration register. The bit field is
+ specified by the StartBit and the EndBit. The value of the bit field is
+ returned.
+
+ If Address > 0x0FFFFFFF, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+ If StartBit is greater than 15, then ASSERT().
+ If EndBit is greater than 15, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+
+ @param Address PCI configuration register to read.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..15.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..15.
+
+ @return The value of the bit field read from the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+PciExpressBitFieldRead16 (
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit
+ );
+
+/**
+ Writes a bit field to a PCI configuration register.
+
+ Writes Value to the bit field of the PCI configuration register. The bit
+ field is specified by the StartBit and the EndBit. All other bits in the
+ destination PCI configuration register are preserved. The new value of the
+ 16-bit register is returned.
+
+ If Address > 0x0FFFFFFF, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+ If StartBit is greater than 15, then ASSERT().
+ If EndBit is greater than 15, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Address PCI configuration register to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..15.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..15.
+ @param Value New value of the bit field.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+PciExpressBitFieldWrite16 (
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT16 Value
+ );
+
+/**
+ Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and
+ writes the result back to the bit field in the 16-bit port.
+
+ Reads the 16-bit PCI configuration register specified by Address, performs a
+ bitwise OR between the read result and the value specified by
+ OrData, and writes the result to the 16-bit PCI configuration register
+ specified by Address. The value written to the PCI configuration register is
+ returned. This function must guarantee that all PCI read and write operations
+ are serialized. Extra left bits in OrData are stripped.
+
+ If Address > 0x0FFFFFFF, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+ If StartBit is greater than 15, then ASSERT().
+ If EndBit is greater than 15, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Address PCI configuration register to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..15.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..15.
+ @param OrData The value to OR with the PCI configuration register.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+PciExpressBitFieldOr16 (
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT16 OrData
+ );
+
+/**
+ Reads a bit field in a 16-bit PCI configuration register, performs a bitwise
+ AND, and writes the result back to the bit field in the 16-bit register.
+
+ Reads the 16-bit PCI configuration register specified by Address, performs a
+ bitwise AND between the read result and the value specified by AndData, and
+ writes the result to the 16-bit PCI configuration register specified by
+ Address. The value written to the PCI configuration register is returned.
+ This function must guarantee that all PCI read and write operations are
+ serialized. Extra left bits in AndData are stripped.
+
+ If Address > 0x0FFFFFFF, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+ If StartBit is greater than 15, then ASSERT().
+ If EndBit is greater than 15, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Address PCI configuration register to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..15.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..15.
+ @param AndData The value to AND with the PCI configuration register.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+PciExpressBitFieldAnd16 (
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT16 AndData
+ );
+
+/**
+ Reads a bit field in a 16-bit port, performs a bitwise AND followed by a
+ bitwise OR, and writes the result back to the bit field in the
+ 16-bit port.
+
+ Reads the 16-bit PCI configuration register specified by Address, performs a
+ bitwise AND followed by a bitwise OR between the read result and
+ the value specified by AndData, and writes the result to the 16-bit PCI
+ configuration register specified by Address. The value written to the PCI
+ configuration register is returned. This function must guarantee that all PCI
+ read and write operations are serialized. Extra left bits in both AndData and
+ OrData are stripped.
+
+ If Address > 0x0FFFFFFF, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+ If StartBit is greater than 15, then ASSERT().
+ If EndBit is greater than 15, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Address PCI configuration register to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..15.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..15.
+ @param AndData The value to AND with the PCI configuration register.
+ @param OrData The value to OR with the result of the AND operation.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+PciExpressBitFieldAndThenOr16 (
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT16 AndData,
+ IN UINT16 OrData
+ );
+
+/**
+ Reads a 32-bit PCI configuration register.
+
+ Reads and returns the 32-bit PCI configuration register specified by Address.
+ This function must guarantee that all PCI read and write operations are
+ serialized.
+
+ If Address > 0x0FFFFFFF, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+
+ @param Address Address that encodes the PCI Bus, Device, Function and
+ Register.
+
+ @return The read value from the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+PciExpressRead32 (
+ IN UINTN Address
+ );
+
+/**
+ Writes a 32-bit PCI configuration register.
+
+ Writes the 32-bit PCI configuration register specified by Address with the
+ value specified by Value. Value is returned. This function must guarantee
+ that all PCI read and write operations are serialized.
+
+ If Address > 0x0FFFFFFF, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+
+ @param Address Address that encodes the PCI Bus, Device, Function and
+ Register.
+ @param Value The value to write.
+
+ @return The value written to the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+PciExpressWrite32 (
+ IN UINTN Address,
+ IN UINT32 Value
+ );
+
+/**
+ Performs a bitwise OR of a 32-bit PCI configuration register with
+ a 32-bit value.
+
+ Reads the 32-bit PCI configuration register specified by Address, performs a
+ bitwise OR between the read result and the value specified by
+ OrData, and writes the result to the 32-bit PCI configuration register
+ specified by Address. The value written to the PCI configuration register is
+ returned. This function must guarantee that all PCI read and write operations
+ are serialized.
+
+ If Address > 0x0FFFFFFF, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+
+ @param Address Address that encodes the PCI Bus, Device, Function and
+ Register.
+ @param OrData The value to OR with the PCI configuration register.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+PciExpressOr32 (
+ IN UINTN Address,
+ IN UINT32 OrData
+ );
+
+/**
+ Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
+ value.
+
+ Reads the 32-bit PCI configuration register specified by Address, performs a
+ bitwise AND between the read result and the value specified by AndData, and
+ writes the result to the 32-bit PCI configuration register specified by
+ Address. The value written to the PCI configuration register is returned.
+ This function must guarantee that all PCI read and write operations are
+ serialized.
+
+ If Address > 0x0FFFFFFF, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+
+ @param Address Address that encodes the PCI Bus, Device, Function and
+ Register.
+ @param AndData The value to AND with the PCI configuration register.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+PciExpressAnd32 (
+ IN UINTN Address,
+ IN UINT32 AndData
+ );
+
+/**
+ Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
+ value, followed a bitwise OR with another 32-bit value.
+
+ Reads the 32-bit PCI configuration register specified by Address, performs a
+ bitwise AND between the read result and the value specified by AndData,
+ performs a bitwise OR between the result of the AND operation and
+ the value specified by OrData, and writes the result to the 32-bit PCI
+ configuration register specified by Address. The value written to the PCI
+ configuration register is returned. This function must guarantee that all PCI
+ read and write operations are serialized.
+
+ If Address > 0x0FFFFFFF, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+
+ @param Address Address that encodes the PCI Bus, Device, Function and
+ Register.
+ @param AndData The value to AND with the PCI configuration register.
+ @param OrData The value to OR with the result of the AND operation.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+PciExpressAndThenOr32 (
+ IN UINTN Address,
+ IN UINT32 AndData,
+ IN UINT32 OrData
+ );
+
+/**
+ Reads a bit field of a PCI configuration register.
+
+ Reads the bit field in a 32-bit PCI configuration register. The bit field is
+ specified by the StartBit and the EndBit. The value of the bit field is
+ returned.
+
+ If Address > 0x0FFFFFFF, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+ If StartBit is greater than 31, then ASSERT().
+ If EndBit is greater than 31, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+
+ @param Address PCI configuration register to read.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..31.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..31.
+
+ @return The value of the bit field read from the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+PciExpressBitFieldRead32 (
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit
+ );
+
+/**
+ Writes a bit field to a PCI configuration register.
+
+ Writes Value to the bit field of the PCI configuration register. The bit
+ field is specified by the StartBit and the EndBit. All other bits in the
+ destination PCI configuration register are preserved. The new value of the
+ 32-bit register is returned.
+
+ If Address > 0x0FFFFFFF, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+ If StartBit is greater than 31, then ASSERT().
+ If EndBit is greater than 31, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Address PCI configuration register to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..31.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..31.
+ @param Value New value of the bit field.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+PciExpressBitFieldWrite32 (
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 Value
+ );
+
+/**
+ Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and
+ writes the result back to the bit field in the 32-bit port.
+
+ Reads the 32-bit PCI configuration register specified by Address, performs a
+ bitwise OR between the read result and the value specified by
+ OrData, and writes the result to the 32-bit PCI configuration register
+ specified by Address. The value written to the PCI configuration register is
+ returned. This function must guarantee that all PCI read and write operations
+ are serialized. Extra left bits in OrData are stripped.
+
+ If Address > 0x0FFFFFFF, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+ If StartBit is greater than 31, then ASSERT().
+ If EndBit is greater than 31, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Address PCI configuration register to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..31.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..31.
+ @param OrData The value to OR with the PCI configuration register.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+PciExpressBitFieldOr32 (
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 OrData
+ );
+
+/**
+ Reads a bit field in a 32-bit PCI configuration register, performs a bitwise
+ AND, and writes the result back to the bit field in the 32-bit register.
+
+ Reads the 32-bit PCI configuration register specified by Address, performs a
+ bitwise AND between the read result and the value specified by AndData, and
+ writes the result to the 32-bit PCI configuration register specified by
+ Address. The value written to the PCI configuration register is returned.
+ This function must guarantee that all PCI read and write operations are
+ serialized. Extra left bits in AndData are stripped.
+
+ If Address > 0x0FFFFFFF, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+ If StartBit is greater than 31, then ASSERT().
+ If EndBit is greater than 31, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Address PCI configuration register to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..31.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..31.
+ @param AndData The value to AND with the PCI configuration register.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+PciExpressBitFieldAnd32 (
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 AndData
+ );
+
+/**
+ Reads a bit field in a 32-bit port, performs a bitwise AND followed by a
+ bitwise OR, and writes the result back to the bit field in the
+ 32-bit port.
+
+ Reads the 32-bit PCI configuration register specified by Address, performs a
+ bitwise AND followed by a bitwise OR between the read result and
+ the value specified by AndData, and writes the result to the 32-bit PCI
+ configuration register specified by Address. The value written to the PCI
+ configuration register is returned. This function must guarantee that all PCI
+ read and write operations are serialized. Extra left bits in both AndData and
+ OrData are stripped.
+
+ If Address > 0x0FFFFFFF, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+ If StartBit is greater than 31, then ASSERT().
+ If EndBit is greater than 31, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Address PCI configuration register to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..31.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..31.
+ @param AndData The value to AND with the PCI configuration register.
+ @param OrData The value to OR with the result of the AND operation.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+PciExpressBitFieldAndThenOr32 (
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 AndData,
+ IN UINT32 OrData
+ );
+
+/**
+ Reads a range of PCI configuration registers into a caller supplied buffer.
+
+ Reads the range of PCI configuration registers specified by StartAddress and
+ Size into the buffer specified by Buffer. This function only allows the PCI
+ configuration registers from a single PCI function to be read. Size is
+ returned. When possible 32-bit PCI configuration read cycles are used to read
+ from StartAddress to StartAddress + Size. Due to alignment restrictions, 8-bit
+ and 16-bit PCI configuration read cycles may be used at the beginning and the
+ end of the range.
+
+ If StartAddress > 0x0FFFFFFF, then ASSERT().
+ If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
+ If Size > 0 and Buffer is NULL, then ASSERT().
+
+ @param StartAddress Starting address that encodes the PCI Bus, Device,
+ Function and Register.
+ @param Size Size in bytes of the transfer.
+ @param Buffer Pointer to a buffer receiving the data read.
+
+ @return Size read data from StartAddress.
+
+**/
+UINTN
+EFIAPI
+PciExpressReadBuffer (
+ IN UINTN StartAddress,
+ IN UINTN Size,
+ OUT VOID *Buffer
+ );
+
+/**
+ Copies the data in a caller supplied buffer to a specified range of PCI
+ configuration space.
+
+ Writes the range of PCI configuration registers specified by StartAddress and
+ Size from the buffer specified by Buffer. This function only allows the PCI
+ configuration registers from a single PCI function to be written. Size is
+ returned. When possible 32-bit PCI configuration write cycles are used to
+ write from StartAddress to StartAddress + Size. Due to alignment restrictions,
+ 8-bit and 16-bit PCI configuration write cycles may be used at the beginning
+ and the end of the range.
+
+ If StartAddress > 0x0FFFFFFF, then ASSERT().
+ If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
+ If Size > 0 and Buffer is NULL, then ASSERT().
+
+ @param StartAddress Starting address that encodes the PCI Bus, Device,
+ Function and Register.
+ @param Size Size in bytes of the transfer.
+ @param Buffer Pointer to a buffer containing the data to write.
+
+ @return Size written to StartAddress.
+
+**/
+UINTN
+EFIAPI
+PciExpressWriteBuffer (
+ IN UINTN StartAddress,
+ IN UINTN Size,
+ IN VOID *Buffer
+ );
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/PciLib.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/PciLib.h
new file mode 100644
index 0000000000..5ced196da1
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/PciLib.h
@@ -0,0 +1,1056 @@
+/** @file
+ Provides services to access PCI Configuration Space.
+
+ These functions perform PCI configuration cycles using the default PCI configuration
+ access method. This may use I/O ports 0xCF8 and 0xCFC to perform PCI configuration accesses,
+ or it may use MMIO registers relative to the PcdPciExpressBaseAddress, or it may use some
+ alternate access method. Modules will typically use the PCI Library for its PCI configuration
+ accesses. However, if a module requires a mix of PCI access methods, the PCI CF8 Library or
+ PCI Express Library may be used in conjunction with the PCI Library. The functionality of
+ these three libraries is identical. The PCI CF8 Library and PCI Express Library simply use
+ explicit access methods.
+
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __PCI_LIB_H__
+#define __PCI_LIB_H__
+
+/**
+ Macro that converts PCI Bus, PCI Device, PCI Function and PCI Register to an
+ address that can be passed to the PCI Library functions.
+
+ @param Bus PCI Bus number. Range 0..255.
+ @param Device PCI Device number. Range 0..31.
+ @param Function PCI Function number. Range 0..7.
+ @param Register PCI Register number. Range 0..255 for PCI. Range 0..4095
+ for PCI Express.
+
+ @return The encoded PCI address.
+
+**/
+#define PCI_LIB_ADDRESS(Bus, Device, Function, Register) \
+ (((Register) & 0xfff) | (((Function) & 0x07) << 12) | (((Device) & 0x1f) << 15) | (((Bus) & 0xff) << 20))
+
+/**
+ Registers a PCI device so PCI configuration registers may be accessed after
+ SetVirtualAddressMap().
+
+ Registers the PCI device specified by Address so all the PCI configuration registers
+ associated with that PCI device may be accessed after SetVirtualAddressMap() is called.
+
+ If Address > 0x0FFFFFFF, then ASSERT().
+
+ @param Address Address that encodes the PCI Bus, Device, Function and
+ Register.
+
+ @retval RETURN_SUCCESS The PCI device was registered for runtime access.
+ @retval RETURN_UNSUPPORTED An attempt was made to call this function
+ after ExitBootServices().
+ @retval RETURN_UNSUPPORTED The resources required to access the PCI device
+ at runtime could not be mapped.
+ @retval RETURN_OUT_OF_RESOURCES There are not enough resources available to
+ complete the registration.
+
+**/
+RETURN_STATUS
+EFIAPI
+PciRegisterForRuntimeAccess (
+ IN UINTN Address
+ );
+
+/**
+ Reads an 8-bit PCI configuration register.
+
+ Reads and returns the 8-bit PCI configuration register specified by Address.
+ This function must guarantee that all PCI read and write operations are
+ serialized.
+
+ If Address > 0x0FFFFFFF, then ASSERT().
+
+ @param Address Address that encodes the PCI Bus, Device, Function and
+ Register.
+
+ @return The read value from the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+PciRead8 (
+ IN UINTN Address
+ );
+
+/**
+ Writes an 8-bit PCI configuration register.
+
+ Writes the 8-bit PCI configuration register specified by Address with the
+ value specified by Value. Value is returned. This function must guarantee
+ that all PCI read and write operations are serialized.
+
+ If Address > 0x0FFFFFFF, then ASSERT().
+
+ @param Address Address that encodes the PCI Bus, Device, Function and
+ Register.
+ @param Value The value to write.
+
+ @return The value written to the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+PciWrite8 (
+ IN UINTN Address,
+ IN UINT8 Value
+ );
+
+/**
+ Performs a bitwise OR of an 8-bit PCI configuration register with
+ an 8-bit value.
+
+ Reads the 8-bit PCI configuration register specified by Address, performs a
+ bitwise OR between the read result and the value specified by
+ OrData, and writes the result to the 8-bit PCI configuration register
+ specified by Address. The value written to the PCI configuration register is
+ returned. This function must guarantee that all PCI read and write operations
+ are serialized.
+
+ If Address > 0x0FFFFFFF, then ASSERT().
+
+ @param Address Address that encodes the PCI Bus, Device, Function and
+ Register.
+ @param OrData The value to OR with the PCI configuration register.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+PciOr8 (
+ IN UINTN Address,
+ IN UINT8 OrData
+ );
+
+/**
+ Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
+ value.
+
+ Reads the 8-bit PCI configuration register specified by Address, performs a
+ bitwise AND between the read result and the value specified by AndData, and
+ writes the result to the 8-bit PCI configuration register specified by
+ Address. The value written to the PCI configuration register is returned.
+ This function must guarantee that all PCI read and write operations are
+ serialized.
+
+ If Address > 0x0FFFFFFF, then ASSERT().
+
+ @param Address Address that encodes the PCI Bus, Device, Function and
+ Register.
+ @param AndData The value to AND with the PCI configuration register.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+PciAnd8 (
+ IN UINTN Address,
+ IN UINT8 AndData
+ );
+
+/**
+ Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
+ value, followed by a bitwise OR with another 8-bit value.
+
+ Reads the 8-bit PCI configuration register specified by Address, performs a
+ bitwise AND between the read result and the value specified by AndData,
+ performs a bitwise OR between the result of the AND operation and
+ the value specified by OrData, and writes the result to the 8-bit PCI
+ configuration register specified by Address. The value written to the PCI
+ configuration register is returned. This function must guarantee that all PCI
+ read and write operations are serialized.
+
+ If Address > 0x0FFFFFFF, then ASSERT().
+
+ @param Address Address that encodes the PCI Bus, Device, Function and
+ Register.
+ @param AndData The value to AND with the PCI configuration register.
+ @param OrData The value to OR with the result of the AND operation.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+PciAndThenOr8 (
+ IN UINTN Address,
+ IN UINT8 AndData,
+ IN UINT8 OrData
+ );
+
+/**
+ Reads a bit field of a PCI configuration register.
+
+ Reads the bit field in an 8-bit PCI configuration register. The bit field is
+ specified by the StartBit and the EndBit. The value of the bit field is
+ returned.
+
+ If Address > 0x0FFFFFFF, then ASSERT().
+ If StartBit is greater than 7, then ASSERT().
+ If EndBit is greater than 7, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+
+ @param Address PCI configuration register to read.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..7.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..7.
+
+ @return The value of the bit field read from the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+PciBitFieldRead8 (
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit
+ );
+
+/**
+ Writes a bit field to a PCI configuration register.
+
+ Writes Value to the bit field of the PCI configuration register. The bit
+ field is specified by the StartBit and the EndBit. All other bits in the
+ destination PCI configuration register are preserved. The new value of the
+ 8-bit register is returned.
+
+ If Address > 0x0FFFFFFF, then ASSERT().
+ If StartBit is greater than 7, then ASSERT().
+ If EndBit is greater than 7, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Address PCI configuration register to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..7.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..7.
+ @param Value New value of the bit field.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+PciBitFieldWrite8 (
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT8 Value
+ );
+
+/**
+ Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and
+ writes the result back to the bit field in the 8-bit port.
+
+ Reads the 8-bit PCI configuration register specified by Address, performs a
+ bitwise OR between the read result and the value specified by
+ OrData, and writes the result to the 8-bit PCI configuration register
+ specified by Address. The value written to the PCI configuration register is
+ returned. This function must guarantee that all PCI read and write operations
+ are serialized. Extra left bits in OrData are stripped.
+
+ If Address > 0x0FFFFFFF, then ASSERT().
+ If StartBit is greater than 7, then ASSERT().
+ If EndBit is greater than 7, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Address PCI configuration register to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..7.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..7.
+ @param OrData The value to OR with the PCI configuration register.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+PciBitFieldOr8 (
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT8 OrData
+ );
+
+/**
+ Reads a bit field in an 8-bit PCI configuration register, performs a bitwise
+ AND, and writes the result back to the bit field in the 8-bit register.
+
+ Reads the 8-bit PCI configuration register specified by Address, performs a
+ bitwise AND between the read result and the value specified by AndData, and
+ writes the result to the 8-bit PCI configuration register specified by
+ Address. The value written to the PCI configuration register is returned.
+ This function must guarantee that all PCI read and write operations are
+ serialized. Extra left bits in AndData are stripped.
+
+ If Address > 0x0FFFFFFF, then ASSERT().
+ If StartBit is greater than 7, then ASSERT().
+ If EndBit is greater than 7, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Address PCI configuration register to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..7.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..7.
+ @param AndData The value to AND with the PCI configuration register.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+PciBitFieldAnd8 (
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT8 AndData
+ );
+
+/**
+ Reads a bit field in an 8-bit port, performs a bitwise AND followed by a
+ bitwise OR, and writes the result back to the bit field in the
+ 8-bit port.
+
+ Reads the 8-bit PCI configuration register specified by Address, performs a
+ bitwise AND followed by a bitwise OR between the read result and
+ the value specified by AndData, and writes the result to the 8-bit PCI
+ configuration register specified by Address. The value written to the PCI
+ configuration register is returned. This function must guarantee that all PCI
+ read and write operations are serialized. Extra left bits in both AndData and
+ OrData are stripped.
+
+ If Address > 0x0FFFFFFF, then ASSERT().
+ If StartBit is greater than 7, then ASSERT().
+ If EndBit is greater than 7, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Address PCI configuration register to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..7.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..7.
+ @param AndData The value to AND with the PCI configuration register.
+ @param OrData The value to OR with the result of the AND operation.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+PciBitFieldAndThenOr8 (
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT8 AndData,
+ IN UINT8 OrData
+ );
+
+/**
+ Reads a 16-bit PCI configuration register.
+
+ Reads and returns the 16-bit PCI configuration register specified by Address.
+ This function must guarantee that all PCI read and write operations are
+ serialized.
+
+ If Address > 0x0FFFFFFF, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+
+ @param Address Address that encodes the PCI Bus, Device, Function and
+ Register.
+
+ @return The read value from the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+PciRead16 (
+ IN UINTN Address
+ );
+
+/**
+ Writes a 16-bit PCI configuration register.
+
+ Writes the 16-bit PCI configuration register specified by Address with the
+ value specified by Value. Value is returned. This function must guarantee
+ that all PCI read and write operations are serialized.
+
+ If Address > 0x0FFFFFFF, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+
+ @param Address Address that encodes the PCI Bus, Device, Function and
+ Register.
+ @param Value The value to write.
+
+ @return The value written to the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+PciWrite16 (
+ IN UINTN Address,
+ IN UINT16 Value
+ );
+
+/**
+ Performs a bitwise OR of a 16-bit PCI configuration register with
+ a 16-bit value.
+
+ Reads the 16-bit PCI configuration register specified by Address, performs a
+ bitwise OR between the read result and the value specified by
+ OrData, and writes the result to the 16-bit PCI configuration register
+ specified by Address. The value written to the PCI configuration register is
+ returned. This function must guarantee that all PCI read and write operations
+ are serialized.
+
+ If Address > 0x0FFFFFFF, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+
+ @param Address Address that encodes the PCI Bus, Device, Function and
+ Register.
+ @param OrData The value to OR with the PCI configuration register.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+PciOr16 (
+ IN UINTN Address,
+ IN UINT16 OrData
+ );
+
+/**
+ Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
+ value.
+
+ Reads the 16-bit PCI configuration register specified by Address, performs a
+ bitwise AND between the read result and the value specified by AndData, and
+ writes the result to the 16-bit PCI configuration register specified by
+ Address. The value written to the PCI configuration register is returned.
+ This function must guarantee that all PCI read and write operations are
+ serialized.
+
+ If Address > 0x0FFFFFFF, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+
+ @param Address Address that encodes the PCI Bus, Device, Function and
+ Register.
+ @param AndData The value to AND with the PCI configuration register.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+PciAnd16 (
+ IN UINTN Address,
+ IN UINT16 AndData
+ );
+
+/**
+ Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
+ value, followed a bitwise OR with another 16-bit value.
+
+ Reads the 16-bit PCI configuration register specified by Address, performs a
+ bitwise AND between the read result and the value specified by AndData,
+ performs a bitwise OR between the result of the AND operation and
+ the value specified by OrData, and writes the result to the 16-bit PCI
+ configuration register specified by Address. The value written to the PCI
+ configuration register is returned. This function must guarantee that all PCI
+ read and write operations are serialized.
+
+ If Address > 0x0FFFFFFF, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+
+ @param Address Address that encodes the PCI Bus, Device, Function and
+ Register.
+ @param AndData The value to AND with the PCI configuration register.
+ @param OrData The value to OR with the result of the AND operation.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+PciAndThenOr16 (
+ IN UINTN Address,
+ IN UINT16 AndData,
+ IN UINT16 OrData
+ );
+
+/**
+ Reads a bit field of a PCI configuration register.
+
+ Reads the bit field in a 16-bit PCI configuration register. The bit field is
+ specified by the StartBit and the EndBit. The value of the bit field is
+ returned.
+
+ If Address > 0x0FFFFFFF, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+ If StartBit is greater than 15, then ASSERT().
+ If EndBit is greater than 15, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+
+ @param Address PCI configuration register to read.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..15.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..15.
+
+ @return The value of the bit field read from the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+PciBitFieldRead16 (
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit
+ );
+
+/**
+ Writes a bit field to a PCI configuration register.
+
+ Writes Value to the bit field of the PCI configuration register. The bit
+ field is specified by the StartBit and the EndBit. All other bits in the
+ destination PCI configuration register are preserved. The new value of the
+ 16-bit register is returned.
+
+ If Address > 0x0FFFFFFF, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+ If StartBit is greater than 15, then ASSERT().
+ If EndBit is greater than 15, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Address PCI configuration register to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..15.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..15.
+ @param Value New value of the bit field.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+PciBitFieldWrite16 (
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT16 Value
+ );
+
+/**
+ Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and
+ writes the result back to the bit field in the 16-bit port.
+
+ Reads the 16-bit PCI configuration register specified by Address, performs a
+ bitwise OR between the read result and the value specified by
+ OrData, and writes the result to the 16-bit PCI configuration register
+ specified by Address. The value written to the PCI configuration register is
+ returned. This function must guarantee that all PCI read and write operations
+ are serialized. Extra left bits in OrData are stripped.
+
+ If Address > 0x0FFFFFFF, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+ If StartBit is greater than 15, then ASSERT().
+ If EndBit is greater than 15, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Address PCI configuration register to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..15.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..15.
+ @param OrData The value to OR with the PCI configuration register.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+PciBitFieldOr16 (
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT16 OrData
+ );
+
+/**
+ Reads a bit field in a 16-bit PCI configuration register, performs a bitwise
+ AND, and writes the result back to the bit field in the 16-bit register.
+
+ Reads the 16-bit PCI configuration register specified by Address, performs a
+ bitwise AND between the read result and the value specified by AndData, and
+ writes the result to the 16-bit PCI configuration register specified by
+ Address. The value written to the PCI configuration register is returned.
+ This function must guarantee that all PCI read and write operations are
+ serialized. Extra left bits in AndData are stripped.
+
+ If Address > 0x0FFFFFFF, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+ If StartBit is greater than 15, then ASSERT().
+ If EndBit is greater than 15, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Address PCI configuration register to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..15.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..15.
+ @param AndData The value to AND with the PCI configuration register.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+PciBitFieldAnd16 (
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT16 AndData
+ );
+
+/**
+ Reads a bit field in a 16-bit port, performs a bitwise AND followed by a
+ bitwise OR, and writes the result back to the bit field in the
+ 16-bit port.
+
+ Reads the 16-bit PCI configuration register specified by Address, performs a
+ bitwise AND followed by a bitwise OR between the read result and
+ the value specified by AndData, and writes the result to the 16-bit PCI
+ configuration register specified by Address. The value written to the PCI
+ configuration register is returned. This function must guarantee that all PCI
+ read and write operations are serialized. Extra left bits in both AndData and
+ OrData are stripped.
+
+ If Address > 0x0FFFFFFF, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+ If StartBit is greater than 15, then ASSERT().
+ If EndBit is greater than 15, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Address PCI configuration register to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..15.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..15.
+ @param AndData The value to AND with the PCI configuration register.
+ @param OrData The value to OR with the result of the AND operation.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+PciBitFieldAndThenOr16 (
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT16 AndData,
+ IN UINT16 OrData
+ );
+
+/**
+ Reads a 32-bit PCI configuration register.
+
+ Reads and returns the 32-bit PCI configuration register specified by Address.
+ This function must guarantee that all PCI read and write operations are
+ serialized.
+
+ If Address > 0x0FFFFFFF, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+
+ @param Address Address that encodes the PCI Bus, Device, Function and
+ Register.
+
+ @return The read value from the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+PciRead32 (
+ IN UINTN Address
+ );
+
+/**
+ Writes a 32-bit PCI configuration register.
+
+ Writes the 32-bit PCI configuration register specified by Address with the
+ value specified by Value. Value is returned. This function must guarantee
+ that all PCI read and write operations are serialized.
+
+ If Address > 0x0FFFFFFF, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+
+ @param Address Address that encodes the PCI Bus, Device, Function and
+ Register.
+ @param Value The value to write.
+
+ @return The value written to the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+PciWrite32 (
+ IN UINTN Address,
+ IN UINT32 Value
+ );
+
+/**
+ Performs a bitwise OR of a 32-bit PCI configuration register with
+ a 32-bit value.
+
+ Reads the 32-bit PCI configuration register specified by Address, performs a
+ bitwise OR between the read result and the value specified by
+ OrData, and writes the result to the 32-bit PCI configuration register
+ specified by Address. The value written to the PCI configuration register is
+ returned. This function must guarantee that all PCI read and write operations
+ are serialized.
+
+ If Address > 0x0FFFFFFF, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+
+ @param Address Address that encodes the PCI Bus, Device, Function and
+ Register.
+ @param OrData The value to OR with the PCI configuration register.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+PciOr32 (
+ IN UINTN Address,
+ IN UINT32 OrData
+ );
+
+/**
+ Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
+ value.
+
+ Reads the 32-bit PCI configuration register specified by Address, performs a
+ bitwise AND between the read result and the value specified by AndData, and
+ writes the result to the 32-bit PCI configuration register specified by
+ Address. The value written to the PCI configuration register is returned.
+ This function must guarantee that all PCI read and write operations are
+ serialized.
+
+ If Address > 0x0FFFFFFF, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+
+ @param Address Address that encodes the PCI Bus, Device, Function and
+ Register.
+ @param AndData The value to AND with the PCI configuration register.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+PciAnd32 (
+ IN UINTN Address,
+ IN UINT32 AndData
+ );
+
+/**
+ Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
+ value, followed a bitwise OR with another 32-bit value.
+
+ Reads the 32-bit PCI configuration register specified by Address, performs a
+ bitwise AND between the read result and the value specified by AndData,
+ performs a bitwise OR between the result of the AND operation and
+ the value specified by OrData, and writes the result to the 32-bit PCI
+ configuration register specified by Address. The value written to the PCI
+ configuration register is returned. This function must guarantee that all PCI
+ read and write operations are serialized.
+
+ If Address > 0x0FFFFFFF, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+
+ @param Address Address that encodes the PCI Bus, Device, Function and
+ Register.
+ @param AndData The value to AND with the PCI configuration register.
+ @param OrData The value to OR with the result of the AND operation.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+PciAndThenOr32 (
+ IN UINTN Address,
+ IN UINT32 AndData,
+ IN UINT32 OrData
+ );
+
+/**
+ Reads a bit field of a PCI configuration register.
+
+ Reads the bit field in a 32-bit PCI configuration register. The bit field is
+ specified by the StartBit and the EndBit. The value of the bit field is
+ returned.
+
+ If Address > 0x0FFFFFFF, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+ If StartBit is greater than 31, then ASSERT().
+ If EndBit is greater than 31, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+
+ @param Address PCI configuration register to read.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..31.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..31.
+
+ @return The value of the bit field read from the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+PciBitFieldRead32 (
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit
+ );
+
+/**
+ Writes a bit field to a PCI configuration register.
+
+ Writes Value to the bit field of the PCI configuration register. The bit
+ field is specified by the StartBit and the EndBit. All other bits in the
+ destination PCI configuration register are preserved. The new value of the
+ 32-bit register is returned.
+
+ If Address > 0x0FFFFFFF, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+ If StartBit is greater than 31, then ASSERT().
+ If EndBit is greater than 31, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Address PCI configuration register to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..31.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..31.
+ @param Value New value of the bit field.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+PciBitFieldWrite32 (
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 Value
+ );
+
+/**
+ Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and
+ writes the result back to the bit field in the 32-bit port.
+
+ Reads the 32-bit PCI configuration register specified by Address, performs a
+ bitwise OR between the read result and the value specified by
+ OrData, and writes the result to the 32-bit PCI configuration register
+ specified by Address. The value written to the PCI configuration register is
+ returned. This function must guarantee that all PCI read and write operations
+ are serialized. Extra left bits in OrData are stripped.
+
+ If Address > 0x0FFFFFFF, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+ If StartBit is greater than 31, then ASSERT().
+ If EndBit is greater than 31, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Address PCI configuration register to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..31.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..31.
+ @param OrData The value to OR with the PCI configuration register.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+PciBitFieldOr32 (
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 OrData
+ );
+
+/**
+ Reads a bit field in a 32-bit PCI configuration register, performs a bitwise
+ AND, and writes the result back to the bit field in the 32-bit register.
+
+ Reads the 32-bit PCI configuration register specified by Address, performs a
+ bitwise AND between the read result and the value specified by AndData, and
+ writes the result to the 32-bit PCI configuration register specified by
+ Address. The value written to the PCI configuration register is returned.
+ This function must guarantee that all PCI read and write operations are
+ serialized. Extra left bits in AndData are stripped.
+
+ If Address > 0x0FFFFFFF, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+ If StartBit is greater than 31, then ASSERT().
+ If EndBit is greater than 31, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Address PCI configuration register to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..31.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..31.
+ @param AndData The value to AND with the PCI configuration register.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+PciBitFieldAnd32 (
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 AndData
+ );
+
+/**
+ Reads a bit field in a 32-bit port, performs a bitwise AND followed by a
+ bitwise OR, and writes the result back to the bit field in the
+ 32-bit port.
+
+ Reads the 32-bit PCI configuration register specified by Address, performs a
+ bitwise AND followed by a bitwise OR between the read result and
+ the value specified by AndData, and writes the result to the 32-bit PCI
+ configuration register specified by Address. The value written to the PCI
+ configuration register is returned. This function must guarantee that all PCI
+ read and write operations are serialized. Extra left bits in both AndData and
+ OrData are stripped.
+
+ If Address > 0x0FFFFFFF, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+ If StartBit is greater than 31, then ASSERT().
+ If EndBit is greater than 31, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Address PCI configuration register to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..31.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..31.
+ @param AndData The value to AND with the PCI configuration register.
+ @param OrData The value to OR with the result of the AND operation.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+PciBitFieldAndThenOr32 (
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 AndData,
+ IN UINT32 OrData
+ );
+
+/**
+ Reads a range of PCI configuration registers into a caller supplied buffer.
+
+ Reads the range of PCI configuration registers specified by StartAddress and
+ Size into the buffer specified by Buffer. This function only allows the PCI
+ configuration registers from a single PCI function to be read. Size is
+ returned. When possible 32-bit PCI configuration read cycles are used to read
+ from StartAddress to StartAddress + Size. Due to alignment restrictions, 8-bit
+ and 16-bit PCI configuration read cycles may be used at the beginning and the
+ end of the range.
+
+ If StartAddress > 0x0FFFFFFF, then ASSERT().
+ If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
+ If Size > 0 and Buffer is NULL, then ASSERT().
+
+ @param StartAddress Starting address that encodes the PCI Bus, Device,
+ Function and Register.
+ @param Size Size in bytes of the transfer.
+ @param Buffer Pointer to a buffer receiving the data read.
+
+ @return Size
+
+**/
+UINTN
+EFIAPI
+PciReadBuffer (
+ IN UINTN StartAddress,
+ IN UINTN Size,
+ OUT VOID *Buffer
+ );
+
+/**
+ Copies the data in a caller supplied buffer to a specified range of PCI
+ configuration space.
+
+ Writes the range of PCI configuration registers specified by StartAddress and
+ Size from the buffer specified by Buffer. This function only allows the PCI
+ configuration registers from a single PCI function to be written. Size is
+ returned. When possible 32-bit PCI configuration write cycles are used to
+ write from StartAddress to StartAddress + Size. Due to alignment restrictions,
+ 8-bit and 16-bit PCI configuration write cycles may be used at the beginning
+ and the end of the range.
+
+ If StartAddress > 0x0FFFFFFF, then ASSERT().
+ If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
+ If Size > 0 and Buffer is NULL, then ASSERT().
+
+ @param StartAddress Starting address that encodes the PCI Bus, Device,
+ Function and Register.
+ @param Size Size in bytes of the transfer.
+ @param Buffer Pointer to a buffer containing the data to write.
+
+ @return Size written to StartAddress.
+
+**/
+UINTN
+EFIAPI
+PciWriteBuffer (
+ IN UINTN StartAddress,
+ IN UINTN Size,
+ IN VOID *Buffer
+ );
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/PciSegmentInfoLib.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/PciSegmentInfoLib.h
new file mode 100644
index 0000000000..574ee1d364
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/PciSegmentInfoLib.h
@@ -0,0 +1,36 @@
+/** @file
+ Provides services to return segment information on a platform with multiple PCI segments.
+
+ This library is consumed by PciSegmentLib to support multiple segment PCI configuration access.
+
+ Copyright (c) 2017 - 2020, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __PCI_SEGMENT_INFO_LIB__
+#define __PCI_SEGMENT_INFO_LIB__
+
+typedef struct {
+ UINT16 SegmentNumber; ///< Segment number.
+ UINT64 BaseAddress; ///< ECAM Base address.
+ UINT8 StartBusNumber; ///< Start BUS number, for verifying the PCI Segment address.
+ UINT8 EndBusNumber; ///< End BUS number, for verifying the PCI Segment address.
+} PCI_SEGMENT_INFO;
+
+/**
+ Return an array of PCI_SEGMENT_INFO holding the segment information.
+
+ Note: The returned array/buffer is owned by callee.
+
+ @param Count Return the count of segments.
+
+ @retval A callee owned array holding the segment information.
+**/
+PCI_SEGMENT_INFO *
+EFIAPI
+GetPciSegmentInfo (
+ UINTN *Count
+ );
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/PciSegmentLib.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/PciSegmentLib.h
new file mode 100644
index 0000000000..09c910e15f
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/PciSegmentLib.h
@@ -0,0 +1,1042 @@
+/** @file
+ Provides services to access PCI Configuration Space on a platform with multiple PCI segments.
+
+ The PCI Segment Library function provide services to read, write, and modify the PCI configuration
+ registers on PCI root bridges on any supported PCI segment. These library services take a single
+ address parameter that encodes the PCI Segment, PCI Bus, PCI Device, PCI Function, and PCI Register.
+ The layout of this address parameter is as follows:
+
+ PCI Register: Bits 0..11
+ PCI Function Bits 12..14
+ PCI Device Bits 15..19
+ PCI Bus Bits 20..27
+ Reserved Bits 28..31. Must be 0.
+ PCI Segment Bits 32..47
+ Reserved Bits 48..63. Must be 0.
+
+ | Reserved (MBZ) | Segment | Reserved (MBZ) | Bus | Device | Function | Register |
+ 63 48 47 32 31 28 27 20 19 15 14 12 11 0
+
+ These functions perform PCI configuration cycles using the default PCI configuration access
+ method. This may use I/O ports 0xCF8 and 0xCFC to perform PCI configuration accesses, or it
+ may use MMIO registers relative to the PcdPciExpressBaseAddress, or it may use some alternate
+ access method. Modules will typically use the PCI Segment Library for its PCI configuration
+ accesses when PCI Segments other than Segment #0 must be accessed.
+
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __PCI_SEGMENT_LIB__
+#define __PCI_SEGMENT_LIB__
+
+/**
+ Macro that converts PCI Segment, PCI Bus, PCI Device, PCI Function,
+ and PCI Register to an address that can be passed to the PCI Segment Library functions.
+
+ Computes an address that is compatible with the PCI Segment Library functions.
+ The unused upper bits of Segment, Bus, Device, Function,
+ and Register are stripped prior to the generation of the address.
+
+ @param Segment PCI Segment number. Range 0..65535.
+ @param Bus PCI Bus number. Range 0..255.
+ @param Device PCI Device number. Range 0..31.
+ @param Function PCI Function number. Range 0..7.
+ @param Register PCI Register number. Range 0..255 for PCI. Range 0..4095 for PCI Express.
+
+ @return The address that is compatible with the PCI Segment Library functions.
+
+**/
+#define PCI_SEGMENT_LIB_ADDRESS(Segment, Bus, Device, Function, Register) \
+ ((Segment != 0) ? \
+ ( ((Register) & 0xfff) | \
+ (((Function) & 0x07) << 12) | \
+ (((Device) & 0x1f) << 15) | \
+ (((Bus) & 0xff) << 20) | \
+ (LShiftU64 ((Segment) & 0xffff, 32)) \
+ ) : \
+ ( ((Register) & 0xfff) | \
+ (((Function) & 0x07) << 12) | \
+ (((Device) & 0x1f) << 15) | \
+ (((Bus) & 0xff) << 20) \
+ ) \
+ )
+
+/**
+ Register a PCI device so PCI configuration registers may be accessed after
+ SetVirtualAddressMap().
+
+ If any reserved bits in Address are set, then ASSERT().
+
+ @param Address Address that encodes the PCI Bus, Device, Function and
+ Register.
+
+ @retval RETURN_SUCCESS The PCI device was registered for runtime access.
+ @retval RETURN_UNSUPPORTED An attempt was made to call this function
+ after ExitBootServices().
+ @retval RETURN_UNSUPPORTED The resources required to access the PCI device
+ at runtime could not be mapped.
+ @retval RETURN_OUT_OF_RESOURCES There are not enough resources available to
+ complete the registration.
+
+**/
+RETURN_STATUS
+EFIAPI
+PciSegmentRegisterForRuntimeAccess (
+ IN UINTN Address
+ );
+
+/**
+ Reads an 8-bit PCI configuration register.
+
+ Reads and returns the 8-bit PCI configuration register specified by Address.
+ This function must guarantee that all PCI read and write operations are serialized.
+
+ If any reserved bits in Address are set, then ASSERT().
+
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
+
+ @return The 8-bit PCI configuration register specified by Address.
+
+**/
+UINT8
+EFIAPI
+PciSegmentRead8 (
+ IN UINT64 Address
+ );
+
+/**
+ Writes an 8-bit PCI configuration register.
+
+ Writes the 8-bit PCI configuration register specified by Address with the value specified by Value.
+ Value is returned. This function must guarantee that all PCI read and write operations are serialized.
+
+ If any reserved bits in Address are set, then ASSERT().
+
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
+ @param Value The value to write.
+
+ @return The value written to the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+PciSegmentWrite8 (
+ IN UINT64 Address,
+ IN UINT8 Value
+ );
+
+/**
+ Performs a bitwise OR of an 8-bit PCI configuration register with an 8-bit value.
+
+ Reads the 8-bit PCI configuration register specified by Address,
+ performs a bitwise OR between the read result and the value specified by OrData,
+ and writes the result to the 8-bit PCI configuration register specified by Address.
+ The value written to the PCI configuration register is returned.
+ This function must guarantee that all PCI read and write operations are serialized.
+
+ If any reserved bits in Address are set, then ASSERT().
+
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
+ @param OrData The value to OR with the PCI configuration register.
+
+ @return The value written to the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+PciSegmentOr8 (
+ IN UINT64 Address,
+ IN UINT8 OrData
+ );
+
+/**
+ Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value.
+
+ Reads the 8-bit PCI configuration register specified by Address,
+ performs a bitwise AND between the read result and the value specified by AndData,
+ and writes the result to the 8-bit PCI configuration register specified by Address.
+ The value written to the PCI configuration register is returned.
+ This function must guarantee that all PCI read and write operations are serialized.
+ If any reserved bits in Address are set, then ASSERT().
+
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
+ @param AndData The value to AND with the PCI configuration register.
+
+ @return The value written to the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+PciSegmentAnd8 (
+ IN UINT64 Address,
+ IN UINT8 AndData
+ );
+
+/**
+ Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value,
+ followed a bitwise OR with another 8-bit value.
+
+ Reads the 8-bit PCI configuration register specified by Address,
+ performs a bitwise AND between the read result and the value specified by AndData,
+ performs a bitwise OR between the result of the AND operation and the value specified by OrData,
+ and writes the result to the 8-bit PCI configuration register specified by Address.
+ The value written to the PCI configuration register is returned.
+ This function must guarantee that all PCI read and write operations are serialized.
+
+ If any reserved bits in Address are set, then ASSERT().
+
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
+ @param AndData The value to AND with the PCI configuration register.
+ @param OrData The value to OR with the PCI configuration register.
+
+ @return The value written to the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+PciSegmentAndThenOr8 (
+ IN UINT64 Address,
+ IN UINT8 AndData,
+ IN UINT8 OrData
+ );
+
+/**
+ Reads a bit field of a PCI configuration register.
+
+ Reads the bit field in an 8-bit PCI configuration register. The bit field is
+ specified by the StartBit and the EndBit. The value of the bit field is
+ returned.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If StartBit is greater than 7, then ASSERT().
+ If EndBit is greater than 7, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+
+ @param Address PCI configuration register to read.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..7.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..7.
+
+ @return The value of the bit field read from the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+PciSegmentBitFieldRead8 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit
+ );
+
+/**
+ Writes a bit field to a PCI configuration register.
+
+ Writes Value to the bit field of the PCI configuration register. The bit
+ field is specified by the StartBit and the EndBit. All other bits in the
+ destination PCI configuration register are preserved. The new value of the
+ 8-bit register is returned.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If StartBit is greater than 7, then ASSERT().
+ If EndBit is greater than 7, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Address PCI configuration register to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..7.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..7.
+ @param Value New value of the bit field.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+PciSegmentBitFieldWrite8 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT8 Value
+ );
+
+/**
+ Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and
+ writes the result back to the bit field in the 8-bit port.
+
+ Reads the 8-bit PCI configuration register specified by Address, performs a
+ bitwise OR between the read result and the value specified by
+ OrData, and writes the result to the 8-bit PCI configuration register
+ specified by Address. The value written to the PCI configuration register is
+ returned. This function must guarantee that all PCI read and write operations
+ are serialized. Extra left bits in OrData are stripped.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If StartBit is greater than 7, then ASSERT().
+ If EndBit is greater than 7, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Address PCI configuration register to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..7.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..7.
+ @param OrData The value to OR with the PCI configuration register.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+PciSegmentBitFieldOr8 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT8 OrData
+ );
+
+/**
+ Reads a bit field in an 8-bit PCI configuration register, performs a bitwise
+ AND, and writes the result back to the bit field in the 8-bit register.
+
+ Reads the 8-bit PCI configuration register specified by Address, performs a
+ bitwise AND between the read result and the value specified by AndData, and
+ writes the result to the 8-bit PCI configuration register specified by
+ Address. The value written to the PCI configuration register is returned.
+ This function must guarantee that all PCI read and write operations are
+ serialized. Extra left bits in AndData are stripped.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If StartBit is greater than 7, then ASSERT().
+ If EndBit is greater than 7, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Address PCI configuration register to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..7.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..7.
+ @param AndData The value to AND with the PCI configuration register.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+PciSegmentBitFieldAnd8 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT8 AndData
+ );
+
+/**
+ Reads a bit field in an 8-bit port, performs a bitwise AND followed by a
+ bitwise OR, and writes the result back to the bit field in the 8-bit port.
+
+ Reads the 8-bit PCI configuration register specified by Address, performs a
+ bitwise AND followed by a bitwise OR between the read result and
+ the value specified by AndData, and writes the result to the 8-bit PCI
+ configuration register specified by Address. The value written to the PCI
+ configuration register is returned. This function must guarantee that all PCI
+ read and write operations are serialized. Extra left bits in both AndData and
+ OrData are stripped.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If StartBit is greater than 7, then ASSERT().
+ If EndBit is greater than 7, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Address PCI configuration register to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..7.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..7.
+ @param AndData The value to AND with the PCI configuration register.
+ @param OrData The value to OR with the result of the AND operation.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+PciSegmentBitFieldAndThenOr8 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT8 AndData,
+ IN UINT8 OrData
+ );
+
+/**
+ Reads a 16-bit PCI configuration register.
+
+ Reads and returns the 16-bit PCI configuration register specified by Address.
+ This function must guarantee that all PCI read and write operations are serialized.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
+
+ @return The 16-bit PCI configuration register specified by Address.
+
+**/
+UINT16
+EFIAPI
+PciSegmentRead16 (
+ IN UINT64 Address
+ );
+
+/**
+ Writes a 16-bit PCI configuration register.
+
+ Writes the 16-bit PCI configuration register specified by Address with the value specified by Value.
+ Value is returned. This function must guarantee that all PCI read and write operations are serialized.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
+ @param Value The value to write.
+
+ @return The parameter of Value.
+
+**/
+UINT16
+EFIAPI
+PciSegmentWrite16 (
+ IN UINT64 Address,
+ IN UINT16 Value
+ );
+
+/**
+ Performs a bitwise OR of a 16-bit PCI configuration register with
+ a 16-bit value.
+
+ Reads the 16-bit PCI configuration register specified by Address, performs a
+ bitwise OR between the read result and the value specified by OrData, and
+ writes the result to the 16-bit PCI configuration register specified by Address.
+ The value written to the PCI configuration register is returned. This function
+ must guarantee that all PCI read and write operations are serialized.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function and
+ Register.
+ @param OrData The value to OR with the PCI configuration register.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+PciSegmentOr16 (
+ IN UINT64 Address,
+ IN UINT16 OrData
+ );
+
+/**
+ Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit value.
+
+ Reads the 16-bit PCI configuration register specified by Address,
+ performs a bitwise AND between the read result and the value specified by AndData,
+ and writes the result to the 16-bit PCI configuration register specified by Address.
+ The value written to the PCI configuration register is returned.
+ This function must guarantee that all PCI read and write operations are serialized.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
+ @param AndData The value to AND with the PCI configuration register.
+
+ @return The value written to the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+PciSegmentAnd16 (
+ IN UINT64 Address,
+ IN UINT16 AndData
+ );
+
+/**
+ Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit value,
+ followed a bitwise OR with another 16-bit value.
+
+ Reads the 16-bit PCI configuration register specified by Address,
+ performs a bitwise AND between the read result and the value specified by AndData,
+ performs a bitwise OR between the result of the AND operation and the value specified by OrData,
+ and writes the result to the 16-bit PCI configuration register specified by Address.
+ The value written to the PCI configuration register is returned.
+ This function must guarantee that all PCI read and write operations are serialized.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
+ @param AndData The value to AND with the PCI configuration register.
+ @param OrData The value to OR with the PCI configuration register.
+
+ @return The value written to the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+PciSegmentAndThenOr16 (
+ IN UINT64 Address,
+ IN UINT16 AndData,
+ IN UINT16 OrData
+ );
+
+/**
+ Reads a bit field of a PCI configuration register.
+
+ Reads the bit field in a 16-bit PCI configuration register. The bit field is
+ specified by the StartBit and the EndBit. The value of the bit field is
+ returned.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+ If StartBit is greater than 15, then ASSERT().
+ If EndBit is greater than 15, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+
+ @param Address PCI configuration register to read.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..15.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..15.
+
+ @return The value of the bit field read from the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+PciSegmentBitFieldRead16 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit
+ );
+
+/**
+ Writes a bit field to a PCI configuration register.
+
+ Writes Value to the bit field of the PCI configuration register. The bit
+ field is specified by the StartBit and the EndBit. All other bits in the
+ destination PCI configuration register are preserved. The new value of the
+ 16-bit register is returned.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+ If StartBit is greater than 15, then ASSERT().
+ If EndBit is greater than 15, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Address PCI configuration register to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..15.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..15.
+ @param Value New value of the bit field.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+PciSegmentBitFieldWrite16 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT16 Value
+ );
+
+/**
+ Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, writes
+ the result back to the bit field in the 16-bit port.
+
+ Reads the 16-bit PCI configuration register specified by Address, performs a
+ bitwise OR between the read result and the value specified by
+ OrData, and writes the result to the 16-bit PCI configuration register
+ specified by Address. The value written to the PCI configuration register is
+ returned. This function must guarantee that all PCI read and write operations
+ are serialized. Extra left bits in OrData are stripped.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+ If StartBit is greater than 15, then ASSERT().
+ If EndBit is greater than 15, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Address PCI configuration register to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..15.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..15.
+ @param OrData The value to OR with the PCI configuration register.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+PciSegmentBitFieldOr16 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT16 OrData
+ );
+
+/**
+ Reads a bit field in a 16-bit PCI configuration register, performs a bitwise
+ AND, writes the result back to the bit field in the 16-bit register.
+
+ Reads the 16-bit PCI configuration register specified by Address, performs a
+ bitwise AND between the read result and the value specified by AndData, and
+ writes the result to the 16-bit PCI configuration register specified by
+ Address. The value written to the PCI configuration register is returned.
+ This function must guarantee that all PCI read and write operations are
+ serialized. Extra left bits in AndData are stripped.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+ If StartBit is greater than 15, then ASSERT().
+ If EndBit is greater than 15, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..15.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..15.
+ @param AndData The value to AND with the PCI configuration register.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+PciSegmentBitFieldAnd16 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT16 AndData
+ );
+
+/**
+ Reads a bit field in a 16-bit port, performs a bitwise AND followed by a
+ bitwise OR, and writes the result back to the bit field in the
+ 16-bit port.
+
+ Reads the 16-bit PCI configuration register specified by Address, performs a
+ bitwise AND followed by a bitwise OR between the read result and
+ the value specified by AndData, and writes the result to the 16-bit PCI
+ configuration register specified by Address. The value written to the PCI
+ configuration register is returned. This function must guarantee that all PCI
+ read and write operations are serialized. Extra left bits in both AndData and
+ OrData are stripped.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If StartBit is greater than 15, then ASSERT().
+ If EndBit is greater than 15, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Address PCI configuration register to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..15.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..15.
+ @param AndData The value to AND with the PCI configuration register.
+ @param OrData The value to OR with the result of the AND operation.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+PciSegmentBitFieldAndThenOr16 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT16 AndData,
+ IN UINT16 OrData
+ );
+
+/**
+ Reads a 32-bit PCI configuration register.
+
+ Reads and returns the 32-bit PCI configuration register specified by Address.
+ This function must guarantee that all PCI read and write operations are serialized.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
+
+ @return The 32-bit PCI configuration register specified by Address.
+
+**/
+UINT32
+EFIAPI
+PciSegmentRead32 (
+ IN UINT64 Address
+ );
+
+/**
+ Writes a 32-bit PCI configuration register.
+
+ Writes the 32-bit PCI configuration register specified by Address with the value specified by Value.
+ Value is returned. This function must guarantee that all PCI read and write operations are serialized.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
+ @param Value The value to write.
+
+ @return The parameter of Value.
+
+**/
+UINT32
+EFIAPI
+PciSegmentWrite32 (
+ IN UINT64 Address,
+ IN UINT32 Value
+ );
+
+/**
+ Performs a bitwise OR of a 32-bit PCI configuration register with a 32-bit value.
+
+ Reads the 32-bit PCI configuration register specified by Address,
+ performs a bitwise OR between the read result and the value specified by OrData,
+ and writes the result to the 32-bit PCI configuration register specified by Address.
+ The value written to the PCI configuration register is returned.
+ This function must guarantee that all PCI read and write operations are serialized.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
+ @param OrData The value to OR with the PCI configuration register.
+
+ @return The value written to the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+PciSegmentOr32 (
+ IN UINT64 Address,
+ IN UINT32 OrData
+ );
+
+/**
+ Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value.
+
+ Reads the 32-bit PCI configuration register specified by Address,
+ performs a bitwise AND between the read result and the value specified by AndData,
+ and writes the result to the 32-bit PCI configuration register specified by Address.
+ The value written to the PCI configuration register is returned.
+ This function must guarantee that all PCI read and write operations are serialized.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
+ @param AndData The value to AND with the PCI configuration register.
+
+ @return The value written to the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+PciSegmentAnd32 (
+ IN UINT64 Address,
+ IN UINT32 AndData
+ );
+
+/**
+ Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value,
+ followed a bitwise OR with another 32-bit value.
+
+ Reads the 32-bit PCI configuration register specified by Address,
+ performs a bitwise AND between the read result and the value specified by AndData,
+ performs a bitwise OR between the result of the AND operation and the value specified by OrData,
+ and writes the result to the 32-bit PCI configuration register specified by Address.
+ The value written to the PCI configuration register is returned.
+ This function must guarantee that all PCI read and write operations are serialized.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
+ @param AndData The value to AND with the PCI configuration register.
+ @param OrData The value to OR with the PCI configuration register.
+
+ @return The value written to the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+PciSegmentAndThenOr32 (
+ IN UINT64 Address,
+ IN UINT32 AndData,
+ IN UINT32 OrData
+ );
+
+/**
+ Reads a bit field of a PCI configuration register.
+
+ Reads the bit field in a 32-bit PCI configuration register. The bit field is
+ specified by the StartBit and the EndBit. The value of the bit field is
+ returned.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+ If StartBit is greater than 31, then ASSERT().
+ If EndBit is greater than 31, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+
+ @param Address PCI configuration register to read.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..31.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..31.
+
+ @return The value of the bit field read from the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+PciSegmentBitFieldRead32 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit
+ );
+
+/**
+ Writes a bit field to a PCI configuration register.
+
+ Writes Value to the bit field of the PCI configuration register. The bit
+ field is specified by the StartBit and the EndBit. All other bits in the
+ destination PCI configuration register are preserved. The new value of the
+ 32-bit register is returned.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+ If StartBit is greater than 31, then ASSERT().
+ If EndBit is greater than 31, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Address PCI configuration register to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..31.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..31.
+ @param Value New value of the bit field.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+PciSegmentBitFieldWrite32 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 Value
+ );
+
+/**
+ Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and
+ writes the result back to the bit field in the 32-bit port.
+
+ Reads the 32-bit PCI configuration register specified by Address, performs a
+ bitwise OR between the read result and the value specified by
+ OrData, and writes the result to the 32-bit PCI configuration register
+ specified by Address. The value written to the PCI configuration register is
+ returned. This function must guarantee that all PCI read and write operations
+ are serialized. Extra left bits in OrData are stripped.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If StartBit is greater than 31, then ASSERT().
+ If EndBit is greater than 31, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Address PCI configuration register to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..31.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..31.
+ @param OrData The value to OR with the PCI configuration register.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+PciSegmentBitFieldOr32 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 OrData
+ );
+
+/**
+ Reads a bit field in a 32-bit PCI configuration register, performs a bitwise
+ AND, and writes the result back to the bit field in the 32-bit register.
+
+
+ Reads the 32-bit PCI configuration register specified by Address, performs a bitwise
+ AND between the read result and the value specified by AndData, and writes the result
+ to the 32-bit PCI configuration register specified by Address. The value written to
+ the PCI configuration register is returned. This function must guarantee that all PCI
+ read and write operations are serialized. Extra left bits in AndData are stripped.
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+ If StartBit is greater than 31, then ASSERT().
+ If EndBit is greater than 31, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..31.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..31.
+ @param AndData The value to AND with the PCI configuration register.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+PciSegmentBitFieldAnd32 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 AndData
+ );
+
+/**
+ Reads a bit field in a 32-bit port, performs a bitwise AND followed by a
+ bitwise OR, and writes the result back to the bit field in the
+ 32-bit port.
+
+ Reads the 32-bit PCI configuration register specified by Address, performs a
+ bitwise AND followed by a bitwise OR between the read result and
+ the value specified by AndData, and writes the result to the 32-bit PCI
+ configuration register specified by Address. The value written to the PCI
+ configuration register is returned. This function must guarantee that all PCI
+ read and write operations are serialized. Extra left bits in both AndData and
+ OrData are stripped.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If StartBit is greater than 31, then ASSERT().
+ If EndBit is greater than 31, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Address PCI configuration register to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..31.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..31.
+ @param AndData The value to AND with the PCI configuration register.
+ @param OrData The value to OR with the result of the AND operation.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+PciSegmentBitFieldAndThenOr32 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 AndData,
+ IN UINT32 OrData
+ );
+
+/**
+ Reads a range of PCI configuration registers into a caller supplied buffer.
+
+ Reads the range of PCI configuration registers specified by StartAddress and
+ Size into the buffer specified by Buffer. This function only allows the PCI
+ configuration registers from a single PCI function to be read. Size is
+ returned. When possible 32-bit PCI configuration read cycles are used to read
+ from StartAddress to StartAddress + Size. Due to alignment restrictions, 8-bit
+ and 16-bit PCI configuration read cycles may be used at the beginning and the
+ end of the range.
+
+ If any reserved bits in StartAddress are set, then ASSERT().
+ If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
+ If Size > 0 and Buffer is NULL, then ASSERT().
+
+ @param StartAddress Starting address that encodes the PCI Segment, Bus, Device,
+ Function and Register.
+ @param Size Size in bytes of the transfer.
+ @param Buffer Pointer to a buffer receiving the data read.
+
+ @return Size
+
+**/
+UINTN
+EFIAPI
+PciSegmentReadBuffer (
+ IN UINT64 StartAddress,
+ IN UINTN Size,
+ OUT VOID *Buffer
+ );
+
+/**
+ Copies the data in a caller supplied buffer to a specified range of PCI
+ configuration space.
+
+ Writes the range of PCI configuration registers specified by StartAddress and
+ Size from the buffer specified by Buffer. This function only allows the PCI
+ configuration registers from a single PCI function to be written. Size is
+ returned. When possible 32-bit PCI configuration write cycles are used to
+ write from StartAddress to StartAddress + Size. Due to alignment restrictions,
+ 8-bit and 16-bit PCI configuration write cycles may be used at the beginning
+ and the end of the range.
+
+ If any reserved bits in StartAddress are set, then ASSERT().
+ If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
+ If Size > 0 and Buffer is NULL, then ASSERT().
+
+ @param StartAddress Starting address that encodes the PCI Segment, Bus, Device,
+ Function and Register.
+ @param Size Size in bytes of the transfer.
+ @param Buffer Pointer to a buffer containing the data to write.
+
+ @return The parameter of Size.
+
+**/
+UINTN
+EFIAPI
+PciSegmentWriteBuffer (
+ IN UINT64 StartAddress,
+ IN UINTN Size,
+ IN VOID *Buffer
+ );
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/PeCoffExtraActionLib.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/PeCoffExtraActionLib.h
new file mode 100644
index 0000000000..97599d9a47
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/PeCoffExtraActionLib.h
@@ -0,0 +1,47 @@
+/** @file
+ Provides services to perform additional actions when a PE/COFF image is loaded
+ or unloaded. This is useful for environment where symbols need to be loaded
+ and unloaded to support source level debugging.
+
+ Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __PE_COFF_EXTRA_ACTION_LIB_H__
+#define __PE_COFF_EXTRA_ACTION_LIB_H__
+
+#include
+
+/**
+ Performs additional actions after a PE/COFF image has been loaded and relocated.
+
+ If ImageContext is NULL, then ASSERT().
+
+ @param ImageContext Pointer to the image context structure that describes the
+ PE/COFF image that has already been loaded and relocated.
+
+**/
+VOID
+EFIAPI
+PeCoffLoaderRelocateImageExtraAction (
+ IN OUT PE_COFF_LOADER_IMAGE_CONTEXT *ImageContext
+ );
+
+/**
+ Performs additional actions just before a PE/COFF image is unloaded. Any resources
+ that were allocated by PeCoffLoaderRelocateImageExtraAction() must be freed.
+
+ If ImageContext is NULL, then ASSERT().
+
+ @param ImageContext Pointer to the image context structure that describes the
+ PE/COFF image that is being unloaded.
+
+**/
+VOID
+EFIAPI
+PeCoffLoaderUnloadImageExtraAction (
+ IN OUT PE_COFF_LOADER_IMAGE_CONTEXT *ImageContext
+ );
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/PeCoffGetEntryPointLib.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/PeCoffGetEntryPointLib.h
new file mode 100644
index 0000000000..1e6e10888a
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/PeCoffGetEntryPointLib.h
@@ -0,0 +1,115 @@
+/** @file
+ Provides a service to retrieve the PE/COFF entry point from a PE/COFF image.
+
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __PE_COFF_GET_ENTRY_POINT_LIB_H__
+#define __PE_COFF_GET_ENTRY_POINT_LIB_H__
+
+/**
+ Retrieves and returns a pointer to the entry point to a PE/COFF image that has been loaded
+ into system memory with the PE/COFF Loader Library functions.
+
+ Retrieves the entry point to the PE/COFF image specified by Pe32Data and returns this entry
+ point in EntryPoint. If the entry point could not be retrieved from the PE/COFF image, then
+ return RETURN_INVALID_PARAMETER. Otherwise return RETURN_SUCCESS.
+ If Pe32Data is NULL, then ASSERT().
+ If EntryPoint is NULL, then ASSERT().
+
+ @param Pe32Data The pointer to the PE/COFF image that is loaded in system memory.
+ @param EntryPoint The pointer to entry point to the PE/COFF image to return.
+
+ @retval RETURN_SUCCESS EntryPoint was returned.
+ @retval RETURN_INVALID_PARAMETER The entry point could not be found in the PE/COFF image.
+
+**/
+RETURN_STATUS
+EFIAPI
+PeCoffLoaderGetEntryPoint (
+ IN VOID *Pe32Data,
+ OUT VOID **EntryPoint
+ );
+
+/**
+ Returns the machine type of a PE/COFF image.
+
+ Returns the machine type from the PE/COFF image specified by Pe32Data.
+ If Pe32Data is NULL, then ASSERT().
+
+ @param Pe32Data The pointer to the PE/COFF image that is loaded in system
+ memory.
+
+ @return Machine type or zero if not a valid image.
+
+**/
+UINT16
+EFIAPI
+PeCoffLoaderGetMachineType (
+ IN VOID *Pe32Data
+ );
+
+/**
+ Returns a pointer to the PDB file name for a PE/COFF image that has been
+ loaded into system memory with the PE/COFF Loader Library functions.
+
+ Returns the PDB file name for the PE/COFF image specified by Pe32Data. If
+ the PE/COFF image specified by Pe32Data is not a valid, then NULL is
+ returned. If the PE/COFF image specified by Pe32Data does not contain a
+ debug directory entry, then NULL is returned. If the debug directory entry
+ in the PE/COFF image specified by Pe32Data does not contain a PDB file name,
+ then NULL is returned.
+ If Pe32Data is NULL, then ASSERT().
+
+ @param Pe32Data The pointer to the PE/COFF image that is loaded in system
+ memory.
+
+ @return The PDB file name for the PE/COFF image specified by Pe32Data, or NULL
+ if it cannot be retrieved.
+
+**/
+VOID *
+EFIAPI
+PeCoffLoaderGetPdbPointer (
+ IN VOID *Pe32Data
+ );
+
+/**
+ Returns the size of the PE/COFF headers
+
+ Returns the size of the PE/COFF header specified by Pe32Data.
+ If Pe32Data is NULL, then ASSERT().
+
+ @param Pe32Data The pointer to the PE/COFF image that is loaded in system
+ memory.
+
+ @return Size of PE/COFF header in bytes, or zero if not a valid image.
+
+**/
+UINT32
+EFIAPI
+PeCoffGetSizeOfHeaders (
+ IN VOID *Pe32Data
+ );
+
+/**
+ Returns PE/COFF image base specified by the address in this PE/COFF image.
+
+ On DEBUG build, searches the PE/COFF image base forward the address in this
+ PE/COFF image and returns it.
+
+ @param Address Address located in one PE/COFF image.
+
+ @retval 0 RELEASE build or cannot find the PE/COFF image base.
+ @retval others PE/COFF image base found.
+
+**/
+UINTN
+EFIAPI
+PeCoffSearchImageBase (
+ IN UINTN Address
+ );
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/PeCoffLib.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/PeCoffLib.h
new file mode 100644
index 0000000000..74b1d1044a
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/PeCoffLib.h
@@ -0,0 +1,385 @@
+/** @file
+ Provides services to load and relocate a PE/COFF image.
+
+ The PE/COFF Loader Library abstracts the implementation of a PE/COFF loader for
+ IA-32, x86, IPF, and EBC processor types. The library functions are memory-based
+ and can be ported easily to any environment.
+
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __BASE_PE_COFF_LIB_H__
+#define __BASE_PE_COFF_LIB_H__
+
+#include
+//
+// Return status codes from the PE/COFF Loader services
+//
+#define IMAGE_ERROR_SUCCESS 0
+#define IMAGE_ERROR_IMAGE_READ 1
+#define IMAGE_ERROR_INVALID_PE_HEADER_SIGNATURE 2
+#define IMAGE_ERROR_INVALID_MACHINE_TYPE 3
+#define IMAGE_ERROR_INVALID_SUBSYSTEM 4
+#define IMAGE_ERROR_INVALID_IMAGE_ADDRESS 5
+#define IMAGE_ERROR_INVALID_IMAGE_SIZE 6
+#define IMAGE_ERROR_INVALID_SECTION_ALIGNMENT 7
+#define IMAGE_ERROR_SECTION_NOT_LOADED 8
+#define IMAGE_ERROR_FAILED_RELOCATION 9
+#define IMAGE_ERROR_FAILED_ICACHE_FLUSH 10
+#define IMAGE_ERROR_UNSUPPORTED 11
+
+/**
+ Reads contents of a PE/COFF image.
+
+ A function of this type reads contents of the PE/COFF image specified by FileHandle. The read
+ operation copies ReadSize bytes from the PE/COFF image starting at byte offset FileOffset into
+ the buffer specified by Buffer. The size of the buffer actually read is returned in ReadSize.
+ If FileOffset specifies an offset past the end of the PE/COFF image, a ReadSize of 0 is returned.
+ A function of this type must be registered in the ImageRead field of a PE_COFF_LOADER_IMAGE_CONTEXT
+ structure for the PE/COFF Loader Library service to function correctly. This function abstracts access
+ to a PE/COFF image so it can be implemented in an environment specific manner. For example, SEC and PEI
+ environments may access memory directly to read the contents of a PE/COFF image, and DXE or UEFI
+ environments may require protocol services to read the contents of PE/COFF image
+ stored on FLASH, disk, or network devices.
+
+ If FileHandle is not a valid handle, then ASSERT().
+ If ReadSize is NULL, then ASSERT().
+ If Buffer is NULL, then ASSERT().
+
+ @param FileHandle Pointer to the file handle to read the PE/COFF image.
+ @param FileOffset Offset into the PE/COFF image to begin the read operation.
+ @param ReadSize On input, the size in bytes of the requested read operation.
+ On output, the number of bytes actually read.
+ @param Buffer Output buffer that contains the data read from the PE/COFF image.
+
+ @retval RETURN_SUCCESS The specified portion of the PE/COFF image was
+ read and the size return in ReadSize.
+ @retval RETURN_DEVICE_ERROR The specified portion of the PE/COFF image
+ could not be read due to a device error.
+
+**/
+typedef
+RETURN_STATUS
+(EFIAPI *PE_COFF_LOADER_READ_FILE)(
+ IN VOID *FileHandle,
+ IN UINTN FileOffset,
+ IN OUT UINTN *ReadSize,
+ OUT VOID *Buffer
+ );
+
+///
+/// The context structure used while PE/COFF image is being loaded and relocated.
+///
+typedef struct {
+ ///
+ /// Set by PeCoffLoaderGetImageInfo() to the ImageBase in the PE/COFF header.
+ ///
+ PHYSICAL_ADDRESS ImageAddress;
+ ///
+ /// Set by PeCoffLoaderGetImageInfo() to the SizeOfImage in the PE/COFF header.
+ /// Image size includes the size of Debug Entry if it is present.
+ ///
+ UINT64 ImageSize;
+ ///
+ /// Is set to zero by PeCoffLoaderGetImageInfo(). If DestinationAddress is non-zero,
+ /// PeCoffLoaderRelocateImage() will relocate the image using this base address.
+ /// If the DestinationAddress is zero, the ImageAddress will be used as the base
+ /// address of relocation.
+ ///
+ PHYSICAL_ADDRESS DestinationAddress;
+ ///
+ /// PeCoffLoaderLoadImage() sets EntryPoint to to the entry point of the PE/COFF image.
+ ///
+ PHYSICAL_ADDRESS EntryPoint;
+ ///
+ /// Passed in by the caller to PeCoffLoaderGetImageInfo() and PeCoffLoaderLoadImage()
+ /// to abstract accessing the image from the library.
+ ///
+ PE_COFF_LOADER_READ_FILE ImageRead;
+ ///
+ /// Used as the FileHandle passed into the ImageRead function when it's called.
+ ///
+ VOID *Handle;
+ ///
+ /// Caller allocated buffer of size FixupDataSize that can be optionally allocated
+ /// prior to calling PeCoffLoaderRelocateImage().
+ /// This buffer is filled with the information used to fix up the image.
+ /// The fixups have been applied to the image and this entry is just for information.
+ ///
+ VOID *FixupData;
+ ///
+ /// Set by PeCoffLoaderGetImageInfo() to the Section Alignment in the PE/COFF header.
+ /// If the image is a TE image, then this field is set to 0.
+ ///
+ UINT32 SectionAlignment;
+ ///
+ /// Set by PeCoffLoaderGetImageInfo() to offset to the PE/COFF header.
+ /// If the PE/COFF image does not start with a DOS header, this value is zero.
+ /// Otherwise, it's the offset to the PE/COFF header.
+ ///
+ UINT32 PeCoffHeaderOffset;
+ ///
+ /// Set by PeCoffLoaderGetImageInfo() to the Relative Virtual Address of the debug directory,
+ /// if it exists in the image
+ ///
+ UINT32 DebugDirectoryEntryRva;
+ ///
+ /// Set by PeCoffLoaderLoadImage() to CodeView area of the PE/COFF Debug directory.
+ ///
+ VOID *CodeView;
+ ///
+ /// Set by PeCoffLoaderLoadImage() to point to the PDB entry contained in the CodeView area.
+ /// The PdbPointer points to the filename of the PDB file used for source-level debug of
+ /// the image by a debugger.
+ ///
+ CHAR8 *PdbPointer;
+ ///
+ /// Is set by PeCoffLoaderGetImageInfo() to the Section Alignment in the PE/COFF header.
+ ///
+ UINTN SizeOfHeaders;
+ ///
+ /// Not used by this library class. Other library classes that layer on top of this library
+ /// class fill in this value as part of their GetImageInfo call.
+ /// This allows the caller of the library to know what type of memory needs to be allocated
+ /// to load and relocate the image.
+ ///
+ UINT32 ImageCodeMemoryType;
+ ///
+ /// Not used by this library class. Other library classes that layer on top of this library
+ /// class fill in this value as part of their GetImageInfo call.
+ /// This allows the caller of the library to know what type of memory needs to be allocated
+ /// to load and relocate the image.
+ ///
+ UINT32 ImageDataMemoryType;
+ ///
+ /// Set by any of the library functions if they encounter an error.
+ ///
+ UINT32 ImageError;
+ ///
+ /// Set by PeCoffLoaderLoadImage() to indicate the size of FixupData that the caller must
+ /// allocate before calling PeCoffLoaderRelocateImage().
+ ///
+ UINTN FixupDataSize;
+ ///
+ /// Set by PeCoffLoaderGetImageInfo() to the machine type stored in the PE/COFF header.
+ ///
+ UINT16 Machine;
+ ///
+ /// Set by PeCoffLoaderGetImageInfo() to the subsystem type stored in the PE/COFF header.
+ ///
+ UINT16 ImageType;
+ ///
+ /// Set by PeCoffLoaderGetImageInfo() to TRUE if the PE/COFF image does not contain
+ /// relocation information.
+ ///
+ BOOLEAN RelocationsStripped;
+ ///
+ /// Set by PeCoffLoaderGetImageInfo() to TRUE if the image is a TE image.
+ /// For a definition of the TE Image format, see the Platform Initialization Pre-EFI
+ /// Initialization Core Interface Specification.
+ ///
+ BOOLEAN IsTeImage;
+ ///
+ /// Set by PeCoffLoaderLoadImage() to the HII resource offset
+ /// if the image contains a custom PE/COFF resource with the type 'HII'.
+ /// Otherwise, the entry remains to be 0.
+ ///
+ PHYSICAL_ADDRESS HiiResourceData;
+ ///
+ /// Private storage for implementation specific data.
+ ///
+ UINT64 Context;
+} PE_COFF_LOADER_IMAGE_CONTEXT;
+
+/**
+ Retrieves information about a PE/COFF image.
+
+ Computes the PeCoffHeaderOffset, IsTeImage, ImageType, ImageAddress, ImageSize,
+ DestinationAddress, RelocationsStripped, SectionAlignment, SizeOfHeaders, and
+ DebugDirectoryEntryRva fields of the ImageContext structure.
+ If ImageContext is NULL, then return RETURN_INVALID_PARAMETER.
+ If the PE/COFF image accessed through the ImageRead service in the ImageContext
+ structure is not a supported PE/COFF image type, then return RETURN_UNSUPPORTED.
+ If any errors occur while computing the fields of ImageContext,
+ then the error status is returned in the ImageError field of ImageContext.
+ If the image is a TE image, then SectionAlignment is set to 0.
+ The ImageRead and Handle fields of ImageContext structure must be valid prior
+ to invoking this service.
+
+ @param ImageContext The pointer to the image context structure that
+ describes the PE/COFF image that needs to be
+ examined by this function.
+
+ @retval RETURN_SUCCESS The information on the PE/COFF image was collected.
+ @retval RETURN_INVALID_PARAMETER ImageContext is NULL.
+ @retval RETURN_UNSUPPORTED The PE/COFF image is not supported.
+
+**/
+RETURN_STATUS
+EFIAPI
+PeCoffLoaderGetImageInfo (
+ IN OUT PE_COFF_LOADER_IMAGE_CONTEXT *ImageContext
+ );
+
+/**
+ Applies relocation fixups to a PE/COFF image that was loaded with PeCoffLoaderLoadImage().
+
+ If the DestinationAddress field of ImageContext is 0, then use the ImageAddress field of
+ ImageContext as the relocation base address. Otherwise, use the DestinationAddress field
+ of ImageContext as the relocation base address. The caller must allocate the relocation
+ fixup log buffer and fill in the FixupData field of ImageContext prior to calling this function.
+
+ The ImageRead, Handle, PeCoffHeaderOffset, IsTeImage, Machine, ImageType, ImageAddress,
+ ImageSize, DestinationAddress, RelocationsStripped, SectionAlignment, SizeOfHeaders,
+ DebugDirectoryEntryRva, EntryPoint, FixupDataSize, CodeView, PdbPointer, and FixupData of
+ the ImageContext structure must be valid prior to invoking this service.
+
+ If ImageContext is NULL, then ASSERT().
+
+ Note that if the platform does not maintain coherency between the instruction cache(s) and the data
+ cache(s) in hardware, then the caller is responsible for performing cache maintenance operations
+ prior to transferring control to a PE/COFF image that is loaded using this library.
+
+ @param ImageContext The pointer to the image context structure that describes the PE/COFF
+ image that is being relocated.
+
+ @retval RETURN_SUCCESS The PE/COFF image was relocated.
+ Extended status information is in the ImageError field of ImageContext.
+ @retval RETURN_LOAD_ERROR The image in not a valid PE/COFF image.
+ Extended status information is in the ImageError field of ImageContext.
+ @retval RETURN_UNSUPPORTED A relocation record type is not supported.
+ Extended status information is in the ImageError field of ImageContext.
+
+**/
+RETURN_STATUS
+EFIAPI
+PeCoffLoaderRelocateImage (
+ IN OUT PE_COFF_LOADER_IMAGE_CONTEXT *ImageContext
+ );
+
+/**
+ Loads a PE/COFF image into memory.
+
+ Loads the PE/COFF image accessed through the ImageRead service of ImageContext into the buffer
+ specified by the ImageAddress and ImageSize fields of ImageContext. The caller must allocate
+ the load buffer and fill in the ImageAddress and ImageSize fields prior to calling this function.
+ The EntryPoint, FixupDataSize, CodeView, PdbPointer and HiiResourceData fields of ImageContext are computed.
+ The ImageRead, Handle, PeCoffHeaderOffset, IsTeImage, Machine, ImageType, ImageAddress, ImageSize,
+ DestinationAddress, RelocationsStripped, SectionAlignment, SizeOfHeaders, and DebugDirectoryEntryRva
+ fields of the ImageContext structure must be valid prior to invoking this service.
+
+ If ImageContext is NULL, then ASSERT().
+
+ Note that if the platform does not maintain coherency between the instruction cache(s) and the data
+ cache(s) in hardware, then the caller is responsible for performing cache maintenance operations
+ prior to transferring control to a PE/COFF image that is loaded using this library.
+
+ @param ImageContext The pointer to the image context structure that describes the PE/COFF
+ image that is being loaded.
+
+ @retval RETURN_SUCCESS The PE/COFF image was loaded into the buffer specified by
+ the ImageAddress and ImageSize fields of ImageContext.
+ Extended status information is in the ImageError field of ImageContext.
+ @retval RETURN_BUFFER_TOO_SMALL The caller did not provide a large enough buffer.
+ Extended status information is in the ImageError field of ImageContext.
+ @retval RETURN_LOAD_ERROR The PE/COFF image is an EFI Runtime image with no relocations.
+ Extended status information is in the ImageError field of ImageContext.
+ @retval RETURN_INVALID_PARAMETER The image address is invalid.
+ Extended status information is in the ImageError field of ImageContext.
+
+**/
+RETURN_STATUS
+EFIAPI
+PeCoffLoaderLoadImage (
+ IN OUT PE_COFF_LOADER_IMAGE_CONTEXT *ImageContext
+ );
+
+/**
+ Reads contents of a PE/COFF image from a buffer in system memory.
+
+ This is the default implementation of a PE_COFF_LOADER_READ_FILE function
+ that assumes FileHandle pointer to the beginning of a PE/COFF image.
+ This function reads contents of the PE/COFF image that starts at the system memory
+ address specified by FileHandle. The read operation copies ReadSize bytes from the
+ PE/COFF image starting at byte offset FileOffset into the buffer specified by Buffer.
+ The size of the buffer actually read is returned in ReadSize.
+
+ If FileHandle is NULL, then ASSERT().
+ If ReadSize is NULL, then ASSERT().
+ If Buffer is NULL, then ASSERT().
+
+ @param FileHandle The pointer to base of the input stream
+ @param FileOffset Offset into the PE/COFF image to begin the read operation.
+ @param ReadSize On input, the size in bytes of the requested read operation.
+ On output, the number of bytes actually read.
+ @param Buffer Output buffer that contains the data read from the PE/COFF image.
+
+ @retval RETURN_SUCCESS The data is read from FileOffset from the Handle into
+ the buffer.
+**/
+RETURN_STATUS
+EFIAPI
+PeCoffLoaderImageReadFromMemory (
+ IN VOID *FileHandle,
+ IN UINTN FileOffset,
+ IN OUT UINTN *ReadSize,
+ OUT VOID *Buffer
+ );
+
+/**
+ Reapply fixups on a fixed up PE32/PE32+ image to allow virtual calling at EFI
+ runtime.
+
+ This function reapplies relocation fixups to the PE/COFF image specified by ImageBase
+ and ImageSize so the image will execute correctly when the PE/COFF image is mapped
+ to the address specified by VirtualImageBase. RelocationData must be identical
+ to the FiuxupData buffer from the PE_COFF_LOADER_IMAGE_CONTEXT structure
+ after this PE/COFF image was relocated with PeCoffLoaderRelocateImage().
+
+ Note that if the platform does not maintain coherency between the instruction cache(s) and the data
+ cache(s) in hardware, then the caller is responsible for performing cache maintenance operations
+ prior to transferring control to a PE/COFF image that is loaded using this library.
+
+ @param ImageBase The base address of a PE/COFF image that has been loaded
+ and relocated into system memory.
+ @param VirtImageBase The request virtual address that the PE/COFF image is to
+ be fixed up for.
+ @param ImageSize The size, in bytes, of the PE/COFF image.
+ @param RelocationData A pointer to the relocation data that was collected when the PE/COFF
+ image was relocated using PeCoffLoaderRelocateImage().
+
+**/
+VOID
+EFIAPI
+PeCoffLoaderRelocateImageForRuntime (
+ IN PHYSICAL_ADDRESS ImageBase,
+ IN PHYSICAL_ADDRESS VirtImageBase,
+ IN UINTN ImageSize,
+ IN VOID *RelocationData
+ );
+
+/**
+ Unloads a loaded PE/COFF image from memory and releases its taken resource.
+ Releases any environment specific resources that were allocated when the image
+ specified by ImageContext was loaded using PeCoffLoaderLoadImage().
+
+ For NT32 emulator, the PE/COFF image loaded by system needs to release.
+ For real platform, the PE/COFF image loaded by Core doesn't needs to be unloaded,
+ this function can simply return RETURN_SUCCESS.
+
+ If ImageContext is NULL, then ASSERT().
+
+ @param ImageContext Pointer to the image context structure that describes the PE/COFF
+ image to be unloaded.
+
+ @retval RETURN_SUCCESS The PE/COFF image was unloaded successfully.
+**/
+RETURN_STATUS
+EFIAPI
+PeCoffLoaderUnloadImage (
+ IN OUT PE_COFF_LOADER_IMAGE_CONTEXT *ImageContext
+ );
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/PeiCoreEntryPoint.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/PeiCoreEntryPoint.h
new file mode 100644
index 0000000000..e83f59e216
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/PeiCoreEntryPoint.h
@@ -0,0 +1,131 @@
+/** @file
+ Module entry point library for PEI core.
+
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __MODULE_ENTRY_POINT_H__
+#define __MODULE_ENTRY_POINT_H__
+
+/**
+ The entry point of PE/COFF Image for the PEI Core.
+
+ This function is the entry point for the PEI Foundation, which allows the SEC phase
+ to pass information about the stack, temporary RAM and the Boot Firmware Volume.
+ In addition, it also allows the SEC phase to pass services and data forward for use
+ during the PEI phase in the form of one or more PPIs.
+ There is no limit to the number of additional PPIs that can be passed from SEC into
+ the PEI Foundation. As part of its initialization phase, the PEI Foundation will add
+ these SEC-hosted PPIs to its PPI database such that both the PEI Foundation and any
+ modules can leverage the associated service calls and/or code in these early PPIs.
+ This function is required to call ProcessModuleEntryPointList() with the Context
+ parameter set to NULL. ProcessModuleEntryPoint() is never expected to return.
+ The PEI Core is responsible for calling ProcessLibraryConstructorList() as soon as
+ the PEI Services Table and the file handle for the PEI Core itself have been established.
+ If ProcessModuleEntryPointList() returns, then ASSERT() and halt the system.
+
+ @param SecCoreData Points to a data structure containing information about the PEI
+ core's operating environment, such as the size and location of
+ temporary RAM, the stack location and the BFV location.
+
+ @param PpiList Points to a list of one or more PPI descriptors to be installed
+ initially by the PEI core. An empty PPI list consists of a single
+ descriptor with the end-tag EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST.
+ As part of its initialization phase, the PEI Foundation will add
+ these SEC-hosted PPIs to its PPI database such that both the PEI
+ Foundation and any modules can leverage the associated service calls
+ and/or code in these early PPIs.
+
+**/
+VOID
+EFIAPI
+_ModuleEntryPoint (
+ IN CONST EFI_SEC_PEI_HAND_OFF *SecCoreData,
+ IN CONST EFI_PEI_PPI_DESCRIPTOR *PpiList
+ );
+
+/**
+ Required by the EBC compiler and identical in functionality to _ModuleEntryPoint().
+
+ This function is required to call _ModuleEntryPoint() passing in SecCoreData and PpiList.
+
+ @param SecCoreData Points to a data structure containing information about the PEI core's
+ operating environment, such as the size and location of temporary RAM,
+ the stack location and the BFV location.
+
+ @param PpiList Points to a list of one or more PPI descriptors to be installed
+ initially by the PEI core. An empty PPI list consists of a single
+ descriptor with the end-tag EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST.
+ As part of its initialization phase, the PEI Foundation will add these
+ SEC-hosted PPIs to its PPI database such that both the PEI Foundation
+ and any modules can leverage the associated service calls and/or code
+ in these early PPIs.
+
+**/
+VOID
+EFIAPI
+EfiMain (
+ IN CONST EFI_SEC_PEI_HAND_OFF *SecCoreData,
+ IN CONST EFI_PEI_PPI_DESCRIPTOR *PpiList
+ );
+
+/**
+ Autogenerated function that calls the library constructors for all of the module's
+ dependent libraries.
+
+ This function must be called by the PEI Core once an initial PEI Services Table has been established.
+ This function calls the set of library constructors for the set of library instances that a
+ module depends on. This include library instances that a module depends on directly and library
+ instances that a module depends on indirectly through other libraries.
+ This function is autogenerated by build tools and those build tools are responsible for collecting
+ the set of library instances, determining which ones have constructors, and calling the library
+ constructors in the proper order based upon the dependencies of each of the library instances.
+ The PEI Core must call this function with a NULL FileHandle value as soon as the initial PEI
+ Services Table has been established.
+
+ @param FileHandle Handle of the file being invoked.
+ @param PeiServices Describes the list of possible PEI Services.
+
+**/
+VOID
+EFIAPI
+ProcessLibraryConstructorList (
+ IN EFI_PEI_FILE_HANDLE FileHandle,
+ IN CONST EFI_PEI_SERVICES **PeiServices
+ );
+
+/**
+ Autogenerated function that calls a set of module entry points.
+
+ This function must be called by _ModuleEntryPoint().
+ This function calls the set of module entry points.
+ This function is autogenerated by build tools and those build tools are responsible
+ for collecting the module entry points and calling them in a specified order.
+
+ @param SecCoreData Points to a data structure containing information about the PEI
+ core's operating environment, such as the size and location of
+ temporary RAM, the stack location and the BFV location.
+
+ @param PpiList Points to a list of one or more PPI descriptors to be installed
+ initially by the PEI core. An empty PPI list consists of a single
+ descriptor with the end-tag EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST.
+ As part of its initialization phase, the PEI Foundation will add
+ these SEC-hosted PPIs to its PPI database such that both the PEI
+ Foundation and any modules can leverage the associated service calls
+ and/or code in these early PPIs.
+ @param Context A pointer to a private context structure defined by the PEI Core
+ implementation. The implementation of _ModuleEntryPoint() must set
+ this parameter is NULL to indicate that this is the first PEI phase.
+
+**/
+VOID
+EFIAPI
+ProcessModuleEntryPointList (
+ IN CONST EFI_SEC_PEI_HAND_OFF *SecCoreData,
+ IN CONST EFI_PEI_PPI_DESCRIPTOR *PpiList,
+ IN VOID *Context
+ );
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/PeiServicesLib.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/PeiServicesLib.h
new file mode 100644
index 0000000000..d7c3a16119
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/PeiServicesLib.h
@@ -0,0 +1,556 @@
+/** @file
+ Provides library functions for all PEI Services.
+
+Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __PEI_SERVICES_LIB_H__
+#define __PEI_SERVICES_LIB_H__
+
+/**
+ This service enables a given PEIM to register an interface into the PEI Foundation.
+
+ @param PpiList A pointer to the list of interfaces that the caller shall install.
+
+ @retval EFI_SUCCESS The interface was successfully installed.
+ @retval EFI_INVALID_PARAMETER The PpiList pointer is NULL.
+ @retval EFI_INVALID_PARAMETER Any of the PEI PPI descriptors in the list do not have the
+ EFI_PEI_PPI_DESCRIPTOR_PPI bit set in the Flags field.
+ @retval EFI_OUT_OF_RESOURCES There is no additional space in the PPI database.
+
+**/
+EFI_STATUS
+EFIAPI
+PeiServicesInstallPpi (
+ IN CONST EFI_PEI_PPI_DESCRIPTOR *PpiList
+ );
+
+/**
+ This service enables PEIMs to replace an entry in the PPI database with an alternate entry.
+
+ @param OldPpi Pointer to the old PEI PPI Descriptors.
+ @param NewPpi Pointer to the new PEI PPI Descriptors.
+
+ @retval EFI_SUCCESS The interface was successfully installed.
+ @retval EFI_INVALID_PARAMETER The OldPpi or NewPpi is NULL.
+ @retval EFI_INVALID_PARAMETER Any of the PEI PPI descriptors in the list do not have the
+ EFI_PEI_PPI_DESCRIPTOR_PPI bit set in the Flags field.
+ @retval EFI_OUT_OF_RESOURCES There is no additional space in the PPI database.
+ @retval EFI_NOT_FOUND The PPI for which the reinstallation was requested has not been
+ installed.
+
+**/
+EFI_STATUS
+EFIAPI
+PeiServicesReInstallPpi (
+ IN CONST EFI_PEI_PPI_DESCRIPTOR *OldPpi,
+ IN CONST EFI_PEI_PPI_DESCRIPTOR *NewPpi
+ );
+
+/**
+ This service enables PEIMs to discover a given instance of an interface.
+
+ @param Guid A pointer to the GUID whose corresponding interface needs to be
+ found.
+ @param Instance The N-th instance of the interface that is required.
+ @param PpiDescriptor A pointer to instance of the EFI_PEI_PPI_DESCRIPTOR.
+ @param Ppi A pointer to the instance of the interface.
+
+ @retval EFI_SUCCESS The interface was successfully returned.
+ @retval EFI_NOT_FOUND The PPI descriptor is not found in the database.
+
+**/
+EFI_STATUS
+EFIAPI
+PeiServicesLocatePpi (
+ IN CONST EFI_GUID *Guid,
+ IN UINTN Instance,
+ IN OUT EFI_PEI_PPI_DESCRIPTOR **PpiDescriptor OPTIONAL,
+ IN OUT VOID **Ppi
+ );
+
+/**
+ This service enables PEIMs to register a given service to be invoked when another service is
+ installed or reinstalled.
+
+ @param NotifyList A pointer to the list of notification interfaces that the caller
+ shall install.
+
+ @retval EFI_SUCCESS The interface was successfully installed.
+ @retval EFI_INVALID_PARAMETER The NotifyList pointer is NULL.
+ @retval EFI_INVALID_PARAMETER Any of the PEI notify descriptors in the list do not have the
+ EFI_PEI_PPI_DESCRIPTOR_NOTIFY_TYPES bit set in the Flags field.
+ @retval EFI_OUT_OF_RESOURCES There is no additional space in the PPI database.
+
+**/
+EFI_STATUS
+EFIAPI
+PeiServicesNotifyPpi (
+ IN CONST EFI_PEI_NOTIFY_DESCRIPTOR *NotifyList
+ );
+
+/**
+ This service enables PEIMs to ascertain the present value of the boot mode.
+
+ @param BootMode A pointer to contain the value of the boot mode.
+
+ @retval EFI_SUCCESS The boot mode was returned successfully.
+ @retval EFI_INVALID_PARAMETER BootMode is NULL.
+
+**/
+EFI_STATUS
+EFIAPI
+PeiServicesGetBootMode (
+ OUT EFI_BOOT_MODE *BootMode
+ );
+
+/**
+ This service enables PEIMs to update the boot mode variable.
+
+ @param BootMode The value of the boot mode to set.
+
+ @retval EFI_SUCCESS The value was successfully updated
+
+**/
+EFI_STATUS
+EFIAPI
+PeiServicesSetBootMode (
+ IN EFI_BOOT_MODE BootMode
+ );
+
+/**
+ This service enables a PEIM to ascertain the address of the list of HOBs in memory.
+
+ @param HobList A pointer to the list of HOBs that the PEI Foundation will initialize.
+
+ @retval EFI_SUCCESS The list was successfully returned.
+ @retval EFI_NOT_AVAILABLE_YET The HOB list is not yet published.
+
+**/
+EFI_STATUS
+EFIAPI
+PeiServicesGetHobList (
+ OUT VOID **HobList
+ );
+
+/**
+ This service enables PEIMs to create various types of HOBs.
+
+ @param Type The type of HOB to be installed.
+ @param Length The length of the HOB to be added.
+ @param Hob The address of a pointer that will contain the HOB header.
+
+ @retval EFI_SUCCESS The HOB was successfully created.
+ @retval EFI_OUT_OF_RESOURCES There is no additional space for HOB creation.
+
+**/
+EFI_STATUS
+EFIAPI
+PeiServicesCreateHob (
+ IN UINT16 Type,
+ IN UINT16 Length,
+ OUT VOID **Hob
+ );
+
+/**
+ This service enables PEIMs to discover additional firmware volumes.
+
+ @param Instance This instance of the firmware volume to find. The value 0 is the
+ Boot Firmware Volume (BFV).
+ @param VolumeHandle Handle of the firmware volume header of the volume to return.
+
+ @retval EFI_SUCCESS The volume was found.
+ @retval EFI_NOT_FOUND The volume was not found.
+ @retval EFI_INVALID_PARAMETER FwVolHeader is NULL.
+
+**/
+EFI_STATUS
+EFIAPI
+PeiServicesFfsFindNextVolume (
+ IN UINTN Instance,
+ IN OUT EFI_PEI_FV_HANDLE *VolumeHandle
+ );
+
+/**
+ This service enables PEIMs to discover additional firmware files.
+
+ @param SearchType A filter to find files only of this type.
+ @param VolumeHandle Pointer to the firmware volume header of the volume to search.
+ This parameter must point to a valid FFS volume.
+ @param FileHandle Handle of the current file from which to begin searching.
+
+ @retval EFI_SUCCESS The file was found.
+ @retval EFI_NOT_FOUND The file was not found.
+ @retval EFI_NOT_FOUND The header checksum was not zero.
+
+**/
+EFI_STATUS
+EFIAPI
+PeiServicesFfsFindNextFile (
+ IN EFI_FV_FILETYPE SearchType,
+ IN EFI_PEI_FV_HANDLE VolumeHandle,
+ IN OUT EFI_PEI_FILE_HANDLE *FileHandle
+ );
+
+/**
+ This service enables PEIMs to discover sections of a given type within a valid FFS file.
+
+ @param SectionType The value of the section type to find.
+ @param FileHandle A pointer to the file header that contains the set of sections to
+ be searched.
+ @param SectionData A pointer to the discovered section, if successful.
+
+ @retval EFI_SUCCESS The section was found.
+ @retval EFI_NOT_FOUND The section was not found.
+
+**/
+EFI_STATUS
+EFIAPI
+PeiServicesFfsFindSectionData (
+ IN EFI_SECTION_TYPE SectionType,
+ IN EFI_PEI_FILE_HANDLE FileHandle,
+ OUT VOID **SectionData
+ );
+
+/**
+ This service enables PEIMs to discover sections of a given instance and type within a valid FFS file.
+
+ @param SectionType The value of the section type to find.
+ @param SectionInstance Section instance to find.
+ @param FileHandle A pointer to the file header that contains the set
+ of sections to be searched.
+ @param SectionData A pointer to the discovered section, if successful.
+ @param AuthenticationStatus A pointer to the authentication status for this section.
+
+ @retval EFI_SUCCESS The section was found.
+ @retval EFI_NOT_FOUND The section was not found.
+
+**/
+EFI_STATUS
+EFIAPI
+PeiServicesFfsFindSectionData3 (
+ IN EFI_SECTION_TYPE SectionType,
+ IN UINTN SectionInstance,
+ IN EFI_PEI_FILE_HANDLE FileHandle,
+ OUT VOID **SectionData,
+ OUT UINT32 *AuthenticationStatus
+ );
+
+/**
+ This service enables PEIMs to register the permanent memory configuration
+ that has been initialized with the PEI Foundation.
+
+ @param MemoryBegin The value of a region of installed memory.
+ @param MemoryLength The corresponding length of a region of installed memory.
+
+ @retval EFI_SUCCESS The region was successfully installed in a HOB.
+ @retval EFI_INVALID_PARAMETER MemoryBegin and MemoryLength are illegal for this system.
+ @retval EFI_OUT_OF_RESOURCES There is no additional space for HOB creation.
+
+**/
+EFI_STATUS
+EFIAPI
+PeiServicesInstallPeiMemory (
+ IN EFI_PHYSICAL_ADDRESS MemoryBegin,
+ IN UINT64 MemoryLength
+ );
+
+/**
+ This service enables PEIMs to allocate memory.
+
+ @param MemoryType Type of memory to allocate.
+ @param Pages The number of pages to allocate.
+ @param Memory Pointer of memory allocated.
+
+ @retval EFI_SUCCESS The memory range was successfully allocated.
+ @retval EFI_INVALID_PARAMETER Type is not equal to EfiLoaderCode, EfiLoaderData, EfiRuntimeServicesCode,
+ EfiRuntimeServicesData, EfiBootServicesCode, EfiBootServicesData,
+ EfiACPIReclaimMemory, EfiReservedMemoryType, or EfiACPIMemoryNVS.
+ @retval EFI_OUT_OF_RESOURCES The pages could not be allocated.
+
+**/
+EFI_STATUS
+EFIAPI
+PeiServicesAllocatePages (
+ IN EFI_MEMORY_TYPE MemoryType,
+ IN UINTN Pages,
+ OUT EFI_PHYSICAL_ADDRESS *Memory
+ );
+
+/**
+ This service enables PEIMs to free memory.
+
+ @param Memory Memory to be freed.
+ @param Pages The number of pages to free.
+
+ @retval EFI_SUCCESS The requested pages were freed.
+ @retval EFI_INVALID_PARAMETER Memory is not a page-aligned address or Pages is invalid.
+ @retval EFI_NOT_FOUND The requested memory pages were not allocated with
+ AllocatePages().
+
+**/
+EFI_STATUS
+EFIAPI
+PeiServicesFreePages (
+ IN EFI_PHYSICAL_ADDRESS Memory,
+ IN UINTN Pages
+ );
+
+/**
+ This service allocates memory from the Hand-Off Block (HOB) heap.
+
+ @param Size The number of bytes to allocate from the pool.
+ @param Buffer If the call succeeds, a pointer to a pointer to the allocate
+ buffer; undefined otherwise.
+
+ @retval EFI_SUCCESS The allocation was successful
+ @retval EFI_OUT_OF_RESOURCES There is not enough heap to allocate the requested size.
+
+**/
+EFI_STATUS
+EFIAPI
+PeiServicesAllocatePool (
+ IN UINTN Size,
+ OUT VOID **Buffer
+ );
+
+/**
+ Resets the entire platform.
+
+ @retval EFI_SUCCESS The function completed successfully.
+ @retval EFI_NOT_AVAILABLE_YET The service has not been installed yet.
+
+**/
+EFI_STATUS
+EFIAPI
+PeiServicesResetSystem (
+ VOID
+ );
+
+/**
+ This service is a wrapper for the PEI Service FfsFindByName(), except the pointer to the PEI Services
+ Table has been removed. See the Platform Initialization Pre-EFI Initialization Core Interface
+ Specification for details.
+
+ @param FileName A pointer to the name of the file to
+ find within the firmware volume.
+
+ @param VolumeHandle The firmware volume to search FileHandle
+ Upon exit, points to the found file's
+ handle or NULL if it could not be found.
+ @param FileHandle Pointer to found file handle
+
+ @retval EFI_SUCCESS File was found.
+
+ @retval EFI_NOT_FOUND File was not found.
+
+ @retval EFI_INVALID_PARAMETER VolumeHandle or FileHandle or
+ FileName was NULL.
+
+**/
+EFI_STATUS
+EFIAPI
+PeiServicesFfsFindFileByName (
+ IN CONST EFI_GUID *FileName,
+ IN CONST EFI_PEI_FV_HANDLE VolumeHandle,
+ OUT EFI_PEI_FILE_HANDLE *FileHandle
+ );
+
+/**
+ This service is a wrapper for the PEI Service FfsGetFileInfo(), except the pointer to the PEI Services
+ Table has been removed. See the Platform Initialization Pre-EFI Initialization Core Interface
+ Specification for details.
+
+ @param FileHandle Handle of the file.
+
+ @param FileInfo Upon exit, points to the file's
+ information.
+
+ @retval EFI_SUCCESS File information returned.
+
+ @retval EFI_INVALID_PARAMETER If FileHandle does not
+ represent a valid file.
+
+ @retval EFI_INVALID_PARAMETER If FileInfo is NULL.
+
+**/
+EFI_STATUS
+EFIAPI
+PeiServicesFfsGetFileInfo (
+ IN CONST EFI_PEI_FILE_HANDLE FileHandle,
+ OUT EFI_FV_FILE_INFO *FileInfo
+ );
+
+/**
+ This service is a wrapper for the PEI Service FfsGetFileInfo2(), except the pointer to the PEI Services
+ Table has been removed. See the Platform Initialization Pre-EFI Initialization Core Interface
+ Specification for details.
+
+ @param FileHandle Handle of the file.
+
+ @param FileInfo Upon exit, points to the file's
+ information.
+
+ @retval EFI_SUCCESS File information returned.
+
+ @retval EFI_INVALID_PARAMETER If FileHandle does not
+ represent a valid file.
+
+ @retval EFI_INVALID_PARAMETER If FileInfo is NULL.
+
+**/
+EFI_STATUS
+EFIAPI
+PeiServicesFfsGetFileInfo2 (
+ IN CONST EFI_PEI_FILE_HANDLE FileHandle,
+ OUT EFI_FV_FILE_INFO2 *FileInfo
+ );
+
+/**
+ This service is a wrapper for the PEI Service FfsGetVolumeInfo(), except the pointer to the PEI Services
+ Table has been removed. See the Platform Initialization Pre-EFI Initialization Core Interface
+ Specification for details.
+
+ @param VolumeHandle Handle of the volume.
+
+ @param VolumeInfo Upon exit, points to the volume's
+ information.
+
+ @retval EFI_SUCCESS File information returned.
+
+ @retval EFI_INVALID_PARAMETER If FileHandle does not
+ represent a valid file.
+
+ @retval EFI_INVALID_PARAMETER If FileInfo is NULL.
+
+**/
+EFI_STATUS
+EFIAPI
+PeiServicesFfsGetVolumeInfo (
+ IN EFI_PEI_FV_HANDLE VolumeHandle,
+ OUT EFI_FV_INFO *VolumeInfo
+ );
+
+/**
+ This service is a wrapper for the PEI Service RegisterForShadow(), except the pointer to the PEI Services
+ Table has been removed. See the Platform Initialization Pre-EFI Initialization Core Interface
+ Specification for details.
+
+ @param FileHandle PEIM's file handle. Must be the currently
+ executing PEIM.
+
+ @retval EFI_SUCCESS The PEIM was successfully registered for
+ shadowing.
+
+ @retval EFI_ALREADY_STARTED The PEIM was previously
+ registered for shadowing.
+
+ @retval EFI_NOT_FOUND The FileHandle does not refer to a
+ valid file handle.
+**/
+EFI_STATUS
+EFIAPI
+PeiServicesRegisterForShadow (
+ IN EFI_PEI_FILE_HANDLE FileHandle
+ );
+
+/**
+ Install a EFI_PEI_FIRMWARE_VOLUME_INFO_PPI instance so the PEI Core will be notified about a new firmware volume.
+
+ This function allocates, initializes, and installs a new EFI_PEI_FIRMWARE_VOLUME_INFO_PPI using
+ the parameters passed in to initialize the fields of the EFI_PEI_FIRMWARE_VOLUME_INFO_PPI instance.
+ If the resources can not be allocated for EFI_PEI_FIRMWARE_VOLUME_INFO_PPI, then ASSERT().
+ If the EFI_PEI_FIRMWARE_VOLUME_INFO_PPI can not be installed, then ASSERT().
+
+
+ @param FvFormat Unique identifier of the format of the memory-mapped firmware volume.
+ This parameter is optional and may be NULL.
+ If NULL is specified, the EFI_FIRMWARE_FILE_SYSTEM2_GUID format is assumed.
+ @param FvInfo Points to a buffer which allows the EFI_PEI_FIRMWARE_VOLUME_PPI to process the volume.
+ The format of this buffer is specific to the FvFormat. For memory-mapped firmware volumes,
+ this typically points to the first byte of the firmware volume.
+ @param FvInfoSize The size, in bytes, of FvInfo. For memory-mapped firmware volumes,
+ this is typically the size of the firmware volume.
+ @param ParentFvName If the new firmware volume originated from a file in a different firmware volume,
+ then this parameter specifies the GUID name of the originating firmware volume.
+ Otherwise, this parameter must be NULL.
+ @param ParentFileName If the new firmware volume originated from a file in a different firmware volume,
+ then this parameter specifies the GUID file name of the originating firmware file.
+ Otherwise, this parameter must be NULL.
+**/
+VOID
+EFIAPI
+PeiServicesInstallFvInfoPpi (
+ IN CONST EFI_GUID *FvFormat OPTIONAL,
+ IN CONST VOID *FvInfo,
+ IN UINT32 FvInfoSize,
+ IN CONST EFI_GUID *ParentFvName OPTIONAL,
+ IN CONST EFI_GUID *ParentFileName OPTIONAL
+ );
+
+/**
+ Install a EFI_PEI_FIRMWARE_VOLUME_INFO2_PPI instance so the PEI Core will be notified about a new firmware volume.
+
+ This function allocates, initializes, and installs a new EFI_PEI_FIRMWARE_VOLUME_INFO2_PPI using
+ the parameters passed in to initialize the fields of the EFI_PEI_FIRMWARE_VOLUME_INFO2_PPI instance.
+ If the resources can not be allocated for EFI_PEI_FIRMWARE_VOLUME_INFO2_PPI, then ASSERT().
+ If the EFI_PEI_FIRMWARE_VOLUME_INFO2_PPI can not be installed, then ASSERT().
+
+ @param FvFormat Unique identifier of the format of the memory-mapped
+ firmware volume. This parameter is optional and
+ may be NULL. If NULL is specified, the
+ EFI_FIRMWARE_FILE_SYSTEM2_GUID format is assumed.
+ @param FvInfo Points to a buffer which allows the
+ EFI_PEI_FIRMWARE_VOLUME_PPI to process the volume.
+ The format of this buffer is specific to the FvFormat.
+ For memory-mapped firmware volumes, this typically
+ points to the first byte of the firmware volume.
+ @param FvInfoSize The size, in bytes, of FvInfo. For memory-mapped
+ firmware volumes, this is typically the size of
+ the firmware volume.
+ @param ParentFvName If the new firmware volume originated from a file
+ in a different firmware volume, then this parameter
+ specifies the GUID name of the originating firmware
+ volume. Otherwise, this parameter must be NULL.
+ @param ParentFileName If the new firmware volume originated from a file
+ in a different firmware volume, then this parameter
+ specifies the GUID file name of the originating
+ firmware file. Otherwise, this parameter must be NULL.
+ @param AuthenticationStatus Authentication Status
+**/
+VOID
+EFIAPI
+PeiServicesInstallFvInfo2Ppi (
+ IN CONST EFI_GUID *FvFormat OPTIONAL,
+ IN CONST VOID *FvInfo,
+ IN UINT32 FvInfoSize,
+ IN CONST EFI_GUID *ParentFvName OPTIONAL,
+ IN CONST EFI_GUID *ParentFileName OPTIONAL,
+ IN UINT32 AuthenticationStatus
+ );
+
+/**
+ Resets the entire platform.
+
+ @param[in] ResetType The type of reset to perform.
+ @param[in] ResetStatus The status code for the reset.
+ @param[in] DataSize The size, in bytes, of ResetData.
+ @param[in] ResetData For a ResetType of EfiResetCold, EfiResetWarm, or EfiResetShutdown
+ the data buffer starts with a Null-terminated string, optionally
+ followed by additional binary data. The string is a description
+ that the caller may use to further indicate the reason for the
+ system reset.
+
+**/
+VOID
+EFIAPI
+PeiServicesResetSystem2 (
+ IN EFI_RESET_TYPE ResetType,
+ IN EFI_STATUS ResetStatus,
+ IN UINTN DataSize,
+ IN VOID *ResetData OPTIONAL
+ );
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/PeiServicesTablePointerLib.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/PeiServicesTablePointerLib.h
new file mode 100644
index 0000000000..922891b21f
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/PeiServicesTablePointerLib.h
@@ -0,0 +1,67 @@
+/** @file
+ Provides a service to retrieve a pointer to the PEI Services Table.
+
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __PEI_SERVICES_TABLE_POINTER_LIB_H__
+#define __PEI_SERVICES_TABLE_POINTER_LIB_H__
+
+/**
+ Retrieves the cached value of the PEI Services Table pointer.
+
+ Returns the cached value of the PEI Services Table pointer in a CPU specific manner
+ as specified in the CPU binding section of the Platform Initialization Pre-EFI
+ Initialization Core Interface Specification.
+
+ If the cached PEI Services Table pointer is NULL, then ASSERT().
+
+ @return The pointer to PeiServices.
+
+**/
+CONST EFI_PEI_SERVICES **
+EFIAPI
+GetPeiServicesTablePointer (
+ VOID
+ );
+
+/**
+ Caches a pointer PEI Services Table.
+
+ Caches the pointer to the PEI Services Table specified by PeiServicesTablePointer
+ in a CPU specific manner as specified in the CPU binding section of the Platform Initialization
+ Pre-EFI Initialization Core Interface Specification.
+
+ If PeiServicesTablePointer is NULL, then ASSERT().
+
+ @param PeiServicesTablePointer The address of PeiServices pointer.
+**/
+VOID
+EFIAPI
+SetPeiServicesTablePointer (
+ IN CONST EFI_PEI_SERVICES **PeiServicesTablePointer
+ );
+
+/**
+ Perform CPU specific actions required to migrate the PEI Services Table
+ pointer from temporary RAM to permanent RAM.
+
+ For IA32 CPUs, the PEI Services Table pointer is stored in the 4 bytes
+ immediately preceding the Interrupt Descriptor Table (IDT) in memory.
+ For X64 CPUs, the PEI Services Table pointer is stored in the 8 bytes
+ immediately preceding the Interrupt Descriptor Table (IDT) in memory.
+ For Itanium and ARM CPUs, a the PEI Services Table Pointer is stored in
+ a dedicated CPU register. This means that there is no memory storage
+ associated with storing the PEI Services Table pointer, so no additional
+ migration actions are required for Itanium or ARM CPUs.
+
+**/
+VOID
+EFIAPI
+MigratePeiServicesTablePointer (
+ VOID
+ );
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/PeimEntryPoint.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/PeimEntryPoint.h
new file mode 100644
index 0000000000..7783800d38
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/PeimEntryPoint.h
@@ -0,0 +1,101 @@
+/** @file
+ Module entry point library for PEIM.
+
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __MODULE_ENTRY_POINT_H__
+#define __MODULE_ENTRY_POINT_H__
+
+///
+/// Declare the EFI/UEFI Specification Revision to which this driver is implemented
+///
+extern CONST UINT32 _gPeimRevision;
+
+/**
+ The entry point of PE/COFF Image for a PEIM.
+
+ This function is the entry point for a PEIM. This function must call ProcessLibraryConstructorList()
+ and ProcessModuleEntryPointList(). The return value from ProcessModuleEntryPointList() is returned.
+ If _gPeimRevision is not zero and PeiServices->Hdr.Revision is less than _gPeimRevison, then ASSERT().
+
+ @param FileHandle Handle of the file being invoked.
+ @param PeiServices Describes the list of possible PEI Services.
+
+ @retval EFI_SUCCESS The PEIM executed normally.
+ @retval !EFI_SUCCESS The PEIM failed to execute normally.
+**/
+EFI_STATUS
+EFIAPI
+_ModuleEntryPoint (
+ IN EFI_PEI_FILE_HANDLE FileHandle,
+ IN CONST EFI_PEI_SERVICES **PeiServices
+ );
+
+/**
+ Required by the EBC compiler and identical in functionality to _ModuleEntryPoint().
+
+ This function is required to call _ModuleEntryPoint() passing in FileHandle and PeiServices.
+
+ @param FileHandle Handle of the file being invoked.
+ @param PeiServices Describes the list of possible PEI Services.
+
+ @retval EFI_SUCCESS The PEIM executed normally.
+ @retval !EFI_SUCCESS The PEIM failed to execute normally.
+
+**/
+EFI_STATUS
+EFIAPI
+EfiMain (
+ IN EFI_PEI_FILE_HANDLE FileHandle,
+ IN CONST EFI_PEI_SERVICES **PeiServices
+ );
+
+/**
+ Autogenerated function that calls the library constructors for all of the module's
+ dependent libraries.
+
+ This function must be called by _ModuleEntryPoint().
+ This function calls the set of library constructors for the set of library instances that a
+ module depends on. This includes library instances that a module depends on directly and library
+ instances that a module depends on indirectly through other libraries.
+ This function is autogenerated by build tools and those build tools are responsible for collecting
+ the set of library instances, determine which ones have constructors, and calling the library
+ constructors in the proper order based upon each of the library instances own dependencies.
+
+ @param FileHandle Handle of the file being invoked.
+ @param PeiServices Describes the list of possible PEI Services.
+
+**/
+VOID
+EFIAPI
+ProcessLibraryConstructorList (
+ IN EFI_PEI_FILE_HANDLE FileHandle,
+ IN CONST EFI_PEI_SERVICES **PeiServices
+ );
+
+/**
+ Autogenerated function that calls a set of module entry points.
+
+ This function must be called by _ModuleEntryPoint().
+ This function calls the set of module entry points.
+ This function is autogenerated by build tools and those build tools are responsible
+ for collecting the module entry points and calling them in a specified order.
+
+ @param FileHandle Handle of the file being invoked.
+ @param PeiServices Describes the list of possible PEI Services.
+
+ @retval EFI_SUCCESS The PEIM executed normally.
+ @retval !EFI_SUCCESS The PEIM failed to execute normally.
+
+**/
+EFI_STATUS
+EFIAPI
+ProcessModuleEntryPointList (
+ IN EFI_PEI_FILE_HANDLE FileHandle,
+ IN CONST EFI_PEI_SERVICES **PeiServices
+ );
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/PerformanceLib.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/PerformanceLib.h
new file mode 100644
index 0000000000..d27412b360
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/PerformanceLib.h
@@ -0,0 +1,764 @@
+/** @file
+ Provides services to log the execution times and retrieve them later.
+
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __PERFORMANCE_LIB_H__
+#define __PERFORMANCE_LIB_H__
+
+///
+/// Performance library propery mask bits
+///
+#define PERFORMANCE_LIBRARY_PROPERTY_MEASUREMENT_ENABLED 0x00000001
+
+//
+// Public Progress Identifiers for Event Records.
+//
+#define PERF_EVENT_ID 0x00
+
+#define MODULE_START_ID 0x01
+#define MODULE_END_ID 0x02
+#define MODULE_LOADIMAGE_START_ID 0x03
+#define MODULE_LOADIMAGE_END_ID 0x04
+#define MODULE_DB_START_ID 0x05
+#define MODULE_DB_END_ID 0x06
+#define MODULE_DB_SUPPORT_START_ID 0x07
+#define MODULE_DB_SUPPORT_END_ID 0x08
+#define MODULE_DB_STOP_START_ID 0x09
+#define MODULE_DB_STOP_END_ID 0x0A
+
+#define PERF_EVENTSIGNAL_START_ID 0x10
+#define PERF_EVENTSIGNAL_END_ID 0x11
+#define PERF_CALLBACK_START_ID 0x20
+#define PERF_CALLBACK_END_ID 0x21
+#define PERF_FUNCTION_START_ID 0x30
+#define PERF_FUNCTION_END_ID 0x31
+#define PERF_INMODULE_START_ID 0x40
+#define PERF_INMODULE_END_ID 0x41
+#define PERF_CROSSMODULE_START_ID 0x50
+#define PERF_CROSSMODULE_END_ID 0x51
+
+//
+// Declare bits for PcdPerformanceLibraryPropertyMask and
+// also used as the Type parameter of LogPerformanceMeasurementEnabled().
+//
+#define PERF_CORE_START_IMAGE 0x0002
+#define PERF_CORE_LOAD_IMAGE 0x0004
+#define PERF_CORE_DB_SUPPORT 0x0008
+#define PERF_CORE_DB_START 0x0010
+#define PERF_CORE_DB_STOP 0x0020
+
+#define PERF_GENERAL_TYPE 0x0040
+
+/**
+ Creates a record for the beginning of a performance measurement.
+
+ Creates a record that contains the Handle, Token, and Module.
+ If TimeStamp is not zero, then TimeStamp is added to the record as the start time.
+ If TimeStamp is zero, then this function reads the current time stamp
+ and adds that time stamp value to the record as the start time.
+
+ @param Handle Pointer to environment specific context used
+ to identify the component being measured.
+ @param Token Pointer to a Null-terminated ASCII string
+ that identifies the component being measured.
+ @param Module Pointer to a Null-terminated ASCII string
+ that identifies the module being measured.
+ @param TimeStamp 64-bit time stamp.
+
+ @retval RETURN_SUCCESS The start of the measurement was recorded.
+ @retval RETURN_OUT_OF_RESOURCES There are not enough resources to record the measurement.
+ @retval RETURN_DEVICE_ERROR A device error reading the time stamp.
+
+**/
+RETURN_STATUS
+EFIAPI
+StartPerformanceMeasurement (
+ IN CONST VOID *Handle OPTIONAL,
+ IN CONST CHAR8 *Token OPTIONAL,
+ IN CONST CHAR8 *Module OPTIONAL,
+ IN UINT64 TimeStamp
+ );
+
+/**
+ Fills in the end time of a performance measurement.
+
+ Looks up the record that matches Handle, Token, and Module.
+ If the record can not be found then return RETURN_NOT_FOUND.
+ If the record is found and TimeStamp is not zero,
+ then TimeStamp is added to the record as the end time.
+ If the record is found and TimeStamp is zero, then this function reads
+ the current time stamp and adds that time stamp value to the record as the end time.
+
+ @param Handle Pointer to environment specific context used
+ to identify the component being measured.
+ @param Token Pointer to a Null-terminated ASCII string
+ that identifies the component being measured.
+ @param Module Pointer to a Null-terminated ASCII string
+ that identifies the module being measured.
+ @param TimeStamp 64-bit time stamp.
+
+ @retval RETURN_SUCCESS The end of the measurement was recorded.
+ @retval RETURN_NOT_FOUND The specified measurement record could not be found.
+ @retval RETURN_DEVICE_ERROR A device error reading the time stamp.
+
+**/
+RETURN_STATUS
+EFIAPI
+EndPerformanceMeasurement (
+ IN CONST VOID *Handle OPTIONAL,
+ IN CONST CHAR8 *Token OPTIONAL,
+ IN CONST CHAR8 *Module OPTIONAL,
+ IN UINT64 TimeStamp
+ );
+
+/**
+ Attempts to retrieve a performance measurement log entry from the performance measurement log.
+ It can also retrieve the log created by StartPerformanceMeasurementEx and EndPerformanceMeasurementEx,
+ and then eliminate the Identifier.
+
+ Attempts to retrieve the performance log entry specified by LogEntryKey. If LogEntryKey is
+ zero on entry, then an attempt is made to retrieve the first entry from the performance log,
+ and the key for the second entry in the log is returned. If the performance log is empty,
+ then no entry is retrieved and zero is returned. If LogEntryKey is not zero, then the performance
+ log entry associated with LogEntryKey is retrieved, and the key for the next entry in the log is
+ returned. If LogEntryKey is the key for the last entry in the log, then the last log entry is
+ retrieved and an implementation specific non-zero key value that specifies the end of the performance
+ log is returned. If LogEntryKey is equal this implementation specific non-zero key value, then no entry
+ is retrieved and zero is returned. In the cases where a performance log entry can be returned,
+ the log entry is returned in Handle, Token, Module, StartTimeStamp, and EndTimeStamp.
+ If LogEntryKey is not a valid log entry key for the performance measurement log, then ASSERT().
+ If Handle is NULL, then ASSERT().
+ If Token is NULL, then ASSERT().
+ If Module is NULL, then ASSERT().
+ If StartTimeStamp is NULL, then ASSERT().
+ If EndTimeStamp is NULL, then ASSERT().
+
+ @param LogEntryKey On entry, the key of the performance measurement log entry to retrieve.
+ 0, then the first performance measurement log entry is retrieved.
+ On exit, the key of the next performance lof entry entry.
+ @param Handle Pointer to environment specific context used to identify the component
+ being measured.
+ @param Token Pointer to a Null-terminated ASCII string that identifies the component
+ being measured.
+ @param Module Pointer to a Null-terminated ASCII string that identifies the module
+ being measured.
+ @param StartTimeStamp Pointer to the 64-bit time stamp that was recorded when the measurement
+ was started.
+ @param EndTimeStamp Pointer to the 64-bit time stamp that was recorded when the measurement
+ was ended.
+
+ @return The key for the next performance log entry (in general case).
+
+**/
+UINTN
+EFIAPI
+GetPerformanceMeasurement (
+ IN UINTN LogEntryKey,
+ OUT CONST VOID **Handle,
+ OUT CONST CHAR8 **Token,
+ OUT CONST CHAR8 **Module,
+ OUT UINT64 *StartTimeStamp,
+ OUT UINT64 *EndTimeStamp
+ );
+
+/**
+ Creates a record for the beginning of a performance measurement.
+
+ Creates a record that contains the Handle, Token, Module and Identifier.
+ If TimeStamp is not zero, then TimeStamp is added to the record as the start time.
+ If TimeStamp is zero, then this function reads the current time stamp
+ and adds that time stamp value to the record as the start time.
+
+ @param Handle Pointer to environment specific context used
+ to identify the component being measured.
+ @param Token Pointer to a Null-terminated ASCII string
+ that identifies the component being measured.
+ @param Module Pointer to a Null-terminated ASCII string
+ that identifies the module being measured.
+ @param TimeStamp 64-bit time stamp.
+ @param Identifier 32-bit identifier. If the value is 0, the created record
+ is same as the one created by StartPerformanceMeasurement.
+
+ @retval RETURN_SUCCESS The start of the measurement was recorded.
+ @retval RETURN_OUT_OF_RESOURCES There are not enough resources to record the measurement.
+ @retval RETURN_DEVICE_ERROR A device error reading the time stamp.
+
+**/
+RETURN_STATUS
+EFIAPI
+StartPerformanceMeasurementEx (
+ IN CONST VOID *Handle OPTIONAL,
+ IN CONST CHAR8 *Token OPTIONAL,
+ IN CONST CHAR8 *Module OPTIONAL,
+ IN UINT64 TimeStamp,
+ IN UINT32 Identifier
+ );
+
+/**
+ Fills in the end time of a performance measurement.
+
+ Looks up the record that matches Handle, Token and Module.
+ If the record can not be found then return RETURN_NOT_FOUND.
+ If the record is found and TimeStamp is not zero,
+ then TimeStamp is added to the record as the end time.
+ If the record is found and TimeStamp is zero, then this function reads
+ the current time stamp and adds that time stamp value to the record as the end time.
+
+ @param Handle Pointer to environment specific context used
+ to identify the component being measured.
+ @param Token Pointer to a Null-terminated ASCII string
+ that identifies the component being measured.
+ @param Module Pointer to a Null-terminated ASCII string
+ that identifies the module being measured.
+ @param TimeStamp 64-bit time stamp.
+ @param Identifier 32-bit identifier. If the value is 0, the found record
+ is same as the one found by EndPerformanceMeasurement.
+
+ @retval RETURN_SUCCESS The end of the measurement was recorded.
+ @retval RETURN_NOT_FOUND The specified measurement record could not be found.
+ @retval RETURN_DEVICE_ERROR A device error reading the time stamp.
+
+**/
+RETURN_STATUS
+EFIAPI
+EndPerformanceMeasurementEx (
+ IN CONST VOID *Handle OPTIONAL,
+ IN CONST CHAR8 *Token OPTIONAL,
+ IN CONST CHAR8 *Module OPTIONAL,
+ IN UINT64 TimeStamp,
+ IN UINT32 Identifier
+ );
+
+/**
+ Attempts to retrieve a performance measurement log entry from the performance measurement log.
+ It can also retrieve the log created by StartPerformanceMeasurement and EndPerformanceMeasurement,
+ and then assign the Identifier with 0.
+
+ Attempts to retrieve the performance log entry specified by LogEntryKey. If LogEntryKey is
+ zero on entry, then an attempt is made to retrieve the first entry from the performance log,
+ and the key for the second entry in the log is returned. If the performance log is empty,
+ then no entry is retrieved and zero is returned. If LogEntryKey is not zero, then the performance
+ log entry associated with LogEntryKey is retrieved, and the key for the next entry in the log is
+ returned. If LogEntryKey is the key for the last entry in the log, then the last log entry is
+ retrieved and an implementation specific non-zero key value that specifies the end of the performance
+ log is returned. If LogEntryKey is equal this implementation specific non-zero key value, then no entry
+ is retrieved and zero is returned. In the cases where a performance log entry can be returned,
+ the log entry is returned in Handle, Token, Module, StartTimeStamp, EndTimeStamp and Identifier.
+ If LogEntryKey is not a valid log entry key for the performance measurement log, then ASSERT().
+ If Handle is NULL, then ASSERT().
+ If Token is NULL, then ASSERT().
+ If Module is NULL, then ASSERT().
+ If StartTimeStamp is NULL, then ASSERT().
+ If EndTimeStamp is NULL, then ASSERT().
+ If Identifier is NULL, then ASSERT().
+
+ @param LogEntryKey On entry, the key of the performance measurement log entry to retrieve.
+ 0, then the first performance measurement log entry is retrieved.
+ On exit, the key of the next performance of entry entry.
+ @param Handle Pointer to environment specific context used to identify the component
+ being measured.
+ @param Token Pointer to a Null-terminated ASCII string that identifies the component
+ being measured.
+ @param Module Pointer to a Null-terminated ASCII string that identifies the module
+ being measured.
+ @param StartTimeStamp Pointer to the 64-bit time stamp that was recorded when the measurement
+ was started.
+ @param EndTimeStamp Pointer to the 64-bit time stamp that was recorded when the measurement
+ was ended.
+ @param Identifier Pointer to the 32-bit identifier that was recorded.
+
+ @return The key for the next performance log entry (in general case).
+
+**/
+UINTN
+EFIAPI
+GetPerformanceMeasurementEx (
+ IN UINTN LogEntryKey,
+ OUT CONST VOID **Handle,
+ OUT CONST CHAR8 **Token,
+ OUT CONST CHAR8 **Module,
+ OUT UINT64 *StartTimeStamp,
+ OUT UINT64 *EndTimeStamp,
+ OUT UINT32 *Identifier
+ );
+
+/**
+ Returns TRUE if the performance measurement macros are enabled.
+
+ This function returns TRUE if the PERFORMANCE_LIBRARY_PROPERTY_MEASUREMENT_ENABLED bit of
+ PcdPerformanceLibraryPropertyMask is set. Otherwise FALSE is returned.
+
+ @retval TRUE The PERFORMANCE_LIBRARY_PROPERTY_MEASUREMENT_ENABLED bit of
+ PcdPerformanceLibraryPropertyMask is set.
+ @retval FALSE The PERFORMANCE_LIBRARY_PROPERTY_MEASUREMENT_ENABLED bit of
+ PcdPerformanceLibraryPropertyMask is clear.
+
+**/
+BOOLEAN
+EFIAPI
+PerformanceMeasurementEnabled (
+ VOID
+ );
+
+/**
+ Check whether the specified performance measurement can be logged.
+
+ This function returns TRUE when the PERFORMANCE_LIBRARY_PROPERTY_MEASUREMENT_ENABLED bit of PcdPerformanceLibraryPropertyMask is set
+ and the Type disable bit in PcdPerformanceLibraryPropertyMask is not set.
+
+ @param Type - Type of the performance measurement entry.
+
+ @retval TRUE The performance measurement can be logged.
+ @retval FALSE The performance measurement can NOT be logged.
+
+**/
+BOOLEAN
+EFIAPI
+LogPerformanceMeasurementEnabled (
+ IN CONST UINTN Type
+ );
+
+/**
+ Create performance record with event description.
+
+ @param CallerIdentifier - Image handle or pointer to caller ID GUID
+ @param Guid - Pointer to a GUID.
+ Used for event signal perf and callback perf to cache the event guid.
+ @param String - Pointer to a string describing the measurement
+ @param Address - Pointer to a location in memory relevant to the measurement.
+ @param Identifier - Performance identifier describing the type of measurement.
+
+ @retval RETURN_SUCCESS - Successfully created performance record
+ @retval RETURN_OUT_OF_RESOURCES - Ran out of space to store the records
+ @retval RETURN_INVALID_PARAMETER - Invalid parameter passed to function - NULL
+ pointer or invalid Identifier.
+
+**/
+RETURN_STATUS
+EFIAPI
+LogPerformanceMeasurement (
+ IN CONST VOID *CallerIdentifier OPTIONAL,
+ IN CONST VOID *Guid OPTIONAL,
+ IN CONST CHAR8 *String OPTIONAL,
+ IN UINT64 Address OPTIONAL,
+ IN UINT32 Identifier
+ );
+
+/**
+ Begin Macro to measure the performance of StartImage in core.
+
+ If the PERFORMANCE_LIBRARY_PROPERTY_MEASUREMENT_ENABLED bit of PcdPerformanceLibraryPropertyMask is set,
+ and the BIT1 (disable PERF_CORE_START_IMAGE) of PcdPerformanceLibraryPropertyMask is not set,
+ then LogPerformanceMeasurement() is called.
+
+**/
+#define PERF_START_IMAGE_BEGIN(ModuleHandle) \
+ do { \
+ if (LogPerformanceMeasurementEnabled (PERF_CORE_START_IMAGE)) { \
+ LogPerformanceMeasurement (ModuleHandle, NULL, NULL, 0, MODULE_START_ID); \
+ } \
+ } while (FALSE)
+
+/**
+ End Macro to measure the performance of StartImage in core.
+
+ If the PERFORMANCE_LIBRARY_PROPERTY_MEASUREMENT_ENABLED bit of PcdPerformanceLibraryPropertyMask is set,
+ and the BIT1 (disable PERF_CORE_START_IMAGE) of PcdPerformanceLibraryPropertyMask is not set,
+ then LogPerformanceMeasurement() is called.
+
+**/
+#define PERF_START_IMAGE_END(ModuleHandle) \
+ do { \
+ if (LogPerformanceMeasurementEnabled (PERF_CORE_START_IMAGE)) { \
+ LogPerformanceMeasurement (ModuleHandle, NULL, NULL, 0, MODULE_END_ID); \
+ } \
+ } while (FALSE)
+
+/**
+ Begin Macro to measure the performance of LoadImage in core.
+
+ If the PERFORMANCE_LIBRARY_PROPERTY_MEASUREMENT_ENABLED bit of PcdPerformanceLibraryPropertyMask is set,
+ and the BIT2 (disable PERF_CORE_LOAD_IMAGE) of PcdPerformanceLibraryPropertyMask is not set,
+ then LogPerformanceMeasurement() is called.
+
+**/
+#define PERF_LOAD_IMAGE_BEGIN(ModuleHandle) \
+ do { \
+ if (LogPerformanceMeasurementEnabled (PERF_CORE_LOAD_IMAGE)) { \
+ LogPerformanceMeasurement (ModuleHandle, NULL, NULL, 0, MODULE_LOADIMAGE_START_ID); \
+ } \
+ } while (FALSE)
+
+/**
+ End Macro to measure the performance of LoadImage in core.
+
+ If the PERFORMANCE_LIBRARY_PROPERTY_MEASUREMENT_ENABLED bit of PcdPerformanceLibraryPropertyMask is set,
+ and the BIT2 (disable PERF_CORE_LOAD_IMAGE) of PcdPerformanceLibraryPropertyMask is not set,
+ then LogPerformanceMeasurement() is called.
+
+**/
+#define PERF_LOAD_IMAGE_END(ModuleHandle) \
+ do { \
+ if (LogPerformanceMeasurementEnabled (PERF_CORE_LOAD_IMAGE)) { \
+ LogPerformanceMeasurement (ModuleHandle, NULL, NULL, 0, MODULE_LOADIMAGE_END_ID); \
+ } \
+ } while (FALSE)
+
+/**
+ Start Macro to measure the performance of DriverBinding Support in core.
+
+ If the PERFORMANCE_LIBRARY_PROPERTY_MEASUREMENT_ENABLED bit of PcdPerformanceLibraryPropertyMask is set,
+ and the BIT3 (disable PERF_CORE_DB_SUPPORT) of PcdPerformanceLibraryPropertyMask is not set,
+ then LogPerformanceMeasurement() is called.
+
+**/
+#define PERF_DRIVER_BINDING_SUPPORT_BEGIN(ModuleHandle, ControllerHandle) \
+ do { \
+ if (LogPerformanceMeasurementEnabled (PERF_CORE_DB_SUPPORT)) { \
+ LogPerformanceMeasurement (ModuleHandle, NULL, NULL, (UINT64)(UINTN)ControllerHandle, MODULE_DB_SUPPORT_START_ID); \
+ } \
+ } while (FALSE)
+
+/**
+ End Macro to measure the performance of DriverBinding Support in core.
+
+ If the PERFORMANCE_LIBRARY_PROPERTY_MEASUREMENT_ENABLED bit of PcdPerformanceLibraryPropertyMask is set,
+ and the BIT3 (disable PERF_CORE_DB_SUPPORT) of PcdPerformanceLibraryPropertyMask is not set,
+ then LogPerformanceMeasurement() is called.
+
+**/
+#define PERF_DRIVER_BINDING_SUPPORT_END(ModuleHandle, ControllerHandle) \
+ do { \
+ if (LogPerformanceMeasurementEnabled (PERF_CORE_DB_SUPPORT)) { \
+ LogPerformanceMeasurement (ModuleHandle, NULL, NULL, (UINT64)(UINTN)ControllerHandle, MODULE_DB_SUPPORT_END_ID); \
+ } \
+ } while (FALSE)
+
+/**
+ Begin Macro to measure the performance of DriverBinding Start in core.
+
+ If the PERFORMANCE_LIBRARY_PROPERTY_MEASUREMENT_ENABLED bit of PcdPerformanceLibraryPropertyMask is set,
+ and the BIT4 (disable PERF_CORE_DB_START) of PcdPerformanceLibraryPropertyMask is not set,
+ then LogPerformanceMeasurement() is called.
+
+**/
+#define PERF_DRIVER_BINDING_START_BEGIN(ModuleHandle, ControllerHandle) \
+ do { \
+ if (LogPerformanceMeasurementEnabled (PERF_CORE_DB_START)) { \
+ LogPerformanceMeasurement (ModuleHandle, NULL, NULL, (UINT64)(UINTN)ControllerHandle, MODULE_DB_START_ID); \
+ } \
+ } while (FALSE)
+
+/**
+ End Macro to measure the performance of DriverBinding Start in core.
+
+ If the PERFORMANCE_LIBRARY_PROPERTY_MEASUREMENT_ENABLED bit of PcdPerformanceLibraryPropertyMask is set,
+ and the BIT4 (disable PERF_CORE_DB_START) of PcdPerformanceLibraryPropertyMask is not set,
+ then LogPerformanceMeasurement() is called.
+
+**/
+#define PERF_DRIVER_BINDING_START_END(ModuleHandle, ControllerHandle) \
+ do { \
+ if (LogPerformanceMeasurementEnabled (PERF_CORE_DB_START)) { \
+ LogPerformanceMeasurement (ModuleHandle, NULL, NULL, (UINT64)(UINTN)ControllerHandle, MODULE_DB_END_ID); \
+ } \
+ } while (FALSE)
+
+/**
+ Start Macro to measure the performance of DriverBinding Stop in core.
+
+ If the PERFORMANCE_LIBRARY_PROPERTY_MEASUREMENT_ENABLED bit of PcdPerformanceLibraryPropertyMask is set,
+ and the BIT5 (disable PERF_CORE_DB_STOP) of PcdPerformanceLibraryPropertyMask is not set,
+ then LogPerformanceMeasurement() is called.
+
+**/
+#define PERF_DRIVER_BINDING_STOP_BEGIN(ModuleHandle, ControllerHandle) \
+ do { \
+ if (LogPerformanceMeasurementEnabled (PERF_CORE_DB_STOP)) { \
+ LogPerformanceMeasurement (ModuleHandle, NULL, NULL, (UINT64)(UINTN)ControllerHandle, MODULE_DB_STOP_START_ID); \
+ } \
+ } while (FALSE)
+
+/**
+ End Macro to measure the performance of DriverBinding Stop in core.
+
+ If the PERFORMANCE_LIBRARY_PROPERTY_MEASUREMENT_ENABLED bit of PcdPerformanceLibraryPropertyMask is set,
+ and the BIT5 (disable PERF_CORE_DB_STOP) of PcdPerformanceLibraryPropertyMask is not set,
+ then LogPerformanceMeasurement() is called.
+
+**/
+#define PERF_DRIVER_BINDING_STOP_END(ModuleHandle, ControllerHandle) \
+ do { \
+ if (LogPerformanceMeasurementEnabled (PERF_CORE_DB_STOP)) { \
+ LogPerformanceMeasurement (ModuleHandle, NULL, NULL, (UINT64)(UINTN)ControllerHandle, MODULE_DB_STOP_END_ID); \
+ } \
+ } while (FALSE)
+
+/**
+ Macro to measure the time from power-on to this macro execution.
+ It can be used to log a meaningful thing which happens at a time point.
+
+ If the PERFORMANCE_LIBRARY_PROPERTY_MEASUREMENT_ENABLED bit of PcdPerformanceLibraryPropertyMask is set,
+ and the BIT6 (disable PERF_GENERAL_TYPE) of PcdPerformanceLibraryPropertyMask is not set,
+ then LogPerformanceMeasurement() is called.
+
+**/
+#define PERF_EVENT(EventString) \
+ do { \
+ if (LogPerformanceMeasurementEnabled (PERF_GENERAL_TYPE)) { \
+ LogPerformanceMeasurement (&gEfiCallerIdGuid, NULL, EventString , 0, PERF_EVENT_ID); \
+ } \
+ } while (FALSE)
+
+/**
+ Begin Macro to measure the performance of evnent signal behavior in any module.
+ The event guid will be passed with this macro.
+
+ If the PERFORMANCE_LIBRARY_PROPERTY_MEASUREMENT_ENABLED bit of PcdPerformanceLibraryPropertyMask is set,
+ and the BIT6 (disable PERF_GENERAL_TYPE) of PcdPerformanceLibraryPropertyMask is not set,
+ then LogPerformanceMeasurement() is called.
+
+**/
+#define PERF_EVENT_SIGNAL_BEGIN(EventGuid) \
+ do { \
+ if (LogPerformanceMeasurementEnabled (PERF_GENERAL_TYPE)) { \
+ LogPerformanceMeasurement (&gEfiCallerIdGuid, EventGuid, __FUNCTION__ , 0, PERF_EVENTSIGNAL_START_ID); \
+ } \
+ } while (FALSE)
+
+/**
+ End Macro to measure the performance of evnent signal behavior in any module.
+ The event guid will be passed with this macro.
+
+ If the PERFORMANCE_LIBRARY_PROPERTY_MEASUREMENT_ENABLED bit of PcdPerformanceLibraryPropertyMask is set,
+ and the BIT6 (disable PERF_GENERAL_TYPE) of PcdPerformanceLibraryPropertyMask is not set,
+ then LogPerformanceMeasurement() is called.
+
+**/
+#define PERF_EVENT_SIGNAL_END(EventGuid) \
+ do { \
+ if (LogPerformanceMeasurementEnabled (PERF_GENERAL_TYPE)) { \
+ LogPerformanceMeasurement (&gEfiCallerIdGuid, EventGuid, __FUNCTION__ , 0, PERF_EVENTSIGNAL_END_ID); \
+ } \
+ } while (FALSE)
+
+/**
+ Begin Macro to measure the performance of a callback function in any module.
+ The event guid which trigger the callback function will be passed with this macro.
+
+ If the PERFORMANCE_LIBRARY_PROPERTY_MEASUREMENT_ENABLED bit of PcdPerformanceLibraryPropertyMask is set,
+ and the BIT6 (disable PERF_GENERAL_TYPE) of PcdPerformanceLibraryPropertyMask is not set,
+ then LogPerformanceMeasurement() is called.
+
+**/
+#define PERF_CALLBACK_BEGIN(TriggerGuid) \
+ do { \
+ if (LogPerformanceMeasurementEnabled (PERF_GENERAL_TYPE)) { \
+ LogPerformanceMeasurement (&gEfiCallerIdGuid, TriggerGuid, __FUNCTION__ , 0, PERF_CALLBACK_START_ID); \
+ } \
+ } while (FALSE)
+
+/**
+ End Macro to measure the performance of a callback function in any module.
+ The event guid which trigger the callback function will be passed with this macro.
+
+ If the PERFORMANCE_LIBRARY_PROPERTY_MEASUREMENT_ENABLED bit of PcdPerformanceLibraryPropertyMask is set,
+ and the BIT6 (disable PERF_GENERAL_TYPE) of PcdPerformanceLibraryPropertyMask is not set,
+ then LogPerformanceMeasurement() is called.
+
+**/
+#define PERF_CALLBACK_END(TriggerGuid) \
+ do { \
+ if (LogPerformanceMeasurementEnabled (PERF_GENERAL_TYPE)) { \
+ LogPerformanceMeasurement (&gEfiCallerIdGuid, TriggerGuid, __FUNCTION__ , 0, PERF_CALLBACK_END_ID); \
+ } \
+ } while (FALSE)
+
+/**
+ Begin Macro to measure the performance of a general function in any module.
+
+ If the PERFORMANCE_LIBRARY_PROPERTY_MEASUREMENT_ENABLED bit of PcdPerformanceLibraryPropertyMask is set,
+ and the BIT6 (disable PERF_GENERAL_TYPE) of PcdPerformanceLibraryPropertyMask is not set,
+ then LogPerformanceMeasurement() is called.
+
+**/
+#define PERF_FUNCTION_BEGIN() \
+ do { \
+ if (LogPerformanceMeasurementEnabled (PERF_GENERAL_TYPE)) { \
+ LogPerformanceMeasurement (&gEfiCallerIdGuid, NULL, __FUNCTION__ , 0, PERF_FUNCTION_START_ID); \
+ } \
+ } while (FALSE)
+
+/**
+ End Macro to measure the performance of a general function in any module.
+
+ If the PERFORMANCE_LIBRARY_PROPERTY_MEASUREMENT_ENABLED bit of PcdPerformanceLibraryPropertyMask is set,
+ and the BIT6 (disable PERF_GENERAL_TYPE) of PcdPerformanceLibraryPropertyMask is not set,
+ then LogPerformanceMeasurement() is called.
+
+**/
+#define PERF_FUNCTION_END() \
+ do { \
+ if (LogPerformanceMeasurementEnabled (PERF_GENERAL_TYPE)) { \
+ LogPerformanceMeasurement (&gEfiCallerIdGuid, NULL, __FUNCTION__ , 0, PERF_FUNCTION_END_ID); \
+ } \
+ } while (FALSE)
+
+/**
+ Begin Macro to measure the performance of a behavior within one module.
+
+ If the PERFORMANCE_LIBRARY_PROPERTY_MEASUREMENT_ENABLED bit of PcdPerformanceLibraryPropertyMask is set,
+ and the BIT6 (disable PERF_GENERAL_TYPE) of PcdPerformanceLibraryPropertyMask is not set,
+ then LogPerformanceMeasurement() is called.
+
+**/
+#define PERF_INMODULE_BEGIN(MeasurementString) \
+ do { \
+ if (LogPerformanceMeasurementEnabled (PERF_GENERAL_TYPE)) { \
+ LogPerformanceMeasurement (&gEfiCallerIdGuid, NULL, MeasurementString, 0, PERF_INMODULE_START_ID); \
+ } \
+ } while (FALSE)
+
+/**
+ End Macro to measure the performance of a behavior within one module.
+
+ If the PERFORMANCE_LIBRARY_PROPERTY_MEASUREMENT_ENABLED bit of PcdPerformanceLibraryPropertyMask is set,
+ and the BIT6 (disable PERF_GENERAL_TYPE) of PcdPerformanceLibraryPropertyMask is not set,
+ then LogPerformanceMeasurement() is called.
+
+**/
+#define PERF_INMODULE_END(MeasurementString) \
+ do { \
+ if (LogPerformanceMeasurementEnabled (PERF_GENERAL_TYPE)) { \
+ LogPerformanceMeasurement (&gEfiCallerIdGuid, NULL, MeasurementString, 0, PERF_INMODULE_END_ID); \
+ } \
+ } while (FALSE)
+
+/**
+ Begin Macro to measure the performance of a behavior in different modules.
+ Such as the performance of PEI phase, DXE phase, BDS phase.
+
+ If the PERFORMANCE_LIBRARY_PROPERTY_MEASUREMENT_ENABLED bit of PcdPerformanceLibraryPropertyMask is set,
+ and the BIT6 (disable PERF_GENERAL_TYPE) of PcdPerformanceLibraryPropertyMask is not set,
+ then LogPerformanceMeasurement() is called.
+
+**/
+#define PERF_CROSSMODULE_BEGIN(MeasurementString) \
+ do { \
+ if (LogPerformanceMeasurementEnabled (PERF_GENERAL_TYPE)) { \
+ LogPerformanceMeasurement (&gEfiCallerIdGuid, NULL, MeasurementString, 0, PERF_CROSSMODULE_START_ID); \
+ } \
+ } while (FALSE)
+
+/**
+ End Macro to measure the performance of a behavior in different modules.
+ Such as the performance of PEI phase, DXE phase, BDS phase.
+
+ If the PERFORMANCE_LIBRARY_PROPERTY_MEASUREMENT_ENABLED bit of PcdPerformanceLibraryPropertyMask is set,
+ and the BIT6 (disable PERF_GENERAL_TYPE) of PcdPerformanceLibraryPropertyMask is not set,
+ then LogPerformanceMeasurement() is called.
+
+**/
+#define PERF_CROSSMODULE_END(MeasurementString) \
+ do { \
+ if (LogPerformanceMeasurementEnabled (PERF_GENERAL_TYPE)) { \
+ LogPerformanceMeasurement (&gEfiCallerIdGuid, NULL, MeasurementString, 0, PERF_CROSSMODULE_END_ID); \
+ } \
+ } while (FALSE)
+
+/**
+ Macro that calls EndPerformanceMeasurement().
+
+ If the PERFORMANCE_LIBRARY_PROPERTY_MEASUREMENT_ENABLED bit of PcdPerformanceLibraryPropertyMask is set,
+ then EndPerformanceMeasurement() is called.
+
+**/
+#define PERF_END(Handle, Token, Module, TimeStamp) \
+ do { \
+ if (PerformanceMeasurementEnabled ()) { \
+ EndPerformanceMeasurement (Handle, Token, Module, TimeStamp); \
+ } \
+ } while (FALSE)
+
+/**
+ Macro that calls StartPerformanceMeasurement().
+
+ If the PERFORMANCE_LIBRARY_PROPERTY_MEASUREMENT_ENABLED bit of PcdPerformanceLibraryPropertyMask is set,
+ then StartPerformanceMeasurement() is called.
+
+**/
+#define PERF_START(Handle, Token, Module, TimeStamp) \
+ do { \
+ if (PerformanceMeasurementEnabled ()) { \
+ StartPerformanceMeasurement (Handle, Token, Module, TimeStamp); \
+ } \
+ } while (FALSE)
+
+/**
+ Macro that calls EndPerformanceMeasurementEx().
+
+ If the PERFORMANCE_LIBRARY_PROPERTY_MEASUREMENT_ENABLED bit of PcdPerformanceLibraryPropertyMask is set,
+ then EndPerformanceMeasurementEx() is called.
+
+**/
+#define PERF_END_EX(Handle, Token, Module, TimeStamp, Identifier) \
+ do { \
+ if (PerformanceMeasurementEnabled ()) { \
+ EndPerformanceMeasurementEx (Handle, Token, Module, TimeStamp, Identifier); \
+ } \
+ } while (FALSE)
+
+/**
+ Macro that calls StartPerformanceMeasurementEx().
+
+ If the PERFORMANCE_LIBRARY_PROPERTY_MEASUREMENT_ENABLED bit of PcdPerformanceLibraryPropertyMask is set,
+ then StartPerformanceMeasurementEx() is called.
+
+**/
+#define PERF_START_EX(Handle, Token, Module, TimeStamp, Identifier) \
+ do { \
+ if (PerformanceMeasurementEnabled ()) { \
+ StartPerformanceMeasurementEx (Handle, Token, Module, TimeStamp, Identifier); \
+ } \
+ } while (FALSE)
+
+/**
+ Macro that marks the beginning of performance measurement source code.
+
+ If the PERFORMANCE_LIBRARY_PROPERTY_MEASUREMENT_ENABLED bit of PcdPerformanceLibraryPropertyMask is set,
+ then this macro marks the beginning of source code that is included in a module.
+ Otherwise, the source lines between PERF_CODE_BEGIN() and PERF_CODE_END() are not included in a module.
+
+**/
+#define PERF_CODE_BEGIN() do { if (PerformanceMeasurementEnabled ()) { UINT8 __PerformanceCodeLocal
+
+/**
+ Macro that marks the end of performance measurement source code.
+
+ If the PERFORMANCE_LIBRARY_PROPERTY_MEASUREMENT_ENABLED bit of PcdPerformanceLibraryPropertyMask is set,
+ then this macro marks the end of source code that is included in a module.
+ Otherwise, the source lines between PERF_CODE_BEGIN() and PERF_CODE_END() are not included in a module.
+
+**/
+#define PERF_CODE_END() __PerformanceCodeLocal = 0; __PerformanceCodeLocal++; } } while (FALSE)
+
+/**
+ Macro that declares a section of performance measurement source code.
+
+ If the PERFORMANCE_LIBRARY_PROPERTY_MEASUREMENT_ENABLED bit of PcdPerformanceLibraryPropertyMask is set,
+ then the source code specified by Expression is included in a module.
+ Otherwise, the source specified by Expression is not included in a module.
+
+ @param Expression Performance measurement source code to include in a module.
+
+**/
+#define PERF_CODE(Expression) \
+ PERF_CODE_BEGIN (); \
+ Expression \
+ PERF_CODE_END ()
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/PostCodeLib.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/PostCodeLib.h
new file mode 100644
index 0000000000..caeba2afd1
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/PostCodeLib.h
@@ -0,0 +1,140 @@
+/** @file
+ Provides services to send progress/error codes to a POST card.
+
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __POST_CODE_LIB_H__
+#define __POST_CODE_LIB_H__
+
+#define POST_CODE_PROPERTY_POST_CODE_ENABLED 0x00000008
+#define POST_CODE_PROPERTY_POST_CODE_DESCRIPTION_ENABLED 0x00000010
+
+/**
+ Sends a 32-bit value to a POST card.
+
+ Sends the 32-bit value specified by Value to a POST card, and returns Value.
+ Some implementations of this library function may perform I/O operations
+ directly to a POST card device. Other implementations may send Value to
+ ReportStatusCode(), and the status code reporting mechanism will eventually
+ display the 32-bit value on the status reporting device.
+
+ PostCode() must actively prevent recursion. If PostCode() is called while
+ processing another Post Code Library function, then
+ PostCode() must return Value immediately.
+
+ @param Value The 32-bit value to write to the POST card.
+
+ @return The 32-bit value to write to the POST card.
+
+**/
+UINT32
+EFIAPI
+PostCode (
+ IN UINT32 Value
+ );
+
+/**
+ Sends a 32-bit value to a POST and associated ASCII string.
+
+ Sends the 32-bit value specified by Value to a POST card, and returns Value.
+ If Description is not NULL, then the ASCII string specified by Description is
+ also passed to the handler that displays the POST card value. Some
+ implementations of this library function may perform I/O operations directly
+ to a POST card device. Other implementations may send Value to ReportStatusCode(),
+ and the status code reporting mechanism will eventually display the 32-bit
+ value on the status reporting device.
+
+ PostCodeWithDescription()must actively prevent recursion. If
+ PostCodeWithDescription() is called while processing another any other Post
+ Code Library function, then PostCodeWithDescription() must return Value
+ immediately.
+
+ @param Value The 32-bit value to write to the POST card.
+ @param Description Pointer to an ASCII string that is a description of the
+ POST code value. This is an optional parameter that may
+ be NULL.
+
+ @return The 32-bit value to write to the POST card.
+
+**/
+UINT32
+EFIAPI
+PostCodeWithDescription (
+ IN UINT32 Value,
+ IN CONST CHAR8 *Description OPTIONAL
+ );
+
+/**
+ Returns TRUE if POST Codes are enabled.
+
+ This function returns TRUE if the POST_CODE_PROPERTY_POST_CODE_ENABLED
+ bit of PcdPostCodePropertyMask is set. Otherwise FALSE is returned.
+
+ @retval TRUE The POST_CODE_PROPERTY_POST_CODE_ENABLED bit of
+ PcdPostCodeProperyMask is set.
+ @retval FALSE The POST_CODE_PROPERTY_POST_CODE_ENABLED bit of
+ PcdPostCodeProperyMask is clear.
+
+**/
+BOOLEAN
+EFIAPI
+PostCodeEnabled (
+ VOID
+ );
+
+/**
+ Returns TRUE if POST code descriptions are enabled.
+
+ This function returns TRUE if the POST_CODE_PROPERTY_POST_CODE_DESCRIPTION_ENABLED
+ bit of PcdPostCodePropertyMask is set. Otherwise FALSE is returned.
+
+ @retval TRUE The POST_CODE_PROPERTY_POST_CODE_DESCRIPTION_ENABLED bit of
+ PcdPostCodeProperyMask is set.
+ @retval FALSE The POST_CODE_PROPERTY_POST_CODE_DESCRIPTION_ENABLED bit of
+ PcdPostCodeProperyMask is clear.
+
+**/
+BOOLEAN
+EFIAPI
+PostCodeDescriptionEnabled (
+ VOID
+ );
+
+/**
+ Sends a 32-bit value to a POST card.
+
+ If POST codes are enabled in PcdPostCodeProperyMask, then call PostCode()
+ passing in Value. Value is returned.
+
+ @param Value The 32-bit value to write to the POST card.
+
+ @return Value The 32-bit value to write to the POST card.
+
+**/
+#define POST_CODE(Value) PostCodeEnabled() ? PostCode(Value) : Value
+
+/**
+ Sends a 32-bit value to a POST and associated ASCII string.
+
+ If POST codes and POST code descriptions are enabled in
+ PcdPostCodeProperyMask, then call PostCodeWithDescription() passing in
+ Value and Description. If only POST codes are enabled, then call PostCode()
+ passing in Value. Value is returned.
+
+ @param Value The 32-bit value to write to the POST card.
+ @param Description Pointer to an ASCII string that is a description of the
+ POST code value.
+
+ @return Value The 32-bit value to write to the POST card.
+**/
+#define POST_CODE_WITH_DESCRIPTION(Value, Description) \
+ PostCodeEnabled() ? \
+ (PostCodeDescriptionEnabled() ? \
+ PostCodeWithDescription(Value,Description) : \
+ PostCode(Value)) : \
+ Value
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/PrintLib.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/PrintLib.h
new file mode 100644
index 0000000000..7ac92ecf35
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/PrintLib.h
@@ -0,0 +1,934 @@
+/** @file
+ Provides services to print a formatted string to a buffer. All combinations of
+ Unicode and ASCII strings are supported.
+
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ The Print Library functions provide a simple means to produce formatted output
+ strings. Many of the output functions use a format string to describe how to
+ format the output of variable arguments. The format string consists of normal
+ text and argument descriptors. There are no restrictions for how the normal
+ text and argument descriptors can be mixed. The following end of line(EOL)
+ translations must be performed on the contents of the format string:
+
+ - '\\r' is translated to '\\r'
+ - '\\r\\n' is translated to '\\r\\n'
+ - '\\n' is translated to '\\r\\n'
+ - '\\n\\r' is translated to '\\r\\n'
+
+ This does not follow the ANSI C standard for sprint(). The format of argument
+ descriptors is described below. The ANSI C standard for sprint() has been
+ followed for some of the format types, and has not been followed for others.
+ The exceptions are noted below.
+
+ %[flags][width][.precision]type
+
+ [flags]:
+ - -
+ - The field is left justified. If not flag is not specified, then the
+ field is right justified.
+ - space
+ - Prefix a space character to a number. Only valid for types X, x, and d.
+ - +
+ - Prefix a plus character to a number. Only valid for types X, x, and d.
+ If both space and + are specified, then space is ignored.
+ - 0
+ - Pad with 0 characters to the left of a number. Only valid for types
+ X, x, and d.
+ - ,
+ - Place a comma every 3rd digit of the number. Only valid for type d.
+ If 0 is also specified, then 0 is ignored.
+ - L, l
+ - The number being printed is size UINT64. Only valid for types X, x, and d.
+ If this flag is not specified, then the number being printed is size int.
+ - NOTE: All invalid flags are ignored.
+
+ [width]:
+
+ - *
+ - The width of the field is specified by a UINTN argument in the
+ argument list.
+ - number
+ - The number specified as a decimal value represents the width of
+ the field.
+ - NOTE: If [width] is not specified, then a field width of 0 is assumed.
+
+ [.precision]:
+
+ - *
+ - The precision of the field is specified by a UINTN argument in the
+ argument list.
+ - number
+ - The number specified as a decimal value represents the precision of
+ the field.
+ - NOTE: If [.precision] is not specified, then a precision of 0 is assumed.
+
+ type:
+
+ - %
+ - Print a %%.
+ - c
+ - The argument is a Unicode character. ASCII characters can be printed
+ using this type too by making sure bits 8..15 of the argument are set to 0.
+ - x
+ - The argument is an unsigned hexadecimal number. The characters used are 0..9 and
+ A..F. If the flag 'L' is not specified, then the argument is assumed
+ to be size int. This does not follow ANSI C.
+ - X
+ - The argument is an unsigned hexadecimal number and the number is padded with
+ zeros. This is equivalent to a format string of "0x". If the flag
+ 'L' is not specified, then the argument is assumed to be size int.
+ This does not follow ANSI C.
+ - d
+ - The argument is a signed decimal number. If the flag 'L' is not specified,
+ then the argument is assumed to be size int.
+ - u
+ - The argument is a unsigned decimal number. If the flag 'L' is not specified,
+ then the argument is assumed to be size int.
+ - p
+ - The argument is a pointer that is a (VOID *), and it is printed as an
+ unsigned hexadecimal number The characters used are 0..9 and A..F.
+ - a
+ - The argument is a pointer to an ASCII string.
+ This does not follow ANSI C.
+ - S, s
+ - The argument is a pointer to a Unicode string.
+ This does not follow ANSI C.
+ - g
+ - The argument is a pointer to a GUID structure. The GUID is printed
+ in the format XXXXXXXX-XXXX-XXXX-XXXX-XXXXXXXXXXXX.
+ This does not follow ANSI C.
+ - t
+ - The argument is a pointer to an EFI_TIME structure. The time and
+ date are printed in the format "mm/dd/yyyy hh:mm" where mm is the
+ month zero padded, dd is the day zero padded, yyyy is the year zero
+ padded, hh is the hour zero padded, and mm is minutes zero padded.
+ This does not follow ANSI C.
+ - r
+ - The argument is a RETURN_STATUS value. This value is converted to
+ a string following the table below. This does not follow ANSI C.
+ - RETURN_SUCCESS
+ - "Success"
+ - RETURN_LOAD_ERROR
+ - "Load Error"
+ - RETURN_INVALID_PARAMETER
+ - "Invalid Parameter"
+ - RETURN_UNSUPPORTED
+ - "Unsupported"
+ - RETURN_BAD_BUFFER_SIZE
+ - "Bad Buffer Size"
+ - RETURN_BUFFER_TOO_SMALL
+ - "Buffer Too Small"
+ - RETURN_NOT_READY
+ - "Not Ready"
+ - RETURN_DEVICE_ERROR
+ - "Device Error"
+ - RETURN_WRITE_PROTECTED
+ - "Write Protected"
+ - RETURN_OUT_OF_RESOURCES
+ - "Out of Resources"
+ - RETURN_VOLUME_CORRUPTED
+ - "Volume Corrupt"
+ - RETURN_VOLUME_FULL
+ - "Volume Full"
+ - RETURN_NO_MEDIA
+ - "No Media"
+ - RETURN_MEDIA_CHANGED
+ - "Media changed"
+ - RETURN_NOT_FOUND
+ - "Not Found"
+ - RETURN_ACCESS_DENIED
+ - "Access Denied"
+ - RETURN_NO_RESPONSE
+ - "No Response"
+ - RETURN_NO_MAPPING
+ - "No mapping"
+ - RETURN_TIMEOUT
+ - "Time out"
+ - RETURN_NOT_STARTED
+ - "Not started"
+ - RETURN_ALREADY_STARTED
+ - "Already started"
+ - RETURN_ABORTED
+ - "Aborted"
+ - RETURN_ICMP_ERROR
+ - "ICMP Error"
+ - RETURN_TFTP_ERROR
+ - "TFTP Error"
+ - RETURN_PROTOCOL_ERROR
+ - "Protocol Error"
+ - RETURN_WARN_UNKNOWN_GLYPH
+ - "Warning Unknown Glyph"
+ - RETURN_WARN_DELETE_FAILURE
+ - "Warning Delete Failure"
+ - RETURN_WARN_WRITE_FAILURE
+ - "Warning Write Failure"
+ - RETURN_WARN_BUFFER_TOO_SMALL
+ - "Warning Buffer Too Small"
+
+**/
+
+#ifndef __PRINT_LIB_H__
+#define __PRINT_LIB_H__
+
+///
+/// Define the maximum number of characters that are required to
+/// encode with a NULL terminator a decimal, hexadecimal, GUID,
+/// or TIME value.
+///
+/// Maximum Length Decimal String = 28
+/// "-9,223,372,036,854,775,808"
+/// Maximum Length Hexadecimal String = 17
+/// "FFFFFFFFFFFFFFFF"
+/// Maximum Length GUID = 37
+/// "00000000-0000-0000-0000-000000000000"
+/// Maximum Length TIME = 18
+/// "12/12/2006 12:12"
+///
+#define MAXIMUM_VALUE_CHARACTERS 38
+
+///
+/// Flags bitmask values use in UnicodeValueToString() and
+/// AsciiValueToString()
+///
+#define LEFT_JUSTIFY 0x01
+#define COMMA_TYPE 0x08
+#define PREFIX_ZERO 0x20
+#define RADIX_HEX 0x80
+
+/**
+ Produces a Null-terminated Unicode string in an output buffer based on
+ a Null-terminated Unicode format string and a VA_LIST argument list.
+
+ This function is similar as vsnprintf_s defined in C11.
+
+ Produces a Null-terminated Unicode string in the output buffer specified by StartOfBuffer
+ and BufferSize.
+ The Unicode string is produced by parsing the format string specified by FormatString.
+ Arguments are pulled from the variable argument list specified by Marker based on the
+ contents of the format string.
+ The number of Unicode characters in the produced output buffer is returned not including
+ the Null-terminator.
+
+ If StartOfBuffer is not aligned on a 16-bit boundary, then ASSERT().
+ If FormatString is not aligned on a 16-bit boundary, then ASSERT().
+
+ If BufferSize > 1 and StartOfBuffer is NULL, then ASSERT(). Also, the output buffer is
+ unmodified and 0 is returned.
+ If BufferSize > 1 and FormatString is NULL, then ASSERT(). Also, the output buffer is
+ unmodified and 0 is returned.
+ If PcdMaximumUnicodeStringLength is not zero, and BufferSize >
+ (PcdMaximumUnicodeStringLength * sizeof (CHAR16) + 1), then ASSERT(). Also, the output
+ buffer is unmodified and 0 is returned.
+ If PcdMaximumUnicodeStringLength is not zero, and FormatString contains more than
+ PcdMaximumUnicodeStringLength Unicode characters not including the Null-terminator, then
+ ASSERT(). Also, the output buffer is unmodified and 0 is returned.
+
+ If BufferSize is 0 or 1, then the output buffer is unmodified and 0 is returned.
+
+ @param StartOfBuffer A pointer to the output buffer for the produced Null-terminated
+ Unicode string.
+ @param BufferSize The size, in bytes, of the output buffer specified by StartOfBuffer.
+ @param FormatString A Null-terminated Unicode format string.
+ @param Marker VA_LIST marker for the variable argument list.
+
+ @return The number of Unicode characters in the produced output buffer not including the
+ Null-terminator.
+
+**/
+UINTN
+EFIAPI
+UnicodeVSPrint (
+ OUT CHAR16 *StartOfBuffer,
+ IN UINTN BufferSize,
+ IN CONST CHAR16 *FormatString,
+ IN VA_LIST Marker
+ );
+
+/**
+ Produces a Null-terminated Unicode string in an output buffer based on
+ a Null-terminated Unicode format string and a BASE_LIST argument list.
+
+ Produces a Null-terminated Unicode string in the output buffer specified by StartOfBuffer
+ and BufferSize.
+ The Unicode string is produced by parsing the format string specified by FormatString.
+ Arguments are pulled from the variable argument list specified by Marker based on the
+ contents of the format string.
+ The number of Unicode characters in the produced output buffer is returned not including
+ the Null-terminator.
+
+ If StartOfBuffer is not aligned on a 16-bit boundary, then ASSERT().
+ If FormatString is not aligned on a 16-bit boundary, then ASSERT().
+
+ If BufferSize > 1 and StartOfBuffer is NULL, then ASSERT(). Also, the output buffer is
+ unmodified and 0 is returned.
+ If BufferSize > 1 and FormatString is NULL, then ASSERT(). Also, the output buffer is
+ unmodified and 0 is returned.
+ If PcdMaximumUnicodeStringLength is not zero, and BufferSize >
+ (PcdMaximumUnicodeStringLength * sizeof (CHAR16) + 1), then ASSERT(). Also, the output
+ buffer is unmodified and 0 is returned.
+ If PcdMaximumUnicodeStringLength is not zero, and FormatString contains more than
+ PcdMaximumUnicodeStringLength Unicode characters not including the Null-terminator, then
+ ASSERT(). Also, the output buffer is unmodified and 0 is returned.
+
+ If BufferSize is 0 or 1, then the output buffer is unmodified and 0 is returned.
+
+ @param StartOfBuffer A pointer to the output buffer for the produced Null-terminated
+ Unicode string.
+ @param BufferSize The size, in bytes, of the output buffer specified by StartOfBuffer.
+ @param FormatString A Null-terminated Unicode format string.
+ @param Marker BASE_LIST marker for the variable argument list.
+
+ @return The number of Unicode characters in the produced output buffer not including the
+ Null-terminator.
+
+**/
+UINTN
+EFIAPI
+UnicodeBSPrint (
+ OUT CHAR16 *StartOfBuffer,
+ IN UINTN BufferSize,
+ IN CONST CHAR16 *FormatString,
+ IN BASE_LIST Marker
+ );
+
+/**
+ Produces a Null-terminated Unicode string in an output buffer based on a Null-terminated
+ Unicode format string and variable argument list.
+
+ This function is similar as snprintf_s defined in C11.
+
+ Produces a Null-terminated Unicode string in the output buffer specified by StartOfBuffer
+ and BufferSize.
+ The Unicode string is produced by parsing the format string specified by FormatString.
+ Arguments are pulled from the variable argument list based on the contents of the format string.
+ The number of Unicode characters in the produced output buffer is returned not including
+ the Null-terminator.
+
+ If StartOfBuffer is not aligned on a 16-bit boundary, then ASSERT().
+ If FormatString is not aligned on a 16-bit boundary, then ASSERT().
+
+ If BufferSize > 1 and StartOfBuffer is NULL, then ASSERT(). Also, the output buffer is
+ unmodified and 0 is returned.
+ If BufferSize > 1 and FormatString is NULL, then ASSERT(). Also, the output buffer is
+ unmodified and 0 is returned.
+ If PcdMaximumUnicodeStringLength is not zero, and BufferSize >
+ (PcdMaximumUnicodeStringLength * sizeof (CHAR16) + 1), then ASSERT(). Also, the output
+ buffer is unmodified and 0 is returned.
+ If PcdMaximumUnicodeStringLength is not zero, and FormatString contains more than
+ PcdMaximumUnicodeStringLength Unicode characters not including the Null-terminator, then
+ ASSERT(). Also, the output buffer is unmodified and 0 is returned.
+
+ If BufferSize is 0 or 1, then the output buffer is unmodified and 0 is returned.
+
+ @param StartOfBuffer A pointer to the output buffer for the produced Null-terminated
+ Unicode string.
+ @param BufferSize The size, in bytes, of the output buffer specified by StartOfBuffer.
+ @param FormatString A Null-terminated Unicode format string.
+ @param ... Variable argument list whose contents are accessed based on the
+ format string specified by FormatString.
+
+ @return The number of Unicode characters in the produced output buffer not including the
+ Null-terminator.
+
+**/
+UINTN
+EFIAPI
+UnicodeSPrint (
+ OUT CHAR16 *StartOfBuffer,
+ IN UINTN BufferSize,
+ IN CONST CHAR16 *FormatString,
+ ...
+ );
+
+/**
+ Produces a Null-terminated Unicode string in an output buffer based on a Null-terminated
+ ASCII format string and a VA_LIST argument list.
+
+ This function is similar as vsnprintf_s defined in C11.
+
+ Produces a Null-terminated Unicode string in the output buffer specified by StartOfBuffer
+ and BufferSize.
+ The Unicode string is produced by parsing the format string specified by FormatString.
+ Arguments are pulled from the variable argument list specified by Marker based on the
+ contents of the format string.
+ The number of Unicode characters in the produced output buffer is returned not including
+ the Null-terminator.
+
+ If StartOfBuffer is not aligned on a 16-bit boundary, then ASSERT().
+
+ If BufferSize > 1 and StartOfBuffer is NULL, then ASSERT(). Also, the output buffer is
+ unmodified and 0 is returned.
+ If BufferSize > 1 and FormatString is NULL, then ASSERT(). Also, the output buffer is
+ unmodified and 0 is returned.
+ If PcdMaximumUnicodeStringLength is not zero, and BufferSize >
+ (PcdMaximumUnicodeStringLength * sizeof (CHAR16) + 1), then ASSERT(). Also, the output
+ buffer is unmodified and 0 is returned.
+ If PcdMaximumAsciiStringLength is not zero, and FormatString contains more than
+ PcdMaximumAsciiStringLength Ascii characters not including the Null-terminator, then
+ ASSERT(). Also, the output buffer is unmodified and 0 is returned.
+
+ If BufferSize is 0 or 1, then no output buffer is produced and 0 is returned.
+
+ @param StartOfBuffer A pointer to the output buffer for the produced Null-terminated
+ Unicode string.
+ @param BufferSize The size, in bytes, of the output buffer specified by StartOfBuffer.
+ @param FormatString A Null-terminated ASCII format string.
+ @param Marker VA_LIST marker for the variable argument list.
+
+ @return The number of Unicode characters in the produced output buffer not including the
+ Null-terminator.
+
+**/
+UINTN
+EFIAPI
+UnicodeVSPrintAsciiFormat (
+ OUT CHAR16 *StartOfBuffer,
+ IN UINTN BufferSize,
+ IN CONST CHAR8 *FormatString,
+ IN VA_LIST Marker
+ );
+
+/**
+ Produces a Null-terminated Unicode string in an output buffer based on a Null-terminated
+ ASCII format string and a BASE_LIST argument list.
+
+ Produces a Null-terminated Unicode string in the output buffer specified by StartOfBuffer
+ and BufferSize.
+ The Unicode string is produced by parsing the format string specified by FormatString.
+ Arguments are pulled from the variable argument list specified by Marker based on the
+ contents of the format string.
+ The number of Unicode characters in the produced output buffer is returned not including
+ the Null-terminator.
+
+ If StartOfBuffer is not aligned on a 16-bit boundary, then ASSERT().
+
+ If BufferSize > 1 and StartOfBuffer is NULL, then ASSERT(). Also, the output buffer is
+ unmodified and 0 is returned.
+ If BufferSize > 1 and FormatString is NULL, then ASSERT(). Also, the output buffer is
+ unmodified and 0 is returned.
+ If PcdMaximumUnicodeStringLength is not zero, and BufferSize >
+ (PcdMaximumUnicodeStringLength * sizeof (CHAR16) + 1), then ASSERT(). Also, the output
+ buffer is unmodified and 0 is returned.
+ If PcdMaximumAsciiStringLength is not zero, and FormatString contains more than
+ PcdMaximumAsciiStringLength Ascii characters not including the Null-terminator, then
+ ASSERT(). Also, the output buffer is unmodified and 0 is returned.
+
+ If BufferSize is 0 or 1, then no output buffer is produced and 0 is returned.
+
+ @param StartOfBuffer A pointer to the output buffer for the produced Null-terminated
+ Unicode string.
+ @param BufferSize The size, in bytes, of the output buffer specified by StartOfBuffer.
+ @param FormatString A Null-terminated ASCII format string.
+ @param Marker BASE_LIST marker for the variable argument list.
+
+ @return The number of Unicode characters in the produced output buffer not including the
+ Null-terminator.
+
+**/
+UINTN
+EFIAPI
+UnicodeBSPrintAsciiFormat (
+ OUT CHAR16 *StartOfBuffer,
+ IN UINTN BufferSize,
+ IN CONST CHAR8 *FormatString,
+ IN BASE_LIST Marker
+ );
+
+/**
+ Produces a Null-terminated Unicode string in an output buffer based on a Null-terminated
+ ASCII format string and variable argument list.
+
+ This function is similar as snprintf_s defined in C11.
+
+ Produces a Null-terminated Unicode string in the output buffer specified by StartOfBuffer
+ and BufferSize.
+ The Unicode string is produced by parsing the format string specified by FormatString.
+ Arguments are pulled from the variable argument list based on the contents of the
+ format string.
+ The number of Unicode characters in the produced output buffer is returned not including
+ the Null-terminator.
+
+ If StartOfBuffer is not aligned on a 16-bit boundary, then ASSERT().
+
+ If BufferSize > 1 and StartOfBuffer is NULL, then ASSERT(). Also, the output buffer is
+ unmodified and 0 is returned.
+ If BufferSize > 1 and FormatString is NULL, then ASSERT(). Also, the output buffer is
+ unmodified and 0 is returned.
+ If PcdMaximumUnicodeStringLength is not zero, and BufferSize >
+ (PcdMaximumUnicodeStringLength * sizeof (CHAR16) + 1), then ASSERT(). Also, the output
+ buffer is unmodified and 0 is returned.
+ If PcdMaximumAsciiStringLength is not zero, and FormatString contains more than
+ PcdMaximumAsciiStringLength Ascii characters not including the Null-terminator, then
+ ASSERT(). Also, the output buffer is unmodified and 0 is returned.
+
+ If BufferSize is 0 or 1, then no output buffer is produced and 0 is returned.
+
+ @param StartOfBuffer A pointer to the output buffer for the produced Null-terminated
+ Unicode string.
+ @param BufferSize The size, in bytes, of the output buffer specified by StartOfBuffer.
+ @param FormatString A Null-terminated ASCII format string.
+ @param ... Variable argument list whose contents are accessed based on the
+ format string specified by FormatString.
+
+ @return The number of Unicode characters in the produced output buffer not including the
+ Null-terminator.
+
+**/
+UINTN
+EFIAPI
+UnicodeSPrintAsciiFormat (
+ OUT CHAR16 *StartOfBuffer,
+ IN UINTN BufferSize,
+ IN CONST CHAR8 *FormatString,
+ ...
+ );
+
+/**
+ Converts a decimal value to a Null-terminated Unicode string.
+
+ Converts the decimal number specified by Value to a Null-terminated Unicode
+ string specified by Buffer containing at most Width characters. No padding of
+ spaces is ever performed. If Width is 0 then a width of
+ MAXIMUM_VALUE_CHARACTERS is assumed. If the conversion contains more than
+ Width characters, then only the first Width characters are placed in Buffer.
+ Additional conversion parameters are specified in Flags.
+
+ The Flags bit LEFT_JUSTIFY is always ignored.
+ All conversions are left justified in Buffer.
+ If Width is 0, PREFIX_ZERO is ignored in Flags.
+ If COMMA_TYPE is set in Flags, then PREFIX_ZERO is ignored in Flags, and
+ commas are inserted every 3rd digit starting from the right.
+ If RADIX_HEX is set in Flags, then the output buffer will be formatted in
+ hexadecimal format.
+ If Value is < 0 and RADIX_HEX is not set in Flags, then the fist character in
+ Buffer is a '-'.
+ If PREFIX_ZERO is set in Flags and PREFIX_ZERO is not being ignored, then
+ Buffer is padded with '0' characters so the combination of the optional '-'
+ sign character, '0' characters, digit characters for Value, and the
+ Null-terminator add up to Width characters.
+
+ If Buffer is not aligned on a 16-bit boundary, then ASSERT().
+ If an error would be returned, then the function will also ASSERT().
+
+ @param Buffer The pointer to the output buffer for the produced
+ Null-terminated Unicode string.
+ @param BufferSize The size of Buffer in bytes, including the
+ Null-terminator.
+ @param Flags The bitmask of flags that specify left justification,
+ zero pad, and commas.
+ @param Value The 64-bit signed value to convert to a string.
+ @param Width The maximum number of Unicode characters to place in
+ Buffer, not including the Null-terminator.
+
+ @retval RETURN_SUCCESS The decimal value is converted.
+ @retval RETURN_BUFFER_TOO_SMALL If BufferSize cannot hold the converted
+ value.
+ @retval RETURN_INVALID_PARAMETER If Buffer is NULL.
+ If PcdMaximumUnicodeStringLength is not
+ zero, and BufferSize is greater than
+ (PcdMaximumUnicodeStringLength *
+ sizeof (CHAR16) + 1).
+ If unsupported bits are set in Flags.
+ If both COMMA_TYPE and RADIX_HEX are set in
+ Flags.
+ If Width >= MAXIMUM_VALUE_CHARACTERS.
+
+**/
+RETURN_STATUS
+EFIAPI
+UnicodeValueToStringS (
+ IN OUT CHAR16 *Buffer,
+ IN UINTN BufferSize,
+ IN UINTN Flags,
+ IN INT64 Value,
+ IN UINTN Width
+ );
+
+/**
+ Produces a Null-terminated ASCII string in an output buffer based on a Null-terminated
+ ASCII format string and a VA_LIST argument list.
+
+ This function is similar as vsnprintf_s defined in C11.
+
+ Produces a Null-terminated ASCII string in the output buffer specified by StartOfBuffer
+ and BufferSize.
+ The ASCII string is produced by parsing the format string specified by FormatString.
+ Arguments are pulled from the variable argument list specified by Marker based on
+ the contents of the format string.
+ The number of ASCII characters in the produced output buffer is returned not including
+ the Null-terminator.
+
+ If BufferSize > 0 and StartOfBuffer is NULL, then ASSERT(). Also, the output buffer is
+ unmodified and 0 is returned.
+ If BufferSize > 0 and FormatString is NULL, then ASSERT(). Also, the output buffer is
+ unmodified and 0 is returned.
+ If PcdMaximumAsciiStringLength is not zero, and BufferSize >
+ (PcdMaximumAsciiStringLength * sizeof (CHAR8)), then ASSERT(). Also, the output buffer
+ is unmodified and 0 is returned.
+ If PcdMaximumAsciiStringLength is not zero, and FormatString contains more than
+ PcdMaximumAsciiStringLength Ascii characters not including the Null-terminator, then
+ ASSERT(). Also, the output buffer is unmodified and 0 is returned.
+
+ If BufferSize is 0, then no output buffer is produced and 0 is returned.
+
+ @param StartOfBuffer A pointer to the output buffer for the produced Null-terminated
+ ASCII string.
+ @param BufferSize The size, in bytes, of the output buffer specified by StartOfBuffer.
+ @param FormatString A Null-terminated ASCII format string.
+ @param Marker VA_LIST marker for the variable argument list.
+
+ @return The number of ASCII characters in the produced output buffer not including the
+ Null-terminator.
+
+**/
+UINTN
+EFIAPI
+AsciiVSPrint (
+ OUT CHAR8 *StartOfBuffer,
+ IN UINTN BufferSize,
+ IN CONST CHAR8 *FormatString,
+ IN VA_LIST Marker
+ );
+
+/**
+ Produces a Null-terminated ASCII string in an output buffer based on a Null-terminated
+ ASCII format string and a BASE_LIST argument list.
+
+ Produces a Null-terminated ASCII string in the output buffer specified by StartOfBuffer
+ and BufferSize.
+ The ASCII string is produced by parsing the format string specified by FormatString.
+ Arguments are pulled from the variable argument list specified by Marker based on
+ the contents of the format string.
+ The number of ASCII characters in the produced output buffer is returned not including
+ the Null-terminator.
+
+ If BufferSize > 0 and StartOfBuffer is NULL, then ASSERT(). Also, the output buffer is
+ unmodified and 0 is returned.
+ If BufferSize > 0 and FormatString is NULL, then ASSERT(). Also, the output buffer is
+ unmodified and 0 is returned.
+ If PcdMaximumAsciiStringLength is not zero, and BufferSize >
+ (PcdMaximumAsciiStringLength * sizeof (CHAR8)), then ASSERT(). Also, the output buffer
+ is unmodified and 0 is returned.
+ If PcdMaximumAsciiStringLength is not zero, and FormatString contains more than
+ PcdMaximumAsciiStringLength Ascii characters not including the Null-terminator, then
+ ASSERT(). Also, the output buffer is unmodified and 0 is returned.
+
+ If BufferSize is 0, then no output buffer is produced and 0 is returned.
+
+ @param StartOfBuffer A pointer to the output buffer for the produced Null-terminated
+ ASCII string.
+ @param BufferSize The size, in bytes, of the output buffer specified by StartOfBuffer.
+ @param FormatString A Null-terminated ASCII format string.
+ @param Marker BASE_LIST marker for the variable argument list.
+
+ @return The number of ASCII characters in the produced output buffer not including the
+ Null-terminator.
+
+**/
+UINTN
+EFIAPI
+AsciiBSPrint (
+ OUT CHAR8 *StartOfBuffer,
+ IN UINTN BufferSize,
+ IN CONST CHAR8 *FormatString,
+ IN BASE_LIST Marker
+ );
+
+/**
+ Produces a Null-terminated ASCII string in an output buffer based on a Null-terminated
+ ASCII format string and variable argument list.
+
+ This function is similar as snprintf_s defined in C11.
+
+ Produces a Null-terminated ASCII string in the output buffer specified by StartOfBuffer
+ and BufferSize.
+ The ASCII string is produced by parsing the format string specified by FormatString.
+ Arguments are pulled from the variable argument list based on the contents of the
+ format string.
+ The number of ASCII characters in the produced output buffer is returned not including
+ the Null-terminator.
+
+ If BufferSize > 0 and StartOfBuffer is NULL, then ASSERT(). Also, the output buffer is
+ unmodified and 0 is returned.
+ If BufferSize > 0 and FormatString is NULL, then ASSERT(). Also, the output buffer is
+ unmodified and 0 is returned.
+ If PcdMaximumAsciiStringLength is not zero, and BufferSize >
+ (PcdMaximumAsciiStringLength * sizeof (CHAR8)), then ASSERT(). Also, the output buffer
+ is unmodified and 0 is returned.
+ If PcdMaximumAsciiStringLength is not zero, and FormatString contains more than
+ PcdMaximumAsciiStringLength Ascii characters not including the Null-terminator, then
+ ASSERT(). Also, the output buffer is unmodified and 0 is returned.
+
+ If BufferSize is 0, then no output buffer is produced and 0 is returned.
+
+ @param StartOfBuffer A pointer to the output buffer for the produced Null-terminated
+ ASCII string.
+ @param BufferSize The size, in bytes, of the output buffer specified by StartOfBuffer.
+ @param FormatString A Null-terminated ASCII format string.
+ @param ... Variable argument list whose contents are accessed based on the
+ format string specified by FormatString.
+
+ @return The number of ASCII characters in the produced output buffer not including the
+ Null-terminator.
+
+**/
+UINTN
+EFIAPI
+AsciiSPrint (
+ OUT CHAR8 *StartOfBuffer,
+ IN UINTN BufferSize,
+ IN CONST CHAR8 *FormatString,
+ ...
+ );
+
+/**
+ Produces a Null-terminated ASCII string in an output buffer based on a Null-terminated
+ Unicode format string and a VA_LIST argument list.
+
+ This function is similar as vsnprintf_s defined in C11.
+
+ Produces a Null-terminated ASCII string in the output buffer specified by StartOfBuffer
+ and BufferSize.
+ The ASCII string is produced by parsing the format string specified by FormatString.
+ Arguments are pulled from the variable argument list specified by Marker based on
+ the contents of the format string.
+ The number of ASCII characters in the produced output buffer is returned not including
+ the Null-terminator.
+
+ If FormatString is not aligned on a 16-bit boundary, then ASSERT().
+
+ If BufferSize > 0 and StartOfBuffer is NULL, then ASSERT(). Also, the output buffer is
+ unmodified and 0 is returned.
+ If BufferSize > 0 and FormatString is NULL, then ASSERT(). Also, the output buffer is
+ unmodified and 0 is returned.
+ If PcdMaximumAsciiStringLength is not zero, and BufferSize >
+ (PcdMaximumAsciiStringLength * sizeof (CHAR8)), then ASSERT(). Also, the output buffer
+ is unmodified and 0 is returned.
+ If PcdMaximumUnicodeStringLength is not zero, and FormatString contains more than
+ PcdMaximumUnicodeStringLength Unicode characters not including the Null-terminator, then
+ ASSERT(). Also, the output buffer is unmodified and 0 is returned.
+
+ If BufferSize is 0, then no output buffer is produced and 0 is returned.
+
+ @param StartOfBuffer A pointer to the output buffer for the produced Null-terminated
+ ASCII string.
+ @param BufferSize The size, in bytes, of the output buffer specified by StartOfBuffer.
+ @param FormatString A Null-terminated Unicode format string.
+ @param Marker VA_LIST marker for the variable argument list.
+
+ @return The number of ASCII characters in the produced output buffer not including the
+ Null-terminator.
+
+**/
+UINTN
+EFIAPI
+AsciiVSPrintUnicodeFormat (
+ OUT CHAR8 *StartOfBuffer,
+ IN UINTN BufferSize,
+ IN CONST CHAR16 *FormatString,
+ IN VA_LIST Marker
+ );
+
+/**
+ Produces a Null-terminated ASCII string in an output buffer based on a Null-terminated
+ Unicode format string and a BASE_LIST argument list.
+
+ Produces a Null-terminated ASCII string in the output buffer specified by StartOfBuffer
+ and BufferSize.
+ The ASCII string is produced by parsing the format string specified by FormatString.
+ Arguments are pulled from the variable argument list specified by Marker based on
+ the contents of the format string.
+ The number of ASCII characters in the produced output buffer is returned not including
+ the Null-terminator.
+
+ If FormatString is not aligned on a 16-bit boundary, then ASSERT().
+
+ If BufferSize > 0 and StartOfBuffer is NULL, then ASSERT(). Also, the output buffer is
+ unmodified and 0 is returned.
+ If BufferSize > 0 and FormatString is NULL, then ASSERT(). Also, the output buffer is
+ unmodified and 0 is returned.
+ If PcdMaximumAsciiStringLength is not zero, and BufferSize >
+ (PcdMaximumAsciiStringLength * sizeof (CHAR8)), then ASSERT(). Also, the output buffer
+ is unmodified and 0 is returned.
+ If PcdMaximumUnicodeStringLength is not zero, and FormatString contains more than
+ PcdMaximumUnicodeStringLength Unicode characters not including the Null-terminator, then
+ ASSERT(). Also, the output buffer is unmodified and 0 is returned.
+
+ If BufferSize is 0, then no output buffer is produced and 0 is returned.
+
+ @param StartOfBuffer A pointer to the output buffer for the produced Null-terminated
+ ASCII string.
+ @param BufferSize The size, in bytes, of the output buffer specified by StartOfBuffer.
+ @param FormatString A Null-terminated Unicode format string.
+ @param Marker BASE_LIST marker for the variable argument list.
+
+ @return The number of ASCII characters in the produced output buffer not including the
+ Null-terminator.
+
+**/
+UINTN
+EFIAPI
+AsciiBSPrintUnicodeFormat (
+ OUT CHAR8 *StartOfBuffer,
+ IN UINTN BufferSize,
+ IN CONST CHAR16 *FormatString,
+ IN BASE_LIST Marker
+ );
+
+/**
+ Produces a Null-terminated ASCII string in an output buffer based on a Null-terminated
+ Unicode format string and variable argument list.
+
+ This function is similar as snprintf_s defined in C11.
+
+ Produces a Null-terminated ASCII string in the output buffer specified by StartOfBuffer
+ and BufferSize.
+ The ASCII string is produced by parsing the format string specified by FormatString.
+ Arguments are pulled from the variable argument list based on the contents of the
+ format string.
+ The number of ASCII characters in the produced output buffer is returned not including
+ the Null-terminator.
+
+ If FormatString is not aligned on a 16-bit boundary, then ASSERT().
+
+ If BufferSize > 0 and StartOfBuffer is NULL, then ASSERT(). Also, the output buffer is
+ unmodified and 0 is returned.
+ If BufferSize > 0 and FormatString is NULL, then ASSERT(). Also, the output buffer is
+ unmodified and 0 is returned.
+ If PcdMaximumAsciiStringLength is not zero, and BufferSize >
+ (PcdMaximumAsciiStringLength * sizeof (CHAR8)), then ASSERT(). Also, the output buffer
+ is unmodified and 0 is returned.
+ If PcdMaximumUnicodeStringLength is not zero, and FormatString contains more than
+ PcdMaximumUnicodeStringLength Unicode characters not including the Null-terminator, then
+ ASSERT(). Also, the output buffer is unmodified and 0 is returned.
+
+ If BufferSize is 0, then no output buffer is produced and 0 is returned.
+
+ @param StartOfBuffer A pointer to the output buffer for the produced Null-terminated
+ ASCII string.
+ @param BufferSize The size, in bytes, of the output buffer specified by StartOfBuffer.
+ @param FormatString A Null-terminated Unicode format string.
+ @param ... Variable argument list whose contents are accessed based on the
+ format string specified by FormatString.
+
+ @return The number of ASCII characters in the produced output buffer not including the
+ Null-terminator.
+
+**/
+UINTN
+EFIAPI
+AsciiSPrintUnicodeFormat (
+ OUT CHAR8 *StartOfBuffer,
+ IN UINTN BufferSize,
+ IN CONST CHAR16 *FormatString,
+ ...
+ );
+
+/**
+ Converts a decimal value to a Null-terminated Ascii string.
+
+ Converts the decimal number specified by Value to a Null-terminated Ascii
+ string specified by Buffer containing at most Width characters. No padding of
+ spaces is ever performed. If Width is 0 then a width of
+ MAXIMUM_VALUE_CHARACTERS is assumed. If the conversion contains more than
+ Width characters, then only the first Width characters are placed in Buffer.
+ Additional conversion parameters are specified in Flags.
+
+ The Flags bit LEFT_JUSTIFY is always ignored.
+ All conversions are left justified in Buffer.
+ If Width is 0, PREFIX_ZERO is ignored in Flags.
+ If COMMA_TYPE is set in Flags, then PREFIX_ZERO is ignored in Flags, and
+ commas are inserted every 3rd digit starting from the right.
+ If RADIX_HEX is set in Flags, then the output buffer will be formatted in
+ hexadecimal format.
+ If Value is < 0 and RADIX_HEX is not set in Flags, then the fist character in
+ Buffer is a '-'.
+ If PREFIX_ZERO is set in Flags and PREFIX_ZERO is not being ignored, then
+ Buffer is padded with '0' characters so the combination of the optional '-'
+ sign character, '0' characters, digit characters for Value, and the
+ Null-terminator add up to Width characters.
+
+ If an error would be returned, then the function will ASSERT().
+
+ @param Buffer The pointer to the output buffer for the produced
+ Null-terminated Ascii string.
+ @param BufferSize The size of Buffer in bytes, including the
+ Null-terminator.
+ @param Flags The bitmask of flags that specify left justification,
+ zero pad, and commas.
+ @param Value The 64-bit signed value to convert to a string.
+ @param Width The maximum number of Ascii characters to place in
+ Buffer, not including the Null-terminator.
+
+ @retval RETURN_SUCCESS The decimal value is converted.
+ @retval RETURN_BUFFER_TOO_SMALL If BufferSize cannot hold the converted
+ value.
+ @retval RETURN_INVALID_PARAMETER If Buffer is NULL.
+ If PcdMaximumAsciiStringLength is not
+ zero, and BufferSize is greater than
+ PcdMaximumAsciiStringLength.
+ If unsupported bits are set in Flags.
+ If both COMMA_TYPE and RADIX_HEX are set in
+ Flags.
+ If Width >= MAXIMUM_VALUE_CHARACTERS.
+
+**/
+RETURN_STATUS
+EFIAPI
+AsciiValueToStringS (
+ IN OUT CHAR8 *Buffer,
+ IN UINTN BufferSize,
+ IN UINTN Flags,
+ IN INT64 Value,
+ IN UINTN Width
+ );
+
+/**
+ Returns the number of characters that would be produced by if the formatted
+ output were produced not including the Null-terminator.
+
+ If FormatString is not aligned on a 16-bit boundary, then ASSERT().
+
+ If FormatString is NULL, then ASSERT() and 0 is returned.
+ If PcdMaximumUnicodeStringLength is not zero, and FormatString contains more
+ than PcdMaximumUnicodeStringLength Unicode characters not including the
+ Null-terminator, then ASSERT() and 0 is returned.
+
+ @param[in] FormatString A Null-terminated Unicode format string.
+ @param[in] Marker VA_LIST marker for the variable argument list.
+
+ @return The number of characters that would be produced, not including the
+ Null-terminator.
+**/
+UINTN
+EFIAPI
+SPrintLength (
+ IN CONST CHAR16 *FormatString,
+ IN VA_LIST Marker
+ );
+
+/**
+ Returns the number of characters that would be produced by if the formatted
+ output were produced not including the Null-terminator.
+
+ If FormatString is NULL, then ASSERT() and 0 is returned.
+ If PcdMaximumAsciiStringLength is not zero, and FormatString contains more
+ than PcdMaximumAsciiStringLength Ascii characters not including the
+ Null-terminator, then ASSERT() and 0 is returned.
+
+ @param[in] FormatString A Null-terminated ASCII format string.
+ @param[in] Marker VA_LIST marker for the variable argument list.
+
+ @return The number of characters that would be produced, not including the
+ Null-terminator.
+**/
+UINTN
+EFIAPI
+SPrintLengthAsciiFormat (
+ IN CONST CHAR8 *FormatString,
+ IN VA_LIST Marker
+ );
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/RegisterFilterLib.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/RegisterFilterLib.h
new file mode 100644
index 0000000000..e51d218019
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/RegisterFilterLib.h
@@ -0,0 +1,244 @@
+/** @file
+ Public include file for the Port IO/MMIO/MSR RegisterFilterLib.
+
+Copyright (c) 2021, Intel Corporation. All rights reserved.
+
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef REGISTER_FILTER_LIB_H_
+#define REGISTER_FILTER_LIB_H_
+
+typedef enum {
+ FilterWidth8,
+ FilterWidth16,
+ FilterWidth32,
+ FilterWidth64
+} FILTER_IO_WIDTH;
+
+/**
+ Filter IO read operation before read IO port.
+ It is used to filter IO read operation.
+
+ It will return the flag to decide whether require read real IO port.
+ It can be used for emulation environment.
+
+ @param[in] Width Signifies the width of the I/O operation.
+ @param[in] Address The base address of the I/O operation.
+ @param[in] Buffer The destination buffer to store the results.
+
+ @retval TRUE Need to excute the IO read.
+ @retval FALSE Skip the IO read.
+
+**/
+BOOLEAN
+EFIAPI
+FilterBeforeIoRead (
+ IN FILTER_IO_WIDTH Width,
+ IN UINTN Address,
+ IN OUT VOID *Buffer
+ );
+
+/**
+ Trace IO read operation after read IO port.
+ It is used to trace IO operation.
+
+ @param[in] Width Signifies the width of the I/O operation.
+ @param[in] Address The base address of the I/O operation.
+ @param[in] Buffer The destination buffer to store the results.
+
+**/
+VOID
+EFIAPI
+FilterAfterIoRead (
+ IN FILTER_IO_WIDTH Width,
+ IN UINTN Address,
+ IN VOID *Buffer
+ );
+
+/**
+ Filter IO Write operation before wirte IO port.
+ It is used to filter IO operation.
+
+ It will return the flag to decide whether require read write IO port.
+ It can be used for emulation environment.
+
+ @param[in] Width Signifies the width of the I/O operation.
+ @param[in] Address The base address of the I/O operation.
+ @param[in] Buffer The source buffer from which to BeforeWrite data.
+
+ @retval TRUE Need to excute the IO write.
+ @retval FALSE Skip the IO write.
+
+**/
+BOOLEAN
+EFIAPI
+FilterBeforeIoWrite (
+ IN FILTER_IO_WIDTH Width,
+ IN UINTN Address,
+ IN VOID *Buffer
+ );
+
+/**
+Trace IO Write operation after wirte IO port.
+It is used to trace IO operation.
+
+@param[in] Width Signifies the width of the I/O operation.
+@param[in] Address The base address of the I/O operation.
+@param[in] Buffer The source buffer from which to BeforeWrite data.
+
+**/
+VOID
+EFIAPI
+FilterAfterIoWrite (
+ IN FILTER_IO_WIDTH Width,
+ IN UINTN Address,
+ IN VOID *Buffer
+ );
+
+/**
+ Filter memory IO before Read operation.
+
+ It will return the flag to decide whether require read real MMIO.
+ It can be used for emulation environment.
+
+ @param[in] Width Signifies the width of the memory I/O operation.
+ @param[in] Address The base address of the memory I/O operation.
+ @param[in] Buffer The destination buffer to store the results.
+
+ @retval TRUE Need to excute the MMIO read.
+ @retval FALSE Skip the MMIO read.
+
+**/
+BOOLEAN
+EFIAPI
+FilterBeforeMmIoRead (
+ IN FILTER_IO_WIDTH Width,
+ IN UINTN Address,
+ IN OUT VOID *Buffer
+ );
+
+/**
+ Tracer memory IO after read operation
+
+ @param[in] Width Signifies the width of the memory I/O operation.
+ @param[in] Address The base address of the memory I/O operation.
+ @param[in] Buffer The destination buffer to store the results.
+
+**/
+VOID
+EFIAPI
+FilterAfterMmIoRead (
+ IN FILTER_IO_WIDTH Width,
+ IN UINTN Address,
+ IN VOID *Buffer
+ );
+
+/**
+ Filter memory IO before write operation
+
+ It will return the flag to decide whether require wirte real MMIO.
+ It can be used for emulation environment.
+
+ @param[in] Width Signifies the width of the memory I/O operation.
+ @param[in] Address The base address of the memory I/O operation.
+ @param[in] Buffer The source buffer from which to BeforeWrite data.
+
+ @retval TRUE Need to excute the MMIO write.
+ @retval FALSE Skip the MMIO write.
+
+**/
+BOOLEAN
+EFIAPI
+FilterBeforeMmIoWrite (
+ IN FILTER_IO_WIDTH Width,
+ IN UINTN Address,
+ IN VOID *Buffer
+ );
+
+/**
+ Tracer memory IO after write operation
+
+ @param[in] Width Signifies the width of the memory I/O operation.
+ @param[in] Address The base address of the memory I/O operation.
+ @param[in] Buffer The source buffer from which to BeforeWrite data.
+
+**/
+VOID
+EFIAPI
+FilterAfterMmIoWrite (
+ IN FILTER_IO_WIDTH Width,
+ IN UINTN Address,
+ IN VOID *Buffer
+ );
+
+/**
+ Filter MSR before read operation.
+
+ It will return the flag to decide whether require read real MSR.
+ It can be used for emulation environment.
+
+ @param Index The 8-bit Machine Specific Register index to BeforeWrite.
+ @param Value The 64-bit value to BeforeRead from the Machine Specific Register.
+
+ @retval TRUE Need to excute the MSR read.
+ @retval FALSE Skip the MSR read.
+
+**/
+BOOLEAN
+EFIAPI
+FilterBeforeMsrRead (
+ IN UINT32 Index,
+ IN OUT UINT64 *Value
+ );
+
+/**
+ Trace MSR after read operation
+
+ @param Index The 8-bit Machine Specific Register index to BeforeWrite.
+ @param Value The 64-bit value to BeforeRead from the Machine Specific Register.
+
+**/
+VOID
+EFIAPI
+FilterAfterMsrRead (
+ IN UINT32 Index,
+ IN UINT64 *Value
+ );
+
+/**
+ Filter MSR before write operation
+
+ It will return the flag to decide whether require write real MSR.
+ It can be used for emulation environment.
+
+ @param Index The 8-bit Machine Specific Register index to BeforeWrite.
+ @param Value The 64-bit value to BeforeWrite to the Machine Specific Register.
+
+ @retval TRUE Need to excute the MSR write.
+ @retval FALSE Skip the MSR write.
+
+**/
+BOOLEAN
+EFIAPI
+FilterBeforeMsrWrite (
+ IN UINT32 Index,
+ IN UINT64 *Value
+ );
+
+/**
+ Trace MSR after write operation
+
+ @param Index The 8-bit Machine Specific Register index to BeforeWrite.
+ @param Value The 64-bit value to BeforeWrite to the Machine Specific Register.
+
+**/
+VOID
+EFIAPI
+FilterAfterMsrWrite (
+ IN UINT32 Index,
+ IN UINT64 *Value
+ );
+
+#endif // REGISTER_FILTER_LIB_H_
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/ReportStatusCodeLib.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/ReportStatusCodeLib.h
new file mode 100644
index 0000000000..7999effaa7
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/ReportStatusCodeLib.h
@@ -0,0 +1,474 @@
+/** @file
+ Provides services to log status code records.
+
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __REPORT_STATUS_CODE_LIB_H__
+#define __REPORT_STATUS_CODE_LIB_H__
+
+#include
+#include
+#include
+
+//
+// Declare bits for PcdReportStatusCodePropertyMask
+//
+#define REPORT_STATUS_CODE_PROPERTY_PROGRESS_CODE_ENABLED 0x00000001
+#define REPORT_STATUS_CODE_PROPERTY_ERROR_CODE_ENABLED 0x00000002
+#define REPORT_STATUS_CODE_PROPERTY_DEBUG_CODE_ENABLED 0x00000004
+
+/**
+ Converts a status code to an 8-bit POST code value.
+
+ Converts the status code specified by CodeType and Value to an 8-bit POST code
+ and returns the 8-bit POST code in PostCode. If CodeType is an
+ EFI_PROGRESS_CODE or CodeType is an EFI_ERROR_CODE, then bits 0..4 of PostCode
+ are set to bits 16..20 of Value, and bits 5..7 of PostCode are set to bits
+ 24..26 of Value., and TRUE is returned. Otherwise, FALSE is returned.
+
+ If PostCode is NULL, then ASSERT().
+
+ @param CodeType The type of status code being converted.
+ @param Value The status code value being converted.
+ @param PostCode A pointer to the 8-bit POST code value to return.
+
+ @retval TRUE The status code specified by CodeType and Value was converted
+ to an 8-bit POST code and returned in PostCode.
+ @retval FALSE The status code specified by CodeType and Value could not be
+ converted to an 8-bit POST code value.
+
+**/
+BOOLEAN
+EFIAPI
+CodeTypeToPostCode (
+ IN EFI_STATUS_CODE_TYPE CodeType,
+ IN EFI_STATUS_CODE_VALUE Value,
+ OUT UINT8 *PostCode
+ );
+
+/**
+ Extracts ASSERT() information from a status code structure.
+
+ Converts the status code specified by CodeType, Value, and Data to the ASSERT()
+ arguments specified by Filename, Description, and LineNumber. If CodeType is
+ an EFI_ERROR_CODE, and CodeType has a severity of EFI_ERROR_UNRECOVERED, and
+ Value has an operation mask of EFI_SW_EC_ILLEGAL_SOFTWARE_STATE, extract
+ Filename, Description, and LineNumber from the optional data area of the
+ status code buffer specified by Data. The optional data area of Data contains
+ a Null-terminated ASCII string for the FileName, followed by a Null-terminated
+ ASCII string for the Description, followed by a 32-bit LineNumber. If the
+ ASSERT() information could be extracted from Data, then return TRUE.
+ Otherwise, FALSE is returned.
+
+ If Data is NULL, then ASSERT().
+ If Filename is NULL, then ASSERT().
+ If Description is NULL, then ASSERT().
+ If LineNumber is NULL, then ASSERT().
+
+ @param CodeType The type of status code being converted.
+ @param Value The status code value being converted.
+ @param Data The pointer to status code data buffer.
+ @param Filename The pointer to the source file name that generated the ASSERT().
+ @param Description The pointer to the description of the ASSERT().
+ @param LineNumber The pointer to source line number that generated the ASSERT().
+
+ @retval TRUE The status code specified by CodeType, Value, and Data was
+ converted ASSERT() arguments specified by Filename, Description,
+ and LineNumber.
+ @retval FALSE The status code specified by CodeType, Value, and Data could
+ not be converted to ASSERT() arguments.
+
+**/
+BOOLEAN
+EFIAPI
+ReportStatusCodeExtractAssertInfo (
+ IN EFI_STATUS_CODE_TYPE CodeType,
+ IN EFI_STATUS_CODE_VALUE Value,
+ IN CONST EFI_STATUS_CODE_DATA *Data,
+ OUT CHAR8 **Filename,
+ OUT CHAR8 **Description,
+ OUT UINT32 *LineNumber
+ );
+
+/**
+ Extracts DEBUG() information from a status code structure.
+
+ Converts the status code specified by Data to the DEBUG() arguments specified
+ by ErrorLevel, Marker, and Format. If type GUID in Data is
+ EFI_STATUS_CODE_DATA_TYPE_DEBUG_GUID, then extract ErrorLevel, Marker, and
+ Format from the optional data area of the status code buffer specified by Data.
+ The optional data area of Data contains a 32-bit ErrorLevel followed by Marker
+ which is 12 UINTN parameters, followed by a Null-terminated ASCII string for
+ the Format. If the DEBUG() information could be extracted from Data, then
+ return TRUE. Otherwise, FALSE is returned.
+
+ If Data is NULL, then ASSERT().
+ If ErrorLevel is NULL, then ASSERT().
+ If Marker is NULL, then ASSERT().
+ If Format is NULL, then ASSERT().
+
+ @param Data The pointer to status code data buffer.
+ @param ErrorLevel The pointer to error level mask for a debug message.
+ @param Marker The pointer to the variable argument list associated with Format.
+ @param Format The pointer to a Null-terminated ASCII format string of a
+ debug message.
+
+ @retval TRUE The status code specified by Data was converted DEBUG() arguments
+ specified by ErrorLevel, Marker, and Format.
+ @retval FALSE The status code specified by Data could not be converted to
+ DEBUG() arguments.
+
+**/
+BOOLEAN
+EFIAPI
+ReportStatusCodeExtractDebugInfo (
+ IN CONST EFI_STATUS_CODE_DATA *Data,
+ OUT UINT32 *ErrorLevel,
+ OUT BASE_LIST *Marker,
+ OUT CHAR8 **Format
+ );
+
+/**
+ Reports a status code.
+
+ Reports the status code specified by the parameters Type and Value. Status
+ code also require an instance, caller ID, and extended data. This function
+ passed in a zero instance, NULL extended data, and a caller ID of
+ gEfiCallerIdGuid, which is the GUID for the module.
+
+ ReportStatusCode()must actively prevent recursion. If ReportStatusCode()
+ is called while processing another any other Report Status Code Library function,
+ then ReportStatusCode() must return immediately.
+
+ @param Type Status code type.
+ @param Value Status code value.
+
+ @retval EFI_SUCCESS The status code was reported.
+ @retval EFI_DEVICE_ERROR There status code could not be reported due to a
+ device error.
+ @retval EFI_UNSUPPORTED The report status code is not supported.
+
+**/
+EFI_STATUS
+EFIAPI
+ReportStatusCode (
+ IN EFI_STATUS_CODE_TYPE Type,
+ IN EFI_STATUS_CODE_VALUE Value
+ );
+
+/**
+ Reports a status code with a Device Path Protocol as the extended data.
+
+ Allocates and fills in the extended data section of a status code with the
+ Device Path Protocol specified by DevicePath. This function is responsible
+ for allocating a buffer large enough for the standard header and the device
+ path. The standard header is filled in with an implementation dependent GUID.
+ The status code is reported with a zero instance and a caller ID of gEfiCallerIdGuid.
+
+ ReportStatusCodeWithDevicePath()must actively prevent recursion. If
+ ReportStatusCodeWithDevicePath() is called while processing another any other
+ Report Status Code Library function, then ReportStatusCodeWithDevicePath()
+ must return EFI_DEVICE_ERROR immediately.
+
+ If DevicePath is NULL, then ASSERT().
+
+ @param Type The status code type.
+ @param Value The status code value.
+ @param DevicePath The pointer to the Device Path Protocol to be reported.
+
+ @retval EFI_SUCCESS The status code was reported with the extended
+ data specified by DevicePath.
+ @retval EFI_OUT_OF_RESOURCES There were not enough resources to allocate the
+ extended data section.
+ @retval EFI_UNSUPPORTED The report status code is not supported.
+ @retval EFI_DEVICE_ERROR A call to a Report Status Code Library function
+ is already in progress.
+
+**/
+EFI_STATUS
+EFIAPI
+ReportStatusCodeWithDevicePath (
+ IN EFI_STATUS_CODE_TYPE Type,
+ IN EFI_STATUS_CODE_VALUE Value,
+ IN CONST EFI_DEVICE_PATH_PROTOCOL *DevicePath
+ );
+
+/**
+ Reports a status code with an extended data buffer.
+
+ Allocates and fills in the extended data section of a status code with the
+ extended data specified by ExtendedData and ExtendedDataSize. ExtendedData
+ is assumed to be one of the data structures specified in Related Definitions.
+ These data structure do not have the standard header, so this function is
+ responsible for allocating a buffer large enough for the standard header and
+ the extended data passed into this function. The standard header is filled
+ in with an implementation dependent GUID. The status code is reported
+ with a zero instance and a caller ID of gEfiCallerIdGuid.
+
+ ReportStatusCodeWithExtendedData()must actively prevent recursion. If
+ ReportStatusCodeWithExtendedData() is called while processing another any other
+ Report Status Code Library function, then ReportStatusCodeWithExtendedData()
+ must return EFI_DEVICE_ERROR immediately.
+
+ If ExtendedData is NULL, then ASSERT().
+ If ExtendedDataSize is 0, then ASSERT().
+
+ @param Type The status code type.
+ @param Value The status code value.
+ @param ExtendedData The pointer to the extended data buffer to be reported.
+ @param ExtendedDataSize The size, in bytes, of the extended data buffer to
+ be reported.
+
+ @retval EFI_SUCCESS The status code was reported with the extended
+ data specified by ExtendedData and ExtendedDataSize.
+ @retval EFI_OUT_OF_RESOURCES There were not enough resources to allocate the
+ extended data section.
+ @retval EFI_UNSUPPORTED The report status code is not supported.
+ @retval EFI_DEVICE_ERROR A call to a Report Status Code Library function
+ is already in progress.
+
+**/
+EFI_STATUS
+EFIAPI
+ReportStatusCodeWithExtendedData (
+ IN EFI_STATUS_CODE_TYPE Type,
+ IN EFI_STATUS_CODE_VALUE Value,
+ IN CONST VOID *ExtendedData,
+ IN UINTN ExtendedDataSize
+ );
+
+/**
+ Reports a status code with full parameters.
+
+ The function reports a status code. If ExtendedData is NULL and ExtendedDataSize
+ is 0, then an extended data buffer is not reported. If ExtendedData is not
+ NULL and ExtendedDataSize is not 0, then an extended data buffer is allocated.
+ ExtendedData is assumed not have the standard status code header, so this function
+ is responsible for allocating a buffer large enough for the standard header and
+ the extended data passed into this function. The standard header is filled in
+ with a GUID specified by ExtendedDataGuid. If ExtendedDataGuid is NULL, then a
+ GUID of gEfiStatusCodeSpecificDataGuid is used. The status code is reported with
+ an instance specified by Instance and a caller ID specified by CallerId. If
+ CallerId is NULL, then a caller ID of gEfiCallerIdGuid is used.
+
+ ReportStatusCodeEx()must actively prevent recursion. If ReportStatusCodeEx()
+ is called while processing another any other Report Status Code Library function,
+ then ReportStatusCodeEx() must return EFI_DEVICE_ERROR immediately.
+
+ If ExtendedData is NULL and ExtendedDataSize is not zero, then ASSERT().
+ If ExtendedData is not NULL and ExtendedDataSize is zero, then ASSERT().
+
+ @param Type The status code type.
+ @param Value The status code value.
+ @param Instance The status code instance number.
+ @param CallerId The pointer to a GUID that identifies the caller of this
+ function. If this parameter is NULL, then a caller
+ ID of gEfiCallerIdGuid is used.
+ @param ExtendedDataGuid The pointer to the GUID for the extended data buffer.
+ If this parameter is NULL, then a the status code
+ standard header is filled in with an implementation dependent GUID.
+ @param ExtendedData The pointer to the extended data buffer. This is an
+ optional parameter that may be NULL.
+ @param ExtendedDataSize The size, in bytes, of the extended data buffer.
+
+ @retval EFI_SUCCESS The status code was reported.
+ @retval EFI_OUT_OF_RESOURCES There were not enough resources to allocate
+ the extended data section if it was specified.
+ @retval EFI_UNSUPPORTED The report status code is not supported.
+ @retval EFI_DEVICE_ERROR A call to a Report Status Code Library function
+ is already in progress.
+
+**/
+EFI_STATUS
+EFIAPI
+ReportStatusCodeEx (
+ IN EFI_STATUS_CODE_TYPE Type,
+ IN EFI_STATUS_CODE_VALUE Value,
+ IN UINT32 Instance,
+ IN CONST EFI_GUID *CallerId OPTIONAL,
+ IN CONST EFI_GUID *ExtendedDataGuid OPTIONAL,
+ IN CONST VOID *ExtendedData OPTIONAL,
+ IN UINTN ExtendedDataSize
+ );
+
+/**
+ Returns TRUE if status codes of type EFI_PROGRESS_CODE are enabled
+
+ This function returns TRUE if the REPORT_STATUS_CODE_PROPERTY_PROGRESS_CODE_ENABLED
+ bit of PcdReportStatusCodeProperyMask is set. Otherwise FALSE is returned.
+
+ @retval TRUE The REPORT_STATUS_CODE_PROPERTY_PROGRESS_CODE_ENABLED bit of
+ PcdReportStatusCodeProperyMask is set.
+ @retval FALSE The REPORT_STATUS_CODE_PROPERTY_PROGRESS_CODE_ENABLED bit of
+ PcdReportStatusCodeProperyMask is clear.
+
+**/
+BOOLEAN
+EFIAPI
+ReportProgressCodeEnabled (
+ VOID
+ );
+
+/**
+ Returns TRUE if status codes of type EFI_ERROR_CODE are enabled
+
+ This function returns TRUE if the REPORT_STATUS_CODE_PROPERTY_ERROR_CODE_ENABLED
+ bit of PcdReportStatusCodeProperyMask is set. Otherwise, FALSE is returned.
+
+ @retval TRUE The REPORT_STATUS_CODE_PROPERTY_ERROR_CODE_ENABLED bit of
+ PcdReportStatusCodeProperyMask is set.
+ @retval FALSE The REPORT_STATUS_CODE_PROPERTY_ERROR_CODE_ENABLED bit of
+ PcdReportStatusCodeProperyMask is clear.
+
+**/
+BOOLEAN
+EFIAPI
+ReportErrorCodeEnabled (
+ VOID
+ );
+
+/**
+ Returns TRUE if status codes of type EFI_DEBUG_CODE are enabled
+
+ This function returns TRUE if the REPORT_STATUS_CODE_PROPERTY_DEBUG_CODE_ENABLED
+ bit of PcdReportStatusCodeProperyMask is set. Otherwise FALSE is returned.
+
+ @retval TRUE The REPORT_STATUS_CODE_PROPERTY_DEBUG_CODE_ENABLED bit of
+ PcdReportStatusCodeProperyMask is set.
+ @retval FALSE The REPORT_STATUS_CODE_PROPERTY_DEBUG_CODE_ENABLED bit of
+ PcdReportStatusCodeProperyMask is clear.
+
+**/
+BOOLEAN
+EFIAPI
+ReportDebugCodeEnabled (
+ VOID
+ );
+
+/**
+ Reports a status code with minimal parameters if the status code type is enabled.
+
+ If the status code type specified by Type is enabled in
+ PcdReportStatusCodeProperyMask, then call ReportStatusCode() passing in Type
+ and Value.
+
+ @param Type The status code type.
+ @param Value The status code value.
+
+ @retval EFI_SUCCESS The status code was reported.
+ @retval EFI_DEVICE_ERROR There status code could not be reported due to a device error.
+ @retval EFI_UNSUPPORTED Report status code is not supported.
+
+**/
+#define REPORT_STATUS_CODE(Type, Value) \
+ (ReportProgressCodeEnabled() && ((Type) & EFI_STATUS_CODE_TYPE_MASK) == EFI_PROGRESS_CODE) ? \
+ ReportStatusCode(Type,Value) : \
+ (ReportErrorCodeEnabled() && ((Type) & EFI_STATUS_CODE_TYPE_MASK) == EFI_ERROR_CODE) ? \
+ ReportStatusCode(Type,Value) : \
+ (ReportDebugCodeEnabled() && ((Type) & EFI_STATUS_CODE_TYPE_MASK) == EFI_DEBUG_CODE) ? \
+ ReportStatusCode(Type,Value) : \
+ EFI_UNSUPPORTED
+
+/**
+ Reports a status code with a Device Path Protocol as the extended data if the
+ status code type is enabled.
+
+ If the status code type specified by Type is enabled in
+ PcdReportStatusCodeProperyMask, then call ReportStatusCodeWithDevicePath()
+ passing in Type, Value, and DevicePath.
+
+ @param Type The status code type.
+ @param Value The status code value.
+ @param DevicePath Pointer to the Device Path Protocol to be reported.
+
+ @retval EFI_SUCCESS The status code was reported with the extended
+ data specified by DevicePath.
+ @retval EFI_OUT_OF_RESOURCES There were not enough resources to allocate the
+ extended data section.
+ @retval EFI_UNSUPPORTED The report status code is not supported.
+ @retval EFI_DEVICE_ERROR A call to a Report Status Code Library function
+ is already in progress.
+
+**/
+#define REPORT_STATUS_CODE_WITH_DEVICE_PATH(Type, Value, DevicePathParameter) \
+ (ReportProgressCodeEnabled() && ((Type) & EFI_STATUS_CODE_TYPE_MASK) == EFI_PROGRESS_CODE) ? \
+ ReportStatusCodeWithDevicePath(Type,Value,DevicePathParameter) : \
+ (ReportErrorCodeEnabled() && ((Type) & EFI_STATUS_CODE_TYPE_MASK) == EFI_ERROR_CODE) ? \
+ ReportStatusCodeWithDevicePath(Type,Value,DevicePathParameter) : \
+ (ReportDebugCodeEnabled() && ((Type) & EFI_STATUS_CODE_TYPE_MASK) == EFI_DEBUG_CODE) ? \
+ ReportStatusCodeWithDevicePath(Type,Value,DevicePathParameter) : \
+ EFI_UNSUPPORTED
+
+/**
+ Reports a status code with an extended data buffer if the status code type
+ is enabled.
+
+ If the status code type specified by Type is enabled in
+ PcdReportStatusCodeProperyMask, then call ReportStatusCodeWithExtendedData()
+ passing in Type, Value, ExtendedData, and ExtendedDataSize.
+
+ @param Type The status code type.
+ @param Value The status code value.
+ @param ExtendedData The pointer to the extended data buffer to be reported.
+ @param ExtendedDataSize The size, in bytes, of the extended data buffer to
+ be reported.
+
+ @retval EFI_SUCCESS The status code was reported with the extended
+ data specified by ExtendedData and ExtendedDataSize.
+ @retval EFI_OUT_OF_RESOURCES There were not enough resources to allocate the
+ extended data section.
+ @retval EFI_UNSUPPORTED The report status code is not supported.
+ @retval EFI_DEVICE_ERROR A call to a Report Status Code Library function
+ is already in progress.
+
+**/
+#define REPORT_STATUS_CODE_WITH_EXTENDED_DATA(Type, Value, ExtendedData, ExtendedDataSize) \
+ (ReportProgressCodeEnabled() && ((Type) & EFI_STATUS_CODE_TYPE_MASK) == EFI_PROGRESS_CODE) ? \
+ ReportStatusCodeWithExtendedData(Type,Value,ExtendedData,ExtendedDataSize) : \
+ (ReportErrorCodeEnabled() && ((Type) & EFI_STATUS_CODE_TYPE_MASK) == EFI_ERROR_CODE) ? \
+ ReportStatusCodeWithExtendedData(Type,Value,ExtendedData,ExtendedDataSize) : \
+ (ReportDebugCodeEnabled() && ((Type) & EFI_STATUS_CODE_TYPE_MASK) == EFI_DEBUG_CODE) ? \
+ ReportStatusCodeWithExtendedData(Type,Value,ExtendedData,ExtendedDataSize) : \
+ EFI_UNSUPPORTED
+
+/**
+ Reports a status code specifying all parameters if the status code type is enabled.
+
+ If the status code type specified by Type is enabled in
+ PcdReportStatusCodeProperyMask, then call ReportStatusCodeEx() passing in Type,
+ Value, Instance, CallerId, ExtendedDataGuid, ExtendedData, and ExtendedDataSize.
+
+ @param Type The status code type.
+ @param Value The status code value.
+ @param Instance The status code instance number.
+ @param CallerId The pointer to a GUID that identifies the caller of this
+ function. If this parameter is NULL, then a caller
+ ID of gEfiCallerIdGuid is used.
+ @param ExtendedDataGuid Pointer to the GUID for the extended data buffer.
+ If this parameter is NULL, then a the status code
+ standard header is filled in with an implementation dependent GUID.
+ @param ExtendedData Pointer to the extended data buffer. This is an
+ optional parameter that may be NULL.
+ @param ExtendedDataSize The size, in bytes, of the extended data buffer.
+
+ @retval EFI_SUCCESS The status code was reported.
+ @retval EFI_OUT_OF_RESOURCES There were not enough resources to allocate the
+ extended data section if it was specified.
+ @retval EFI_UNSUPPORTED The report status code is not supported.
+ @retval EFI_DEVICE_ERROR A call to a Report Status Code Library function
+ is already in progress.
+
+**/
+#define REPORT_STATUS_CODE_EX(Type, Value, Instance, CallerId, ExtendedDataGuid, ExtendedData, ExtendedDataSize) \
+ (ReportProgressCodeEnabled() && ((Type) & EFI_STATUS_CODE_TYPE_MASK) == EFI_PROGRESS_CODE) ? \
+ ReportStatusCodeEx(Type,Value,Instance,CallerId,ExtendedDataGuid,ExtendedData,ExtendedDataSize) : \
+ (ReportErrorCodeEnabled() && ((Type) & EFI_STATUS_CODE_TYPE_MASK) == EFI_ERROR_CODE) ? \
+ ReportStatusCodeEx(Type,Value,Instance,CallerId,ExtendedDataGuid,ExtendedData,ExtendedDataSize) : \
+ (ReportDebugCodeEnabled() && ((Type) & EFI_STATUS_CODE_TYPE_MASK) == EFI_DEBUG_CODE) ? \
+ ReportStatusCodeEx(Type,Value,Instance,CallerId,ExtendedDataGuid,ExtendedData,ExtendedDataSize) : \
+ EFI_UNSUPPORTED
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/ResourcePublicationLib.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/ResourcePublicationLib.h
new file mode 100644
index 0000000000..357c4aa532
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/ResourcePublicationLib.h
@@ -0,0 +1,36 @@
+/** @file
+ Provides a service to publish discovered system resources.
+
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __RESOURCE_PUBLICATION_LIB__
+#define __RESOURCE_PUBLICATION_LIB__
+
+/**
+ Declares the presence of permanent system memory in the platform.
+
+ Declares that the system memory buffer specified by MemoryBegin and MemoryLength
+ as permanent memory that may be used for general purpose use by software.
+ The amount of memory available to software may be less than MemoryLength
+ if published memory has alignment restrictions.
+ If MemoryLength is 0, then ASSERT().
+ If MemoryLength is greater than (MAX_ADDRESS - MemoryBegin + 1), then ASSERT().
+
+ @param MemoryBegin The start address of the memory being declared.
+ @param MemoryLength The number of bytes of memory being declared.
+
+ @retval RETURN_SUCCESS The memory buffer was published.
+ @retval RETURN_OUT_OF_RESOURCES There are not enough resources to publish the memory buffer
+
+**/
+RETURN_STATUS
+EFIAPI
+PublishSystemMemory (
+ IN PHYSICAL_ADDRESS MemoryBegin,
+ IN UINT64 MemoryLength
+ );
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/RngLib.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/RngLib.h
new file mode 100644
index 0000000000..1aff366689
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/RngLib.h
@@ -0,0 +1,80 @@
+/** @file
+ Provides random number generator services.
+
+Copyright (c) 2015, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __RNG_LIB_H__
+#define __RNG_LIB_H__
+
+/**
+ Generates a 16-bit random number.
+
+ if Rand is NULL, then ASSERT().
+
+ @param[out] Rand Buffer pointer to store the 16-bit random value.
+
+ @retval TRUE Random number generated successfully.
+ @retval FALSE Failed to generate the random number.
+
+**/
+BOOLEAN
+EFIAPI
+GetRandomNumber16 (
+ OUT UINT16 *Rand
+ );
+
+/**
+ Generates a 32-bit random number.
+
+ if Rand is NULL, then ASSERT().
+
+ @param[out] Rand Buffer pointer to store the 32-bit random value.
+
+ @retval TRUE Random number generated successfully.
+ @retval FALSE Failed to generate the random number.
+
+**/
+BOOLEAN
+EFIAPI
+GetRandomNumber32 (
+ OUT UINT32 *Rand
+ );
+
+/**
+ Generates a 64-bit random number.
+
+ if Rand is NULL, then ASSERT().
+
+ @param[out] Rand Buffer pointer to store the 64-bit random value.
+
+ @retval TRUE Random number generated successfully.
+ @retval FALSE Failed to generate the random number.
+
+**/
+BOOLEAN
+EFIAPI
+GetRandomNumber64 (
+ OUT UINT64 *Rand
+ );
+
+/**
+ Generates a 128-bit random number.
+
+ if Rand is NULL, then ASSERT().
+
+ @param[out] Rand Buffer pointer to store the 128-bit random value.
+
+ @retval TRUE Random number generated successfully.
+ @retval FALSE Failed to generate the random number.
+
+**/
+BOOLEAN
+EFIAPI
+GetRandomNumber128 (
+ OUT UINT64 *Rand
+ );
+
+#endif // __RNG_LIB_H__
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/S3BootScriptLib.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/S3BootScriptLib.h
new file mode 100644
index 0000000000..4cf1042489
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/S3BootScriptLib.h
@@ -0,0 +1,601 @@
+/** @file
+ Defines library APIs used by modules to save EFI Boot Script Opcodes.
+ These OpCode will be restored by S3 related modules.
+ Note that some of the API defined in the Library class may not
+ be provided in the Framework version library instance, which means some of these
+ APIs cannot be used if the underlying firmware is Framework and not PI.
+
+ Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _S3_BOOT_SCRIPT_LIB_H_
+#define _S3_BOOT_SCRIPT_LIB_H_
+
+#include
+#include
+
+/**
+ Macro that converts PCI Bus, PCI Device, PCI Function and PCI Register to an
+ address that can be passed to the S3 Boot Script Library PCI functions.
+
+ @param Bus PCI Bus number. Range 0..255.
+ @param Device PCI Device number. Range 0..31.
+ @param Function PCI Function number. Range 0..7.
+ @param Register PCI Register number. Range 0..255 for PCI. Range 0..4095
+ for PCI Express.
+
+ @return The encoded PCI address.
+
+**/
+#define S3_BOOT_SCRIPT_LIB_PCI_ADDRESS(Bus, Device, Function, Register) \
+ (UINT64) ( \
+ (((UINTN) Bus) << 24) | \
+ (((UINTN) Device) << 16) | \
+ (((UINTN) Function) << 8) | \
+ (((UINTN) (Register)) < 256 ? ((UINTN) (Register)) : (UINT64) (LShiftU64 ((UINT64) (Register), 32))))
+
+///
+/// S3 Boot Script Width.
+///
+typedef enum {
+ S3BootScriptWidthUint8, ///< 8-bit operation.
+ S3BootScriptWidthUint16, ///< 16-bit operation.
+ S3BootScriptWidthUint32, ///< 32-bit operation.
+ S3BootScriptWidthUint64, ///< 64-bit operation.
+ S3BootScriptWidthFifoUint8, ///< 8-bit FIFO operation.
+ S3BootScriptWidthFifoUint16, ///< 16-bit FIFO operation.
+ S3BootScriptWidthFifoUint32, ///< 32-bit FIFO operation.
+ S3BootScriptWidthFifoUint64, ///< 64-bit FIFO operation.
+ S3BootScriptWidthFillUint8, ///< 8-bit Fill operation.
+ S3BootScriptWidthFillUint16, ///< 16-bit Fill operation.
+ S3BootScriptWidthFillUint32, ///< 32-bit Fill operation.
+ S3BootScriptWidthFillUint64, ///< 64-bit Fill operation.
+ S3BootScriptWidthMaximum
+} S3_BOOT_SCRIPT_LIB_WIDTH;
+
+/**
+ Save I/O write to boot script.
+
+ @param[in] Width The width of the I/O operations.
+ @param[in] Address The base address of the I/O operations.
+ @param[in] Count The number of I/O operations to perform.
+ @param[in] Buffer The source buffer from which to write data.
+
+ @retval RETURN_OUT_OF_RESOURCES Not enough memory for the table to perform
+ the operation.
+ @retval RETURN_SUCCESS The opcode was added.
+
+**/
+RETURN_STATUS
+EFIAPI
+S3BootScriptSaveIoWrite (
+ IN S3_BOOT_SCRIPT_LIB_WIDTH Width,
+ IN UINT64 Address,
+ IN UINTN Count,
+ IN VOID *Buffer
+ );
+
+/**
+ Adds a record for an I/O modify operation into a S3 boot script table.
+
+ @param[in] Width The width of the I/O operations.
+ @param[in] Address The base address of the I/O operations.
+ @param[in] Data A pointer to the data to be OR-ed.
+ @param[in] DataMask A pointer to the data mask to be AND-ed with the data
+ read from the register.
+
+ @retval RETURN_OUT_OF_RESOURCES Not enough memory for the table to perform
+ the operation.
+ @retval RETURN_SUCCESS The opcode was added.
+
+**/
+RETURN_STATUS
+EFIAPI
+S3BootScriptSaveIoReadWrite (
+ IN S3_BOOT_SCRIPT_LIB_WIDTH Width,
+ IN UINT64 Address,
+ IN VOID *Data,
+ IN VOID *DataMask
+ );
+
+/**
+ Adds a record for a memory write operation into a specified boot script table.
+
+ @param[in] Width The width of the I/O operations.
+ @param[in] Address The base address of the memory operations
+ @param[in] Count The number of memory operations to perform.
+ @param[in] Buffer The source buffer from which to write the data.
+
+ @retval RETURN_OUT_OF_RESOURCES Not enough memory for the table to perform
+ the operation.
+ @retval RETURN_SUCCESS The opcode was added.
+**/
+RETURN_STATUS
+EFIAPI
+S3BootScriptSaveMemWrite (
+ IN S3_BOOT_SCRIPT_LIB_WIDTH Width,
+ IN UINT64 Address,
+ IN UINTN Count,
+ IN VOID *Buffer
+ );
+
+/**
+ Adds a record for a memory modify operation into a specified boot script table.
+
+ @param[in] Width The width of the I/O operations.
+ @param[in] Address The base address of the memory operations. Address needs
+ alignment, if required
+ @param[in] Data A pointer to the data to be OR-ed.
+ @param[in] DataMask A pointer to the data mask to be AND-ed with the data
+ read from the register.
+
+ @retval RETURN_OUT_OF_RESOURCES Not enough memory for the table to perform
+ the operation.
+ @retval RETURN_SUCCESS The opcode was added.
+**/
+RETURN_STATUS
+EFIAPI
+S3BootScriptSaveMemReadWrite (
+ IN S3_BOOT_SCRIPT_LIB_WIDTH Width,
+ IN UINT64 Address,
+ IN VOID *Data,
+ IN VOID *DataMask
+ );
+
+/**
+ Adds a record for a PCI configuration space write operation into a specified boot script table.
+
+ @param[in] Width The width of the I/O operations.
+ @param[in] Address The address within the PCI configuration space.
+ @param[in] Count The number of PCI operations to perform.
+ @param[in] Buffer The source buffer from which to write the data.
+
+ @retval RETURN_OUT_OF_RESOURCES Not enough memory for the table to perform
+ the operation.
+ @retval RETURN_SUCCESS The opcode was added.
+**/
+RETURN_STATUS
+EFIAPI
+S3BootScriptSavePciCfgWrite (
+ IN S3_BOOT_SCRIPT_LIB_WIDTH Width,
+ IN UINT64 Address,
+ IN UINTN Count,
+ IN VOID *Buffer
+ );
+
+/**
+ Adds a record for a PCI configuration space modify operation into a specified boot script table.
+
+ @param[in] Width The width of the I/O operations.
+ @param[in] Address The address within the PCI configuration space.
+ @param[in] Data A pointer to the data to be OR-ed.The size depends on Width.
+ @param[in] DataMask A pointer to the data mask to be AND-ed.
+
+ @retval RETURN_OUT_OF_RESOURCES Not enough memory for the table to perform
+ the operation.
+ @retval RETURN__SUCCESS The opcode was added.
+**/
+RETURN_STATUS
+EFIAPI
+S3BootScriptSavePciCfgReadWrite (
+ IN S3_BOOT_SCRIPT_LIB_WIDTH Width,
+ IN UINT64 Address,
+ IN VOID *Data,
+ IN VOID *DataMask
+ );
+
+/**
+ Adds a record for a PCI configuration space modify operation into a specified boot script table.
+
+ @param[in] Width The width of the I/O operations.
+ @param[in] Segment The PCI segment number for Address.
+ @param[in] Address The address within the PCI configuration space.
+ @param[in] Count The number of PCI operations to perform.
+ @param[in] Buffer The source buffer from which to write the data.
+
+ @retval RETURN_OUT_OF_RESOURCES Not enough memory for the table to perform
+ the operation.
+ @retval RETURN_SUCCESS The opcode was added.
+**/
+RETURN_STATUS
+EFIAPI
+S3BootScriptSavePciCfg2Write (
+ IN S3_BOOT_SCRIPT_LIB_WIDTH Width,
+ IN UINT16 Segment,
+ IN UINT64 Address,
+ IN UINTN Count,
+ IN VOID *Buffer
+ );
+
+/**
+ Adds a record for a PCI configuration space modify operation into a specified boot script table.
+
+ @param[in] Width The width of the I/O operations.
+ @param[in] Segment The PCI segment number for Address.
+ @param[in] Address The address within the PCI configuration space.
+ @param[in] Data A pointer to the data to be OR-ed. The size depends on Width.
+ @param[in] DataMask A pointer to the data mask to be AND-ed.
+
+ @retval RETURN_OUT_OF_RESOURCES Not enough memory for the table to perform
+ the operation.
+ @retval RETURN_SUCCESS The opcode was added.
+**/
+RETURN_STATUS
+EFIAPI
+S3BootScriptSavePciCfg2ReadWrite (
+ IN S3_BOOT_SCRIPT_LIB_WIDTH Width,
+ IN UINT16 Segment,
+ IN UINT64 Address,
+ IN VOID *Data,
+ IN VOID *DataMask
+ );
+
+/**
+ Adds a record for an SMBus command execution into a specified boot script table.
+
+ @param[in] SmBusAddress Address that encodes the SMBUS Slave Address, SMBUS
+ Command, SMBUS Data Length, and PEC.
+ @param[in] Operation Indicates which particular SMBus protocol it will use
+ to execute the SMBus transactions.
+ @param[in] Length A pointer to signify the number of bytes that this
+ operation will do.
+ @param[in] Buffer Contains the value of data to execute to the SMBUS
+ slave device.
+
+ @retval RETURN_OUT_OF_RESOURCES Not enough memory for the table to perform
+ the operation.
+ @retval RETURN_SUCCESS The opcode was added.
+**/
+RETURN_STATUS
+EFIAPI
+S3BootScriptSaveSmbusExecute (
+ IN UINTN SmBusAddress,
+ IN EFI_SMBUS_OPERATION Operation,
+ IN UINTN *Length,
+ IN VOID *Buffer
+ );
+
+/**
+ Adds a record for an execution stall on the processor into a specified boot script table.
+
+ @param[in] Duration The duration in microseconds of the stall.
+
+ @retval RETURN_OUT_OF_RESOURCES Not enough memory for the table to perform
+ the operation.
+ @retval RETURN_SUCCESS The opcode was added.
+**/
+RETURN_STATUS
+EFIAPI
+S3BootScriptSaveStall (
+ IN UINTN Duration
+ );
+
+/**
+ Adds a record for dispatching specified arbitrary code into a specified boot script table.
+
+ @param[in] EntryPoint The entry point of the code to be dispatched.
+ @param[in] Context The argument to be passed into the EntryPoint of the code
+ to be dispatched.
+
+ @retval RETURN_OUT_OF_RESOURCES Not enough memory for the table to perform
+ the operation.
+ @retval RETURN_SUCCESS The opcode was added.
+**/
+RETURN_STATUS
+EFIAPI
+S3BootScriptSaveDispatch2 (
+ IN VOID *EntryPoint,
+ IN VOID *Context
+ );
+
+/**
+ Adds a record for dispatching specified arbitrary code into a specified boot script table.
+
+ @param[in] EntryPoint The entry point of the code to be dispatched.
+
+ @retval RETURN_OUT_OF_RESOURCES Not enough memory for the table to perform
+ the operation.
+ @retval RETURN_SUCCESS The opcode was added.
+**/
+RETURN_STATUS
+EFIAPI
+S3BootScriptSaveDispatch (
+ IN VOID *EntryPoint
+ );
+
+/**
+ Adds a record for memory reads of the memory location and continues when the exit
+ criteria is satisfied, or after a defined duration.
+
+ Please aware, below interface is different with PI specification, Vol 5:
+ EFI_S3_SAVE_STATE_PROTOCOL.Write() for EFI_BOOT_SCRIPT_MEM_POLL_OPCODE.
+ "Duration" below is microseconds, while "Delay" in PI specification means
+ the number of 100ns units to poll.
+
+ @param[in] Width The width of the memory operations.
+ @param[in] Address The base address of the memory operations.
+ @param[in] BitMask A pointer to the bit mask to be AND-ed with the data read
+ from the register.
+ @param[in] BitValue A pointer to the data value after to be Masked.
+ @param[in] Duration The duration in microseconds of the stall.
+ @param[in] LoopTimes The times of the register polling.
+
+ @retval RETURN_OUT_OF_RESOURCES Not enough memory for the table to perform
+ the operation.
+ @retval RETURN_SUCCESS The opcode was added.
+
+**/
+RETURN_STATUS
+EFIAPI
+S3BootScriptSaveMemPoll (
+ IN S3_BOOT_SCRIPT_LIB_WIDTH Width,
+ IN UINT64 Address,
+ IN VOID *BitMask,
+ IN VOID *BitValue,
+ IN UINTN Duration,
+ IN UINT64 LoopTimes
+ );
+
+/**
+ Store arbitrary information in the boot script table. This opcode is a no-op on
+ dispatch and is only used for debugging script issues.
+
+ @param[in] InformationLength Length of the data in bytes
+ @param[in] Information Information to be logged in the boot scrpit
+
+ @retval RETURN_OUT_OF_RESOURCES Not enough memory for the table to perform
+ the operation.
+ @retval RETURN_SUCCESS The opcode was added.
+
+**/
+RETURN_STATUS
+EFIAPI
+S3BootScriptSaveInformation (
+ IN UINT32 InformationLength,
+ IN VOID *Information
+ );
+
+/**
+ Adds a record for I/O reads the I/O location and continues when the exit criteria
+ is satisfied, or after a defined duration.
+
+ @param Width The width of the I/O operations.
+ @param Address The base address of the I/O operations.
+ @param Data The comparison value used for the polling exit criteria.
+ @param DataMask The mask used for the polling criteria. The bits in
+ the bytes below Width which are zero in Data are
+ ignored when polling the memory address.
+ @param Delay The number of 100ns units to poll. Note that timer
+ available may be of insufficient granularity, so the
+ delay may be longer.
+
+ @retval RETURN_OUT_OF_RESOURCES Not enough memory for the table to perform the
+ operation.
+ @retval RETURN_SUCCESS The opcode was added.
+ @note The FRAMEWORK version implementation does not support this API
+**/
+RETURN_STATUS
+EFIAPI
+S3BootScriptSaveIoPoll (
+ IN S3_BOOT_SCRIPT_LIB_WIDTH Width,
+ IN UINT64 Address,
+ IN VOID *Data,
+ IN VOID *DataMask,
+ IN UINT64 Delay
+ );
+
+/**
+ Adds a record for PCI configuration space reads and continues when the exit
+ criteria is satisfied ,or after a defined duration.
+
+ @param Width The width of the I/O operations.
+ @param Address The address within the PCI configuration space.
+ @param Data The comparison value used for the polling exit
+ criteria.
+ @param DataMask Mask used for the polling criteria. The bits in
+ the bytes below Width which are zero in Data are
+ ignored when polling the memory address.
+ @param Delay The number of 100ns units to poll. Note that timer
+ available may be of insufficient granularity, so the
+ delay may be longer.
+
+ @retval RETURN_OUT_OF_RESOURCES Not enough memory for the table to perform the
+ operation.
+ @retval RETURN_SUCCESS The opcode was added.
+ @note The FRAMEWORK version implementation does not support this API
+**/
+RETURN_STATUS
+EFIAPI
+S3BootScriptSavePciPoll (
+ IN S3_BOOT_SCRIPT_LIB_WIDTH Width,
+ IN UINT64 Address,
+ IN VOID *Data,
+ IN VOID *DataMask,
+ IN UINT64 Delay
+ );
+
+/**
+ Adds a record for PCI configuration space reads and continues when the exit criteria
+ is satisfied, or after a defined duration.
+
+ @param Width The width of the I/O operations.
+ @param Segment The PCI segment number for Address.
+ @param Address The address within the PCI configuration space.
+ @param Data The comparison value used for the polling exit
+ criteria.
+ @param DataMask Mask used for the polling criteria. The bits in
+ the bytes below Width which are zero
+ in Data are ignored when polling the memory address
+ @param Delay The number of 100ns units to poll. Note that timer
+ available may be of insufficient granularity so the delay
+ may be longer.
+
+ @retval RETURN_OUT_OF_RESOURCES Not enough memory for the table to perform the
+ operation.
+ @retval RETURN_SUCCESS The opcode was added.
+ @note A known Limitations in the implementation: When interpreting the opcode
+ EFI_BOOT_SCRIPT_PCI_CONFIG2_WRITE_OPCODE, EFI_BOOT_SCRIPT_PCI_CONFIG2_READ_WRITE_OPCODE
+ and EFI_BOOT_SCRIPT_PCI_CONFIG2_POLL_OPCODE, the 'Segment' parameter is assumed as
+ Zero, or else, assert.
+ The FRAMEWORK version implementation does not support this API.
+
+**/
+RETURN_STATUS
+EFIAPI
+S3BootScriptSavePci2Poll (
+ IN S3_BOOT_SCRIPT_LIB_WIDTH Width,
+ IN UINT16 Segment,
+ IN UINT64 Address,
+ IN VOID *Data,
+ IN VOID *DataMask,
+ IN UINT64 Delay
+ );
+
+/**
+ Save ASCII string information specified by Buffer to boot script with opcode
+ EFI_BOOT_SCRIPT_INFORMATION_OPCODE.
+
+ @param[in] String The Null-terminated ASCII string to store into the S3 boot
+ script table.
+
+ @retval RETURN_OUT_OF_RESOURCES Not enough memory for the table to perform
+ the operation.
+ @retval RETURN_SUCCESS The opcode was added.
+
+**/
+RETURN_STATUS
+EFIAPI
+S3BootScriptSaveInformationAsciiString (
+ IN CONST CHAR8 *String
+ );
+
+/**
+ This is an function to close the S3 boot script table. The function could only
+ be called in BOOT time phase. To comply with the Framework spec definition on
+ EFI_BOOT_SCRIPT_SAVE_PROTOCOL.CloseTable(), this function will fulfill following things:
+ 1. Closes the specified boot script table
+ 2. It allocates a new memory pool to duplicate all the boot scripts in the specified table.
+ Once this function is called, the table maintained by the library will be destroyed
+ after it is copied into the allocated pool.
+ 3. Any attempts to add a script record after calling this function will cause a
+ new table to be created by the library.
+ 4. The base address of the allocated pool will be returned in Address. Note that
+ after using the boot script table, the CALLER is responsible for freeing the
+ pool that is allocated by this function.
+
+ In Spec PI1.1, this EFI_BOOT_SCRIPT_SAVE_PROTOCOL.CloseTable() is retired. This
+ API is supplied here to meet the requirements of the Framework Spec.
+
+ If anyone does call CloseTable() on a real platform, then the caller is responsible
+ for figuring out how to get the script to run on an S3 resume because the boot script
+ maintained by the lib will be destroyed.
+
+ @return the base address of the new copy of the boot script table.
+
+**/
+UINT8 *
+EFIAPI
+S3BootScriptCloseTable (
+ VOID
+ );
+
+/**
+ Executes the S3 boot script table.
+
+ @retval RETURN_SUCCESS The boot script table was executed successfully.
+ @retval RETURN_UNSUPPORTED Invalid script table or opcode.
+
+**/
+RETURN_STATUS
+EFIAPI
+S3BootScriptExecute (
+ VOID
+ );
+
+/**
+ Move the last boot script entry to the position
+
+ @param BeforeOrAfter Specifies whether the opcode is stored before
+ (TRUE) or after (FALSE) the positionin the boot
+ script table specified by Position. If Position
+ is NULL or points to NULL then the new opcode is
+ inserted at the beginning of the table (if TRUE)
+ or end of the table (if FALSE).
+ @param Position On entry, specifies the position in the boot script
+ table where the opcode will be inserted, either
+ before or after, depending on BeforeOrAfter. On
+ exit, specifies the position of the inserted opcode
+ in the boot script table.
+
+ @retval RETURN_OUT_OF_RESOURCES The table is not available.
+ @retval RETURN_INVALID_PARAMETER The Position is not a valid position in the
+ boot script table.
+ @retval RETURN_SUCCESS The opcode was inserted.
+ @note The FRAMEWORK version implementation does not support this API.
+**/
+RETURN_STATUS
+EFIAPI
+S3BootScriptMoveLastOpcode (
+ IN BOOLEAN BeforeOrAfter,
+ IN OUT VOID **Position OPTIONAL
+ );
+
+/**
+ Find a label within the boot script table and, if not present, optionally create it.
+
+ @param BeforeOrAfter Specifies whether the opcode is stored before (TRUE)
+ or after (FALSE) the position in the boot script table
+ specified by Position.
+ @param CreateIfNotFound Specifies whether the label will be created if the
+ label does not exists (TRUE) or not (FALSE).
+ @param Position On entry, specifies the position in the boot script
+ table where the opcode will be inserted, either
+ before or after, depending on BeforeOrAfter. On exit,
+ specifies the positionof the inserted opcode in
+ the boot script table.
+ @param Label Points to the label which will be inserted in the
+ boot script table.
+ @retval EFI_SUCCESS The operation succeeded. A record was added into
+ the specified script table.
+ @retval EFI_INVALID_PARAMETER The parameter is illegal or the given boot script
+ is not supported. If the opcode is unknow or not
+ supported because of the PCD Feature Flags.
+ @retval EFI_OUT_OF_RESOURCES There is insufficient memory to store the boot script.
+ @note The FRAMEWORK version implementation does not support this API
+
+**/
+RETURN_STATUS
+EFIAPI
+S3BootScriptLabel (
+ IN BOOLEAN BeforeOrAfter,
+ IN BOOLEAN CreateIfNotFound,
+ IN OUT VOID **Position OPTIONAL,
+ IN CONST CHAR8 *Label
+ );
+
+/**
+ Compare two positions in the boot script table and return their relative position.
+ @param Position1 The positions in the boot script table to compare
+ @param Position2 The positions in the boot script table to compare
+ @param RelativePosition On return, points to the result of the comparison
+
+ @retval EFI_SUCCESS The operation succeeded. A record was added into the
+ specified script table.
+ @retval EFI_INVALID_PARAMETER The parameter is illegal or the given boot script
+ is not supported. If the opcode is unknow or not s
+ upported because of the PCD Feature Flags.
+ @retval EFI_OUT_OF_RESOURCES There is insufficient memory to store the boot script.
+ @note The FRAMEWORK version implementation does not support this API
+**/
+RETURN_STATUS
+EFIAPI
+S3BootScriptCompare (
+ IN UINT8 *Position1,
+ IN UINT8 *Position2,
+ OUT UINTN *RelativePosition
+ );
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/S3IoLib.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/S3IoLib.h
new file mode 100644
index 0000000000..dc473d9c62
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/S3IoLib.h
@@ -0,0 +1,2670 @@
+/** @file
+ I/O and MMIO Library Services that do I/O and also enable the I/O operation
+ to be replayed during an S3 resume. This library class maps directly on top
+ of the IoLib class.
+
+ Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __S3_IO_LIB_H__
+#define __S3_IO_LIB_H__
+
+/**
+ Reads an 8-bit I/O port and saves the value in the S3 script to be replayed
+ on S3 resume.
+
+ Reads the 8-bit I/O port specified by Port. The 8-bit read value is returned.
+ This function must guarantee that all I/O read and write operations are
+ serialized.
+
+ If 8-bit I/O port operations are not supported, then ASSERT().
+
+ @param[in] Port The I/O port to read.
+
+ @return The value read.
+
+**/
+UINT8
+EFIAPI
+S3IoRead8 (
+ IN UINTN Port
+ );
+
+/**
+ Writes an 8-bit I/O port, and saves the value in the S3 script to be replayed
+ on S3 resume.
+
+ Writes the 8-bit I/O port specified by Port with the value specified by Value
+ and returns Value. This function must guarantee that all I/O read and write
+ operations are serialized.
+
+ If 8-bit I/O port operations are not supported, then ASSERT().
+
+ @param[in] Port The I/O port to write.
+ @param[in] Value The value to write to the I/O port.
+
+ @return The value written the I/O port.
+
+**/
+UINT8
+EFIAPI
+S3IoWrite8 (
+ IN UINTN Port,
+ IN UINT8 Value
+ );
+
+/**
+ Reads an 8-bit I/O port, performs a bitwise OR, writes the
+ result back to the 8-bit I/O port, and saves the value in the S3 script to be
+ replayed on S3 resume.
+
+ Reads the 8-bit I/O port specified by Port, performs a bitwise OR
+ between the read result and the value specified by OrData, and writes the
+ result to the 8-bit I/O port specified by Port. The value written to the I/O
+ port is returned. This function must guarantee that all I/O read and write
+ operations are serialized.
+
+ If 8-bit I/O port operations are not supported, then ASSERT().
+
+ @param[in] Port The I/O port to write.
+ @param[in] OrData The value to OR with the read value from the I/O port.
+
+ @return The value written back to the I/O port.
+
+**/
+UINT8
+EFIAPI
+S3IoOr8 (
+ IN UINTN Port,
+ IN UINT8 OrData
+ );
+
+/**
+ Reads an 8-bit I/O port, performs a bitwise AND, writes the result back
+ to the 8-bit I/O port, and saves the value in the S3 script to be replayed
+ on S3 resume.
+
+ Reads the 8-bit I/O port specified by Port, performs a bitwise AND between
+ the read result and the value specified by AndData, and writes the result to
+ the 8-bit I/O port specified by Port. The value written to the I/O port is
+ returned. This function must guarantee that all I/O read and write operations
+ are serialized.
+
+ If 8-bit I/O port operations are not supported, then ASSERT().
+
+ @param[in] Port The I/O port to write.
+ @param[in] AndData The value to AND with the read value from the I/O port.
+
+ @return The value written back to the I/O port.
+
+**/
+UINT8
+EFIAPI
+S3IoAnd8 (
+ IN UINTN Port,
+ IN UINT8 AndData
+ );
+
+/**
+ Reads an 8-bit I/O port, performs a bitwise AND followed by a bitwise
+ inclusive OR, writes the result back to the 8-bit I/O port, and saves
+ the value in the S3 script to be replayed on S3 resume.
+
+ Reads the 8-bit I/O port specified by Port, performs a bitwise AND between
+ the read result and the value specified by AndData, performs a bitwise OR
+ between the result of the AND operation and the value specified by OrData,
+ and writes the result to the 8-bit I/O port specified by Port. The value
+ written to the I/O port is returned. This function must guarantee that all
+ I/O read and write operations are serialized.
+
+ If 8-bit I/O port operations are not supported, then ASSERT().
+
+ @param[in] Port The I/O port to write.
+ @param[in] AndData The value to AND with the read value from the I/O port.
+ @param[in] OrData The value to OR with the result of the AND operation.
+
+ @return The value written back to the I/O port.
+
+**/
+UINT8
+EFIAPI
+S3IoAndThenOr8 (
+ IN UINTN Port,
+ IN UINT8 AndData,
+ IN UINT8 OrData
+ );
+
+/**
+ Reads a bit field of an I/O register, and saves the value in the S3 script to
+ be replayed on S3 resume.
+
+ Reads the bit field in an 8-bit I/O register. The bit field is specified by
+ the StartBit and the EndBit. The value of the bit field is returned.
+
+ If 8-bit I/O port operations are not supported, then ASSERT().
+ If StartBit is greater than 7, then ASSERT().
+ If EndBit is greater than 7, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+
+ @param[in] Port The I/O port to read.
+ @param[in] StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..7.
+ @param[in] EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..7.
+
+ @return The value read.
+
+**/
+UINT8
+EFIAPI
+S3IoBitFieldRead8 (
+ IN UINTN Port,
+ IN UINTN StartBit,
+ IN UINTN EndBit
+ );
+
+/**
+ Writes a bit field to an I/O register and saves the value in the S3 script to
+ be replayed on S3 resume.
+
+ Writes Value to the bit field of the I/O register. The bit field is specified
+ by the StartBit and the EndBit. All other bits in the destination I/O
+ register are preserved. The value written to the I/O port is returned.
+ Remaining bits in Value are stripped.
+
+ If 8-bit I/O port operations are not supported, then ASSERT().
+ If StartBit is greater than 7, then ASSERT().
+ If EndBit is greater than 7, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param[in] Port The I/O port to write.
+ @param[in] StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..7.
+ @param[in] EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..7.
+ @param[in] Value New value of the bit field.
+
+ @return The value written back to the I/O port.
+
+**/
+UINT8
+EFIAPI
+S3IoBitFieldWrite8 (
+ IN UINTN Port,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT8 Value
+ );
+
+/**
+ Reads a bit field in an 8-bit port, performs a bitwise OR, writes the
+ result back to the bit field in the 8-bit port, and saves the value in the
+ S3 script to be replayed on S3 resume.
+
+ Reads the 8-bit I/O port specified by Port, performs a bitwise OR
+ between the read result and the value specified by OrData, and writes the
+ result to the 8-bit I/O port specified by Port. The value written to the I/O
+ port is returned. This function must guarantee that all I/O read and write
+ operations are serialized. Extra left bits in OrData are stripped.
+
+ If 8-bit I/O port operations are not supported, then ASSERT().
+ If StartBit is greater than 7, then ASSERT().
+ If EndBit is greater than 7, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param[in] Port The I/O port to write.
+ @param[in] StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..7.
+ @param[in] EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..7.
+ @param[in] OrData The value to OR with the read value from the I/O port.
+
+ @return The value written back to the I/O port.
+
+**/
+UINT8
+EFIAPI
+S3IoBitFieldOr8 (
+ IN UINTN Port,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT8 OrData
+ );
+
+/**
+ Reads a bit field in an 8-bit port, performs a bitwise AND, writes the
+ result back to the bit field in the 8-bit port, and saves the value in the
+ S3 script to be replayed on S3 resume.
+
+ Reads the 8-bit I/O port specified by Port, performs a bitwise AND between
+ the read result and the value specified by AndData, and writes the result to
+ the 8-bit I/O port specified by Port. The value written to the I/O port is
+ returned. This function must guarantee that all I/O read and write operations
+ are serialized. Extra left bits in AndData are stripped.
+
+ If 8-bit I/O port operations are not supported, then ASSERT().
+ If StartBit is greater than 7, then ASSERT().
+ If EndBit is greater than 7, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param[in] Port The I/O port to write.
+ @param[in] StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..7.
+ @param[in] EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..7.
+ @param[in] AndData The value to AND with the read value from the I/O port.
+
+ @return The value written back to the I/O port.
+
+**/
+UINT8
+EFIAPI
+S3IoBitFieldAnd8 (
+ IN UINTN Port,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT8 AndData
+ );
+
+/**
+ Reads a bit field in an 8-bit port, performs a bitwise AND followed by a
+ bitwise OR, writes the result back to the bit field in the
+ 8-bit port, and saves the value in the S3 script to be replayed on S3 resume.
+
+ Reads the 8-bit I/O port specified by Port, performs a bitwise AND followed
+ by a bitwise OR between the read result and the value specified by
+ AndData, and writes the result to the 8-bit I/O port specified by Port. The
+ value written to the I/O port is returned. This function must guarantee that
+ all I/O read and write operations are serialized. Extra left bits in both
+ AndData and OrData are stripped.
+
+ If 8-bit I/O port operations are not supported, then ASSERT().
+ If StartBit is greater than 7, then ASSERT().
+ If EndBit is greater than 7, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param[in] Port The I/O port to write.
+ @param[in] StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..7.
+ @param[in] EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..7.
+ @param[in] AndData The value to AND with the read value from the I/O port.
+ @param[in] OrData The value to OR with the result of the AND operation.
+
+ @return The value written back to the I/O port.
+
+**/
+UINT8
+EFIAPI
+S3IoBitFieldAndThenOr8 (
+ IN UINTN Port,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT8 AndData,
+ IN UINT8 OrData
+ );
+
+/**
+ Reads a 16-bit I/O port, and saves the value in the S3 script to be replayed
+ on S3 resume.
+
+ Reads the 16-bit I/O port specified by Port. The 16-bit read value is returned.
+ This function must guarantee that all I/O read and write operations are
+ serialized.
+
+ If 16-bit I/O port operations are not supported, then ASSERT().
+
+ @param[in] Port The I/O port to read.
+
+ @return The value read.
+
+**/
+UINT16
+EFIAPI
+S3IoRead16 (
+ IN UINTN Port
+ );
+
+/**
+ Writes a 16-bit I/O port, and saves the value in the S3 script to be replayed
+ on S3 resume.
+
+ Writes the 16-bit I/O port specified by Port with the value specified by Value
+ and returns Value. This function must guarantee that all I/O read and write
+ operations are serialized.
+
+ If 16-bit I/O port operations are not supported, then ASSERT().
+
+ @param[in] Port The I/O port to write.
+ @param[in] Value The value to write to the I/O port.
+
+ @return The value written the I/O port.
+
+**/
+UINT16
+EFIAPI
+S3IoWrite16 (
+ IN UINTN Port,
+ IN UINT16 Value
+ );
+
+/**
+ Reads a 16-bit I/O port, performs a bitwise OR, writes the
+ result back to the 16-bit I/O port, and saves the value in the S3 script to
+ be replayed on S3 resume.
+
+ Reads the 16-bit I/O port specified by Port, performs a bitwise OR
+ between the read result and the value specified by OrData, and writes the
+ result to the 16-bit I/O port specified by Port. The value written to the I/O
+ port is returned. This function must guarantee that all I/O read and write
+ operations are serialized.
+
+ If 16-bit I/O port operations are not supported, then ASSERT().
+
+ @param[in] Port The I/O port to write.
+ @param[in] OrData The value to OR with the read value from the I/O port.
+
+ @return The value written back to the I/O port.
+
+**/
+UINT16
+EFIAPI
+S3IoOr16 (
+ IN UINTN Port,
+ IN UINT16 OrData
+ );
+
+/**
+ Reads a 16-bit I/O port, performs a bitwise AND, writes the result back
+ to the 16-bit I/O port , and saves the value in the S3 script to be replayed
+ on S3 resume.
+
+ Reads the 16-bit I/O port specified by Port, performs a bitwise AND between
+ the read result and the value specified by AndData, and writes the result to
+ the 16-bit I/O port specified by Port. The value written to the I/O port is
+ returned. This function must guarantee that all I/O read and write operations
+ are serialized.
+
+ If 16-bit I/O port operations are not supported, then ASSERT().
+
+ @param[in] Port The I/O port to write.
+ @param[in] AndData The value to AND with the read value from the I/O port.
+
+ @return The value written back to the I/O port.
+
+**/
+UINT16
+EFIAPI
+S3IoAnd16 (
+ IN UINTN Port,
+ IN UINT16 AndData
+ );
+
+/**
+ Reads a 16-bit I/O port, performs a bitwise AND followed by a bitwise
+ inclusive OR, writes the result back to the 16-bit I/O port, and saves
+ the value in the S3 script to be replayed on S3 resume.
+
+ Reads the 16-bit I/O port specified by Port, performs a bitwise AND between
+ the read result and the value specified by AndData, performs a bitwise OR
+ between the result of the AND operation and the value specified by OrData,
+ and writes the result to the 16-bit I/O port specified by Port. The value
+ written to the I/O port is returned. This function must guarantee that all
+ I/O read and write operations are serialized.
+
+ If 16-bit I/O port operations are not supported, then ASSERT().
+
+ @param[in] Port The I/O port to write.
+ @param[in] AndData The value to AND with the read value from the I/O port.
+ @param[in] OrData The value to OR with the result of the AND operation.
+
+ @return The value written back to the I/O port.
+
+**/
+UINT16
+EFIAPI
+S3IoAndThenOr16 (
+ IN UINTN Port,
+ IN UINT16 AndData,
+ IN UINT16 OrData
+ );
+
+/**
+ Reads a bit field of an I/O register saves the value in the S3 script to be
+ replayed on S3 resume.
+
+ Reads the bit field in a 16-bit I/O register. The bit field is specified by
+ the StartBit and the EndBit. The value of the bit field is returned.
+
+ If 16-bit I/O port operations are not supported, then ASSERT().
+ If StartBit is greater than 15, then ASSERT().
+ If EndBit is greater than 15, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+
+ @param[in] Port The I/O port to read.
+ @param[in] StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..15.
+ @param[in] EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..15.
+
+ @return The value read.
+
+**/
+UINT16
+EFIAPI
+S3IoBitFieldRead16 (
+ IN UINTN Port,
+ IN UINTN StartBit,
+ IN UINTN EndBit
+ );
+
+/**
+ Writes a bit field to an I/O register, and saves the value in the S3 script
+ to be replayed on S3 resume.
+
+ Writes Value to the bit field of the I/O register. The bit field is specified
+ by the StartBit and the EndBit. All other bits in the destination I/O
+ register are preserved. The value written to the I/O port is returned. Extra
+ left bits in Value are stripped.
+
+ If 16-bit I/O port operations are not supported, then ASSERT().
+ If StartBit is greater than 15, then ASSERT().
+ If EndBit is greater than 15, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param[in] Port The I/O port to write.
+ @param[in] StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..15.
+ @param[in] EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..15.
+ @param[in] Value New value of the bit field.
+
+ @return The value written back to the I/O port.
+
+**/
+UINT16
+EFIAPI
+S3IoBitFieldWrite16 (
+ IN UINTN Port,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT16 Value
+ );
+
+/**
+ Reads a bit field in a 16-bit port, performs a bitwise OR, writes the
+ result back to the bit field in the 16-bit port, and saves the value in the
+ S3 script to be replayed on S3 resume.
+
+ Reads the 16-bit I/O port specified by Port, performs a bitwise OR
+ between the read result and the value specified by OrData, and writes the
+ result to the 16-bit I/O port specified by Port. The value written to the I/O
+ port is returned. This function must guarantee that all I/O read and write
+ operations are serialized. Extra left bits in OrData are stripped.
+
+ If 16-bit I/O port operations are not supported, then ASSERT().
+ If StartBit is greater than 15, then ASSERT().
+ If EndBit is greater than 15, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param[in] Port The I/O port to write.
+ @param[in] StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..15.
+ @param[in] EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..15.
+ @param[in] OrData The value to OR with the read value from the I/O port.
+
+ @return The value written back to the I/O port.
+
+**/
+UINT16
+EFIAPI
+S3IoBitFieldOr16 (
+ IN UINTN Port,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT16 OrData
+ );
+
+/**
+ Reads a bit field in a 16-bit port, performs a bitwise AND, writes the
+ result back to the bit field in the 16-bit port, and saves the value in the
+ S3 script to be replayed on S3 resume.
+
+ Reads the 16-bit I/O port specified by Port, performs a bitwise AND between
+ the read result and the value specified by AndData, and writes the result to
+ the 16-bit I/O port specified by Port. The value written to the I/O port is
+ returned. This function must guarantee that all I/O read and write operations
+ are serialized. Extra left bits in AndData are stripped.
+
+ If 16-bit I/O port operations are not supported, then ASSERT().
+ If StartBit is greater than 15, then ASSERT().
+ If EndBit is greater than 15, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param[in] Port The I/O port to write.
+ @param[in] StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..15.
+ @param[in] EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..15.
+ @param[in] AndData The value to AND with the read value from the I/O port.
+
+ @return The value written back to the I/O port.
+
+**/
+UINT16
+EFIAPI
+S3IoBitFieldAnd16 (
+ IN UINTN Port,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT16 AndData
+ );
+
+/**
+ Reads a bit field in a 16-bit port, performs a bitwise AND followed by a
+ bitwise OR, writes the result back to the bit field in the
+ 16-bit port, and saves the value in the S3 script to be replayed on S3
+ resume.
+
+ Reads the 16-bit I/O port specified by Port, performs a bitwise AND followed
+ by a bitwise OR between the read result and the value specified by
+ AndData, and writes the result to the 16-bit I/O port specified by Port. The
+ value written to the I/O port is returned. This function must guarantee that
+ all I/O read and write operations are serialized. Extra left bits in both
+ AndData and OrData are stripped.
+
+ If 16-bit I/O port operations are not supported, then ASSERT().
+ If StartBit is greater than 15, then ASSERT().
+ If EndBit is greater than 15, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param[in] Port The I/O port to write.
+ @param[in] StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..15.
+ @param[in] EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..15.
+ @param[in] AndData The value to AND with the read value from the I/O port.
+ @param[in] OrData The value to OR with the result of the AND operation.
+
+ @return The value written back to the I/O port.
+
+**/
+UINT16
+EFIAPI
+S3IoBitFieldAndThenOr16 (
+ IN UINTN Port,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT16 AndData,
+ IN UINT16 OrData
+ );
+
+/**
+ Reads a 32-bit I/O port, and saves the value in the S3 script to be replayed
+ on S3 resume.
+
+ Reads the 32-bit I/O port specified by Port. The 32-bit read value is returned.
+ This function must guarantee that all I/O read and write operations are
+ serialized.
+
+ If 32-bit I/O port operations are not supported, then ASSERT().
+
+ @param[in] Port The I/O port to read.
+
+ @return The value read.
+
+**/
+UINT32
+EFIAPI
+S3IoRead32 (
+ IN UINTN Port
+ );
+
+/**
+ Writes a 32-bit I/O port, and saves the value in the S3 script to be replayed
+ on S3 resume.
+
+ Writes the 32-bit I/O port specified by Port with the value specified by Value
+ and returns Value. This function must guarantee that all I/O read and write
+ operations are serialized.
+
+ If 32-bit I/O port operations are not supported, then ASSERT().
+
+ @param[in] Port The I/O port to write.
+ @param[in] Value The value to write to the I/O port.
+
+ @return The value written the I/O port.
+
+**/
+UINT32
+EFIAPI
+S3IoWrite32 (
+ IN UINTN Port,
+ IN UINT32 Value
+ );
+
+/**
+ Reads a 32-bit I/O port, performs a bitwise OR, writes the
+ result back to the 32-bit I/O port, and saves the value in the S3 script to
+ be replayed on S3 resume.
+
+ Reads the 32-bit I/O port specified by Port, performs a bitwise OR
+ between the read result and the value specified by OrData, and writes the
+ result to the 32-bit I/O port specified by Port. The value written to the I/O
+ port is returned. This function must guarantee that all I/O read and write
+ operations are serialized.
+
+ If 32-bit I/O port operations are not supported, then ASSERT().
+
+ @param[in] Port The I/O port to write.
+ @param[in] OrData The value to OR with the read value from the I/O port.
+
+ @return The value written back to the I/O port.
+
+**/
+UINT32
+EFIAPI
+S3IoOr32 (
+ IN UINTN Port,
+ IN UINT32 OrData
+ );
+
+/**
+ Reads a 32-bit I/O port, performs a bitwise AND, writes the result back
+ to the 32-bit I/O port, and saves the value in the S3 script to be replayed
+ on S3 resume.
+
+ Reads the 32-bit I/O port specified by Port, performs a bitwise AND between
+ the read result and the value specified by AndData, and writes the result to
+ the 32-bit I/O port specified by Port. The value written to the I/O port is
+ returned. This function must guarantee that all I/O read and write operations
+ are serialized.
+
+ If 32-bit I/O port operations are not supported, then ASSERT().
+
+ @param[in] Port The I/O port to write.
+ @param[in] AndData The value to AND with the read value from the I/O port.
+
+ @return The value written back to the I/O port.
+
+**/
+UINT32
+EFIAPI
+S3IoAnd32 (
+ IN UINTN Port,
+ IN UINT32 AndData
+ );
+
+/**
+ Reads a 32-bit I/O port, performs a bitwise AND followed by a bitwise
+ inclusive OR, writes the result back to the 32-bit I/O port, and saves
+ the value in the S3 script to be replayed on S3 resume.
+
+ Reads the 32-bit I/O port specified by Port, performs a bitwise AND between
+ the read result and the value specified by AndData, performs a bitwise OR
+ between the result of the AND operation and the value specified by OrData,
+ and writes the result to the 32-bit I/O port specified by Port. The value
+ written to the I/O port is returned. This function must guarantee that all
+ I/O read and write operations are serialized.
+
+ If 32-bit I/O port operations are not supported, then ASSERT().
+
+ @param[in] Port The I/O port to write.
+ @param[in] AndData The value to AND with the read value from the I/O port.
+ @param[in] OrData The value to OR with the result of the AND operation.
+
+ @return The value written back to the I/O port.
+
+**/
+UINT32
+EFIAPI
+S3IoAndThenOr32 (
+ IN UINTN Port,
+ IN UINT32 AndData,
+ IN UINT32 OrData
+ );
+
+/**
+ Reads a bit field of an I/O register, and saves the value in the S3 script to
+ be replayed on S3 resume.
+
+ Reads the bit field in a 32-bit I/O register. The bit field is specified by
+ the StartBit and the EndBit. The value of the bit field is returned.
+
+ If 32-bit I/O port operations are not supported, then ASSERT().
+ If StartBit is greater than 31, then ASSERT().
+ If EndBit is greater than 31, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+
+ @param[in] Port The I/O port to read.
+ @param[in] StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..31.
+ @param[in] EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..31.
+
+ @return The value read.
+
+**/
+UINT32
+EFIAPI
+S3IoBitFieldRead32 (
+ IN UINTN Port,
+ IN UINTN StartBit,
+ IN UINTN EndBit
+ );
+
+/**
+ Writes a bit field to an I/O register, and saves the value in the S3 script to
+ be replayed on S3 resume.
+
+ Writes Value to the bit field of the I/O register. The bit field is specified
+ by the StartBit and the EndBit. All other bits in the destination I/O
+ register are preserved. The value written to the I/O port is returned. Extra
+ left bits in Value are stripped.
+
+ If 32-bit I/O port operations are not supported, then ASSERT().
+ If StartBit is greater than 31, then ASSERT().
+ If EndBit is greater than 31, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param[in] Port The I/O port to write.
+ @param[in] StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..31.
+ @param[in] EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..31.
+ @param[in] Value New value of the bit field.
+
+ @return The value written back to the I/O port.
+
+**/
+UINT32
+EFIAPI
+S3IoBitFieldWrite32 (
+ IN UINTN Port,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 Value
+ );
+
+/**
+ Reads a bit field in a 32-bit port, performs a bitwise OR, writes the
+ result back to the bit field in the 32-bit port, and saves the value in the
+ S3 script to be replayed on S3 resume.
+
+ Reads the 32-bit I/O port specified by Port, performs a bitwise OR
+ between the read result and the value specified by OrData, and writes the
+ result to the 32-bit I/O port specified by Port. The value written to the I/O
+ port is returned. This function must guarantee that all I/O read and write
+ operations are serialized. Extra left bits in OrData are stripped.
+
+ If 32-bit I/O port operations are not supported, then ASSERT().
+ If StartBit is greater than 31, then ASSERT().
+ If EndBit is greater than 31, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param[in] Port The I/O port to write.
+ @param[in] StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..31.
+ @param[in] EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..31.
+ @param[in] OrData The value to OR with the read value from the I/O port.
+
+ @return The value written back to the I/O port.
+
+**/
+UINT32
+EFIAPI
+S3IoBitFieldOr32 (
+ IN UINTN Port,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 OrData
+ );
+
+/**
+ Reads a bit field in a 32-bit port, performs a bitwise AND, writes the
+ result back to the bit field in the 32-bit port, and saves the value in the
+ S3 script to be replayed on S3 resume.
+
+ Reads the 32-bit I/O port specified by Port, performs a bitwise AND between
+ the read result and the value specified by AndData, and writes the result to
+ the 32-bit I/O port specified by Port. The value written to the I/O port is
+ returned. This function must guarantee that all I/O read and write operations
+ are serialized. Extra left bits in AndData are stripped.
+
+ If 32-bit I/O port operations are not supported, then ASSERT().
+ If StartBit is greater than 31, then ASSERT().
+ If EndBit is greater than 31, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param[in] Port The I/O port to write.
+ @param[in] StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..31.
+ @param[in] EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..31.
+ @param[in] AndData The value to AND with the read value from the I/O port.
+
+ @return The value written back to the I/O port.
+
+**/
+UINT32
+EFIAPI
+S3IoBitFieldAnd32 (
+ IN UINTN Port,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 AndData
+ );
+
+/**
+ Reads a bit field in a 32-bit port, performs a bitwise AND followed by a
+ bitwise OR, writes the result back to the bit field in the
+ 32-bit port, and saves the value in the S3 script to be replayed on S3
+ resume.
+
+ Reads the 32-bit I/O port specified by Port, performs a bitwise AND followed
+ by a bitwise OR between the read result and the value specified by
+ AndData, and writes the result to the 32-bit I/O port specified by Port. The
+ value written to the I/O port is returned. This function must guarantee that
+ all I/O read and write operations are serialized. Extra left bits in both
+ AndData and OrData are stripped.
+
+ If 32-bit I/O port operations are not supported, then ASSERT().
+ If StartBit is greater than 31, then ASSERT().
+ If EndBit is greater than 31, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param[in] Port The I/O port to write.
+ @param[in] StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..31.
+ @param[in] EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..31.
+ @param[in] AndData The value to AND with the read value from the I/O port.
+ @param[in] OrData The value to OR with the result of the AND operation.
+
+ @return The value written back to the I/O port.
+
+**/
+UINT32
+EFIAPI
+S3IoBitFieldAndThenOr32 (
+ IN UINTN Port,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 AndData,
+ IN UINT32 OrData
+ );
+
+/**
+ Reads a 64-bit I/O port, and saves the value in the S3 script to be replayed
+ on S3 resume.
+
+ Reads the 64-bit I/O port specified by Port. The 64-bit read value is returned.
+ This function must guarantee that all I/O read and write operations are
+ serialized.
+
+ If 64-bit I/O port operations are not supported, then ASSERT().
+
+ @param[in] Port The I/O port to read.
+
+ @return The value read.
+
+**/
+UINT64
+EFIAPI
+S3IoRead64 (
+ IN UINTN Port
+ );
+
+/**
+ Writes a 64-bit I/O port, and saves the value in the S3 script to be replayed
+ on S3 resume.
+
+ Writes the 64-bit I/O port specified by Port with the value specified by Value
+ and returns Value. This function must guarantee that all I/O read and write
+ operations are serialized.
+
+ If 64-bit I/O port operations are not supported, then ASSERT().
+
+ @param[in] Port The I/O port to write.
+ @param[in] Value The value to write to the I/O port.
+
+ @return The value written to the I/O port.
+
+**/
+UINT64
+EFIAPI
+S3IoWrite64 (
+ IN UINTN Port,
+ IN UINT64 Value
+ );
+
+/**
+ Reads a 64-bit I/O port, performs a bitwise OR, writes the
+ result back to the 64-bit I/O port, and saves the value in the S3 script to
+ be replayed on S3 resume.
+
+ Reads the 64-bit I/O port specified by Port, performs a bitwise OR
+ between the read result and the value specified by OrData, and writes the
+ result to the 64-bit I/O port specified by Port. The value written to the I/O
+ port is returned. This function must guarantee that all I/O read and write
+ operations are serialized.
+
+ If 64-bit I/O port operations are not supported, then ASSERT().
+
+ @param[in] Port The I/O port to write.
+ @param[in] OrData The value to OR with the read value from the I/O port.
+
+ @return The value written back to the I/O port.
+
+**/
+UINT64
+EFIAPI
+S3IoOr64 (
+ IN UINTN Port,
+ IN UINT64 OrData
+ );
+
+/**
+ Reads a 64-bit I/O port, performs a bitwise AND, writes the result back
+ to the 64-bit I/O port, and saves the value in the S3 script to be replayed
+ on S3 resume.
+
+ Reads the 64-bit I/O port specified by Port, performs a bitwise AND between
+ the read result and the value specified by AndData, and writes the result to
+ the 64-bit I/O port specified by Port. The value written to the I/O port is
+ returned. This function must guarantee that all I/O read and write operations
+ are serialized.
+
+ If 64-bit I/O port operations are not supported, then ASSERT().
+
+ @param[in] Port The I/O port to write.
+ @param[in] AndData The value to AND with the read value from the I/O port.
+
+ @return The value written back to the I/O port.
+
+**/
+UINT64
+EFIAPI
+S3IoAnd64 (
+ IN UINTN Port,
+ IN UINT64 AndData
+ );
+
+/**
+ Reads a 64-bit I/O port, performs a bitwise AND followed by a bitwise
+ inclusive OR, writes the result back to the 64-bit I/O port, and saves
+ the value in the S3 script to be replayed on S3 resume.
+
+ Reads the 64-bit I/O port specified by Port, performs a bitwise AND between
+ the read result and the value specified by AndData, performs a bitwise OR
+ between the result of the AND operation and the value specified by OrData,
+ and writes the result to the 64-bit I/O port specified by Port. The value
+ written to the I/O port is returned. This function must guarantee that all
+ I/O read and write operations are serialized.
+
+ If 64-bit I/O port operations are not supported, then ASSERT().
+
+ @param[in] Port The I/O port to write.
+ @param[in] AndData The value to AND with the read value from the I/O port.
+ @param[in] OrData The value to OR with the result of the AND operation.
+
+ @return The value written back to the I/O port.
+
+**/
+UINT64
+EFIAPI
+S3IoAndThenOr64 (
+ IN UINTN Port,
+ IN UINT64 AndData,
+ IN UINT64 OrData
+ );
+
+/**
+ Reads a bit field of an I/O register, and saves the value in the S3 script to
+ be replayed on S3 resume.
+
+ Reads the bit field in a 64-bit I/O register. The bit field is specified by
+ the StartBit and the EndBit. The value of the bit field is returned.
+
+ If 64-bit I/O port operations are not supported, then ASSERT().
+ If StartBit is greater than 63, then ASSERT().
+ If EndBit is greater than 63, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+
+ @param[in] Port The I/O port to read.
+ @param[in] StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..63.
+ @param[in] EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..63.
+
+ @return The value read.
+
+**/
+UINT64
+EFIAPI
+S3IoBitFieldRead64 (
+ IN UINTN Port,
+ IN UINTN StartBit,
+ IN UINTN EndBit
+ );
+
+/**
+ Writes a bit field to an I/O register, and saves the value in the S3 script to
+ be replayed on S3 resume.
+
+ Writes Value to the bit field of the I/O register. The bit field is specified
+ by the StartBit and the EndBit. All other bits in the destination I/O
+ register are preserved. The value written to the I/O port is returned. Extra
+ left bits in Value are stripped.
+
+ If 64-bit I/O port operations are not supported, then ASSERT().
+ If StartBit is greater than 63, then ASSERT().
+ If EndBit is greater than 63, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param[in] Port The I/O port to write.
+ @param[in] StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..63.
+ @param[in] EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..63.
+ @param[in] Value New value of the bit field.
+
+ @return The value written back to the I/O port.
+
+**/
+UINT64
+EFIAPI
+S3IoBitFieldWrite64 (
+ IN UINTN Port,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT64 Value
+ );
+
+/**
+ Reads a bit field in a 64-bit port, performs a bitwise OR, writes the
+ result back to the bit field in the 64-bit port, and saves the value in the
+ S3 script to be replayed on S3 resume.
+
+ Reads the 64-bit I/O port specified by Port, performs a bitwise OR
+ between the read result and the value specified by OrData, and writes the
+ result to the 64-bit I/O port specified by Port. The value written to the I/O
+ port is returned. This function must guarantee that all I/O read and write
+ operations are serialized. Extra left bits in OrData are stripped.
+
+ If 64-bit I/O port operations are not supported, then ASSERT().
+ If StartBit is greater than 63, then ASSERT().
+ If EndBit is greater than 63, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param[in] Port The I/O port to write.
+ @param[in] StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..63.
+ @param[in] EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..63.
+ @param[in] OrData The value to OR with the read value from the I/O port.
+
+ @return The value written back to the I/O port.
+
+**/
+UINT64
+EFIAPI
+S3IoBitFieldOr64 (
+ IN UINTN Port,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT64 OrData
+ );
+
+/**
+ Reads a bit field in a 64-bit port, performs a bitwise AND, writes the
+ result back to the bit field in the 64-bit port, and saves the value in the
+ S3 script to be replayed on S3 resume.
+
+ Reads the 64-bit I/O port specified by Port, performs a bitwise AND between
+ the read result and the value specified by AndData, and writes the result to
+ the 64-bit I/O port specified by Port. The value written to the I/O port is
+ returned. This function must guarantee that all I/O read and write operations
+ are serialized. Extra left bits in AndData are stripped.
+
+ If 64-bit I/O port operations are not supported, then ASSERT().
+ If StartBit is greater than 63, then ASSERT().
+ If EndBit is greater than 63, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param[in] Port The I/O port to write.
+ @param[in] StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..63.
+ @param[in] EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..63.
+ @param[in] AndData The value to AND with the read value from the I/O port.
+
+ @return The value written back to the I/O port.
+
+**/
+UINT64
+EFIAPI
+S3IoBitFieldAnd64 (
+ IN UINTN Port,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT64 AndData
+ );
+
+/**
+ Reads a bit field in a 64-bit port, performs a bitwise AND followed by a
+ bitwise OR, writes the result back to the bit field in the
+ 64-bit port, and saves the value in the S3 script to be replayed on S3
+ resume.
+
+ Reads the 64-bit I/O port specified by Port, performs a bitwise AND followed
+ by a bitwise OR between the read result and the value specified by
+ AndData, and writes the result to the 64-bit I/O port specified by Port. The
+ value written to the I/O port is returned. This function must guarantee that
+ all I/O read and write operations are serialized. Extra left bits in both
+ AndData and OrData are stripped.
+
+ If 64-bit I/O port operations are not supported, then ASSERT().
+ If StartBit is greater than 63, then ASSERT().
+ If EndBit is greater than 63, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param[in] Port The I/O port to write.
+ @param[in] StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..63.
+ @param[in] EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..63.
+ @param[in] AndData The value to AND with the read value from the I/O port.
+ @param[in] OrData The value to OR with the result of the AND operation.
+
+ @return The value written back to the I/O port.
+
+**/
+UINT64
+EFIAPI
+S3IoBitFieldAndThenOr64 (
+ IN UINTN Port,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT64 AndData,
+ IN UINT64 OrData
+ );
+
+/**
+ Reads an 8-bit MMIO register, and saves the value in the S3 script to be
+ replayed on S3 resume.
+
+ Reads the 8-bit MMIO register specified by Address. The 8-bit read value is
+ returned. This function must guarantee that all MMIO read and write
+ operations are serialized.
+
+ If 8-bit MMIO register operations are not supported, then ASSERT().
+
+ @param[in] Address The MMIO register to read.
+
+ @return The value read.
+
+**/
+UINT8
+EFIAPI
+S3MmioRead8 (
+ IN UINTN Address
+ );
+
+/**
+ Writes an 8-bit MMIO register, and saves the value in the S3 script to be
+ replayed on S3 resume.
+
+ Writes the 8-bit MMIO register specified by Address with the value specified
+ by Value and returns Value. This function must guarantee that all MMIO read
+ and write operations are serialized.
+
+ If 8-bit MMIO register operations are not supported, then ASSERT().
+
+ @param[in] Address The MMIO register to write.
+ @param[in] Value The value to write to the MMIO register.
+
+ @return The value written the MMIO register.
+
+**/
+UINT8
+EFIAPI
+S3MmioWrite8 (
+ IN UINTN Address,
+ IN UINT8 Value
+ );
+
+/**
+ Reads an 8-bit MMIO register, performs a bitwise OR, writes the
+ result back to the 8-bit MMIO register, and saves the value in the S3 script
+ to be replayed on S3 resume.
+
+ Reads the 8-bit MMIO register specified by Address, performs a bitwise
+ inclusive OR between the read result and the value specified by OrData, and
+ writes the result to the 8-bit MMIO register specified by Address. The value
+ written to the MMIO register is returned. This function must guarantee that
+ all MMIO read and write operations are serialized.
+
+ If 8-bit MMIO register operations are not supported, then ASSERT().
+
+ @param[in] Address The MMIO register to write.
+ @param[in] OrData The value to OR with the read value from the MMIO register.
+
+ @return The value written back to the MMIO register.
+
+**/
+UINT8
+EFIAPI
+S3MmioOr8 (
+ IN UINTN Address,
+ IN UINT8 OrData
+ );
+
+/**
+ Reads an 8-bit MMIO register, performs a bitwise AND, writes the result
+ back to the 8-bit MMIO register, and saves the value in the S3 script to be
+ replayed on S3 resume.
+
+ Reads the 8-bit MMIO register specified by Address, performs a bitwise AND
+ between the read result and the value specified by AndData, and writes the
+ result to the 8-bit MMIO register specified by Address. The value written to
+ the MMIO register is returned. This function must guarantee that all MMIO
+ read and write operations are serialized.
+
+ If 8-bit MMIO register operations are not supported, then ASSERT().
+
+ @param[in] Address The MMIO register to write.
+ @param[in] AndData The value to AND with the read value from the MMIO register.
+
+ @return The value written back to the MMIO register.
+
+**/
+UINT8
+EFIAPI
+S3MmioAnd8 (
+ IN UINTN Address,
+ IN UINT8 AndData
+ );
+
+/**
+ Reads an 8-bit MMIO register, performs a bitwise AND followed by a bitwise
+ inclusive OR, writes the result back to the 8-bit MMIO register, and saves
+ the value in the S3 script to be replayed on S3 resume.
+
+ Reads the 8-bit MMIO register specified by Address, performs a bitwise AND
+ between the read result and the value specified by AndData, performs a
+ bitwise OR between the result of the AND operation and the value specified by
+ OrData, and writes the result to the 8-bit MMIO register specified by
+ Address. The value written to the MMIO register is returned. This function
+ must guarantee that all MMIO read and write operations are serialized.
+
+ If 8-bit MMIO register operations are not supported, then ASSERT().
+
+ @param[in] Address The MMIO register to write.
+ @param[in] AndData The value to AND with the read value from the MMIO register.
+ @param[in] OrData The value to OR with the result of the AND operation.
+
+ @return The value written back to the MMIO register.
+
+**/
+UINT8
+EFIAPI
+S3MmioAndThenOr8 (
+ IN UINTN Address,
+ IN UINT8 AndData,
+ IN UINT8 OrData
+ );
+
+/**
+ Reads a bit field of a MMIO register, and saves the value in the S3 script to
+ be replayed on S3 resume.
+
+ Reads the bit field in an 8-bit MMIO register. The bit field is specified by
+ the StartBit and the EndBit. The value of the bit field is returned.
+
+ If 8-bit MMIO register operations are not supported, then ASSERT().
+ If StartBit is greater than 7, then ASSERT().
+ If EndBit is greater than 7, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+
+ @param[in] Address MMIO register to read.
+ @param[in] StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..7.
+ @param[in] EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..7.
+
+ @return The value read.
+
+**/
+UINT8
+EFIAPI
+S3MmioBitFieldRead8 (
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit
+ );
+
+/**
+ Writes a bit field to an MMIO register, and saves the value in the S3 script to
+ be replayed on S3 resume.
+
+ Writes Value to the bit field of the MMIO register. The bit field is
+ specified by the StartBit and the EndBit. All other bits in the destination
+ MMIO register are preserved. The new value of the 8-bit register is returned.
+
+ If 8-bit MMIO register operations are not supported, then ASSERT().
+ If StartBit is greater than 7, then ASSERT().
+ If EndBit is greater than 7, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param[in] Address The MMIO register to write.
+ @param[in] StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..7.
+ @param[in] EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..7.
+ @param[in] Value New value of the bit field.
+
+ @return The value written back to the MMIO register.
+
+**/
+UINT8
+EFIAPI
+S3MmioBitFieldWrite8 (
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT8 Value
+ );
+
+/**
+ Reads a bit field in an 8-bit MMIO register, performs a bitwise OR,
+ writes the result back to the bit field in the 8-bit MMIO register, and saves
+ the value in the S3 script to be replayed on S3 resume.
+
+ Reads the 8-bit MMIO register specified by Address, performs a bitwise
+ inclusive OR between the read result and the value specified by OrData, and
+ writes the result to the 8-bit MMIO register specified by Address. The value
+ written to the MMIO register is returned. This function must guarantee that
+ all MMIO read and write operations are serialized. Extra left bits in OrData
+ are stripped.
+
+ If 8-bit MMIO register operations are not supported, then ASSERT().
+ If StartBit is greater than 7, then ASSERT().
+ If EndBit is greater than 7, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param[in] Address The MMIO register to write.
+ @param[in] StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..7.
+ @param[in] EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..7.
+ @param[in] OrData The value to OR with the read value from the MMIO register.
+
+ @return The value written back to the MMIO register.
+
+**/
+UINT8
+EFIAPI
+S3MmioBitFieldOr8 (
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT8 OrData
+ );
+
+/**
+ Reads a bit field in an 8-bit MMIO register, performs a bitwise AND, and
+ writes the result back to the bit field in the 8-bit MMIO register, and saves
+ the value in the S3 script to be replayed on S3 resume.
+
+ Reads the 8-bit MMIO register specified by Address, performs a bitwise AND
+ between the read result and the value specified by AndData, and writes the
+ result to the 8-bit MMIO register specified by Address. The value written to
+ the MMIO register is returned. This function must guarantee that all MMIO
+ read and write operations are serialized. Extra left bits in AndData are
+ stripped.
+
+ If 8-bit MMIO register operations are not supported, then ASSERT().
+ If StartBit is greater than 7, then ASSERT().
+ If EndBit is greater than 7, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param[in] Address The MMIO register to write.
+ @param[in] StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..7.
+ @param[in] EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..7.
+ @param[in] AndData The value to AND with the read value from the MMIO register.
+
+ @return The value written back to the MMIO register.
+
+**/
+UINT8
+EFIAPI
+S3MmioBitFieldAnd8 (
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT8 AndData
+ );
+
+/**
+ Reads a bit field in an 8-bit MMIO register, performs a bitwise AND followed
+ by a bitwise OR, writes the result back to the bit field in the
+ 8-bit MMIO register, and saves the value in the S3 script to be replayed
+ on S3 resume.
+
+ Reads the 8-bit MMIO register specified by Address, performs a bitwise AND
+ followed by a bitwise OR between the read result and the value
+ specified by AndData, and writes the result to the 8-bit MMIO register
+ specified by Address. The value written to the MMIO register is returned.
+ This function must guarantee that all MMIO read and write operations are
+ serialized. Extra left bits in both AndData and OrData are stripped.
+
+ If 8-bit MMIO register operations are not supported, then ASSERT().
+ If StartBit is greater than 7, then ASSERT().
+ If EndBit is greater than 7, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param[in] Address The MMIO register to write.
+ @param[in] StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..7.
+ @param[in] EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..7.
+ @param[in] AndData The value to AND with the read value from the MMIO register.
+ @param[in] OrData The value to OR with the result of the AND operation.
+
+ @return The value written back to the MMIO register.
+
+**/
+UINT8
+EFIAPI
+S3MmioBitFieldAndThenOr8 (
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT8 AndData,
+ IN UINT8 OrData
+ );
+
+/**
+ Reads a 16-bit MMIO register, and saves the value in the S3 script to be replayed
+ on S3 resume.
+
+ Reads the 16-bit MMIO register specified by Address. The 16-bit read value is
+ returned. This function must guarantee that all MMIO read and write
+ operations are serialized.
+
+ If 16-bit MMIO register operations are not supported, then ASSERT().
+
+ @param[in] Address The MMIO register to read.
+
+ @return The value read.
+
+**/
+UINT16
+EFIAPI
+S3MmioRead16 (
+ IN UINTN Address
+ );
+
+/**
+ Writes a 16-bit MMIO register, and saves the value in the S3 script to be replayed
+ on S3 resume.
+
+ Writes the 16-bit MMIO register specified by Address with the value specified
+ by Value and returns Value. This function must guarantee that all MMIO read
+ and write operations are serialized, and saves the value in the S3 script to be
+ replayed on S3 resume.
+
+ If 16-bit MMIO register operations are not supported, then ASSERT().
+
+ @param[in] Address The MMIO register to write.
+ @param[in] Value The value to write to the MMIO register.
+
+ @return The value written the MMIO register.
+
+**/
+UINT16
+EFIAPI
+S3MmioWrite16 (
+ IN UINTN Address,
+ IN UINT16 Value
+ );
+
+/**
+ Reads a 16-bit MMIO register, performs a bitwise OR, writes the
+ result back to the 16-bit MMIO register, and saves the value in the S3 script
+ to be replayed on S3 resume.
+
+ Reads the 16-bit MMIO register specified by Address, performs a bitwise
+ inclusive OR between the read result and the value specified by OrData, and
+ writes the result to the 16-bit MMIO register specified by Address. The value
+ written to the MMIO register is returned. This function must guarantee that
+ all MMIO read and write operations are serialized.
+
+ If 16-bit MMIO register operations are not supported, then ASSERT().
+
+ @param[in] Address The MMIO register to write.
+ @param[in] OrData The value to OR with the read value from the MMIO register.
+
+ @return The value written back to the MMIO register.
+
+**/
+UINT16
+EFIAPI
+S3MmioOr16 (
+ IN UINTN Address,
+ IN UINT16 OrData
+ );
+
+/**
+ Reads a 16-bit MMIO register, performs a bitwise AND, writes the result
+ back to the 16-bit MMIO register, and saves the value in the S3 script to be
+ replayed on S3 resume.
+
+ Reads the 16-bit MMIO register specified by Address, performs a bitwise AND
+ between the read result and the value specified by AndData, and writes the
+ result to the 16-bit MMIO register specified by Address. The value written to
+ the MMIO register is returned. This function must guarantee that all MMIO
+ read and write operations are serialized.
+
+ If 16-bit MMIO register operations are not supported, then ASSERT().
+
+ @param[in] Address The MMIO register to write.
+ @param[in] AndData The value to AND with the read value from the MMIO register.
+
+ @return The value written back to the MMIO register.
+
+**/
+UINT16
+EFIAPI
+S3MmioAnd16 (
+ IN UINTN Address,
+ IN UINT16 AndData
+ );
+
+/**
+ Reads a 16-bit MMIO register, performs a bitwise AND followed by a bitwise
+ inclusive OR, writes the result back to the 16-bit MMIO register, and
+ saves the value in the S3 script to be replayed on S3 resume.
+
+ Reads the 16-bit MMIO register specified by Address, performs a bitwise AND
+ between the read result and the value specified by AndData, performs a
+ bitwise OR between the result of the AND operation and the value specified by
+ OrData, and writes the result to the 16-bit MMIO register specified by
+ Address. The value written to the MMIO register is returned. This function
+ must guarantee that all MMIO read and write operations are serialized.
+
+ If 16-bit MMIO register operations are not supported, then ASSERT().
+
+ @param[in] Address The MMIO register to write.
+ @param[in] AndData The value to AND with the read value from the MMIO register.
+ @param[in] OrData The value to OR with the result of the AND operation.
+
+ @return The value written back to the MMIO register.
+
+**/
+UINT16
+EFIAPI
+S3MmioAndThenOr16 (
+ IN UINTN Address,
+ IN UINT16 AndData,
+ IN UINT16 OrData
+ );
+
+/**
+ Reads a bit field of a MMIO register, and saves the value in the S3 script to
+ be replayed on S3 resume.
+
+ Reads the bit field in a 16-bit MMIO register. The bit field is specified by
+ the StartBit and the EndBit. The value of the bit field is returned.
+
+ If 16-bit MMIO register operations are not supported, then ASSERT().
+ If StartBit is greater than 15, then ASSERT().
+ If EndBit is greater than 15, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+
+ @param[in] Address MMIO register to read.
+ @param[in] StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..15.
+ @param[in] EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..15.
+
+ @return The value read.
+
+**/
+UINT16
+EFIAPI
+S3MmioBitFieldRead16 (
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit
+ );
+
+/**
+ Writes a bit field to a MMIO register, and saves the value in the S3 script to
+ be replayed on S3 resume.
+
+ Writes Value to the bit field of the MMIO register. The bit field is
+ specified by the StartBit and the EndBit. All other bits in the destination
+ MMIO register are preserved. The new value of the 16-bit register is returned.
+
+ If 16-bit MMIO register operations are not supported, then ASSERT().
+ If StartBit is greater than 15, then ASSERT().
+ If EndBit is greater than 15, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param[in] Address The MMIO register to write.
+ @param[in] StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..15.
+ @param[in] EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..15.
+ @param[in] Value New value of the bit field.
+
+ @return The value written back to the MMIO register.
+
+**/
+UINT16
+EFIAPI
+S3MmioBitFieldWrite16 (
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT16 Value
+ );
+
+/**
+ Reads a bit field in a 16-bit MMIO register, performs a bitwise OR,
+ writes the result back to the bit field in the 16-bit MMIO register, and
+ saves the value in the S3 script to be replayed on S3 resume.
+
+ Reads the 16-bit MMIO register specified by Address, performs a bitwise
+ inclusive OR between the read result and the value specified by OrData, and
+ writes the result to the 16-bit MMIO register specified by Address. The value
+ written to the MMIO register is returned. This function must guarantee that
+ all MMIO read and write operations are serialized. Extra left bits in OrData
+ are stripped.
+
+ If 16-bit MMIO register operations are not supported, then ASSERT().
+ If StartBit is greater than 15, then ASSERT().
+ If EndBit is greater than 15, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param[in] Address The MMIO register to write.
+ @param[in] StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..15.
+ @param[in] EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..15.
+ @param[in] OrData The value to OR with the read value from the MMIO register.
+
+ @return The value written back to the MMIO register.
+
+**/
+UINT16
+EFIAPI
+S3MmioBitFieldOr16 (
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT16 OrData
+ );
+
+/**
+ Reads a bit field in a 16-bit MMIO register, performs a bitwise AND, and
+ writes the result back to the bit field in the 16-bit MMIO register and
+ saves the value in the S3 script to be replayed on S3 resume.
+
+ Reads the 16-bit MMIO register specified by Address, performs a bitwise AND
+ between the read result and the value specified by AndData, and writes the
+ result to the 16-bit MMIO register specified by Address. The value written to
+ the MMIO register is returned. This function must guarantee that all MMIO
+ read and write operations are serialized. Extra left bits in AndData are
+ stripped.
+
+ If 16-bit MMIO register operations are not supported, then ASSERT().
+ If StartBit is greater than 15, then ASSERT().
+ If EndBit is greater than 15, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param[in] Address The MMIO register to write.
+ @param[in] StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..15.
+ @param[in] EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..15.
+ @param[in] AndData The value to AND with the read value from the MMIO register.
+
+ @return The value written back to the MMIO register.
+
+**/
+UINT16
+EFIAPI
+S3MmioBitFieldAnd16 (
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT16 AndData
+ );
+
+/**
+ Reads a bit field in a 16-bit MMIO register, performs a bitwise AND followed
+ by a bitwise OR, writes the result back to the bit field in the
+ 16-bit MMIO register, and saves the value in the S3 script to be replayed
+ on S3 resume.
+
+ Reads the 16-bit MMIO register specified by Address, performs a bitwise AND
+ followed by a bitwise OR between the read result and the value
+ specified by AndData, and writes the result to the 16-bit MMIO register
+ specified by Address. The value written to the MMIO register is returned.
+ This function must guarantee that all MMIO read and write operations are
+ serialized. Extra left bits in both AndData and OrData are stripped.
+
+ If 16-bit MMIO register operations are not supported, then ASSERT().
+ If StartBit is greater than 15, then ASSERT().
+ If EndBit is greater than 15, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param[in] Address The MMIO register to write.
+ @param[in] StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..15.
+ @param[in] EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..15.
+ @param[in] AndData The value to AND with the read value from the MMIO register.
+ @param[in] OrData The value to OR with the result of the AND operation.
+
+ @return The value written back to the MMIO register.
+
+**/
+UINT16
+EFIAPI
+S3MmioBitFieldAndThenOr16 (
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT16 AndData,
+ IN UINT16 OrData
+ );
+
+/**
+ Reads a 32-bit MMIO register saves the value in the S3 script to be
+ replayed on S3 resume.
+
+ Reads the 32-bit MMIO register specified by Address. The 32-bit read value is
+ returned. This function must guarantee that all MMIO read and write
+ operations are serialized.
+
+ If 32-bit MMIO register operations are not supported, then ASSERT().
+
+ @param[in] Address The MMIO register to read.
+
+ @return The value read.
+
+**/
+UINT32
+EFIAPI
+S3MmioRead32 (
+ IN UINTN Address
+ );
+
+/**
+ Writes a 32-bit MMIO register, and saves the value in the S3 script to be
+ replayed on S3 resume.
+
+ Writes the 32-bit MMIO register specified by Address with the value specified
+ by Value and returns Value. This function must guarantee that all MMIO read
+ and write operations are serialized.
+
+ If 32-bit MMIO register operations are not supported, then ASSERT().
+
+ @param[in] Address The MMIO register to write.
+ @param[in] Value The value to write to the MMIO register.
+
+ @return The value written the MMIO register.
+
+**/
+UINT32
+EFIAPI
+S3MmioWrite32 (
+ IN UINTN Address,
+ IN UINT32 Value
+ );
+
+/**
+ Reads a 32-bit MMIO register, performs a bitwise OR, writes the
+ result back to the 32-bit MMIO register, and saves the value in the S3 script
+ to be replayed on S3 resume.
+
+ Reads the 32-bit MMIO register specified by Address, performs a bitwise
+ inclusive OR between the read result and the value specified by OrData, and
+ writes the result to the 32-bit MMIO register specified by Address. The value
+ written to the MMIO register is returned. This function must guarantee that
+ all MMIO read and write operations are serialized.
+
+ If 32-bit MMIO register operations are not supported, then ASSERT().
+
+ @param[in] Address The MMIO register to write.
+ @param[in] OrData The value to OR with the read value from the MMIO register.
+
+ @return The value written back to the MMIO register.
+
+**/
+UINT32
+EFIAPI
+S3MmioOr32 (
+ IN UINTN Address,
+ IN UINT32 OrData
+ );
+
+/**
+ Reads a 32-bit MMIO register, performs a bitwise AND, writes the result
+ back to the 32-bit MMIO register, and saves the value in the S3 script to be
+ replayed on S3 resume.
+
+ Reads the 32-bit MMIO register specified by Address, performs a bitwise AND
+ between the read result and the value specified by AndData, and writes the
+ result to the 32-bit MMIO register specified by Address. The value written to
+ the MMIO register is returned. This function must guarantee that all MMIO
+ read and write operations are serialized.
+
+ If 32-bit MMIO register operations are not supported, then ASSERT().
+
+ @param[in] Address The MMIO register to write.
+ @param[in] AndData The value to AND with the read value from the MMIO register.
+
+ @return The value written back to the MMIO register.
+
+**/
+UINT32
+EFIAPI
+S3MmioAnd32 (
+ IN UINTN Address,
+ IN UINT32 AndData
+ );
+
+/**
+ Reads a 32-bit MMIO register, performs a bitwise AND followed by a bitwise
+ inclusive OR, writes the result back to the 32-bit MMIO register, and
+ saves the value in the S3 script to be replayed on S3 resume.
+
+ Reads the 32-bit MMIO register specified by Address, performs a bitwise AND
+ between the read result and the value specified by AndData, performs a
+ bitwise OR between the result of the AND operation and the value specified by
+ OrData, and writes the result to the 32-bit MMIO register specified by
+ Address. The value written to the MMIO register is returned. This function
+ must guarantee that all MMIO read and write operations are serialized.
+
+ If 32-bit MMIO register operations are not supported, then ASSERT().
+
+ @param[in] Address The MMIO register to write.
+ @param[in] AndData The value to AND with the read value from the MMIO register.
+ @param[in] OrData The value to OR with the result of the AND operation.
+
+ @return The value written back to the MMIO register.
+
+**/
+UINT32
+EFIAPI
+S3MmioAndThenOr32 (
+ IN UINTN Address,
+ IN UINT32 AndData,
+ IN UINT32 OrData
+ );
+
+/**
+ Reads a bit field of a MMIO register, and saves the value in the S3 script
+ to be replayed on S3 resume.
+
+ Reads the bit field in a 32-bit MMIO register. The bit field is specified by
+ the StartBit and the EndBit. The value of the bit field is returned.
+
+ If 32-bit MMIO register operations are not supported, then ASSERT().
+ If StartBit is greater than 31, then ASSERT().
+ If EndBit is greater than 31, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+
+ @param[in] Address MMIO register to read.
+ @param[in] StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..31.
+ @param[in] EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..31.
+
+ @return The value read.
+
+**/
+UINT32
+EFIAPI
+S3MmioBitFieldRead32 (
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit
+ );
+
+/**
+ Writes a bit field to a MMIO register, and saves the value in the S3 script
+ to be replayed on S3 resume.
+
+ Writes Value to the bit field of the MMIO register. The bit field is
+ specified by the StartBit and the EndBit. All other bits in the destination
+ MMIO register are preserved. The new value of the 32-bit register is returned.
+
+ If 32-bit MMIO register operations are not supported, then ASSERT().
+ If StartBit is greater than 31, then ASSERT().
+ If EndBit is greater than 31, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param[in] Address The MMIO register to write.
+ @param[in] StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..31.
+ @param[in] EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..31.
+ @param[in] Value New value of the bit field.
+
+ @return The value written back to the MMIO register.
+
+**/
+UINT32
+EFIAPI
+S3MmioBitFieldWrite32 (
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 Value
+ );
+
+/**
+ Reads a bit field in a 32-bit MMIO register, performs a bitwise OR,
+ writes the result back to the bit field in the 32-bit MMIO register, and
+ saves the value in the S3 script to be replayed on S3 resume.
+
+ Reads the 32-bit MMIO register specified by Address, performs a bitwise
+ inclusive OR between the read result and the value specified by OrData, and
+ writes the result to the 32-bit MMIO register specified by Address. The value
+ written to the MMIO register is returned. This function must guarantee that
+ all MMIO read and write operations are serialized. Extra left bits in OrData
+ are stripped.
+
+ If 32-bit MMIO register operations are not supported, then ASSERT().
+ If StartBit is greater than 31, then ASSERT().
+ If EndBit is greater than 31, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param[in] Address The MMIO register to write.
+ @param[in] StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..31.
+ @param[in] EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..31.
+ @param[in] OrData The value to OR with the read value from the MMIO register.
+
+ @return The value written back to the MMIO register.
+
+**/
+UINT32
+EFIAPI
+S3MmioBitFieldOr32 (
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 OrData
+ );
+
+/**
+ Reads a bit field in a 32-bit MMIO register, performs a bitwise AND, and
+ writes the result back to the bit field in the 32-bit MMIO register and
+ saves the value in the S3 script to be replayed on S3 resume.
+
+ Reads the 32-bit MMIO register specified by Address, performs a bitwise AND
+ between the read result and the value specified by AndData, and writes the
+ result to the 32-bit MMIO register specified by Address. The value written to
+ the MMIO register is returned. This function must guarantee that all MMIO
+ read and write operations are serialized. Extra left bits in AndData are
+ stripped.
+
+ If 32-bit MMIO register operations are not supported, then ASSERT().
+ If StartBit is greater than 31, then ASSERT().
+ If EndBit is greater than 31, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param[in] Address The MMIO register to write.
+ @param[in] StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..31.
+ @param[in] EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..31.
+ @param[in] AndData The value to AND with the read value from the MMIO register.
+
+ @return The value written back to the MMIO register.
+
+**/
+UINT32
+EFIAPI
+S3MmioBitFieldAnd32 (
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 AndData
+ );
+
+/**
+ Reads a bit field in a 32-bit MMIO register, performs a bitwise AND followed
+ by a bitwise OR, writes the result back to the bit field in the
+ 32-bit MMIO register, and saves the value in the S3 script to be replayed
+ on S3 resume.
+
+ Reads the 32-bit MMIO register specified by Address, performs a bitwise AND
+ followed by a bitwise OR between the read result and the value
+ specified by AndData, and writes the result to the 32-bit MMIO register
+ specified by Address. The value written to the MMIO register is returned.
+ This function must guarantee that all MMIO read and write operations are
+ serialized. Extra left bits in both AndData and OrData are stripped.
+
+ If 32-bit MMIO register operations are not supported, then ASSERT().
+ If StartBit is greater than 31, then ASSERT().
+ If EndBit is greater than 31, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param[in] Address The MMIO register to write.
+ @param[in] StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..31.
+ @param[in] EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..31.
+ @param[in] AndData The value to AND with the read value from the MMIO register.
+ @param[in] OrData The value to OR with the result of the AND operation.
+
+ @return The value written back to the MMIO register.
+
+**/
+UINT32
+EFIAPI
+S3MmioBitFieldAndThenOr32 (
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 AndData,
+ IN UINT32 OrData
+ );
+
+/**
+ Reads a 64-bit MMIO register, and saves the value in the S3 script to be
+ replayed on S3 resume.
+
+ Reads the 64-bit MMIO register specified by Address. The 64-bit read value is
+ returned. This function must guarantee that all MMIO read and write
+ operations are serialized.
+
+ If 64-bit MMIO register operations are not supported, then ASSERT().
+
+ @param[in] Address The MMIO register to read.
+
+ @return The value read.
+
+**/
+UINT64
+EFIAPI
+S3MmioRead64 (
+ IN UINTN Address
+ );
+
+/**
+ Writes a 64-bit MMIO register, and saves the value in the S3 script to be
+ replayed on S3 resume.
+
+ Writes the 64-bit MMIO register specified by Address with the value specified
+ by Value and returns Value. This function must guarantee that all MMIO read
+ and write operations are serialized.
+
+ If 64-bit MMIO register operations are not supported, then ASSERT().
+
+ @param[in] Address The MMIO register to write.
+ @param[in] Value The value to write to the MMIO register.
+
+ @return The value written the MMIO register.
+
+**/
+UINT64
+EFIAPI
+S3MmioWrite64 (
+ IN UINTN Address,
+ IN UINT64 Value
+ );
+
+/**
+ Reads a 64-bit MMIO register, performs a bitwise OR, writes the
+ result back to the 64-bit MMIO register, and saves the value in the S3 script
+ to be replayed on S3 resume.
+
+ Reads the 64-bit MMIO register specified by Address, performs a bitwise
+ inclusive OR between the read result and the value specified by OrData, and
+ writes the result to the 64-bit MMIO register specified by Address. The value
+ written to the MMIO register is returned. This function must guarantee that
+ all MMIO read and write operations are serialized.
+
+ If 64-bit MMIO register operations are not supported, then ASSERT().
+
+ @param[in] Address The MMIO register to write.
+ @param[in] OrData The value to OR with the read value from the MMIO register.
+
+ @return The value written back to the MMIO register.
+
+**/
+UINT64
+EFIAPI
+S3MmioOr64 (
+ IN UINTN Address,
+ IN UINT64 OrData
+ );
+
+/**
+ Reads a 64-bit MMIO register, performs a bitwise AND, writes the result
+ back to the 64-bit MMIO register, and saves the value in the S3 script to be
+ replayed on S3 resume.
+
+ Reads the 64-bit MMIO register specified by Address, performs a bitwise AND
+ between the read result and the value specified by AndData, and writes the
+ result to the 64-bit MMIO register specified by Address. The value written to
+ the MMIO register is returned. This function must guarantee that all MMIO
+ read and write operations are serialized.
+
+ If 64-bit MMIO register operations are not supported, then ASSERT().
+
+ @param[in] Address The MMIO register to write.
+ @param[in] AndData The value to AND with the read value from the MMIO register.
+
+ @return The value written back to the MMIO register.
+
+**/
+UINT64
+EFIAPI
+S3MmioAnd64 (
+ IN UINTN Address,
+ IN UINT64 AndData
+ );
+
+/**
+ Reads a 64-bit MMIO register, performs a bitwise AND followed by a bitwise
+ inclusive OR, writes the result back to the 64-bit MMIO register, and
+ saves the value in the S3 script to be replayed on S3 resume.
+
+ Reads the 64-bit MMIO register specified by Address, performs a bitwise AND
+ between the read result and the value specified by AndData, performs a
+ bitwise OR between the result of the AND operation and the value specified by
+ OrData, and writes the result to the 64-bit MMIO register specified by
+ Address. The value written to the MMIO register is returned. This function
+ must guarantee that all MMIO read and write operations are serialized.
+
+ If 64-bit MMIO register operations are not supported, then ASSERT().
+
+ @param[in] Address The MMIO register to write.
+ @param[in] AndData The value to AND with the read value from the MMIO register.
+ @param[in] OrData The value to OR with the result of the AND operation.
+
+ @return The value written back to the MMIO register.
+
+**/
+UINT64
+EFIAPI
+S3MmioAndThenOr64 (
+ IN UINTN Address,
+ IN UINT64 AndData,
+ IN UINT64 OrData
+ );
+
+/**
+ Reads a bit field of a MMIO register saves the value in the S3 script to
+ be replayed on S3 resume.
+
+ Reads the bit field in a 64-bit MMIO register. The bit field is specified by
+ the StartBit and the EndBit. The value of the bit field is returned.
+
+ If 64-bit MMIO register operations are not supported, then ASSERT().
+ If StartBit is greater than 63, then ASSERT().
+ If EndBit is greater than 63, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+
+ @param[in] Address MMIO register to read.
+ @param[in] StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..63.
+ @param[in] EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..63.
+
+ @return The value read.
+
+**/
+UINT64
+EFIAPI
+S3MmioBitFieldRead64 (
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit
+ );
+
+/**
+ Writes a bit field to a MMIO register, and saves the value in the S3 script to
+ be replayed on S3 resume.
+
+ Writes Value to the bit field of the MMIO register. The bit field is
+ specified by the StartBit and the EndBit. All other bits in the destination
+ MMIO register are preserved. The new value of the 64-bit register is returned.
+
+ If 64-bit MMIO register operations are not supported, then ASSERT().
+ If StartBit is greater than 63, then ASSERT().
+ If EndBit is greater than 63, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param[in] Address The MMIO register to write.
+ @param[in] StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..63.
+ @param[in] EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..63.
+ @param[in] Value New value of the bit field.
+
+ @return The value written back to the MMIO register.
+
+**/
+UINT64
+EFIAPI
+S3MmioBitFieldWrite64 (
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT64 Value
+ );
+
+/**
+ Reads a bit field in a 64-bit MMIO register, performs a bitwise OR,
+ writes the result back to the bit field in the 64-bit MMIO register, and
+ saves the value in the S3 script to be replayed on S3 resume.
+
+ Reads the 64-bit MMIO register specified by Address, performs a bitwise
+ inclusive OR between the read result and the value specified by OrData, and
+ writes the result to the 64-bit MMIO register specified by Address. The value
+ written to the MMIO register is returned. This function must guarantee that
+ all MMIO read and write operations are serialized. Extra left bits in OrData
+ are stripped.
+
+ If 64-bit MMIO register operations are not supported, then ASSERT().
+ If StartBit is greater than 63, then ASSERT().
+ If EndBit is greater than 63, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param[in] Address The MMIO register to write.
+ @param[in] StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..63.
+ @param[in] EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..63.
+ @param[in] OrData The value to OR with the read value from the MMIO register.
+
+ @return The value written back to the MMIO register.
+
+**/
+UINT64
+EFIAPI
+S3MmioBitFieldOr64 (
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT64 OrData
+ );
+
+/**
+ Reads a bit field in a 64-bit MMIO register, performs a bitwise AND, and
+ writes the result back to the bit field in the 64-bit MMIO register, and saves
+ the value in the S3 script to be replayed on S3 resume.
+
+ Reads the 64-bit MMIO register specified by Address, performs a bitwise AND
+ between the read result and the value specified by AndData, and writes the
+ result to the 64-bit MMIO register specified by Address. The value written to
+ the MMIO register is returned. This function must guarantee that all MMIO
+ read and write operations are serialized. Extra left bits in AndData are
+ stripped.
+
+ If 64-bit MMIO register operations are not supported, then ASSERT().
+ If StartBit is greater than 63, then ASSERT().
+ If EndBit is greater than 63, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param[in] Address The MMIO register to write.
+ @param[in] StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..63.
+ @param[in] EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..63.
+ @param[in] AndData The value to AND with the read value from the MMIO register.
+
+ @return The value written back to the MMIO register.
+
+**/
+UINT64
+EFIAPI
+S3MmioBitFieldAnd64 (
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT64 AndData
+ );
+
+/**
+ Reads a bit field in a 64-bit MMIO register, performs a bitwise AND followed
+ by a bitwise OR, writes the result back to the bit field in the
+ 64-bit MMIO register, and saves the value in the S3 script to be replayed
+ on S3 resume.
+
+ Reads the 64-bit MMIO register specified by Address, performs a bitwise AND
+ followed by a bitwise OR between the read result and the value
+ specified by AndData, and writes the result to the 64-bit MMIO register
+ specified by Address. The value written to the MMIO register is returned.
+ This function must guarantee that all MMIO read and write operations are
+ serialized. Extra left bits in both AndData and OrData are stripped.
+
+ If 64-bit MMIO register operations are not supported, then ASSERT().
+ If StartBit is greater than 63, then ASSERT().
+ If EndBit is greater than 63, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param[in] Address The MMIO register to write.
+ @param[in] StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..63.
+ @param[in] EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..63.
+ @param[in] AndData The value to AND with the read value from the MMIO register.
+ @param[in] OrData The value to OR with the result of the AND operation.
+
+ @return The value written back to the MMIO register.
+
+**/
+UINT64
+EFIAPI
+S3MmioBitFieldAndThenOr64 (
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT64 AndData,
+ IN UINT64 OrData
+ );
+
+/**
+ Copies data from MMIO region to system memory by using 8-bit access,
+ and saves the value in the S3 script to be replayed on S3 resume.
+
+ Copy data from MMIO region specified by starting address StartAddress
+ to system memory specified by Buffer by using 8-bit access. The total
+ number of bytes to be copied is specified by Length. Buffer is returned.
+
+ If Length is greater than (MAX_ADDRESS - StartAddress + 1), then ASSERT().
+ If Length is greater than (MAX_ADDRESS - Buffer + 1), then ASSERT().
+
+
+ @param[in] StartAddress Starting address for the MMIO region to be copied from.
+ @param[in] Length Size in bytes of the copy.
+ @param[out] Buffer Pointer to a system memory buffer receiving the data read.
+
+ @return Buffer.
+
+**/
+UINT8 *
+EFIAPI
+S3MmioReadBuffer8 (
+ IN UINTN StartAddress,
+ IN UINTN Length,
+ OUT UINT8 *Buffer
+ );
+
+/**
+ Copies data from MMIO region to system memory by using 16-bit access,
+ and saves the value in the S3 script to be replayed on S3 resume.
+
+ Copy data from MMIO region specified by starting address StartAddress
+ to system memory specified by Buffer by using 16-bit access. The total
+ number of bytes to be copied is specified by Length. Buffer is returned.
+
+ If StartAddress is not aligned on a 16-bit boundary, then ASSERT().
+
+ If Length is greater than (MAX_ADDRESS - StartAddress + 1), then ASSERT().
+ If Length is greater than (MAX_ADDRESS - Buffer + 1), then ASSERT().
+
+ If Length is not aligned on a 16-bit boundary, then ASSERT().
+ If Buffer is not aligned on a 16-bit boundary, then ASSERT().
+
+ @param[in] StartAddress Starting address for the MMIO region to be copied from.
+ @param[in] Length Size in bytes of the copy.
+ @param[out] Buffer Pointer to a system memory buffer receiving the data read.
+
+ @return Buffer.
+
+**/
+UINT16 *
+EFIAPI
+S3MmioReadBuffer16 (
+ IN UINTN StartAddress,
+ IN UINTN Length,
+ OUT UINT16 *Buffer
+ );
+
+/**
+ Copies data from MMIO region to system memory by using 32-bit access,
+ and saves the value in the S3 script to be replayed on S3 resume.
+
+ Copy data from MMIO region specified by starting address StartAddress
+ to system memory specified by Buffer by using 32-bit access. The total
+ number of byte to be copied is specified by Length. Buffer is returned.
+
+ If StartAddress is not aligned on a 32-bit boundary, then ASSERT().
+
+ If Length is greater than (MAX_ADDRESS - StartAddress + 1), then ASSERT().
+ If Length is greater than (MAX_ADDRESS - Buffer + 1), then ASSERT().
+
+ If Length is not aligned on a 32-bit boundary, then ASSERT().
+ If Buffer is not aligned on a 32-bit boundary, then ASSERT().
+
+ @param[in] StartAddress Starting address for the MMIO region to be copied from.
+ @param[in] Length Size in bytes of the copy.
+ @param[out] Buffer Pointer to a system memory buffer receiving the data read.
+
+ @return Buffer.
+
+**/
+UINT32 *
+EFIAPI
+S3MmioReadBuffer32 (
+ IN UINTN StartAddress,
+ IN UINTN Length,
+ OUT UINT32 *Buffer
+ );
+
+/**
+ Copies data from MMIO region to system memory by using 64-bit access,
+ and saves the value in the S3 script to be replayed on S3 resume.
+
+ Copy data from MMIO region specified by starting address StartAddress
+ to system memory specified by Buffer by using 64-bit access. The total
+ number of byte to be copied is specified by Length. Buffer is returned.
+
+ If StartAddress is not aligned on a 64-bit boundary, then ASSERT().
+
+ If Length is greater than (MAX_ADDRESS - StartAddress + 1), then ASSERT().
+ If Length is greater than (MAX_ADDRESS - Buffer + 1), then ASSERT().
+
+ If Length is not aligned on a 64-bit boundary, then ASSERT().
+ If Buffer is not aligned on a 64-bit boundary, then ASSERT().
+
+ @param[in] StartAddress Starting address for the MMIO region to be copied from.
+ @param[in] Length Size in bytes of the copy.
+ @param[out] Buffer Pointer to a system memory buffer receiving the data read.
+
+ @return Buffer.
+
+**/
+UINT64 *
+EFIAPI
+S3MmioReadBuffer64 (
+ IN UINTN StartAddress,
+ IN UINTN Length,
+ OUT UINT64 *Buffer
+ );
+
+/**
+ Copies data from system memory to MMIO region by using 8-bit access,
+ and saves the value in the S3 script to be replayed on S3 resume.
+
+ Copy data from system memory specified by Buffer to MMIO region specified
+ by starting address StartAddress by using 8-bit access. The total number
+ of byte to be copied is specified by Length. Buffer is returned.
+
+ If Length is greater than (MAX_ADDRESS - StartAddress + 1), then ASSERT().
+ If Length is greater than (MAX_ADDRESS -Buffer + 1), then ASSERT().
+
+
+ @param[in] StartAddress Starting address for the MMIO region to be copied to.
+ @param[in] Length Size in bytes of the copy.
+ @param[in] Buffer Pointer to a system memory buffer containing the data to write.
+
+ @return Buffer.
+
+**/
+UINT8 *
+EFIAPI
+S3MmioWriteBuffer8 (
+ IN UINTN StartAddress,
+ IN UINTN Length,
+ IN CONST UINT8 *Buffer
+ );
+
+/**
+ Copies data from system memory to MMIO region by using 16-bit access,
+ and saves the value in the S3 script to be replayed on S3 resume.
+
+ Copy data from system memory specified by Buffer to MMIO region specified
+ by starting address StartAddress by using 16-bit access. The total number
+ of bytes to be copied is specified by Length. Buffer is returned.
+
+ If StartAddress is not aligned on a 16-bit boundary, then ASSERT().
+
+ If Length is greater than (MAX_ADDRESS - StartAddress + 1), then ASSERT().
+ If Length is greater than (MAX_ADDRESS -Buffer + 1), then ASSERT().
+
+ If Length is not aligned on a 16-bit boundary, then ASSERT().
+
+ If Buffer is not aligned on a 16-bit boundary, then ASSERT().
+
+ @param[in] StartAddress Starting address for the MMIO region to be copied to.
+ @param[in] Length Size in bytes of the copy.
+ @param[in] Buffer Pointer to a system memory buffer containing the data to write.
+
+ @return Buffer.
+
+**/
+UINT16 *
+EFIAPI
+S3MmioWriteBuffer16 (
+ IN UINTN StartAddress,
+ IN UINTN Length,
+ IN CONST UINT16 *Buffer
+ );
+
+/**
+ Copies data from system memory to MMIO region by using 32-bit access,
+ and saves the value in the S3 script to be replayed on S3 resume.
+
+ Copy data from system memory specified by Buffer to MMIO region specified
+ by starting address StartAddress by using 32-bit access. The total number
+ of bytes to be copied is specified by Length. Buffer is returned.
+
+ If StartAddress is not aligned on a 32-bit boundary, then ASSERT().
+
+ If Length is greater than (MAX_ADDRESS - StartAddress + 1), then ASSERT().
+ If Length is greater than (MAX_ADDRESS -Buffer + 1), then ASSERT().
+
+ If Length is not aligned on a 32-bit boundary, then ASSERT().
+
+ If Buffer is not aligned on a 32-bit boundary, then ASSERT().
+
+ @param[in] StartAddress Starting address for the MMIO region to be copied to.
+ @param[in] Length Size in bytes of the copy.
+ @param[in] Buffer Pointer to a system memory buffer containing the data to write.
+
+ @return Buffer.
+
+**/
+UINT32 *
+EFIAPI
+S3MmioWriteBuffer32 (
+ IN UINTN StartAddress,
+ IN UINTN Length,
+ IN CONST UINT32 *Buffer
+ );
+
+/**
+ Copies data from system memory to MMIO region by using 64-bit access,
+ and saves the value in the S3 script to be replayed on S3 resume.
+
+ Copy data from system memory specified by Buffer to MMIO region specified
+ by starting address StartAddress by using 64-bit access. The total number
+ of bytes to be copied is specified by Length. Buffer is returned.
+
+ If StartAddress is not aligned on a 64-bit boundary, then ASSERT().
+
+ If Length is greater than (MAX_ADDRESS - StartAddress + 1), then ASSERT().
+ If Length is greater than (MAX_ADDRESS -Buffer + 1), then ASSERT().
+
+ If Length is not aligned on a 64-bit boundary, then ASSERT().
+
+ If Buffer is not aligned on a 64-bit boundary, then ASSERT().
+
+ @param[in] StartAddress Starting address for the MMIO region to be copied to.
+ @param[in] Length Size in bytes of the copy.
+ @param[in] Buffer Pointer to a system memory buffer containing the data to write.
+
+ @return Buffer.
+
+**/
+UINT64 *
+EFIAPI
+S3MmioWriteBuffer64 (
+ IN UINTN StartAddress,
+ IN UINTN Length,
+ IN CONST UINT64 *Buffer
+ );
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/S3PciLib.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/S3PciLib.h
new file mode 100644
index 0000000000..2580cff0dd
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/S3PciLib.h
@@ -0,0 +1,1045 @@
+/** @file
+ The PCI configuration Library Services that carry out PCI configuration and enable
+ the PCI operations to be replayed during an S3 resume. This library class
+ maps directly on top of the PciLib class.
+
+ Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __S3_PCI_LIB_H__
+#define __S3_PCI_LIB_H__
+
+/**
+ Macro that converts PCI Bus, PCI Device, PCI Function and PCI Register to an
+ address that can be passed to the S3 PCI Library functions.
+
+ @param Bus The PCI Bus number. Range 0..255.
+ @param Device The PCI Device number. Range 0..31.
+ @param Function The PCI Function number. Range 0..7.
+ @param Register The PCI Register number. Range 0..255 for PCI. Range 0..4095
+ for PCI Express.
+
+ @return The encoded PCI address.
+
+**/
+#define S3_PCI_LIB_ADDRESS(Bus, Device, Function, Register) \
+ (((Register) & 0xfff) | (((Function) & 0x07) << 12) | (((Device) & 0x1f) << 15) | (((Bus) & 0xff) << 20))
+
+/**
+
+ Reads and returns the 8-bit PCI configuration register specified by Address,
+ and saves the value in the S3 script to be replayed on S3 resume.
+ This function must guarantee that all PCI read and write operations are
+ serialized.
+
+ If Address > 0x0FFFFFFF, then ASSERT().
+
+ @param[in] Address The address that encodes the PCI Bus, Device, Function and
+ Register.
+
+ @return The value read from the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+S3PciRead8 (
+ IN UINTN Address
+ );
+
+/**
+ Writes an 8-bit PCI configuration register, and saves the value in the S3
+ script to be replayed on S3 resume.
+
+ Writes the 8-bit PCI configuration register specified by Address with the
+ value specified by Value. Value is returned. This function must guarantee
+ that all PCI read and write operations are serialized.
+
+ If Address > 0x0FFFFFFF, then ASSERT().
+
+ @param[in] Address The address that encodes the PCI Bus, Device, Function and
+ Register.
+ @param[in] Value The value to write.
+
+ @return The value written to the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+S3PciWrite8 (
+ IN UINTN Address,
+ IN UINT8 Value
+ );
+
+/**
+ Performs a bitwise OR of an 8-bit PCI configuration register with
+ an 8-bit value, and saves the value in the S3 script to be replayed on S3 resume.
+
+ Reads the 8-bit PCI configuration register specified by Address, performs a
+ bitwise OR between the read result and the value specified by
+ OrData, and writes the result to the 8-bit PCI configuration register
+ specified by Address. The value written to the PCI configuration register is
+ returned. This function must guarantee that all PCI read and write operations
+ are serialized.
+
+ If Address > 0x0FFFFFFF, then ASSERT().
+
+ @param[in] Address The address that encodes the PCI Bus, Device, Function and
+ Register.
+ @param[in] OrData The value to OR with the PCI configuration register.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+S3PciOr8 (
+ IN UINTN Address,
+ IN UINT8 OrData
+ );
+
+/**
+ Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
+ value, and saves the value in the S3 script to be replayed on S3 resume.
+
+ Reads the 8-bit PCI configuration register specified by Address, performs a
+ bitwise AND between the read result and the value specified by AndData, and
+ writes the result to the 8-bit PCI configuration register specified by
+ Address. The value written to the PCI configuration register is returned.
+ This function must guarantee that all PCI read and write operations are
+ serialized.
+
+ If Address > 0x0FFFFFFF, then ASSERT().
+
+ @param[in] Address The address that encodes the PCI Bus, Device, Function and
+ Register.
+ @param[in] AndData The value to AND with the PCI configuration register.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+S3PciAnd8 (
+ IN UINTN Address,
+ IN UINT8 AndData
+ );
+
+/**
+ Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
+ value, followed a bitwise OR with another 8-bit value, and saves
+ the value in the S3 script to be replayed on S3 resume.
+
+ Reads the 8-bit PCI configuration register specified by Address, performs a
+ bitwise AND between the read result and the value specified by AndData,
+ performs a bitwise OR between the result of the AND operation and
+ the value specified by OrData, and writes the result to the 8-bit PCI
+ configuration register specified by Address. The value written to the PCI
+ configuration register is returned. This function must guarantee that all PCI
+ read and write operations are serialized.
+
+ If Address > 0x0FFFFFFF, then ASSERT().
+
+ @param[in] Address The address that encodes the PCI Bus, Device, Function and
+ Register.
+ @param[in] AndData The value to AND with the PCI configuration register.
+ @param[in] OrData The value to OR with the result of the AND operation.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+S3PciAndThenOr8 (
+ IN UINTN Address,
+ IN UINT8 AndData,
+ IN UINT8 OrData
+ );
+
+/**
+ Reads a bit field of a PCI configuration register, and saves the value in
+ the S3 script to be replayed on S3 resume.
+
+ Reads the bit field in an 8-bit PCI configuration register. The bit field is
+ specified by the StartBit and the EndBit. The value of the bit field is
+ returned.
+
+ If Address > 0x0FFFFFFF, then ASSERT().
+ If StartBit is greater than 7, then ASSERT().
+ If EndBit is greater than 7, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+
+ @param[in] Address The PCI configuration register to read.
+ @param[in] StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..7.
+ @param[in] EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..7.
+
+ @return The value of the bit field read from the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+S3PciBitFieldRead8 (
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit
+ );
+
+/**
+ Writes a bit field to a PCI configuration register, and saves the value in
+ the S3 script to be replayed on S3 resume.
+
+ Writes Value to the bit field of the PCI configuration register. The bit
+ field is specified by the StartBit and the EndBit. All other bits in the
+ destination PCI configuration register are preserved. The new value of the
+ 8-bit register is returned.
+
+ If Address > 0x0FFFFFFF, then ASSERT().
+ If StartBit is greater than 7, then ASSERT().
+ If EndBit is greater than 7, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param[in] Address The PCI configuration register to write.
+ @param[in] StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..7.
+ @param[in] EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..7.
+ @param[in] Value New value of the bit field.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+S3PciBitFieldWrite8 (
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT8 Value
+ );
+
+/**
+ Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and
+ writes the result back to the bit field in the 8-bit port, and saves the value
+ in the S3 script to be replayed on S3 resume.
+
+ Reads the 8-bit PCI configuration register specified by Address, performs a
+ bitwise OR between the read result and the value specified by
+ OrData, and writes the result to the 8-bit PCI configuration register
+ specified by Address. The value written to the PCI configuration register is
+ returned. This function must guarantee that all PCI read and write operations
+ are serialized. Extra left bits in OrData are stripped.
+
+ If Address > 0x0FFFFFFF, then ASSERT().
+ If StartBit is greater than 7, then ASSERT().
+ If EndBit is greater than 7, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param[in] Address The PCI configuration register to write.
+ @param[in] StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..7.
+ @param[in] EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..7.
+ @param[in] OrData The value to OR with the PCI configuration register.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+S3PciBitFieldOr8 (
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT8 OrData
+ );
+
+/**
+ Reads a bit field in an 8-bit PCI configuration register, performs a bitwise
+ AND, and writes the result back to the bit field in the 8-bit register and
+ saves the value in the S3 script to be replayed on S3 resume.
+
+ Reads the 8-bit PCI configuration register specified by Address, performs a
+ bitwise AND between the read result and the value specified by AndData, and
+ writes the result to the 8-bit PCI configuration register specified by
+ Address. The value written to the PCI configuration register is returned.
+ This function must guarantee that all PCI read and write operations are
+ serialized. Extra left bits in AndData are stripped.
+
+ If Address > 0x0FFFFFFF, then ASSERT().
+ If StartBit is greater than 7, then ASSERT().
+ If EndBit is greater than 7, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param[in] Address The PCI configuration register to write.
+ @param[in] StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..7.
+ @param[in] EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..7.
+ @param[in] AndData The value to AND with the PCI configuration register.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+S3PciBitFieldAnd8 (
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT8 AndData
+ );
+
+/**
+ Reads a bit field in an 8-bit Address, performs a bitwise AND followed by a
+ bitwise OR, and writes the result back to the bit field in the
+ 8-bit port, and saves the value in the S3 script to be replayed on S3 resume.
+
+ Reads the 8-bit PCI configuration register specified by Address, performs a
+ bitwise AND followed by a bitwise OR between the read result and
+ the value specified by AndData, and writes the result to the 8-bit PCI
+ configuration register specified by Address. The value written to the PCI
+ configuration register is returned. This function must guarantee that all PCI
+ read and write operations are serialized. Extra left bits in both AndData and
+ OrData are stripped.
+
+ If Address > 0x0FFFFFFF, then ASSERT().
+ If StartBit is greater than 7, then ASSERT().
+ If EndBit is greater than 7, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param[in] Address The PCI configuration register to write.
+ @param[in] StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..7.
+ @param[in] EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..7.
+ @param[in] AndData The value to AND with the PCI configuration register.
+ @param[in] OrData The value to OR with the result of the AND operation.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+S3PciBitFieldAndThenOr8 (
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT8 AndData,
+ IN UINT8 OrData
+ );
+
+/**
+ Reads a 16-bit PCI configuration register, and saves the value in the S3
+ script to be replayed on S3 resume.
+
+ Reads and returns the 16-bit PCI configuration register specified by Address.
+ This function must guarantee that all PCI read and write operations are
+ serialized.
+
+ If Address > 0x0FFFFFFF, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+
+ @param[in] Address The address that encodes the PCI Bus, Device, Function and
+ Register.
+
+ @return The read value from the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+S3PciRead16 (
+ IN UINTN Address
+ );
+
+/**
+ Writes a 16-bit PCI configuration register, and saves the value in the S3
+ script to be replayed on S3 resume.
+
+ Writes the 16-bit PCI configuration register specified by Address with the
+ value specified by Value. Value is returned. This function must guarantee
+ that all PCI read and write operations are serialized.
+
+ If Address > 0x0FFFFFFF, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+
+ @param[in] Address The address that encodes the PCI Bus, Device, Function and
+ Register.
+ @param[in] Value The value to write.
+
+ @return The value written to the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+S3PciWrite16 (
+ IN UINTN Address,
+ IN UINT16 Value
+ );
+
+/**
+ Performs a bitwise OR of a 16-bit PCI configuration register with
+ a 16-bit value, and saves the value in the S3 script to be replayed on S3 resume.
+
+ Reads the 16-bit PCI configuration register specified by Address, performs a
+ bitwise OR between the read result and the value specified by
+ OrData, and writes the result to the 16-bit PCI configuration register
+ specified by Address. The value written to the PCI configuration register is
+ returned. This function must guarantee that all PCI read and write operations
+ are serialized.
+
+ If Address > 0x0FFFFFFF, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+
+ @param[in] Address The address that encodes the PCI Bus, Device, Function and
+ Register.
+ @param[in] OrData The value to OR with the PCI configuration register.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+S3PciOr16 (
+ IN UINTN Address,
+ IN UINT16 OrData
+ );
+
+/**
+ Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
+ value, and saves the value in the S3 script to be replayed on S3 resume.
+
+ Reads the 16-bit PCI configuration register specified by Address, performs a
+ bitwise AND between the read result and the value specified by AndData, and
+ writes the result to the 16-bit PCI configuration register specified by
+ Address. The value written to the PCI configuration register is returned.
+ This function must guarantee that all PCI read and write operations are
+ serialized.
+
+ If Address > 0x0FFFFFFF, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+
+ @param[in] Address The address that encodes the PCI Bus, Device, Function and
+ Register.
+ @param[in] AndData The value to AND with the PCI configuration register.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+S3PciAnd16 (
+ IN UINTN Address,
+ IN UINT16 AndData
+ );
+
+/**
+ Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
+ value, followed a bitwise OR with another 16-bit value, and saves
+ the value in the S3 script to be replayed on S3 resume.
+
+ Reads the 16-bit PCI configuration register specified by Address, performs a
+ bitwise AND between the read result and the value specified by AndData,
+ performs a bitwise OR between the result of the AND operation and
+ the value specified by OrData, and writes the result to the 16-bit PCI
+ configuration register specified by Address. The value written to the PCI
+ configuration register is returned. This function must guarantee that all PCI
+ read and write operations are serialized.
+
+ If Address > 0x0FFFFFFF, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+
+ @param[in] Address The address that encodes the PCI Bus, Device, Function and
+ Register.
+ @param[in] AndData The value to AND with the PCI configuration register.
+ @param[in] OrData The value to OR with the result of the AND operation.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+S3PciAndThenOr16 (
+ IN UINTN Address,
+ IN UINT16 AndData,
+ IN UINT16 OrData
+ );
+
+/**
+ Reads a bit field of a PCI configuration register, and saves the value in
+ the S3 script to be replayed on S3 resume.
+
+ Reads the bit field in a 16-bit PCI configuration register. The bit field is
+ specified by the StartBit and the EndBit. The value of the bit field is
+ returned.
+
+ If Address > 0x0FFFFFFF, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+ If StartBit is greater than 15, then ASSERT().
+ If EndBit is greater than 15, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+
+ @param[in] Address The PCI configuration register to read.
+ @param[in] StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..15.
+ @param[in] EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..15.
+
+ @return The value of the bit field read from the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+S3PciBitFieldRead16 (
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit
+ );
+
+/**
+ Writes a bit field to a PCI configuration register, and saves the value in
+ the S3 script to be replayed on S3 resume.
+
+ Writes Value to the bit field of the PCI configuration register. The bit
+ field is specified by the StartBit and the EndBit. All other bits in the
+ destination PCI configuration register are preserved. The new value of the
+ 16-bit register is returned.
+
+ If Address > 0x0FFFFFFF, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+ If StartBit is greater than 15, then ASSERT().
+ If EndBit is greater than 15, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param[in] Address The PCI configuration register to write.
+ @param[in] StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..15.
+ @param[in] EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..15.
+ @param[in] Value New value of the bit field.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+S3PciBitFieldWrite16 (
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT16 Value
+ );
+
+/**
+ Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and
+ writes the result back to the bit field in the 16-bit port, and saves the value
+ in the S3 script to be replayed on S3 resume.
+
+ Reads the 16-bit PCI configuration register specified by Address, performs a
+ bitwise OR between the read result and the value specified by
+ OrData, and writes the result to the 16-bit PCI configuration register
+ specified by Address. The value written to the PCI configuration register is
+ returned. This function must guarantee that all PCI read and write operations
+ are serialized. Extra left bits in OrData are stripped.
+
+ If Address > 0x0FFFFFFF, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+ If StartBit is greater than 15, then ASSERT().
+ If EndBit is greater than 15, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param[in] Address The PCI configuration register to write.
+ @param[in] StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..15.
+ @param[in] EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..15.
+ @param[in] OrData The value to OR with the PCI configuration register.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+S3PciBitFieldOr16 (
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT16 OrData
+ );
+
+/**
+ Reads a bit field in a 16-bit PCI configuration register, performs a bitwise
+ AND, and writes the result back to the bit field in the 16-bit register and
+ saves the value in the S3 script to be replayed on S3 resume.
+
+ Reads the 16-bit PCI configuration register specified by Address, performs a
+ bitwise AND between the read result and the value specified by AndData, and
+ writes the result to the 16-bit PCI configuration register specified by
+ Address. The value written to the PCI configuration register is returned.
+ This function must guarantee that all PCI read and write operations are
+ serialized. Extra left bits in AndData are stripped.
+
+ If Address > 0x0FFFFFFF, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+ If StartBit is greater than 15, then ASSERT().
+ If EndBit is greater than 15, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param[in] Address The PCI configuration register to write.
+ @param[in] StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..15.
+ @param[in] EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..15.
+ @param[in] AndData The value to AND with the PCI configuration register.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+S3PciBitFieldAnd16 (
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT16 AndData
+ );
+
+/**
+ Reads a bit field in a 16-bit Address, performs a bitwise AND followed by a
+ bitwise OR, and writes the result back to the bit field in the
+ 16-bit port, and saves the value in the S3 script to be replayed on S3 resume.
+
+ Reads the 16-bit PCI configuration register specified by Address, performs a
+ bitwise AND followed by a bitwise OR between the read result and
+ the value specified by AndData, and writes the result to the 16-bit PCI
+ configuration register specified by Address. The value written to the PCI
+ configuration register is returned. This function must guarantee that all PCI
+ read and write operations are serialized. Extra left bits in both AndData and
+ OrData are stripped.
+
+ If Address > 0x0FFFFFFF, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+ If StartBit is greater than 15, then ASSERT().
+ If EndBit is greater than 15, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param[in] Address The PCI configuration register to write.
+ @param[in] StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..15.
+ @param[in] EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..15.
+ @param[in] AndData The value to AND with the PCI configuration register.
+ @param[in] OrData The value to OR with the result of the AND operation.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+S3PciBitFieldAndThenOr16 (
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT16 AndData,
+ IN UINT16 OrData
+ );
+
+/**
+ Reads a 32-bit PCI configuration register, and saves the value in the S3
+ script to be replayed on S3 resume.
+
+ Reads and returns the 32-bit PCI configuration register specified by Address.
+ This function must guarantee that all PCI read and write operations are
+ serialized.
+
+ If Address > 0x0FFFFFFF, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+
+ @param[in] Address The address that encodes the PCI Bus, Device, Function and
+ Register.
+
+ @return The read value from the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+S3PciRead32 (
+ IN UINTN Address
+ );
+
+/**
+ Writes a 32-bit PCI configuration register, and saves the value in the S3
+ script to be replayed on S3 resume.
+
+ Writes the 32-bit PCI configuration register specified by Address with the
+ value specified by Value. Value is returned. This function must guarantee
+ that all PCI read and write operations are serialized.
+
+ If Address > 0x0FFFFFFF, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+
+ @param[in] Address The address that encodes the PCI Bus, Device, Function and
+ Register.
+ @param[in] Value The value to write.
+
+ @return The value written to the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+S3PciWrite32 (
+ IN UINTN Address,
+ IN UINT32 Value
+ );
+
+/**
+ Performs a bitwise OR of a 32-bit PCI configuration register with
+ a 32-bit value, and saves the value in the S3 script to be replayed on S3 resume.
+
+ Reads the 32-bit PCI configuration register specified by Address, performs a
+ bitwise OR between the read result and the value specified by
+ OrData, and writes the result to the 32-bit PCI configuration register
+ specified by Address. The value written to the PCI configuration register is
+ returned. This function must guarantee that all PCI read and write operations
+ are serialized.
+
+ If Address > 0x0FFFFFFF, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+
+ @param[in] Address The address that encodes the PCI Bus, Device, Function and
+ Register.
+ @param[in] OrData The value to OR with the PCI configuration register.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+S3PciOr32 (
+ IN UINTN Address,
+ IN UINT32 OrData
+ );
+
+/**
+ Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
+ value, and saves the value in the S3 script to be replayed on S3 resume.
+
+ Reads the 32-bit PCI configuration register specified by Address, performs a
+ bitwise AND between the read result and the value specified by AndData, and
+ writes the result to the 32-bit PCI configuration register specified by
+ Address. The value written to the PCI configuration register is returned.
+ This function must guarantee that all PCI read and write operations are
+ serialized.
+
+ If Address > 0x0FFFFFFF, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+
+ @param[in] Address The address that encodes the PCI Bus, Device, Function and
+ Register.
+ @param[in] AndData The value to AND with the PCI configuration register.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+S3PciAnd32 (
+ IN UINTN Address,
+ IN UINT32 AndData
+ );
+
+/**
+ Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
+ value, followed a bitwise OR with another 32-bit value, and saves
+ the value in the S3 script to be replayed on S3 resume.
+
+ Reads the 32-bit PCI configuration register specified by Address, performs a
+ bitwise AND between the read result and the value specified by AndData,
+ performs a bitwise OR between the result of the AND operation and
+ the value specified by OrData, and writes the result to the 32-bit PCI
+ configuration register specified by Address. The value written to the PCI
+ configuration register is returned. This function must guarantee that all PCI
+ read and write operations are serialized.
+
+ If Address > 0x0FFFFFFF, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+
+ @param[in] Address The address that encodes the PCI Bus, Device, Function and
+ Register.
+ @param[in] AndData The value to AND with the PCI configuration register.
+ @param[in] OrData The value to OR with the result of the AND operation.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+S3PciAndThenOr32 (
+ IN UINTN Address,
+ IN UINT32 AndData,
+ IN UINT32 OrData
+ );
+
+/**
+ Reads a bit field of a PCI configuration register, and saves the value in
+ the S3 script to be replayed on S3 resume.
+
+ Reads the bit field in a 32-bit PCI configuration register. The bit field is
+ specified by the StartBit and the EndBit. The value of the bit field is
+ returned.
+
+ If Address > 0x0FFFFFFF, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+ If StartBit is greater than 31, then ASSERT().
+ If EndBit is greater than 31, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+
+ @param[in] Address The PCI configuration register to read.
+ @param[in] StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..31.
+ @param[in] EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..31.
+
+ @return The value of the bit field read from the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+S3PciBitFieldRead32 (
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit
+ );
+
+/**
+ Writes a bit field to a PCI configuration register, and saves the value in
+ the S3 script to be replayed on S3 resume.
+
+ Writes Value to the bit field of the PCI configuration register. The bit
+ field is specified by the StartBit and the EndBit. All other bits in the
+ destination PCI configuration register are preserved. The new value of the
+ 32-bit register is returned.
+
+ If Address > 0x0FFFFFFF, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+ If StartBit is greater than 31, then ASSERT().
+ If EndBit is greater than 31, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param[in] Address The PCI configuration register to write.
+ @param[in] StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..31.
+ @param[in] EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..31.
+ @param[in] Value New value of the bit field.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+S3PciBitFieldWrite32 (
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 Value
+ );
+
+/**
+ Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and
+ writes the result back to the bit field in the 32-bit port, and saves the value
+ in the S3 script to be replayed on S3 resume.
+
+ Reads the 32-bit PCI configuration register specified by Address, performs a
+ bitwise OR between the read result and the value specified by
+ OrData, and writes the result to the 32-bit PCI configuration register
+ specified by Address. The value written to the PCI configuration register is
+ returned. This function must guarantee that all PCI read and write operations
+ are serialized. Extra left bits in OrData are stripped.
+
+ If Address > 0x0FFFFFFF, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+ If StartBit is greater than 31, then ASSERT().
+ If EndBit is greater than 31, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param[in] Address The PCI configuration register to write.
+ @param[in] StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..31.
+ @param[in] EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..31.
+ @param[in] OrData The value to OR with the PCI configuration register.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+S3PciBitFieldOr32 (
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 OrData
+ );
+
+/**
+ Reads a bit field in a 32-bit PCI configuration register, performs a bitwise
+ AND, and writes the result back to the bit field in the 32-bit register and
+ saves the value in the S3 script to be replayed on S3 resume.
+
+ Reads the 32-bit PCI configuration register specified by Address, performs a
+ bitwise AND between the read result and the value specified by AndData, and
+ writes the result to the 32-bit PCI configuration register specified by
+ Address. The value written to the PCI configuration register is returned.
+ This function must guarantee that all PCI read and write operations are
+ serialized. Extra left bits in AndData are stripped.
+
+ If Address > 0x0FFFFFFF, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+ If StartBit is greater than 31, then ASSERT().
+ If EndBit is greater than 31, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param[in] Address The PCI configuration register to write.
+ @param[in] StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..31.
+ @param[in] EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..31.
+ @param[in] AndData The value to AND with the PCI configuration register.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+S3PciBitFieldAnd32 (
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 AndData
+ );
+
+/**
+ Reads a bit field in a 32-bit Address, performs a bitwise AND followed by a
+ bitwise OR, and writes the result back to the bit field in the
+ 32-bit port, and saves the value in the S3 script to be replayed on S3 resume.
+
+ Reads the 32-bit PCI configuration register specified by Address, performs a
+ bitwise AND followed by a bitwise OR between the read result and
+ the value specified by AndData, and writes the result to the 32-bit PCI
+ configuration register specified by Address. The value written to the PCI
+ configuration register is returned. This function must guarantee that all PCI
+ read and write operations are serialized. Extra left bits in both AndData and
+ OrData are stripped.
+
+ If Address > 0x0FFFFFFF, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+ If StartBit is greater than 31, then ASSERT().
+ If EndBit is greater than 31, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param[in] Address The PCI configuration register to write.
+ @param[in] StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..31.
+ @param[in] EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..31.
+ @param[in] AndData The value to AND with the PCI configuration register.
+ @param[in] OrData The value to OR with the result of the AND operation.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+S3PciBitFieldAndThenOr32 (
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 AndData,
+ IN UINT32 OrData
+ );
+
+/**
+ Reads a range of PCI configuration registers into a caller supplied buffer,
+ and saves the value in the S3 script to be replayed on S3 resume.
+
+ Reads the range of PCI configuration registers specified by StartAddress and
+ Size into the buffer specified by Buffer. This function only allows the PCI
+ configuration registers from a single PCI function to be read. Size is
+ returned. When possible 32-bit PCI configuration read cycles are used to read
+ from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit
+ and 16-bit PCI configuration read cycles may be used at the beginning and the
+ end of the range.
+
+ If StartAddress > 0x0FFFFFFF, then ASSERT().
+ If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
+ If Size > 0 and Buffer is NULL, then ASSERT().
+
+ @param[in] StartAddress Starting address that encodes the PCI Bus, Device,
+ Function and Register.
+ @param[in] Size Size in bytes of the transfer.
+ @param[out] Buffer The pointer to a buffer receiving the data read.
+
+ @return Size.
+
+**/
+UINTN
+EFIAPI
+S3PciReadBuffer (
+ IN UINTN StartAddress,
+ IN UINTN Size,
+ OUT VOID *Buffer
+ );
+
+/**
+ Copies the data in a caller supplied buffer to a specified range of PCI
+ configuration space, and saves the value in the S3 script to be replayed on S3
+ resume.
+
+ Writes the range of PCI configuration registers specified by StartAddress and
+ Size from the buffer specified by Buffer. This function only allows the PCI
+ configuration registers from a single PCI function to be written. Size is
+ returned. When possible 32-bit PCI configuration write cycles are used to
+ write from StartAdress to StartAddress + Size. Due to alignment restrictions,
+ 8-bit and 16-bit PCI configuration write cycles may be used at the beginning
+ and the end of the range.
+
+ If StartAddress > 0x0FFFFFFF, then ASSERT().
+ If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
+ If Size > 0 and Buffer is NULL, then ASSERT().
+
+ @param[in] StartAddress Starting address that encodes the PCI Bus, Device,
+ Function and Register.
+ @param[in] Size Size in bytes of the transfer.
+ @param[in] Buffer The pointer to a buffer containing the data to write.
+
+ @return Size.
+
+**/
+UINTN
+EFIAPI
+S3PciWriteBuffer (
+ IN UINTN StartAddress,
+ IN UINTN Size,
+ IN VOID *Buffer
+ );
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/S3PciSegmentLib.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/S3PciSegmentLib.h
new file mode 100644
index 0000000000..1923c45e6f
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/S3PciSegmentLib.h
@@ -0,0 +1,1030 @@
+/** @file
+ The multiple segments PCI configuration Library Services that carry out
+ PCI configuration and enable the PCI operations to be replayed during an
+ S3 resume. This library class maps directly on top of the PciSegmentLib class.
+
+ Copyright (c) 2017, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __S3_PCI_SEGMENT_LIB__
+#define __S3_PCI_SEGMENT_LIB__
+
+/**
+ Macro that converts PCI Segment, PCI Bus, PCI Device, PCI Function,
+ and PCI Register to an address that can be passed to the S3 PCI Segment Library functions.
+
+ Computes an address that is compatible with the PCI Segment Library functions.
+ The unused upper bits of Segment, Bus, Device, Function,
+ and Register are stripped prior to the generation of the address.
+
+ @param Segment PCI Segment number. Range 0..65535.
+ @param Bus PCI Bus number. Range 0..255.
+ @param Device PCI Device number. Range 0..31.
+ @param Function PCI Function number. Range 0..7.
+ @param Register PCI Register number. Range 0..255 for PCI. Range 0..4095 for PCI Express.
+
+ @return The address that is compatible with the PCI Segment Library functions.
+
+**/
+#define S3_PCI_SEGMENT_LIB_ADDRESS(Segment, Bus, Device, Function, Register) \
+ ((Segment != 0) ? \
+ ( ((Register) & 0xfff) | \
+ (((Function) & 0x07) << 12) | \
+ (((Device) & 0x1f) << 15) | \
+ (((Bus) & 0xff) << 20) | \
+ (LShiftU64 ((Segment) & 0xffff, 32)) \
+ ) : \
+ ( ((Register) & 0xfff) | \
+ (((Function) & 0x07) << 12) | \
+ (((Device) & 0x1f) << 15) | \
+ (((Bus) & 0xff) << 20) \
+ ) \
+ )
+
+/**
+ Reads an 8-bit PCI configuration register, and saves the value in the S3 script to
+ be replayed on S3 resume.
+
+ Reads and returns the 8-bit PCI configuration register specified by Address.
+ This function must guarantee that all PCI read and write operations are serialized.
+
+ If any reserved bits in Address are set, then ASSERT().
+
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
+
+ @return The 8-bit PCI configuration register specified by Address.
+
+**/
+UINT8
+EFIAPI
+S3PciSegmentRead8 (
+ IN UINT64 Address
+ );
+
+/**
+ Writes an 8-bit PCI configuration register, and saves the value in the S3 script to
+ be replayed on S3 resume.
+
+ Writes the 8-bit PCI configuration register specified by Address with the value specified by Value.
+ Value is returned. This function must guarantee that all PCI read and write operations are serialized.
+
+ If any reserved bits in Address are set, then ASSERT().
+
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
+ @param Value The value to write.
+
+ @return The value written to the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+S3PciSegmentWrite8 (
+ IN UINT64 Address,
+ IN UINT8 Value
+ );
+
+/**
+ Performs a bitwise OR of an 8-bit PCI configuration register with an 8-bit value, and saves
+ the value in the S3 script to be replayed on S3 resume.
+
+ Reads the 8-bit PCI configuration register specified by Address,
+ performs a bitwise OR between the read result and the value specified by OrData,
+ and writes the result to the 8-bit PCI configuration register specified by Address.
+ The value written to the PCI configuration register is returned.
+ This function must guarantee that all PCI read and write operations are serialized.
+
+ If any reserved bits in Address are set, then ASSERT().
+
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
+ @param OrData The value to OR with the PCI configuration register.
+
+ @return The value written to the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+S3PciSegmentOr8 (
+ IN UINT64 Address,
+ IN UINT8 OrData
+ );
+
+/**
+ Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value, and
+ saves the value in the S3 script to be replayed on S3 resume.
+
+ Reads the 8-bit PCI configuration register specified by Address,
+ performs a bitwise AND between the read result and the value specified by AndData,
+ and writes the result to the 8-bit PCI configuration register specified by Address.
+ The value written to the PCI configuration register is returned.
+ This function must guarantee that all PCI read and write operations are serialized.
+ If any reserved bits in Address are set, then ASSERT().
+
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
+ @param AndData The value to AND with the PCI configuration register.
+
+ @return The value written to the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+S3PciSegmentAnd8 (
+ IN UINT64 Address,
+ IN UINT8 AndData
+ );
+
+/**
+ Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value,
+ followed a bitwise OR with another 8-bit value, and saves the value in the S3 script to
+ be replayed on S3 resume.
+
+ Reads the 8-bit PCI configuration register specified by Address,
+ performs a bitwise AND between the read result and the value specified by AndData,
+ performs a bitwise OR between the result of the AND operation and the value specified by OrData,
+ and writes the result to the 8-bit PCI configuration register specified by Address.
+ The value written to the PCI configuration register is returned.
+ This function must guarantee that all PCI read and write operations are serialized.
+
+ If any reserved bits in Address are set, then ASSERT().
+
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
+ @param AndData The value to AND with the PCI configuration register.
+ @param OrData The value to OR with the PCI configuration register.
+
+ @return The value written to the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+S3PciSegmentAndThenOr8 (
+ IN UINT64 Address,
+ IN UINT8 AndData,
+ IN UINT8 OrData
+ );
+
+/**
+ Reads a bit field of a PCI configuration register, and saves the value in the
+ S3 script to be replayed on S3 resume.
+
+ Reads the bit field in an 8-bit PCI configuration register. The bit field is
+ specified by the StartBit and the EndBit. The value of the bit field is
+ returned.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If StartBit is greater than 7, then ASSERT().
+ If EndBit is greater than 7, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+
+ @param Address PCI configuration register to read.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..7.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..7.
+
+ @return The value of the bit field read from the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+S3PciSegmentBitFieldRead8 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit
+ );
+
+/**
+ Writes a bit field to a PCI configuration register, and saves the value in
+ the S3 script to be replayed on S3 resume.
+
+ Writes Value to the bit field of the PCI configuration register. The bit
+ field is specified by the StartBit and the EndBit. All other bits in the
+ destination PCI configuration register are preserved. The new value of the
+ 8-bit register is returned.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If StartBit is greater than 7, then ASSERT().
+ If EndBit is greater than 7, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Address PCI configuration register to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..7.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..7.
+ @param Value New value of the bit field.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+S3PciSegmentBitFieldWrite8 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT8 Value
+ );
+
+/**
+ Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, writes
+ the result back to the bit field in the 8-bit port, and saves the value in the
+ S3 script to be replayed on S3 resume.
+
+ Reads the 8-bit PCI configuration register specified by Address, performs a
+ bitwise OR between the read result and the value specified by
+ OrData, and writes the result to the 8-bit PCI configuration register
+ specified by Address. The value written to the PCI configuration register is
+ returned. This function must guarantee that all PCI read and write operations
+ are serialized. Extra left bits in OrData are stripped.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If StartBit is greater than 7, then ASSERT().
+ If EndBit is greater than 7, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Address PCI configuration register to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..7.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..7.
+ @param OrData The value to OR with the PCI configuration register.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+S3PciSegmentBitFieldOr8 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT8 OrData
+ );
+
+/**
+ Reads a bit field in an 8-bit PCI configuration register, performs a bitwise
+ AND, writes the result back to the bit field in the 8-bit register, and
+ saves the value in the S3 script to be replayed on S3 resume.
+
+ Reads the 8-bit PCI configuration register specified by Address, performs a
+ bitwise AND between the read result and the value specified by AndData, and
+ writes the result to the 8-bit PCI configuration register specified by
+ Address. The value written to the PCI configuration register is returned.
+ This function must guarantee that all PCI read and write operations are
+ serialized. Extra left bits in AndData are stripped.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If StartBit is greater than 7, then ASSERT().
+ If EndBit is greater than 7, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Address PCI configuration register to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..7.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..7.
+ @param AndData The value to AND with the PCI configuration register.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+S3PciSegmentBitFieldAnd8 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT8 AndData
+ );
+
+/**
+ Reads a bit field in an 8-bit port, performs a bitwise AND followed by a
+ bitwise OR, writes the result back to the bit field in the 8-bit port,
+ and saves the value in the S3 script to be replayed on S3 resume.
+
+ Reads the 8-bit PCI configuration register specified by Address, performs a
+ bitwise AND followed by a bitwise OR between the read result and
+ the value specified by AndData, and writes the result to the 8-bit PCI
+ configuration register specified by Address. The value written to the PCI
+ configuration register is returned. This function must guarantee that all PCI
+ read and write operations are serialized. Extra left bits in both AndData and
+ OrData are stripped.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If StartBit is greater than 7, then ASSERT().
+ If EndBit is greater than 7, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Address PCI configuration register to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..7.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..7.
+ @param AndData The value to AND with the PCI configuration register.
+ @param OrData The value to OR with the result of the AND operation.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+S3PciSegmentBitFieldAndThenOr8 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT8 AndData,
+ IN UINT8 OrData
+ );
+
+/**
+ Reads a 16-bit PCI configuration register, and saves the value in the S3 script
+ to be replayed on S3 resume.
+
+ Reads and returns the 16-bit PCI configuration register specified by Address.
+ This function must guarantee that all PCI read and write operations are serialized.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
+
+ @return The 16-bit PCI configuration register specified by Address.
+
+**/
+UINT16
+EFIAPI
+S3PciSegmentRead16 (
+ IN UINT64 Address
+ );
+
+/**
+ Writes a 16-bit PCI configuration register, and saves the value in the S3 script to
+ be replayed on S3 resume.
+
+ Writes the 16-bit PCI configuration register specified by Address with the value specified by Value.
+ Value is returned. This function must guarantee that all PCI read and write operations are serialized.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
+ @param Value The value to write.
+
+ @return The parameter of Value.
+
+**/
+UINT16
+EFIAPI
+S3PciSegmentWrite16 (
+ IN UINT64 Address,
+ IN UINT16 Value
+ );
+
+/**
+ Performs a bitwise OR of a 16-bit PCI configuration register with a 16-bit
+ value, and saves the value in the S3 script to be replayed on S3 resume.
+
+ Reads the 16-bit PCI configuration register specified by Address, performs a
+ bitwise OR between the read result and the value specified by OrData, and
+ writes the result to the 16-bit PCI configuration register specified by Address.
+ The value written to the PCI configuration register is returned. This function
+ must guarantee that all PCI read and write operations are serialized.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function and
+ Register.
+ @param OrData The value to OR with the PCI configuration register.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+S3PciSegmentOr16 (
+ IN UINT64 Address,
+ IN UINT16 OrData
+ );
+
+/**
+ Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit value, and
+ saves the value in the S3 script to be replayed on S3 resume.
+
+ Reads the 16-bit PCI configuration register specified by Address,
+ performs a bitwise AND between the read result and the value specified by AndData,
+ and writes the result to the 16-bit PCI configuration register specified by Address.
+ The value written to the PCI configuration register is returned.
+ This function must guarantee that all PCI read and write operations are serialized.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
+ @param AndData The value to AND with the PCI configuration register.
+
+ @return The value written to the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+S3PciSegmentAnd16 (
+ IN UINT64 Address,
+ IN UINT16 AndData
+ );
+
+/**
+ Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit value,
+ followed a bitwise OR with another 16-bit value, and saves the value in the S3 script to
+ be replayed on S3 resume.
+
+ Reads the 16-bit PCI configuration register specified by Address,
+ performs a bitwise AND between the read result and the value specified by AndData,
+ performs a bitwise OR between the result of the AND operation and the value specified by OrData,
+ and writes the result to the 16-bit PCI configuration register specified by Address.
+ The value written to the PCI configuration register is returned.
+ This function must guarantee that all PCI read and write operations are serialized.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
+ @param AndData The value to AND with the PCI configuration register.
+ @param OrData The value to OR with the PCI configuration register.
+
+ @return The value written to the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+S3PciSegmentAndThenOr16 (
+ IN UINT64 Address,
+ IN UINT16 AndData,
+ IN UINT16 OrData
+ );
+
+/**
+ Reads a bit field of a PCI configuration register, and saves the value in the
+ S3 script to be replayed on S3 resume.
+
+ Reads the bit field in a 16-bit PCI configuration register. The bit field is
+ specified by the StartBit and the EndBit. The value of the bit field is
+ returned.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+ If StartBit is greater than 15, then ASSERT().
+ If EndBit is greater than 15, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+
+ @param Address PCI configuration register to read.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..15.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..15.
+
+ @return The value of the bit field read from the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+S3PciSegmentBitFieldRead16 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit
+ );
+
+/**
+ Writes a bit field to a PCI configuration register, and saves the value in
+ the S3 script to be replayed on S3 resume.
+
+ Writes Value to the bit field of the PCI configuration register. The bit
+ field is specified by the StartBit and the EndBit. All other bits in the
+ destination PCI configuration register are preserved. The new value of the
+ 16-bit register is returned.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+ If StartBit is greater than 15, then ASSERT().
+ If EndBit is greater than 15, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Address PCI configuration register to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..15.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..15.
+ @param Value New value of the bit field.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+S3PciSegmentBitFieldWrite16 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT16 Value
+ );
+
+/**
+ Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, writes
+ the result back to the bit field in the 16-bit port, and saves the value in the
+ S3 script to be replayed on S3 resume.
+
+ Reads the 16-bit PCI configuration register specified by Address, performs a
+ bitwise OR between the read result and the value specified by
+ OrData, and writes the result to the 16-bit PCI configuration register
+ specified by Address. The value written to the PCI configuration register is
+ returned. This function must guarantee that all PCI read and write operations
+ are serialized. Extra left bits in OrData are stripped.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+ If StartBit is greater than 15, then ASSERT().
+ If EndBit is greater than 15, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Address PCI configuration register to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..15.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..15.
+ @param OrData The value to OR with the PCI configuration register.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+S3PciSegmentBitFieldOr16 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT16 OrData
+ );
+
+/**
+ Reads a bit field in a 16-bit PCI configuration register, performs a bitwise
+ AND, writes the result back to the bit field in the 16-bit register, and
+ saves the value in the S3 script to be replayed on S3 resume.
+
+ Reads the 16-bit PCI configuration register specified by Address, performs a
+ bitwise AND between the read result and the value specified by AndData, and
+ writes the result to the 16-bit PCI configuration register specified by
+ Address. The value written to the PCI configuration register is returned.
+ This function must guarantee that all PCI read and write operations are
+ serialized. Extra left bits in AndData are stripped.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+ If StartBit is greater than 15, then ASSERT().
+ If EndBit is greater than 15, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..15.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..15.
+ @param AndData The value to AND with the PCI configuration register.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+S3PciSegmentBitFieldAnd16 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT16 AndData
+ );
+
+/**
+ Reads a bit field in a 16-bit port, performs a bitwise AND followed by a
+ bitwise OR, writes the result back to the bit field in the 16-bit port,
+ and saves the value in the S3 script to be replayed on S3 resume.
+
+ Reads the 16-bit PCI configuration register specified by Address, performs a
+ bitwise AND followed by a bitwise OR between the read result and
+ the value specified by AndData, and writes the result to the 16-bit PCI
+ configuration register specified by Address. The value written to the PCI
+ configuration register is returned. This function must guarantee that all PCI
+ read and write operations are serialized. Extra left bits in both AndData and
+ OrData are stripped.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If StartBit is greater than 15, then ASSERT().
+ If EndBit is greater than 15, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Address PCI configuration register to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..15.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..15.
+ @param AndData The value to AND with the PCI configuration register.
+ @param OrData The value to OR with the result of the AND operation.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+S3PciSegmentBitFieldAndThenOr16 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT16 AndData,
+ IN UINT16 OrData
+ );
+
+/**
+ Reads a 32-bit PCI configuration register, and saves the value in the S3 script
+ to be replayed on S3 resume.
+
+ Reads and returns the 32-bit PCI configuration register specified by Address.
+ This function must guarantee that all PCI read and write operations are serialized.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
+
+ @return The 32-bit PCI configuration register specified by Address.
+
+**/
+UINT32
+EFIAPI
+S3PciSegmentRead32 (
+ IN UINT64 Address
+ );
+
+/**
+ Writes a 32-bit PCI configuration register, and saves the value in the S3 script to
+ be replayed on S3 resume.
+
+ Writes the 32-bit PCI configuration register specified by Address with the value specified by Value.
+ Value is returned. This function must guarantee that all PCI read and write operations are serialized.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
+ @param Value The value to write.
+
+ @return The parameter of Value.
+
+**/
+UINT32
+EFIAPI
+S3PciSegmentWrite32 (
+ IN UINT64 Address,
+ IN UINT32 Value
+ );
+
+/**
+ Performs a bitwise OR of a 32-bit PCI configuration register with a 32-bit
+ value, and saves the value in the S3 script to be replayed on S3 resume.
+
+ Reads the 32-bit PCI configuration register specified by Address, performs a
+ bitwise OR between the read result and the value specified by OrData, and
+ writes the result to the 32-bit PCI configuration register specified by Address.
+ The value written to the PCI configuration register is returned. This function
+ must guarantee that all PCI read and write operations are serialized.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and
+ Register.
+ @param OrData The value to OR with the PCI configuration register.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+S3PciSegmentOr32 (
+ IN UINT64 Address,
+ IN UINT32 OrData
+ );
+
+/**
+ Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value, and
+ saves the value in the S3 script to be replayed on S3 resume.
+
+ Reads the 32-bit PCI configuration register specified by Address,
+ performs a bitwise AND between the read result and the value specified by AndData,
+ and writes the result to the 32-bit PCI configuration register specified by Address.
+ The value written to the PCI configuration register is returned.
+ This function must guarantee that all PCI read and write operations are serialized.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
+ @param AndData The value to AND with the PCI configuration register.
+
+ @return The value written to the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+S3PciSegmentAnd32 (
+ IN UINT64 Address,
+ IN UINT32 AndData
+ );
+
+/**
+ Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value,
+ followed a bitwise OR with another 32-bit value, and saves the value in the S3 script to
+ be replayed on S3 resume.
+
+ Reads the 32-bit PCI configuration register specified by Address,
+ performs a bitwise AND between the read result and the value specified by AndData,
+ performs a bitwise OR between the result of the AND operation and the value specified by OrData,
+ and writes the result to the 32-bit PCI configuration register specified by Address.
+ The value written to the PCI configuration register is returned.
+ This function must guarantee that all PCI read and write operations are serialized.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
+ @param AndData The value to AND with the PCI configuration register.
+ @param OrData The value to OR with the PCI configuration register.
+
+ @return The value written to the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+S3PciSegmentAndThenOr32 (
+ IN UINT64 Address,
+ IN UINT32 AndData,
+ IN UINT32 OrData
+ );
+
+/**
+ Reads a bit field of a PCI configuration register, and saves the value in the
+ S3 script to be replayed on S3 resume.
+
+ Reads the bit field in a 32-bit PCI configuration register. The bit field is
+ specified by the StartBit and the EndBit. The value of the bit field is
+ returned.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+ If StartBit is greater than 31, then ASSERT().
+ If EndBit is greater than 31, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+
+ @param Address PCI configuration register to read.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..31.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..31.
+
+ @return The value of the bit field read from the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+S3PciSegmentBitFieldRead32 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit
+ );
+
+/**
+ Writes a bit field to a PCI configuration register, and saves the value in
+ the S3 script to be replayed on S3 resume.
+
+ Writes Value to the bit field of the PCI configuration register. The bit
+ field is specified by the StartBit and the EndBit. All other bits in the
+ destination PCI configuration register are preserved. The new value of the
+ 32-bit register is returned.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+ If StartBit is greater than 31, then ASSERT().
+ If EndBit is greater than 31, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Address PCI configuration register to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..31.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..31.
+ @param Value New value of the bit field.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+S3PciSegmentBitFieldWrite32 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 Value
+ );
+
+/**
+ Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, writes
+ the result back to the bit field in the 32-bit port, and saves the value in the
+ S3 script to be replayed on S3 resume.
+
+ Reads the 32-bit PCI configuration register specified by Address, performs a
+ bitwise OR between the read result and the value specified by
+ OrData, and writes the result to the 32-bit PCI configuration register
+ specified by Address. The value written to the PCI configuration register is
+ returned. This function must guarantee that all PCI read and write operations
+ are serialized. Extra left bits in OrData are stripped.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+ If StartBit is greater than 31, then ASSERT().
+ If EndBit is greater than 31, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Address PCI configuration register to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..31.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..31.
+ @param OrData The value to OR with the PCI configuration register.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+S3PciSegmentBitFieldOr32 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 OrData
+ );
+
+/**
+ Reads a bit field in a 32-bit PCI configuration register, performs a bitwise
+ AND, and writes the result back to the bit field in the 32-bit register, and
+ saves the value in the S3 script to be replayed on S3 resume.
+
+ Reads the 32-bit PCI configuration register specified by Address, performs a
+ bitwise AND between the read result and the value specified by AndData, and
+ writes the result to the 32-bit PCI configuration register specified by
+ Address. The value written to the PCI configuration register is returned.
+ This function must guarantee that all PCI read and write operations are
+ serialized. Extra left bits in AndData are stripped.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+ If StartBit is greater than 31, then ASSERT().
+ If EndBit is greater than 31, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..31.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..31.
+ @param AndData The value to AND with the PCI configuration register.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+S3PciSegmentBitFieldAnd32 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 AndData
+ );
+
+/**
+ Reads a bit field in a 32-bit port, performs a bitwise AND followed by a
+ bitwise OR, writes the result back to the bit field in the 32-bit port,
+ and saves the value in the S3 script to be replayed on S3 resume.
+
+ Reads the 32-bit PCI configuration register specified by Address, performs a
+ bitwise AND followed by a bitwise OR between the read result and
+ the value specified by AndData, and writes the result to the 32-bit PCI
+ configuration register specified by Address. The value written to the PCI
+ configuration register is returned. This function must guarantee that all PCI
+ read and write operations are serialized. Extra left bits in both AndData and
+ OrData are stripped.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If StartBit is greater than 31, then ASSERT().
+ If EndBit is greater than 31, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Address PCI configuration register to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..31.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..31.
+ @param AndData The value to AND with the PCI configuration register.
+ @param OrData The value to OR with the result of the AND operation.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+S3PciSegmentBitFieldAndThenOr32 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 AndData,
+ IN UINT32 OrData
+ );
+
+/**
+ Reads a range of PCI configuration registers into a caller supplied buffer,
+ and saves the value in the S3 script to be replayed on S3 resume.
+
+ Reads the range of PCI configuration registers specified by StartAddress and
+ Size into the buffer specified by Buffer. This function only allows the PCI
+ configuration registers from a single PCI function to be read. Size is
+ returned. When possible 32-bit PCI configuration read cycles are used to read
+ from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit
+ and 16-bit PCI configuration read cycles may be used at the beginning and the
+ end of the range.
+
+ If any reserved bits in StartAddress are set, then ASSERT().
+ If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
+ If Size > 0 and Buffer is NULL, then ASSERT().
+
+ @param StartAddress Starting address that encodes the PCI Segment, Bus, Device,
+ Function and Register.
+ @param Size Size in bytes of the transfer.
+ @param Buffer Pointer to a buffer receiving the data read.
+
+ @return Size
+
+**/
+UINTN
+EFIAPI
+S3PciSegmentReadBuffer (
+ IN UINT64 StartAddress,
+ IN UINTN Size,
+ OUT VOID *Buffer
+ );
+
+/**
+ Copies the data in a caller supplied buffer to a specified range of PCI
+ configuration space, and saves the value in the S3 script to be replayed on S3
+ resume.
+
+ Writes the range of PCI configuration registers specified by StartAddress and
+ Size from the buffer specified by Buffer. This function only allows the PCI
+ configuration registers from a single PCI function to be written. Size is
+ returned. When possible 32-bit PCI configuration write cycles are used to
+ write from StartAdress to StartAddress + Size. Due to alignment restrictions,
+ 8-bit and 16-bit PCI configuration write cycles may be used at the beginning
+ and the end of the range.
+
+ If any reserved bits in StartAddress are set, then ASSERT().
+ If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
+ If Size > 0 and Buffer is NULL, then ASSERT().
+
+ @param StartAddress Starting address that encodes the PCI Segment, Bus, Device,
+ Function and Register.
+ @param Size Size in bytes of the transfer.
+ @param Buffer Pointer to a buffer containing the data to write.
+
+ @return The parameter of Size.
+
+**/
+UINTN
+EFIAPI
+S3PciSegmentWriteBuffer (
+ IN UINT64 StartAddress,
+ IN UINTN Size,
+ IN VOID *Buffer
+ );
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/S3SmbusLib.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/S3SmbusLib.h
new file mode 100644
index 0000000000..471725641e
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/S3SmbusLib.h
@@ -0,0 +1,448 @@
+/** @file
+ Smbus Library Services that conduct SMBus transactions and enable the operatation
+ to be replayed during an S3 resume. This library class maps directly on top
+ of the SmbusLib class.
+
+ Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __S3_SMBUS_LIB_H__
+#define __S3_SMBUS_LIB_H__
+
+/**
+ Executes an SMBUS quick read command, and saves the value in the S3 script to be replayed
+ on S3 resume.
+
+ Executes an SMBUS quick read command on the SMBUS device specified by SmBusAddress.
+ Only the SMBUS slave address field of SmBusAddress is required.
+ If Status is not NULL, then the status of the executed command is returned in Status.
+ If PEC is set in SmBusAddress, then ASSERT().
+ If Command in SmBusAddress is not zero, then ASSERT().
+ If Length in SmBusAddress is not zero, then ASSERT().
+ If any reserved bits of SmBusAddress are set, then ASSERT().
+
+ @param[in] SmBusAddress The address that encodes the SMBUS Slave Address,
+ SMBUS Command, SMBUS Data Length, and PEC.
+ @param[out] Status The return status for the executed command.
+ This is an optional parameter and may be NULL.
+ RETURN_SUCCESS The SMBUS command was executed.
+ RETURN_TIMEOUT A timeout occurred while executing the SMBUS command.
+ RETURN_DEVICE_ERROR The request was not completed because a failure
+ was recorded in the Host Status Register bit. Device errors are a result
+ of a transaction collision, illegal command field, unclaimed cycle
+ (host initiated), or bus error (collision).
+ RETURN_UNSUPPORTED The SMBus operation is not supported.
+
+**/
+VOID
+EFIAPI
+S3SmBusQuickRead (
+ IN UINTN SmBusAddress,
+ OUT RETURN_STATUS *Status OPTIONAL
+ );
+
+/**
+ Executes an SMBUS quick write command, and saves the value in the S3 script to be replayed
+ on S3 resume.
+
+ Executes an SMBUS quick write command on the SMBUS device specified by SmBusAddress.
+ Only the SMBUS slave address field of SmBusAddress is required.
+ If Status is not NULL, then the status of the executed command is returned in Status.
+ If PEC is set in SmBusAddress, then ASSERT().
+ If Command in SmBusAddress is not zero, then ASSERT().
+ If Length in SmBusAddress is not zero, then ASSERT().
+ If any reserved bits of SmBusAddress are set, then ASSERT().
+
+ @param[in] SmBusAddress The address that encodes the SMBUS Slave Address,
+ SMBUS Command, SMBUS Data Length, and PEC.
+ @param[out] Status The return status for the executed command.
+ This is an optional parameter and may be NULL.
+ RETURN_SUCCESS The SMBUS command was executed.
+ RETURN_TIMEOUT A timeout occurred while executing the SMBUS command.
+ RETURN_DEVICE_ERROR The request was not completed because a failure
+ was recorded in the Host Status Register bit. Device errors are a result
+ of a transaction collision, illegal command field, unclaimed cycle
+ (host initiated), or bus error (collision).
+ RETURN_UNSUPPORTED The SMBus operation is not supported.
+
+**/
+VOID
+EFIAPI
+S3SmBusQuickWrite (
+ IN UINTN SmBusAddress,
+ OUT RETURN_STATUS *Status OPTIONAL
+ );
+
+/**
+ Executes an SMBUS receive byte command, and saves the value in the S3 script to be replayed
+ on S3 resume.
+
+ Executes an SMBUS receive byte command on the SMBUS device specified by SmBusAddress.
+ Only the SMBUS slave address field of SmBusAddress is required.
+ The byte received from the SMBUS is returned.
+ If Status is not NULL, then the status of the executed command is returned in Status.
+ If Command in SmBusAddress is not zero, then ASSERT().
+ If Length in SmBusAddress is not zero, then ASSERT().
+ If any reserved bits of SmBusAddress are set, then ASSERT().
+
+ @param[in] SmBusAddress The address that encodes the SMBUS Slave Address,
+ SMBUS Command, SMBUS Data Length, and PEC.
+ @param[out] Status The return status for the executed command.
+ This is an optional parameter and may be NULL.
+ RETURN_SUCCESS The SMBUS command was executed.
+ RETURN_TIMEOUT A timeout occurred while executing the SMBUS command.
+ RETURN_DEVICE_ERROR The request was not completed because a failure
+ was recorded in the Host Status Register bit. Device errors are a result
+ of a transaction collision, illegal command field, unclaimed cycle
+ (host initiated), or bus error (collision).
+ RETURN_CRC_ERROR The checksum is not correct (PEC is incorrect).
+ RETURN_UNSUPPORTED The SMBus operation is not supported.
+
+ @return The byte received from the SMBUS.
+
+**/
+UINT8
+EFIAPI
+S3SmBusReceiveByte (
+ IN UINTN SmBusAddress,
+ OUT RETURN_STATUS *Status OPTIONAL
+ );
+
+/**
+ Executes an SMBUS send byte command, and saves the value in the S3 script to be replayed
+ on S3 resume.
+
+ Executes an SMBUS send byte command on the SMBUS device specified by SmBusAddress.
+ The byte specified by Value is sent.
+ Only the SMBUS slave address field of SmBusAddress is required. Value is returned.
+ If Status is not NULL, then the status of the executed command is returned in Status.
+ If Command in SmBusAddress is not zero, then ASSERT().
+ If Length in SmBusAddress is not zero, then ASSERT().
+ If any reserved bits of SmBusAddress are set, then ASSERT().
+
+ @param[in] SmBusAddress The address that encodes the SMBUS Slave Address,
+ SMBUS Command, SMBUS Data Length, and PEC.
+ @param[in] Value The 8-bit value to send.
+ @param[out] Status The return status for the executed command.
+ This is an optional parameter and may be NULL.
+ RETURN_SUCCESS The SMBUS command was executed.
+ RETURN_TIMEOUT A timeout occurred while executing the SMBUS command.
+ RETURN_DEVICE_ERROR The request was not completed because a failure
+ was recorded in the Host Status Register bit. Device errors are a result
+ of a transaction collision, illegal command field, unclaimed cycle
+ (host initiated), or bus errors (collisions).
+ RETURN_CRC_ERROR The checksum is not correct (PEC is incorrect).
+ RETURN_UNSUPPORTED The SMBus operation is not supported.
+
+ @return The parameter of Value.
+
+**/
+UINT8
+EFIAPI
+S3SmBusSendByte (
+ IN UINTN SmBusAddress,
+ IN UINT8 Value,
+ OUT RETURN_STATUS *Status OPTIONAL
+ );
+
+/**
+ Executes an SMBUS read data byte command, and saves the value in the S3 script to be replayed
+ on S3 resume.
+
+ Executes an SMBUS read data byte command on the SMBUS device specified by SmBusAddress.
+ Only the SMBUS slave address and SMBUS command fields of SmBusAddress are required.
+ The 8-bit value read from the SMBUS is returned.
+ If Status is not NULL, then the status of the executed command is returned in Status.
+ If Length in SmBusAddress is not zero, then ASSERT().
+ If any reserved bits of SmBusAddress are set, then ASSERT().
+
+ @param[in] SmBusAddress The address that encodes the SMBUS Slave Address,
+ SMBUS Command, SMBUS Data Length, and PEC.
+ @param[out] Status The return status for the executed command.
+ This is an optional parameter and may be NULL.
+ RETURN_SUCCESS The SMBUS command was executed.
+ RETURN_TIMEOUT A timeout occurred while executing the SMBUS command.
+ RETURN_DEVICE_ERROR The request was not completed because a failure
+ was recorded in the Host Status Register bit. Device errors are a result
+ of a transaction collision, illegal command field, unclaimed cycle
+ (host initiated), or bus error (collision).
+ RETURN_CRC_ERROR The checksum is not correct (PEC is incorrect).
+ RETURN_UNSUPPORTED The SMBus operation is not supported.
+
+ @return The byte read from the SMBUS.
+
+**/
+UINT8
+EFIAPI
+S3SmBusReadDataByte (
+ IN UINTN SmBusAddress,
+ OUT RETURN_STATUS *Status OPTIONAL
+ );
+
+/**
+ Executes an SMBUS write data byte command, and saves the value in the S3 script to be replayed
+ on S3 resume.
+
+ Executes an SMBUS write data byte command on the SMBUS device specified by SmBusAddress.
+ The 8-bit value specified by Value is written.
+ Only the SMBUS slave address and SMBUS command fields of SmBusAddress are required.
+ Value is returned.
+ If Status is not NULL, then the status of the executed command is returned in Status.
+ If Length in SmBusAddress is not zero, then ASSERT().
+ If any reserved bits of SmBusAddress are set, then ASSERT().
+
+ @param[in] SmBusAddress The address that encodes the SMBUS Slave Address,
+ SMBUS Command, SMBUS Data Length, and PEC.
+ @param[in] Value The 8-bit value to write.
+ @param[out] Status The return status for the executed command.
+ This is an optional parameter and may be NULL.
+ RETURN_SUCCESS The SMBUS command was executed.
+ RETURN_TIMEOUT A timeout occurred while executing the SMBUS command.
+ RETURN_DEVICE_ERROR The request was not completed because a failure
+ was recorded in the Host Status Register bit. Device errors are a result
+ of a transaction collision, illegal command field, unclaimed cycle
+ (host initiated), or bus error (collision).
+ RETURN_CRC_ERROR The checksum is not correct (PEC is incorrect).
+ RETURN_UNSUPPORTED The SMBus operation is not supported.
+
+ @return The parameter of Value.
+
+**/
+UINT8
+EFIAPI
+S3SmBusWriteDataByte (
+ IN UINTN SmBusAddress,
+ IN UINT8 Value,
+ OUT RETURN_STATUS *Status OPTIONAL
+ );
+
+/**
+ Executes an SMBUS read data word command, and saves the value in the S3 script to be replayed
+ on S3 resume.
+
+ Executes an SMBUS read data word command on the SMBUS device specified by SmBusAddress.
+ Only the SMBUS slave address and SMBUS command fields of SmBusAddress are required.
+ The 16-bit value read from the SMBUS is returned.
+ If Status is not NULL, then the status of the executed command is returned in Status.
+ If Length in SmBusAddress is not zero, then ASSERT().
+ If any reserved bits of SmBusAddress are set, then ASSERT().
+
+ @param[in] SmBusAddress The address that encodes the SMBUS Slave Address,
+ SMBUS Command, SMBUS Data Length, and PEC.
+ @param[out] Status The return status for the executed command.
+ This is an optional parameter and may be NULL.
+ RETURN_SUCCESS The SMBUS command was executed.
+ RETURN_TIMEOUT A timeout occurred while executing the SMBUS command.
+ RETURN_DEVICE_ERROR The request was not completed because a failure
+ was recorded in the Host Status Register bit. Device errors are a result
+ of a transaction collision, illegal command field, unclaimed cycle
+ (host initiated), or bus error (collision).
+ RETURN_CRC_ERROR The checksum is not correct (PEC is incorrect).
+ RETURN_UNSUPPORTED The SMBus operation is not supported.
+
+ @return The byte read from the SMBUS.
+
+**/
+UINT16
+EFIAPI
+S3SmBusReadDataWord (
+ IN UINTN SmBusAddress,
+ OUT RETURN_STATUS *Status OPTIONAL
+ );
+
+/**
+ Executes an SMBUS write data word command, and saves the value in the S3 script to be replayed
+ on S3 resume.
+
+ Executes an SMBUS write data word command on the SMBUS device specified by SmBusAddress.
+ The 16-bit value specified by Value is written.
+ Only the SMBUS slave address and SMBUS command fields of SmBusAddress are required.
+ Value is returned.
+ If Status is not NULL, then the status of the executed command is returned in Status.
+ If Length in SmBusAddress is not zero, then ASSERT().
+ If any reserved bits of SmBusAddress are set, then ASSERT().
+
+ @param[in] SmBusAddress The address that encodes the SMBUS Slave Address,
+ SMBUS Command, SMBUS Data Length, and PEC.
+ @param[in] Value The 16-bit value to write.
+ @param[out] Status The return status for the executed command.
+ This is an optional parameter and may be NULL.
+ RETURN_SUCCESS The SMBUS command was executed.
+ RETURN_TIMEOUT A timeout occurred while executing the SMBUS command.
+ RETURN_DEVICE_ERROR The request was not completed because a failure
+ was recorded in the Host Status Register bit. Device errors are a result
+ of a transaction collision, illegal command field, unclaimed cycle
+ (host initiated), or bus error (collision).
+ RETURN_CRC_ERROR The checksum is not correct (PEC is incorrect).
+ RETURN_UNSUPPORTED The SMBus operation is not supported.
+
+ @return The parameter of Value.
+
+**/
+UINT16
+EFIAPI
+S3SmBusWriteDataWord (
+ IN UINTN SmBusAddress,
+ IN UINT16 Value,
+ OUT RETURN_STATUS *Status OPTIONAL
+ );
+
+/**
+ Executes an SMBUS process call command, and saves the value in the S3 script to be replayed
+ on S3 resume.
+
+ Executes an SMBUS process call command on the SMBUS device specified by SmBusAddress.
+ The 16-bit value specified by Value is written.
+ Only the SMBUS slave address and SMBUS command fields of SmBusAddress are required.
+ The 16-bit value returned by the process call command is returned.
+ If Status is not NULL, then the status of the executed command is returned in Status.
+ If Length in SmBusAddress is not zero, then ASSERT().
+ If any reserved bits of SmBusAddress are set, then ASSERT().
+
+ @param[in] SmBusAddress The address that encodes the SMBUS Slave Address,
+ SMBUS Command, SMBUS Data Length, and PEC.
+ @param[in] Value The 16-bit value to write.
+ @param[out] Status The return status for the executed command.
+ This is an optional parameter and may be NULL.
+ RETURN_SUCCESS The SMBUS command was executed.
+ RETURN_TIMEOUT A timeout occurred while executing the SMBUS command.
+ RETURN_DEVICE_ERROR The request was not completed because a failure
+ was recorded in the Host Status Register bit. Device errors are a result
+ of a transaction collision, illegal command field, unclaimed cycle
+ (host initiated), or bus error (collision).
+ RETURN_CRC_ERROR The checksum is not correct (PEC is incorrect).
+ RETURN_UNSUPPORTED The SMBus operation is not supported.
+
+ @return The 16-bit value returned by the process call command.
+
+**/
+UINT16
+EFIAPI
+S3SmBusProcessCall (
+ IN UINTN SmBusAddress,
+ IN UINT16 Value,
+ OUT RETURN_STATUS *Status OPTIONAL
+ );
+
+/**
+ Executes an SMBUS read block command, and saves the value in the S3 script to be replayed
+ on S3 resume.
+
+ Executes an SMBUS read block command on the SMBUS device specified by SmBusAddress.
+ Only the SMBUS slave address and SMBUS command fields of SmBusAddress are required.
+ Bytes are read from the SMBUS and stored in Buffer.
+ The number of bytes read is returned, and will never return a value larger than 32-bytes.
+ If Status is not NULL, then the status of the executed command is returned in Status.
+ It is the caller's responsibility to make sure Buffer is large enough for the total number of bytes read.
+ SMBUS supports a maximum transfer size of 32 bytes, so Buffer does not need to be any larger than 32 bytes.
+ If Length in SmBusAddress is not zero, then ASSERT().
+ If Buffer is NULL, then ASSERT().
+ If any reserved bits of SmBusAddress are set, then ASSERT().
+
+ @param[in] SmBusAddress The address that encodes the SMBUS Slave Address,
+ SMBUS Command, SMBUS Data Length, and PEC.
+ @param[out] Buffer The pointer to the buffer to store the bytes read from the SMBUS.
+ @param[out] Status The return status for the executed command.
+ This is an optional parameter and may be NULL.
+ RETURN_SUCCESS The SMBUS command was executed.
+ RETURN_TIMEOUT A timeout occurred while executing the SMBUS command.
+ RETURN_DEVICE_ERROR The request was not completed because a failure
+ was recorded in the Host Status Register bit. Device errors are a result
+ of a transaction collision, illegal command field, unclaimed cycle
+ (host initiated), or bus error (collision).
+ RETURN_CRC_ERROR The checksum is not correct (PEC is incorrect).
+ RETURN_UNSUPPORTED The SMBus operation is not supported.
+
+ @return The number of bytes read.
+
+**/
+UINTN
+EFIAPI
+S3SmBusReadBlock (
+ IN UINTN SmBusAddress,
+ OUT VOID *Buffer,
+ OUT RETURN_STATUS *Status OPTIONAL
+ );
+
+/**
+ Executes an SMBUS write block command, and saves the value in the S3 script to be replayed
+ on S3 resume.
+
+ Executes an SMBUS write block command on the SMBUS device specified by SmBusAddress.
+ The SMBUS slave address, SMBUS command, and SMBUS length fields of SmBusAddress are required.
+ Bytes are written to the SMBUS from Buffer.
+ The number of bytes written is returned, and will never return a value larger than 32-bytes.
+ If Status is not NULL, then the status of the executed command is returned in Status.
+ If Length in SmBusAddress is zero or greater than 32, then ASSERT().
+ If Buffer is NULL, then ASSERT().
+ If any reserved bits of SmBusAddress are set, then ASSERT().
+
+ @param[in] SmBusAddress The address that encodes the SMBUS Slave Address,
+ SMBUS Command, SMBUS Data Length, and PEC.
+ @param[out] Buffer The pointer to the buffer to store the bytes read from the SMBUS.
+ @param[out] Status The return status for the executed command.
+ This is an optional parameter and may be NULL.
+ RETURN_TIMEOUT A timeout occurred while executing the SMBUS command.
+ RETURN_DEVICE_ERROR The request was not completed because a failure
+ was recorded in the Host Status Register bit. Device errors are a result
+ of a transaction collision, illegal command field, unclaimed cycle
+ (host initiated), or bus error (collision).
+ RETURN_CRC_ERROR The checksum is not correct (PEC is incorrect).
+ RETURN_UNSUPPORTED The SMBus operation is not supported.
+
+ @return The number of bytes written.
+
+**/
+UINTN
+EFIAPI
+S3SmBusWriteBlock (
+ IN UINTN SmBusAddress,
+ OUT VOID *Buffer,
+ OUT RETURN_STATUS *Status OPTIONAL
+ );
+
+/**
+ Executes an SMBUS block process call command, and saves the value in the S3 script to be replayed
+ on S3 resume.
+
+ Executes an SMBUS block process call command on the SMBUS device specified by SmBusAddress.
+ The SMBUS slave address, SMBUS command, and SMBUS length fields of SmBusAddress are required.
+ Bytes are written to the SMBUS from WriteBuffer. Bytes are then read from the SMBUS into ReadBuffer.
+ If Status is not NULL, then the status of the executed command is returned in Status.
+ It is the caller's responsibility to make sure ReadBuffer is large enough for the total number of bytes read.
+ SMBUS supports a maximum transfer size of 32 bytes, so Buffer does not need to be any larger than 32 bytes.
+ If Length in SmBusAddress is zero or greater than 32, then ASSERT().
+ If WriteBuffer is NULL, then ASSERT().
+ If ReadBuffer is NULL, then ASSERT().
+ If any reserved bits of SmBusAddress are set, then ASSERT().
+
+ @param[in] SmBusAddress The address that encodes the SMBUS Slave Address,
+ SMBUS Command, SMBUS Data Length, and PEC.
+ @param[in] WriteBuffer The pointer to the buffer of bytes to write to the SMBUS.
+ @param[out] ReadBuffer The pointer to the buffer of bytes to read from the SMBUS.
+ @param[out] Status The return status for the executed command.
+ This is an optional parameter and may be NULL.
+ RETURN_TIMEOUT A timeout occurred while executing the SMBUS command.
+ RETURN_DEVICE_ERROR The request was not completed because a failure
+ was recorded in the Host Status Register bit. Device errors are a result
+ of a transaction collision, illegal command field, unclaimed cycle
+ (host initiated), or bus error (collision).
+ RETURN_CRC_ERROR The checksum is not correct (PEC is incorrect).
+ RETURN_UNSUPPORTED The SMBus operation is not supported.
+
+ @return The number of bytes written.
+
+**/
+UINTN
+EFIAPI
+S3SmBusBlockProcessCall (
+ IN UINTN SmBusAddress,
+ IN VOID *WriteBuffer,
+ OUT VOID *ReadBuffer,
+ OUT RETURN_STATUS *Status OPTIONAL
+ );
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/S3StallLib.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/S3StallLib.h
new file mode 100644
index 0000000000..aab86679dc
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/S3StallLib.h
@@ -0,0 +1,32 @@
+/** @file
+ Stall Services that perform stalls and also enable the Stall operatation
+ to be replayed during an S3 resume. This library class maps directly on top
+ of the Timer class.
+
+ Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __S3_STALL_LIB_H__
+#define __S3_STALL_LIB_H__
+
+/**
+ Stalls the CPU for at least the given number of microseconds and saves
+ the value in the S3 script to be replayed on S3 resume.
+
+ Stalls the CPU for the number of microseconds specified by MicroSeconds.
+
+ @param[in] MicroSeconds The minimum number of microseconds to delay.
+
+ @return MicroSeconds.
+
+**/
+UINTN
+EFIAPI
+S3Stall (
+ IN UINTN MicroSeconds
+ );
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/SafeIntLib.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/SafeIntLib.h
new file mode 100644
index 0000000000..bbeac582f7
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/SafeIntLib.h
@@ -0,0 +1,3013 @@
+/** @file
+ This library provides helper functions to prevent integer overflow during
+ type conversion, addition, subtraction, and multiplication.
+
+ Copyright (c) 2017, Microsoft Corporation
+
+ All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __INT_SAFE_LIB_H__
+#define __INT_SAFE_LIB_H__
+
+//
+// It is common for -1 to be used as an error value
+//
+#define INT8_ERROR ((INT8) -1)
+#define UINT8_ERROR MAX_UINT8
+#define CHAR8_ERROR ((CHAR8)(MAX_INT8))
+#define INT16_ERROR ((INT16) -1)
+#define UINT16_ERROR MAX_UINT16
+#define CHAR16_ERROR MAX_UINT16
+#define INT32_ERROR ((INT32) -1)
+#define UINT32_ERROR MAX_UINT32
+#define INT64_ERROR ((INT64) -1)
+#define UINT64_ERROR MAX_UINT64
+#define INTN_ERROR ((INTN) -1)
+#define UINTN_ERROR MAX_UINTN
+
+//
+// CHAR16 is defined to be the same as UINT16, so for CHAR16
+// operations redirect to the UINT16 ones:
+//
+#define SafeInt8ToChar16 SafeInt8ToUint16
+#define SafeInt16ToChar16 SafeInt16ToUint16
+#define SafeInt32ToChar16 SafeInt32ToUint16
+#define SafeUint32ToChar16 SafeUint32ToUint16
+#define SafeInt64ToChar16 SafeInt64ToUint16
+#define SafeUint64ToChar16 SafeUint64ToUint16
+#define SafeIntnToChar16 SafeIntnToUint16
+#define SafeUintnToChar16 SafeUintnToUint16
+
+#define SafeChar16ToInt8 SafeUint16ToInt8
+#define SafeChar16ToUint8 SafeUint16ToUint8
+#define SafeChar16ToChar8 SafeUint16ToChar8
+#define SafeChar16ToInt16 SafeUint16ToInt16
+
+#define SafeChar16Mult SafeUint16Mult
+#define SafeChar16Sub SafeUint16Sub
+#define SafeChar16Add SafeUint16Add
+
+//
+// Conversion functions
+//
+// There are three reasons for having conversion functions:
+//
+// 1. We are converting from a signed type to an unsigned type of the same
+// size, or vice-versa.
+//
+// 2. We are converting to a smaller type, and we could therefore possibly
+// overflow.
+//
+// 3. We are converting to a bigger type, and we are signed and the type we are
+// converting to is unsigned.
+//
+
+/**
+ INT8 -> UINT8 conversion
+
+ Converts the value specified by Operand to a value specified by Result type
+ and stores the converted value into the caller allocated output buffer
+ specified by Result. The caller must pass in a Result buffer that is at
+ least as large as the Result type.
+
+ If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+ If the conversion results in an overflow or an underflow condition, then
+ Result is set to UINT8_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+ @param[in] Operand Operand to be converted to new type
+ @param[out] Result Pointer to the result of conversion
+
+ @retval RETURN_SUCCESS Successful conversion
+ @retval RETURN_BUFFER_TOO_SMALL Overflow
+ @retval RETURN_INVALID_PARAMETER Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeInt8ToUint8 (
+ IN INT8 Operand,
+ OUT UINT8 *Result
+ );
+
+/**
+ INT8 -> CHAR8 conversion
+
+ Converts the value specified by Operand to a value specified by Result type
+ and stores the converted value into the caller allocated output buffer
+ specified by Result. The caller must pass in a Result buffer that is at
+ least as large as the Result type.
+
+ If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+ If the conversion results in an overflow or an underflow condition, then
+ Result is set to CHAR8_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+ @param[in] Operand Operand to be converted to new type
+ @param[out] Result Pointer to the result of conversion
+
+ @retval RETURN_SUCCESS Successful conversion
+ @retval RETURN_BUFFER_TOO_SMALL Overflow
+ @retval RETURN_INVALID_PARAMETER Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeInt8ToChar8 (
+ IN INT8 Operand,
+ OUT CHAR8 *Result
+ );
+
+/**
+ INT8 -> UINT16 conversion
+
+ Converts the value specified by Operand to a value specified by Result type
+ and stores the converted value into the caller allocated output buffer
+ specified by Result. The caller must pass in a Result buffer that is at
+ least as large as the Result type.
+
+ If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+ If the conversion results in an overflow or an underflow condition, then
+ Result is set to UINT16_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+ @param[in] Operand Operand to be converted to new type
+ @param[out] Result Pointer to the result of conversion
+
+ @retval RETURN_SUCCESS Successful conversion
+ @retval RETURN_BUFFER_TOO_SMALL Overflow
+ @retval RETURN_INVALID_PARAMETER Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeInt8ToUint16 (
+ IN INT8 Operand,
+ OUT UINT16 *Result
+ );
+
+/**
+ INT8 -> UINT32 conversion
+
+ Converts the value specified by Operand to a value specified by Result type
+ and stores the converted value into the caller allocated output buffer
+ specified by Result. The caller must pass in a Result buffer that is at
+ least as large as the Result type.
+
+ If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+ If the conversion results in an overflow or an underflow condition, then
+ Result is set to UINT32_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+ @param[in] Operand Operand to be converted to new type
+ @param[out] Result Pointer to the result of conversion
+
+ @retval RETURN_SUCCESS Successful conversion
+ @retval RETURN_BUFFER_TOO_SMALL Overflow
+ @retval RETURN_INVALID_PARAMETER Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeInt8ToUint32 (
+ IN INT8 Operand,
+ OUT UINT32 *Result
+ );
+
+/**
+ INT8 -> UINTN conversion
+
+ Converts the value specified by Operand to a value specified by Result type
+ and stores the converted value into the caller allocated output buffer
+ specified by Result. The caller must pass in a Result buffer that is at
+ least as large as the Result type.
+
+ If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+ If the conversion results in an overflow or an underflow condition, then
+ Result is set to UINTN_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+ @param[in] Operand Operand to be converted to new type
+ @param[out] Result Pointer to the result of conversion
+
+ @retval RETURN_SUCCESS Successful conversion
+ @retval RETURN_BUFFER_TOO_SMALL Overflow
+ @retval RETURN_INVALID_PARAMETER Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeInt8ToUintn (
+ IN INT8 Operand,
+ OUT UINTN *Result
+ );
+
+/**
+ INT8 -> UINT64 conversion
+
+ Converts the value specified by Operand to a value specified by Result type
+ and stores the converted value into the caller allocated output buffer
+ specified by Result. The caller must pass in a Result buffer that is at
+ least as large as the Result type.
+
+ If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+ If the conversion results in an overflow or an underflow condition, then
+ Result is set to UINT64_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+ @param[in] Operand Operand to be converted to new type
+ @param[out] Result Pointer to the result of conversion
+
+ @retval RETURN_SUCCESS Successful conversion
+ @retval RETURN_BUFFER_TOO_SMALL Overflow
+ @retval RETURN_INVALID_PARAMETER Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeInt8ToUint64 (
+ IN INT8 Operand,
+ OUT UINT64 *Result
+ );
+
+/**
+ UINT8 -> INT8 conversion
+
+ Converts the value specified by Operand to a value specified by Result type
+ and stores the converted value into the caller allocated output buffer
+ specified by Result. The caller must pass in a Result buffer that is at
+ least as large as the Result type.
+
+ If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+ If the conversion results in an overflow or an underflow condition, then
+ Result is set to INT8_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+ @param[in] Operand Operand to be converted to new type
+ @param[out] Result Pointer to the result of conversion
+
+ @retval RETURN_SUCCESS Successful conversion
+ @retval RETURN_BUFFER_TOO_SMALL Overflow
+ @retval RETURN_INVALID_PARAMETER Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeUint8ToInt8 (
+ IN UINT8 Operand,
+ OUT INT8 *Result
+ );
+
+/**
+ UINT8 -> CHAR8 conversion
+
+ Converts the value specified by Operand to a value specified by Result type
+ and stores the converted value into the caller allocated output buffer
+ specified by Result. The caller must pass in a Result buffer that is at
+ least as large as the Result type.
+
+ If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+ If the conversion results in an overflow or an underflow condition, then
+ Result is set to CHAR8_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+ @param[in] Operand Operand to be converted to new type
+ @param[out] Result Pointer to the result of conversion
+
+ @retval RETURN_SUCCESS Successful conversion
+ @retval RETURN_BUFFER_TOO_SMALL Overflow
+ @retval RETURN_INVALID_PARAMETER Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeUint8ToChar8 (
+ IN UINT8 Operand,
+ OUT CHAR8 *Result
+ );
+
+/**
+ INT16 -> INT8 conversion
+
+ Converts the value specified by Operand to a value specified by Result type
+ and stores the converted value into the caller allocated output buffer
+ specified by Result. The caller must pass in a Result buffer that is at
+ least as large as the Result type.
+
+ If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+ If the conversion results in an overflow or an underflow condition, then
+ Result is set to INT8_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+ @param[in] Operand Operand to be converted to new type
+ @param[out] Result Pointer to the result of conversion
+
+ @retval RETURN_SUCCESS Successful conversion
+ @retval RETURN_BUFFER_TOO_SMALL Overflow
+ @retval RETURN_INVALID_PARAMETER Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeInt16ToInt8 (
+ IN INT16 Operand,
+ OUT INT8 *Result
+ );
+
+/**
+ INT16 -> CHAR8 conversion
+
+ Converts the value specified by Operand to a value specified by Result type
+ and stores the converted value into the caller allocated output buffer
+ specified by Result. The caller must pass in a Result buffer that is at
+ least as large as the Result type.
+
+ If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+ If the conversion results in an overflow or an underflow condition, then
+ Result is set to CHAR8_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+ @param[in] Operand Operand to be converted to new type
+ @param[out] Result Pointer to the result of conversion
+
+ @retval RETURN_SUCCESS Successful conversion
+ @retval RETURN_BUFFER_TOO_SMALL Overflow
+ @retval RETURN_INVALID_PARAMETER Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeInt16ToChar8 (
+ IN INT16 Operand,
+ OUT CHAR8 *Result
+ );
+
+/**
+ INT16 -> UINT8 conversion
+
+ Converts the value specified by Operand to a value specified by Result type
+ and stores the converted value into the caller allocated output buffer
+ specified by Result. The caller must pass in a Result buffer that is at
+ least as large as the Result type.
+
+ If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+ If the conversion results in an overflow or an underflow condition, then
+ Result is set to UINT8_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+ @param[in] Operand Operand to be converted to new type
+ @param[out] Result Pointer to the result of conversion
+
+ @retval RETURN_SUCCESS Successful conversion
+ @retval RETURN_BUFFER_TOO_SMALL Overflow
+ @retval RETURN_INVALID_PARAMETER Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeInt16ToUint8 (
+ IN INT16 Operand,
+ OUT UINT8 *Result
+ );
+
+/**
+ INT16 -> UINT16 conversion
+
+ Converts the value specified by Operand to a value specified by Result type
+ and stores the converted value into the caller allocated output buffer
+ specified by Result. The caller must pass in a Result buffer that is at
+ least as large as the Result type.
+
+ If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+ If the conversion results in an overflow or an underflow condition, then
+ Result is set to UINT16_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+ @param[in] Operand Operand to be converted to new type
+ @param[out] Result Pointer to the result of conversion
+
+ @retval RETURN_SUCCESS Successful conversion
+ @retval RETURN_BUFFER_TOO_SMALL Overflow
+ @retval RETURN_INVALID_PARAMETER Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeInt16ToUint16 (
+ IN INT16 Operand,
+ OUT UINT16 *Result
+ );
+
+/**
+ INT16 -> UINT32 conversion
+
+ Converts the value specified by Operand to a value specified by Result type
+ and stores the converted value into the caller allocated output buffer
+ specified by Result. The caller must pass in a Result buffer that is at
+ least as large as the Result type.
+
+ If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+ If the conversion results in an overflow or an underflow condition, then
+ Result is set to UINT32_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+ @param[in] Operand Operand to be converted to new type
+ @param[out] Result Pointer to the result of conversion
+
+ @retval RETURN_SUCCESS Successful conversion
+ @retval RETURN_BUFFER_TOO_SMALL Overflow
+ @retval RETURN_INVALID_PARAMETER Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeInt16ToUint32 (
+ IN INT16 Operand,
+ OUT UINT32 *Result
+ );
+
+/**
+ INT16 -> UINTN conversion
+
+ Converts the value specified by Operand to a value specified by Result type
+ and stores the converted value into the caller allocated output buffer
+ specified by Result. The caller must pass in a Result buffer that is at
+ least as large as the Result type.
+
+ If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+ If the conversion results in an overflow or an underflow condition, then
+ Result is set to UINTN_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+ @param[in] Operand Operand to be converted to new type
+ @param[out] Result Pointer to the result of conversion
+
+ @retval RETURN_SUCCESS Successful conversion
+ @retval RETURN_BUFFER_TOO_SMALL Overflow
+ @retval RETURN_INVALID_PARAMETER Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeInt16ToUintn (
+ IN INT16 Operand,
+ OUT UINTN *Result
+ );
+
+/**
+ INT16 -> UINT64 conversion
+
+ Converts the value specified by Operand to a value specified by Result type
+ and stores the converted value into the caller allocated output buffer
+ specified by Result. The caller must pass in a Result buffer that is at
+ least as large as the Result type.
+
+ If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+ If the conversion results in an overflow or an underflow condition, then
+ Result is set to UINT64_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+ @param[in] Operand Operand to be converted to new type
+ @param[out] Result Pointer to the result of conversion
+
+ @retval RETURN_SUCCESS Successful conversion
+ @retval RETURN_BUFFER_TOO_SMALL Overflow
+ @retval RETURN_INVALID_PARAMETER Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeInt16ToUint64 (
+ IN INT16 Operand,
+ OUT UINT64 *Result
+ );
+
+/**
+ UINT16 -> INT8 conversion
+
+ Converts the value specified by Operand to a value specified by Result type
+ and stores the converted value into the caller allocated output buffer
+ specified by Result. The caller must pass in a Result buffer that is at
+ least as large as the Result type.
+
+ If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+ If the conversion results in an overflow or an underflow condition, then
+ Result is set to INT8_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+ @param[in] Operand Operand to be converted to new type
+ @param[out] Result Pointer to the result of conversion
+
+ @retval RETURN_SUCCESS Successful conversion
+ @retval RETURN_BUFFER_TOO_SMALL Overflow
+ @retval RETURN_INVALID_PARAMETER Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeUint16ToInt8 (
+ IN UINT16 Operand,
+ OUT INT8 *Result
+ );
+
+/**
+ UINT16 -> CHAR8 conversion
+
+ Converts the value specified by Operand to a value specified by Result type
+ and stores the converted value into the caller allocated output buffer
+ specified by Result. The caller must pass in a Result buffer that is at
+ least as large as the Result type.
+
+ If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+ If the conversion results in an overflow or an underflow condition, then
+ Result is set to CHAR8_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+ @param[in] Operand Operand to be converted to new type
+ @param[out] Result Pointer to the result of conversion
+
+ @retval RETURN_SUCCESS Successful conversion
+ @retval RETURN_BUFFER_TOO_SMALL Overflow
+ @retval RETURN_INVALID_PARAMETER Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeUint16ToChar8 (
+ IN UINT16 Operand,
+ OUT CHAR8 *Result
+ );
+
+/**
+ UINT16 -> UINT8 conversion
+
+ Converts the value specified by Operand to a value specified by Result type
+ and stores the converted value into the caller allocated output buffer
+ specified by Result. The caller must pass in a Result buffer that is at
+ least as large as the Result type.
+
+ If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+ If the conversion results in an overflow or an underflow condition, then
+ Result is set to UINT8_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+ @param[in] Operand Operand to be converted to new type
+ @param[out] Result Pointer to the result of conversion
+
+ @retval RETURN_SUCCESS Successful conversion
+ @retval RETURN_BUFFER_TOO_SMALL Overflow
+ @retval RETURN_INVALID_PARAMETER Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeUint16ToUint8 (
+ IN UINT16 Operand,
+ OUT UINT8 *Result
+ );
+
+/**
+ UINT16 -> INT16 conversion
+
+ Converts the value specified by Operand to a value specified by Result type
+ and stores the converted value into the caller allocated output buffer
+ specified by Result. The caller must pass in a Result buffer that is at
+ least as large as the Result type.
+
+ If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+ If the conversion results in an overflow or an underflow condition, then
+ Result is set to INT16_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+ @param[in] Operand Operand to be converted to new type
+ @param[out] Result Pointer to the result of conversion
+
+ @retval RETURN_SUCCESS Successful conversion
+ @retval RETURN_BUFFER_TOO_SMALL Overflow
+ @retval RETURN_INVALID_PARAMETER Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeUint16ToInt16 (
+ IN UINT16 Operand,
+ OUT INT16 *Result
+ );
+
+/**
+ INT32 -> INT8 conversion
+
+ Converts the value specified by Operand to a value specified by Result type
+ and stores the converted value into the caller allocated output buffer
+ specified by Result. The caller must pass in a Result buffer that is at
+ least as large as the Result type.
+
+ If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+ If the conversion results in an overflow or an underflow condition, then
+ Result is set to INT8_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+ @param[in] Operand Operand to be converted to new type
+ @param[out] Result Pointer to the result of conversion
+
+ @retval RETURN_SUCCESS Successful conversion
+ @retval RETURN_BUFFER_TOO_SMALL Overflow
+ @retval RETURN_INVALID_PARAMETER Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeInt32ToInt8 (
+ IN INT32 Operand,
+ OUT INT8 *Result
+ );
+
+/**
+ INT32 -> CHAR8 conversion
+
+ Converts the value specified by Operand to a value specified by Result type
+ and stores the converted value into the caller allocated output buffer
+ specified by Result. The caller must pass in a Result buffer that is at
+ least as large as the Result type.
+
+ If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+ If the conversion results in an overflow or an underflow condition, then
+ Result is set to CHAR8_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+ @param[in] Operand Operand to be converted to new type
+ @param[out] Result Pointer to the result of conversion
+
+ @retval RETURN_SUCCESS Successful conversion
+ @retval RETURN_BUFFER_TOO_SMALL Overflow
+ @retval RETURN_INVALID_PARAMETER Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeInt32ToChar8 (
+ IN INT32 Operand,
+ OUT CHAR8 *Result
+ );
+
+/**
+ INT32 -> UINT8 conversion
+
+ Converts the value specified by Operand to a value specified by Result type
+ and stores the converted value into the caller allocated output buffer
+ specified by Result. The caller must pass in a Result buffer that is at
+ least as large as the Result type.
+
+ If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+ If the conversion results in an overflow or an underflow condition, then
+ Result is set to UINT8_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+ @param[in] Operand Operand to be converted to new type
+ @param[out] Result Pointer to the result of conversion
+
+ @retval RETURN_SUCCESS Successful conversion
+ @retval RETURN_BUFFER_TOO_SMALL Overflow
+ @retval RETURN_INVALID_PARAMETER Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeInt32ToUint8 (
+ IN INT32 Operand,
+ OUT UINT8 *Result
+ );
+
+/**
+ INT32 -> INT16 conversion
+
+ Converts the value specified by Operand to a value specified by Result type
+ and stores the converted value into the caller allocated output buffer
+ specified by Result. The caller must pass in a Result buffer that is at
+ least as large as the Result type.
+
+ If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+ If the conversion results in an overflow or an underflow condition, then
+ Result is set to INT16_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+ @param[in] Operand Operand to be converted to new type
+ @param[out] Result Pointer to the result of conversion
+
+ @retval RETURN_SUCCESS Successful conversion
+ @retval RETURN_BUFFER_TOO_SMALL Overflow
+ @retval RETURN_INVALID_PARAMETER Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeInt32ToInt16 (
+ IN INT32 Operand,
+ OUT INT16 *Result
+ );
+
+/**
+ INT32 -> UINT16 conversion
+
+ Converts the value specified by Operand to a value specified by Result type
+ and stores the converted value into the caller allocated output buffer
+ specified by Result. The caller must pass in a Result buffer that is at
+ least as large as the Result type.
+
+ If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+ If the conversion results in an overflow or an underflow condition, then
+ Result is set to UINT16_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+ @param[in] Operand Operand to be converted to new type
+ @param[out] Result Pointer to the result of conversion
+
+ @retval RETURN_SUCCESS Successful conversion
+ @retval RETURN_BUFFER_TOO_SMALL Overflow
+ @retval RETURN_INVALID_PARAMETER Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeInt32ToUint16 (
+ IN INT32 Operand,
+ OUT UINT16 *Result
+ );
+
+/**
+ INT32 -> UINT32 conversion
+
+ Converts the value specified by Operand to a value specified by Result type
+ and stores the converted value into the caller allocated output buffer
+ specified by Result. The caller must pass in a Result buffer that is at
+ least as large as the Result type.
+
+ If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+ If the conversion results in an overflow or an underflow condition, then
+ Result is set to UINT32_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+ @param[in] Operand Operand to be converted to new type
+ @param[out] Result Pointer to the result of conversion
+
+ @retval RETURN_SUCCESS Successful conversion
+ @retval RETURN_BUFFER_TOO_SMALL Overflow
+ @retval RETURN_INVALID_PARAMETER Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeInt32ToUint32 (
+ IN INT32 Operand,
+ OUT UINT32 *Result
+ );
+
+/**
+ INT32 -> UINTN conversion
+
+ Converts the value specified by Operand to a value specified by Result type
+ and stores the converted value into the caller allocated output buffer
+ specified by Result. The caller must pass in a Result buffer that is at
+ least as large as the Result type.
+
+ If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+ If the conversion results in an overflow or an underflow condition, then
+ Result is set to UINTN_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+ @param[in] Operand Operand to be converted to new type
+ @param[out] Result Pointer to the result of conversion
+
+ @retval RETURN_SUCCESS Successful conversion
+ @retval RETURN_BUFFER_TOO_SMALL Overflow
+ @retval RETURN_INVALID_PARAMETER Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeInt32ToUintn (
+ IN INT32 Operand,
+ OUT UINTN *Result
+ );
+
+/**
+ INT32 -> UINT64 conversion
+
+ Converts the value specified by Operand to a value specified by Result type
+ and stores the converted value into the caller allocated output buffer
+ specified by Result. The caller must pass in a Result buffer that is at
+ least as large as the Result type.
+
+ If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+ If the conversion results in an overflow or an underflow condition, then
+ Result is set to UINT64_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+ @param[in] Operand Operand to be converted to new type
+ @param[out] Result Pointer to the result of conversion
+
+ @retval RETURN_SUCCESS Successful conversion
+ @retval RETURN_BUFFER_TOO_SMALL Overflow
+ @retval RETURN_INVALID_PARAMETER Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeInt32ToUint64 (
+ IN INT32 Operand,
+ OUT UINT64 *Result
+ );
+
+/**
+ UINT32 -> INT8 conversion
+
+ Converts the value specified by Operand to a value specified by Result type
+ and stores the converted value into the caller allocated output buffer
+ specified by Result. The caller must pass in a Result buffer that is at
+ least as large as the Result type.
+
+ If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+ If the conversion results in an overflow or an underflow condition, then
+ Result is set to INT8_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+ @param[in] Operand Operand to be converted to new type
+ @param[out] Result Pointer to the result of conversion
+
+ @retval RETURN_SUCCESS Successful conversion
+ @retval RETURN_BUFFER_TOO_SMALL Overflow
+ @retval RETURN_INVALID_PARAMETER Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeUint32ToInt8 (
+ IN UINT32 Operand,
+ OUT INT8 *Result
+ );
+
+/**
+ UINT32 -> CHAR8 conversion
+
+ Converts the value specified by Operand to a value specified by Result type
+ and stores the converted value into the caller allocated output buffer
+ specified by Result. The caller must pass in a Result buffer that is at
+ least as large as the Result type.
+
+ If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+ If the conversion results in an overflow or an underflow condition, then
+ Result is set to CHAR8_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+ @param[in] Operand Operand to be converted to new type
+ @param[out] Result Pointer to the result of conversion
+
+ @retval RETURN_SUCCESS Successful conversion
+ @retval RETURN_BUFFER_TOO_SMALL Overflow
+ @retval RETURN_INVALID_PARAMETER Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeUint32ToChar8 (
+ IN UINT32 Operand,
+ OUT CHAR8 *Result
+ );
+
+/**
+ UINT32 -> UINT8 conversion
+
+ Converts the value specified by Operand to a value specified by Result type
+ and stores the converted value into the caller allocated output buffer
+ specified by Result. The caller must pass in a Result buffer that is at
+ least as large as the Result type.
+
+ If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+ If the conversion results in an overflow or an underflow condition, then
+ Result is set to UINT8_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+ @param[in] Operand Operand to be converted to new type
+ @param[out] Result Pointer to the result of conversion
+
+ @retval RETURN_SUCCESS Successful conversion
+ @retval RETURN_BUFFER_TOO_SMALL Overflow
+ @retval RETURN_INVALID_PARAMETER Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeUint32ToUint8 (
+ IN UINT32 Operand,
+ OUT UINT8 *Result
+ );
+
+/**
+ UINT32 -> INT16 conversion
+
+ Converts the value specified by Operand to a value specified by Result type
+ and stores the converted value into the caller allocated output buffer
+ specified by Result. The caller must pass in a Result buffer that is at
+ least as large as the Result type.
+
+ If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+ If the conversion results in an overflow or an underflow condition, then
+ Result is set to INT16_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+ @param[in] Operand Operand to be converted to new type
+ @param[out] Result Pointer to the result of conversion
+
+ @retval RETURN_SUCCESS Successful conversion
+ @retval RETURN_BUFFER_TOO_SMALL Overflow
+ @retval RETURN_INVALID_PARAMETER Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeUint32ToInt16 (
+ IN UINT32 Operand,
+ OUT INT16 *Result
+ );
+
+/**
+ UINT32 -> UINT16 conversion
+
+ Converts the value specified by Operand to a value specified by Result type
+ and stores the converted value into the caller allocated output buffer
+ specified by Result. The caller must pass in a Result buffer that is at
+ least as large as the Result type.
+
+ If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+ If the conversion results in an overflow or an underflow condition, then
+ Result is set to UINT16_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+ @param[in] Operand Operand to be converted to new type
+ @param[out] Result Pointer to the result of conversion
+
+ @retval RETURN_SUCCESS Successful conversion
+ @retval RETURN_BUFFER_TOO_SMALL Overflow
+ @retval RETURN_INVALID_PARAMETER Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeUint32ToUint16 (
+ IN UINT32 Operand,
+ OUT UINT16 *Result
+ );
+
+/**
+ UINT32 -> INT32 conversion
+
+ Converts the value specified by Operand to a value specified by Result type
+ and stores the converted value into the caller allocated output buffer
+ specified by Result. The caller must pass in a Result buffer that is at
+ least as large as the Result type.
+
+ If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+ If the conversion results in an overflow or an underflow condition, then
+ Result is set to INT32_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+ @param[in] Operand Operand to be converted to new type
+ @param[out] Result Pointer to the result of conversion
+
+ @retval RETURN_SUCCESS Successful conversion
+ @retval RETURN_BUFFER_TOO_SMALL Overflow
+ @retval RETURN_INVALID_PARAMETER Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeUint32ToInt32 (
+ IN UINT32 Operand,
+ OUT INT32 *Result
+ );
+
+/**
+ UINT32 -> INTN conversion
+
+ Converts the value specified by Operand to a value specified by Result type
+ and stores the converted value into the caller allocated output buffer
+ specified by Result. The caller must pass in a Result buffer that is at
+ least as large as the Result type.
+
+ If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+ If the conversion results in an overflow or an underflow condition, then
+ Result is set to INTN_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+ @param[in] Operand Operand to be converted to new type
+ @param[out] Result Pointer to the result of conversion
+
+ @retval RETURN_SUCCESS Successful conversion
+ @retval RETURN_BUFFER_TOO_SMALL Overflow
+ @retval RETURN_INVALID_PARAMETER Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeUint32ToIntn (
+ IN UINT32 Operand,
+ OUT INTN *Result
+ );
+
+/**
+ INTN -> INT8 conversion
+
+ Converts the value specified by Operand to a value specified by Result type
+ and stores the converted value into the caller allocated output buffer
+ specified by Result. The caller must pass in a Result buffer that is at
+ least as large as the Result type.
+
+ If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+ If the conversion results in an overflow or an underflow condition, then
+ Result is set to INT8_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+ @param[in] Operand Operand to be converted to new type
+ @param[out] Result Pointer to the result of conversion
+
+ @retval RETURN_SUCCESS Successful conversion
+ @retval RETURN_BUFFER_TOO_SMALL Overflow
+ @retval RETURN_INVALID_PARAMETER Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeIntnToInt8 (
+ IN INTN Operand,
+ OUT INT8 *Result
+ );
+
+/**
+ INTN -> CHAR8 conversion
+
+ Converts the value specified by Operand to a value specified by Result type
+ and stores the converted value into the caller allocated output buffer
+ specified by Result. The caller must pass in a Result buffer that is at
+ least as large as the Result type.
+
+ If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+ If the conversion results in an overflow or an underflow condition, then
+ Result is set to CHAR8_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+ @param[in] Operand Operand to be converted to new type
+ @param[out] Result Pointer to the result of conversion
+
+ @retval RETURN_SUCCESS Successful conversion
+ @retval RETURN_BUFFER_TOO_SMALL Overflow
+ @retval RETURN_INVALID_PARAMETER Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeIntnToChar8 (
+ IN INTN Operand,
+ OUT CHAR8 *Result
+ );
+
+/**
+ INTN -> UINT8 conversion
+
+ Converts the value specified by Operand to a value specified by Result type
+ and stores the converted value into the caller allocated output buffer
+ specified by Result. The caller must pass in a Result buffer that is at
+ least as large as the Result type.
+
+ If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+ If the conversion results in an overflow or an underflow condition, then
+ Result is set to UINT8_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+ @param[in] Operand Operand to be converted to new type
+ @param[out] Result Pointer to the result of conversion
+
+ @retval RETURN_SUCCESS Successful conversion
+ @retval RETURN_BUFFER_TOO_SMALL Overflow
+ @retval RETURN_INVALID_PARAMETER Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeIntnToUint8 (
+ IN INTN Operand,
+ OUT UINT8 *Result
+ );
+
+/**
+ INTN -> INT16 conversion
+
+ Converts the value specified by Operand to a value specified by Result type
+ and stores the converted value into the caller allocated output buffer
+ specified by Result. The caller must pass in a Result buffer that is at
+ least as large as the Result type.
+
+ If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+ If the conversion results in an overflow or an underflow condition, then
+ Result is set to INT16_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+ @param[in] Operand Operand to be converted to new type
+ @param[out] Result Pointer to the result of conversion
+
+ @retval RETURN_SUCCESS Successful conversion
+ @retval RETURN_BUFFER_TOO_SMALL Overflow
+ @retval RETURN_INVALID_PARAMETER Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeIntnToInt16 (
+ IN INTN Operand,
+ OUT INT16 *Result
+ );
+
+/**
+ INTN -> UINT16 conversion
+
+ Converts the value specified by Operand to a value specified by Result type
+ and stores the converted value into the caller allocated output buffer
+ specified by Result. The caller must pass in a Result buffer that is at
+ least as large as the Result type.
+
+ If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+ If the conversion results in an overflow or an underflow condition, then
+ Result is set to UINT16_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+ @param[in] Operand Operand to be converted to new type
+ @param[out] Result Pointer to the result of conversion
+
+ @retval RETURN_SUCCESS Successful conversion
+ @retval RETURN_BUFFER_TOO_SMALL Overflow
+ @retval RETURN_INVALID_PARAMETER Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeIntnToUint16 (
+ IN INTN Operand,
+ OUT UINT16 *Result
+ );
+
+/**
+ INTN -> INT32 conversion
+
+ Converts the value specified by Operand to a value specified by Result type
+ and stores the converted value into the caller allocated output buffer
+ specified by Result. The caller must pass in a Result buffer that is at
+ least as large as the Result type.
+
+ If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+ If the conversion results in an overflow or an underflow condition, then
+ Result is set to INT32_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+ @param[in] Operand Operand to be converted to new type
+ @param[out] Result Pointer to the result of conversion
+
+ @retval RETURN_SUCCESS Successful conversion
+ @retval RETURN_BUFFER_TOO_SMALL Overflow
+ @retval RETURN_INVALID_PARAMETER Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeIntnToInt32 (
+ IN INTN Operand,
+ OUT INT32 *Result
+ );
+
+/**
+ INTN -> UINT32 conversion
+
+ Converts the value specified by Operand to a value specified by Result type
+ and stores the converted value into the caller allocated output buffer
+ specified by Result. The caller must pass in a Result buffer that is at
+ least as large as the Result type.
+
+ If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+ If the conversion results in an overflow or an underflow condition, then
+ Result is set to UINT32_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+ @param[in] Operand Operand to be converted to new type
+ @param[out] Result Pointer to the result of conversion
+
+ @retval RETURN_SUCCESS Successful conversion
+ @retval RETURN_BUFFER_TOO_SMALL Overflow
+ @retval RETURN_INVALID_PARAMETER Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeIntnToUint32 (
+ IN INTN Operand,
+ OUT UINT32 *Result
+ );
+
+/**
+ INTN -> UINTN conversion
+
+ Converts the value specified by Operand to a value specified by Result type
+ and stores the converted value into the caller allocated output buffer
+ specified by Result. The caller must pass in a Result buffer that is at
+ least as large as the Result type.
+
+ If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+ If the conversion results in an overflow or an underflow condition, then
+ Result is set to UINTN_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+ @param[in] Operand Operand to be converted to new type
+ @param[out] Result Pointer to the result of conversion
+
+ @retval RETURN_SUCCESS Successful conversion
+ @retval RETURN_BUFFER_TOO_SMALL Overflow
+ @retval RETURN_INVALID_PARAMETER Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeIntnToUintn (
+ IN INTN Operand,
+ OUT UINTN *Result
+ );
+
+/**
+ INTN -> UINT64 conversion
+
+ Converts the value specified by Operand to a value specified by Result type
+ and stores the converted value into the caller allocated output buffer
+ specified by Result. The caller must pass in a Result buffer that is at
+ least as large as the Result type.
+
+ If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+ If the conversion results in an overflow or an underflow condition, then
+ Result is set to UINT64_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+ @param[in] Operand Operand to be converted to new type
+ @param[out] Result Pointer to the result of conversion
+
+ @retval RETURN_SUCCESS Successful conversion
+ @retval RETURN_BUFFER_TOO_SMALL Overflow
+ @retval RETURN_INVALID_PARAMETER Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeIntnToUint64 (
+ IN INTN Operand,
+ OUT UINT64 *Result
+ );
+
+/**
+ UINTN -> INT8 conversion
+
+ Converts the value specified by Operand to a value specified by Result type
+ and stores the converted value into the caller allocated output buffer
+ specified by Result. The caller must pass in a Result buffer that is at
+ least as large as the Result type.
+
+ If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+ If the conversion results in an overflow or an underflow condition, then
+ Result is set to INT8_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+ @param[in] Operand Operand to be converted to new type
+ @param[out] Result Pointer to the result of conversion
+
+ @retval RETURN_SUCCESS Successful conversion
+ @retval RETURN_BUFFER_TOO_SMALL Overflow
+ @retval RETURN_INVALID_PARAMETER Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeUintnToInt8 (
+ IN UINTN Operand,
+ OUT INT8 *Result
+ );
+
+/**
+ UINTN -> CHAR8 conversion
+
+ Converts the value specified by Operand to a value specified by Result type
+ and stores the converted value into the caller allocated output buffer
+ specified by Result. The caller must pass in a Result buffer that is at
+ least as large as the Result type.
+
+ If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+ If the conversion results in an overflow or an underflow condition, then
+ Result is set to CHAR8_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+ @param[in] Operand Operand to be converted to new type
+ @param[out] Result Pointer to the result of conversion
+
+ @retval RETURN_SUCCESS Successful conversion
+ @retval RETURN_BUFFER_TOO_SMALL Overflow
+ @retval RETURN_INVALID_PARAMETER Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeUintnToChar8 (
+ IN UINTN Operand,
+ OUT CHAR8 *Result
+ );
+
+/**
+ UINTN -> UINT8 conversion
+
+ Converts the value specified by Operand to a value specified by Result type
+ and stores the converted value into the caller allocated output buffer
+ specified by Result. The caller must pass in a Result buffer that is at
+ least as large as the Result type.
+
+ If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+ If the conversion results in an overflow or an underflow condition, then
+ Result is set to UINT8_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+ @param[in] Operand Operand to be converted to new type
+ @param[out] Result Pointer to the result of conversion
+
+ @retval RETURN_SUCCESS Successful conversion
+ @retval RETURN_BUFFER_TOO_SMALL Overflow
+ @retval RETURN_INVALID_PARAMETER Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeUintnToUint8 (
+ IN UINTN Operand,
+ OUT UINT8 *Result
+ );
+
+/**
+ UINTN -> INT16 conversion
+
+ Converts the value specified by Operand to a value specified by Result type
+ and stores the converted value into the caller allocated output buffer
+ specified by Result. The caller must pass in a Result buffer that is at
+ least as large as the Result type.
+
+ If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+ If the conversion results in an overflow or an underflow condition, then
+ Result is set to INT16_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+ @param[in] Operand Operand to be converted to new type
+ @param[out] Result Pointer to the result of conversion
+
+ @retval RETURN_SUCCESS Successful conversion
+ @retval RETURN_BUFFER_TOO_SMALL Overflow
+ @retval RETURN_INVALID_PARAMETER Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeUintnToInt16 (
+ IN UINTN Operand,
+ OUT INT16 *Result
+ );
+
+/**
+ UINTN -> UINT16 conversion
+
+ Converts the value specified by Operand to a value specified by Result type
+ and stores the converted value into the caller allocated output buffer
+ specified by Result. The caller must pass in a Result buffer that is at
+ least as large as the Result type.
+
+ If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+ If the conversion results in an overflow or an underflow condition, then
+ Result is set to UINT16_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+ @param[in] Operand Operand to be converted to new type
+ @param[out] Result Pointer to the result of conversion
+
+ @retval RETURN_SUCCESS Successful conversion
+ @retval RETURN_BUFFER_TOO_SMALL Overflow
+ @retval RETURN_INVALID_PARAMETER Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeUintnToUint16 (
+ IN UINTN Operand,
+ OUT UINT16 *Result
+ );
+
+/**
+ UINTN -> INT32 conversion
+
+ Converts the value specified by Operand to a value specified by Result type
+ and stores the converted value into the caller allocated output buffer
+ specified by Result. The caller must pass in a Result buffer that is at
+ least as large as the Result type.
+
+ If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+ If the conversion results in an overflow or an underflow condition, then
+ Result is set to INT32_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+ @param[in] Operand Operand to be converted to new type
+ @param[out] Result Pointer to the result of conversion
+
+ @retval RETURN_SUCCESS Successful conversion
+ @retval RETURN_BUFFER_TOO_SMALL Overflow
+ @retval RETURN_INVALID_PARAMETER Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeUintnToInt32 (
+ IN UINTN Operand,
+ OUT INT32 *Result
+ );
+
+/**
+ UINTN -> UINT32 conversion
+
+ Converts the value specified by Operand to a value specified by Result type
+ and stores the converted value into the caller allocated output buffer
+ specified by Result. The caller must pass in a Result buffer that is at
+ least as large as the Result type.
+
+ If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+ If the conversion results in an overflow or an underflow condition, then
+ Result is set to UINT32_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+ @param[in] Operand Operand to be converted to new type
+ @param[out] Result Pointer to the result of conversion
+
+ @retval RETURN_SUCCESS Successful conversion
+ @retval RETURN_BUFFER_TOO_SMALL Overflow
+ @retval RETURN_INVALID_PARAMETER Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeUintnToUint32 (
+ IN UINTN Operand,
+ OUT UINT32 *Result
+ );
+
+/**
+ UINTN -> INTN conversion
+
+ Converts the value specified by Operand to a value specified by Result type
+ and stores the converted value into the caller allocated output buffer
+ specified by Result. The caller must pass in a Result buffer that is at
+ least as large as the Result type.
+
+ If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+ If the conversion results in an overflow or an underflow condition, then
+ Result is set to INTN_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+ @param[in] Operand Operand to be converted to new type
+ @param[out] Result Pointer to the result of conversion
+
+ @retval RETURN_SUCCESS Successful conversion
+ @retval RETURN_BUFFER_TOO_SMALL Overflow
+ @retval RETURN_INVALID_PARAMETER Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeUintnToIntn (
+ IN UINTN Operand,
+ OUT INTN *Result
+ );
+
+/**
+ UINTN -> INT64 conversion
+
+ Converts the value specified by Operand to a value specified by Result type
+ and stores the converted value into the caller allocated output buffer
+ specified by Result. The caller must pass in a Result buffer that is at
+ least as large as the Result type.
+
+ If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+ If the conversion results in an overflow or an underflow condition, then
+ Result is set to INT64_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+ @param[in] Operand Operand to be converted to new type
+ @param[out] Result Pointer to the result of conversion
+
+ @retval RETURN_SUCCESS Successful conversion
+ @retval RETURN_BUFFER_TOO_SMALL Overflow
+ @retval RETURN_INVALID_PARAMETER Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeUintnToInt64 (
+ IN UINTN Operand,
+ OUT INT64 *Result
+ );
+
+/**
+ INT64 -> INT8 conversion
+
+ Converts the value specified by Operand to a value specified by Result type
+ and stores the converted value into the caller allocated output buffer
+ specified by Result. The caller must pass in a Result buffer that is at
+ least as large as the Result type.
+
+ If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+ If the conversion results in an overflow or an underflow condition, then
+ Result is set to INT8_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+ @param[in] Operand Operand to be converted to new type
+ @param[out] Result Pointer to the result of conversion
+
+ @retval RETURN_SUCCESS Successful conversion
+ @retval RETURN_BUFFER_TOO_SMALL Overflow
+ @retval RETURN_INVALID_PARAMETER Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeInt64ToInt8 (
+ IN INT64 Operand,
+ OUT INT8 *Result
+ );
+
+/**
+ INT64 -> CHAR8 conversion
+
+ Converts the value specified by Operand to a value specified by Result type
+ and stores the converted value into the caller allocated output buffer
+ specified by Result. The caller must pass in a Result buffer that is at
+ least as large as the Result type.
+
+ If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+ If the conversion results in an overflow or an underflow condition, then
+ Result is set to CHAR8_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+ @param[in] Operand Operand to be converted to new type
+ @param[out] Result Pointer to the result of conversion
+
+ @retval RETURN_SUCCESS Successful conversion
+ @retval RETURN_BUFFER_TOO_SMALL Overflow
+ @retval RETURN_INVALID_PARAMETER Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeInt64ToChar8 (
+ IN INT64 Operand,
+ OUT CHAR8 *Result
+ );
+
+/**
+ INT64 -> UINT8 conversion
+
+ Converts the value specified by Operand to a value specified by Result type
+ and stores the converted value into the caller allocated output buffer
+ specified by Result. The caller must pass in a Result buffer that is at
+ least as large as the Result type.
+
+ If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+ If the conversion results in an overflow or an underflow condition, then
+ Result is set to UINT8_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+ @param[in] Operand Operand to be converted to new type
+ @param[out] Result Pointer to the result of conversion
+
+ @retval RETURN_SUCCESS Successful conversion
+ @retval RETURN_BUFFER_TOO_SMALL Overflow
+ @retval RETURN_INVALID_PARAMETER Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeInt64ToUint8 (
+ IN INT64 Operand,
+ OUT UINT8 *Result
+ );
+
+/**
+ INT64 -> INT16 conversion
+
+ Converts the value specified by Operand to a value specified by Result type
+ and stores the converted value into the caller allocated output buffer
+ specified by Result. The caller must pass in a Result buffer that is at
+ least as large as the Result type.
+
+ If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+ If the conversion results in an overflow or an underflow condition, then
+ Result is set to INT16_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+ @param[in] Operand Operand to be converted to new type
+ @param[out] Result Pointer to the result of conversion
+
+ @retval RETURN_SUCCESS Successful conversion
+ @retval RETURN_BUFFER_TOO_SMALL Overflow
+ @retval RETURN_INVALID_PARAMETER Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeInt64ToInt16 (
+ IN INT64 Operand,
+ OUT INT16 *Result
+ );
+
+/**
+ INT64 -> UINT16 conversion
+
+ Converts the value specified by Operand to a value specified by Result type
+ and stores the converted value into the caller allocated output buffer
+ specified by Result. The caller must pass in a Result buffer that is at
+ least as large as the Result type.
+
+ If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+ If the conversion results in an overflow or an underflow condition, then
+ Result is set to UINT16_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+ @param[in] Operand Operand to be converted to new type
+ @param[out] Result Pointer to the result of conversion
+
+ @retval RETURN_SUCCESS Successful conversion
+ @retval RETURN_BUFFER_TOO_SMALL Overflow
+ @retval RETURN_INVALID_PARAMETER Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeInt64ToUint16 (
+ IN INT64 Operand,
+ OUT UINT16 *Result
+ );
+
+/**
+ INT64 -> INT32 conversion
+
+ Converts the value specified by Operand to a value specified by Result type
+ and stores the converted value into the caller allocated output buffer
+ specified by Result. The caller must pass in a Result buffer that is at
+ least as large as the Result type.
+
+ If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+ If the conversion results in an overflow or an underflow condition, then
+ Result is set to INT32_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+ @param[in] Operand Operand to be converted to new type
+ @param[out] Result Pointer to the result of conversion
+
+ @retval RETURN_SUCCESS Successful conversion
+ @retval RETURN_BUFFER_TOO_SMALL Overflow
+ @retval RETURN_INVALID_PARAMETER Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeInt64ToInt32 (
+ IN INT64 Operand,
+ OUT INT32 *Result
+ );
+
+/**
+ INT64 -> UINT32 conversion
+
+ Converts the value specified by Operand to a value specified by Result type
+ and stores the converted value into the caller allocated output buffer
+ specified by Result. The caller must pass in a Result buffer that is at
+ least as large as the Result type.
+
+ If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+ If the conversion results in an overflow or an underflow condition, then
+ Result is set to UINT32_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+ @param[in] Operand Operand to be converted to new type
+ @param[out] Result Pointer to the result of conversion
+
+ @retval RETURN_SUCCESS Successful conversion
+ @retval RETURN_BUFFER_TOO_SMALL Overflow
+ @retval RETURN_INVALID_PARAMETER Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeInt64ToUint32 (
+ IN INT64 Operand,
+ OUT UINT32 *Result
+ );
+
+/**
+ INT64 -> INTN conversion
+
+ Converts the value specified by Operand to a value specified by Result type
+ and stores the converted value into the caller allocated output buffer
+ specified by Result. The caller must pass in a Result buffer that is at
+ least as large as the Result type.
+
+ If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+ If the conversion results in an overflow or an underflow condition, then
+ Result is set to INTN_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+ @param[in] Operand Operand to be converted to new type
+ @param[out] Result Pointer to the result of conversion
+
+ @retval RETURN_SUCCESS Successful conversion
+ @retval RETURN_BUFFER_TOO_SMALL Overflow
+ @retval RETURN_INVALID_PARAMETER Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeInt64ToIntn (
+ IN INT64 Operand,
+ OUT INTN *Result
+ );
+
+/**
+ INT64 -> UINTN conversion
+
+ Converts the value specified by Operand to a value specified by Result type
+ and stores the converted value into the caller allocated output buffer
+ specified by Result. The caller must pass in a Result buffer that is at
+ least as large as the Result type.
+
+ If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+ If the conversion results in an overflow or an underflow condition, then
+ Result is set to UINTN_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+ @param[in] Operand Operand to be converted to new type
+ @param[out] Result Pointer to the result of conversion
+
+ @retval RETURN_SUCCESS Successful conversion
+ @retval RETURN_BUFFER_TOO_SMALL Overflow
+ @retval RETURN_INVALID_PARAMETER Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeInt64ToUintn (
+ IN INT64 Operand,
+ OUT UINTN *Result
+ );
+
+/**
+ INT64 -> UINT64 conversion
+
+ Converts the value specified by Operand to a value specified by Result type
+ and stores the converted value into the caller allocated output buffer
+ specified by Result. The caller must pass in a Result buffer that is at
+ least as large as the Result type.
+
+ If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+ If the conversion results in an overflow or an underflow condition, then
+ Result is set to UINT64_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+ @param[in] Operand Operand to be converted to new type
+ @param[out] Result Pointer to the result of conversion
+
+ @retval RETURN_SUCCESS Successful conversion
+ @retval RETURN_BUFFER_TOO_SMALL Overflow
+ @retval RETURN_INVALID_PARAMETER Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeInt64ToUint64 (
+ IN INT64 Operand,
+ OUT UINT64 *Result
+ );
+
+/**
+ UINT64 -> INT8 conversion
+
+ Converts the value specified by Operand to a value specified by Result type
+ and stores the converted value into the caller allocated output buffer
+ specified by Result. The caller must pass in a Result buffer that is at
+ least as large as the Result type.
+
+ If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+ If the conversion results in an overflow or an underflow condition, then
+ Result is set to INT8_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+ @param[in] Operand Operand to be converted to new type
+ @param[out] Result Pointer to the result of conversion
+
+ @retval RETURN_SUCCESS Successful conversion
+ @retval RETURN_BUFFER_TOO_SMALL Overflow
+ @retval RETURN_INVALID_PARAMETER Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeUint64ToInt8 (
+ IN UINT64 Operand,
+ OUT INT8 *Result
+ );
+
+/**
+ UINT64 -> CHAR8 conversion
+
+ Converts the value specified by Operand to a value specified by Result type
+ and stores the converted value into the caller allocated output buffer
+ specified by Result. The caller must pass in a Result buffer that is at
+ least as large as the Result type.
+
+ If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+ If the conversion results in an overflow or an underflow condition, then
+ Result is set to CHAR8_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+ @param[in] Operand Operand to be converted to new type
+ @param[out] Result Pointer to the result of conversion
+
+ @retval RETURN_SUCCESS Successful conversion
+ @retval RETURN_BUFFER_TOO_SMALL Overflow
+ @retval RETURN_INVALID_PARAMETER Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeUint64ToChar8 (
+ IN UINT64 Operand,
+ OUT CHAR8 *Result
+ );
+
+/**
+ UINT64 -> UINT8 conversion
+
+ Converts the value specified by Operand to a value specified by Result type
+ and stores the converted value into the caller allocated output buffer
+ specified by Result. The caller must pass in a Result buffer that is at
+ least as large as the Result type.
+
+ If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+ If the conversion results in an overflow or an underflow condition, then
+ Result is set to UINT8_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+ @param[in] Operand Operand to be converted to new type
+ @param[out] Result Pointer to the result of conversion
+
+ @retval RETURN_SUCCESS Successful conversion
+ @retval RETURN_BUFFER_TOO_SMALL Overflow
+ @retval RETURN_INVALID_PARAMETER Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeUint64ToUint8 (
+ IN UINT64 Operand,
+ OUT UINT8 *Result
+ );
+
+/**
+ UINT64 -> INT16 conversion
+
+ Converts the value specified by Operand to a value specified by Result type
+ and stores the converted value into the caller allocated output buffer
+ specified by Result. The caller must pass in a Result buffer that is at
+ least as large as the Result type.
+
+ If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+ If the conversion results in an overflow or an underflow condition, then
+ Result is set to INT16_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+ @param[in] Operand Operand to be converted to new type
+ @param[out] Result Pointer to the result of conversion
+
+ @retval RETURN_SUCCESS Successful conversion
+ @retval RETURN_BUFFER_TOO_SMALL Overflow
+ @retval RETURN_INVALID_PARAMETER Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeUint64ToInt16 (
+ IN UINT64 Operand,
+ OUT INT16 *Result
+ );
+
+/**
+ UINT64 -> UINT16 conversion
+
+ Converts the value specified by Operand to a value specified by Result type
+ and stores the converted value into the caller allocated output buffer
+ specified by Result. The caller must pass in a Result buffer that is at
+ least as large as the Result type.
+
+ If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+ If the conversion results in an overflow or an underflow condition, then
+ Result is set to UINT16_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+ @param[in] Operand Operand to be converted to new type
+ @param[out] Result Pointer to the result of conversion
+
+ @retval RETURN_SUCCESS Successful conversion
+ @retval RETURN_BUFFER_TOO_SMALL Overflow
+ @retval RETURN_INVALID_PARAMETER Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeUint64ToUint16 (
+ IN UINT64 Operand,
+ OUT UINT16 *Result
+ );
+
+/**
+ UINT64 -> INT32 conversion
+
+ Converts the value specified by Operand to a value specified by Result type
+ and stores the converted value into the caller allocated output buffer
+ specified by Result. The caller must pass in a Result buffer that is at
+ least as large as the Result type.
+
+ If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+ If the conversion results in an overflow or an underflow condition, then
+ Result is set to INT32_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+ @param[in] Operand Operand to be converted to new type
+ @param[out] Result Pointer to the result of conversion
+
+ @retval RETURN_SUCCESS Successful conversion
+ @retval RETURN_BUFFER_TOO_SMALL Overflow
+ @retval RETURN_INVALID_PARAMETER Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeUint64ToInt32 (
+ IN UINT64 Operand,
+ OUT INT32 *Result
+ );
+
+/**
+ UINT64 -> UINT32 conversion
+
+ Converts the value specified by Operand to a value specified by Result type
+ and stores the converted value into the caller allocated output buffer
+ specified by Result. The caller must pass in a Result buffer that is at
+ least as large as the Result type.
+
+ If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+ If the conversion results in an overflow or an underflow condition, then
+ Result is set to UINT32_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+ @param[in] Operand Operand to be converted to new type
+ @param[out] Result Pointer to the result of conversion
+
+ @retval RETURN_SUCCESS Successful conversion
+ @retval RETURN_BUFFER_TOO_SMALL Overflow
+ @retval RETURN_INVALID_PARAMETER Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeUint64ToUint32 (
+ IN UINT64 Operand,
+ OUT UINT32 *Result
+ );
+
+/**
+ UINT64 -> INTN conversion
+
+ Converts the value specified by Operand to a value specified by Result type
+ and stores the converted value into the caller allocated output buffer
+ specified by Result. The caller must pass in a Result buffer that is at
+ least as large as the Result type.
+
+ If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+ If the conversion results in an overflow or an underflow condition, then
+ Result is set to INTN_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+ @param[in] Operand Operand to be converted to new type
+ @param[out] Result Pointer to the result of conversion
+
+ @retval RETURN_SUCCESS Successful conversion
+ @retval RETURN_BUFFER_TOO_SMALL Overflow
+ @retval RETURN_INVALID_PARAMETER Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeUint64ToIntn (
+ IN UINT64 Operand,
+ OUT INTN *Result
+ );
+
+/**
+ UINT64 -> UINTN conversion
+
+ Converts the value specified by Operand to a value specified by Result type
+ and stores the converted value into the caller allocated output buffer
+ specified by Result. The caller must pass in a Result buffer that is at
+ least as large as the Result type.
+
+ If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+ If the conversion results in an overflow or an underflow condition, then
+ Result is set to UINTN_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+ @param[in] Operand Operand to be converted to new type
+ @param[out] Result Pointer to the result of conversion
+
+ @retval RETURN_SUCCESS Successful conversion
+ @retval RETURN_BUFFER_TOO_SMALL Overflow
+ @retval RETURN_INVALID_PARAMETER Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeUint64ToUintn (
+ IN UINT64 Operand,
+ OUT UINTN *Result
+ );
+
+/**
+ UINT64 -> INT64 conversion
+
+ Converts the value specified by Operand to a value specified by Result type
+ and stores the converted value into the caller allocated output buffer
+ specified by Result. The caller must pass in a Result buffer that is at
+ least as large as the Result type.
+
+ If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+ If the conversion results in an overflow or an underflow condition, then
+ Result is set to INT64_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+ @param[in] Operand Operand to be converted to new type
+ @param[out] Result Pointer to the result of conversion
+
+ @retval RETURN_SUCCESS Successful conversion
+ @retval RETURN_BUFFER_TOO_SMALL Overflow
+ @retval RETURN_INVALID_PARAMETER Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeUint64ToInt64 (
+ IN UINT64 Operand,
+ OUT INT64 *Result
+ );
+
+//
+// Addition functions
+//
+
+/**
+ UINT8 addition
+
+ Performs the requested operation using the input parameters into a value
+ specified by Result type and stores the converted value into the caller
+ allocated output buffer specified by Result. The caller must pass in a
+ Result buffer that is at least as large as the Result type.
+
+ If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+ If the requested operation results in an overflow or an underflow condition,
+ then Result is set to UINT8_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+ @param[in] Augend A number to which addend will be added
+ @param[in] Addend A number to be added to another
+ @param[out] Result Pointer to the result of addition
+
+ @retval RETURN_SUCCESS Successful addition
+ @retval RETURN_BUFFER_TOO_SMALL Overflow
+ @retval RETURN_INVALID_PARAMETER Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeUint8Add (
+ IN UINT8 Augend,
+ IN UINT8 Addend,
+ OUT UINT8 *Result
+ );
+
+/**
+ UINT16 addition
+
+ Performs the requested operation using the input parameters into a value
+ specified by Result type and stores the converted value into the caller
+ allocated output buffer specified by Result. The caller must pass in a
+ Result buffer that is at least as large as the Result type.
+
+ If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+ If the requested operation results in an overflow or an underflow condition,
+ then Result is set to UINT16_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+ @param[in] Augend A number to which addend will be added
+ @param[in] Addend A number to be added to another
+ @param[out] Result Pointer to the result of addition
+
+ @retval RETURN_SUCCESS Successful addition
+ @retval RETURN_BUFFER_TOO_SMALL Overflow
+ @retval RETURN_INVALID_PARAMETER Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeUint16Add (
+ IN UINT16 Augend,
+ IN UINT16 Addend,
+ OUT UINT16 *Result
+ );
+
+/**
+ UINT32 addition
+
+ Performs the requested operation using the input parameters into a value
+ specified by Result type and stores the converted value into the caller
+ allocated output buffer specified by Result. The caller must pass in a
+ Result buffer that is at least as large as the Result type.
+
+ If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+ If the requested operation results in an overflow or an underflow condition,
+ then Result is set to UINT32_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+ @param[in] Augend A number to which addend will be added
+ @param[in] Addend A number to be added to another
+ @param[out] Result Pointer to the result of addition
+
+ @retval RETURN_SUCCESS Successful addition
+ @retval RETURN_BUFFER_TOO_SMALL Overflow
+ @retval RETURN_INVALID_PARAMETER Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeUint32Add (
+ IN UINT32 Augend,
+ IN UINT32 Addend,
+ OUT UINT32 *Result
+ );
+
+/**
+ UINTN addition
+
+ Performs the requested operation using the input parameters into a value
+ specified by Result type and stores the converted value into the caller
+ allocated output buffer specified by Result. The caller must pass in a
+ Result buffer that is at least as large as the Result type.
+
+ If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+ If the requested operation results in an overflow or an underflow condition,
+ then Result is set to UINTN_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+ @param[in] Augend A number to which addend will be added
+ @param[in] Addend A number to be added to another
+ @param[out] Result Pointer to the result of addition
+
+ @retval RETURN_SUCCESS Successful addition
+ @retval RETURN_BUFFER_TOO_SMALL Overflow
+ @retval RETURN_INVALID_PARAMETER Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeUintnAdd (
+ IN UINTN Augend,
+ IN UINTN Addend,
+ OUT UINTN *Result
+ );
+
+/**
+ UINT64 addition
+
+ Performs the requested operation using the input parameters into a value
+ specified by Result type and stores the converted value into the caller
+ allocated output buffer specified by Result. The caller must pass in a
+ Result buffer that is at least as large as the Result type.
+
+ If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+ If the requested operation results in an overflow or an underflow condition,
+ then Result is set to UINT64_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+ @param[in] Augend A number to which addend will be added
+ @param[in] Addend A number to be added to another
+ @param[out] Result Pointer to the result of addition
+
+ @retval RETURN_SUCCESS Successful addition
+ @retval RETURN_BUFFER_TOO_SMALL Overflow
+ @retval RETURN_INVALID_PARAMETER Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeUint64Add (
+ IN UINT64 Augend,
+ IN UINT64 Addend,
+ OUT UINT64 *Result
+ );
+
+//
+// Subtraction functions
+//
+
+/**
+ UINT8 subtraction
+
+ Performs the requested operation using the input parameters into a value
+ specified by Result type and stores the converted value into the caller
+ allocated output buffer specified by Result. The caller must pass in a
+ Result buffer that is at least as large as the Result type.
+
+ If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+ If the requested operation results in an overflow or an underflow condition,
+ then Result is set to UINT8_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+ @param[in] Minuend A number from which another is to be subtracted.
+ @param[in] Subtrahend A number to be subtracted from another
+ @param[out] Result Pointer to the result of subtraction
+
+ @retval RETURN_SUCCESS Successful subtraction
+ @retval RETURN_BUFFER_TOO_SMALL Underflow
+ @retval RETURN_INVALID_PARAMETER Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeUint8Sub (
+ IN UINT8 Minuend,
+ IN UINT8 Subtrahend,
+ OUT UINT8 *Result
+ );
+
+/**
+ UINT16 subtraction
+
+ Performs the requested operation using the input parameters into a value
+ specified by Result type and stores the converted value into the caller
+ allocated output buffer specified by Result. The caller must pass in a
+ Result buffer that is at least as large as the Result type.
+
+ If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+ If the requested operation results in an overflow or an underflow condition,
+ then Result is set to UINT16_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+ @param[in] Minuend A number from which another is to be subtracted.
+ @param[in] Subtrahend A number to be subtracted from another
+ @param[out] Result Pointer to the result of subtraction
+
+ @retval RETURN_SUCCESS Successful subtraction
+ @retval RETURN_BUFFER_TOO_SMALL Underflow
+ @retval RETURN_INVALID_PARAMETER Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeUint16Sub (
+ IN UINT16 Minuend,
+ IN UINT16 Subtrahend,
+ OUT UINT16 *Result
+ );
+
+/**
+ UINT32 subtraction
+
+ Performs the requested operation using the input parameters into a value
+ specified by Result type and stores the converted value into the caller
+ allocated output buffer specified by Result. The caller must pass in a
+ Result buffer that is at least as large as the Result type.
+
+ If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+ If the requested operation results in an overflow or an underflow condition,
+ then Result is set to UINT32_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+ @param[in] Minuend A number from which another is to be subtracted.
+ @param[in] Subtrahend A number to be subtracted from another
+ @param[out] Result Pointer to the result of subtraction
+
+ @retval RETURN_SUCCESS Successful subtraction
+ @retval RETURN_BUFFER_TOO_SMALL Underflow
+ @retval RETURN_INVALID_PARAMETER Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeUint32Sub (
+ IN UINT32 Minuend,
+ IN UINT32 Subtrahend,
+ OUT UINT32 *Result
+ );
+
+/**
+ UINTN subtraction
+
+ Performs the requested operation using the input parameters into a value
+ specified by Result type and stores the converted value into the caller
+ allocated output buffer specified by Result. The caller must pass in a
+ Result buffer that is at least as large as the Result type.
+
+ If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+ If the requested operation results in an overflow or an underflow condition,
+ then Result is set to UINTN_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+ @param[in] Minuend A number from which another is to be subtracted.
+ @param[in] Subtrahend A number to be subtracted from another
+ @param[out] Result Pointer to the result of subtraction
+
+ @retval RETURN_SUCCESS Successful subtraction
+ @retval RETURN_BUFFER_TOO_SMALL Underflow
+ @retval RETURN_INVALID_PARAMETER Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeUintnSub (
+ IN UINTN Minuend,
+ IN UINTN Subtrahend,
+ OUT UINTN *Result
+ );
+
+/**
+ UINT64 subtraction
+
+ Performs the requested operation using the input parameters into a value
+ specified by Result type and stores the converted value into the caller
+ allocated output buffer specified by Result. The caller must pass in a
+ Result buffer that is at least as large as the Result type.
+
+ If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+ If the requested operation results in an overflow or an underflow condition,
+ then Result is set to UINT64_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+ @param[in] Minuend A number from which another is to be subtracted.
+ @param[in] Subtrahend A number to be subtracted from another
+ @param[out] Result Pointer to the result of subtraction
+
+ @retval RETURN_SUCCESS Successful subtraction
+ @retval RETURN_BUFFER_TOO_SMALL Underflow
+ @retval RETURN_INVALID_PARAMETER Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeUint64Sub (
+ IN UINT64 Minuend,
+ IN UINT64 Subtrahend,
+ OUT UINT64 *Result
+ );
+
+//
+// Multiplication functions
+//
+
+/**
+ UINT8 multiplication
+
+ Performs the requested operation using the input parameters into a value
+ specified by Result type and stores the converted value into the caller
+ allocated output buffer specified by Result. The caller must pass in a
+ Result buffer that is at least as large as the Result type.
+
+ If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+ If the requested operation results in an overflow or an underflow condition,
+ then Result is set to UINT8_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+ @param[in] Multiplicand A number that is to be multiplied by another
+ @param[in] Multiplier A number by which the multiplicand is to be multiplied
+ @param[out] Result Pointer to the result of multiplication
+
+ @retval RETURN_SUCCESS Successful multiplication
+ @retval RETURN_BUFFER_TOO_SMALL Overflow
+ @retval RETURN_INVALID_PARAMETER Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeUint8Mult (
+ IN UINT8 Multiplicand,
+ IN UINT8 Multiplier,
+ OUT UINT8 *Result
+ );
+
+/**
+ UINT16 multiplication
+
+ Performs the requested operation using the input parameters into a value
+ specified by Result type and stores the converted value into the caller
+ allocated output buffer specified by Result. The caller must pass in a
+ Result buffer that is at least as large as the Result type.
+
+ If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+ If the requested operation results in an overflow or an underflow condition,
+ then Result is set to UINT16_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+ @param[in] Multiplicand A number that is to be multiplied by another
+ @param[in] Multiplier A number by which the multiplicand is to be multiplied
+ @param[out] Result Pointer to the result of multiplication
+
+ @retval RETURN_SUCCESS Successful multiplication
+ @retval RETURN_BUFFER_TOO_SMALL Overflow
+ @retval RETURN_INVALID_PARAMETER Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeUint16Mult (
+ IN UINT16 Multiplicand,
+ IN UINT16 Multiplier,
+ OUT UINT16 *Result
+ );
+
+/**
+ UINT32 multiplication
+
+ Performs the requested operation using the input parameters into a value
+ specified by Result type and stores the converted value into the caller
+ allocated output buffer specified by Result. The caller must pass in a
+ Result buffer that is at least as large as the Result type.
+
+ If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+ If the requested operation results in an overflow or an underflow condition,
+ then Result is set to UINT32_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+ @param[in] Multiplicand A number that is to be multiplied by another
+ @param[in] Multiplier A number by which the multiplicand is to be multiplied
+ @param[out] Result Pointer to the result of multiplication
+
+ @retval RETURN_SUCCESS Successful multiplication
+ @retval RETURN_BUFFER_TOO_SMALL Overflow
+ @retval RETURN_INVALID_PARAMETER Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeUint32Mult (
+ IN UINT32 Multiplicand,
+ IN UINT32 Multiplier,
+ OUT UINT32 *Result
+ );
+
+/**
+ UINTN multiplication
+
+ Performs the requested operation using the input parameters into a value
+ specified by Result type and stores the converted value into the caller
+ allocated output buffer specified by Result. The caller must pass in a
+ Result buffer that is at least as large as the Result type.
+
+ If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+ If the requested operation results in an overflow or an underflow condition,
+ then Result is set to UINTN_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+ @param[in] Multiplicand A number that is to be multiplied by another
+ @param[in] Multiplier A number by which the multiplicand is to be multiplied
+ @param[out] Result Pointer to the result of multiplication
+
+ @retval RETURN_SUCCESS Successful multiplication
+ @retval RETURN_BUFFER_TOO_SMALL Overflow
+ @retval RETURN_INVALID_PARAMETER Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeUintnMult (
+ IN UINTN Multiplicand,
+ IN UINTN Multiplier,
+ OUT UINTN *Result
+ );
+
+/**
+ UINT64 multiplication
+
+ Performs the requested operation using the input parameters into a value
+ specified by Result type and stores the converted value into the caller
+ allocated output buffer specified by Result. The caller must pass in a
+ Result buffer that is at least as large as the Result type.
+
+ If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+ If the requested operation results in an overflow or an underflow condition,
+ then Result is set to UINT64_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+ @param[in] Multiplicand A number that is to be multiplied by another
+ @param[in] Multiplier A number by which the multiplicand is to be multiplied
+ @param[out] Result Pointer to the result of multiplication
+
+ @retval RETURN_SUCCESS Successful multiplication
+ @retval RETURN_BUFFER_TOO_SMALL Overflow
+ @retval RETURN_INVALID_PARAMETER Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeUint64Mult (
+ IN UINT64 Multiplicand,
+ IN UINT64 Multiplier,
+ OUT UINT64 *Result
+ );
+
+//
+// Signed operations
+//
+// Strongly consider using unsigned numbers.
+//
+// Signed numbers are often used where unsigned numbers should be used.
+// For example file sizes and array indices should always be unsigned.
+// Subtracting a larger positive signed number from a smaller positive
+// signed number with SafeInt32Sub will succeed, producing a negative number,
+// that then must not be used as an array index (but can occasionally be
+// used as a pointer index.) Similarly for adding a larger magnitude
+// negative number to a smaller magnitude positive number.
+//
+// This library does not protect you from such errors. It tells you if your
+// integer operations overflowed, not if you are doing the right thing
+// with your non-overflowed integers.
+//
+// Likewise you can overflow a buffer with a non-overflowed unsigned index.
+//
+
+//
+// Signed addition functions
+//
+
+/**
+ INT8 Addition
+
+ Performs the requested operation using the input parameters into a value
+ specified by Result type and stores the converted value into the caller
+ allocated output buffer specified by Result. The caller must pass in a
+ Result buffer that is at least as large as the Result type.
+
+ If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+ If the requested operation results in an overflow or an underflow condition,
+ then Result is set to INT8_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+ @param[in] Augend A number to which addend will be added
+ @param[in] Addend A number to be added to another
+ @param[out] Result Pointer to the result of addition
+
+ @retval RETURN_SUCCESS Successful addition
+ @retval RETURN_BUFFER_TOO_SMALL Overflow
+ @retval RETURN_INVALID_PARAMETER Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeInt8Add (
+ IN INT8 Augend,
+ IN INT8 Addend,
+ OUT INT8 *Result
+ );
+
+/**
+ CHAR8 Addition
+
+ Performs the requested operation using the input parameters into a value
+ specified by Result type and stores the converted value into the caller
+ allocated output buffer specified by Result. The caller must pass in a
+ Result buffer that is at least as large as the Result type.
+
+ If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+ If the requested operation results in an overflow or an underflow condition,
+ then Result is set to CHAR8_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+ @param[in] Augend A number to which addend will be added
+ @param[in] Addend A number to be added to another
+ @param[out] Result Pointer to the result of addition
+
+ @retval RETURN_SUCCESS Successful addition
+ @retval RETURN_BUFFER_TOO_SMALL Overflow
+ @retval RETURN_INVALID_PARAMETER Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeChar8Add (
+ IN CHAR8 Augend,
+ IN CHAR8 Addend,
+ OUT CHAR8 *Result
+ );
+
+/**
+ INT16 Addition
+
+ Performs the requested operation using the input parameters into a value
+ specified by Result type and stores the converted value into the caller
+ allocated output buffer specified by Result. The caller must pass in a
+ Result buffer that is at least as large as the Result type.
+
+ If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+ If the requested operation results in an overflow or an underflow condition,
+ then Result is set to INT16_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+ @param[in] Augend A number to which addend will be added
+ @param[in] Addend A number to be added to another
+ @param[out] Result Pointer to the result of addition
+
+ @retval RETURN_SUCCESS Successful addition
+ @retval RETURN_BUFFER_TOO_SMALL Overflow
+ @retval RETURN_INVALID_PARAMETER Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeInt16Add (
+ IN INT16 Augend,
+ IN INT16 Addend,
+ OUT INT16 *Result
+ );
+
+/**
+ INT32 Addition
+
+ Performs the requested operation using the input parameters into a value
+ specified by Result type and stores the converted value into the caller
+ allocated output buffer specified by Result. The caller must pass in a
+ Result buffer that is at least as large as the Result type.
+
+ If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+ If the requested operation results in an overflow or an underflow condition,
+ then Result is set to INT32_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+ @param[in] Augend A number to which addend will be added
+ @param[in] Addend A number to be added to another
+ @param[out] Result Pointer to the result of addition
+
+ @retval RETURN_SUCCESS Successful addition
+ @retval RETURN_BUFFER_TOO_SMALL Overflow
+ @retval RETURN_INVALID_PARAMETER Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeInt32Add (
+ IN INT32 Augend,
+ IN INT32 Addend,
+ OUT INT32 *Result
+ );
+
+/**
+ INTN Addition
+
+ Performs the requested operation using the input parameters into a value
+ specified by Result type and stores the converted value into the caller
+ allocated output buffer specified by Result. The caller must pass in a
+ Result buffer that is at least as large as the Result type.
+
+ If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+ If the requested operation results in an overflow or an underflow condition,
+ then Result is set to INTN_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+ @param[in] Augend A number to which addend will be added
+ @param[in] Addend A number to be added to another
+ @param[out] Result Pointer to the result of addition
+
+ @retval RETURN_SUCCESS Successful addition
+ @retval RETURN_BUFFER_TOO_SMALL Overflow
+ @retval RETURN_INVALID_PARAMETER Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeIntnAdd (
+ IN INTN Augend,
+ IN INTN Addend,
+ OUT INTN *Result
+ );
+
+/**
+ INT64 Addition
+
+ Performs the requested operation using the input parameters into a value
+ specified by Result type and stores the converted value into the caller
+ allocated output buffer specified by Result. The caller must pass in a
+ Result buffer that is at least as large as the Result type.
+
+ If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+ If the requested operation results in an overflow or an underflow condition,
+ then Result is set to INT64_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+ @param[in] Augend A number to which addend will be added
+ @param[in] Addend A number to be added to another
+ @param[out] Result Pointer to the result of addition
+
+ @retval RETURN_SUCCESS Successful addition
+ @retval RETURN_BUFFER_TOO_SMALL Overflow
+ @retval RETURN_INVALID_PARAMETER Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeInt64Add (
+ IN INT64 Augend,
+ IN INT64 Addend,
+ OUT INT64 *Result
+ );
+
+//
+// Signed subtraction functions
+//
+
+/**
+ INT8 Subtraction
+
+ Performs the requested operation using the input parameters into a value
+ specified by Result type and stores the converted value into the caller
+ allocated output buffer specified by Result. The caller must pass in a
+ Result buffer that is at least as large as the Result type.
+
+ If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+ If the requested operation results in an overflow or an underflow condition,
+ then Result is set to INT8_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+ @param[in] Minuend A number from which another is to be subtracted.
+ @param[in] Subtrahend A number to be subtracted from another
+ @param[out] Result Pointer to the result of subtraction
+
+ @retval RETURN_SUCCESS Successful subtraction
+ @retval RETURN_BUFFER_TOO_SMALL Underflow
+ @retval RETURN_INVALID_PARAMETER Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeInt8Sub (
+ IN INT8 Minuend,
+ IN INT8 Subtrahend,
+ OUT INT8 *Result
+ );
+
+/**
+ CHAR8 Subtraction
+
+ Performs the requested operation using the input parameters into a value
+ specified by Result type and stores the converted value into the caller
+ allocated output buffer specified by Result. The caller must pass in a
+ Result buffer that is at least as large as the Result type.
+
+ If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+ If the requested operation results in an overflow or an underflow condition,
+ then Result is set to CHAR8_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+ @param[in] Minuend A number from which another is to be subtracted.
+ @param[in] Subtrahend A number to be subtracted from another
+ @param[out] Result Pointer to the result of subtraction
+
+ @retval RETURN_SUCCESS Successful subtraction
+ @retval RETURN_BUFFER_TOO_SMALL Underflow
+ @retval RETURN_INVALID_PARAMETER Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeChar8Sub (
+ IN CHAR8 Minuend,
+ IN CHAR8 Subtrahend,
+ OUT CHAR8 *Result
+ );
+
+/**
+ INT16 Subtraction
+
+ Performs the requested operation using the input parameters into a value
+ specified by Result type and stores the converted value into the caller
+ allocated output buffer specified by Result. The caller must pass in a
+ Result buffer that is at least as large as the Result type.
+
+ If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+ If the requested operation results in an overflow or an underflow condition,
+ then Result is set to INT16_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+ @param[in] Minuend A number from which another is to be subtracted.
+ @param[in] Subtrahend A number to be subtracted from another
+ @param[out] Result Pointer to the result of subtraction
+
+ @retval RETURN_SUCCESS Successful subtraction
+ @retval RETURN_BUFFER_TOO_SMALL Underflow
+ @retval RETURN_INVALID_PARAMETER Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeInt16Sub (
+ IN INT16 Minuend,
+ IN INT16 Subtrahend,
+ OUT INT16 *Result
+ );
+
+/**
+ INT32 Subtraction
+
+ Performs the requested operation using the input parameters into a value
+ specified by Result type and stores the converted value into the caller
+ allocated output buffer specified by Result. The caller must pass in a
+ Result buffer that is at least as large as the Result type.
+
+ If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+ If the requested operation results in an overflow or an underflow condition,
+ then Result is set to INT32_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+ @param[in] Minuend A number from which another is to be subtracted.
+ @param[in] Subtrahend A number to be subtracted from another
+ @param[out] Result Pointer to the result of subtraction
+
+ @retval RETURN_SUCCESS Successful subtraction
+ @retval RETURN_BUFFER_TOO_SMALL Underflow
+ @retval RETURN_INVALID_PARAMETER Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeInt32Sub (
+ IN INT32 Minuend,
+ IN INT32 Subtrahend,
+ OUT INT32 *Result
+ );
+
+/**
+ INTN Subtraction
+
+ Performs the requested operation using the input parameters into a value
+ specified by Result type and stores the converted value into the caller
+ allocated output buffer specified by Result. The caller must pass in a
+ Result buffer that is at least as large as the Result type.
+
+ If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+ If the requested operation results in an overflow or an underflow condition,
+ then Result is set to INTN_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+ @param[in] Minuend A number from which another is to be subtracted.
+ @param[in] Subtrahend A number to be subtracted from another
+ @param[out] Result Pointer to the result of subtraction
+
+ @retval RETURN_SUCCESS Successful subtraction
+ @retval RETURN_BUFFER_TOO_SMALL Underflow
+ @retval RETURN_INVALID_PARAMETER Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeIntnSub (
+ IN INTN Minuend,
+ IN INTN Subtrahend,
+ OUT INTN *Result
+ );
+
+/**
+ INT64 Subtraction
+
+ Performs the requested operation using the input parameters into a value
+ specified by Result type and stores the converted value into the caller
+ allocated output buffer specified by Result. The caller must pass in a
+ Result buffer that is at least as large as the Result type.
+
+ If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+ If the requested operation results in an overflow or an underflow condition,
+ then Result is set to INT64_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+ @param[in] Minuend A number from which another is to be subtracted.
+ @param[in] Subtrahend A number to be subtracted from another
+ @param[out] Result Pointer to the result of subtraction
+
+ @retval RETURN_SUCCESS Successful subtraction
+ @retval RETURN_BUFFER_TOO_SMALL Underflow
+ @retval RETURN_INVALID_PARAMETER Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeInt64Sub (
+ IN INT64 Minuend,
+ IN INT64 Subtrahend,
+ OUT INT64 *Result
+ );
+
+//
+// Signed multiplication functions
+//
+
+/**
+ INT8 multiplication
+
+ Performs the requested operation using the input parameters into a value
+ specified by Result type and stores the converted value into the caller
+ allocated output buffer specified by Result. The caller must pass in a
+ Result buffer that is at least as large as the Result type.
+
+ If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+ If the requested operation results in an overflow or an underflow condition,
+ then Result is set to INT8_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+ @param[in] Multiplicand A number that is to be multiplied by another
+ @param[in] Multiplier A number by which the multiplicand is to be multiplied
+ @param[out] Result Pointer to the result of multiplication
+
+ @retval RETURN_SUCCESS Successful multiplication
+ @retval RETURN_BUFFER_TOO_SMALL Overflow
+ @retval RETURN_INVALID_PARAMETER Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeInt8Mult (
+ IN INT8 Multiplicand,
+ IN INT8 Multiplier,
+ OUT INT8 *Result
+ );
+
+/**
+ CHAR8 multiplication
+
+ Performs the requested operation using the input parameters into a value
+ specified by Result type and stores the converted value into the caller
+ allocated output buffer specified by Result. The caller must pass in a
+ Result buffer that is at least as large as the Result type.
+
+ If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+ If the requested operation results in an overflow or an underflow condition,
+ then Result is set to CHAR8_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+ @param[in] Multiplicand A number that is to be multiplied by another
+ @param[in] Multiplier A number by which the multiplicand is to be multiplied
+ @param[out] Result Pointer to the result of multiplication
+
+ @retval RETURN_SUCCESS Successful multiplication
+ @retval RETURN_BUFFER_TOO_SMALL Overflow
+ @retval RETURN_INVALID_PARAMETER Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeChar8Mult (
+ IN CHAR8 Multiplicand,
+ IN CHAR8 Multiplier,
+ OUT CHAR8 *Result
+ );
+
+/**
+ INT16 multiplication
+
+ Performs the requested operation using the input parameters into a value
+ specified by Result type and stores the converted value into the caller
+ allocated output buffer specified by Result. The caller must pass in a
+ Result buffer that is at least as large as the Result type.
+
+ If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+ If the requested operation results in an overflow or an underflow condition,
+ then Result is set to INT16_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+ @param[in] Multiplicand A number that is to be multiplied by another
+ @param[in] Multiplier A number by which the multiplicand is to be multiplied
+ @param[out] Result Pointer to the result of multiplication
+
+ @retval RETURN_SUCCESS Successful multiplication
+ @retval RETURN_BUFFER_TOO_SMALL Overflow
+ @retval RETURN_INVALID_PARAMETER Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeInt16Mult (
+ IN INT16 Multiplicand,
+ IN INT16 Multiplier,
+ OUT INT16 *Result
+ );
+
+/**
+ INT32 multiplication
+
+ Performs the requested operation using the input parameters into a value
+ specified by Result type and stores the converted value into the caller
+ allocated output buffer specified by Result. The caller must pass in a
+ Result buffer that is at least as large as the Result type.
+
+ If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+ If the requested operation results in an overflow or an underflow condition,
+ then Result is set to INT32_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+ @param[in] Multiplicand A number that is to be multiplied by another
+ @param[in] Multiplier A number by which the multiplicand is to be multiplied
+ @param[out] Result Pointer to the result of multiplication
+
+ @retval RETURN_SUCCESS Successful multiplication
+ @retval RETURN_BUFFER_TOO_SMALL Overflow
+ @retval RETURN_INVALID_PARAMETER Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeInt32Mult (
+ IN INT32 Multiplicand,
+ IN INT32 Multiplier,
+ OUT INT32 *Result
+ );
+
+/**
+ INTN multiplication
+
+ Performs the requested operation using the input parameters into a value
+ specified by Result type and stores the converted value into the caller
+ allocated output buffer specified by Result. The caller must pass in a
+ Result buffer that is at least as large as the Result type.
+
+ If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+ If the requested operation results in an overflow or an underflow condition,
+ then Result is set to INTN_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+ @param[in] Multiplicand A number that is to be multiplied by another
+ @param[in] Multiplier A number by which the multiplicand is to be multiplied
+ @param[out] Result Pointer to the result of multiplication
+
+ @retval RETURN_SUCCESS Successful multiplication
+ @retval RETURN_BUFFER_TOO_SMALL Overflow
+ @retval RETURN_INVALID_PARAMETER Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeIntnMult (
+ IN INTN Multiplicand,
+ IN INTN Multiplier,
+ OUT INTN *Result
+ );
+
+/**
+ INT64 multiplication
+
+ Performs the requested operation using the input parameters into a value
+ specified by Result type and stores the converted value into the caller
+ allocated output buffer specified by Result. The caller must pass in a
+ Result buffer that is at least as large as the Result type.
+
+ If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+ If the requested operation results in an overflow or an underflow condition,
+ then Result is set to INT64_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+ @param[in] Multiplicand A number that is to be multiplied by another
+ @param[in] Multiplier A number by which the multiplicand is to be multiplied
+ @param[out] Result Pointer to the result of multiplication
+
+ @retval RETURN_SUCCESS Successful multiplication
+ @retval RETURN_BUFFER_TOO_SMALL Overflow
+ @retval RETURN_INVALID_PARAMETER Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeInt64Mult (
+ IN INT64 Multiplicand,
+ IN INT64 Multiplier,
+ OUT INT64 *Result
+ );
+
+#endif // __INT_SAFE_LIB_H__
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/SerialPortLib.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/SerialPortLib.h
new file mode 100644
index 0000000000..9b633c60a2
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/SerialPortLib.h
@@ -0,0 +1,173 @@
+/** @file
+ This library class provides common serial I/O port functions.
+
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+Copyright (c) 2012 - 2014, ARM Ltd. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __SERIAL_PORT_LIB__
+#define __SERIAL_PORT_LIB__
+
+#include
+#include
+
+/**
+ Initialize the serial device hardware.
+
+ If no initialization is required, then return RETURN_SUCCESS.
+ If the serial device was successfully initialized, then return RETURN_SUCCESS.
+ If the serial device could not be initialized, then return RETURN_DEVICE_ERROR.
+
+ @retval RETURN_SUCCESS The serial device was initialized.
+ @retval RETURN_DEVICE_ERROR The serial device could not be initialized.
+
+**/
+RETURN_STATUS
+EFIAPI
+SerialPortInitialize (
+ VOID
+ );
+
+/**
+ Write data from buffer to serial device.
+
+ Writes NumberOfBytes data bytes from Buffer to the serial device.
+ The number of bytes actually written to the serial device is returned.
+ If the return value is less than NumberOfBytes, then the write operation failed.
+ If Buffer is NULL, then ASSERT().
+ If NumberOfBytes is zero, then return 0.
+
+ @param Buffer Pointer to the data buffer to be written.
+ @param NumberOfBytes Number of bytes to written to the serial device.
+
+ @retval 0 NumberOfBytes is 0.
+ @retval >0 The number of bytes written to the serial device.
+ If this value is less than NumberOfBytes, then the write operation failed.
+
+**/
+UINTN
+EFIAPI
+SerialPortWrite (
+ IN UINT8 *Buffer,
+ IN UINTN NumberOfBytes
+ );
+
+/**
+ Read data from serial device and save the datas in buffer.
+
+ Reads NumberOfBytes data bytes from a serial device into the buffer
+ specified by Buffer. The number of bytes actually read is returned.
+ If the return value is less than NumberOfBytes, then the rest operation failed.
+ If Buffer is NULL, then ASSERT().
+ If NumberOfBytes is zero, then return 0.
+
+ @param Buffer Pointer to the data buffer to store the data read from the serial device.
+ @param NumberOfBytes Number of bytes which will be read.
+
+ @retval 0 Read data failed, no data is to be read.
+ @retval >0 Actual number of bytes read from serial device.
+
+**/
+UINTN
+EFIAPI
+SerialPortRead (
+ OUT UINT8 *Buffer,
+ IN UINTN NumberOfBytes
+ );
+
+/**
+ Polls a serial device to see if there is any data waiting to be read.
+
+ Polls a serial device to see if there is any data waiting to be read.
+ If there is data waiting to be read from the serial device, then TRUE is returned.
+ If there is no data waiting to be read from the serial device, then FALSE is returned.
+
+ @retval TRUE Data is waiting to be read from the serial device.
+ @retval FALSE There is no data waiting to be read from the serial device.
+
+**/
+BOOLEAN
+EFIAPI
+SerialPortPoll (
+ VOID
+ );
+
+/**
+ Sets the control bits on a serial device.
+
+ @param Control Sets the bits of Control that are settable.
+
+ @retval RETURN_SUCCESS The new control bits were set on the serial device.
+ @retval RETURN_UNSUPPORTED The serial device does not support this operation.
+ @retval RETURN_DEVICE_ERROR The serial device is not functioning correctly.
+
+**/
+RETURN_STATUS
+EFIAPI
+SerialPortSetControl (
+ IN UINT32 Control
+ );
+
+/**
+ Retrieve the status of the control bits on a serial device.
+
+ @param Control A pointer to return the current control signals from the serial device.
+
+ @retval RETURN_SUCCESS The control bits were read from the serial device.
+ @retval RETURN_UNSUPPORTED The serial device does not support this operation.
+ @retval RETURN_DEVICE_ERROR The serial device is not functioning correctly.
+
+**/
+RETURN_STATUS
+EFIAPI
+SerialPortGetControl (
+ OUT UINT32 *Control
+ );
+
+/**
+ Sets the baud rate, receive FIFO depth, transmit/receice time out, parity,
+ data bits, and stop bits on a serial device.
+
+ @param BaudRate The requested baud rate. A BaudRate value of 0 will use the
+ device's default interface speed.
+ On output, the value actually set.
+ @param ReveiveFifoDepth The requested depth of the FIFO on the receive side of the
+ serial interface. A ReceiveFifoDepth value of 0 will use
+ the device's default FIFO depth.
+ On output, the value actually set.
+ @param Timeout The requested time out for a single character in microseconds.
+ This timeout applies to both the transmit and receive side of the
+ interface. A Timeout value of 0 will use the device's default time
+ out value.
+ On output, the value actually set.
+ @param Parity The type of parity to use on this serial device. A Parity value of
+ DefaultParity will use the device's default parity value.
+ On output, the value actually set.
+ @param DataBits The number of data bits to use on the serial device. A DataBits
+ vaule of 0 will use the device's default data bit setting.
+ On output, the value actually set.
+ @param StopBits The number of stop bits to use on this serial device. A StopBits
+ value of DefaultStopBits will use the device's default number of
+ stop bits.
+ On output, the value actually set.
+
+ @retval RETURN_SUCCESS The new attributes were set on the serial device.
+ @retval RETURN_UNSUPPORTED The serial device does not support this operation.
+ @retval RETURN_INVALID_PARAMETER One or more of the attributes has an unsupported value.
+ @retval RETURN_DEVICE_ERROR The serial device is not functioning correctly.
+
+**/
+RETURN_STATUS
+EFIAPI
+SerialPortSetAttributes (
+ IN OUT UINT64 *BaudRate,
+ IN OUT UINT32 *ReceiveFifoDepth,
+ IN OUT UINT32 *Timeout,
+ IN OUT EFI_PARITY_TYPE *Parity,
+ IN OUT UINT8 *DataBits,
+ IN OUT EFI_STOP_BITS_TYPE *StopBits
+ );
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/SmbusLib.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/SmbusLib.h
new file mode 100644
index 0000000000..13adfb4f69
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/SmbusLib.h
@@ -0,0 +1,490 @@
+/** @file
+ Provides library functions to access SMBUS devices. Libraries of this class
+ must be ported to a specific SMBUS controller.
+
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __SMBUS_LIB__
+#define __SMBUS_LIB__
+
+/**
+ Macro that converts SMBUS slave address, SMBUS command, SMBUS data length,
+ and PEC to a value that can be passed to the SMBUS Library functions.
+
+ Computes an address that is compatible with the SMBUS Library functions.
+ The unused upper bits of SlaveAddress, Command, and Length are stripped
+ prior to the generation of the address.
+
+ @param SlaveAddress SMBUS Slave Address. Range 0..127.
+ @param Command SMBUS Command. Range 0..255.
+ @param Length SMBUS Data Length. Range 0..32.
+ @param Pec TRUE if Packet Error Checking is enabled. Otherwise FALSE.
+
+**/
+#define SMBUS_LIB_ADDRESS(SlaveAddress, Command, Length, Pec) \
+ ( ((Pec) ? BIT22: 0) | \
+ (((SlaveAddress) & 0x7f) << 1) | \
+ (((Command) & 0xff) << 8) | \
+ (((Length) & 0x3f) << 16) \
+ )
+
+/**
+ Macro that returns the SMBUS Slave Address value from an SmBusAddress Parameter value.
+
+ @param SmBusAddress Address that encodes the SMBUS Slave Address, SMBUS Command, SMBUS Data Length, and PEC
+**/
+#define SMBUS_LIB_SLAVE_ADDRESS(SmBusAddress) (((SmBusAddress) >> 1) & 0x7f)
+
+/**
+ Macro that returns the SMBUS Command value from an SmBusAddress Parameter value.
+
+ @param SmBusAddress Address that encodes the SMBUS Slave Address, SMBUS Command, SMBUS Data Length, and PEC
+**/
+#define SMBUS_LIB_COMMAND(SmBusAddress) (((SmBusAddress) >> 8) & 0xff)
+
+/**
+ Macro that returns the SMBUS Data Length value from an SmBusAddress Parameter value.
+
+ @param SmBusAddress Address that encodes the SMBUS Slave Address, SMBUS Command, SMBUS Data Length, and PEC
+**/
+#define SMBUS_LIB_LENGTH(SmBusAddress) (((SmBusAddress) >> 16) & 0x3f)
+
+/**
+ Macro that returns the SMBUS PEC value from an SmBusAddress Parameter value.
+
+ @param SmBusAddress Address that encodes the SMBUS Slave Address, SMBUS Command, SMBUS Data Length, and PEC
+**/
+#define SMBUS_LIB_PEC(SmBusAddress) ((BOOLEAN) (((SmBusAddress) & BIT22) != 0))
+
+/**
+ Macro that returns the set of reserved bits from an SmBusAddress Parameter value.
+
+ @param SmBusAddress Address that encodes the SMBUS Slave Address, SMBUS Command, SMBUS Data Length, and PEC
+**/
+#define SMBUS_LIB_RESERVED(SmBusAddress) ((SmBusAddress) & ~(BIT23 - 2))
+
+/**
+ Executes an SMBUS quick read command.
+
+ Executes an SMBUS quick read command on the SMBUS device specified by SmBusAddress.
+ Only the SMBUS slave address field of SmBusAddress is required.
+ If Status is not NULL, then the status of the executed command is returned in Status.
+ If PEC is set in SmBusAddress, then ASSERT().
+ If Command in SmBusAddress is not zero, then ASSERT().
+ If Length in SmBusAddress is not zero, then ASSERT().
+ If any reserved bits of SmBusAddress are set, then ASSERT().
+
+ @param SmBusAddress Address that encodes the SMBUS Slave Address,
+ SMBUS Command, SMBUS Data Length, and PEC.
+ @param Status Return status for the executed command.
+ This is an optional parameter and may be NULL.
+ RETURN_SUCCESS The SMBUS command was executed.
+ RETURN_TIMEOUT A timeout occurred while executing the SMBUS command.
+ RETURN_DEVICE_ERROR The request was not completed because a failure
+ reflected in the Host Status Register bit. Device errors are a result
+ of a transaction collision, illegal command field, unclaimed cycle
+ (host initiated), or bus errors (collisions).
+ RETURN_UNSUPPORTED The SMBus operation is not supported.
+
+**/
+VOID
+EFIAPI
+SmBusQuickRead (
+ IN UINTN SmBusAddress,
+ OUT RETURN_STATUS *Status OPTIONAL
+ );
+
+/**
+ Executes an SMBUS quick write command.
+
+ Executes an SMBUS quick write command on the SMBUS device specified by SmBusAddress.
+ Only the SMBUS slave address field of SmBusAddress is required.
+ If Status is not NULL, then the status of the executed command is returned in Status.
+ If PEC is set in SmBusAddress, then ASSERT().
+ If Command in SmBusAddress is not zero, then ASSERT().
+ If Length in SmBusAddress is not zero, then ASSERT().
+ If any reserved bits of SmBusAddress are set, then ASSERT().
+
+ @param SmBusAddress Address that encodes the SMBUS Slave Address,
+ SMBUS Command, SMBUS Data Length, and PEC.
+ @param Status Return status for the executed command.
+ This is an optional parameter and may be NULL.
+ RETURN_SUCCESS The SMBUS command was executed.
+ RETURN_TIMEOUT A timeout occurred while executing the SMBUS command.
+ RETURN_DEVICE_ERROR The request was not completed because a failure
+ reflected in the Host Status Register bit. Device errors are a result
+ of a transaction collision, illegal command field, unclaimed cycle
+ (host initiated), or bus errors (collisions).
+ RETURN_UNSUPPORTED The SMBus operation is not supported.
+
+**/
+VOID
+EFIAPI
+SmBusQuickWrite (
+ IN UINTN SmBusAddress,
+ OUT RETURN_STATUS *Status OPTIONAL
+ );
+
+/**
+ Executes an SMBUS receive byte command.
+
+ Executes an SMBUS receive byte command on the SMBUS device specified by SmBusAddress.
+ Only the SMBUS slave address field of SmBusAddress is required.
+ The byte received from the SMBUS is returned.
+ If Status is not NULL, then the status of the executed command is returned in Status.
+ If Command in SmBusAddress is not zero, then ASSERT().
+ If Length in SmBusAddress is not zero, then ASSERT().
+ If any reserved bits of SmBusAddress are set, then ASSERT().
+
+ @param SmBusAddress Address that encodes the SMBUS Slave Address,
+ SMBUS Command, SMBUS Data Length, and PEC.
+ @param Status Return status for the executed command.
+ This is an optional parameter and may be NULL.
+ RETURN_SUCCESS The SMBUS command was executed.
+ RETURN_TIMEOUT A timeout occurred while executing the SMBUS command.
+ RETURN_DEVICE_ERROR The request was not completed because a failure
+ reflected in the Host Status Register bit. Device errors are a result
+ of a transaction collision, illegal command field, unclaimed cycle
+ (host initiated), or bus errors (collisions).
+ RETURN_CRC_ERROR The checksum is not correct (PEC is incorrect)
+ RETURN_UNSUPPORTED The SMBus operation is not supported.
+
+ @return The byte received from the SMBUS.
+
+**/
+UINT8
+EFIAPI
+SmBusReceiveByte (
+ IN UINTN SmBusAddress,
+ OUT RETURN_STATUS *Status OPTIONAL
+ );
+
+/**
+ Executes an SMBUS send byte command.
+
+ Executes an SMBUS send byte command on the SMBUS device specified by SmBusAddress.
+ The byte specified by Value is sent.
+ Only the SMBUS slave address field of SmBusAddress is required. Value is returned.
+ If Status is not NULL, then the status of the executed command is returned in Status.
+ If Command in SmBusAddress is not zero, then ASSERT().
+ If Length in SmBusAddress is not zero, then ASSERT().
+ If any reserved bits of SmBusAddress are set, then ASSERT().
+
+ @param SmBusAddress Address that encodes the SMBUS Slave Address,
+ SMBUS Command, SMBUS Data Length, and PEC.
+ @param Value The 8-bit value to send.
+ @param Status Return status for the executed command.
+ This is an optional parameter and may be NULL.
+ RETURN_SUCCESS The SMBUS command was executed.
+ RETURN_TIMEOUT A timeout occurred while executing the SMBUS command.
+ RETURN_DEVICE_ERROR The request was not completed because a failure
+ reflected in the Host Status Register bit. Device errors are a result
+ of a transaction collision, illegal command field, unclaimed cycle
+ (host initiated), or bus errors (collisions).
+ RETURN_CRC_ERROR The checksum is not correct (PEC is incorrect)
+ RETURN_UNSUPPORTED The SMBus operation is not supported.
+
+ @return The parameter of Value.
+
+**/
+UINT8
+EFIAPI
+SmBusSendByte (
+ IN UINTN SmBusAddress,
+ IN UINT8 Value,
+ OUT RETURN_STATUS *Status OPTIONAL
+ );
+
+/**
+ Executes an SMBUS read data byte command.
+
+ Executes an SMBUS read data byte command on the SMBUS device specified by SmBusAddress.
+ Only the SMBUS slave address and SMBUS command fields of SmBusAddress are required.
+ The 8-bit value read from the SMBUS is returned.
+ If Status is not NULL, then the status of the executed command is returned in Status.
+ If Length in SmBusAddress is not zero, then ASSERT().
+ If any reserved bits of SmBusAddress are set, then ASSERT().
+
+ @param SmBusAddress Address that encodes the SMBUS Slave Address,
+ SMBUS Command, SMBUS Data Length, and PEC.
+ @param Status Return status for the executed command.
+ This is an optional parameter and may be NULL.
+ RETURN_SUCCESS The SMBUS command was executed.
+ RETURN_TIMEOUT A timeout occurred while executing the SMBUS command.
+ RETURN_DEVICE_ERROR The request was not completed because a failure
+ reflected in the Host Status Register bit. Device errors are a result
+ of a transaction collision, illegal command field, unclaimed cycle
+ (host initiated), or bus errors (collisions).
+ RETURN_CRC_ERROR The checksum is not correct (PEC is incorrect)
+ RETURN_UNSUPPORTED The SMBus operation is not supported.
+
+ @return The byte read from the SMBUS.
+
+**/
+UINT8
+EFIAPI
+SmBusReadDataByte (
+ IN UINTN SmBusAddress,
+ OUT RETURN_STATUS *Status OPTIONAL
+ );
+
+/**
+ Executes an SMBUS write data byte command.
+
+ Executes an SMBUS write data byte command on the SMBUS device specified by SmBusAddress.
+ The 8-bit value specified by Value is written.
+ Only the SMBUS slave address and SMBUS command fields of SmBusAddress are required.
+ Value is returned.
+ If Status is not NULL, then the status of the executed command is returned in Status.
+ If Length in SmBusAddress is not zero, then ASSERT().
+ If any reserved bits of SmBusAddress are set, then ASSERT().
+
+ @param SmBusAddress Address that encodes the SMBUS Slave Address,
+ SMBUS Command, SMBUS Data Length, and PEC.
+ @param Value The 8-bit value to write.
+ @param Status Return status for the executed command.
+ This is an optional parameter and may be NULL.
+ RETURN_SUCCESS The SMBUS command was executed.
+ RETURN_TIMEOUT A timeout occurred while executing the SMBUS command.
+ RETURN_DEVICE_ERROR The request was not completed because a failure
+ reflected in the Host Status Register bit. Device errors are a result
+ of a transaction collision, illegal command field, unclaimed cycle
+ (host initiated), or bus errors (collisions).
+ RETURN_CRC_ERROR The checksum is not correct (PEC is incorrect)
+ RETURN_UNSUPPORTED The SMBus operation is not supported.
+
+ @return The parameter of Value.
+
+**/
+UINT8
+EFIAPI
+SmBusWriteDataByte (
+ IN UINTN SmBusAddress,
+ IN UINT8 Value,
+ OUT RETURN_STATUS *Status OPTIONAL
+ );
+
+/**
+ Executes an SMBUS read data word command.
+
+ Executes an SMBUS read data word command on the SMBUS device specified by SmBusAddress.
+ Only the SMBUS slave address and SMBUS command fields of SmBusAddress are required.
+ The 16-bit value read from the SMBUS is returned.
+ If Status is not NULL, then the status of the executed command is returned in Status.
+ If Length in SmBusAddress is not zero, then ASSERT().
+ If any reserved bits of SmBusAddress are set, then ASSERT().
+
+ @param SmBusAddress Address that encodes the SMBUS Slave Address,
+ SMBUS Command, SMBUS Data Length, and PEC.
+ @param Status Return status for the executed command.
+ This is an optional parameter and may be NULL.
+ RETURN_SUCCESS The SMBUS command was executed.
+ RETURN_TIMEOUT A timeout occurred while executing the SMBUS command.
+ RETURN_DEVICE_ERROR The request was not completed because a failure
+ reflected in the Host Status Register bit. Device errors are a result
+ of a transaction collision, illegal command field, unclaimed cycle
+ (host initiated), or bus errors (collisions).
+ RETURN_CRC_ERROR The checksum is not correct (PEC is incorrect)
+ RETURN_UNSUPPORTED The SMBus operation is not supported.
+
+ @return The byte read from the SMBUS.
+
+**/
+UINT16
+EFIAPI
+SmBusReadDataWord (
+ IN UINTN SmBusAddress,
+ OUT RETURN_STATUS *Status OPTIONAL
+ );
+
+/**
+ Executes an SMBUS write data word command.
+
+ Executes an SMBUS write data word command on the SMBUS device specified by SmBusAddress.
+ The 16-bit value specified by Value is written.
+ Only the SMBUS slave address and SMBUS command fields of SmBusAddress are required.
+ Value is returned.
+ If Status is not NULL, then the status of the executed command is returned in Status.
+ If Length in SmBusAddress is not zero, then ASSERT().
+ If any reserved bits of SmBusAddress are set, then ASSERT().
+
+ @param SmBusAddress Address that encodes the SMBUS Slave Address,
+ SMBUS Command, SMBUS Data Length, and PEC.
+ @param Value The 16-bit value to write.
+ @param Status Return status for the executed command.
+ This is an optional parameter and may be NULL.
+ RETURN_SUCCESS The SMBUS command was executed.
+ RETURN_TIMEOUT A timeout occurred while executing the SMBUS command.
+ RETURN_DEVICE_ERROR The request was not completed because a failure
+ reflected in the Host Status Register bit. Device errors are a result
+ of a transaction collision, illegal command field, unclaimed cycle
+ (host initiated), or bus errors (collisions).
+ RETURN_CRC_ERROR The checksum is not correct (PEC is incorrect)
+ RETURN_UNSUPPORTED The SMBus operation is not supported.
+
+ @return The parameter of Value.
+
+**/
+UINT16
+EFIAPI
+SmBusWriteDataWord (
+ IN UINTN SmBusAddress,
+ IN UINT16 Value,
+ OUT RETURN_STATUS *Status OPTIONAL
+ );
+
+/**
+ Executes an SMBUS process call command.
+
+ Executes an SMBUS process call command on the SMBUS device specified by SmBusAddress.
+ The 16-bit value specified by Value is written.
+ Only the SMBUS slave address and SMBUS command fields of SmBusAddress are required.
+ The 16-bit value returned by the process call command is returned.
+ If Status is not NULL, then the status of the executed command is returned in Status.
+ If Length in SmBusAddress is not zero, then ASSERT().
+ If any reserved bits of SmBusAddress are set, then ASSERT().
+
+ @param SmBusAddress Address that encodes the SMBUS Slave Address,
+ SMBUS Command, SMBUS Data Length, and PEC.
+ @param Value The 16-bit value to write.
+ @param Status Return status for the executed command.
+ This is an optional parameter and may be NULL.
+ RETURN_SUCCESS The SMBUS command was executed.
+ RETURN_TIMEOUT A timeout occurred while executing the SMBUS command.
+ RETURN_DEVICE_ERROR The request was not completed because a failure
+ reflected in the Host Status Register bit. Device errors are a result
+ of a transaction collision, illegal command field, unclaimed cycle
+ (host initiated), or bus errors (collisions).
+ RETURN_CRC_ERROR The checksum is not correct (PEC is incorrect)
+ RETURN_UNSUPPORTED The SMBus operation is not supported.
+
+ @return The 16-bit value returned by the process call command.
+
+**/
+UINT16
+EFIAPI
+SmBusProcessCall (
+ IN UINTN SmBusAddress,
+ IN UINT16 Value,
+ OUT RETURN_STATUS *Status OPTIONAL
+ );
+
+/**
+ Executes an SMBUS read block command.
+
+ Executes an SMBUS read block command on the SMBUS device specified by SmBusAddress.
+ Only the SMBUS slave address and SMBUS command fields of SmBusAddress are required.
+ Bytes are read from the SMBUS and stored in Buffer.
+ The number of bytes read is returned, and will never return a value larger than 32-bytes.
+ If Status is not NULL, then the status of the executed command is returned in Status.
+ It is the caller's responsibility to make sure Buffer is large enough for the total number of bytes read.
+ SMBUS supports a maximum transfer size of 32 bytes, so Buffer does not need to be any larger than 32 bytes.
+ If Length in SmBusAddress is not zero, then ASSERT().
+ If Buffer is NULL, then ASSERT().
+ If any reserved bits of SmBusAddress are set, then ASSERT().
+
+ @param SmBusAddress Address that encodes the SMBUS Slave Address,
+ SMBUS Command, SMBUS Data Length, and PEC.
+ @param Buffer Pointer to the buffer to store the bytes read from the SMBUS.
+ @param Status Return status for the executed command.
+ This is an optional parameter and may be NULL.
+ RETURN_SUCCESS The SMBUS command was executed.
+ RETURN_TIMEOUT A timeout occurred while executing the SMBUS command.
+ RETURN_DEVICE_ERROR The request was not completed because a failure
+ reflected in the Host Status Register bit. Device errors are a result
+ of a transaction collision, illegal command field, unclaimed cycle
+ (host initiated), or bus errors (collisions).
+ RETURN_CRC_ERROR The checksum is not correct (PEC is incorrect)
+ RETURN_UNSUPPORTED The SMBus operation is not supported.
+
+ @return The number of bytes read.
+
+**/
+UINTN
+EFIAPI
+SmBusReadBlock (
+ IN UINTN SmBusAddress,
+ OUT VOID *Buffer,
+ OUT RETURN_STATUS *Status OPTIONAL
+ );
+
+/**
+ Executes an SMBUS write block command.
+
+ Executes an SMBUS write block command on the SMBUS device specified by SmBusAddress.
+ The SMBUS slave address, SMBUS command, and SMBUS length fields of SmBusAddress are required.
+ Bytes are written to the SMBUS from Buffer.
+ The number of bytes written is returned, and will never return a value larger than 32-bytes.
+ If Status is not NULL, then the status of the executed command is returned in Status.
+ If Length in SmBusAddress is zero or greater than 32, then ASSERT().
+ If Buffer is NULL, then ASSERT().
+ If any reserved bits of SmBusAddress are set, then ASSERT().
+
+ @param SmBusAddress Address that encodes the SMBUS Slave Address,
+ SMBUS Command, SMBUS Data Length, and PEC.
+ @param Buffer Pointer to the buffer to store the bytes read from the SMBUS.
+ @param Status Return status for the executed command.
+ This is an optional parameter and may be NULL.
+ RETURN_TIMEOUT A timeout occurred while executing the SMBUS command.
+ RETURN_DEVICE_ERROR The request was not completed because a failure
+ reflected in the Host Status Register bit. Device errors are a result
+ of a transaction collision, illegal command field, unclaimed cycle
+ (host initiated), or bus errors (collisions).
+ RETURN_CRC_ERROR The checksum is not correct (PEC is incorrect)
+ RETURN_UNSUPPORTED The SMBus operation is not supported.
+
+ @return The number of bytes written.
+
+**/
+UINTN
+EFIAPI
+SmBusWriteBlock (
+ IN UINTN SmBusAddress,
+ OUT VOID *Buffer,
+ OUT RETURN_STATUS *Status OPTIONAL
+ );
+
+/**
+ Executes an SMBUS block process call command.
+
+ Executes an SMBUS block process call command on the SMBUS device specified by SmBusAddress.
+ The SMBUS slave address, SMBUS command, and SMBUS length fields of SmBusAddress are required.
+ Bytes are written to the SMBUS from WriteBuffer. Bytes are then read from the SMBUS into ReadBuffer.
+ If Status is not NULL, then the status of the executed command is returned in Status.
+ It is the caller's responsibility to make sure ReadBuffer is large enough for the total number of bytes read.
+ SMBUS supports a maximum transfer size of 32 bytes, so Buffer does not need to be any larger than 32 bytes.
+ If Length in SmBusAddress is zero or greater than 32, then ASSERT().
+ If WriteBuffer is NULL, then ASSERT().
+ If ReadBuffer is NULL, then ASSERT().
+ If any reserved bits of SmBusAddress are set, then ASSERT().
+
+ @param SmBusAddress Address that encodes the SMBUS Slave Address,
+ SMBUS Command, SMBUS Data Length, and PEC.
+ @param WriteBuffer Pointer to the buffer of bytes to write to the SMBUS.
+ @param ReadBuffer Pointer to the buffer of bytes to read from the SMBUS.
+ @param Status Return status for the executed command.
+ This is an optional parameter and may be NULL.
+ RETURN_TIMEOUT A timeout occurred while executing the SMBUS command.
+ RETURN_DEVICE_ERROR The request was not completed because a failure
+ reflected in the Host Status Register bit. Device errors are a result
+ of a transaction collision, illegal command field, unclaimed cycle
+ (host initiated), or bus errors (collisions).
+ RETURN_CRC_ERROR The checksum is not correct (PEC is incorrect)
+ RETURN_UNSUPPORTED The SMBus operation is not supported.
+
+ @return The number of bytes written.
+
+**/
+UINTN
+EFIAPI
+SmBusBlockProcessCall (
+ IN UINTN SmBusAddress,
+ IN VOID *WriteBuffer,
+ OUT VOID *ReadBuffer,
+ OUT RETURN_STATUS *Status OPTIONAL
+ );
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/SmiHandlerProfileLib.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/SmiHandlerProfileLib.h
new file mode 100644
index 0000000000..2dcfca8193
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/SmiHandlerProfileLib.h
@@ -0,0 +1,81 @@
+/** @file
+ Provides services to log the SMI handler registration.
+
+ This API provides services for the SMM Child Dispatch Protocols provider,
+ to register SMI handler information to SmmCore.
+
+ NOTE:
+ There is no need to update the consumers of SMST->SmiHandlerRegister() or
+ the consumers of SMM Child Dispatch Protocols.
+ The SmmCore (who produces SMST) should have ability to register such
+ information directly.
+ The SmmChildDispatcher (who produces SMM Child Dispatch Protocols) should
+ be responsible to call the services to register information to SMM Core.
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __SMI_HANDLER_PROFILE_LIB_H__
+#define __SMI_HANDLER_PROFILE_LIB_H__
+
+#include
+
+/**
+ This function is called by SmmChildDispatcher module to report
+ a new SMI handler is registered, to SmmCore.
+
+ @param HandlerGuid The GUID to identify the type of the handler.
+ For the SmmChildDispatch protocol, the HandlerGuid
+ must be the GUID of SmmChildDispatch protocol.
+ @param Handler The SMI handler.
+ @param CallerAddress The address of the module who registers the SMI handler.
+ @param Context The context of the SMI handler.
+ For the SmmChildDispatch protocol, the Context
+ must match the one defined for SmmChildDispatch protocol.
+ @param ContextSize The size of the context in bytes.
+ For the SmmChildDispatch protocol, the Context
+ must match the one defined for SmmChildDispatch protocol.
+
+ @retval EFI_SUCCESS The information is recorded.
+ @retval EFI_UNSUPPORTED The feature is unsupported.
+ @retval EFI_OUT_OF_RESOURCES There is no enough resource to record the information.
+**/
+EFI_STATUS
+EFIAPI
+SmiHandlerProfileRegisterHandler (
+ IN EFI_GUID *HandlerGuid,
+ IN EFI_SMM_HANDLER_ENTRY_POINT2 Handler,
+ IN PHYSICAL_ADDRESS CallerAddress,
+ IN VOID *Context OPTIONAL,
+ IN UINTN ContextSize OPTIONAL
+ );
+
+/**
+ This function is called by SmmChildDispatcher module to report
+ an existing SMI handler is unregistered, to SmmCore.
+
+ @param HandlerGuid The GUID to identify the type of the handler.
+ For the SmmChildDispatch protocol, the HandlerGuid
+ must be the GUID of SmmChildDispatch protocol.
+ @param Handler The SMI handler.
+ @param Context The context of the SMI handler.
+ If it is NOT NULL, it will be used to check what is registered.
+ @param ContextSize The size of the context in bytes.
+ If Context is NOT NULL, it will be used to check what is registered.
+
+ @retval EFI_SUCCESS The original record is removed.
+ @retval EFI_UNSUPPORTED The feature is unsupported.
+ @retval EFI_NOT_FOUND There is no record for the HandlerGuid and handler.
+**/
+EFI_STATUS
+EFIAPI
+SmiHandlerProfileUnregisterHandler (
+ IN EFI_GUID *HandlerGuid,
+ IN EFI_SMM_HANDLER_ENTRY_POINT2 Handler,
+ IN VOID *Context OPTIONAL,
+ IN UINTN ContextSize OPTIONAL
+ );
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/SmmCpuRendezvousLib.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/SmmCpuRendezvousLib.h
new file mode 100644
index 0000000000..da56d9694d
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/SmmCpuRendezvousLib.h
@@ -0,0 +1,27 @@
+/** @file
+ SMM CPU Rendezvous library header file.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef SMM_CPU_RENDEZVOUS_H_
+#define SMM_CPU_RENDEZVOUS_H_
+
+/**
+ This routine wait for all AP processors to arrive in SMM.
+
+ @param[in] BlockingMode Blocking mode or non-blocking mode.
+
+ @retval EFI_SUCCESS All processors checked in to SMM.
+ @retval EFI_TIMEOUT Wait for all APs until timeout.
+
+**/
+EFI_STATUS
+EFIAPI
+SmmWaitForAllProcessor (
+ IN BOOLEAN BlockingMode
+ );
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/SmmIoLib.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/SmmIoLib.h
new file mode 100644
index 0000000000..0da8ffc198
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/SmmIoLib.h
@@ -0,0 +1,35 @@
+/** @file
+ Provides services for SMM IO Operation.
+
+ The SMM IO Library provides function for checking if IO resource is accessible inside of SMM.
+
+ Copyright (c) 2017, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _SMM_IO_LIB_H_
+#define _SMM_IO_LIB_H_
+
+/**
+ This function check if the MMIO resource is valid per processor architecture and
+ valid per platform design.
+
+ @param BaseAddress The MMIO start address to be checked.
+ @param Length The MMIO length to be checked.
+ @param Owner A GUID representing the owner of the resource.
+ This GUID may be used by producer to correlate the device ownership of the resource.
+ NULL means no specific owner.
+
+ @retval TRUE This MMIO resource is valid per processor architecture and valid per platform design.
+ @retval FALSE This MMIO resource is not valid per processor architecture or valid per platform design.
+**/
+BOOLEAN
+EFIAPI
+SmmIsMmioValid (
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,
+ IN UINT64 Length,
+ IN EFI_GUID *Owner OPTIONAL
+ );
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/SmmLib.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/SmmLib.h
new file mode 100644
index 0000000000..7a8cf74af2
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/SmmLib.h
@@ -0,0 +1,80 @@
+/** @file
+ Library class name: SmmLib
+
+ SMM Library Services that abstracts both S/W SMI generation and detection.
+
+ Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __SMM_LIB_H__
+#define __SMM_LIB_H__
+
+/**
+ Triggers an SMI at boot time.
+
+ This function triggers a software SMM interrupt at boot time.
+
+**/
+VOID
+EFIAPI
+TriggerBootServiceSoftwareSmi (
+ VOID
+ );
+
+/**
+ Triggers an SMI at run time.
+
+ This function triggers a software SMM interrupt at run time.
+
+**/
+VOID
+EFIAPI
+TriggerRuntimeSoftwareSmi (
+ VOID
+ );
+
+/**
+ Test if a boot time software SMI happened.
+
+ This function tests if a software SMM interrupt happened. If a software SMM interrupt happened and
+ it was triggered at boot time, it returns TRUE. Otherwise, it returns FALSE.
+
+ @retval TRUE A software SMI triggered at boot time happened.
+ @retval FALSE No software SMI happened, or the software SMI was triggered at run time.
+
+**/
+BOOLEAN
+EFIAPI
+IsBootServiceSoftwareSmi (
+ VOID
+ );
+
+/**
+ Test if a run time software SMI happened.
+
+ This function tests if a software SMM interrupt happened. If a software SMM interrupt happened and
+ it was triggered at run time, it returns TRUE. Otherwise, it returns FALSE.
+
+ @retval TRUE A software SMI triggered at run time happened.
+ @retval FALSE No software SMI happened or the software SMI was triggered at boot time.
+
+**/
+BOOLEAN
+EFIAPI
+IsRuntimeSoftwareSmi (
+ VOID
+ );
+
+/**
+ Clear APM SMI Status Bit; Set the EOS bit.
+
+**/
+VOID
+EFIAPI
+ClearSmi (
+ VOID
+ );
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/SmmMemLib.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/SmmMemLib.h
new file mode 100644
index 0000000000..feb81d11c9
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/SmmMemLib.h
@@ -0,0 +1,132 @@
+/** @file
+ Provides services for SMM Memory Operation.
+
+ The SMM Mem Library provides function for checking if buffer is outside SMRAM and valid.
+ It also provides functions for copy data from SMRAM to non-SMRAM, from non-SMRAM to SMRAM,
+ from non-SMRAM to non-SMRAM, or set data in non-SMRAM.
+
+ Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _SMM_MEM_LIB_H_
+#define _SMM_MEM_LIB_H_
+
+/**
+ This function check if the buffer is valid per processor architecture and not overlap with SMRAM.
+
+ @param Buffer The buffer start address to be checked.
+ @param Length The buffer length to be checked.
+
+ @retval TRUE This buffer is valid per processor architecture and not overlap with SMRAM.
+ @retval FALSE This buffer is not valid per processor architecture or overlap with SMRAM.
+**/
+BOOLEAN
+EFIAPI
+SmmIsBufferOutsideSmmValid (
+ IN EFI_PHYSICAL_ADDRESS Buffer,
+ IN UINT64 Length
+ );
+
+/**
+ Copies a source buffer (non-SMRAM) to a destination buffer (SMRAM).
+
+ This function copies a source buffer (non-SMRAM) to a destination buffer (SMRAM).
+ It checks if source buffer is valid per processor architecture and not overlap with SMRAM.
+ If the check passes, it copies memory and returns EFI_SUCCESS.
+ If the check fails, it return EFI_SECURITY_VIOLATION.
+ The implementation must be reentrant.
+
+ @param DestinationBuffer The pointer to the destination buffer of the memory copy.
+ @param SourceBuffer The pointer to the source buffer of the memory copy.
+ @param Length The number of bytes to copy from SourceBuffer to DestinationBuffer.
+
+ @retval EFI_SECURITY_VIOLATION The SourceBuffer is invalid per processor architecture or overlap with SMRAM.
+ @retval EFI_SUCCESS Memory is copied.
+
+**/
+EFI_STATUS
+EFIAPI
+SmmCopyMemToSmram (
+ OUT VOID *DestinationBuffer,
+ IN CONST VOID *SourceBuffer,
+ IN UINTN Length
+ );
+
+/**
+ Copies a source buffer (SMRAM) to a destination buffer (NON-SMRAM).
+
+ This function copies a source buffer (non-SMRAM) to a destination buffer (SMRAM).
+ It checks if destination buffer is valid per processor architecture and not overlap with SMRAM.
+ If the check passes, it copies memory and returns EFI_SUCCESS.
+ If the check fails, it returns EFI_SECURITY_VIOLATION.
+ The implementation must be reentrant.
+
+ @param DestinationBuffer The pointer to the destination buffer of the memory copy.
+ @param SourceBuffer The pointer to the source buffer of the memory copy.
+ @param Length The number of bytes to copy from SourceBuffer to DestinationBuffer.
+
+ @retval EFI_SECURITY_VIOLATION The DestinationBuffer is invalid per processor architecture or overlap with SMRAM.
+ @retval EFI_SUCCESS Memory is copied.
+
+**/
+EFI_STATUS
+EFIAPI
+SmmCopyMemFromSmram (
+ OUT VOID *DestinationBuffer,
+ IN CONST VOID *SourceBuffer,
+ IN UINTN Length
+ );
+
+/**
+ Copies a source buffer (NON-SMRAM) to a destination buffer (NON-SMRAM).
+
+ This function copies a source buffer (non-SMRAM) to a destination buffer (SMRAM).
+ It checks if source buffer and destination buffer are valid per processor architecture and not overlap with SMRAM.
+ If the check passes, it copies memory and returns EFI_SUCCESS.
+ If the check fails, it returns EFI_SECURITY_VIOLATION.
+ The implementation must be reentrant, and it must handle the case where source buffer overlaps destination buffer.
+
+ @param DestinationBuffer The pointer to the destination buffer of the memory copy.
+ @param SourceBuffer The pointer to the source buffer of the memory copy.
+ @param Length The number of bytes to copy from SourceBuffer to DestinationBuffer.
+
+ @retval EFI_SECURITY_VIOLATION The DestinationBuffer is invalid per processor architecture or overlap with SMRAM.
+ @retval EFI_SECURITY_VIOLATION The SourceBuffer is invalid per processor architecture or overlap with SMRAM.
+ @retval EFI_SUCCESS Memory is copied.
+
+**/
+EFI_STATUS
+EFIAPI
+SmmCopyMem (
+ OUT VOID *DestinationBuffer,
+ IN CONST VOID *SourceBuffer,
+ IN UINTN Length
+ );
+
+/**
+ Fills a target buffer (NON-SMRAM) with a byte value.
+
+ This function fills a target buffer (non-SMRAM) with a byte value.
+ It checks if target buffer is valid per processor architecture and not overlap with SMRAM.
+ If the check passes, it fills memory and returns EFI_SUCCESS.
+ If the check fails, it returns EFI_SECURITY_VIOLATION.
+
+ @param Buffer The memory to set.
+ @param Length The number of bytes to set.
+ @param Value The value with which to fill Length bytes of Buffer.
+
+ @retval EFI_SECURITY_VIOLATION The Buffer is invalid per processor architecture or overlap with SMRAM.
+ @retval EFI_SUCCESS Memory is set.
+
+**/
+EFI_STATUS
+EFIAPI
+SmmSetMem (
+ OUT VOID *Buffer,
+ IN UINTN Length,
+ IN UINT8 Value
+ );
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/SmmPeriodicSmiLib.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/SmmPeriodicSmiLib.h
new file mode 100644
index 0000000000..39408d92c5
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/SmmPeriodicSmiLib.h
@@ -0,0 +1,178 @@
+/** @file
+ Provides services to enable and disable periodic SMI handlers.
+
+Copyright (c) 2011 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __PERIODIC_SMI_LIB_H__
+#define __PERIODIC_SMI_LIB_H__
+
+#define PERIODIC_SMI_LIBRARY_ANY_CPU 0xffffffff
+
+/**
+ This function returns a pointer to a table of supported periodic
+ SMI tick periods in 100 ns units sorted from largest to smallest.
+ The table contains a array of UINT64 values terminated by a tick
+ period value of 0. The returned table must be treated as read-only
+ data and must not be freed.
+
+ @return A pointer to a table of UINT64 tick period values in
+ 100ns units sorted from largest to smallest terminated
+ by a tick period of 0.
+
+**/
+UINT64 *
+EFIAPI
+PeriodicSmiSupportedTickPeriod (
+ VOID
+ );
+
+/**
+ This function returns the time in 100ns units since the periodic SMI
+ handler function was called. If the periodic SMI handler was resumed
+ through PeriodicSmiYield(), then the time returned is the time in
+ 100ns units since PeriodicSmiYield() returned.
+
+ @return The actual time in 100ns units that the periodic SMI handler
+ has been executing. If this function is not called from within
+ an enabled periodic SMI handler, then 0 is returned.
+
+**/
+UINT64
+EFIAPI
+PeriodicSmiExecutionTime (
+ VOID
+ );
+
+/**
+ This function returns control back to the SMM Foundation. When the next
+ periodic SMI for the currently executing handler is triggered, the periodic
+ SMI handler will restarted from its registered DispatchFunction entry point.
+ If this function is not called from within an enabled periodic SMI handler,
+ then control is returned to the calling function.
+
+**/
+VOID
+EFIAPI
+PeriodicSmiExit (
+ VOID
+ );
+
+/**
+ This function yields control back to the SMM Foundation. When the next
+ periodic SMI for the currently executing handler is triggered, the periodic
+ SMI handler will be resumed and this function will return. Use of this
+ function requires a separate stack for the periodic SMI handler. A non zero
+ stack size must be specified in PeriodicSmiEnable() for this function to be
+ used.
+
+ If the stack size passed into PeriodicSmiEnable() was zero, the 0 is returned.
+
+ If this function is not called from within an enabled periodic SMI handler,
+ then 0 is returned.
+
+ @return The actual time in 100ns units elapsed since this function was
+ called. A value of 0 indicates an unknown amount of time.
+
+**/
+UINT64
+EFIAPI
+PeriodicSmiYield (
+ VOID
+ );
+
+/**
+ This function is a prototype for a periodic SMI handler function
+ that may be enabled with PeriodicSmiEnable() and disabled with
+ PeriodicSmiDisable().
+
+ @param[in] Context Content registered with PeriodicSmiEnable().
+ @param[in] ElapsedTime The actual time in 100ns units elapsed since
+ this function was called. A value of 0 indicates
+ an unknown amount of time.
+
+**/
+typedef
+VOID
+(EFIAPI *PERIODIC_SMI_LIBRARY_HANDLER)(
+ IN CONST VOID *Context OPTIONAL,
+ IN UINT64 ElapsedTime
+ );
+
+/**
+ This function enables a periodic SMI handler.
+
+ @param[in, out] DispatchHandle A pointer to the handle associated with the
+ enabled periodic SMI handler. This is an
+ optional parameter that may be NULL. If it is
+ NULL, then the handle will not be returned,
+ which means that the periodic SMI handler can
+ never be disabled.
+ @param[in] DispatchFunction A pointer to a periodic SMI handler function.
+ @param[in] Context Optional content to pass into DispatchFunction.
+ @param[in] TickPeriod The requested tick period in 100ns units that
+ control should be given to the periodic SMI
+ handler. Must be one of the supported values
+ returned by PeriodicSmiSupportedPickPeriod().
+ @param[in] Cpu Specifies the CPU that is required to execute
+ the periodic SMI handler. If Cpu is
+ PERIODIC_SMI_LIBRARY_ANY_CPU, then the periodic
+ SMI handler will always be executed on the SMST
+ CurrentlyExecutingCpu, which may vary across
+ periodic SMIs. If Cpu is between 0 and the SMST
+ NumberOfCpus, then the periodic SMI will always
+ be executed on the requested CPU.
+ @param[in] StackSize The size, in bytes, of the stack to allocate for
+ use by the periodic SMI handler. If 0, then the
+ default stack will be used.
+
+ @retval EFI_INVALID_PARAMETER DispatchFunction is NULL.
+ @retval EFI_UNSUPPORTED TickPeriod is not a supported tick period. The
+ supported tick periods can be retrieved using
+ PeriodicSmiSupportedTickPeriod().
+ @retval EFI_INVALID_PARAMETER Cpu is not PERIODIC_SMI_LIBRARY_ANY_CPU or in
+ the range 0 to SMST NumberOfCpus.
+ @retval EFI_OUT_OF_RESOURCES There are not enough resources to enable the
+ periodic SMI handler.
+ @retval EFI_OUT_OF_RESOURCES There are not enough resources to allocate the
+ stack specified by StackSize.
+ @retval EFI_SUCCESS The periodic SMI handler was enabled.
+
+**/
+EFI_STATUS
+EFIAPI
+PeriodicSmiEnable (
+ IN OUT EFI_HANDLE *DispatchHandle OPTIONAL,
+ IN PERIODIC_SMI_LIBRARY_HANDLER DispatchFunction,
+ IN CONST VOID *Context OPTIONAL,
+ IN UINT64 TickPeriod,
+ IN UINTN Cpu,
+ IN UINTN StackSize
+ );
+
+/**
+ This function disables a periodic SMI handler that has been previously
+ enabled with PeriodicSmiEnable().
+
+ @param[in] DispatchHandle A handle associated with a previously enabled periodic
+ SMI handler. This is an optional parameter that may
+ be NULL. If it is NULL, then the active periodic SMI
+ handlers is disabled.
+
+ @retval FALSE DispatchHandle is NULL and there is no active periodic SMI handler.
+ @retval FALSE The periodic SMI handler specified by DispatchHandle has
+ not been enabled with PeriodicSmiEnable().
+ @retval TRUE The periodic SMI handler specified by DispatchHandle has
+ been disabled. If DispatchHandle is NULL, then the active
+ periodic SMI handler has been disabled.
+
+**/
+BOOLEAN
+EFIAPI
+PeriodicSmiDisable (
+ IN EFI_HANDLE DispatchHandle OPTIONAL
+ );
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/SmmServicesTableLib.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/SmmServicesTableLib.h
new file mode 100644
index 0000000000..c1eb2a89be
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/SmmServicesTableLib.h
@@ -0,0 +1,37 @@
+/** @file
+ Provides a service to retrieve a pointer to the SMM Services Table.
+ Only available to SMM module types.
+
+Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __SMM_SERVICES_TABLE_LIB_H__
+#define __SMM_SERVICES_TABLE_LIB_H__
+
+#include
+
+///
+/// Cache pointer to the SMM Services Table
+///
+extern EFI_SMM_SYSTEM_TABLE2 *gSmst;
+
+/**
+ This function allows the caller to determine if the driver is executing in
+ System Management Mode(SMM).
+
+ This function returns TRUE if the driver is executing in SMM and FALSE if the
+ driver is not executing in SMM.
+
+ @retval TRUE The driver is executing in System Management Mode (SMM).
+ @retval FALSE The driver is not executing in System Management Mode (SMM).
+
+**/
+BOOLEAN
+EFIAPI
+InSmm (
+ VOID
+ );
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/StandaloneMmDriverEntryPoint.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/StandaloneMmDriverEntryPoint.h
new file mode 100644
index 0000000000..4e34ef7654
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/StandaloneMmDriverEntryPoint.h
@@ -0,0 +1,147 @@
+/** @file
+ Module entry point library for Standalone MM Drivers.
+
+Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.
+Copyright (c) 2016 - 2018, ARM Limited. All rights reserved.
+Copyright (c) 2018, Linaro, Limited. All rights reserved.
+
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __MODULE_ENTRY_POINT_H__
+#define __MODULE_ENTRY_POINT_H__
+
+///
+/// Declare the PI Specification Revision that this driver requires to execute
+/// correctly.
+///
+extern CONST UINT32 _gMmRevision;
+
+///
+/// Declare the number of unload handler in the image.
+///
+extern CONST UINT8 _gDriverUnloadImageCount;
+
+/**
+ The entry point of PE/COFF Image for a Standalone MM Driver.
+
+ This function is the entry point for a Standalone MM Driver.
+ This function must call ProcessLibraryConstructorList() and
+ ProcessModuleEntryPointList().
+ If the return status from ProcessModuleEntryPointList()
+ is an error status, then ProcessLibraryDestructorList() must be called.
+ The return value from ProcessModuleEntryPointList() is returned.
+ If _gMmRevision is not zero and MmSystemTable->Hdr.Revision is
+ less than _gMmRevision, then return EFI_INCOMPATIBLE_VERSION.
+
+ @param ImageHandle The image handle of the Standalone MM Driver.
+ @param MmSystemTable A pointer to the MM System Table.
+
+ @retval EFI_SUCCESS The Standalone MM Driver exited normally.
+ @retval EFI_INCOMPATIBLE_VERSION _gMmRevision is greater than
+ MmSystemTable->Hdr.Revision.
+ @retval Other Return value from
+ ProcessModuleEntryPointList().
+
+**/
+EFI_STATUS
+EFIAPI
+_ModuleEntryPoint (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_MM_SYSTEM_TABLE *MmSystemTable
+ );
+
+/**
+ Auto generated function that calls the library constructors for all of the
+ module's dependent libraries.
+
+ This function must be called by _ModuleEntryPoint().
+ This function calls the set of library constructors for the set of library
+ instances that a module depends on. This includes library instances that a
+ module depends on directly and library instances that a module depends on
+ indirectly through other libraries. This function is auto generated by build
+ tools and those build tools are responsible for collecting the set of library
+ instances, determine which ones have constructors, and calling the library
+ constructors in the proper order based upon each of the library instances own
+ dependencies.
+
+ @param ImageHandle The image handle of the Standalone MM Driver.
+ @param MmSystemTable A pointer to the MM System Table.
+
+**/
+VOID
+EFIAPI
+ProcessLibraryConstructorList (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_MM_SYSTEM_TABLE *MmSystemTable
+ );
+
+/**
+ Auto generated function that calls the library descructors for all of the
+ module's dependent libraries.
+
+ This function may be called by _ModuleEntryPoint().
+ This function calls the set of library destructors for the set of library
+ instances that a module depends on. This includes library instances that a
+ module depends on directly and library instances that a module depends on
+ indirectly through other libraries.
+ This function is auto generated by build tools and those build tools are
+ responsible for collecting the set of library instances, determine which ones
+ have destructors, and calling the library destructors in the proper order
+ based upon each of the library instances own dependencies.
+
+ @param ImageHandle The image handle of the Standalone MM Driver.
+ @param MmSystemTable A pointer to the MM System Table.
+
+**/
+VOID
+EFIAPI
+ProcessLibraryDestructorList (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_MM_SYSTEM_TABLE *MmSystemTable
+ );
+
+/**
+ Auto generated function that calls a set of module entry points.
+
+ This function must be called by _ModuleEntryPoint().
+ This function calls the set of module entry points.
+ This function is auto generated by build tools and those build tools are
+ responsible for collecting the module entry points and calling them in a
+ specified order.
+
+ @param ImageHandle The image handle of the Standalone MM Driver.
+ @param MmSystemTable A pointer to the MM System Table.
+
+ @retval EFI_SUCCESS The Standalone MM Driver executed normally.
+ @retval !EFI_SUCCESS The Standalone MM Driver failed to execute normally.
+**/
+EFI_STATUS
+EFIAPI
+ProcessModuleEntryPointList (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_MM_SYSTEM_TABLE *MmSystemTable
+ );
+
+/**
+ Autogenerated function that calls a set of module unload handlers.
+
+ This function must be called from the unload handler registered by _ModuleEntryPoint().
+ This function calls the set of module unload handlers.
+ This function is autogenerated by build tools and those build tools are responsible
+ for collecting the module unload handlers and calling them in a specified order.
+
+ @param ImageHandle The image handle of the DXE Driver, DXE Runtime Driver, DXE SMM Driver, or UEFI Driver.
+
+ @retval EFI_SUCCESS The unload handlers executed normally.
+ @retval !EFI_SUCCESS The unload handlers failed to execute normally.
+
+**/
+EFI_STATUS
+EFIAPI
+ProcessModuleUnloadList (
+ IN EFI_HANDLE ImageHandle
+ );
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/SynchronizationLib.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/SynchronizationLib.h
new file mode 100644
index 0000000000..07a98c237a
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/SynchronizationLib.h
@@ -0,0 +1,275 @@
+/** @file
+ Provides synchronization functions.
+
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __SYNCHRONIZATION_LIB__
+#define __SYNCHRONIZATION_LIB__
+
+///
+/// Definitions for SPIN_LOCK
+///
+typedef volatile UINTN SPIN_LOCK;
+
+/**
+ Retrieves the architecture-specific spin lock alignment requirements for
+ optimal spin lock performance.
+
+ This function retrieves the spin lock alignment requirements for optimal
+ performance on a given CPU architecture. The spin lock alignment is byte alignment.
+ It must be a power of two and is returned by this function. If there are no alignment
+ requirements, then 1 must be returned. The spin lock synchronization
+ functions must function correctly if the spin lock size and alignment values
+ returned by this function are not used at all. These values are hints to the
+ consumers of the spin lock synchronization functions to obtain optimal spin
+ lock performance.
+
+ @return The architecture-specific spin lock alignment.
+
+**/
+UINTN
+EFIAPI
+GetSpinLockProperties (
+ VOID
+ );
+
+/**
+ Initializes a spin lock to the released state and returns the spin lock.
+
+ This function initializes the spin lock specified by SpinLock to the released
+ state, and returns SpinLock. Optimal performance can be achieved by calling
+ GetSpinLockProperties() to determine the size and alignment requirements for
+ SpinLock.
+
+ If SpinLock is NULL, then ASSERT().
+
+ @param SpinLock A pointer to the spin lock to initialize to the released
+ state.
+
+ @return SpinLock in release state.
+
+**/
+SPIN_LOCK *
+EFIAPI
+InitializeSpinLock (
+ OUT SPIN_LOCK *SpinLock
+ );
+
+/**
+ Waits until a spin lock can be placed in the acquired state.
+
+ This function checks the state of the spin lock specified by SpinLock. If
+ SpinLock is in the released state, then this function places SpinLock in the
+ acquired state and returns SpinLock. Otherwise, this function waits
+ indefinitely for the spin lock to be released, and then places it in the
+ acquired state and returns SpinLock. All state transitions of SpinLock must
+ be performed using MP safe mechanisms.
+
+ If SpinLock is NULL, then ASSERT().
+ If SpinLock was not initialized with InitializeSpinLock(), then ASSERT().
+ If PcdSpinLockTimeout is not zero, and SpinLock is can not be acquired in
+ PcdSpinLockTimeout microseconds, then ASSERT().
+
+ @param SpinLock A pointer to the spin lock to place in the acquired state.
+
+ @return SpinLock acquired lock.
+
+**/
+SPIN_LOCK *
+EFIAPI
+AcquireSpinLock (
+ IN OUT SPIN_LOCK *SpinLock
+ );
+
+/**
+ Attempts to place a spin lock in the acquired state.
+
+ This function checks the state of the spin lock specified by SpinLock. If
+ SpinLock is in the released state, then this function places SpinLock in the
+ acquired state and returns TRUE. Otherwise, FALSE is returned. All state
+ transitions of SpinLock must be performed using MP safe mechanisms.
+
+ If SpinLock is NULL, then ASSERT().
+ If SpinLock was not initialized with InitializeSpinLock(), then ASSERT().
+
+ @param SpinLock A pointer to the spin lock to place in the acquired state.
+
+ @retval TRUE SpinLock was placed in the acquired state.
+ @retval FALSE SpinLock could not be acquired.
+
+**/
+BOOLEAN
+EFIAPI
+AcquireSpinLockOrFail (
+ IN OUT SPIN_LOCK *SpinLock
+ );
+
+/**
+ Releases a spin lock.
+
+ This function places the spin lock specified by SpinLock in the release state
+ and returns SpinLock.
+
+ If SpinLock is NULL, then ASSERT().
+ If SpinLock was not initialized with InitializeSpinLock(), then ASSERT().
+
+ @param SpinLock A pointer to the spin lock to release.
+
+ @return SpinLock released lock.
+
+**/
+SPIN_LOCK *
+EFIAPI
+ReleaseSpinLock (
+ IN OUT SPIN_LOCK *SpinLock
+ );
+
+/**
+ Performs an atomic increment of a 32-bit unsigned integer.
+
+ Performs an atomic increment of the 32-bit unsigned integer specified by
+ Value and returns the incremented value. The increment operation must be
+ performed using MP safe mechanisms.
+
+ If Value is NULL, then ASSERT().
+
+ @param Value A pointer to the 32-bit value to increment.
+
+ @return The incremented value.
+
+**/
+UINT32
+EFIAPI
+InterlockedIncrement (
+ IN volatile UINT32 *Value
+ );
+
+/**
+ Performs an atomic decrement of a 32-bit unsigned integer.
+
+ Performs an atomic decrement of the 32-bit unsigned integer specified by
+ Value and returns the decremented value. The decrement operation must be
+ performed using MP safe mechanisms.
+
+ If Value is NULL, then ASSERT().
+
+ @param Value A pointer to the 32-bit value to decrement.
+
+ @return The decremented value.
+
+**/
+UINT32
+EFIAPI
+InterlockedDecrement (
+ IN volatile UINT32 *Value
+ );
+
+/**
+ Performs an atomic compare exchange operation on a 16-bit unsigned integer.
+
+ Performs an atomic compare exchange operation on the 16-bit unsigned integer
+ specified by Value. If Value is equal to CompareValue, then Value is set to
+ ExchangeValue and CompareValue is returned. If Value is not equal to CompareValue,
+ then Value is returned. The compare exchange operation must be performed using
+ MP safe mechanisms.
+
+ If Value is NULL, then ASSERT().
+
+ @param Value A pointer to the 16-bit value for the compare exchange
+ operation.
+ @param CompareValue 16-bit value used in compare operation.
+ @param ExchangeValue 16-bit value used in exchange operation.
+
+ @return The original *Value before exchange.
+**/
+UINT16
+EFIAPI
+InterlockedCompareExchange16 (
+ IN OUT volatile UINT16 *Value,
+ IN UINT16 CompareValue,
+ IN UINT16 ExchangeValue
+ );
+
+/**
+ Performs an atomic compare exchange operation on a 32-bit unsigned integer.
+
+ Performs an atomic compare exchange operation on the 32-bit unsigned integer
+ specified by Value. If Value is equal to CompareValue, then Value is set to
+ ExchangeValue and CompareValue is returned. If Value is not equal to CompareValue,
+ then Value is returned. The compare exchange operation must be performed using
+ MP safe mechanisms.
+
+ If Value is NULL, then ASSERT().
+
+ @param Value A pointer to the 32-bit value for the compare exchange
+ operation.
+ @param CompareValue 32-bit value used in compare operation.
+ @param ExchangeValue 32-bit value used in exchange operation.
+
+ @return The original *Value before exchange.
+
+**/
+UINT32
+EFIAPI
+InterlockedCompareExchange32 (
+ IN OUT volatile UINT32 *Value,
+ IN UINT32 CompareValue,
+ IN UINT32 ExchangeValue
+ );
+
+/**
+ Performs an atomic compare exchange operation on a 64-bit unsigned integer.
+
+ Performs an atomic compare exchange operation on the 64-bit unsigned integer specified
+ by Value. If Value is equal to CompareValue, then Value is set to ExchangeValue and
+ CompareValue is returned. If Value is not equal to CompareValue, then Value is returned.
+ The compare exchange operation must be performed using MP safe mechanisms.
+
+ If Value is NULL, then ASSERT().
+
+ @param Value A pointer to the 64-bit value for the compare exchange
+ operation.
+ @param CompareValue 64-bit value used in compare operation.
+ @param ExchangeValue 64-bit value used in exchange operation.
+
+ @return The original *Value before exchange.
+
+**/
+UINT64
+EFIAPI
+InterlockedCompareExchange64 (
+ IN OUT volatile UINT64 *Value,
+ IN UINT64 CompareValue,
+ IN UINT64 ExchangeValue
+ );
+
+/**
+ Performs an atomic compare exchange operation on a pointer value.
+
+ Performs an atomic compare exchange operation on the pointer value specified
+ by Value. If Value is equal to CompareValue, then Value is set to
+ ExchangeValue and CompareValue is returned. If Value is not equal to
+ CompareValue, then Value is returned. The compare exchange operation must be
+ performed using MP safe mechanisms.
+
+ If Value is NULL, then ASSERT().
+
+ @param Value A pointer to the pointer value for the compare exchange
+ operation.
+ @param CompareValue Pointer value used in compare operation.
+ @param ExchangeValue Pointer value used in exchange operation.
+
+ @return The original *Value before exchange.
+**/
+VOID *
+EFIAPI
+InterlockedCompareExchangePointer (
+ IN OUT VOID *volatile *Value,
+ IN VOID *CompareValue,
+ IN VOID *ExchangeValue
+ );
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/TdxLib.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/TdxLib.h
new file mode 100644
index 0000000000..367459836c
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/TdxLib.h
@@ -0,0 +1,92 @@
+/** @file
+ TdxLib definitions
+
+ Copyright (c) 2020 - 2021, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef TDX_LIB_H_
+#define TDX_LIB_H_
+
+/**
+ This function accepts a pending private page, and initialize the page to
+ all-0 using the TD ephemeral private key.
+
+ @param[in] StartAddress Guest physical address of the private page
+ to accept. [63:52] and [11:0] must be 0.
+ @param[in] NumberOfPages Number of the pages to be accepted.
+ @param[in] PageSize GPA page size. Accept 2M/4K page size.
+
+ @return EFI_SUCCESS
+**/
+EFI_STATUS
+EFIAPI
+TdAcceptPages (
+ IN UINT64 StartAddress,
+ IN UINT64 NumberOfPages,
+ IN UINT32 PageSize
+ );
+
+/**
+ This function extends one of the RTMR measurement register
+ in TDCS with the provided extension data in memory.
+ RTMR extending supports SHA384 which length is 48 bytes.
+
+ @param[in] Data Point to the data to be extended
+ @param[in] DataLen Length of the data. Must be 48
+ @param[in] Index RTMR index
+
+ @return EFI_SUCCESS
+ @return EFI_INVALID_PARAMETER
+ @return EFI_DEVICE_ERROR
+
+**/
+EFI_STATUS
+EFIAPI
+TdExtendRtmr (
+ IN UINT32 *Data,
+ IN UINT32 DataLen,
+ IN UINT8 Index
+ );
+
+/**
+ This function gets the Td guest shared page mask.
+
+ The guest indicates if a page is shared using the Guest Physical Address
+ (GPA) Shared (S) bit. If the GPA Width(GPAW) is 48, the S-bit is bit-47.
+ If the GPAW is 52, the S-bit is bit-51.
+
+ @return Shared page bit mask
+**/
+UINT64
+EFIAPI
+TdSharedPageMask (
+ VOID
+ );
+
+/**
+ This function gets the maximum number of Virtual CPUs that are usable for
+ Td Guest.
+
+ @return maximum Virtual CPUs number
+**/
+UINT32
+EFIAPI
+TdMaxVCpuNum (
+ VOID
+ );
+
+/**
+ This function gets the number of Virtual CPUs that are usable for Td
+ Guest.
+
+ @return Virtual CPUs number
+**/
+UINT32
+EFIAPI
+TdVCpuNum (
+ VOID
+ );
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/TimerLib.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/TimerLib.h
new file mode 100644
index 0000000000..a853811ece
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/TimerLib.h
@@ -0,0 +1,108 @@
+/** @file
+ Provides calibrated delay and performance counter services.
+
+Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __TIMER_LIB__
+#define __TIMER_LIB__
+
+/**
+ Stalls the CPU for at least the given number of microseconds.
+
+ Stalls the CPU for the number of microseconds specified by MicroSeconds.
+
+ @param MicroSeconds The minimum number of microseconds to delay.
+
+ @return The value of MicroSeconds inputted.
+
+**/
+UINTN
+EFIAPI
+MicroSecondDelay (
+ IN UINTN MicroSeconds
+ );
+
+/**
+ Stalls the CPU for at least the given number of nanoseconds.
+
+ Stalls the CPU for the number of nanoseconds specified by NanoSeconds.
+
+ @param NanoSeconds The minimum number of nanoseconds to delay.
+
+ @return The value of NanoSeconds inputted.
+
+**/
+UINTN
+EFIAPI
+NanoSecondDelay (
+ IN UINTN NanoSeconds
+ );
+
+/**
+ Retrieves the current value of a 64-bit free running performance counter.
+
+ The counter can either count up by 1 or count down by 1. If the physical
+ performance counter counts by a larger increment, then the counter values
+ must be translated. The properties of the counter can be retrieved from
+ GetPerformanceCounterProperties().
+
+ @return The current value of the free running performance counter.
+
+**/
+UINT64
+EFIAPI
+GetPerformanceCounter (
+ VOID
+ );
+
+/**
+ Retrieves the 64-bit frequency in Hz and the range of performance counter
+ values.
+
+ If StartValue is not NULL, then the value that the performance counter starts
+ with immediately after is it rolls over is returned in StartValue. If
+ EndValue is not NULL, then the value that the performance counter end with
+ immediately before it rolls over is returned in EndValue. The 64-bit
+ frequency of the performance counter in Hz is always returned. If StartValue
+ is less than EndValue, then the performance counter counts up. If StartValue
+ is greater than EndValue, then the performance counter counts down. For
+ example, a 64-bit free running counter that counts up would have a StartValue
+ of 0 and an EndValue of 0xFFFFFFFFFFFFFFFF. A 24-bit free running counter
+ that counts down would have a StartValue of 0xFFFFFF and an EndValue of 0.
+
+ @param StartValue The value the performance counter starts with when it
+ rolls over.
+ @param EndValue The value that the performance counter ends with before
+ it rolls over.
+
+ @return The frequency in Hz.
+
+**/
+UINT64
+EFIAPI
+GetPerformanceCounterProperties (
+ OUT UINT64 *StartValue OPTIONAL,
+ OUT UINT64 *EndValue OPTIONAL
+ );
+
+/**
+ Converts elapsed ticks of performance counter to time in nanoseconds.
+
+ This function converts the elapsed ticks of running performance counter to
+ time value in unit of nanoseconds.
+
+ @param Ticks The number of elapsed ticks of running performance counter.
+
+ @return The elapsed time in nanoseconds.
+
+**/
+UINT64
+EFIAPI
+GetTimeInNanoSecond (
+ IN UINT64 Ticks
+ );
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/UefiApplicationEntryPoint.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/UefiApplicationEntryPoint.h
new file mode 100644
index 0000000000..34547e5cc7
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/UefiApplicationEntryPoint.h
@@ -0,0 +1,143 @@
+/** @file
+ Module entry point library for UEFI Applications.
+
+Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __UEFI_APPLICATION_ENTRY_POINT_H__
+#define __UEFI_APPLICATION_ENTRY_POINT_H__
+
+///
+/// Declare the EFI/UEFI Specification Revision to which this driver is implemented
+///
+extern CONST UINT32 _gUefiDriverRevision;
+
+/**
+ Entry point to UEFI Application.
+
+ This function is the entry point for a UEFI Application. This function must call
+ ProcessLibraryConstructorList(), ProcessModuleEntryPointList(), and ProcessLibraryDestructorList().
+ The return value from ProcessModuleEntryPointList() is returned.
+ If _gUefiDriverRevision is not zero and SystemTable->Hdr.Revision is less than _gUefiDriverRevison,
+ then return EFI_INCOMPATIBLE_VERSION.
+
+ @param ImageHandle The image handle of the UEFI Application.
+ @param SystemTable A pointer to the EFI System Table.
+
+ @retval EFI_SUCCESS The UEFI Application exited normally.
+ @retval EFI_INCOMPATIBLE_VERSION _gUefiDriverRevision is greater than SystemTable->Hdr.Revision.
+ @retval Other Return value from ProcessModuleEntryPointList().
+
+**/
+EFI_STATUS
+EFIAPI
+_ModuleEntryPoint (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ );
+
+/**
+ Required by the EBC compiler and identical in functionality to _ModuleEntryPoint().
+
+ @param ImageHandle The image handle of the UEFI Application.
+ @param SystemTable A pointer to the EFI System Table.
+
+ @retval EFI_SUCCESS The UEFI Application exited normally.
+ @retval EFI_INCOMPATIBLE_VERSION _gUefiDriverRevision is greater than SystemTable->Hdr.Revision.
+ @retval Other Return value from ProcessModuleEntryPointList().
+
+**/
+EFI_STATUS
+EFIAPI
+EfiMain (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ );
+
+/**
+ Invokes the library destructors for all dependent libraries and terminates
+ the UEFI Application.
+
+ This function calls ProcessLibraryDestructorList() and the EFI Boot Service Exit()
+ with a status specified by Status.
+
+ @param Status Status returned by the application that is exiting.
+
+**/
+VOID
+EFIAPI
+Exit (
+ IN EFI_STATUS Status
+ );
+
+/**
+ Autogenerated function that calls the library constructors for all of the module's
+ dependent libraries.
+
+ This function must be called by _ModuleEntryPoint().
+ This function calls the set of library constructors for the set of library instances
+ that a module depends on. This includes library instances that a module depends on
+ directly and library instances that a module depends on indirectly through other libraries.
+ This function is autogenerated by build tools and those build tools are responsible for
+ collecting the set of library instances, determine which ones have constructors, and
+ calling the library constructors in the proper order based upon each of the library
+ instances own dependencies.
+
+ @param ImageHandle The image handle of the UEFI Application.
+ @param SystemTable A pointer to the EFI System Table.
+
+**/
+VOID
+EFIAPI
+ProcessLibraryConstructorList (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ );
+
+/**
+ Autogenerated function that calls the library descructors for all of the module's
+ dependent libraries.
+
+ This function may be called by _ModuleEntryPoint()or Exit().
+ This function calls the set of library destructors for the set of library instances
+ that a module depends on. This includes library instances that a module depends on
+ directly and library instances that a module depends on indirectly through other libraries.
+ This function is autogenerated by build tools and those build tools are responsible
+ for collecting the set of library instances, determine which ones have destructors,
+ and calling the library destructors in the proper order based upon each of the library
+ instances own dependencies.
+
+ @param ImageHandle The image handle of the UEFI Application.
+ @param SystemTable A pointer to the EFI System Table.
+
+**/
+VOID
+EFIAPI
+ProcessLibraryDestructorList (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ );
+
+/**
+ This function calls the set of module entry points. It must be called by _ModuleEntryPoint().
+
+ This function is autogenerated by build tools and those build tools are
+ responsible for collecting the module entry points and calling them in a specified order.
+
+ @param ImageHandle The image handle of the UEFI Application.
+ @param SystemTable A pointer to the EFI System Table.
+
+ @retval EFI_SUCCESS The UEFI Application executed normally.
+ @retval !EFI_SUCCESS The UEFI Application failed to execute normally.
+
+**/
+EFI_STATUS
+EFIAPI
+ProcessModuleEntryPointList (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ );
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/UefiBootServicesTableLib.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/UefiBootServicesTableLib.h
new file mode 100644
index 0000000000..b2e019e25c
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/UefiBootServicesTableLib.h
@@ -0,0 +1,28 @@
+/** @file
+ Provides a service to retrieve a pointer to the EFI Boot Services Table.
+ Only available to DXE and UEFI module types.
+
+Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __UEFI_BOOT_SERVICES_TABLE_LIB_H__
+#define __UEFI_BOOT_SERVICES_TABLE_LIB_H__
+
+///
+/// Cache the Image Handle
+///
+extern EFI_HANDLE gImageHandle;
+
+///
+/// Cache pointer to the EFI System Table
+///
+extern EFI_SYSTEM_TABLE *gST;
+
+///
+/// Cache pointer to the EFI Boot Services Table
+///
+extern EFI_BOOT_SERVICES *gBS;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/UefiDecompressLib.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/UefiDecompressLib.h
new file mode 100644
index 0000000000..510e80aa9c
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/UefiDecompressLib.h
@@ -0,0 +1,102 @@
+/** @file
+ Provides services to decompress a buffer using the UEFI Decompress algorithm.
+
+ The UEFI Decompress Library enables the decompression of objects that
+ were compressed using the UEFI compression scheme. The UEFI Decompress
+ Library is independent of environment and requires the caller to allocate
+ all required memory buffers.
+
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __UEFI_DECPOMPRESS_LIB_H__
+#define __UEFI_DECPOMPRESS_LIB_H__
+
+/**
+ Given a compressed source buffer, this function retrieves the size of
+ the uncompressed buffer and the size of the scratch buffer required
+ to decompress the compressed source buffer.
+
+ Retrieves the size of the uncompressed buffer and the temporary scratch buffer
+ required to decompress the buffer specified by Source and SourceSize.
+ If the size of the uncompressed buffer or the size of the scratch buffer cannot
+ be determined from the compressed data specified by Source and SourceData,
+ then RETURN_INVALID_PARAMETER is returned. Otherwise, the size of the uncompressed
+ buffer is returned in DestinationSize, the size of the scratch buffer is returned
+ in ScratchSize, and RETURN_SUCCESS is returned.
+ This function does not have scratch buffer available to perform a thorough
+ checking of the validity of the source data. It just retrieves the "Original Size"
+ field from the beginning bytes of the source data and output it as DestinationSize.
+ And ScratchSize is specific to the decompression implementation.
+
+ If Source is NULL, then ASSERT().
+ If DestinationSize is NULL, then ASSERT().
+ If ScratchSize is NULL, then ASSERT().
+
+ @param Source The source buffer containing the compressed data.
+ @param SourceSize The size, in bytes, of the source buffer.
+ @param DestinationSize A pointer to the size, in bytes, of the uncompressed buffer
+ that will be generated when the compressed buffer specified
+ by Source and SourceSize is decompressed.
+ @param ScratchSize A pointer to the size, in bytes, of the scratch buffer that
+ is required to decompress the compressed buffer specified
+ by Source and SourceSize.
+
+ @retval RETURN_SUCCESS The size of the uncompressed data was returned
+ in DestinationSize and the size of the scratch
+ buffer was returned in ScratchSize.
+ @retval RETURN_INVALID_PARAMETER
+ The size of the uncompressed data or the size of
+ the scratch buffer cannot be determined from
+ the compressed data specified by Source
+ and SourceSize.
+**/
+RETURN_STATUS
+EFIAPI
+UefiDecompressGetInfo (
+ IN CONST VOID *Source,
+ IN UINT32 SourceSize,
+ OUT UINT32 *DestinationSize,
+ OUT UINT32 *ScratchSize
+ );
+
+/**
+ Decompresses a compressed source buffer.
+
+ Extracts decompressed data to its original form.
+ This function is designed so that the decompression algorithm can be implemented
+ without using any memory services. As a result, this function is not allowed to
+ call any memory allocation services in its implementation. It is the caller's
+ responsibility to allocate and free the Destination and Scratch buffers.
+ If the compressed source data specified by Source is successfully decompressed
+ into Destination, then RETURN_SUCCESS is returned. If the compressed source data
+ specified by Source is not in a valid compressed data format,
+ then RETURN_INVALID_PARAMETER is returned.
+
+ If Source is NULL, then ASSERT().
+ If Destination is NULL, then ASSERT().
+ If the required scratch buffer size > 0 and Scratch is NULL, then ASSERT().
+
+ @param Source The source buffer containing the compressed data.
+ @param Destination The destination buffer to store the decompressed data
+ @param Scratch A temporary scratch buffer that is used to perform the decompression.
+ This is an optional parameter that may be NULL if the
+ required scratch buffer size is 0.
+
+ @retval RETURN_SUCCESS Decompression completed successfully, and
+ the uncompressed buffer is returned in Destination.
+ @retval RETURN_INVALID_PARAMETER
+ The source buffer specified by Source is corrupted
+ (not in a valid compressed format).
+**/
+RETURN_STATUS
+EFIAPI
+UefiDecompress (
+ IN CONST VOID *Source,
+ IN OUT VOID *Destination,
+ IN OUT VOID *Scratch OPTIONAL
+ );
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/UefiDriverEntryPoint.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/UefiDriverEntryPoint.h
new file mode 100644
index 0000000000..69672fd0cb
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/UefiDriverEntryPoint.h
@@ -0,0 +1,182 @@
+/** @file
+ Module entry point library for UEFI drivers, DXE Drivers, DXE Runtime Drivers,
+ and DXE SMM Drivers.
+
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __MODULE_ENTRY_POINT_H__
+#define __MODULE_ENTRY_POINT_H__
+
+///
+/// Declare the PI Specification Revision that this driver requires to execute correctly.
+///
+extern CONST UINT32 _gDxeRevision;
+
+///
+/// Declare the EFI/UEFI Specification Revision to which this driver is implemented
+///
+extern CONST UINT32 _gUefiDriverRevision;
+
+///
+/// Declare the number of unload handler in the image.
+///
+extern CONST UINT8 _gDriverUnloadImageCount;
+
+/**
+ The entry point of PE/COFF Image for a DXE Driver, DXE Runtime Driver, DXE SMM Driver, or UEFI Driver.
+
+ This function is the entry point for a DXE Driver, DXE Runtime Driver, DXE SMM Driver,
+ or UEFI Driver. This function must call ProcessLibraryConstructorList() and
+ ProcessModuleEntryPointList(). If the return status from ProcessModuleEntryPointList()
+ is an error status, then ProcessLibraryDestructorList() must be called. The return value
+ from ProcessModuleEntryPointList() is returned. If _gDriverUnloadImageCount is greater
+ than zero, then an unload handler must be registered for this image and the unload handler
+ must invoke ProcessModuleUnloadList().
+ If _gUefiDriverRevision is not zero and SystemTable->Hdr.Revision is less than _gUefiDriverRevison,
+ then return EFI_INCOMPATIBLE_VERSION.
+
+
+ @param ImageHandle The image handle of the DXE Driver, DXE Runtime Driver, DXE SMM Driver, or UEFI Driver.
+ @param SystemTable A pointer to the EFI System Table.
+
+ @retval EFI_SUCCESS The DXE Driver, DXE Runtime Driver, DXE SMM Driver,
+ or UEFI Driver exited normally.
+ @retval EFI_INCOMPATIBLE_VERSION _gUefiDriverRevision is greater than SystemTable->Hdr.Revision.
+ @retval Other Return value from ProcessModuleEntryPointList().
+
+**/
+EFI_STATUS
+EFIAPI
+_ModuleEntryPoint (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ );
+
+/**
+ Required by the EBC compiler and identical in functionality to _ModuleEntryPoint().
+
+ This function is required to call _ModuleEntryPoint() passing in ImageHandle, and SystemTable.
+
+ @param ImageHandle The image handle of the DXE Driver, DXE Runtime Driver, DXE SMM Driver, or UEFI Driver.
+ @param SystemTable A pointer to the EFI System Table.
+
+ @retval EFI_SUCCESS The DXE Driver, DXE Runtime Driver, DXE SMM Driver,
+ or UEFI Driver exited normally.
+ @retval EFI_INCOMPATIBLE_VERSION _gUefiDriverRevision is greater than SystemTable->Hdr.Revision.
+ @retval Other Return value from ProcessModuleEntryPointList().
+**/
+EFI_STATUS
+EFIAPI
+EfiMain (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ );
+
+/**
+ Invokes the library destructors for all dependent libraries and terminates the
+ DXE Driver, DXE Runtime Driver, DXE SMM Driver, or UEFI Driver.
+
+ This function calls ProcessLibraryDestructorList() and the EFI Boot Service Exit()
+ with a status specified by Status.
+
+ @param Status Status returned by the driver that is exiting.
+
+**/
+VOID
+EFIAPI
+ExitDriver (
+ IN EFI_STATUS Status
+ );
+
+/**
+ Autogenerated function that calls the library constructors for all of the module's
+ dependent libraries.
+
+ This function must be called by _ModuleEntryPoint().
+ This function calls the set of library constructors for the set of library instances
+ that a module depends on. This includes library instances that a module depends on
+ directly and library instances that a module depends on indirectly through other libraries.
+ This function is autogenerated by build tools and those build tools are responsible
+ for collecting the set of library instances, determine which ones have constructors,
+ and calling the library constructors in the proper order based upon each of the library
+ instances own dependencies.
+
+ @param ImageHandle The image handle of the DXE Driver, DXE Runtime Driver, DXE SMM Driver, or UEFI Driver.
+ @param SystemTable A pointer to the EFI System Table.
+
+**/
+VOID
+EFIAPI
+ProcessLibraryConstructorList (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ );
+
+/**
+ Autogenerated function that calls the library descructors for all of the module's
+ dependent libraries.
+
+ This function may be called by _ModuleEntryPoint() or ExitDriver().
+ This function calls the set of library destructors for the set of library instances
+ that a module depends on. This includes library instances that a module depends on
+ directly and library instances that a module depends on indirectly through other libraries.
+ This function is autogenerated by build tools and those build tools are responsible for
+ collecting the set of library instances, determine which ones have destructors, and calling
+ the library destructors in the proper order based upon each of the library instances own dependencies.
+
+ @param ImageHandle The image handle of the DXE Driver, DXE Runtime Driver, DXE SMM Driver, or UEFI Driver.
+ @param SystemTable A pointer to the EFI System Table.
+
+**/
+VOID
+EFIAPI
+ProcessLibraryDestructorList (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ );
+
+/**
+ Autogenerated function that calls a set of module entry points.
+
+ This function must be called by _ModuleEntryPoint().
+ This function calls the set of module entry points.
+ This function is autogenerated by build tools and those build tools are responsible
+ for collecting the module entry points and calling them in a specified order.
+
+ @param ImageHandle The image handle of the DXE Driver, DXE Runtime Driver, DXE SMM Driver, or UEFI Driver.
+ @param SystemTable A pointer to the EFI System Table.
+
+ @retval EFI_SUCCESS The DXE Driver, DXE Runtime Driver, DXE SMM Driver, or UEFI Driver executed normally.
+ @retval !EFI_SUCCESS The DXE Driver, DXE Runtime Driver, DXE SMM Driver, or UEFI Driver failed to execute normally.
+**/
+EFI_STATUS
+EFIAPI
+ProcessModuleEntryPointList (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ );
+
+/**
+ Autogenerated function that calls a set of module unload handlers.
+
+ This function must be called from the unload handler registered by _ModuleEntryPoint().
+ This function calls the set of module unload handlers.
+ This function is autogenerated by build tools and those build tools are responsible
+ for collecting the module unload handlers and calling them in a specified order.
+
+ @param ImageHandle The image handle of the DXE Driver, DXE Runtime Driver, DXE SMM Driver, or UEFI Driver.
+
+ @retval EFI_SUCCESS The unload handlers executed normally.
+ @retval !EFI_SUCCESS The unload handlers failed to execute normally.
+
+**/
+EFI_STATUS
+EFIAPI
+ProcessModuleUnloadList (
+ IN EFI_HANDLE ImageHandle
+ );
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/UefiLib.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/UefiLib.h
new file mode 100644
index 0000000000..a958a20c78
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/UefiLib.h
@@ -0,0 +1,1749 @@
+/** @file
+ Provides library functions for common UEFI operations. Only available to DXE
+ and UEFI module types.
+
+ The UEFI Library provides functions and macros that simplify the development of
+ UEFI Drivers and UEFI Applications. These functions and macros help manage EFI
+ events, build simple locks utilizing EFI Task Priority Levels (TPLs), install
+ EFI Driver Model related protocols, manage Unicode string tables for UEFI Drivers,
+ and print messages on the console output and standard error devices.
+
+ Note that a reserved macro named MDEPKG_NDEBUG is introduced for the intention
+ of size reduction when compiler optimization is disabled. If MDEPKG_NDEBUG is
+ defined, then debug and assert related macros wrapped by it are the NULL implementations.
+
+Copyright (c) 2019, NVIDIA Corporation. All rights reserved.
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __UEFI_LIB_H__
+#define __UEFI_LIB_H__
+
+#include
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+
+///
+/// Unicode String Table
+///
+typedef struct {
+ CHAR8 *Language;
+ CHAR16 *UnicodeString;
+} EFI_UNICODE_STRING_TABLE;
+
+///
+/// EFI Lock Status
+///
+typedef enum {
+ EfiLockUninitialized = 0,
+ EfiLockReleased = 1,
+ EfiLockAcquired = 2
+} EFI_LOCK_STATE;
+
+///
+/// EFI Lock
+///
+typedef struct {
+ EFI_TPL Tpl;
+ EFI_TPL OwnerTpl;
+ EFI_LOCK_STATE Lock;
+} EFI_LOCK;
+
+/**
+ Macro that returns the number of 100 ns units for a specified number of microseconds.
+ This is useful for managing EFI timer events.
+
+ @param Microseconds The number of microseconds.
+
+ @return The number of 100 ns units equivalent to the number of microseconds specified
+ by Microseconds.
+
+**/
+#define EFI_TIMER_PERIOD_MICROSECONDS(Microseconds) MultU64x32((UINT64)(Microseconds), 10)
+
+/**
+ Macro that returns the number of 100 ns units for a specified number of milliseconds.
+ This is useful for managing EFI timer events.
+
+ @param Milliseconds The number of milliseconds.
+
+ @return The number of 100 ns units equivalent to the number of milliseconds specified
+ by Milliseconds.
+
+**/
+#define EFI_TIMER_PERIOD_MILLISECONDS(Milliseconds) MultU64x32((UINT64)(Milliseconds), 10000)
+
+/**
+ Macro that returns the number of 100 ns units for a specified number of seconds.
+ This is useful for managing EFI timer events.
+
+ @param Seconds The number of seconds.
+
+ @return The number of 100 ns units equivalent to the number of seconds specified
+ by Seconds.
+
+**/
+#define EFI_TIMER_PERIOD_SECONDS(Seconds) MultU64x32((UINT64)(Seconds), 10000000)
+
+/**
+ Macro that returns the a pointer to the next EFI_MEMORY_DESCRIPTOR in an array
+ returned from GetMemoryMap().
+
+ @param MemoryDescriptor A pointer to an EFI_MEMORY_DESCRIPTOR.
+
+ @param Size The size, in bytes, of the current EFI_MEMORY_DESCRIPTOR.
+
+ @return A pointer to the next EFI_MEMORY_DESCRIPTOR.
+
+**/
+#define NEXT_MEMORY_DESCRIPTOR(MemoryDescriptor, Size) \
+ ((EFI_MEMORY_DESCRIPTOR *)((UINT8 *)(MemoryDescriptor) + (Size)))
+
+/**
+ Retrieves a pointer to the system configuration table from the EFI System Table
+ based on a specified GUID.
+
+ This function searches the list of configuration tables stored in the EFI System Table
+ for a table with a GUID that matches TableGuid. If a match is found, then a pointer to
+ the configuration table is returned in Table, and EFI_SUCCESS is returned. If a matching GUID
+ is not found, then EFI_NOT_FOUND is returned.
+ If TableGuid is NULL, then ASSERT().
+ If Table is NULL, then ASSERT().
+
+ @param TableGuid The pointer to table's GUID type..
+ @param Table The pointer to the table associated with TableGuid in the EFI System Table.
+
+ @retval EFI_SUCCESS A configuration table matching TableGuid was found.
+ @retval EFI_NOT_FOUND A configuration table matching TableGuid could not be found.
+
+**/
+EFI_STATUS
+EFIAPI
+EfiGetSystemConfigurationTable (
+ IN EFI_GUID *TableGuid,
+ OUT VOID **Table
+ );
+
+/**
+ Creates and returns a notification event and registers that event with all the protocol
+ instances specified by ProtocolGuid.
+
+ This function causes the notification function to be executed for every protocol of type
+ ProtocolGuid instance that exists in the system when this function is invoked. If there are
+ no instances of ProtocolGuid in the handle database at the time this function is invoked,
+ then the notification function is still executed one time. In addition, every time a protocol
+ of type ProtocolGuid instance is installed or reinstalled, the notification function is also
+ executed. This function returns the notification event that was created.
+ If ProtocolGuid is NULL, then ASSERT().
+ If NotifyTpl is not a legal TPL value, then ASSERT().
+ If NotifyFunction is NULL, then ASSERT().
+ If Registration is NULL, then ASSERT().
+
+
+ @param ProtocolGuid Supplies GUID of the protocol upon whose installation the event is fired.
+ @param NotifyTpl Supplies the task priority level of the event notifications.
+ @param NotifyFunction Supplies the function to notify when the event is signaled.
+ @param NotifyContext The context parameter to pass to NotifyFunction.
+ @param Registration A pointer to a memory location to receive the registration value.
+ This value is passed to LocateHandle() to obtain new handles that
+ have been added that support the ProtocolGuid-specified protocol.
+
+ @return The notification event that was created.
+
+**/
+EFI_EVENT
+EFIAPI
+EfiCreateProtocolNotifyEvent (
+ IN EFI_GUID *ProtocolGuid,
+ IN EFI_TPL NotifyTpl,
+ IN EFI_EVENT_NOTIFY NotifyFunction,
+ IN VOID *NotifyContext OPTIONAL,
+ OUT VOID **Registration
+ );
+
+/**
+ Creates a named event that can be signaled with EfiNamedEventSignal().
+
+ This function creates an event using NotifyTpl, NoifyFunction, and NotifyContext.
+ This event is signaled with EfiNamedEventSignal(). This provides the ability for one or more
+ listeners on the same event named by the GUID specified by Name.
+ If Name is NULL, then ASSERT().
+ If NotifyTpl is not a legal TPL value, then ASSERT().
+ If NotifyFunction is NULL, then ASSERT().
+
+ @param Name Supplies GUID name of the event.
+ @param NotifyTpl Supplies the task priority level of the event notifications.
+ @param NotifyFunction Supplies the function to notify when the event is signaled.
+ @param NotifyContext The context parameter to pass to NotifyFunction.
+ @param Registration A pointer to a memory location to receive the registration value.
+
+ @retval EFI_SUCCESS A named event was created.
+ @retval EFI_OUT_OF_RESOURCES There are not enough resources to create the named event.
+
+**/
+EFI_STATUS
+EFIAPI
+EfiNamedEventListen (
+ IN CONST EFI_GUID *Name,
+ IN EFI_TPL NotifyTpl,
+ IN EFI_EVENT_NOTIFY NotifyFunction,
+ IN CONST VOID *NotifyContext OPTIONAL,
+ OUT VOID *Registration OPTIONAL
+ );
+
+/**
+ Signals a named event created with EfiNamedEventListen().
+
+ This function signals the named event specified by Name. The named event must have been
+ created with EfiNamedEventListen().
+ If Name is NULL, then ASSERT().
+
+ @param Name Supplies the GUID name of the event.
+
+ @retval EFI_SUCCESS A named event was signaled.
+ @retval EFI_OUT_OF_RESOURCES There are not enough resources to signal the named event.
+
+**/
+EFI_STATUS
+EFIAPI
+EfiNamedEventSignal (
+ IN CONST EFI_GUID *Name
+ );
+
+/**
+ Signals an event group by placing a new event in the group temporarily and
+ signaling it.
+
+ @param[in] EventGroup Supplies the unique identifier of the event
+ group to signal.
+
+ @retval EFI_SUCCESS The event group was signaled successfully.
+ @retval EFI_INVALID_PARAMETER EventGroup is NULL.
+ @return Error codes that report problems about event
+ creation or signaling.
+**/
+EFI_STATUS
+EFIAPI
+EfiEventGroupSignal (
+ IN CONST EFI_GUID *EventGroup
+ );
+
+/**
+ An empty function that can be used as NotifyFunction parameter of
+ CreateEvent() or CreateEventEx().
+
+ @param Event Event whose notification function is being invoked.
+ @param Context The pointer to the notification function's context,
+ which is implementation-dependent.
+
+**/
+VOID
+EFIAPI
+EfiEventEmptyFunction (
+ IN EFI_EVENT Event,
+ IN VOID *Context
+ );
+
+/**
+ Returns the current TPL.
+
+ This function returns the current TPL. There is no EFI service to directly
+ retrieve the current TPL. Instead, the RaiseTPL() function is used to raise
+ the TPL to TPL_HIGH_LEVEL. This will return the current TPL. The TPL level
+ can then immediately be restored back to the current TPL level with a call
+ to RestoreTPL().
+
+ @return The current TPL.
+
+**/
+EFI_TPL
+EFIAPI
+EfiGetCurrentTpl (
+ VOID
+ );
+
+/**
+ Initializes a basic mutual exclusion lock.
+
+ This function initializes a basic mutual exclusion lock to the released state
+ and returns the lock. Each lock provides mutual exclusion access at its task
+ priority level. Since there is no preemption or multiprocessor support in EFI,
+ acquiring the lock only consists of raising to the locks TPL.
+ If Lock is NULL, then ASSERT().
+ If Priority is not a valid TPL value, then ASSERT().
+
+ @param Lock A pointer to the lock data structure to initialize.
+ @param Priority The EFI TPL associated with the lock.
+
+ @return The lock.
+
+**/
+EFI_LOCK *
+EFIAPI
+EfiInitializeLock (
+ IN OUT EFI_LOCK *Lock,
+ IN EFI_TPL Priority
+ );
+
+/**
+ Initializes a basic mutual exclusion lock.
+
+ This macro initializes the contents of a basic mutual exclusion lock to the
+ released state. Each lock provides mutual exclusion access at its task
+ priority level. Since there is no preemption or multiprocessor support in EFI,
+ acquiring the lock only consists of raising to the locks TPL.
+
+ @param Priority The task priority level of the lock.
+
+ @return The lock.
+
+**/
+#define EFI_INITIALIZE_LOCK_VARIABLE(Priority) \
+ {Priority, TPL_APPLICATION, EfiLockReleased }
+
+/**
+ Macro that calls DebugAssert() if an EFI_LOCK structure is not in the locked state.
+
+ If MDEPKG_NDEBUG is not defined and the DEBUG_PROPERTY_DEBUG_ASSERT_ENABLED
+ bit of PcdDebugProperyMask is set, then this macro evaluates the EFI_LOCK
+ structure specified by Lock. If Lock is not in the locked state, then
+ DebugAssert() is called passing in the source filename, source line number,
+ and Lock.
+
+ If Lock is NULL, then ASSERT().
+
+ @param LockParameter A pointer to the lock to acquire.
+
+**/
+#if !defined (MDEPKG_NDEBUG)
+#define ASSERT_LOCKED(LockParameter) \
+ do { \
+ if (DebugAssertEnabled ()) { \
+ ASSERT (LockParameter != NULL); \
+ if ((LockParameter)->Lock != EfiLockAcquired) { \
+ _ASSERT (LockParameter not locked); \
+ } \
+ } \
+ } while (FALSE)
+#else
+#define ASSERT_LOCKED(LockParameter)
+#endif
+
+/**
+ Acquires ownership of a lock.
+
+ This function raises the system's current task priority level to the task
+ priority level of the mutual exclusion lock. Then, it places the lock in the
+ acquired state.
+ If Lock is NULL, then ASSERT().
+ If Lock is not initialized, then ASSERT().
+ If Lock is already in the acquired state, then ASSERT().
+
+ @param Lock A pointer to the lock to acquire.
+
+**/
+VOID
+EFIAPI
+EfiAcquireLock (
+ IN EFI_LOCK *Lock
+ );
+
+/**
+ Acquires ownership of a lock.
+
+ This function raises the system's current task priority level to the task priority
+ level of the mutual exclusion lock. Then, it attempts to place the lock in the acquired state.
+ If the lock is already in the acquired state, then EFI_ACCESS_DENIED is returned.
+ Otherwise, EFI_SUCCESS is returned.
+ If Lock is NULL, then ASSERT().
+ If Lock is not initialized, then ASSERT().
+
+ @param Lock A pointer to the lock to acquire.
+
+ @retval EFI_SUCCESS The lock was acquired.
+ @retval EFI_ACCESS_DENIED The lock could not be acquired because it is already owned.
+
+**/
+EFI_STATUS
+EFIAPI
+EfiAcquireLockOrFail (
+ IN EFI_LOCK *Lock
+ );
+
+/**
+ Releases ownership of a lock.
+
+ This function transitions a mutual exclusion lock from the acquired state to
+ the released state, and restores the system's task priority level to its
+ previous level.
+ If Lock is NULL, then ASSERT().
+ If Lock is not initialized, then ASSERT().
+ If Lock is already in the released state, then ASSERT().
+
+ @param Lock A pointer to the lock to release.
+
+**/
+VOID
+EFIAPI
+EfiReleaseLock (
+ IN EFI_LOCK *Lock
+ );
+
+/**
+ Tests whether a controller handle is being managed by a specific driver.
+
+ This function tests whether the driver specified by DriverBindingHandle is
+ currently managing the controller specified by ControllerHandle. This test
+ is performed by evaluating if the the protocol specified by ProtocolGuid is
+ present on ControllerHandle and is was opened by DriverBindingHandle with an
+ attribute of EFI_OPEN_PROTOCOL_BY_DRIVER.
+ If ProtocolGuid is NULL, then ASSERT().
+
+ @param ControllerHandle A handle for a controller to test.
+ @param DriverBindingHandle Specifies the driver binding handle for the
+ driver.
+ @param ProtocolGuid Specifies the protocol that the driver specified
+ by DriverBindingHandle opens in its Start()
+ function.
+
+ @retval EFI_SUCCESS ControllerHandle is managed by the driver
+ specified by DriverBindingHandle.
+ @retval EFI_UNSUPPORTED ControllerHandle is not managed by the driver
+ specified by DriverBindingHandle.
+
+**/
+EFI_STATUS
+EFIAPI
+EfiTestManagedDevice (
+ IN CONST EFI_HANDLE ControllerHandle,
+ IN CONST EFI_HANDLE DriverBindingHandle,
+ IN CONST EFI_GUID *ProtocolGuid
+ );
+
+/**
+ Tests whether a child handle is a child device of the controller.
+
+ This function tests whether ChildHandle is one of the children of
+ ControllerHandle. This test is performed by checking to see if the protocol
+ specified by ProtocolGuid is present on ControllerHandle and opened by
+ ChildHandle with an attribute of EFI_OPEN_PROTOCOL_BY_CHILD_CONTROLLER.
+ If ProtocolGuid is NULL, then ASSERT().
+
+ @param ControllerHandle A handle for a (parent) controller to test.
+ @param ChildHandle A child handle to test.
+ @param ProtocolGuid Supplies the protocol that the child controller
+ opens on its parent controller.
+
+ @retval EFI_SUCCESS ChildHandle is a child of the ControllerHandle.
+ @retval EFI_UNSUPPORTED ChildHandle is not a child of the
+ ControllerHandle.
+
+**/
+EFI_STATUS
+EFIAPI
+EfiTestChildHandle (
+ IN CONST EFI_HANDLE ControllerHandle,
+ IN CONST EFI_HANDLE ChildHandle,
+ IN CONST EFI_GUID *ProtocolGuid
+ );
+
+/**
+ This function checks the supported languages list for a target language,
+ This only supports RFC 4646 Languages.
+
+ @param SupportedLanguages The supported languages
+ @param TargetLanguage The target language
+
+ @retval Returns EFI_SUCCESS if the language is supported,
+ EFI_UNSUPPORTED otherwise
+
+**/
+EFI_STATUS
+EFIAPI
+IsLanguageSupported (
+ IN CONST CHAR8 *SupportedLanguages,
+ IN CONST CHAR8 *TargetLanguage
+ );
+
+/**
+ This function looks up a Unicode string in UnicodeStringTable.
+
+ If Language is a member of SupportedLanguages and a Unicode string is found in
+ UnicodeStringTable that matches the language code specified by Language, then it
+ is returned in UnicodeString.
+
+ @param Language A pointer to the ISO 639-2 language code for the
+ Unicode string to look up and return.
+ @param SupportedLanguages A pointer to the set of ISO 639-2 language codes
+ that the Unicode string table supports. Language
+ must be a member of this set.
+ @param UnicodeStringTable A pointer to the table of Unicode strings.
+ @param UnicodeString A pointer to the Unicode string from UnicodeStringTable
+ that matches the language specified by Language.
+
+ @retval EFI_SUCCESS The Unicode string that matches the language
+ specified by Language was found
+ in the table of Unicode strings UnicodeStringTable,
+ and it was returned in UnicodeString.
+ @retval EFI_INVALID_PARAMETER Language is NULL.
+ @retval EFI_INVALID_PARAMETER UnicodeString is NULL.
+ @retval EFI_UNSUPPORTED SupportedLanguages is NULL.
+ @retval EFI_UNSUPPORTED UnicodeStringTable is NULL.
+ @retval EFI_UNSUPPORTED The language specified by Language is not a
+ member of SupportedLanguages.
+ @retval EFI_UNSUPPORTED The language specified by Language is not
+ supported by UnicodeStringTable.
+
+**/
+EFI_STATUS
+EFIAPI
+LookupUnicodeString (
+ IN CONST CHAR8 *Language,
+ IN CONST CHAR8 *SupportedLanguages,
+ IN CONST EFI_UNICODE_STRING_TABLE *UnicodeStringTable,
+ OUT CHAR16 **UnicodeString
+ );
+
+/**
+ This function looks up a Unicode string in UnicodeStringTable.
+
+ If Language is a member of SupportedLanguages and a Unicode string is found in
+ UnicodeStringTable that matches the language code specified by Language, then
+ it is returned in UnicodeString.
+
+ @param Language A pointer to an ASCII string containing the ISO 639-2 or the
+ RFC 4646 language code for the Unicode string to look up and
+ return. If Iso639Language is TRUE, then this ASCII string is
+ not assumed to be Null-terminated, and only the first three
+ characters are used. If Iso639Language is FALSE, then this ASCII
+ string must be Null-terminated.
+ @param SupportedLanguages A pointer to a Null-terminated ASCII string that contains a
+ set of ISO 639-2 or RFC 4646 language codes that the Unicode
+ string table supports. Language must be a member of this set.
+ If Iso639Language is TRUE, then this string contains one or more
+ ISO 639-2 language codes with no separator characters. If Iso639Language
+ is FALSE, then is string contains one or more RFC 4646 language
+ codes separated by ';'.
+ @param UnicodeStringTable A pointer to the table of Unicode strings. Type EFI_UNICODE_STRING_TABLE
+ is defined in "Related Definitions".
+ @param UnicodeString A pointer to the Null-terminated Unicode string from UnicodeStringTable
+ that matches the language specified by Language.
+ @param Iso639Language Specifies the supported language code format. If it is TRUE, then
+ Language and SupportedLanguages follow ISO 639-2 language code format.
+ Otherwise, they follow the RFC 4646 language code format.
+
+
+ @retval EFI_SUCCESS The Unicode string that matches the language specified by Language
+ was found in the table of Unicode strings UnicodeStringTable, and
+ it was returned in UnicodeString.
+ @retval EFI_INVALID_PARAMETER Language is NULL.
+ @retval EFI_INVALID_PARAMETER UnicodeString is NULL.
+ @retval EFI_UNSUPPORTED SupportedLanguages is NULL.
+ @retval EFI_UNSUPPORTED UnicodeStringTable is NULL.
+ @retval EFI_UNSUPPORTED The language specified by Language is not a member of SupportedLanguages.
+ @retval EFI_UNSUPPORTED The language specified by Language is not supported by UnicodeStringTable.
+
+**/
+EFI_STATUS
+EFIAPI
+LookupUnicodeString2 (
+ IN CONST CHAR8 *Language,
+ IN CONST CHAR8 *SupportedLanguages,
+ IN CONST EFI_UNICODE_STRING_TABLE *UnicodeStringTable,
+ OUT CHAR16 **UnicodeString,
+ IN BOOLEAN Iso639Language
+ );
+
+/**
+ This function adds a Unicode string to UnicodeStringTable.
+
+ If Language is a member of SupportedLanguages then UnicodeString is added to
+ UnicodeStringTable. New buffers are allocated for both Language and
+ UnicodeString. The contents of Language and UnicodeString are copied into
+ these new buffers. These buffers are automatically freed when
+ FreeUnicodeStringTable() is called.
+
+ @param Language A pointer to the ISO 639-2 language code for the Unicode
+ string to add.
+ @param SupportedLanguages A pointer to the set of ISO 639-2 language codes
+ that the Unicode string table supports.
+ Language must be a member of this set.
+ @param UnicodeStringTable A pointer to the table of Unicode strings.
+ @param UnicodeString A pointer to the Unicode string to add.
+
+ @retval EFI_SUCCESS The Unicode string that matches the language
+ specified by Language was found in the table of
+ Unicode strings UnicodeStringTable, and it was
+ returned in UnicodeString.
+ @retval EFI_INVALID_PARAMETER Language is NULL.
+ @retval EFI_INVALID_PARAMETER UnicodeString is NULL.
+ @retval EFI_INVALID_PARAMETER UnicodeString is an empty string.
+ @retval EFI_UNSUPPORTED SupportedLanguages is NULL.
+ @retval EFI_ALREADY_STARTED A Unicode string with language Language is
+ already present in UnicodeStringTable.
+ @retval EFI_OUT_OF_RESOURCES There is not enough memory to add another
+ Unicode string to UnicodeStringTable.
+ @retval EFI_UNSUPPORTED The language specified by Language is not a
+ member of SupportedLanguages.
+
+**/
+EFI_STATUS
+EFIAPI
+AddUnicodeString (
+ IN CONST CHAR8 *Language,
+ IN CONST CHAR8 *SupportedLanguages,
+ IN OUT EFI_UNICODE_STRING_TABLE **UnicodeStringTable,
+ IN CONST CHAR16 *UnicodeString
+ );
+
+/**
+ This function adds the Null-terminated Unicode string specified by UnicodeString
+ to UnicodeStringTable.
+
+ If Language is a member of SupportedLanguages then UnicodeString is added to
+ UnicodeStringTable. New buffers are allocated for both Language and UnicodeString.
+ The contents of Language and UnicodeString are copied into these new buffers.
+ These buffers are automatically freed when EfiLibFreeUnicodeStringTable() is called.
+
+ @param Language A pointer to an ASCII string containing the ISO 639-2 or
+ the RFC 4646 language code for the Unicode string to add.
+ If Iso639Language is TRUE, then this ASCII string is not
+ assumed to be Null-terminated, and only the first three
+ chacters are used. If Iso639Language is FALSE, then this
+ ASCII string must be Null-terminated.
+ @param SupportedLanguages A pointer to a Null-terminated ASCII string that contains
+ a set of ISO 639-2 or RFC 4646 language codes that the Unicode
+ string table supports. Language must be a member of this set.
+ If Iso639Language is TRUE, then this string contains one or more
+ ISO 639-2 language codes with no separator characters.
+ If Iso639Language is FALSE, then is string contains one or more
+ RFC 4646 language codes separated by ';'.
+ @param UnicodeStringTable A pointer to the table of Unicode strings. Type EFI_UNICODE_STRING_TABLE
+ is defined in "Related Definitions".
+ @param UnicodeString A pointer to the Unicode string to add.
+ @param Iso639Language Specifies the supported language code format. If it is TRUE,
+ then Language and SupportedLanguages follow ISO 639-2 language code format.
+ Otherwise, they follow RFC 4646 language code format.
+
+ @retval EFI_SUCCESS The Unicode string that matches the language specified by
+ Language was found in the table of Unicode strings UnicodeStringTable,
+ and it was returned in UnicodeString.
+ @retval EFI_INVALID_PARAMETER Language is NULL.
+ @retval EFI_INVALID_PARAMETER UnicodeString is NULL.
+ @retval EFI_INVALID_PARAMETER UnicodeString is an empty string.
+ @retval EFI_UNSUPPORTED SupportedLanguages is NULL.
+ @retval EFI_ALREADY_STARTED A Unicode string with language Language is already present in
+ UnicodeStringTable.
+ @retval EFI_OUT_OF_RESOURCES There is not enough memory to add another Unicode string UnicodeStringTable.
+ @retval EFI_UNSUPPORTED The language specified by Language is not a member of SupportedLanguages.
+
+**/
+EFI_STATUS
+EFIAPI
+AddUnicodeString2 (
+ IN CONST CHAR8 *Language,
+ IN CONST CHAR8 *SupportedLanguages,
+ IN OUT EFI_UNICODE_STRING_TABLE **UnicodeStringTable,
+ IN CONST CHAR16 *UnicodeString,
+ IN BOOLEAN Iso639Language
+ );
+
+/**
+ This function frees the table of Unicode strings in UnicodeStringTable.
+
+ If UnicodeStringTable is NULL, then EFI_SUCCESS is returned.
+ Otherwise, each language code, and each Unicode string in the Unicode string
+ table are freed, and EFI_SUCCESS is returned.
+
+ @param UnicodeStringTable A pointer to the table of Unicode strings.
+
+ @retval EFI_SUCCESS The Unicode string table was freed.
+
+**/
+EFI_STATUS
+EFIAPI
+FreeUnicodeStringTable (
+ IN EFI_UNICODE_STRING_TABLE *UnicodeStringTable
+ );
+
+/**
+ Returns the status whether get the variable success. The function retrieves
+ variable through the UEFI Runtime Service GetVariable(). The
+ returned buffer is allocated using AllocatePool(). The caller is responsible
+ for freeing this buffer with FreePool().
+
+ If Name is NULL, then ASSERT().
+ If Guid is NULL, then ASSERT().
+ If Value is NULL, then ASSERT().
+
+ @param[in] Name The pointer to a Null-terminated Unicode string.
+ @param[in] Guid The pointer to an EFI_GUID structure
+ @param[out] Value The buffer point saved the variable info.
+ @param[out] Size The buffer size of the variable.
+
+ @retval EFI_OUT_OF_RESOURCES Allocate buffer failed.
+ @retval EFI_SUCCESS Find the specified variable.
+ @retval Others Errors Return errors from call to gRT->GetVariable.
+
+**/
+EFI_STATUS
+EFIAPI
+GetVariable2 (
+ IN CONST CHAR16 *Name,
+ IN CONST EFI_GUID *Guid,
+ OUT VOID **Value,
+ OUT UINTN *Size OPTIONAL
+ );
+
+/**
+ Returns a pointer to an allocated buffer that contains the contents of a
+ variable retrieved through the UEFI Runtime Service GetVariable(). This
+ function always uses the EFI_GLOBAL_VARIABLE GUID to retrieve variables.
+ The returned buffer is allocated using AllocatePool(). The caller is
+ responsible for freeing this buffer with FreePool().
+
+ If Name is NULL, then ASSERT().
+ If Value is NULL, then ASSERT().
+
+ @param[in] Name The pointer to a Null-terminated Unicode string.
+ @param[out] Value The buffer point saved the variable info.
+ @param[out] Size The buffer size of the variable.
+
+ @retval EFI_OUT_OF_RESOURCES Allocate buffer failed.
+ @retval EFI_SUCCESS Find the specified variable.
+ @retval Others Errors Return errors from call to gRT->GetVariable.
+
+**/
+EFI_STATUS
+EFIAPI
+GetEfiGlobalVariable2 (
+ IN CONST CHAR16 *Name,
+ OUT VOID **Value,
+ OUT UINTN *Size OPTIONAL
+ );
+
+/** Return the attributes of the variable.
+
+ Returns the status whether get the variable success. The function retrieves
+ variable through the UEFI Runtime Service GetVariable(). The
+ returned buffer is allocated using AllocatePool(). The caller is responsible
+ for freeing this buffer with FreePool(). The attributes are returned if
+ the caller provides a valid Attribute parameter.
+
+ If Name is NULL, then ASSERT().
+ If Guid is NULL, then ASSERT().
+ If Value is NULL, then ASSERT().
+
+ @param[in] Name The pointer to a Null-terminated Unicode string.
+ @param[in] Guid The pointer to an EFI_GUID structure
+ @param[out] Value The buffer point saved the variable info.
+ @param[out] Size The buffer size of the variable.
+ @param[out] Attr The pointer to the variable attributes as found in var store
+
+ @retval EFI_OUT_OF_RESOURCES Allocate buffer failed.
+ @retval EFI_SUCCESS Find the specified variable.
+ @retval Others Errors Return errors from call to gRT->GetVariable.
+
+**/
+EFI_STATUS
+EFIAPI
+GetVariable3 (
+ IN CONST CHAR16 *Name,
+ IN CONST EFI_GUID *Guid,
+ OUT VOID **Value,
+ OUT UINTN *Size OPTIONAL,
+ OUT UINT32 *Attr OPTIONAL
+ );
+
+/**
+ Returns a pointer to an allocated buffer that contains the best matching language
+ from a set of supported languages.
+
+ This function supports both ISO 639-2 and RFC 4646 language codes, but language
+ code types may not be mixed in a single call to this function. The language
+ code returned is allocated using AllocatePool(). The caller is responsible for
+ freeing the allocated buffer using FreePool(). This function supports a variable
+ argument list that allows the caller to pass in a prioritized list of language
+ codes to test against all the language codes in SupportedLanguages.
+
+ If SupportedLanguages is NULL, then ASSERT().
+
+ @param[in] SupportedLanguages A pointer to a Null-terminated ASCII string that
+ contains a set of language codes in the format
+ specified by Iso639Language.
+ @param[in] Iso639Language If not zero, then all language codes are assumed to be
+ in ISO 639-2 format. If zero, then all language
+ codes are assumed to be in RFC 4646 language format
+ @param[in] ... A variable argument list that contains pointers to
+ Null-terminated ASCII strings that contain one or more
+ language codes in the format specified by Iso639Language.
+ The first language code from each of these language
+ code lists is used to determine if it is an exact or
+ close match to any of the language codes in
+ SupportedLanguages. Close matches only apply to RFC 4646
+ language codes, and the matching algorithm from RFC 4647
+ is used to determine if a close match is present. If
+ an exact or close match is found, then the matching
+ language code from SupportedLanguages is returned. If
+ no matches are found, then the next variable argument
+ parameter is evaluated. The variable argument list
+ is terminated by a NULL.
+
+ @retval NULL The best matching language could not be found in SupportedLanguages.
+ @retval NULL There are not enough resources available to return the best matching
+ language.
+ @retval Other A pointer to a Null-terminated ASCII string that is the best matching
+ language in SupportedLanguages.
+
+**/
+CHAR8 *
+EFIAPI
+GetBestLanguage (
+ IN CONST CHAR8 *SupportedLanguages,
+ IN UINTN Iso639Language,
+ ...
+ );
+
+/**
+ Draws a dialog box to the console output device specified by
+ ConOut defined in the EFI_SYSTEM_TABLE and waits for a keystroke
+ from the console input device specified by ConIn defined in the
+ EFI_SYSTEM_TABLE.
+
+ If there are no strings in the variable argument list, then ASSERT().
+ If all the strings in the variable argument list are empty, then ASSERT().
+
+ @param[in] Attribute Specifies the foreground and background color of the popup.
+ @param[out] Key A pointer to the EFI_KEY value of the key that was
+ pressed. This is an optional parameter that may be NULL.
+ If it is NULL then no wait for a keypress will be performed.
+ @param[in] ... The variable argument list that contains pointers to Null-
+ terminated Unicode strings to display in the dialog box.
+ The variable argument list is terminated by a NULL.
+
+**/
+VOID
+EFIAPI
+CreatePopUp (
+ IN UINTN Attribute,
+ OUT EFI_INPUT_KEY *Key OPTIONAL,
+ ...
+ );
+
+/**
+ Retrieves the width of a Unicode character.
+
+ This function computes and returns the width of the Unicode character specified
+ by UnicodeChar.
+
+ @param UnicodeChar A Unicode character.
+
+ @retval 0 The width if UnicodeChar could not be determined.
+ @retval 1 UnicodeChar is a narrow glyph.
+ @retval 2 UnicodeChar is a wide glyph.
+
+**/
+UINTN
+EFIAPI
+GetGlyphWidth (
+ IN CHAR16 UnicodeChar
+ );
+
+/**
+ Computes the display length of a Null-terminated Unicode String.
+
+ This function computes and returns the display length of the Null-terminated Unicode
+ string specified by String. If String is NULL then 0 is returned. If any of the widths
+ of the Unicode characters in String can not be determined, then 0 is returned. The display
+ width of String can be computed by summing the display widths of each Unicode character
+ in String. Unicode characters that are narrow glyphs have a width of 1, and Unicode
+ characters that are width glyphs have a width of 2.
+ If String is not aligned on a 16-bit boundary, then ASSERT().
+
+ @param String A pointer to a Null-terminated Unicode string.
+
+ @return The display length of the Null-terminated Unicode string specified by String.
+
+**/
+UINTN
+EFIAPI
+UnicodeStringDisplayLength (
+ IN CONST CHAR16 *String
+ );
+
+//
+// Functions that abstract early Framework contamination of UEFI.
+//
+
+/**
+ Create, Signal, and Close the Ready to Boot event using EfiSignalEventReadyToBoot().
+
+ This function abstracts the signaling of the Ready to Boot Event. The Framework moved
+ from a proprietary to UEFI 2.0 based mechanism. This library abstracts the caller
+ from how this event is created to prevent to code form having to change with the
+ version of the specification supported.
+
+**/
+VOID
+EFIAPI
+EfiSignalEventReadyToBoot (
+ VOID
+ );
+
+/**
+ Create, Signal, and Close the Ready to Boot event using EfiSignalEventLegacyBoot().
+
+ This function abstracts the signaling of the Legacy Boot Event. The Framework moved from
+ a proprietary to UEFI 2.0 based mechanism. This library abstracts the caller from how
+ this event is created to prevent to code form having to change with the version of the
+ specification supported.
+
+**/
+VOID
+EFIAPI
+EfiSignalEventLegacyBoot (
+ VOID
+ );
+
+/**
+ Creates an EFI event in the Legacy Boot Event Group.
+
+ Prior to UEFI 2.0 this was done via a non blessed UEFI extensions and this library
+ abstracts the implementation mechanism of this event from the caller. This function
+ abstracts the creation of the Legacy Boot Event. The Framework moved from a proprietary
+ to UEFI 2.0 based mechanism. This library abstracts the caller from how this event
+ is created to prevent to code form having to change with the version of the
+ specification supported.
+ If LegacyBootEvent is NULL, then ASSERT().
+
+ @param LegacyBootEvent Returns the EFI event returned from gBS->CreateEvent(Ex).
+
+ @retval EFI_SUCCESS The event was created.
+ @retval Other The event was not created.
+
+**/
+EFI_STATUS
+EFIAPI
+EfiCreateEventLegacyBoot (
+ OUT EFI_EVENT *LegacyBootEvent
+ );
+
+/**
+ Create an EFI event in the Legacy Boot Event Group and allows
+ the caller to specify a notification function.
+
+ This function abstracts the creation of the Legacy Boot Event.
+ The Framework moved from a proprietary to UEFI 2.0 based mechanism.
+ This library abstracts the caller from how this event is created to prevent
+ to code form having to change with the version of the specification supported.
+ If LegacyBootEvent is NULL, then ASSERT().
+
+ @param NotifyTpl The task priority level of the event.
+ @param NotifyFunction The notification function to call when the event is signaled.
+ @param NotifyContext The content to pass to NotifyFunction when the event is signaled.
+ @param LegacyBootEvent Returns the EFI event returned from gBS->CreateEvent(Ex).
+
+ @retval EFI_SUCCESS The event was created.
+ @retval Other The event was not created.
+
+**/
+EFI_STATUS
+EFIAPI
+EfiCreateEventLegacyBootEx (
+ IN EFI_TPL NotifyTpl,
+ IN EFI_EVENT_NOTIFY NotifyFunction OPTIONAL,
+ IN VOID *NotifyContext OPTIONAL,
+ OUT EFI_EVENT *LegacyBootEvent
+ );
+
+/**
+ Create an EFI event in the Ready To Boot Event Group.
+
+ Prior to UEFI 2.0 this was done via a non-standard UEFI extension, and this library
+ abstracts the implementation mechanism of this event from the caller.
+ This function abstracts the creation of the Ready to Boot Event. The Framework
+ moved from a proprietary to UEFI 2.0-based mechanism. This library abstracts
+ the caller from how this event is created to prevent the code form having to
+ change with the version of the specification supported.
+ If ReadyToBootEvent is NULL, then ASSERT().
+
+ @param ReadyToBootEvent Returns the EFI event returned from gBS->CreateEvent(Ex).
+
+ @retval EFI_SUCCESS The event was created.
+ @retval Other The event was not created.
+
+**/
+EFI_STATUS
+EFIAPI
+EfiCreateEventReadyToBoot (
+ OUT EFI_EVENT *ReadyToBootEvent
+ );
+
+/**
+ Create an EFI event in the Ready To Boot Event Group and allows
+ the caller to specify a notification function.
+
+ This function abstracts the creation of the Ready to Boot Event.
+ The Framework moved from a proprietary to UEFI 2.0 based mechanism.
+ This library abstracts the caller from how this event is created to prevent
+ to code form having to change with the version of the specification supported.
+ If ReadyToBootEvent is NULL, then ASSERT().
+
+ @param NotifyTpl The task priority level of the event.
+ @param NotifyFunction The notification function to call when the event is signaled.
+ @param NotifyContext The content to pass to NotifyFunction when the event is signaled.
+ @param ReadyToBootEvent Returns the EFI event returned from gBS->CreateEvent(Ex).
+
+ @retval EFI_SUCCESS The event was created.
+ @retval Other The event was not created.
+
+**/
+EFI_STATUS
+EFIAPI
+EfiCreateEventReadyToBootEx (
+ IN EFI_TPL NotifyTpl,
+ IN EFI_EVENT_NOTIFY NotifyFunction OPTIONAL,
+ IN VOID *NotifyContext OPTIONAL,
+ OUT EFI_EVENT *ReadyToBootEvent
+ );
+
+/**
+ Initialize a Firmware Volume (FV) Media Device Path node.
+
+ The Framework FwVol Device Path changed to conform to the UEFI 2.0 specification.
+ This library function abstracts initializing a device path node.
+ Initialize the MEDIA_FW_VOL_FILEPATH_DEVICE_PATH data structure. This device
+ path changed in the DXE CIS version 0.92 in a non back ward compatible way to
+ not conflict with the UEFI 2.0 specification. This function abstracts the
+ differences from the caller.
+ If FvDevicePathNode is NULL, then ASSERT().
+ If NameGuid is NULL, then ASSERT().
+
+ @param FvDevicePathNode The pointer to a FV device path node to initialize
+ @param NameGuid FV file name to use in FvDevicePathNode
+
+**/
+VOID
+EFIAPI
+EfiInitializeFwVolDevicepathNode (
+ IN OUT MEDIA_FW_VOL_FILEPATH_DEVICE_PATH *FvDevicePathNode,
+ IN CONST EFI_GUID *NameGuid
+ );
+
+/**
+ Check to see if the Firmware Volume (FV) Media Device Path is valid
+
+ The Framework FwVol Device Path changed to conform to the UEFI 2.0 specification.
+ This library function abstracts validating a device path node.
+ Check the MEDIA_FW_VOL_FILEPATH_DEVICE_PATH data structure to see if it's valid.
+ If it is valid, then return the GUID file name from the device path node. Otherwise,
+ return NULL. This device path changed in the DXE CIS version 0.92 in a non backward
+ compatible way to not conflict with the UEFI 2.0 specification. This function abstracts
+ the differences from the caller.
+ If FvDevicePathNode is NULL, then ASSERT().
+
+ @param FvDevicePathNode The pointer to FV device path to check.
+
+ @retval NULL FvDevicePathNode is not valid.
+ @retval Other FvDevicePathNode is valid and pointer to NameGuid was returned.
+
+**/
+EFI_GUID *
+EFIAPI
+EfiGetNameGuidFromFwVolDevicePathNode (
+ IN CONST MEDIA_FW_VOL_FILEPATH_DEVICE_PATH *FvDevicePathNode
+ );
+
+/**
+ Prints a formatted Unicode string to the console output device specified by
+ ConOut defined in the EFI_SYSTEM_TABLE.
+
+ This function prints a formatted Unicode string to the console output device
+ specified by ConOut in EFI_SYSTEM_TABLE and returns the number of Unicode
+ characters that printed to ConOut. If the length of the formatted Unicode
+ string is greater than PcdUefiLibMaxPrintBufferSize, then only the first
+ PcdUefiLibMaxPrintBufferSize characters are sent to ConOut.
+ If Format is NULL, then ASSERT().
+ If Format is not aligned on a 16-bit boundary, then ASSERT().
+ If gST->ConOut is NULL, then ASSERT().
+
+ @param Format A null-terminated Unicode format string.
+ @param ... The variable argument list whose contents are accessed based
+ on the format string specified by Format.
+
+ @return Number of Unicode characters printed to ConOut.
+
+**/
+UINTN
+EFIAPI
+Print (
+ IN CONST CHAR16 *Format,
+ ...
+ );
+
+/**
+ Prints a formatted Unicode string to the console output device specified by
+ StdErr defined in the EFI_SYSTEM_TABLE.
+
+ This function prints a formatted Unicode string to the console output device
+ specified by StdErr in EFI_SYSTEM_TABLE and returns the number of Unicode
+ characters that printed to StdErr. If the length of the formatted Unicode
+ string is greater than PcdUefiLibMaxPrintBufferSize, then only the first
+ PcdUefiLibMaxPrintBufferSize characters are sent to StdErr.
+ If Format is NULL, then ASSERT().
+ If Format is not aligned on a 16-bit boundary, then ASSERT().
+ If gST->StdErr is NULL, then ASSERT().
+
+ @param Format A null-terminated Unicode format string.
+ @param ... The variable argument list whose contents are accessed based
+ on the format string specified by Format.
+
+ @return Number of Unicode characters printed to StdErr.
+
+**/
+UINTN
+EFIAPI
+ErrorPrint (
+ IN CONST CHAR16 *Format,
+ ...
+ );
+
+/**
+ Prints a formatted ASCII string to the console output device specified by
+ ConOut defined in the EFI_SYSTEM_TABLE.
+
+ This function prints a formatted ASCII string to the console output device
+ specified by ConOut in EFI_SYSTEM_TABLE and returns the number of ASCII
+ characters that printed to ConOut. If the length of the formatted ASCII
+ string is greater than PcdUefiLibMaxPrintBufferSize, then only the first
+ PcdUefiLibMaxPrintBufferSize characters are sent to ConOut.
+ If Format is NULL, then ASSERT().
+ If gST->ConOut is NULL, then ASSERT().
+
+ @param Format A null-terminated ASCII format string.
+ @param ... The variable argument list whose contents are accessed based
+ on the format string specified by Format.
+
+ @return Number of ASCII characters printed to ConOut.
+
+**/
+UINTN
+EFIAPI
+AsciiPrint (
+ IN CONST CHAR8 *Format,
+ ...
+ );
+
+/**
+ Prints a formatted ASCII string to the console output device specified by
+ StdErr defined in the EFI_SYSTEM_TABLE.
+
+ This function prints a formatted ASCII string to the console output device
+ specified by StdErr in EFI_SYSTEM_TABLE and returns the number of ASCII
+ characters that printed to StdErr. If the length of the formatted ASCII
+ string is greater than PcdUefiLibMaxPrintBufferSize, then only the first
+ PcdUefiLibMaxPrintBufferSize characters are sent to StdErr.
+ If Format is NULL, then ASSERT().
+ If gST->StdErr is NULL, then ASSERT().
+
+ @param Format A null-terminated ASCII format string.
+ @param ... The variable argument list whose contents are accessed based
+ on the format string specified by Format.
+
+ @return Number of ASCII characters printed to ConErr.
+
+**/
+UINTN
+EFIAPI
+AsciiErrorPrint (
+ IN CONST CHAR8 *Format,
+ ...
+ );
+
+/**
+ Prints a formatted Unicode string to a graphics console device specified by
+ ConsoleOutputHandle defined in the EFI_SYSTEM_TABLE at the given (X,Y) coordinates.
+
+ This function prints a formatted Unicode string to the graphics console device
+ specified by ConsoleOutputHandle in EFI_SYSTEM_TABLE and returns the number of
+ Unicode characters displayed, not including partial characters that may be clipped
+ by the right edge of the display. If the length of the formatted Unicode string is
+ greater than PcdUefiLibMaxPrintBufferSize, then at most the first
+ PcdUefiLibMaxPrintBufferSize characters are printed. The EFI_HII_FONT_PROTOCOL
+ is used to convert the string to a bitmap using the glyphs registered with the
+ HII database. No wrapping is performed, so any portions of the string the fall
+ outside the active display region will not be displayed.
+
+ If a graphics console device is not associated with the ConsoleOutputHandle
+ defined in the EFI_SYSTEM_TABLE then no string is printed, and 0 is returned.
+ If the EFI_HII_FONT_PROTOCOL is not present in the handle database, then no
+ string is printed, and 0 is returned.
+ If Format is NULL, then ASSERT().
+ If Format is not aligned on a 16-bit boundary, then ASSERT().
+ If gST->ConsoleOutputHandle is NULL, then ASSERT().
+
+ @param PointX X coordinate to print the string.
+ @param PointY Y coordinate to print the string.
+ @param ForeGround The foreground color of the string being printed. This is
+ an optional parameter that may be NULL. If it is NULL,
+ then the foreground color of the current ConOut device
+ in the EFI_SYSTEM_TABLE is used.
+ @param BackGround The background color of the string being printed. This is
+ an optional parameter that may be NULL. If it is NULL,
+ then the background color of the current ConOut device
+ in the EFI_SYSTEM_TABLE is used.
+ @param Format A null-terminated Unicode format string. See Print Library
+ for the supported format string syntax.
+ @param ... Variable argument list whose contents are accessed based on
+ the format string specified by Format.
+
+ @return The number of Unicode characters printed.
+
+**/
+UINTN
+EFIAPI
+PrintXY (
+ IN UINTN PointX,
+ IN UINTN PointY,
+ IN EFI_GRAPHICS_OUTPUT_BLT_PIXEL *ForeGround OPTIONAL,
+ IN EFI_GRAPHICS_OUTPUT_BLT_PIXEL *BackGround OPTIONAL,
+ IN CONST CHAR16 *Format,
+ ...
+ );
+
+/**
+ Prints a formatted ASCII string to a graphics console device specified by
+ ConsoleOutputHandle defined in the EFI_SYSTEM_TABLE at the given (X,Y) coordinates.
+
+ This function prints a formatted ASCII string to the graphics console device
+ specified by ConsoleOutputHandle in EFI_SYSTEM_TABLE and returns the number of
+ ASCII characters displayed, not including partial characters that may be clipped
+ by the right edge of the display. If the length of the formatted ASCII string is
+ greater than PcdUefiLibMaxPrintBufferSize, then at most the first
+ PcdUefiLibMaxPrintBufferSize characters are printed. The EFI_HII_FONT_PROTOCOL
+ is used to convert the string to a bitmap using the glyphs registered with the
+ HII database. No wrapping is performed, so any portions of the string the fall
+ outside the active display region will not be displayed.
+
+ If a graphics console device is not associated with the ConsoleOutputHandle
+ defined in the EFI_SYSTEM_TABLE then no string is printed, and 0 is returned.
+ If the EFI_HII_FONT_PROTOCOL is not present in the handle database, then no
+ string is printed, and 0 is returned.
+ If Format is NULL, then ASSERT().
+ If gST->ConsoleOutputHandle is NULL, then ASSERT().
+
+ @param PointX X coordinate to print the string.
+ @param PointY Y coordinate to print the string.
+ @param ForeGround The foreground color of the string being printed. This is
+ an optional parameter that may be NULL. If it is NULL,
+ then the foreground color of the current ConOut device
+ in the EFI_SYSTEM_TABLE is used.
+ @param BackGround The background color of the string being printed. This is
+ an optional parameter that may be NULL. If it is NULL,
+ then the background color of the current ConOut device
+ in the EFI_SYSTEM_TABLE is used.
+ @param Format A null-terminated ASCII format string. See Print Library
+ for the supported format string syntax.
+ @param ... The variable argument list whose contents are accessed based on
+ the format string specified by Format.
+
+ @return The number of ASCII characters printed.
+
+**/
+UINTN
+EFIAPI
+AsciiPrintXY (
+ IN UINTN PointX,
+ IN UINTN PointY,
+ IN EFI_GRAPHICS_OUTPUT_BLT_PIXEL *ForeGround OPTIONAL,
+ IN EFI_GRAPHICS_OUTPUT_BLT_PIXEL *BackGround OPTIONAL,
+ IN CONST CHAR8 *Format,
+ ...
+ );
+
+/**
+ Installs and completes the initialization of a Driver Binding Protocol instance.
+
+ Installs the Driver Binding Protocol specified by DriverBinding onto the handle
+ specified by DriverBindingHandle. If DriverBindingHandle is NULL, then DriverBinding
+ is installed onto a newly created handle. DriverBindingHandle is typically the same
+ as the driver's ImageHandle, but it can be different if the driver produces multiple
+ Driver Binding Protocols.
+ If DriverBinding is NULL, then ASSERT().
+ If DriverBinding can not be installed onto a handle, then ASSERT().
+
+ @param ImageHandle The image handle of the driver.
+ @param SystemTable The EFI System Table that was passed to the driver's entry point.
+ @param DriverBinding A Driver Binding Protocol instance that this driver is producing.
+ @param DriverBindingHandle The handle that DriverBinding is to be installed onto. If this
+ parameter is NULL, then a new handle is created.
+
+ @retval EFI_SUCCESS The protocol installation completed successfully.
+ @retval EFI_OUT_OF_RESOURCES There was not enough system resources to install the protocol.
+ @retval Others Status from gBS->InstallMultipleProtocolInterfaces().
+
+**/
+EFI_STATUS
+EFIAPI
+EfiLibInstallDriverBinding (
+ IN CONST EFI_HANDLE ImageHandle,
+ IN CONST EFI_SYSTEM_TABLE *SystemTable,
+ IN EFI_DRIVER_BINDING_PROTOCOL *DriverBinding,
+ IN EFI_HANDLE DriverBindingHandle
+ );
+
+/**
+ Uninstalls a Driver Binding Protocol instance.
+
+ If DriverBinding is NULL, then ASSERT().
+ If DriverBinding can not be uninstalled, then ASSERT().
+
+ @param DriverBinding A Driver Binding Protocol instance that this driver produced.
+
+ @retval EFI_SUCCESS The protocol uninstallation successfully completed.
+ @retval Others Status from gBS->UninstallMultipleProtocolInterfaces().
+
+**/
+EFI_STATUS
+EFIAPI
+EfiLibUninstallDriverBinding (
+ IN EFI_DRIVER_BINDING_PROTOCOL *DriverBinding
+ );
+
+/**
+ Installs and completes the initialization of a Driver Binding Protocol instance and
+ optionally installs the Component Name, Driver Configuration and Driver Diagnostics Protocols.
+
+ Initializes a driver by installing the Driver Binding Protocol together with the
+ optional Component Name, optional Driver Configure and optional Driver Diagnostic
+ Protocols onto the driver's DriverBindingHandle. If DriverBindingHandle is NULL,
+ then the protocols are installed onto a newly created handle. DriverBindingHandle
+ is typically the same as the driver's ImageHandle, but it can be different if the
+ driver produces multiple Driver Binding Protocols.
+ If DriverBinding is NULL, then ASSERT().
+ If the installation fails, then ASSERT().
+
+ @param ImageHandle The image handle of the driver.
+ @param SystemTable The EFI System Table that was passed to the driver's entry point.
+ @param DriverBinding A Driver Binding Protocol instance that this driver is producing.
+ @param DriverBindingHandle The handle that DriverBinding is to be installed onto. If this
+ parameter is NULL, then a new handle is created.
+ @param ComponentName A Component Name Protocol instance that this driver is producing.
+ @param DriverConfiguration A Driver Configuration Protocol instance that this driver is producing.
+ @param DriverDiagnostics A Driver Diagnostics Protocol instance that this driver is producing.
+
+ @retval EFI_SUCCESS The protocol installation completed successfully.
+ @retval EFI_OUT_OF_RESOURCES There was not enough memory in the pool to install all the protocols.
+
+**/
+EFI_STATUS
+EFIAPI
+EfiLibInstallAllDriverProtocols (
+ IN CONST EFI_HANDLE ImageHandle,
+ IN CONST EFI_SYSTEM_TABLE *SystemTable,
+ IN EFI_DRIVER_BINDING_PROTOCOL *DriverBinding,
+ IN EFI_HANDLE DriverBindingHandle,
+ IN CONST EFI_COMPONENT_NAME_PROTOCOL *ComponentName OPTIONAL,
+ IN CONST EFI_DRIVER_CONFIGURATION_PROTOCOL *DriverConfiguration OPTIONAL,
+ IN CONST EFI_DRIVER_DIAGNOSTICS_PROTOCOL *DriverDiagnostics OPTIONAL
+ );
+
+/**
+ Uninstalls a Driver Binding Protocol instance and optionally uninstalls the
+ Component Name, Driver Configuration and Driver Diagnostics Protocols.
+
+ If DriverBinding is NULL, then ASSERT().
+ If the uninstallation fails, then ASSERT().
+
+ @param DriverBinding A Driver Binding Protocol instance that this driver produced.
+ @param ComponentName A Component Name Protocol instance that this driver produced.
+ @param DriverConfiguration A Driver Configuration Protocol instance that this driver produced.
+ @param DriverDiagnostics A Driver Diagnostics Protocol instance that this driver produced.
+
+ @retval EFI_SUCCESS The protocol uninstallation successfully completed.
+ @retval Others Status from gBS->UninstallMultipleProtocolInterfaces().
+
+**/
+EFI_STATUS
+EFIAPI
+EfiLibUninstallAllDriverProtocols (
+ IN EFI_DRIVER_BINDING_PROTOCOL *DriverBinding,
+ IN CONST EFI_COMPONENT_NAME_PROTOCOL *ComponentName OPTIONAL,
+ IN CONST EFI_DRIVER_CONFIGURATION_PROTOCOL *DriverConfiguration OPTIONAL,
+ IN CONST EFI_DRIVER_DIAGNOSTICS_PROTOCOL *DriverDiagnostics OPTIONAL
+ );
+
+/**
+ Installs Driver Binding Protocol with optional Component Name and Component Name 2 Protocols.
+
+ Initializes a driver by installing the Driver Binding Protocol together with the
+ optional Component Name and optional Component Name 2 protocols onto the driver's
+ DriverBindingHandle. If DriverBindingHandle is NULL, then the protocols are installed
+ onto a newly created handle. DriverBindingHandle is typically the same as the driver's
+ ImageHandle, but it can be different if the driver produces multiple Driver Binding Protocols.
+ If DriverBinding is NULL, then ASSERT().
+ If the installation fails, then ASSERT().
+
+ @param ImageHandle The image handle of the driver.
+ @param SystemTable The EFI System Table that was passed to the driver's entry point.
+ @param DriverBinding A Driver Binding Protocol instance that this driver is producing.
+ @param DriverBindingHandle The handle that DriverBinding is to be installed onto. If this
+ parameter is NULL, then a new handle is created.
+ @param ComponentName A Component Name Protocol instance that this driver is producing.
+ @param ComponentName2 A Component Name 2 Protocol instance that this driver is producing.
+
+ @retval EFI_SUCCESS The protocol installation completed successfully.
+ @retval EFI_OUT_OF_RESOURCES There was not enough memory in pool to install all the protocols.
+
+**/
+EFI_STATUS
+EFIAPI
+EfiLibInstallDriverBindingComponentName2 (
+ IN CONST EFI_HANDLE ImageHandle,
+ IN CONST EFI_SYSTEM_TABLE *SystemTable,
+ IN EFI_DRIVER_BINDING_PROTOCOL *DriverBinding,
+ IN EFI_HANDLE DriverBindingHandle,
+ IN CONST EFI_COMPONENT_NAME_PROTOCOL *ComponentName OPTIONAL,
+ IN CONST EFI_COMPONENT_NAME2_PROTOCOL *ComponentName2 OPTIONAL
+ );
+
+/**
+ Uninstalls Driver Binding Protocol with optional Component Name and Component Name 2 Protocols.
+
+ If DriverBinding is NULL, then ASSERT().
+ If the uninstallation fails, then ASSERT().
+
+ @param DriverBinding A Driver Binding Protocol instance that this driver produced.
+ @param ComponentName A Component Name Protocol instance that this driver produced.
+ @param ComponentName2 A Component Name 2 Protocol instance that this driver produced.
+
+ @retval EFI_SUCCESS The protocol installation successfully completed.
+ @retval Others Status from gBS->UninstallMultipleProtocolInterfaces().
+
+**/
+EFI_STATUS
+EFIAPI
+EfiLibUninstallDriverBindingComponentName2 (
+ IN EFI_DRIVER_BINDING_PROTOCOL *DriverBinding,
+ IN CONST EFI_COMPONENT_NAME_PROTOCOL *ComponentName OPTIONAL,
+ IN CONST EFI_COMPONENT_NAME2_PROTOCOL *ComponentName2 OPTIONAL
+ );
+
+/**
+ Installs Driver Binding Protocol with optional Component Name, Component Name 2, Driver
+ Configuration, Driver Configuration 2, Driver Diagnostics, and Driver Diagnostics 2 Protocols.
+
+ Initializes a driver by installing the Driver Binding Protocol together with the optional
+ Component Name, optional Component Name 2, optional Driver Configuration, optional Driver Configuration 2,
+ optional Driver Diagnostic, and optional Driver Diagnostic 2 Protocols onto the driver's DriverBindingHandle.
+ DriverBindingHandle is typically the same as the driver's ImageHandle, but it can be different if the driver
+ produces multiple Driver Binding Protocols.
+ If DriverBinding is NULL, then ASSERT().
+ If the installation fails, then ASSERT().
+
+
+ @param ImageHandle The image handle of the driver.
+ @param SystemTable The EFI System Table that was passed to the driver's entry point.
+ @param DriverBinding A Driver Binding Protocol instance that this driver is producing.
+ @param DriverBindingHandle The handle that DriverBinding is to be installed onto. If this
+ parameter is NULL, then a new handle is created.
+ @param ComponentName A Component Name Protocol instance that this driver is producing.
+ @param ComponentName2 A Component Name 2 Protocol instance that this driver is producing.
+ @param DriverConfiguration A Driver Configuration Protocol instance that this driver is producing.
+ @param DriverConfiguration2 A Driver Configuration Protocol 2 instance that this driver is producing.
+ @param DriverDiagnostics A Driver Diagnostics Protocol instance that this driver is producing.
+ @param DriverDiagnostics2 A Driver Diagnostics Protocol 2 instance that this driver is producing.
+
+ @retval EFI_SUCCESS The protocol installation completed successfully.
+ @retval EFI_OUT_OF_RESOURCES There was not enough memory in pool to install all the protocols.
+
+**/
+EFI_STATUS
+EFIAPI
+EfiLibInstallAllDriverProtocols2 (
+ IN CONST EFI_HANDLE ImageHandle,
+ IN CONST EFI_SYSTEM_TABLE *SystemTable,
+ IN EFI_DRIVER_BINDING_PROTOCOL *DriverBinding,
+ IN EFI_HANDLE DriverBindingHandle,
+ IN CONST EFI_COMPONENT_NAME_PROTOCOL *ComponentName OPTIONAL,
+ IN CONST EFI_COMPONENT_NAME2_PROTOCOL *ComponentName2 OPTIONAL,
+ IN CONST EFI_DRIVER_CONFIGURATION_PROTOCOL *DriverConfiguration OPTIONAL,
+ IN CONST EFI_DRIVER_CONFIGURATION2_PROTOCOL *DriverConfiguration2 OPTIONAL,
+ IN CONST EFI_DRIVER_DIAGNOSTICS_PROTOCOL *DriverDiagnostics OPTIONAL,
+ IN CONST EFI_DRIVER_DIAGNOSTICS2_PROTOCOL *DriverDiagnostics2 OPTIONAL
+ );
+
+/**
+ Uninstalls Driver Binding Protocol with optional Component Name, Component Name 2, Driver
+ Configuration, Driver Configuration 2, Driver Diagnostics, and Driver Diagnostics 2 Protocols.
+
+ If DriverBinding is NULL, then ASSERT().
+ If the installation fails, then ASSERT().
+
+
+ @param DriverBinding A Driver Binding Protocol instance that this driver produced.
+ @param ComponentName A Component Name Protocol instance that this driver produced.
+ @param ComponentName2 A Component Name 2 Protocol instance that this driver produced.
+ @param DriverConfiguration A Driver Configuration Protocol instance that this driver produced.
+ @param DriverConfiguration2 A Driver Configuration Protocol 2 instance that this driver produced.
+ @param DriverDiagnostics A Driver Diagnostics Protocol instance that this driver produced.
+ @param DriverDiagnostics2 A Driver Diagnostics Protocol 2 instance that this driver produced.
+
+ @retval EFI_SUCCESS The protocol uninstallation successfully completed.
+ @retval Others Status from gBS->UninstallMultipleProtocolInterfaces().
+
+**/
+EFI_STATUS
+EFIAPI
+EfiLibUninstallAllDriverProtocols2 (
+ IN EFI_DRIVER_BINDING_PROTOCOL *DriverBinding,
+ IN CONST EFI_COMPONENT_NAME_PROTOCOL *ComponentName OPTIONAL,
+ IN CONST EFI_COMPONENT_NAME2_PROTOCOL *ComponentName2 OPTIONAL,
+ IN CONST EFI_DRIVER_CONFIGURATION_PROTOCOL *DriverConfiguration OPTIONAL,
+ IN CONST EFI_DRIVER_CONFIGURATION2_PROTOCOL *DriverConfiguration2 OPTIONAL,
+ IN CONST EFI_DRIVER_DIAGNOSTICS_PROTOCOL *DriverDiagnostics OPTIONAL,
+ IN CONST EFI_DRIVER_DIAGNOSTICS2_PROTOCOL *DriverDiagnostics2 OPTIONAL
+ );
+
+/**
+ Appends a formatted Unicode string to a Null-terminated Unicode string
+
+ This function appends a formatted Unicode string to the Null-terminated
+ Unicode string specified by String. String is optional and may be NULL.
+ Storage for the formatted Unicode string returned is allocated using
+ AllocatePool(). The pointer to the appended string is returned. The caller
+ is responsible for freeing the returned string.
+
+ If String is not NULL and not aligned on a 16-bit boundary, then ASSERT().
+ If FormatString is NULL, then ASSERT().
+ If FormatString is not aligned on a 16-bit boundary, then ASSERT().
+
+ @param[in] String A Null-terminated Unicode string.
+ @param[in] FormatString A Null-terminated Unicode format string.
+ @param[in] Marker VA_LIST marker for the variable argument list.
+
+ @retval NULL There was not enough available memory.
+ @return Null-terminated Unicode string is that is the formatted
+ string appended to String.
+**/
+CHAR16 *
+EFIAPI
+CatVSPrint (
+ IN CHAR16 *String OPTIONAL,
+ IN CONST CHAR16 *FormatString,
+ IN VA_LIST Marker
+ );
+
+/**
+ Appends a formatted Unicode string to a Null-terminated Unicode string
+
+ This function appends a formatted Unicode string to the Null-terminated
+ Unicode string specified by String. String is optional and may be NULL.
+ Storage for the formatted Unicode string returned is allocated using
+ AllocatePool(). The pointer to the appended string is returned. The caller
+ is responsible for freeing the returned string.
+
+ If String is not NULL and not aligned on a 16-bit boundary, then ASSERT().
+ If FormatString is NULL, then ASSERT().
+ If FormatString is not aligned on a 16-bit boundary, then ASSERT().
+
+ @param[in] String A Null-terminated Unicode string.
+ @param[in] FormatString A Null-terminated Unicode format string.
+ @param[in] ... The variable argument list whose contents are
+ accessed based on the format string specified by
+ FormatString.
+
+ @retval NULL There was not enough available memory.
+ @return Null-terminated Unicode string is that is the formatted
+ string appended to String.
+**/
+CHAR16 *
+EFIAPI
+CatSPrint (
+ IN CHAR16 *String OPTIONAL,
+ IN CONST CHAR16 *FormatString,
+ ...
+ );
+
+/**
+ Returns an array of protocol instance that matches the given protocol.
+
+ @param[in] Protocol Provides the protocol to search for.
+ @param[out] NoProtocols The number of protocols returned in Buffer.
+ @param[out] Buffer A pointer to the buffer to return the requested
+ array of protocol instances that match Protocol.
+ The returned buffer is allocated using
+ EFI_BOOT_SERVICES.AllocatePool(). The caller is
+ responsible for freeing this buffer with
+ EFI_BOOT_SERVICES.FreePool().
+
+ @retval EFI_SUCCESS The array of protocols was returned in Buffer,
+ and the number of protocols in Buffer was
+ returned in NoProtocols.
+ @retval EFI_NOT_FOUND No protocols found.
+ @retval EFI_OUT_OF_RESOURCES There is not enough pool memory to store the
+ matching results.
+ @retval EFI_INVALID_PARAMETER Protocol is NULL.
+ @retval EFI_INVALID_PARAMETER NoProtocols is NULL.
+ @retval EFI_INVALID_PARAMETER Buffer is NULL.
+
+**/
+EFI_STATUS
+EFIAPI
+EfiLocateProtocolBuffer (
+ IN EFI_GUID *Protocol,
+ OUT UINTN *NoProtocols,
+ OUT VOID ***Buffer
+ );
+
+/**
+ Open or create a file or directory, possibly creating the chain of
+ directories leading up to the directory.
+
+ EfiOpenFileByDevicePath() first locates EFI_SIMPLE_FILE_SYSTEM_PROTOCOL on
+ FilePath, and opens the root directory of that filesystem with
+ EFI_SIMPLE_FILE_SYSTEM_PROTOCOL.OpenVolume().
+
+ On the remaining device path, the longest initial sequence of
+ FILEPATH_DEVICE_PATH nodes is node-wise traversed with
+ EFI_FILE_PROTOCOL.Open().
+
+ (As a consequence, if OpenMode includes EFI_FILE_MODE_CREATE, and Attributes
+ includes EFI_FILE_DIRECTORY, and each FILEPATH_DEVICE_PATH specifies a single
+ pathname component, then EfiOpenFileByDevicePath() ensures that the specified
+ series of subdirectories exist on return.)
+
+ The EFI_FILE_PROTOCOL identified by the last FILEPATH_DEVICE_PATH node is
+ output to the caller; intermediate EFI_FILE_PROTOCOL instances are closed. If
+ there are no FILEPATH_DEVICE_PATH nodes past the node that identifies the
+ filesystem, then the EFI_FILE_PROTOCOL of the root directory of the
+ filesystem is output to the caller. If a device path node that is different
+ from FILEPATH_DEVICE_PATH is encountered relative to the filesystem, the
+ traversal is stopped with an error, and a NULL EFI_FILE_PROTOCOL is output.
+
+ @param[in,out] FilePath On input, the device path to the file or directory
+ to open or create. The caller is responsible for
+ ensuring that the device path pointed-to by FilePath
+ is well-formed. On output, FilePath points one past
+ the last node in the original device path that has
+ been successfully processed. FilePath is set on
+ output even if EfiOpenFileByDevicePath() returns an
+ error.
+
+ @param[out] File On error, File is set to NULL. On success, File is
+ set to the EFI_FILE_PROTOCOL of the root directory
+ of the filesystem, if there are no
+ FILEPATH_DEVICE_PATH nodes in FilePath; otherwise,
+ File is set to the EFI_FILE_PROTOCOL identified by
+ the last node in FilePath.
+
+ @param[in] OpenMode The OpenMode parameter to pass to
+ EFI_FILE_PROTOCOL.Open().
+
+ @param[in] Attributes The Attributes parameter to pass to
+ EFI_FILE_PROTOCOL.Open().
+
+ @retval EFI_SUCCESS The file or directory has been opened or
+ created.
+
+ @retval EFI_INVALID_PARAMETER FilePath is NULL; or File is NULL; or FilePath
+ contains a device path node, past the node
+ that identifies
+ EFI_SIMPLE_FILE_SYSTEM_PROTOCOL, that is not a
+ FILEPATH_DEVICE_PATH node.
+
+ @retval EFI_OUT_OF_RESOURCES Memory allocation failed.
+
+ @return Error codes propagated from the
+ LocateDevicePath() and OpenProtocol() boot
+ services, and from the
+ EFI_SIMPLE_FILE_SYSTEM_PROTOCOL.OpenVolume()
+ and EFI_FILE_PROTOCOL.Open() member functions.
+**/
+EFI_STATUS
+EFIAPI
+EfiOpenFileByDevicePath (
+ IN OUT EFI_DEVICE_PATH_PROTOCOL **FilePath,
+ OUT EFI_FILE_PROTOCOL **File,
+ IN UINT64 OpenMode,
+ IN UINT64 Attributes
+ );
+
+/**
+ This function locates next ACPI table in XSDT/RSDT based on Signature and
+ previous returned Table.
+
+ If PreviousTable is NULL:
+ This function will locate the first ACPI table in XSDT/RSDT based on
+ Signature in gEfiAcpi20TableGuid system configuration table first, and then
+ gEfiAcpi10TableGuid system configuration table.
+ This function will locate in XSDT first, and then RSDT.
+ For DSDT, this function will locate XDsdt in FADT first, and then Dsdt in
+ FADT.
+ For FACS, this function will locate XFirmwareCtrl in FADT first, and then
+ FirmwareCtrl in FADT.
+
+ If PreviousTable is not NULL:
+ 1. If it could be located in XSDT in gEfiAcpi20TableGuid system configuration
+ table, then this function will just locate next table in XSDT in
+ gEfiAcpi20TableGuid system configuration table.
+ 2. If it could be located in RSDT in gEfiAcpi20TableGuid system configuration
+ table, then this function will just locate next table in RSDT in
+ gEfiAcpi20TableGuid system configuration table.
+ 3. If it could be located in RSDT in gEfiAcpi10TableGuid system configuration
+ table, then this function will just locate next table in RSDT in
+ gEfiAcpi10TableGuid system configuration table.
+
+ It's not supported that PreviousTable is not NULL but PreviousTable->Signature
+ is not same with Signature, NULL will be returned.
+
+ @param Signature ACPI table signature.
+ @param PreviousTable Pointer to previous returned table to locate next
+ table, or NULL to locate first table.
+
+ @return Next ACPI table or NULL if not found.
+
+**/
+EFI_ACPI_COMMON_HEADER *
+EFIAPI
+EfiLocateNextAcpiTable (
+ IN UINT32 Signature,
+ IN EFI_ACPI_COMMON_HEADER *PreviousTable OPTIONAL
+ );
+
+/**
+ This function locates first ACPI table in XSDT/RSDT based on Signature.
+
+ This function will locate the first ACPI table in XSDT/RSDT based on
+ Signature in gEfiAcpi20TableGuid system configuration table first, and then
+ gEfiAcpi10TableGuid system configuration table.
+ This function will locate in XSDT first, and then RSDT.
+ For DSDT, this function will locate XDsdt in FADT first, and then Dsdt in
+ FADT.
+ For FACS, this function will locate XFirmwareCtrl in FADT first, and then
+ FirmwareCtrl in FADT.
+
+ @param Signature ACPI table signature.
+
+ @return First ACPI table or NULL if not found.
+
+**/
+EFI_ACPI_COMMON_HEADER *
+EFIAPI
+EfiLocateFirstAcpiTable (
+ IN UINT32 Signature
+ );
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/UefiRuntimeLib.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/UefiRuntimeLib.h
new file mode 100644
index 0000000000..62cf71715e
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/UefiRuntimeLib.h
@@ -0,0 +1,577 @@
+/** @file
+ Provides library functions for each of the UEFI Runtime Services.
+ Only available to DXE and UEFI module types.
+
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef __UEFI_RUNTIME_LIB__
+#define __UEFI_RUNTIME_LIB__
+
+/**
+ This function allows the caller to determine if UEFI ExitBootServices() has been called.
+
+ This function returns TRUE after all the EVT_SIGNAL_EXIT_BOOT_SERVICES functions have
+ executed as a result of the OS calling ExitBootServices(). Prior to this time FALSE
+ is returned. This function is used by runtime code to decide it is legal to access
+ services that go away after ExitBootServices().
+
+ @retval TRUE The system has finished executing the EVT_SIGNAL_EXIT_BOOT_SERVICES event.
+ @retval FALSE The system has not finished executing the EVT_SIGNAL_EXIT_BOOT_SERVICES event.
+
+**/
+BOOLEAN
+EFIAPI
+EfiAtRuntime (
+ VOID
+ );
+
+/**
+ This function allows the caller to determine if UEFI SetVirtualAddressMap() has been called.
+
+ This function returns TRUE after all the EVT_SIGNAL_VIRTUAL_ADDRESS_CHANGE functions have
+ executed as a result of the OS calling SetVirtualAddressMap(). Prior to this time FALSE
+ is returned. This function is used by runtime code to decide it is legal to access services
+ that go away after SetVirtualAddressMap().
+
+ @retval TRUE The system has finished executing the EVT_SIGNAL_VIRTUAL_ADDRESS_CHANGE event.
+ @retval FALSE The system has not finished executing the EVT_SIGNAL_VIRTUAL_ADDRESS_CHANGE event.
+
+**/
+BOOLEAN
+EFIAPI
+EfiGoneVirtual (
+ VOID
+ );
+
+/**
+ This service is a wrapper for the UEFI Runtime Service GetTime().
+
+ The GetTime() function returns a time that was valid sometime during the call to the function.
+ While the returned EFI_TIME structure contains TimeZone and Daylight savings time information,
+ the actual clock does not maintain these values. The current time zone and daylight saving time
+ information returned by GetTime() are the values that were last set via SetTime().
+ The GetTime() function should take approximately the same amount of time to read the time each
+ time it is called. All reported device capabilities are to be rounded up.
+ During runtime, if a PC-AT CMOS device is present in the platform, the caller must synchronize
+ access to the device before calling GetTime().
+
+ @param Time A pointer to storage to receive a snapshot of the current time.
+ @param Capabilities An optional pointer to a buffer to receive the real time clock device's
+ capabilities.
+
+ @retval EFI_SUCCESS The operation completed successfully.
+ @retval EFI_INVALID_PARAMETER Time is NULL.
+ @retval EFI_DEVICE_ERROR The time could not be retrieved due to a hardware error.
+
+**/
+EFI_STATUS
+EFIAPI
+EfiGetTime (
+ OUT EFI_TIME *Time,
+ OUT EFI_TIME_CAPABILITIES *Capabilities OPTIONAL
+ );
+
+/**
+ This service is a wrapper for the UEFI Runtime Service SetTime().
+
+ The SetTime() function sets the real time clock device to the supplied time, and records the
+ current time zone and daylight savings time information. The SetTime() function is not allowed
+ to loop based on the current time. For example, if the device does not support a hardware reset
+ for the sub-resolution time, the code is not to implement the feature by waiting for the time to
+ wrap.
+ During runtime, if a PC-AT CMOS device is present in the platform, the caller must synchronize
+ access to the device before calling SetTime().
+
+ @param Time A pointer to the current time. Type EFI_TIME is defined in the GetTime()
+ function description. Full error checking is performed on the different
+ fields of the EFI_TIME structure (refer to the EFI_TIME definition in the
+ GetTime() function description for full details), and EFI_INVALID_PARAMETER
+ is returned if any field is out of range.
+
+ @retval EFI_SUCCESS The operation completed successfully.
+ @retval EFI_INVALID_PARAMETER A time field is out of range.
+ @retval EFI_DEVICE_ERROR The time could not be set due to a hardware error.
+
+**/
+EFI_STATUS
+EFIAPI
+EfiSetTime (
+ IN EFI_TIME *Time
+ );
+
+/**
+ This service is a wrapper for the UEFI Runtime Service GetWakeupTime().
+
+ The alarm clock time may be rounded from the set alarm clock time to be within the resolution
+ of the alarm clock device. The resolution of the alarm clock device is defined to be one second.
+ During runtime, if a PC-AT CMOS device is present in the platform the caller must synchronize
+ access to the device before calling GetWakeupTime().
+
+ @param Enabled Indicates if the alarm is currently enabled or disabled.
+ @param Pending Indicates if the alarm signal is pending and requires acknowledgement.
+ @param Time The current alarm setting. Type EFI_TIME is defined in the GetTime()
+ function description.
+
+ @retval EFI_SUCCESS The alarm settings were returned.
+ @retval EFI_INVALID_PARAMETER Enabled is NULL.
+ @retval EFI_INVALID_PARAMETER Pending is NULL.
+ @retval EFI_INVALID_PARAMETER Time is NULL.
+ @retval EFI_DEVICE_ERROR The wakeup time could not be retrieved due to a hardware error.
+ @retval EFI_UNSUPPORTED A wakeup timer is not supported on this platform.
+
+**/
+EFI_STATUS
+EFIAPI
+EfiGetWakeupTime (
+ OUT BOOLEAN *Enabled,
+ OUT BOOLEAN *Pending,
+ OUT EFI_TIME *Time
+ );
+
+/**
+ This service is a wrapper for the UEFI Runtime Service SetWakeupTime()
+
+ Setting a system wakeup alarm causes the system to wake up or power on at the set time.
+ When the alarm fires, the alarm signal is latched until it is acknowledged by calling SetWakeupTime()
+ to disable the alarm. If the alarm fires before the system is put into a sleeping or off state,
+ since the alarm signal is latched the system will immediately wake up. If the alarm fires while
+ the system is off and there is insufficient power to power on the system, the system is powered
+ on when power is restored.
+
+ @param Enable Enable or disable the wakeup alarm.
+ @param Time If Enable is TRUE, the time to set the wakeup alarm for. Type EFI_TIME
+ is defined in the GetTime() function description. If Enable is FALSE,
+ then this parameter is optional, and may be NULL.
+
+ @retval EFI_SUCCESS If Enable is TRUE, then the wakeup alarm was enabled.
+ If Enable is FALSE, then the wakeup alarm was disabled.
+ @retval EFI_INVALID_PARAMETER A time field is out of range.
+ @retval EFI_DEVICE_ERROR The wakeup time could not be set due to a hardware error.
+ @retval EFI_UNSUPPORTED A wakeup timer is not supported on this platform.
+
+**/
+EFI_STATUS
+EFIAPI
+EfiSetWakeupTime (
+ IN BOOLEAN Enable,
+ IN EFI_TIME *Time OPTIONAL
+ );
+
+/**
+ This service is a wrapper for the UEFI Runtime Service GetVariable().
+
+ Each vendor may create and manage its own variables without the risk of name conflicts by
+ using a unique VendorGuid. When a variable is set, its Attributes are supplied to indicate
+ how the data variable should be stored and maintained by the system. The attributes affect
+ when the variable may be accessed and volatility of the data. Any attempts to access a variable
+ that does not have the attribute set for runtime access will yield the EFI_NOT_FOUND error.
+ If the Data buffer is too small to hold the contents of the variable, the error EFI_BUFFER_TOO_SMALL
+ is returned and DataSize is set to the required buffer size to obtain the data.
+
+ @param VariableName the name of the vendor's variable, it's a Null-Terminated Unicode String
+ @param VendorGuid Unify identifier for vendor.
+ @param Attributes Point to memory location to return the attributes of variable. If the point
+ is NULL, the parameter would be ignored.
+ @param DataSize As input, point to the maximum size of return Data-Buffer.
+ As output, point to the actual size of the returned Data-Buffer.
+ @param Data Point to return Data-Buffer.
+
+ @retval EFI_SUCCESS The function completed successfully.
+ @retval EFI_NOT_FOUND The variable was not found.
+ @retval EFI_BUFFER_TOO_SMALL The DataSize is too small for the result. DataSize has
+ been updated with the size needed to complete the request.
+ @retval EFI_INVALID_PARAMETER VariableName is NULL.
+ @retval EFI_INVALID_PARAMETER VendorGuid is NULL.
+ @retval EFI_INVALID_PARAMETER DataSize is NULL.
+ @retval EFI_INVALID_PARAMETER The DataSize is not too small and Data is NULL.
+ @retval EFI_DEVICE_ERROR The variable could not be retrieved due to a hardware error.
+ @retval EFI_SECURITY_VIOLATION The variable could not be retrieved due to an authentication failure.
+**/
+EFI_STATUS
+EFIAPI
+EfiGetVariable (
+ IN CHAR16 *VariableName,
+ IN EFI_GUID *VendorGuid,
+ OUT UINT32 *Attributes OPTIONAL,
+ IN OUT UINTN *DataSize,
+ OUT VOID *Data
+ );
+
+/**
+ This service is a wrapper for the UEFI Runtime Service GetNextVariableName().
+
+ GetNextVariableName() is called multiple times to retrieve the VariableName and VendorGuid of
+ all variables currently available in the system. On each call to GetNextVariableName() the
+ previous results are passed into the interface, and on output the interface returns the next
+ variable name data. When the entire variable list has been returned, the error EFI_NOT_FOUND
+ is returned.
+
+ @param VariableNameSize As input, point to maximum size of variable name.
+ As output, point to actual size of variable name.
+ @param VariableName As input, supplies the last VariableName that was returned by
+ GetNextVariableName().
+ As output, returns the name of variable. The name
+ string is Null-Terminated Unicode string.
+ @param VendorGuid As input, supplies the last VendorGuid that was returned by
+ GetNextVriableName().
+ As output, returns the VendorGuid of the current variable.
+
+ @retval EFI_SUCCESS The function completed successfully.
+ @retval EFI_NOT_FOUND The next variable was not found.
+ @retval EFI_BUFFER_TOO_SMALL The VariableNameSize is too small for the result.
+ VariableNameSize has been updated with the size needed
+ to complete the request.
+ @retval EFI_INVALID_PARAMETER VariableNameSize is NULL.
+ @retval EFI_INVALID_PARAMETER VariableName is NULL.
+ @retval EFI_INVALID_PARAMETER VendorGuid is NULL.
+ @retval EFI_DEVICE_ERROR The variable name could not be retrieved due to a hardware error.
+
+**/
+EFI_STATUS
+EFIAPI
+EfiGetNextVariableName (
+ IN OUT UINTN *VariableNameSize,
+ IN OUT CHAR16 *VariableName,
+ IN OUT EFI_GUID *VendorGuid
+ );
+
+/**
+ This service is a wrapper for the UEFI Runtime Service GetNextVariableName()
+
+ Variables are stored by the firmware and may maintain their values across power cycles. Each vendor
+ may create and manage its own variables without the risk of name conflicts by using a unique VendorGuid.
+
+ @param VariableName the name of the vendor's variable, as a
+ Null-Terminated Unicode String
+ @param VendorGuid Unify identifier for vendor.
+ @param Attributes Point to memory location to return the attributes of variable. If the point
+ is NULL, the parameter would be ignored.
+ @param DataSize The size in bytes of Data-Buffer.
+ @param Data Point to the content of the variable.
+
+ @retval EFI_SUCCESS The firmware has successfully stored the variable and its data as
+ defined by the Attributes.
+ @retval EFI_INVALID_PARAMETER An invalid combination of attribute bits was supplied, or the
+ DataSize exceeds the maximum allowed.
+ @retval EFI_INVALID_PARAMETER VariableName is an empty Unicode string.
+ @retval EFI_OUT_OF_RESOURCES Not enough storage is available to hold the variable and its data.
+ @retval EFI_DEVICE_ERROR The variable could not be saved due to a hardware failure.
+ @retval EFI_WRITE_PROTECTED The variable in question is read-only.
+ @retval EFI_WRITE_PROTECTED The variable in question cannot be deleted.
+ @retval EFI_SECURITY_VIOLATION The variable could not be written due to EFI_VARIABLE_AUTHENTICATED_WRITE_ACCESS
+ set but the AuthInfo does NOT pass the validation check carried
+ out by the firmware.
+ @retval EFI_NOT_FOUND The variable trying to be updated or deleted was not found.
+
+**/
+EFI_STATUS
+EFIAPI
+EfiSetVariable (
+ IN CHAR16 *VariableName,
+ IN EFI_GUID *VendorGuid,
+ IN UINT32 Attributes,
+ IN UINTN DataSize,
+ IN VOID *Data
+ );
+
+/**
+ This service is a wrapper for the UEFI Runtime Service GetNextHighMonotonicCount().
+
+ The platform's monotonic counter is comprised of two 32-bit quantities: the high 32 bits and
+ the low 32 bits. During boot service time the low 32-bit value is volatile: it is reset to zero
+ on every system reset and is increased by 1 on every call to GetNextMonotonicCount(). The high
+ 32-bit value is nonvolatile and is increased by 1 whenever the system resets or whenever the low
+ 32-bit count (returned by GetNextMonoticCount()) overflows.
+
+ @param HighCount Pointer to returned value.
+
+ @retval EFI_SUCCESS The next high monotonic count was returned.
+ @retval EFI_DEVICE_ERROR The device is not functioning properly.
+ @retval EFI_INVALID_PARAMETER HighCount is NULL.
+
+**/
+EFI_STATUS
+EFIAPI
+EfiGetNextHighMonotonicCount (
+ OUT UINT32 *HighCount
+ );
+
+/**
+ This service is a wrapper for the UEFI Runtime Service ResetSystem().
+
+ The ResetSystem()function resets the entire platform, including all processors and devices,and reboots the system.
+ Calling this interface with ResetType of EfiResetCold causes a system-wide reset. This sets all circuitry within
+ the system to its initial state. This type of reset is asynchronous to system operation and operates without regard
+ to cycle boundaries. EfiResetCold is tantamount to a system power cycle.
+ Calling this interface with ResetType of EfiResetWarm causes a system-wide initialization. The processors are set to
+ their initial state, and pending cycles are not corrupted. If the system does not support this reset type, then an
+ EfiResetCold must be performed.
+ Calling this interface with ResetType of EfiResetShutdown causes the system to enter a power state equivalent to the
+ ACPI G2/S5 or G3 states. If the system does not support this reset type, then when the system is rebooted, it should
+ exhibit the EfiResetCold attributes.
+ The platform may optionally log the parameters from any non-normal reset that occurs.
+ The ResetSystem() function does not return.
+
+ @param ResetType The type of reset to perform.
+ @param ResetStatus The status code for the reset. If the system reset is part of a normal operation, the status code
+ would be EFI_SUCCESS. If the system reset is due to some type of failure the most appropriate EFI
+ Status code would be used.
+ @param DataSizeThe size, in bytes, of ResetData.
+ @param ResetData For a ResetType of EfiResetCold, EfiResetWarm, or EfiResetShutdown the data buffer starts with a
+ Null-terminated Unicode string, optionally followed by additional binary data. The string is a
+ description that the caller may use to further indicate the reason for the system reset. ResetData
+ is only valid if ResetStatus is something other then EFI_SUCCESS. This pointer must be a physical
+ address. For a ResetType of EfiResetPlatformSpecific the data buffer also starts with a Null-terminated
+ string that is followed by an EFI_GUID that describes the specific type of reset to perform.
+**/
+VOID
+EFIAPI
+EfiResetSystem (
+ IN EFI_RESET_TYPE ResetType,
+ IN EFI_STATUS ResetStatus,
+ IN UINTN DataSize,
+ IN VOID *ResetData OPTIONAL
+ );
+
+/**
+ This service is a wrapper for the UEFI Runtime Service ConvertPointer().
+
+ The ConvertPointer() function is used by an EFI component during the SetVirtualAddressMap() operation.
+ ConvertPointer()must be called using physical address pointers during the execution of SetVirtualAddressMap().
+
+ @param DebugDisposition Supplies type information for the pointer being converted.
+ @param Address The pointer to a pointer that is to be fixed to be the
+ value needed for the new virtual address mapping being
+ applied.
+
+ @retval EFI_SUCCESS The pointer pointed to by Address was modified.
+ @retval EFI_NOT_FOUND The pointer pointed to by Address was not found to be part of
+ the current memory map. This is normally fatal.
+ @retval EFI_INVALID_PARAMETER Address is NULL.
+ @retval EFI_INVALID_PARAMETER *Address is NULL and DebugDispositio
+
+**/
+EFI_STATUS
+EFIAPI
+EfiConvertPointer (
+ IN UINTN DebugDisposition,
+ IN OUT VOID **Address
+ );
+
+/**
+ Determines the new virtual address that is to be used on subsequent memory accesses.
+
+ For IA32, x64, and EBC, this service is a wrapper for the UEFI Runtime Service
+ ConvertPointer(). See the UEFI Specification for details.
+ For IPF, this function interprets Address as a pointer to an EFI_PLABEL structure
+ and both the EntryPoint and GP fields of an EFI_PLABEL are converted from physical
+ to virtiual addressing. Since IPF allows the GP to point to an address outside
+ a PE/COFF image, the physical to virtual offset for the EntryPoint field is used
+ to adjust the GP field. The UEFI Runtime Service ConvertPointer() is used to convert
+ EntryPoint and the status code for this conversion is always returned. If the convertion
+ of EntryPoint fails, then neither EntryPoint nor GP are modified. See the UEFI
+ Specification for details on the UEFI Runtime Service ConvertPointer().
+
+ @param DebugDisposition Supplies type information for the pointer being converted.
+ @param Address The pointer to a pointer that is to be fixed to be the
+ value needed for the new virtual address mapping being
+ applied.
+
+ @return EFI_STATUS value from EfiConvertPointer().
+
+**/
+EFI_STATUS
+EFIAPI
+EfiConvertFunctionPointer (
+ IN UINTN DebugDisposition,
+ IN OUT VOID **Address
+ );
+
+/**
+ This service is a wrapper for the UEFI Runtime Service SetVirtualAddressMap().
+
+ The SetVirtualAddressMap() function is used by the OS loader. The function can only be called
+ at runtime, and is called by the owner of the system's memory map. I.e., the component which
+ called ExitBootServices(). All events of type EVT_SIGNAL_VIRTUAL_ADDRESS_CHANGE must be signaled
+ before SetVirtualAddressMap() returns.
+
+ @param MemoryMapSize The size in bytes of VirtualMap.
+ @param DescriptorSize The size in bytes of an entry in the VirtualMap.
+ @param DescriptorVersion The version of the structure entries in VirtualMap.
+ @param VirtualMap An array of memory descriptors which contain new virtual
+ address mapping information for all runtime ranges. Type
+ EFI_MEMORY_DESCRIPTOR is defined in the
+ GetMemoryMap() function description.
+
+ @retval EFI_SUCCESS The virtual address map has been applied.
+ @retval EFI_UNSUPPORTED EFI firmware is not at runtime, or the EFI firmware is already in
+ virtual address mapped mode.
+ @retval EFI_INVALID_PARAMETER DescriptorSize or DescriptorVersion is
+ invalid.
+ @retval EFI_NO_MAPPING A virtual address was not supplied for a range in the memory
+ map that requires a mapping.
+ @retval EFI_NOT_FOUND A virtual address was supplied for an address that is not found
+ in the memory map.
+**/
+EFI_STATUS
+EFIAPI
+EfiSetVirtualAddressMap (
+ IN UINTN MemoryMapSize,
+ IN UINTN DescriptorSize,
+ IN UINT32 DescriptorVersion,
+ IN CONST EFI_MEMORY_DESCRIPTOR *VirtualMap
+ );
+
+/**
+ Convert the standard Lib double linked list to a virtual mapping.
+
+ This service uses EfiConvertPointer() to walk a double linked list and convert all the link
+ pointers to their virtual mappings. This function is only guaranteed to work during the
+ EVT_SIGNAL_VIRTUAL_ADDRESS_CHANGE event and calling it at other times has undefined results.
+
+ @param DebugDisposition Supplies type information for the pointer being converted.
+ @param ListHead Head of linked list to convert.
+
+ @retval EFI_SUCCESS Successfully executed the function.
+ @retval !EFI_SUCCESS Failed to execute the function.
+
+**/
+EFI_STATUS
+EFIAPI
+EfiConvertList (
+ IN UINTN DebugDisposition,
+ IN OUT LIST_ENTRY *ListHead
+ );
+
+/**
+ This service is a wrapper for the UEFI Runtime Service UpdateCapsule().
+
+ Passes capsules to the firmware with both virtual and physical mapping. Depending on the intended
+ consumption, the firmware may process the capsule immediately. If the payload should persist across a
+ system reset, the reset value returned from EFI_QueryCapsuleCapabilities must be passed into ResetSystem()
+ and will cause the capsule to be processed by the firmware as part of the reset process.
+
+ @param CapsuleHeaderArray Virtual pointer to an array of virtual pointers to the capsules
+ being passed into update capsule. Each capsules is assumed to
+ stored in contiguous virtual memory. The capsules in the
+ CapsuleHeaderArray must be the same capsules as the
+ ScatterGatherList. The CapsuleHeaderArray must
+ have the capsules in the same order as the ScatterGatherList.
+ @param CapsuleCount Number of pointers to EFI_CAPSULE_HEADER in
+ CaspuleHeaderArray.
+ @param ScatterGatherList Physical pointer to a set of
+ EFI_CAPSULE_BLOCK_DESCRIPTOR that describes the
+ location in physical memory of a set of capsules. See Related
+ Definitions for an explanation of how more than one capsule is
+ passed via this interface. The capsules in the
+ ScatterGatherList must be in the same order as the
+ CapsuleHeaderArray. This parameter is only referenced if
+ the capsules are defined to persist across system reset.
+
+ @retval EFI_SUCCESS A valid capsule was passed. If CAPSULE_FLAGS_PERSIT_ACROSS_RESET is not set,
+ the capsule has been successfully processed by the firmware.
+ @retval EFI_INVALID_PARAMETER CapsuleSize is NULL, or an incompatible set of flags were
+ set in the capsule header.
+ @retval EFI_INVALID_PARAMETER CapsuleCount is 0
+ @retval EFI_DEVICE_ERROR The capsule update was started, but failed due to a device error.
+ @retval EFI_UNSUPPORTED The capsule type is not supported on this platform.
+ @retval EFI_OUT_OF_RESOURCES There were insufficient resources to process the capsule.
+
+**/
+EFI_STATUS
+EFIAPI
+EfiUpdateCapsule (
+ IN EFI_CAPSULE_HEADER **CapsuleHeaderArray,
+ IN UINTN CapsuleCount,
+ IN EFI_PHYSICAL_ADDRESS ScatterGatherList OPTIONAL
+ );
+
+/**
+ This service is a wrapper for the UEFI Runtime Service QueryCapsuleCapabilities().
+
+ The QueryCapsuleCapabilities() function allows a caller to test to see if a capsule or
+ capsules can be updated via UpdateCapsule(). The Flags values in the capsule header and
+ size of the entire capsule is checked.
+ If the caller needs to query for generic capsule capability a fake EFI_CAPSULE_HEADER can be
+ constructed where CapsuleImageSize is equal to HeaderSize that is equal to sizeof
+ (EFI_CAPSULE_HEADER). To determine reset requirements,
+ CAPSULE_FLAGS_PERSIST_ACROSS_RESET should be set in the Flags field of the
+ EFI_CAPSULE_HEADER.
+ The firmware must support any capsule that has the
+ CAPSULE_FLAGS_PERSIST_ACROSS_RESET flag set in EFI_CAPSULE_HEADER. The
+ firmware sets the policy for what capsules are supported that do not have the
+ CAPSULE_FLAGS_PERSIST_ACROSS_RESET flag set.
+
+ @param CapsuleHeaderArray Virtual pointer to an array of virtual pointers to the capsules
+ being passed into update capsule. The capsules are assumed to
+ stored in contiguous virtual memory.
+ @param CapsuleCount Number of pointers to EFI_CAPSULE_HEADER in
+ CaspuleHeaderArray.
+ @param MaximumCapsuleSize On output the maximum size that UpdateCapsule() can
+ support as an argument to UpdateCapsule() via
+ CapsuleHeaderArray and ScatterGatherList.
+ Undefined on input.
+ @param ResetType Returns the type of reset required for the capsule update.
+
+ @retval EFI_SUCCESS A valid answer was returned.
+ @retval EFI_INVALID_PARAMETER MaximumCapsuleSize is NULL.
+ @retval EFI_UNSUPPORTED The capsule type is not supported on this platform, and
+ MaximumCapsuleSize and ResetType are undefined.
+ @retval EFI_OUT_OF_RESOURCES There were insufficient resources to process the query request.
+
+**/
+EFI_STATUS
+EFIAPI
+EfiQueryCapsuleCapabilities (
+ IN EFI_CAPSULE_HEADER **CapsuleHeaderArray,
+ IN UINTN CapsuleCount,
+ OUT UINT64 *MaximumCapsuleSize,
+ OUT EFI_RESET_TYPE *ResetType
+ );
+
+/**
+ This service is a wrapper for the UEFI Runtime Service QueryVariableInfo().
+
+ The QueryVariableInfo() function allows a caller to obtain the information about the
+ maximum size of the storage space available for the EFI variables, the remaining size of the storage
+ space available for the EFI variables and the maximum size of each individual EFI variable,
+ associated with the attributes specified.
+ The returned MaximumVariableStorageSize, RemainingVariableStorageSize,
+ MaximumVariableSize information may change immediately after the call based on other
+ runtime activities including asynchronous error events. Also, these values associated with different
+ attributes are not additive in nature.
+
+ @param Attributes Attributes bitmask to specify the type of variables on
+ which to return information. Refer to the
+ GetVariable() function description.
+ @param MaximumVariableStorageSize
+ On output the maximum size of the storage space
+ available for the EFI variables associated with the
+ attributes specified.
+ @param RemainingVariableStorageSize
+ Returns the remaining size of the storage space
+ available for the EFI variables associated with the
+ attributes specified.
+ @param MaximumVariableSize Returns the maximum size of the individual EFI
+ variables associated with the attributes specified.
+
+ @retval EFI_SUCCESS A valid answer was returned.
+ @retval EFI_INVALID_PARAMETER An invalid combination of attribute bits was supplied.
+ @retval EFI_UNSUPPORTED EFI_UNSUPPORTED The attribute is not supported on this platform, and the
+ MaximumVariableStorageSize,
+ RemainingVariableStorageSize, MaximumVariableSize
+ are undefined.
+
+**/
+EFI_STATUS
+EFIAPI
+EfiQueryVariableInfo (
+ IN UINT32 Attributes,
+ OUT UINT64 *MaximumVariableStorageSize,
+ OUT UINT64 *RemainingVariableStorageSize,
+ OUT UINT64 *MaximumVariableSize
+ );
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/UefiRuntimeServicesTableLib.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/UefiRuntimeServicesTableLib.h
new file mode 100644
index 0000000000..daacc2a9e7
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/UefiRuntimeServicesTableLib.h
@@ -0,0 +1,26 @@
+/** @file
+ Provides a service to retrieve a pointer to the EFI Runtime Services Table.
+
+ This library does not contain any functions or macros. It simply exports the
+ global variable gRT that is a pointer to the EFI Runtime Services Table as defined
+ in the UEFI Specification. The global variable gRT must be preinitialized to NULL.
+ The library constructor must set gRT to point at the EFI Runtime Services Table so
+ it is available at the module's entry point. Since there is overhead in initializing
+ this global variable, only those modules that actually require access to the EFI
+ Runtime Services Table should use this library.
+ Only available to DXE and UEFI module types.
+
+Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __UEFI_RUNTIME_SERVICES_TABLE_LIB_H__
+#define __UEFI_RUNTIME_SERVICES_TABLE_LIB_H__
+
+///
+/// Cached copy of the EFI Runtime Services Table
+///
+extern EFI_RUNTIME_SERVICES *gRT;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/UefiScsiLib.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/UefiScsiLib.h
new file mode 100644
index 0000000000..3b4cf58c04
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/UefiScsiLib.h
@@ -0,0 +1,1287 @@
+/** @file
+ Provides the functions to submit Scsi commands defined in SCSI-2 specification for SCSI devices.
+
+ This library class provides the functions to submit SCSI commands defined in SCSI-2 specification
+ for hard drive, CD and DVD devices that are the most common SCSI boot targets used by UEFI platforms.
+ This library class depends on SCSI I/O Protocol defined in UEFI Specification and SCSI-2 industry standard.
+
+Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __SCSI_LIB_H__
+#define __SCSI_LIB_H__
+
+#include
+
+/**
+ Execute Test Unit Ready SCSI command on a specific SCSI target.
+
+ Executes the Test Unit Ready command on the SCSI target specified by ScsiIo.
+ If Timeout is zero, then this function waits indefinitely for the command to complete.
+ If Timeout is greater than zero, then the command is executed and will timeout after Timeout 100 ns units.
+ If ScsiIo is NULL, then ASSERT().
+ If SenseDataLength is NULL, then ASSERT().
+ If HostAdapterStatus is NULL, then ASSERT().
+ If TargetStatus is NULL, then ASSERT().
+
+ If SenseDataLength is non-zero and SenseData is not NULL, SenseData must meet buffer
+ alignment requirement defined in EFI_SCSI_IO_PROTOCOL. Otherwise EFI_INVALID_PARAMETER
+ gets returned.
+
+ @param[in] ScsiIo A pointer to the SCSI I/O Protocol instance
+ for the specific SCSI target.
+ @param[in] Timeout The timeout in 100 ns units to use for the execution
+ of this SCSI Request Packet. A Timeout value of
+ zero means that this function will wait indefinitely
+ for the SCSI Request Packet to execute. If Timeout
+ is greater than zero, then this function will return
+ EFI_TIMEOUT if the time required to execute the SCSI
+ Request Packet is greater than Timeout.
+ @param[in, out] SenseData A pointer to sense data that was generated by
+ the execution of the SCSI Request Packet. This
+ buffer must be allocated by the caller.
+ If SenseDataLength is 0, then this parameter is
+ optional and may be NULL.
+ @param[in, out] SenseDataLength On input, a pointer to the length in bytes of
+ the SenseData buffer. On output, a pointer to
+ the number of bytes written to the SenseData buffer.
+ @param[out] HostAdapterStatus The status of the SCSI Host Controller that produces
+ the SCSI bus containing the SCSI target specified by
+ ScsiIo when the SCSI Request Packet was executed.
+ See the EFI SCSI I/O Protocol in the UEFI Specification
+ for details on the possible return values.
+ @param[out] TargetStatus The status returned by the SCSI target specified
+ by ScsiIo when the SCSI Request Packet was executed
+ on the SCSI Host Controller. See the EFI SCSI I/O
+ Protocol in the UEFI Specification for details on
+ the possible return values.
+
+ @retval EFI_SUCCESS The command was executed successfully.
+ See HostAdapterStatus, TargetStatus, SenseDataLength,
+ and SenseData in that order for additional status
+ information.
+ @retval EFI_NOT_READY The SCSI Request Packet could not be sent because
+ there are too many SCSI Command Packets already
+ queued. The SCSI Request Packet was not sent, so
+ no additional status information is available.
+ The caller may retry again later.
+ @retval EFI_DEVICE_ERROR A device error occurred while attempting to send
+ SCSI Request Packet. See HostAdapterStatus,
+ TargetStatus, SenseDataLength, and SenseData in that
+ order for additional status information.
+ @retval EFI_UNSUPPORTED The command described by the SCSI Request Packet
+ is not supported by the SCSI initiator(i.e., SCSI
+ Host Controller). The SCSI Request Packet was not
+ sent, so no additional status information is available.
+ @retval EFI_TIMEOUT A timeout occurred while waiting for the SCSI Request
+ Packet to execute. See HostAdapterStatus, TargetStatus,
+ SenseDataLength, and SenseData in that order for
+ additional status information.
+ @retval EFI_INVALID_PARAMETER The contents of the SCSI Request Packet are invalid.
+
+**/
+EFI_STATUS
+EFIAPI
+ScsiTestUnitReadyCommand (
+ IN EFI_SCSI_IO_PROTOCOL *ScsiIo,
+ IN UINT64 Timeout,
+ IN OUT VOID *SenseData OPTIONAL,
+ IN OUT UINT8 *SenseDataLength,
+ OUT UINT8 *HostAdapterStatus,
+ OUT UINT8 *TargetStatus
+ );
+
+/**
+ Execute Inquiry SCSI command on a specific SCSI target.
+
+ Executes the Inquiry command on the SCSI target specified by ScsiIo.
+ If Timeout is zero, then this function waits indefinitely for the command to complete.
+ If Timeout is greater than zero, then the command is executed and will timeout after Timeout 100 ns units.
+ If ScsiIo is NULL, then ASSERT().
+ If SenseDataLength is NULL, then ASSERT().
+ If HostAdapterStatus is NULL, then ASSERT().
+ If TargetStatus is NULL, then ASSERT().
+ If InquiryDataLength is NULL, then ASSERT().
+
+ If SenseDataLength is non-zero and SenseData is not NULL, SenseData must meet buffer
+ alignment requirement defined in EFI_SCSI_IO_PROTOCOL. Otherwise EFI_INVALID_PARAMETER
+ gets returned.
+
+ If InquiryDataLength is non-zero and InquiryDataBuffer is not NULL, InquiryDataBuffer
+ must meet buffer alignment requirement defined in EFI_SCSI_IO_PROTOCOL. Otherwise
+ EFI_INVALID_PARAMETER gets returned.
+
+ @param[in] ScsiIo A pointer to the SCSI I/O Protocol instance
+ for the specific SCSI target.
+ @param[in] Timeout The timeout in 100 ns units to use for the
+ execution of this SCSI Request Packet. A Timeout
+ value of zero means that this function will wait
+ indefinitely for the SCSI Request Packet to execute.
+ If Timeout is greater than zero, then this function
+ will return EFI_TIMEOUT if the time required to
+ execute the SCSI Request Packet is greater than Timeout.
+ @param[in, out] SenseData A pointer to sense data that was generated
+ by the execution of the SCSI Request Packet.
+ This buffer must be allocated by the caller.
+ If SenseDataLength is 0, then this parameter
+ is optional and may be NULL.
+ @param[in, out] SenseDataLength On input, the length in bytes of the SenseData buffer.
+ On output, the number of bytes written to the SenseData buffer.
+ @param[out] HostAdapterStatus The status of the SCSI Host Controller that
+ produces the SCSI bus containing the SCSI
+ target specified by ScsiIo when the SCSI
+ Request Packet was executed. See the EFI
+ SCSI I/O Protocol in the UEFI Specification
+ for details on the possible return values.
+ @param[out] TargetStatus The status returned by the SCSI target specified
+ by ScsiIo when the SCSI Request Packet was
+ executed on the SCSI Host Controller.
+ See the EFI SCSI I/O Protocol in the UEFI
+ Specification for details on the possible
+ return values.
+ @param[in, out] InquiryDataBuffer A pointer to inquiry data that was generated
+ by the execution of the SCSI Request Packet.
+ This buffer must be allocated by the caller.
+ If InquiryDataLength is 0, then this parameter
+ is optional and may be NULL.
+ @param[in, out] InquiryDataLength On input, a pointer to the length in bytes
+ of the InquiryDataBuffer buffer.
+ On output, a pointer to the number of bytes
+ written to the InquiryDataBuffer buffer.
+ @param[in] EnableVitalProductData If TRUE, then the supported vital product
+ data is returned in InquiryDataBuffer.
+ If FALSE, then the standard inquiry data is
+ returned in InquiryDataBuffer.
+
+ @retval EFI_SUCCESS The command was executed successfully. See HostAdapterStatus,
+ TargetStatus, SenseDataLength, and SenseData in that order
+ for additional status information.
+ @retval EFI_BAD_BUFFER_SIZE The SCSI Request Packet was executed, but the entire
+ InquiryDataBuffer could not be transferred. The actual
+ number of bytes transferred is returned in InquiryDataLength.
+ @retval EFI_NOT_READY The SCSI Request Packet could not be sent because there
+ are too many SCSI Command Packets already queued.
+ The SCSI Request Packet was not sent, so no additional
+ status information is available. The caller may retry again later.
+ @retval EFI_DEVICE_ERROR A device error occurred while attempting to send SCSI
+ Request Packet. See HostAdapterStatus, TargetStatus,
+ SenseDataLength, and SenseData in that order for additional
+ status information.
+ @retval EFI_UNSUPPORTED The command described by the SCSI Request Packet is not
+ supported by the SCSI initiator(i.e., SCSI Host Controller).
+ The SCSI Request Packet was not sent, so no additional
+ status information is available.
+ @retval EFI_TIMEOUT A timeout occurred while waiting for the SCSI Request
+ Packet to execute. See HostAdapterStatus, TargetStatus,
+ SenseDataLength, and SenseData in that order for
+ additional status information.
+ @retval EFI_INVALID_PARAMETER The contents of the SCSI Request Packet are invalid.
+
+**/
+EFI_STATUS
+EFIAPI
+ScsiInquiryCommand (
+ IN EFI_SCSI_IO_PROTOCOL *ScsiIo,
+ IN UINT64 Timeout,
+ IN OUT VOID *SenseData OPTIONAL,
+ IN OUT UINT8 *SenseDataLength,
+ OUT UINT8 *HostAdapterStatus,
+ OUT UINT8 *TargetStatus,
+ IN OUT VOID *InquiryDataBuffer OPTIONAL,
+ IN OUT UINT32 *InquiryDataLength,
+ IN BOOLEAN EnableVitalProductData
+ );
+
+/**
+ Execute Inquiry SCSI command on a specific SCSI target.
+
+ Executes the Inquiry command on the SCSI target specified by ScsiIo.
+ If Timeout is zero, then this function waits indefinitely for the command to complete.
+ If Timeout is greater than zero, then the command is executed and will timeout after Timeout 100 ns units.
+ If ScsiIo is NULL, then ASSERT().
+ If SenseDataLength is NULL, then ASSERT().
+ If HostAdapterStatus is NULL, then ASSERT().
+ If TargetStatus is NULL, then ASSERT().
+ If InquiryDataLength is NULL, then ASSERT().
+
+ If SenseDataLength is non-zero and SenseData is not NULL, SenseData must meet buffer
+ alignment requirement defined in EFI_SCSI_IO_PROTOCOL. Otherwise EFI_INVALID_PARAMETER
+ gets returned.
+
+ If InquiryDataLength is non-zero and InquiryDataBuffer is not NULL, InquiryDataBuffer
+ must meet buffer alignment requirement defined in EFI_SCSI_IO_PROTOCOL. Otherwise
+ EFI_INVALID_PARAMETER gets returned.
+
+ @param[in] ScsiIo A pointer to the SCSI I/O Protocol instance
+ for the specific SCSI target.
+ @param[in] Timeout The timeout in 100 ns units to use for the
+ execution of this SCSI Request Packet. A Timeout
+ value of zero means that this function will wait
+ indefinitely for the SCSI Request Packet to execute.
+ If Timeout is greater than zero, then this function
+ will return EFI_TIMEOUT if the time required to
+ execute the SCSI Request Packet is greater than Timeout.
+ @param[in, out] SenseData A pointer to sense data that was generated
+ by the execution of the SCSI Request Packet.
+ This buffer must be allocated by the caller.
+ If SenseDataLength is 0, then this parameter
+ is optional and may be NULL.
+ @param[in, out] SenseDataLength On input, the length in bytes of the SenseData buffer.
+ On output, the number of bytes written to the SenseData buffer.
+ @param[out] HostAdapterStatus The status of the SCSI Host Controller that
+ produces the SCSI bus containing the SCSI
+ target specified by ScsiIo when the SCSI
+ Request Packet was executed. See the EFI
+ SCSI I/O Protocol in the UEFI Specification
+ for details on the possible return values.
+ @param[out] TargetStatus The status returned by the SCSI target specified
+ by ScsiIo when the SCSI Request Packet was
+ executed on the SCSI Host Controller.
+ See the EFI SCSI I/O Protocol in the UEFI
+ Specification for details on the possible
+ return values.
+ @param[in, out] InquiryDataBuffer A pointer to inquiry data that was generated
+ by the execution of the SCSI Request Packet.
+ This buffer must be allocated by the caller.
+ If InquiryDataLength is 0, then this parameter
+ is optional and may be NULL.
+ @param[in, out] InquiryDataLength On input, a pointer to the length in bytes
+ of the InquiryDataBuffer buffer.
+ On output, a pointer to the number of bytes
+ written to the InquiryDataBuffer buffer.
+ @param[in] EnableVitalProductData If TRUE, then the supported vital product
+ data for the PageCode is returned in InquiryDataBuffer.
+ If FALSE, then the standard inquiry data is
+ returned in InquiryDataBuffer and PageCode is ignored.
+ @param[in] PageCode The page code of the vital product data.
+ It's ignored if EnableVitalProductData is FALSE.
+
+ @retval EFI_SUCCESS The command executed successfully. See HostAdapterStatus,
+ TargetStatus, SenseDataLength, and SenseData in that order
+ for additional status information.
+ @retval EFI_BAD_BUFFER_SIZE The SCSI Request Packet was executed, but the entire
+ InquiryDataBuffer could not be transferred. The actual
+ number of bytes transferred is returned in InquiryDataLength.
+ @retval EFI_NOT_READY The SCSI Request Packet could not be sent because there
+ are too many SCSI Command Packets already queued.
+ The SCSI Request Packet was not sent, so no additional
+ status information is available. The caller may retry again later.
+ @retval EFI_DEVICE_ERROR A device error occurred while attempting to send SCSI
+ Request Packet. See HostAdapterStatus, TargetStatus,
+ SenseDataLength, and SenseData in that order for additional
+ status information.
+ @retval EFI_UNSUPPORTED The command described by the SCSI Request Packet is not
+ supported by the SCSI initiator(i.e., SCSI Host Controller).
+ The SCSI Request Packet was not sent, so no additional
+ status information is available.
+ @retval EFI_TIMEOUT A timeout occurred while waiting for the SCSI Request
+ Packet to execute. See HostAdapterStatus, TargetStatus,
+ SenseDataLength, and SenseData in that order for
+ additional status information.
+ @retval EFI_INVALID_PARAMETER The contents of the SCSI Request Packet are invalid.
+
+**/
+EFI_STATUS
+EFIAPI
+ScsiInquiryCommandEx (
+ IN EFI_SCSI_IO_PROTOCOL *ScsiIo,
+ IN UINT64 Timeout,
+ IN OUT VOID *SenseData OPTIONAL,
+ IN OUT UINT8 *SenseDataLength,
+ OUT UINT8 *HostAdapterStatus,
+ OUT UINT8 *TargetStatus,
+ IN OUT VOID *InquiryDataBuffer OPTIONAL,
+ IN OUT UINT32 *InquiryDataLength,
+ IN BOOLEAN EnableVitalProductData,
+ IN UINT8 PageCode
+ );
+
+/**
+ Execute Mode Sense(10) SCSI command on a specific SCSI target.
+
+ Executes the SCSI Mode Sense(10) command on the SCSI target specified by ScsiIo.
+ If Timeout is zero, then this function waits indefinitely for the command to complete.
+ If Timeout is greater than zero, then the command is executed and will timeout
+ after Timeout 100 ns units. The DBDField, PageControl, and PageCode parameters
+ are used to construct the CDB for this SCSI command.
+ If ScsiIo is NULL, then ASSERT().
+ If SenseDataLength is NULL, then ASSERT().
+ If HostAdapterStatus is NULL, then ASSERT().
+ If TargetStatus is NULL, then ASSERT().
+ If DataLength is NULL, then ASSERT().
+
+ If SenseDataLength is non-zero and SenseData is not NULL, SenseData must meet buffer
+ alignment requirement defined in EFI_SCSI_IO_PROTOCOL. Otherwise EFI_INVALID_PARAMETER
+ gets returned.
+
+ If DataLength is non-zero and DataBuffer is not NULL, DataBuffer must meet buffer
+ alignment requirement defined in EFI_SCSI_IO_PROTOCOL. Otherwise EFI_INVALID_PARAMETER
+ gets returned.
+
+ @param[in] ScsiIo A pointer to the SCSI I/O Protocol instance
+ for the specific SCSI target.
+ @param[in] Timeout The timeout in 100 ns units to use for the
+ execution of this SCSI Request Packet. A Timeout
+ value of zero means that this function will wait
+ indefinitely for the SCSI Request Packet to execute.
+ If Timeout is greater than zero, then this function
+ will return EFI_TIMEOUT if the time required to
+ execute the SCSI Request Packet is greater than Timeout.
+ @param[in, out] SenseData A pointer to sense data that was generated
+ by the execution of the SCSI Request Packet.
+ This buffer must be allocated by the caller.
+ If SenseDataLength is 0, then this parameter
+ is optional and may be NULL.
+ @param[in, out] SenseDataLength On input, the length in bytes of the SenseData buffer.
+ On output, the number of bytes written to the SenseData buffer.
+ @param[out] HostAdapterStatus The status of the SCSI Host Controller that
+ produces the SCSI bus containing the SCSI target
+ specified by ScsiIo when the SCSI Request Packet
+ was executed. See the EFI SCSI I/O Protocol in the
+ UEFI Specification for details on the possible
+ return values.
+ @param[out] TargetStatus The status returned by the SCSI target specified
+ by ScsiIo when the SCSI Request Packet was executed
+ on the SCSI Host Controller. See the EFI SCSI
+ I/O Protocol in the UEFI Specification for details
+ on the possible return values.
+ @param[in, out] DataBuffer A pointer to data that was generated by the
+ execution of the SCSI Request Packet. This
+ buffer must be allocated by the caller. If
+ DataLength is 0, then this parameter is optional
+ and may be NULL.
+ @param[in, out] DataLength On input, a pointer to the length in bytes of
+ the DataBuffer buffer. On output, a pointer
+ to the number of bytes written to the DataBuffer
+ buffer.
+ @param[in] DBDField Specifies the DBD field of the CDB for this SCSI Command.
+ @param[in] PageControl Specifies the PC field of the CDB for this SCSI Command.
+ @param[in] PageCode Specifies the Page Control field of the CDB for this SCSI Command.
+
+ @retval EFI_SUCCESS The command was executed successfully.
+ See HostAdapterStatus, TargetStatus, SenseDataLength,
+ and SenseData in that order for additional status information.
+ @retval EFI_BAD_BUFFER_SIZE The SCSI Request Packet was executed, but the
+ entire DataBuffer could not be transferred.
+ The actual number of bytes transferred is returned
+ in DataLength.
+ @retval EFI_NOT_READY The SCSI Request Packet could not be sent because
+ there are too many SCSI Command Packets already queued.
+ The SCSI Request Packet was not sent, so no additional
+ status information is available. The caller may retry
+ again later.
+ @retval EFI_DEVICE_ERROR A device error occurred while attempting to send
+ SCSI Request Packet. See HostAdapterStatus, TargetStatus,
+ SenseDataLength, and SenseData in that order for
+ additional status information.
+ @retval EFI_UNSUPPORTED The command described by the SCSI Request Packet
+ is not supported by the SCSI initiator(i.e., SCSI
+ Host Controller). The SCSI Request Packet was not
+ sent, so no additional status information is available.
+ @retval EFI_TIMEOUT A timeout occurred while waiting for the SCSI
+ Request Packet to execute. See HostAdapterStatus,
+ TargetStatus, SenseDataLength, and SenseData in that
+ order for additional status information.
+ @retval EFI_INVALID_PARAMETER The contents of the SCSI Request Packet are invalid.
+
+**/
+EFI_STATUS
+EFIAPI
+ScsiModeSense10Command (
+ IN EFI_SCSI_IO_PROTOCOL *ScsiIo,
+ IN UINT64 Timeout,
+ IN OUT VOID *SenseData OPTIONAL,
+ IN OUT UINT8 *SenseDataLength,
+ OUT UINT8 *HostAdapterStatus,
+ OUT UINT8 *TargetStatus,
+ IN OUT VOID *DataBuffer OPTIONAL,
+ IN OUT UINT32 *DataLength,
+ IN UINT8 DBDField OPTIONAL,
+ IN UINT8 PageControl,
+ IN UINT8 PageCode
+ );
+
+/**
+ Execute Request Sense SCSI command on a specific SCSI target.
+
+ Executes the Request Sense command on the SCSI target specified by ScsiIo.
+ If Timeout is zero, then this function waits indefinitely for the command to complete.
+ If Timeout is greater than zero, then the command is executed and will timeout after Timeout 100 ns units.
+ If ScsiIo is NULL, then ASSERT().
+ If SenseDataLength is NULL, then ASSERT().
+ If HostAdapterStatus is NULL, then ASSERT().
+ If TargetStatus is NULL, then ASSERT().
+
+ If SenseDataLength is non-zero and SenseData is not NULL, SenseData must meet buffer
+ alignment requirement defined in EFI_SCSI_IO_PROTOCOL. Otherwise EFI_INVALID_PARAMETER
+ gets returned.
+
+ @param[in] ScsiIo A pointer to SCSI IO protocol.
+ @param[in] Timeout The length of timeout period.
+ @param[in, out] SenseData A pointer to output sense data.
+ @param[in, out] SenseDataLength The length of output sense data.
+ @param[out] HostAdapterStatus The status of Host Adapter.
+ @param[out] TargetStatus The status of the target.
+
+ @retval EFI_SUCCESS Command is executed successfully.
+ @retval EFI_NOT_READY The SCSI Request Packet could not be sent because there are
+ too many SCSI Command Packets already queued.
+ @retval EFI_DEVICE_ERROR A device error occurred while attempting to send SCSI Request Packet.
+ @retval EFI_UNSUPPORTED The command described by the SCSI Request Packet is not supported by
+ the SCSI initiator(i.e., SCSI Host Controller)
+ @retval EFI_TIMEOUT A timeout occurred while waiting for the SCSI Request Packet to execute.
+ @retval EFI_INVALID_PARAMETER The contents of the SCSI Request Packet are invalid.
+
+**/
+EFI_STATUS
+EFIAPI
+ScsiRequestSenseCommand (
+ IN EFI_SCSI_IO_PROTOCOL *ScsiIo,
+ IN UINT64 Timeout,
+ IN OUT VOID *SenseData OPTIONAL,
+ IN OUT UINT8 *SenseDataLength,
+ OUT UINT8 *HostAdapterStatus,
+ OUT UINT8 *TargetStatus
+ );
+
+/**
+ Execute Read Capacity SCSI command on a specific SCSI target.
+
+ Executes the SCSI Read Capacity command on the SCSI target specified by ScsiIo.
+ If Timeout is zero, then this function waits indefinitely for the command to complete.
+ If Timeout is greater than zero, then the command is executed and will timeout after
+ Timeout 100 ns units. The Pmi parameter is used to construct the CDB for this SCSI command.
+ If ScsiIo is NULL, then ASSERT().
+ If SenseDataLength is NULL, then ASSERT().
+ If HostAdapterStatus is NULL, then ASSERT().
+ If TargetStatus is NULL, then ASSERT().
+ If DataLength is NULL, then ASSERT().
+
+ If SenseDataLength is non-zero and SenseData is not NULL, SenseData must meet buffer
+ alignment requirement defined in EFI_SCSI_IO_PROTOCOL. Otherwise EFI_INVALID_PARAMETER
+ gets returned.
+
+ If DataLength is non-zero and DataBuffer is not NULL, DataBuffer must meet buffer
+ alignment requirement defined in EFI_SCSI_IO_PROTOCOL. Otherwise EFI_INVALID_PARAMETER
+ gets returned.
+
+ @param[in] ScsiIo A pointer to SCSI IO protocol.
+ @param[in] Timeout The length of timeout period.
+ @param[in, out] SenseData A pointer to output sense data.
+ @param[in, out] SenseDataLength The length of output sense data.
+ @param[out] HostAdapterStatus The status of Host Adapter.
+ @param[out] TargetStatus The status of the target.
+ @param[in, out] DataBuffer A pointer to a data buffer.
+ @param[in, out] DataLength The length of data buffer.
+ @param[in] Pmi Partial medium indicator.
+
+ @retval EFI_SUCCESS Command is executed successfully.
+ @retval EFI_BAD_BUFFER_SIZE The SCSI Request Packet was executed, but the entire
+ DataBuffer could not be transferred. The actual
+ number of bytes transferred is returned in DataLength.
+ @retval EFI_NOT_READY The SCSI Request Packet could not be sent because
+ there are too many SCSI Command Packets already queued.
+ @retval EFI_DEVICE_ERROR A device error occurred while attempting to send SCSI Request Packet.
+ @retval EFI_UNSUPPORTED The command described by the SCSI Request Packet
+ is not supported by the SCSI initiator(i.e., SCSI Host Controller)
+ @retval EFI_TIMEOUT A timeout occurred while waiting for the SCSI Request Packet to execute.
+ @retval EFI_INVALID_PARAMETER The contents of the SCSI Request Packet are invalid.
+
+**/
+EFI_STATUS
+EFIAPI
+ScsiReadCapacityCommand (
+ IN EFI_SCSI_IO_PROTOCOL *ScsiIo,
+ IN UINT64 Timeout,
+ IN OUT VOID *SenseData OPTIONAL,
+ IN OUT UINT8 *SenseDataLength,
+ OUT UINT8 *HostAdapterStatus,
+ OUT UINT8 *TargetStatus,
+ IN OUT VOID *DataBuffer OPTIONAL,
+ IN OUT UINT32 *DataLength,
+ IN BOOLEAN Pmi
+ );
+
+/**
+ Execute Read Capacity SCSI 16 command on a specific SCSI target.
+
+ Executes the SCSI Read Capacity 16 command on the SCSI target specified by ScsiIo.
+ If Timeout is zero, then this function waits indefinitely for the command to complete.
+ If Timeout is greater than zero, then the command is executed and will timeout after
+ Timeout 100 ns units. The Pmi parameter is used to construct the CDB for this SCSI command.
+ If ScsiIo is NULL, then ASSERT().
+ If SenseDataLength is NULL, then ASSERT().
+ If HostAdapterStatus is NULL, then ASSERT().
+ If TargetStatus is NULL, then ASSERT().
+ If DataLength is NULL, then ASSERT().
+
+ If SenseDataLength is non-zero and SenseData is not NULL, SenseData must meet buffer
+ alignment requirement defined in EFI_SCSI_IO_PROTOCOL. Otherwise EFI_INVALID_PARAMETER
+ gets returned.
+
+ If DataLength is non-zero and DataBuffer is not NULL, DataBuffer must meet buffer
+ alignment requirement defined in EFI_SCSI_IO_PROTOCOL. Otherwise EFI_INVALID_PARAMETER
+ gets returned.
+
+ @param[in] ScsiIo A pointer to SCSI IO protocol.
+ @param[in] Timeout The length of timeout period.
+ @param[in, out] SenseData A pointer to output sense data.
+ @param[in, out] SenseDataLength The length of output sense data.
+ @param[out] HostAdapterStatus The status of Host Adapter.
+ @param[out] TargetStatus The status of the target.
+ @param[in, out] DataBuffer A pointer to a data buffer.
+ @param[in, out] DataLength The length of data buffer.
+ @param[in] Pmi Partial medium indicator.
+
+ @retval EFI_SUCCESS Command is executed successfully.
+ @retval EFI_BAD_BUFFER_SIZE The SCSI Request Packet was executed, but the entire
+ DataBuffer could not be transferred. The actual
+ number of bytes transferred is returned in DataLength.
+ @retval EFI_NOT_READY The SCSI Request Packet could not be sent because
+ there are too many SCSI Command Packets already queued.
+ @retval EFI_DEVICE_ERROR A device error occurred while attempting to send SCSI Request Packet.
+ @retval EFI_UNSUPPORTED The command described by the SCSI Request Packet
+ is not supported by the SCSI initiator(i.e., SCSI Host Controller)
+ @retval EFI_TIMEOUT A timeout occurred while waiting for the SCSI Request Packet to execute.
+ @retval EFI_INVALID_PARAMETER The contents of the SCSI Request Packet are invalid.
+
+**/
+EFI_STATUS
+EFIAPI
+ScsiReadCapacity16Command (
+ IN EFI_SCSI_IO_PROTOCOL *ScsiIo,
+ IN UINT64 Timeout,
+ IN OUT VOID *SenseData OPTIONAL,
+ IN OUT UINT8 *SenseDataLength,
+ OUT UINT8 *HostAdapterStatus,
+ OUT UINT8 *TargetStatus,
+ IN OUT VOID *DataBuffer OPTIONAL,
+ IN OUT UINT32 *DataLength,
+ IN BOOLEAN Pmi
+ );
+
+/**
+ Execute Read(10) SCSI command on a specific SCSI target.
+
+ Executes the SCSI Read(10) command on the SCSI target specified by ScsiIo.
+ If Timeout is zero, then this function waits indefinitely for the command to complete.
+ If Timeout is greater than zero, then the command is executed and will timeout
+ after Timeout 100 ns units. The StartLba and SectorSize parameters are used to
+ construct the CDB for this SCSI command.
+ If ScsiIo is NULL, then ASSERT().
+ If SenseDataLength is NULL, then ASSERT().
+ If HostAdapterStatus is NULL, then ASSERT().
+ If TargetStatus is NULL, then ASSERT().
+ If DataLength is NULL, then ASSERT().
+
+ If SenseDataLength is non-zero and SenseData is not NULL, SenseData must meet buffer
+ alignment requirement defined in EFI_SCSI_IO_PROTOCOL. Otherwise EFI_INVALID_PARAMETER
+ gets returned.
+
+ If DataLength is non-zero and DataBuffer is not NULL, DataBuffer must meet buffer
+ alignment requirement defined in EFI_SCSI_IO_PROTOCOL. Otherwise EFI_INVALID_PARAMETER
+ gets returned.
+
+ @param[in] ScsiIo A pointer to SCSI IO protocol.
+ @param[in] Timeout The length of timeout period.
+ @param[in, out] SenseData A pointer to output sense data.
+ @param[in, out] SenseDataLength The length of output sense data.
+ @param[out] HostAdapterStatus The status of Host Adapter.
+ @param[out] TargetStatus The status of the target.
+ @param[in, out] DataBuffer Read 10 command data.
+ @param[in, out] DataLength The length of data buffer.
+ @param[in] StartLba The start address of LBA.
+ @param[in] SectorSize The number of contiguous logical blocks of data that shall be transferred.
+
+ @retval EFI_SUCCESS Command is executed successfully.
+ @retval EFI_BAD_BUFFER_SIZE The SCSI Request Packet was executed, but the entire DataBuffer could
+ not be transferred. The actual number of bytes transferred is returned in DataLength.
+ @retval EFI_NOT_READY The SCSI Request Packet could not be sent because there are too many
+ SCSI Command Packets already queued.
+ @retval EFI_DEVICE_ERROR A device error occurred while attempting to send SCSI Request Packet.
+ @retval EFI_UNSUPPORTED The command described by the SCSI Request Packet is not supported by
+ the SCSI initiator(i.e., SCSI Host Controller)
+ @retval EFI_TIMEOUT A timeout occurred while waiting for the SCSI Request Packet to execute.
+ @retval EFI_INVALID_PARAMETER The contents of the SCSI Request Packet are invalid.
+
+**/
+EFI_STATUS
+EFIAPI
+ScsiRead10Command (
+ IN EFI_SCSI_IO_PROTOCOL *ScsiIo,
+ IN UINT64 Timeout,
+ IN OUT VOID *SenseData OPTIONAL,
+ IN OUT UINT8 *SenseDataLength,
+ OUT UINT8 *HostAdapterStatus,
+ OUT UINT8 *TargetStatus,
+ IN OUT VOID *DataBuffer OPTIONAL,
+ IN OUT UINT32 *DataLength,
+ IN UINT32 StartLba,
+ IN UINT32 SectorSize
+ );
+
+/**
+ Execute Write(10) SCSI command on a specific SCSI target.
+
+ Executes the SCSI Write(10) command on the SCSI target specified by ScsiIo.
+ If Timeout is zero, then this function waits indefinitely for the command to complete.
+ If Timeout is greater than zero, then the command is executed and will timeout after
+ Timeout 100 ns units. The StartLba and SectorSize parameters are used to construct
+ the CDB for this SCSI command.
+ If ScsiIo is NULL, then ASSERT().
+ If SenseDataLength is NULL, then ASSERT().
+ If HostAdapterStatus is NULL, then ASSERT().
+ If TargetStatus is NULL, then ASSERT().
+ If DataLength is NULL, then ASSERT().
+
+ If SenseDataLength is non-zero and SenseData is not NULL, SenseData must meet buffer
+ alignment requirement defined in EFI_SCSI_IO_PROTOCOL. Otherwise EFI_INVALID_PARAMETER
+ gets returned.
+
+ If DataLength is non-zero and DataBuffer is not NULL, DataBuffer must meet buffer
+ alignment requirement defined in EFI_SCSI_IO_PROTOCOL. Otherwise EFI_INVALID_PARAMETER
+ gets returned.
+
+ @param[in] ScsiIo SCSI IO Protocol to use
+ @param[in] Timeout The length of timeout period.
+ @param[in, out] SenseData A pointer to output sense data.
+ @param[in, out] SenseDataLength The length of output sense data.
+ @param[out] HostAdapterStatus The status of Host Adapter.
+ @param[out] TargetStatus The status of the target.
+ @param[in, out] DataBuffer A pointer to a data buffer.
+ @param[in, out] DataLength The length of data buffer.
+ @param[in] StartLba The start address of LBA.
+ @param[in] SectorSize The number of contiguous logical blocks of data that shall be transferred.
+
+ @retval EFI_SUCCESS Command is executed successfully.
+ @retval EFI_BAD_BUFFER_SIZE The SCSI Request Packet was executed, but the entire DataBuffer could
+ not be transferred. The actual number of bytes transferred is returned in DataLength.
+ @retval EFI_NOT_READY The SCSI Request Packet could not be sent because there are too many
+ SCSI Command Packets already queued.
+ @retval EFI_DEVICE_ERROR A device error occurred while attempting to send SCSI Request Packet.
+ @retval EFI_UNSUPPORTED The command described by the SCSI Request Packet is not supported by
+ the SCSI initiator(i.e., SCSI Host Controller)
+ @retval EFI_TIMEOUT A timeout occurred while waiting for the SCSI Request Packet to execute.
+ @retval EFI_INVALID_PARAMETER The contents of the SCSI Request Packet are invalid.
+
+**/
+EFI_STATUS
+EFIAPI
+ScsiWrite10Command (
+ IN EFI_SCSI_IO_PROTOCOL *ScsiIo,
+ IN UINT64 Timeout,
+ IN OUT VOID *SenseData OPTIONAL,
+ IN OUT UINT8 *SenseDataLength,
+ OUT UINT8 *HostAdapterStatus,
+ OUT UINT8 *TargetStatus,
+ IN OUT VOID *DataBuffer OPTIONAL,
+ IN OUT UINT32 *DataLength,
+ IN UINT32 StartLba,
+ IN UINT32 SectorSize
+ );
+
+/**
+ Execute Read(16) SCSI command on a specific SCSI target.
+
+ Executes the SCSI Read(16) command on the SCSI target specified by ScsiIo.
+ If Timeout is zero, then this function waits indefinitely for the command to complete.
+ If Timeout is greater than zero, then the command is executed and will timeout
+ after Timeout 100 ns units. The StartLba and SectorSize parameters are used to
+ construct the CDB for this SCSI command.
+ If ScsiIo is NULL, then ASSERT().
+ If SenseDataLength is NULL, then ASSERT().
+ If HostAdapterStatus is NULL, then ASSERT().
+ If TargetStatus is NULL, then ASSERT().
+ If DataLength is NULL, then ASSERT().
+
+ If SenseDataLength is non-zero and SenseData is not NULL, SenseData must meet buffer
+ alignment requirement defined in EFI_SCSI_IO_PROTOCOL. Otherwise EFI_INVALID_PARAMETER
+ gets returned.
+
+ If DataLength is non-zero and DataBuffer is not NULL, DataBuffer must meet buffer
+ alignment requirement defined in EFI_SCSI_IO_PROTOCOL. Otherwise EFI_INVALID_PARAMETER
+ gets returned.
+
+ @param[in] ScsiIo A pointer to SCSI IO protocol.
+ @param[in] Timeout The length of timeout period.
+ @param[in, out] SenseData A pointer to output sense data.
+ @param[in, out] SenseDataLength The length of output sense data.
+ @param[out] HostAdapterStatus The status of Host Adapter.
+ @param[out] TargetStatus The status of the target.
+ @param[in, out] DataBuffer Read 16 command data.
+ @param[in, out] DataLength The length of data buffer.
+ @param[in] StartLba The start address of LBA.
+ @param[in] SectorSize The number of contiguous logical blocks of data that shall be transferred.
+
+ @retval EFI_SUCCESS Command is executed successfully.
+ @retval EFI_BAD_BUFFER_SIZE The SCSI Request Packet was executed, but the entire DataBuffer could
+ not be transferred. The actual number of bytes transferred is returned in DataLength.
+ @retval EFI_NOT_READY The SCSI Request Packet could not be sent because there are too many
+ SCSI Command Packets already queued.
+ @retval EFI_DEVICE_ERROR A device error occurred while attempting to send SCSI Request Packet.
+ @retval EFI_UNSUPPORTED The command described by the SCSI Request Packet is not supported by
+ the SCSI initiator(i.e., SCSI Host Controller)
+ @retval EFI_TIMEOUT A timeout occurred while waiting for the SCSI Request Packet to execute.
+ @retval EFI_INVALID_PARAMETER The contents of the SCSI Request Packet are invalid.
+
+**/
+EFI_STATUS
+EFIAPI
+ScsiRead16Command (
+ IN EFI_SCSI_IO_PROTOCOL *ScsiIo,
+ IN UINT64 Timeout,
+ IN OUT VOID *SenseData OPTIONAL,
+ IN OUT UINT8 *SenseDataLength,
+ OUT UINT8 *HostAdapterStatus,
+ OUT UINT8 *TargetStatus,
+ IN OUT VOID *DataBuffer OPTIONAL,
+ IN OUT UINT32 *DataLength,
+ IN UINT64 StartLba,
+ IN UINT32 SectorSize
+ );
+
+/**
+ Execute Write(16) SCSI command on a specific SCSI target.
+
+ Executes the SCSI Write(16) command on the SCSI target specified by ScsiIo.
+ If Timeout is zero, then this function waits indefinitely for the command to complete.
+ If Timeout is greater than zero, then the command is executed and will timeout after
+ Timeout 100 ns units. The StartLba and SectorSize parameters are used to construct
+ the CDB for this SCSI command.
+ If ScsiIo is NULL, then ASSERT().
+ If SenseDataLength is NULL, then ASSERT().
+ If HostAdapterStatus is NULL, then ASSERT().
+ If TargetStatus is NULL, then ASSERT().
+ If DataLength is NULL, then ASSERT().
+
+ If SenseDataLength is non-zero and SenseData is not NULL, SenseData must meet buffer
+ alignment requirement defined in EFI_SCSI_IO_PROTOCOL. Otherwise EFI_INVALID_PARAMETER
+ gets returned.
+
+ If DataLength is non-zero and DataBuffer is not NULL, DataBuffer must meet buffer
+ alignment requirement defined in EFI_SCSI_IO_PROTOCOL. Otherwise EFI_INVALID_PARAMETER
+ gets returned.
+
+ @param[in] ScsiIo SCSI IO Protocol to use
+ @param[in] Timeout The length of timeout period.
+ @param[in, out] SenseData A pointer to output sense data.
+ @param[in, out] SenseDataLength The length of output sense data.
+ @param[out] HostAdapterStatus The status of Host Adapter.
+ @param[out] TargetStatus The status of the target.
+ @param[in, out] DataBuffer A pointer to a data buffer.
+ @param[in, out] DataLength The length of data buffer.
+ @param[in] StartLba The start address of LBA.
+ @param[in] SectorSize The number of contiguous logical blocks of data that shall be transferred.
+
+ @retval EFI_SUCCESS Command is executed successfully.
+ @retval EFI_BAD_BUFFER_SIZE The SCSI Request Packet was executed, but the entire DataBuffer could
+ not be transferred. The actual number of bytes transferred is returned in DataLength.
+ @retval EFI_NOT_READY The SCSI Request Packet could not be sent because there are too many
+ SCSI Command Packets already queued.
+ @retval EFI_DEVICE_ERROR A device error occurred while attempting to send SCSI Request Packet.
+ @retval EFI_UNSUPPORTED The command described by the SCSI Request Packet is not supported by
+ the SCSI initiator(i.e., SCSI Host Controller)
+ @retval EFI_TIMEOUT A timeout occurred while waiting for the SCSI Request Packet to execute.
+ @retval EFI_INVALID_PARAMETER The contents of the SCSI Request Packet are invalid.
+
+**/
+EFI_STATUS
+EFIAPI
+ScsiWrite16Command (
+ IN EFI_SCSI_IO_PROTOCOL *ScsiIo,
+ IN UINT64 Timeout,
+ IN OUT VOID *SenseData OPTIONAL,
+ IN OUT UINT8 *SenseDataLength,
+ OUT UINT8 *HostAdapterStatus,
+ OUT UINT8 *TargetStatus,
+ IN OUT VOID *DataBuffer OPTIONAL,
+ IN OUT UINT32 *DataLength,
+ IN UINT64 StartLba,
+ IN UINT32 SectorSize
+ );
+
+/**
+ Execute Security Protocol In SCSI command on a specific SCSI target.
+
+ Executes the SCSI Security Protocol In command on the SCSI target specified by ScsiIo.
+ If Timeout is zero, then this function waits indefinitely for the command to complete.
+ If Timeout is greater than zero, then the command is executed and will timeout after
+ Timeout 100 ns units.
+ If ScsiIo is NULL, then ASSERT().
+ If SenseDataLength is NULL, then ASSERT().
+ If HostAdapterStatus is NULL, then ASSERT().
+ If TargetStatus is NULL, then ASSERT().
+ If TransferLength is NULL, then ASSERT().
+
+ If SenseDataLength is non-zero and SenseData is not NULL, SenseData must meet buffer
+ alignment requirement defined in EFI_SCSI_IO_PROTOCOL. Otherwise EFI_INVALID_PARAMETER
+ gets returned.
+
+ If DataLength is non-zero and DataBuffer is not NULL, DataBuffer must meet buffer
+ alignment requirement defined in EFI_SCSI_IO_PROTOCOL. Otherwise EFI_INVALID_PARAMETER
+ gets returned.
+
+ @param[in] ScsiIo SCSI IO Protocol to use.
+ @param[in] Timeout The length of timeout period.
+ @param[in, out] SenseData A pointer to output sense data.
+ @param[in, out] SenseDataLength The length of output sense data.
+ @param[out] HostAdapterStatus The status of Host Adapter.
+ @param[out] TargetStatus The status of the target.
+ @param[in] SecurityProtocol The Security Protocol to use.
+ @param[in] SecurityProtocolSpecific The Security Protocol Specific data.
+ @param[in] Inc512 If TRUE, 512 increment (INC_512) bit will be set for the
+ SECURITY PROTOCOL IN command.
+ @param[in] DataLength The size in bytes of the data buffer.
+ @param[in, out] DataBuffer A pointer to a data buffer.
+ @param[out] TransferLength A pointer to a buffer to store the size in
+ bytes of the data written to the data buffer.
+
+ @retval EFI_SUCCESS Command is executed successfully.
+ @retval EFI_BAD_BUFFER_SIZE The SCSI Request Packet was executed, but the entire DataBuffer could
+ not be transferred. The actual number of bytes transferred is returned in TransferLength.
+ @retval EFI_NOT_READY The SCSI Request Packet could not be sent because there are too many
+ SCSI Command Packets already queued.
+ @retval EFI_DEVICE_ERROR A device error occurred while attempting to send SCSI Request Packet.
+ @retval EFI_UNSUPPORTED The command described by the SCSI Request Packet is not supported by
+ the SCSI initiator(i.e., SCSI Host Controller)
+ @retval EFI_TIMEOUT A timeout occurred while waiting for the SCSI Request Packet to execute.
+ @retval EFI_INVALID_PARAMETER The contents of the SCSI Request Packet are invalid.
+
+**/
+EFI_STATUS
+EFIAPI
+ScsiSecurityProtocolInCommand (
+ IN EFI_SCSI_IO_PROTOCOL *ScsiIo,
+ IN UINT64 Timeout,
+ IN OUT VOID *SenseData OPTIONAL,
+ IN OUT UINT8 *SenseDataLength,
+ OUT UINT8 *HostAdapterStatus,
+ OUT UINT8 *TargetStatus,
+ IN UINT8 SecurityProtocol,
+ IN UINT16 SecurityProtocolSpecific,
+ IN BOOLEAN Inc512,
+ IN UINTN DataLength,
+ IN OUT VOID *DataBuffer OPTIONAL,
+ OUT UINTN *TransferLength
+ );
+
+/**
+ Execute Security Protocol Out SCSI command on a specific SCSI target.
+
+ Executes the SCSI Security Protocol Out command on the SCSI target specified by ScsiIo.
+ If Timeout is zero, then this function waits indefinitely for the command to complete.
+ If Timeout is greater than zero, then the command is executed and will timeout after
+ Timeout 100 ns units.
+ If ScsiIo is NULL, then ASSERT().
+ If SenseDataLength is NULL, then ASSERT().
+ If HostAdapterStatus is NULL, then ASSERT().
+ If TargetStatus is NULL, then ASSERT().
+
+ If SenseDataLength is non-zero and SenseData is not NULL, SenseData must meet buffer
+ alignment requirement defined in EFI_SCSI_IO_PROTOCOL. Otherwise EFI_INVALID_PARAMETER
+ gets returned.
+
+ If DataLength is non-zero and DataBuffer is not NULL, DataBuffer must meet buffer
+ alignment requirement defined in EFI_SCSI_IO_PROTOCOL. Otherwise EFI_INVALID_PARAMETER
+ gets returned.
+
+ @param[in] ScsiIo SCSI IO Protocol to use.
+ @param[in] Timeout The length of timeout period.
+ @param[in, out] SenseData A pointer to output sense data.
+ @param[in, out] SenseDataLength The length of output sense data.
+ @param[out] HostAdapterStatus The status of Host Adapter.
+ @param[out] TargetStatus The status of the target.
+ @param[in] SecurityProtocol The Security Protocol to use.
+ @param[in] SecurityProtocolSpecific The Security Protocol Specific data.
+ @param[in] Inc512 If TRUE, 512 increment (INC_512) bit will be set for the
+ SECURITY PROTOCOL OUT command.
+ @param[in] DataLength The size in bytes of the transfer data.
+ @param[in, out] DataBuffer A pointer to a data buffer.
+
+ @retval EFI_SUCCESS Command is executed successfully.
+ @retval EFI_BAD_BUFFER_SIZE The SCSI Request Packet was executed, but the entire DataBuffer could
+ not be transferred. The actual number of bytes transferred is returned in DataLength.
+ @retval EFI_NOT_READY The SCSI Request Packet could not be sent because there are too many
+ SCSI Command Packets already queued.
+ @retval EFI_DEVICE_ERROR A device error occurred while attempting to send SCSI Request Packet.
+ @retval EFI_UNSUPPORTED The command described by the SCSI Request Packet is not supported by
+ the SCSI initiator(i.e., SCSI Host Controller)
+ @retval EFI_TIMEOUT A timeout occurred while waiting for the SCSI Request Packet to execute.
+ @retval EFI_INVALID_PARAMETER The contents of the SCSI Request Packet are invalid.
+
+**/
+EFI_STATUS
+EFIAPI
+ScsiSecurityProtocolOutCommand (
+ IN EFI_SCSI_IO_PROTOCOL *ScsiIo,
+ IN UINT64 Timeout,
+ IN OUT VOID *SenseData OPTIONAL,
+ IN OUT UINT8 *SenseDataLength,
+ OUT UINT8 *HostAdapterStatus,
+ OUT UINT8 *TargetStatus,
+ IN UINT8 SecurityProtocol,
+ IN UINT16 SecurityProtocolSpecific,
+ IN BOOLEAN Inc512,
+ IN UINTN DataLength,
+ IN OUT VOID *DataBuffer OPTIONAL
+ );
+
+/**
+ Execute blocking/non-blocking Read(10) SCSI command on a specific SCSI
+ target.
+
+ Executes the SCSI Read(10) command on the SCSI target specified by ScsiIo.
+ When Event is NULL, blocking command will be executed. Otherwise non-blocking
+ command will be executed.
+ For blocking I/O, if Timeout is zero, this function will wait indefinitely
+ for the command to complete. If Timeout is greater than zero, then the
+ command is executed and will timeout after Timeout 100 ns units.
+ For non-blocking I/O, if Timeout is zero, Event will be signaled only after
+ the command to completes. If Timeout is greater than zero, Event will also be
+ signaled after Timeout 100 ns units.
+ The StartLba and SectorSize parameters are used to construct the CDB for this
+ SCSI command.
+
+ If ScsiIo is NULL, then ASSERT().
+ If SenseDataLength is NULL, then ASSERT().
+ If HostAdapterStatus is NULL, then ASSERT().
+ If TargetStatus is NULL, then ASSERT().
+ If DataLength is NULL, then ASSERT().
+
+ If SenseDataLength is non-zero and SenseData is not NULL, SenseData must meet
+ buffer alignment requirement defined in EFI_SCSI_IO_PROTOCOL. Otherwise
+ EFI_INVALID_PARAMETER gets returned.
+
+ If DataLength is non-zero and DataBuffer is not NULL, DataBuffer must meet
+ buffer alignment requirement defined in EFI_SCSI_IO_PROTOCOL. Otherwise
+ EFI_INVALID_PARAMETER gets returned.
+
+ @param[in] ScsiIo A pointer to SCSI IO protocol.
+ @param[in] Timeout The length of timeout period.
+ @param[in, out] SenseData A pointer to output sense data.
+ @param[in, out] SenseDataLength The length of output sense data.
+ @param[out] HostAdapterStatus The status of Host Adapter.
+ @param[out] TargetStatus The status of the target.
+ @param[in, out] DataBuffer Read 16 command data.
+ @param[in, out] DataLength The length of data buffer.
+ @param[in] StartLba The start address of LBA.
+ @param[in] SectorSize The number of contiguous logical blocks
+ of data that shall be transferred.
+ @param[in] Event If the SCSI target does not support
+ non-blocking I/O, then Event is ignored,
+ and blocking I/O is performed. If Event
+ is NULL, then blocking I/O is performed.
+ If Event is not NULL and non-blocking
+ I/O is supported, then non-blocking I/O
+ is performed, and Event will be signaled
+ when the SCSI Read(10) command
+ completes.
+
+ @retval EFI_SUCCESS Command is executed successfully.
+ @retval EFI_BAD_BUFFER_SIZE The SCSI Request Packet was executed,
+ but the entire DataBuffer could not be
+ transferred. The actual number of bytes
+ transferred is returned in DataLength.
+ @retval EFI_NOT_READY The SCSI Request Packet could not be
+ sent because there are too many SCSI
+ Command Packets already queued.
+ @retval EFI_DEVICE_ERROR A device error occurred while attempting
+ to send SCSI Request Packet.
+ @retval EFI_UNSUPPORTED The command described by the SCSI
+ Request Packet is not supported by the
+ SCSI initiator(i.e., SCSI Host
+ Controller)
+ @retval EFI_TIMEOUT A timeout occurred while waiting for the
+ SCSI Request Packet to execute.
+ @retval EFI_INVALID_PARAMETER The contents of the SCSI Request Packet
+ are invalid.
+ @retval EFI_OUT_OF_RESOURCES The request could not be completed due
+ to a lack of resources.
+
+**/
+EFI_STATUS
+EFIAPI
+ScsiRead10CommandEx (
+ IN EFI_SCSI_IO_PROTOCOL *ScsiIo,
+ IN UINT64 Timeout,
+ IN OUT VOID *SenseData OPTIONAL,
+ IN OUT UINT8 *SenseDataLength,
+ OUT UINT8 *HostAdapterStatus,
+ OUT UINT8 *TargetStatus,
+ IN OUT VOID *DataBuffer OPTIONAL,
+ IN OUT UINT32 *DataLength,
+ IN UINT32 StartLba,
+ IN UINT32 SectorSize,
+ IN EFI_EVENT Event OPTIONAL
+ );
+
+/**
+ Execute blocking/non-blocking Write(10) SCSI command on a specific SCSI
+ target.
+
+ Executes the SCSI Write(10) command on the SCSI target specified by ScsiIo.
+ When Event is NULL, blocking command will be executed. Otherwise non-blocking
+ command will be executed.
+ For blocking I/O, if Timeout is zero, this function will wait indefinitely
+ for the command to complete. If Timeout is greater than zero, then the
+ command is executed and will timeout after Timeout 100 ns units.
+ For non-blocking I/O, if Timeout is zero, Event will be signaled only after
+ the command to completes. If Timeout is greater than zero, Event will also be
+ signaled after Timeout 100 ns units.
+ The StartLba and SectorSize parameters are used to construct the CDB for this
+ SCSI command.
+
+ If ScsiIo is NULL, then ASSERT().
+ If SenseDataLength is NULL, then ASSERT().
+ If HostAdapterStatus is NULL, then ASSERT().
+ If TargetStatus is NULL, then ASSERT().
+ If DataLength is NULL, then ASSERT().
+
+ If SenseDataLength is non-zero and SenseData is not NULL, SenseData must meet
+ buffer alignment requirement defined in EFI_SCSI_IO_PROTOCOL. Otherwise
+ EFI_INVALID_PARAMETER gets returned.
+
+ If DataLength is non-zero and DataBuffer is not NULL, DataBuffer must meet
+ buffer alignment requirement defined in EFI_SCSI_IO_PROTOCOL. Otherwise
+ EFI_INVALID_PARAMETER gets returned.
+
+ @param[in] ScsiIo SCSI IO Protocol to use
+ @param[in] Timeout The length of timeout period.
+ @param[in, out] SenseData A pointer to output sense data.
+ @param[in, out] SenseDataLength The length of output sense data.
+ @param[out] HostAdapterStatus The status of Host Adapter.
+ @param[out] TargetStatus The status of the target.
+ @param[in, out] DataBuffer A pointer to a data buffer.
+ @param[in, out] DataLength The length of data buffer.
+ @param[in] StartLba The start address of LBA.
+ @param[in] SectorSize The number of contiguous logical blocks
+ of data that shall be transferred.
+ @param[in] Event If the SCSI target does not support
+ non-blocking I/O, then Event is ignored,
+ and blocking I/O is performed. If Event
+ is NULL, then blocking I/O is performed.
+ If Event is not NULL and non-blocking
+ I/O is supported, then non-blocking I/O
+ is performed, and Event will be signaled
+ when the SCSI Write(10) command
+ completes.
+
+ @retval EFI_SUCCESS Command is executed successfully.
+ @retval EFI_BAD_BUFFER_SIZE The SCSI Request Packet was executed,
+ but the entire DataBuffer could not be
+ transferred. The actual number of bytes
+ transferred is returned in DataLength.
+ @retval EFI_NOT_READY The SCSI Request Packet could not be
+ sent because there are too many SCSI
+ Command Packets already queued.
+ @retval EFI_DEVICE_ERROR A device error occurred while attempting
+ to send SCSI Request Packet.
+ @retval EFI_UNSUPPORTED The command described by the SCSI
+ Request Packet is not supported by the
+ SCSI initiator(i.e., SCSI Host
+ Controller)
+ @retval EFI_TIMEOUT A timeout occurred while waiting for the
+ SCSI Request Packet to execute.
+ @retval EFI_INVALID_PARAMETER The contents of the SCSI Request Packet
+ are invalid.
+ @retval EFI_OUT_OF_RESOURCES The request could not be completed due
+ to a lack of resources.
+
+**/
+EFI_STATUS
+EFIAPI
+ScsiWrite10CommandEx (
+ IN EFI_SCSI_IO_PROTOCOL *ScsiIo,
+ IN UINT64 Timeout,
+ IN OUT VOID *SenseData OPTIONAL,
+ IN OUT UINT8 *SenseDataLength,
+ OUT UINT8 *HostAdapterStatus,
+ OUT UINT8 *TargetStatus,
+ IN OUT VOID *DataBuffer OPTIONAL,
+ IN OUT UINT32 *DataLength,
+ IN UINT32 StartLba,
+ IN UINT32 SectorSize,
+ IN EFI_EVENT Event OPTIONAL
+ );
+
+/**
+ Execute blocking/non-blocking Read(16) SCSI command on a specific SCSI
+ target.
+
+ Executes the SCSI Read(16) command on the SCSI target specified by ScsiIo.
+ When Event is NULL, blocking command will be executed. Otherwise non-blocking
+ command will be executed.
+ For blocking I/O, if Timeout is zero, this function will wait indefinitely
+ for the command to complete. If Timeout is greater than zero, then the
+ command is executed and will timeout after Timeout 100 ns units.
+ For non-blocking I/O, if Timeout is zero, Event will be signaled only after
+ the command to completes. If Timeout is greater than zero, Event will also be
+ signaled after Timeout 100 ns units.
+ The StartLba and SectorSize parameters are used to construct the CDB for this
+ SCSI command.
+
+ If ScsiIo is NULL, then ASSERT().
+ If SenseDataLength is NULL, then ASSERT().
+ If HostAdapterStatus is NULL, then ASSERT().
+ If TargetStatus is NULL, then ASSERT().
+ If DataLength is NULL, then ASSERT().
+
+ If SenseDataLength is non-zero and SenseData is not NULL, SenseData must meet
+ buffer alignment requirement defined in EFI_SCSI_IO_PROTOCOL. Otherwise
+ EFI_INVALID_PARAMETER gets returned.
+
+ If DataLength is non-zero and DataBuffer is not NULL, DataBuffer must meet
+ buffer alignment requirement defined in EFI_SCSI_IO_PROTOCOL. Otherwise
+ EFI_INVALID_PARAMETER gets returned.
+
+ @param[in] ScsiIo A pointer to SCSI IO protocol.
+ @param[in] Timeout The length of timeout period.
+ @param[in, out] SenseData A pointer to output sense data.
+ @param[in, out] SenseDataLength The length of output sense data.
+ @param[out] HostAdapterStatus The status of Host Adapter.
+ @param[out] TargetStatus The status of the target.
+ @param[in, out] DataBuffer Read 16 command data.
+ @param[in, out] DataLength The length of data buffer.
+ @param[in] StartLba The start address of LBA.
+ @param[in] SectorSize The number of contiguous logical blocks
+ of data that shall be transferred.
+ @param[in] Event If the SCSI target does not support
+ non-blocking I/O, then Event is ignored,
+ and blocking I/O is performed. If Event
+ is NULL, then blocking I/O is performed.
+ If Event is not NULL and non-blocking
+ I/O is supported, then non-blocking I/O
+ is performed, and Event will be signaled
+ when the SCSI Read(16) command
+ completes.
+
+ @retval EFI_SUCCESS Command is executed successfully.
+ @retval EFI_BAD_BUFFER_SIZE The SCSI Request Packet was executed,
+ but the entire DataBuffer could not be
+ transferred. The actual number of bytes
+ transferred is returned in DataLength.
+ @retval EFI_NOT_READY The SCSI Request Packet could not be
+ sent because there are too many SCSI
+ Command Packets already queued.
+ @retval EFI_DEVICE_ERROR A device error occurred while attempting
+ to send SCSI Request Packet.
+ @retval EFI_UNSUPPORTED The command described by the SCSI
+ Request Packet is not supported by the
+ SCSI initiator(i.e., SCSI Host
+ Controller)
+ @retval EFI_TIMEOUT A timeout occurred while waiting for the
+ SCSI Request Packet to execute.
+ @retval EFI_INVALID_PARAMETER The contents of the SCSI Request Packet
+ are invalid.
+ @retval EFI_OUT_OF_RESOURCES The request could not be completed due
+ to a lack of resources.
+
+**/
+EFI_STATUS
+EFIAPI
+ScsiRead16CommandEx (
+ IN EFI_SCSI_IO_PROTOCOL *ScsiIo,
+ IN UINT64 Timeout,
+ IN OUT VOID *SenseData OPTIONAL,
+ IN OUT UINT8 *SenseDataLength,
+ OUT UINT8 *HostAdapterStatus,
+ OUT UINT8 *TargetStatus,
+ IN OUT VOID *DataBuffer OPTIONAL,
+ IN OUT UINT32 *DataLength,
+ IN UINT64 StartLba,
+ IN UINT32 SectorSize,
+ IN EFI_EVENT Event OPTIONAL
+ );
+
+/**
+ Execute blocking/non-blocking Write(16) SCSI command on a specific SCSI
+ target.
+
+ Executes the SCSI Write(16) command on the SCSI target specified by ScsiIo.
+ When Event is NULL, blocking command will be executed. Otherwise non-blocking
+ command will be executed.
+ For blocking I/O, if Timeout is zero, this function will wait indefinitely
+ for the command to complete. If Timeout is greater than zero, then the
+ command is executed and will timeout after Timeout 100 ns units.
+ For non-blocking I/O, if Timeout is zero, Event will be signaled only after
+ the command to completes. If Timeout is greater than zero, Event will also be
+ signaled after Timeout 100 ns units.
+ The StartLba and SectorSize parameters are used to construct the CDB for this
+ SCSI command.
+
+ If ScsiIo is NULL, then ASSERT().
+ If SenseDataLength is NULL, then ASSERT().
+ If HostAdapterStatus is NULL, then ASSERT().
+ If TargetStatus is NULL, then ASSERT().
+ If DataLength is NULL, then ASSERT().
+
+ If SenseDataLength is non-zero and SenseData is not NULL, SenseData must meet
+ buffer alignment requirement defined in EFI_SCSI_IO_PROTOCOL. Otherwise
+ EFI_INVALID_PARAMETER gets returned.
+
+ If DataLength is non-zero and DataBuffer is not NULL, DataBuffer must meet
+ buffer alignment requirement defined in EFI_SCSI_IO_PROTOCOL. Otherwise
+ EFI_INVALID_PARAMETER gets returned.
+
+ @param[in] ScsiIo SCSI IO Protocol to use
+ @param[in] Timeout The length of timeout period.
+ @param[in, out] SenseData A pointer to output sense data.
+ @param[in, out] SenseDataLength The length of output sense data.
+ @param[out] HostAdapterStatus The status of Host Adapter.
+ @param[out] TargetStatus The status of the target.
+ @param[in, out] DataBuffer A pointer to a data buffer.
+ @param[in, out] DataLength The length of data buffer.
+ @param[in] StartLba The start address of LBA.
+ @param[in] SectorSize The number of contiguous logical blocks
+ of data that shall be transferred.
+ @param[in] Event If the SCSI target does not support
+ non-blocking I/O, then Event is ignored,
+ and blocking I/O is performed. If Event
+ is NULL, then blocking I/O is performed.
+ If Event is not NULL and non-blocking
+ I/O is supported, then non-blocking I/O
+ is performed, and Event will be signaled
+ when the SCSI Write(16) command
+ completes.
+
+ @retval EFI_SUCCESS Command is executed successfully.
+ @retval EFI_BAD_BUFFER_SIZE The SCSI Request Packet was executed,
+ but the entire DataBuffer could not be
+ transferred. The actual number of bytes
+ transferred is returned in DataLength.
+ @retval EFI_NOT_READY The SCSI Request Packet could not be
+ sent because there are too many SCSI
+ Command Packets already queued.
+ @retval EFI_DEVICE_ERROR A device error occurred while attempting
+ to send SCSI Request Packet.
+ @retval EFI_UNSUPPORTED The command described by the SCSI
+ Request Packet is not supported by the
+ SCSI initiator(i.e., SCSI Host
+ Controller)
+ @retval EFI_TIMEOUT A timeout occurred while waiting for the
+ SCSI Request Packet to execute.
+ @retval EFI_INVALID_PARAMETER The contents of the SCSI Request Packet
+ are invalid.
+ @retval EFI_OUT_OF_RESOURCES The request could not be completed due
+ to a lack of resources.
+
+**/
+EFI_STATUS
+EFIAPI
+ScsiWrite16CommandEx (
+ IN EFI_SCSI_IO_PROTOCOL *ScsiIo,
+ IN UINT64 Timeout,
+ IN OUT VOID *SenseData OPTIONAL,
+ IN OUT UINT8 *SenseDataLength,
+ OUT UINT8 *HostAdapterStatus,
+ OUT UINT8 *TargetStatus,
+ IN OUT VOID *DataBuffer OPTIONAL,
+ IN OUT UINT32 *DataLength,
+ IN UINT64 StartLba,
+ IN UINT32 SectorSize,
+ IN EFI_EVENT Event OPTIONAL
+ );
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/UefiUsbLib.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/UefiUsbLib.h
new file mode 100644
index 0000000000..c570d71ad6
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/UefiUsbLib.h
@@ -0,0 +1,555 @@
+/** @file
+ Provides most USB APIs to support the Hid requests defined in USB Hid 1.1 spec
+ and the standard requests defined in USB 1.1 spec.
+
+Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __USB_DXE_LIB_H__
+#define __USB_DXE_LIB_H__
+
+#include
+
+/**
+ Get the descriptor of the specified USB HID interface.
+
+ Submit a UsbGetHidDescriptor() request for the USB device specified by UsbIo
+ and Interface, and return the HID descriptor in HidDescriptor.
+ If UsbIo is NULL, then ASSERT().
+ If HidDescriptor is NULL, then ASSERT().
+
+ @param UsbIo A pointer to the USB I/O Protocol instance for the specific USB target.
+ @param Interface The index of the HID interface on the USB target.
+ @param HidDescriptor Pointer to the USB HID descriptor that was retrieved from
+ the specified USB target and interface. Type EFI_USB_HID_DESCRIPTOR
+ is defined in the MDE Package Industry Standard include file Usb.h.
+
+ @retval EFI_SUCCESS The request executed successfully.
+ @retval EFI_TIMEOUT A timeout occurred executing the request.
+ @retval EFI_DEVICE_ERROR The request failed due to a device error.
+
+**/
+EFI_STATUS
+EFIAPI
+UsbGetHidDescriptor (
+ IN EFI_USB_IO_PROTOCOL *UsbIo,
+ IN UINT8 Interface,
+ OUT EFI_USB_HID_DESCRIPTOR *HidDescriptor
+ );
+
+/**
+ Get the report descriptor of the specified USB HID interface.
+
+ Submit a USB get HID report descriptor request for the USB device specified by
+ UsbIo and Interface, and return the report descriptor in DescriptorBuffer.
+ If UsbIo is NULL, then ASSERT().
+ If DescriptorBuffer is NULL, then ASSERT().
+
+ @param UsbIo A pointer to the USB I/O Protocol instance for the specific USB target.
+ @param Interface The index of the report interface on the USB target.
+ @param DescriptorLength The size, in bytes, of DescriptorBuffer.
+ @param DescriptorBuffer A pointer to the buffer to store the report class descriptor.
+
+ @retval EFI_SUCCESS The request executed successfully.
+ @retval EFI_OUT_OF_RESOURCES The request could not be completed because the
+ buffer specified by DescriptorLength and DescriptorBuffer
+ is not large enough to hold the result of the request.
+ @retval EFI_TIMEOUT A timeout occurred executing the request.
+ @retval EFI_DEVICE_ERROR The request failed due to a device error.
+
+**/
+EFI_STATUS
+EFIAPI
+UsbGetReportDescriptor (
+ IN EFI_USB_IO_PROTOCOL *UsbIo,
+ IN UINT8 Interface,
+ IN UINT16 DescriptorLength,
+ OUT UINT8 *DescriptorBuffer
+ );
+
+/**
+ Get the HID protocol of the specified USB HID interface.
+
+ Submit a USB get HID protocol request for the USB device specified by UsbIo
+ and Interface, and return the protocol retrieved in Protocol.
+ If UsbIo is NULL, then ASSERT().
+ If Protocol is NULL, then ASSERT().
+
+ @param UsbIo A pointer to the USB I/O Protocol instance for the specific USB target.
+ @param Interface The index of the report interface on the USB target.
+ @param Protocol A pointer to the protocol for the specified USB target.
+
+ @retval EFI_SUCCESS The request executed successfully.
+ @retval EFI_TIMEOUT A timeout occurred executing the request.
+ @retval EFI_DEVICE_ERROR The request failed due to a device error.
+
+**/
+EFI_STATUS
+EFIAPI
+UsbGetProtocolRequest (
+ IN EFI_USB_IO_PROTOCOL *UsbIo,
+ IN UINT8 Interface,
+ OUT UINT8 *Protocol
+ );
+
+/**
+ Set the HID protocol of the specified USB HID interface.
+
+ Submit a USB set HID protocol request for the USB device specified by UsbIo
+ and Interface, and set the protocol to the value specified by Protocol.
+ If UsbIo is NULL, then ASSERT().
+
+ @param UsbIo A pointer to the USB I/O Protocol instance for the specific USB target.
+ @param Interface The index of the report interface on the USB target.
+ @param Protocol The protocol value to set for the specified USB target.
+
+ @retval EFI_SUCCESS The request executed successfully.
+ @retval EFI_TIMEOUT A timeout occurred executing the request.
+ @retval EFI_DEVICE_ERROR The request failed due to a device error.
+
+**/
+EFI_STATUS
+EFIAPI
+UsbSetProtocolRequest (
+ IN EFI_USB_IO_PROTOCOL *UsbIo,
+ IN UINT8 Interface,
+ IN UINT8 Protocol
+ );
+
+/**
+ Set the idle rate of the specified USB HID report.
+
+ Submit a USB set HID report idle request for the USB device specified by UsbIo,
+ Interface, and ReportId, and set the idle rate to the value specified by Duration.
+ If UsbIo is NULL, then ASSERT().
+
+ @param UsbIo A pointer to the USB I/O Protocol instance for the specific USB target.
+ @param Interface The index of the report interface on the USB target.
+ @param ReportId The identifier of the report to retrieve.
+ @param Duration The idle rate to set for the specified USB target.
+
+ @retval EFI_SUCCESS The request executed successfully.
+ @retval EFI_TIMEOUT A timeout occurred executing the request.
+ @retval EFI_DEVICE_ERROR The request failed due to a device error.
+
+**/
+EFI_STATUS
+EFIAPI
+UsbSetIdleRequest (
+ IN EFI_USB_IO_PROTOCOL *UsbIo,
+ IN UINT8 Interface,
+ IN UINT8 ReportId,
+ IN UINT8 Duration
+ );
+
+/**
+ Get the idle rate of the specified USB HID report.
+
+ Submit a USB get HID report idle request for the USB device specified by UsbIo,
+ Interface, and ReportId, and return the ide rate in Duration.
+ If UsbIo is NULL, then ASSERT().
+ If Duration is NULL, then ASSERT().
+
+ @param UsbIo A pointer to the USB I/O Protocol instance for the specific USB target.
+ @param Interface The index of the report interface on the USB target.
+ @param ReportId The identifier of the report to retrieve.
+ @param Duration A pointer to the idle rate retrieved from the specified USB target.
+
+ @retval EFI_SUCCESS The request executed successfully.
+ @retval EFI_TIMEOUT A timeout occurred executing the request.
+ @retval EFI_DEVICE_ERROR The request failed due to a device error.
+
+**/
+EFI_STATUS
+EFIAPI
+UsbGetIdleRequest (
+ IN EFI_USB_IO_PROTOCOL *UsbIo,
+ IN UINT8 Interface,
+ IN UINT8 ReportId,
+ OUT UINT8 *Duration
+ );
+
+/**
+ Set the report descriptor of the specified USB HID interface.
+
+ Submit a USB set HID report request for the USB device specified by UsbIo,
+ Interface, ReportId, and ReportType, and set the report descriptor using the
+ buffer specified by ReportLength and Report.
+ If UsbIo is NULL, then ASSERT().
+ If Report is NULL, then ASSERT().
+
+ @param UsbIo A pointer to the USB I/O Protocol instance for the specific USB target.
+ @param Interface The index of the report interface on the USB target.
+ @param ReportId The identifier of the report to retrieve.
+ @param ReportType The type of report to retrieve.
+ @param ReportLength The size, in bytes, of Report.
+ @param Report A pointer to the report descriptor buffer to set.
+
+ @retval EFI_SUCCESS The request executed successfully.
+ @retval EFI_TIMEOUT A timeout occurred executing the request.
+ @retval EFI_DEVICE_ERROR The request failed due to a device error.
+
+**/
+EFI_STATUS
+EFIAPI
+UsbSetReportRequest (
+ IN EFI_USB_IO_PROTOCOL *UsbIo,
+ IN UINT8 Interface,
+ IN UINT8 ReportId,
+ IN UINT8 ReportType,
+ IN UINT16 ReportLen,
+ IN UINT8 *Report
+ );
+
+/**
+ Get the report descriptor of the specified USB HID interface.
+
+ Submit a USB get HID report request for the USB device specified by UsbIo,
+ Interface, ReportId, and ReportType, and return the report in the buffer
+ specified by Report.
+ If UsbIo is NULL, then ASSERT().
+ If Report is NULL, then ASSERT().
+
+ @param UsbIo A pointer to the USB I/O Protocol instance for the specific USB target.
+ @param Interface The index of the report interface on the USB target.
+ @param ReportId The identifier of the report to retrieve.
+ @param ReportType The type of report to retrieve.
+ @param ReportLength The size, in bytes, of Report.
+ @param Report A pointer to the buffer to store the report descriptor.
+
+ @retval EFI_SUCCESS The request executed successfully.
+ @retval EFI_OUT_OF_RESOURCES The request could not be completed because the
+ buffer specified by ReportLength and Report is not
+ large enough to hold the result of the request.
+ @retval EFI_TIMEOUT A timeout occurred executing the request.
+ @retval EFI_DEVICE_ERROR The request failed due to a device error.
+
+**/
+EFI_STATUS
+EFIAPI
+UsbGetReportRequest (
+ IN EFI_USB_IO_PROTOCOL *UsbIo,
+ IN UINT8 Interface,
+ IN UINT8 ReportId,
+ IN UINT8 ReportType,
+ IN UINT16 ReportLen,
+ OUT UINT8 *Report
+ );
+
+/**
+ Get the descriptor of the specified USB device.
+
+ Submit a USB get descriptor request for the USB device specified by UsbIo, Value,
+ and Index, and return the descriptor in the buffer specified by Descriptor.
+ The status of the transfer is returned in Status.
+ If UsbIo is NULL, then ASSERT().
+ If Descriptor is NULL, then ASSERT().
+ If Status is NULL, then ASSERT().
+
+ @param UsbIo A pointer to the USB I/O Protocol instance for the specific USB target.
+ @param Value The device request value.
+ @param Index The device request index.
+ @param DescriptorLength The size, in bytes, of Descriptor.
+ @param Descriptor A pointer to the descriptor buffer to get.
+ @param Status A pointer to the status of the transfer.
+
+ @retval EFI_SUCCESS The request executed successfully.
+ @retval EFI_OUT_OF_RESOURCES The request could not be completed because the
+ buffer specified by DescriptorLength and Descriptor
+ is not large enough to hold the result of the request.
+ @retval EFI_TIMEOUT A timeout occurred executing the request.
+ @retval EFI_DEVICE_ERROR The request failed due to a device error. The transfer
+ status is returned in Status.
+
+**/
+EFI_STATUS
+EFIAPI
+UsbGetDescriptor (
+ IN EFI_USB_IO_PROTOCOL *UsbIo,
+ IN UINT16 Value,
+ IN UINT16 Index,
+ IN UINT16 DescriptorLength,
+ OUT VOID *Descriptor,
+ OUT UINT32 *Status
+ );
+
+/**
+ Set the descriptor of the specified USB device.
+
+ Submit a USB set descriptor request for the USB device specified by UsbIo,
+ Value, and Index, and set the descriptor using the buffer specified by DesriptorLength
+ and Descriptor. The status of the transfer is returned in Status.
+ If UsbIo is NULL, then ASSERT().
+ If Descriptor is NULL, then ASSERT().
+ If Status is NULL, then ASSERT().
+
+ @param UsbIo A pointer to the USB I/O Protocol instance for the specific USB target.
+ @param Value The device request value.
+ @param Index The device request index.
+ @param DescriptorLength The size, in bytes, of Descriptor.
+ @param Descriptor A pointer to the descriptor buffer to set.
+ @param Status A pointer to the status of the transfer.
+
+ @retval EFI_SUCCESS The request executed successfully.
+ @retval EFI_TIMEOUT A timeout occurred executing the request.
+ @retval EFI_DEVICE_ERROR The request failed due to a device error.
+ The transfer status is returned in Status.
+
+**/
+EFI_STATUS
+EFIAPI
+UsbSetDescriptor (
+ IN EFI_USB_IO_PROTOCOL *UsbIo,
+ IN UINT16 Value,
+ IN UINT16 Index,
+ IN UINT16 DescriptorLength,
+ IN VOID *Descriptor,
+ OUT UINT32 *Status
+ );
+
+/**
+ Get the interface setting of the specified USB device.
+
+ Submit a USB get interface request for the USB device specified by UsbIo,
+ and Interface, and place the result in the buffer specified by AlternateSetting.
+ The status of the transfer is returned in Status.
+ If UsbIo is NULL, then ASSERT().
+ If AlternateSetting is NULL, then ASSERT().
+ If Status is NULL, then ASSERT().
+
+ @param UsbIo A pointer to the USB I/O Protocol instance for the specific USB target.
+ @param Interface The interface index value.
+ @param AlternateSetting A pointer to the alternate setting to be retrieved.
+ @param Status A pointer to the status of the transfer.
+
+ @retval EFI_SUCCESS The request executed successfully.
+ @retval EFI_TIMEOUT A timeout occurred executing the request.
+ @retval EFI_DEVICE_ERROR The request failed due to a device error.
+ The transfer status is returned in Status.
+
+**/
+EFI_STATUS
+EFIAPI
+UsbGetInterface (
+ IN EFI_USB_IO_PROTOCOL *UsbIo,
+ IN UINT16 Interface,
+ OUT UINT16 *AlternateSetting,
+ OUT UINT32 *Status
+ );
+
+/**
+ Set the interface setting of the specified USB device.
+
+ Submit a USB set interface request for the USB device specified by UsbIo, and
+ Interface, and set the alternate setting to the value specified by AlternateSetting.
+ The status of the transfer is returned in Status.
+ If UsbIo is NULL, then ASSERT().
+ If Status is NULL, then ASSERT().
+
+ @param UsbIo A pointer to the USB I/O Protocol instance for the specific USB target.
+ @param Interface The interface index value.
+ @param AlternateSetting The alternate setting to be set.
+ @param Status A pointer to the status of the transfer.
+
+ @retval EFI_SUCCESS The request executed successfully.
+ @retval EFI_TIMEOUT A timeout occurred executing the request.
+ @retval EFI_SUCCESS The request failed due to a device error.
+ The transfer status is returned in Status.
+
+**/
+EFI_STATUS
+EFIAPI
+UsbSetInterface (
+ IN EFI_USB_IO_PROTOCOL *UsbIo,
+ IN UINT16 Interface,
+ IN UINT16 AlternateSetting,
+ OUT UINT32 *Status
+ );
+
+/**
+ Get the device configuration.
+
+ Submit a USB get configuration request for the USB device specified by UsbIo
+ and place the result in the buffer specified by ConfigurationValue. The status
+ of the transfer is returned in Status.
+ If UsbIo is NULL, then ASSERT().
+ If ConfigurationValue is NULL, then ASSERT().
+ If Status is NULL, then ASSERT().
+
+ @param UsbIo A pointer to the USB I/O Protocol instance for the specific USB target.
+ @param ConfigurationValue A pointer to the device configuration to be retrieved.
+ @param Status A pointer to the status of the transfer.
+
+ @retval EFI_SUCCESS The request executed successfully.
+ @retval EFI_TIMEOUT A timeout occurred executing the request.
+ @retval EFI_DEVICE_ERROR The request failed due to a device error.
+ The transfer status is returned in Status.
+
+**/
+EFI_STATUS
+EFIAPI
+UsbGetConfiguration (
+ IN EFI_USB_IO_PROTOCOL *UsbIo,
+ OUT UINT16 *ConfigurationValue,
+ OUT UINT32 *Status
+ );
+
+/**
+ Set the device configuration.
+
+ Submit a USB set configuration request for the USB device specified by UsbIo
+ and set the device configuration to the value specified by ConfigurationValue.
+ The status of the transfer is returned in Status.
+ If UsbIo is NULL, then ASSERT().
+ If Status is NULL, then ASSERT().
+
+ @param UsbIo A pointer to the USB I/O Protocol instance for the specific USB target.
+ @param ConfigurationValue The device configuration value to be set.
+ @param Status A pointer to the status of the transfer.
+
+ @retval EFI_SUCCESS The request executed successfully.
+ @retval EFI_TIMEOUT A timeout occurred executing the request.
+ @retval EFI_DEVICE_ERROR The request failed due to a device error.
+ The transfer status is returned in Status.
+
+**/
+EFI_STATUS
+EFIAPI
+UsbSetConfiguration (
+ IN EFI_USB_IO_PROTOCOL *UsbIo,
+ IN UINT16 ConfigurationValue,
+ OUT UINT32 *Status
+ );
+
+/**
+ Set the specified feature of the specified device.
+
+ Submit a USB set device feature request for the USB device specified by UsbIo,
+ Recipient, and Target to the value specified by Value. The status of the
+ transfer is returned in Status.
+ If UsbIo is NULL, then ASSERT().
+ If Status is NULL, then ASSERT().
+
+ @param UsbIo A pointer to the USB I/O Protocol instance for the specific USB target.
+ @param Recipient The USB data recipient type (i.e. Device, Interface, Endpoint).
+ Type USB_TYPES_DEFINITION is defined in the MDE Package Industry
+ Standard include file Usb.h.
+ @param Value The value of the feature to be set.
+ @param Target The index of the device to be set.
+ @param Status A pointer to the status of the transfer.
+
+ @retval EFI_SUCCESS The request executed successfully.
+ @retval EFI_TIMEOUT A timeout occurred executing the request.
+ @retval EFI_DEVICE_ERROR The request failed due to a device error.
+ The transfer status is returned in Status.
+
+**/
+EFI_STATUS
+EFIAPI
+UsbSetFeature (
+ IN EFI_USB_IO_PROTOCOL *UsbIo,
+ IN USB_TYPES_DEFINITION Recipient,
+ IN UINT16 Value,
+ IN UINT16 Target,
+ OUT UINT32 *Status
+ );
+
+/**
+ Clear the specified feature of the specified device.
+
+ Submit a USB clear device feature request for the USB device specified by UsbIo,
+ Recipient, and Target to the value specified by Value. The status of the transfer
+ is returned in Status.
+ If UsbIo is NULL, then ASSERT().
+ If Status is NULL, then ASSERT().
+
+ @param UsbIo A pointer to the USB I/O Protocol instance for the specific USB target.
+ @param Recipient The USB data recipient type (i.e. Device, Interface, Endpoint).
+ Type USB_TYPES_DEFINITION is defined in the MDE Package Industry Standard
+ include file Usb.h.
+ @param Value The value of the feature to be cleared.
+ @param Target The index of the device to be cleared.
+ @param Status A pointer to the status of the transfer.
+
+ @retval EFI_SUCCESS The request executed successfully.
+ @retval EFI_TIMEOUT A timeout occurred executing the request.
+ @retval EFI_DEVICE_ERROR The request failed due to a device error.
+ The transfer status is returned in Status.
+
+**/
+EFI_STATUS
+EFIAPI
+UsbClearFeature (
+ IN EFI_USB_IO_PROTOCOL *UsbIo,
+ IN USB_TYPES_DEFINITION Recipient,
+ IN UINT16 Value,
+ IN UINT16 Target,
+ OUT UINT32 *Status
+ );
+
+/**
+ Get the status of the specified device.
+
+ Submit a USB device get status request for the USB device specified by UsbIo,
+ Recipient, and Target, and place the result in the buffer specified by DeviceStatus.
+ The status of the transfer is returned in Status.
+ If UsbIo is NULL, then ASSERT().
+ If DeviceStatus is NULL, then ASSERT().
+ If Status is NULL, then ASSERT().
+
+ @param UsbIo A pointer to the USB I/O Protocol instance for the specific USB target.
+ @param Recipient The USB data recipient type (i.e. Device, Interface, Endpoint).
+ Type USB_TYPES_DEFINITION is defined in the MDE Package Industry Standard
+ include file Usb.h.
+ @param Target The index of the device to be get the status of.
+ @param DeviceStatus A pointer to the device status to be retrieved.
+ @param Status A pointer to the status of the transfer.
+
+ @retval EFI_SUCCESS The request executed successfully.
+ @retval EFI_TIMEOUT A timeout occurred executing the request.
+ @retval EFI_DEVICE_ERROR The request failed due to a device error.
+ The transfer status is returned in Status.
+
+**/
+EFI_STATUS
+EFIAPI
+UsbGetStatus (
+ IN EFI_USB_IO_PROTOCOL *UsbIo,
+ IN USB_TYPES_DEFINITION Recipient,
+ IN UINT16 Target,
+ OUT UINT16 *DeviceStatus,
+ OUT UINT32 *Status
+ );
+
+/**
+ Clear halt feature of the specified usb endpoint.
+
+ Retrieve the USB endpoint descriptor specified by UsbIo and EndPoint.
+ If the USB endpoint descriptor can not be retrieved, then return EFI_NOT_FOUND.
+ If the endpoint descriptor is found, then clear the halt feature of this USB endpoint.
+ The status of the transfer is returned in Status.
+ If UsbIo is NULL, then ASSERT().
+ If Status is NULL, then ASSERT().
+
+ @param UsbIo A pointer to the USB I/O Protocol instance for the specific USB target.
+ @param Endpoint The endpoint address.
+ @param Status A pointer to the status of the transfer.
+
+ @retval EFI_SUCCESS The request executed successfully.
+ @retval EFI_TIMEOUT A timeout occurred executing the request.
+ @retval EFI_DEVICE_ERROR The request failed due to a device error.
+ The transfer status is returned in Status.
+ @retval EFI_NOT_FOUND The specified USB endpoint descriptor can not be found
+
+**/
+EFI_STATUS
+EFIAPI
+UsbClearEndpointHalt (
+ IN EFI_USB_IO_PROTOCOL *UsbIo,
+ IN UINT8 Endpoint,
+ OUT UINT32 *Status
+ );
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/UnitTestLib.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/UnitTestLib.h
new file mode 100644
index 0000000000..875a5690e6
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Library/UnitTestLib.h
@@ -0,0 +1,844 @@
+/** @file
+ Provides a unit test framework. This allows tests to focus on testing logic
+ and the framework to focus on runnings, reporting, statistics, etc.
+
+ Copyright (c) Microsoft Corporation.
+ Copyright (c) 2020, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef __UNIT_TEST_LIB_H__
+#define __UNIT_TEST_LIB_H__
+
+///
+/// Unit Test Status
+///
+typedef UINT32 UNIT_TEST_STATUS;
+#define UNIT_TEST_PASSED (0)
+#define UNIT_TEST_ERROR_PREREQUISITE_NOT_MET (1)
+#define UNIT_TEST_ERROR_TEST_FAILED (2)
+#define UNIT_TEST_ERROR_CLEANUP_FAILED (3)
+#define UNIT_TEST_SKIPPED (0xFFFFFFFD)
+#define UNIT_TEST_RUNNING (0xFFFFFFFE)
+#define UNIT_TEST_PENDING (0xFFFFFFFF)
+
+///
+/// Declare PcdUnitTestLogLevel bits and UnitTestLog() ErrorLevel parameter.
+///
+#define UNIT_TEST_LOG_LEVEL_ERROR BIT0
+#define UNIT_TEST_LOG_LEVEL_WARN BIT1
+#define UNIT_TEST_LOG_LEVEL_INFO BIT2
+#define UNIT_TEST_LOG_LEVEL_VERBOSE BIT3
+
+///
+/// Unit Test Framework Handle
+///
+struct UNIT_TEST_FRAMEWORK_OBJECT;
+typedef struct UNIT_TEST_FRAMEWORK_OBJECT *UNIT_TEST_FRAMEWORK_HANDLE;
+
+///
+/// Unit Test Suite Handle
+///
+struct UNIT_TEST_SUITE_OBJECT;
+typedef struct UNIT_TEST_SUITE_OBJECT *UNIT_TEST_SUITE_HANDLE;
+
+///
+/// Unit Test Handle
+///
+struct UNIT_TEST_OBJECT;
+typedef struct UNIT_TEST_OBJECT *UNIT_TEST_HANDLE;
+
+///
+/// Unit Test Context
+///
+typedef VOID *UNIT_TEST_CONTEXT;
+
+/**
+ The prototype for a single UnitTest case function.
+
+ Functions with this prototype are registered to be dispatched by the
+ UnitTest framework, and results are recorded as test Pass or Fail.
+
+ @param[in] Context [Optional] An optional parameter that enables:
+ 1) test-case reuse with varied parameters and
+ 2) test-case re-entry for Target tests that need a
+ reboot. This parameter is a VOID* and it is the
+ responsibility of the test author to ensure that the
+ contents are well understood by all test cases that may
+ consume it.
+
+ @retval UNIT_TEST_PASSED The Unit test has completed and the test
+ case was successful.
+ @retval UNIT_TEST_ERROR_TEST_FAILED A test case assertion has failed.
+
+**/
+typedef
+UNIT_TEST_STATUS
+(EFIAPI *UNIT_TEST_FUNCTION)(
+ IN UNIT_TEST_CONTEXT Context
+ );
+
+/**
+ Unit-Test Prerequisite Function pointer type.
+
+ Functions with this prototype are registered to be dispatched by the unit test
+ framework prior to a given test case. If this prereq function returns
+ UNIT_TEST_ERROR_PREREQUISITE_NOT_MET, the test case will be skipped.
+
+ @param[in] Context [Optional] An optional parameter that enables:
+ 1) test-case reuse with varied parameters and
+ 2) test-case re-entry for Target tests that need a
+ reboot. This parameter is a VOID* and it is the
+ responsibility of the test author to ensure that the
+ contents are well understood by all test cases that may
+ consume it.
+
+ @retval UNIT_TEST_PASSED Unit test case prerequisites
+ are met.
+ @retval UNIT_TEST_ERROR_PREREQUISITE_NOT_MET Test case should be skipped.
+
+**/
+typedef
+UNIT_TEST_STATUS
+(EFIAPI *UNIT_TEST_PREREQUISITE)(
+ IN UNIT_TEST_CONTEXT Context
+ );
+
+/**
+ Unit-Test Cleanup (after) function pointer type.
+
+ Functions with this prototype are registered to be dispatched by the
+ unit test framework after a given test case. This will be called even if the
+ test case returns an error, but not if the prerequisite fails and the test is
+ skipped. The purpose of this function is to clean up any global state or
+ test data.
+
+ @param[in] Context [Optional] An optional parameter that enables:
+ 1) test-case reuse with varied parameters and
+ 2) test-case re-entry for Target tests that need a
+ reboot. This parameter is a VOID* and it is the
+ responsibility of the test author to ensure that the
+ contents are well understood by all test cases that may
+ consume it.
+
+ @retval UNIT_TEST_PASSED Test case cleanup succeeded.
+ @retval UNIT_TEST_ERROR_CLEANUP_FAILED Test case cleanup failed.
+
+**/
+typedef
+VOID
+(EFIAPI *UNIT_TEST_CLEANUP)(
+ IN UNIT_TEST_CONTEXT Context
+ );
+
+/**
+ Unit-Test Test Suite Setup (before) function pointer type. Functions with this
+ prototype are registered to be dispatched by the UnitTest framework prior to
+ running any of the test cases in a test suite. It will only be run once at
+ the beginning of the suite (not prior to each case).
+
+ The purpose of this function is to set up any global state or test data.
+**/
+typedef
+VOID
+(EFIAPI *UNIT_TEST_SUITE_SETUP)(
+ VOID
+ );
+
+/**
+ Unit-Test Test Suite Teardown (after) function pointer type. Functions with
+ this prototype are registered to be dispatched by the UnitTest framework after
+ running all of the test cases in a test suite. It will only be run once at
+ the end of the suite.
+
+ The purpose of this function is to clean up any global state or test data.
+**/
+typedef
+VOID
+(EFIAPI *UNIT_TEST_SUITE_TEARDOWN)(
+ VOID
+ );
+
+/**
+ Method to Initialize the Unit Test framework. This function registers the
+ test name and also initializes the internal state of the test framework to
+ receive any new suites and tests.
+
+ @param[out] FrameworkHandle Unit test framework to be created.
+ @param[in] Title Null-terminated ASCII string that is the user
+ friendly name of the framework. String is
+ copied.
+ @param[in] ShortTitle Null-terminated ASCII short string that is the
+ short name of the framework with no spaces.
+ String is copied.
+ @param[in] VersionString Null-terminated ASCII version string for the
+ framework. String is copied.
+
+ @retval EFI_SUCCESS The unit test framework was initialized.
+ @retval EFI_INVALID_PARAMETER FrameworkHandle is NULL.
+ @retval EFI_INVALID_PARAMETER Title is NULL.
+ @retval EFI_INVALID_PARAMETER ShortTitle is NULL.
+ @retval EFI_INVALID_PARAMETER VersionString is NULL.
+ @retval EFI_INVALID_PARAMETER ShortTitle is invalid.
+ @retval EFI_OUT_OF_RESOURCES There are not enough resources available to
+ initialize the unit test framework.
+**/
+EFI_STATUS
+EFIAPI
+InitUnitTestFramework (
+ OUT UNIT_TEST_FRAMEWORK_HANDLE *FrameworkHandle,
+ IN CHAR8 *Title,
+ IN CHAR8 *ShortTitle,
+ IN CHAR8 *VersionString
+ );
+
+/**
+ Registers a Unit Test Suite in the Unit Test Framework.
+ At least one test suite must be registered, because all test cases must be
+ within a unit test suite.
+
+ @param[out] SuiteHandle Unit test suite to create
+ @param[in] FrameworkHandle Unit test framework to add unit test suite to
+ @param[in] Title Null-terminated ASCII string that is the user
+ friendly name of the test suite. String is
+ copied.
+ @param[in] Name Null-terminated ASCII string that is the short
+ name of the test suite with no spaces. String
+ is copied.
+ @param[in] Setup Setup function, runs before suite. This is an
+ optional parameter that may be NULL.
+ @param[in] Teardown Teardown function, runs after suite. This is an
+ optional parameter that may be NULL.
+
+ @retval EFI_SUCCESS The unit test suite was created.
+ @retval EFI_INVALID_PARAMETER SuiteHandle is NULL.
+ @retval EFI_INVALID_PARAMETER FrameworkHandle is NULL.
+ @retval EFI_INVALID_PARAMETER Title is NULL.
+ @retval EFI_INVALID_PARAMETER Name is NULL.
+ @retval EFI_OUT_OF_RESOURCES There are not enough resources available to
+ initialize the unit test suite.
+**/
+EFI_STATUS
+EFIAPI
+CreateUnitTestSuite (
+ OUT UNIT_TEST_SUITE_HANDLE *SuiteHandle,
+ IN UNIT_TEST_FRAMEWORK_HANDLE FrameworkHandle,
+ IN CHAR8 *Title,
+ IN CHAR8 *Name,
+ IN UNIT_TEST_SUITE_SETUP Setup OPTIONAL,
+ IN UNIT_TEST_SUITE_TEARDOWN Teardown OPTIONAL
+ );
+
+/**
+ Adds test case to Suite
+
+ @param[in] SuiteHandle Unit test suite to add test to.
+ @param[in] Description Null-terminated ASCII string that is the user
+ friendly description of a test. String is copied.
+ @param[in] Name Null-terminated ASCII string that is the short name
+ of the test with no spaces. String is copied.
+ @param[in] Function Unit test function.
+ @param[in] Prerequisite Prerequisite function, runs before test. This is
+ an optional parameter that may be NULL.
+ @param[in] CleanUp Clean up function, runs after test. This is an
+ optional parameter that may be NULL.
+ @param[in] Context Pointer to context. This is an optional parameter
+ that may be NULL.
+
+ @retval EFI_SUCCESS The unit test case was added to Suite.
+ @retval EFI_INVALID_PARAMETER SuiteHandle is NULL.
+ @retval EFI_INVALID_PARAMETER Description is NULL.
+ @retval EFI_INVALID_PARAMETER Name is NULL.
+ @retval EFI_INVALID_PARAMETER Function is NULL.
+ @retval EFI_OUT_OF_RESOURCES There are not enough resources available to
+ add the unit test case to Suite.
+**/
+EFI_STATUS
+EFIAPI
+AddTestCase (
+ IN UNIT_TEST_SUITE_HANDLE SuiteHandle,
+ IN CHAR8 *Description,
+ IN CHAR8 *Name,
+ IN UNIT_TEST_FUNCTION Function,
+ IN UNIT_TEST_PREREQUISITE Prerequisite OPTIONAL,
+ IN UNIT_TEST_CLEANUP CleanUp OPTIONAL,
+ IN UNIT_TEST_CONTEXT Context OPTIONAL
+ );
+
+/**
+ Execute all unit test cases in all unit test suites added to a Framework.
+
+ Once a unit test framework is initialized and all unit test suites and unit
+ test cases are registered, this function will cause the unit test framework to
+ dispatch all unit test cases in sequence and record the results for reporting.
+
+ @param[in] FrameworkHandle A handle to the current running framework that
+ dispatched the test. Necessary for recording
+ certain test events with the framework.
+
+ @retval EFI_SUCCESS All test cases were dispatched.
+ @retval EFI_INVALID_PARAMETER FrameworkHandle is NULL.
+**/
+EFI_STATUS
+EFIAPI
+RunAllTestSuites (
+ IN UNIT_TEST_FRAMEWORK_HANDLE FrameworkHandle
+ );
+
+/**
+ Cleanup a test framework.
+
+ After tests are run, this will teardown the entire framework and free all
+ allocated data within.
+
+ @param[in] FrameworkHandle A handle to the current running framework that
+ dispatched the test. Necessary for recording
+ certain test events with the framework.
+
+ @retval EFI_SUCCESS All resources associated with framework were
+ freed.
+ @retval EFI_INVALID_PARAMETER FrameworkHandle is NULL.
+**/
+EFI_STATUS
+EFIAPI
+FreeUnitTestFramework (
+ IN UNIT_TEST_FRAMEWORK_HANDLE FrameworkHandle
+ );
+
+/**
+ Leverages a framework-specific mechanism (see UnitTestPersistenceLib if you're
+ a framework author) to save the state of the executing framework along with
+ any allocated data so that the test may be resumed upon reentry. A test case
+ should pass any needed context (which, to prevent an infinite loop, should be
+ at least the current execution count) which will be saved by the framework and
+ passed to the test case upon resume.
+
+ This should be called while the current test framework is valid and active. It is
+ generally called from within a test case prior to quitting or rebooting.
+
+ @param[in] ContextToSave A buffer of test case-specific data to be saved
+ along with framework state. Will be passed as
+ "Context" to the test case upon resume. This
+ is an optional parameter that may be NULL.
+ @param[in] ContextToSaveSize Size of the ContextToSave buffer.
+
+ @retval EFI_SUCCESS The framework state and context were saved.
+ @retval EFI_NOT_FOUND An active framework handle was not found.
+ @retval EFI_INVALID_PARAMETER ContextToSave is not NULL and
+ ContextToSaveSize is 0.
+ @retval EFI_INVALID_PARAMETER ContextToSave is >= 4GB.
+ @retval EFI_OUT_OF_RESOURCES There are not enough resources available to
+ save the framework and context state.
+ @retval EFI_DEVICE_ERROR The framework and context state could not be
+ saved to a persistent storage device due to a
+ device error.
+**/
+EFI_STATUS
+EFIAPI
+SaveFrameworkState (
+ IN UNIT_TEST_CONTEXT ContextToSave OPTIONAL,
+ IN UINTN ContextToSaveSize
+ );
+
+/**
+ This macro uses the framework assertion logic to check an expression for
+ "TRUE". If the expression evaluates to TRUE, execution continues.
+ Otherwise, the test case immediately returns UNIT_TEST_ERROR_TEST_FAILED.
+
+ @param[in] Expression Expression to be evaluated for TRUE.
+**/
+#define UT_ASSERT_TRUE(Expression) \
+ if(!UnitTestAssertTrue ((Expression), __FUNCTION__, DEBUG_LINE_NUMBER, __FILE__, #Expression)) { \
+ return UNIT_TEST_ERROR_TEST_FAILED; \
+ }
+
+/**
+ This macro uses the framework assertion logic to check an expression for
+ "FALSE". If the expression evaluates to FALSE, execution continues.
+ Otherwise, the test case immediately returns UNIT_TEST_ERROR_TEST_FAILED.
+
+ @param[in] Expression Expression to be evaluated for FALSE.
+**/
+#define UT_ASSERT_FALSE(Expression) \
+ if(!UnitTestAssertFalse ((Expression), __FUNCTION__, DEBUG_LINE_NUMBER, __FILE__, #Expression)) { \
+ return UNIT_TEST_ERROR_TEST_FAILED; \
+ }
+
+/**
+ This macro uses the framework assertion logic to check whether two simple
+ values are equal. If the values are equal, execution continues.
+ Otherwise, the test case immediately returns UNIT_TEST_ERROR_TEST_FAILED.
+
+ @param[in] ValueA Value to be compared for equality (64-bit comparison).
+ @param[in] ValueB Value to be compared for equality (64-bit comparison).
+**/
+#define UT_ASSERT_EQUAL(ValueA, ValueB) \
+ if(!UnitTestAssertEqual ((UINT64)(ValueA), (UINT64)(ValueB), __FUNCTION__, DEBUG_LINE_NUMBER, __FILE__, #ValueA, #ValueB)) { \
+ return UNIT_TEST_ERROR_TEST_FAILED; \
+ }
+
+/**
+ This macro uses the framework assertion logic to check whether two memory
+ buffers are equal. If the buffers are equal, execution continues.
+ Otherwise, the test case immediately returns UNIT_TEST_ERROR_TEST_FAILED.
+
+ @param[in] BufferA Pointer to a buffer for comparison.
+ @param[in] BufferB Pointer to a buffer for comparison.
+ @param[in] Length Number of bytes to compare in BufferA and BufferB.
+**/
+#define UT_ASSERT_MEM_EQUAL(BufferA, BufferB, Length) \
+ if(!UnitTestAssertMemEqual ((VOID *)(UINTN)(BufferA), (VOID *)(UINTN)(BufferB), (UINTN)Length, __FUNCTION__, DEBUG_LINE_NUMBER, __FILE__, #BufferA, #BufferB)) { \
+ return UNIT_TEST_ERROR_TEST_FAILED; \
+ }
+
+/**
+ This macro uses the framework assertion logic to check whether two simple
+ values are non-equal. If the values are non-equal, execution continues.
+ Otherwise, the test case immediately returns UNIT_TEST_ERROR_TEST_FAILED.
+
+ @param[in] ValueA Value to be compared for inequality (64-bit comparison).
+ @param[in] ValueB Value to be compared for inequality (64-bit comparison).
+**/
+#define UT_ASSERT_NOT_EQUAL(ValueA, ValueB) \
+ if(!UnitTestAssertNotEqual ((UINT64)(ValueA), (UINT64)(ValueB), __FUNCTION__, DEBUG_LINE_NUMBER, __FILE__, #ValueA, #ValueB)) { \
+ return UNIT_TEST_ERROR_TEST_FAILED; \
+ }
+
+/**
+ This macro uses the framework assertion logic to check whether an EFI_STATUS
+ value is !EFI_ERROR(). If the status is !EFI_ERROR(), execution continues.
+ Otherwise, the test case immediately returns UNIT_TEST_ERROR_TEST_FAILED.
+
+ @param[in] Status EFI_STATUS value to check.
+**/
+#define UT_ASSERT_NOT_EFI_ERROR(Status) \
+ if(!UnitTestAssertNotEfiError ((Status), __FUNCTION__, DEBUG_LINE_NUMBER, __FILE__, #Status)) { \
+ return UNIT_TEST_ERROR_TEST_FAILED; \
+ }
+
+/**
+ This macro uses the framework assertion logic to check whether two EFI_STATUS
+ values are equal. If the values are equal, execution continues.
+ Otherwise, the test case immediately returns UNIT_TEST_ERROR_TEST_FAILED.
+
+ @param[in] Status EFI_STATUS values to compare for equality.
+ @param[in] Expected EFI_STATUS values to compare for equality.
+**/
+#define UT_ASSERT_STATUS_EQUAL(Status, Expected) \
+ if(!UnitTestAssertStatusEqual ((Status), (Expected), __FUNCTION__, DEBUG_LINE_NUMBER, __FILE__, #Status)) { \
+ return UNIT_TEST_ERROR_TEST_FAILED; \
+ }
+
+/**
+ This macro uses the framework assertion logic to check whether a pointer is
+ not NULL. If the pointer is not NULL, execution continues. Otherwise, the
+ test case immediately returns UNIT_TEST_ERROR_TEST_FAILED.
+
+ @param[in] Pointer Pointer to be checked against NULL.
+**/
+#define UT_ASSERT_NOT_NULL(Pointer) \
+ if(!UnitTestAssertNotNull ((Pointer), __FUNCTION__, DEBUG_LINE_NUMBER, __FILE__, #Pointer)) { \
+ return UNIT_TEST_ERROR_TEST_FAILED; \
+ }
+
+/**
+ This macro uses the framework assertion logic to check whether a function call
+ triggers an ASSERT() condition. The BaseLib SetJump()/LongJump() services
+ are used to establish a safe return point when an ASSERT() is triggered.
+ If an ASSERT() is triggered, unit test execution continues and Status is set
+ to UNIT_TEST_PASSED. Otherwise, a unit test case failure is raised and
+ Status is set to UNIT_TEST_ERROR_TEST_FAILED.
+
+ If ASSERT() macros are disabled, then the test case is skipped and a warning
+ message is added to the unit test log. Status is set to UNIT_TEST_SKIPPED.
+
+ @param[in] FunctionCall Function call that is expected to trigger ASSERT().
+ @param[out] Status Pointer to a UNIT_TEST_STATUS return value. This
+ is an optional parameter that may be NULL.
+**/
+#if defined (EDKII_UNIT_TEST_FRAMEWORK_ENABLED)
+ #include
+
+///
+/// Pointer to jump buffer used with SetJump()/LongJump() to test if a
+/// function under test generates an expected ASSERT() condition.
+///
+extern BASE_LIBRARY_JUMP_BUFFER *gUnitTestExpectAssertFailureJumpBuffer;
+
+#define UT_EXPECT_ASSERT_FAILURE(FunctionCall, Status) \
+ do { \
+ UNIT_TEST_STATUS UnitTestJumpStatus; \
+ BASE_LIBRARY_JUMP_BUFFER UnitTestJumpBuffer; \
+ UnitTestJumpStatus = UNIT_TEST_SKIPPED; \
+ if (DebugAssertEnabled ()) { \
+ gUnitTestExpectAssertFailureJumpBuffer = &UnitTestJumpBuffer; \
+ if (SetJump (gUnitTestExpectAssertFailureJumpBuffer) == 0) { \
+ FunctionCall; \
+ UnitTestJumpStatus = UNIT_TEST_ERROR_TEST_FAILED; \
+ } else { \
+ UnitTestJumpStatus = UNIT_TEST_PASSED; \
+ } \
+ gUnitTestExpectAssertFailureJumpBuffer = NULL; \
+ } \
+ if (!UnitTestExpectAssertFailure ( \
+ UnitTestJumpStatus, \
+ __FUNCTION__, DEBUG_LINE_NUMBER, __FILE__, \
+ #FunctionCall, Status)) { \
+ return UNIT_TEST_ERROR_TEST_FAILED; \
+ } \
+ } while (FALSE)
+#else
+#define UT_EXPECT_ASSERT_FAILURE(FunctionCall, Status) FunctionCall;
+#endif
+
+/**
+ If Expression is TRUE, then TRUE is returned.
+ If Expression is FALSE, then an assert is triggered and the location of the
+ assert provided by FunctionName, LineNumber, FileName, and Description are
+ recorded and FALSE is returned.
+
+ @param[in] Expression The BOOLEAN result of the expression evaluation.
+ @param[in] FunctionName Null-terminated ASCII string of the function
+ executing the assert macro.
+ @param[in] LineNumber The source file line number of the assert macro.
+ @param[in] FileName Null-terminated ASCII string of the filename
+ executing the assert macro.
+ @param[in] Description Null-terminated ASCII string of the expression being
+ evaluated.
+
+ @retval TRUE Expression is TRUE.
+ @retval FALSE Expression is FALSE.
+**/
+BOOLEAN
+EFIAPI
+UnitTestAssertTrue (
+ IN BOOLEAN Expression,
+ IN CONST CHAR8 *FunctionName,
+ IN UINTN LineNumber,
+ IN CONST CHAR8 *FileName,
+ IN CONST CHAR8 *Description
+ );
+
+/**
+ If Expression is FALSE, then TRUE is returned.
+ If Expression is TRUE, then an assert is triggered and the location of the
+ assert provided by FunctionName, LineNumber, FileName, and Description are
+ recorded and FALSE is returned.
+
+ @param[in] Expression The BOOLEAN result of the expression evaluation.
+ @param[in] FunctionName Null-terminated ASCII string of the function
+ executing the assert macro.
+ @param[in] LineNumber The source file line number of the assert macro.
+ @param[in] FileName Null-terminated ASCII string of the filename
+ executing the assert macro.
+ @param[in] Description Null-terminated ASCII string of the expression being
+ evaluated.
+
+ @retval TRUE Expression is FALSE.
+ @retval FALSE Expression is TRUE.
+**/
+BOOLEAN
+EFIAPI
+UnitTestAssertFalse (
+ IN BOOLEAN Expression,
+ IN CONST CHAR8 *FunctionName,
+ IN UINTN LineNumber,
+ IN CONST CHAR8 *FileName,
+ IN CONST CHAR8 *Description
+ );
+
+/**
+ If Status is not an EFI_ERROR(), then TRUE is returned.
+ If Status is an EFI_ERROR(), then an assert is triggered and the location of
+ the assert provided by FunctionName, LineNumber, FileName, and Description are
+ recorded and FALSE is returned.
+
+ @param[in] Status The EFI_STATUS value to evaluate.
+ @param[in] FunctionName Null-terminated ASCII string of the function
+ executing the assert macro.
+ @param[in] LineNumber The source file line number of the assert macro.
+ @param[in] FileName Null-terminated ASCII string of the filename
+ executing the assert macro.
+ @param[in] Description Null-terminated ASCII string of the status
+ expression being evaluated.
+
+ @retval TRUE Status is not an EFI_ERROR().
+ @retval FALSE Status is an EFI_ERROR().
+**/
+BOOLEAN
+EFIAPI
+UnitTestAssertNotEfiError (
+ IN EFI_STATUS Status,
+ IN CONST CHAR8 *FunctionName,
+ IN UINTN LineNumber,
+ IN CONST CHAR8 *FileName,
+ IN CONST CHAR8 *Description
+ );
+
+/**
+ If ValueA is equal ValueB, then TRUE is returned.
+ If ValueA is not equal to ValueB, then an assert is triggered and the location
+ of the assert provided by FunctionName, LineNumber, FileName, DescriptionA,
+ and DescriptionB are recorded and FALSE is returned.
+
+ @param[in] ValueA 64-bit value.
+ @param[in] ValueB 64-bit value.
+ @param[in] FunctionName Null-terminated ASCII string of the function
+ executing the assert macro.
+ @param[in] LineNumber The source file line number of the assert macro.
+ @param[in] FileName Null-terminated ASCII string of the filename
+ executing the assert macro.
+ @param[in] DescriptionA Null-terminated ASCII string that is a description
+ of ValueA.
+ @param[in] DescriptionB Null-terminated ASCII string that is a description
+ of ValueB.
+
+ @retval TRUE ValueA is equal to ValueB.
+ @retval FALSE ValueA is not equal to ValueB.
+**/
+BOOLEAN
+EFIAPI
+UnitTestAssertEqual (
+ IN UINT64 ValueA,
+ IN UINT64 ValueB,
+ IN CONST CHAR8 *FunctionName,
+ IN UINTN LineNumber,
+ IN CONST CHAR8 *FileName,
+ IN CONST CHAR8 *DescriptionA,
+ IN CONST CHAR8 *DescriptionB
+ );
+
+/**
+ If the contents of BufferA are identical to the contents of BufferB, then TRUE
+ is returned. If the contents of BufferA are not identical to the contents of
+ BufferB, then an assert is triggered and the location of the assert provided
+ by FunctionName, LineNumber, FileName, DescriptionA, and DescriptionB are
+ recorded and FALSE is returned.
+
+ @param[in] BufferA Pointer to a buffer for comparison.
+ @param[in] BufferB Pointer to a buffer for comparison.
+ @param[in] Length Number of bytes to compare in BufferA and BufferB.
+ @param[in] FunctionName Null-terminated ASCII string of the function
+ executing the assert macro.
+ @param[in] LineNumber The source file line number of the assert macro.
+ @param[in] FileName Null-terminated ASCII string of the filename
+ executing the assert macro.
+ @param[in] DescriptionA Null-terminated ASCII string that is a description
+ of BufferA.
+ @param[in] DescriptionB Null-terminated ASCII string that is a description
+ of BufferB.
+
+ @retval TRUE The contents of BufferA are identical to the contents of
+ BufferB.
+ @retval FALSE The contents of BufferA are not identical to the contents of
+ BufferB.
+**/
+BOOLEAN
+EFIAPI
+UnitTestAssertMemEqual (
+ IN VOID *BufferA,
+ IN VOID *BufferB,
+ IN UINTN Length,
+ IN CONST CHAR8 *FunctionName,
+ IN UINTN LineNumber,
+ IN CONST CHAR8 *FileName,
+ IN CONST CHAR8 *DescriptionA,
+ IN CONST CHAR8 *DescriptionB
+ );
+
+/**
+ If ValueA is not equal ValueB, then TRUE is returned.
+ If ValueA is equal to ValueB, then an assert is triggered and the location
+ of the assert provided by FunctionName, LineNumber, FileName, DescriptionA
+ and DescriptionB are recorded and FALSE is returned.
+
+ @param[in] ValueA 64-bit value.
+ @param[in] ValueB 64-bit value.
+ @param[in] FunctionName Null-terminated ASCII string of the function
+ executing the assert macro.
+ @param[in] LineNumber The source file line number of the assert macro.
+ @param[in] FileName Null-terminated ASCII string of the filename
+ executing the assert macro.
+ @param[in] DescriptionA Null-terminated ASCII string that is a description
+ of ValueA.
+ @param[in] DescriptionB Null-terminated ASCII string that is a description
+ of ValueB.
+
+ @retval TRUE ValueA is not equal to ValueB.
+ @retval FALSE ValueA is equal to ValueB.
+**/
+BOOLEAN
+EFIAPI
+UnitTestAssertNotEqual (
+ IN UINT64 ValueA,
+ IN UINT64 ValueB,
+ IN CONST CHAR8 *FunctionName,
+ IN UINTN LineNumber,
+ IN CONST CHAR8 *FileName,
+ IN CONST CHAR8 *DescriptionA,
+ IN CONST CHAR8 *DescriptionB
+ );
+
+/**
+ If Status is equal to Expected, then TRUE is returned.
+ If Status is not equal to Expected, then an assert is triggered and the
+ location of the assert provided by FunctionName, LineNumber, FileName, and
+ Description are recorded and FALSE is returned.
+
+ @param[in] Status EFI_STATUS value returned from an API under test.
+ @param[in] Expected The expected EFI_STATUS return value from an API
+ under test.
+ @param[in] FunctionName Null-terminated ASCII string of the function
+ executing the assert macro.
+ @param[in] LineNumber The source file line number of the assert macro.
+ @param[in] FileName Null-terminated ASCII string of the filename
+ executing the assert macro.
+ @param[in] Description Null-terminated ASCII string that is a description
+ of Status.
+
+ @retval TRUE Status is equal to Expected.
+ @retval FALSE Status is not equal to Expected.
+**/
+BOOLEAN
+EFIAPI
+UnitTestAssertStatusEqual (
+ IN EFI_STATUS Status,
+ IN EFI_STATUS Expected,
+ IN CONST CHAR8 *FunctionName,
+ IN UINTN LineNumber,
+ IN CONST CHAR8 *FileName,
+ IN CONST CHAR8 *Description
+ );
+
+/**
+ If Pointer is not equal to NULL, then TRUE is returned.
+ If Pointer is equal to NULL, then an assert is triggered and the location of
+ the assert provided by FunctionName, LineNumber, FileName, and PointerName
+ are recorded and FALSE is returned.
+
+ @param[in] Pointer Pointer value to be checked against NULL.
+ @param[in] Expected The expected EFI_STATUS return value from a function
+ under test.
+ @param[in] FunctionName Null-terminated ASCII string of the function
+ executing the assert macro.
+ @param[in] LineNumber The source file line number of the assert macro.
+ @param[in] FileName Null-terminated ASCII string of the filename
+ executing the assert macro.
+ @param[in] PointerName Null-terminated ASCII string that is a description
+ of Pointer.
+
+ @retval TRUE Pointer is not equal to NULL.
+ @retval FALSE Pointer is equal to NULL.
+**/
+BOOLEAN
+EFIAPI
+UnitTestAssertNotNull (
+ IN VOID *Pointer,
+ IN CONST CHAR8 *FunctionName,
+ IN UINTN LineNumber,
+ IN CONST CHAR8 *FileName,
+ IN CONST CHAR8 *PointerName
+ );
+
+/**
+ If UnitTestStatus is UNIT_TEST_PASSED, then log an info message and return
+ TRUE because an ASSERT() was expected when FunctionCall was executed and an
+ ASSERT() was triggered. If UnitTestStatus is UNIT_TEST_SKIPPED, then log a
+ warning message and return TRUE because ASSERT() macros are disabled. If
+ UnitTestStatus is UNIT_TEST_ERROR_TEST_FAILED, then log an error message and
+ return FALSE because an ASSERT() was expected when FunctionCall was executed,
+ but no ASSERT() conditions were triggered. The log messages contain
+ FunctionName, LineNumber, and FileName strings to provide the location of the
+ UT_EXPECT_ASSERT_FAILURE() macro.
+
+ @param[in] UnitTestStatus The status from UT_EXPECT_ASSERT_FAILURE() that
+ is either pass, skipped, or failed.
+ @param[in] FunctionName Null-terminated ASCII string of the function
+ executing the UT_EXPECT_ASSERT_FAILURE() macro.
+ @param[in] LineNumber The source file line number of the the function
+ executing the UT_EXPECT_ASSERT_FAILURE() macro.
+ @param[in] FileName Null-terminated ASCII string of the filename
+ executing the UT_EXPECT_ASSERT_FAILURE() macro.
+ @param[in] FunctionCall Null-terminated ASCII string of the function call
+ executed by the UT_EXPECT_ASSERT_FAILURE() macro.
+ @param[out] ResultStatus Used to return the UnitTestStatus value to the
+ caller of UT_EXPECT_ASSERT_FAILURE(). This is
+ optional parameter that may be NULL.
+
+ @retval TRUE UnitTestStatus is UNIT_TEST_PASSED.
+ @retval TRUE UnitTestStatus is UNIT_TEST_SKIPPED.
+ @retval FALSE UnitTestStatus is UNIT_TEST_ERROR_TEST_FAILED.
+**/
+BOOLEAN
+EFIAPI
+UnitTestExpectAssertFailure (
+ IN UNIT_TEST_STATUS UnitTestStatus,
+ IN CONST CHAR8 *FunctionName,
+ IN UINTN LineNumber,
+ IN CONST CHAR8 *FileName,
+ IN CONST CHAR8 *FunctionCall,
+ OUT UNIT_TEST_STATUS *ResultStatus OPTIONAL
+ );
+
+/**
+ Test logging macro that records an ERROR message in the test framework log.
+ Record is associated with the currently executing test case.
+
+ @param[in] Format Formatting string following the format defined in
+ MdePkg/Include/Library/PrintLib.h.
+ @param[in] ... Print args.
+**/
+#define UT_LOG_ERROR(Format, ...) \
+ UnitTestLog (UNIT_TEST_LOG_LEVEL_ERROR, Format, ##__VA_ARGS__)
+
+/**
+ Test logging macro that records a WARNING message in the test framework log.
+ Record is associated with the currently executing test case.
+
+ @param[in] Format Formatting string following the format defined in
+ MdePkg/Include/Library/PrintLib.h.
+ @param[in] ... Print args.
+**/
+#define UT_LOG_WARNING(Format, ...) \
+ UnitTestLog (UNIT_TEST_LOG_LEVEL_WARN, Format, ##__VA_ARGS__)
+
+/**
+ Test logging macro that records an INFO message in the test framework log.
+ Record is associated with the currently executing test case.
+
+ @param[in] Format Formatting string following the format defined in
+ MdePkg/Include/Library/PrintLib.h.
+ @param[in] ... Print args.
+**/
+#define UT_LOG_INFO(Format, ...) \
+ UnitTestLog (UNIT_TEST_LOG_LEVEL_INFO, Format, ##__VA_ARGS__)
+
+/**
+ Test logging macro that records a VERBOSE message in the test framework log.
+ Record is associated with the currently executing test case.
+
+ @param[in] Format Formatting string following the format defined in
+ MdePkg/Include/Library/PrintLib.h.
+ @param[in] ... Print args.
+**/
+#define UT_LOG_VERBOSE(Format, ...) \
+ UnitTestLog (UNIT_TEST_LOG_LEVEL_VERBOSE, Format, ##__VA_ARGS__)
+
+/**
+ Test logging function that records a messages in the test framework log.
+ Record is associated with the currently executing test case.
+
+ @param[in] ErrorLevel The error level of the unit test log message.
+ @param[in] Format Formatting string following the format defined in the
+ MdePkg/Include/Library/PrintLib.h.
+ @param[in] ... Print args.
+**/
+VOID
+EFIAPI
+UnitTestLog (
+ IN UINTN ErrorLevel,
+ IN CONST CHAR8 *Format,
+ ...
+ );
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/LoongArch64/ProcessorBind.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/LoongArch64/ProcessorBind.h
new file mode 100644
index 0000000000..fa40264e51
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/LoongArch64/ProcessorBind.h
@@ -0,0 +1,120 @@
+/** @file
+ Processor or Compiler specific defines and types for LoongArch
+
+ Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef PROCESSOR_BIND_H_
+#define PROCESSOR_BIND_H_
+
+//
+// Define the processor type so other code can make processor based choices
+//
+#define MDE_CPU_LOONGARCH64
+
+#define EFIAPI
+
+//
+// Make sure we are using the correct packing rules per EFI specification
+//
+#ifndef __GNUC__
+ #pragma pack()
+#endif
+
+//
+// Assume standard LoongArch 64-bit alignment.
+// Need to check portability of long long
+//
+typedef unsigned long long UINT64;
+typedef long long INT64;
+typedef unsigned int UINT32;
+typedef int INT32;
+typedef unsigned short UINT16;
+typedef unsigned short CHAR16;
+typedef short INT16;
+typedef unsigned char BOOLEAN;
+typedef unsigned char UINT8;
+typedef char CHAR8;
+typedef char INT8;
+
+//
+// Unsigned value of native width. (4 bytes on supported 32-bit processor instructions,
+// 8 bytes on supported 64-bit processor instructions)
+//
+
+typedef UINT64 UINTN;
+
+//
+// Signed value of native width. (4 bytes on supported 32-bit processor instructions,
+// 8 bytes on supported 64-bit processor instructions)
+//
+typedef INT64 INTN;
+
+//
+// Processor specific defines
+//
+
+//
+// A value of native width with the highest bit set.
+//
+#define MAX_BIT 0x8000000000000000ULL
+//
+// A value of native width with the two highest bits set.
+//
+#define MAX_2_BITS 0xC000000000000000ULL
+
+//
+// Maximum legal LoongArch 64-bit address
+//
+#define MAX_ADDRESS 0xFFFFFFFFFFFFFFFFULL
+
+//
+// Maximum usable address at boot time (48 bits using 4KB pages)
+//
+#define MAX_ALLOC_ADDRESS 0xFFFFFFFFFFFFULL
+
+//
+// Maximum legal LoongArch 64-bit INTN and UINTN values.
+//
+#define MAX_INTN ((INTN)0x7FFFFFFFFFFFFFFFULL)
+#define MAX_UINTN ((UINTN)0xFFFFFFFFFFFFFFFFULL)
+
+//
+// Page allocation granularity for LoongArch
+//
+#define DEFAULT_PAGE_ALLOCATION_GRANULARITY (0x1000)
+#define RUNTIME_PAGE_ALLOCATION_GRANULARITY (0x10000)
+
+#if defined (__GNUC__)
+//
+// For GNU assembly code, .global or .globl can declare global symbols.
+// Define this macro to unify the usage.
+//
+#define ASM_GLOBAL .globl
+#endif
+
+//
+// The stack alignment required for LoongArch
+//
+#define CPU_STACK_ALIGNMENT 16
+
+/**
+ Return the pointer to the first instruction of a function given a function pointer.
+ On LOONGARCH CPU architectures, these two pointer values are the same,
+ so the implementation of this macro is very simple.
+
+ @param FunctionPointer A pointer to a function.
+
+ @return The pointer to the first instruction of a function given a function pointer.
+
+**/
+#define FUNCTION_ENTRY_POINT(FunctionPointer) (VOID *)(UINTN)(FunctionPointer)
+
+#ifndef __USER_LABEL_PREFIX__
+#define __USER_LABEL_PREFIX__
+#endif
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Pi/PiBootMode.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Pi/PiBootMode.h
new file mode 100644
index 0000000000..59a0557f88
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Pi/PiBootMode.h
@@ -0,0 +1,36 @@
+/** @file
+ Present the boot mode values in PI.
+
+ Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Revision Reference:
+ PI Version 1.2.1A
+
+**/
+
+#ifndef __PI_BOOT_MODE_H__
+#define __PI_BOOT_MODE_H__
+
+///
+/// EFI boot mode
+///
+typedef UINT32 EFI_BOOT_MODE;
+
+//
+// 0x21 - 0xf..f are reserved.
+//
+#define BOOT_WITH_FULL_CONFIGURATION 0x00
+#define BOOT_WITH_MINIMAL_CONFIGURATION 0x01
+#define BOOT_ASSUMING_NO_CONFIGURATION_CHANGES 0x02
+#define BOOT_WITH_FULL_CONFIGURATION_PLUS_DIAGNOSTICS 0x03
+#define BOOT_WITH_DEFAULT_SETTINGS 0x04
+#define BOOT_ON_S4_RESUME 0x05
+#define BOOT_ON_S5_RESUME 0x06
+#define BOOT_WITH_MFG_MODE_SETTINGS 0x07
+#define BOOT_ON_S2_RESUME 0x10
+#define BOOT_ON_S3_RESUME 0x11
+#define BOOT_ON_FLASH_UPDATE 0x12
+#define BOOT_IN_RECOVERY_MODE 0x20
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Pi/PiDependency.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Pi/PiDependency.h
new file mode 100644
index 0000000000..8e6f53c582
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Pi/PiDependency.h
@@ -0,0 +1,41 @@
+/** @file
+ Present the dependency expression values in PI.
+
+ Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Revision Reference:
+ PI Version 1.0
+
+**/
+
+#ifndef __PI_DEPENDENCY_H__
+#define __PI_DEPENDENCY_H__
+
+///
+/// If present, this must be the first and only opcode,
+/// EFI_DEP_BEFORE may be used by DXE and SMM drivers.
+///
+#define EFI_DEP_BEFORE 0x00
+
+///
+/// If present, this must be the first and only opcode,
+/// EFI_DEP_AFTER may be used by DXE and SMM drivers.
+///
+#define EFI_DEP_AFTER 0x01
+
+#define EFI_DEP_PUSH 0x02
+#define EFI_DEP_AND 0x03
+#define EFI_DEP_OR 0x04
+#define EFI_DEP_NOT 0x05
+#define EFI_DEP_TRUE 0x06
+#define EFI_DEP_FALSE 0x07
+#define EFI_DEP_END 0x08
+
+///
+/// If present, this must be the first opcode,
+/// EFI_DEP_SOR is only used by DXE driver.
+///
+#define EFI_DEP_SOR 0x09
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Pi/PiDxeCis.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Pi/PiDxeCis.h
new file mode 100644
index 0000000000..5c8ece2142
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Pi/PiDxeCis.h
@@ -0,0 +1,743 @@
+/** @file
+ Include file matches things in PI.
+
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Revision Reference:
+ PI Version 1.7
+
+**/
+
+#ifndef __PI_DXECIS_H__
+#define __PI_DXECIS_H__
+
+#include
+#include
+
+///
+/// Global Coherencey Domain types - Memory type.
+///
+typedef enum {
+ ///
+ /// A memory region that is visible to the boot processor. However, there are no system
+ /// components that are currently decoding this memory region.
+ ///
+ EfiGcdMemoryTypeNonExistent,
+ ///
+ /// A memory region that is visible to the boot processor. This memory region is being
+ /// decoded by a system component, but the memory region is not considered to be either
+ /// system memory or memory-mapped I/O.
+ ///
+ EfiGcdMemoryTypeReserved,
+ ///
+ /// A memory region that is visible to the boot processor. A memory controller is
+ /// currently decoding this memory region and the memory controller is producing a
+ /// tested system memory region that is available to the memory services.
+ ///
+ EfiGcdMemoryTypeSystemMemory,
+ ///
+ /// A memory region that is visible to the boot processor. This memory region is
+ /// currently being decoded by a component as memory-mapped I/O that can be used to
+ /// access I/O devices in the platform.
+ ///
+ EfiGcdMemoryTypeMemoryMappedIo,
+ ///
+ /// A memory region that is visible to the boot processor.
+ /// This memory supports byte-addressable non-volatility.
+ ///
+ EfiGcdMemoryTypePersistent,
+ //
+ // Keep original one for the compatibility.
+ //
+ EfiGcdMemoryTypePersistentMemory = EfiGcdMemoryTypePersistent,
+ ///
+ /// A memory region that provides higher reliability relative to other memory in the
+ /// system. If all memory has the same reliability, then this bit is not used.
+ ///
+ EfiGcdMemoryTypeMoreReliable,
+ // ///
+ // /// A memory region that describes system memory that has not been accepted
+ // /// by a corresponding call to the underlying isolation architecture.
+ // ///
+ // /// Please be noted:
+ // /// EfiGcdMemoryTypeUnaccepted is defined in PrePiDxeCis.h because it has not been
+ // /// defined in PI spec.
+ // EfiGcdMemoryTypeUnaccepted,
+ EfiGcdMemoryTypeMaximum = 7
+} EFI_GCD_MEMORY_TYPE;
+
+///
+/// Global Coherencey Domain types - IO type.
+///
+typedef enum {
+ ///
+ /// An I/O region that is visible to the boot processor. However, there are no system
+ /// components that are currently decoding this I/O region.
+ ///
+ EfiGcdIoTypeNonExistent,
+ ///
+ /// An I/O region that is visible to the boot processor. This I/O region is currently being
+ /// decoded by a system component, but the I/O region cannot be used to access I/O devices.
+ ///
+ EfiGcdIoTypeReserved,
+ ///
+ /// An I/O region that is visible to the boot processor. This I/O region is currently being
+ /// decoded by a system component that is producing I/O ports that can be used to access I/O devices.
+ ///
+ EfiGcdIoTypeIo,
+ EfiGcdIoTypeMaximum
+} EFI_GCD_IO_TYPE;
+
+///
+/// The type of allocation to perform.
+///
+typedef enum {
+ ///
+ /// The GCD memory space map is searched from the lowest address up to the highest address
+ /// looking for unallocated memory ranges.
+ ///
+ EfiGcdAllocateAnySearchBottomUp,
+ ///
+ /// The GCD memory space map is searched from the lowest address up
+ /// to the specified MaxAddress looking for unallocated memory ranges.
+ ///
+ EfiGcdAllocateMaxAddressSearchBottomUp,
+ ///
+ /// The GCD memory space map is checked to see if the memory range starting
+ /// at the specified Address is available.
+ ///
+ EfiGcdAllocateAddress,
+ ///
+ /// The GCD memory space map is searched from the highest address down to the lowest address
+ /// looking for unallocated memory ranges.
+ ///
+ EfiGcdAllocateAnySearchTopDown,
+ ///
+ /// The GCD memory space map is searched from the specified MaxAddress
+ /// down to the lowest address looking for unallocated memory ranges.
+ ///
+ EfiGcdAllocateMaxAddressSearchTopDown,
+ EfiGcdMaxAllocateType
+} EFI_GCD_ALLOCATE_TYPE;
+
+///
+/// EFI_GCD_MEMORY_SPACE_DESCRIPTOR.
+///
+typedef struct {
+ ///
+ /// The physical address of the first byte in the memory region. Type
+ /// EFI_PHYSICAL_ADDRESS is defined in the AllocatePages() function
+ /// description in the UEFI 2.0 specification.
+ ///
+ EFI_PHYSICAL_ADDRESS BaseAddress;
+
+ ///
+ /// The number of bytes in the memory region.
+ ///
+ UINT64 Length;
+
+ ///
+ /// The bit mask of attributes that the memory region is capable of supporting. The bit
+ /// mask of available attributes is defined in the GetMemoryMap() function description
+ /// in the UEFI 2.0 specification.
+ ///
+ UINT64 Capabilities;
+ ///
+ /// The bit mask of attributes that the memory region is currently using. The bit mask of
+ /// available attributes is defined in GetMemoryMap().
+ ///
+ UINT64 Attributes;
+ ///
+ /// Type of the memory region. Type EFI_GCD_MEMORY_TYPE is defined in the
+ /// AddMemorySpace() function description.
+ ///
+ EFI_GCD_MEMORY_TYPE GcdMemoryType;
+
+ ///
+ /// The image handle of the agent that allocated the memory resource described by
+ /// PhysicalStart and NumberOfBytes. If this field is NULL, then the memory
+ /// resource is not currently allocated. Type EFI_HANDLE is defined in
+ /// InstallProtocolInterface() in the UEFI 2.0 specification.
+ ///
+ EFI_HANDLE ImageHandle;
+
+ ///
+ /// The device handle for which the memory resource has been allocated. If
+ /// ImageHandle is NULL, then the memory resource is not currently allocated. If this
+ /// field is NULL, then the memory resource is not associated with a device that is
+ /// described by a device handle. Type EFI_HANDLE is defined in
+ /// InstallProtocolInterface() in the UEFI 2.0 specification.
+ ///
+ EFI_HANDLE DeviceHandle;
+} EFI_GCD_MEMORY_SPACE_DESCRIPTOR;
+
+///
+/// EFI_GCD_IO_SPACE_DESCRIPTOR.
+///
+typedef struct {
+ ///
+ /// Physical address of the first byte in the I/O region. Type
+ /// EFI_PHYSICAL_ADDRESS is defined in the AllocatePages() function
+ /// description in the UEFI 2.0 specification.
+ ///
+ EFI_PHYSICAL_ADDRESS BaseAddress;
+
+ ///
+ /// Number of bytes in the I/O region.
+ ///
+ UINT64 Length;
+
+ ///
+ /// Type of the I/O region. Type EFI_GCD_IO_TYPE is defined in the
+ /// AddIoSpace() function description.
+ ///
+ EFI_GCD_IO_TYPE GcdIoType;
+
+ ///
+ /// The image handle of the agent that allocated the I/O resource described by
+ /// PhysicalStart and NumberOfBytes. If this field is NULL, then the I/O
+ /// resource is not currently allocated. Type EFI_HANDLE is defined in
+ /// InstallProtocolInterface() in the UEFI 2.0 specification.
+ ///
+ EFI_HANDLE ImageHandle;
+
+ ///
+ /// The device handle for which the I/O resource has been allocated. If ImageHandle
+ /// is NULL, then the I/O resource is not currently allocated. If this field is NULL, then
+ /// the I/O resource is not associated with a device that is described by a device handle.
+ /// Type EFI_HANDLE is defined in InstallProtocolInterface() in the UEFI
+ /// 2.0 specification.
+ ///
+ EFI_HANDLE DeviceHandle;
+} EFI_GCD_IO_SPACE_DESCRIPTOR;
+
+/**
+ Adds reserved memory, system memory, or memory-mapped I/O resources to the
+ global coherency domain of the processor.
+
+ @param GcdMemoryType The type of memory resource being added.
+ @param BaseAddress The physical address that is the start address
+ of the memory resource being added.
+ @param Length The size, in bytes, of the memory resource that
+ is being added.
+ @param Capabilities The bit mask of attributes that the memory
+ resource region supports.
+
+ @retval EFI_SUCCESS The memory resource was added to the global
+ coherency domain of the processor.
+ @retval EFI_INVALID_PARAMETER GcdMemoryType is invalid.
+ @retval EFI_INVALID_PARAMETER Length is zero.
+ @retval EFI_OUT_OF_RESOURCES There are not enough system resources to add
+ the memory resource to the global coherency
+ domain of the processor.
+ @retval EFI_UNSUPPORTED The processor does not support one or more bytes
+ of the memory resource range specified by
+ BaseAddress and Length.
+ @retval EFI_ACCESS_DENIED One or more bytes of the memory resource range
+ specified by BaseAddress and Length conflicts
+ with a memory resource range that was previously
+ added to the global coherency domain of the processor.
+ @retval EFI_ACCESS_DENIED One or more bytes of the memory resource range
+ specified by BaseAddress and Length was allocated
+ in a prior call to AllocateMemorySpace().
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_ADD_MEMORY_SPACE)(
+ IN EFI_GCD_MEMORY_TYPE GcdMemoryType,
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,
+ IN UINT64 Length,
+ IN UINT64 Capabilities
+ );
+
+/**
+ Allocates nonexistent memory, reserved memory, system memory, or memorymapped
+ I/O resources from the global coherency domain of the processor.
+
+ @param GcdAllocateType The type of allocation to perform.
+ @param GcdMemoryType The type of memory resource being allocated.
+ @param Alignment The log base 2 of the boundary that BaseAddress must
+ be aligned on output. Align with 2^Alignment.
+ @param Length The size in bytes of the memory resource range that
+ is being allocated.
+ @param BaseAddress A pointer to a physical address to allocate.
+ @param Imagehandle The image handle of the agent that is allocating
+ the memory resource.
+ @param DeviceHandle The device handle for which the memory resource
+ is being allocated.
+
+ @retval EFI_INVALID_PARAMETER GcdAllocateType is invalid.
+ @retval EFI_INVALID_PARAMETER GcdMemoryType is invalid.
+ @retval EFI_INVALID_PARAMETER Length is zero.
+ @retval EFI_INVALID_PARAMETER BaseAddress is NULL.
+ @retval EFI_INVALID_PARAMETER ImageHandle is NULL.
+ @retval EFI_NOT_FOUND The memory resource request could not be satisfied.
+ No descriptor contains the desired space.
+ @retval EFI_OUT_OF_RESOURCES There are not enough system resources to allocate the memory
+ resource from the global coherency domain of the processor.
+ @retval EFI_SUCCESS The memory resource was allocated from the global coherency
+ domain of the processor.
+
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_ALLOCATE_MEMORY_SPACE)(
+ IN EFI_GCD_ALLOCATE_TYPE GcdAllocateType,
+ IN EFI_GCD_MEMORY_TYPE GcdMemoryType,
+ IN UINTN Alignment,
+ IN UINT64 Length,
+ IN OUT EFI_PHYSICAL_ADDRESS *BaseAddress,
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_HANDLE DeviceHandle OPTIONAL
+ );
+
+/**
+ Frees nonexistent memory, reserved memory, system memory, or memory-mapped
+ I/O resources from the global coherency domain of the processor.
+
+ @param BaseAddress The physical address that is the start address of the memory resource being freed.
+ @param Length The size in bytes of the memory resource range that is being freed.
+
+ @retval EFI_SUCCESS The memory resource was freed from the global coherency domain of
+ the processor.
+ @retval EFI_INVALID_PARAMETER Length is zero.
+ @retval EFI_UNSUPPORTED The processor does not support one or more bytes of the memory
+ resource range specified by BaseAddress and Length.
+ @retval EFI_NOT_FOUND The memory resource range specified by BaseAddress and
+ Length was not allocated with previous calls to AllocateMemorySpace().
+ @retval EFI_OUT_OF_RESOURCES There are not enough system resources to free the memory resource
+ from the global coherency domain of the processor.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_FREE_MEMORY_SPACE)(
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,
+ IN UINT64 Length
+ );
+
+/**
+ Removes reserved memory, system memory, or memory-mapped I/O resources from
+ the global coherency domain of the processor.
+
+ @param BaseAddress The physical address that is the start address of the memory resource being removed.
+ @param Length The size in bytes of the memory resource that is being removed.
+
+ @retval EFI_SUCCESS The memory resource was removed from the global coherency
+ domain of the processor.
+ @retval EFI_INVALID_PARAMETER Length is zero.
+ @retval EFI_UNSUPPORTED The processor does not support one or more bytes of the memory
+ resource range specified by BaseAddress and Length.
+ @retval EFI_NOT_FOUND One or more bytes of the memory resource range specified by
+ BaseAddress and Length was not added with previous calls to
+ AddMemorySpace().
+ @retval EFI_ACCESS_DEFINED One or more bytes of the memory resource range specified by
+ BaseAddress and Length has been allocated with AllocateMemorySpace().
+ @retval EFI_OUT_OF_RESOURCES There are not enough system resources to remove the memory
+ resource from the global coherency domain of the processor.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_REMOVE_MEMORY_SPACE)(
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,
+ IN UINT64 Length
+ );
+
+/**
+ Retrieves the descriptor for a memory region containing a specified address.
+
+ @param BaseAddress The physical address that is the start address of a memory region.
+ @param Descriptor A pointer to a caller allocated descriptor.
+
+ @retval EFI_SUCCESS The descriptor for the memory resource region containing
+ BaseAddress was returned in Descriptor.
+ @retval EFI_INVALID_PARAMETER Descriptor is NULL.
+ @retval EFI_NOT_FOUND A memory resource range containing BaseAddress was not found.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_GET_MEMORY_SPACE_DESCRIPTOR)(
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,
+ OUT EFI_GCD_MEMORY_SPACE_DESCRIPTOR *Descriptor
+ );
+
+/**
+ Modifies the attributes for a memory region in the global coherency domain of the
+ processor.
+
+ @param BaseAddress The physical address that is the start address of a memory region.
+ @param Length The size in bytes of the memory region.
+ @param Attributes The bit mask of attributes to set for the memory region.
+
+ @retval EFI_SUCCESS The attributes were set for the memory region.
+ @retval EFI_INVALID_PARAMETER Length is zero.
+ @retval EFI_UNSUPPORTED The processor does not support one or more bytes of the memory
+ resource range specified by BaseAddress and Length.
+ @retval EFI_UNSUPPORTED The bit mask of attributes is not support for the memory resource
+ range specified by BaseAddress and Length.
+ @retval EFI_ACCESS_DENIED The attributes for the memory resource range specified by
+ BaseAddress and Length cannot be modified.
+ @retval EFI_OUT_OF_RESOURCES There are not enough system resources to modify the attributes of
+ the memory resource range.
+ @retval EFI_NOT_AVAILABLE_YET The attributes cannot be set because CPU architectural protocol is
+ not available yet.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_SET_MEMORY_SPACE_ATTRIBUTES)(
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,
+ IN UINT64 Length,
+ IN UINT64 Attributes
+ );
+
+/**
+ Modifies the capabilities for a memory region in the global coherency domain of the
+ processor.
+
+ @param BaseAddress The physical address that is the start address of a memory region.
+ @param Length The size in bytes of the memory region.
+ @param Capabilities The bit mask of capabilities that the memory region supports.
+
+ @retval EFI_SUCCESS The capabilities were set for the memory region.
+ @retval EFI_INVALID_PARAMETER Length is zero.
+ @retval EFI_UNSUPPORTED The capabilities specified by Capabilities do not include the
+ memory region attributes currently in use.
+ @retval EFI_ACCESS_DENIED The capabilities for the memory resource range specified by
+ BaseAddress and Length cannot be modified.
+ @retval EFI_OUT_OF_RESOURCES There are not enough system resources to modify the capabilities
+ of the memory resource range.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_SET_MEMORY_SPACE_CAPABILITIES)(
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,
+ IN UINT64 Length,
+ IN UINT64 Capabilities
+ );
+
+/**
+ Returns a map of the memory resources in the global coherency domain of the
+ processor.
+
+ @param NumberOfDescriptors A pointer to number of descriptors returned in the MemorySpaceMap buffer.
+ @param MemorySpaceMap A pointer to the array of EFI_GCD_MEMORY_SPACE_DESCRIPTORs.
+
+ @retval EFI_SUCCESS The memory space map was returned in the MemorySpaceMap
+ buffer, and the number of descriptors in MemorySpaceMap was
+ returned in NumberOfDescriptors.
+ @retval EFI_INVALID_PARAMETER NumberOfDescriptors is NULL.
+ @retval EFI_INVALID_PARAMETER MemorySpaceMap is NULL.
+ @retval EFI_OUT_OF_RESOURCES There are not enough resources to allocate MemorySpaceMap.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_GET_MEMORY_SPACE_MAP)(
+ OUT UINTN *NumberOfDescriptors,
+ OUT EFI_GCD_MEMORY_SPACE_DESCRIPTOR **MemorySpaceMap
+ );
+
+/**
+ Adds reserved I/O or I/O resources to the global coherency domain of the processor.
+
+ @param GcdIoType The type of I/O resource being added.
+ @param BaseAddress The physical address that is the start address of the I/O resource being added.
+ @param Length The size in bytes of the I/O resource that is being added.
+
+ @retval EFI_SUCCESS The I/O resource was added to the global coherency domain of
+ the processor.
+ @retval EFI_INVALID_PARAMETER GcdIoType is invalid.
+ @retval EFI_INVALID_PARAMETER Length is zero.
+ @retval EFI_OUT_OF_RESOURCES There are not enough system resources to add the I/O resource to
+ the global coherency domain of the processor.
+ @retval EFI_UNSUPPORTED The processor does not support one or more bytes of the I/O
+ resource range specified by BaseAddress and Length.
+ @retval EFI_ACCESS_DENIED One or more bytes of the I/O resource range specified by
+ BaseAddress and Length conflicts with an I/O resource
+ range that was previously added to the global coherency domain
+ of the processor.
+ @retval EFI_ACCESS_DENIED One or more bytes of the I/O resource range specified by
+ BaseAddress and Length was allocated in a prior call to
+ AllocateIoSpace().
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_ADD_IO_SPACE)(
+ IN EFI_GCD_IO_TYPE GcdIoType,
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,
+ IN UINT64 Length
+ );
+
+/**
+ Allocates nonexistent I/O, reserved I/O, or I/O resources from the global coherency
+ domain of the processor.
+
+ @param GcdAllocateType The type of allocation to perform.
+ @param GcdIoType The type of I/O resource being allocated.
+ @param Alignment The log base 2 of the boundary that BaseAddress must be aligned on output.
+ @param Length The size in bytes of the I/O resource range that is being allocated.
+ @param BaseAddress A pointer to a physical address.
+ @param Imagehandle The image handle of the agent that is allocating the I/O resource.
+ @param DeviceHandle The device handle for which the I/O resource is being allocated.
+
+ @retval EFI_SUCCESS The I/O resource was allocated from the global coherency domain
+ of the processor.
+ @retval EFI_INVALID_PARAMETER GcdAllocateType is invalid.
+ @retval EFI_INVALID_PARAMETER GcdIoType is invalid.
+ @retval EFI_INVALID_PARAMETER Length is zero.
+ @retval EFI_INVALID_PARAMETER BaseAddress is NULL.
+ @retval EFI_INVALID_PARAMETER ImageHandle is NULL.
+ @retval EFI_OUT_OF_RESOURCES There are not enough system resources to allocate the I/O
+ resource from the global coherency domain of the processor.
+ @retval EFI_NOT_FOUND The I/O resource request could not be satisfied.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_ALLOCATE_IO_SPACE)(
+ IN EFI_GCD_ALLOCATE_TYPE GcdAllocateType,
+ IN EFI_GCD_IO_TYPE GcdIoType,
+ IN UINTN Alignment,
+ IN UINT64 Length,
+ IN OUT EFI_PHYSICAL_ADDRESS *BaseAddress,
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_HANDLE DeviceHandle OPTIONAL
+ );
+
+/**
+ Frees nonexistent I/O, reserved I/O, or I/O resources from the global coherency
+ domain of the processor.
+
+ @param BaseAddress The physical address that is the start address of the I/O resource being freed.
+ @param Length The size in bytes of the I/O resource range that is being freed.
+
+ @retval EFI_SUCCESS The I/O resource was freed from the global coherency domain of the
+ processor.
+ @retval EFI_INVALID_PARAMETER Length is zero.
+ @retval EFI_UNSUPPORTED The processor does not support one or more bytes of the I/O resource
+ range specified by BaseAddress and Length.
+ @retval EFI_NOT_FOUND The I/O resource range specified by BaseAddress and Length
+ was not allocated with previous calls to AllocateIoSpace().
+ @retval EFI_OUT_OF_RESOURCES There are not enough system resources to free the I/O resource from
+ the global coherency domain of the processor.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_FREE_IO_SPACE)(
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,
+ IN UINT64 Length
+ );
+
+/**
+ Removes reserved I/O or I/O resources from the global coherency domain of the
+ processor.
+
+ @param BaseAddress A pointer to a physical address that is the start address of the I/O resource being
+ removed.
+ @param Length The size in bytes of the I/O resource that is being removed.
+
+ @retval EFI_SUCCESS The I/O resource was removed from the global coherency domain
+ of the processor.
+ @retval EFI_INVALID_PARAMETER Length is zero.
+ @retval EFI_UNSUPPORTED The processor does not support one or more bytes of the I/O
+ resource range specified by BaseAddress and Length.
+ @retval EFI_NOT_FOUND One or more bytes of the I/O resource range specified by
+ BaseAddress and Length was not added with previous
+ calls to AddIoSpace().
+ @retval EFI_ACCESS_DENIED One or more bytes of the I/O resource range specified by
+ BaseAddress and Length has been allocated with
+ AllocateIoSpace().
+ @retval EFI_OUT_OF_RESOURCES There are not enough system resources to remove the I/O
+ resource from the global coherency domain of the processor.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_REMOVE_IO_SPACE)(
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,
+ IN UINT64 Length
+ );
+
+/**
+ Retrieves the descriptor for an I/O region containing a specified address.
+
+ @param BaseAddress The physical address that is the start address of an I/O region.
+ @param Descriptor A pointer to a caller allocated descriptor.
+
+ @retval EFI_SUCCESS The descriptor for the I/O resource region containing
+ BaseAddress was returned in Descriptor.
+ @retval EFI_INVALID_PARAMETER Descriptor is NULL.
+ @retval EFI_NOT_FOUND An I/O resource range containing BaseAddress was not found.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_GET_IO_SPACE_DESCRIPTOR)(
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,
+ OUT EFI_GCD_IO_SPACE_DESCRIPTOR *Descriptor
+ );
+
+/**
+ Returns a map of the I/O resources in the global coherency domain of the processor.
+
+ @param NumberOfDescriptors A pointer to number of descriptors returned in the IoSpaceMap buffer.
+ @param MemorySpaceMap A pointer to the array of EFI_GCD_IO_SPACE_DESCRIPTORs.
+
+ @retval EFI_SUCCESS The I/O space map was returned in the IoSpaceMap buffer, and
+ the number of descriptors in IoSpaceMap was returned in
+ NumberOfDescriptors.
+ @retval EFI_INVALID_PARAMETER NumberOfDescriptors is NULL.
+ @retval EFI_INVALID_PARAMETER IoSpaceMap is NULL.
+ @retval EFI_OUT_OF_RESOURCES There are not enough resources to allocate IoSpaceMap.
+
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_GET_IO_SPACE_MAP)(
+ OUT UINTN *NumberOfDescriptors,
+ OUT EFI_GCD_IO_SPACE_DESCRIPTOR **IoSpaceMap
+ );
+
+/**
+ Loads and executed DXE drivers from firmware volumes.
+
+ The Dispatch() function searches for DXE drivers in firmware volumes that have been
+ installed since the last time the Dispatch() service was called. It then evaluates
+ the dependency expressions of all the DXE drivers and loads and executes those DXE
+ drivers whose dependency expression evaluate to TRUE. This service must interact with
+ the Security Architectural Protocol to authenticate DXE drivers before they are executed.
+ This process is continued until no more DXE drivers can be executed.
+
+ @retval EFI_SUCCESS One or more DXE driver were dispatched.
+ @retval EFI_NOT_FOUND No DXE drivers were dispatched.
+ @retval EFI_ALREADY_STARTED An attempt is being made to start the DXE Dispatcher recursively.
+ Thus, no action was taken.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_DISPATCH)(
+ VOID
+ );
+
+/**
+ Clears the Schedule on Request (SOR) flag for a component that is stored in a firmware volume.
+
+ @param FirmwareVolumeHandle The handle of the firmware volume that contains the file specified by FileName.
+ @param FileName A pointer to the name of the file in a firmware volume.
+
+ @retval EFI_SUCCESS The DXE driver was found and its SOR bit was cleared.
+ @retval EFI_NOT_FOUND The DXE driver does not exist, or the DXE driver exists and its SOR
+ bit is not set.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_SCHEDULE)(
+ IN EFI_HANDLE FirmwareVolumeHandle,
+ IN CONST EFI_GUID *FileName
+ );
+
+/**
+ Promotes a file stored in a firmware volume from the untrusted to the trusted state.
+
+ @param FirmwareVolumeHandle The handle of the firmware volume that contains the file specified by FileName.
+ @param DriverName A pointer to the name of the file in a firmware volume.
+
+ @return Status of promoting FFS from untrusted to trusted
+ state.
+ @retval EFI_NOT_FOUND The file was not found in the untrusted state.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_TRUST)(
+ IN EFI_HANDLE FirmwareVolumeHandle,
+ IN CONST EFI_GUID *FileName
+ );
+
+/**
+ Creates a firmware volume handle for a firmware volume that is present in system memory.
+
+ @param FirmwareVolumeHeader A pointer to the header of the firmware volume.
+ @param Size The size, in bytes, of the firmware volume.
+ @param FirmwareVolumeHandle On output, a pointer to the created handle.
+
+ @retval EFI_SUCCESS The EFI_FIRMWARE_VOLUME_PROTOCOL and
+ EFI_DEVICE_PATH_PROTOCOL were installed onto
+ FirmwareVolumeHandle for the firmware volume described
+ by FirmwareVolumeHeader and Size.
+ @retval EFI_VOLUME_CORRUPTED The firmware volume described by FirmwareVolumeHeader
+ and Size is corrupted.
+ @retval EFI_OUT_OF_RESOURCES There are not enough system resources available to produce the
+ EFI_FIRMWARE_VOLUME_PROTOCOL and EFI_DEVICE_PATH_PROTOCOL
+ for the firmware volume described by FirmwareVolumeHeader and Size.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_PROCESS_FIRMWARE_VOLUME)(
+ IN CONST VOID *FirmwareVolumeHeader,
+ IN UINTN Size,
+ OUT EFI_HANDLE *FirmwareVolumeHandle
+ );
+
+//
+// DXE Services Table
+//
+#define DXE_SERVICES_SIGNATURE 0x565245535f455844ULL
+#define DXE_SPECIFICATION_MAJOR_REVISION 1
+#define DXE_SPECIFICATION_MINOR_REVISION 70
+#define DXE_SERVICES_REVISION ((DXE_SPECIFICATION_MAJOR_REVISION<<16) | (DXE_SPECIFICATION_MINOR_REVISION))
+
+typedef struct {
+ ///
+ /// The table header for the DXE Services Table.
+ /// This header contains the DXE_SERVICES_SIGNATURE and DXE_SERVICES_REVISION values.
+ ///
+ EFI_TABLE_HEADER Hdr;
+
+ //
+ // Global Coherency Domain Services
+ //
+ EFI_ADD_MEMORY_SPACE AddMemorySpace;
+ EFI_ALLOCATE_MEMORY_SPACE AllocateMemorySpace;
+ EFI_FREE_MEMORY_SPACE FreeMemorySpace;
+ EFI_REMOVE_MEMORY_SPACE RemoveMemorySpace;
+ EFI_GET_MEMORY_SPACE_DESCRIPTOR GetMemorySpaceDescriptor;
+ EFI_SET_MEMORY_SPACE_ATTRIBUTES SetMemorySpaceAttributes;
+ EFI_GET_MEMORY_SPACE_MAP GetMemorySpaceMap;
+ EFI_ADD_IO_SPACE AddIoSpace;
+ EFI_ALLOCATE_IO_SPACE AllocateIoSpace;
+ EFI_FREE_IO_SPACE FreeIoSpace;
+ EFI_REMOVE_IO_SPACE RemoveIoSpace;
+ EFI_GET_IO_SPACE_DESCRIPTOR GetIoSpaceDescriptor;
+ EFI_GET_IO_SPACE_MAP GetIoSpaceMap;
+
+ //
+ // Dispatcher Services
+ //
+ EFI_DISPATCH Dispatch;
+ EFI_SCHEDULE Schedule;
+ EFI_TRUST Trust;
+ //
+ // Service to process a single firmware volume found in a capsule
+ //
+ EFI_PROCESS_FIRMWARE_VOLUME ProcessFirmwareVolume;
+ //
+ // Extensions to Global Coherency Domain Services
+ //
+ EFI_SET_MEMORY_SPACE_CAPABILITIES SetMemorySpaceCapabilities;
+} DXE_SERVICES;
+
+typedef DXE_SERVICES EFI_DXE_SERVICES;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Pi/PiFirmwareFile.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Pi/PiFirmwareFile.h
new file mode 100644
index 0000000000..58d6ebf9aa
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Pi/PiFirmwareFile.h
@@ -0,0 +1,506 @@
+/** @file
+ The firmware file related definitions in PI.
+
+Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Revision Reference:
+ PI Version 1.6.
+
+**/
+
+#ifndef __PI_FIRMWARE_FILE_H__
+#define __PI_FIRMWARE_FILE_H__
+
+#pragma pack(1)
+///
+/// Used to verify the integrity of the file.
+///
+typedef union {
+ struct {
+ ///
+ /// The IntegrityCheck.Checksum.Header field is an 8-bit checksum of the file
+ /// header. The State and IntegrityCheck.Checksum.File fields are assumed
+ /// to be zero and the checksum is calculated such that the entire header sums to zero.
+ ///
+ UINT8 Header;
+ ///
+ /// If the FFS_ATTRIB_CHECKSUM (see definition below) bit of the Attributes
+ /// field is set to one, the IntegrityCheck.Checksum.File field is an 8-bit
+ /// checksum of the file data.
+ /// If the FFS_ATTRIB_CHECKSUM bit of the Attributes field is cleared to zero,
+ /// the IntegrityCheck.Checksum.File field must be initialized with a value of
+ /// 0xAA. The IntegrityCheck.Checksum.File field is valid any time the
+ /// EFI_FILE_DATA_VALID bit is set in the State field.
+ ///
+ UINT8 File;
+ } Checksum;
+ ///
+ /// This is the full 16 bits of the IntegrityCheck field.
+ ///
+ UINT16 Checksum16;
+} EFI_FFS_INTEGRITY_CHECK;
+
+///
+/// FFS_FIXED_CHECKSUM is the checksum value used when the
+/// FFS_ATTRIB_CHECKSUM attribute bit is clear.
+///
+#define FFS_FIXED_CHECKSUM 0xAA
+
+typedef UINT8 EFI_FV_FILETYPE;
+typedef UINT8 EFI_FFS_FILE_ATTRIBUTES;
+typedef UINT8 EFI_FFS_FILE_STATE;
+
+///
+/// File Types Definitions
+///
+#define EFI_FV_FILETYPE_ALL 0x00
+#define EFI_FV_FILETYPE_RAW 0x01
+#define EFI_FV_FILETYPE_FREEFORM 0x02
+#define EFI_FV_FILETYPE_SECURITY_CORE 0x03
+#define EFI_FV_FILETYPE_PEI_CORE 0x04
+#define EFI_FV_FILETYPE_DXE_CORE 0x05
+#define EFI_FV_FILETYPE_PEIM 0x06
+#define EFI_FV_FILETYPE_DRIVER 0x07
+#define EFI_FV_FILETYPE_COMBINED_PEIM_DRIVER 0x08
+#define EFI_FV_FILETYPE_APPLICATION 0x09
+#define EFI_FV_FILETYPE_MM 0x0A
+#define EFI_FV_FILETYPE_SMM EFI_FV_FILETYPE_MM
+#define EFI_FV_FILETYPE_FIRMWARE_VOLUME_IMAGE 0x0B
+#define EFI_FV_FILETYPE_COMBINED_MM_DXE 0x0C
+#define EFI_FV_FILETYPE_COMBINED_SMM_DXE EFI_FV_FILETYPE_COMBINED_MM_DXE
+#define EFI_FV_FILETYPE_MM_CORE 0x0D
+#define EFI_FV_FILETYPE_SMM_CORE EFI_FV_FILETYPE_MM_CORE
+#define EFI_FV_FILETYPE_MM_STANDALONE 0x0E
+#define EFI_FV_FILETYPE_MM_CORE_STANDALONE 0x0F
+#define EFI_FV_FILETYPE_OEM_MIN 0xc0
+#define EFI_FV_FILETYPE_OEM_MAX 0xdf
+#define EFI_FV_FILETYPE_DEBUG_MIN 0xe0
+#define EFI_FV_FILETYPE_DEBUG_MAX 0xef
+#define EFI_FV_FILETYPE_FFS_MIN 0xf0
+#define EFI_FV_FILETYPE_FFS_MAX 0xff
+#define EFI_FV_FILETYPE_FFS_PAD 0xf0
+///
+/// FFS File Attributes.
+///
+#define FFS_ATTRIB_LARGE_FILE 0x01
+#define FFS_ATTRIB_DATA_ALIGNMENT_2 0x02
+#define FFS_ATTRIB_FIXED 0x04
+#define FFS_ATTRIB_DATA_ALIGNMENT 0x38
+#define FFS_ATTRIB_CHECKSUM 0x40
+
+///
+/// FFS File State Bits.
+///
+#define EFI_FILE_HEADER_CONSTRUCTION 0x01
+#define EFI_FILE_HEADER_VALID 0x02
+#define EFI_FILE_DATA_VALID 0x04
+#define EFI_FILE_MARKED_FOR_UPDATE 0x08
+#define EFI_FILE_DELETED 0x10
+#define EFI_FILE_HEADER_INVALID 0x20
+
+///
+/// Each file begins with the header that describe the
+/// contents and state of the files.
+///
+typedef struct {
+ ///
+ /// This GUID is the file name. It is used to uniquely identify the file.
+ ///
+ EFI_GUID Name;
+ ///
+ /// Used to verify the integrity of the file.
+ ///
+ EFI_FFS_INTEGRITY_CHECK IntegrityCheck;
+ ///
+ /// Identifies the type of file.
+ ///
+ EFI_FV_FILETYPE Type;
+ ///
+ /// Declares various file attribute bits.
+ ///
+ EFI_FFS_FILE_ATTRIBUTES Attributes;
+ ///
+ /// The length of the file in bytes, including the FFS header.
+ ///
+ UINT8 Size[3];
+ ///
+ /// Used to track the state of the file throughout the life of the file from creation to deletion.
+ ///
+ EFI_FFS_FILE_STATE State;
+} EFI_FFS_FILE_HEADER;
+
+typedef struct {
+ ///
+ /// This GUID is the file name. It is used to uniquely identify the file. There may be only
+ /// one instance of a file with the file name GUID of Name in any given firmware
+ /// volume, except if the file type is EFI_FV_FILETYPE_FFS_PAD.
+ ///
+ EFI_GUID Name;
+
+ ///
+ /// Used to verify the integrity of the file.
+ ///
+ EFI_FFS_INTEGRITY_CHECK IntegrityCheck;
+
+ ///
+ /// Identifies the type of file.
+ ///
+ EFI_FV_FILETYPE Type;
+
+ ///
+ /// Declares various file attribute bits.
+ ///
+ EFI_FFS_FILE_ATTRIBUTES Attributes;
+
+ ///
+ /// The length of the file in bytes, including the FFS header.
+ /// The length of the file data is either (Size - sizeof(EFI_FFS_FILE_HEADER)). This calculation means a
+ /// zero-length file has a Size of 24 bytes, which is sizeof(EFI_FFS_FILE_HEADER).
+ /// Size is not required to be a multiple of 8 bytes. Given a file F, the next file header is
+ /// located at the next 8-byte aligned firmware volume offset following the last byte of the file F.
+ ///
+ UINT8 Size[3];
+
+ ///
+ /// Used to track the state of the file throughout the life of the file from creation to deletion.
+ ///
+ EFI_FFS_FILE_STATE State;
+
+ ///
+ /// If FFS_ATTRIB_LARGE_FILE is set in Attributes, then ExtendedSize exists and Size must be set to zero.
+ /// If FFS_ATTRIB_LARGE_FILE is not set then EFI_FFS_FILE_HEADER is used.
+ ///
+ UINT64 ExtendedSize;
+} EFI_FFS_FILE_HEADER2;
+
+#define IS_FFS_FILE2(FfsFileHeaderPtr) \
+ (((((EFI_FFS_FILE_HEADER *) (UINTN) FfsFileHeaderPtr)->Attributes) & FFS_ATTRIB_LARGE_FILE) == FFS_ATTRIB_LARGE_FILE)
+
+///
+/// The argument passed as the FfsFileHeaderPtr parameter to the
+/// FFS_FILE_SIZE() function-like macro below must not have side effects:
+/// FfsFileHeaderPtr is evaluated multiple times.
+///
+#define FFS_FILE_SIZE(FfsFileHeaderPtr) ((UINT32) (\
+ (((EFI_FFS_FILE_HEADER *) (UINTN) (FfsFileHeaderPtr))->Size[0] ) | \
+ (((EFI_FFS_FILE_HEADER *) (UINTN) (FfsFileHeaderPtr))->Size[1] << 8) | \
+ (((EFI_FFS_FILE_HEADER *) (UINTN) (FfsFileHeaderPtr))->Size[2] << 16)))
+
+#define FFS_FILE2_SIZE(FfsFileHeaderPtr) \
+ ((UINT32) (((EFI_FFS_FILE_HEADER2 *) (UINTN) FfsFileHeaderPtr)->ExtendedSize))
+
+typedef UINT8 EFI_SECTION_TYPE;
+
+///
+/// Pseudo type. It is used as a wild card when retrieving sections.
+/// The section type EFI_SECTION_ALL matches all section types.
+///
+#define EFI_SECTION_ALL 0x00
+
+///
+/// Encapsulation section Type values.
+///
+#define EFI_SECTION_COMPRESSION 0x01
+
+#define EFI_SECTION_GUID_DEFINED 0x02
+
+#define EFI_SECTION_DISPOSABLE 0x03
+
+///
+/// Leaf section Type values.
+///
+#define EFI_SECTION_PE32 0x10
+#define EFI_SECTION_PIC 0x11
+#define EFI_SECTION_TE 0x12
+#define EFI_SECTION_DXE_DEPEX 0x13
+#define EFI_SECTION_VERSION 0x14
+#define EFI_SECTION_USER_INTERFACE 0x15
+#define EFI_SECTION_COMPATIBILITY16 0x16
+#define EFI_SECTION_FIRMWARE_VOLUME_IMAGE 0x17
+#define EFI_SECTION_FREEFORM_SUBTYPE_GUID 0x18
+#define EFI_SECTION_RAW 0x19
+#define EFI_SECTION_PEI_DEPEX 0x1B
+#define EFI_SECTION_MM_DEPEX 0x1C
+#define EFI_SECTION_SMM_DEPEX EFI_SECTION_MM_DEPEX
+
+///
+/// Common section header.
+///
+typedef struct {
+ ///
+ /// A 24-bit unsigned integer that contains the total size of the section in bytes,
+ /// including the EFI_COMMON_SECTION_HEADER.
+ ///
+ UINT8 Size[3];
+ EFI_SECTION_TYPE Type;
+ ///
+ /// Declares the section type.
+ ///
+} EFI_COMMON_SECTION_HEADER;
+
+typedef struct {
+ ///
+ /// A 24-bit unsigned integer that contains the total size of the section in bytes,
+ /// including the EFI_COMMON_SECTION_HEADER.
+ ///
+ UINT8 Size[3];
+
+ EFI_SECTION_TYPE Type;
+
+ ///
+ /// If Size is 0xFFFFFF, then ExtendedSize contains the size of the section. If
+ /// Size is not equal to 0xFFFFFF, then this field does not exist.
+ ///
+ UINT32 ExtendedSize;
+} EFI_COMMON_SECTION_HEADER2;
+
+///
+/// Leaf section type that contains an
+/// IA-32 16-bit executable image.
+///
+typedef EFI_COMMON_SECTION_HEADER EFI_COMPATIBILITY16_SECTION;
+typedef EFI_COMMON_SECTION_HEADER2 EFI_COMPATIBILITY16_SECTION2;
+
+///
+/// CompressionType of EFI_COMPRESSION_SECTION.
+///
+#define EFI_NOT_COMPRESSED 0x00
+#define EFI_STANDARD_COMPRESSION 0x01
+///
+/// An encapsulation section type in which the
+/// section data is compressed.
+///
+typedef struct {
+ ///
+ /// Usual common section header. CommonHeader.Type = EFI_SECTION_COMPRESSION.
+ ///
+ EFI_COMMON_SECTION_HEADER CommonHeader;
+ ///
+ /// The UINT32 that indicates the size of the section data after decompression.
+ ///
+ UINT32 UncompressedLength;
+ ///
+ /// Indicates which compression algorithm is used.
+ ///
+ UINT8 CompressionType;
+} EFI_COMPRESSION_SECTION;
+
+typedef struct {
+ ///
+ /// Usual common section header. CommonHeader.Type = EFI_SECTION_COMPRESSION.
+ ///
+ EFI_COMMON_SECTION_HEADER2 CommonHeader;
+ ///
+ /// UINT32 that indicates the size of the section data after decompression.
+ ///
+ UINT32 UncompressedLength;
+ ///
+ /// Indicates which compression algorithm is used.
+ ///
+ UINT8 CompressionType;
+} EFI_COMPRESSION_SECTION2;
+
+///
+/// An encapsulation section type in which the section data is disposable.
+/// A disposable section is an encapsulation section in which the section data may be disposed of during
+/// the process of creating or updating a firmware image without significant impact on the usefulness of
+/// the file. The Type field in the section header is set to EFI_SECTION_DISPOSABLE. This
+/// allows optional or descriptive data to be included with the firmware file which can be removed in
+/// order to conserve space. The contents of this section are implementation specific, but might contain
+/// debug data or detailed integration instructions.
+///
+typedef EFI_COMMON_SECTION_HEADER EFI_DISPOSABLE_SECTION;
+typedef EFI_COMMON_SECTION_HEADER2 EFI_DISPOSABLE_SECTION2;
+
+///
+/// The leaf section which could be used to determine the dispatch order of DXEs.
+///
+typedef EFI_COMMON_SECTION_HEADER EFI_DXE_DEPEX_SECTION;
+typedef EFI_COMMON_SECTION_HEADER2 EFI_DXE_DEPEX_SECTION2;
+
+///
+/// The leaf section which contains a PI FV.
+///
+typedef EFI_COMMON_SECTION_HEADER EFI_FIRMWARE_VOLUME_IMAGE_SECTION;
+typedef EFI_COMMON_SECTION_HEADER2 EFI_FIRMWARE_VOLUME_IMAGE_SECTION2;
+
+///
+/// The leaf section which contains a single GUID.
+///
+typedef struct {
+ ///
+ /// Common section header. CommonHeader.Type = EFI_SECTION_FREEFORM_SUBTYPE_GUID.
+ ///
+ EFI_COMMON_SECTION_HEADER CommonHeader;
+ ///
+ /// This GUID is defined by the creator of the file. It is a vendor-defined file type.
+ ///
+ EFI_GUID SubTypeGuid;
+} EFI_FREEFORM_SUBTYPE_GUID_SECTION;
+
+typedef struct {
+ ///
+ /// The common section header. CommonHeader.Type = EFI_SECTION_FREEFORM_SUBTYPE_GUID.
+ ///
+ EFI_COMMON_SECTION_HEADER2 CommonHeader;
+ ///
+ /// This GUID is defined by the creator of the file. It is a vendor-defined file type.
+ ///
+ EFI_GUID SubTypeGuid;
+} EFI_FREEFORM_SUBTYPE_GUID_SECTION2;
+
+///
+/// Attributes of EFI_GUID_DEFINED_SECTION.
+///
+#define EFI_GUIDED_SECTION_PROCESSING_REQUIRED 0x01
+#define EFI_GUIDED_SECTION_AUTH_STATUS_VALID 0x02
+///
+/// The leaf section which is encapsulation defined by specific GUID.
+///
+typedef struct {
+ ///
+ /// The common section header. CommonHeader.Type = EFI_SECTION_GUID_DEFINED.
+ ///
+ EFI_COMMON_SECTION_HEADER CommonHeader;
+ ///
+ /// The GUID that defines the format of the data that follows. It is a vendor-defined section type.
+ ///
+ EFI_GUID SectionDefinitionGuid;
+ ///
+ /// Contains the offset in bytes from the beginning of the common header to the first byte of the data.
+ ///
+ UINT16 DataOffset;
+ ///
+ /// The bit field that declares some specific characteristics of the section contents.
+ ///
+ UINT16 Attributes;
+} EFI_GUID_DEFINED_SECTION;
+
+typedef struct {
+ ///
+ /// The common section header. CommonHeader.Type = EFI_SECTION_GUID_DEFINED.
+ ///
+ EFI_COMMON_SECTION_HEADER2 CommonHeader;
+ ///
+ /// The GUID that defines the format of the data that follows. It is a vendor-defined section type.
+ ///
+ EFI_GUID SectionDefinitionGuid;
+ ///
+ /// Contains the offset in bytes from the beginning of the common header to the first byte of the data.
+ ///
+ UINT16 DataOffset;
+ ///
+ /// The bit field that declares some specific characteristics of the section contents.
+ ///
+ UINT16 Attributes;
+} EFI_GUID_DEFINED_SECTION2;
+
+///
+/// The leaf section which contains PE32+ image.
+///
+typedef EFI_COMMON_SECTION_HEADER EFI_PE32_SECTION;
+typedef EFI_COMMON_SECTION_HEADER2 EFI_PE32_SECTION2;
+
+///
+/// The leaf section used to determine the dispatch order of PEIMs.
+///
+typedef EFI_COMMON_SECTION_HEADER EFI_PEI_DEPEX_SECTION;
+typedef EFI_COMMON_SECTION_HEADER2 EFI_PEI_DEPEX_SECTION2;
+
+///
+/// A leaf section type that contains a position-independent-code (PIC) image.
+/// A PIC image section is a leaf section that contains a position-independent-code (PIC) image.
+/// In addition to normal PE32+ images that contain relocation information, PEIM executables may be
+/// PIC and are referred to as PIC images. A PIC image is the same as a PE32+ image except that all
+/// relocation information has been stripped from the image and the image can be moved and will
+/// execute correctly without performing any relocation or other fix-ups. EFI_PIC_SECTION2 must
+/// be used if the section is 16MB or larger.
+///
+typedef EFI_COMMON_SECTION_HEADER EFI_PIC_SECTION;
+typedef EFI_COMMON_SECTION_HEADER2 EFI_PIC_SECTION2;
+
+///
+/// The leaf section which constains the position-independent-code image.
+///
+typedef EFI_COMMON_SECTION_HEADER EFI_TE_SECTION;
+typedef EFI_COMMON_SECTION_HEADER2 EFI_TE_SECTION2;
+
+///
+/// The leaf section which contains an array of zero or more bytes.
+///
+typedef EFI_COMMON_SECTION_HEADER EFI_RAW_SECTION;
+typedef EFI_COMMON_SECTION_HEADER2 EFI_RAW_SECTION2;
+
+///
+/// The SMM dependency expression section is a leaf section that contains a dependency expression that
+/// is used to determine the dispatch order for SMM drivers. Before the SMRAM invocation of the
+/// SMM driver's entry point, this dependency expression must evaluate to TRUE. See the Platform
+/// Initialization Specification, Volume 2, for details regarding the format of the dependency expression.
+/// The dependency expression may refer to protocols installed in either the UEFI or the SMM protocol
+/// database. EFI_SMM_DEPEX_SECTION2 must be used if the section is 16MB or larger.
+///
+typedef EFI_COMMON_SECTION_HEADER EFI_SMM_DEPEX_SECTION;
+typedef EFI_COMMON_SECTION_HEADER2 EFI_SMM_DEPEX_SECTION2;
+
+///
+/// The leaf section which contains a unicode string that
+/// is human readable file name.
+///
+typedef struct {
+ EFI_COMMON_SECTION_HEADER CommonHeader;
+
+ ///
+ /// Array of unicode string.
+ ///
+ CHAR16 FileNameString[1];
+} EFI_USER_INTERFACE_SECTION;
+
+typedef struct {
+ EFI_COMMON_SECTION_HEADER2 CommonHeader;
+ CHAR16 FileNameString[1];
+} EFI_USER_INTERFACE_SECTION2;
+
+///
+/// The leaf section which contains a numeric build number and
+/// an optional unicode string that represents the file revision.
+///
+typedef struct {
+ EFI_COMMON_SECTION_HEADER CommonHeader;
+ UINT16 BuildNumber;
+
+ ///
+ /// Array of unicode string.
+ ///
+ CHAR16 VersionString[1];
+} EFI_VERSION_SECTION;
+
+typedef struct {
+ EFI_COMMON_SECTION_HEADER2 CommonHeader;
+ ///
+ /// A UINT16 that represents a particular build. Subsequent builds have monotonically
+ /// increasing build numbers relative to earlier builds.
+ ///
+ UINT16 BuildNumber;
+ CHAR16 VersionString[1];
+} EFI_VERSION_SECTION2;
+
+///
+/// The argument passed as the SectionHeaderPtr parameter to the SECTION_SIZE()
+/// and IS_SECTION2() function-like macros below must not have side effects:
+/// SectionHeaderPtr is evaluated multiple times.
+///
+#define SECTION_SIZE(SectionHeaderPtr) ((UINT32) (\
+ (((EFI_COMMON_SECTION_HEADER *) (UINTN) (SectionHeaderPtr))->Size[0] ) | \
+ (((EFI_COMMON_SECTION_HEADER *) (UINTN) (SectionHeaderPtr))->Size[1] << 8) | \
+ (((EFI_COMMON_SECTION_HEADER *) (UINTN) (SectionHeaderPtr))->Size[2] << 16)))
+
+#define IS_SECTION2(SectionHeaderPtr) \
+ (SECTION_SIZE (SectionHeaderPtr) == 0x00ffffff)
+
+#define SECTION2_SIZE(SectionHeaderPtr) \
+ (((EFI_COMMON_SECTION_HEADER2 *) (UINTN) SectionHeaderPtr)->ExtendedSize)
+
+#pragma pack()
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Pi/PiFirmwareVolume.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Pi/PiFirmwareVolume.h
new file mode 100644
index 0000000000..0b0382671c
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Pi/PiFirmwareVolume.h
@@ -0,0 +1,247 @@
+/** @file
+ The firmware volume related definitions in PI.
+
+ Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Revision Reference:
+ PI Version 1.6
+
+**/
+
+#ifndef __PI_FIRMWAREVOLUME_H__
+#define __PI_FIRMWAREVOLUME_H__
+
+///
+/// EFI_FV_FILE_ATTRIBUTES
+///
+typedef UINT32 EFI_FV_FILE_ATTRIBUTES;
+
+//
+// Value of EFI_FV_FILE_ATTRIBUTES.
+//
+#define EFI_FV_FILE_ATTRIB_ALIGNMENT 0x0000001F
+#define EFI_FV_FILE_ATTRIB_FIXED 0x00000100
+#define EFI_FV_FILE_ATTRIB_MEMORY_MAPPED 0x00000200
+
+///
+/// type of EFI FVB attribute
+///
+typedef UINT32 EFI_FVB_ATTRIBUTES_2;
+
+//
+// Attributes bit definitions
+//
+#define EFI_FVB2_READ_DISABLED_CAP 0x00000001
+#define EFI_FVB2_READ_ENABLED_CAP 0x00000002
+#define EFI_FVB2_READ_STATUS 0x00000004
+#define EFI_FVB2_WRITE_DISABLED_CAP 0x00000008
+#define EFI_FVB2_WRITE_ENABLED_CAP 0x00000010
+#define EFI_FVB2_WRITE_STATUS 0x00000020
+#define EFI_FVB2_LOCK_CAP 0x00000040
+#define EFI_FVB2_LOCK_STATUS 0x00000080
+#define EFI_FVB2_STICKY_WRITE 0x00000200
+#define EFI_FVB2_MEMORY_MAPPED 0x00000400
+#define EFI_FVB2_ERASE_POLARITY 0x00000800
+#define EFI_FVB2_READ_LOCK_CAP 0x00001000
+#define EFI_FVB2_READ_LOCK_STATUS 0x00002000
+#define EFI_FVB2_WRITE_LOCK_CAP 0x00004000
+#define EFI_FVB2_WRITE_LOCK_STATUS 0x00008000
+#define EFI_FVB2_ALIGNMENT 0x001F0000
+#define EFI_FVB2_ALIGNMENT_1 0x00000000
+#define EFI_FVB2_ALIGNMENT_2 0x00010000
+#define EFI_FVB2_ALIGNMENT_4 0x00020000
+#define EFI_FVB2_ALIGNMENT_8 0x00030000
+#define EFI_FVB2_ALIGNMENT_16 0x00040000
+#define EFI_FVB2_ALIGNMENT_32 0x00050000
+#define EFI_FVB2_ALIGNMENT_64 0x00060000
+#define EFI_FVB2_ALIGNMENT_128 0x00070000
+#define EFI_FVB2_ALIGNMENT_256 0x00080000
+#define EFI_FVB2_ALIGNMENT_512 0x00090000
+#define EFI_FVB2_ALIGNMENT_1K 0x000A0000
+#define EFI_FVB2_ALIGNMENT_2K 0x000B0000
+#define EFI_FVB2_ALIGNMENT_4K 0x000C0000
+#define EFI_FVB2_ALIGNMENT_8K 0x000D0000
+#define EFI_FVB2_ALIGNMENT_16K 0x000E0000
+#define EFI_FVB2_ALIGNMENT_32K 0x000F0000
+#define EFI_FVB2_ALIGNMENT_64K 0x00100000
+#define EFI_FVB2_ALIGNMENT_128K 0x00110000
+#define EFI_FVB2_ALIGNMENT_256K 0x00120000
+#define EFI_FVB2_ALIGNMENT_512K 0x00130000
+#define EFI_FVB2_ALIGNMENT_1M 0x00140000
+#define EFI_FVB2_ALIGNMENT_2M 0x00150000
+#define EFI_FVB2_ALIGNMENT_4M 0x00160000
+#define EFI_FVB2_ALIGNMENT_8M 0x00170000
+#define EFI_FVB2_ALIGNMENT_16M 0x00180000
+#define EFI_FVB2_ALIGNMENT_32M 0x00190000
+#define EFI_FVB2_ALIGNMENT_64M 0x001A0000
+#define EFI_FVB2_ALIGNMENT_128M 0x001B0000
+#define EFI_FVB2_ALIGNMENT_256M 0x001C0000
+#define EFI_FVB2_ALIGNMENT_512M 0x001D0000
+#define EFI_FVB2_ALIGNMENT_1G 0x001E0000
+#define EFI_FVB2_ALIGNMENT_2G 0x001F0000
+#define EFI_FVB2_WEAK_ALIGNMENT 0x80000000
+
+typedef struct {
+ ///
+ /// The number of sequential blocks which are of the same size.
+ ///
+ UINT32 NumBlocks;
+ ///
+ /// The size of the blocks.
+ ///
+ UINT32 Length;
+} EFI_FV_BLOCK_MAP_ENTRY;
+
+///
+/// Describes the features and layout of the firmware volume.
+///
+typedef struct {
+ ///
+ /// The first 16 bytes are reserved to allow for the reset vector of
+ /// processors whose reset vector is at address 0.
+ ///
+ UINT8 ZeroVector[16];
+ ///
+ /// Declares the file system with which the firmware volume is formatted.
+ ///
+ EFI_GUID FileSystemGuid;
+ ///
+ /// Length in bytes of the complete firmware volume, including the header.
+ ///
+ UINT64 FvLength;
+ ///
+ /// Set to EFI_FVH_SIGNATURE
+ ///
+ UINT32 Signature;
+ ///
+ /// Declares capabilities and power-on defaults for the firmware volume.
+ ///
+ EFI_FVB_ATTRIBUTES_2 Attributes;
+ ///
+ /// Length in bytes of the complete firmware volume header.
+ ///
+ UINT16 HeaderLength;
+ ///
+ /// A 16-bit checksum of the firmware volume header. A valid header sums to zero.
+ ///
+ UINT16 Checksum;
+ ///
+ /// Offset, relative to the start of the header, of the extended header
+ /// (EFI_FIRMWARE_VOLUME_EXT_HEADER) or zero if there is no extended header.
+ ///
+ UINT16 ExtHeaderOffset;
+ ///
+ /// This field must always be set to zero.
+ ///
+ UINT8 Reserved[1];
+ ///
+ /// Set to 2. Future versions of this specification may define new header fields and will
+ /// increment the Revision field accordingly.
+ ///
+ UINT8 Revision;
+ ///
+ /// An array of run-length encoded FvBlockMapEntry structures. The array is
+ /// terminated with an entry of {0,0}.
+ ///
+ EFI_FV_BLOCK_MAP_ENTRY BlockMap[1];
+} EFI_FIRMWARE_VOLUME_HEADER;
+
+#define EFI_FVH_SIGNATURE SIGNATURE_32 ('_', 'F', 'V', 'H')
+
+///
+/// Firmware Volume Header Revision definition
+///
+#define EFI_FVH_REVISION 0x02
+
+///
+/// Extension header pointed by ExtHeaderOffset of volume header.
+///
+typedef struct {
+ ///
+ /// Firmware volume name.
+ ///
+ EFI_GUID FvName;
+ ///
+ /// Size of the rest of the extension header, including this structure.
+ ///
+ UINT32 ExtHeaderSize;
+} EFI_FIRMWARE_VOLUME_EXT_HEADER;
+
+///
+/// Entry struture for describing FV extension header
+///
+typedef struct {
+ ///
+ /// Size of this header extension.
+ ///
+ UINT16 ExtEntrySize;
+ ///
+ /// Type of the header.
+ ///
+ UINT16 ExtEntryType;
+} EFI_FIRMWARE_VOLUME_EXT_ENTRY;
+
+#define EFI_FV_EXT_TYPE_OEM_TYPE 0x01
+///
+/// This extension header provides a mapping between a GUID and an OEM file type.
+///
+typedef struct {
+ ///
+ /// Standard extension entry, with the type EFI_FV_EXT_TYPE_OEM_TYPE.
+ ///
+ EFI_FIRMWARE_VOLUME_EXT_ENTRY Hdr;
+ ///
+ /// A bit mask, one bit for each file type between 0xC0 (bit 0) and 0xDF (bit 31). If a bit
+ /// is '1', then the GUID entry exists in Types. If a bit is '0' then no GUID entry exists in Types.
+ ///
+ UINT32 TypeMask;
+ ///
+ /// An array of GUIDs, each GUID representing an OEM file type.
+ ///
+ /// EFI_GUID Types[1];
+ ///
+} EFI_FIRMWARE_VOLUME_EXT_ENTRY_OEM_TYPE;
+
+#define EFI_FV_EXT_TYPE_GUID_TYPE 0x0002
+
+///
+/// This extension header EFI_FIRMWARE_VOLUME_EXT_ENTRY_GUID_TYPE provides a vendor specific
+/// GUID FormatType type which includes a length and a successive series of data bytes.
+///
+typedef struct {
+ ///
+ /// Standard extension entry, with the type EFI_FV_EXT_TYPE_OEM_TYPE.
+ ///
+ EFI_FIRMWARE_VOLUME_EXT_ENTRY Hdr;
+ ///
+ /// Vendor-specific GUID.
+ ///
+ EFI_GUID FormatType;
+ ///
+ /// An arry of bytes of length Length.
+ ///
+ /// UINT8 Data[1];
+ ///
+} EFI_FIRMWARE_VOLUME_EXT_ENTRY_GUID_TYPE;
+
+#define EFI_FV_EXT_TYPE_USED_SIZE_TYPE 0x03
+
+///
+/// The EFI_FIRMWARE_VOLUME_EXT_ENTRY_USED_SIZE_TYPE can be used to find
+/// out how many EFI_FVB2_ERASE_POLARITY bytes are at the end of the FV.
+///
+typedef struct {
+ ///
+ /// Standard extension entry, with the type EFI_FV_EXT_TYPE_USED_SIZE_TYPE.
+ ///
+ EFI_FIRMWARE_VOLUME_EXT_ENTRY Hdr;
+ ///
+ /// The number of bytes of the FV that are in uses. The remaining
+ /// EFI_FIRMWARE_VOLUME_HEADER FvLength minus UsedSize bytes in
+ /// the FV must contain the value implied by EFI_FVB2_ERASE_POLARITY.
+ ///
+ UINT32 UsedSize;
+} EFI_FIRMWARE_VOLUME_EXT_ENTRY_USED_SIZE_TYPE;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Pi/PiHob.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Pi/PiHob.h
new file mode 100644
index 0000000000..6c9095ccb7
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Pi/PiHob.h
@@ -0,0 +1,517 @@
+/** @file
+ HOB related definitions in PI.
+
+Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Revision Reference:
+ PI Version 1.6
+
+**/
+
+#ifndef __PI_HOB_H__
+#define __PI_HOB_H__
+
+//
+// HobType of EFI_HOB_GENERIC_HEADER.
+//
+#define EFI_HOB_TYPE_HANDOFF 0x0001
+#define EFI_HOB_TYPE_MEMORY_ALLOCATION 0x0002
+#define EFI_HOB_TYPE_RESOURCE_DESCRIPTOR 0x0003
+#define EFI_HOB_TYPE_GUID_EXTENSION 0x0004
+#define EFI_HOB_TYPE_FV 0x0005
+#define EFI_HOB_TYPE_CPU 0x0006
+#define EFI_HOB_TYPE_MEMORY_POOL 0x0007
+#define EFI_HOB_TYPE_FV2 0x0009
+#define EFI_HOB_TYPE_LOAD_PEIM_UNUSED 0x000A
+#define EFI_HOB_TYPE_UEFI_CAPSULE 0x000B
+#define EFI_HOB_TYPE_FV3 0x000C
+#define EFI_HOB_TYPE_UNUSED 0xFFFE
+#define EFI_HOB_TYPE_END_OF_HOB_LIST 0xFFFF
+
+///
+/// Describes the format and size of the data inside the HOB.
+/// All HOBs must contain this generic HOB header.
+///
+typedef struct {
+ ///
+ /// Identifies the HOB data structure type.
+ ///
+ UINT16 HobType;
+ ///
+ /// The length in bytes of the HOB.
+ ///
+ UINT16 HobLength;
+ ///
+ /// This field must always be set to zero.
+ ///
+ UINT32 Reserved;
+} EFI_HOB_GENERIC_HEADER;
+
+///
+/// Value of version in EFI_HOB_HANDOFF_INFO_TABLE.
+///
+#define EFI_HOB_HANDOFF_TABLE_VERSION 0x0009
+
+///
+/// Contains general state information used by the HOB producer phase.
+/// This HOB must be the first one in the HOB list.
+///
+typedef struct {
+ ///
+ /// The HOB generic header. Header.HobType = EFI_HOB_TYPE_HANDOFF.
+ ///
+ EFI_HOB_GENERIC_HEADER Header;
+ ///
+ /// The version number pertaining to the PHIT HOB definition.
+ /// This value is four bytes in length to provide an 8-byte aligned entry
+ /// when it is combined with the 4-byte BootMode.
+ ///
+ UINT32 Version;
+ ///
+ /// The system boot mode as determined during the HOB producer phase.
+ ///
+ EFI_BOOT_MODE BootMode;
+ ///
+ /// The highest address location of memory that is allocated for use by the HOB producer
+ /// phase. This address must be 4-KB aligned to meet page restrictions of UEFI.
+ ///
+ EFI_PHYSICAL_ADDRESS EfiMemoryTop;
+ ///
+ /// The lowest address location of memory that is allocated for use by the HOB producer phase.
+ ///
+ EFI_PHYSICAL_ADDRESS EfiMemoryBottom;
+ ///
+ /// The highest address location of free memory that is currently available
+ /// for use by the HOB producer phase.
+ ///
+ EFI_PHYSICAL_ADDRESS EfiFreeMemoryTop;
+ ///
+ /// The lowest address location of free memory that is available for use by the HOB producer phase.
+ ///
+ EFI_PHYSICAL_ADDRESS EfiFreeMemoryBottom;
+ ///
+ /// The end of the HOB list.
+ ///
+ EFI_PHYSICAL_ADDRESS EfiEndOfHobList;
+} EFI_HOB_HANDOFF_INFO_TABLE;
+
+///
+/// EFI_HOB_MEMORY_ALLOCATION_HEADER describes the
+/// various attributes of the logical memory allocation. The type field will be used for
+/// subsequent inclusion in the UEFI memory map.
+///
+typedef struct {
+ ///
+ /// A GUID that defines the memory allocation region's type and purpose, as well as
+ /// other fields within the memory allocation HOB. This GUID is used to define the
+ /// additional data within the HOB that may be present for the memory allocation HOB.
+ /// Type EFI_GUID is defined in InstallProtocolInterface() in the UEFI 2.0
+ /// specification.
+ ///
+ EFI_GUID Name;
+
+ ///
+ /// The base address of memory allocated by this HOB. Type
+ /// EFI_PHYSICAL_ADDRESS is defined in AllocatePages() in the UEFI 2.0
+ /// specification.
+ ///
+ EFI_PHYSICAL_ADDRESS MemoryBaseAddress;
+
+ ///
+ /// The length in bytes of memory allocated by this HOB.
+ ///
+ UINT64 MemoryLength;
+
+ ///
+ /// Defines the type of memory allocated by this HOB. The memory type definition
+ /// follows the EFI_MEMORY_TYPE definition. Type EFI_MEMORY_TYPE is defined
+ /// in AllocatePages() in the UEFI 2.0 specification.
+ ///
+ EFI_MEMORY_TYPE MemoryType;
+
+ ///
+ /// Padding for Itanium processor family
+ ///
+ UINT8 Reserved[4];
+} EFI_HOB_MEMORY_ALLOCATION_HEADER;
+
+///
+/// Describes all memory ranges used during the HOB producer
+/// phase that exist outside the HOB list. This HOB type
+/// describes how memory is used, not the physical attributes of memory.
+///
+typedef struct {
+ ///
+ /// The HOB generic header. Header.HobType = EFI_HOB_TYPE_MEMORY_ALLOCATION.
+ ///
+ EFI_HOB_GENERIC_HEADER Header;
+ ///
+ /// An instance of the EFI_HOB_MEMORY_ALLOCATION_HEADER that describes the
+ /// various attributes of the logical memory allocation.
+ ///
+ EFI_HOB_MEMORY_ALLOCATION_HEADER AllocDescriptor;
+ //
+ // Additional data pertaining to the "Name" Guid memory
+ // may go here.
+ //
+} EFI_HOB_MEMORY_ALLOCATION;
+
+///
+/// Describes the memory stack that is produced by the HOB producer
+/// phase and upon which all post-memory-installed executable
+/// content in the HOB producer phase is executing.
+///
+typedef struct {
+ ///
+ /// The HOB generic header. Header.HobType = EFI_HOB_TYPE_MEMORY_ALLOCATION.
+ ///
+ EFI_HOB_GENERIC_HEADER Header;
+ ///
+ /// An instance of the EFI_HOB_MEMORY_ALLOCATION_HEADER that describes the
+ /// various attributes of the logical memory allocation.
+ ///
+ EFI_HOB_MEMORY_ALLOCATION_HEADER AllocDescriptor;
+} EFI_HOB_MEMORY_ALLOCATION_STACK;
+
+///
+/// Defines the location of the boot-strap
+/// processor (BSP) BSPStore ("Backing Store Pointer Store").
+/// This HOB is valid for the Itanium processor family only
+/// register overflow store.
+///
+typedef struct {
+ ///
+ /// The HOB generic header. Header.HobType = EFI_HOB_TYPE_MEMORY_ALLOCATION.
+ ///
+ EFI_HOB_GENERIC_HEADER Header;
+ ///
+ /// An instance of the EFI_HOB_MEMORY_ALLOCATION_HEADER that describes the
+ /// various attributes of the logical memory allocation.
+ ///
+ EFI_HOB_MEMORY_ALLOCATION_HEADER AllocDescriptor;
+} EFI_HOB_MEMORY_ALLOCATION_BSP_STORE;
+
+///
+/// Defines the location and entry point of the HOB consumer phase.
+///
+typedef struct {
+ ///
+ /// The HOB generic header. Header.HobType = EFI_HOB_TYPE_MEMORY_ALLOCATION.
+ ///
+ EFI_HOB_GENERIC_HEADER Header;
+ ///
+ /// An instance of the EFI_HOB_MEMORY_ALLOCATION_HEADER that describes the
+ /// various attributes of the logical memory allocation.
+ ///
+ EFI_HOB_MEMORY_ALLOCATION_HEADER MemoryAllocationHeader;
+ ///
+ /// The GUID specifying the values of the firmware file system name
+ /// that contains the HOB consumer phase component.
+ ///
+ EFI_GUID ModuleName;
+ ///
+ /// The address of the memory-mapped firmware volume
+ /// that contains the HOB consumer phase firmware file.
+ ///
+ EFI_PHYSICAL_ADDRESS EntryPoint;
+} EFI_HOB_MEMORY_ALLOCATION_MODULE;
+
+///
+/// The resource type.
+///
+typedef UINT32 EFI_RESOURCE_TYPE;
+
+//
+// Value of ResourceType in EFI_HOB_RESOURCE_DESCRIPTOR.
+//
+#define EFI_RESOURCE_SYSTEM_MEMORY 0x00000000
+#define EFI_RESOURCE_MEMORY_MAPPED_IO 0x00000001
+#define EFI_RESOURCE_IO 0x00000002
+#define EFI_RESOURCE_FIRMWARE_DEVICE 0x00000003
+#define EFI_RESOURCE_MEMORY_MAPPED_IO_PORT 0x00000004
+#define EFI_RESOURCE_MEMORY_RESERVED 0x00000005
+#define EFI_RESOURCE_IO_RESERVED 0x00000006
+//
+// BZ3937_EFI_RESOURCE_MEMORY_UNACCEPTED is defined for unaccepted memory.
+// But this defitinion has not been officially in the PI spec. Base
+// on the code-first we define BZ3937_EFI_RESOURCE_MEMORY_UNACCEPTED at
+// MdeModulePkg/Include/Pi/PrePiHob.h and update EFI_RESOURCE_MAX_MEMORY_TYPE
+// to 8. After BZ3937_EFI_RESOURCE_MEMORY_UNACCEPTED is officially published
+// in PI spec, we will re-visit here.
+//
+// #define BZ3937_EFI_RESOURCE_MEMORY_UNACCEPTED 0x00000007
+#define EFI_RESOURCE_MAX_MEMORY_TYPE 0x00000008
+
+///
+/// A type of recount attribute type.
+///
+typedef UINT32 EFI_RESOURCE_ATTRIBUTE_TYPE;
+
+//
+// These types can be ORed together as needed.
+//
+// The following attributes are used to describe settings
+//
+#define EFI_RESOURCE_ATTRIBUTE_PRESENT 0x00000001
+#define EFI_RESOURCE_ATTRIBUTE_INITIALIZED 0x00000002
+#define EFI_RESOURCE_ATTRIBUTE_TESTED 0x00000004
+#define EFI_RESOURCE_ATTRIBUTE_READ_PROTECTED 0x00000080
+//
+// This is typically used as memory cacheability attribute today.
+// NOTE: Since PI spec 1.4, please use EFI_RESOURCE_ATTRIBUTE_READ_ONLY_PROTECTED
+// as Physical write protected attribute, and EFI_RESOURCE_ATTRIBUTE_WRITE_PROTECTED
+// means Memory cacheability attribute: The memory supports being programmed with
+// a writeprotected cacheable attribute.
+//
+#define EFI_RESOURCE_ATTRIBUTE_WRITE_PROTECTED 0x00000100
+#define EFI_RESOURCE_ATTRIBUTE_EXECUTION_PROTECTED 0x00000200
+#define EFI_RESOURCE_ATTRIBUTE_PERSISTENT 0x00800000
+//
+// The rest of the attributes are used to describe capabilities
+//
+#define EFI_RESOURCE_ATTRIBUTE_SINGLE_BIT_ECC 0x00000008
+#define EFI_RESOURCE_ATTRIBUTE_MULTIPLE_BIT_ECC 0x00000010
+#define EFI_RESOURCE_ATTRIBUTE_ECC_RESERVED_1 0x00000020
+#define EFI_RESOURCE_ATTRIBUTE_ECC_RESERVED_2 0x00000040
+#define EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE 0x00000400
+#define EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE 0x00000800
+#define EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE 0x00001000
+#define EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE 0x00002000
+#define EFI_RESOURCE_ATTRIBUTE_16_BIT_IO 0x00004000
+#define EFI_RESOURCE_ATTRIBUTE_32_BIT_IO 0x00008000
+#define EFI_RESOURCE_ATTRIBUTE_64_BIT_IO 0x00010000
+#define EFI_RESOURCE_ATTRIBUTE_UNCACHED_EXPORTED 0x00020000
+#define EFI_RESOURCE_ATTRIBUTE_READ_PROTECTABLE 0x00100000
+//
+// This is typically used as memory cacheability attribute today.
+// NOTE: Since PI spec 1.4, please use EFI_RESOURCE_ATTRIBUTE_READ_ONLY_PROTECTABLE
+// as Memory capability attribute: The memory supports being protected from processor
+// writes, and EFI_RESOURCE_ATTRIBUTE_WRITE_PROTEC TABLE means Memory cacheability attribute:
+// The memory supports being programmed with a writeprotected cacheable attribute.
+//
+#define EFI_RESOURCE_ATTRIBUTE_WRITE_PROTECTABLE 0x00200000
+#define EFI_RESOURCE_ATTRIBUTE_EXECUTION_PROTECTABLE 0x00400000
+#define EFI_RESOURCE_ATTRIBUTE_PERSISTABLE 0x01000000
+
+#define EFI_RESOURCE_ATTRIBUTE_READ_ONLY_PROTECTED 0x00040000
+#define EFI_RESOURCE_ATTRIBUTE_READ_ONLY_PROTECTABLE 0x00080000
+
+//
+// Physical memory relative reliability attribute. This
+// memory provides higher reliability relative to other
+// memory in the system. If all memory has the same
+// reliability, then this bit is not used.
+//
+#define EFI_RESOURCE_ATTRIBUTE_MORE_RELIABLE 0x02000000
+
+///
+/// Describes the resource properties of all fixed,
+/// nonrelocatable resource ranges found on the processor
+/// host bus during the HOB producer phase.
+///
+typedef struct {
+ ///
+ /// The HOB generic header. Header.HobType = EFI_HOB_TYPE_RESOURCE_DESCRIPTOR.
+ ///
+ EFI_HOB_GENERIC_HEADER Header;
+ ///
+ /// A GUID representing the owner of the resource. This GUID is used by HOB
+ /// consumer phase components to correlate device ownership of a resource.
+ ///
+ EFI_GUID Owner;
+ ///
+ /// The resource type enumeration as defined by EFI_RESOURCE_TYPE.
+ ///
+ EFI_RESOURCE_TYPE ResourceType;
+ ///
+ /// Resource attributes as defined by EFI_RESOURCE_ATTRIBUTE_TYPE.
+ ///
+ EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttribute;
+ ///
+ /// The physical start address of the resource region.
+ ///
+ EFI_PHYSICAL_ADDRESS PhysicalStart;
+ ///
+ /// The number of bytes of the resource region.
+ ///
+ UINT64 ResourceLength;
+} EFI_HOB_RESOURCE_DESCRIPTOR;
+
+///
+/// Allows writers of executable content in the HOB producer phase to
+/// maintain and manage HOBs with specific GUID.
+///
+typedef struct {
+ ///
+ /// The HOB generic header. Header.HobType = EFI_HOB_TYPE_GUID_EXTENSION.
+ ///
+ EFI_HOB_GENERIC_HEADER Header;
+ ///
+ /// A GUID that defines the contents of this HOB.
+ ///
+ EFI_GUID Name;
+ //
+ // Guid specific data goes here
+ //
+} EFI_HOB_GUID_TYPE;
+
+///
+/// Details the location of firmware volumes that contain firmware files.
+///
+typedef struct {
+ ///
+ /// The HOB generic header. Header.HobType = EFI_HOB_TYPE_FV.
+ ///
+ EFI_HOB_GENERIC_HEADER Header;
+ ///
+ /// The physical memory-mapped base address of the firmware volume.
+ ///
+ EFI_PHYSICAL_ADDRESS BaseAddress;
+ ///
+ /// The length in bytes of the firmware volume.
+ ///
+ UINT64 Length;
+} EFI_HOB_FIRMWARE_VOLUME;
+
+///
+/// Details the location of a firmware volume that was extracted
+/// from a file within another firmware volume.
+///
+typedef struct {
+ ///
+ /// The HOB generic header. Header.HobType = EFI_HOB_TYPE_FV2.
+ ///
+ EFI_HOB_GENERIC_HEADER Header;
+ ///
+ /// The physical memory-mapped base address of the firmware volume.
+ ///
+ EFI_PHYSICAL_ADDRESS BaseAddress;
+ ///
+ /// The length in bytes of the firmware volume.
+ ///
+ UINT64 Length;
+ ///
+ /// The name of the firmware volume.
+ ///
+ EFI_GUID FvName;
+ ///
+ /// The name of the firmware file that contained this firmware volume.
+ ///
+ EFI_GUID FileName;
+} EFI_HOB_FIRMWARE_VOLUME2;
+
+///
+/// Details the location of a firmware volume that was extracted
+/// from a file within another firmware volume.
+///
+typedef struct {
+ ///
+ /// The HOB generic header. Header.HobType = EFI_HOB_TYPE_FV3.
+ ///
+ EFI_HOB_GENERIC_HEADER Header;
+ ///
+ /// The physical memory-mapped base address of the firmware volume.
+ ///
+ EFI_PHYSICAL_ADDRESS BaseAddress;
+ ///
+ /// The length in bytes of the firmware volume.
+ ///
+ UINT64 Length;
+ ///
+ /// The authentication status.
+ ///
+ UINT32 AuthenticationStatus;
+ ///
+ /// TRUE if the FV was extracted as a file within another firmware volume.
+ /// FALSE otherwise.
+ ///
+ BOOLEAN ExtractedFv;
+ ///
+ /// The name of the firmware volume.
+ /// Valid only if IsExtractedFv is TRUE.
+ ///
+ EFI_GUID FvName;
+ ///
+ /// The name of the firmware file that contained this firmware volume.
+ /// Valid only if IsExtractedFv is TRUE.
+ ///
+ EFI_GUID FileName;
+} EFI_HOB_FIRMWARE_VOLUME3;
+
+///
+/// Describes processor information, such as address space and I/O space capabilities.
+///
+typedef struct {
+ ///
+ /// The HOB generic header. Header.HobType = EFI_HOB_TYPE_CPU.
+ ///
+ EFI_HOB_GENERIC_HEADER Header;
+ ///
+ /// Identifies the maximum physical memory addressability of the processor.
+ ///
+ UINT8 SizeOfMemorySpace;
+ ///
+ /// Identifies the maximum physical I/O addressability of the processor.
+ ///
+ UINT8 SizeOfIoSpace;
+ ///
+ /// This field will always be set to zero.
+ ///
+ UINT8 Reserved[6];
+} EFI_HOB_CPU;
+
+///
+/// Describes pool memory allocations.
+///
+typedef struct {
+ ///
+ /// The HOB generic header. Header.HobType = EFI_HOB_TYPE_MEMORY_POOL.
+ ///
+ EFI_HOB_GENERIC_HEADER Header;
+} EFI_HOB_MEMORY_POOL;
+
+///
+/// Each UEFI capsule HOB details the location of a UEFI capsule. It includes a base address and length
+/// which is based upon memory blocks with a EFI_CAPSULE_HEADER and the associated
+/// CapsuleImageSize-based payloads. These HOB's shall be created by the PEI PI firmware
+/// sometime after the UEFI UpdateCapsule service invocation with the
+/// CAPSULE_FLAGS_POPULATE_SYSTEM_TABLE flag set in the EFI_CAPSULE_HEADER.
+///
+typedef struct {
+ ///
+ /// The HOB generic header where Header.HobType = EFI_HOB_TYPE_UEFI_CAPSULE.
+ ///
+ EFI_HOB_GENERIC_HEADER Header;
+
+ ///
+ /// The physical memory-mapped base address of an UEFI capsule. This value is set to
+ /// point to the base of the contiguous memory of the UEFI capsule.
+ /// The length of the contiguous memory in bytes.
+ ///
+ EFI_PHYSICAL_ADDRESS BaseAddress;
+ UINT64 Length;
+} EFI_HOB_UEFI_CAPSULE;
+
+///
+/// Union of all the possible HOB Types.
+///
+typedef union {
+ EFI_HOB_GENERIC_HEADER *Header;
+ EFI_HOB_HANDOFF_INFO_TABLE *HandoffInformationTable;
+ EFI_HOB_MEMORY_ALLOCATION *MemoryAllocation;
+ EFI_HOB_MEMORY_ALLOCATION_BSP_STORE *MemoryAllocationBspStore;
+ EFI_HOB_MEMORY_ALLOCATION_STACK *MemoryAllocationStack;
+ EFI_HOB_MEMORY_ALLOCATION_MODULE *MemoryAllocationModule;
+ EFI_HOB_RESOURCE_DESCRIPTOR *ResourceDescriptor;
+ EFI_HOB_GUID_TYPE *Guid;
+ EFI_HOB_FIRMWARE_VOLUME *FirmwareVolume;
+ EFI_HOB_FIRMWARE_VOLUME2 *FirmwareVolume2;
+ EFI_HOB_FIRMWARE_VOLUME3 *FirmwareVolume3;
+ EFI_HOB_CPU *Cpu;
+ EFI_HOB_MEMORY_POOL *Pool;
+ EFI_HOB_UEFI_CAPSULE *Capsule;
+ UINT8 *Raw;
+} EFI_PEI_HOB_POINTERS;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Pi/PiI2c.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Pi/PiI2c.h
new file mode 100644
index 0000000000..18805746f1
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Pi/PiI2c.h
@@ -0,0 +1,301 @@
+/** @file
+ Include file matches things in PI.
+
+Copyright (c) 2013 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Revision Reference:
+ PI Version 1.3
+
+**/
+
+#ifndef __PI_I2C_H__
+#define __PI_I2C_H__
+
+///
+/// A 10-bit slave address is or'ed with the following value enabling the
+/// I2C protocol stack to address the duplicated address space between 0
+// and 127 in 10-bit mode.
+///
+#define I2C_ADDRESSING_10_BIT 0x80000000
+
+///
+/// I2C controller capabilities
+///
+/// The EFI_I2C_CONTROLLER_CAPABILITIES specifies the capabilities of the
+/// I2C host controller. The StructureSizeInBytes enables variations of
+/// this structure to be identified if there is need to extend this
+/// structure in the future.
+///
+typedef struct {
+ ///
+ /// Length of this data structure in bytes
+ ///
+ UINT32 StructureSizeInBytes;
+
+ ///
+ /// The maximum number of bytes the I2C host controller is able to
+ /// receive from the I2C bus.
+ ///
+ UINT32 MaximumReceiveBytes;
+
+ ///
+ /// The maximum number of bytes the I2C host controller is able to send
+ /// on the I2C bus.
+ ///
+ UINT32 MaximumTransmitBytes;
+
+ ///
+ /// The maximum number of bytes in the I2C bus transaction.
+ ///
+ UINT32 MaximumTotalBytes;
+} EFI_I2C_CONTROLLER_CAPABILITIES;
+
+///
+/// I2C device description
+///
+/// The EFI_I2C_ENUMERATE_PROTOCOL uses the EFI_I2C_DEVICE to describe
+/// the platform specific details associated with an I2C device. This
+/// description is passed to the I2C bus driver during enumeration where
+/// it is made available to the third party I2C device driver via the
+/// EFI_I2C_IO_PROTOCOL.
+///
+typedef struct {
+ ///
+ /// Unique value assigned by the silicon manufacture or the third
+ /// party I2C driver writer for the I2C part. This value logically
+ /// combines both the manufacture name and the I2C part number into
+ /// a single value specified as a GUID.
+ ///
+ CONST EFI_GUID *DeviceGuid;
+
+ ///
+ /// Unique ID of the I2C part within the system
+ ///
+ UINT32 DeviceIndex;
+
+ ///
+ /// Hardware revision - ACPI _HRV value. See the Advanced
+ /// Configuration and Power Interface Specification, Revision 5.0
+ /// for the field format and the Plug and play support for I2C
+ /// web-page for restriction on values.
+ ///
+ /// http://www.acpi.info/spec.htm
+ /// http://msdn.microsoft.com/en-us/library/windows/hardware/jj131711(v=vs.85).aspx
+ ///
+ UINT32 HardwareRevision;
+
+ ///
+ /// I2C bus configuration for the I2C device
+ ///
+ UINT32 I2cBusConfiguration;
+
+ ///
+ /// Number of slave addresses for the I2C device.
+ ///
+ UINT32 SlaveAddressCount;
+
+ ///
+ /// Pointer to the array of slave addresses for the I2C device.
+ ///
+ CONST UINT32 *SlaveAddressArray;
+} EFI_I2C_DEVICE;
+
+///
+/// Define the I2C flags
+///
+/// I2C read operation when set
+#define I2C_FLAG_READ 0x00000001
+
+///
+/// Define the flags for SMBus operation
+///
+/// The following flags are also present in only the first I2C operation
+/// and are ignored when present in other operations. These flags
+/// describe a particular SMB transaction as shown in the following table.
+///
+
+/// SMBus operation
+#define I2C_FLAG_SMBUS_OPERATION 0x00010000
+
+/// SMBus block operation
+/// The flag I2C_FLAG_SMBUS_BLOCK causes the I2C master protocol to update
+/// the LengthInBytes field of the operation in the request packet with
+/// the actual number of bytes read or written. These values are only
+/// valid when the entire I2C transaction is successful.
+/// This flag also changes the LengthInBytes meaning to be: A maximum
+/// of LengthInBytes is to be read from the device. The first byte
+/// read contains the number of bytes remaining to be read, plus an
+/// optional PEC value.
+#define I2C_FLAG_SMBUS_BLOCK 0x00020000
+
+/// SMBus process call operation
+#define I2C_FLAG_SMBUS_PROCESS_CALL 0x00040000
+
+/// SMBus use packet error code (PEC)
+/// Note that the I2C master protocol may clear the I2C_FLAG_SMBUS_PEC bit
+/// to indicate that the PEC value was checked by the hardware and is
+/// not appended to the returned read data.
+///
+#define I2C_FLAG_SMBUS_PEC 0x00080000
+
+// ----------------------------------------------------------------------
+///
+/// QuickRead: OperationCount=1,
+/// LengthInBytes=0, Flags=I2C_FLAG_READ
+/// QuickWrite: OperationCount=1,
+/// LengthInBytes=0, Flags=0
+///
+///
+/// ReceiveByte: OperationCount=1,
+/// LengthInBytes=1, Flags=I2C_FLAG_SMBUS_OPERATION
+/// | I2C_FLAG_READ
+/// ReceiveByte+PEC: OperationCount=1,
+/// LengthInBytes=2, Flags=I2C_FLAG_SMBUS_OPERATION
+/// | I2C_FLAG_READ
+/// | I2C_FLAG_SMBUS_PEC
+///
+///
+/// SendByte: OperationCount=1,
+/// LengthInBytes=1, Flags=I2C_FLAG_SMBUS_OPERATION
+/// SendByte+PEC: OperationCount=1,
+/// LengthInBytes=2, Flags=I2C_FLAG_SMBUS_OPERATION
+/// | I2C_FLAG_SMBUS_PEC
+///
+///
+/// ReadDataByte: OperationCount=2,
+/// LengthInBytes=1, Flags=I2C_FLAG_SMBUS_OPERATION
+/// LengthInBytes=1, Flags=I2C_FLAG_READ
+/// ReadDataByte+PEC: OperationCount=2,
+/// LengthInBytes=1, Flags=I2C_FLAG_SMBUS_OPERATION
+/// | I2C_FLAG_SMBUS_PEC
+/// LengthInBytes=2, Flags=I2C_FLAG_READ
+///
+///
+/// WriteDataByte: OperationCount=1,
+/// LengthInBytes=2, Flags=I2C_FLAG_SMBUS_OPERATION
+/// WriteDataByte+PEC: OperationCount=1,
+/// LengthInBytes=3, Flags=I2C_FLAG_SMBUS_OPERATION
+/// | I2C_FLAG_SMBUS_PEC
+///
+///
+/// ReadDataWord: OperationCount=2,
+/// LengthInBytes=1, Flags=I2C_FLAG_SMBUS_OPERATION
+/// LengthInBytes=2, Flags=I2C_FLAG_READ
+/// ReadDataWord+PEC: OperationCount=2,
+/// LengthInBytes=1, Flags=I2C_FLAG_SMBUS_OPERATION
+/// | I2C_FLAG_SMBUS_PEC
+/// LengthInBytes=3, Flags=I2C_FLAG_READ
+///
+///
+/// WriteDataWord: OperationCount=1,
+/// LengthInBytes=3, Flags=I2C_FLAG_SMBUS_OPERATION
+/// WriteDataWord+PEC: OperationCount=1,
+/// LengthInBytes=4, Flags=I2C_FLAG_SMBUS_OPERATION
+/// | I2C_FLAG_SMBUS_PEC
+///
+///
+/// ReadBlock: OperationCount=2,
+/// LengthInBytes=1, Flags=I2C_FLAG_SMBUS_OPERATION
+/// | I2C_FLAG_SMBUS_BLOCK
+/// LengthInBytes=33, Flags=I2C_FLAG_READ
+/// ReadBlock+PEC: OperationCount=2,
+/// LengthInBytes=1, Flags=I2C_FLAG_SMBUS_OPERATION
+/// | I2C_FLAG_SMBUS_BLOCK
+/// | I2C_FLAG_SMBUS_PEC
+/// LengthInBytes=34, Flags=I2C_FLAG_READ
+///
+///
+/// WriteBlock: OperationCount=1,
+/// LengthInBytes=N+2, Flags=I2C_FLAG_SMBUS_OPERATION
+/// | I2C_FLAG_SMBUS_BLOCK
+/// WriteBlock+PEC: OperationCount=1,
+/// LengthInBytes=N+3, Flags=I2C_FLAG_SMBUS_OPERATION
+/// | I2C_FLAG_SMBUS_BLOCK
+/// | I2C_FLAG_SMBUS_PEC
+///
+///
+/// ProcessCall: OperationCount=2,
+/// LengthInBytes=3, Flags=I2C_FLAG_SMBUS_OPERATION
+/// | I2C_FLAG_SMBUS_PROCESS_CALL
+/// LengthInBytes=2, Flags=I2C_FLAG_READ
+/// ProcessCall+PEC: OperationCount=2,
+/// LengthInBytes=3, Flags=I2C_FLAG_SMBUS_OPERATION
+/// | I2C_FLAG_SMBUS_PROCESS_CALL
+/// | I2C_FLAG_SMBUS_PEC
+/// LengthInBytes=3, Flags=I2C_FLAG_READ
+///
+///
+/// BlkProcessCall: OperationCount=2,
+/// LengthInBytes=N+2, Flags=I2C_FLAG_SMBUS_OPERATION
+/// | I2C_FLAG_SMBUS_PROCESS_CALL
+/// | I2C_FLAG_SMBUS_BLOCK
+/// LengthInBytes=33, Flags=I2C_FLAG_READ
+/// BlkProcessCall+PEC: OperationCount=2,
+/// LengthInBytes=N+2, Flags=I2C_FLAG_SMBUS_OPERATION
+/// | I2C_FLAG_SMBUS_PROCESS_CALL
+/// | I2C_FLAG_SMBUS_BLOCK
+/// | I2C_FLAG_SMBUS_PEC
+/// LengthInBytes=34, Flags=I2C_FLAG_READ
+///
+// ----------------------------------------------------------------------
+
+///
+/// I2C device operation
+///
+/// The EFI_I2C_OPERATION describes a subset of an I2C transaction in which
+/// the I2C controller is either sending or receiving bytes from the bus.
+/// Some transactions will consist of a single operation while others will
+/// be two or more.
+///
+/// Note: Some I2C controllers do not support read or write ping (address
+/// only) operation and will return EFI_UNSUPPORTED status when these
+/// operations are requested.
+///
+/// Note: I2C controllers which do not support complex transactions requiring
+/// multiple repeated start bits return EFI_UNSUPPORTED without processing
+/// any of the transaction.
+///
+typedef struct {
+ ///
+ /// Flags to qualify the I2C operation.
+ ///
+ UINT32 Flags;
+
+ ///
+ /// Number of bytes to send to or receive from the I2C device. A ping
+ /// (address only byte/bytes) is indicated by setting the LengthInBytes
+ /// to zero.
+ ///
+ UINT32 LengthInBytes;
+
+ ///
+ /// Pointer to a buffer containing the data to send or to receive from
+ /// the I2C device. The Buffer must be at least LengthInBytes in size.
+ ///
+ UINT8 *Buffer;
+} EFI_I2C_OPERATION;
+
+///
+/// I2C device request
+///
+/// The EFI_I2C_REQUEST_PACKET describes a single I2C transaction. The
+/// transaction starts with a start bit followed by the first operation
+/// in the operation array. Subsequent operations are separated with
+/// repeated start bits and the last operation is followed by a stop bit
+/// which concludes the transaction. Each operation is described by one
+/// of the elements in the Operation array.
+///
+typedef struct {
+ ///
+ /// Number of elements in the operation array
+ ///
+ UINTN OperationCount;
+
+ ///
+ /// Description of the I2C operation
+ ///
+ EFI_I2C_OPERATION Operation[1];
+} EFI_I2C_REQUEST_PACKET;
+
+#endif // __PI_I2C_H__
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Pi/PiMmCis.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Pi/PiMmCis.h
new file mode 100644
index 0000000000..10ff02c1b4
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Pi/PiMmCis.h
@@ -0,0 +1,345 @@
+/** @file
+ Common definitions in the Platform Initialization Specification version 1.5
+ VOLUME 4 Management Mode Core Interface version.
+
+ Copyright (c) 2017, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _PI_MMCIS_H_
+#define _PI_MMCIS_H_
+
+#include
+#include
+
+typedef struct _EFI_MM_SYSTEM_TABLE EFI_MM_SYSTEM_TABLE;
+
+///
+/// The Management Mode System Table (MMST) signature
+///
+#define MM_MMST_SIGNATURE SIGNATURE_32 ('S', 'M', 'S', 'T')
+///
+/// The Management Mode System Table (MMST) revision is 1.6
+///
+#define MM_SPECIFICATION_MAJOR_REVISION 1
+#define MM_SPECIFICATION_MINOR_REVISION 60
+#define EFI_MM_SYSTEM_TABLE_REVISION ((MM_SPECIFICATION_MAJOR_REVISION<<16) | (MM_SPECIFICATION_MINOR_REVISION))
+
+/**
+ Adds, updates, or removes a configuration table entry from the Management Mode System Table.
+
+ The MmInstallConfigurationTable() function is used to maintain the list
+ of configuration tables that are stored in the Management Mode System
+ Table. The list is stored as an array of (GUID, Pointer) pairs. The list
+ must be allocated from pool memory with PoolType set to EfiRuntimeServicesData.
+
+ @param[in] SystemTable A pointer to the MM System Table (MMST).
+ @param[in] Guid A pointer to the GUID for the entry to add, update, or remove.
+ @param[in] Table A pointer to the buffer of the table to add.
+ @param[in] TableSize The size of the table to install.
+
+ @retval EFI_SUCCESS The (Guid, Table) pair was added, updated, or removed.
+ @retval EFI_INVALID_PARAMETER Guid is not valid.
+ @retval EFI_NOT_FOUND An attempt was made to delete a non-existent entry.
+ @retval EFI_OUT_OF_RESOURCES There is not enough memory available to complete the operation.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_MM_INSTALL_CONFIGURATION_TABLE)(
+ IN CONST EFI_MM_SYSTEM_TABLE *SystemTable,
+ IN CONST EFI_GUID *Guid,
+ IN VOID *Table,
+ IN UINTN TableSize
+ );
+
+/**
+ This service lets the caller to get one distinct application processor (AP) to execute
+ a caller-provided code stream while in MM.
+
+ @param[in] Procedure A pointer to the code stream to be run on the designated
+ AP of the system.
+ @param[in] CpuNumber The zero-based index of the processor number of the AP
+ on which the code stream is supposed to run.
+ @param[in,out] ProcArguments Allows the caller to pass a list of parameters to the code
+ that is run by the AP.
+
+ @retval EFI_SUCCESS The call was successful and the return parameters are valid.
+ @retval EFI_INVALID_PARAMETER The input arguments are out of range.
+ @retval EFI_INVALID_PARAMETER The CPU requested is not available on this SMI invocation.
+ @retval EFI_INVALID_PARAMETER The CPU cannot support an additional service invocation.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_MM_STARTUP_THIS_AP)(
+ IN EFI_AP_PROCEDURE Procedure,
+ IN UINTN CpuNumber,
+ IN OUT VOID *ProcArguments OPTIONAL
+ );
+
+/**
+ Function prototype for protocol install notification.
+
+ @param[in] Protocol Points to the protocol's unique identifier.
+ @param[in] Interface Points to the interface instance.
+ @param[in] Handle The handle on which the interface was installed.
+
+ @return Status Code
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_MM_NOTIFY_FN)(
+ IN CONST EFI_GUID *Protocol,
+ IN VOID *Interface,
+ IN EFI_HANDLE Handle
+ );
+
+/**
+ Register a callback function be called when a particular protocol interface is installed.
+
+ The MmRegisterProtocolNotify() function creates a registration Function that is to be
+ called whenever a protocol interface is installed for Protocol by
+ MmInstallProtocolInterface().
+ If Function == NULL and Registration is an existing registration, then the callback is unhooked.
+
+ @param[in] Protocol The unique ID of the protocol for which the event is to be registered.
+ @param[in] Function Points to the notification function.
+ @param[out] Registration A pointer to a memory location to receive the registration value.
+
+ @retval EFI_SUCCESS Successfully returned the registration record
+ that has been added or unhooked.
+ @retval EFI_INVALID_PARAMETER Protocol is NULL or Registration is NULL.
+ @retval EFI_OUT_OF_RESOURCES Not enough memory resource to finish the request.
+ @retval EFI_NOT_FOUND If the registration is not found when Function == NULL.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_MM_REGISTER_PROTOCOL_NOTIFY)(
+ IN CONST EFI_GUID *Protocol,
+ IN EFI_MM_NOTIFY_FN Function,
+ OUT VOID **Registration
+ );
+
+/**
+ Manage MMI of a particular type.
+
+ @param[in] HandlerType Points to the handler type or NULL for root MMI handlers.
+ @param[in] Context Points to an optional context buffer.
+ @param[in,out] CommBuffer Points to the optional communication buffer.
+ @param[in,out] CommBufferSize Points to the size of the optional communication buffer.
+
+ @retval EFI_WARN_INTERRUPT_SOURCE_PENDING Interrupt source was processed successfully but not quiesced.
+ @retval EFI_INTERRUPT_PENDING One or more SMI sources could not be quiesced.
+ @retval EFI_NOT_FOUND Interrupt source was not handled or quiesced.
+ @retval EFI_SUCCESS Interrupt source was handled and quiesced.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_MM_INTERRUPT_MANAGE)(
+ IN CONST EFI_GUID *HandlerType,
+ IN CONST VOID *Context OPTIONAL,
+ IN OUT VOID *CommBuffer OPTIONAL,
+ IN OUT UINTN *CommBufferSize OPTIONAL
+ );
+
+/**
+ Main entry point for an MM handler dispatch or communicate-based callback.
+
+ @param[in] DispatchHandle The unique handle assigned to this handler by MmiHandlerRegister().
+ @param[in] Context Points to an optional handler context which was specified when the
+ handler was registered.
+ @param[in,out] CommBuffer A pointer to a collection of data in memory that will
+ be conveyed from a non-MM environment into an MM environment.
+ @param[in,out] CommBufferSize The size of the CommBuffer.
+
+ @retval EFI_SUCCESS The interrupt was handled and quiesced. No other handlers
+ should still be called.
+ @retval EFI_WARN_INTERRUPT_SOURCE_QUIESCED The interrupt has been quiesced but other handlers should
+ still be called.
+ @retval EFI_WARN_INTERRUPT_SOURCE_PENDING The interrupt is still pending and other handlers should still
+ be called.
+ @retval EFI_INTERRUPT_PENDING The interrupt could not be quiesced.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_MM_HANDLER_ENTRY_POINT)(
+ IN EFI_HANDLE DispatchHandle,
+ IN CONST VOID *Context OPTIONAL,
+ IN OUT VOID *CommBuffer OPTIONAL,
+ IN OUT UINTN *CommBufferSize OPTIONAL
+ );
+
+/**
+ Registers a handler to execute within MM.
+
+ @param[in] Handler Handler service function pointer.
+ @param[in] HandlerType Points to the handler type or NULL for root MMI handlers.
+ @param[out] DispatchHandle On return, contains a unique handle which can be used to later
+ unregister the handler function.
+
+ @retval EFI_SUCCESS MMI handler added successfully.
+ @retval EFI_INVALID_PARAMETER Handler is NULL or DispatchHandle is NULL.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_MM_INTERRUPT_REGISTER)(
+ IN EFI_MM_HANDLER_ENTRY_POINT Handler,
+ IN CONST EFI_GUID *HandlerType OPTIONAL,
+ OUT EFI_HANDLE *DispatchHandle
+ );
+
+/**
+ Unregister a handler in MM.
+
+ @param[in] DispatchHandle The handle that was specified when the handler was registered.
+
+ @retval EFI_SUCCESS Handler function was successfully unregistered.
+ @retval EFI_INVALID_PARAMETER DispatchHandle does not refer to a valid handle.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_MM_INTERRUPT_UNREGISTER)(
+ IN EFI_HANDLE DispatchHandle
+ );
+
+///
+/// Processor information and functionality needed by MM Foundation.
+///
+typedef struct _EFI_MM_ENTRY_CONTEXT {
+ EFI_MM_STARTUP_THIS_AP MmStartupThisAp;
+ ///
+ /// A number between zero and the NumberOfCpus field. This field designates which
+ /// processor is executing the MM Foundation.
+ ///
+ UINTN CurrentlyExecutingCpu;
+ ///
+ /// The number of possible processors in the platform. This is a 1 based
+ /// counter. This does not indicate the number of processors that entered MM.
+ ///
+ UINTN NumberOfCpus;
+ ///
+ /// Points to an array, where each element describes the number of bytes in the
+ /// corresponding save state specified by CpuSaveState. There are always
+ /// NumberOfCpus entries in the array.
+ ///
+ UINTN *CpuSaveStateSize;
+ ///
+ /// Points to an array, where each element is a pointer to a CPU save state. The
+ /// corresponding element in CpuSaveStateSize specifies the number of bytes in the
+ /// save state area. There are always NumberOfCpus entries in the array.
+ ///
+ VOID **CpuSaveState;
+} EFI_MM_ENTRY_CONTEXT;
+
+/**
+ This function is the main entry point to the MM Foundation.
+
+ @param[in] MmEntryContext Processor information and functionality needed by MM Foundation.
+**/
+typedef
+VOID
+(EFIAPI *EFI_MM_ENTRY_POINT)(
+ IN CONST EFI_MM_ENTRY_CONTEXT *MmEntryContext
+ );
+
+///
+/// Management Mode System Table (MMST)
+///
+/// The Management Mode System Table (MMST) is a table that contains a collection of common
+/// services for managing MMRAM allocation and providing basic I/O services. These services are
+/// intended for both preboot and runtime usage.
+///
+struct _EFI_MM_SYSTEM_TABLE {
+ ///
+ /// The table header for the SMST.
+ ///
+ EFI_TABLE_HEADER Hdr;
+ ///
+ /// A pointer to a NULL-terminated Unicode string containing the vendor name.
+ /// It is permissible for this pointer to be NULL.
+ ///
+ CHAR16 *MmFirmwareVendor;
+ ///
+ /// The particular revision of the firmware.
+ ///
+ UINT32 MmFirmwareRevision;
+
+ EFI_MM_INSTALL_CONFIGURATION_TABLE MmInstallConfigurationTable;
+
+ ///
+ /// I/O Service
+ ///
+ EFI_MM_CPU_IO_PROTOCOL MmIo;
+
+ ///
+ /// Runtime memory services
+ ///
+ EFI_ALLOCATE_POOL MmAllocatePool;
+ EFI_FREE_POOL MmFreePool;
+ EFI_ALLOCATE_PAGES MmAllocatePages;
+ EFI_FREE_PAGES MmFreePages;
+
+ ///
+ /// MP service
+ ///
+ EFI_MM_STARTUP_THIS_AP MmStartupThisAp;
+
+ ///
+ /// CPU information records
+ ///
+
+ ///
+ /// A number between zero and and the NumberOfCpus field. This field designates
+ /// which processor is executing the MM infrastructure.
+ ///
+ UINTN CurrentlyExecutingCpu;
+ ///
+ /// The number of possible processors in the platform. This is a 1 based counter.
+ ///
+ UINTN NumberOfCpus;
+ ///
+ /// Points to an array, where each element describes the number of bytes in the
+ /// corresponding save state specified by CpuSaveState. There are always
+ /// NumberOfCpus entries in the array.
+ ///
+ UINTN *CpuSaveStateSize;
+ ///
+ /// Points to an array, where each element is a pointer to a CPU save state. The
+ /// corresponding element in CpuSaveStateSize specifies the number of bytes in the
+ /// save state area. There are always NumberOfCpus entries in the array.
+ ///
+ VOID **CpuSaveState;
+
+ ///
+ /// Extensibility table
+ ///
+
+ ///
+ /// The number of UEFI Configuration Tables in the buffer MmConfigurationTable.
+ ///
+ UINTN NumberOfTableEntries;
+ ///
+ /// A pointer to the UEFI Configuration Tables. The number of entries in the table is
+ /// NumberOfTableEntries.
+ ///
+ EFI_CONFIGURATION_TABLE *MmConfigurationTable;
+
+ ///
+ /// Protocol services
+ ///
+ EFI_INSTALL_PROTOCOL_INTERFACE MmInstallProtocolInterface;
+ EFI_UNINSTALL_PROTOCOL_INTERFACE MmUninstallProtocolInterface;
+ EFI_HANDLE_PROTOCOL MmHandleProtocol;
+ EFI_MM_REGISTER_PROTOCOL_NOTIFY MmRegisterProtocolNotify;
+ EFI_LOCATE_HANDLE MmLocateHandle;
+ EFI_LOCATE_PROTOCOL MmLocateProtocol;
+
+ ///
+ /// MMI Management functions
+ ///
+ EFI_MM_INTERRUPT_MANAGE MmiManage;
+ EFI_MM_INTERRUPT_REGISTER MmiHandlerRegister;
+ EFI_MM_INTERRUPT_UNREGISTER MmiHandlerUnRegister;
+};
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Pi/PiMultiPhase.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Pi/PiMultiPhase.h
new file mode 100644
index 0000000000..bb01db168c
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Pi/PiMultiPhase.h
@@ -0,0 +1,211 @@
+/** @file
+ Include file matches things in PI for multiple module types.
+
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Revision Reference:
+ These elements are defined in UEFI Platform Initialization Specification 1.2.
+
+**/
+
+#ifndef __PI_MULTIPHASE_H__
+#define __PI_MULTIPHASE_H__
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+/**
+ Produces an error code in the range reserved for use by the Platform Initialization
+ Architecture Specification.
+
+ The supported 32-bit range is 0xA0000000-0xBFFFFFFF
+ The supported 64-bit range is 0xA000000000000000-0xBFFFFFFFFFFFFFFF
+
+ @param StatusCode The status code value to convert into a warning code.
+ StatusCode must be in the range 0x00000000..0x1FFFFFFF.
+
+ @return The value specified by StatusCode in the PI reserved range.
+
+**/
+#define DXE_ERROR(StatusCode) (MAX_BIT | (MAX_BIT >> 2) | StatusCode)
+
+///
+/// If this value is returned by an EFI image, then the image should be unloaded.
+///
+#define EFI_REQUEST_UNLOAD_IMAGE DXE_ERROR (1)
+
+///
+/// If this value is returned by an API, it means the capability is not yet
+/// installed/available/ready to use.
+///
+#define EFI_NOT_AVAILABLE_YET DXE_ERROR (2)
+
+///
+/// Success and warning codes reserved for use by PI.
+/// Supported 32-bit range is 0x20000000-0x3fffffff.
+/// Supported 64-bit range is 0x2000000000000000-0x3fffffffffffffff.
+///
+#define PI_ENCODE_WARNING(a) ((MAX_BIT >> 2) | (a))
+
+///
+/// Error codes reserved for use by PI.
+/// Supported 32-bit range is 0xa0000000-0xbfffffff.
+/// Supported 64-bit range is 0xa000000000000000-0xbfffffffffffffff.
+///
+#define PI_ENCODE_ERROR(a) (MAX_BIT | (MAX_BIT >> 2) | (a))
+
+///
+/// Return status codes defined in SMM CIS.
+///
+#define EFI_INTERRUPT_PENDING PI_ENCODE_ERROR (0)
+
+#define EFI_WARN_INTERRUPT_SOURCE_PENDING PI_ENCODE_WARNING (0)
+#define EFI_WARN_INTERRUPT_SOURCE_QUIESCED PI_ENCODE_WARNING (1)
+
+///
+/// Bitmask of values for Authentication Status.
+/// Authentication Status is returned from EFI_GUIDED_SECTION_EXTRACTION_PROTOCOL
+/// and the EFI_PEI_GUIDED_SECTION_EXTRACTION_PPI
+///
+/// xx00 Image was not signed.
+/// xxx1 Platform security policy override. Assumes the same meaning as 0010 (the image was signed, the
+/// signature was tested, and the signature passed authentication test).
+/// 0010 Image was signed, the signature was tested, and the signature passed authentication test.
+/// 0110 Image was signed and the signature was not tested.
+/// 1010 Image was signed, the signature was tested, and the signature failed the authentication test.
+///
+///@{
+#define EFI_AUTH_STATUS_PLATFORM_OVERRIDE 0x01
+#define EFI_AUTH_STATUS_IMAGE_SIGNED 0x02
+#define EFI_AUTH_STATUS_NOT_TESTED 0x04
+#define EFI_AUTH_STATUS_TEST_FAILED 0x08
+#define EFI_AUTH_STATUS_ALL 0x0f
+///@}
+
+///
+/// MMRAM states and capabilities
+///
+#define EFI_MMRAM_OPEN 0x00000001
+#define EFI_MMRAM_CLOSED 0x00000002
+#define EFI_MMRAM_LOCKED 0x00000004
+#define EFI_CACHEABLE 0x00000008
+#define EFI_ALLOCATED 0x00000010
+#define EFI_NEEDS_TESTING 0x00000020
+#define EFI_NEEDS_ECC_INITIALIZATION 0x00000040
+
+#define EFI_SMRAM_OPEN EFI_MMRAM_OPEN
+#define EFI_SMRAM_CLOSED EFI_MMRAM_CLOSED
+#define EFI_SMRAM_LOCKED EFI_MMRAM_LOCKED
+
+///
+/// Structure describing a MMRAM region and its accessibility attributes.
+///
+typedef struct {
+ ///
+ /// Designates the physical address of the MMRAM in memory. This view of memory is
+ /// the same as seen by I/O-based agents, for example, but it may not be the address seen
+ /// by the processors.
+ ///
+ EFI_PHYSICAL_ADDRESS PhysicalStart;
+ ///
+ /// Designates the address of the MMRAM, as seen by software executing on the
+ /// processors. This address may or may not match PhysicalStart.
+ ///
+ EFI_PHYSICAL_ADDRESS CpuStart;
+ ///
+ /// Describes the number of bytes in the MMRAM region.
+ ///
+ UINT64 PhysicalSize;
+ ///
+ /// Describes the accessibility attributes of the MMRAM. These attributes include the
+ /// hardware state (e.g., Open/Closed/Locked), capability (e.g., cacheable), logical
+ /// allocation (e.g., allocated), and pre-use initialization (e.g., needs testing/ECC
+ /// initialization).
+ ///
+ UINT64 RegionState;
+} EFI_MMRAM_DESCRIPTOR;
+
+typedef EFI_MMRAM_DESCRIPTOR EFI_SMRAM_DESCRIPTOR;
+
+///
+/// Structure describing a MMRAM region which cannot be used for the MMRAM heap.
+///
+typedef struct _EFI_MM_RESERVED_MMRAM_REGION {
+ ///
+ /// Starting address of the reserved MMRAM area, as it appears while MMRAM is open.
+ /// Ignored if MmramReservedSize is 0.
+ ///
+ EFI_PHYSICAL_ADDRESS MmramReservedStart;
+ ///
+ /// Number of bytes occupied by the reserved MMRAM area. A size of zero indicates the
+ /// last MMRAM area.
+ ///
+ UINT64 MmramReservedSize;
+} EFI_MM_RESERVED_MMRAM_REGION;
+
+typedef enum {
+ EFI_PCD_TYPE_8,
+ EFI_PCD_TYPE_16,
+ EFI_PCD_TYPE_32,
+ EFI_PCD_TYPE_64,
+ EFI_PCD_TYPE_BOOL,
+ EFI_PCD_TYPE_PTR
+} EFI_PCD_TYPE;
+
+typedef struct {
+ ///
+ /// The returned information associated with the requested TokenNumber. If
+ /// TokenNumber is 0, then PcdType is set to EFI_PCD_TYPE_8.
+ ///
+ EFI_PCD_TYPE PcdType;
+ ///
+ /// The size of the data in bytes associated with the TokenNumber specified. If
+ /// TokenNumber is 0, then PcdSize is set 0.
+ ///
+ UINTN PcdSize;
+ ///
+ /// The null-terminated ASCII string associated with a given token. If the
+ /// TokenNumber specified was 0, then this field corresponds to the null-terminated
+ /// ASCII string associated with the token's namespace Guid. If NULL, there is no
+ /// name associated with this request.
+ ///
+ CHAR8 *PcdName;
+} EFI_PCD_INFO;
+
+/**
+ The function prototype for invoking a function on an Application Processor.
+
+ This definition is used by the UEFI MP Serices Protocol, and the
+ PI SMM System Table.
+
+ @param[in,out] Buffer The pointer to private data buffer.
+**/
+typedef
+VOID
+(EFIAPI *EFI_AP_PROCEDURE)(
+ IN OUT VOID *Buffer
+ );
+
+/**
+ The function prototype for invoking a function on an Application Processor.
+
+ This definition is used by the UEFI MM MP Serices Protocol.
+
+ @param[in] ProcedureArgument The pointer to private data buffer.
+
+ @retval EFI_SUCCESS Excutive the procedure successfully
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_AP_PROCEDURE2)(
+ IN VOID *ProcedureArgument
+ );
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Pi/PiPeiCis.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Pi/PiPeiCis.h
new file mode 100644
index 0000000000..7271ea954f
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Pi/PiPeiCis.h
@@ -0,0 +1,1056 @@
+/** @file
+ PI PEI master include file. This file should match the PI spec.
+
+Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Revision Reference:
+ PI Version 1.7.
+
+**/
+
+#ifndef __PI_PEICIS_H__
+#define __PI_PEICIS_H__
+
+#include
+#include
+
+///
+/// The handles of EFI FV.
+///
+typedef VOID *EFI_PEI_FV_HANDLE;
+
+///
+/// The handles of EFI FFS.
+///
+typedef VOID *EFI_PEI_FILE_HANDLE;
+
+///
+/// Declare the forward reference data structure for EFI_PEI_SERVICE.
+///
+typedef struct _EFI_PEI_SERVICES EFI_PEI_SERVICES;
+
+///
+/// Declare the forward reference data structure for EFI_PEI_NOTIFY_DESCRIPTOR.
+///
+typedef struct _EFI_PEI_NOTIFY_DESCRIPTOR EFI_PEI_NOTIFY_DESCRIPTOR;
+
+#include
+#include
+
+/**
+ The PEI Dispatcher will invoke each PEIM one time. During this pass, the PEI
+ Dispatcher will pass control to the PEIM at the AddressOfEntryPoint in the PE Header.
+
+ @param FileHandle Pointer to the FFS file header.
+ @param PeiServices Describes the list of possible PEI Services.
+
+ @retval EFI_SUCCESS The PEI completed successfully.
+ @retval !EFI_SUCCESS There is error in PEIM.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_PEIM_ENTRY_POINT2)(
+ IN EFI_PEI_FILE_HANDLE FileHandle,
+ IN CONST EFI_PEI_SERVICES **PeiServices
+ );
+
+/**
+ Entry point of the notification callback function itself within the PEIM.
+
+ @param PeiServices Indirect reference to the PEI Services Table.
+ @param NotifyDescriptor Address of the notification descriptor data structure.
+ @param Ppi Address of the PPI that was installed.
+
+ @return Status of the notification.
+ The status code returned from this function is ignored.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_PEIM_NOTIFY_ENTRY_POINT)(
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
+ IN VOID *Ppi
+ );
+
+//
+// PEI Ppi Services List Descriptors
+//
+#define EFI_PEI_PPI_DESCRIPTOR_PIC 0x00000001
+#define EFI_PEI_PPI_DESCRIPTOR_PPI 0x00000010
+#define EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK 0x00000020
+#define EFI_PEI_PPI_DESCRIPTOR_NOTIFY_DISPATCH 0x00000040
+#define EFI_PEI_PPI_DESCRIPTOR_NOTIFY_TYPES 0x00000060
+#define EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST 0x80000000
+
+///
+/// The data structure through which a PEIM describes available services to the PEI Foundation.
+///
+typedef struct {
+ ///
+ /// This field is a set of flags describing the characteristics of this imported table entry.
+ /// All flags are defined as EFI_PEI_PPI_DESCRIPTOR_***, which can also be combined into one.
+ ///
+ UINTN Flags;
+ ///
+ /// The address of the EFI_GUID that names the interface.
+ ///
+ EFI_GUID *Guid;
+ ///
+ /// A pointer to the PPI. It contains the information necessary to install a service.
+ ///
+ VOID *Ppi;
+} EFI_PEI_PPI_DESCRIPTOR;
+
+///
+/// The data structure in a given PEIM that tells the PEI
+/// Foundation where to invoke the notification service.
+///
+struct _EFI_PEI_NOTIFY_DESCRIPTOR {
+ ///
+ /// Details if the type of notification are callback or dispatch.
+ ///
+ UINTN Flags;
+ ///
+ /// The address of the EFI_GUID that names the interface.
+ ///
+ EFI_GUID *Guid;
+ ///
+ /// Address of the notification callback function itself within the PEIM.
+ ///
+ EFI_PEIM_NOTIFY_ENTRY_POINT Notify;
+};
+
+///
+/// This data structure is the means by which callable services are installed and
+/// notifications are registered in the PEI phase.
+///
+typedef union {
+ ///
+ /// The typedef structure of the notification descriptor.
+ ///
+ EFI_PEI_NOTIFY_DESCRIPTOR Notify;
+ ///
+ /// The typedef structure of the PPI descriptor.
+ ///
+ EFI_PEI_PPI_DESCRIPTOR Ppi;
+} EFI_PEI_DESCRIPTOR;
+
+/**
+ This service is the first one provided by the PEI Foundation. This function
+ installs an interface in the PEI PPI database by GUID. The purpose of the
+ service is to publish an interface that other parties can use to call
+ additional PEIMs.
+
+ @param PeiServices An indirect pointer to the EFI_PEI_SERVICES table
+ published by the PEI Foundation.
+ @param PpiList A pointer to the list of interfaces that the caller shall install.
+
+ @retval EFI_SUCCESS The interface was successfully installed.
+ @retval EFI_INVALID_PARAMETER The PpiList pointer is NULL or Any of the PEI PPI
+ descriptors in the list do not have the
+ EFI_PEI_PPI_DESCRIPTOR_PPI bit set in the Flags field.
+ @retval EFI_OUT_OF_RESOURCES There is no additional space in the PPI database.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_PEI_INSTALL_PPI)(
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN CONST EFI_PEI_PPI_DESCRIPTOR *PpiList
+ );
+
+/**
+ This function reinstalls an interface in the PEI PPI database by GUID.
+ The purpose of the service is to publish an interface that other parties
+ can use to replace a same-named interface in the protocol database
+ with a different interface.
+
+ @param PeiServices An indirect pointer to the EFI_PEI_SERVICES table
+ published by the PEI Foundation.
+ @param OldPpi A pointer to the former PPI in the database.
+ @param NewPpi A pointer to the new interfaces that the caller shall install.
+
+ @retval EFI_SUCCESS The interface was successfully installed.
+ @retval EFI_INVALID_PARAMETER The PpiList pointer is NULL or Any of the PEI PPI descriptors in the
+ list do not have the EFI_PEI_PPI_DESCRIPTOR_PPI bit set in the Flags field.
+ @retval EFI_OUT_OF_RESOURCES There is no additional space in the PPI database.
+ @retval EFI_NOT_FOUND The PPI for which the reinstallation was requested has not been installed.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_PEI_REINSTALL_PPI)(
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN CONST EFI_PEI_PPI_DESCRIPTOR *OldPpi,
+ IN CONST EFI_PEI_PPI_DESCRIPTOR *NewPpi
+ );
+
+/**
+ This function locates an interface in the PEI PPI database by GUID.
+
+ @param PeiServices An indirect pointer to the EFI_PEI_SERVICES published by the PEI Foundation.
+ @param Guid A pointer to the GUID whose corresponding interface needs to be found.
+ @param Instance The N-th instance of the interface that is required.
+ @param PpiDescriptor A pointer to instance of the EFI_PEI_PPI_DESCRIPTOR.
+ @param Ppi A pointer to the instance of the interface.
+
+ @retval EFI_SUCCESS The interface was successfully returned.
+ @retval EFI_NOT_FOUND The PPI descriptor is not found in the database.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_PEI_LOCATE_PPI)(
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN CONST EFI_GUID *Guid,
+ IN UINTN Instance,
+ IN OUT EFI_PEI_PPI_DESCRIPTOR **PpiDescriptor OPTIONAL,
+ IN OUT VOID **Ppi
+ );
+
+/**
+ This function installs a notification service to be called back when a
+ given interface is installed or reinstalled. The purpose of the service
+ is to publish an interface that other parties can use to call additional PPIs
+ that may materialize later.
+
+ @param PeiServices An indirect pointer to the EFI_PEI_SERVICES table published by the PEI Foundation
+ @param NotifyList A pointer to the list of notification interfaces that the caller shall install.
+
+ @retval EFI_SUCCESS The interface was successfully installed.
+ @retval EFI_INVALID_PARAMETER The PpiList pointer is NULL, or any of the PEI PPI descriptors in the
+ list do not have the EFI_PEI_PPI_DESCRIPTOR_NOTIFY_TYPES bit set in the Flags field.
+ @retval EFI_OUT_OF_RESOURCES There is no additional space in the PPI database.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_PEI_NOTIFY_PPI)(
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN CONST EFI_PEI_NOTIFY_DESCRIPTOR *NotifyList
+ );
+
+/**
+ This function returns the present value of the boot mode.
+
+ @param PeiServices An indirect pointer to the EFI_PEI_SERVICES table published by the PEI Foundation.
+ @param BootMode A pointer to contain the value of the boot mode.
+
+ @retval EFI_SUCCESS The boot mode returned successfully.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_PEI_GET_BOOT_MODE)(
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ OUT EFI_BOOT_MODE *BootMode
+ );
+
+/**
+ This function sets the value of the boot mode.
+
+ @param PeiServices An indirect pointer to the EFI_PEI_SERVICES table published by the PEI Foundation
+ @param BootMode The value of the boot mode to set.
+
+ @retval EFI_SUCCESS The boot mode returned successfully.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_PEI_SET_BOOT_MODE)(
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN EFI_BOOT_MODE BootMode
+ );
+
+/**
+ This function returns the pointer to the list of Hand-Off Blocks (HOBs) in memory.
+
+ @param PeiServices An indirect pointer to the EFI_PEI_SERVICES table published by the PEI Foundation
+ @param HobList A pointer to the list of HOBs that the PEI Foundation will initialize
+
+ @retval EFI_SUCCESS The list was successfully returned.
+ @retval EFI_NOT_AVAILABLE_YET The HOB list is not yet published.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_PEI_GET_HOB_LIST)(
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ OUT VOID **HobList
+ );
+
+/**
+ This service, published by the PEI Foundation, abstracts the creation of a Hand-Off Block's (HOB's) headers.
+
+ @param PeiServices An indirect pointer to the EFI_PEI_SERVICES table published by the PEI Foundation.
+ @param Type The type of HOB to be installed.
+ @param Length The length of the HOB to be added.
+ @param Hob The address of a pointer that will contain the HOB header.
+
+ @retval EFI_SUCCESS The HOB was successfully created.
+ @retval EFI_OUT_OF_RESOURCES There is no additional space for HOB creation.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_PEI_CREATE_HOB)(
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN UINT16 Type,
+ IN UINT16 Length,
+ IN OUT VOID **Hob
+ );
+
+/**
+ The purpose of the service is to abstract the capability of the PEI
+ Foundation to discover instances of firmware volumes in the system.
+
+ This service enables PEIMs to discover additional firmware volumes. The PEI Foundation uses this
+ service to abstract the locations and formats of various firmware volumes. These volumes include
+ the Boot Firmware Volume and any other volumes exposed by EFI_PEI_FV_PPI. The service
+ returns a volume handle of type EFI_PEI_FV_HANDLE, which must be unique within the system.
+
+ @param PeiServices An indirect pointer to the EFI_PEI_SERVICES table published by the PEI Foundation.
+ @param Instance This instance of the firmware volume to find.
+ The value 0 is the Boot Firmware Volume (BFV).
+ @param VolumeHandle On exit, points to the next volumn handle or NULL if it does not exist.
+
+ @retval EFI_SUCCESS The volume was found.
+ @retval EFI_NOT_FOUND The volume was not found.
+ @retval EFI_INVALID_PARAMETER VolumeHandle is NULL.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_PEI_FFS_FIND_NEXT_VOLUME2)(
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN UINTN Instance,
+ OUT EFI_PEI_FV_HANDLE *VolumeHandle
+ );
+
+/**
+ Searches for the next matching file in the firmware volume.
+
+ This service enables PEIMs to discover firmware files within a specified volume.
+ To find the first instance of a firmware file, pass a FileHandle value of NULL into the service.
+ The service returns a file handle of type EFI_PEI_FILE_HANDLE, which must be unique within
+ the system.
+
+ @param PeiServices An indirect pointer to the EFI_PEI_SERVICES table published by the PEI Foundation.
+ @param SearchType A filter to find files only of this type.
+ @param FvHandle Handle of firmware volume in which to search.
+ @param FileHandle On entry, points to the current handle from which to begin searching
+ or NULL to start at the beginning of the firmware volume.
+ On exit, points the file handle of the next file in the volume or NULL
+ if there are no more files.
+
+ @retval EFI_SUCCESS The file was found.
+ @retval EFI_NOT_FOUND The file was not found.
+ @retval EFI_NOT_FOUND The header checksum was not zero.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_PEI_FFS_FIND_NEXT_FILE2)(
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN EFI_FV_FILETYPE SearchType,
+ IN CONST EFI_PEI_FV_HANDLE FvHandle,
+ IN OUT EFI_PEI_FILE_HANDLE *FileHandle
+ );
+
+/**
+ Searches for the next matching section within the specified file.
+
+ This service enables PEI modules to discover the first section of a given type within a valid file.
+ This service will search within encapsulation sections (compression and GUIDed) as well. It will
+ search inside of a GUIDed section or a compressed section, but may not, for example, search a
+ GUIDed section inside a GUIDes section.
+ This service will not search within compression sections or GUIDed sections that require
+ extraction if memory is not present.
+
+ @param PeiServices An indirect pointer to the EFI_PEI_SERVICES table published by the PEI Foundation.
+ @param SectionType The value of the section type to find.
+ @param FileHandle Handle of the firmware file to search.
+ @param SectionData A pointer to the discovered section, if successful.
+
+ @retval EFI_SUCCESS The section was found.
+ @retval EFI_NOT_FOUND The section was not found.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_PEI_FFS_FIND_SECTION_DATA2)(
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN EFI_SECTION_TYPE SectionType,
+ IN EFI_PEI_FILE_HANDLE FileHandle,
+ OUT VOID **SectionData
+ );
+
+/**
+ Searches for the next matching section within the specified file.
+
+ This service enables PEI modules to discover the section of a given type within a valid file.
+ This service will search within encapsulation sections (compression and GUIDed) as well. It will
+ search inside of a GUIDed section or a compressed section, but may not, for example, search a
+ GUIDed section inside a GUIDes section.
+ This service will not search within compression sections or GUIDed sections that require
+ extraction if memory is not present.
+
+ @param PeiServices An indirect pointer to the EFI_PEI_SERVICES table published by the PEI Foundation.
+ @param SectionType The value of the section type to find.
+ @param SectionInstance Section instance to find.
+ @param FileHandle Handle of the firmware file to search.
+ @param SectionData A pointer to the discovered section, if successful.
+ @param AuthenticationStatus A pointer to the authentication status for this section.
+
+ @retval EFI_SUCCESS The section was found.
+ @retval EFI_NOT_FOUND The section was not found.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_PEI_FFS_FIND_SECTION_DATA3)(
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN EFI_SECTION_TYPE SectionType,
+ IN UINTN SectionInstance,
+ IN EFI_PEI_FILE_HANDLE FileHandle,
+ OUT VOID **SectionData,
+ OUT UINT32 *AuthenticationStatus
+ );
+
+/**
+ This function registers the found memory configuration with the PEI Foundation.
+
+ @param PeiServices An indirect pointer to the EFI_PEI_SERVICES table published by the PEI Foundation.
+ @param MemoryBegin The value of a region of installed memory.
+ @param MemoryLength The corresponding length of a region of installed memory.
+
+ @retval EFI_SUCCESS The region was successfully installed in a HOB.
+ @retval EFI_INVALID_PARAMETER MemoryBegin and MemoryLength are illegal for this system.
+ @retval EFI_OUT_OF_RESOURCES There is no additional space for HOB creation.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_PEI_INSTALL_PEI_MEMORY)(
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PHYSICAL_ADDRESS MemoryBegin,
+ IN UINT64 MemoryLength
+ );
+
+/**
+ The purpose of the service is to publish an interface that allows
+ PEIMs to allocate memory ranges that are managed by the PEI Foundation.
+
+ Prior to InstallPeiMemory() being called, PEI will allocate pages from the heap.
+ After InstallPeiMemory() is called, PEI will allocate pages within the region
+ of memory provided by InstallPeiMemory() service in a best-effort fashion.
+ Location-specific allocations are not managed by the PEI foundation code.
+
+ @param PeiServices An indirect pointer to the EFI_PEI_SERVICES table published by the PEI Foundation.
+ @param MemoryType The type of memory to allocate.
+ @param Pages The number of contiguous 4 KB pages to allocate.
+ @param Memory A pointer to a physical address. On output, the address is set to the base
+ of the page range that was allocated.
+
+ @retval EFI_SUCCESS The memory range was successfully allocated.
+ @retval EFI_OUT_OF_RESOURCES The pages could not be allocated.
+ @retval EFI_INVALID_PARAMETER The type is not equal to EfiLoaderCode, EfiLoaderData, EfiRuntimeServicesCode,
+ EfiRuntimeServicesData, EfiBootServicesCode, EfiBootServicesData,
+ EfiACPIReclaimMemory, EfiReservedMemoryType, or EfiACPIMemoryNVS.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_PEI_ALLOCATE_PAGES)(
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN EFI_MEMORY_TYPE MemoryType,
+ IN UINTN Pages,
+ OUT EFI_PHYSICAL_ADDRESS *Memory
+ );
+
+/**
+ Frees memory pages.
+
+ @param[in] PeiServices An indirect pointer to the EFI_PEI_SERVICES table published by the PEI Foundation.
+ @param[in] Memory The base physical address of the pages to be freed.
+ @param[in] Pages The number of contiguous 4 KB pages to free.
+
+ @retval EFI_SUCCESS The requested pages were freed.
+ @retval EFI_INVALID_PARAMETER Memory is not a page-aligned address or Pages is invalid.
+ @retval EFI_NOT_FOUND The requested memory pages were not allocated with
+ AllocatePages().
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_PEI_FREE_PAGES)(
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PHYSICAL_ADDRESS Memory,
+ IN UINTN Pages
+ );
+
+/**
+ The purpose of this service is to publish an interface that
+ allows PEIMs to allocate memory ranges that are managed by the PEI Foundation.
+
+ @param PeiServices An indirect pointer to the EFI_PEI_SERVICES table published by the PEI Foundation.
+ @param Size The number of bytes to allocate from the pool.
+ @param Buffer If the call succeeds, a pointer to a pointer to the allocated buffer; undefined otherwise.
+
+ @retval EFI_SUCCESS The allocation was successful.
+ @retval EFI_OUT_OF_RESOURCES There is not enough heap to allocate the requested size.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_PEI_ALLOCATE_POOL)(
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN UINTN Size,
+ OUT VOID **Buffer
+ );
+
+/**
+ This service copies the contents of one buffer to another buffer.
+
+ @param Destination The pointer to the destination buffer of the memory copy.
+ @param Source The pointer to the source buffer of the memory copy.
+ @param Length The number of bytes to copy from Source to Destination.
+
+**/
+typedef
+VOID
+(EFIAPI *EFI_PEI_COPY_MEM)(
+ IN VOID *Destination,
+ IN VOID *Source,
+ IN UINTN Length
+ );
+
+/**
+ The service fills a buffer with a specified value.
+
+ @param Buffer The pointer to the buffer to fill.
+ @param Size The number of bytes in Buffer to fill.
+ @param Value The value to fill Buffer with.
+
+**/
+typedef
+VOID
+(EFIAPI *EFI_PEI_SET_MEM)(
+ IN VOID *Buffer,
+ IN UINTN Size,
+ IN UINT8 Value
+ );
+
+/**
+ This service publishes an interface that allows PEIMs to report status codes.
+
+ ReportStatusCode() is called by PEIMs that wish to report status information on their
+ progress. The principal use model is for a PEIM to emit one of the standard 32-bit error codes. This
+ will allow a platform owner to ascertain the state of the system, especially under conditions where
+ the full consoles might not have been installed.
+
+ @param PeiServices An indirect pointer to the EFI_PEI_SERVICES table published by the PEI Foundation.
+ @param Type Indicates the type of status code being reported.
+ @param Value Describes the current status of a hardware or
+ software entity. This includes information about the class and
+ subclass that is used to classify the entity as well as an operation.
+ For progress codes, the operation is the current activity.
+ For error codes, it is the exception.For debug codes,it is not defined at this time.
+ @param Instance The enumeration of a hardware or software entity within
+ the system. A system may contain multiple entities that match a class/subclass
+ pairing. The instance differentiates between them. An instance of 0 indicates
+ that instance information is unavailable, not meaningful, or not relevant.
+ Valid instance numbers start with 1.
+ @param CallerId This optional parameter may be used to identify the caller.
+ This parameter allows the status code driver to apply different rules to
+ different callers.
+ @param Data This optional parameter may be used to pass additional data.
+
+ @retval EFI_SUCCESS The function completed successfully.
+ @retval EFI_NOT_AVAILABLE_YET No progress code provider has installed an interface in the system.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_PEI_REPORT_STATUS_CODE)(
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN EFI_STATUS_CODE_TYPE Type,
+ IN EFI_STATUS_CODE_VALUE Value,
+ IN UINT32 Instance,
+ IN CONST EFI_GUID *CallerId OPTIONAL,
+ IN CONST EFI_STATUS_CODE_DATA *Data OPTIONAL
+ );
+
+/**
+ Resets the entire platform.
+
+ This service resets the entire platform, including all processors
+ and devices, and reboots the system.
+ This service will never return EFI_SUCCESS.
+
+ @param PeiServices An indirect pointer to the EFI_PEI_SERVICES
+ table published by the PEI Foundation.
+
+ @retval EFI_NOT_AVAILABLE_YET The service has not been installed yet.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_PEI_RESET_SYSTEM)(
+ IN CONST EFI_PEI_SERVICES **PeiServices
+ );
+
+/**
+ Resets the entire platform.
+
+ @param[in] ResetType The type of reset to perform.
+ @param[in] ResetStatus The status code for the reset.
+ @param[in] DataSize The size, in bytes, of ResetData.
+ @param[in] ResetData For a ResetType of EfiResetCold, EfiResetWarm, or EfiResetShutdown
+ the data buffer starts with a Null-terminated string, optionally
+ followed by additional binary data. The string is a description
+ that the caller may use to further indicate the reason for the
+ system reset.
+
+**/
+typedef
+VOID
+(EFIAPI *EFI_PEI_RESET2_SYSTEM)(
+ IN EFI_RESET_TYPE ResetType,
+ IN EFI_STATUS ResetStatus,
+ IN UINTN DataSize,
+ IN VOID *ResetData OPTIONAL
+ );
+
+/**
+ Find a file within a volume by its name.
+
+ This service searches for files with a specific name, within
+ either the specified firmware volume or all firmware volumes.
+ The service returns a file handle of type EFI_PEI_FILE_HANDLE,
+ which must be unique within the system.
+
+ @param FileName A pointer to the name of the file to
+ find within the firmware volume.
+ @param VolumeHandle The firmware volume to search.
+ @param FileHandle Upon exit, points to the found file's
+ handle or NULL if it could not be found.
+
+ @retval EFI_SUCCESS The file was found.
+ @retval EFI_NOT_FOUND The file was not found.
+ @retval EFI_INVALID_PARAMETER VolumeHandle or FileHandle or
+ FileName was NULL.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_PEI_FFS_FIND_BY_NAME)(
+ IN CONST EFI_GUID *FileName,
+ IN EFI_PEI_FV_HANDLE VolumeHandle,
+ OUT EFI_PEI_FILE_HANDLE *FileHandle
+ );
+
+///
+/// The information of the FV file.
+///
+typedef struct {
+ ///
+ /// Name of the file.
+ ///
+ EFI_GUID FileName;
+ ///
+ /// File type.
+ ///
+ EFI_FV_FILETYPE FileType;
+ ///
+ /// Attributes of the file.
+ ///
+ EFI_FV_FILE_ATTRIBUTES FileAttributes;
+ ///
+ /// Points to the file's data (not the header).
+ /// Not valid if EFI_FV_FILE_ATTRIB_MEMORY_MAPPED
+ /// is zero.
+ ///
+ VOID *Buffer;
+ ///
+ /// Size of the file's data.
+ ///
+ UINT32 BufferSize;
+} EFI_FV_FILE_INFO;
+
+///
+/// The information with authentication status of the FV file.
+///
+typedef struct {
+ ///
+ /// Name of the file.
+ ///
+ EFI_GUID FileName;
+ ///
+ /// File type.
+ ///
+ EFI_FV_FILETYPE FileType;
+ ///
+ /// Attributes of the file.
+ ///
+ EFI_FV_FILE_ATTRIBUTES FileAttributes;
+ ///
+ /// Points to the file's data (not the header).
+ /// Not valid if EFI_FV_FILE_ATTRIB_MEMORY_MAPPED
+ /// is zero.
+ ///
+ VOID *Buffer;
+ ///
+ /// Size of the file's data.
+ ///
+ UINT32 BufferSize;
+ ///
+ /// Authentication status for this file.
+ ///
+ UINT32 AuthenticationStatus;
+} EFI_FV_FILE_INFO2;
+
+/**
+ Returns information about a specific file.
+
+ This function returns information about a specific file,
+ including its file name, type, attributes, starting address and
+ size. If the firmware volume is not memory mapped, then the
+ Buffer member will be NULL.
+
+ @param FileHandle The handle of the file.
+ @param FileInfo Upon exit, points to the file's
+ information.
+
+ @retval EFI_SUCCESS File information was returned.
+ @retval EFI_INVALID_PARAMETER FileHandle does not
+ represent a valid file.
+ @retval EFI_INVALID_PARAMETER FileInfo is NULL.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_PEI_FFS_GET_FILE_INFO)(
+ IN EFI_PEI_FILE_HANDLE FileHandle,
+ OUT EFI_FV_FILE_INFO *FileInfo
+ );
+
+/**
+ Returns information about a specific file.
+
+ This function returns information about a specific file,
+ including its file name, type, attributes, starting address, size and authentication status.
+ If the firmware volume is not memory mapped, then the Buffer member will be NULL.
+
+ @param FileHandle The handle of the file.
+ @param FileInfo Upon exit, points to the file's
+ information.
+
+ @retval EFI_SUCCESS File information was returned.
+ @retval EFI_INVALID_PARAMETER FileHandle does not
+ represent a valid file.
+ @retval EFI_INVALID_PARAMETER FileInfo is NULL.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_PEI_FFS_GET_FILE_INFO2)(
+ IN EFI_PEI_FILE_HANDLE FileHandle,
+ OUT EFI_FV_FILE_INFO2 *FileInfo
+ );
+
+///
+/// The information of the FV volume.
+///
+typedef struct {
+ ///
+ /// Attributes of the firmware volume.
+ ///
+ EFI_FVB_ATTRIBUTES_2 FvAttributes;
+ ///
+ /// Format of the firmware volume.
+ ///
+ EFI_GUID FvFormat;
+ ///
+ /// Name of the firmware volume.
+ ///
+ EFI_GUID FvName;
+ ///
+ /// Points to the first byte of the firmware
+ /// volume, if bit EFI_FVB_MEMORY_MAPPED is
+ /// set in FvAttributes.
+ ///
+ VOID *FvStart;
+ ///
+ /// Size of the firmware volume.
+ ///
+ UINT64 FvSize;
+} EFI_FV_INFO;
+
+/**
+ Returns information about the specified volume.
+
+ This function returns information about a specific firmware
+ volume, including its name, type, attributes, starting address
+ and size.
+
+ @param VolumeHandle Handle of the volume.
+ @param VolumeInfo Upon exit, points to the volume's information.
+
+ @retval EFI_SUCCESS The volume information returned.
+ @retval EFI_INVALID_PARAMETER If VolumeHandle does not represent a valid volume.
+ @retval EFI_INVALID_PARAMETER If VolumeHandle is NULL.
+ @retval EFI_SUCCESS Information was successfully returned.
+ @retval EFI_INVALID_PARAMETER The volume designated by the VolumeHandle is not available.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_PEI_FFS_GET_VOLUME_INFO)(
+ IN EFI_PEI_FV_HANDLE VolumeHandle,
+ OUT EFI_FV_INFO *VolumeInfo
+ );
+
+/**
+ Register a PEIM so that it will be shadowed and called again.
+
+ This service registers a file handle so that after memory is
+ available, the PEIM will be re-loaded into permanent memory and
+ re-initialized. The PEIM registered this way will always be
+ initialized twice. The first time, this function call will
+ return EFI_SUCCESS. The second time, this function call will
+ return EFI_ALREADY_STARTED. Depending on the order in which
+ PEIMs are dispatched, the PEIM making this call may be
+ initialized after permanent memory is installed, even the first
+ time.
+
+ @param FileHandle PEIM's file handle. Must be the currently
+ executing PEIM.
+
+ @retval EFI_SUCCESS The PEIM was successfully registered for
+ shadowing.
+ @retval EFI_ALREADY_STARTED The PEIM was previously
+ registered for shadowing.
+ @retval EFI_NOT_FOUND The FileHandle does not refer to a
+ valid file handle.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_PEI_REGISTER_FOR_SHADOW)(
+ IN EFI_PEI_FILE_HANDLE FileHandle
+ );
+
+//
+// PEI Specification Revision information
+//
+#define PEI_SPECIFICATION_MAJOR_REVISION 1
+#define PEI_SPECIFICATION_MINOR_REVISION 70
+///
+/// Specification inconsistency here:
+/// In the PI1.0 spec, PEI_SERVICES_SIGNATURE is defined as 0x5652455320494550. But
+/// to pass a multiple tool chain, it appends an ULL.
+///
+//
+// PEI Services Table
+//
+#define PEI_SERVICES_SIGNATURE 0x5652455320494550ULL
+///
+/// Specification inconsistency here:
+/// In the PI1.0 specification, there is a typo error in PEI_SERVICES_REVISION. In the specification the defintion is
+/// #define ((PEI_SPECIFICATION_MAJOR_REVISION<<16) |(PEI_SPECIFICATION_MINOR_REVISION))
+/// and it should be as follows:
+///
+#define PEI_SERVICES_REVISION ((PEI_SPECIFICATION_MAJOR_REVISION<<16) | (PEI_SPECIFICATION_MINOR_REVISION))
+
+///
+/// EFI_PEI_SERVICES is a collection of functions whose implementation is provided by the PEI
+/// Foundation. These services fall into various classes, including the following:
+/// - Managing the boot mode
+/// - Allocating both early and permanent memory
+/// - Supporting the Firmware File System (FFS)
+/// - Abstracting the PPI database abstraction
+/// - Creating Hand-Off Blocks (HOBs).
+///
+struct _EFI_PEI_SERVICES {
+ ///
+ /// The table header for the PEI Services Table.
+ ///
+ EFI_TABLE_HEADER Hdr;
+
+ //
+ // PPI Functions
+ //
+ EFI_PEI_INSTALL_PPI InstallPpi;
+ EFI_PEI_REINSTALL_PPI ReInstallPpi;
+ EFI_PEI_LOCATE_PPI LocatePpi;
+ EFI_PEI_NOTIFY_PPI NotifyPpi;
+
+ //
+ // Boot Mode Functions
+ //
+ EFI_PEI_GET_BOOT_MODE GetBootMode;
+ EFI_PEI_SET_BOOT_MODE SetBootMode;
+
+ //
+ // HOB Functions
+ //
+ EFI_PEI_GET_HOB_LIST GetHobList;
+ EFI_PEI_CREATE_HOB CreateHob;
+
+ //
+ // Firmware Volume Functions
+ //
+ EFI_PEI_FFS_FIND_NEXT_VOLUME2 FfsFindNextVolume;
+ EFI_PEI_FFS_FIND_NEXT_FILE2 FfsFindNextFile;
+ EFI_PEI_FFS_FIND_SECTION_DATA2 FfsFindSectionData;
+
+ //
+ // PEI Memory Functions
+ //
+ EFI_PEI_INSTALL_PEI_MEMORY InstallPeiMemory;
+ EFI_PEI_ALLOCATE_PAGES AllocatePages;
+ EFI_PEI_ALLOCATE_POOL AllocatePool;
+ EFI_PEI_COPY_MEM CopyMem;
+ EFI_PEI_SET_MEM SetMem;
+
+ //
+ // Status Code
+ //
+ EFI_PEI_REPORT_STATUS_CODE ReportStatusCode;
+
+ //
+ // Reset
+ //
+ EFI_PEI_RESET_SYSTEM ResetSystem;
+
+ //
+ // (the following interfaces are installed by publishing PEIM)
+ // I/O Abstractions
+ //
+ EFI_PEI_CPU_IO_PPI *CpuIo;
+ EFI_PEI_PCI_CFG2_PPI *PciCfg;
+
+ //
+ // Future Installed Services
+ //
+ EFI_PEI_FFS_FIND_BY_NAME FfsFindFileByName;
+ EFI_PEI_FFS_GET_FILE_INFO FfsGetFileInfo;
+ EFI_PEI_FFS_GET_VOLUME_INFO FfsGetVolumeInfo;
+ EFI_PEI_REGISTER_FOR_SHADOW RegisterForShadow;
+ EFI_PEI_FFS_FIND_SECTION_DATA3 FindSectionData3;
+ EFI_PEI_FFS_GET_FILE_INFO2 FfsGetFileInfo2;
+ EFI_PEI_RESET2_SYSTEM ResetSystem2;
+ EFI_PEI_FREE_PAGES FreePages;
+};
+
+///
+/// EFI_SEC_PEI_HAND_OFF structure holds information about
+/// PEI core's operating environment, such as the size of location of
+/// temporary RAM, the stack location and BFV location.
+///
+typedef struct _EFI_SEC_PEI_HAND_OFF {
+ ///
+ /// Size of the data structure.
+ ///
+ UINT16 DataSize;
+
+ ///
+ /// Points to the first byte of the boot firmware volume,
+ /// which the PEI Dispatcher should search for
+ /// PEI modules.
+ ///
+ VOID *BootFirmwareVolumeBase;
+
+ ///
+ /// Size of the boot firmware volume, in bytes.
+ ///
+ UINTN BootFirmwareVolumeSize;
+
+ ///
+ /// Points to the first byte of the temporary RAM.
+ ///
+ VOID *TemporaryRamBase;
+
+ ///
+ /// Size of the temporary RAM, in bytes.
+ ///
+ UINTN TemporaryRamSize;
+
+ ///
+ /// Points to the first byte of the temporary RAM
+ /// available for use by the PEI Foundation. The area
+ /// described by PeiTemporaryRamBase and PeiTemporaryRamSize
+ /// must not extend outside beyond the area described by
+ /// TemporaryRamBase & TemporaryRamSize. This area should not
+ /// overlap with the area reported by StackBase and
+ /// StackSize.
+ ///
+ VOID *PeiTemporaryRamBase;
+
+ ///
+ /// The size of the available temporary RAM available for
+ /// use by the PEI Foundation, in bytes.
+ ///
+ UINTN PeiTemporaryRamSize;
+
+ ///
+ /// Points to the first byte of the stack.
+ /// This are may be part of the memory described by
+ /// TemporaryRamBase and TemporaryRamSize
+ /// or may be an entirely separate area.
+ ///
+ VOID *StackBase;
+
+ ///
+ /// Size of the stack, in bytes.
+ ///
+ UINTN StackSize;
+} EFI_SEC_PEI_HAND_OFF;
+
+/**
+ The entry point of PEI Foundation.
+
+ This function is the entry point for the PEI Foundation, which
+ allows the SEC phase to pass information about the stack,
+ temporary RAM and the Boot Firmware Volume. In addition, it also
+ allows the SEC phase to pass services and data forward for use
+ during the PEI phase in the form of one or more PPIs. These PPI's
+ will be installed and/or immediately signaled if they are
+ notification type. There is no limit to the number of additional
+ PPIs that can be passed from SEC into the PEI Foundation. As part
+ of its initialization phase, the PEI Foundation will add these
+ SEC-hosted PPIs to its PPI database such that both the PEI
+ Foundation and any modules can leverage the associated service
+ calls and/or code in these early PPIs.
+
+ @param SecCoreData Points to a data structure containing
+ information about the PEI core's
+ operating environment, such as the size
+ and location of temporary RAM, the stack
+ location and the BFV location.
+
+ @param PpiList Points to a list of one or more PPI
+ descriptors to be installed initially by
+ the PEI core. An empty PPI list consists
+ of a single descriptor with the end-tag
+ EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST.
+ As part of its initialization phase, the
+ PEI Foundation will add these SEC-hosted
+ PPIs to its PPI database such that both
+ the PEI Foundation and any modules can
+ leverage the associated service calls
+ and/or code in these early PPIs.
+
+
+**/
+typedef
+VOID
+(EFIAPI *EFI_PEI_CORE_ENTRY_POINT)(
+ IN CONST EFI_SEC_PEI_HAND_OFF *SecCoreData,
+ IN CONST EFI_PEI_PPI_DESCRIPTOR *PpiList
+ );
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Pi/PiS3BootScript.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Pi/PiS3BootScript.h
new file mode 100644
index 0000000000..4779556a6d
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Pi/PiS3BootScript.h
@@ -0,0 +1,53 @@
+/** @file
+ This file contains the boot script defintions that are shared between the
+ Boot Script Executor PPI and the Boot Script Save Protocol.
+
+ Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _PI_S3_BOOT_SCRIPT_H_
+#define _PI_S3_BOOT_SCRIPT_H_
+
+// *******************************************
+// EFI Boot Script Opcode definitions
+// *******************************************
+#define EFI_BOOT_SCRIPT_IO_WRITE_OPCODE 0x00
+#define EFI_BOOT_SCRIPT_IO_READ_WRITE_OPCODE 0x01
+#define EFI_BOOT_SCRIPT_MEM_WRITE_OPCODE 0x02
+#define EFI_BOOT_SCRIPT_MEM_READ_WRITE_OPCODE 0x03
+#define EFI_BOOT_SCRIPT_PCI_CONFIG_WRITE_OPCODE 0x04
+#define EFI_BOOT_SCRIPT_PCI_CONFIG_READ_WRITE_OPCODE 0x05
+#define EFI_BOOT_SCRIPT_SMBUS_EXECUTE_OPCODE 0x06
+#define EFI_BOOT_SCRIPT_STALL_OPCODE 0x07
+#define EFI_BOOT_SCRIPT_DISPATCH_OPCODE 0x08
+#define EFI_BOOT_SCRIPT_DISPATCH_2_OPCODE 0x09
+#define EFI_BOOT_SCRIPT_INFORMATION_OPCODE 0x0A
+#define EFI_BOOT_SCRIPT_PCI_CONFIG2_WRITE_OPCODE 0x0B
+#define EFI_BOOT_SCRIPT_PCI_CONFIG2_READ_WRITE_OPCODE 0x0C
+#define EFI_BOOT_SCRIPT_IO_POLL_OPCODE 0x0D
+#define EFI_BOOT_SCRIPT_MEM_POLL_OPCODE 0x0E
+#define EFI_BOOT_SCRIPT_PCI_CONFIG_POLL_OPCODE 0x0F
+#define EFI_BOOT_SCRIPT_PCI_CONFIG2_POLL_OPCODE 0x10
+
+// *******************************************
+// EFI_BOOT_SCRIPT_WIDTH
+// *******************************************
+typedef enum {
+ EfiBootScriptWidthUint8,
+ EfiBootScriptWidthUint16,
+ EfiBootScriptWidthUint32,
+ EfiBootScriptWidthUint64,
+ EfiBootScriptWidthFifoUint8,
+ EfiBootScriptWidthFifoUint16,
+ EfiBootScriptWidthFifoUint32,
+ EfiBootScriptWidthFifoUint64,
+ EfiBootScriptWidthFillUint8,
+ EfiBootScriptWidthFillUint16,
+ EfiBootScriptWidthFillUint32,
+ EfiBootScriptWidthFillUint64,
+ EfiBootScriptWidthMaximum
+} EFI_BOOT_SCRIPT_WIDTH;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Pi/PiSmmCis.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Pi/PiSmmCis.h
new file mode 100644
index 0000000000..50f90c1d5b
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Pi/PiSmmCis.h
@@ -0,0 +1,200 @@
+/** @file
+ Common definitions in the Platform Initialization Specification version 1.4a
+ VOLUME 4 System Management Mode Core Interface version.
+
+ Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _PI_SMMCIS_H_
+#define _PI_SMMCIS_H_
+
+#include
+#include
+
+typedef struct _EFI_SMM_SYSTEM_TABLE2 EFI_SMM_SYSTEM_TABLE2;
+//
+// Define new MM related definition introduced by PI 1.5.
+//
+#define SMM_SMST_SIGNATURE MM_MMST_SIGNATURE
+#define SMM_SPECIFICATION_MAJOR_REVISION MM_SPECIFICATION_MAJOR_REVISION
+#define SMM_SPECIFICATION_MINOR_REVISION MM_SPECIFICATION_MINOR_REVISION
+#define EFI_SMM_SYSTEM_TABLE2_REVISION EFI_MM_SYSTEM_TABLE_REVISION
+
+/**
+ Adds, updates, or removes a configuration table entry from the System Management System Table.
+
+ The SmmInstallConfigurationTable() function is used to maintain the list
+ of configuration tables that are stored in the System Management System
+ Table. The list is stored as an array of (GUID, Pointer) pairs. The list
+ must be allocated from pool memory with PoolType set to EfiRuntimeServicesData.
+
+ @param[in] SystemTable A pointer to the SMM System Table (SMST).
+ @param[in] Guid A pointer to the GUID for the entry to add, update, or remove.
+ @param[in] Table A pointer to the buffer of the table to add.
+ @param[in] TableSize The size of the table to install.
+
+ @retval EFI_SUCCESS The (Guid, Table) pair was added, updated, or removed.
+ @retval EFI_INVALID_PARAMETER Guid is not valid.
+ @retval EFI_NOT_FOUND An attempt was made to delete a non-existent entry.
+ @retval EFI_OUT_OF_RESOURCES There is not enough memory available to complete the operation.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_SMM_INSTALL_CONFIGURATION_TABLE2)(
+ IN CONST EFI_SMM_SYSTEM_TABLE2 *SystemTable,
+ IN CONST EFI_GUID *Guid,
+ IN VOID *Table,
+ IN UINTN TableSize
+ );
+
+typedef EFI_MM_STARTUP_THIS_AP EFI_SMM_STARTUP_THIS_AP;
+typedef EFI_MM_NOTIFY_FN EFI_SMM_NOTIFY_FN;
+typedef EFI_MM_REGISTER_PROTOCOL_NOTIFY EFI_SMM_REGISTER_PROTOCOL_NOTIFY;
+typedef EFI_MM_INTERRUPT_MANAGE EFI_SMM_INTERRUPT_MANAGE;
+typedef EFI_MM_HANDLER_ENTRY_POINT EFI_SMM_HANDLER_ENTRY_POINT2;
+typedef EFI_MM_INTERRUPT_REGISTER EFI_SMM_INTERRUPT_REGISTER;
+typedef EFI_MM_INTERRUPT_UNREGISTER EFI_SMM_INTERRUPT_UNREGISTER;
+
+///
+/// Processor information and functionality needed by SMM Foundation.
+///
+typedef struct _EFI_SMM_ENTRY_CONTEXT {
+ EFI_SMM_STARTUP_THIS_AP SmmStartupThisAp;
+ ///
+ /// A number between zero and the NumberOfCpus field. This field designates which
+ /// processor is executing the SMM Foundation.
+ ///
+ UINTN CurrentlyExecutingCpu;
+ ///
+ /// The number of possible processors in the platform. This is a 1 based
+ /// counter. This does not indicate the number of processors that entered SMM.
+ ///
+ UINTN NumberOfCpus;
+ ///
+ /// Points to an array, where each element describes the number of bytes in the
+ /// corresponding save state specified by CpuSaveState. There are always
+ /// NumberOfCpus entries in the array.
+ ///
+ UINTN *CpuSaveStateSize;
+ ///
+ /// Points to an array, where each element is a pointer to a CPU save state. The
+ /// corresponding element in CpuSaveStateSize specifies the number of bytes in the
+ /// save state area. There are always NumberOfCpus entries in the array.
+ ///
+ VOID **CpuSaveState;
+} EFI_SMM_ENTRY_CONTEXT;
+
+/**
+ This function is the main entry point to the SMM Foundation.
+
+ @param[in] SmmEntryContext Processor information and functionality needed by SMM Foundation.
+**/
+typedef
+VOID
+(EFIAPI *EFI_SMM_ENTRY_POINT)(
+ IN CONST EFI_SMM_ENTRY_CONTEXT *SmmEntryContext
+ );
+
+///
+/// System Management System Table (SMST)
+///
+/// The System Management System Table (SMST) is a table that contains a collection of common
+/// services for managing SMRAM allocation and providing basic I/O services. These services are
+/// intended for both preboot and runtime usage.
+///
+struct _EFI_SMM_SYSTEM_TABLE2 {
+ ///
+ /// The table header for the SMST.
+ ///
+ EFI_TABLE_HEADER Hdr;
+ ///
+ /// A pointer to a NULL-terminated Unicode string containing the vendor name.
+ /// It is permissible for this pointer to be NULL.
+ ///
+ CHAR16 *SmmFirmwareVendor;
+ ///
+ /// The particular revision of the firmware.
+ ///
+ UINT32 SmmFirmwareRevision;
+
+ EFI_SMM_INSTALL_CONFIGURATION_TABLE2 SmmInstallConfigurationTable;
+
+ ///
+ /// I/O Service
+ ///
+ EFI_SMM_CPU_IO2_PROTOCOL SmmIo;
+
+ ///
+ /// Runtime memory services
+ ///
+ EFI_ALLOCATE_POOL SmmAllocatePool;
+ EFI_FREE_POOL SmmFreePool;
+ EFI_ALLOCATE_PAGES SmmAllocatePages;
+ EFI_FREE_PAGES SmmFreePages;
+
+ ///
+ /// MP service
+ ///
+ EFI_SMM_STARTUP_THIS_AP SmmStartupThisAp;
+
+ ///
+ /// CPU information records
+ ///
+
+ ///
+ /// A number between zero and and the NumberOfCpus field. This field designates
+ /// which processor is executing the SMM infrastructure.
+ ///
+ UINTN CurrentlyExecutingCpu;
+ ///
+ /// The number of possible processors in the platform. This is a 1 based counter.
+ ///
+ UINTN NumberOfCpus;
+ ///
+ /// Points to an array, where each element describes the number of bytes in the
+ /// corresponding save state specified by CpuSaveState. There are always
+ /// NumberOfCpus entries in the array.
+ ///
+ UINTN *CpuSaveStateSize;
+ ///
+ /// Points to an array, where each element is a pointer to a CPU save state. The
+ /// corresponding element in CpuSaveStateSize specifies the number of bytes in the
+ /// save state area. There are always NumberOfCpus entries in the array.
+ ///
+ VOID **CpuSaveState;
+
+ ///
+ /// Extensibility table
+ ///
+
+ ///
+ /// The number of UEFI Configuration Tables in the buffer SmmConfigurationTable.
+ ///
+ UINTN NumberOfTableEntries;
+ ///
+ /// A pointer to the UEFI Configuration Tables. The number of entries in the table is
+ /// NumberOfTableEntries.
+ ///
+ EFI_CONFIGURATION_TABLE *SmmConfigurationTable;
+
+ ///
+ /// Protocol services
+ ///
+ EFI_INSTALL_PROTOCOL_INTERFACE SmmInstallProtocolInterface;
+ EFI_UNINSTALL_PROTOCOL_INTERFACE SmmUninstallProtocolInterface;
+ EFI_HANDLE_PROTOCOL SmmHandleProtocol;
+ EFI_SMM_REGISTER_PROTOCOL_NOTIFY SmmRegisterProtocolNotify;
+ EFI_LOCATE_HANDLE SmmLocateHandle;
+ EFI_LOCATE_PROTOCOL SmmLocateProtocol;
+
+ ///
+ /// SMI Management functions
+ ///
+ EFI_SMM_INTERRUPT_MANAGE SmiManage;
+ EFI_SMM_INTERRUPT_REGISTER SmiHandlerRegister;
+ EFI_SMM_INTERRUPT_UNREGISTER SmiHandlerUnRegister;
+};
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Pi/PiStatusCode.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Pi/PiStatusCode.h
new file mode 100644
index 0000000000..344b9d267a
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Pi/PiStatusCode.h
@@ -0,0 +1,1206 @@
+/** @file
+ StatusCode related definitions in PI.
+
+Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Revision Reference:
+ These status codes are defined in UEFI Platform Initialization Specification 1.2,
+ Volume 3: Shared Architectural Elements.
+
+**/
+
+#ifndef __PI_STATUS_CODE_H__
+#define __PI_STATUS_CODE_H__
+
+//
+// Required for IA32, X64, IPF, ARM and EBC defines for CPU exception types
+//
+#include
+
+///
+/// Status Code Type Definition.
+///
+typedef UINT32 EFI_STATUS_CODE_TYPE;
+
+///
+/// A Status Code Type is made up of the code type and severity.
+/// All values masked by EFI_STATUS_CODE_RESERVED_MASK are
+/// reserved for use by this specification.
+///
+///@{
+#define EFI_STATUS_CODE_TYPE_MASK 0x000000FF
+#define EFI_STATUS_CODE_SEVERITY_MASK 0xFF000000
+#define EFI_STATUS_CODE_RESERVED_MASK 0x00FFFF00
+///@}
+
+///
+/// Definition of code types. All other values masked by
+/// EFI_STATUS_CODE_TYPE_MASK are reserved for use by
+/// this specification.
+///
+///@{
+#define EFI_PROGRESS_CODE 0x00000001
+#define EFI_ERROR_CODE 0x00000002
+#define EFI_DEBUG_CODE 0x00000003
+///@}
+
+///
+/// Definitions of severities, all other values masked by
+/// EFI_STATUS_CODE_SEVERITY_MASK are reserved for use by
+/// this specification.
+/// Uncontained errors are major errors that could not contained
+/// to the specific component that is reporting the error.
+/// For example, if a memory error was not detected early enough,
+/// the bad data could be consumed by other drivers.
+///
+///@{
+#define EFI_ERROR_MINOR 0x40000000
+#define EFI_ERROR_MAJOR 0x80000000
+#define EFI_ERROR_UNRECOVERED 0x90000000
+#define EFI_ERROR_UNCONTAINED 0xa0000000
+///@}
+
+///
+/// Status Code Value Definition.
+///
+typedef UINT32 EFI_STATUS_CODE_VALUE;
+
+///
+/// A Status Code Value is made up of the class, subclass, and
+/// an operation.
+///
+///@{
+#define EFI_STATUS_CODE_CLASS_MASK 0xFF000000
+#define EFI_STATUS_CODE_SUBCLASS_MASK 0x00FF0000
+#define EFI_STATUS_CODE_OPERATION_MASK 0x0000FFFF
+///@}
+
+///
+/// Definition of Status Code extended data header.
+/// The data will follow HeaderSize bytes from the beginning of
+/// the structure and is Size bytes long.
+///
+typedef struct {
+ ///
+ /// The size of the structure. This is specified to enable future expansion.
+ ///
+ UINT16 HeaderSize;
+ ///
+ /// The size of the data in bytes. This does not include the size of the header structure.
+ ///
+ UINT16 Size;
+ ///
+ /// The GUID defining the type of the data.
+ ///
+ EFI_GUID Type;
+} EFI_STATUS_CODE_DATA;
+
+///
+/// General partitioning scheme for Progress and Error Codes are:
+/// - 0x0000-0x0FFF Shared by all sub-classes in a given class.
+/// - 0x1000-0x7FFF Subclass Specific.
+/// - 0x8000-0xFFFF OEM specific.
+///@{
+#define EFI_SUBCLASS_SPECIFIC 0x1000
+#define EFI_OEM_SPECIFIC 0x8000
+///@}
+
+///
+/// Debug Code definitions for all classes and subclass.
+/// Only one debug code is defined at this point and should
+/// be used for anything that is sent to the debug stream.
+///
+///@{
+#define EFI_DC_UNSPECIFIED 0x0
+///@}
+
+///
+/// Class definitions.
+/// Values of 4-127 are reserved for future use by this specification.
+/// Values in the range 127-255 are reserved for OEM use.
+///
+///@{
+#define EFI_COMPUTING_UNIT 0x00000000
+#define EFI_PERIPHERAL 0x01000000
+#define EFI_IO_BUS 0x02000000
+#define EFI_SOFTWARE 0x03000000
+///@}
+
+///
+/// Computing Unit Subclass definitions.
+/// Values of 8-127 are reserved for future use by this specification.
+/// Values of 128-255 are reserved for OEM use.
+///
+///@{
+#define EFI_COMPUTING_UNIT_UNSPECIFIED (EFI_COMPUTING_UNIT | 0x00000000)
+#define EFI_COMPUTING_UNIT_HOST_PROCESSOR (EFI_COMPUTING_UNIT | 0x00010000)
+#define EFI_COMPUTING_UNIT_FIRMWARE_PROCESSOR (EFI_COMPUTING_UNIT | 0x00020000)
+#define EFI_COMPUTING_UNIT_IO_PROCESSOR (EFI_COMPUTING_UNIT | 0x00030000)
+#define EFI_COMPUTING_UNIT_CACHE (EFI_COMPUTING_UNIT | 0x00040000)
+#define EFI_COMPUTING_UNIT_MEMORY (EFI_COMPUTING_UNIT | 0x00050000)
+#define EFI_COMPUTING_UNIT_CHIPSET (EFI_COMPUTING_UNIT | 0x00060000)
+///@}
+
+///
+/// Computing Unit Class Progress Code definitions.
+/// These are shared by all subclasses.
+///
+///@{
+#define EFI_CU_PC_INIT_BEGIN 0x00000000
+#define EFI_CU_PC_INIT_END 0x00000001
+///@}
+
+//
+// Computing Unit Unspecified Subclass Progress Code definitions.
+//
+
+///
+/// Computing Unit Host Processor Subclass Progress Code definitions.
+///@{
+#define EFI_CU_HP_PC_POWER_ON_INIT (EFI_SUBCLASS_SPECIFIC | 0x00000000)
+#define EFI_CU_HP_PC_CACHE_INIT (EFI_SUBCLASS_SPECIFIC | 0x00000001)
+#define EFI_CU_HP_PC_RAM_INIT (EFI_SUBCLASS_SPECIFIC | 0x00000002)
+#define EFI_CU_HP_PC_MEMORY_CONTROLLER_INIT (EFI_SUBCLASS_SPECIFIC | 0x00000003)
+#define EFI_CU_HP_PC_IO_INIT (EFI_SUBCLASS_SPECIFIC | 0x00000004)
+#define EFI_CU_HP_PC_BSP_SELECT (EFI_SUBCLASS_SPECIFIC | 0x00000005)
+#define EFI_CU_HP_PC_BSP_RESELECT (EFI_SUBCLASS_SPECIFIC | 0x00000006)
+#define EFI_CU_HP_PC_AP_INIT (EFI_SUBCLASS_SPECIFIC | 0x00000007)
+#define EFI_CU_HP_PC_SMM_INIT (EFI_SUBCLASS_SPECIFIC | 0x00000008)
+///@}
+
+//
+// Computing Unit Firmware Processor Subclass Progress Code definitions.
+//
+
+//
+// Computing Unit IO Processor Subclass Progress Code definitions.
+//
+
+///
+/// Computing Unit Cache Subclass Progress Code definitions.
+///
+///@{
+#define EFI_CU_CACHE_PC_PRESENCE_DETECT (EFI_SUBCLASS_SPECIFIC | 0x00000000)
+#define EFI_CU_CACHE_PC_CONFIGURATION (EFI_SUBCLASS_SPECIFIC | 0x00000001)
+///@}
+
+///
+/// Computing Unit Memory Subclass Progress Code definitions.
+///
+///@{
+#define EFI_CU_MEMORY_PC_SPD_READ (EFI_SUBCLASS_SPECIFIC | 0x00000000)
+#define EFI_CU_MEMORY_PC_PRESENCE_DETECT (EFI_SUBCLASS_SPECIFIC | 0x00000001)
+#define EFI_CU_MEMORY_PC_TIMING (EFI_SUBCLASS_SPECIFIC | 0x00000002)
+#define EFI_CU_MEMORY_PC_CONFIGURING (EFI_SUBCLASS_SPECIFIC | 0x00000003)
+#define EFI_CU_MEMORY_PC_OPTIMIZING (EFI_SUBCLASS_SPECIFIC | 0x00000004)
+#define EFI_CU_MEMORY_PC_INIT (EFI_SUBCLASS_SPECIFIC | 0x00000005)
+#define EFI_CU_MEMORY_PC_TEST (EFI_SUBCLASS_SPECIFIC | 0x00000006)
+///@}
+
+//
+// Computing Unit Chipset Subclass Progress Code definitions.
+//
+
+///
+/// South Bridge initialization prior to memory detection.
+///
+#define EFI_CHIPSET_PC_PEI_CAR_SB_INIT (EFI_SUBCLASS_SPECIFIC|0x00000000)
+
+///
+/// North Bridge initialization prior to memory detection.
+///
+#define EFI_CHIPSET_PC_PEI_CAR_NB_INIT (EFI_SUBCLASS_SPECIFIC|0x00000001)
+
+///
+/// South Bridge initialization after memory detection.
+///
+#define EFI_CHIPSET_PC_PEI_MEM_SB_INIT (EFI_SUBCLASS_SPECIFIC|0x00000002)
+
+///
+/// North Bridge initialization after memory detection.
+///
+#define EFI_CHIPSET_PC_PEI_MEM_NB_INIT (EFI_SUBCLASS_SPECIFIC|0x00000003)
+
+///
+/// PCI Host Bridge DXE initialization.
+///
+#define EFI_CHIPSET_PC_DXE_HB_INIT (EFI_SUBCLASS_SPECIFIC|0x00000004)
+
+///
+/// North Bridge DXE initialization.
+///
+#define EFI_CHIPSET_PC_DXE_NB_INIT (EFI_SUBCLASS_SPECIFIC|0x00000005)
+
+///
+/// North Bridge specific SMM initialization in DXE.
+///
+#define EFI_CHIPSET_PC_DXE_NB_SMM_INIT (EFI_SUBCLASS_SPECIFIC|0x00000006)
+
+///
+/// Initialization of the South Bridge specific UEFI Runtime Services.
+///
+#define EFI_CHIPSET_PC_DXE_SB_RT_INIT (EFI_SUBCLASS_SPECIFIC|0x00000007)
+
+///
+/// South Bridge DXE initialization
+///
+#define EFI_CHIPSET_PC_DXE_SB_INIT (EFI_SUBCLASS_SPECIFIC|0x00000008)
+
+///
+/// South Bridge specific SMM initialization in DXE.
+///
+#define EFI_CHIPSET_PC_DXE_SB_SMM_INIT (EFI_SUBCLASS_SPECIFIC|0x00000009)
+
+///
+/// Initialization of the South Bridge devices.
+///
+#define EFI_CHIPSET_PC_DXE_SB_DEVICES_INIT (EFI_SUBCLASS_SPECIFIC|0x0000000a)
+
+///
+/// Computing Unit Class Error Code definitions.
+/// These are shared by all subclasses.
+///
+///@{
+#define EFI_CU_EC_NON_SPECIFIC 0x00000000
+#define EFI_CU_EC_DISABLED 0x00000001
+#define EFI_CU_EC_NOT_SUPPORTED 0x00000002
+#define EFI_CU_EC_NOT_DETECTED 0x00000003
+#define EFI_CU_EC_NOT_CONFIGURED 0x00000004
+///@}
+
+//
+// Computing Unit Unspecified Subclass Error Code definitions.
+//
+
+///
+/// Computing Unit Host Processor Subclass Error Code definitions.
+///
+///@{
+#define EFI_CU_HP_EC_INVALID_TYPE (EFI_SUBCLASS_SPECIFIC | 0x00000000)
+#define EFI_CU_HP_EC_INVALID_SPEED (EFI_SUBCLASS_SPECIFIC | 0x00000001)
+#define EFI_CU_HP_EC_MISMATCH (EFI_SUBCLASS_SPECIFIC | 0x00000002)
+#define EFI_CU_HP_EC_TIMER_EXPIRED (EFI_SUBCLASS_SPECIFIC | 0x00000003)
+#define EFI_CU_HP_EC_SELF_TEST (EFI_SUBCLASS_SPECIFIC | 0x00000004)
+#define EFI_CU_HP_EC_INTERNAL (EFI_SUBCLASS_SPECIFIC | 0x00000005)
+#define EFI_CU_HP_EC_THERMAL (EFI_SUBCLASS_SPECIFIC | 0x00000006)
+#define EFI_CU_HP_EC_LOW_VOLTAGE (EFI_SUBCLASS_SPECIFIC | 0x00000007)
+#define EFI_CU_HP_EC_HIGH_VOLTAGE (EFI_SUBCLASS_SPECIFIC | 0x00000008)
+#define EFI_CU_HP_EC_CACHE (EFI_SUBCLASS_SPECIFIC | 0x00000009)
+#define EFI_CU_HP_EC_MICROCODE_UPDATE (EFI_SUBCLASS_SPECIFIC | 0x0000000A)
+#define EFI_CU_HP_EC_CORRECTABLE (EFI_SUBCLASS_SPECIFIC | 0x0000000B)
+#define EFI_CU_HP_EC_UNCORRECTABLE (EFI_SUBCLASS_SPECIFIC | 0x0000000C)
+#define EFI_CU_HP_EC_NO_MICROCODE_UPDATE (EFI_SUBCLASS_SPECIFIC | 0x0000000D)
+///@}
+
+///
+/// Computing Unit Firmware Processor Subclass Error Code definitions.
+///
+///@{
+#define EFI_CU_FP_EC_HARD_FAIL (EFI_SUBCLASS_SPECIFIC | 0x00000000)
+#define EFI_CU_FP_EC_SOFT_FAIL (EFI_SUBCLASS_SPECIFIC | 0x00000001)
+#define EFI_CU_FP_EC_COMM_ERROR (EFI_SUBCLASS_SPECIFIC | 0x00000002)
+///@}
+
+//
+// Computing Unit IO Processor Subclass Error Code definitions.
+//
+
+///
+/// Computing Unit Cache Subclass Error Code definitions.
+///
+///@{
+#define EFI_CU_CACHE_EC_INVALID_TYPE (EFI_SUBCLASS_SPECIFIC | 0x00000000)
+#define EFI_CU_CACHE_EC_INVALID_SPEED (EFI_SUBCLASS_SPECIFIC | 0x00000001)
+#define EFI_CU_CACHE_EC_INVALID_SIZE (EFI_SUBCLASS_SPECIFIC | 0x00000002)
+#define EFI_CU_CACHE_EC_MISMATCH (EFI_SUBCLASS_SPECIFIC | 0x00000003)
+///@}
+
+///
+/// Computing Unit Memory Subclass Error Code definitions.
+///
+///@{
+#define EFI_CU_MEMORY_EC_INVALID_TYPE (EFI_SUBCLASS_SPECIFIC | 0x00000000)
+#define EFI_CU_MEMORY_EC_INVALID_SPEED (EFI_SUBCLASS_SPECIFIC | 0x00000001)
+#define EFI_CU_MEMORY_EC_CORRECTABLE (EFI_SUBCLASS_SPECIFIC | 0x00000002)
+#define EFI_CU_MEMORY_EC_UNCORRECTABLE (EFI_SUBCLASS_SPECIFIC | 0x00000003)
+#define EFI_CU_MEMORY_EC_SPD_FAIL (EFI_SUBCLASS_SPECIFIC | 0x00000004)
+#define EFI_CU_MEMORY_EC_INVALID_SIZE (EFI_SUBCLASS_SPECIFIC | 0x00000005)
+#define EFI_CU_MEMORY_EC_MISMATCH (EFI_SUBCLASS_SPECIFIC | 0x00000006)
+#define EFI_CU_MEMORY_EC_S3_RESUME_FAIL (EFI_SUBCLASS_SPECIFIC | 0x00000007)
+#define EFI_CU_MEMORY_EC_UPDATE_FAIL (EFI_SUBCLASS_SPECIFIC | 0x00000008)
+#define EFI_CU_MEMORY_EC_NONE_DETECTED (EFI_SUBCLASS_SPECIFIC | 0x00000009)
+#define EFI_CU_MEMORY_EC_NONE_USEFUL (EFI_SUBCLASS_SPECIFIC | 0x0000000A)
+///@}
+
+///
+/// Computing Unit Chipset Subclass Error Code definitions.
+///
+///@{
+#define EFI_CHIPSET_EC_BAD_BATTERY (EFI_SUBCLASS_SPECIFIC | 0x00000000)
+#define EFI_CHIPSET_EC_DXE_NB_ERROR (EFI_SUBCLASS_SPECIFIC | 0x00000001)
+#define EFI_CHIPSET_EC_DXE_SB_ERROR (EFI_SUBCLASS_SPECIFIC | 0x00000002)
+#define EFI_CHIPSET_EC_INTRUDER_DETECT (EFI_SUBCLASS_SPECIFIC | 0x00000003)
+///@}
+
+///
+/// Peripheral Subclass definitions.
+/// Values of 12-127 are reserved for future use by this specification.
+/// Values of 128-255 are reserved for OEM use.
+///
+///@{
+#define EFI_PERIPHERAL_UNSPECIFIED (EFI_PERIPHERAL | 0x00000000)
+#define EFI_PERIPHERAL_KEYBOARD (EFI_PERIPHERAL | 0x00010000)
+#define EFI_PERIPHERAL_MOUSE (EFI_PERIPHERAL | 0x00020000)
+#define EFI_PERIPHERAL_LOCAL_CONSOLE (EFI_PERIPHERAL | 0x00030000)
+#define EFI_PERIPHERAL_REMOTE_CONSOLE (EFI_PERIPHERAL | 0x00040000)
+#define EFI_PERIPHERAL_SERIAL_PORT (EFI_PERIPHERAL | 0x00050000)
+#define EFI_PERIPHERAL_PARALLEL_PORT (EFI_PERIPHERAL | 0x00060000)
+#define EFI_PERIPHERAL_FIXED_MEDIA (EFI_PERIPHERAL | 0x00070000)
+#define EFI_PERIPHERAL_REMOVABLE_MEDIA (EFI_PERIPHERAL | 0x00080000)
+#define EFI_PERIPHERAL_AUDIO_INPUT (EFI_PERIPHERAL | 0x00090000)
+#define EFI_PERIPHERAL_AUDIO_OUTPUT (EFI_PERIPHERAL | 0x000A0000)
+#define EFI_PERIPHERAL_LCD_DEVICE (EFI_PERIPHERAL | 0x000B0000)
+#define EFI_PERIPHERAL_NETWORK (EFI_PERIPHERAL | 0x000C0000)
+#define EFI_PERIPHERAL_DOCKING (EFI_PERIPHERAL | 0x000D0000)
+///@}
+
+///
+/// Peripheral Class Progress Code definitions.
+/// These are shared by all subclasses.
+///
+///@{
+#define EFI_P_PC_INIT 0x00000000
+#define EFI_P_PC_RESET 0x00000001
+#define EFI_P_PC_DISABLE 0x00000002
+#define EFI_P_PC_PRESENCE_DETECT 0x00000003
+#define EFI_P_PC_ENABLE 0x00000004
+#define EFI_P_PC_RECONFIG 0x00000005
+#define EFI_P_PC_DETECTED 0x00000006
+#define EFI_P_PC_REMOVED 0x00000007
+///@}
+
+//
+// Peripheral Class Unspecified Subclass Progress Code definitions.
+//
+
+///
+/// Peripheral Class Keyboard Subclass Progress Code definitions.
+///
+///@{
+#define EFI_P_KEYBOARD_PC_CLEAR_BUFFER (EFI_SUBCLASS_SPECIFIC | 0x00000000)
+#define EFI_P_KEYBOARD_PC_SELF_TEST (EFI_SUBCLASS_SPECIFIC | 0x00000001)
+///@}
+
+///
+/// Peripheral Class Mouse Subclass Progress Code definitions.
+///
+///@{
+#define EFI_P_MOUSE_PC_SELF_TEST (EFI_SUBCLASS_SPECIFIC | 0x00000000)
+///@}
+
+//
+// Peripheral Class Local Console Subclass Progress Code definitions.
+//
+
+//
+// Peripheral Class Remote Console Subclass Progress Code definitions.
+//
+
+///
+/// Peripheral Class Serial Port Subclass Progress Code definitions.
+///
+///@{
+#define EFI_P_SERIAL_PORT_PC_CLEAR_BUFFER (EFI_SUBCLASS_SPECIFIC | 0x00000000)
+///@}
+
+//
+// Peripheral Class Parallel Port Subclass Progress Code definitions.
+//
+
+//
+// Peripheral Class Fixed Media Subclass Progress Code definitions.
+//
+
+//
+// Peripheral Class Removable Media Subclass Progress Code definitions.
+//
+
+//
+// Peripheral Class Audio Input Subclass Progress Code definitions.
+//
+
+//
+// Peripheral Class Audio Output Subclass Progress Code definitions.
+//
+
+//
+// Peripheral Class LCD Device Subclass Progress Code definitions.
+//
+
+//
+// Peripheral Class Network Subclass Progress Code definitions.
+//
+
+///
+/// Peripheral Class Error Code definitions.
+/// These are shared by all subclasses.
+///
+///@{
+#define EFI_P_EC_NON_SPECIFIC 0x00000000
+#define EFI_P_EC_DISABLED 0x00000001
+#define EFI_P_EC_NOT_SUPPORTED 0x00000002
+#define EFI_P_EC_NOT_DETECTED 0x00000003
+#define EFI_P_EC_NOT_CONFIGURED 0x00000004
+#define EFI_P_EC_INTERFACE_ERROR 0x00000005
+#define EFI_P_EC_CONTROLLER_ERROR 0x00000006
+#define EFI_P_EC_INPUT_ERROR 0x00000007
+#define EFI_P_EC_OUTPUT_ERROR 0x00000008
+#define EFI_P_EC_RESOURCE_CONFLICT 0x00000009
+///@}
+
+//
+// Peripheral Class Unspecified Subclass Error Code definitions.
+//
+
+///
+/// Peripheral Class Keyboard Subclass Error Code definitions.
+///
+///@{
+#define EFI_P_KEYBOARD_EC_LOCKED (EFI_SUBCLASS_SPECIFIC | 0x00000000)
+#define EFI_P_KEYBOARD_EC_STUCK_KEY (EFI_SUBCLASS_SPECIFIC | 0x00000001)
+#define EFI_P_KEYBOARD_EC_BUFFER_FULL (EFI_SUBCLASS_SPECIFIC | 0x00000002)
+///@}
+
+///
+/// Peripheral Class Mouse Subclass Error Code definitions.
+///
+///@{
+#define EFI_P_MOUSE_EC_LOCKED (EFI_SUBCLASS_SPECIFIC | 0x00000000)
+///@}
+
+//
+// Peripheral Class Local Console Subclass Error Code definitions.
+//
+
+//
+// Peripheral Class Remote Console Subclass Error Code definitions.
+//
+
+//
+// Peripheral Class Serial Port Subclass Error Code definitions.
+//
+
+//
+// Peripheral Class Parallel Port Subclass Error Code definitions.
+//
+
+//
+// Peripheral Class Fixed Media Subclass Error Code definitions.
+//
+
+//
+// Peripheral Class Removable Media Subclass Error Code definitions.
+//
+
+//
+// Peripheral Class Audio Input Subclass Error Code definitions.
+//
+
+//
+// Peripheral Class Audio Output Subclass Error Code definitions.
+//
+
+//
+// Peripheral Class LCD Device Subclass Error Code definitions.
+//
+
+//
+// Peripheral Class Network Subclass Error Code definitions.
+//
+
+///
+/// IO Bus Subclass definitions.
+/// Values of 14-127 are reserved for future use by this specification.
+/// Values of 128-255 are reserved for OEM use.
+///
+///@{
+#define EFI_IO_BUS_UNSPECIFIED (EFI_IO_BUS | 0x00000000)
+#define EFI_IO_BUS_PCI (EFI_IO_BUS | 0x00010000)
+#define EFI_IO_BUS_USB (EFI_IO_BUS | 0x00020000)
+#define EFI_IO_BUS_IBA (EFI_IO_BUS | 0x00030000)
+#define EFI_IO_BUS_AGP (EFI_IO_BUS | 0x00040000)
+#define EFI_IO_BUS_PC_CARD (EFI_IO_BUS | 0x00050000)
+#define EFI_IO_BUS_LPC (EFI_IO_BUS | 0x00060000)
+#define EFI_IO_BUS_SCSI (EFI_IO_BUS | 0x00070000)
+#define EFI_IO_BUS_ATA_ATAPI (EFI_IO_BUS | 0x00080000)
+#define EFI_IO_BUS_FC (EFI_IO_BUS | 0x00090000)
+#define EFI_IO_BUS_IP_NETWORK (EFI_IO_BUS | 0x000A0000)
+#define EFI_IO_BUS_SMBUS (EFI_IO_BUS | 0x000B0000)
+#define EFI_IO_BUS_I2C (EFI_IO_BUS | 0x000C0000)
+///@}
+
+///
+/// IO Bus Class Progress Code definitions.
+/// These are shared by all subclasses.
+///
+///@{
+#define EFI_IOB_PC_INIT 0x00000000
+#define EFI_IOB_PC_RESET 0x00000001
+#define EFI_IOB_PC_DISABLE 0x00000002
+#define EFI_IOB_PC_DETECT 0x00000003
+#define EFI_IOB_PC_ENABLE 0x00000004
+#define EFI_IOB_PC_RECONFIG 0x00000005
+#define EFI_IOB_PC_HOTPLUG 0x00000006
+///@}
+
+//
+// IO Bus Class Unspecified Subclass Progress Code definitions.
+//
+
+///
+/// IO Bus Class PCI Subclass Progress Code definitions.
+///
+///@{
+#define EFI_IOB_PCI_BUS_ENUM (EFI_SUBCLASS_SPECIFIC | 0x00000000)
+#define EFI_IOB_PCI_RES_ALLOC (EFI_SUBCLASS_SPECIFIC | 0x00000001)
+#define EFI_IOB_PCI_HPC_INIT (EFI_SUBCLASS_SPECIFIC | 0x00000002)
+///@}
+
+//
+// IO Bus Class USB Subclass Progress Code definitions.
+//
+
+//
+// IO Bus Class IBA Subclass Progress Code definitions.
+//
+
+//
+// IO Bus Class AGP Subclass Progress Code definitions.
+//
+
+//
+// IO Bus Class PC Card Subclass Progress Code definitions.
+//
+
+//
+// IO Bus Class LPC Subclass Progress Code definitions.
+//
+
+//
+// IO Bus Class SCSI Subclass Progress Code definitions.
+//
+
+//
+// IO Bus Class ATA/ATAPI Subclass Progress Code definitions.
+//
+#define EFI_IOB_ATA_BUS_SMART_ENABLE (EFI_SUBCLASS_SPECIFIC | 0x00000000)
+#define EFI_IOB_ATA_BUS_SMART_DISABLE (EFI_SUBCLASS_SPECIFIC | 0x00000001)
+#define EFI_IOB_ATA_BUS_SMART_OVERTHRESHOLD (EFI_SUBCLASS_SPECIFIC | 0x00000002)
+#define EFI_IOB_ATA_BUS_SMART_UNDERTHRESHOLD (EFI_SUBCLASS_SPECIFIC | 0x00000003)
+//
+// IO Bus Class FC Subclass Progress Code definitions.
+//
+
+//
+// IO Bus Class IP Network Subclass Progress Code definitions.
+//
+
+//
+// IO Bus Class SMBUS Subclass Progress Code definitions.
+//
+
+//
+// IO Bus Class I2C Subclass Progress Code definitions.
+//
+
+///
+/// IO Bus Class Error Code definitions.
+/// These are shared by all subclasses.
+///
+///@{
+#define EFI_IOB_EC_NON_SPECIFIC 0x00000000
+#define EFI_IOB_EC_DISABLED 0x00000001
+#define EFI_IOB_EC_NOT_SUPPORTED 0x00000002
+#define EFI_IOB_EC_NOT_DETECTED 0x00000003
+#define EFI_IOB_EC_NOT_CONFIGURED 0x00000004
+#define EFI_IOB_EC_INTERFACE_ERROR 0x00000005
+#define EFI_IOB_EC_CONTROLLER_ERROR 0x00000006
+#define EFI_IOB_EC_READ_ERROR 0x00000007
+#define EFI_IOB_EC_WRITE_ERROR 0x00000008
+#define EFI_IOB_EC_RESOURCE_CONFLICT 0x00000009
+///@}
+
+//
+// IO Bus Class Unspecified Subclass Error Code definitions.
+//
+
+///
+/// IO Bus Class PCI Subclass Error Code definitions.
+///
+///@{
+#define EFI_IOB_PCI_EC_PERR (EFI_SUBCLASS_SPECIFIC | 0x00000000)
+#define EFI_IOB_PCI_EC_SERR (EFI_SUBCLASS_SPECIFIC | 0x00000001)
+///@}
+
+//
+// IO Bus Class USB Subclass Error Code definitions.
+//
+
+//
+// IO Bus Class IBA Subclass Error Code definitions.
+//
+
+//
+// IO Bus Class AGP Subclass Error Code definitions.
+//
+
+//
+// IO Bus Class PC Card Subclass Error Code definitions.
+//
+
+//
+// IO Bus Class LPC Subclass Error Code definitions.
+//
+
+//
+// IO Bus Class SCSI Subclass Error Code definitions.
+//
+
+//
+// IO Bus Class ATA/ATAPI Subclass Error Code definitions.
+//
+#define EFI_IOB_ATA_BUS_SMART_NOTSUPPORTED (EFI_SUBCLASS_SPECIFIC | 0x00000000)
+#define EFI_IOB_ATA_BUS_SMART_DISABLED (EFI_SUBCLASS_SPECIFIC | 0x00000001)
+
+//
+// IO Bus Class FC Subclass Error Code definitions.
+//
+
+//
+// IO Bus Class IP Network Subclass Error Code definitions.
+//
+
+//
+// IO Bus Class SMBUS Subclass Error Code definitions.
+//
+
+//
+// IO Bus Class I2C Subclass Error Code definitions.
+//
+
+///
+/// Software Subclass definitions.
+/// Values of 14-127 are reserved for future use by this specification.
+/// Values of 128-255 are reserved for OEM use.
+///
+///@{
+#define EFI_SOFTWARE_UNSPECIFIED (EFI_SOFTWARE | 0x00000000)
+#define EFI_SOFTWARE_SEC (EFI_SOFTWARE | 0x00010000)
+#define EFI_SOFTWARE_PEI_CORE (EFI_SOFTWARE | 0x00020000)
+#define EFI_SOFTWARE_PEI_MODULE (EFI_SOFTWARE | 0x00030000)
+#define EFI_SOFTWARE_DXE_CORE (EFI_SOFTWARE | 0x00040000)
+#define EFI_SOFTWARE_DXE_BS_DRIVER (EFI_SOFTWARE | 0x00050000)
+#define EFI_SOFTWARE_DXE_RT_DRIVER (EFI_SOFTWARE | 0x00060000)
+#define EFI_SOFTWARE_SMM_DRIVER (EFI_SOFTWARE | 0x00070000)
+#define EFI_SOFTWARE_EFI_APPLICATION (EFI_SOFTWARE | 0x00080000)
+#define EFI_SOFTWARE_EFI_OS_LOADER (EFI_SOFTWARE | 0x00090000)
+#define EFI_SOFTWARE_RT (EFI_SOFTWARE | 0x000A0000)
+#define EFI_SOFTWARE_AL (EFI_SOFTWARE | 0x000B0000)
+#define EFI_SOFTWARE_EBC_EXCEPTION (EFI_SOFTWARE | 0x000C0000)
+#define EFI_SOFTWARE_IA32_EXCEPTION (EFI_SOFTWARE | 0x000D0000)
+#define EFI_SOFTWARE_IPF_EXCEPTION (EFI_SOFTWARE | 0x000E0000)
+#define EFI_SOFTWARE_PEI_SERVICE (EFI_SOFTWARE | 0x000F0000)
+#define EFI_SOFTWARE_EFI_BOOT_SERVICE (EFI_SOFTWARE | 0x00100000)
+#define EFI_SOFTWARE_EFI_RUNTIME_SERVICE (EFI_SOFTWARE | 0x00110000)
+#define EFI_SOFTWARE_EFI_DXE_SERVICE (EFI_SOFTWARE | 0x00120000)
+#define EFI_SOFTWARE_X64_EXCEPTION (EFI_SOFTWARE | 0x00130000)
+#define EFI_SOFTWARE_ARM_EXCEPTION (EFI_SOFTWARE | 0x00140000)
+
+///@}
+
+///
+/// Software Class Progress Code definitions.
+/// These are shared by all subclasses.
+///
+///@{
+#define EFI_SW_PC_INIT 0x00000000
+#define EFI_SW_PC_LOAD 0x00000001
+#define EFI_SW_PC_INIT_BEGIN 0x00000002
+#define EFI_SW_PC_INIT_END 0x00000003
+#define EFI_SW_PC_AUTHENTICATE_BEGIN 0x00000004
+#define EFI_SW_PC_AUTHENTICATE_END 0x00000005
+#define EFI_SW_PC_INPUT_WAIT 0x00000006
+#define EFI_SW_PC_USER_SETUP 0x00000007
+///@}
+
+//
+// Software Class Unspecified Subclass Progress Code definitions.
+//
+
+///
+/// Software Class SEC Subclass Progress Code definitions.
+///
+///@{
+#define EFI_SW_SEC_PC_ENTRY_POINT (EFI_SUBCLASS_SPECIFIC | 0x00000000)
+#define EFI_SW_SEC_PC_HANDOFF_TO_NEXT (EFI_SUBCLASS_SPECIFIC | 0x00000001)
+///@}
+
+///
+/// Software Class PEI Core Subclass Progress Code definitions.
+///
+///@{
+#define EFI_SW_PEI_CORE_PC_ENTRY_POINT (EFI_SUBCLASS_SPECIFIC | 0x00000000)
+#define EFI_SW_PEI_CORE_PC_HANDOFF_TO_NEXT (EFI_SUBCLASS_SPECIFIC | 0x00000001)
+#define EFI_SW_PEI_CORE_PC_RETURN_TO_LAST (EFI_SUBCLASS_SPECIFIC | 0x00000002)
+///@}
+
+///
+/// Software Class PEI Module Subclass Progress Code definitions.
+///
+///@{
+#define EFI_SW_PEI_PC_RECOVERY_BEGIN (EFI_SUBCLASS_SPECIFIC | 0x00000000)
+#define EFI_SW_PEI_PC_CAPSULE_LOAD (EFI_SUBCLASS_SPECIFIC | 0x00000001)
+#define EFI_SW_PEI_PC_CAPSULE_START (EFI_SUBCLASS_SPECIFIC | 0x00000002)
+#define EFI_SW_PEI_PC_RECOVERY_USER (EFI_SUBCLASS_SPECIFIC | 0x00000003)
+#define EFI_SW_PEI_PC_RECOVERY_AUTO (EFI_SUBCLASS_SPECIFIC | 0x00000004)
+#define EFI_SW_PEI_PC_S3_BOOT_SCRIPT (EFI_SUBCLASS_SPECIFIC | 0x00000005)
+#define EFI_SW_PEI_PC_OS_WAKE (EFI_SUBCLASS_SPECIFIC | 0x00000006)
+#define EFI_SW_PEI_PC_S3_STARTED (EFI_SUBCLASS_SPECIFIC | 0x00000007)
+///@}
+
+///
+/// Software Class DXE Core Subclass Progress Code definitions.
+///
+///@{
+#define EFI_SW_DXE_CORE_PC_ENTRY_POINT (EFI_SUBCLASS_SPECIFIC | 0x00000000)
+#define EFI_SW_DXE_CORE_PC_HANDOFF_TO_NEXT (EFI_SUBCLASS_SPECIFIC | 0x00000001)
+#define EFI_SW_DXE_CORE_PC_RETURN_TO_LAST (EFI_SUBCLASS_SPECIFIC | 0x00000002)
+#define EFI_SW_DXE_CORE_PC_START_DRIVER (EFI_SUBCLASS_SPECIFIC | 0x00000003)
+#define EFI_SW_DXE_CORE_PC_ARCH_READY (EFI_SUBCLASS_SPECIFIC | 0x00000004)
+///@}
+
+///
+/// Software Class DXE BS Driver Subclass Progress Code definitions.
+///
+///@{
+#define EFI_SW_DXE_BS_PC_LEGACY_OPROM_INIT (EFI_SUBCLASS_SPECIFIC | 0x00000000)
+#define EFI_SW_DXE_BS_PC_READY_TO_BOOT_EVENT (EFI_SUBCLASS_SPECIFIC | 0x00000001)
+#define EFI_SW_DXE_BS_PC_LEGACY_BOOT_EVENT (EFI_SUBCLASS_SPECIFIC | 0x00000002)
+#define EFI_SW_DXE_BS_PC_EXIT_BOOT_SERVICES_EVENT (EFI_SUBCLASS_SPECIFIC | 0x00000003)
+#define EFI_SW_DXE_BS_PC_VIRTUAL_ADDRESS_CHANGE_EVENT (EFI_SUBCLASS_SPECIFIC | 0x00000004)
+#define EFI_SW_DXE_BS_PC_VARIABLE_SERVICES_INIT (EFI_SUBCLASS_SPECIFIC | 0x00000005)
+#define EFI_SW_DXE_BS_PC_VARIABLE_RECLAIM (EFI_SUBCLASS_SPECIFIC | 0x00000006)
+#define EFI_SW_DXE_BS_PC_ATTEMPT_BOOT_ORDER_EVENT (EFI_SUBCLASS_SPECIFIC | 0x00000007)
+#define EFI_SW_DXE_BS_PC_CONFIG_RESET (EFI_SUBCLASS_SPECIFIC | 0x00000008)
+#define EFI_SW_DXE_BS_PC_CSM_INIT (EFI_SUBCLASS_SPECIFIC | 0x00000009)
+///@}
+
+//
+// Software Class SMM Driver Subclass Progress Code definitions.
+//
+
+//
+// Software Class EFI Application Subclass Progress Code definitions.
+//
+
+//
+// Software Class EFI OS Loader Subclass Progress Code definitions.
+//
+
+///
+/// Software Class EFI RT Subclass Progress Code definitions.
+///
+///@{
+#define EFI_SW_RT_PC_ENTRY_POINT (EFI_SUBCLASS_SPECIFIC | 0x00000000)
+#define EFI_SW_RT_PC_HANDOFF_TO_NEXT (EFI_SUBCLASS_SPECIFIC | 0x00000001)
+#define EFI_SW_RT_PC_RETURN_TO_LAST (EFI_SUBCLASS_SPECIFIC | 0x00000002)
+///@}
+
+//
+// Software Class X64 Exception Subclass Progress Code definitions.
+//
+
+//
+// Software Class ARM Exception Subclass Progress Code definitions.
+//
+
+//
+// Software Class EBC Exception Subclass Progress Code definitions.
+//
+
+//
+// Software Class IA32 Exception Subclass Progress Code definitions.
+//
+
+//
+// Software Class X64 Exception Subclass Progress Code definitions.
+//
+
+//
+// Software Class IPF Exception Subclass Progress Code definitions.
+//
+
+///
+/// Software Class PEI Services Subclass Progress Code definitions.
+///
+///@{
+#define EFI_SW_PS_PC_INSTALL_PPI (EFI_SUBCLASS_SPECIFIC | 0x00000000)
+#define EFI_SW_PS_PC_REINSTALL_PPI (EFI_SUBCLASS_SPECIFIC | 0x00000001)
+#define EFI_SW_PS_PC_LOCATE_PPI (EFI_SUBCLASS_SPECIFIC | 0x00000002)
+#define EFI_SW_PS_PC_NOTIFY_PPI (EFI_SUBCLASS_SPECIFIC | 0x00000003)
+#define EFI_SW_PS_PC_GET_BOOT_MODE (EFI_SUBCLASS_SPECIFIC | 0x00000004)
+#define EFI_SW_PS_PC_SET_BOOT_MODE (EFI_SUBCLASS_SPECIFIC | 0x00000005)
+#define EFI_SW_PS_PC_GET_HOB_LIST (EFI_SUBCLASS_SPECIFIC | 0x00000006)
+#define EFI_SW_PS_PC_CREATE_HOB (EFI_SUBCLASS_SPECIFIC | 0x00000007)
+#define EFI_SW_PS_PC_FFS_FIND_NEXT_VOLUME (EFI_SUBCLASS_SPECIFIC | 0x00000008)
+#define EFI_SW_PS_PC_FFS_FIND_NEXT_FILE (EFI_SUBCLASS_SPECIFIC | 0x00000009)
+#define EFI_SW_PS_PC_FFS_FIND_SECTION_DATA (EFI_SUBCLASS_SPECIFIC | 0x0000000A)
+#define EFI_SW_PS_PC_INSTALL_PEI_MEMORY (EFI_SUBCLASS_SPECIFIC | 0x0000000B)
+#define EFI_SW_PS_PC_ALLOCATE_PAGES (EFI_SUBCLASS_SPECIFIC | 0x0000000C)
+#define EFI_SW_PS_PC_ALLOCATE_POOL (EFI_SUBCLASS_SPECIFIC | 0x0000000D)
+#define EFI_SW_PS_PC_COPY_MEM (EFI_SUBCLASS_SPECIFIC | 0x0000000E)
+#define EFI_SW_PS_PC_SET_MEM (EFI_SUBCLASS_SPECIFIC | 0x0000000F)
+#define EFI_SW_PS_PC_RESET_SYSTEM (EFI_SUBCLASS_SPECIFIC | 0x00000010)
+#define EFI_SW_PS_PC_FFS_FIND_FILE_BY_NAME (EFI_SUBCLASS_SPECIFIC | 0x00000013)
+#define EFI_SW_PS_PC_FFS_GET_FILE_INFO (EFI_SUBCLASS_SPECIFIC | 0x00000014)
+#define EFI_SW_PS_PC_FFS_GET_VOLUME_INFO (EFI_SUBCLASS_SPECIFIC | 0x00000015)
+#define EFI_SW_PS_PC_FFS_REGISTER_FOR_SHADOW (EFI_SUBCLASS_SPECIFIC | 0x00000016)
+///@}
+
+///
+/// Software Class EFI Boot Services Subclass Progress Code definitions.
+///
+///@{
+#define EFI_SW_BS_PC_RAISE_TPL (EFI_SUBCLASS_SPECIFIC | 0x00000000)
+#define EFI_SW_BS_PC_RESTORE_TPL (EFI_SUBCLASS_SPECIFIC | 0x00000001)
+#define EFI_SW_BS_PC_ALLOCATE_PAGES (EFI_SUBCLASS_SPECIFIC | 0x00000002)
+#define EFI_SW_BS_PC_FREE_PAGES (EFI_SUBCLASS_SPECIFIC | 0x00000003)
+#define EFI_SW_BS_PC_GET_MEMORY_MAP (EFI_SUBCLASS_SPECIFIC | 0x00000004)
+#define EFI_SW_BS_PC_ALLOCATE_POOL (EFI_SUBCLASS_SPECIFIC | 0x00000005)
+#define EFI_SW_BS_PC_FREE_POOL (EFI_SUBCLASS_SPECIFIC | 0x00000006)
+#define EFI_SW_BS_PC_CREATE_EVENT (EFI_SUBCLASS_SPECIFIC | 0x00000007)
+#define EFI_SW_BS_PC_SET_TIMER (EFI_SUBCLASS_SPECIFIC | 0x00000008)
+#define EFI_SW_BS_PC_WAIT_FOR_EVENT (EFI_SUBCLASS_SPECIFIC | 0x00000009)
+#define EFI_SW_BS_PC_SIGNAL_EVENT (EFI_SUBCLASS_SPECIFIC | 0x0000000A)
+#define EFI_SW_BS_PC_CLOSE_EVENT (EFI_SUBCLASS_SPECIFIC | 0x0000000B)
+#define EFI_SW_BS_PC_CHECK_EVENT (EFI_SUBCLASS_SPECIFIC | 0x0000000C)
+#define EFI_SW_BS_PC_INSTALL_PROTOCOL_INTERFACE (EFI_SUBCLASS_SPECIFIC | 0x0000000D)
+#define EFI_SW_BS_PC_REINSTALL_PROTOCOL_INTERFACE (EFI_SUBCLASS_SPECIFIC | 0x0000000E)
+#define EFI_SW_BS_PC_UNINSTALL_PROTOCOL_INTERFACE (EFI_SUBCLASS_SPECIFIC | 0x0000000F)
+#define EFI_SW_BS_PC_HANDLE_PROTOCOL (EFI_SUBCLASS_SPECIFIC | 0x00000010)
+#define EFI_SW_BS_PC_PC_HANDLE_PROTOCOL (EFI_SUBCLASS_SPECIFIC | 0x00000011)
+#define EFI_SW_BS_PC_REGISTER_PROTOCOL_NOTIFY (EFI_SUBCLASS_SPECIFIC | 0x00000012)
+#define EFI_SW_BS_PC_LOCATE_HANDLE (EFI_SUBCLASS_SPECIFIC | 0x00000013)
+#define EFI_SW_BS_PC_INSTALL_CONFIGURATION_TABLE (EFI_SUBCLASS_SPECIFIC | 0x00000014)
+#define EFI_SW_BS_PC_LOAD_IMAGE (EFI_SUBCLASS_SPECIFIC | 0x00000015)
+#define EFI_SW_BS_PC_START_IMAGE (EFI_SUBCLASS_SPECIFIC | 0x00000016)
+#define EFI_SW_BS_PC_EXIT (EFI_SUBCLASS_SPECIFIC | 0x00000017)
+#define EFI_SW_BS_PC_UNLOAD_IMAGE (EFI_SUBCLASS_SPECIFIC | 0x00000018)
+#define EFI_SW_BS_PC_EXIT_BOOT_SERVICES (EFI_SUBCLASS_SPECIFIC | 0x00000019)
+#define EFI_SW_BS_PC_GET_NEXT_MONOTONIC_COUNT (EFI_SUBCLASS_SPECIFIC | 0x0000001A)
+#define EFI_SW_BS_PC_STALL (EFI_SUBCLASS_SPECIFIC | 0x0000001B)
+#define EFI_SW_BS_PC_SET_WATCHDOG_TIMER (EFI_SUBCLASS_SPECIFIC | 0x0000001C)
+#define EFI_SW_BS_PC_CONNECT_CONTROLLER (EFI_SUBCLASS_SPECIFIC | 0x0000001D)
+#define EFI_SW_BS_PC_DISCONNECT_CONTROLLER (EFI_SUBCLASS_SPECIFIC | 0x0000001E)
+#define EFI_SW_BS_PC_OPEN_PROTOCOL (EFI_SUBCLASS_SPECIFIC | 0x0000001F)
+#define EFI_SW_BS_PC_CLOSE_PROTOCOL (EFI_SUBCLASS_SPECIFIC | 0x00000020)
+#define EFI_SW_BS_PC_OPEN_PROTOCOL_INFORMATION (EFI_SUBCLASS_SPECIFIC | 0x00000021)
+#define EFI_SW_BS_PC_PROTOCOLS_PER_HANDLE (EFI_SUBCLASS_SPECIFIC | 0x00000022)
+#define EFI_SW_BS_PC_LOCATE_HANDLE_BUFFER (EFI_SUBCLASS_SPECIFIC | 0x00000023)
+#define EFI_SW_BS_PC_LOCATE_PROTOCOL (EFI_SUBCLASS_SPECIFIC | 0x00000024)
+#define EFI_SW_BS_PC_INSTALL_MULTIPLE_INTERFACES (EFI_SUBCLASS_SPECIFIC | 0x00000025)
+#define EFI_SW_BS_PC_UNINSTALL_MULTIPLE_INTERFACES (EFI_SUBCLASS_SPECIFIC | 0x00000026)
+#define EFI_SW_BS_PC_CALCULATE_CRC_32 (EFI_SUBCLASS_SPECIFIC | 0x00000027)
+#define EFI_SW_BS_PC_COPY_MEM (EFI_SUBCLASS_SPECIFIC | 0x00000028)
+#define EFI_SW_BS_PC_SET_MEM (EFI_SUBCLASS_SPECIFIC | 0x00000029)
+#define EFI_SW_BS_PC_CREATE_EVENT_EX (EFI_SUBCLASS_SPECIFIC | 0x0000002A)
+///@}
+
+///
+/// Software Class EFI Runtime Services Subclass Progress Code definitions.
+///
+///@{
+#define EFI_SW_RS_PC_GET_TIME (EFI_SUBCLASS_SPECIFIC | 0x00000000)
+#define EFI_SW_RS_PC_SET_TIME (EFI_SUBCLASS_SPECIFIC | 0x00000001)
+#define EFI_SW_RS_PC_GET_WAKEUP_TIME (EFI_SUBCLASS_SPECIFIC | 0x00000002)
+#define EFI_SW_RS_PC_SET_WAKEUP_TIME (EFI_SUBCLASS_SPECIFIC | 0x00000003)
+#define EFI_SW_RS_PC_SET_VIRTUAL_ADDRESS_MAP (EFI_SUBCLASS_SPECIFIC | 0x00000004)
+#define EFI_SW_RS_PC_CONVERT_POINTER (EFI_SUBCLASS_SPECIFIC | 0x00000005)
+#define EFI_SW_RS_PC_GET_VARIABLE (EFI_SUBCLASS_SPECIFIC | 0x00000006)
+#define EFI_SW_RS_PC_GET_NEXT_VARIABLE_NAME (EFI_SUBCLASS_SPECIFIC | 0x00000007)
+#define EFI_SW_RS_PC_SET_VARIABLE (EFI_SUBCLASS_SPECIFIC | 0x00000008)
+#define EFI_SW_RS_PC_GET_NEXT_HIGH_MONOTONIC_COUNT (EFI_SUBCLASS_SPECIFIC | 0x00000009)
+#define EFI_SW_RS_PC_RESET_SYSTEM (EFI_SUBCLASS_SPECIFIC | 0x0000000A)
+#define EFI_SW_RS_PC_UPDATE_CAPSULE (EFI_SUBCLASS_SPECIFIC | 0x0000000B)
+#define EFI_SW_RS_PC_QUERY_CAPSULE_CAPABILITIES (EFI_SUBCLASS_SPECIFIC | 0x0000000C)
+#define EFI_SW_RS_PC_QUERY_VARIABLE_INFO (EFI_SUBCLASS_SPECIFIC | 0x0000000D)
+///@}
+
+///
+/// Software Class EFI DXE Services Subclass Progress Code definitions
+///
+///@{
+#define EFI_SW_DS_PC_ADD_MEMORY_SPACE (EFI_SUBCLASS_SPECIFIC | 0x00000000)
+#define EFI_SW_DS_PC_ALLOCATE_MEMORY_SPACE (EFI_SUBCLASS_SPECIFIC | 0x00000001)
+#define EFI_SW_DS_PC_FREE_MEMORY_SPACE (EFI_SUBCLASS_SPECIFIC | 0x00000002)
+#define EFI_SW_DS_PC_REMOVE_MEMORY_SPACE (EFI_SUBCLASS_SPECIFIC | 0x00000003)
+#define EFI_SW_DS_PC_GET_MEMORY_SPACE_DESCRIPTOR (EFI_SUBCLASS_SPECIFIC | 0x00000004)
+#define EFI_SW_DS_PC_SET_MEMORY_SPACE_ATTRIBUTES (EFI_SUBCLASS_SPECIFIC | 0x00000005)
+#define EFI_SW_DS_PC_GET_MEMORY_SPACE_MAP (EFI_SUBCLASS_SPECIFIC | 0x00000006)
+#define EFI_SW_DS_PC_ADD_IO_SPACE (EFI_SUBCLASS_SPECIFIC | 0x00000007)
+#define EFI_SW_DS_PC_ALLOCATE_IO_SPACE (EFI_SUBCLASS_SPECIFIC | 0x00000008)
+#define EFI_SW_DS_PC_FREE_IO_SPACE (EFI_SUBCLASS_SPECIFIC | 0x00000009)
+#define EFI_SW_DS_PC_REMOVE_IO_SPACE (EFI_SUBCLASS_SPECIFIC | 0x0000000A)
+#define EFI_SW_DS_PC_GET_IO_SPACE_DESCRIPTOR (EFI_SUBCLASS_SPECIFIC | 0x0000000B)
+#define EFI_SW_DS_PC_GET_IO_SPACE_MAP (EFI_SUBCLASS_SPECIFIC | 0x0000000C)
+#define EFI_SW_DS_PC_DISPATCH (EFI_SUBCLASS_SPECIFIC | 0x0000000D)
+#define EFI_SW_DS_PC_SCHEDULE (EFI_SUBCLASS_SPECIFIC | 0x0000000E)
+#define EFI_SW_DS_PC_TRUST (EFI_SUBCLASS_SPECIFIC | 0x0000000F)
+#define EFI_SW_DS_PC_PROCESS_FIRMWARE_VOLUME (EFI_SUBCLASS_SPECIFIC | 0x00000010)
+///@}
+
+///
+/// Software Class Error Code definitions.
+/// These are shared by all subclasses.
+///
+///@{
+#define EFI_SW_EC_NON_SPECIFIC 0x00000000
+#define EFI_SW_EC_LOAD_ERROR 0x00000001
+#define EFI_SW_EC_INVALID_PARAMETER 0x00000002
+#define EFI_SW_EC_UNSUPPORTED 0x00000003
+#define EFI_SW_EC_INVALID_BUFFER 0x00000004
+#define EFI_SW_EC_OUT_OF_RESOURCES 0x00000005
+#define EFI_SW_EC_ABORTED 0x00000006
+#define EFI_SW_EC_ILLEGAL_SOFTWARE_STATE 0x00000007
+#define EFI_SW_EC_ILLEGAL_HARDWARE_STATE 0x00000008
+#define EFI_SW_EC_START_ERROR 0x00000009
+#define EFI_SW_EC_BAD_DATE_TIME 0x0000000A
+#define EFI_SW_EC_CFG_INVALID 0x0000000B
+#define EFI_SW_EC_CFG_CLR_REQUEST 0x0000000C
+#define EFI_SW_EC_CFG_DEFAULT 0x0000000D
+#define EFI_SW_EC_PWD_INVALID 0x0000000E
+#define EFI_SW_EC_PWD_CLR_REQUEST 0x0000000F
+#define EFI_SW_EC_PWD_CLEARED 0x00000010
+#define EFI_SW_EC_EVENT_LOG_FULL 0x00000011
+#define EFI_SW_EC_WRITE_PROTECTED 0x00000012
+#define EFI_SW_EC_FV_CORRUPTED 0x00000013
+///@}
+
+//
+// Software Class Unspecified Subclass Error Code definitions.
+//
+
+//
+// Software Class SEC Subclass Error Code definitions.
+//
+
+///
+/// Software Class PEI Core Subclass Error Code definitions.
+///
+///@{
+#define EFI_SW_PEI_CORE_EC_DXE_CORRUPT (EFI_SUBCLASS_SPECIFIC | 0x00000000)
+#define EFI_SW_PEI_CORE_EC_DXEIPL_NOT_FOUND (EFI_SUBCLASS_SPECIFIC | 0x00000001)
+#define EFI_SW_PEI_CORE_EC_MEMORY_NOT_INSTALLED (EFI_SUBCLASS_SPECIFIC | 0x00000002)
+///@}
+
+///
+/// Software Class PEI Module Subclass Error Code definitions.
+///
+///@{
+#define EFI_SW_PEI_EC_NO_RECOVERY_CAPSULE (EFI_SUBCLASS_SPECIFIC | 0x00000000)
+#define EFI_SW_PEI_EC_INVALID_CAPSULE_DESCRIPTOR (EFI_SUBCLASS_SPECIFIC | 0x00000001)
+#define EFI_SW_PEI_EC_S3_RESUME_PPI_NOT_FOUND (EFI_SUBCLASS_SPECIFIC | 0x00000002)
+#define EFI_SW_PEI_EC_S3_BOOT_SCRIPT_ERROR (EFI_SUBCLASS_SPECIFIC | 0x00000003)
+#define EFI_SW_PEI_EC_S3_OS_WAKE_ERROR (EFI_SUBCLASS_SPECIFIC | 0x00000004)
+#define EFI_SW_PEI_EC_S3_RESUME_FAILED (EFI_SUBCLASS_SPECIFIC | 0x00000005)
+#define EFI_SW_PEI_EC_RECOVERY_PPI_NOT_FOUND (EFI_SUBCLASS_SPECIFIC | 0x00000006)
+#define EFI_SW_PEI_EC_RECOVERY_FAILED (EFI_SUBCLASS_SPECIFIC | 0x00000007)
+#define EFI_SW_PEI_EC_S3_RESUME_ERROR (EFI_SUBCLASS_SPECIFIC | 0x00000008)
+#define EFI_SW_PEI_EC_INVALID_CAPSULE (EFI_SUBCLASS_SPECIFIC | 0x00000009)
+///@}
+
+///
+/// Software Class DXE Foundation Subclass Error Code definitions.
+///
+///@{
+#define EFI_SW_DXE_CORE_EC_NO_ARCH (EFI_SUBCLASS_SPECIFIC | 0x00000000)
+///@}
+
+///
+/// Software Class DXE Boot Service Driver Subclass Error Code definitions.
+///
+///@{
+#define EFI_SW_DXE_BS_EC_LEGACY_OPROM_NO_SPACE (EFI_SUBCLASS_SPECIFIC | 0x00000000)
+#define EFI_SW_DXE_BS_EC_INVALID_PASSWORD (EFI_SUBCLASS_SPECIFIC | 0x00000001)
+#define EFI_SW_DXE_BS_EC_BOOT_OPTION_LOAD_ERROR (EFI_SUBCLASS_SPECIFIC | 0x00000002)
+#define EFI_SW_DXE_BS_EC_BOOT_OPTION_FAILED (EFI_SUBCLASS_SPECIFIC | 0x00000003)
+#define EFI_SW_DXE_BS_EC_INVALID_IDE_PASSWORD (EFI_SUBCLASS_SPECIFIC | 0x00000004)
+///@}
+
+//
+// Software Class DXE Runtime Service Driver Subclass Error Code definitions.
+//
+
+//
+// Software Class SMM Driver Subclass Error Code definitions.
+//
+
+//
+// Software Class EFI Application Subclass Error Code definitions.
+//
+
+//
+// Software Class EFI OS Loader Subclass Error Code definitions.
+//
+
+//
+// Software Class EFI RT Subclass Error Code definitions.
+//
+
+//
+// Software Class EFI AL Subclass Error Code definitions.
+//
+
+///
+/// Software Class EBC Exception Subclass Error Code definitions.
+/// These exceptions are derived from the debug protocol definitions in the EFI
+/// specification.
+///
+///@{
+#define EFI_SW_EC_EBC_UNDEFINED 0x00000000
+#define EFI_SW_EC_EBC_DIVIDE_ERROR EXCEPT_EBC_DIVIDE_ERROR
+#define EFI_SW_EC_EBC_DEBUG EXCEPT_EBC_DEBUG
+#define EFI_SW_EC_EBC_BREAKPOINT EXCEPT_EBC_BREAKPOINT
+#define EFI_SW_EC_EBC_OVERFLOW EXCEPT_EBC_OVERFLOW
+#define EFI_SW_EC_EBC_INVALID_OPCODE EXCEPT_EBC_INVALID_OPCODE
+#define EFI_SW_EC_EBC_STACK_FAULT EXCEPT_EBC_STACK_FAULT
+#define EFI_SW_EC_EBC_ALIGNMENT_CHECK EXCEPT_EBC_ALIGNMENT_CHECK
+#define EFI_SW_EC_EBC_INSTRUCTION_ENCODING EXCEPT_EBC_INSTRUCTION_ENCODING
+#define EFI_SW_EC_EBC_BAD_BREAK EXCEPT_EBC_BAD_BREAK
+#define EFI_SW_EC_EBC_STEP EXCEPT_EBC_STEP
+///@}
+
+///
+/// Software Class IA32 Exception Subclass Error Code definitions.
+/// These exceptions are derived from the debug protocol definitions in the EFI
+/// specification.
+///
+///@{
+#define EFI_SW_EC_IA32_DIVIDE_ERROR EXCEPT_IA32_DIVIDE_ERROR
+#define EFI_SW_EC_IA32_DEBUG EXCEPT_IA32_DEBUG
+#define EFI_SW_EC_IA32_NMI EXCEPT_IA32_NMI
+#define EFI_SW_EC_IA32_BREAKPOINT EXCEPT_IA32_BREAKPOINT
+#define EFI_SW_EC_IA32_OVERFLOW EXCEPT_IA32_OVERFLOW
+#define EFI_SW_EC_IA32_BOUND EXCEPT_IA32_BOUND
+#define EFI_SW_EC_IA32_INVALID_OPCODE EXCEPT_IA32_INVALID_OPCODE
+#define EFI_SW_EC_IA32_DOUBLE_FAULT EXCEPT_IA32_DOUBLE_FAULT
+#define EFI_SW_EC_IA32_INVALID_TSS EXCEPT_IA32_INVALID_TSS
+#define EFI_SW_EC_IA32_SEG_NOT_PRESENT EXCEPT_IA32_SEG_NOT_PRESENT
+#define EFI_SW_EC_IA32_STACK_FAULT EXCEPT_IA32_STACK_FAULT
+#define EFI_SW_EC_IA32_GP_FAULT EXCEPT_IA32_GP_FAULT
+#define EFI_SW_EC_IA32_PAGE_FAULT EXCEPT_IA32_PAGE_FAULT
+#define EFI_SW_EC_IA32_FP_ERROR EXCEPT_IA32_FP_ERROR
+#define EFI_SW_EC_IA32_ALIGNMENT_CHECK EXCEPT_IA32_ALIGNMENT_CHECK
+#define EFI_SW_EC_IA32_MACHINE_CHECK EXCEPT_IA32_MACHINE_CHECK
+#define EFI_SW_EC_IA32_SIMD EXCEPT_IA32_SIMD
+///@}
+
+///
+/// Software Class IPF Exception Subclass Error Code definitions.
+/// These exceptions are derived from the debug protocol definitions in the EFI
+/// specification.
+///
+///@{
+#define EFI_SW_EC_IPF_ALT_DTLB EXCEPT_IPF_ALT_DTLB
+#define EFI_SW_EC_IPF_DNESTED_TLB EXCEPT_IPF_DNESTED_TLB
+#define EFI_SW_EC_IPF_BREAKPOINT EXCEPT_IPF_BREAKPOINT
+#define EFI_SW_EC_IPF_EXTERNAL_INTERRUPT EXCEPT_IPF_EXTERNAL_INTERRUPT
+#define EFI_SW_EC_IPF_GEN_EXCEPT EXCEPT_IPF_GEN_EXCEPT
+#define EFI_SW_EC_IPF_NAT_CONSUMPTION EXCEPT_IPF_NAT_CONSUMPTION
+#define EFI_SW_EC_IPF_DEBUG_EXCEPT EXCEPT_IPF_DEBUG_EXCEPT
+#define EFI_SW_EC_IPF_UNALIGNED_ACCESS EXCEPT_IPF_UNALIGNED_ACCESS
+#define EFI_SW_EC_IPF_FP_FAULT EXCEPT_IPF_FP_FAULT
+#define EFI_SW_EC_IPF_FP_TRAP EXCEPT_IPF_FP_TRAP
+#define EFI_SW_EC_IPF_TAKEN_BRANCH EXCEPT_IPF_TAKEN_BRANCH
+#define EFI_SW_EC_IPF_SINGLE_STEP EXCEPT_IPF_SINGLE_STEP
+///@}
+
+///
+/// Software Class PEI Service Subclass Error Code definitions.
+///
+///@{
+#define EFI_SW_PS_EC_RESET_NOT_AVAILABLE (EFI_SUBCLASS_SPECIFIC | 0x00000000)
+#define EFI_SW_PS_EC_MEMORY_INSTALLED_TWICE (EFI_SUBCLASS_SPECIFIC | 0x00000001)
+///@}
+
+//
+// Software Class EFI Boot Service Subclass Error Code definitions.
+//
+
+//
+// Software Class EFI Runtime Service Subclass Error Code definitions.
+//
+
+///
+/// Software Class EFI DXE Service Subclass Error Code definitions.
+///
+///@{
+#define EFI_SW_DXE_BS_PC_BEGIN_CONNECTING_DRIVERS (EFI_SUBCLASS_SPECIFIC | 0x00000005)
+#define EFI_SW_DXE_BS_PC_VERIFYING_PASSWORD (EFI_SUBCLASS_SPECIFIC | 0x00000006)
+///@}
+
+///
+/// Software Class DXE RT Driver Subclass Progress Code definitions.
+///
+///@{
+#define EFI_SW_DXE_RT_PC_S0 (EFI_SUBCLASS_SPECIFIC | 0x00000000)
+#define EFI_SW_DXE_RT_PC_S1 (EFI_SUBCLASS_SPECIFIC | 0x00000001)
+#define EFI_SW_DXE_RT_PC_S2 (EFI_SUBCLASS_SPECIFIC | 0x00000002)
+#define EFI_SW_DXE_RT_PC_S3 (EFI_SUBCLASS_SPECIFIC | 0x00000003)
+#define EFI_SW_DXE_RT_PC_S4 (EFI_SUBCLASS_SPECIFIC | 0x00000004)
+#define EFI_SW_DXE_RT_PC_S5 (EFI_SUBCLASS_SPECIFIC | 0x00000005)
+///@}
+
+///
+/// Software Class X64 Exception Subclass Error Code definitions.
+/// These exceptions are derived from the debug protocol
+/// definitions in the EFI specification.
+///
+///@{
+#define EFI_SW_EC_X64_DIVIDE_ERROR EXCEPT_X64_DIVIDE_ERROR
+#define EFI_SW_EC_X64_DEBUG EXCEPT_X64_DEBUG
+#define EFI_SW_EC_X64_NMI EXCEPT_X64_NMI
+#define EFI_SW_EC_X64_BREAKPOINT EXCEPT_X64_BREAKPOINT
+#define EFI_SW_EC_X64_OVERFLOW EXCEPT_X64_OVERFLOW
+#define EFI_SW_EC_X64_BOUND EXCEPT_X64_BOUND
+#define EFI_SW_EC_X64_INVALID_OPCODE EXCEPT_X64_INVALID_OPCODE
+#define EFI_SW_EC_X64_DOUBLE_FAULT EXCEPT_X64_DOUBLE_FAULT
+#define EFI_SW_EC_X64_INVALID_TSS EXCEPT_X64_INVALID_TSS
+#define EFI_SW_EC_X64_SEG_NOT_PRESENT EXCEPT_X64_SEG_NOT_PRESENT
+#define EFI_SW_EC_X64_STACK_FAULT EXCEPT_X64_STACK_FAULT
+#define EFI_SW_EC_X64_GP_FAULT EXCEPT_X64_GP_FAULT
+#define EFI_SW_EC_X64_PAGE_FAULT EXCEPT_X64_PAGE_FAULT
+#define EFI_SW_EC_X64_FP_ERROR EXCEPT_X64_FP_ERROR
+#define EFI_SW_EC_X64_ALIGNMENT_CHECK EXCEPT_X64_ALIGNMENT_CHECK
+#define EFI_SW_EC_X64_MACHINE_CHECK EXCEPT_X64_MACHINE_CHECK
+#define EFI_SW_EC_X64_SIMD EXCEPT_X64_SIMD
+///@}
+
+///
+/// Software Class ARM Exception Subclass Error Code definitions.
+/// These exceptions are derived from the debug protocol
+/// definitions in the EFI specification.
+///
+///@{
+#define EFI_SW_EC_ARM_RESET EXCEPT_ARM_RESET
+#define EFI_SW_EC_ARM_UNDEFINED_INSTRUCTION EXCEPT_ARM_UNDEFINED_INSTRUCTION
+#define EFI_SW_EC_ARM_SOFTWARE_INTERRUPT EXCEPT_ARM_SOFTWARE_INTERRUPT
+#define EFI_SW_EC_ARM_PREFETCH_ABORT EXCEPT_ARM_PREFETCH_ABORT
+#define EFI_SW_EC_ARM_DATA_ABORT EXCEPT_ARM_DATA_ABORT
+#define EFI_SW_EC_ARM_RESERVED EXCEPT_ARM_RESERVED
+#define EFI_SW_EC_ARM_IRQ EXCEPT_ARM_IRQ
+#define EFI_SW_EC_ARM_FIQ EXCEPT_ARM_FIQ
+///@}
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/PiDxe.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/PiDxe.h
new file mode 100644
index 0000000000..2911adeb8e
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/PiDxe.h
@@ -0,0 +1,18 @@
+/** @file
+
+ Root include file for Mde Package DXE_CORE, DXE, RUNTIME, SMM, SAL type modules.
+
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __PI_DXE_H__
+#define __PI_DXE_H__
+
+#include
+#include
+
+#include
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/PiMm.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/PiMm.h
new file mode 100644
index 0000000000..db253e4305
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/PiMm.h
@@ -0,0 +1,18 @@
+/** @file
+
+ Root include file for Mde Package MM modules.
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __PI_MM_H__
+#define __PI_MM_H__
+
+#include
+#include
+
+#include
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/PiPei.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/PiPei.h
new file mode 100644
index 0000000000..eea9fa3e50
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/PiPei.h
@@ -0,0 +1,20 @@
+/** @file
+
+ Root include file for Mde Package SEC, PEIM, PEI_CORE type modules.
+
+ This is the include file for any module of type PEIM. PEIM
+ modules only use types defined via this include file and can
+ be ported easily to any environment.
+
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __PI_PEI_H__
+#define __PI_PEI_H__
+
+#include
+#include
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/PiSmm.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/PiSmm.h
new file mode 100644
index 0000000000..4fccf89f7f
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/PiSmm.h
@@ -0,0 +1,18 @@
+/** @file
+
+ Root include file for Mde Package SMM modules.
+
+Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __PI_SMM_H__
+#define __PI_SMM_H__
+
+#include
+#include
+
+#include
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Ppi/BlockIo.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Ppi/BlockIo.h
new file mode 100644
index 0000000000..4f3227db5b
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Ppi/BlockIo.h
@@ -0,0 +1,232 @@
+/** @file
+ Provides the services required to access a block I/O device during PEI recovery
+ boot mode.
+
+ The Recovery Module PPI and the Device Recovery Module PPI are device neutral.
+ This PPI is device specific and addresses the most common form of recovery
+ media-block I/O devices such as legacy floppy, CD-ROM, or IDE devices.
+
+ The Recovery Block I/O PPI is used to access block devices. Because the Recovery
+ Block I/O PPIs that are provided by the PEI ATAPI driver and PEI legacy floppy
+ driver are the same, here we define a set of general PPIs for both drivers to use.
+
+Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Revision Reference:
+ This PPI is defined in UEFI Platform Initialization Specification 1.2 Volume 1:
+ Pre-EFI Initialization Core Interface.
+
+**/
+
+#ifndef _PEI_BLOCK_IO_H_
+#define _PEI_BLOCK_IO_H_
+
+///
+/// Global ID for EFI_PEI_RECOVERY_BLOCK_IO_PPI
+///
+#define EFI_PEI_RECOVERY_BLOCK_IO_PPI_GUID \
+ { \
+ 0x695d8aa1, 0x42ee, 0x4c46, { 0x80, 0x5c, 0x6e, 0xa6, 0xbc, 0xe7, 0x99, 0xe3 } \
+ }
+
+///
+/// The forward declaration for EFI_PEI_RECOVERY_BLOCK_IO_PPI.
+///
+typedef struct _EFI_PEI_RECOVERY_BLOCK_IO_PPI EFI_PEI_RECOVERY_BLOCK_IO_PPI;
+
+///
+/// All blocks on the recovery device are addressed with a 64-bit Logical Block Address (LBA).
+///
+typedef UINT64 EFI_PEI_LBA;
+
+///
+/// EFI_PEI_BLOCK_DEVICE_TYPE
+///
+typedef enum {
+ LegacyFloppy = 0, ///< The recovery device is a floppy.
+ IdeCDROM = 1, ///< The recovery device is an IDE CD-ROM
+ IdeLS120 = 2, ///< The recovery device is an IDE LS-120
+ UsbMassStorage = 3, ///< The recovery device is a USB Mass Storage device
+ SD = 4, ///< The recovery device is a Secure Digital device
+ EMMC = 5, ///< The recovery device is a eMMC device
+ UfsDevice = 6, ///< The recovery device is a Universal Flash Storage device
+ MaxDeviceType
+} EFI_PEI_BLOCK_DEVICE_TYPE;
+
+///
+/// Specification inconsistency here:
+/// PEI_BLOCK_IO_MEDIA has been changed to EFI_PEI_BLOCK_IO_MEDIA.
+/// Inconsistency exists in UEFI Platform Initialization Specification 1.2
+/// Volume 1: Pre-EFI Initialization Core Interface, where all references to
+/// this structure name are with the "EFI_" prefix, except for the definition
+/// which is without "EFI_". So the name of PEI_BLOCK_IO_MEDIA is taken as the
+/// exception, and EFI_PEI_BLOCK_IO_MEDIA is used to comply with most of
+/// the specification.
+///
+typedef struct {
+ ///
+ /// The type of media device being referenced by DeviceIndex.
+ ///
+ EFI_PEI_BLOCK_DEVICE_TYPE DeviceType;
+ ///
+ /// A flag that indicates if media is present. This flag is always set for
+ /// nonremovable media devices.
+ ///
+ BOOLEAN MediaPresent;
+ ///
+ /// The last logical block that the device supports.
+ ///
+ UINTN LastBlock;
+ ///
+ /// The size of a logical block in bytes.
+ ///
+ UINTN BlockSize;
+} EFI_PEI_BLOCK_IO_MEDIA;
+
+/**
+ Gets the count of block I/O devices that one specific block driver detects.
+
+ This function is used for getting the count of block I/O devices that one
+ specific block driver detects. To the PEI ATAPI driver, it returns the number
+ of all the detected ATAPI devices it detects during the enumeration process.
+ To the PEI legacy floppy driver, it returns the number of all the legacy
+ devices it finds during its enumeration process. If no device is detected,
+ then the function will return zero.
+
+ @param[in] PeiServices General-purpose services that are available
+ to every PEIM.
+ @param[in] This Indicates the EFI_PEI_RECOVERY_BLOCK_IO_PPI
+ instance.
+ @param[out] NumberBlockDevices The number of block I/O devices discovered.
+
+ @retval EFI_SUCCESS The operation performed successfully.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_PEI_GET_NUMBER_BLOCK_DEVICES)(
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PEI_RECOVERY_BLOCK_IO_PPI *This,
+ OUT UINTN *NumberBlockDevices
+ );
+
+/**
+ Gets a block device's media information.
+
+ This function will provide the caller with the specified block device's media
+ information. If the media changes, calling this function will update the media
+ information accordingly.
+
+ @param[in] PeiServices General-purpose services that are available to every
+ PEIM
+ @param[in] This Indicates the EFI_PEI_RECOVERY_BLOCK_IO_PPI instance.
+ @param[in] DeviceIndex Specifies the block device to which the function wants
+ to talk. Because the driver that implements Block I/O
+ PPIs will manage multiple block devices, the PPIs that
+ want to talk to a single device must specify the
+ device index that was assigned during the enumeration
+ process. This index is a number from one to
+ NumberBlockDevices.
+ @param[out] MediaInfo The media information of the specified block media.
+ The caller is responsible for the ownership of this
+ data structure.
+
+ @par Note:
+ The MediaInfo structure describes an enumeration of possible block device
+ types. This enumeration exists because no device paths are actually passed
+ across interfaces that describe the type or class of hardware that is publishing
+ the block I/O interface. This enumeration will allow for policy decisions
+ in the Recovery PEIM, such as "Try to recover from legacy floppy first,
+ LS-120 second, CD-ROM third." If there are multiple partitions abstracted
+ by a given device type, they should be reported in ascending order; this
+ order also applies to nested partitions, such as legacy MBR, where the
+ outermost partitions would have precedence in the reporting order. The
+ same logic applies to systems such as IDE that have precedence relationships
+ like "Master/Slave" or "Primary/Secondary". The master device should be
+ reported first, the slave second.
+
+ @retval EFI_SUCCESS Media information about the specified block device
+ was obtained successfully.
+ @retval EFI_DEVICE_ERROR Cannot get the media information due to a hardware
+ error.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_PEI_GET_DEVICE_MEDIA_INFORMATION)(
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PEI_RECOVERY_BLOCK_IO_PPI *This,
+ IN UINTN DeviceIndex,
+ OUT EFI_PEI_BLOCK_IO_MEDIA *MediaInfo
+ );
+
+/**
+ Reads the requested number of blocks from the specified block device.
+
+ The function reads the requested number of blocks from the device. All the
+ blocks are read, or an error is returned. If there is no media in the device,
+ the function returns EFI_NO_MEDIA.
+
+ @param[in] PeiServices General-purpose services that are available to
+ every PEIM.
+ @param[in] This Indicates the EFI_PEI_RECOVERY_BLOCK_IO_PPI instance.
+ @param[in] DeviceIndex Specifies the block device to which the function wants
+ to talk. Because the driver that implements Block I/O
+ PPIs will manage multiple block devices, PPIs that
+ want to talk to a single device must specify the device
+ index that was assigned during the enumeration process.
+ This index is a number from one to NumberBlockDevices.
+ @param[in] StartLBA The starting logical block address (LBA) to read from
+ on the device
+ @param[in] BufferSize The size of the Buffer in bytes. This number must be
+ a multiple of the intrinsic block size of the device.
+ @param[out] Buffer A pointer to the destination buffer for the data.
+ The caller is responsible for the ownership of the
+ buffer.
+
+ @retval EFI_SUCCESS The data was read correctly from the device.
+ @retval EFI_DEVICE_ERROR The device reported an error while attempting
+ to perform the read operation.
+ @retval EFI_INVALID_PARAMETER The read request contains LBAs that are not
+ valid, or the buffer is not properly aligned.
+ @retval EFI_NO_MEDIA There is no media in the device.
+ @retval EFI_BAD_BUFFER_SIZE The BufferSize parameter is not a multiple of
+ the intrinsic block size of the device.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_PEI_READ_BLOCKS)(
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PEI_RECOVERY_BLOCK_IO_PPI *This,
+ IN UINTN DeviceIndex,
+ IN EFI_PEI_LBA StartLBA,
+ IN UINTN BufferSize,
+ OUT VOID *Buffer
+ );
+
+///
+/// EFI_PEI_RECOVERY_BLOCK_IO_PPI provides the services that are required
+/// to access a block I/O device during PEI recovery boot mode.
+///
+struct _EFI_PEI_RECOVERY_BLOCK_IO_PPI {
+ ///
+ /// Gets the number of block I/O devices that the specific block driver manages.
+ ///
+ EFI_PEI_GET_NUMBER_BLOCK_DEVICES GetNumberOfBlockDevices;
+
+ ///
+ /// Gets the specified media information.
+ ///
+ EFI_PEI_GET_DEVICE_MEDIA_INFORMATION GetBlockDeviceMediaInfo;
+
+ ///
+ /// Reads the requested number of blocks from the specified block device.
+ ///
+ EFI_PEI_READ_BLOCKS ReadBlocks;
+};
+
+extern EFI_GUID gEfiPeiVirtualBlockIoPpiGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Ppi/BlockIo2.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Ppi/BlockIo2.h
new file mode 100644
index 0000000000..661b3eff62
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Ppi/BlockIo2.h
@@ -0,0 +1,217 @@
+/** @file
+ Provides the services required to access a block I/O 2 device during PEI recovery
+ boot mode.
+
+Copyright (c) 2015, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Revision Reference:
+ This PPI is defined in UEFI Platform Initialization Specification 1.4 Volume 1:
+ Pre-EFI Initialization Core Interface.
+
+**/
+
+#ifndef _PEI_BLOCK_IO2_H_
+#define _PEI_BLOCK_IO2_H_
+
+#include
+#include
+
+///
+/// Global ID for EFI_PEI_RECOVERY_BLOCK_IO2_PPI
+///
+#define EFI_PEI_RECOVERY_BLOCK_IO2_PPI_GUID \
+ { \
+ 0x26cc0fad, 0xbeb3, 0x478a, { 0x91, 0xb2, 0xc, 0x18, 0x8f, 0x72, 0x61, 0x98 } \
+ }
+
+///
+/// The forward declaration for EFI_PEI_RECOVERY_BLOCK_IO_PPI.
+///
+typedef struct _EFI_PEI_RECOVERY_BLOCK_IO2_PPI EFI_PEI_RECOVERY_BLOCK_IO2_PPI;
+
+#define EFI_PEI_RECOVERY_BLOCK_IO2_PPI_REVISION 0x00010000
+
+typedef struct {
+ ///
+ /// A type of interface that the device being referenced by DeviceIndex is
+ /// attached to. This field re-uses Messaging Device Path Node sub-type values
+ /// as defined by Section 9.3.5 Messaging Device Path of UEFI Specification.
+ /// When more than one sub-type is associated with the interface, sub-type with
+ /// the smallest number must be used.
+ ///
+ UINT8 InterfaceType;
+ ///
+ /// A flag that indicates if media is removable.
+ ///
+ BOOLEAN RemovableMedia;
+ ///
+ /// A flag that indicates if media is present. This flag is always set for
+ /// non-removable media devices.
+ ///
+ BOOLEAN MediaPresent;
+ ///
+ /// A flag that indicates if media is read-only.
+ ///
+ BOOLEAN ReadOnly;
+ ///
+ /// The size of a logical block in bytes.
+ ///
+ UINT32 BlockSize;
+ ///
+ /// The last logical block that the device supports.
+ ///
+ EFI_PEI_LBA LastBlock;
+} EFI_PEI_BLOCK_IO2_MEDIA;
+
+/**
+ Gets the count of block I/O devices that one specific block driver detects.
+
+ This function is used for getting the count of block I/O devices that one
+ specific block driver detects. To the PEI ATAPI driver, it returns the number
+ of all the detected ATAPI devices it detects during the enumeration process.
+ To the PEI legacy floppy driver, it returns the number of all the legacy
+ devices it finds during its enumeration process. If no device is detected,
+ then the function will return zero.
+
+ @param[in] PeiServices General-purpose services that are available
+ to every PEIM.
+ @param[in] This Indicates the EFI_PEI_RECOVERY_BLOCK_IO2_PPI
+ instance.
+ @param[out] NumberBlockDevices The number of block I/O devices discovered.
+
+ @retval EFI_SUCCESS The operation performed successfully.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_PEI_GET_NUMBER_BLOCK_DEVICES2)(
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PEI_RECOVERY_BLOCK_IO2_PPI *This,
+ OUT UINTN *NumberBlockDevices
+ );
+
+/**
+ Gets a block device's media information.
+
+ This function will provide the caller with the specified block device's media
+ information. If the media changes, calling this function will update the media
+ information accordingly.
+
+ @param[in] PeiServices General-purpose services that are available to every
+ PEIM
+ @param[in] This Indicates the EFI_PEI_RECOVERY_BLOCK_IO2_PPI instance.
+ @param[in] DeviceIndex Specifies the block device to which the function wants
+ to talk. Because the driver that implements Block I/O
+ PPIs will manage multiple block devices, the PPIs that
+ want to talk to a single device must specify the
+ device index that was assigned during the enumeration
+ process. This index is a number from one to
+ NumberBlockDevices.
+ @param[out] MediaInfo The media information of the specified block media.
+ The caller is responsible for the ownership of this
+ data structure.
+
+ @par Note:
+ The MediaInfo structure describes an enumeration of possible block device
+ types. This enumeration exists because no device paths are actually passed
+ across interfaces that describe the type or class of hardware that is publishing
+ the block I/O interface. This enumeration will allow for policy decisions
+ in the Recovery PEIM, such as "Try to recover from legacy floppy first,
+ LS-120 second, CD-ROM third." If there are multiple partitions abstracted
+ by a given device type, they should be reported in ascending order; this
+ order also applies to nested partitions, such as legacy MBR, where the
+ outermost partitions would have precedence in the reporting order. The
+ same logic applies to systems such as IDE that have precedence relationships
+ like "Master/Slave" or "Primary/Secondary". The master device should be
+ reported first, the slave second.
+
+ @retval EFI_SUCCESS Media information about the specified block device
+ was obtained successfully.
+ @retval EFI_DEVICE_ERROR Cannot get the media information due to a hardware
+ error.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_PEI_GET_DEVICE_MEDIA_INFORMATION2)(
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PEI_RECOVERY_BLOCK_IO2_PPI *This,
+ IN UINTN DeviceIndex,
+ OUT EFI_PEI_BLOCK_IO2_MEDIA *MediaInfo
+ );
+
+/**
+ Reads the requested number of blocks from the specified block device.
+
+ The function reads the requested number of blocks from the device. All the
+ blocks are read, or an error is returned. If there is no media in the device,
+ the function returns EFI_NO_MEDIA.
+
+ @param[in] PeiServices General-purpose services that are available to
+ every PEIM.
+ @param[in] This Indicates the EFI_PEI_RECOVERY_BLOCK_IO2_PPI instance.
+ @param[in] DeviceIndex Specifies the block device to which the function wants
+ to talk. Because the driver that implements Block I/O
+ PPIs will manage multiple block devices, PPIs that
+ want to talk to a single device must specify the device
+ index that was assigned during the enumeration process.
+ This index is a number from one to NumberBlockDevices.
+ @param[in] StartLBA The starting logical block address (LBA) to read from
+ on the device
+ @param[in] BufferSize The size of the Buffer in bytes. This number must be
+ a multiple of the intrinsic block size of the device.
+ @param[out] Buffer A pointer to the destination buffer for the data.
+ The caller is responsible for the ownership of the
+ buffer.
+
+ @retval EFI_SUCCESS The data was read correctly from the device.
+ @retval EFI_DEVICE_ERROR The device reported an error while attempting
+ to perform the read operation.
+ @retval EFI_INVALID_PARAMETER The read request contains LBAs that are not
+ valid, or the buffer is not properly aligned.
+ @retval EFI_NO_MEDIA There is no media in the device.
+ @retval EFI_BAD_BUFFER_SIZE The BufferSize parameter is not a multiple of
+ the intrinsic block size of the device.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_PEI_READ_BLOCKS2)(
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PEI_RECOVERY_BLOCK_IO2_PPI *This,
+ IN UINTN DeviceIndex,
+ IN EFI_PEI_LBA StartLBA,
+ IN UINTN BufferSize,
+ OUT VOID *Buffer
+ );
+
+///
+/// EFI_PEI_RECOVERY_BLOCK_IO_PPI provides the services that are required
+/// to access a block I/O device during PEI recovery boot mode.
+///
+struct _EFI_PEI_RECOVERY_BLOCK_IO2_PPI {
+ ///
+ /// The revision to which the interface adheres.
+ /// All future revisions must be backwards compatible.
+ ///
+ UINT64 Revision;
+ ///
+ /// Gets the number of block I/O devices that the specific block driver manages.
+ ///
+ EFI_PEI_GET_NUMBER_BLOCK_DEVICES2 GetNumberOfBlockDevices;
+
+ ///
+ /// Gets the specified media information.
+ ///
+ EFI_PEI_GET_DEVICE_MEDIA_INFORMATION2 GetBlockDeviceMediaInfo;
+
+ ///
+ /// Reads the requested number of blocks from the specified block device.
+ ///
+ EFI_PEI_READ_BLOCKS2 ReadBlocks;
+};
+
+extern EFI_GUID gEfiPeiVirtualBlockIo2PpiGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Ppi/BootInRecoveryMode.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Ppi/BootInRecoveryMode.h
new file mode 100644
index 0000000000..e8b0dd6c31
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Ppi/BootInRecoveryMode.h
@@ -0,0 +1,23 @@
+/** @file
+ This PPI is installed by the platform PEIM to designate that a recovery boot
+ is in progress.
+
+ Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Revision Reference:
+ This PPI is introduced in PI Version 1.0.
+
+**/
+
+#ifndef __BOOT_IN_RECOVERY_MODE_PPI_H__
+#define __BOOT_IN_RECOVERY_MODE_PPI_H__
+
+#define EFI_PEI_BOOT_IN_RECOVERY_MODE_PPI \
+ { \
+ 0x17ee496a, 0xd8e4, 0x4b9a, {0x94, 0xd1, 0xce, 0x82, 0x72, 0x30, 0x8, 0x50 } \
+ }
+
+extern EFI_GUID gEfiPeiBootInRecoveryModePpiGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Ppi/Capsule.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Ppi/Capsule.h
new file mode 100644
index 0000000000..8c21a1f9e8
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Ppi/Capsule.h
@@ -0,0 +1,130 @@
+/** @file
+ Defines the APIs that enable PEI services to work with
+ the underlying capsule capabilities of the platform.
+
+Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Revision Reference:
+ This PPI is introduced in PI Version 1.4.
+
+**/
+
+#ifndef _PEI_CAPSULE_PPI_H_
+#define _PEI_CAPSULE_PPI_H_
+
+///
+/// Global ID for the EFI_PEI_CAPSULE_PPI.
+///
+#define EFI_PEI_CAPSULE_PPI_GUID \
+ { \
+ 0x3acf33ee, 0xd892, 0x40f4, {0xa2, 0xfc, 0x38, 0x54, 0xd2, 0xe1, 0x32, 0x3d } \
+ }
+
+///
+/// Forward declaration for the EFI_PEI_CAPSULE_PPI.
+///
+typedef struct _EFI_PEI_CAPSULE_PPI EFI_PEI_CAPSULE_PPI;
+
+///
+/// Keep name backwards compatible before PI Version 1.4
+///
+typedef struct _EFI_PEI_CAPSULE_PPI PEI_CAPSULE_PPI;
+
+/**
+ Upon determining that there is a capsule to operate on, this service
+ will use a series of EFI_CAPSULE_BLOCK_DESCRIPTOR entries to determine
+ the current location of the various capsule fragments and coalesce them
+ into a contiguous region of system memory.
+
+ @param[in] PeiServices Pointer to the PEI Services Table.
+ @param[out] MemoryBase Pointer to the base of a block of memory into which the buffers will be coalesced.
+ On output, this variable will hold the base address
+ of a coalesced capsule.
+ @param[out] MemorySize Size of the memory region pointed to by MemoryBase.
+ On output, this variable will contain the size of the
+ coalesced capsule.
+
+ @retval EFI_NOT_FOUND If: boot mode could not be determined, or the
+ boot mode is not flash-update, or the capsule descriptors were not found.
+ @retval EFI_BUFFER_TOO_SMALL The capsule could not be coalesced in the provided memory region.
+ @retval EFI_SUCCESS There was no capsule, or the capsule was processed successfully.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_PEI_CAPSULE_COALESCE)(
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN OUT VOID **MemoryBase,
+ IN OUT UINTN *MemSize
+ );
+
+/**
+ Determine if a capsule needs to be processed.
+ The means by which the presence of a capsule is determined is platform
+ specific. For example, an implementation could be driven by the presence
+ of a Capsule EFI Variable containing a list of EFI_CAPSULE_BLOCK_DESCRIPTOR
+ entries. If present, return EFI_SUCCESS, otherwise return EFI_NOT_FOUND.
+
+ @param[in] PeiServices Pointer to the PEI Services Table.
+
+ @retval EFI_SUCCESS If a capsule is available.
+ @retval EFI_NOT_FOUND No capsule detected.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_PEI_CAPSULE_CHECK_CAPSULE_UPDATE)(
+ IN EFI_PEI_SERVICES **PeiServices
+ );
+
+/**
+ The Capsule PPI service that gets called after memory is available. The
+ capsule coalesce function, which must be called first, returns a base
+ address and size. Once the memory init PEIM has discovered memory,
+ it should call this function and pass in the base address and size
+ returned by the Coalesce() function. Then this function can create a
+ capsule HOB and return.
+
+ @par Notes:
+ This function assumes it will not be called until the
+ actual capsule update.
+
+ @param[in] PeiServices Pointer to the PEI Services Table.
+ @param[in] CapsuleBase Address returned by the capsule coalesce function.
+ @param[in] CapsuleSize Value returned by the capsule coalesce function.
+
+ @retval EFI_VOLUME_CORRUPTED CapsuleBase does not appear to point to a
+ coalesced capsule.
+ @retval EFI_SUCCESS Capsule HOB was created successfully.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_PEI_CAPSULE_CREATE_STATE)(
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN VOID *CapsuleBase,
+ IN UINTN CapsuleSize
+ );
+
+///
+/// This PPI provides several services in PEI to work with the underlying
+/// capsule capabilities of the platform. These services include the ability
+/// for PEI to coalesce a capsule from a scattered set of memory locations
+/// into a contiguous space in memory, detect if a capsule is present for
+/// processing, and once memory is available, create a HOB for the capsule.
+///
+struct _EFI_PEI_CAPSULE_PPI {
+ EFI_PEI_CAPSULE_COALESCE Coalesce;
+ EFI_PEI_CAPSULE_CHECK_CAPSULE_UPDATE CheckCapsuleUpdate;
+ EFI_PEI_CAPSULE_CREATE_STATE CreateState;
+};
+
+///
+/// Keep name backwards compatible before PI Version 1.4
+///
+extern EFI_GUID gPeiCapsulePpiGuid;
+
+extern EFI_GUID gEfiPeiCapsulePpiGuid;
+
+#endif // #ifndef _PEI_CAPSULE_PPI_H_
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Ppi/CpuIo.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Ppi/CpuIo.h
new file mode 100644
index 0000000000..3e31ae9982
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Ppi/CpuIo.h
@@ -0,0 +1,422 @@
+/** @file
+ This PPI provides a set of memory and I/O-based services.
+ The perspective of the services is that of the processor, not the bus or system.
+
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Revision Reference:
+ This PPI is introduced in PI Version 1.0.
+
+**/
+
+#ifndef __PEI_CPUIO_PPI_H__
+#define __PEI_CPUIO_PPI_H__
+
+#define EFI_PEI_CPU_IO_PPI_INSTALLED_GUID \
+ { 0xe6af1f7b, 0xfc3f, 0x46da, {0xa8, 0x28, 0xa3, 0xb4, 0x57, 0xa4, 0x42, 0x82 } }
+
+typedef struct _EFI_PEI_CPU_IO_PPI EFI_PEI_CPU_IO_PPI;
+
+///
+/// EFI_PEI_CPU_IO_PPI_WIDTH.
+///
+typedef enum {
+ EfiPeiCpuIoWidthUint8,
+ EfiPeiCpuIoWidthUint16,
+ EfiPeiCpuIoWidthUint32,
+ EfiPeiCpuIoWidthUint64,
+ EfiPeiCpuIoWidthFifoUint8,
+ EfiPeiCpuIoWidthFifoUint16,
+ EfiPeiCpuIoWidthFifoUint32,
+ EfiPeiCpuIoWidthFifoUint64,
+ EfiPeiCpuIoWidthFillUint8,
+ EfiPeiCpuIoWidthFillUint16,
+ EfiPeiCpuIoWidthFillUint32,
+ EfiPeiCpuIoWidthFillUint64,
+ EfiPeiCpuIoWidthMaximum
+} EFI_PEI_CPU_IO_PPI_WIDTH;
+
+/**
+ Memory-based access services and I/O-based access services.
+
+ @param[in] PeiServices An indirect pointer to the PEI Services Table
+ published by the PEI Foundation.
+ @param[in] This The pointer to local data for the interface.
+ @param[in] Width The width of the access. Enumerated in bytes.
+ @param[in] Address The physical address of the access.
+ @param[in] Count The number of accesses to perform.
+ @param[in, out] Buffer A pointer to the buffer of data.
+
+ @retval EFI_SUCCESS The function completed successfully.
+ @retval EFI_NOT_YET_AVAILABLE The service has not been installed.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_PEI_CPU_IO_PPI_IO_MEM)(
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN CONST EFI_PEI_CPU_IO_PPI *This,
+ IN EFI_PEI_CPU_IO_PPI_WIDTH Width,
+ IN UINT64 Address,
+ IN UINTN Count,
+ IN OUT VOID *Buffer
+ );
+
+///
+/// EFI_PEI_CPU_IO_PPI_ACCESS
+///
+typedef struct {
+ ///
+ /// This service provides the various modalities of memory and I/O read.
+ ///
+ EFI_PEI_CPU_IO_PPI_IO_MEM Read;
+ ///
+ /// This service provides the various modalities of memory and I/O write.
+ ///
+ EFI_PEI_CPU_IO_PPI_IO_MEM Write;
+} EFI_PEI_CPU_IO_PPI_ACCESS;
+
+/**
+ 8-bit I/O read operations.
+
+ @param[in] PeiServices An indirect pointer to the PEI Services Table published
+ by the PEI Foundation.
+ @param[in] This The pointer to local data for the interface.
+ @param[in] Address The physical address of the access.
+
+ @return An 8-bit value returned from the I/O space.
+
+**/
+typedef
+UINT8
+(EFIAPI *EFI_PEI_CPU_IO_PPI_IO_READ8)(
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN CONST EFI_PEI_CPU_IO_PPI *This,
+ IN UINT64 Address
+ );
+
+/**
+ 16-bit I/O read operations.
+
+ @param[in] PeiServices An indirect pointer to the PEI Services Table published
+ by the PEI Foundation.
+ @param[in] This The pointer to local data for the interface.
+ @param[in] Address The physical address of the access.
+
+ @return A 16-bit value returned from the I/O space.
+
+**/
+typedef
+UINT16
+(EFIAPI *EFI_PEI_CPU_IO_PPI_IO_READ16)(
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN CONST EFI_PEI_CPU_IO_PPI *This,
+ IN UINT64 Address
+ );
+
+/**
+ 32-bit I/O read operations.
+
+ @param[in] PeiServices An indirect pointer to the PEI Services Table published
+ by the PEI Foundation.
+ @param[in] This The pointer to local data for the interface.
+ @param[in] Address The physical address of the access.
+
+ @return A 32-bit value returned from the I/O space.
+
+**/
+typedef
+UINT32
+(EFIAPI *EFI_PEI_CPU_IO_PPI_IO_READ32)(
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN CONST EFI_PEI_CPU_IO_PPI *This,
+ IN UINT64 Address
+ );
+
+/**
+ 64-bit I/O read operations.
+
+ @param[in] PeiServices An indirect pointer to the PEI Services Table published
+ by the PEI Foundation.
+ @param[in] This The pointer to local data for the interface.
+ @param[in] Address The physical address of the access.
+
+ @return A 64-bit value returned from the I/O space.
+
+**/
+typedef
+UINT64
+(EFIAPI *EFI_PEI_CPU_IO_PPI_IO_READ64)(
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN CONST EFI_PEI_CPU_IO_PPI *This,
+ IN UINT64 Address
+ );
+
+/**
+ 8-bit I/O write operations.
+
+ @param[in] PeiServices An indirect pointer to the PEI Services Table published
+ by the PEI Foundation.
+ @param[in] This The pointer to local data for the interface.
+ @param[in] Address The physical address of the access.
+ @param[in] Data The data to write.
+
+**/
+typedef
+VOID
+(EFIAPI *EFI_PEI_CPU_IO_PPI_IO_WRITE8)(
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN CONST EFI_PEI_CPU_IO_PPI *This,
+ IN UINT64 Address,
+ IN UINT8 Data
+ );
+
+/**
+ 16-bit I/O write operations.
+
+ @param[in] PeiServices An indirect pointer to the PEI Services Table published
+ by the PEI Foundation.
+ @param[in] This The pointer to local data for the interface.
+ @param[in] Address The physical address of the access.
+ @param[in] Data The data to write.
+
+**/
+typedef
+VOID
+(EFIAPI *EFI_PEI_CPU_IO_PPI_IO_WRITE16)(
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN CONST EFI_PEI_CPU_IO_PPI *This,
+ IN UINT64 Address,
+ IN UINT16 Data
+ );
+
+/**
+ 32-bit I/O write operations.
+
+ @param[in] PeiServices An indirect pointer to the PEI Services Table published
+ by the PEI Foundation.
+ @param[in] This The pointer to local data for the interface.
+ @param[in] Address The physical address of the access.
+ @param[in] Data The data to write.
+
+**/
+typedef
+VOID
+(EFIAPI *EFI_PEI_CPU_IO_PPI_IO_WRITE32)(
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN CONST EFI_PEI_CPU_IO_PPI *This,
+ IN UINT64 Address,
+ IN UINT32 Data
+ );
+
+/**
+ 64-bit I/O write operations.
+
+ @param[in] PeiServices An indirect pointer to the PEI Services Table published
+ by the PEI Foundation.
+ @param[in] This The pointer to local data for the interface.
+ @param[in] Address The physical address of the access.
+ @param[in] Data The data to write.
+
+**/
+typedef
+VOID
+(EFIAPI *EFI_PEI_CPU_IO_PPI_IO_WRITE64)(
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN CONST EFI_PEI_CPU_IO_PPI *This,
+ IN UINT64 Address,
+ IN UINT64 Data
+ );
+
+/**
+ 8-bit memory read operations.
+
+ @param[in] PeiServices An indirect pointer to the PEI Services Table published
+ by the PEI Foundation.
+ @param[in] This The pointer to local data for the interface.
+ @param[in] Address The physical address of the access.
+
+ @return An 8-bit value returned from the memory space.
+
+**/
+typedef
+UINT8
+(EFIAPI *EFI_PEI_CPU_IO_PPI_MEM_READ8)(
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN CONST EFI_PEI_CPU_IO_PPI *This,
+ IN UINT64 Address
+ );
+
+/**
+ 16-bit memory read operations.
+
+ @param[in] PeiServices An indirect pointer to the PEI Services Table published
+ by the PEI Foundation.
+ @param[in] This The pointer to local data for the interface.
+ @param[in] Address The physical address of the access.
+
+ @return A 16-bit value returned from the memory space.
+
+**/
+typedef
+UINT16
+(EFIAPI *EFI_PEI_CPU_IO_PPI_MEM_READ16)(
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN CONST EFI_PEI_CPU_IO_PPI *This,
+ IN UINT64 Address
+ );
+
+/**
+ 32-bit memory read operations.
+
+ @param[in] PeiServices An indirect pointer to the PEI Services Table published
+ by the PEI Foundation.
+ @param[in] This The pointer to local data for the interface.
+ @param[in] Address The physical address of the access.
+
+ @return A 32-bit value returned from the memory space.
+
+**/
+typedef
+UINT32
+(EFIAPI *EFI_PEI_CPU_IO_PPI_MEM_READ32)(
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN CONST EFI_PEI_CPU_IO_PPI *This,
+ IN UINT64 Address
+ );
+
+/**
+ 64-bit memory read operations.
+
+ @param[in] PeiServices An indirect pointer to the PEI Services Table published
+ by the PEI Foundation.
+ @param[in] This The pointer to local data for the interface.
+ @param[in] Address The physical address of the access.
+
+ @return A 64-bit value returned from the memory space.
+
+**/
+typedef
+UINT64
+(EFIAPI *EFI_PEI_CPU_IO_PPI_MEM_READ64)(
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN CONST EFI_PEI_CPU_IO_PPI *This,
+ IN UINT64 Address
+ );
+
+/**
+ 8-bit memory write operations.
+
+ @param[in] PeiServices An indirect pointer to the PEI Services Table published
+ by the PEI Foundation.
+ @param[in] This The pointer to local data for the interface.
+ @param[in] Address The physical address of the access.
+ @param[in] Data The data to write.
+
+**/
+typedef
+VOID
+(EFIAPI *EFI_PEI_CPU_IO_PPI_MEM_WRITE8)(
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN CONST EFI_PEI_CPU_IO_PPI *This,
+ IN UINT64 Address,
+ IN UINT8 Data
+ );
+
+/**
+ 16-bit memory write operations.
+
+ @param[in] PeiServices An indirect pointer to the PEI Services Table published
+ by the PEI Foundation.
+ @param[in] This The pointer to local data for the interface.
+ @param[in] Address The physical address of the access.
+ @param[in] Data The data to write.
+
+**/
+typedef
+VOID
+(EFIAPI *EFI_PEI_CPU_IO_PPI_MEM_WRITE16)(
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN CONST EFI_PEI_CPU_IO_PPI *This,
+ IN UINT64 Address,
+ IN UINT16 Data
+ );
+
+/**
+ 32-bit memory write operations.
+
+ @param[in] PeiServices An indirect pointer to the PEI Services Table published
+ by the PEI Foundation.
+ @param[in] This The pointer to local data for the interface.
+ @param[in] Address The physical address of the access.
+ @param[in] Data The data to write.
+
+**/
+typedef
+VOID
+(EFIAPI *EFI_PEI_CPU_IO_PPI_MEM_WRITE32)(
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN CONST EFI_PEI_CPU_IO_PPI *This,
+ IN UINT64 Address,
+ IN UINT32 Data
+ );
+
+/**
+ 64-bit memory write operations.
+
+ @param[in] PeiServices An indirect pointer to the PEI Services Table published
+ by the PEI Foundation.
+ @param[in] This The pointer to local data for the interface.
+ @param[in] Address The physical address of the access.
+ @param[in] Data The data to write.
+
+**/
+typedef
+VOID
+(EFIAPI *EFI_PEI_CPU_IO_PPI_MEM_WRITE64)(
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN CONST EFI_PEI_CPU_IO_PPI *This,
+ IN UINT64 Address,
+ IN UINT64 Data
+ );
+
+///
+/// EFI_PEI_CPU_IO_PPI provides a set of memory and I/O-based services.
+/// The perspective of the services is that of the processor, not that of the
+/// bus or system.
+///
+struct _EFI_PEI_CPU_IO_PPI {
+ ///
+ /// Collection of memory-access services.
+ ///
+ EFI_PEI_CPU_IO_PPI_ACCESS Mem;
+ ///
+ /// Collection of I/O-access services.
+ ///
+ EFI_PEI_CPU_IO_PPI_ACCESS Io;
+
+ EFI_PEI_CPU_IO_PPI_IO_READ8 IoRead8;
+ EFI_PEI_CPU_IO_PPI_IO_READ16 IoRead16;
+ EFI_PEI_CPU_IO_PPI_IO_READ32 IoRead32;
+ EFI_PEI_CPU_IO_PPI_IO_READ64 IoRead64;
+
+ EFI_PEI_CPU_IO_PPI_IO_WRITE8 IoWrite8;
+ EFI_PEI_CPU_IO_PPI_IO_WRITE16 IoWrite16;
+ EFI_PEI_CPU_IO_PPI_IO_WRITE32 IoWrite32;
+ EFI_PEI_CPU_IO_PPI_IO_WRITE64 IoWrite64;
+
+ EFI_PEI_CPU_IO_PPI_MEM_READ8 MemRead8;
+ EFI_PEI_CPU_IO_PPI_MEM_READ16 MemRead16;
+ EFI_PEI_CPU_IO_PPI_MEM_READ32 MemRead32;
+ EFI_PEI_CPU_IO_PPI_MEM_READ64 MemRead64;
+
+ EFI_PEI_CPU_IO_PPI_MEM_WRITE8 MemWrite8;
+ EFI_PEI_CPU_IO_PPI_MEM_WRITE16 MemWrite16;
+ EFI_PEI_CPU_IO_PPI_MEM_WRITE32 MemWrite32;
+ EFI_PEI_CPU_IO_PPI_MEM_WRITE64 MemWrite64;
+};
+
+extern EFI_GUID gEfiPeiCpuIoPpiInstalledGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Ppi/Decompress.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Ppi/Decompress.h
new file mode 100644
index 0000000000..a5c40cdc5c
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Ppi/Decompress.h
@@ -0,0 +1,66 @@
+/** @file
+ Provides decompression services to the PEI Foundation.
+
+ Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Revision Reference:
+ This PPI is introduced in PI Version 1.0.
+
+**/
+
+#ifndef __DECOMPRESS_PPI_H__
+#define __DECOMPRESS_PPI_H__
+
+#define EFI_PEI_DECOMPRESS_PPI_GUID \
+ { 0x1a36e4e7, 0xfab6, 0x476a, { 0x8e, 0x75, 0x69, 0x5a, 0x5, 0x76, 0xfd, 0xd7 } }
+
+typedef struct _EFI_PEI_DECOMPRESS_PPI EFI_PEI_DECOMPRESS_PPI;
+
+/**
+ Decompress a single compression section in a firmware file.
+
+ Decompresses the data in a compressed section and returns it
+ as a series of standard PI Firmware File Sections. The
+ required memory is allocated from permanent memory.
+
+ @param This Points to this instance of the
+ EFI_PEI_DECOMPRESS_PEI PPI.
+ @param InputSection Points to the compressed section.
+ @param OutputBuffer Holds the returned pointer to the
+ decompressed sections.
+ @param OutputSize Holds the returned size of the decompress
+ section streams.
+
+ @retval EFI_SUCCESS The section was decompressed
+ successfully. OutputBuffer contains the
+ resulting data and OutputSize contains
+ the resulting size.
+ @retval EFI_OUT_OF_RESOURCES Unable to allocate sufficient
+ memory to hold the decompressed data.
+ @retval EFI_UNSUPPORTED The compression type specified
+ in the compression header is unsupported.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_PEI_DECOMPRESS_DECOMPRESS)(
+ IN CONST EFI_PEI_DECOMPRESS_PPI *This,
+ IN CONST EFI_COMPRESSION_SECTION *InputSection,
+ OUT VOID **OutputBuffer,
+ OUT UINTN *OutputSize
+ );
+
+///
+/// This PPI's single member function decompresses a compression
+/// encapsulated section. It is used by the PEI Foundation to
+/// process sectioned files. Prior to the installation of this PPI,
+/// compression sections will be ignored.
+///
+struct _EFI_PEI_DECOMPRESS_PPI {
+ EFI_PEI_DECOMPRESS_DECOMPRESS Decompress;
+};
+
+extern EFI_GUID gEfiPeiDecompressPpiGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Ppi/DelayedDispatch.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Ppi/DelayedDispatch.h
new file mode 100644
index 0000000000..1fcd1d746c
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Ppi/DelayedDispatch.h
@@ -0,0 +1,80 @@
+/** @file
+ EFI Delayed Dispatch PPI as defined in the PI 1.7 Specification
+
+ Provide timed event service in PEI
+
+ Copyright (c) 2020, American Megatrends International LLC. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef __DELAYED_DISPATCH_PPI_H__
+#define __DELAYED_DISPATCH_PPI_H__
+
+///
+/// Global ID for EFI_DELAYED_DISPATCH_PPI_GUID
+///
+#define EFI_DELAYED_DISPATCH_PPI_GUID \
+ { \
+ 0x869c711d, 0x649c, 0x44fe, { 0x8b, 0x9e, 0x2c, 0xbb, 0x29, 0x11, 0xc3, 0xe6} } \
+ }
+
+/**
+ Delayed Dispatch function. This routine is called sometime after the required
+ delay. Upon return, if NewDelay is 0, the function is unregistered. If NewDelay
+ is not zero, this routine will be called again after the new delay period.
+
+ @param[in,out] Context Pointer to Context. Can be updated by routine.
+ @param[out] NewDelay The new delay in us. Leave at 0 to unregister callback.
+
+**/
+
+typedef
+VOID
+(EFIAPI *EFI_DELAYED_DISPATCH_FUNCTION)(
+ IN OUT UINT64 *Context,
+ OUT UINT32 *NewDelay
+ );
+
+///
+/// The forward declaration for EFI_DELAYED_DISPATCH_PPI
+///
+
+typedef struct _EFI_DELAYED_DISPATCH_PPI EFI_DELAYED_DISPATCH_PPI;
+
+/**
+Register a callback to be called after a minimum delay has occurred.
+
+This service is the single member function of the EFI_DELAYED_DISPATCH_PPI
+
+ @param This Pointer to the EFI_DELAYED_DISPATCH_PPI instance
+ @param Function Function to call back
+ @param Context Context data
+ @param Delay Delay interval
+
+ @retval EFI_SUCCESS Function successfully loaded
+ @retval EFI_INVALID_PARAMETER One of the Arguments is not supported
+ @retval EFI_OUT_OF_RESOURCES No more entries
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_DELAYED_DISPATCH_REGISTER)(
+ IN EFI_DELAYED_DISPATCH_PPI *This,
+ IN EFI_DELAYED_DISPATCH_FUNCTION Function,
+ IN UINT64 Context,
+ OUT UINT32 Delay
+ );
+
+///
+/// This PPI is a pointer to the Delayed Dispatch Service.
+/// This service will be published by the Pei Foundation. The PEI Foundation
+/// will use this service to relaunch a known function that requests a delayed
+/// execution.
+///
+struct _EFI_DELAYED_DISPATCH_PPI {
+ EFI_DELAYED_DISPATCH_REGISTER Register;
+};
+
+extern EFI_GUID gEfiPeiDelayedDispatchPpiGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Ppi/DeviceRecoveryModule.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Ppi/DeviceRecoveryModule.h
new file mode 100644
index 0000000000..542d550b16
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Ppi/DeviceRecoveryModule.h
@@ -0,0 +1,138 @@
+/** @file
+ This file declares the Device Recovery Module PPI.
+
+ The interface of this PPI does the following:
+ - Reports the number of recovery DXE capsules that exist on the associated device(s)
+ - Finds the requested firmware binary capsule
+ - Loads that capsule into memory
+
+ A device can be either a group of devices, such as a block device, or an individual device.
+ The module determines the internal search order, with capsule number 1 as the highest load
+ priority and number N as the lowest priority.
+
+ Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Revision Reference:
+ This PPI is defined in UEFI Platform Initialization Specification 1.2 Volume 1:
+ Pre-EFI Initialization Core Interface
+
+**/
+
+#ifndef _PEI_DEVICE_RECOVERY_MODULE_PPI_H_
+#define _PEI_DEVICE_RECOVERY_MODULE_PPI_H_
+
+#define EFI_PEI_DEVICE_RECOVERY_MODULE_PPI_GUID \
+ { \
+ 0x0DE2CE25, 0x446A, 0x45a7, {0xBF, 0xC9, 0x37, 0xDA, 0x26, 0x34, 0x4B, 0x37 } \
+ }
+
+typedef struct _EFI_PEI_DEVICE_RECOVERY_MODULE_PPI EFI_PEI_DEVICE_RECOVERY_MODULE_PPI;
+
+/**
+ Returns the number of DXE capsules residing on the device.
+
+ This function searches for DXE capsules from the associated device and returns
+ the number and maximum size in bytes of the capsules discovered. Entry 1 is
+ assumed to be the highest load priority and entry N is assumed to be the lowest
+ priority.
+
+ @param[in] PeiServices General-purpose services that are available
+ to every PEIM
+ @param[in] This Indicates the EFI_PEI_DEVICE_RECOVERY_MODULE_PPI
+ instance.
+ @param[out] NumberRecoveryCapsules Pointer to a caller-allocated UINTN. On
+ output, *NumberRecoveryCapsules contains
+ the number of recovery capsule images
+ available for retrieval from this PEIM
+ instance.
+
+ @retval EFI_SUCCESS One or more capsules were discovered.
+ @retval EFI_DEVICE_ERROR A device error occurred.
+ @retval EFI_NOT_FOUND A recovery DXE capsule cannot be found.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_PEI_DEVICE_GET_NUMBER_RECOVERY_CAPSULE)(
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PEI_DEVICE_RECOVERY_MODULE_PPI *This,
+ OUT UINTN *NumberRecoveryCapsules
+ );
+
+/**
+ Returns the size and type of the requested recovery capsule.
+
+ This function gets the size and type of the capsule specified by CapsuleInstance.
+
+ @param[in] PeiServices General-purpose services that are available to every PEIM
+ @param[in] This Indicates the EFI_PEI_DEVICE_RECOVERY_MODULE_PPI
+ instance.
+ @param[in] CapsuleInstance Specifies for which capsule instance to retrieve
+ the information. This parameter must be between
+ one and the value returned by GetNumberRecoveryCapsules()
+ in NumberRecoveryCapsules.
+ @param[out] Size A pointer to a caller-allocated UINTN in which
+ the size of the requested recovery module is
+ returned.
+ @param[out] CapsuleType A pointer to a caller-allocated EFI_GUID in which
+ the type of the requested recovery capsule is
+ returned. The semantic meaning of the value
+ returned is defined by the implementation.
+
+ @retval EFI_SUCCESS One or more capsules were discovered.
+ @retval EFI_DEVICE_ERROR A device error occurred.
+ @retval EFI_NOT_FOUND A recovery DXE capsule cannot be found.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_PEI_DEVICE_GET_RECOVERY_CAPSULE_INFO)(
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PEI_DEVICE_RECOVERY_MODULE_PPI *This,
+ IN UINTN CapsuleInstance,
+ OUT UINTN *Size,
+ OUT EFI_GUID *CapsuleType
+ );
+
+/**
+ Loads a DXE capsule from some media into memory.
+
+ This function, by whatever mechanism, retrieves a DXE capsule from some device
+ and loads it into memory. Note that the published interface is device neutral.
+
+ @param[in] PeiServices General-purpose services that are available
+ to every PEIM
+ @param[in] This Indicates the EFI_PEI_DEVICE_RECOVERY_MODULE_PPI
+ instance.
+ @param[in] CapsuleInstance Specifies which capsule instance to retrieve.
+ @param[out] Buffer Specifies a caller-allocated buffer in which
+ the requested recovery capsule will be returned.
+
+ @retval EFI_SUCCESS The capsule was loaded correctly.
+ @retval EFI_DEVICE_ERROR A device error occurred.
+ @retval EFI_NOT_FOUND A requested recovery DXE capsule cannot be found.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_PEI_DEVICE_LOAD_RECOVERY_CAPSULE)(
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PEI_DEVICE_RECOVERY_MODULE_PPI *This,
+ IN UINTN CapsuleInstance,
+ OUT VOID *Buffer
+ );
+
+///
+/// Presents a standard interface to EFI_PEI_DEVICE_RECOVERY_MODULE_PPI,
+/// regardless of the underlying device(s).
+///
+struct _EFI_PEI_DEVICE_RECOVERY_MODULE_PPI {
+ EFI_PEI_DEVICE_GET_NUMBER_RECOVERY_CAPSULE GetNumberRecoveryCapsules; ///< Returns the number of DXE capsules residing on the device.
+ EFI_PEI_DEVICE_GET_RECOVERY_CAPSULE_INFO GetRecoveryCapsuleInfo; ///< Returns the size and type of the requested recovery capsule.
+ EFI_PEI_DEVICE_LOAD_RECOVERY_CAPSULE LoadRecoveryCapsule; ///< Loads a DXE capsule from some media into memory.
+};
+
+extern EFI_GUID gEfiPeiDeviceRecoveryModulePpiGuid;
+
+#endif /* _PEI_DEVICE_RECOVERY_MODULE_PPI_H_ */
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Ppi/DxeIpl.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Ppi/DxeIpl.h
new file mode 100644
index 0000000000..26a2ebec91
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Ppi/DxeIpl.h
@@ -0,0 +1,66 @@
+/** @file
+ This file declares DXE Initial Program Load PPI.
+ When the PEI core is done it calls the DXE IPL PPI to load the DXE Foundation.
+
+ Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Revision Reference:
+ This PPI is introduced in PI Version 1.0.
+
+**/
+
+#ifndef __DXE_IPL_H__
+#define __DXE_IPL_H__
+
+#define EFI_DXE_IPL_PPI_GUID \
+ { \
+ 0xae8ce5d, 0xe448, 0x4437, {0xa8, 0xd7, 0xeb, 0xf5, 0xf1, 0x94, 0xf7, 0x31 } \
+ }
+
+typedef struct _EFI_DXE_IPL_PPI EFI_DXE_IPL_PPI;
+
+/**
+ The architectural PPI that the PEI Foundation invokes when
+ there are no additional PEIMs to invoke.
+
+ This function is invoked by the PEI Foundation.
+ The PEI Foundation will invoke this service when there are
+ no additional PEIMs to invoke in the system.
+ If this PPI does not exist, it is an error condition and
+ an ill-formed firmware set. The DXE IPL PPI should never
+ return after having been invoked by the PEI Foundation.
+ The DXE IPL PPI can do many things internally, including the following:
+ - Invoke the DXE entry point from a firmware volume
+ - Invoke the recovery processing modules
+ - Invoke the S3 resume modules
+
+ @param This Pointer to the DXE IPL PPI instance
+ @param PeiServices Pointer to the PEI Services Table.
+ @param HobList Pointer to the list of Hand-Off Block (HOB) entries.
+
+ @retval EFI_SUCCESS Upon this return code, the PEI Foundation should enter
+ some exception handling.Under normal circumstances,
+ the DXE IPL PPI should not return.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_DXE_IPL_ENTRY)(
+ IN CONST EFI_DXE_IPL_PPI *This,
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PEI_HOB_POINTERS HobList
+ );
+
+///
+/// Final service to be invoked by the PEI Foundation.
+/// The DXE IPL PPI is responsible for locating and loading the DXE Foundation.
+/// The DXE IPL PPI may use PEI services to locate and load the DXE Foundation.
+///
+struct _EFI_DXE_IPL_PPI {
+ EFI_DXE_IPL_ENTRY Entry;
+};
+
+extern EFI_GUID gEfiDxeIplPpiGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Ppi/EndOfPeiPhase.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Ppi/EndOfPeiPhase.h
new file mode 100644
index 0000000000..d1165c2b30
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Ppi/EndOfPeiPhase.h
@@ -0,0 +1,25 @@
+/** @file
+ This PPI will be installed at the end of PEI for all boot paths, including
+ normal, recovery, and S3. It allows for PEIMs to possibly quiesce hardware,
+ build handoff information for the next phase of execution,
+ or provide some terminal processing behavior.
+
+ Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Revision Reference:
+ This PPI is introduced in PI Version 1.0.
+
+**/
+
+#ifndef __END_OF_PEI_PHASE_PPI_H__
+#define __END_OF_PEI_PHASE_PPI_H__
+
+#define EFI_PEI_END_OF_PEI_PHASE_PPI_GUID \
+ { \
+ 0x605EA650, 0xC65C, 0x42e1, {0xBA, 0x80, 0x91, 0xA5, 0x2A, 0xB6, 0x18, 0xC6 } \
+ }
+
+extern EFI_GUID gEfiEndOfPeiSignalPpiGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Ppi/FirmwareVolume.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Ppi/FirmwareVolume.h
new file mode 100644
index 0000000000..abade11566
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Ppi/FirmwareVolume.h
@@ -0,0 +1,285 @@
+/** @file
+ This file provides functions for accessing a memory-mapped firmware volume of a specific format.
+
+ Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Revision Reference:
+ This PPI is from PI Version 1.0 errata.
+
+**/
+
+#ifndef __FIRMWARE_VOLUME_PPI_H__
+#define __FIRMWARE_VOLUME_PPI_H__
+
+///
+/// The GUID for this PPI is the same as the firmware volume format GUID.
+/// The FV format can be EFI_FIRMWARE_FILE_SYSTEM2_GUID or the GUID for a user-defined
+/// format. The EFI_FIRMWARE_FILE_SYSTEM2_GUID is the PI Firmware Volume format.
+///
+typedef struct _EFI_PEI_FIRMWARE_VOLUME_PPI EFI_PEI_FIRMWARE_VOLUME_PPI;
+
+/**
+ Process a firmware volume and create a volume handle.
+
+ Create a volume handle from the information in the buffer. For
+ memory-mapped firmware volumes, Buffer and BufferSize refer to
+ the start of the firmware volume and the firmware volume size.
+ For non memory-mapped firmware volumes, this points to a
+ buffer which contains the necessary information for creating
+ the firmware volume handle. Normally, these values are derived
+ from the EFI_FIRMWARE_VOLUME_INFO_PPI.
+
+
+ @param This Points to this instance of the
+ EFI_PEI_FIRMWARE_VOLUME_PPI.
+ @param Buffer Points to the start of the buffer.
+ @param BufferSize Size of the buffer.
+ @param FvHandle Points to the returned firmware volume
+ handle. The firmware volume handle must
+ be unique within the system.
+
+ @retval EFI_SUCCESS Firmware volume handle created.
+ @retval EFI_VOLUME_CORRUPTED Volume was corrupt.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_PEI_FV_PROCESS_FV)(
+ IN CONST EFI_PEI_FIRMWARE_VOLUME_PPI *This,
+ IN VOID *Buffer,
+ IN UINTN BufferSize,
+ OUT EFI_PEI_FV_HANDLE *FvHandle
+ );
+
+/**
+ Finds the next file of the specified type.
+
+ This service enables PEI modules to discover additional firmware files.
+ The FileHandle must be unique within the system.
+
+ @param This Points to this instance of the
+ EFI_PEI_FIRMWARE_VOLUME_PPI.
+ @param SearchType A filter to find only files of this type. Type
+ EFI_FV_FILETYPE_ALL causes no filtering to be
+ done.
+ @param FvHandle Handle of firmware volume in which to
+ search.
+ @param FileHandle Points to the current handle from which to
+ begin searching or NULL to start at the
+ beginning of the firmware volume. Updated
+ upon return to reflect the file found.
+
+ @retval EFI_SUCCESS The file was found.
+ @retval EFI_NOT_FOUND The file was not found. FileHandle contains NULL.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_PEI_FV_FIND_FILE_TYPE)(
+ IN CONST EFI_PEI_FIRMWARE_VOLUME_PPI *This,
+ IN EFI_FV_FILETYPE SearchType,
+ IN EFI_PEI_FV_HANDLE FvHandle,
+ IN OUT EFI_PEI_FILE_HANDLE *FileHandle
+ );
+
+/**
+ Find a file within a volume by its name.
+
+ This service searches for files with a specific name, within
+ either the specified firmware volume or all firmware volumes.
+
+ @param This Points to this instance of the
+ EFI_PEI_FIRMWARE_VOLUME_PPI.
+ @param FileName A pointer to the name of the file to find
+ within the firmware volume.
+ @param FvHandle Upon entry, the pointer to the firmware
+ volume to search or NULL if all firmware
+ volumes should be searched. Upon exit, the
+ actual firmware volume in which the file was
+ found.
+ @param FileHandle Upon exit, points to the found file's
+ handle or NULL if it could not be found.
+
+ @retval EFI_SUCCESS File was found.
+ @retval EFI_NOT_FOUND File was not found.
+ @retval EFI_INVALID_PARAMETER FvHandle or FileHandle or
+ FileName was NULL.
+
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_PEI_FV_FIND_FILE_NAME)(
+ IN CONST EFI_PEI_FIRMWARE_VOLUME_PPI *This,
+ IN CONST EFI_GUID *FileName,
+ IN EFI_PEI_FV_HANDLE *FvHandle,
+ OUT EFI_PEI_FILE_HANDLE *FileHandle
+ );
+
+/**
+ Returns information about a specific file.
+
+ This function returns information about a specific
+ file, including its file name, type, attributes, starting
+ address and size.
+
+ @param This Points to this instance of the
+ EFI_PEI_FIRMWARE_VOLUME_PPI.
+ @param FileHandle Handle of the file.
+ @param FileInfo Upon exit, points to the file's
+ information.
+
+ @retval EFI_SUCCESS File information returned.
+ @retval EFI_INVALID_PARAMETER If FileHandle does not
+ represent a valid file.
+ @retval EFI_INVALID_PARAMETER If FileInfo is NULL.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_PEI_FV_GET_FILE_INFO)(
+ IN CONST EFI_PEI_FIRMWARE_VOLUME_PPI *This,
+ IN EFI_PEI_FILE_HANDLE FileHandle,
+ OUT EFI_FV_FILE_INFO *FileInfo
+ );
+
+/**
+ Returns information about a specific file.
+
+ This function returns information about a specific
+ file, including its file name, type, attributes, starting
+ address, size and authentication status.
+
+ @param This Points to this instance of the
+ EFI_PEI_FIRMWARE_VOLUME_PPI.
+ @param FileHandle Handle of the file.
+ @param FileInfo Upon exit, points to the file's
+ information.
+
+ @retval EFI_SUCCESS File information returned.
+ @retval EFI_INVALID_PARAMETER If FileHandle does not
+ represent a valid file.
+ @retval EFI_INVALID_PARAMETER If FileInfo is NULL.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_PEI_FV_GET_FILE_INFO2)(
+ IN CONST EFI_PEI_FIRMWARE_VOLUME_PPI *This,
+ IN EFI_PEI_FILE_HANDLE FileHandle,
+ OUT EFI_FV_FILE_INFO2 *FileInfo
+ );
+
+/**
+ This function returns information about the firmware volume.
+
+ @param This Points to this instance of the
+ EFI_PEI_FIRMWARE_VOLUME_PPI.
+ @param FvHandle Handle to the firmware handle.
+ @param VolumeInfo Points to the returned firmware volume
+ information.
+
+ @retval EFI_SUCCESS Information returned successfully.
+ @retval EFI_INVALID_PARAMETER FvHandle does not indicate a valid
+ firmware volume or VolumeInfo is NULL.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_PEI_FV_GET_INFO)(
+ IN CONST EFI_PEI_FIRMWARE_VOLUME_PPI *This,
+ IN EFI_PEI_FV_HANDLE FvHandle,
+ OUT EFI_FV_INFO *VolumeInfo
+ );
+
+/**
+ Find the next matching section in the firmware file.
+
+ This service enables PEI modules to discover sections
+ of a given type within a valid file.
+
+ @param This Points to this instance of the
+ EFI_PEI_FIRMWARE_VOLUME_PPI.
+ @param SearchType A filter to find only sections of this
+ type.
+ @param FileHandle Handle of firmware file in which to
+ search.
+ @param SectionData Updated upon return to point to the
+ section found.
+
+ @retval EFI_SUCCESS Section was found.
+ @retval EFI_NOT_FOUND Section of the specified type was not
+ found. SectionData contains NULL.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_PEI_FV_FIND_SECTION)(
+ IN CONST EFI_PEI_FIRMWARE_VOLUME_PPI *This,
+ IN EFI_SECTION_TYPE SearchType,
+ IN EFI_PEI_FILE_HANDLE FileHandle,
+ OUT VOID **SectionData
+ );
+
+/**
+ Find the next matching section in the firmware file.
+
+ This service enables PEI modules to discover sections
+ of a given instance and type within a valid file.
+
+ @param This Points to this instance of the
+ EFI_PEI_FIRMWARE_VOLUME_PPI.
+ @param SearchType A filter to find only sections of this
+ type.
+ @param SearchInstance A filter to find the specific instance
+ of sections.
+ @param FileHandle Handle of firmware file in which to
+ search.
+ @param SectionData Updated upon return to point to the
+ section found.
+ @param AuthenticationStatus Updated upon return to point to the
+ authentication status for this section.
+
+ @retval EFI_SUCCESS Section was found.
+ @retval EFI_NOT_FOUND Section of the specified type was not
+ found. SectionData contains NULL.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_PEI_FV_FIND_SECTION2)(
+ IN CONST EFI_PEI_FIRMWARE_VOLUME_PPI *This,
+ IN EFI_SECTION_TYPE SearchType,
+ IN UINTN SearchInstance,
+ IN EFI_PEI_FILE_HANDLE FileHandle,
+ OUT VOID **SectionData,
+ OUT UINT32 *AuthenticationStatus
+ );
+
+#define EFI_PEI_FIRMWARE_VOLUME_PPI_SIGNATURE SIGNATURE_32 ('P', 'F', 'V', 'P')
+#define EFI_PEI_FIRMWARE_VOLUME_PPI_REVISION 0x00010030
+
+///
+/// This PPI provides functions for accessing a memory-mapped firmware volume of a specific format.
+///
+struct _EFI_PEI_FIRMWARE_VOLUME_PPI {
+ EFI_PEI_FV_PROCESS_FV ProcessVolume;
+ EFI_PEI_FV_FIND_FILE_TYPE FindFileByType;
+ EFI_PEI_FV_FIND_FILE_NAME FindFileByName;
+ EFI_PEI_FV_GET_FILE_INFO GetFileInfo;
+ EFI_PEI_FV_GET_INFO GetVolumeInfo;
+ EFI_PEI_FV_FIND_SECTION FindSectionByType;
+ EFI_PEI_FV_GET_FILE_INFO2 GetFileInfo2;
+ EFI_PEI_FV_FIND_SECTION2 FindSectionByType2;
+ ///
+ /// Signature is used to keep backward-compatibility, set to {'P','F','V','P'}.
+ ///
+ UINT32 Signature;
+ ///
+ /// Revision for further extension.
+ ///
+ UINT32 Revision;
+};
+
+extern EFI_GUID gEfiPeiFirmwareVolumePpiGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Ppi/FirmwareVolumeInfo.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Ppi/FirmwareVolumeInfo.h
new file mode 100644
index 0000000000..cfcd77c313
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Ppi/FirmwareVolumeInfo.h
@@ -0,0 +1,59 @@
+/** @file
+ This file provides location and format of a firmware volume.
+
+ Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Revision Reference:
+ This PPI is introduced in PI Version 1.0.
+
+**/
+
+#ifndef __EFI_PEI_FIRMWARE_VOLUME_INFO_H__
+#define __EFI_PEI_FIRMWARE_VOLUME_INFO_H__
+
+#define EFI_PEI_FIRMWARE_VOLUME_INFO_PPI_GUID \
+{ 0x49edb1c1, 0xbf21, 0x4761, { 0xbb, 0x12, 0xeb, 0x0, 0x31, 0xaa, 0xbb, 0x39 } }
+
+typedef struct _EFI_PEI_FIRMWARE_VOLUME_INFO_PPI EFI_PEI_FIRMWARE_VOLUME_INFO_PPI;
+
+///
+/// This PPI describes the location and format of a firmware volume.
+/// The FvFormat can be EFI_FIRMWARE_FILE_SYSTEM2_GUID or the GUID for
+/// a user-defined format. The EFI_FIRMWARE_FILE_SYSTEM2_GUID is
+/// the PI Firmware Volume format.
+///
+struct _EFI_PEI_FIRMWARE_VOLUME_INFO_PPI {
+ ///
+ /// Unique identifier of the format of the memory-mapped firmware volume.
+ ///
+ EFI_GUID FvFormat;
+ ///
+ /// Points to a buffer which allows the EFI_PEI_FIRMWARE_VOLUME_PPI to process
+ /// the volume. The format of this buffer is specific to the FvFormat.
+ /// For memory-mapped firmware volumes, this typically points to the first byte
+ /// of the firmware volume.
+ ///
+ VOID *FvInfo;
+ ///
+ /// Size of the data provided by FvInfo. For memory-mapped firmware volumes,
+ /// this is typically the size of the firmware volume.
+ ///
+ UINT32 FvInfoSize;
+ ///
+ /// If the firmware volume originally came from a firmware file, then these
+ /// point to the parent firmware volume name and firmware volume file.
+ /// If it did not originally come from a firmware file, these should be NULL.
+ ///
+ EFI_GUID *ParentFvName;
+ ///
+ /// If the firmware volume originally came from a firmware file, then these
+ /// point to the parent firmware volume name and firmware volume file.
+ /// If it did not originally come from a firmware file, these should be NULL.
+ ///
+ EFI_GUID *ParentFileName;
+};
+
+extern EFI_GUID gEfiPeiFirmwareVolumeInfoPpiGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Ppi/FirmwareVolumeInfo2.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Ppi/FirmwareVolumeInfo2.h
new file mode 100644
index 0000000000..8c44b2ace9
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Ppi/FirmwareVolumeInfo2.h
@@ -0,0 +1,63 @@
+/** @file
+ This file provides location, format and authentication status of a firmware volume.
+
+ Copyright (c) 2013 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Revision Reference:
+ This PPI is introduced in PI Version 1.3 errata.
+
+**/
+
+#ifndef __EFI_PEI_FIRMWARE_VOLUME_INFO2_H__
+#define __EFI_PEI_FIRMWARE_VOLUME_INFO2_H__
+
+#define EFI_PEI_FIRMWARE_VOLUME_INFO2_PPI_GUID \
+{ 0xea7ca24b, 0xded5, 0x4dad, { 0xa3, 0x89, 0xbf, 0x82, 0x7e, 0x8f, 0x9b, 0x38 } }
+
+typedef struct _EFI_PEI_FIRMWARE_VOLUME_INFO2_PPI EFI_PEI_FIRMWARE_VOLUME_INFO2_PPI;
+
+///
+/// This PPI describes the location and format of a firmware volume.
+/// The FvFormat can be EFI_FIRMWARE_FILE_SYSTEM2_GUID or the GUID for
+/// a user-defined format. The EFI_FIRMWARE_FILE_SYSTEM2_GUID is
+/// the PI Firmware Volume format.
+///
+struct _EFI_PEI_FIRMWARE_VOLUME_INFO2_PPI {
+ ///
+ /// Unique identifier of the format of the memory-mapped firmware volume.
+ ///
+ EFI_GUID FvFormat;
+ ///
+ /// Points to a buffer which allows the EFI_PEI_FIRMWARE_VOLUME_PPI to process
+ /// the volume. The format of this buffer is specific to the FvFormat.
+ /// For memory-mapped firmware volumes, this typically points to the first byte
+ /// of the firmware volume.
+ ///
+ VOID *FvInfo;
+ ///
+ /// Size of the data provided by FvInfo. For memory-mapped firmware volumes,
+ /// this is typically the size of the firmware volume.
+ ///
+ UINT32 FvInfoSize;
+ ///
+ /// If the firmware volume originally came from a firmware file, then these
+ /// point to the parent firmware volume name and firmware volume file.
+ /// If it did not originally come from a firmware file, these should be NULL.
+ ///
+ EFI_GUID *ParentFvName;
+ ///
+ /// If the firmware volume originally came from a firmware file, then these
+ /// point to the parent firmware volume name and firmware volume file.
+ /// If it did not originally come from a firmware file, these should be NULL.
+ ///
+ EFI_GUID *ParentFileName;
+ ///
+ /// Authentication Status.
+ ///
+ UINT32 AuthenticationStatus;
+};
+
+extern EFI_GUID gEfiPeiFirmwareVolumeInfo2PpiGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Ppi/Graphics.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Ppi/Graphics.h
new file mode 100644
index 0000000000..05a8fb5dea
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Ppi/Graphics.h
@@ -0,0 +1,79 @@
+/** @file
+ This file declares Graphics PPI.
+ This PPI is the main interface exposed by the Graphics PEIM to be used by the
+ other firmware modules.
+
+ Copyright (c) 2015, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Revision Reference:
+ This PPI is introduced in PI Version 1.4.
+
+**/
+
+#ifndef __PEI_GRAPHICS_PPI_H__
+#define __PEI_GRAPHICS_PPI_H__
+
+#include
+
+#define EFI_PEI_GRAPHICS_PPI_GUID \
+ { \
+ 0x6ecd1463, 0x4a4a, 0x461b, { 0xaf, 0x5f, 0x5a, 0x33, 0xe3, 0xb2, 0x16, 0x2b } \
+ }
+
+typedef struct _EFI_PEI_GRAPHICS_PPI EFI_PEI_GRAPHICS_PPI;
+
+/**
+ The GraphicsPpiInit initializes the graphics subsystem in phases.
+
+ @param[in] GraphicsPolicyPtr GraphicsPolicyPtr points to a configuration data
+ block of policy settings required by Graphics PEIM.
+
+ @retval EFI_SUCCESS The invocation was successful.
+ @retval EFI_INVALID_PARAMETER The phase parameter is not valid.
+ @retval EFI_NOT_ABORTED The stages was not called in the proper order.
+ @retval EFI_NOT_FOUND The PeiGraphicsPlatformPolicyPpi is not located.
+ @retval EFI_DEVICE_ERROR The initialization failed due to device error.
+ @retval EFI_NOT_READY The previous init stage is still in progress and not
+ ready for the current initialization phase yet. The
+ platform code should call this again sometime later.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_PEI_GRAPHICS_INIT)(
+ IN VOID *GraphicsPolicyPtr
+ );
+
+/**
+ The GraphicsPpiGetMode returns the mode information supported by the Graphics PEI
+ Module.
+
+ @param[in, out] Mode Pointer to EFI_GRAPHICS_OUTPUT_PROTOCOL_MODE data.
+
+ @retval EFI_SUCCESS Valid mode information was returned.
+ @retval EFI_INVALID_PARAMETER The Mode parameter is not valid.
+ @retval EFI_DEVICE_ERROR A hardware error occurred trying to retrieve the video
+ mode.
+ @retval EFI_NOT_READY The Graphics Initialization is not competed and Mode
+ information is not yet available.The platform code
+ should call this again after the Graphics
+ initialization is done.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_PEI_GRAPHICS_GET_MODE)(
+ IN OUT EFI_GRAPHICS_OUTPUT_PROTOCOL_MODE *Mode
+ );
+
+///
+/// This PPI is the main interface exposed by the Graphics PEIM to be used by the other
+/// firmware modules.
+///
+struct _EFI_PEI_GRAPHICS_PPI {
+ EFI_PEI_GRAPHICS_INIT GraphicsPpiInit;
+ EFI_PEI_GRAPHICS_GET_MODE GraphicsPpiGetMode;
+};
+
+extern EFI_GUID gEfiPeiGraphicsPpiGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Ppi/GuidedSectionExtraction.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Ppi/GuidedSectionExtraction.h
new file mode 100644
index 0000000000..83ed6a1805
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Ppi/GuidedSectionExtraction.h
@@ -0,0 +1,93 @@
+/** @file
+ If a GUID-defined section is encountered when doing section extraction,
+ the PEI Foundation or the EFI_PEI_FILE_LOADER_PPI instance
+ calls the appropriate instance of the GUIDed Section Extraction PPI
+ to extract the section stream contained therein.
+
+ Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Revision Reference:
+ This PPI is introduced in PI Version 1.0.
+
+**/
+
+#ifndef __EFI_GUIDED_SECTION_EXTRACTION_PPI_H__
+#define __EFI_GUIDED_SECTION_EXTRACTION_PPI_H__
+
+//
+// Typically, protocol interface structures are identified
+// by associating them with a GUID. Each instance of
+// a protocol with a given GUID must have
+// the same interface structure. While all instances of
+// the GUIDed Section Extraction PPI must have
+// the same interface structure, they do not all have
+// te same GUID. The GUID that is associated with
+// an instance of the GUIDed Section Extraction Protocol
+// is used to correlate it with the GUIDed section type
+// that it is intended to process.
+//
+
+typedef struct _EFI_PEI_GUIDED_SECTION_EXTRACTION_PPI EFI_PEI_GUIDED_SECTION_EXTRACTION_PPI;
+
+/**
+ Processes the input section and returns the data contained therein
+ along with the authentication status.
+
+ The ExtractSection() function processes the input section and
+ returns a pointer to the section contents. If the section being
+ extracted does not require processing (if the section
+ GuidedSectionHeader.Attributes has the
+ EFI_GUIDED_SECTION_PROCESSING_REQUIRED field cleared), then
+ OutputBuffer is just updated to point to the start of the
+ section's contents. Otherwise, *Buffer must be allocated
+ from PEI permanent memory.
+
+ @param This Indicates the EFI_PEI_GUIDED_SECTION_EXTRACTION_PPI
+ instance.
+ @param InputSection Buffer containing the input GUIDed section to be
+ processed.
+ @param OutputBuffer *OutputBuffer is allocated from PEI permanent memory
+ and contains the new section stream.
+ @param OutputSize A pointer to a caller-allocated UINTN in which
+ the size of *OutputBuffer allocation is stored.
+ If the function returns anything other than
+ EFI_SUCCESS, the value of *OutputSize is undefined.
+ @param AuthenticationStatus A pointer to a caller-allocated UINT32 that indicates
+ the authentication status of the output buffer.
+ If the input section's
+ GuidedSectionHeader.Attributes field has the
+ EFI_GUIDED_SECTION_AUTH_STATUS_VALID bit as clear,
+ *AuthenticationStatus must return zero. These bits
+ reflect the status of the extraction operation.
+ If the function returns anything other than EFI_SUCCESS,
+ the value of *AuthenticationStatus is undefined.
+
+ @retval EFI_SUCCESS The InputSection was successfully processed and the
+ section contents were returned.
+ @retval EFI_OUT_OF_RESOURCES The system has insufficient resources to process the request.
+ @retval EFI_INVALID_PARAMETER The GUID in InputSection does not match this instance of the
+ GUIDed Section Extraction PPI.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_PEI_EXTRACT_GUIDED_SECTION)(
+ IN CONST EFI_PEI_GUIDED_SECTION_EXTRACTION_PPI *This,
+ IN CONST VOID *InputSection,
+ OUT VOID **OutputBuffer,
+ OUT UINTN *OutputSize,
+ OUT UINT32 *AuthenticationStatus
+ );
+
+///
+/// If a GUID-defined section is encountered when doing section extraction,
+/// the PEI Foundation or the EFI_PEI_FILE_LOADER_PPI instance
+/// calls the appropriate instance of the GUIDed Section
+/// Extraction PPI to extract the section stream contained
+/// therein.
+///
+struct _EFI_PEI_GUIDED_SECTION_EXTRACTION_PPI {
+ EFI_PEI_EXTRACT_GUIDED_SECTION ExtractSection;
+};
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Ppi/I2cMaster.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Ppi/I2cMaster.h
new file mode 100644
index 0000000000..bac91b4cc3
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Ppi/I2cMaster.h
@@ -0,0 +1,102 @@
+/** @file
+ This PPI manipulates the I2C host controller to perform transactions as a master
+ on the I2C bus using the current state of any switches or multiplexers in the I2C bus.
+
+ Copyright (c) 2013 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Revision Reference:
+ This PPI is introduced in PI Version 1.3.
+
+**/
+
+#ifndef __I2C_MASTER_PPI_H__
+#define __I2C_MASTER_PPI_H__
+
+#include
+
+#define EFI_PEI_I2C_MASTER_PPI_GUID \
+ { 0xb3bfab9b, 0x9f9c, 0x4e8b, { 0xad, 0x37, 0x7f, 0x8c, 0x51, 0xfc, 0x62, 0x80 }}
+
+typedef struct _EFI_PEI_I2C_MASTER_PPI EFI_PEI_I2C_MASTER_PPI;
+
+/**
+ Set the frequency for the I2C clock line.
+
+ @param This Pointer to an EFI_PEI_I2C_MASTER_PPI structure.
+ @param BusClockHertz Pointer to the requested I2C bus clock frequency in Hertz.
+ Upon return this value contains the actual frequency
+ in use by the I2C controller.
+
+ @retval EFI_SUCCESS The bus frequency was set successfully.
+ @retval EFI_INVALID_PARAMETER BusClockHertz is NULL
+ @retval EFI_UNSUPPORTED The controller does not support this frequency.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_PEI_I2C_MASTER_PPI_SET_BUS_FREQUENCY)(
+ IN EFI_PEI_I2C_MASTER_PPI *This,
+ IN UINTN *BusClockHertz
+ );
+
+/**
+ Reset the I2C controller and configure it for use.
+
+ @param This Pointer to an EFI_PEI_I2C_MASTER_PPI structure.
+
+ @retval EFI_SUCCESS The reset completed successfully.
+ @retval EFI_DEVICE_ERROR The reset operation failed.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_PEI_I2C_MASTER_PPI_RESET)(
+ IN CONST EFI_PEI_I2C_MASTER_PPI *This
+ );
+
+/**
+ Start an I2C transaction on the host controller.
+
+ @param This Pointer to an EFI_PEI_I2C_MASTER_PPI structure.
+ @param SlaveAddress Address of the device on the I2C bus.
+ Set the I2C_ADDRESSING_10_BIT when using 10-bit addresses,
+ clear this bit for 7-bit addressing.
+ Bits 0-6 are used for 7-bit I2C slave addresses and
+ bits 0-9 are used for 10-bit I2C slave addresses.
+ @param RequestPacket Pointer to an EFI_I2C_REQUEST_PACKET structure describing the I2C transaction.
+
+ @retval EFI_SUCCESS The transaction completed successfully.
+ @retval EFI_BAD_BUFFER_SIZE The RequestPacket->LengthInBytes value is too large.
+ @retval EFI_DEVICE_ERROR There was an I2C error (NACK) during the transaction.
+ @retval EFI_INVALID_PARAMETER RequestPacket is NULL
+ @retval EFI_NO_RESPONSE The I2C device is not responding to the slave address.
+ EFI_DEVICE_ERROR will be returned if the controller cannot distinguish when the NACK occurred.
+ @retval EFI_NOT_FOUND Reserved bit set in the SlaveAddress parameter
+ @retval EFI_OUT_OF_RESOURCES Insufficient memory for I2C transaction
+ @retval EFI_UNSUPPORTED The controller does not support the requested transaction.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_PEI_I2C_MASTER_PPI_START_REQUEST)(
+ IN CONST EFI_PEI_I2C_MASTER_PPI *This,
+ IN UINTN SlaveAddress,
+ IN EFI_I2C_REQUEST_PACKET *RequestPacket
+ );
+
+///
+/// This PPI manipulates the I2C host controller to perform transactions as a master on the I2C bus
+/// using the current state of any switches or multiplexers in the I2C bus.
+///
+struct _EFI_PEI_I2C_MASTER_PPI {
+ EFI_PEI_I2C_MASTER_PPI_SET_BUS_FREQUENCY SetBusFrequency;
+ EFI_PEI_I2C_MASTER_PPI_RESET Reset;
+ EFI_PEI_I2C_MASTER_PPI_START_REQUEST StartRequest;
+ CONST EFI_I2C_CONTROLLER_CAPABILITIES *I2cControllerCapabilities;
+ EFI_GUID Identifier;
+};
+
+extern EFI_GUID gEfiPeiI2cMasterPpiGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Ppi/IsaHc.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Ppi/IsaHc.h
new file mode 100644
index 0000000000..587b4bbcab
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Ppi/IsaHc.h
@@ -0,0 +1,113 @@
+/** @file
+ This PPI opens or closes an I/O aperture in a ISA HOST controller.
+
+ Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Revision Reference:
+ This PPI is from PI Version 1.2.1.
+
+**/
+
+#ifndef __ISA_HC_PPI_H__
+#define __ISA_HC_PPI_H__
+
+#define EFI_ISA_HC_PPI_GUID \
+ { \
+ 0x8d48bd70, 0xc8a3, 0x4c06, {0x90, 0x1b, 0x74, 0x79, 0x46, 0xaa, 0xc3, 0x58} \
+ }
+
+typedef struct _EFI_ISA_HC_PPI EFI_ISA_HC_PPI;
+typedef struct _EFI_ISA_HC_PPI *PEFI_ISA_HC_PPI;
+
+/**
+ Open I/O aperture.
+
+ This function opens an I/O aperture in a ISA Host Controller for the I/O
+ addresses specified by IoAddress to IoAddress + IoLength - 1. It is possible
+ that more than one caller may be assigned to the same aperture.
+ It may be possible that a single hardware aperture may be used for more than
+ one device. This function tracks the number of times that each aperture is
+ referenced, and does not close the hardware aperture (via CloseIoAperture())
+ until there are no more references to it.
+
+ @param This A pointer to this instance of the EFI_ISA_HC_PPI.
+ @param IoAddress An unsigned integer that specifies the first byte of
+ the I/O space required.
+ @param IoLength An unsigned integer that specifies the number of
+ bytes of the I/O space required.
+ @param IoApertureHandle A pointer to the returned I/O aperture handle.
+ This value can be used on subsequent calls to CloseIoAperture().
+
+ @retval EFI_SUCCESS The I/O aperture was opened successfully.
+ @retval EFI_UNSUPPORTED The ISA Host Controller is a subtractive-decode controller.
+ @retval EFI_OUT_OF_RESOURCES There is no available I/O aperture.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_PEI_ISA_HC_OPEN_IO)(
+ IN CONST EFI_ISA_HC_PPI *This,
+ IN UINT16 IoAddress,
+ IN UINT16 IoLength,
+ OUT UINT64 *IoApertureHandle
+ );
+
+/**
+ Close I/O aperture.
+
+ This function closes a previously opened I/O aperture handle. If there are no
+ more I/O aperture handles that refer to the hardware I/O aperture resource,
+ then the hardware I/O aperture is closed.
+ It may be possible that a single hardware aperture may be used for more than
+ one device. This function tracks the number of times that each aperture is
+ referenced, and does not close the hardware aperture (via CloseIoAperture())
+ until there are no more references to it.
+
+ @param This A pointer to this instance of the EFI_ISA_HC_PPI.
+ @param IoApertureHandle The I/O aperture handle previously returned from a
+ call to OpenIoAperture().
+
+ @retval EFI_SUCCESS The I/O aperture was closed successfully.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_PEI_ISA_HC_CLOSE_IO)(
+ IN CONST EFI_ISA_HC_PPI *This,
+ IN UINT64 IoApertureHandle
+ );
+
+///
+/// This PPI provides functions for opening or closing an I/O aperture.
+///
+struct _EFI_ISA_HC_PPI {
+ ///
+ /// An unsigned integer that specifies the version of the PPI structure.
+ ///
+ UINT32 Version;
+ ///
+ /// The address of the ISA/LPC Bridge device.
+ /// For PCI, this is the segment, bus, device and function of the a ISA/LPC
+ /// Bridge device.
+ ///
+ /// If bits 24-31 are 0, then the definition is:
+ /// Bits 0:2 - Function
+ /// Bits 3-7 - Device
+ /// Bits 8:15 - Bus
+ /// Bits 16-23 - Segment
+ /// Bits 24-31 - Bus Type
+ /// If bits 24-31 are 0xff, then the definition is platform-specific.
+ ///
+ UINT32 Address;
+ ///
+ /// Opens an aperture on a positive-decode ISA Host Controller.
+ ///
+ EFI_PEI_ISA_HC_OPEN_IO OpenIoAperture;
+ ///
+ /// Closes an aperture on a positive-decode ISA Host Controller.
+ ///
+ EFI_PEI_ISA_HC_CLOSE_IO CloseIoAperture;
+};
+
+extern EFI_GUID gEfiIsaHcPpiGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Ppi/LoadFile.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Ppi/LoadFile.h
new file mode 100644
index 0000000000..1c6c4930e5
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Ppi/LoadFile.h
@@ -0,0 +1,70 @@
+/** @file
+ Load image file from fv to memory.
+
+ Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Revision Reference:
+ This PPI is introduced in PI Version 1.0.
+
+**/
+
+#ifndef __LOAD_FILE_PPI_H__
+#define __LOAD_FILE_PPI_H__
+
+#define EFI_PEI_LOAD_FILE_PPI_GUID \
+ { 0xb9e0abfe, 0x5979, 0x4914, { 0x97, 0x7f, 0x6d, 0xee, 0x78, 0xc2, 0x78, 0xa6 } }
+
+typedef struct _EFI_PEI_LOAD_FILE_PPI EFI_PEI_LOAD_FILE_PPI;
+
+/**
+ Loads a PEIM into memory for subsequent execution.
+
+ This service is the single member function of EFI_LOAD_FILE_PPI.
+ This service separates image loading and relocating from the PEI Foundation.
+
+ @param This Interface pointer that implements
+ the Load File PPI instance.
+ @param FileHandle File handle of the file to load.
+ @param ImageAddress Pointer to the address of the loaded image.
+ @param ImageSize Pointer to the size of the loaded image.
+ @param EntryPoint Pointer to the entry point of the image.
+ @param AuthenticationState On exit, points to the attestation
+ authentication state of the image
+ or 0 if no attestation was performed.
+
+ @retval EFI_SUCCESS The image was loaded successfully.
+ @retval EFI_OUT_OF_RESOURCES There was not enough memory.
+ @retval EFI_LOAD_ERROR There was no supported image in the file.
+ @retval EFI_INVALID_PARAMETER FileHandle was not a valid firmware file handle.
+ @retval EFI_INVALID_PARAMETER EntryPoint was NULL.
+ @retval EFI_UNSUPPORTED An image requires relocations or is not
+ memory mapped.
+ @retval EFI_WARN_BUFFER_TOO_SMALL
+ There is not enough heap to allocate the requested size.
+ This will not prevent the XIP image from being invoked.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_PEI_LOAD_FILE)(
+ IN CONST EFI_PEI_LOAD_FILE_PPI *This,
+ IN EFI_PEI_FILE_HANDLE FileHandle,
+ OUT EFI_PHYSICAL_ADDRESS *ImageAddress,
+ OUT UINT64 *ImageSize,
+ OUT EFI_PHYSICAL_ADDRESS *EntryPoint,
+ OUT UINT32 *AuthenticationState
+ );
+
+///
+/// This PPI is a pointer to the Load File service.
+/// This service will be published by a PEIM. The PEI Foundation
+/// will use this service to launch the known PEI module images.
+///
+struct _EFI_PEI_LOAD_FILE_PPI {
+ EFI_PEI_LOAD_FILE LoadFile;
+};
+
+extern EFI_GUID gEfiPeiLoadFilePpiGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Ppi/LoadImage.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Ppi/LoadImage.h
new file mode 100644
index 0000000000..e1aa85ac3c
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Ppi/LoadImage.h
@@ -0,0 +1,44 @@
+/** @file
+ The file describes the PPI which notifies other drivers
+ of the PEIM being initialized by the PEI Dispatcher.
+
+ Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Revision Reference:
+ This PPI is introduced in PI Version 1.0.
+
+**/
+
+#ifndef __LOADED_IMAGE_PPI_H__
+#define __LOADED_IMAGE_PPI_H__
+
+#define EFI_PEI_LOADED_IMAGE_PPI_GUID \
+ { 0xc1fcd448, 0x6300, 0x4458, { 0xb8, 0x64, 0x28, 0xdf, 0x1, 0x53, 0x64, 0xbc } }
+
+typedef struct _EFI_PEI_LOADED_IMAGE_PPI EFI_PEI_LOADED_IMAGE_PPI;
+
+///
+/// This interface is installed by the PEI Dispatcher after the image has been
+/// loaded and after all security checks have been performed,
+/// to notify other PEIMs of the files which are being loaded.
+///
+struct _EFI_PEI_LOADED_IMAGE_PPI {
+ ///
+ /// Address of the image at the address where it will be executed.
+ ///
+ EFI_PHYSICAL_ADDRESS ImageAddress;
+ ///
+ /// Size of the image as it will be executed.
+ ///
+ UINT64 ImageSize;
+ ///
+ /// File handle from which the image was loaded.
+ /// Can be NULL, indicating the image was not loaded from a handle.
+ ///
+ EFI_PEI_FILE_HANDLE FileHandle;
+};
+
+extern EFI_GUID gEfiPeiLoadedImagePpiGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Ppi/MasterBootMode.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Ppi/MasterBootMode.h
new file mode 100644
index 0000000000..16d7a3fcee
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Ppi/MasterBootMode.h
@@ -0,0 +1,26 @@
+/** @file
+ This file declares Boot Mode PPI.
+
+ The Master Boot Mode PPI is installed by a PEIM to signal that a final
+ boot has been determined and set. This signal is useful in that PEIMs
+ with boot-mode-specific behavior can put this PPI in their dependency expression.
+
+ Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Revision Reference:
+ This PPI is introduced in PI Version 1.0.
+
+**/
+
+#ifndef __MASTER_BOOT_MODE_PPI_H__
+#define __MASTER_BOOT_MODE_PPI_H__
+
+#define EFI_PEI_MASTER_BOOT_MODE_PEIM_PPI \
+ { \
+ 0x7408d748, 0xfc8c, 0x4ee6, {0x92, 0x88, 0xc4, 0xbe, 0xc0, 0x92, 0xa4, 0x10 } \
+ }
+
+extern EFI_GUID gEfiPeiMasterBootModePpiGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Ppi/MemoryDiscovered.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Ppi/MemoryDiscovered.h
new file mode 100644
index 0000000000..69c4adda81
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Ppi/MemoryDiscovered.h
@@ -0,0 +1,26 @@
+/** @file
+ This file declares Memory Discovered PPI.
+
+ This PPI is published by the PEI Foundation when the main memory is installed.
+ It is essentially a PPI with no associated interface. Its purpose is to be used
+ as a signal for other PEIMs who can register for a notification on its installation.
+
+ Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Revision Reference:
+ This PPI is introduced in PI Version 1.0.
+
+**/
+
+#ifndef __PEI_MEMORY_DISCOVERED_PPI_H__
+#define __PEI_MEMORY_DISCOVERED_PPI_H__
+
+#define EFI_PEI_PERMANENT_MEMORY_INSTALLED_PPI_GUID \
+ { \
+ 0xf894643d, 0xc449, 0x42d1, {0x8e, 0xa8, 0x85, 0xbd, 0xd8, 0xc6, 0x5b, 0xde } \
+ }
+
+extern EFI_GUID gEfiPeiMemoryDiscoveredPpiGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Ppi/MmAccess.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Ppi/MmAccess.h
new file mode 100644
index 0000000000..03a9f697f1
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Ppi/MmAccess.h
@@ -0,0 +1,155 @@
+/** @file
+ EFI MM Access PPI definition.
+
+ This PPI is used to control the visibility of the MMRAM on the platform.
+ The EFI_PEI_MM_ACCESS_PPI abstracts the location and characteristics of MMRAM. The
+ principal functionality found in the memory controller includes the following:
+ - Exposing the MMRAM to all non-MM agents, or the "open" state
+ - Shrouding the MMRAM to all but the MM agents, or the "closed" state
+ - Preserving the system integrity, or "locking" the MMRAM, such that the settings cannot be
+ perturbed by either boot service or runtime agents
+
+ Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Revision Reference:
+ This PPI is introduced in PI Version 1.5.
+
+**/
+
+#ifndef _MM_ACCESS_PPI_H_
+#define _MM_ACCESS_PPI_H_
+
+#define EFI_PEI_MM_ACCESS_PPI_GUID \
+ { 0x268f33a9, 0xcccd, 0x48be, { 0x88, 0x17, 0x86, 0x5, 0x3a, 0xc3, 0x2e, 0xd6 }}
+
+typedef struct _EFI_PEI_MM_ACCESS_PPI EFI_PEI_MM_ACCESS_PPI;
+
+/**
+ Opens the MMRAM area to be accessible by a PEIM.
+
+ This function "opens" MMRAM so that it is visible while not inside of MM. The function should
+ return EFI_UNSUPPORTED if the hardware does not support hiding of MMRAM. The function
+ should return EFI_DEVICE_ERROR if the MMRAM configuration is locked.
+
+ @param PeiServices An indirect pointer to the PEI Services Table published by the PEI Foundation.
+ @param This The EFI_PEI_MM_ACCESS_PPI instance.
+ @param DescriptorIndex The region of MMRAM to Open.
+
+ @retval EFI_SUCCESS The operation was successful.
+ @retval EFI_UNSUPPORTED The system does not support opening and closing of MMRAM.
+ @retval EFI_DEVICE_ERROR MMRAM cannot be opened, perhaps because it is locked.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_PEI_MM_OPEN)(
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PEI_MM_ACCESS_PPI *This,
+ IN UINTN DescriptorIndex
+ );
+
+/**
+ Inhibits access to the MMRAM.
+
+ This function "closes" MMRAM so that it is not visible while outside of MM. The function should
+ return EFI_UNSUPPORTED if the hardware does not support hiding of MMRAM.
+
+ @param PeiServices An indirect pointer to the PEI Services Table published by the PEI Foundation.
+ @param This The EFI_PEI_MM_ACCESS_PPI instance.
+ @param DescriptorIndex The region of MMRAM to Close.
+
+ @retval EFI_SUCCESS The operation was successful.
+ @retval EFI_UNSUPPORTED The system does not support opening and closing of MMRAM.
+ @retval EFI_DEVICE_ERROR MMRAM cannot be closed.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_PEI_MM_CLOSE)(
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PEI_MM_ACCESS_PPI *This,
+ IN UINTN DescriptorIndex
+ );
+
+/**
+ This function prohibits access to the MMRAM region. This function is usually implemented such
+ that it is a write-once operation.
+
+ @param PeiServices An indirect pointer to the PEI Services Table published by the PEI Foundation.
+ @param This The EFI_PEI_MM_ACCESS_PPI instance.
+ @param DescriptorIndex The region of MMRAM to Lock.
+
+ @retval EFI_SUCCESS The operation was successful.
+ @retval EFI_UNSUPPORTED The system does not support opening and closing of MMRAM.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_PEI_MM_LOCK)(
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PEI_MM_ACCESS_PPI *This,
+ IN UINTN DescriptorIndex
+ );
+
+/**
+ Queries the memory controller for the possible regions that will support MMRAM.
+
+ This function describes the MMRAM regions.
+ This data structure forms the contract between the MM_ACCESS and MM_IPL drivers. There is an
+ ambiguity when any MMRAM region is remapped. For example, on some chipsets, some MMRAM
+ regions can be initialized at one physical address but is later accessed at another processor address.
+ There is currently no way for the MM IPL driver to know that it must use two different addresses
+ depending on what it is trying to do. As a result, initial configuration and loading can use the
+ physical address PhysicalStart while MMRAM is open. However, once the region has been
+ closed and needs to be accessed by agents in MM, the CpuStart address must be used.
+ This PPI publishes the available memory that the chipset can shroud for the use of installing code.
+ These regions serve the dual purpose of describing which regions have been open, closed, or locked.
+ In addition, these regions may include overlapping memory ranges, depending on the chipset
+ implementation. The latter might include a chipset that supports T-SEG, where memory near the top
+ of the physical DRAM can be allocated for MMRAM too.
+ The key thing to note is that the regions that are described by the PPI are a subset of the capabilities
+ of the hardware.
+
+ @param PeiServices An indirect pointer to the PEI Services Table published by the PEI Foundation.
+ @param This The EFI_PEI_MM_ACCESS_PPI instance.
+ @param MmramMapSize A pointer to the size, in bytes, of the MmramMemoryMap buffer. On input, this value is
+ the size of the buffer that is allocated by the caller. On output, it is the size of the
+ buffer that was returned by the firmware if the buffer was large enough, or, if the
+ buffer was too small, the size of the buffer that is needed to contain the map.
+ @param MmramMap A pointer to the buffer in which firmware places the current memory map. The map is
+ an array of EFI_MMRAM_DESCRIPTORs
+
+ @retval EFI_SUCCESS The chipset supported the given resource.
+ @retval EFI_BUFFER_TOO_SMALL The MmramMap parameter was too small. The current
+ buffer size needed to hold the memory map is returned in
+ MmramMapSize.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_PEI_MM_CAPABILITIES)(
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PEI_MM_ACCESS_PPI *This,
+ IN OUT UINTN *MmramMapSize,
+ IN OUT EFI_MMRAM_DESCRIPTOR *MmramMap
+ );
+
+///
+/// EFI MM Access PPI is used to control the visibility of the MMRAM on the platform.
+/// It abstracts the location and characteristics of MMRAM. The platform should report
+/// all MMRAM via EFI_PEI_MM_ACCESS_PPI. The expectation is that the north bridge or
+/// memory controller would publish this PPI.
+///
+struct _EFI_PEI_MM_ACCESS_PPI {
+ EFI_PEI_MM_OPEN Open;
+ EFI_PEI_MM_CLOSE Close;
+ EFI_PEI_MM_LOCK Lock;
+ EFI_PEI_MM_CAPABILITIES GetCapabilities;
+ BOOLEAN LockState;
+ BOOLEAN OpenState;
+};
+
+extern EFI_GUID gEfiPeiMmAccessPpiGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Ppi/MmCommunication.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Ppi/MmCommunication.h
new file mode 100644
index 0000000000..33a0544de4
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Ppi/MmCommunication.h
@@ -0,0 +1,71 @@
+/** @file
+ EFI MM Communication PPI definition.
+
+ This PPI provides a means of communicating between drivers outside
+ of MM and MMI handlers inside of MM in PEI phase.
+
+ Copyright (c) 2010 - 2018, Intel Corporation. All rights reserved.
+ Copyright (c) Microsoft Corporation.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef MM_COMMUNICATION_PPI_H_
+#define MM_COMMUNICATION_PPI_H_
+
+#define EFI_PEI_MM_COMMUNICATION_PPI_GUID \
+ { \
+ 0xae933e1c, 0xcc47, 0x4e38, { 0x8f, 0xe, 0xe2, 0xf6, 0x1d, 0x26, 0x5, 0xdf } \
+ }
+
+typedef struct _EFI_PEI_MM_COMMUNICATION_PPI EFI_PEI_MM_COMMUNICATION_PPI;
+
+/**
+ Communicates with a registered handler.
+
+ This function provides a service to send and receive messages from a registered PEI service.
+ The EFI_PEI_MM_COMMUNICATION_PPI driver is responsible for doing any of the copies such that
+ the data lives in PEI-service-accessible RAM.
+
+ A given implementation of the EFI_PEI_MM_COMMUNICATION_PPI may choose to use the
+ EFI_MM_CONTROL_PPI for effecting the mode transition, or it may use some other method.
+
+ The agent invoking the communication interface must be physical/virtually 1:1 mapped.
+
+ To avoid confusion in interpreting frames, the CommBuffer parameter should always begin with
+ EFI_MM_COMMUNICATE_HEADER. The header data is mandatory for messages sent into the MM agent.
+
+ Once inside of MM, the MM infrastructure will call all registered handlers with the same
+ HandlerType as the GUID specified by HeaderGuid and the CommBuffer pointing to Data.
+
+ This function is not reentrant.
+
+ @param[in] This The EFI_PEI_MM_COMMUNICATION_PPI instance.
+ @param[in] CommBuffer Pointer to the buffer to convey into MMRAM.
+ @param[in] CommSize The size of the data buffer being passed in. On exit, the
+ size of data being returned. Zero if the handler does not
+ wish to reply with any data.
+
+ @retval EFI_SUCCESS The message was successfully posted.
+ @retval EFI_INVALID_PARAMETER The buffer was NULL.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_PEI_MM_COMMUNICATE)(
+ IN CONST EFI_PEI_MM_COMMUNICATION_PPI *This,
+ IN OUT VOID *CommBuffer,
+ IN OUT UINTN *CommSize
+ );
+
+///
+/// EFI MM Communication PPI provides services for communicating between PEIM and a registered
+/// MMI handler.
+///
+struct _EFI_PEI_MM_COMMUNICATION_PPI {
+ EFI_PEI_MM_COMMUNICATE Communicate;
+};
+
+extern EFI_GUID gEfiPeiMmCommunicationPpiGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Ppi/MmConfiguration.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Ppi/MmConfiguration.h
new file mode 100644
index 0000000000..6ec776ebbd
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Ppi/MmConfiguration.h
@@ -0,0 +1,62 @@
+/** @file
+ EFI MM Configuration PPI as defined in PI 1.5 specification.
+
+ This PPI is used to:
+ 1) report the portions of MMRAM regions which cannot be used for the MMRAM heap.
+ 2) register the MM Foundation entry point with the processor code. The entry
+ point will be invoked by the MM processor entry code.
+
+ Copyright (c) Microsoft Corporation.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef MM_CONFIGURATION_PPI_H_
+#define MM_CONFIGURATION_PPI_H_
+
+#include
+
+#define EFI_PEI_MM_CONFIGURATION_PPI_GUID \
+ { \
+ 0xc109319, 0xc149, 0x450e, { 0xa3, 0xe3, 0xb9, 0xba, 0xdd, 0x9d, 0xc3, 0xa4 } \
+ }
+
+typedef struct _EFI_PEI_MM_CONFIGURATION_PPI EFI_PEI_MM_CONFIGURATION_PPI;
+
+/**
+ This function registers the MM Foundation entry point with the processor code. This entry point will be
+ invoked by the MM Processor entry code as defined in PI specification.
+
+ @param[in] This The EFI_PEI_MM_CONFIGURATION_PPI instance.
+ @param[in] MmEntryPoint MM Foundation entry point.
+
+ @retval EFI_SUCCESS The entry-point was successfully registered.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_PEI_MM_REGISTER_MM_ENTRY)(
+ IN CONST EFI_PEI_MM_CONFIGURATION_PPI *This,
+ IN EFI_MM_ENTRY_POINT MmEntryPoint
+ );
+
+///
+/// This PPI is a PPI published by a CPU PEIM to indicate which areas within MMRAM are reserved for use by
+/// the CPU for any purpose, such as stack, save state or MM entry point. If a platform chooses to let a CPU
+/// PEIM do MMRAM relocation, this PPI must be produced by this CPU PEIM.
+///
+/// The MmramReservedRegions points to an array of one or more EFI_MM_RESERVED_MMRAM_REGION structures, with
+/// the last structure having the MmramReservedSize set to 0. An empty array would contain only the last
+/// structure.
+///
+/// The RegisterMmEntry() function allows the MM IPL PEIM to register the MM Foundation entry point with the
+/// MM entry vector code.
+///
+struct _EFI_PEI_MM_CONFIGURATION_PPI {
+ EFI_MM_RESERVED_MMRAM_REGION *MmramReservedRegions;
+ EFI_PEI_MM_REGISTER_MM_ENTRY RegisterMmEntry;
+};
+
+extern EFI_GUID gEfiPeiMmConfigurationPpi;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Ppi/MmControl.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Ppi/MmControl.h
new file mode 100644
index 0000000000..70c093697a
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Ppi/MmControl.h
@@ -0,0 +1,89 @@
+/** @file
+ EFI MM Control PPI definition.
+
+ This PPI is used initiate synchronous MMI activations. This PPI could be published by a processor
+ driver to abstract the MMI IPI or a driver which abstracts the ASIC that is supporting the APM port.
+ Because of the possibility of performing MMI IPI transactions, the ability to generate this event
+ from a platform chipset agent is an optional capability for both IA-32 and x64-based systems.
+
+ Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Revision Reference:
+ This PPI is introduced in PI Version 1.5.
+
+**/
+
+#ifndef _MM_CONTROL_PPI_H_
+#define _MM_CONTROL_PPI_H_
+
+#define EFI_PEI_MM_CONTROL_PPI_GUID \
+ { 0x61c68702, 0x4d7e, 0x4f43, 0x8d, 0xef, 0xa7, 0x43, 0x5, 0xce, 0x74, 0xc5 }
+
+typedef struct _EFI_PEI_MM_CONTROL_PPI EFI_PEI_MM_CONTROL_PPI;
+
+/**
+ Invokes PPI activation from the PI PEI environment.
+
+ @param PeiServices An indirect pointer to the PEI Services Table published by the PEI Foundation.
+ @param This The PEI_MM_CONTROL_PPI instance.
+ @param ArgumentBuffer The value passed to the MMI handler. This value corresponds to the
+ SwMmiInputValue in the RegisterContext parameter for the Register()
+ function in the EFI_MM_SW_DISPATCH_PROTOCOL and in the Context parameter
+ in the call to the DispatchFunction
+ @param ArgumentBufferSize The size of the data passed in ArgumentBuffer or NULL if ArgumentBuffer is NULL.
+ @param Periodic An optional mechanism to periodically repeat activation.
+ @param ActivationInterval An optional parameter to repeat at this period one
+ time or, if the Periodic Boolean is set, periodically.
+
+ @retval EFI_SUCCESS The MMI has been engendered.
+ @retval EFI_DEVICE_ERROR The timing is unsupported.
+ @retval EFI_INVALID_PARAMETER The activation period is unsupported.
+ @retval EFI_NOT_STARTED The MM base service has not been initialized.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_PEI_MM_ACTIVATE)(
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PEI_MM_CONTROL_PPI *This,
+ IN OUT INT8 *ArgumentBuffer OPTIONAL,
+ IN OUT UINTN *ArgumentBufferSize OPTIONAL,
+ IN BOOLEAN Periodic OPTIONAL,
+ IN UINTN ActivationInterval OPTIONAL
+ );
+
+/**
+ Clears any system state that was created in response to the Trigger() call.
+
+ @param PeiServices General purpose services available to every PEIM.
+ @param This The PEI_MM_CONTROL_PPI instance.
+ @param Periodic Optional parameter to repeat at this period one
+ time or, if the Periodic Boolean is set, periodically.
+
+ @retval EFI_SUCCESS The MMI has been engendered.
+ @retval EFI_DEVICE_ERROR The source could not be cleared.
+ @retval EFI_INVALID_PARAMETER The service did not support the Periodic input argument.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_PEI_MM_DEACTIVATE)(
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PEI_MM_CONTROL_PPI *This,
+ IN BOOLEAN Periodic OPTIONAL
+ );
+
+///
+/// The EFI_PEI_MM_CONTROL_PPI is produced by a PEIM. It provides an abstraction of the
+/// platform hardware that generates an MMI. There are often I/O ports that, when accessed, will
+/// generate the MMI. Also, the hardware optionally supports the periodic generation of these signals.
+///
+struct _EFI_PEI_MM_CONTROL_PPI {
+ EFI_PEI_MM_ACTIVATE Trigger;
+ EFI_PEI_MM_DEACTIVATE Clear;
+};
+
+extern EFI_GUID gEfiPeiMmControlPpiGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Ppi/MpServices.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Ppi/MpServices.h
new file mode 100644
index 0000000000..27964d8566
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Ppi/MpServices.h
@@ -0,0 +1,277 @@
+/** @file
+ This file declares UEFI PI Multi-processor PPI.
+ This PPI is installed by some platform or chipset-specific PEIM that abstracts
+ handling multiprocessor support.
+
+ Copyright (c) 2015 - 2017, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Revision Reference:
+ This PPI is introduced in PI Version 1.4.
+
+**/
+
+#ifndef __PEI_MP_SERVICES_PPI_H__
+#define __PEI_MP_SERVICES_PPI_H__
+
+#include
+
+#define EFI_PEI_MP_SERVICES_PPI_GUID \
+ { \
+ 0xee16160a, 0xe8be, 0x47a6, { 0x82, 0xa, 0xc6, 0x90, 0xd, 0xb0, 0x25, 0xa } \
+ }
+
+typedef struct _EFI_PEI_MP_SERVICES_PPI EFI_PEI_MP_SERVICES_PPI;
+
+/**
+ Get the number of CPU's.
+
+ @param[in] PeiServices An indirect pointer to the PEI Services Table
+ published by the PEI Foundation.
+ @param[in] This Pointer to this instance of the PPI.
+ @param[out] NumberOfProcessors Pointer to the total number of logical processors in
+ the system, including the BSP and disabled APs.
+ @param[out] NumberOfEnabledProcessors
+ Number of processors in the system that are enabled.
+
+ @retval EFI_SUCCESS The number of logical processors and enabled
+ logical processors was retrieved.
+ @retval EFI_DEVICE_ERROR The calling processor is an AP.
+ @retval EFI_INVALID_PARAMETER NumberOfProcessors is NULL.
+ NumberOfEnabledProcessors is NULL.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_PEI_MP_SERVICES_GET_NUMBER_OF_PROCESSORS)(
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PEI_MP_SERVICES_PPI *This,
+ OUT UINTN *NumberOfProcessors,
+ OUT UINTN *NumberOfEnabledProcessors
+ );
+
+/**
+ Get information on a specific CPU.
+
+ @param[in] PeiServices An indirect pointer to the PEI Services Table
+ published by the PEI Foundation.
+ @param[in] This Pointer to this instance of the PPI.
+ @param[in] ProcessorNumber Pointer to the total number of logical processors in
+ the system, including the BSP and disabled APs.
+ @param[out] ProcessorInfoBuffer Number of processors in the system that are enabled.
+
+ @retval EFI_SUCCESS Processor information was returned.
+ @retval EFI_DEVICE_ERROR The calling processor is an AP.
+ @retval EFI_INVALID_PARAMETER ProcessorInfoBuffer is NULL.
+ @retval EFI_NOT_FOUND The processor with the handle specified by
+ ProcessorNumber does not exist in the platform.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_PEI_MP_SERVICES_GET_PROCESSOR_INFO)(
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PEI_MP_SERVICES_PPI *This,
+ IN UINTN ProcessorNumber,
+ OUT EFI_PROCESSOR_INFORMATION *ProcessorInfoBuffer
+ );
+
+/**
+ Activate all of the application processors.
+
+ @param[in] PeiServices An indirect pointer to the PEI Services Table
+ published by the PEI Foundation.
+ @param[in] This A pointer to the EFI_PEI_MP_SERVICES_PPI instance.
+ @param[in] Procedure A pointer to the function to be run on enabled APs of
+ the system.
+ @param[in] SingleThread If TRUE, then all the enabled APs execute the function
+ specified by Procedure one by one, in ascending order
+ of processor handle number. If FALSE, then all the
+ enabled APs execute the function specified by Procedure
+ simultaneously.
+ @param[in] TimeoutInMicroSeconds
+ Indicates the time limit in microseconds for APs to
+ return from Procedure, for blocking mode only. Zero
+ means infinity. If the timeout expires before all APs
+ return from Procedure, then Procedure on the failed APs
+ is terminated. All enabled APs are available for next
+ function assigned by EFI_PEI_MP_SERVICES_PPI.StartupAllAPs()
+ or EFI_PEI_MP_SERVICES_PPI.StartupThisAP(). If the
+ timeout expires in blocking mode, BSP returns
+ EFI_TIMEOUT.
+ @param[in] ProcedureArgument The parameter passed into Procedure for all APs.
+
+ @retval EFI_SUCCESS In blocking mode, all APs have finished before the
+ timeout expired.
+ @retval EFI_DEVICE_ERROR Caller processor is AP.
+ @retval EFI_NOT_STARTED No enabled APs exist in the system.
+ @retval EFI_NOT_READY Any enabled APs are busy.
+ @retval EFI_TIMEOUT In blocking mode, the timeout expired before all
+ enabled APs have finished.
+ @retval EFI_INVALID_PARAMETER Procedure is NULL.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_PEI_MP_SERVICES_STARTUP_ALL_APS)(
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PEI_MP_SERVICES_PPI *This,
+ IN EFI_AP_PROCEDURE Procedure,
+ IN BOOLEAN SingleThread,
+ IN UINTN TimeoutInMicroSeconds,
+ IN VOID *ProcedureArgument OPTIONAL
+ );
+
+/**
+ Activate a specific application processor.
+
+ @param[in] PeiServices An indirect pointer to the PEI Services Table
+ published by the PEI Foundation.
+ @param[in] This A pointer to the EFI_PEI_MP_SERVICES_PPI instance.
+ @param[in] Procedure A pointer to the function to be run on enabled APs of
+ the system.
+ @param[in] ProcessorNumber The handle number of the AP. The range is from 0 to the
+ total number of logical processors minus 1. The total
+ number of logical processors can be retrieved by
+ EFI_PEI_MP_SERVICES_PPI.GetNumberOfProcessors().
+ @param[in] TimeoutInMicroSeconds
+ Indicates the time limit in microseconds for APs to
+ return from Procedure, for blocking mode only. Zero
+ means infinity. If the timeout expires before all APs
+ return from Procedure, then Procedure on the failed APs
+ is terminated. All enabled APs are available for next
+ function assigned by EFI_PEI_MP_SERVICES_PPI.StartupAllAPs()
+ or EFI_PEI_MP_SERVICES_PPI.StartupThisAP(). If the
+ timeout expires in blocking mode, BSP returns
+ EFI_TIMEOUT.
+ @param[in] ProcedureArgument The parameter passed into Procedure for all APs.
+
+ @retval EFI_SUCCESS In blocking mode, specified AP finished before the
+ timeout expires.
+ @retval EFI_DEVICE_ERROR The calling processor is an AP.
+ @retval EFI_TIMEOUT In blocking mode, the timeout expired before the
+ specified AP has finished.
+ @retval EFI_NOT_FOUND The processor with the handle specified by
+ ProcessorNumber does not exist.
+ @retval EFI_INVALID_PARAMETER ProcessorNumber specifies the BSP or disabled AP.
+ @retval EFI_INVALID_PARAMETER Procedure is NULL.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_PEI_MP_SERVICES_STARTUP_THIS_AP)(
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PEI_MP_SERVICES_PPI *This,
+ IN EFI_AP_PROCEDURE Procedure,
+ IN UINTN ProcessorNumber,
+ IN UINTN TimeoutInMicroseconds,
+ IN VOID *ProcedureArgument OPTIONAL
+ );
+
+/**
+ Switch the boot strap processor.
+
+ @param[in] PeiServices An indirect pointer to the PEI Services Table
+ published by the PEI Foundation.
+ @param[in] This A pointer to the EFI_PEI_MP_SERVICES_PPI instance.
+ @param[in] ProcessorNumber The handle number of the AP. The range is from 0 to the
+ total number of logical processors minus 1. The total
+ number of logical processors can be retrieved by
+ EFI_PEI_MP_SERVICES_PPI.GetNumberOfProcessors().
+ @param[in] EnableOldBSP If TRUE, then the old BSP will be listed as an enabled
+ AP. Otherwise, it will be disabled.
+
+ @retval EFI_SUCCESS BSP successfully switched.
+ @retval EFI_UNSUPPORTED Switching the BSP cannot be completed prior to this
+ service returning.
+ @retval EFI_UNSUPPORTED Switching the BSP is not supported.
+ @retval EFI_DEVICE_ERROR The calling processor is an AP.
+ @retval EFI_NOT_FOUND The processor with the handle specified by
+ ProcessorNumber does not exist.
+ @retval EFI_INVALID_PARAMETER ProcessorNumber specifies the current BSP or a disabled
+ AP.
+ @retval EFI_NOT_READY The specified AP is busy.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_PEI_MP_SERVICES_SWITCH_BSP)(
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PEI_MP_SERVICES_PPI *This,
+ IN UINTN ProcessorNumber,
+ IN BOOLEAN EnableOldBSP
+ );
+
+/**
+ Enable or disable an application processor.
+
+ @param[in] PeiServices An indirect pointer to the PEI Services Table
+ published by the PEI Foundation.
+ @param[in] This A pointer to the EFI_PEI_MP_SERVICES_PPI instance.
+ @param[in] ProcessorNumber The handle number of the AP. The range is from 0 to the
+ total number of logical processors minus 1. The total
+ number of logical processors can be retrieved by
+ EFI_PEI_MP_SERVICES_PPI.GetNumberOfProcessors().
+ @param[in] EnableAP Specifies the new state for the processor for enabled,
+ FALSE for disabled.
+ @param[in] HealthFlag If not NULL, a pointer to a value that specifies the
+ new health status of the AP. This flag corresponds to
+ StatusFlag defined in EFI_PEI_MP_SERVICES_PPI.GetProcessorInfo().
+ Only the PROCESSOR_HEALTH_STATUS_BIT is used. All other
+ bits are ignored. If it is NULL, this parameter is
+ ignored.
+
+ @retval EFI_SUCCESS The specified AP was enabled or disabled successfully.
+ @retval EFI_UNSUPPORTED Enabling or disabling an AP cannot be completed prior
+ to this service returning.
+ @retval EFI_UNSUPPORTED Enabling or disabling an AP is not supported.
+ @retval EFI_DEVICE_ERROR The calling processor is an AP.
+ @retval EFI_NOT_FOUND Processor with the handle specified by ProcessorNumber
+ does not exist.
+ @retval EFI_INVALID_PARAMETER ProcessorNumber specifies the BSP.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_PEI_MP_SERVICES_ENABLEDISABLEAP)(
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PEI_MP_SERVICES_PPI *This,
+ IN UINTN ProcessorNumber,
+ IN BOOLEAN EnableAP,
+ IN UINT32 *HealthFlag OPTIONAL
+ );
+
+/**
+ Identify the currently executing processor.
+
+ @param[in] PeiServices An indirect pointer to the PEI Services Table
+ published by the PEI Foundation.
+ @param[in] This A pointer to the EFI_PEI_MP_SERVICES_PPI instance.
+ @param[out] ProcessorNumber The handle number of the AP. The range is from 0 to the
+ total number of logical processors minus 1. The total
+ number of logical processors can be retrieved by
+ EFI_PEI_MP_SERVICES_PPI.GetNumberOfProcessors().
+
+ @retval EFI_SUCCESS The current processor handle number was returned in
+ ProcessorNumber.
+ @retval EFI_INVALID_PARAMETER ProcessorNumber is NULL.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_PEI_MP_SERVICES_WHOAMI)(
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PEI_MP_SERVICES_PPI *This,
+ OUT UINTN *ProcessorNumber
+ );
+
+///
+/// This PPI is installed by some platform or chipset-specific PEIM that abstracts
+/// handling multiprocessor support.
+///
+struct _EFI_PEI_MP_SERVICES_PPI {
+ EFI_PEI_MP_SERVICES_GET_NUMBER_OF_PROCESSORS GetNumberOfProcessors;
+ EFI_PEI_MP_SERVICES_GET_PROCESSOR_INFO GetProcessorInfo;
+ EFI_PEI_MP_SERVICES_STARTUP_ALL_APS StartupAllAPs;
+ EFI_PEI_MP_SERVICES_STARTUP_THIS_AP StartupThisAP;
+ EFI_PEI_MP_SERVICES_SWITCH_BSP SwitchBSP;
+ EFI_PEI_MP_SERVICES_ENABLEDISABLEAP EnableDisableAP;
+ EFI_PEI_MP_SERVICES_WHOAMI WhoAmI;
+};
+
+extern EFI_GUID gEfiPeiMpServicesPpiGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Ppi/Pcd.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Ppi/Pcd.h
new file mode 100644
index 0000000000..99c00917ec
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Ppi/Pcd.h
@@ -0,0 +1,794 @@
+/** @file
+ Native Platform Configuration Database (PCD) PPI
+
+ Different with the EFI_PCD_PPI defined in PI 1.2 specification, the native
+ PCD PPI provide interfaces for dynamic and dynamic-ex type PCD.
+ The interfaces for dynamic type PCD do not require the token space guid as parameter,
+ but interfaces for dynamic-ex type PCD require token space guid as parameter.
+
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __PCD_PPI_H__
+#define __PCD_PPI_H__
+
+#define PCD_PPI_GUID \
+ { 0x6e81c58, 0x4ad7, 0x44bc, { 0x83, 0x90, 0xf1, 0x2, 0x65, 0xf7, 0x24, 0x80 } }
+
+#define PCD_INVALID_TOKEN_NUMBER ((UINTN) 0)
+
+/**
+ Sets the SKU value for subsequent calls to set or get PCD token values.
+
+ SetSku() sets the SKU Id to be used for subsequent calls to set or get PCD values.
+ SetSku() is normally called only once by the system.
+
+ For each item (token), the database can hold a single value that applies to all SKUs,
+ or multiple values, where each value is associated with a specific SKU Id. Items with multiple,
+ SKU-specific values are called SKU enabled.
+
+ The SKU Id of zero is reserved as a default. The valid SkuId range is 1 to 255.
+ For tokens that are not SKU enabled, the system ignores any set SKU Id and works with the
+ single value for that token. For SKU-enabled tokens, the system will use the SKU Id set by the
+ last call to SetSku(). If no SKU Id is set or the currently set SKU Id isn't valid for the specified token,
+ the system uses the default SKU Id. If the system attempts to use the default SKU Id and no value has been
+ set for that Id, the results are unpredictable.
+
+ @param[in] SkuId The SKU value that will be used when the PCD service will retrieve and
+ set values associated with a PCD token.
+
+ @retval VOID
+
+**/
+typedef
+VOID
+(EFIAPI *PCD_PPI_SET_SKU)(
+ IN UINTN SkuId
+ );
+
+/**
+ Retrieves an 8-bit value for a given PCD token.
+
+ Retrieves the current byte-sized value for a PCD token number.
+ If the TokenNumber is invalid, the results are unpredictable.
+
+ @param[in] TokenNumber The PCD token number.
+
+ @return The UINT8 value.
+
+**/
+typedef
+UINT8
+(EFIAPI *PCD_PPI_GET8)(
+ IN UINTN TokenNumber
+ );
+
+/**
+ Retrieves a 16-bit value for a given PCD token.
+
+ Retrieves the current 16-bit value for a PCD token number.
+ If the TokenNumber is invalid, the results are unpredictable.
+
+ @param[in] TokenNumber The PCD token number.
+
+ @return The UINT16 value.
+
+**/
+typedef
+UINT16
+(EFIAPI *PCD_PPI_GET16)(
+ IN UINTN TokenNumber
+ );
+
+/**
+ Retrieves a 32-bit value for a given PCD token.
+
+ Retrieves the current 32-bit value for a PCD token number.
+ If the TokenNumber is invalid, the results are unpredictable.
+
+ @param[in] TokenNumber The PCD token number.
+
+ @return The UINT32 value.
+
+**/
+typedef
+UINT32
+(EFIAPI *PCD_PPI_GET32)(
+ IN UINTN TokenNumber
+ );
+
+/**
+ Retrieves a 64-bit value for a given PCD token.
+
+ Retrieves the current 64-bit value for a PCD token number.
+ If the TokenNumber is invalid, the results are unpredictable.
+
+ @param[in] TokenNumber The PCD token number.
+
+ @return The UINT64 value.
+
+**/
+typedef
+UINT64
+(EFIAPI *PCD_PPI_GET64)(
+ IN UINTN TokenNumber
+ );
+
+/**
+ Retrieves a pointer to a value for a given PCD token.
+
+ Retrieves the current pointer to the buffer for a PCD token number.
+ Do not make any assumptions about the alignment of the pointer that
+ is returned by this function call. If the TokenNumber is invalid,
+ the results are unpredictable.
+
+ @param[in] TokenNumber The PCD token number.
+
+ @return The pointer to the buffer to be retrieved.
+
+**/
+typedef
+VOID *
+(EFIAPI *PCD_PPI_GET_POINTER)(
+ IN UINTN TokenNumber
+ );
+
+/**
+ Retrieves a Boolean value for a given PCD token.
+
+ Retrieves the current boolean value for a PCD token number.
+ Do not make any assumptions about the alignment of the pointer that
+ is returned by this function call. If the TokenNumber is invalid,
+ the results are unpredictable.
+
+ @param[in] TokenNumber The PCD token number.
+
+ @return The Boolean value.
+
+**/
+typedef
+BOOLEAN
+(EFIAPI *PCD_PPI_GET_BOOLEAN)(
+ IN UINTN TokenNumber
+ );
+
+/**
+ Retrieves the size of the value for a given PCD token.
+
+ Retrieves the current size of a particular PCD token.
+ If the TokenNumber is invalid, the results are unpredictable.
+
+ @param[in] TokenNumber The PCD token number.
+
+ @return The size of the value for the PCD token.
+
+**/
+typedef
+UINTN
+(EFIAPI *PCD_PPI_GET_SIZE)(
+ IN UINTN TokenNumber
+ );
+
+/**
+ Retrieves an 8-bit value for a given PCD token and token space.
+
+ Retrieves the 8-bit value of a particular PCD token.
+ If the TokenNumber is invalid or the token space
+ specified by Guid does not exist, the results are
+ unpredictable.
+
+ @param[in] Guid The token space for the token number.
+ @param[in] TokenNumber The PCD token number.
+
+ @return The size 8-bit value for the PCD token.
+
+**/
+typedef
+UINT8
+(EFIAPI *PCD_PPI_GET_EX_8)(
+ IN CONST EFI_GUID *Guid,
+ IN UINTN TokenNumber
+ );
+
+/**
+ Retrieves a 16-bit value for a given PCD token and token space.
+
+ Retrieves the 16-bit value of a particular PCD token.
+ If the TokenNumber is invalid or the token space
+ specified by Guid does not exist, the results are
+ unpredictable.
+
+ @param[in] Guid The token space for the token number.
+ @param[in] TokenNumber The PCD token number.
+
+ @return The size 16-bit value for the PCD token.
+
+**/
+typedef
+UINT16
+(EFIAPI *PCD_PPI_GET_EX_16)(
+ IN CONST EFI_GUID *Guid,
+ IN UINTN TokenNumber
+ );
+
+/**
+ Retrieves a 32-bit value for a given PCD token and token space.
+
+ Retrieves the 32-bit value of a particular PCD token.
+ If the TokenNumber is invalid or the token space
+ specified by Guid does not exist, the results are
+ unpredictable.
+
+ @param[in] Guid The token space for the token number.
+ @param[in] TokenNumber The PCD token number.
+
+ @return The size 32-bit value for the PCD token.
+
+**/
+typedef
+UINT32
+(EFIAPI *PCD_PPI_GET_EX_32)(
+ IN CONST EFI_GUID *Guid,
+ IN UINTN TokenNumber
+ );
+
+/**
+ Retrieves a 64-bit value for a given PCD token and token space.
+
+ Retrieves the 64-bit value of a particular PCD token.
+ If the TokenNumber is invalid or the token space
+ specified by Guid does not exist, the results are
+ unpredictable.
+
+ @param[in] Guid The token space for the token number.
+ @param[in] TokenNumber The PCD token number.
+
+ @return The size 64-bit value for the PCD token.
+
+**/
+typedef
+UINT64
+(EFIAPI *PCD_PPI_GET_EX_64)(
+ IN CONST EFI_GUID *Guid,
+ IN UINTN TokenNumber
+ );
+
+/**
+ Retrieves a pointer to a value for a given PCD token and token space.
+
+ Retrieves the current pointer to the buffer for a PCD token number.
+ Do not make any assumptions about the alignment of the pointer that
+ is returned by this function call. If the TokenNumber is invalid,
+ the results are unpredictable.
+
+ @param[in] Guid The token space for the token number.
+ @param[in] TokenNumber The PCD token number.
+
+ @return The pointer to the buffer to be retrieved.
+
+**/
+typedef
+VOID *
+(EFIAPI *PCD_PPI_GET_EX_POINTER)(
+ IN CONST EFI_GUID *Guid,
+ IN UINTN TokenNumber
+ );
+
+/**
+ Retrieves an Boolean value for a given PCD token and token space.
+
+ Retrieves the Boolean value of a particular PCD token.
+ If the TokenNumber is invalid or the token space
+ specified by Guid does not exist, the results are
+ unpredictable.
+
+ @param[in] Guid The token space for the token number.
+ @param[in] TokenNumber The PCD token number.
+
+ @return The size Boolean value for the PCD token.
+
+**/
+typedef
+BOOLEAN
+(EFIAPI *PCD_PPI_GET_EX_BOOLEAN)(
+ IN CONST EFI_GUID *Guid,
+ IN UINTN TokenNumber
+ );
+
+/**
+ Retrieves the size of the value for a given PCD token and token space.
+
+ Retrieves the current size of a particular PCD token.
+ If the TokenNumber is invalid, the results are unpredictable.
+
+ @param[in] Guid The token space for the token number.
+ @param[in] TokenNumber The PCD token number.
+
+ @return The size of the value for the PCD token.
+
+**/
+typedef
+UINTN
+(EFIAPI *PCD_PPI_GET_EX_SIZE)(
+ IN CONST EFI_GUID *Guid,
+ IN UINTN TokenNumber
+ );
+
+/**
+ Sets an 8-bit value for a given PCD token.
+
+ When the PCD service sets a value, it will check to ensure that the
+ size of the value being set is compatible with the Token's existing definition.
+ If it is not, an error will be returned.
+
+ @param[in] TokenNumber The PCD token number.
+ @param[in] Value The value to set for the PCD token.
+
+ @retval EFI_SUCCESS The procedure returned successfully.
+ @retval EFI_INVALID_PARAMETER The PCD service determined that the size of the data
+ being set was incompatible with a call to this function.
+ Use GetSize() to retrieve the size of the target data.
+ @retval EFI_NOT_FOUND The PCD service could not find the requested token number.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *PCD_PPI_SET8)(
+ IN UINTN TokenNumber,
+ IN UINT8 Value
+ );
+
+/**
+ Sets a 16-bit value for a given PCD token.
+
+ When the PCD service sets a value, it will check to ensure that the
+ size of the value being set is compatible with the Token's existing definition.
+ If it is not, an error will be returned.
+
+ @param[in] TokenNumber The PCD token number.
+ @param[in] Value The value to set for the PCD token.
+
+ @retval EFI_SUCCESS The procedure returned successfully.
+ @retval EFI_INVALID_PARAMETER The PCD service determined that the size of the data
+ being set was incompatible with a call to this function.
+ Use GetSize() to retrieve the size of the target data.
+ @retval EFI_NOT_FOUND The PCD service could not find the requested token number.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *PCD_PPI_SET16)(
+ IN UINTN TokenNumber,
+ IN UINT16 Value
+ );
+
+/**
+ Sets a 32-bit value for a given PCD token.
+
+ When the PCD service sets a value, it will check to ensure that the
+ size of the value being set is compatible with the Token's existing definition.
+ If it is not, an error will be returned.
+
+ @param[in] TokenNumber The PCD token number.
+ @param[in] Value The value to set for the PCD token.
+
+ @retval EFI_SUCCESS The procedure returned successfully.
+ @retval EFI_INVALID_PARAMETER The PCD service determined that the size of the data
+ being set was incompatible with a call to this function.
+ Use GetSize() to retrieve the size of the target data.
+ @retval EFI_NOT_FOUND The PCD service could not find the requested token number.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *PCD_PPI_SET32)(
+ IN UINTN TokenNumber,
+ IN UINT32 Value
+ );
+
+/**
+ Sets a 64-bit value for a given PCD token.
+
+ When the PCD service sets a value, it will check to ensure that the
+ size of the value being set is compatible with the Token's existing definition.
+ If it is not, an error will be returned.
+
+ @param[in] TokenNumber The PCD token number.
+ @param[in] Value The value to set for the PCD token.
+
+ @retval EFI_SUCCESS The procedure returned successfully.
+ @retval EFI_INVALID_PARAMETER The PCD service determined that the size of the data
+ being set was incompatible with a call to this function.
+ Use GetSize() to retrieve the size of the target data.
+ @retval EFI_NOT_FOUND The PCD service could not find the requested token number.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *PCD_PPI_SET64)(
+ IN UINTN TokenNumber,
+ IN UINT64 Value
+ );
+
+/**
+ Sets a value of a specified size for a given PCD token.
+
+ When the PCD service sets a value, it will check to ensure that the
+ size of the value being set is compatible with the Token's existing definition.
+ If it is not, an error will be returned.
+
+ @param[in] TokenNumber The PCD token number.
+ @param[in, out] SizeOfValue A pointer to the length of the value being set for the PCD token.
+ On input, if the SizeOfValue is greater than the maximum size supported
+ for this TokenNumber then the output value of SizeOfValue will reflect
+ the maximum size supported for this TokenNumber.
+ @param[in] Buffer The buffer to set for the PCD token.
+
+ @retval EFI_SUCCESS The procedure returned successfully.
+ @retval EFI_INVALID_PARAMETER The PCD service determined that the size of the data
+ being set was incompatible with a call to this function.
+ Use GetSize() to retrieve the size of the target data.
+ @retval EFI_NOT_FOUND The PCD service could not find the requested token number.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *PCD_PPI_SET_POINTER)(
+ IN UINTN TokenNumber,
+ IN OUT UINTN *SizeOfValue,
+ IN VOID *Buffer
+ );
+
+/**
+ Sets an Boolean value for a given PCD token.
+
+ When the PCD service sets a value, it will check to ensure that the
+ size of the value being set is compatible with the Token's existing definition.
+ If it is not, an error will be returned.
+
+ @param[in] TokenNumber The PCD token number.
+ @param[in] Value The value to set for the PCD token.
+
+ @retval EFI_SUCCESS The procedure returned successfully.
+ @retval EFI_INVALID_PARAMETER The PCD service determined that the size of the data
+ being set was incompatible with a call to this function.
+ Use GetSize() to retrieve the size of the target data.
+ @retval EFI_NOT_FOUND The PCD service could not find the requested token number.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *PCD_PPI_SET_BOOLEAN)(
+ IN UINTN TokenNumber,
+ IN BOOLEAN Value
+ );
+
+/**
+ Sets an 8-bit value for a given PCD token.
+
+ When the PCD service sets a value, it will check to ensure that the
+ size of the value being set is compatible with the Token's existing definition.
+ If it is not, an error will be returned.
+
+ @param[in] Guid The 128-bit unique value that designates the namespace from which to extract the value.
+ @param[in] TokenNumber The PCD token number.
+ @param[in] Value The value to set for the PCD token.
+
+ @retval EFI_SUCCESS The procedure returned successfully.
+ @retval EFI_INVALID_PARAMETER The PCD service determined that the size of the data
+ being set was incompatible with a call to this function.
+ Use GetSize() to retrieve the size of the target data.
+ @retval EFI_NOT_FOUND The PCD service could not find the requested token number.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *PCD_PPI_SET_EX_8)(
+ IN CONST EFI_GUID *Guid,
+ IN UINTN TokenNumber,
+ IN UINT8 Value
+ );
+
+/**
+ Sets a 16-bit value for a given PCD token.
+
+ When the PCD service sets a value, it will check to ensure that the
+ size of the value being set is compatible with the Token's existing definition.
+ If it is not, an error will be returned.
+
+ @param[in] Guid The 128-bit unique value that designates the namespace from which to extract the value.
+ @param[in] TokenNumber The PCD token number.
+ @param[in] Value The value to set for the PCD token.
+
+ @retval EFI_SUCCESS The procedure returned successfully.
+ @retval EFI_INVALID_PARAMETER The PCD service determined that the size of the data
+ being set was incompatible with a call to this function.
+ Use GetSize() to retrieve the size of the target data.
+ @retval EFI_NOT_FOUND The PCD service could not find the requested token number.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *PCD_PPI_SET_EX_16)(
+ IN CONST EFI_GUID *Guid,
+ IN UINTN TokenNumber,
+ IN UINT16 Value
+ );
+
+/**
+ Sets a 32-bit value for a given PCD token.
+
+ When the PCD service sets a value, it will check to ensure that the
+ size of the value being set is compatible with the Token's existing definition.
+ If it is not, an error will be returned.
+
+ @param[in] Guid The 128-bit unique value that designates the namespace from which to extract the value.
+ @param[in] TokenNumber The PCD token number.
+ @param[in] Value The value to set for the PCD token.
+
+ @retval EFI_SUCCESS The procedure returned successfully.
+ @retval EFI_INVALID_PARAMETER The PCD service determined that the size of the data
+ being set was incompatible with a call to this function.
+ Use GetSize() to retrieve the size of the target data.
+ @retval EFI_NOT_FOUND The PCD service could not find the requested token number.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *PCD_PPI_SET_EX_32)(
+ IN CONST EFI_GUID *Guid,
+ IN UINTN TokenNumber,
+ IN UINT32 Value
+ );
+
+/**
+ Sets a 64-bit value for a given PCD token.
+
+ When the PCD service sets a value, it will check to ensure that the
+ size of the value being set is compatible with the Token's existing definition.
+ If it is not, an error will be returned.
+
+ @param[in] Guid The 128-bit unique value that designates the namespace from which to extract the value.
+ @param[in] TokenNumber The PCD token number.
+ @param[in] Value The value to set for the PCD token.
+
+ @retval EFI_SUCCESS The procedure returned successfully.
+ @retval EFI_INVALID_PARAMETER The PCD service determined that the size of the data
+ being set was incompatible with a call to this function.
+ Use GetSize() to retrieve the size of the target data.
+ @retval EFI_NOT_FOUND The PCD service could not find the requested token number.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *PCD_PPI_SET_EX_64)(
+ IN CONST EFI_GUID *Guid,
+ IN UINTN TokenNumber,
+ IN UINT64 Value
+ );
+
+/**
+ Sets a value of a specified size for a given PCD token.
+
+ When the PCD service sets a value, it will check to ensure that the
+ size of the value being set is compatible with the Token's existing definition.
+ If it is not, an error will be returned.
+
+ @param[in] Guid The 128-bit unique value that designates the namespace from which to extract the value.
+ @param[in] TokenNumber The PCD token number.
+ @param[in, out] SizeOfValue A pointer to the length of the value being set for the PCD token.
+ On input, if the SizeOfValue is greater than the maximum size supported
+ for this TokenNumber then the output value of SizeOfValue will reflect
+ the maximum size supported for this TokenNumber.
+ @param[in] Buffer The buffer to set for the PCD token.
+
+ @retval EFI_SUCCESS The procedure returned successfully.
+ @retval EFI_INVALID_PARAMETER The PCD service determined that the size of the data
+ being set was incompatible with a call to this function.
+ Use GetSize() to retrieve the size of the target data.
+ @retval EFI_NOT_FOUND The PCD service could not find the requested token number.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *PCD_PPI_SET_EX_POINTER)(
+ IN CONST EFI_GUID *Guid,
+ IN UINTN TokenNumber,
+ IN OUT UINTN *SizeOfValue,
+ IN VOID *Buffer
+ );
+
+/**
+ Sets an Boolean value for a given PCD token.
+
+ When the PCD service sets a value, it will check to ensure that the
+ size of the value being set is compatible with the Token's existing definition.
+ If it is not, an error will be returned.
+
+ @param[in] Guid The 128-bit unique value that designates the namespace from which to extract the value.
+ @param[in] TokenNumber The PCD token number.
+ @param[in] Value The value to set for the PCD token.
+
+ @retval EFI_SUCCESS The procedure returned successfully.
+ @retval EFI_INVALID_PARAMETER The PCD service determined that the size of the data
+ being set was incompatible with a call to this function.
+ Use GetSize() to retrieve the size of the target data.
+ @retval EFI_NOT_FOUND The PCD service could not find the requested token number.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *PCD_PPI_SET_EX_BOOLEAN)(
+ IN CONST EFI_GUID *Guid,
+ IN UINTN TokenNumber,
+ IN BOOLEAN Value
+ );
+
+/**
+ Callback on SET function prototype definition.
+
+ This notification function serves two purposes. Firstly, it notifies the module
+ which did the registration that the value of this PCD token has been set. Secondly,
+ it provides a mechanism for the module which did the registration to intercept the set
+ operation and override the value been set if necessary. After the invocation of the
+ callback function, TokenData will be used by PCD service PEIM to modify the internal data
+ in PCD database.
+
+ @param[in] CallBackGuid The PCD token GUID being set.
+ @param[in] CallBackToken The PCD token number being set.
+ @param[in, out] TokenData A pointer to the token data being set.
+ @param[in] TokenDataSize The size, in bytes, of the data being set.
+
+ @retval VOID
+
+**/
+typedef
+VOID
+(EFIAPI *PCD_PPI_CALLBACK)(
+ IN CONST EFI_GUID *CallBackGuid OPTIONAL,
+ IN UINTN CallBackToken,
+ IN OUT VOID *TokenData,
+ IN UINTN TokenDataSize
+ );
+
+/**
+ Specifies a function to be called anytime the value of a designated token is changed.
+
+ @param[in] TokenNumber The PCD token number.
+ @param[in] Guid The 128-bit unique value that designates the namespace from which to extract the value.
+ @param[in] CallBackFunction The function prototype called when the value associated with the CallBackToken is set.
+
+ @retval EFI_SUCCESS The PCD service has successfully established a call event
+ for the CallBackToken requested.
+ @retval EFI_NOT_FOUND The PCD service could not find the referenced token number.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *PCD_PPI_CALLBACK_ONSET)(
+ IN CONST EFI_GUID *Guid OPTIONAL,
+ IN UINTN TokenNumber,
+ IN PCD_PPI_CALLBACK CallBackFunction
+ );
+
+/**
+ Cancels a previously set callback function for a particular PCD token number.
+
+ @param[in] TokenNumber The PCD token number.
+ @param[in] Guid The 128-bit unique value that designates the namespace from which to extract the value.
+ @param[in] CallBackFunction The function prototype called when the value associated with the CallBackToken is set.
+
+ @retval EFI_SUCCESS The PCD service has successfully established a call event
+ for the CallBackToken requested.
+ @retval EFI_NOT_FOUND The PCD service could not find the referenced token number.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *PCD_PPI_CANCEL_CALLBACK)(
+ IN CONST EFI_GUID *Guid OPTIONAL,
+ IN UINTN TokenNumber,
+ IN PCD_PPI_CALLBACK CallBackFunction
+ );
+
+/**
+ Retrieves the next valid token number in a given namespace.
+
+ This is useful since the PCD infrastructure contains a sparse list of token numbers,
+ and one cannot a priori know what token numbers are valid in the database.
+
+ If TokenNumber is 0 and Guid is not NULL, then the first token from the token space specified by Guid is returned.
+ If TokenNumber is not 0 and Guid is not NULL, then the next token in the token space specified by Guid is returned.
+ If TokenNumber is 0 and Guid is NULL, then the first token in the default token space is returned.
+ If TokenNumber is not 0 and Guid is NULL, then the next token in the default token space is returned.
+ The token numbers in the default token space may not be related to token numbers in token spaces that are named by Guid.
+ If the next token number can be retrieved, then it is returned in TokenNumber, and EFI_SUCCESS is returned.
+ If TokenNumber represents the last token number in the token space specified by Guid, then EFI_NOT_FOUND is returned.
+ If TokenNumber is not present in the token space specified by Guid, then EFI_NOT_FOUND is returned.
+
+
+ @param[in] Guid The 128-bit unique value that designates the namespace from which to extract the value.
+ This is an optional parameter that may be NULL. If this parameter is NULL, then a request
+ is being made to retrieve tokens from the default token space.
+ @param[in, out] TokenNumber A pointer to the PCD token number to use to find the subsequent token number.
+
+ @retval EFI_SUCCESS The PCD service has retrieved the next valid token number.
+ @retval EFI_NOT_FOUND The PCD service could not find data from the requested token number.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *PCD_PPI_GET_NEXT_TOKEN)(
+ IN CONST EFI_GUID *Guid OPTIONAL,
+ IN OUT UINTN *TokenNumber
+ );
+
+/**
+ Retrieves the next valid PCD token namespace for a given namespace.
+
+ Gets the next valid token namespace for a given namespace. This is useful to traverse the valid
+ token namespaces on a platform.
+
+ @param[in, out] Guid An indirect pointer to EFI_GUID. On input it designates a known token
+ namespace from which the search will start. On output, it designates the next valid
+ token namespace on the platform. If *Guid is NULL, then the GUID of the first token
+ space of the current platform is returned. If the search cannot locate the next valid
+ token namespace, an error is returned and the value of *Guid is undefined.
+
+ @retval EFI_SUCCESS The PCD service retrieved the value requested.
+ @retval EFI_NOT_FOUND The PCD service could not find the next valid token namespace.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *PCD_PPI_GET_NEXT_TOKENSPACE)(
+ IN OUT CONST EFI_GUID **Guid
+ );
+
+///
+/// This service abstracts the ability to set/get Platform Configuration Database (PCD).
+///
+typedef struct {
+ PCD_PPI_SET_SKU SetSku;
+
+ PCD_PPI_GET8 Get8;
+ PCD_PPI_GET16 Get16;
+ PCD_PPI_GET32 Get32;
+ PCD_PPI_GET64 Get64;
+ PCD_PPI_GET_POINTER GetPtr;
+ PCD_PPI_GET_BOOLEAN GetBool;
+ PCD_PPI_GET_SIZE GetSize;
+
+ PCD_PPI_GET_EX_8 Get8Ex;
+ PCD_PPI_GET_EX_16 Get16Ex;
+ PCD_PPI_GET_EX_32 Get32Ex;
+ PCD_PPI_GET_EX_64 Get64Ex;
+ PCD_PPI_GET_EX_POINTER GetPtrEx;
+ PCD_PPI_GET_EX_BOOLEAN GetBoolEx;
+ PCD_PPI_GET_EX_SIZE GetSizeEx;
+
+ PCD_PPI_SET8 Set8;
+ PCD_PPI_SET16 Set16;
+ PCD_PPI_SET32 Set32;
+ PCD_PPI_SET64 Set64;
+ PCD_PPI_SET_POINTER SetPtr;
+ PCD_PPI_SET_BOOLEAN SetBool;
+
+ PCD_PPI_SET_EX_8 Set8Ex;
+ PCD_PPI_SET_EX_16 Set16Ex;
+ PCD_PPI_SET_EX_32 Set32Ex;
+ PCD_PPI_SET_EX_64 Set64Ex;
+ PCD_PPI_SET_EX_POINTER SetPtrEx;
+ PCD_PPI_SET_EX_BOOLEAN SetBoolEx;
+
+ PCD_PPI_CALLBACK_ONSET CallbackOnSet;
+ PCD_PPI_CANCEL_CALLBACK CancelCallback;
+ PCD_PPI_GET_NEXT_TOKEN GetNextToken;
+ PCD_PPI_GET_NEXT_TOKENSPACE GetNextTokenSpace;
+} PCD_PPI;
+
+extern EFI_GUID gPcdPpiGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Ppi/PcdInfo.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Ppi/PcdInfo.h
new file mode 100644
index 0000000000..17b04b0ccc
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Ppi/PcdInfo.h
@@ -0,0 +1,98 @@
+/** @file
+ Native Platform Configuration Database (PCD) INFO PPI
+
+ The PPI that provides additional information about items that reside in the PCD database.
+
+ Different with the EFI_GET_PCD_INFO_PPI defined in PI 1.2.1 specification,
+ the native PCD INFO PPI provide interfaces for dynamic and dynamic-ex type PCD.
+ The interfaces for dynamic type PCD do not require the token space guid as parameter,
+ but interfaces for dynamic-ex type PCD require token space guid as parameter.
+
+ Copyright (c) 2013 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __PCD_INFO_PPI_H__
+#define __PCD_INFO_PPI_H__
+
+extern EFI_GUID gGetPcdInfoPpiGuid;
+
+#define GET_PCD_INFO_PPI_GUID \
+ { 0x4d8b155b, 0xc059, 0x4c8f, { 0x89, 0x26, 0x6, 0xfd, 0x43, 0x31, 0xdb, 0x8a } }
+
+///
+/// The forward declaration for GET_PCD_INFO_PPI.
+///
+typedef struct _GET_PCD_INFO_PPI GET_PCD_INFO_PPI;
+
+/**
+ Retrieve additional information associated with a PCD token in the default token space.
+
+ This includes information such as the type of value the TokenNumber is associated with as well as possible
+ human readable name that is associated with the token.
+
+ @param[in] TokenNumber The PCD token number.
+ @param[out] PcdInfo The returned information associated with the requested TokenNumber.
+
+ @retval EFI_SUCCESS The PCD information was returned successfully
+ @retval EFI_NOT_FOUND The PCD service could not find the requested token number.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *GET_PCD_INFO_PPI_GET_INFO)(
+ IN UINTN TokenNumber,
+ OUT EFI_PCD_INFO *PcdInfo
+ );
+
+/**
+ Retrieve additional information associated with a PCD token.
+
+ This includes information such as the type of value the TokenNumber is associated with as well as possible
+ human readable name that is associated with the token.
+
+ @param[in] Guid The 128-bit unique value that designates the namespace from which to extract the value.
+ @param[in] TokenNumber The PCD token number.
+ @param[out] PcdInfo The returned information associated with the requested TokenNumber.
+
+ @retval EFI_SUCCESS The PCD information was returned successfully
+ @retval EFI_NOT_FOUND The PCD service could not find the requested token number.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *GET_PCD_INFO_PPI_GET_INFO_EX)(
+ IN CONST EFI_GUID *Guid,
+ IN UINTN TokenNumber,
+ OUT EFI_PCD_INFO *PcdInfo
+ );
+
+/**
+ Retrieve the currently set SKU Id.
+
+ @return The currently set SKU Id. If the platform has not set at a SKU Id, then the
+ default SKU Id value of 0 is returned. If the platform has set a SKU Id, then the currently set SKU
+ Id is returned.
+**/
+typedef
+UINTN
+(EFIAPI *GET_PCD_INFO_PPI_GET_SKU)(
+ VOID
+ );
+
+///
+/// This is the PCD service to use when querying for some additional data that can be contained in the
+/// PCD database.
+///
+struct _GET_PCD_INFO_PPI {
+ ///
+ /// Retrieve additional information associated with a PCD.
+ ///
+ GET_PCD_INFO_PPI_GET_INFO GetInfo;
+ GET_PCD_INFO_PPI_GET_INFO_EX GetInfoEx;
+ ///
+ /// Retrieve the currently set SKU Id.
+ ///
+ GET_PCD_INFO_PPI_GET_SKU GetSku;
+};
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Ppi/PciCfg2.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Ppi/PciCfg2.h
new file mode 100644
index 0000000000..f5812c3484
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Ppi/PciCfg2.h
@@ -0,0 +1,176 @@
+/** @file
+ This file declares PciCfg2 PPI.
+
+ This ppi Provides platform or chipset-specific access to
+ the PCI configuration space for a specific PCI segment.
+
+ Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Revision Reference:
+ This PPI is introduced in PI Version 1.0.
+
+**/
+
+#ifndef __PEI_PCI_CFG2_H__
+#define __PEI_PCI_CFG2_H__
+
+#include
+
+#define EFI_PEI_PCI_CFG2_PPI_GUID \
+ { 0x57a449a, 0x1fdc, 0x4c06, { 0xbf, 0xc9, 0xf5, 0x3f, 0x6a, 0x99, 0xbb, 0x92 } }
+
+typedef struct _EFI_PEI_PCI_CFG2_PPI EFI_PEI_PCI_CFG2_PPI;
+
+#define EFI_PEI_PCI_CFG_ADDRESS(bus, dev, func, reg) \
+ (UINT64) ( \
+ (((UINTN) bus) << 24) | \
+ (((UINTN) dev) << 16) | \
+ (((UINTN) func) << 8) | \
+ (((UINTN) (reg)) < 256 ? ((UINTN) (reg)) : (UINT64) (LShiftU64 ((UINT64) (reg), 32))))
+
+///
+/// EFI_PEI_PCI_CFG_PPI_WIDTH
+///
+typedef enum {
+ ///
+ /// 8-bit access
+ ///
+ EfiPeiPciCfgWidthUint8 = 0,
+ ///
+ /// 16-bit access
+ ///
+ EfiPeiPciCfgWidthUint16 = 1,
+ ///
+ /// 32-bit access
+ ///
+ EfiPeiPciCfgWidthUint32 = 2,
+ ///
+ /// 64-bit access
+ ///
+ EfiPeiPciCfgWidthUint64 = 3,
+ EfiPeiPciCfgWidthMaximum
+} EFI_PEI_PCI_CFG_PPI_WIDTH;
+
+///
+/// EFI_PEI_PCI_CFG_PPI_PCI_ADDRESS
+///
+typedef struct {
+ ///
+ /// 8-bit register offset within the PCI configuration space for a given device's function
+ /// space.
+ ///
+ UINT8 Register;
+ ///
+ /// Only the 3 least-significant bits are used to encode one of 8 possible functions within a
+ /// given device.
+ ///
+ UINT8 Function;
+ ///
+ /// Only the 5 least-significant bits are used to encode one of 32 possible devices.
+ ///
+ UINT8 Device;
+ ///
+ /// 8-bit value to encode between 0 and 255 buses.
+ ///
+ UINT8 Bus;
+ ///
+ /// Register number in PCI configuration space. If this field is zero, then Register is used
+ /// for the register number. If this field is non-zero, then Register is ignored and this field
+ /// is used for the register number.
+ ///
+ UINT32 ExtendedRegister;
+} EFI_PEI_PCI_CFG_PPI_PCI_ADDRESS;
+
+/**
+ Reads from or write to a given location in the PCI configuration space.
+
+ @param PeiServices An indirect pointer to the PEI Services Table published by the PEI Foundation.
+
+ @param This Pointer to local data for the interface.
+
+ @param Width The width of the access. Enumerated in bytes.
+ See EFI_PEI_PCI_CFG_PPI_WIDTH above.
+
+ @param Address The physical address of the access. The format of
+ the address is described by EFI_PEI_PCI_CFG_PPI_PCI_ADDRESS.
+
+ @param Buffer A pointer to the buffer of data..
+
+
+ @retval EFI_SUCCESS The function completed successfully.
+
+ @retval EFI_DEVICE_ERROR There was a problem with the transaction.
+
+ @retval EFI_DEVICE_NOT_READY The device is not capable of supporting the operation at this
+ time.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_PEI_PCI_CFG2_PPI_IO)(
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN CONST EFI_PEI_PCI_CFG2_PPI *This,
+ IN EFI_PEI_PCI_CFG_PPI_WIDTH Width,
+ IN UINT64 Address,
+ IN OUT VOID *Buffer
+ );
+
+/**
+ Performs a read-modify-write operation on the contents
+ from a given location in the PCI configuration space.
+
+ @param PeiServices An indirect pointer to the PEI Services Table
+ published by the PEI Foundation.
+
+ @param This Pointer to local data for the interface.
+
+ @param Width The width of the access. Enumerated in bytes. Type
+ EFI_PEI_PCI_CFG_PPI_WIDTH is defined in Read().
+
+ @param Address The physical address of the access.
+
+ @param SetBits Points to value to bitwise-OR with the read configuration value.
+
+ The size of the value is determined by Width.
+
+ @param ClearBits Points to the value to negate and bitwise-AND with the read configuration value.
+ The size of the value is determined by Width.
+
+
+ @retval EFI_SUCCESS The function completed successfully.
+
+ @retval EFI_DEVICE_ERROR There was a problem with the transaction.
+
+ @retval EFI_DEVICE_NOT_READY The device is not capable of supporting
+ the operation at this time.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_PEI_PCI_CFG2_PPI_RW)(
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN CONST EFI_PEI_PCI_CFG2_PPI *This,
+ IN EFI_PEI_PCI_CFG_PPI_WIDTH Width,
+ IN UINT64 Address,
+ IN VOID *SetBits,
+ IN VOID *ClearBits
+ );
+
+///
+/// The EFI_PEI_PCI_CFG_PPI interfaces are used to abstract accesses to PCI
+/// controllers behind a PCI root bridge controller.
+///
+struct _EFI_PEI_PCI_CFG2_PPI {
+ EFI_PEI_PCI_CFG2_PPI_IO Read;
+ EFI_PEI_PCI_CFG2_PPI_IO Write;
+ EFI_PEI_PCI_CFG2_PPI_RW Modify;
+ ///
+ /// The PCI bus segment which the specified functions will access.
+ ///
+ UINT16 Segment;
+};
+
+extern EFI_GUID gEfiPciCfg2PpiGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Ppi/PeiCoreFvLocation.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Ppi/PeiCoreFvLocation.h
new file mode 100644
index 0000000000..78861256db
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Ppi/PeiCoreFvLocation.h
@@ -0,0 +1,41 @@
+/** @file
+ Header file for Pei Core FV Location PPI.
+
+ This PPI contains a pointer to the firmware volume which contains the PEI Foundation.
+ If the PEI Foundation does not reside in the BFV, then SEC must pass this PPI as a part
+ of the PPI list provided to the PEI Foundation Entry Point, otherwise the PEI Foundation
+ shall assume that it resides within the BFV.
+
+ Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Revision Reference:
+ This PPI is defined in UEFI Platform Initialization Specification 1.7 Volume 1:
+ Standards
+
+**/
+
+#ifndef _EFI_PEI_CORE_FV_LOCATION_H_
+#define _EFI_PEI_CORE_FV_LOCATION_H_
+
+///
+/// Global ID for EFI_PEI_CORE_FV_LOCATION_PPI
+///
+#define EFI_PEI_CORE_FV_LOCATION_GUID \
+ { \
+ 0x52888eae, 0x5b10, 0x47d0, {0xa8, 0x7f, 0xb8, 0x22, 0xab, 0xa0, 0xca, 0xf4 } \
+ }
+
+///
+/// This PPI provides location of EFI PeiCoreFv.
+///
+typedef struct {
+ ///
+ /// Pointer to the first byte of the firmware volume which contains the PEI Foundation.
+ ///
+ VOID *PeiCoreFvLocation;
+} EFI_PEI_CORE_FV_LOCATION_PPI;
+
+extern EFI_GUID gEfiPeiCoreFvLocationPpiGuid;
+
+#endif // _EFI_PEI_CORE_FV_LOCATION_H_
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Ppi/PiPcd.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Ppi/PiPcd.h
new file mode 100644
index 0000000000..a593feaf0c
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Ppi/PiPcd.h
@@ -0,0 +1,426 @@
+/** @file
+ Platform Configuration Database (PCD) PPI defined in PI 1.2 Vol3
+
+ A platform database that contains a variety of current platform settings or
+ directives that can be accessed by a driver or application.
+ PI PCD ppi only provide the accessing interfaces for Dynamic-Ex type PCD.
+
+ This is the base PCD service API that provides an abstraction for accessing configuration content in
+ the platform. It a seamless mechanism for extracting information regardless of where the
+ information is stored (such as in Read-only data, or an EFI Variable).
+ This protocol allows access to data through size-granular APIs and provides a mechanism for a
+ firmware component to monitor specific settings and be alerted when a setting is changed.
+
+ Copyright (c) 2009 - 2013, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Revision Reference:
+ PI Version 1.2 Vol 3.
+**/
+
+#ifndef __PI_PCD_PPI_H__
+#define __PI_PCD_PPI_H__
+
+extern EFI_GUID gEfiPeiPcdPpiGuid;
+
+#define EFI_PEI_PCD_PPI_GUID \
+ { 0x1f34d25, 0x4de2, 0x23ad, { 0x3f, 0xf3, 0x36, 0x35, 0x3f, 0xf3, 0x23, 0xf1 } }
+
+#define EFI_PCD_INVALID_TOKEN_NUMBER ((UINTN) 0)
+
+/**
+ SetSku() sets the SKU Id to be used for subsequent calls to set or get PCD values. SetSku() is
+ normally called only once by the system.
+ For each item (token), the database can hold a single value that applies to all SKUs, or multiple
+ values, where each value is associated with a specific SKU Id. Items with multiple, SKU-specific
+ values are called SKU enabled.
+ The SKU Id of zero is reserved as a default. The valid SkuId range is 1 to 255. For tokens that are
+ not SKU enabled, the system ignores any set SKU Id and works with the single value for that token.
+ For SKU-enabled tokens, the system will use the SKU Id set by the last call to SetSku(). If no
+ SKU Id is set or the currently set SKU Id isn't valid for the specified token, the system uses the
+ default SKU Id. If the system attempts to use the default SKU Id and no value has been set for that
+ Id, the results are unpredictable.
+
+ @param[in] SkuId The SKU value to set.
+**/
+typedef
+VOID
+(EFIAPI *EFI_PEI_PCD_PPI_SET_SKU)(
+ IN UINTN SkuId
+ );
+
+/**
+ Retrieves the current byte-sized value for a PCD token number. If the TokenNumber is invalid,
+ the results are unpredictable.
+
+ @param[in] Guid The 128-bit unique value that designates which namespace to extract the value from.
+ @param[in] TokenNumber The PCD token number.
+
+ @return 8-bit value for a given PCD token.
+**/
+typedef
+UINT8
+(EFIAPI *EFI_PEI_PCD_PPI_GET_8)(
+ IN CONST EFI_GUID *Guid,
+ IN UINTN TokenNumber
+ );
+
+/**
+ Retrieves the current word-sized value for a PCD token number. If the TokenNumber is invalid,
+ the results are unpredictable.
+
+ @param[in] Guid The 128-bit unique value that designates which namespace to extract the value from.
+ @param[in] TokenNumber The PCD token number.
+
+ @return 16-bit value for a given PCD token.
+**/
+typedef
+UINT16
+(EFIAPI *EFI_PEI_PCD_PPI_GET_16)(
+ IN CONST EFI_GUID *Guid,
+ IN UINTN TokenNumber
+ );
+
+/**
+ Retrieves the current 32-bit value for a PCD token number. If the TokenNumber is invalid, the
+ results are unpredictable.
+
+ @param[in] Guid The 128-bit unique value that designates which namespace to extract the value from.
+ @param[in] TokenNumber The PCD token number.
+
+ @return 32-bit value for a given PCD token.
+**/
+typedef
+UINT32
+(EFIAPI *EFI_PEI_PCD_PPI_GET_32)(
+ IN CONST EFI_GUID *Guid,
+ IN UINTN TokenNumber
+ );
+
+/**
+ Retrieves the current 64-bit value for a PCD token number. If the TokenNumber is invalid, the
+ results are unpredictable.
+
+ @param[in] Guid The 128-bit unique value that designates which namespace to extract the value from.
+ @param[in] TokenNumber The PCD token number.
+
+ @return 64-bit value for a given PCD token.
+**/
+typedef
+UINT64
+(EFIAPI *EFI_PEI_PCD_PPI_GET_64)(
+ IN CONST EFI_GUID *Guid,
+ IN UINTN TokenNumber
+ );
+
+/**
+ Retrieves the current pointer to the value for a PCD token number. There should not be any
+ alignment assumptions about the pointer that is returned by this function call. If the TokenNumber
+ is invalid, the results are unpredictable.
+
+ @param[in] Guid The 128-bit unique value that designates which namespace to extract the value from.
+ @param[in] TokenNumber The PCD token number.
+**/
+typedef
+VOID *
+(EFIAPI *EFI_PEI_PCD_PPI_GET_POINTER)(
+ IN CONST EFI_GUID *Guid,
+ IN UINTN TokenNumber
+ );
+
+/**
+ Retrieves the current Boolean-sized value for a PCD token number. If the TokenNumber is
+ invalid, the results are unpredictable.
+
+ @param[in] Guid The 128-bit unique value that designates which namespace to extract the value from.
+ @param[in] TokenNumber The PCD token number.
+
+ @return Boolean value for a given PCD token.
+**/
+typedef
+BOOLEAN
+(EFIAPI *EFI_PEI_PCD_PPI_GET_BOOLEAN)(
+ IN CONST EFI_GUID *Guid,
+ IN UINTN TokenNumber
+ );
+
+/**
+ Retrieves the current size of a particular PCD token. If the TokenNumber is invalid, the results are
+ unpredictable.
+
+ @param[in] Guid The 128-bit unique value that designates which namespace to extract the value from.
+ @param[in] TokenNumber The PCD token number.
+
+ @return the size of the value for a given PCD token.
+**/
+typedef
+UINTN
+(EFIAPI *EFI_PEI_PCD_PPI_GET_SIZE)(
+ IN CONST EFI_GUID *Guid,
+ IN UINTN TokenNumber
+ );
+
+/**
+ Sets an 8-bit value for a given PCD token.
+
+ When the PCD service sets a value, it will check to ensure that the size of the value being set is
+ compatible with the Token's existing definition. If it is not, an error will be returned.
+
+ @param[in] Guid The 128-bit unique value that designates which namespace to extract the value from.
+ @param[in] TokenNumber The PCD token number.
+ @param[in] Value The value to set for the PCD token.
+
+ @retval EFI_SUCCESS The PCD service has set the value requested
+ @retval EFI_INVALID_PARAMETER The PCD service determined that the size of the data being set was
+ incompatible with a call to this function. Use GetSizeEx() to
+ retrieve the size of the target data.
+ @retval EFI_NOT_FOUND The PCD service could not find the requested token number.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_PEI_PCD_PPI_SET_8)(
+ IN CONST EFI_GUID *Guid,
+ IN UINTN TokenNumber,
+ IN UINT8 Value
+ );
+
+/**
+ Sets an 16-bit value for a given PCD token.
+
+ When the PCD service sets a value, it will check to ensure that the size of the value being set is
+ compatible with the Token's existing definition. If it is not, an error will be returned.
+
+ @param[in] Guid The 128-bit unique value that designates which namespace to extract the value from.
+ @param[in] TokenNumber The PCD token number.
+ @param[in] Value The value to set for the PCD token.
+
+ @retval EFI_SUCCESS The PCD service has set the value requested
+ @retval EFI_INVALID_PARAMETER The PCD service determined that the size of the data being set was
+ incompatible with a call to this function. Use GetSizeEx() to
+ retrieve the size of the target data.
+ @retval EFI_NOT_FOUND The PCD service could not find the requested token number.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_PEI_PCD_PPI_SET_16)(
+ IN CONST EFI_GUID *Guid,
+ IN UINTN TokenNumber,
+ IN UINT16 Value
+ );
+
+/**
+ Sets an 32-bit value for a given PCD token.
+
+ When the PCD service sets a value, it will check to ensure that the size of the value being set is
+ compatible with the Token's existing definition. If it is not, an error will be returned.
+
+ @param[in] Guid The 128-bit unique value that designates which namespace to extract the value from.
+ @param[in] TokenNumber The PCD token number.
+ @param[in] Value The value to set for the PCD token.
+
+ @retval EFI_SUCCESS The PCD service has set the value requested
+ @retval EFI_INVALID_PARAMETER The PCD service determined that the size of the data being set was
+ incompatible with a call to this function. Use GetSizeEx() to
+ retrieve the size of the target data.
+ @retval EFI_NOT_FOUND The PCD service could not find the requested token number.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_PEI_PCD_PPI_SET_32)(
+ IN CONST EFI_GUID *Guid,
+ IN UINTN TokenNumber,
+ IN UINT32 Value
+ );
+
+/**
+ Sets an 64-bit value for a given PCD token.
+
+ When the PCD service sets a value, it will check to ensure that the size of the value being set is
+ compatible with the Token's existing definition. If it is not, an error will be returned.
+
+ @param[in] Guid The 128-bit unique value that designates which namespace to extract the value from.
+ @param[in] TokenNumber The PCD token number.
+ @param[in] Value The value to set for the PCD token.
+
+ @retval EFI_SUCCESS The PCD service has set the value requested
+ @retval EFI_INVALID_PARAMETER The PCD service determined that the size of the data being set was
+ incompatible with a call to this function. Use GetSizeEx() to
+ retrieve the size of the target data.
+ @retval EFI_NOT_FOUND The PCD service could not find the requested token number.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_PEI_PCD_PPI_SET_64)(
+ IN CONST EFI_GUID *Guid,
+ IN UINTN TokenNumber,
+ IN UINT64 Value
+ );
+
+/**
+ Sets a value of the specified size for a given PCD token.
+
+ When the PCD service sets a value, it will check to ensure that the size of the value being set is
+ compatible with the Token's existing definition. If it is not, an error will be returned.
+
+ @param[in] Guid The 128-bit unique value that designates which namespace to extract the value from.
+ @param[in] TokenNumber The PCD token number.
+ @param[in] SizeOfValue The length of the value being set for the PCD token. If too large of a length is
+ specified, upon return from this function the value of SizeOfValue will reflect the
+ maximum size for the PCD token.
+ @param[in] Buffer A pointer to the buffer containing the value to set for the PCD token.
+
+ @retval EFI_SUCCESS The PCD service has set the value requested
+ @retval EFI_INVALID_PARAMETER The PCD service determined that the size of the data being set was
+ incompatible with a call to this function. Use GetSizeEx() to
+ retrieve the size of the target data.
+ @retval EFI_NOT_FOUND The PCD service could not find the requested token number.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_PEI_PCD_PPI_SET_POINTER)(
+ IN CONST EFI_GUID *Guid,
+ IN UINTN TokenNumber,
+ IN OUT UINTN *SizeOfValue,
+ IN VOID *Buffer
+ );
+
+/**
+ Sets a Boolean value for a given PCD token.
+
+ When the PCD service sets a value, it will check to ensure that the size of the value being set is
+ compatible with the Token's existing definition. If it is not, an error will be returned.
+
+ @param[in] Guid The 128-bit unique value that designates which namespace to extract the value from.
+ @param[in] TokenNumber The PCD token number.
+ @param[in] Value The value to set for the PCD token.
+
+ @retval EFI_SUCCESS The PCD service has set the value requested
+ @retval EFI_INVALID_PARAMETER The PCD service determined that the size of the data being set was
+ incompatible with a call to this function. Use GetSizeEx() to
+ retrieve the size of the target data.
+ @retval EFI_NOT_FOUND The PCD service could not find the requested token number.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_PEI_PCD_PPI_SET_BOOLEAN)(
+ IN CONST EFI_GUID *Guid,
+ IN UINTN TokenNumber,
+ IN BOOLEAN Value
+ );
+
+typedef
+VOID
+(EFIAPI *EFI_PEI_PCD_PPI_CALLBACK)(
+ IN EFI_GUID *Guid OPTIONAL,
+ IN UINTN CallBackToken,
+ IN OUT VOID *TokenData,
+ IN UINTN TokenDatSize
+ );
+
+/**
+ Specifies a function to be called anytime the value of a designated token is changed.
+
+ @param[in] Guid The 128-bit unique value that designates which namespace to monitor. If NULL, use
+ the standard platform namespace.
+ @param[in] CallBackToken The PCD token number to monitor.
+ @param[in] CallBackFunction The function prototype that will be called when the value associated with the
+ CallBackToken is set.
+
+ @retval EFI_SUCCESS The PCD service has successfully established a call event for the
+ CallBackToken requested.
+ @retval EFI_NOT_FOUND The PCD service could not find the referenced token number.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_PEI_PCD_PPI_CALLBACK_ON_SET)(
+ IN CONST EFI_GUID *Guid OPTIONAL,
+ IN UINTN CallBackToken,
+ IN EFI_PEI_PCD_PPI_CALLBACK CallBackFunction
+ );
+
+/**
+ Cancels a previously set callback function for a particular PCD token number.
+
+ @param[in] Guid The 128-bit unique value that designates which namespace to monitor. If NULL, use
+ the standard platform namespace.
+ @param[in] CallBackToken The PCD token number to cancel monitoring.
+ @param[in] CallBackFunction The function prototype that was originally passed to the CallBackOnSet function.
+
+ @retval EFI_SUCCESS The PCD service has cancelled the call event associated with the
+ CallBackToken.
+ @retval EFI_INVALID_PARAMETER The PCD service did not match the CallBackFunction to one
+ that is currently being monitored.
+ @retval EFI_NOT_FOUND The PCD service could not find data the requested token number.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_PEI_PCD_PPI_CANCEL_CALLBACK)(
+ IN CONST EFI_GUID *Guid OPTIONAL,
+ IN UINTN CallBackToken,
+ IN EFI_PEI_PCD_PPI_CALLBACK CallBackFunction
+ );
+
+/**
+ Retrieves the next valid PCD token for a given namespace.
+
+ This provides a means by which to get the next valid token number in a given namespace. This is
+ useful since the PCD infrastructure has a sparse list of token numbers in it, and one cannot a priori
+ know what token numbers are valid in the database.
+
+ @param[in] Guid The 128-bit unique value that designates which namespace to extract the value from.
+ @param[in] TokenNumber A pointer to the PCD token number to use to find the subsequent token number. To
+ retrieve the "first" token, have the pointer reference a TokenNumber value of 0.
+
+ @retval EFI_SUCCESS The PCD service has retrieved the value requested.
+ @retval EFI_NOT_FOUND The PCD service could not find data from the requested token number.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_PEI_PCD_PPI_GET_NEXT_TOKEN)(
+ IN CONST EFI_GUID *Guid OPTIONAL,
+ IN UINTN *TokenNumber
+ );
+
+/**
+ Retrieves the next valid PCD token namespace for a given namespace.
+
+ Gets the next valid token namespace for a given namespace. This is useful to traverse the valid
+ token namespaces on a platform.
+
+ @param[in, out] Guid An indirect pointer to EFI_GUID. On input it designates a known token
+ namespace from which the search will start. On output, it designates the next valid
+ token namespace on the platform. If *Guid is NULL, then the GUID of the first token
+ space of the current platform is returned. If the search cannot locate the next valid
+ token namespace, an error is returned and the value of *Guid is undefined.
+
+ @retval EFI_SUCCESS The PCD service retrieved the value requested.
+ @retval EFI_NOT_FOUND The PCD service could not find the next valid token namespace.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_PEI_PCD_PPI_GET_NEXT_TOKEN_SPACE)(
+ IN OUT CONST EFI_GUID **Guid
+ );
+
+typedef struct {
+ EFI_PEI_PCD_PPI_SET_SKU SetSku;
+ EFI_PEI_PCD_PPI_GET_8 Get8;
+ EFI_PEI_PCD_PPI_GET_16 Get16;
+ EFI_PEI_PCD_PPI_GET_32 Get32;
+ EFI_PEI_PCD_PPI_GET_64 Get64;
+ EFI_PEI_PCD_PPI_GET_POINTER GetPtr;
+ EFI_PEI_PCD_PPI_GET_BOOLEAN GetBool;
+ EFI_PEI_PCD_PPI_GET_SIZE GetSize;
+ EFI_PEI_PCD_PPI_SET_8 Set8;
+ EFI_PEI_PCD_PPI_SET_16 Set16;
+ EFI_PEI_PCD_PPI_SET_32 Set32;
+ EFI_PEI_PCD_PPI_SET_64 Set64;
+ EFI_PEI_PCD_PPI_SET_POINTER SetPtr;
+ EFI_PEI_PCD_PPI_SET_BOOLEAN SetBool;
+ EFI_PEI_PCD_PPI_CALLBACK_ON_SET CallbackOnSet;
+ EFI_PEI_PCD_PPI_CANCEL_CALLBACK CancelCallback;
+ EFI_PEI_PCD_PPI_GET_NEXT_TOKEN GetNextToken;
+ EFI_PEI_PCD_PPI_GET_NEXT_TOKEN_SPACE GetNextTokenSpace;
+} EFI_PEI_PCD_PPI;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Ppi/PiPcdInfo.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Ppi/PiPcdInfo.h
new file mode 100644
index 0000000000..e329cf8d5f
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Ppi/PiPcdInfo.h
@@ -0,0 +1,75 @@
+/** @file
+ Platform Configuration Database (PCD) Info Ppi defined in PI 1.2.1 Vol3.
+
+ The PPI that provides additional information about items that reside in the PCD database.
+
+ Copyright (c) 2013, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Revision Reference:
+ PI Version 1.2.1 Vol 3.
+**/
+
+#ifndef __PI_PCD_INFO_PPI_H__
+#define __PI_PCD_INFO_PPI_H__
+
+extern EFI_GUID gEfiGetPcdInfoPpiGuid;
+
+#define EFI_GET_PCD_INFO_PPI_GUID \
+ { 0xa60c6b59, 0xe459, 0x425d, { 0x9c, 0x69, 0xb, 0xcc, 0x9c, 0xb2, 0x7d, 0x81 } }
+
+///
+/// The forward declaration for EFI_GET_PCD_INFO_PPI.
+///
+typedef struct _EFI_GET_PCD_INFO_PPI EFI_GET_PCD_INFO_PPI;
+
+/**
+ Retrieve additional information associated with a PCD token.
+
+ This includes information such as the type of value the TokenNumber is associated with as well as possible
+ human readable name that is associated with the token.
+
+ @param[in] Guid The 128-bit unique value that designates the namespace from which to extract the value.
+ @param[in] TokenNumber The PCD token number.
+ @param[out] PcdInfo The returned information associated with the requested TokenNumber.
+
+ @retval EFI_SUCCESS The PCD information was returned successfully
+ @retval EFI_NOT_FOUND The PCD service could not find the requested token number.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_GET_PCD_INFO_PPI_GET_INFO)(
+ IN CONST EFI_GUID *Guid,
+ IN UINTN TokenNumber,
+ OUT EFI_PCD_INFO *PcdInfo
+ );
+
+/**
+ Retrieve the currently set SKU Id.
+
+ @return The currently set SKU Id. If the platform has not set at a SKU Id, then the
+ default SKU Id value of 0 is returned. If the platform has set a SKU Id, then the currently set SKU
+ Id is returned.
+**/
+typedef
+UINTN
+(EFIAPI *EFI_GET_PCD_INFO_PPI_GET_SKU)(
+ VOID
+ );
+
+///
+/// This is the PCD service to use when querying for some additional data that can be contained in the
+/// PCD database.
+///
+struct _EFI_GET_PCD_INFO_PPI {
+ ///
+ /// Retrieve additional information associated with a PCD.
+ ///
+ EFI_GET_PCD_INFO_PPI_GET_INFO GetInfo;
+ ///
+ /// Retrieve the currently set SKU Id.
+ ///
+ EFI_GET_PCD_INFO_PPI_GET_SKU GetSku;
+};
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Ppi/ReadOnlyVariable2.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Ppi/ReadOnlyVariable2.h
new file mode 100644
index 0000000000..02fbd5b2e6
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Ppi/ReadOnlyVariable2.h
@@ -0,0 +1,109 @@
+/** @file
+ This file declares Read-only Variable Service2 PPI.
+ This ppi permits read-only access to the UEFI variable store during the PEI phase.
+
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Revision Reference:
+ This PPI is introduced in PI Version 1.0.
+
+**/
+
+#ifndef __PEI_READ_ONLY_VARIABLE2_PPI_H__
+#define __PEI_READ_ONLY_VARIABLE2_PPI_H__
+
+#define EFI_PEI_READ_ONLY_VARIABLE2_PPI_GUID \
+ { 0x2ab86ef5, 0xecb5, 0x4134, { 0xb5, 0x56, 0x38, 0x54, 0xca, 0x1f, 0xe1, 0xb4 } }
+
+typedef struct _EFI_PEI_READ_ONLY_VARIABLE2_PPI EFI_PEI_READ_ONLY_VARIABLE2_PPI;
+
+/**
+ This service retrieves a variable's value using its name and GUID.
+
+ Read the specified variable from the UEFI variable store. If the Data
+ buffer is too small to hold the contents of the variable,
+ the error EFI_BUFFER_TOO_SMALL is returned and DataSize is set to the
+ required buffer size to obtain the data.
+
+ @param This A pointer to this instance of the EFI_PEI_READ_ONLY_VARIABLE2_PPI.
+ @param VariableName A pointer to a null-terminated string that is the variable's name.
+ @param VariableGuid A pointer to an EFI_GUID that is the variable's GUID. The combination of
+ VariableGuid and VariableName must be unique.
+ @param Attributes If non-NULL, on return, points to the variable's attributes.
+ @param DataSize On entry, points to the size in bytes of the Data buffer.
+ On return, points to the size of the data returned in Data.
+ @param Data Points to the buffer which will hold the returned variable value.
+ May be NULL with a zero DataSize in order to determine the size of the buffer needed.
+
+ @retval EFI_SUCCESS The variable was read successfully.
+ @retval EFI_NOT_FOUND The variable was not found.
+ @retval EFI_BUFFER_TOO_SMALL The DataSize is too small for the resulting data.
+ DataSize is updated with the size required for
+ the specified variable.
+ @retval EFI_INVALID_PARAMETER VariableName, VariableGuid, DataSize or Data is NULL.
+ @retval EFI_DEVICE_ERROR The variable could not be retrieved because of a device error.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_PEI_GET_VARIABLE2)(
+ IN CONST EFI_PEI_READ_ONLY_VARIABLE2_PPI *This,
+ IN CONST CHAR16 *VariableName,
+ IN CONST EFI_GUID *VariableGuid,
+ OUT UINT32 *Attributes,
+ IN OUT UINTN *DataSize,
+ OUT VOID *Data OPTIONAL
+ );
+
+/**
+ Return the next variable name and GUID.
+
+ This function is called multiple times to retrieve the VariableName
+ and VariableGuid of all variables currently available in the system.
+ On each call, the previous results are passed into the interface,
+ and, on return, the interface returns the data for the next
+ interface. When the entire variable list has been returned,
+ EFI_NOT_FOUND is returned.
+
+ @param This A pointer to this instance of the EFI_PEI_READ_ONLY_VARIABLE2_PPI.
+
+ @param VariableNameSize On entry, points to the size of the buffer pointed to by VariableName.
+ On return, the size of the variable name buffer.
+ @param VariableName On entry, a pointer to a null-terminated string that is the variable's name.
+ On return, points to the next variable's null-terminated name string.
+
+ @param VariableGuid On entry, a pointer to an EFI_GUID that is the variable's GUID.
+ On return, a pointer to the next variable's GUID.
+
+ @retval EFI_SUCCESS The variable was read successfully.
+ @retval EFI_NOT_FOUND The variable could not be found.
+ @retval EFI_BUFFER_TOO_SMALL The VariableNameSize is too small for the resulting
+ data. VariableNameSize is updated with the size
+ required for the specified variable.
+ @retval EFI_INVALID_PARAMETER VariableName, VariableGuid or
+ VariableNameSize is NULL.
+ @retval EFI_DEVICE_ERROR The variable could not be retrieved because of a device error.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_PEI_GET_NEXT_VARIABLE_NAME2)(
+ IN CONST EFI_PEI_READ_ONLY_VARIABLE2_PPI *This,
+ IN OUT UINTN *VariableNameSize,
+ IN OUT CHAR16 *VariableName,
+ IN OUT EFI_GUID *VariableGuid
+ );
+
+///
+/// This PPI provides a lightweight, read-only variant of the full EFI
+/// variable services.
+///
+struct _EFI_PEI_READ_ONLY_VARIABLE2_PPI {
+ EFI_PEI_GET_VARIABLE2 GetVariable;
+ EFI_PEI_GET_NEXT_VARIABLE_NAME2 NextVariableName;
+};
+
+extern EFI_GUID gEfiPeiReadOnlyVariable2PpiGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Ppi/RecoveryModule.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Ppi/RecoveryModule.h
new file mode 100644
index 0000000000..7e3b64106c
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Ppi/RecoveryModule.h
@@ -0,0 +1,81 @@
+/** @file
+ This file declares Recovery Module PPI. This PPI is used to find and load the
+ recovery files.
+
+ A module that produces this PPI has many roles and is responsible for the following:
+ -# Calling the driver recovery PPI EFI_PEI_DEVICE_RECOVERY_MODULE_PPI.
+ GetNumberRecoveryCapsules() to determine if one or more DXE recovery
+ entities exist.
+ -# If no capsules exist, then performing appropriate error handling.
+ -# Allocating a buffer of MaxRecoveryCapsuleSize as determined by
+ EFI_PEI_DEVICE_RECOVERY_MODULE_PPI.GetRecoveryCapsuleInfo() or
+ larger.
+ -# Determining the policy in which DXE recovery capsules are loaded.
+ -# Calling the driver recovery PPI EFI_PEI_DEVICE_RECOVERY_MODULE_PPI.
+ LoadRecoveryCapsule() for capsule number x.
+ -# If the load failed, performing appropriate error handling.
+ -# Performing security checks for a loaded DXE recovery capsule.
+ -# If the security checks failed, then logging the failure in a data HOB.
+ -# If the security checks failed, then determining the next
+ EFI_PEI_DEVICE_RECOVERY_MODULE_PPI.LoadRecoveryCapsule()capsule number;
+ otherwise, go to step 11.
+ -# If more DXE recovery capsules exist, then go to step 5; otherwise, perform
+ error handling.
+ -# Decomposing the capsule loaded by EFI_PEI_DEVICE_RECOVERY_MODULE_PPI.
+ LoadRecoveryCapsule() into its components. It is assumed that the path
+ parameters are redundant for recovery and Setup parameters are either
+ redundant or canned.
+ -# Invalidating all HOB entries for updateable firmware volume entries.
+ This invalidation prevents possible errant drivers from being executed.
+ -# Updating the HOB table with the recovery DXE firmware volume information
+ generated from the capsule decomposition.
+ -# Returning to the PEI Dispatcher.
+
+ Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Revision Reference:
+ This PPI is defined in UEFI Platform Initialization Specification 1.2 Errata B Volume 1:
+ Pre-EFI Initialization Core Interface
+
+**/
+
+#ifndef __PEI_RECOVERY_MODULE_PPI_H__
+#define __PEI_RECOVERY_MODULE_PPI_H__
+
+#define EFI_PEI_RECOVERY_MODULE_PPI_GUID \
+ { \
+ 0xFB6D9542, 0x612D, 0x4f45, {0x87, 0x2F, 0x5C, 0xFF, 0x52, 0xE9, 0x3D, 0xCF } \
+ }
+
+typedef struct _EFI_PEI_RECOVERY_MODULE_PPI EFI_PEI_RECOVERY_MODULE_PPI;
+
+/**
+ Loads a DXE capsule from some media into memory and updates the HOB table
+ with the DXE firmware volume information.
+
+ @param PeiServices General-purpose services that are available to every PEIM.
+ @param This Indicates the EFI_PEI_RECOVERY_MODULE_PPI instance.
+
+ @retval EFI_SUCCESS The capsule was loaded correctly.
+ @retval EFI_DEVICE_ERROR A device error occurred.
+ @retval EFI_NOT_FOUND A recovery DXE capsule cannot be found.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_PEI_LOAD_RECOVERY_CAPSULE)(
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PEI_RECOVERY_MODULE_PPI *This
+ );
+
+///
+/// Finds and loads the recovery files.
+///
+struct _EFI_PEI_RECOVERY_MODULE_PPI {
+ EFI_PEI_LOAD_RECOVERY_CAPSULE LoadRecoveryCapsule; ///< Loads a DXE binary capsule into memory.
+};
+
+extern EFI_GUID gEfiPeiRecoveryModulePpiGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Ppi/ReportStatusCodeHandler.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Ppi/ReportStatusCodeHandler.h
new file mode 100644
index 0000000000..87c9b3b1fb
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Ppi/ReportStatusCodeHandler.h
@@ -0,0 +1,76 @@
+/** @file
+ This PPI provides registering and unregistering services to status code consumers.
+
+ Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __REPORT_STATUS_CODE_HANDLER_PPI_H__
+#define __REPORT_STATUS_CODE_HANDLER_PPI_H__
+
+#define EFI_PEI_RSC_HANDLER_PPI_GUID \
+ { \
+ 0x65d394, 0x9951, 0x4144, {0x82, 0xa3, 0xa, 0xfc, 0x85, 0x79, 0xc2, 0x51} \
+ }
+
+typedef
+EFI_STATUS
+(EFIAPI *EFI_PEI_RSC_HANDLER_CALLBACK)(
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN EFI_STATUS_CODE_TYPE Type,
+ IN EFI_STATUS_CODE_VALUE Value,
+ IN UINT32 Instance,
+ IN CONST EFI_GUID *CallerId,
+ IN CONST EFI_STATUS_CODE_DATA *Data
+ );
+
+/**
+ Register the callback function for ReportStatusCode() notification.
+
+ When this function is called the function pointer is added to an internal list and any future calls to
+ ReportStatusCode() will be forwarded to the Callback function.
+
+ @param[in] Callback A pointer to a function of type EFI_PEI_RSC_HANDLER_CALLBACK that is called
+ when a call to ReportStatusCode() occurs.
+
+ @retval EFI_SUCCESS Function was successfully registered.
+ @retval EFI_INVALID_PARAMETER The callback function was NULL.
+ @retval EFI_OUT_OF_RESOURCES The internal buffer ran out of space. No more functions can be
+ registered.
+ @retval EFI_ALREADY_STARTED The function was already registered. It can't be registered again.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_PEI_RSC_HANDLER_REGISTER)(
+ IN EFI_PEI_RSC_HANDLER_CALLBACK Callback
+ );
+
+/**
+ Remove a previously registered callback function from the notification list.
+
+ ReportStatusCode() messages will no longer be forwarded to the Callback function.
+
+ @param[in] Callback A pointer to a function of type EFI_PEI_RSC_HANDLER_CALLBACK that is to be
+ unregistered.
+
+ @retval EFI_SUCCESS The function was successfully unregistered.
+ @retval EFI_INVALID_PARAMETER The callback function was NULL.
+ @retval EFI_NOT_FOUND The callback function was not found to be unregistered.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_PEI_RSC_HANDLER_UNREGISTER)(
+ IN EFI_PEI_RSC_HANDLER_CALLBACK Callback
+ );
+
+typedef struct _EFI_PEI_RSC_HANDLER_PPI {
+ EFI_PEI_RSC_HANDLER_REGISTER Register;
+ EFI_PEI_RSC_HANDLER_UNREGISTER Unregister;
+} EFI_PEI_RSC_HANDLER_PPI;
+
+extern EFI_GUID gEfiPeiRscHandlerPpiGuid;
+
+#endif // __REPORT_STATUS_CODE_HANDLER_PPI_H__
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Ppi/Reset.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Ppi/Reset.h
new file mode 100644
index 0000000000..9415b52ed2
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Ppi/Reset.h
@@ -0,0 +1,38 @@
+/** @file
+ This file declares Reset PPI used to reset the platform.
+
+ This PPI is installed by some platform- or chipset-specific PEIM that
+ abstracts the Reset Service to other agents.
+
+ Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Revision Reference:
+ This PPI is introduced in PI Version 1.0.
+
+**/
+
+#ifndef __RESET_PPI_H__
+#define __RESET_PPI_H__
+
+#define EFI_PEI_RESET_PPI_GUID \
+ { \
+ 0xef398d58, 0x9dfd, 0x4103, {0xbf, 0x94, 0x78, 0xc6, 0xf4, 0xfe, 0x71, 0x2f } \
+ }
+
+//
+// EFI_PEI_RESET_PPI.ResetSystem() is equivalent to the
+// PEI Service ResetSystem().
+// It is introduced in PIPeiCis.h.
+//
+
+///
+/// This PPI provides provide a simple reset service.
+///
+typedef struct {
+ EFI_PEI_RESET_SYSTEM ResetSystem;
+} EFI_PEI_RESET_PPI;
+
+extern EFI_GUID gEfiPeiResetPpiGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Ppi/Reset2.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Ppi/Reset2.h
new file mode 100644
index 0000000000..65cf72b7d1
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Ppi/Reset2.h
@@ -0,0 +1,32 @@
+/** @file
+ This file declares Reset2 PPI used to reset the platform.
+
+ This PPI is installed by some platform- or chipset-specific PEIM that
+ abstracts the Reset Service to other agents.
+
+ Copyright (c) 2015, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Revision Reference:
+ This PPI is introduced in PI Version 1.4.
+
+**/
+
+#ifndef __RESET2_PPI_H__
+#define __RESET2_PPI_H__
+
+#define EFI_PEI_RESET2_PPI_GUID \
+ { \
+ 0x6cc45765, 0xcce4, 0x42fd, {0xbc, 0x56, 0x1, 0x1a, 0xaa, 0xc6, 0xc9, 0xa8 } \
+ }
+
+///
+/// This PPI provides provide a simple reset service.
+///
+typedef struct _EFI_PEI_RESET2_PPI {
+ EFI_PEI_RESET2_SYSTEM ResetSystem;
+} EFI_PEI_RESET2_PPI;
+
+extern EFI_GUID gEfiPeiReset2PpiGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Ppi/S3Resume2.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Ppi/S3Resume2.h
new file mode 100644
index 0000000000..0555261ba1
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Ppi/S3Resume2.h
@@ -0,0 +1,86 @@
+/** @file
+ This PPI produces functions to interpret and execute the PI boot script table.
+
+ This PPI is published by a PEIM and provides for the restoration of the platform's
+ configuration when resuming from the ACPI S3 power state. The ability to execute
+ the boot script may depend on the availability of other PPIs. For example, if
+ the boot script includes an SMBus command, this PEIM looks for the relevant PPI
+ that is able to execute that command.
+
+ Copyright (c) 2010 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Revision Reference:
+ This PPI is defined in UEFI Platform Initialization Specification 1.2 Volume 5:
+ Standards
+
+**/
+
+#ifndef __PEI_S3_RESUME_PPI_H__
+#define __PEI_S3_RESUME_PPI_H__
+
+///
+/// Global ID for EFI_PEI_S3_RESUME2_PPI
+///
+#define EFI_PEI_S3_RESUME2_PPI_GUID \
+ { \
+ 0x6D582DBC, 0xDB85, 0x4514, {0x8F, 0xCC, 0x5A, 0xDF, 0x62, 0x27, 0xB1, 0x47 } \
+ }
+
+///
+/// Forward declaration for EFI_PEI_S3_RESUME_PPI
+///
+typedef struct _EFI_PEI_S3_RESUME2_PPI EFI_PEI_S3_RESUME2_PPI;
+
+/**
+ Restores the platform to its preboot configuration for an S3 resume and
+ jumps to the OS waking vector.
+
+ This function will restore the platform to its pre-boot configuration that was
+ pre-stored in the boot script table and transfer control to OS waking vector.
+ Upon invocation, this function is responsible for locating the following
+ information before jumping to OS waking vector:
+ - ACPI tables
+ - boot script table
+ - any other information that it needs
+
+ The S3RestoreConfig() function then executes the pre-stored boot script table
+ and transitions the platform to the pre-boot state. The boot script is recorded
+ during regular boot using the EFI_S3_SAVE_STATE_PROTOCOL.Write() and
+ EFI_S3_SMM_SAVE_STATE_PROTOCOL.Write() functions. Finally, this function
+ transfers control to the OS waking vector. If the OS supports only a real-mode
+ waking vector, this function will switch from flat mode to real mode before
+ jumping to the waking vector. If all platform pre-boot configurations are
+ successfully restored and all other necessary information is ready, this
+ function will never return and instead will directly jump to the OS waking
+ vector. If this function returns, it indicates that the attempt to resume
+ from the ACPI S3 sleep state failed.
+
+ @param[in] This Pointer to this instance of the PEI_S3_RESUME_PPI
+
+ @retval EFI_ABORTED Execution of the S3 resume boot script table failed.
+ @retval EFI_NOT_FOUND Some necessary information that is used for the S3
+ resume boot path could not be located.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_PEI_S3_RESUME_PPI_RESTORE_CONFIG2)(
+ IN EFI_PEI_S3_RESUME2_PPI *This
+ );
+
+/**
+ EFI_PEI_S3_RESUME2_PPI accomplishes the firmware S3 resume boot
+ path and transfers control to OS.
+**/
+struct _EFI_PEI_S3_RESUME2_PPI {
+ ///
+ /// Restores the platform to its preboot configuration for an S3 resume and
+ /// jumps to the OS waking vector.
+ ///
+ EFI_PEI_S3_RESUME_PPI_RESTORE_CONFIG2 S3RestoreConfig2;
+};
+
+extern EFI_GUID gEfiPeiS3Resume2PpiGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Ppi/SecHobData.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Ppi/SecHobData.h
new file mode 100644
index 0000000000..f372782aab
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Ppi/SecHobData.h
@@ -0,0 +1,59 @@
+/** @file
+ This file declares Sec Hob Data PPI.
+
+ This PPI provides a way for the SEC code to pass zero or more HOBs in a HOB list.
+
+Copyright (c) 2017 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Revision Reference:
+ This PPI is introduced in PI Version 1.5.
+
+**/
+
+#ifndef __SEC_HOB_DATA_PPI_H__
+#define __SEC_HOB_DATA_PPI_H__
+
+#include
+
+#define EFI_SEC_HOB_DATA_PPI_GUID \
+ { \
+ 0x3ebdaf20, 0x6667, 0x40d8, {0xb4, 0xee, 0xf5, 0x99, 0x9a, 0xc1, 0xb7, 0x1f } \
+ }
+
+typedef struct _EFI_SEC_HOB_DATA_PPI EFI_SEC_HOB_DATA_PPI;
+
+/**
+ Return a pointer to a buffer containing zero or more HOBs that
+ will be installed into the PEI HOB List.
+
+ This function returns a pointer to a pointer to zero or more HOBs,
+ terminated with a HOB of type EFI_HOB_TYPE_END_OF_HOB_LIST.
+ Note: The HobList must not contain a EFI_HOB_HANDOFF_INFO_TABLE HOB (PHIT) HOB.
+
+ @param[in] This Pointer to this PPI structure.
+ @param[out] HobList A pointer to a returned pointer to zero or more HOBs.
+ If no HOBs are to be returned, then the returned pointer
+ is a pointer to a HOB of type EFI_HOB_TYPE_END_OF_HOB_LIST.
+
+ @retval EFI_SUCCESS This function completed successfully.
+ @retval EFI_NOT_FOUND No HOBS are available.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_SEC_HOB_DATA_GET)(
+ IN CONST EFI_SEC_HOB_DATA_PPI *This,
+ OUT EFI_HOB_GENERIC_HEADER **HobList
+ );
+
+///
+/// This PPI provides a way for the SEC code to pass zero or more HOBs in a HOB list.
+///
+struct _EFI_SEC_HOB_DATA_PPI {
+ EFI_SEC_HOB_DATA_GET GetHobs;
+};
+
+extern EFI_GUID gEfiSecHobDataPpiGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Ppi/SecPlatformInformation.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Ppi/SecPlatformInformation.h
new file mode 100644
index 0000000000..4dad202cf9
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Ppi/SecPlatformInformation.h
@@ -0,0 +1,179 @@
+/** @file
+ This file declares Sec Platform Information PPI.
+
+ This service is the primary handoff state into the PEI Foundation.
+ The Security (SEC) component creates the early, transitory memory
+ environment and also encapsulates knowledge of at least the
+ location of the Boot Firmware Volume (BFV).
+
+Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Revision Reference:
+ This PPI is introduced in PI Version 1.0.
+
+**/
+
+#ifndef __SEC_PLATFORM_INFORMATION_PPI_H__
+#define __SEC_PLATFORM_INFORMATION_PPI_H__
+
+#include
+
+#define EFI_SEC_PLATFORM_INFORMATION_GUID \
+ { \
+ 0x6f8c2b35, 0xfef4, 0x448d, {0x82, 0x56, 0xe1, 0x1b, 0x19, 0xd6, 0x10, 0x77 } \
+ }
+
+typedef struct _EFI_SEC_PLATFORM_INFORMATION_PPI EFI_SEC_PLATFORM_INFORMATION_PPI;
+
+///
+/// EFI_HEALTH_FLAGS
+/// Contains information generated by microcode, hardware, and/or the Itanium
+/// processor PAL code about the state of the processor upon reset.
+///
+typedef union {
+ struct {
+ ///
+ /// A 2-bit field indicating self-test state after reset.
+ ///
+ UINT32 Status : 2;
+ ///
+ /// A 1-bit field indicating whether testing has occurred.
+ /// If this field is zero, the processor has not been tested,
+ /// and no further fields in the self-test State parameter are valid.
+ ///
+ UINT32 Tested : 1;
+ ///
+ /// Reserved 13 bits.
+ ///
+ UINT32 Reserved1 : 13;
+ ///
+ /// A 1-bit field. If set to 1, this indicates that virtual
+ /// memory features are not available.
+ ///
+ UINT32 VirtualMemoryUnavailable : 1;
+ ///
+ /// A 1-bit field. If set to 1, this indicates that IA-32 execution
+ /// is not available.
+ ///
+ UINT32 Ia32ExecutionUnavailable : 1;
+ ///
+ /// A 1-bit field. If set to 1, this indicates that the floating
+ /// point unit is not available.
+ ///
+ UINT32 FloatingPointUnavailable : 1;
+ ///
+ /// A 1-bit field. If set to 1, this indicates miscellaneous
+ /// functional failure other than vm, ia, or fp.
+ /// The test status field provides additional information on
+ /// test failures when the State field returns a value of
+ /// performance restricted or functionally restricted.
+ /// The value returned is implementation dependent.
+ ///
+ UINT32 MiscFeaturesUnavailable : 1;
+ ///
+ /// Reserved 12 bits.
+ ///
+ UINT32 Reserved2 : 12;
+ } Bits;
+ UINT32 Uint32;
+} EFI_HEALTH_FLAGS;
+
+#define NORMAL_BOOT_CALL 0x0
+#define RECOVERY_CHECK_CALL 0x3
+
+typedef EFI_HEALTH_FLAGS X64_HANDOFF_STATUS;
+typedef EFI_HEALTH_FLAGS IA32_HANDOFF_STATUS;
+///
+/// The hand-off status structure for Itanium architecture.
+///
+typedef struct {
+ ///
+ /// SALE_ENTRY state : 3 = Recovery_Check
+ /// and 0 = RESET or Normal_Boot phase.
+ ///
+ UINT8 BootPhase;
+ ///
+ /// Firmware status on entry to SALE.
+ ///
+ UINT8 FWStatus;
+ UINT16 Reserved1;
+ UINT32 Reserved2;
+ ///
+ /// Geographically significant unique processor ID assigned by PAL.
+ ///
+ UINT16 ProcId;
+ UINT16 Reserved3;
+ UINT8 IdMask;
+ UINT8 EidMask;
+ UINT16 Reserved4;
+ ///
+ /// Address to make PAL calls.
+ ///
+ UINT64 PalCallAddress;
+ ///
+ /// If the entry state is RECOVERY_CHECK, this contains the PAL_RESET
+ /// return address, and if entry state is RESET, this contains
+ /// address for PAL_authentication call.
+ ///
+ UINT64 PalSpecialAddress;
+ ///
+ /// GR35 from PALE_EXIT state.
+ ///
+ UINT64 SelfTestStatus;
+ ///
+ /// GR37 from PALE_EXIT state.
+ ///
+ UINT64 SelfTestControl;
+ UINT64 MemoryBufferRequired;
+} ITANIUM_HANDOFF_STATUS;
+
+///
+/// EFI_SEC_PLATFORM_INFORMATION_RECORD.
+///
+typedef union {
+ IA32_HANDOFF_STATUS IA32HealthFlags;
+ X64_HANDOFF_STATUS x64HealthFlags;
+ ITANIUM_HANDOFF_STATUS ItaniumHealthFlags;
+} EFI_SEC_PLATFORM_INFORMATION_RECORD;
+
+/**
+ This interface conveys state information out of the Security (SEC) phase into PEI.
+
+ This service is published by the SEC phase. The SEC phase handoff has an optional
+ EFI_PEI_PPI_DESCRIPTOR list as its final argument when control is passed from SEC into the
+ PEI Foundation. As such, if the platform supports the built-in self test (BIST) on IA-32 Intel
+ architecture or the PAL-A handoff state for Itanium architecture, this information is encapsulated
+ into the data structure abstracted by this service. This information is collected for the boot-strap
+ processor (BSP) on IA-32. For Itanium architecture, it is available on all processors that execute
+ the PEI Foundation.
+
+ @param PeiServices The pointer to the PEI Services Table.
+ @param StructureSize The pointer to the variable describing size of the input buffer.
+ @param PlatformInformationRecord The pointer to the EFI_SEC_PLATFORM_INFORMATION_RECORD.
+
+ @retval EFI_SUCCESS The data was successfully returned.
+ @retval EFI_BUFFER_TOO_SMALL The buffer was too small. The current buffer size needed to
+ hold the record is returned in StructureSize.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_SEC_PLATFORM_INFORMATION)(
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN OUT UINT64 *StructureSize,
+ OUT EFI_SEC_PLATFORM_INFORMATION_RECORD *PlatformInformationRecord
+ );
+
+///
+/// This service abstracts platform-specific information. It is necessary
+/// to convey this information to the PEI Foundation so that it can
+/// discover where to begin dispatching PEIMs.
+///
+struct _EFI_SEC_PLATFORM_INFORMATION_PPI {
+ EFI_SEC_PLATFORM_INFORMATION PlatformInformation;
+};
+
+extern EFI_GUID gEfiSecPlatformInformationPpiGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Ppi/SecPlatformInformation2.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Ppi/SecPlatformInformation2.h
new file mode 100644
index 0000000000..8730144db9
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Ppi/SecPlatformInformation2.h
@@ -0,0 +1,79 @@
+/** @file
+ This file declares Sec Platform Information2 PPI.
+
+ This service is the primary handoff state into the PEI Foundation.
+ This service abstracts platform-specific information for many CPU's.
+
+Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Revision Reference:
+ This PPI is introduced from PI Version 1.4.
+
+**/
+
+#ifndef __SEC_PLATFORM_INFORMATION2_PPI_H__
+#define __SEC_PLATFORM_INFORMATION2_PPI_H__
+
+#include
+
+#define EFI_SEC_PLATFORM_INFORMATION2_GUID \
+ { \
+ 0x9e9f374b, 0x8f16, 0x4230, {0x98, 0x24, 0x58, 0x46, 0xee, 0x76, 0x6a, 0x97 } \
+ }
+
+typedef struct _EFI_SEC_PLATFORM_INFORMATION2_PPI EFI_SEC_PLATFORM_INFORMATION2_PPI;
+
+///
+/// EFI_SEC_PLATFORM_INFORMATION_CPU.
+///
+typedef struct {
+ UINT32 CpuLocation;
+ EFI_SEC_PLATFORM_INFORMATION_RECORD InfoRecord;
+} EFI_SEC_PLATFORM_INFORMATION_CPU;
+
+///
+/// EFI_SEC_PLATFORM_INFORMATION_RECORD2.
+///
+typedef struct {
+ ///
+ /// The CPU location would be the local APIC ID
+ ///
+ UINT32 NumberOfCpus;
+ EFI_SEC_PLATFORM_INFORMATION_CPU CpuInstance[1];
+} EFI_SEC_PLATFORM_INFORMATION_RECORD2;
+
+/**
+ This interface conveys state information out of the Security (SEC) phase into PEI.
+
+ This service is published by the SEC phase.
+
+ @param PeiServices The pointer to the PEI Services Table.
+ @param StructureSize The pointer to the variable describing size of the input buffer.
+ @param PlatformInformationRecord2 The pointer to the EFI_SEC_PLATFORM_INFORMATION_RECORD2.
+
+ @retval EFI_SUCCESS The data was successfully returned.
+ @retval EFI_BUFFER_TOO_SMALL The buffer was too small. The current buffer size needed to
+ hold the record is returned in StructureSize.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_SEC_PLATFORM_INFORMATION2)(
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN OUT UINT64 *StructureSize,
+ OUT EFI_SEC_PLATFORM_INFORMATION_RECORD2 *PlatformInformationRecord2
+ );
+
+///
+/// This service abstracts platform-specific information for many CPU's.
+/// It is the multi-processor equivalent of PlatformInformation for
+/// implementations that synchronize some, if not all CPU's in the SEC phase.
+///
+struct _EFI_SEC_PLATFORM_INFORMATION2_PPI {
+ EFI_SEC_PLATFORM_INFORMATION2 PlatformInformation2;
+};
+
+extern EFI_GUID gEfiSecPlatformInformation2PpiGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Ppi/Security2.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Ppi/Security2.h
new file mode 100644
index 0000000000..48a068b3c7
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Ppi/Security2.h
@@ -0,0 +1,93 @@
+/** @file
+ This file declares Pei Security2 PPI.
+
+ This PPI is installed by some platform PEIM that abstracts the security
+ policy to the PEI Foundation, namely the case of a PEIM's authentication
+ state being returned during the PEI section extraction process.
+
+ Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Revision Reference:
+ This PPI is introduced in PI Version 1.0.
+
+**/
+
+#ifndef __SECURITY2_PPI_H__
+#define __SECURITY2_PPI_H__
+
+#define EFI_PEI_SECURITY2_PPI_GUID \
+ { 0xdcd0be23, 0x9586, 0x40f4, { 0xb6, 0x43, 0x6, 0x52, 0x2c, 0xed, 0x4e, 0xde } }
+
+typedef struct _EFI_PEI_SECURITY2_PPI EFI_PEI_SECURITY2_PPI;
+
+/**
+ Allows the platform builder to implement a security policy
+ in response to varying file authentication states.
+
+ This service is published by some platform PEIM. The purpose of
+ this service is to expose a given platform's policy-based
+ response to the PEI Foundation. For example, if there is a PEIM
+ in a GUIDed encapsulation section and the extraction of the PEI
+ file section yields an authentication failure, there is no a
+ priori policy in the PEI Foundation. Specifically, this
+ situation leads to the question whether PEIMs that are either
+ not in GUIDed sections or are in sections whose authentication
+ fails should still be executed.
+
+ @param PeiServices An indirect pointer to the PEI Services
+ Table published by the PEI Foundation.
+ @param This Interface pointer that implements the
+ particular EFI_PEI_SECURITY2_PPI instance.
+ @param AuthenticationStatus Authentication status of the file.
+ xx00 Image was not signed.
+ xxx1 Platform security policy override.
+ Assumes same meaning as 0010 (the image was signed, the
+ signature was tested, and the signature passed authentication test).
+ 0010 Image was signed, the signature was tested,
+ and the signature passed authentication test.
+ 0110 Image was signed and the signature was not tested.
+ 1010 Image was signed, the signature was tested,
+ and the signature failed the authentication test.
+ @param FvHandle Handle of the volume in which the file
+ resides. This allows different policies
+ depending on different firmware volumes.
+ @param FileHandle Handle of the file under review.
+ @param DeferExecution Pointer to a variable that alerts the
+ PEI Foundation to defer execution of a
+ PEIM.
+
+ @retval EFI_SUCCESS The service performed its action successfully.
+ @retval EFI_SECURITY_VIOLATION The object cannot be trusted.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_PEI_SECURITY_AUTHENTICATION_STATE)(
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN CONST EFI_PEI_SECURITY2_PPI *This,
+ IN UINT32 AuthenticationStatus,
+ IN EFI_PEI_FV_HANDLE FvHandle,
+ IN EFI_PEI_FILE_HANDLE FileHandle,
+ IN OUT BOOLEAN *DeferExecution
+ );
+
+///
+/// This PPI is a means by which the platform builder can indicate
+/// a response to a PEIM's authentication state. This can be in
+/// the form of a requirement for the PEI Foundation to skip a
+/// module using the DeferExecution Boolean output in the
+/// AuthenticationState() member function. Alternately, the
+/// Security PPI can invoke something like a cryptographic PPI
+/// that hashes the PEIM contents to log attestations, for which
+/// the FileHandle parameter in AuthenticationState() will be
+/// useful. If this PPI does not exist, PEIMs will be considered
+/// trusted.
+///
+struct _EFI_PEI_SECURITY2_PPI {
+ EFI_PEI_SECURITY_AUTHENTICATION_STATE AuthenticationState;
+};
+
+extern EFI_GUID gEfiPeiSecurity2PpiGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Ppi/Smbus2.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Ppi/Smbus2.h
new file mode 100644
index 0000000000..eaba2a1b8a
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Ppi/Smbus2.h
@@ -0,0 +1,196 @@
+/** @file
+ This file declares Smbus2 PPI.
+ This PPI provides the basic I/O interfaces that a PEIM uses to access its
+ SMBus controller and the slave devices attached to it.
+
+ Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Revision Reference:
+ This PPI is introduced in PI Version 1.0.
+
+**/
+
+#ifndef __PEI_SMBUS2_PPI_H__
+#define __PEI_SMBUS2_PPI_H__
+
+#include
+
+#define EFI_PEI_SMBUS2_PPI_GUID \
+ { 0x9ca93627, 0xb65b, 0x4324, { 0xa2, 0x2, 0xc0, 0xb4, 0x61, 0x76, 0x45, 0x43 } }
+
+typedef struct _EFI_PEI_SMBUS2_PPI EFI_PEI_SMBUS2_PPI;
+
+/**
+ Executes an SMBus operation to an SMBus controller. Returns when either
+ the command has been executed or an error is encountered in doing the operation.
+
+ @param This A pointer to the EFI_PEI_SMBUS2_PPI instance.
+ @param SlaveAddress The SMBUS hardware address to which the SMBUS device is preassigned or
+ allocated.
+ @param Command This command is transmitted by the SMBus host controller to the SMBus slave
+ device and the interpretation is SMBus slave device specific.
+ It can mean the offset to a list of functions inside
+ an SMBus slave device. Not all operations or slave devices support
+ this command's registers.
+ @param Operation Signifies which particular SMBus hardware protocol instance that it
+ will use to execute the SMBus transactions.
+ This SMBus hardware protocol is defined by the System Management Bus (SMBus)
+ Specification and is not related to UEFI.
+ @param PecCheck Defines if Packet Error Code (PEC) checking is required for this operation.
+ @param Length Signifies the number of bytes that this operation will do.
+ The maximum number of bytes can be revision specific and operation specific.
+ This parameter will contain the actual number of bytes that are executed
+ for this operation. Not all operations require this argument.
+ @param Buffer Contains the value of data to execute to the SMBus slave device.
+ Not all operations require this argument.
+ The length of this buffer is identified by Length.
+
+
+ @retval EFI_SUCCESS The last data that was returned from the access
+ matched the poll exit criteria.
+ @retval EFI_CRC_ERROR The checksum is not correct (PEC is incorrect)
+ @retval EFI_TIMEOUT Timeout expired before the operation was completed.
+ Timeout is determined by the SMBus host controller device.
+ @retval EFI_OUT_OF_RESOURCES The request could not be completed
+ due to a lack of resources.
+ @retval EFI_DEVICE_ERROR The request was not completed because
+ a failure reflected in the Host Status Register bit.
+ @retval EFI_INVALID_PARAMETER Operation is not defined in EFI_SMBUS_OPERATION.
+ Or Length/Buffer is NULL for operations except for EfiSmbusQuickRead and
+ EfiSmbusQuickWrite. Or Length is outside the range of valid values.
+ @retval EFI_UNSUPPORTED The SMBus operation or PEC is not supported.
+ @retval EFI_BUFFER_TOO_SMALL Buffer is not sufficient for this operation.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_PEI_SMBUS2_PPI_EXECUTE_OPERATION)(
+ IN CONST EFI_PEI_SMBUS2_PPI *This,
+ IN EFI_SMBUS_DEVICE_ADDRESS SlaveAddress,
+ IN EFI_SMBUS_DEVICE_COMMAND Command,
+ IN EFI_SMBUS_OPERATION Operation,
+ IN BOOLEAN PecCheck,
+ IN OUT UINTN *Length,
+ IN OUT VOID *Buffer
+ );
+
+/**
+ The ArpDevice() function enumerates the entire bus or enumerates a specific
+ device that is identified by SmbusUdid.
+
+ @param This A pointer to the EFI_PEI_SMBUS2_PPI instance.
+ @param ArpAll A Boolean expression that indicates if the host drivers need
+ to enumerate all the devices or enumerate only the device that is identified
+ by SmbusUdid. If ArpAll is TRUE, SmbusUdid and SlaveAddress are optional.
+ If ArpAll is FALSE, ArpDevice will enumerate SmbusUdid and the address
+ will be at SlaveAddress.
+ @param SmbusUdid The targeted SMBus Unique Device Identifier (UDID).
+ The UDID may not exist for SMBus devices with fixed addresses.
+ @param SlaveAddress The new SMBus address for the slave device for
+ which the operation is targeted.
+
+ @retval EFI_SUCCESS The SMBus slave device address was set.
+ @retval EFI_INVALID_PARAMETER SlaveAddress is NULL.
+ @retval EFI_OUT_OF_RESOURCES The request could not be completed
+ due to a lack of resources.
+ @retval EFI_TIMEOUT The SMBus slave device did not respond.
+ @retval EFI_DEVICE_ERROR The request was not completed because the transaction failed.
+ @retval EFI_UNSUPPORTED ArpDevice, GetArpMap, and Notify are not implemented by this PEIM.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_PEI_SMBUS2_PPI_ARP_DEVICE)(
+ IN CONST EFI_PEI_SMBUS2_PPI *This,
+ IN BOOLEAN ArpAll,
+ IN EFI_SMBUS_UDID *SmbusUdid OPTIONAL,
+ IN OUT EFI_SMBUS_DEVICE_ADDRESS *SlaveAddress OPTIONAL
+ );
+
+/**
+ The GetArpMap() function returns the mapping of all the SMBus devices
+ that are enumerated by the SMBus host driver.
+
+ @param This A pointer to the EFI_PEI_SMBUS2_PPI instance.
+ @param Length Size of the buffer that contains the SMBus device map.
+ @param SmbusDeviceMap The pointer to the device map as enumerated
+ by the SMBus controller driver.
+
+ @retval EFI_SUCCESS The device map was returned correctly in the buffer.
+ @retval EFI_UNSUPPORTED ArpDevice, GetArpMap, and Notify are not implemented by this PEIM.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_PEI_SMBUS2_PPI_GET_ARP_MAP)(
+ IN CONST EFI_PEI_SMBUS2_PPI *This,
+ IN OUT UINTN *Length,
+ IN OUT EFI_SMBUS_DEVICE_MAP **SmbusDeviceMap
+ );
+
+/**
+ CallBack function can be registered in EFI_PEI_SMBUS2_PPI_NOTIFY.
+
+ @param This A pointer to the EFI_PEI_SMBUS2_PPI instance.
+ @param SlaveAddress The SMBUS hardware address to which the SMBUS
+ device is preassigned or allocated.
+ @param Data Data of the SMBus host notify command that
+ the caller wants to be called.
+
+ @retval EFI_SUCCESS NotifyFunction has been registered.
+ @retval EFI_UNSUPPORTED ArpDevice, GetArpMap, and Notify are not
+ implemented by this PEIM.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_PEI_SMBUS_NOTIFY2_FUNCTION)(
+ IN CONST EFI_PEI_SMBUS2_PPI *SmbusPpi,
+ IN EFI_SMBUS_DEVICE_ADDRESS SlaveAddress,
+ IN UINTN Data
+ );
+
+/**
+ The Notify() function registers all the callback functions to allow the
+ bus driver to call these functions when the SlaveAddress/Data pair happens.
+
+ @param This A pointer to the EFI_PEI_SMBUS2_PPI instance.
+ @param SlaveAddress Address that the host controller detects as
+ sending a message and calls all the registered functions.
+ @param Data Data that the host controller detects as sending a message
+ and calls all the registered functions.
+ @param NotifyFunction The function to call when the bus driver
+ detects the SlaveAddress and Data pair.
+
+ @retval EFI_SUCCESS NotifyFunction has been registered.
+ @retval EFI_UNSUPPORTED ArpDevice, GetArpMap, and Notify are not
+ implemented by this PEIM.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_PEI_SMBUS2_PPI_NOTIFY)(
+ IN CONST EFI_PEI_SMBUS2_PPI *This,
+ IN EFI_SMBUS_DEVICE_ADDRESS SlaveAddress,
+ IN UINTN Data,
+ IN EFI_PEI_SMBUS_NOTIFY2_FUNCTION NotifyFunction
+ );
+
+///
+/// Provides the basic I/O interfaces that a PEIM uses to access
+/// its SMBus controller and the slave devices attached to it.
+///
+struct _EFI_PEI_SMBUS2_PPI {
+ EFI_PEI_SMBUS2_PPI_EXECUTE_OPERATION Execute;
+ EFI_PEI_SMBUS2_PPI_ARP_DEVICE ArpDevice;
+ EFI_PEI_SMBUS2_PPI_GET_ARP_MAP GetArpMap;
+ EFI_PEI_SMBUS2_PPI_NOTIFY Notify;
+ ///
+ /// Identifier which uniquely identifies this SMBus controller in a system.
+ ///
+ EFI_GUID Identifier;
+};
+
+extern EFI_GUID gEfiPeiSmbus2PpiGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Ppi/Stall.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Ppi/Stall.h
new file mode 100644
index 0000000000..adb552fe99
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Ppi/Stall.h
@@ -0,0 +1,56 @@
+/** @file
+ This file declares Stall PPI.
+
+ This ppi abstracts the blocking stall service to other agents.
+
+ Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Revision Reference:
+ This PPI is introduced in PI Version 1.0.
+
+**/
+
+#ifndef __STALL_PPI_H__
+#define __STALL_PPI_H__
+
+#define EFI_PEI_STALL_PPI_GUID \
+ { 0x1f4c6f90, 0xb06b, 0x48d8, {0xa2, 0x01, 0xba, 0xe5, 0xf1, 0xcd, 0x7d, 0x56 } }
+
+typedef struct _EFI_PEI_STALL_PPI EFI_PEI_STALL_PPI;
+
+/**
+ The Stall() function provides a blocking stall for at least the number
+ of microseconds stipulated in the final argument of the API.
+
+ @param PeiServices An indirect pointer to the PEI Services Table
+ published by the PEI Foundation.
+ @param This Pointer to the local data for the interface.
+ @param Microseconds Number of microseconds for which to stall.
+
+ @retval EFI_SUCCESS The service provided at least the required delay.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_PEI_STALL)(
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN CONST EFI_PEI_STALL_PPI *This,
+ IN UINTN Microseconds
+ );
+
+///
+/// This service provides a simple, blocking stall with platform-specific resolution.
+///
+struct _EFI_PEI_STALL_PPI {
+ ///
+ /// The resolution in microseconds of the stall services.
+ ///
+ UINTN Resolution;
+
+ EFI_PEI_STALL Stall;
+};
+
+extern EFI_GUID gEfiPeiStallPpiGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Ppi/StatusCode.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Ppi/StatusCode.h
new file mode 100644
index 0000000000..57d61767e1
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Ppi/StatusCode.h
@@ -0,0 +1,35 @@
+/** @file
+ This file declares Status Code PPI.
+ This ppi provides a service that allows PEIMs to report status codes.
+
+ Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Revision Reference:
+ This PPI is introduced in PI Version 1.0.
+
+**/
+
+#ifndef __STATUS_CODE_PPI_H__
+#define __STATUS_CODE_PPI_H__
+
+#define EFI_PEI_REPORT_PROGRESS_CODE_PPI_GUID \
+ { 0x229832d3, 0x7a30, 0x4b36, {0xb8, 0x27, 0xf4, 0xc, 0xb7, 0xd4, 0x54, 0x36 } }
+
+//
+// EFI_PEI_PROGRESS_CODE_PPI.ReportStatusCode() is equivalent to the
+// PEI Service ReportStatusCode().
+// It is introduced in PIPeiCis.h.
+//
+
+///
+/// This PPI provides the service to report status code.
+/// There can be only one instance of this service in the system.
+///
+typedef struct {
+ EFI_PEI_REPORT_STATUS_CODE ReportStatusCode;
+} EFI_PEI_PROGRESS_CODE_PPI;
+
+extern EFI_GUID gEfiPeiStatusCodePpiGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Ppi/SuperIo.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Ppi/SuperIo.h
new file mode 100644
index 0000000000..7f2c9bb478
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Ppi/SuperIo.h
@@ -0,0 +1,183 @@
+/** @file
+ This PPI provides the super I/O register access functionality.
+
+ Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Revision Reference:
+ This PPI is from PI Version 1.2.1.
+
+**/
+
+#ifndef __EFI_SUPER_IO_PPI_H__
+#define __EFI_SUPER_IO_PPI_H__
+
+#include
+
+#define EFI_SIO_PPI_GUID \
+ { \
+ 0x23a464ad, 0xcb83, 0x48b8, {0x94, 0xab, 0x1a, 0x6f, 0xef, 0xcf, 0xe5, 0x22} \
+ }
+
+typedef struct _EFI_SIO_PPI EFI_SIO_PPI;
+typedef struct _EFI_SIO_PPI *PEFI_SIO_PPI;
+
+typedef UINT16 EFI_SIO_REGISTER;
+#define EFI_SIO_REG(ldn, reg) (EFI_SIO_REGISTER) (((ldn) << 8) | reg)
+#define EFI_SIO_LDN_GLOBAL 0xFF
+
+/**
+ Read a Super I/O register.
+
+ The register is specified as an 8-bit logical device number and an 8-bit
+ register value. The logical device numbers for specific SIO devices can be
+ determined using the Info member of the PPI structure.
+
+ @param PeiServices A pointer to a pointer to the PEI Services.
+ @param This A pointer to this instance of the EFI_SIO_PPI.
+ @param ExitCfgMode A boolean specifying whether the driver should turn on
+ configuration mode (FALSE) or turn off configuration mode
+ (TRUE) after completing the read operation. The driver must
+ track the current state of the configuration mode (if any)
+ and turn on configuration mode (if necessary) prior to
+ register access.
+ @param Register A value specifying the logical device number (bits 15:8)
+ and the register to read (bits 7:0). The logical device
+ number of EFI_SIO_LDN_GLOBAL indicates that global
+ registers will be used.
+ @param IoData A pointer to the returned register value.
+
+ @retval EFI_SUCCESS Success.
+ @retval EFI_TIMEOUT The register could not be read in the a reasonable
+ amount of time. The exact time is device-specific.
+ @retval EFI_INVALID_PARAMETERS Register was out of range for this device.
+ @retval EFI_INVALID_PARAMETERS IoData was NULL
+ @retval EFI_DEVICE_ERROR There was a device fault or the device was not present.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_PEI_SIO_REGISTER_READ)(
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN CONST EFI_SIO_PPI *This,
+ IN BOOLEAN ExitCfgMode,
+ IN EFI_SIO_REGISTER Register,
+ OUT UINT8 *IoData
+ );
+
+/**
+ Write a Super I/O register.
+
+ The register is specified as an 8-bit logical device number and an 8-bit register
+ value. The logical device numbers for specific SIO devices can be determined
+ using the Info member of the PPI structure.
+
+ @param PeiServices A pointer to a pointer to the PEI Services.
+ @param This A pointer to this instance of the EFI_SIO_PPI.
+ @param ExitCfgMode A boolean specifying whether the driver should turn on
+ configuration mode (FALSE) or turn off configuration mode
+ (TRUE) after completing the read operation. The driver must
+ track the current state of the configuration mode (if any)
+ and turn on configuration mode (if necessary) prior to
+ register access.
+ @param Register A value specifying the logical device number (bits 15:8)
+ and the register to read (bits 7:0). The logical device
+ number of EFI_SIO_LDN_GLOBAL indicates that global
+ registers will be used.
+ @param IoData A pointer to the returned register value.
+
+ @retval EFI_SUCCESS Success.
+ @retval EFI_TIMEOUT The register could not be read in the a reasonable
+ amount of time. The exact time is device-specific.
+ @retval EFI_INVALID_PARAMETERS Register was out of range for this device.
+ @retval EFI_INVALID_PARAMETERS IoData was NULL
+ @retval EFI_DEVICE_ERROR There was a device fault or the device was not present.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_PEI_SIO_REGISTER_WRITE)(
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN CONST EFI_SIO_PPI *This,
+ IN BOOLEAN ExitCfgMode,
+ IN EFI_SIO_REGISTER Register,
+ IN UINT8 IoData
+ );
+
+/**
+ Provides an interface for a table based programming of the Super I/O registers.
+
+ The Modify() function provides an interface for table based programming of the
+ Super I/O registers. This function can be used to perform programming of
+ multiple Super I/O registers with a single function call. For each table entry,
+ the Register is read, its content is bitwise ANDed with AndMask, and then ORed
+ with OrMask before being written back to the Register. The Super I/O driver
+ must track the current state of the Super I/O and enable the configuration mode
+ of Super I/O if necessary prior to table processing. Once the table is processed,
+ the Super I/O device must be returned to the original state.
+
+ @param PeiServices A pointer to a pointer to the PEI Services.
+ @param This A pointer to this instance of the EFI_SIO_PPI.
+ @param Command A pointer to an array of NumberOfCommands EFI_SIO_REGISTER_MODIFY
+ structures. Each structure specifies a single Super I/O register
+ modify operation.
+ @param NumberOfCommands The number of elements in the Command array.
+
+ @retval EFI_SUCCESS The operation completed successfully.
+ @retval EFI_INVALID_PARAMETERS Command is NULL.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_PEI_SIO_REGISTER_MODIFY)(
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN CONST EFI_SIO_PPI *This,
+ IN CONST EFI_SIO_REGISTER_MODIFY *Command,
+ IN UINTN NumberOfCommands
+ );
+
+///
+/// Specifies the end of the information list.
+///
+#define EFI_ACPI_PNP_HID_END EFI_PNP_ID (0x0000)
+
+typedef UINT32 EFI_ACPI_HID;
+typedef UINT32 EFI_ACPI_UID;
+#pragma pack(1)
+typedef struct _EFI_SIO_INFO {
+ EFI_ACPI_HID Hid;
+ EFI_ACPI_UID Uid;
+ UINT8 Ldn;
+} EFI_SIO_INFO, *PEFI_SIO_INFO;
+#pragma pack()
+
+///
+/// This PPI provides low-level access to Super I/O registers using Read() and
+/// Write(). It also uniquely identifies this Super I/O controller using a GUID
+/// and provides mappings between ACPI style PNP IDs and the logical device numbers.
+/// There is one instance of this PPI per Super I/O device.
+///
+struct _EFI_SIO_PPI {
+ ///
+ /// This function reads a register's value from the Super I/O controller.
+ ///
+ EFI_PEI_SIO_REGISTER_READ Read;
+ ///
+ /// This function writes a value to a register in the Super I/O controller.
+ ///
+ EFI_PEI_SIO_REGISTER_WRITE Write;
+ ///
+ /// This function modifies zero or more registers in the Super I/O controller
+ /// using a table.
+ ///
+ EFI_PEI_SIO_REGISTER_MODIFY Modify;
+ ///
+ /// This GUID uniquely identifies the Super I/O controller.
+ ///
+ EFI_GUID SioGuid;
+ ///
+ /// This pointer is to an array which maps EISA identifiers to logical devices numbers.
+ ///
+ PEFI_SIO_INFO Info;
+};
+
+extern EFI_GUID gEfiSioPpiGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Ppi/TemporaryRamDone.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Ppi/TemporaryRamDone.h
new file mode 100644
index 0000000000..04468dae03
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Ppi/TemporaryRamDone.h
@@ -0,0 +1,46 @@
+/** @file
+ This file declares Temporary RAM Done PPI.
+ The PPI that provides a service to disable the use of Temporary RAM.
+
+ Copyright (c) 2013 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Revision Reference:
+ This PPI is introduced in PI Version 1.2.1.
+
+**/
+
+#ifndef __TEMPORARY_RAM_DONE_H__
+#define __TEMPORARY_RAM_DONE_H__
+
+#define EFI_PEI_TEMPORARY_RAM_DONE_PPI_GUID \
+ { 0xceab683c, 0xec56, 0x4a2d, { 0xa9, 0x6, 0x40, 0x53, 0xfa, 0x4e, 0x9c, 0x16 } }
+
+/**
+ TemporaryRamDone() disables the use of Temporary RAM. If present, this service is invoked
+ by the PEI Foundation after the EFI_PEI_PERMANENT_MEMORY_INSTALLED_PPI is installed.
+
+ @retval EFI_SUCCESS Use of Temporary RAM was disabled.
+ @retval EFI_INVALID_PARAMETER Temporary RAM could not be disabled.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_PEI_TEMPORARY_RAM_DONE)(
+ VOID
+ );
+
+///
+/// This is an optional PPI that may be produced by SEC or a PEIM. If present, it provide a service to
+/// disable the use of Temporary RAM. This service may only be called by the PEI Foundation after the
+/// transition from Temporary RAM to Permanent RAM is complete. This PPI provides an alternative
+/// to the Temporary RAM Migration PPI for system architectures that allow Temporary RAM and
+/// Permanent RAM to be enabled and accessed at the same time with no side effects.
+///
+typedef struct _EFI_PEI_TEMPORARY_RAM_DONE_PPI {
+ EFI_PEI_TEMPORARY_RAM_DONE TemporaryRamDone;
+} EFI_PEI_TEMPORARY_RAM_DONE_PPI;
+
+extern EFI_GUID gEfiTemporaryRamDonePpiGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Ppi/TemporaryRamSupport.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Ppi/TemporaryRamSupport.h
new file mode 100644
index 0000000000..9d52afdc1e
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Ppi/TemporaryRamSupport.h
@@ -0,0 +1,59 @@
+/** @file
+ This file declares Temporary RAM Support PPI.
+ This Ppi provides the service that migrates temporary RAM into permanent memory.
+
+ Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Revision Reference:
+ This PPI is introduced in PI Version 1.0.
+
+**/
+
+#ifndef __TEMPORARY_RAM_SUPPORT_H__
+#define __TEMPORARY_RAM_SUPPORT_H__
+
+///
+/// Note: The GUID name EFI_PEI_TEMPORARY_RAM_SUPPORT_PPI_GUID is different from the current
+/// PI 1.2 spec.
+///
+#define EFI_PEI_TEMPORARY_RAM_SUPPORT_PPI_GUID \
+ { 0xdbe23aa9, 0xa345, 0x4b97, {0x85, 0xb6, 0xb2, 0x26, 0xf1, 0x61, 0x73, 0x89} }
+
+/**
+ This service of the EFI_PEI_TEMPORARY_RAM_SUPPORT_PPI that migrates temporary RAM into
+ permanent memory.
+
+ @param PeiServices Pointer to the PEI Services Table.
+ @param TemporaryMemoryBase Source Address in temporary memory from which the SEC or PEIM will copy the
+ Temporary RAM contents.
+ @param PermanentMemoryBase Destination Address in permanent memory into which the SEC or PEIM will copy the
+ Temporary RAM contents.
+ @param CopySize Amount of memory to migrate from temporary to permanent memory.
+
+ @retval EFI_SUCCESS The data was successfully returned.
+ @retval EFI_INVALID_PARAMETER PermanentMemoryBase + CopySize > TemporaryMemoryBase when
+ TemporaryMemoryBase > PermanentMemoryBase.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *TEMPORARY_RAM_MIGRATION)(
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PHYSICAL_ADDRESS TemporaryMemoryBase,
+ IN EFI_PHYSICAL_ADDRESS PermanentMemoryBase,
+ IN UINTN CopySize
+ );
+
+///
+/// This service abstracts the ability to migrate contents of the platform early memory store.
+/// Note: The name EFI_PEI_TEMPORARY_RAM_SUPPORT_PPI is different from the current PI 1.2 spec.
+/// This PPI was optional.
+///
+typedef struct {
+ TEMPORARY_RAM_MIGRATION TemporaryRamMigration;
+} EFI_PEI_TEMPORARY_RAM_SUPPORT_PPI;
+
+extern EFI_GUID gEfiTemporaryRamSupportPpiGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Ppi/VectorHandoffInfo.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Ppi/VectorHandoffInfo.h
new file mode 100644
index 0000000000..f13981067e
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Ppi/VectorHandoffInfo.h
@@ -0,0 +1,69 @@
+/** @file
+ This file declares Vector Handoff Info PPI that describes an array of
+ interrupt and/or exception vectors that are in use and need to persist.
+
+ This is an optional PPI that may be produced by SEC. If present, it provides
+ a description of the interrupt and/or exception vectors that were established
+ in the SEC Phase and need to persist into PEI and DXE.
+
+ Copyright (c) 2013 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Revision Reference:
+ This PPI is introduced in PI Version 1.2.1.
+
+**/
+
+#ifndef __VECTOR_HANDOFF_INFO_H__
+#define __VECTOR_HANDOFF_INFO_H__
+
+///
+/// NOTE: EFI_PEI_VECTOR_HANDOFF_INFO_PPI_GUID can also be used in the PEI Phase
+/// to build a GUIDed HOB that contains an array of EFI_VECTOR_HANDOFF_INFO.
+///
+#define EFI_PEI_VECTOR_HANDOFF_INFO_PPI_GUID \
+ { 0x3cd652b4, 0x6d33, 0x4dce, { 0x89, 0xdb, 0x83, 0xdf, 0x97, 0x66, 0xfc, 0xca }}
+
+///
+/// Vector Handoff Info Attributes
+///@{
+#define EFI_VECTOR_HANDOFF_DO_NOT_HOOK 0x00000000
+#define EFI_VECTOR_HANDOFF_HOOK_BEFORE 0x00000001
+#define EFI_VECTOR_HANDOFF_HOOK_AFTER 0x00000002
+#define EFI_VECTOR_HANDOFF_LAST_ENTRY 0x80000000
+///@}
+
+///
+/// EFI_VECTOR_HANDOFF_INFO entries that describes the interrupt and/or
+/// exception vectors in use in the PEI Phase.
+///
+typedef struct {
+ //
+ // The interrupt or exception vector that is in use and must be preserved.
+ //
+ UINT32 VectorNumber;
+ //
+ // A bitmask that describes the attributes of the interrupt or exception vector.
+ //
+ UINT32 Attribute;
+ //
+ // The GUID identifies the party who created the entry. For the
+ // EFI_VECTOR_HANDOFF_DO_NOT_HOOK case, this establishes the single owner.
+ //
+ EFI_GUID Owner;
+} EFI_VECTOR_HANDOFF_INFO;
+
+///
+/// Provides a description of the interrupt and/or exception vectors that
+/// were established in the SEC Phase and need to persist into PEI and DXE.
+///
+typedef struct _EFI_PEI_VECTOR_HANDOFF_INFO_PPI {
+ //
+ // Pointer to an array of interrupt and /or exception vectors.
+ //
+ EFI_VECTOR_HANDOFF_INFO *Info;
+} EFI_PEI_VECTOR_HANDOFF_INFO_PPI;
+
+extern EFI_GUID gEfiVectorHandoffInfoPpiGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/AbsolutePointer.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/AbsolutePointer.h
new file mode 100644
index 0000000000..fbbba9ab32
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/AbsolutePointer.h
@@ -0,0 +1,192 @@
+/** @file
+ The file provides services that allow information about an
+ absolute pointer device to be retrieved.
+
+ Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Revision Reference:
+ This Protocol was introduced in UEFI Specification 2.3.
+
+**/
+
+#ifndef __ABSOLUTE_POINTER_H__
+#define __ABSOLUTE_POINTER_H__
+
+#define EFI_ABSOLUTE_POINTER_PROTOCOL_GUID \
+ { 0x8D59D32B, 0xC655, 0x4AE9, { 0x9B, 0x15, 0xF2, 0x59, 0x04, 0x99, 0x2A, 0x43 } }
+
+typedef struct _EFI_ABSOLUTE_POINTER_PROTOCOL EFI_ABSOLUTE_POINTER_PROTOCOL;
+
+// *******************************************************
+// EFI_ABSOLUTE_POINTER_MODE
+// *******************************************************
+
+/**
+ The following data values in the EFI_ABSOLUTE_POINTER_MODE
+ interface are read-only and are changed by using the appropriate
+ interface functions.
+**/
+typedef struct {
+ UINT64 AbsoluteMinX; ///< The Absolute Minimum of the device on the x-axis
+ UINT64 AbsoluteMinY; ///< The Absolute Minimum of the device on the y axis.
+ UINT64 AbsoluteMinZ; ///< The Absolute Minimum of the device on the z-axis
+ UINT64 AbsoluteMaxX; ///< The Absolute Maximum of the device on the x-axis. If 0, and the
+ ///< AbsoluteMinX is 0, then the pointer device does not support a xaxis
+ UINT64 AbsoluteMaxY; ///< The Absolute Maximum of the device on the y -axis. If 0, and the
+ ///< AbsoluteMinX is 0, then the pointer device does not support a yaxis.
+ UINT64 AbsoluteMaxZ; ///< The Absolute Maximum of the device on the z-axis. If 0 , and the
+ ///< AbsoluteMinX is 0, then the pointer device does not support a zaxis
+ UINT32 Attributes; ///< The following bits are set as needed (or'd together) to indicate the
+ ///< capabilities of the device supported. The remaining bits are undefined
+ ///< and should be 0
+} EFI_ABSOLUTE_POINTER_MODE;
+
+///
+/// If set, indicates this device supports an alternate button input.
+///
+#define EFI_ABSP_SupportsAltActive 0x00000001
+
+///
+/// If set, indicates this device returns pressure data in parameter CurrentZ.
+///
+#define EFI_ABSP_SupportsPressureAsZ 0x00000002
+
+/**
+ This function resets the pointer device hardware. As part of
+ initialization process, the firmware/device will make a quick
+ but reasonable attempt to verify that the device is
+ functioning. If the ExtendedVerification flag is TRUE the
+ firmware may take an extended amount of time to verify the
+ device is operating on reset. Otherwise the reset operation is
+ to occur as quickly as possible. The hardware verification
+ process is not defined by this specification and is left up to
+ the platform firmware or driver to implement.
+
+ @param This A pointer to the EFI_ABSOLUTE_POINTER_PROTOCOL
+ instance.
+
+ @param ExtendedVerification Indicates that the driver may
+ perform a more exhaustive
+ verification operation of the
+ device during reset.
+
+ @retval EFI_SUCCESS The device was reset.
+
+ @retval EFI_DEVICE_ERROR The device is not functioning
+ correctly and could not be reset.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_ABSOLUTE_POINTER_RESET)(
+ IN EFI_ABSOLUTE_POINTER_PROTOCOL *This,
+ IN BOOLEAN ExtendedVerification
+ );
+
+///
+/// This bit is set if the touch sensor is active.
+///
+#define EFI_ABSP_TouchActive 0x00000001
+
+///
+/// This bit is set if the alt sensor, such as pen-side button, is active
+///
+#define EFI_ABS_AltActive 0x00000002
+
+/**
+ Definition of EFI_ABSOLUTE_POINTER_STATE.
+**/
+typedef struct {
+ ///
+ /// The unsigned position of the activation on the x axis. If the AboluteMinX
+ /// and the AboluteMaxX fields of the EFI_ABSOLUTE_POINTER_MODE structure are
+ /// both 0, then this pointer device does not support an x-axis, and this field
+ /// must be ignored.
+ ///
+ UINT64 CurrentX;
+
+ ///
+ /// The unsigned position of the activation on the y axis. If the AboluteMinY
+ /// and the AboluteMaxY fields of the EFI_ABSOLUTE_POINTER_MODE structure are
+ /// both 0, then this pointer device does not support an y-axis, and this field
+ /// must be ignored.
+ ///
+ UINT64 CurrentY;
+
+ ///
+ /// The unsigned position of the activation on the z axis, or the pressure
+ /// measurement. If the AboluteMinZ and the AboluteMaxZ fields of the
+ /// EFI_ABSOLUTE_POINTER_MODE structure are both 0, then this pointer device
+ /// does not support an z-axis, and this field must be ignored.
+ ///
+ UINT64 CurrentZ;
+
+ ///
+ /// Bits are set to 1 in this structure item to indicate that device buttons are
+ /// active.
+ ///
+ UINT32 ActiveButtons;
+} EFI_ABSOLUTE_POINTER_STATE;
+
+/**
+ The GetState() function retrieves the current state of a pointer
+ device. This includes information on the active state associated
+ with the pointer device and the current position of the axes
+ associated with the pointer device. If the state of the pointer
+ device has not changed since the last call to GetState(), then
+ EFI_NOT_READY is returned. If the state of the pointer device
+ has changed since the last call to GetState(), then the state
+ information is placed in State, and EFI_SUCCESS is returned. If
+ a device error occurs while attempting to retrieve the state
+ information, then EFI_DEVICE_ERROR is returned.
+
+
+ @param This A pointer to the EFI_ABSOLUTE_POINTER_PROTOCOL
+ instance.
+
+ @param State A pointer to the state information on the
+ pointer device.
+
+ @retval EFI_SUCCESS The state of the pointer device was
+ returned in State.
+
+ @retval EFI_NOT_READY The state of the pointer device has not
+ changed since the last call to GetState().
+
+ @retval EFI_DEVICE_ERROR A device error occurred while
+ attempting to retrieve the pointer
+ device's current state.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_ABSOLUTE_POINTER_GET_STATE)(
+ IN EFI_ABSOLUTE_POINTER_PROTOCOL *This,
+ OUT EFI_ABSOLUTE_POINTER_STATE *State
+ );
+
+///
+/// The EFI_ABSOLUTE_POINTER_PROTOCOL provides a set of services
+/// for a pointer device that can be used as an input device from an
+/// application written to this specification. The services include
+/// the ability to: reset the pointer device, retrieve the state of
+/// the pointer device, and retrieve the capabilities of the pointer
+/// device. The service also provides certain data items describing the device.
+///
+struct _EFI_ABSOLUTE_POINTER_PROTOCOL {
+ EFI_ABSOLUTE_POINTER_RESET Reset;
+ EFI_ABSOLUTE_POINTER_GET_STATE GetState;
+ ///
+ /// Event to use with WaitForEvent() to wait for input from the pointer device.
+ ///
+ EFI_EVENT WaitForInput;
+ ///
+ /// Pointer to EFI_ABSOLUTE_POINTER_MODE data.
+ ///
+ EFI_ABSOLUTE_POINTER_MODE *Mode;
+};
+
+extern EFI_GUID gEfiAbsolutePointerProtocolGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/AcpiSystemDescriptionTable.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/AcpiSystemDescriptionTable.h
new file mode 100644
index 0000000000..fadfca1215
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/AcpiSystemDescriptionTable.h
@@ -0,0 +1,263 @@
+/** @file
+ This protocol provides services for creating ACPI system description tables.
+
+ Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Revision Reference:
+ This Protocol was introduced in PI Specification 1.2.
+
+**/
+
+#ifndef __ACPI_SYSTEM_DESCRIPTION_TABLE_H___
+#define __ACPI_SYSTEM_DESCRIPTION_TABLE_H___
+
+#define EFI_ACPI_SDT_PROTOCOL_GUID \
+ { 0xeb97088e, 0xcfdf, 0x49c6, { 0xbe, 0x4b, 0xd9, 0x6, 0xa5, 0xb2, 0xe, 0x86 }}
+
+typedef UINT32 EFI_ACPI_TABLE_VERSION;
+typedef VOID *EFI_ACPI_HANDLE;
+
+#define EFI_ACPI_TABLE_VERSION_NONE (1 << 0)
+#define EFI_ACPI_TABLE_VERSION_1_0B (1 << 1)
+#define EFI_ACPI_TABLE_VERSION_2_0 (1 << 2)
+#define EFI_ACPI_TABLE_VERSION_3_0 (1 << 3)
+#define EFI_ACPI_TABLE_VERSION_4_0 (1 << 4)
+#define EFI_ACPI_TABLE_VERSION_5_0 (1 << 5)
+
+typedef UINT32 EFI_ACPI_DATA_TYPE;
+#define EFI_ACPI_DATA_TYPE_NONE 0
+#define EFI_ACPI_DATA_TYPE_OPCODE 1
+#define EFI_ACPI_DATA_TYPE_NAME_STRING 2
+#define EFI_ACPI_DATA_TYPE_OP 3
+#define EFI_ACPI_DATA_TYPE_UINT 4
+#define EFI_ACPI_DATA_TYPE_STRING 5
+#define EFI_ACPI_DATA_TYPE_CHILD 6
+
+typedef struct {
+ UINT32 Signature;
+ UINT32 Length;
+ UINT8 Revision;
+ UINT8 Checksum;
+ CHAR8 OemId[6];
+ CHAR8 OemTableId[8];
+ UINT32 OemRevision;
+ UINT32 CreatorId;
+ UINT32 CreatorRevision;
+} EFI_ACPI_SDT_HEADER;
+
+typedef
+EFI_STATUS
+(EFIAPI *EFI_ACPI_NOTIFICATION_FN)(
+ IN EFI_ACPI_SDT_HEADER *Table, ///< A pointer to the ACPI table header.
+ IN EFI_ACPI_TABLE_VERSION Version, ///< The ACPI table's version.
+ IN UINTN TableKey ///< The table key for this ACPI table.
+ );
+
+/**
+ Returns a requested ACPI table.
+
+ The GetAcpiTable() function returns a pointer to a buffer containing the ACPI table associated
+ with the Index that was input. The following structures are not considered elements in the list of
+ ACPI tables:
+ - Root System Description Pointer (RSD_PTR)
+ - Root System Description Table (RSDT)
+ - Extended System Description Table (XSDT)
+ Version is updated with a bit map containing all the versions of ACPI of which the table is a
+ member. For tables installed via the EFI_ACPI_TABLE_PROTOCOL.InstallAcpiTable() interface,
+ the function returns the value of EFI_ACPI_STD_PROTOCOL.AcpiVersion.
+
+ @param[in] Index The zero-based index of the table to retrieve.
+ @param[out] Table Pointer for returning the table buffer.
+ @param[out] Version On return, updated with the ACPI versions to which this table belongs. Type
+ EFI_ACPI_TABLE_VERSION is defined in "Related Definitions" in the
+ EFI_ACPI_SDT_PROTOCOL.
+ @param[out] TableKey On return, points to the table key for the specified ACPI system definition table.
+ This is identical to the table key used in the EFI_ACPI_TABLE_PROTOCOL.
+ The TableKey can be passed to EFI_ACPI_TABLE_PROTOCOL.UninstallAcpiTable()
+ to uninstall the table.
+
+ @retval EFI_SUCCESS The function completed successfully.
+ @retval EFI_NOT_FOUND The requested index is too large and a table was not found.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_ACPI_GET_ACPI_TABLE2)(
+ IN UINTN Index,
+ OUT EFI_ACPI_SDT_HEADER **Table,
+ OUT EFI_ACPI_TABLE_VERSION *Version,
+ OUT UINTN *TableKey
+ );
+
+/**
+ Register or unregister a callback when an ACPI table is installed.
+
+ This function registers or unregisters a function which will be called whenever a new ACPI table is
+ installed.
+
+ @param[in] Register If TRUE, then the specified function will be registered. If FALSE, then the specified
+ function will be unregistered.
+ @param[in] Notification Points to the callback function to be registered or unregistered.
+
+ @retval EFI_SUCCESS Callback successfully registered or unregistered.
+ @retval EFI_INVALID_PARAMETER Notification is NULL
+ @retval EFI_INVALID_PARAMETER Register is FALSE and Notification does not match a known registration function.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_ACPI_REGISTER_NOTIFY)(
+ IN BOOLEAN Register,
+ IN EFI_ACPI_NOTIFICATION_FN Notification
+ );
+
+/**
+ Create a handle from an ACPI opcode
+
+ @param[in] Buffer Points to the ACPI opcode.
+ @param[out] Handle Upon return, holds the handle.
+
+ @retval EFI_SUCCESS Success
+ @retval EFI_INVALID_PARAMETER Buffer is NULL or Handle is NULL or Buffer points to an
+ invalid opcode.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_ACPI_OPEN)(
+ IN VOID *Buffer,
+ OUT EFI_ACPI_HANDLE *Handle
+ );
+
+/**
+ Create a handle for the first ACPI opcode in an ACPI system description table.
+
+ @param[in] TableKey The table key for the ACPI table, as returned by GetTable().
+ @param[out] Handle On return, points to the newly created ACPI handle.
+
+ @retval EFI_SUCCESS Handle created successfully.
+ @retval EFI_NOT_FOUND TableKey does not refer to a valid ACPI table.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_ACPI_OPEN_SDT)(
+ IN UINTN TableKey,
+ OUT EFI_ACPI_HANDLE *Handle
+ );
+
+/**
+ Close an ACPI handle.
+
+ @param[in] Handle Returns the handle.
+
+ @retval EFI_SUCCESS Success
+ @retval EFI_INVALID_PARAMETER Handle is NULL or does not refer to a valid ACPI object.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_ACPI_CLOSE)(
+ IN EFI_ACPI_HANDLE Handle
+ );
+
+/**
+ Return the child ACPI objects.
+
+ @param[in] ParentHandle Parent handle.
+ @param[in, out] Handle On entry, points to the previously returned handle or NULL to start with the first
+ handle. On return, points to the next returned ACPI handle or NULL if there are no
+ child objects.
+
+ @retval EFI_SUCCESS Success
+ @retval EFI_INVALID_PARAMETER ParentHandle is NULL or does not refer to a valid ACPI object.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_ACPI_GET_CHILD)(
+ IN EFI_ACPI_HANDLE ParentHandle,
+ IN OUT EFI_ACPI_HANDLE *Handle
+ );
+
+/**
+ Retrieve information about an ACPI object.
+
+ @param[in] Handle ACPI object handle.
+ @param[in] Index Index of the data to retrieve from the object. In general, indexes read from left-to-right
+ in the ACPI encoding, with index 0 always being the ACPI opcode.
+ @param[out] DataType Points to the returned data type or EFI_ACPI_DATA_TYPE_NONE if no data exists
+ for the specified index.
+ @param[out] Data Upon return, points to the pointer to the data.
+ @param[out] DataSize Upon return, points to the size of Data.
+
+ @retval
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_ACPI_GET_OPTION)(
+ IN EFI_ACPI_HANDLE Handle,
+ IN UINTN Index,
+ OUT EFI_ACPI_DATA_TYPE *DataType,
+ OUT CONST VOID **Data,
+ OUT UINTN *DataSize
+ );
+
+/**
+ Change information about an ACPI object.
+
+ @param[in] Handle ACPI object handle.
+ @param[in] Index Index of the data to retrieve from the object. In general, indexes read from left-to-right
+ in the ACPI encoding, with index 0 always being the ACPI opcode.
+ @param[in] Data Points to the data.
+ @param[in] DataSize The size of the Data.
+
+ @retval EFI_SUCCESS Success
+ @retval EFI_INVALID_PARAMETER Handle is NULL or does not refer to a valid ACPI object.
+ @retval EFI_BAD_BUFFER_SIZE Data cannot be accommodated in the space occupied by
+ the option.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_ACPI_SET_OPTION)(
+ IN EFI_ACPI_HANDLE Handle,
+ IN UINTN Index,
+ IN CONST VOID *Data,
+ IN UINTN DataSize
+ );
+
+/**
+ Returns the handle of the ACPI object representing the specified ACPI path
+
+ @param[in] HandleIn Points to the handle of the object representing the starting point for the path search.
+ @param[in] AcpiPath Points to the ACPI path, which conforms to the ACPI encoded path format.
+ @param[out] HandleOut On return, points to the ACPI object which represents AcpiPath, relative to
+ HandleIn.
+
+ @retval EFI_SUCCESS Success
+ @retval EFI_INVALID_PARAMETER HandleIn is NULL or does not refer to a valid ACPI object.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_ACPI_FIND_PATH)(
+ IN EFI_ACPI_HANDLE HandleIn,
+ IN VOID *AcpiPath,
+ OUT EFI_ACPI_HANDLE *HandleOut
+ );
+
+typedef struct _EFI_ACPI_SDT_PROTOCOL {
+ ///
+ /// A bit map containing all the ACPI versions supported by this protocol.
+ ///
+ EFI_ACPI_TABLE_VERSION AcpiVersion;
+ EFI_ACPI_GET_ACPI_TABLE2 GetAcpiTable;
+ EFI_ACPI_REGISTER_NOTIFY RegisterNotify;
+ EFI_ACPI_OPEN Open;
+ EFI_ACPI_OPEN_SDT OpenSdt;
+ EFI_ACPI_CLOSE Close;
+ EFI_ACPI_GET_CHILD GetChild;
+ EFI_ACPI_GET_OPTION GetOption;
+ EFI_ACPI_SET_OPTION SetOption;
+ EFI_ACPI_FIND_PATH FindPath;
+} EFI_ACPI_SDT_PROTOCOL;
+
+extern EFI_GUID gEfiAcpiSdtProtocolGuid;
+
+#endif // __ACPI_SYSTEM_DESCRIPTION_TABLE_H___
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/AcpiTable.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/AcpiTable.h
new file mode 100644
index 0000000000..d5143b271a
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/AcpiTable.h
@@ -0,0 +1,121 @@
+/** @file
+ The file provides the protocol to install or remove an ACPI
+ table from a platform.
+
+ Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Revision Reference:
+ This Protocol was introduced in UEFI Specification 2.3.
+
+**/
+
+#ifndef __ACPI_TABLE_H___
+#define __ACPI_TABLE_H___
+
+#define EFI_ACPI_TABLE_PROTOCOL_GUID \
+ { 0xffe06bdd, 0x6107, 0x46a6, { 0x7b, 0xb2, 0x5a, 0x9c, 0x7e, 0xc5, 0x27, 0x5c }}
+
+typedef struct _EFI_ACPI_TABLE_PROTOCOL EFI_ACPI_TABLE_PROTOCOL;
+
+/**
+
+ The InstallAcpiTable() function allows a caller to install an
+ ACPI table. When successful, the table will be linked by the
+ RSDT/XSDT. AcpiTableBuffer specifies the table to be installed.
+ InstallAcpiTable() will make a copy of the table and insert the
+ copy into the RSDT/XSDT. InstallAcpiTable() must insert the new
+ table at the end of the RSDT/XSDT. To prevent namespace
+ collision, ACPI tables may be created using UEFI ACPI table
+ format. If this protocol is used to install a table with a
+ signature already present in the system, the new table will not
+ replace the existing table. It is a platform implementation
+ decision to add a new table with a signature matching an
+ existing table or disallow duplicate table signatures and
+ return EFI_ACCESS_DENIED. On successful output, TableKey is
+ initialized with a unique key. Its value may be used in a
+ subsequent call to UninstallAcpiTable to remove an ACPI table.
+ If an EFI application is running at the time of this call, the
+ relevant EFI_CONFIGURATION_TABLE pointer to the RSDT is no
+ longer considered valid.
+
+
+ @param This A pointer to a EFI_ACPI_TABLE_PROTOCOL.
+
+ @param AcpiTableBuffer A pointer to a buffer containing the
+ ACPI table to be installed.
+
+ @param AcpiTableBufferSize Specifies the size, in bytes, of
+ the AcpiTableBuffer buffer.
+
+
+ @param TableKey Returns a key to refer to the ACPI table.
+
+ @retval EFI_SUCCESS The table was successfully inserted
+
+ @retval EFI_INVALID_PARAMETER Either AcpiTableBuffer is NULL,
+ TableKey is NULL, or
+ AcpiTableBufferSize and the size
+ field embedded in the ACPI table
+ pointed to by AcpiTableBuffer
+ are not in sync.
+
+ @retval EFI_OUT_OF_RESOURCES Insufficient resources exist to
+ complete the request.
+ @retval EFI_ACCESS_DENIED The table signature matches a table already
+ present in the system and platform policy
+ does not allow duplicate tables of this type.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_ACPI_TABLE_INSTALL_ACPI_TABLE)(
+ IN EFI_ACPI_TABLE_PROTOCOL *This,
+ IN VOID *AcpiTableBuffer,
+ IN UINTN AcpiTableBufferSize,
+ OUT UINTN *TableKey
+ );
+
+/**
+
+ The UninstallAcpiTable() function allows a caller to remove an
+ ACPI table. The routine will remove its reference from the
+ RSDT/XSDT. A table is referenced by the TableKey parameter
+ returned from a prior call to InstallAcpiTable(). If an EFI
+ application is running at the time of this call, the relevant
+ EFI_CONFIGURATION_TABLE pointer to the RSDT is no longer
+ considered valid.
+
+ @param This A pointer to a EFI_ACPI_TABLE_PROTOCOL.
+
+ @param TableKey Specifies the table to uninstall. The key was
+ returned from InstallAcpiTable().
+
+ @retval EFI_SUCCESS The table was successfully inserted
+
+ @retval EFI_NOT_FOUND TableKey does not refer to a valid key
+ for a table entry.
+
+ @retval EFI_OUT_OF_RESOURCES Insufficient resources exist to
+ complete the request.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_ACPI_TABLE_UNINSTALL_ACPI_TABLE)(
+ IN EFI_ACPI_TABLE_PROTOCOL *This,
+ IN UINTN TableKey
+ );
+
+///
+/// The EFI_ACPI_TABLE_PROTOCOL provides the ability for a component
+/// to install and uninstall ACPI tables from a platform.
+///
+struct _EFI_ACPI_TABLE_PROTOCOL {
+ EFI_ACPI_TABLE_INSTALL_ACPI_TABLE InstallAcpiTable;
+ EFI_ACPI_TABLE_UNINSTALL_ACPI_TABLE UninstallAcpiTable;
+};
+
+extern EFI_GUID gEfiAcpiTableProtocolGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/AdapterInformation.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/AdapterInformation.h
new file mode 100644
index 0000000000..638d57e810
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/AdapterInformation.h
@@ -0,0 +1,252 @@
+/** @file
+ EFI Adapter Information Protocol definition.
+ The EFI Adapter Information Protocol is used to dynamically and quickly discover
+ or set device information for an adapter.
+
+ Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Revision Reference:
+ This Protocol is introduced in UEFI Specification 2.4
+
+**/
+
+#ifndef __EFI_ADAPTER_INFORMATION_PROTOCOL_H__
+#define __EFI_ADAPTER_INFORMATION_PROTOCOL_H__
+
+#define EFI_ADAPTER_INFORMATION_PROTOCOL_GUID \
+ { \
+ 0xE5DD1403, 0xD622, 0xC24E, {0x84, 0x88, 0xC7, 0x1B, 0x17, 0xF5, 0xE8, 0x02 } \
+ }
+
+#define EFI_ADAPTER_INFO_MEDIA_STATE_GUID \
+ { \
+ 0xD7C74207, 0xA831, 0x4A26, {0xB1, 0xF5, 0xD1, 0x93, 0x06, 0x5C, 0xE8, 0xB6 } \
+ }
+
+#define EFI_ADAPTER_INFO_NETWORK_BOOT_GUID \
+ { \
+ 0x1FBD2960, 0x4130, 0x41E5, {0x94, 0xAC, 0xD2, 0xCF, 0x03, 0x7F, 0xB3, 0x7C } \
+ }
+
+#define EFI_ADAPTER_INFO_SAN_MAC_ADDRESS_GUID \
+ { \
+ 0x114da5ef, 0x2cf1, 0x4e12, {0x9b, 0xbb, 0xc4, 0x70, 0xb5, 0x52, 0x5, 0xd9 } \
+ }
+
+#define EFI_ADAPTER_INFO_UNDI_IPV6_SUPPORT_GUID \
+ { \
+ 0x4bd56be3, 0x4975, 0x4d8a, {0xa0, 0xad, 0xc4, 0x91, 0x20, 0x4b, 0x5d, 0x4d} \
+ }
+
+#define EFI_ADAPTER_INFO_MEDIA_TYPE_GUID \
+ { \
+ 0x8484472f, 0x71ec, 0x411a, { 0xb3, 0x9c, 0x62, 0xcd, 0x94, 0xd9, 0x91, 0x6e } \
+ }
+
+typedef struct _EFI_ADAPTER_INFORMATION_PROTOCOL EFI_ADAPTER_INFORMATION_PROTOCOL;
+
+///
+/// EFI_ADAPTER_INFO_MEDIA_STATE
+///
+typedef struct {
+ ///
+ /// Returns the current media state status. MediaState can have any of the following values:
+ /// EFI_SUCCESS: There is media attached to the network adapter. EFI_NOT_READY: This detects a bounced state.
+ /// There was media attached to the network adapter, but it was removed and reattached. EFI_NO_MEDIA: There is
+ /// not any media attached to the network.
+ ///
+ EFI_STATUS MediaState;
+} EFI_ADAPTER_INFO_MEDIA_STATE;
+
+///
+/// EFI_ADAPTER_INFO_MEDIA_TYPE
+///
+typedef struct {
+ ///
+ /// Indicates the current media type. MediaType can have any of the following values:
+ /// 1: Ethernet Network Adapter
+ /// 2: Ethernet Wireless Network Adapter
+ /// 3~255: Reserved
+ ///
+ UINT8 MediaType;
+} EFI_ADAPTER_INFO_MEDIA_TYPE;
+
+///
+/// EFI_ADAPTER_INFO_NETWORK_BOOT
+///
+typedef struct {
+ ///
+ /// TRUE if the adapter supports booting from iSCSI IPv4 targets.
+ ///
+ BOOLEAN iScsiIpv4BootCapablity;
+ ///
+ /// TRUE if the adapter supports booting from iSCSI IPv6 targets.
+ ///
+ BOOLEAN iScsiIpv6BootCapablity;
+ ///
+ /// TRUE if the adapter supports booting from FCoE targets.
+ ///
+ BOOLEAN FCoeBootCapablity;
+ ///
+ /// TRUE if the adapter supports an offload engine (such as TCP
+ /// Offload Engine (TOE)) for its iSCSI or FCoE boot operations.
+ ///
+ BOOLEAN OffloadCapability;
+ ///
+ /// TRUE if the adapter supports multipath I/O (MPIO) for its iSCSI
+ /// boot operations.
+ ///
+ BOOLEAN iScsiMpioCapability;
+ ///
+ /// TRUE if the adapter is currently configured to boot from iSCSI
+ /// IPv4 targets.
+ ///
+ BOOLEAN iScsiIpv4Boot;
+ ///
+ /// TRUE if the adapter is currently configured to boot from iSCSI
+ /// IPv6 targets.
+ ///
+ BOOLEAN iScsiIpv6Boot;
+ ///
+ /// TRUE if the adapter is currently configured to boot from FCoE targets.
+ ///
+ BOOLEAN FCoeBoot;
+} EFI_ADAPTER_INFO_NETWORK_BOOT;
+
+///
+/// EFI_ADAPTER_INFO_SAN_MAC_ADDRESS
+///
+typedef struct {
+ ///
+ /// Returns the SAN MAC address for the adapter.For adapters that support today's 802.3 ethernet
+ /// networking and Fibre-Channel Over Ethernet (FCOE), this conveys the FCOE SAN MAC address from the adapter.
+ ///
+ EFI_MAC_ADDRESS SanMacAddress;
+} EFI_ADAPTER_INFO_SAN_MAC_ADDRESS;
+
+///
+/// EFI_ADAPTER_INFO_UNDI_IPV6_SUPPORT
+///
+typedef struct {
+ ///
+ /// Returns capability of UNDI to support IPv6 traffic.
+ ///
+ BOOLEAN Ipv6Support;
+} EFI_ADAPTER_INFO_UNDI_IPV6_SUPPORT;
+
+/**
+ Returns the current state information for the adapter.
+
+ This function returns information of type InformationType from the adapter.
+ If an adapter does not support the requested informational type, then
+ EFI_UNSUPPORTED is returned.
+
+ @param[in] This A pointer to the EFI_ADAPTER_INFORMATION_PROTOCOL instance.
+ @param[in] InformationType A pointer to an EFI_GUID that defines the contents of InformationBlock.
+ @param[out] InforamtionBlock The service returns a pointer to the buffer with the InformationBlock
+ structure which contains details about the data specific to InformationType.
+ @param[out] InforamtionBlockSize The driver returns the size of the InformationBlock in bytes.
+
+ @retval EFI_SUCCESS The InformationType information was retrieved.
+ @retval EFI_UNSUPPORTED The InformationType is not known.
+ @retval EFI_DEVICE_ERROR The device reported an error.
+ @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
+ @retval EFI_INVALID_PARAMETER This is NULL.
+ @retval EFI_INVALID_PARAMETER InformationBlock is NULL.
+ @retval EFI_INVALID_PARAMETER InformationBlockSize is NULL.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_ADAPTER_INFO_GET_INFO)(
+ IN EFI_ADAPTER_INFORMATION_PROTOCOL *This,
+ IN EFI_GUID *InformationType,
+ OUT VOID **InformationBlock,
+ OUT UINTN *InformationBlockSize
+ );
+
+/**
+ Sets state information for an adapter.
+
+ This function sends information of type InformationType for an adapter.
+ If an adapter does not support the requested information type, then EFI_UNSUPPORTED
+ is returned.
+
+ @param[in] This A pointer to the EFI_ADAPTER_INFORMATION_PROTOCOL instance.
+ @param[in] InformationType A pointer to an EFI_GUID that defines the contents of InformationBlock.
+ @param[in] InforamtionBlock A pointer to the InformationBlock structure which contains details
+ about the data specific to InformationType.
+ @param[in] InforamtionBlockSize The size of the InformationBlock in bytes.
+
+ @retval EFI_SUCCESS The information was received and interpreted successfully.
+ @retval EFI_UNSUPPORTED The InformationType is not known.
+ @retval EFI_DEVICE_ERROR The device reported an error.
+ @retval EFI_INVALID_PARAMETER This is NULL.
+ @retval EFI_INVALID_PARAMETER InformationBlock is NULL.
+ @retval EFI_WRITE_PROTECTED The InformationType cannot be modified using EFI_ADAPTER_INFO_SET_INFO().
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_ADAPTER_INFO_SET_INFO)(
+ IN EFI_ADAPTER_INFORMATION_PROTOCOL *This,
+ IN EFI_GUID *InformationType,
+ IN VOID *InformationBlock,
+ IN UINTN InformationBlockSize
+ );
+
+/**
+ Get a list of supported information types for this instance of the protocol.
+
+ This function returns a list of InformationType GUIDs that are supported on an
+ adapter with this instance of EFI_ADAPTER_INFORMATION_PROTOCOL. The list is returned
+ in InfoTypesBuffer, and the number of GUID pointers in InfoTypesBuffer is returned in
+ InfoTypesBufferCount.
+
+ @param[in] This A pointer to the EFI_ADAPTER_INFORMATION_PROTOCOL instance.
+ @param[out] InfoTypesBuffer A pointer to the array of InformationType GUIDs that are supported
+ by This.
+ @param[out] InfoTypesBufferCount A pointer to the number of GUIDs present in InfoTypesBuffer.
+
+ @retval EFI_SUCCESS The list of information type GUIDs that are supported on this adapter was
+ returned in InfoTypesBuffer. The number of information type GUIDs was
+ returned in InfoTypesBufferCount.
+ @retval EFI_INVALID_PARAMETER This is NULL.
+ @retval EFI_INVALID_PARAMETER InfoTypesBuffer is NULL.
+ @retval EFI_INVALID_PARAMETER InfoTypesBufferCount is NULL.
+ @retval EFI_OUT_OF_RESOURCES There is not enough pool memory to store the results.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_ADAPTER_INFO_GET_SUPPORTED_TYPES)(
+ IN EFI_ADAPTER_INFORMATION_PROTOCOL *This,
+ OUT EFI_GUID **InfoTypesBuffer,
+ OUT UINTN *InfoTypesBufferCount
+ );
+
+///
+/// EFI_ADAPTER_INFORMATION_PROTOCOL
+/// The protocol for adapter provides the following services.
+/// - Gets device state information from adapter.
+/// - Sets device information for adapter.
+/// - Gets a list of supported information types for this instance of the protocol.
+///
+struct _EFI_ADAPTER_INFORMATION_PROTOCOL {
+ EFI_ADAPTER_INFO_GET_INFO GetInformation;
+ EFI_ADAPTER_INFO_SET_INFO SetInformation;
+ EFI_ADAPTER_INFO_GET_SUPPORTED_TYPES GetSupportedTypes;
+};
+
+extern EFI_GUID gEfiAdapterInformationProtocolGuid;
+
+extern EFI_GUID gEfiAdapterInfoMediaStateGuid;
+
+extern EFI_GUID gEfiAdapterInfoNetworkBootGuid;
+
+extern EFI_GUID gEfiAdapterInfoSanMacAddressGuid;
+
+extern EFI_GUID gEfiAdapterInfoUndiIpv6SupportGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/Arp.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/Arp.h
new file mode 100644
index 0000000000..b250a6f42e
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/Arp.h
@@ -0,0 +1,376 @@
+/** @file
+ EFI ARP Protocol Definition
+
+ The EFI ARP Service Binding Protocol is used to locate EFI
+ ARP Protocol drivers to create and destroy child of the
+ driver to communicate with other host using ARP protocol.
+ The EFI ARP Protocol provides services to map IP network
+ address to hardware address used by a data link protocol.
+
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Revision Reference:
+ This Protocol was introduced in UEFI Specification 2.0.
+
+**/
+
+#ifndef __EFI_ARP_PROTOCOL_H__
+#define __EFI_ARP_PROTOCOL_H__
+
+#define EFI_ARP_SERVICE_BINDING_PROTOCOL_GUID \
+ { \
+ 0xf44c00ee, 0x1f2c, 0x4a00, {0xaa, 0x9, 0x1c, 0x9f, 0x3e, 0x8, 0x0, 0xa3 } \
+ }
+
+#define EFI_ARP_PROTOCOL_GUID \
+ { \
+ 0xf4b427bb, 0xba21, 0x4f16, {0xbc, 0x4e, 0x43, 0xe4, 0x16, 0xab, 0x61, 0x9c } \
+ }
+
+typedef struct _EFI_ARP_PROTOCOL EFI_ARP_PROTOCOL;
+
+typedef struct {
+ ///
+ /// Length in bytes of this entry.
+ ///
+ UINT32 Size;
+
+ ///
+ /// Set to TRUE if this entry is a "deny" entry.
+ /// Set to FALSE if this entry is a "normal" entry.
+ ///
+ BOOLEAN DenyFlag;
+
+ ///
+ /// Set to TRUE if this entry will not time out.
+ /// Set to FALSE if this entry will time out.
+ ///
+ BOOLEAN StaticFlag;
+
+ ///
+ /// 16-bit ARP hardware identifier number.
+ ///
+ UINT16 HwAddressType;
+
+ ///
+ /// 16-bit protocol type number.
+ ///
+ UINT16 SwAddressType;
+
+ ///
+ /// The length of the hardware address.
+ ///
+ UINT8 HwAddressLength;
+
+ ///
+ /// The length of the protocol address.
+ ///
+ UINT8 SwAddressLength;
+} EFI_ARP_FIND_DATA;
+
+typedef struct {
+ ///
+ /// 16-bit protocol type number in host byte order.
+ ///
+ UINT16 SwAddressType;
+
+ ///
+ /// The length in bytes of the station's protocol address to register.
+ ///
+ UINT8 SwAddressLength;
+
+ ///
+ /// The pointer to the first byte of the protocol address to register. For
+ /// example, if SwAddressType is 0x0800 (IP), then
+ /// StationAddress points to the first byte of this station's IP
+ /// address stored in network byte order.
+ ///
+ VOID *StationAddress;
+
+ ///
+ /// The timeout value in 100-ns units that is associated with each
+ /// new dynamic ARP cache entry. If it is set to zero, the value is
+ /// implementation-specific.
+ ///
+ UINT32 EntryTimeOut;
+
+ ///
+ /// The number of retries before a MAC address is resolved. If it is
+ /// set to zero, the value is implementation-specific.
+ ///
+ UINT32 RetryCount;
+
+ ///
+ /// The timeout value in 100-ns units that is used to wait for the ARP
+ /// reply packet or the timeout value between two retries. Set to zero
+ /// to use implementation-specific value.
+ ///
+ UINT32 RetryTimeOut;
+} EFI_ARP_CONFIG_DATA;
+
+/**
+ This function is used to assign a station address to the ARP cache for this instance
+ of the ARP driver.
+
+ Each ARP instance has one station address. The EFI_ARP_PROTOCOL driver will
+ respond to ARP requests that match this registered station address. A call to
+ this function with the ConfigData field set to NULL will reset this ARP instance.
+
+ Once a protocol type and station address have been assigned to this ARP instance,
+ all the following ARP functions will use this information. Attempting to change
+ the protocol type or station address to a configured ARP instance will result in errors.
+
+ @param This The pointer to the EFI_ARP_PROTOCOL instance.
+ @param ConfigData The pointer to the EFI_ARP_CONFIG_DATA structure.
+
+ @retval EFI_SUCCESS The new station address was successfully
+ registered.
+ @retval EFI_INVALID_PARAMETER One or more of the following conditions is TRUE:
+ * This is NULL.
+ * SwAddressLength is zero when ConfigData is not NULL.
+ * StationAddress is NULL when ConfigData is not NULL.
+ @retval EFI_ACCESS_DENIED The SwAddressType, SwAddressLength, or
+ StationAddress is different from the one that is
+ already registered.
+ @retval EFI_OUT_OF_RESOURCES Storage for the new StationAddress could not be
+ allocated.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_ARP_CONFIGURE)(
+ IN EFI_ARP_PROTOCOL *This,
+ IN EFI_ARP_CONFIG_DATA *ConfigData OPTIONAL
+ );
+
+/**
+ This function is used to insert entries into the ARP cache.
+
+ ARP cache entries are typically inserted and updated by network protocol drivers
+ as network traffic is processed. Most ARP cache entries will time out and be
+ deleted if the network traffic stops. ARP cache entries that were inserted
+ by the Add() function may be static (will not time out) or dynamic (will time out).
+ Default ARP cache timeout values are not covered in most network protocol
+ specifications (although RFC 1122 comes pretty close) and will only be
+ discussed in general terms in this specification. The timeout values that are
+ used in the EFI Sample Implementation should be used only as a guideline.
+ Final product implementations of the EFI network stack should be tuned for
+ their expected network environments.
+
+ @param This Pointer to the EFI_ARP_PROTOCOL instance.
+ @param DenyFlag Set to TRUE if this entry is a deny entry. Set to
+ FALSE if this entry is a normal entry.
+ @param TargetSwAddress Pointer to a protocol address to add (or deny).
+ May be set to NULL if DenyFlag is TRUE.
+ @param TargetHwAddress Pointer to a hardware address to add (or deny).
+ May be set to NULL if DenyFlag is TRUE.
+ @param TimeoutValue Time in 100-ns units that this entry will remain
+ in the ARP cache. A value of zero means that the
+ entry is permanent. A nonzero value will override
+ the one given by Configure() if the entry to be
+ added is a dynamic entry.
+ @param Overwrite If TRUE, the matching cache entry will be
+ overwritten with the supplied parameters. If
+ FALSE, EFI_ACCESS_DENIED is returned if the
+ corresponding cache entry already exists.
+
+ @retval EFI_SUCCESS The entry has been added or updated.
+ @retval EFI_INVALID_PARAMETER One or more of the following conditions is TRUE:
+ * This is NULL.
+ * DenyFlag is FALSE and TargetHwAddress is NULL.
+ * DenyFlag is FALSE and TargetSwAddress is NULL.
+ * TargetHwAddress is NULL and TargetSwAddress is NULL.
+ * Neither TargetSwAddress nor TargetHwAddress are NULL when DenyFlag is
+ TRUE.
+ @retval EFI_OUT_OF_RESOURCES The new ARP cache entry could not be allocated.
+ @retval EFI_ACCESS_DENIED The ARP cache entry already exists and Overwrite
+ is not true.
+ @retval EFI_NOT_STARTED The ARP driver instance has not been configured.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_ARP_ADD)(
+ IN EFI_ARP_PROTOCOL *This,
+ IN BOOLEAN DenyFlag,
+ IN VOID *TargetSwAddress OPTIONAL,
+ IN VOID *TargetHwAddress OPTIONAL,
+ IN UINT32 TimeoutValue,
+ IN BOOLEAN Overwrite
+ );
+
+/**
+ This function searches the ARP cache for matching entries and allocates a buffer into
+ which those entries are copied.
+
+ The first part of the allocated buffer is EFI_ARP_FIND_DATA, following which
+ are protocol address pairs and hardware address pairs.
+ When finding a specific protocol address (BySwAddress is TRUE and AddressBuffer
+ is not NULL), the ARP cache timeout for the found entry is reset if Refresh is
+ set to TRUE. If the found ARP cache entry is a permanent entry, it is not
+ affected by Refresh.
+
+ @param This The pointer to the EFI_ARP_PROTOCOL instance.
+ @param BySwAddress Set to TRUE to look for matching software protocol
+ addresses. Set to FALSE to look for matching
+ hardware protocol addresses.
+ @param AddressBuffer The pointer to the address buffer. Set to NULL
+ to match all addresses.
+ @param EntryLength The size of an entry in the entries buffer.
+ @param EntryCount The number of ARP cache entries that are found by
+ the specified criteria.
+ @param Entries The pointer to the buffer that will receive the ARP
+ cache entries.
+ @param Refresh Set to TRUE to refresh the timeout value of the
+ matching ARP cache entry.
+
+ @retval EFI_SUCCESS The requested ARP cache entries were copied into
+ the buffer.
+ @retval EFI_INVALID_PARAMETER One or more of the following conditions is TRUE:
+ This is NULL. Both EntryCount and EntryLength are
+ NULL, when Refresh is FALSE.
+ @retval EFI_NOT_FOUND No matching entries were found.
+ @retval EFI_NOT_STARTED The ARP driver instance has not been configured.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_ARP_FIND)(
+ IN EFI_ARP_PROTOCOL *This,
+ IN BOOLEAN BySwAddress,
+ IN VOID *AddressBuffer OPTIONAL,
+ OUT UINT32 *EntryLength OPTIONAL,
+ OUT UINT32 *EntryCount OPTIONAL,
+ OUT EFI_ARP_FIND_DATA **Entries OPTIONAL,
+ IN BOOLEAN Refresh
+ );
+
+/**
+ This function removes specified ARP cache entries.
+
+ @param This The pointer to the EFI_ARP_PROTOCOL instance.
+ @param BySwAddress Set to TRUE to delete matching protocol addresses.
+ Set to FALSE to delete matching hardware
+ addresses.
+ @param AddressBuffer The pointer to the address buffer that is used as a
+ key to look for the cache entry. Set to NULL to
+ delete all entries.
+
+ @retval EFI_SUCCESS The entry was removed from the ARP cache.
+ @retval EFI_INVALID_PARAMETER This is NULL.
+ @retval EFI_NOT_FOUND The specified deletion key was not found.
+ @retval EFI_NOT_STARTED The ARP driver instance has not been configured.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_ARP_DELETE)(
+ IN EFI_ARP_PROTOCOL *This,
+ IN BOOLEAN BySwAddress,
+ IN VOID *AddressBuffer OPTIONAL
+ );
+
+/**
+ This function delete all dynamic entries from the ARP cache that match the specified
+ software protocol type.
+
+ @param This The pointer to the EFI_ARP_PROTOCOL instance.
+
+ @retval EFI_SUCCESS The cache has been flushed.
+ @retval EFI_INVALID_PARAMETER This is NULL.
+ @retval EFI_NOT_FOUND There are no matching dynamic cache entries.
+ @retval EFI_NOT_STARTED The ARP driver instance has not been configured.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_ARP_FLUSH)(
+ IN EFI_ARP_PROTOCOL *This
+ );
+
+/**
+ This function tries to resolve the TargetSwAddress and optionally returns a
+ TargetHwAddress if it already exists in the ARP cache.
+
+ @param This The pointer to the EFI_ARP_PROTOCOL instance.
+ @param TargetSwAddress The pointer to the protocol address to resolve.
+ @param ResolvedEvent The pointer to the event that will be signaled when
+ the address is resolved or some error occurs.
+ @param TargetHwAddress The pointer to the buffer for the resolved hardware
+ address in network byte order.
+
+ @retval EFI_SUCCESS The data is copied from the ARP cache into the
+ TargetHwAddress buffer.
+ @retval EFI_INVALID_PARAMETER One or more of the following conditions is TRUE:
+ This is NULL. TargetHwAddress is NULL.
+ @retval EFI_ACCESS_DENIED The requested address is not present in the normal
+ ARP cache but is present in the deny address list.
+ Outgoing traffic to that address is forbidden.
+ @retval EFI_NOT_STARTED The ARP driver instance has not been configured.
+ @retval EFI_NOT_READY The request has been started and is not finished.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_ARP_REQUEST)(
+ IN EFI_ARP_PROTOCOL *This,
+ IN VOID *TargetSwAddress OPTIONAL,
+ IN EFI_EVENT ResolvedEvent OPTIONAL,
+ OUT VOID *TargetHwAddress
+ );
+
+/**
+ This function aborts the previous ARP request (identified by This, TargetSwAddress
+ and ResolvedEvent) that is issued by EFI_ARP_PROTOCOL.Request().
+
+ If the request is in the internal ARP request queue, the request is aborted
+ immediately and its ResolvedEvent is signaled. Only an asynchronous address
+ request needs to be canceled. If TargeSwAddress and ResolveEvent are both
+ NULL, all the pending asynchronous requests that have been issued by This
+ instance will be cancelled and their corresponding events will be signaled.
+
+ @param This The pointer to the EFI_ARP_PROTOCOL instance.
+ @param TargetSwAddress The pointer to the protocol address in previous
+ request session.
+ @param ResolvedEvent Pointer to the event that is used as the
+ notification event in previous request session.
+
+ @retval EFI_SUCCESS The pending request session(s) is/are aborted and
+ corresponding event(s) is/are signaled.
+ @retval EFI_INVALID_PARAMETER One or more of the following conditions is TRUE:
+ This is NULL. TargetSwAddress is not NULL and
+ ResolvedEvent is NULL. TargetSwAddress is NULL and
+ ResolvedEvent is not NULL.
+ @retval EFI_NOT_STARTED The ARP driver instance has not been configured.
+ @retval EFI_NOT_FOUND The request is not issued by
+ EFI_ARP_PROTOCOL.Request().
+
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_ARP_CANCEL)(
+ IN EFI_ARP_PROTOCOL *This,
+ IN VOID *TargetSwAddress OPTIONAL,
+ IN EFI_EVENT ResolvedEvent OPTIONAL
+ );
+
+///
+/// ARP is used to resolve local network protocol addresses into
+/// network hardware addresses.
+///
+struct _EFI_ARP_PROTOCOL {
+ EFI_ARP_CONFIGURE Configure;
+ EFI_ARP_ADD Add;
+ EFI_ARP_FIND Find;
+ EFI_ARP_DELETE Delete;
+ EFI_ARP_FLUSH Flush;
+ EFI_ARP_REQUEST Request;
+ EFI_ARP_CANCEL Cancel;
+};
+
+extern EFI_GUID gEfiArpServiceBindingProtocolGuid;
+extern EFI_GUID gEfiArpProtocolGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/AtaPassThru.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/AtaPassThru.h
new file mode 100644
index 0000000000..545a88db75
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/AtaPassThru.h
@@ -0,0 +1,466 @@
+/** @file
+ The EFI_ATA_PASS_THRU_PROTOCOL provides information about an ATA controller and the ability
+ to send ATA Command Blocks to any ATA device attached to that ATA controller. The information
+ includes the attributes of the ATA controller.
+
+ Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Revision Reference:
+ This Protocol was introduced in UEFI Specification 2.3.
+
+**/
+
+#ifndef __ATA_PASS_THROUGH_H__
+#define __ATA_PASS_THROUGH_H__
+
+#define EFI_ATA_PASS_THRU_PROTOCOL_GUID \
+ { \
+ 0x1d3de7f0, 0x807, 0x424f, {0xaa, 0x69, 0x11, 0xa5, 0x4e, 0x19, 0xa4, 0x6f } \
+ }
+
+typedef struct _EFI_ATA_PASS_THRU_PROTOCOL EFI_ATA_PASS_THRU_PROTOCOL;
+
+typedef struct {
+ UINT32 Attributes;
+ UINT32 IoAlign;
+} EFI_ATA_PASS_THRU_MODE;
+
+///
+/// If this bit is set, then the EFI_ATA_PASS_THRU_PROTOCOL interface is for physical
+/// devices on the ATA controller.
+///
+#define EFI_ATA_PASS_THRU_ATTRIBUTES_PHYSICAL 0x0001
+///
+/// If this bit is set, then the EFI_ATA_PASS_THRU_PROTOCOL interface is for logical
+/// devices on the ATA controller.
+///
+#define EFI_ATA_PASS_THRU_ATTRIBUTES_LOGICAL 0x0002
+///
+/// If this bit is set, then the EFI_ATA_PASS_THRU_PROTOCOL interface supports non blocking
+/// I/O. Every EFI_ATA_PASS_THRU_PROTOCOL must support blocking I/O. The support of non-blocking
+/// I/O is optional.
+///
+#define EFI_ATA_PASS_THRU_ATTRIBUTES_NONBLOCKIO 0x0004
+
+typedef struct _EFI_ATA_COMMAND_BLOCK {
+ UINT8 Reserved1[2];
+ UINT8 AtaCommand;
+ UINT8 AtaFeatures;
+ UINT8 AtaSectorNumber;
+ UINT8 AtaCylinderLow;
+ UINT8 AtaCylinderHigh;
+ UINT8 AtaDeviceHead;
+ UINT8 AtaSectorNumberExp;
+ UINT8 AtaCylinderLowExp;
+ UINT8 AtaCylinderHighExp;
+ UINT8 AtaFeaturesExp;
+ UINT8 AtaSectorCount;
+ UINT8 AtaSectorCountExp;
+ UINT8 Reserved2[6];
+} EFI_ATA_COMMAND_BLOCK;
+
+typedef struct _EFI_ATA_STATUS_BLOCK {
+ UINT8 Reserved1[2];
+ UINT8 AtaStatus;
+ UINT8 AtaError;
+ UINT8 AtaSectorNumber;
+ UINT8 AtaCylinderLow;
+ UINT8 AtaCylinderHigh;
+ UINT8 AtaDeviceHead;
+ UINT8 AtaSectorNumberExp;
+ UINT8 AtaCylinderLowExp;
+ UINT8 AtaCylinderHighExp;
+ UINT8 Reserved2;
+ UINT8 AtaSectorCount;
+ UINT8 AtaSectorCountExp;
+ UINT8 Reserved3[6];
+} EFI_ATA_STATUS_BLOCK;
+
+typedef UINT8 EFI_ATA_PASS_THRU_CMD_PROTOCOL;
+
+#define EFI_ATA_PASS_THRU_PROTOCOL_ATA_HARDWARE_RESET 0x00
+#define EFI_ATA_PASS_THRU_PROTOCOL_ATA_SOFTWARE_RESET 0x01
+#define EFI_ATA_PASS_THRU_PROTOCOL_ATA_NON_DATA 0x02
+#define EFI_ATA_PASS_THRU_PROTOCOL_PIO_DATA_IN 0x04
+#define EFI_ATA_PASS_THRU_PROTOCOL_PIO_DATA_OUT 0x05
+#define EFI_ATA_PASS_THRU_PROTOCOL_DMA 0x06
+#define EFI_ATA_PASS_THRU_PROTOCOL_DMA_QUEUED 0x07
+#define EFI_ATA_PASS_THRU_PROTOCOL_DEVICE_DIAGNOSTIC 0x08
+#define EFI_ATA_PASS_THRU_PROTOCOL_DEVICE_RESET 0x09
+#define EFI_ATA_PASS_THRU_PROTOCOL_UDMA_DATA_IN 0x0A
+#define EFI_ATA_PASS_THRU_PROTOCOL_UDMA_DATA_OUT 0x0B
+#define EFI_ATA_PASS_THRU_PROTOCOL_FPDMA 0x0C
+#define EFI_ATA_PASS_THRU_PROTOCOL_RETURN_RESPONSE 0xFF
+
+typedef UINT8 EFI_ATA_PASS_THRU_LENGTH;
+
+#define EFI_ATA_PASS_THRU_LENGTH_BYTES 0x80
+
+#define EFI_ATA_PASS_THRU_LENGTH_MASK 0x70
+#define EFI_ATA_PASS_THRU_LENGTH_NO_DATA_TRANSFER 0x00
+#define EFI_ATA_PASS_THRU_LENGTH_FEATURES 0x10
+#define EFI_ATA_PASS_THRU_LENGTH_SECTOR_COUNT 0x20
+#define EFI_ATA_PASS_THRU_LENGTH_TPSIU 0x30
+
+#define EFI_ATA_PASS_THRU_LENGTH_COUNT 0x0F
+
+typedef struct {
+ ///
+ /// A pointer to the sense data that was generated by the execution of the ATA
+ /// command. It must be aligned to the boundary specified in the IoAlign field
+ /// in the EFI_ATA_PASS_THRU_MODE structure.
+ ///
+ EFI_ATA_STATUS_BLOCK *Asb;
+ ///
+ /// A pointer to buffer that contains the Command Data Block to send to the ATA
+ /// device specified by Port and PortMultiplierPort.
+ ///
+ EFI_ATA_COMMAND_BLOCK *Acb;
+ ///
+ /// The timeout, in 100 ns units, to use for the execution of this ATA command.
+ /// A Timeout value of 0 means that this function will wait indefinitely for the
+ /// ATA command to execute. If Timeout is greater than zero, then this function
+ /// will return EFI_TIMEOUT if the time required to execute the ATA command is
+ /// greater than Timeout.
+ ///
+ UINT64 Timeout;
+ ///
+ /// A pointer to the data buffer to transfer between the ATA controller and the
+ /// ATA device for read and bidirectional commands. For all write and non data
+ /// commands where InTransferLength is 0 this field is optional and may be NULL.
+ /// If this field is not NULL, then it must be aligned on the boundary specified
+ /// by the IoAlign field in the EFI_ATA_PASS_THRU_MODE structure.
+ ///
+ VOID *InDataBuffer;
+ ///
+ /// A pointer to the data buffer to transfer between the ATA controller and the
+ /// ATA device for write or bidirectional commands. For all read and non data
+ /// commands where OutTransferLength is 0 this field is optional and may be NULL.
+ /// If this field is not NULL, then it must be aligned on the boundary specified
+ /// by the IoAlign field in the EFI_ATA_PASS_THRU_MODE structure.
+ ///
+ VOID *OutDataBuffer;
+ ///
+ /// On input, the size, in bytes, of InDataBuffer. On output, the number of bytes
+ /// transferred between the ATA controller and the ATA device. If InTransferLength
+ /// is larger than the ATA controller can handle, no data will be transferred,
+ /// InTransferLength will be updated to contain the number of bytes that the ATA
+ /// controller is able to transfer, and EFI_BAD_BUFFER_SIZE will be returned.
+ ///
+ UINT32 InTransferLength;
+ ///
+ /// On Input, the size, in bytes of OutDataBuffer. On Output, the Number of bytes
+ /// transferred between ATA Controller and the ATA device. If OutTransferLength is
+ /// larger than the ATA controller can handle, no data will be transferred,
+ /// OutTransferLength will be updated to contain the number of bytes that the ATA
+ /// controller is able to transfer, and EFI_BAD_BUFFER_SIZE will be returned.
+ ///
+ UINT32 OutTransferLength;
+ ///
+ /// Specifies the protocol used when the ATA device executes the command.
+ ///
+ EFI_ATA_PASS_THRU_CMD_PROTOCOL Protocol;
+ ///
+ /// Specifies the way in which the ATA command length is encoded.
+ ///
+ EFI_ATA_PASS_THRU_LENGTH Length;
+} EFI_ATA_PASS_THRU_COMMAND_PACKET;
+
+/**
+ Sends an ATA command to an ATA device that is attached to the ATA controller. This function
+ supports both blocking I/O and non-blocking I/O. The blocking I/O functionality is required,
+ and the non-blocking I/O functionality is optional.
+
+ @param[in] This A pointer to the EFI_ATA_PASS_THRU_PROTOCOL instance.
+ @param[in] Port The port number of the ATA device to send the command.
+ @param[in] PortMultiplierPort The port multiplier port number of the ATA device to send the command.
+ If there is no port multiplier, then specify 0xFFFF.
+ @param[in,out] Packet A pointer to the ATA command to send to the ATA device specified by Port
+ and PortMultiplierPort.
+ @param[in] Event If non-blocking I/O is not supported then Event is ignored, and blocking
+ I/O is performed. If Event is NULL, then blocking I/O is performed. If
+ Event is not NULL and non blocking I/O is supported, then non-blocking
+ I/O is performed, and Event will be signaled when the ATA command completes.
+
+ @retval EFI_SUCCESS The ATA command was sent by the host. For bi-directional commands,
+ InTransferLength bytes were transferred from InDataBuffer. For write and
+ bi-directional commands, OutTransferLength bytes were transferred by OutDataBuffer.
+ @retval EFI_BAD_BUFFER_SIZE The ATA command was not executed. The number of bytes that could be transferred
+ is returned in InTransferLength. For write and bi-directional commands,
+ OutTransferLength bytes were transferred by OutDataBuffer.
+ @retval EFI_NOT_READY The ATA command could not be sent because there are too many ATA commands
+ already queued. The caller may retry again later.
+ @retval EFI_DEVICE_ERROR A device error occurred while attempting to send the ATA command.
+ @retval EFI_INVALID_PARAMETER Port, PortMultiplierPort, or the contents of Acb are invalid. The ATA
+ command was not sent, so no additional status information is available.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_ATA_PASS_THRU_PASSTHRU)(
+ IN EFI_ATA_PASS_THRU_PROTOCOL *This,
+ IN UINT16 Port,
+ IN UINT16 PortMultiplierPort,
+ IN OUT EFI_ATA_PASS_THRU_COMMAND_PACKET *Packet,
+ IN EFI_EVENT Event OPTIONAL
+ );
+
+/**
+ Used to retrieve the list of legal port numbers for ATA devices on an ATA controller.
+ These can either be the list of ports where ATA devices are actually present or the
+ list of legal port numbers for the ATA controller. Regardless, the caller of this
+ function must probe the port number returned to see if an ATA device is actually
+ present at that location on the ATA controller.
+
+ The GetNextPort() function retrieves the port number on an ATA controller. If on input
+ Port is 0xFFFF, then the port number of the first port on the ATA controller is returned
+ in Port and EFI_SUCCESS is returned.
+
+ If Port is a port number that was returned on a previous call to GetNextPort(), then the
+ port number of the next port on the ATA controller is returned in Port, and EFI_SUCCESS
+ is returned. If Port is not 0xFFFF and Port was not returned on a previous call to
+ GetNextPort(), then EFI_INVALID_PARAMETER is returned.
+
+ If Port is the port number of the last port on the ATA controller, then EFI_NOT_FOUND is
+ returned.
+
+ @param[in] This A pointer to the EFI_ATA_PASS_THRU_PROTOCOL instance.
+ @param[in,out] Port On input, a pointer to the port number on the ATA controller.
+ On output, a pointer to the next port number on the ATA
+ controller. An input value of 0xFFFF retrieves the first port
+ number on the ATA controller.
+
+ @retval EFI_SUCCESS The next port number on the ATA controller was returned in Port.
+ @retval EFI_NOT_FOUND There are no more ports on this ATA controller.
+ @retval EFI_INVALID_PARAMETER Port is not 0xFFFF and Port was not returned on a previous call
+ to GetNextPort().
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_ATA_PASS_THRU_GET_NEXT_PORT)(
+ IN EFI_ATA_PASS_THRU_PROTOCOL *This,
+ IN OUT UINT16 *Port
+ );
+
+/**
+ Used to retrieve the list of legal port multiplier port numbers for ATA devices on a port of an ATA
+ controller. These can either be the list of port multiplier ports where ATA devices are actually
+ present on port or the list of legal port multiplier ports on that port. Regardless, the caller of this
+ function must probe the port number and port multiplier port number returned to see if an ATA
+ device is actually present.
+
+ The GetNextDevice() function retrieves the port multiplier port number of an ATA device
+ present on a port of an ATA controller.
+
+ If PortMultiplierPort points to a port multiplier port number value that was returned on a
+ previous call to GetNextDevice(), then the port multiplier port number of the next ATA device
+ on the port of the ATA controller is returned in PortMultiplierPort, and EFI_SUCCESS is
+ returned.
+
+ If PortMultiplierPort points to 0xFFFF, then the port multiplier port number of the first
+ ATA device on port of the ATA controller is returned in PortMultiplierPort and
+ EFI_SUCCESS is returned.
+
+ If PortMultiplierPort is not 0xFFFF and the value pointed to by PortMultiplierPort
+ was not returned on a previous call to GetNextDevice(), then EFI_INVALID_PARAMETER
+ is returned.
+
+ If PortMultiplierPort is the port multiplier port number of the last ATA device on the port of
+ the ATA controller, then EFI_NOT_FOUND is returned.
+
+ @param[in] This A pointer to the EFI_ATA_PASS_THRU_PROTOCOL instance.
+ @param[in] Port The port number present on the ATA controller.
+ @param[in,out] PortMultiplierPort On input, a pointer to the port multiplier port number of an
+ ATA device present on the ATA controller.
+ If on input a PortMultiplierPort of 0xFFFF is specified,
+ then the port multiplier port number of the first ATA device
+ is returned. On output, a pointer to the port multiplier port
+ number of the next ATA device present on an ATA controller.
+
+ @retval EFI_SUCCESS The port multiplier port number of the next ATA device on the port
+ of the ATA controller was returned in PortMultiplierPort.
+ @retval EFI_NOT_FOUND There are no more ATA devices on this port of the ATA controller.
+ @retval EFI_INVALID_PARAMETER PortMultiplierPort is not 0xFFFF, and PortMultiplierPort was not
+ returned on a previous call to GetNextDevice().
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_ATA_PASS_THRU_GET_NEXT_DEVICE)(
+ IN EFI_ATA_PASS_THRU_PROTOCOL *This,
+ IN UINT16 Port,
+ IN OUT UINT16 *PortMultiplierPort
+ );
+
+/**
+ Used to allocate and build a device path node for an ATA device on an ATA controller.
+
+ The BuildDevicePath() function allocates and builds a single device node for the ATA
+ device specified by Port and PortMultiplierPort. If the ATA device specified by Port and
+ PortMultiplierPort is not present on the ATA controller, then EFI_NOT_FOUND is returned.
+ If DevicePath is NULL, then EFI_INVALID_PARAMETER is returned. If there are not enough
+ resources to allocate the device path node, then EFI_OUT_OF_RESOURCES is returned.
+
+ Otherwise, DevicePath is allocated with the boot service AllocatePool(), the contents of
+ DevicePath are initialized to describe the ATA device specified by Port and PortMultiplierPort,
+ and EFI_SUCCESS is returned.
+
+ @param[in] This A pointer to the EFI_ATA_PASS_THRU_PROTOCOL instance.
+ @param[in] Port Port specifies the port number of the ATA device for which a
+ device path node is to be allocated and built.
+ @param[in] PortMultiplierPort The port multiplier port number of the ATA device for which a
+ device path node is to be allocated and built. If there is no
+ port multiplier, then specify 0xFFFF.
+ @param[out] DevicePath A pointer to a single device path node that describes the ATA
+ device specified by Port and PortMultiplierPort. This function
+ is responsible for allocating the buffer DevicePath with the
+ boot service AllocatePool(). It is the caller's responsibility
+ to free DevicePath when the caller is finished with DevicePath.
+ @retval EFI_SUCCESS The device path node that describes the ATA device specified by
+ Port and PortMultiplierPort was allocated and returned in DevicePath.
+ @retval EFI_NOT_FOUND The ATA device specified by Port and PortMultiplierPort does not
+ exist on the ATA controller.
+ @retval EFI_INVALID_PARAMETER DevicePath is NULL.
+ @retval EFI_OUT_OF_RESOURCES There are not enough resources to allocate DevicePath.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_ATA_PASS_THRU_BUILD_DEVICE_PATH)(
+ IN EFI_ATA_PASS_THRU_PROTOCOL *This,
+ IN UINT16 Port,
+ IN UINT16 PortMultiplierPort,
+ OUT EFI_DEVICE_PATH_PROTOCOL **DevicePath
+ );
+
+/**
+ Used to translate a device path node to a port number and port multiplier port number.
+
+ The GetDevice() function determines the port and port multiplier port number associated with
+ the ATA device described by DevicePath. If DevicePath is a device path node type that the
+ ATA Pass Thru driver supports, then the ATA Pass Thru driver will attempt to translate the contents
+ DevicePath into a port number and port multiplier port number.
+
+ If this translation is successful, then that port number and port multiplier port number are returned
+ in Port and PortMultiplierPort, and EFI_SUCCESS is returned.
+
+ If DevicePath, Port, or PortMultiplierPort are NULL, then EFI_INVALID_PARAMETER is returned.
+
+ If DevicePath is not a device path node type that the ATA Pass Thru driver supports, then
+ EFI_UNSUPPORTED is returned.
+
+ If DevicePath is a device path node type that the ATA Pass Thru driver supports, but there is not
+ a valid translation from DevicePath to a port number and port multiplier port number, then
+ EFI_NOT_FOUND is returned.
+
+ @param[in] This A pointer to the EFI_ATA_PASS_THRU_PROTOCOL instance.
+ @param[in] DevicePath A pointer to the device path node that describes an ATA device on the
+ ATA controller.
+ @param[out] Port On return, points to the port number of an ATA device on the ATA controller.
+ @param[out] PortMultiplierPort On return, points to the port multiplier port number of an ATA device
+ on the ATA controller.
+
+ @retval EFI_SUCCESS DevicePath was successfully translated to a port number and port multiplier
+ port number, and they were returned in Port and PortMultiplierPort.
+ @retval EFI_INVALID_PARAMETER DevicePath is NULL.
+ @retval EFI_INVALID_PARAMETER Port is NULL.
+ @retval EFI_INVALID_PARAMETER PortMultiplierPort is NULL.
+ @retval EFI_UNSUPPORTED This driver does not support the device path node type in DevicePath.
+ @retval EFI_NOT_FOUND A valid translation from DevicePath to a port number and port multiplier
+ port number does not exist.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_ATA_PASS_THRU_GET_DEVICE)(
+ IN EFI_ATA_PASS_THRU_PROTOCOL *This,
+ IN EFI_DEVICE_PATH_PROTOCOL *DevicePath,
+ OUT UINT16 *Port,
+ OUT UINT16 *PortMultiplierPort
+ );
+
+/**
+ Resets a specific port on the ATA controller. This operation also resets all the ATA devices
+ connected to the port.
+
+ The ResetChannel() function resets an a specific port on an ATA controller. This operation
+ resets all the ATA devices connected to that port. If this ATA controller does not support
+ a reset port operation, then EFI_UNSUPPORTED is returned.
+
+ If a device error occurs while executing that port reset operation, then EFI_DEVICE_ERROR is
+ returned.
+
+ If a timeout occurs during the execution of the port reset operation, then EFI_TIMEOUT is returned.
+
+ If the port reset operation is completed, then EFI_SUCCESS is returned.
+
+ @param[in] This A pointer to the EFI_ATA_PASS_THRU_PROTOCOL instance.
+ @param[in] Port The port number on the ATA controller.
+
+ @retval EFI_SUCCESS The ATA controller port was reset.
+ @retval EFI_UNSUPPORTED The ATA controller does not support a port reset operation.
+ @retval EFI_DEVICE_ERROR A device error occurred while attempting to reset the ATA port.
+ @retval EFI_TIMEOUT A timeout occurred while attempting to reset the ATA port.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_ATA_PASS_THRU_RESET_PORT)(
+ IN EFI_ATA_PASS_THRU_PROTOCOL *This,
+ IN UINT16 Port
+ );
+
+/**
+ Resets an ATA device that is connected to an ATA controller.
+
+ The ResetDevice() function resets the ATA device specified by Port and PortMultiplierPort.
+ If this ATA controller does not support a device reset operation, then EFI_UNSUPPORTED is
+ returned.
+
+ If Port or PortMultiplierPort are not in a valid range for this ATA controller, then
+ EFI_INVALID_PARAMETER is returned.
+
+ If a device error occurs while executing that device reset operation, then EFI_DEVICE_ERROR
+ is returned.
+
+ If a timeout occurs during the execution of the device reset operation, then EFI_TIMEOUT is
+ returned.
+
+ If the device reset operation is completed, then EFI_SUCCESS is returned.
+
+ @param[in] This A pointer to the EFI_ATA_PASS_THRU_PROTOCOL instance.
+ @param[in] Port Port represents the port number of the ATA device to be reset.
+ @param[in] PortMultiplierPort The port multiplier port number of the ATA device to reset.
+ If there is no port multiplier, then specify 0xFFFF.
+ @retval EFI_SUCCESS The ATA device specified by Port and PortMultiplierPort was reset.
+ @retval EFI_UNSUPPORTED The ATA controller does not support a device reset operation.
+ @retval EFI_INVALID_PARAMETER Port or PortMultiplierPort are invalid.
+ @retval EFI_DEVICE_ERROR A device error occurred while attempting to reset the ATA device
+ specified by Port and PortMultiplierPort.
+ @retval EFI_TIMEOUT A timeout occurred while attempting to reset the ATA device
+ specified by Port and PortMultiplierPort.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_ATA_PASS_THRU_RESET_DEVICE)(
+ IN EFI_ATA_PASS_THRU_PROTOCOL *This,
+ IN UINT16 Port,
+ IN UINT16 PortMultiplierPort
+ );
+
+struct _EFI_ATA_PASS_THRU_PROTOCOL {
+ EFI_ATA_PASS_THRU_MODE *Mode;
+ EFI_ATA_PASS_THRU_PASSTHRU PassThru;
+ EFI_ATA_PASS_THRU_GET_NEXT_PORT GetNextPort;
+ EFI_ATA_PASS_THRU_GET_NEXT_DEVICE GetNextDevice;
+ EFI_ATA_PASS_THRU_BUILD_DEVICE_PATH BuildDevicePath;
+ EFI_ATA_PASS_THRU_GET_DEVICE GetDevice;
+ EFI_ATA_PASS_THRU_RESET_PORT ResetPort;
+ EFI_ATA_PASS_THRU_RESET_DEVICE ResetDevice;
+};
+
+extern EFI_GUID gEfiAtaPassThruProtocolGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/AuthenticationInfo.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/AuthenticationInfo.h
new file mode 100644
index 0000000000..7f1a9b8d1c
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/AuthenticationInfo.h
@@ -0,0 +1,231 @@
+/** @file
+ EFI_AUTHENTICATION_INFO_PROTOCOL as defined in UEFI 2.0.
+ This protocol is used on any device handle to obtain authentication information
+ associated with the physical or logical device.
+
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __AUTHENTICATION_INFO_H__
+#define __AUTHENTICATION_INFO_H__
+
+#define EFI_AUTHENTICATION_INFO_PROTOCOL_GUID \
+ { \
+ 0x7671d9d0, 0x53db, 0x4173, {0xaa, 0x69, 0x23, 0x27, 0xf2, 0x1f, 0x0b, 0xc7 } \
+ }
+
+#define EFI_AUTHENTICATION_CHAP_RADIUS_GUID \
+ { \
+ 0xd6062b50, 0x15ca, 0x11da, {0x92, 0x19, 0x00, 0x10, 0x83, 0xff, 0xca, 0x4d } \
+ }
+
+#define EFI_AUTHENTICATION_CHAP_LOCAL_GUID \
+ { \
+ 0xc280c73e, 0x15ca, 0x11da, {0xb0, 0xca, 0x00, 0x10, 0x83, 0xff, 0xca, 0x4d } \
+ }
+
+typedef struct _EFI_AUTHENTICATION_INFO_PROTOCOL EFI_AUTHENTICATION_INFO_PROTOCOL;
+
+#pragma pack(1)
+typedef struct {
+ ///
+ /// Authentication Type GUID.
+ ///
+ EFI_GUID Guid;
+
+ ///
+ /// Length of this structure in bytes.
+ ///
+ UINT16 Length;
+} AUTH_NODE_HEADER;
+
+typedef struct {
+ AUTH_NODE_HEADER Header;
+
+ ///
+ /// RADIUS Server IPv4 or IPv6 Address.
+ ///
+ UINT8 RadiusIpAddr[16]; ///< IPv4 or IPv6 address.
+
+ ///
+ /// Reserved for future use.
+ ///
+ UINT16 Reserved;
+
+ ///
+ /// Network Access Server IPv4 or IPv6 Address (OPTIONAL).
+ ///
+ UINT8 NasIpAddr[16]; ///< IPv4 or IPv6 address.
+
+ ///
+ /// Network Access Server Secret Length in bytes (OPTIONAL).
+ ///
+ UINT16 NasSecretLength;
+
+ ///
+ /// Network Access Server Secret (OPTIONAL).
+ ///
+ UINT8 NasSecret[1];
+
+ ///
+ /// CHAP Initiator Secret Length in bytes on offset NasSecret + NasSecretLength.
+ ///
+ /// UINT16 ChapSecretLength;
+ ///
+ /// CHAP Initiator Secret.
+ ///
+ /// UINT8 ChapSecret[];
+ ///
+ /// CHAP Initiator Name Length in bytes on offset ChapSecret + ChapSecretLength.
+ ///
+ /// UINT16 ChapNameLength;
+ ///
+ /// CHAP Initiator Name.
+ ///
+ /// UINT8 ChapName[];
+ ///
+ /// Reverse CHAP Name Length in bytes on offset ChapName + ChapNameLength.
+ ///
+ /// UINT16 ReverseChapNameLength;
+ ///
+ /// Reverse CHAP Name.
+ ///
+ /// UINT8 ReverseChapName[];
+ ///
+ /// Reverse CHAP Secret Length in bytes on offseet ReverseChapName + ReverseChapNameLength.
+ ///
+ /// UINT16 ReverseChapSecretLength;
+ ///
+ /// Reverse CHAP Secret.
+ ///
+ /// UINT8 ReverseChapSecret[];
+ ///
+} CHAP_RADIUS_AUTH_NODE;
+
+typedef struct {
+ AUTH_NODE_HEADER Header;
+
+ ///
+ /// Reserved for future use.
+ ///
+ UINT16 Reserved;
+
+ ///
+ /// User Secret Length in bytes.
+ ///
+ UINT16 UserSecretLength;
+
+ ///
+ /// User Secret.
+ ///
+ UINT8 UserSecret[1];
+
+ ///
+ /// User Name Length in bytes on offset UserSecret + UserSecretLength.
+ ///
+ /// UINT16 UserNameLength;
+ ///
+ /// User Name.
+ ///
+ /// UINT8 UserName[];
+ ///
+ /// CHAP Initiator Secret Length in bytes on offset UserName + UserNameLength.
+ ///
+ /// UINT16 ChapSecretLength;
+ ///
+ /// CHAP Initiator Secret.
+ ///
+ /// UINT8 ChapSecret[];
+ ///
+ /// CHAP Initiator Name Length in bytes on offset ChapSecret + ChapSecretLength.
+ ///
+ /// UINT16 ChapNameLength;
+ ///
+ /// CHAP Initiator Name.
+ ///
+ /// UINT8 ChapName[];
+ ///
+ /// Reverse CHAP Name Length in bytes on offset ChapName + ChapNameLength.
+ ///
+ /// UINT16 ReverseChapNameLength;
+ ///
+ /// Reverse CHAP Name.
+ ///
+ /// UINT8 ReverseChapName[];
+ ///
+ /// Reverse CHAP Secret Length in bytes on offset ReverseChapName + ReverseChapNameLength.
+ ///
+ /// UINT16 ReverseChapSecretLength;
+ ///
+ /// Reverse CHAP Secret.
+ ///
+ /// UINT8 ReverseChapSecret[];
+ ///
+} CHAP_LOCAL_AUTH_NODE;
+#pragma pack()
+
+/**
+ Retrieves the authentication information associated with a particular controller handle.
+
+ @param[in] This The pointer to the EFI_AUTHENTICATION_INFO_PROTOCOL.
+ @param[in] ControllerHandle The handle to the Controller.
+ @param[out] Buffer The pointer to the authentication information. This function is
+ responsible for allocating the buffer and it is the caller's
+ responsibility to free buffer when the caller is finished with buffer.
+
+ @retval EFI_SUCCESS Successfully retrieved authentication information
+ for the given ControllerHandle.
+ @retval EFI_INVALID_PARAMETER No matching authentication information found for
+ the given ControllerHandle.
+ @retval EFI_DEVICE_ERROR The authentication information could not be retrieved
+ due to a hardware error.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_AUTHENTICATION_INFO_PROTOCOL_GET)(
+ IN EFI_AUTHENTICATION_INFO_PROTOCOL *This,
+ IN EFI_HANDLE ControllerHandle,
+ OUT VOID **Buffer
+ );
+
+/**
+ Set the authentication information for a given controller handle.
+
+ @param[in] This The pointer to the EFI_AUTHENTICATION_INFO_PROTOCOL.
+ @param[in] ControllerHandle The handle to the Controller.
+ @param[in] Buffer The pointer to the authentication information.
+
+ @retval EFI_SUCCESS Successfully set authentication information for the
+ given ControllerHandle.
+ @retval EFI_UNSUPPORTED If the platform policies do not allow setting of
+ the authentication information.
+ @retval EFI_DEVICE_ERROR The authentication information could not be configured
+ due to a hardware error.
+ @retval EFI_OUT_OF_RESOURCES Not enough storage is available to hold the data.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_AUTHENTICATION_INFO_PROTOCOL_SET)(
+ IN EFI_AUTHENTICATION_INFO_PROTOCOL *This,
+ IN EFI_HANDLE ControllerHandle,
+ IN VOID *Buffer
+ );
+
+///
+/// This protocol is used on any device handle to obtain authentication
+/// information associated with the physical or logical device.
+///
+struct _EFI_AUTHENTICATION_INFO_PROTOCOL {
+ EFI_AUTHENTICATION_INFO_PROTOCOL_GET Get;
+ EFI_AUTHENTICATION_INFO_PROTOCOL_SET Set;
+};
+
+extern EFI_GUID gEfiAuthenticationInfoProtocolGuid;
+extern EFI_GUID gEfiAuthenticationChapRadiusGuid;
+extern EFI_GUID gEfiAuthenticationChapLocalGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/Bds.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/Bds.h
new file mode 100644
index 0000000000..d0b973e9b8
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/Bds.h
@@ -0,0 +1,66 @@
+/** @file
+ Boot Device Selection Architectural Protocol as defined in PI spec Volume 2 DXE
+
+ When the DXE core is done it calls the BDS via this protocol.
+
+ Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __ARCH_PROTOCOL_BDS_H__
+#define __ARCH_PROTOCOL_BDS_H__
+
+///
+/// Global ID for the BDS Architectural Protocol
+///
+#define EFI_BDS_ARCH_PROTOCOL_GUID \
+ { 0x665E3FF6, 0x46CC, 0x11d4, {0x9A, 0x38, 0x00, 0x90, 0x27, 0x3F, 0xC1, 0x4D } }
+
+///
+/// Declare forward reference for the BDS Architectural Protocol
+///
+typedef struct _EFI_BDS_ARCH_PROTOCOL EFI_BDS_ARCH_PROTOCOL;
+
+/**
+ This function uses policy data from the platform to determine what operating
+ system or system utility should be loaded and invoked. This function call
+ also optionally make the use of user input to determine the operating system
+ or system utility to be loaded and invoked. When the DXE Core has dispatched
+ all the drivers on the dispatch queue, this function is called. This
+ function will attempt to connect the boot devices required to load and invoke
+ the selected operating system or system utility. During this process,
+ additional firmware volumes may be discovered that may contain addition DXE
+ drivers that can be dispatched by the DXE Core. If a boot device cannot be
+ fully connected, this function calls the DXE Service Dispatch() to allow the
+ DXE drivers from any newly discovered firmware volumes to be dispatched.
+ Then the boot device connection can be attempted again. If the same boot
+ device connection operation fails twice in a row, then that boot device has
+ failed, and should be skipped. This function should never return.
+
+ @param This The EFI_BDS_ARCH_PROTOCOL instance.
+
+ @return None.
+
+**/
+typedef
+VOID
+(EFIAPI *EFI_BDS_ENTRY)(
+ IN EFI_BDS_ARCH_PROTOCOL *This
+ );
+
+///
+/// The EFI_BDS_ARCH_PROTOCOL transfers control from DXE to an operating
+/// system or a system utility. If there are not enough drivers initialized
+/// when this protocol is used to access the required boot device(s), then
+/// this protocol should add drivers to the dispatch queue and return control
+/// back to the dispatcher. Once the required boot devices are available, then
+/// the boot device can be used to load and invoke an OS or a system utility.
+///
+struct _EFI_BDS_ARCH_PROTOCOL {
+ EFI_BDS_ENTRY Entry;
+};
+
+extern EFI_GUID gEfiBdsArchProtocolGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/Bis.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/Bis.h
new file mode 100644
index 0000000000..1519529303
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/Bis.h
@@ -0,0 +1,442 @@
+/** @file
+ The EFI_BIS_PROTOCOL is used to check a digital signature of a data block
+ against a digital certificate for the purpose of an integrity and authorization check.
+
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Revision Reference:
+ This Protocol is introduced in EFI Specification 1.10.
+
+**/
+
+#ifndef __BIS_H__
+#define __BIS_H__
+
+#define EFI_BIS_PROTOCOL_GUID \
+ { \
+ 0x0b64aab0, 0x5429, 0x11d4, {0x98, 0x16, 0x00, 0xa0, 0xc9, 0x1f, 0xad, 0xcf } \
+ }
+
+//
+// X-Intel-BIS-ParameterSet
+// Attribute value
+// Binary Value of X-Intel-BIS-ParameterSet Attribute.
+// (Value is Base-64 encoded in actual signed manifest).
+//
+#define BOOT_OBJECT_AUTHORIZATION_PARMSET_GUID \
+ { \
+ 0xedd35e31, 0x7b9, 0x11d2, { 0x83,0xa3,0x0,0xa0,0xc9,0x1f,0xad,0xcf } \
+ }
+
+typedef struct _EFI_BIS_PROTOCOL EFI_BIS_PROTOCOL;
+
+//
+// Basic types
+//
+typedef VOID *BIS_APPLICATION_HANDLE;
+typedef UINT16 BIS_ALG_ID;
+typedef UINT32 BIS_CERT_ID;
+
+///
+/// EFI_BIS_DATA instances obtained from BIS must be freed by calling Free( ).
+///
+typedef struct {
+ UINT32 Length; ///< The length of Data in 8 bit bytes.
+ UINT8 *Data; ///< 32 Bit Flat Address of data.
+} EFI_BIS_DATA;
+
+///
+/// EFI_BIS_VERSION type.
+///
+typedef struct {
+ UINT32 Major; ///< The major BIS version number.
+ UINT32 Minor; ///< A minor BIS version number.
+} EFI_BIS_VERSION;
+
+//
+// ----------------------------------------------------//
+// Use these values to initialize EFI_BIS_VERSION.Major
+// and to interpret results of Initialize.
+// ----------------------------------------------------//
+//
+#define BIS_CURRENT_VERSION_MAJOR BIS_VERSION_1
+#define BIS_VERSION_1 1
+
+///
+/// EFI_BIS_SIGNATURE_INFO type.
+///
+typedef struct {
+ BIS_CERT_ID CertificateID; ///< Truncated hash of platform Boot Object
+ BIS_ALG_ID AlgorithmID; ///< A signature algorithm number.
+ UINT16 KeyLength; ///< The length of alg. keys in bits.
+} EFI_BIS_SIGNATURE_INFO;
+
+///
+/// values for EFI_BIS_SIGNATURE_INFO.AlgorithmID.
+/// The exact numeric values come from the
+/// "Common Data Security Architecture (CDSA) Specification".
+///
+#define BIS_ALG_DSA (41) // CSSM_ALGID_DSA
+#define BIS_ALG_RSA_MD5 (42) // CSSM_ALGID_MD5_WITH_RSA
+///
+/// values for EFI_BIS_SIGNATURE_INFO.CertificateId.
+///
+#define BIS_CERT_ID_DSA BIS_ALG_DSA // CSSM_ALGID_DSA
+#define BIS_CERT_ID_RSA_MD5 BIS_ALG_RSA_MD5 // CSSM_ALGID_MD5_WITH_RSA
+///
+/// The mask value that gets applied to the truncated hash of a
+/// platform Boot Object Authorization Certificate to create the certificateID.
+/// A certificateID must not have any bits set to the value 1 other than bits in
+/// this mask.
+///
+#define BIS_CERT_ID_MASK (0xFF7F7FFF)
+
+///
+/// Macros for dealing with the EFI_BIS_DATA object obtained
+/// from BIS_GetSignatureInfo().
+/// BIS_GET_SIGINFO_COUNT - tells how many EFI_BIS_SIGNATURE_INFO
+/// elements are contained in a EFI_BIS_DATA struct pointed to
+/// by the provided EFI_BIS_DATA*.
+///
+#define BIS_GET_SIGINFO_COUNT(BisDataPtr) ((BisDataPtr)->Length / sizeof (EFI_BIS_SIGNATURE_INFO))
+
+///
+/// BIS_GET_SIGINFO_ARRAY - produces a EFI_BIS_SIGNATURE_INFO*
+/// from a given EFI_BIS_DATA*.
+///
+#define BIS_GET_SIGINFO_ARRAY(BisDataPtr) ((EFI_BIS_SIGNATURE_INFO *) (BisDataPtr)->Data)
+
+///
+/// Support an old name for backward compatibility.
+///
+#define BOOT_OBJECT_AUTHORIZATION_PARMSET_GUIDVALUE \
+ BOOT_OBJECT_AUTHORIZATION_PARMSET_GUID
+
+/**
+ Initializes the BIS service, checking that it is compatible with the version requested by the caller.
+ After this call, other BIS functions may be invoked.
+
+ @param This A pointer to the EFI_BIS_PROTOCOL object.
+ @param AppHandle The function writes the new BIS_APPLICATION_HANDLE if
+ successful, otherwise it writes NULL. The caller must eventually
+ destroy this handle by calling Shutdown().
+ @param InterfaceVersion On input, the caller supplies the major version number of the
+ interface version desired.
+ On output, both the major and minor
+ version numbers are updated with the major and minor version
+ numbers of the interface. This update is done whether or not the
+ initialization was successful.
+ @param TargetAddress Indicates a network or device address of the BIS platform to connect to.
+
+ @retval EFI_SUCCESS The function completed successfully.
+ @retval EFI_INCOMPATIBLE_VERSION The InterfaceVersion.Major requested by the
+ caller was not compatible with the interface version of the
+ implementation. The InterfaceVersion.Major has
+ been updated with the current interface version.
+ @retval EFI_UNSUPPORTED This is a local-platform implementation and
+ TargetAddress.Data was not NULL, or
+ TargetAddress.Data was any other value that was not
+ supported by the implementation.
+ @retval EFI_OUT_OF_RESOURCES The function failed due to lack of memory or other resources.
+ @retval EFI_DEVICE_ERROR One of the following device errors:
+ * The function encountered an unexpected internal failure while initializing a cryptographic software module
+ * No cryptographic software module with compatible version was found
+ found
+ * A resource limitation was encountered while using a cryptographic software module.
+ @retval EFI_INVALID_PARAMETER The This parameter supplied by the caller is NULL or does not
+ reference a valid EFI_BIS_PROTOCOL object. Or,
+ the AppHandle parameter supplied by the caller is NULL or
+ an invalid memory reference. Or,
+ the InterfaceVersion parameter supplied by the caller
+ is NULL or an invalid memory reference. Or,
+ the TargetAddress parameter supplied by the caller is
+ NULL or an invalid memory reference.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_BIS_INITIALIZE)(
+ IN EFI_BIS_PROTOCOL *This,
+ OUT BIS_APPLICATION_HANDLE *AppHandle,
+ IN OUT EFI_BIS_VERSION *InterfaceVersion,
+ IN EFI_BIS_DATA *TargetAddress
+ );
+
+/**
+ Frees memory structures allocated and returned by other functions in the EFI_BIS protocol.
+
+ @param AppHandle An opaque handle that identifies the caller's instance of initialization
+ of the BIS service.
+ @param ToFree An EFI_BIS_DATA* and associated memory block to be freed.
+ This EFI_BIS_DATA* must have been allocated by one of the other BIS functions.
+
+ @retval EFI_SUCCESS The function completed successfully.
+ @retval EFI_NO_MAPPING The AppHandle parameter is not or is no longer a valid
+ application instance handle associated with the EFI_BIS protocol.
+ @retval EFI_OUT_OF_RESOURCES The function failed due to lack of memory or other resources.
+ @retval EFI_INVALID_PARAMETER The ToFree parameter is not or is no longer a memory resource
+ associated with this AppHandle.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_BIS_FREE)(
+ IN BIS_APPLICATION_HANDLE AppHandle,
+ IN EFI_BIS_DATA *ToFree
+ );
+
+/**
+ Shuts down an application's instance of the BIS service, invalidating the application handle. After
+ this call, other BIS functions may no longer be invoked using the application handle value.
+
+ @param AppHandle An opaque handle that identifies the caller's instance of initialization
+ of the BIS service.
+
+ @retval EFI_SUCCESS The function completed successfully.
+ @retval EFI_NO_MAPPING The AppHandle parameter is not, or is no longer, a valid
+ application instance handle associated with the EFI_BIS protocol.
+ @retval EFI_OUT_OF_RESOURCES The function failed due to lack of memory or other resources.
+ @retval EFI_DEVICE_ERROR The function encountered an unexpected internal failure while
+ returning resources associated with a cryptographic software module, or
+ while trying to shut down a cryptographic software module.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_BIS_SHUTDOWN)(
+ IN BIS_APPLICATION_HANDLE AppHandle
+ );
+
+/**
+ Retrieves the certificate that has been configured as the identity of the organization designated as
+ the source of authorization for signatures of boot objects.
+
+ @param AppHandle An opaque handle that identifies the caller's instance of initialization
+ of the BIS service.
+ @param Certificate The function writes an allocated EFI_BIS_DATA* containing the Boot
+ Object Authorization Certificate object. The caller must
+ eventually free the memory allocated by this function using the function Free().
+
+ @retval EFI_SUCCESS The function completed successfully.
+ @retval EFI_NO_MAPPING The AppHandle parameter is not or is no longer a valid
+ application instance handle associated with the EFI_BIS protocol.
+ @retval EFI_NOT_FOUND There is no Boot Object Authorization Certificate currently installed.
+ @retval EFI_OUT_OF_RESOURCES The function failed due to lack of memory or other resources.
+ @retval EFI_INVALID_PARAMETER The Certificate parameter supplied by the caller is NULL or
+ an invalid memory reference.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_BIS_GET_BOOT_OBJECT_AUTHORIZATION_CERTIFICATE)(
+ IN BIS_APPLICATION_HANDLE AppHandle,
+ OUT EFI_BIS_DATA **Certificate
+ );
+
+/**
+ Verifies the integrity and authorization of the indicated data object according to the
+ indicated credentials.
+
+ @param AppHandle An opaque handle that identifies the caller's instance of initialization
+ of the BIS service.
+ @param Credentials A Signed Manifest containing verification information for the indicated
+ data object.
+ @param DataObject An in-memory copy of the raw data object to be verified.
+ @param IsVerified The function writes TRUE if the verification succeeded, otherwise
+ FALSE.
+
+ @retval EFI_SUCCESS The function completed successfully.
+ @retval EFI_NO_MAPPING The AppHandle parameter is not or is no longer a valid
+ application instance handle associated with the EFI_BIS protocol.
+ @retval EFI_OUT_OF_RESOURCES The function failed due to lack of memory or other resources.
+ @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
+ @retval EFI_SECURITY_VIOLATION The signed manifest supplied as the Credentials parameter
+ was invalid (could not be parsed) or Platform-specific authorization failed, etc.
+ @retval EFI_DEVICE_ERROR An unexpected internal error occurred.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_BIS_VERIFY_BOOT_OBJECT)(
+ IN BIS_APPLICATION_HANDLE AppHandle,
+ IN EFI_BIS_DATA *Credentials,
+ IN EFI_BIS_DATA *DataObject,
+ OUT BOOLEAN *IsVerified
+ );
+
+/**
+ Retrieves the current status of the Boot Authorization Check Flag.
+
+ @param AppHandle An opaque handle that identifies the caller's instance of initialization
+ of the BIS service.
+ @param CheckIsRequired The function writes the value TRUE if a Boot Authorization Check is
+ currently required on this platform, otherwise the function writes
+ FALSE.
+
+ @retval EFI_SUCCESS The function completed successfully.
+ @retval EFI_NO_MAPPING The AppHandle parameter is not or is no longer a valid
+ application instance handle associated with the EFI_BIS protocol.
+ @retval EFI_OUT_OF_RESOURCES The function failed due to lack of memory or other resources.
+ @retval EFI_INVALID_PARAMETER The CheckIsRequired parameter supplied by the caller is
+ NULL or an invalid memory reference.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_BIS_GET_BOOT_OBJECT_AUTHORIZATION_CHECKFLAG)(
+ IN BIS_APPLICATION_HANDLE AppHandle,
+ OUT BOOLEAN *CheckIsRequired
+ );
+
+/**
+ Retrieves a unique token value to be included in the request credential for the next update of any
+ parameter in the Boot Object Authorization set
+
+ @param AppHandle An opaque handle that identifies the caller's
+ instance of initialization of the BIS service.
+ @param UpdateToken The function writes an allocated EFI_BIS_DATA*
+ containing the newunique update token value.
+ The caller musteventually free the memory allocated
+ by this function using the function Free().
+
+ @retval EFI_SUCCESS The function completed successfully.
+ @retval EFI_NO_MAPPING The AppHandle parameter is not or is no longer a valid
+ application instance handle associated with the EFI_BIS protocol.
+ @retval EFI_OUT_OF_RESOURCES The function failed due to lack of memory or other resources.
+ @retval EFI_INVALID_PARAMETER The UpdateToken parameter supplied by the caller is NULL or
+ an invalid memory reference.
+ @retval EFI_DEVICE_ERROR An unexpected internal error occurred.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_BIS_GET_BOOT_OBJECT_AUTHORIZATION_UPDATE_TOKEN)(
+ IN BIS_APPLICATION_HANDLE AppHandle,
+ OUT EFI_BIS_DATA **UpdateToken
+ );
+
+/**
+ Updates one of the configurable parameters of the Boot Object Authorization set.
+
+ @param AppHandle An opaque handle that identifies the caller's
+ instance of initialization of the BIS service.
+ @param RequestCredential This is a Signed Manifest with embedded attributes
+ that carry the details of the requested update.
+ @param NewUpdateToken The function writes an allocated EFI_BIS_DATA*
+ containing the new unique update token value.
+ The caller must eventually free the memory allocated
+ by this function using the function Free().
+
+ @retval EFI_SUCCESS The function completed successfully.
+ @retval EFI_NO_MAPPING The AppHandle parameter is not or is no longer a valid
+ application instance handle associated with the EFI_BIS protocol.
+ @retval EFI_OUT_OF_RESOURCES The function failed due to lack of memory or other resources.
+ @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
+ @retval EFI_SECURITY_VIOLATION The signed manifest supplied as the RequestCredential parameter
+ was invalid (could not be parsed) or Platform-specific authorization failed, etc.
+ @retval EFI_DEVICE_ERROR An unexpected internal error occurred while analyzing the new
+ certificate's key algorithm, or while attempting to retrieve
+ the public key algorithm of the manifest's signer's certificate,
+ or An unexpected internal error occurred in a cryptographic software module.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_BIS_UPDATE_BOOT_OBJECT_AUTHORIZATION)(
+ IN BIS_APPLICATION_HANDLE AppHandle,
+ IN EFI_BIS_DATA *RequestCredential,
+ OUT EFI_BIS_DATA **NewUpdateToken
+ );
+
+/**
+ Verifies the integrity and authorization of the indicated data object according to the indicated
+ credentials and authority certificate.
+
+ @param AppHandle An opaque handle that identifies the caller's instance of initialization
+ of the BIS service.
+ @param Credentials A Signed Manifest containing verification information for the
+ indicated data object.
+ @param DataObject An in-memory copy of the raw data object to be verified.
+ @param SectionName An ASCII string giving the section name in the
+ manifest holding the verification information (in other words,
+ hash value) that corresponds to DataObject.
+ @param AuthorityCertificate A digital certificate whose public key must match the signer's
+ public key which is found in the credentials.
+ @param IsVerified The function writes TRUE if the verification was successful.
+ Otherwise, the function writes FALSE.
+
+ @retval EFI_SUCCESS The function completed successfully.
+ @retval EFI_NO_MAPPING The AppHandle parameter is not or is no longer a valid
+ application instance handle associated with the EFI_BIS protocol.
+ @retval EFI_OUT_OF_RESOURCES The function failed due to lack of memory or other resources.
+ @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
+ @retval EFI_SECURITY_VIOLATION The Credentials.Data supplied by the caller is NULL,
+ or the AuthorityCertificate supplied by the caller was
+ invalid (could not be parsed),
+ or Platform-specific authorization failed, etc.
+ @retval EFI_DEVICE_ERROR An unexpected internal error occurred while attempting to retrieve
+ the public key algorithm of the manifest's signer's certificate,
+ or An unexpected internal error occurred in a cryptographic software module.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_BIS_VERIFY_OBJECT_WITH_CREDENTIAL)(
+ IN BIS_APPLICATION_HANDLE AppHandle,
+ IN EFI_BIS_DATA *Credentials,
+ IN EFI_BIS_DATA *DataObject,
+ IN EFI_BIS_DATA *SectionName,
+ IN EFI_BIS_DATA *AuthorityCertificate,
+ OUT BOOLEAN *IsVerified
+ );
+
+/**
+ Retrieves a list of digital certificate identifier, digital signature algorithm, hash algorithm, and keylength
+ combinations that the platform supports.
+
+ @param AppHandle An opaque handle that identifies the caller's instance of initialization
+ of the BIS service.
+ @param SignatureInfo The function writes an allocated EFI_BIS_DATA* containing the array
+ of EFI_BIS_SIGNATURE_INFO structures representing the supported
+ digital certificate identifier, algorithm, and key length combinations.
+ The caller must eventually free the memory allocated by this function using the function Free().
+
+ @retval EFI_SUCCESS The function completed successfully.
+ @retval EFI_NO_MAPPING The AppHandle parameter is not or is no longer a valid
+ application instance handle associated with the EFI_BIS protocol.
+ @retval EFI_OUT_OF_RESOURCES The function failed due to lack of memory or other resources.
+ @retval EFI_INVALID_PARAMETER The SignatureInfo parameter supplied by the caller is NULL
+ or an invalid memory reference.
+ @retval EFI_DEVICE_ERROR An unexpected internal error occurred in a
+ cryptographic software module, or
+ The function encountered an unexpected internal consistency check
+ failure (possible corruption of stored Boot Object Authorization Certificate).
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_BIS_GET_SIGNATURE_INFO)(
+ IN BIS_APPLICATION_HANDLE AppHandle,
+ OUT EFI_BIS_DATA **SignatureInfo
+ );
+
+///
+/// The EFI_BIS_PROTOCOL is used to check a digital signature of a data block against a digital
+/// certificate for the purpose of an integrity and authorization check.
+///
+struct _EFI_BIS_PROTOCOL {
+ EFI_BIS_INITIALIZE Initialize;
+ EFI_BIS_SHUTDOWN Shutdown;
+ EFI_BIS_FREE Free;
+ EFI_BIS_GET_BOOT_OBJECT_AUTHORIZATION_CERTIFICATE GetBootObjectAuthorizationCertificate;
+ EFI_BIS_GET_BOOT_OBJECT_AUTHORIZATION_CHECKFLAG GetBootObjectAuthorizationCheckFlag;
+ EFI_BIS_GET_BOOT_OBJECT_AUTHORIZATION_UPDATE_TOKEN GetBootObjectAuthorizationUpdateToken;
+ EFI_BIS_GET_SIGNATURE_INFO GetSignatureInfo;
+ EFI_BIS_UPDATE_BOOT_OBJECT_AUTHORIZATION UpdateBootObjectAuthorization;
+ EFI_BIS_VERIFY_BOOT_OBJECT VerifyBootObject;
+ EFI_BIS_VERIFY_OBJECT_WITH_CREDENTIAL VerifyObjectWithCredential;
+};
+
+extern EFI_GUID gEfiBisProtocolGuid;
+extern EFI_GUID gBootObjectAuthorizationParmsetGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/BlockIo.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/BlockIo.h
new file mode 100644
index 0000000000..d8fe6c2ff0
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/BlockIo.h
@@ -0,0 +1,234 @@
+/** @file
+ Block IO protocol as defined in the UEFI 2.0 specification.
+
+ The Block IO protocol is used to abstract block devices like hard drives,
+ DVD-ROMs and floppy drives.
+
+ Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __BLOCK_IO_H__
+#define __BLOCK_IO_H__
+
+#define EFI_BLOCK_IO_PROTOCOL_GUID \
+ { \
+ 0x964e5b21, 0x6459, 0x11d2, {0x8e, 0x39, 0x0, 0xa0, 0xc9, 0x69, 0x72, 0x3b } \
+ }
+
+typedef struct _EFI_BLOCK_IO_PROTOCOL EFI_BLOCK_IO_PROTOCOL;
+
+///
+/// Protocol GUID name defined in EFI1.1.
+///
+#define BLOCK_IO_PROTOCOL EFI_BLOCK_IO_PROTOCOL_GUID
+
+///
+/// Protocol defined in EFI1.1.
+///
+typedef EFI_BLOCK_IO_PROTOCOL EFI_BLOCK_IO;
+
+/**
+ Reset the Block Device.
+
+ @param This Indicates a pointer to the calling context.
+ @param ExtendedVerification Driver may perform diagnostics on reset.
+
+ @retval EFI_SUCCESS The device was reset.
+ @retval EFI_DEVICE_ERROR The device is not functioning properly and could
+ not be reset.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_BLOCK_RESET)(
+ IN EFI_BLOCK_IO_PROTOCOL *This,
+ IN BOOLEAN ExtendedVerification
+ );
+
+/**
+ Read BufferSize bytes from Lba into Buffer.
+
+ @param This Indicates a pointer to the calling context.
+ @param MediaId Id of the media, changes every time the media is replaced.
+ @param Lba The starting Logical Block Address to read from
+ @param BufferSize Size of Buffer, must be a multiple of device block size.
+ @param Buffer A pointer to the destination buffer for the data. The caller is
+ responsible for either having implicit or explicit ownership of the buffer.
+
+ @retval EFI_SUCCESS The data was read correctly from the device.
+ @retval EFI_DEVICE_ERROR The device reported an error while performing the read.
+ @retval EFI_NO_MEDIA There is no media in the device.
+ @retval EFI_MEDIA_CHANGED The MediaId does not matched the current device.
+ @retval EFI_BAD_BUFFER_SIZE The Buffer was not a multiple of the block size of the device.
+ @retval EFI_INVALID_PARAMETER The read request contains LBAs that are not valid,
+ or the buffer is not on proper alignment.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_BLOCK_READ)(
+ IN EFI_BLOCK_IO_PROTOCOL *This,
+ IN UINT32 MediaId,
+ IN EFI_LBA Lba,
+ IN UINTN BufferSize,
+ OUT VOID *Buffer
+ );
+
+/**
+ Write BufferSize bytes from Lba into Buffer.
+
+ @param This Indicates a pointer to the calling context.
+ @param MediaId The media ID that the write request is for.
+ @param Lba The starting logical block address to be written. The caller is
+ responsible for writing to only legitimate locations.
+ @param BufferSize Size of Buffer, must be a multiple of device block size.
+ @param Buffer A pointer to the source buffer for the data.
+
+ @retval EFI_SUCCESS The data was written correctly to the device.
+ @retval EFI_WRITE_PROTECTED The device can not be written to.
+ @retval EFI_DEVICE_ERROR The device reported an error while performing the write.
+ @retval EFI_NO_MEDIA There is no media in the device.
+ @retval EFI_MEDIA_CHNAGED The MediaId does not matched the current device.
+ @retval EFI_BAD_BUFFER_SIZE The Buffer was not a multiple of the block size of the device.
+ @retval EFI_INVALID_PARAMETER The write request contains LBAs that are not valid,
+ or the buffer is not on proper alignment.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_BLOCK_WRITE)(
+ IN EFI_BLOCK_IO_PROTOCOL *This,
+ IN UINT32 MediaId,
+ IN EFI_LBA Lba,
+ IN UINTN BufferSize,
+ IN VOID *Buffer
+ );
+
+/**
+ Flush the Block Device.
+
+ @param This Indicates a pointer to the calling context.
+
+ @retval EFI_SUCCESS All outstanding data was written to the device
+ @retval EFI_DEVICE_ERROR The device reported an error while writting back the data
+ @retval EFI_NO_MEDIA There is no media in the device.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_BLOCK_FLUSH)(
+ IN EFI_BLOCK_IO_PROTOCOL *This
+ );
+
+/**
+ Block IO read only mode data and updated only via members of BlockIO
+**/
+typedef struct {
+ ///
+ /// The curent media Id. If the media changes, this value is changed.
+ ///
+ UINT32 MediaId;
+
+ ///
+ /// TRUE if the media is removable; otherwise, FALSE.
+ ///
+ BOOLEAN RemovableMedia;
+
+ ///
+ /// TRUE if there is a media currently present in the device;
+ /// othersise, FALSE. THis field shows the media present status
+ /// as of the most recent ReadBlocks() or WriteBlocks() call.
+ ///
+ BOOLEAN MediaPresent;
+
+ ///
+ /// TRUE if LBA 0 is the first block of a partition; otherwise
+ /// FALSE. For media with only one partition this would be TRUE.
+ ///
+ BOOLEAN LogicalPartition;
+
+ ///
+ /// TRUE if the media is marked read-only otherwise, FALSE.
+ /// This field shows the read-only status as of the most recent WriteBlocks () call.
+ ///
+ BOOLEAN ReadOnly;
+
+ ///
+ /// TRUE if the WriteBlock () function caches write data.
+ ///
+ BOOLEAN WriteCaching;
+
+ ///
+ /// The intrinsic block size of the device. If the media changes, then
+ /// this field is updated.
+ ///
+ UINT32 BlockSize;
+
+ ///
+ /// Supplies the alignment requirement for any buffer to read or write block(s).
+ ///
+ UINT32 IoAlign;
+
+ ///
+ /// The last logical block address on the device.
+ /// If the media changes, then this field is updated.
+ ///
+ EFI_LBA LastBlock;
+
+ ///
+ /// Only present if EFI_BLOCK_IO_PROTOCOL.Revision is greater than or equal to
+ /// EFI_BLOCK_IO_PROTOCOL_REVISION2. Returns the first LBA is aligned to
+ /// a physical block boundary.
+ ///
+ EFI_LBA LowestAlignedLba;
+
+ ///
+ /// Only present if EFI_BLOCK_IO_PROTOCOL.Revision is greater than or equal to
+ /// EFI_BLOCK_IO_PROTOCOL_REVISION2. Returns the number of logical blocks
+ /// per physical block.
+ ///
+ UINT32 LogicalBlocksPerPhysicalBlock;
+
+ ///
+ /// Only present if EFI_BLOCK_IO_PROTOCOL.Revision is greater than or equal to
+ /// EFI_BLOCK_IO_PROTOCOL_REVISION3. Returns the optimal transfer length
+ /// granularity as a number of logical blocks.
+ ///
+ UINT32 OptimalTransferLengthGranularity;
+} EFI_BLOCK_IO_MEDIA;
+
+#define EFI_BLOCK_IO_PROTOCOL_REVISION 0x00010000
+#define EFI_BLOCK_IO_PROTOCOL_REVISION2 0x00020001
+#define EFI_BLOCK_IO_PROTOCOL_REVISION3 0x0002001F
+
+///
+/// Revision defined in EFI1.1.
+///
+#define EFI_BLOCK_IO_INTERFACE_REVISION EFI_BLOCK_IO_PROTOCOL_REVISION
+
+///
+/// This protocol provides control over block devices.
+///
+struct _EFI_BLOCK_IO_PROTOCOL {
+ ///
+ /// The revision to which the block IO interface adheres. All future
+ /// revisions must be backwards compatible. If a future version is not
+ /// back wards compatible, it is not the same GUID.
+ ///
+ UINT64 Revision;
+ ///
+ /// Pointer to the EFI_BLOCK_IO_MEDIA data for this device.
+ ///
+ EFI_BLOCK_IO_MEDIA *Media;
+
+ EFI_BLOCK_RESET Reset;
+ EFI_BLOCK_READ ReadBlocks;
+ EFI_BLOCK_WRITE WriteBlocks;
+ EFI_BLOCK_FLUSH FlushBlocks;
+};
+
+extern EFI_GUID gEfiBlockIoProtocolGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/BlockIo2.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/BlockIo2.h
new file mode 100644
index 0000000000..f629d8ebbf
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/BlockIo2.h
@@ -0,0 +1,197 @@
+/** @file
+ Block IO2 protocol as defined in the UEFI 2.3.1 specification.
+
+ The Block IO2 protocol defines an extension to the Block IO protocol which
+ enables the ability to read and write data at a block level in a non-blocking
+ manner.
+
+ Copyright (c) 2011 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __BLOCK_IO2_H__
+#define __BLOCK_IO2_H__
+
+#include
+
+#define EFI_BLOCK_IO2_PROTOCOL_GUID \
+ { \
+ 0xa77b2472, 0xe282, 0x4e9f, {0xa2, 0x45, 0xc2, 0xc0, 0xe2, 0x7b, 0xbc, 0xc1} \
+ }
+
+typedef struct _EFI_BLOCK_IO2_PROTOCOL EFI_BLOCK_IO2_PROTOCOL;
+
+/**
+ The struct of Block IO2 Token.
+**/
+typedef struct {
+ ///
+ /// If Event is NULL, then blocking I/O is performed.If Event is not NULL and
+ /// non-blocking I/O is supported, then non-blocking I/O is performed, and
+ /// Event will be signaled when the read request is completed.
+ ///
+ EFI_EVENT Event;
+
+ ///
+ /// Defines whether or not the signaled event encountered an error.
+ ///
+ EFI_STATUS TransactionStatus;
+} EFI_BLOCK_IO2_TOKEN;
+
+/**
+ Reset the block device hardware.
+
+ @param[in] This Indicates a pointer to the calling context.
+ @param[in] ExtendedVerification Indicates that the driver may perform a more
+ exhausive verification operation of the device
+ during reset.
+
+ @retval EFI_SUCCESS The device was reset.
+ @retval EFI_DEVICE_ERROR The device is not functioning properly and could
+ not be reset.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_BLOCK_RESET_EX)(
+ IN EFI_BLOCK_IO2_PROTOCOL *This,
+ IN BOOLEAN ExtendedVerification
+ );
+
+/**
+ Read BufferSize bytes from Lba into Buffer.
+
+ This function reads the requested number of blocks from the device. All the
+ blocks are read, or an error is returned.
+ If EFI_DEVICE_ERROR, EFI_NO_MEDIA,_or EFI_MEDIA_CHANGED is returned and
+ non-blocking I/O is being used, the Event associated with this request will
+ not be signaled.
+
+ @param[in] This Indicates a pointer to the calling context.
+ @param[in] MediaId Id of the media, changes every time the media is
+ replaced.
+ @param[in] Lba The starting Logical Block Address to read from.
+ @param[in, out] Token A pointer to the token associated with the transaction.
+ @param[in] BufferSize Size of Buffer, must be a multiple of device block size.
+ @param[out] Buffer A pointer to the destination buffer for the data. The
+ caller is responsible for either having implicit or
+ explicit ownership of the buffer.
+
+ @retval EFI_SUCCESS The read request was queued if Token->Event is
+ not NULL.The data was read correctly from the
+ device if the Token->Event is NULL.
+ @retval EFI_DEVICE_ERROR The device reported an error while performing
+ the read.
+ @retval EFI_NO_MEDIA There is no media in the device.
+ @retval EFI_MEDIA_CHANGED The MediaId is not for the current media.
+ @retval EFI_BAD_BUFFER_SIZE The BufferSize parameter is not a multiple of the
+ intrinsic block size of the device.
+ @retval EFI_INVALID_PARAMETER The read request contains LBAs that are not valid,
+ or the buffer is not on proper alignment.
+ @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack
+ of resources.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_BLOCK_READ_EX)(
+ IN EFI_BLOCK_IO2_PROTOCOL *This,
+ IN UINT32 MediaId,
+ IN EFI_LBA LBA,
+ IN OUT EFI_BLOCK_IO2_TOKEN *Token,
+ IN UINTN BufferSize,
+ OUT VOID *Buffer
+ );
+
+/**
+ Write BufferSize bytes from Lba into Buffer.
+
+ This function writes the requested number of blocks to the device. All blocks
+ are written, or an error is returned.If EFI_DEVICE_ERROR, EFI_NO_MEDIA,
+ EFI_WRITE_PROTECTED or EFI_MEDIA_CHANGED is returned and non-blocking I/O is
+ being used, the Event associated with this request will not be signaled.
+
+ @param[in] This Indicates a pointer to the calling context.
+ @param[in] MediaId The media ID that the write request is for.
+ @param[in] Lba The starting logical block address to be written. The
+ caller is responsible for writing to only legitimate
+ locations.
+ @param[in, out] Token A pointer to the token associated with the transaction.
+ @param[in] BufferSize Size of Buffer, must be a multiple of device block size.
+ @param[in] Buffer A pointer to the source buffer for the data.
+
+ @retval EFI_SUCCESS The write request was queued if Event is not NULL.
+ The data was written correctly to the device if
+ the Event is NULL.
+ @retval EFI_WRITE_PROTECTED The device can not be written to.
+ @retval EFI_NO_MEDIA There is no media in the device.
+ @retval EFI_MEDIA_CHNAGED The MediaId does not matched the current device.
+ @retval EFI_DEVICE_ERROR The device reported an error while performing the write.
+ @retval EFI_BAD_BUFFER_SIZE The Buffer was not a multiple of the block size of the device.
+ @retval EFI_INVALID_PARAMETER The write request contains LBAs that are not valid,
+ or the buffer is not on proper alignment.
+ @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack
+ of resources.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_BLOCK_WRITE_EX)(
+ IN EFI_BLOCK_IO2_PROTOCOL *This,
+ IN UINT32 MediaId,
+ IN EFI_LBA LBA,
+ IN OUT EFI_BLOCK_IO2_TOKEN *Token,
+ IN UINTN BufferSize,
+ IN VOID *Buffer
+ );
+
+/**
+ Flush the Block Device.
+
+ If EFI_DEVICE_ERROR, EFI_NO_MEDIA,_EFI_WRITE_PROTECTED or EFI_MEDIA_CHANGED
+ is returned and non-blocking I/O is being used, the Event associated with
+ this request will not be signaled.
+
+ @param[in] This Indicates a pointer to the calling context.
+ @param[in,out] Token A pointer to the token associated with the transaction
+
+ @retval EFI_SUCCESS The flush request was queued if Event is not NULL.
+ All outstanding data was written correctly to the
+ device if the Event is NULL.
+ @retval EFI_DEVICE_ERROR The device reported an error while writting back
+ the data.
+ @retval EFI_WRITE_PROTECTED The device cannot be written to.
+ @retval EFI_NO_MEDIA There is no media in the device.
+ @retval EFI_MEDIA_CHANGED The MediaId is not for the current media.
+ @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack
+ of resources.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_BLOCK_FLUSH_EX)(
+ IN EFI_BLOCK_IO2_PROTOCOL *This,
+ IN OUT EFI_BLOCK_IO2_TOKEN *Token
+ );
+
+///
+/// The Block I/O2 protocol defines an extension to the Block I/O protocol which
+/// enables the ability to read and write data at a block level in a non-blocking
+// manner.
+///
+struct _EFI_BLOCK_IO2_PROTOCOL {
+ ///
+ /// A pointer to the EFI_BLOCK_IO_MEDIA data for this device.
+ /// Type EFI_BLOCK_IO_MEDIA is defined in BlockIo.h.
+ ///
+ EFI_BLOCK_IO_MEDIA *Media;
+
+ EFI_BLOCK_RESET_EX Reset;
+ EFI_BLOCK_READ_EX ReadBlocksEx;
+ EFI_BLOCK_WRITE_EX WriteBlocksEx;
+ EFI_BLOCK_FLUSH_EX FlushBlocksEx;
+};
+
+extern EFI_GUID gEfiBlockIo2ProtocolGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/BlockIoCrypto.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/BlockIoCrypto.h
new file mode 100644
index 0000000000..95c9cf27f7
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/BlockIoCrypto.h
@@ -0,0 +1,523 @@
+/** @file
+ The UEFI Inline Cryptographic Interface protocol provides services to abstract
+ access to inline cryptographic capabilities.
+
+ Copyright (c) 2015-2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Revision Reference:
+ This Protocol was introduced in UEFI Specification 2.5.
+
+**/
+
+#ifndef __BLOCK_IO_CRYPTO_H__
+#define __BLOCK_IO_CRYPTO_H__
+
+#include
+
+#define EFI_BLOCK_IO_CRYPTO_PROTOCOL_GUID \
+ { \
+ 0xa00490ba, 0x3f1a, 0x4b4c, {0xab, 0x90, 0x4f, 0xa9, 0x97, 0x26, 0xa1, 0xe8} \
+ }
+
+typedef struct _EFI_BLOCK_IO_CRYPTO_PROTOCOL EFI_BLOCK_IO_CRYPTO_PROTOCOL;
+
+///
+/// The struct of Block I/O Crypto Token.
+///
+typedef struct {
+ //
+ // If Event is NULL, then blocking I/O is performed. If Event is not NULL and
+ // non-blocking I/O is supported, then non-blocking I/O is performed, and
+ // Event will be signaled when the read request is completed and data was
+ // decrypted (when Index was specified).
+ //
+ EFI_EVENT Event;
+ //
+ // Defines whether or not the signaled event encountered an error.
+ //
+ EFI_STATUS TransactionStatus;
+} EFI_BLOCK_IO_CRYPTO_TOKEN;
+
+typedef struct {
+ //
+ // GUID of the algorithm.
+ //
+ EFI_GUID Algorithm;
+ //
+ // Specifies KeySizein bits used with this Algorithm.
+ //
+ UINT64 KeySize;
+ //
+ // Specifies bitmask of block sizes supported by this algorithm.
+ // Bit j being set means that 2^j bytes crypto block size is supported.
+ //
+ UINT64 CryptoBlockSizeBitMask;
+} EFI_BLOCK_IO_CRYPTO_CAPABILITY;
+
+///
+/// EFI_BLOCK_IO_CRYPTO_IV_INPUT structure is used as a common header in CryptoIvInput
+/// parameters passed to the ReadExtended and WriteExtended methods for Inline
+/// Cryptographic Interface.
+/// Its purpose is to pass size of the entire CryptoIvInputparameter memory buffer to
+/// the Inline Cryptographic Interface.
+///
+typedef struct {
+ UINT64 InputSize;
+} EFI_BLOCK_IO_CRYPTO_IV_INPUT;
+
+#define EFI_BLOCK_IO_CRYPTO_ALGO_GUID_AES_XTS \
+ { \
+ 0x2f87ba6a, 0x5c04, 0x4385, {0xa7, 0x80, 0xf3, 0xbf, 0x78, 0xa9, 0x7b, 0xec} \
+ }
+
+extern EFI_GUID gEfiBlockIoCryptoAlgoAesXtsGuid;
+
+typedef struct {
+ EFI_BLOCK_IO_CRYPTO_IV_INPUT Header;
+ UINT64 CryptoBlockNumber;
+ UINT64 CryptoBlockByteSize;
+} EFI_BLOCK_IO_CRYPTO_IV_INPUT_AES_XTS;
+
+#define EFI_BLOCK_IO_CRYPTO_ALGO_GUID_AES_CBC_MICROSOFT_BITLOCKER \
+ { \
+ 0x689e4c62, 0x70bf, 0x4cf3, {0x88, 0xbb, 0x33, 0xb3, 0x18, 0x26, 0x86, 0x70} \
+ }
+
+extern EFI_GUID gEfiBlockIoCryptoAlgoAesCbcMsBitlockerGuid;
+
+typedef struct {
+ EFI_BLOCK_IO_CRYPTO_IV_INPUT Header;
+ UINT64 CryptoBlockByteOffset;
+ UINT64 CryptoBlockByteSize;
+} EFI_BLOCK_IO_CRYPTO_IV_INPUT_AES_CBC_MICROSOFT_BITLOCKER;
+
+#define EFI_BLOCK_IO_CRYPTO_INDEX_ANY 0xFFFFFFFFFFFFFFFF
+
+typedef struct {
+ //
+ // Is inline cryptographic capability supported on this device.
+ //
+ BOOLEAN Supported;
+ //
+ // Maximum number of keys that can be configured at the same time.
+ //
+ UINT64 KeyCount;
+ //
+ // Number of supported capabilities.
+ //
+ UINT64 CapabilityCount;
+ //
+ // Array of supported capabilities.
+ //
+ EFI_BLOCK_IO_CRYPTO_CAPABILITY Capabilities[1];
+} EFI_BLOCK_IO_CRYPTO_CAPABILITIES;
+
+typedef struct {
+ //
+ // Configuration table index. A special Index EFI_BLOCK_IO_CRYPTO_INDEX_ANY can be
+ // used to set any available entry in the configuration table.
+ //
+ UINT64 Index;
+ //
+ // Identifies the owner of the configuration table entry. Entry can also be used
+ // with the Nil value to clear key from the configuration table index.
+ //
+ EFI_GUID KeyOwnerGuid;
+ //
+ // A supported capability to be used. The CryptoBlockSizeBitMask field of the
+ // structure should have only one bit set from the supported mask.
+ //
+ EFI_BLOCK_IO_CRYPTO_CAPABILITY Capability;
+ //
+ // Pointer to the key. The size of the key is defined by the KeySize field of
+ // the capability specified by the Capability parameter.
+ //
+ VOID *CryptoKey;
+} EFI_BLOCK_IO_CRYPTO_CONFIGURATION_TABLE_ENTRY;
+
+typedef struct {
+ //
+ // Configuration table index.
+ //
+ UINT64 Index;
+ //
+ // Identifies the current owner of the entry.
+ //
+ EFI_GUID KeyOwnerGuid;
+ //
+ // The capability to be used. The CryptoBlockSizeBitMask field of the structure
+ // has only one bit set from the supported mask.
+ //
+ EFI_BLOCK_IO_CRYPTO_CAPABILITY Capability;
+} EFI_BLOCK_IO_CRYPTO_RESPONSE_CONFIGURATION_ENTRY;
+
+/**
+ Reset the block device hardware.
+
+ The Reset() function resets the block device hardware.
+
+ As part of the initialization process, the firmware/device will make a quick but
+ reasonable attempt to verify that the device is functioning.
+
+ If the ExtendedVerificationflag is TRUE the firmware may take an extended amount
+ of time to verify the device is operating on reset. Otherwise the reset operation
+ is to occur as quickly as possible.
+
+ The hardware verification process is not defined by this specification and is left
+ up to the platform firmware or driver to implement.
+
+ @param[in] This Pointer to the EFI_BLOCK_IO_CRYPTO_PROTOCOL instance.
+ @param[in] ExtendedVerification Indicates that the driver may perform a more exhausive
+ verification operation of the device during reset.
+
+ @retval EFI_SUCCESS The block device was reset.
+ @retval EFI_DEVICE_ERROR The block device is not functioning correctly and could
+ not be reset.
+ @retval EFI_INVALID_PARAMETER This is NULL.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_BLOCK_IO_CRYPTO_RESET)(
+ IN EFI_BLOCK_IO_CRYPTO_PROTOCOL *This,
+ IN BOOLEAN ExtendedVerification
+ );
+
+/**
+ Get the capabilities of the underlying inline cryptographic interface.
+
+ The GetCapabilities() function determines whether pre-OS controllable inline crypto
+ is supported by the system for the current disk and, if so, returns the capabilities
+ of the crypto engine.
+
+ The caller is responsible for providing the Capabilities structure with a sufficient
+ number of entries.
+
+ If the structure is too small, the EFI_BUFFER_TOO_SMALL error code is returned and the
+ CapabilityCount field contains the number of entries needed to contain the capabilities.
+
+ @param[in] This Pointer to the EFI_BLOCK_IO_CRYPTO_PROTOCOL instance.
+ @param[out] Capabilities Pointer to the EFI_BLOCK_IO_CRYPTO_CAPABILITIES structure.
+
+ @retval EFI_SUCCESS The ICI is ready for use.
+ @retval EFI_BUFFER_TOO_SMALL The Capabilities structure was too small. The number of
+ entries needed is returned in the CapabilityCount field
+ of the structure.
+ @retval EFI_NO_RESPONSE No response was received from the ICI.
+ @retval EFI_DEVICE_ERROR An error occurred when attempting to access the ICI.
+ @retval EFI_INVALID_PARAMETER This is NULL.
+ @retval EFI_INVALID_PARAMETER Capabilities is NULL.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_BLOCK_IO_CRYPTO_GET_CAPABILITIES)(
+ IN EFI_BLOCK_IO_CRYPTO_PROTOCOL *This,
+ OUT EFI_BLOCK_IO_CRYPTO_CAPABILITIES *Capabilities
+ );
+
+/**
+ Set the configuration of the underlying inline cryptographic interface.
+
+ The SetConfiguration() function allows the user to set the current configuration of the
+ inline cryptographic interface and should be called before attempting any crypto operations.
+
+ This configures the configuration table entries with algorithms, key sizes and keys. Each
+ configured entry can later be referred to by index at the time of storage transaction.
+
+ The configuration table index will refer to the combination ofKeyOwnerGuid, Algorithm, and
+ CryptoKey.
+
+ KeyOwnerGuid identifies the component taking ownership of the entry. It helps components to
+ identify their own entries, cooperate with other owner components, and avoid conflicts. This
+ Guid identifier is there to help coordination between cooperating components and not a security
+ or synchronization feature. The Nil GUID can be used by a component to release use of entry
+ owned. It is also used to identify potentially available entries (see GetConfiguration).
+
+ CryptoKey specifies algorithm-specific key material to use within parameters of selected crypto
+ capability.
+
+ This function is called infrequently typically once, on device start, before IO starts. It
+ can be called at later times in cases the number of keysused on the drive is higher than what
+ can be configured at a time or a new key has to be added.
+
+ Components setting or changing an entry or entries for a given index or indices must ensure
+ that IO referencing affected indices is temporarily blocked (run-down) at the time of change.
+
+ Indices parameters in each parameter table entry allow to set only a portion of the available
+ table entries in the crypto module anywhere from single entry to entire table supported.
+
+ If corresponding table entry or entries being set are already in use by another owner the call
+ should be failed and none of the entries should be modified. The interface implementation must
+ enforce atomicity of this operation (should either succeed fully or fail completely without
+ modifying state).
+
+ Note that components using GetConfiguration command to discover available entries should be
+ prepared that by the time of calling SetConfiguration the previously available entry may have
+ become occupied. Such components should be prepared to re-try the sequence of operations.
+
+ Alternatively EFI_BLOCK_IO_CRYPTO_INDEX_ANY can be used to have the implementation discover
+ and allocate available,if any, indices atomically.
+
+ An optional ResultingTable pointer can be provided by the caller to receive the newly configured
+ entries. The array provided by the caller must have at least ConfigurationCount of entries.
+
+ @param[in] This Pointer to the EFI_BLOCK_IO_CRYPTO_PROTOCOL instance.
+ @param[in] ConfigurationCount Number of entries being configured with this call.
+ @param[in] ConfigurationTable Pointer to a table used to populate the configuration table.
+ @param[out] ResultingTable Optional pointer to a table that receives the newly configured
+ entries.
+
+ @retval EFI_SUCCESS The ICI is ready for use.
+ @retval EFI_NO_RESPONSE No response was received from the ICI.
+ @retval EFI_DEVICE_ERROR An error occurred when attempting to access the ICI.
+ @retval EFI_INVALID_PARAMETER This is NULL.
+ @retval EFI_INVALID_PARAMETER ConfigurationTable is NULL.
+ @retval EFI_INVALID_PARAMETER ConfigurationCount is 0.
+ @retval EFI_OUT_OF_RESOURCES Could not find the requested number of available entries in the
+ configuration table.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_BLOCK_IO_CRYPTO_SET_CONFIGURATION)(
+ IN EFI_BLOCK_IO_CRYPTO_PROTOCOL *This,
+ IN UINT64 ConfigurationCount,
+ IN EFI_BLOCK_IO_CRYPTO_CONFIGURATION_TABLE_ENTRY *ConfigurationTable,
+ OUT EFI_BLOCK_IO_CRYPTO_RESPONSE_CONFIGURATION_ENTRY *ResultingTable OPTIONAL
+ );
+
+/**
+ Get the configuration of the underlying inline cryptographic interface.
+
+ The GetConfiguration() function allows the user to get the configuration of the inline
+ cryptographic interface.
+
+ Retrieves, entirely or partially, the currently configured key table. Note that the keys
+ themselves are not retrieved, but rather just indices, owner GUIDs and capabilities.
+
+ If fewer entries than specified by ConfigurationCount are returned, the Index field of the
+ unused entries is set to EFI_BLOCK_IO_CRYPTO_INDEX_ANY.
+
+ @param[in] This Pointer to the EFI_BLOCK_IO_CRYPTO_PROTOCOL instance.
+ @param[in] StartIndex Configuration table index at which to start the configuration
+ query.
+ @param[in] ConfigurationCount Number of entries to return in the response table.
+ @param[in] KeyOwnerGuid Optional parameter to filter response down to entries with a
+ given owner. A pointer to the Nil value can be used to return
+ available entries. Set to NULL when no owner filtering is required.
+ @param[out] ConfigurationTable Table of configured configuration table entries (with no CryptoKey
+ returned): configuration table index, KeyOwnerGuid, Capability.
+ Should have sufficient space to store up to ConfigurationCount
+ entries.
+
+ @retval EFI_SUCCESS The ICI is ready for use.
+ @retval EFI_NO_RESPONSE No response was received from the ICI.
+ @retval EFI_DEVICE_ERROR An error occurred when attempting to access the ICI.
+ @retval EFI_INVALID_PARAMETER This is NULL.
+ @retval EFI_INVALID_PARAMETER Configuration table is NULL.
+ @retval EFI_INVALID_PARAMETER StartIndex is out of bounds.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_BLOCK_IO_CRYPTO_GET_CONFIGURATION)(
+ IN EFI_BLOCK_IO_CRYPTO_PROTOCOL *This,
+ IN UINT64 StartIndex,
+ IN UINT64 ConfigurationCount,
+ IN EFI_GUID *KeyOwnerGuid OPTIONAL,
+ OUT EFI_BLOCK_IO_CRYPTO_RESPONSE_CONFIGURATION_ENTRY *ConfigurationTable
+ );
+
+/**
+ Reads the requested number of blocks from the device and optionally decrypts
+ them inline.
+
+ TheReadExtended() function allows the caller to perform a storage device read
+ operation. The function reads the requested number of blocks from the device
+ and then if Index is specified decrypts them inline. All the blocks are read
+ and decrypted (if decryption requested), or an error is returned.
+
+ If there is no media in the device, the function returns EFI_NO_MEDIA. If the
+ MediaId is not the ID for the current media in the device, the function returns
+ EFI_MEDIA_CHANGED.
+
+ If EFI_DEVICE_ERROR, EFI_NO_MEDIA, or EFI_MEDIA_CHANGED is returned and nonblocking
+ I/O is being used, the Event associated with this request will not be signaled.
+
+ In addition to standard storage transaction parameters (LBA, IO size, and buffer),
+ this command will also specify a configuration table Index and CryptoIvInput
+ when data has to be decrypted inline by the controller after being read from
+ the storage device. If an Index parameter is not specified, no decryption is
+ performed.
+
+ @param[in] This Pointer to the EFI_BLOCK_IO_CRYPTO_PROTOCOL instance.
+ @param[in] MediaId The media ID that the read request is for.
+ @param[in] LBA The starting logical block address to read from on
+ the device.
+ @param[in, out] Token A pointer to the token associated with the transaction.
+ @param[in] BufferSize The size of the Buffer in bytes. This must be a multiple
+ of the intrinsic block size of the device.
+ @param[out] Buffer A pointer to the destination buffer for the data. The
+ caller is responsible for either having implicit or
+ explicit ownership of the buffer.
+ @param[in] Index A pointer to the configuration table index. This is
+ optional.
+ @param[in] CryptoIvInput A pointer to a buffer that contains additional
+ cryptographic parameters as required by the capability
+ referenced by the configuration table index, such as
+ cryptographic initialization vector.
+
+ @retval EFI_SUCCESS The read request was queued if Token-> Event is not NULL.
+ The data was read correctly from the device if the
+ Token->Event is NULL.
+ @retval EFI_DEVICE_ERROR The device reported an error while attempting to perform
+ the read operation and/or decryption operation.
+ @retval EFI_NO_MEDIA There is no media in the device.
+ @retval EFI_MEDIA_CHANGED The MediaId is not for the current media.
+ @retval EFI_BAD_BUFFER_SIZE The BufferSize parameter is not a multiple of the intrinsic
+ block size of the device.
+ @retval EFI_INVALID_PARAMETER This is NULL, or the read request contains LBAs that are
+ not valid, or the buffer is not on proper alignment.
+ @retval EFI_INVALID_PARAMETER CryptoIvInput is incorrect.
+ @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of
+ resources.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_BLOCK_IO_CRYPTO_READ_EXTENDED)(
+ IN EFI_BLOCK_IO_CRYPTO_PROTOCOL *This,
+ IN UINT32 MediaId,
+ IN EFI_LBA LBA,
+ IN OUT EFI_BLOCK_IO_CRYPTO_TOKEN *Token,
+ IN UINT64 BufferSize,
+ OUT VOID *Buffer,
+ IN UINT64 *Index OPTIONAL,
+ IN VOID *CryptoIvInput OPTIONAL
+ );
+
+/**
+ Optionally encrypts a specified number of blocks inline and then writes to the
+ device.
+
+ The WriteExtended() function allows the caller to perform a storage device write
+ operation. The function encrypts the requested number of blocks inline if Index
+ is specified and then writes them to the device. All the blocks are encrypted
+ (if encryption requested) and written, or an error is returned.
+
+ If there is no media in the device, the function returns EFI_NO_MEDIA. If the
+ MediaId is not the ID for the current media in the device, the function returns
+ EFI_MEDIA_CHANGED.
+
+ If EFI_DEVICE_ERROR, EFI_NO_MEDIA, or EFI_MEDIA_CHANGED is returned and nonblocking
+ I/O is being used, the Event associated with this request will not be signaled.
+
+ In addition to standard storage transaction parameters (LBA, IO size, and buffer),
+ this command will also specify a configuration table Index and a CryptoIvInput
+ when data has to be decrypted inline by the controller before being written to
+ the storage device. If no Index parameter is specified, no encryption is performed.
+
+ @param[in] This Pointer to the EFI_BLOCK_IO_CRYPTO_PROTOCOL instance.
+ @param[in] MediaId The media ID that the read request is for.
+ @param[in] LBA The starting logical block address to read from on
+ the device.
+ @param[in, out] Token A pointer to the token associated with the transaction.
+ @param[in] BufferSize The size of the Buffer in bytes. This must be a multiple
+ of the intrinsic block size of the device.
+ @param[in] Buffer A pointer to the source buffer for the data.
+ @param[in] Index A pointer to the configuration table index. This is
+ optional.
+ @param[in] CryptoIvInput A pointer to a buffer that contains additional
+ cryptographic parameters as required by the capability
+ referenced by the configuration table index, such as
+ cryptographic initialization vector.
+
+ @retval EFI_SUCCESS The request to encrypt (optionally) and write was queued
+ if Event is not NULL. The data was encrypted (optionally)
+ and written correctly to the device if the Event is NULL.
+ @retval EFI_WRITE_PROTECTED The device cannot be written to.
+ @retval EFI_NO_MEDIA There is no media in the device.
+ @retval EFI_MEDIA_CHANGED The MediaId is not for the current media.
+ @retval EFI_DEVICE_ERROR The device reported an error while attempting to encrypt
+ blocks or to perform the write operation.
+ @retval EFI_BAD_BUFFER_SIZE The BufferSize parameter is not a multiple of the intrinsic
+ block size of the device.
+ @retval EFI_INVALID_PARAMETER This is NULL, or the write request contains LBAs that are
+ not valid, or the buffer is not on proper alignment.
+ @retval EFI_INVALID_PARAMETER CryptoIvInput is incorrect.
+ @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of
+ resources.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_BLOCK_IO_CRYPTO_WRITE_EXTENDED)(
+ IN EFI_BLOCK_IO_CRYPTO_PROTOCOL *This,
+ IN UINT32 MediaId,
+ IN EFI_LBA LBA,
+ IN OUT EFI_BLOCK_IO_CRYPTO_TOKEN *Token,
+ IN UINT64 BufferSize,
+ IN VOID *Buffer,
+ IN UINT64 *Index OPTIONAL,
+ IN VOID *CryptoIvInput OPTIONAL
+ );
+
+/**
+ Flushes all modified data toa physical block device.
+
+ The FlushBlocks() function flushes all modified data to the physical block device.
+ Any modified data that has to be encrypted must have been already encrypted as a
+ part of WriteExtended() operation - inline crypto operation cannot be a part of
+ flush operation.
+
+ All data written to the device prior to the flush must be physically written before
+ returning EFI_SUCCESS from this function. This would include any cached data the
+ driver may have cached, and cached data the device may have cached. A flush may
+ cause a read request following the flush to force a device access.
+
+ If EFI_DEVICE_ERROR, EFI_NO_MEDIA, EFI_WRITE_PROTECTED or EFI_MEDIA_CHANGED is
+ returned and non-blocking I/O is being used, the Event associated with this request
+ will not be signaled.
+
+ @param[in] This Pointer to the EFI_BLOCK_IO_CRYPTO_PROTOCOL instance.
+ @param[in, out] Token A pointer to the token associated with the transaction.
+
+ @retval EFI_SUCCESS The flush request was queued if Event is not NULL. All
+ outstanding data was written correctly to the device if
+ the Event is NULL.
+ @retval EFI_DEVICE_ERROR The device reported an error while attempting to write data.
+ @retval EFI_WRITE_PROTECTED The device cannot be written to.
+ @retval EFI_NO_MEDIA There is no media in the device.
+ @retval EFI_MEDIA_CHANGED The MediaId is not for the current media.
+ @retval EFI_INVALID_PARAMETER This is NULL.
+ @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of
+ resources.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_BLOCK_IO_CRYPTO_FLUSH)(
+ IN EFI_BLOCK_IO_CRYPTO_PROTOCOL *This,
+ IN OUT EFI_BLOCK_IO_CRYPTO_TOKEN *Token
+ );
+
+///
+/// The EFI_BLOCK_IO_CRYPTO_PROTOCOL defines a UEFI protocol that can be used by UEFI
+/// drivers and applications to perform block encryption on a storage device, such as UFS.
+///
+struct _EFI_BLOCK_IO_CRYPTO_PROTOCOL {
+ EFI_BLOCK_IO_MEDIA *Media;
+ EFI_BLOCK_IO_CRYPTO_RESET Reset;
+ EFI_BLOCK_IO_CRYPTO_GET_CAPABILITIES GetCapabilities;
+ EFI_BLOCK_IO_CRYPTO_SET_CONFIGURATION SetConfiguration;
+ EFI_BLOCK_IO_CRYPTO_GET_CONFIGURATION GetConfiguration;
+ EFI_BLOCK_IO_CRYPTO_READ_EXTENDED ReadExtended;
+ EFI_BLOCK_IO_CRYPTO_WRITE_EXTENDED WriteExtended;
+ EFI_BLOCK_IO_CRYPTO_FLUSH FlushBlocks;
+};
+
+extern EFI_GUID gEfiBlockIoCryptoProtocolGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/BluetoothAttribute.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/BluetoothAttribute.h
new file mode 100644
index 0000000000..83a8807a30
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/BluetoothAttribute.h
@@ -0,0 +1,274 @@
+/** @file
+ EFI Bluetooth Attribute Protocol as defined in UEFI 2.7.
+ This protocol provides service for Bluetooth ATT (Attribute Protocol) and GATT (Generic
+ Attribute Profile) based protocol interfaces.
+
+ Copyright (c) 2017, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Revision Reference:
+ This Protocol is introduced in UEFI Specification 2.7
+
+**/
+
+#ifndef __EFI_BLUETOOTH_ATTRIBUTE_H__
+#define __EFI_BLUETOOTH_ATTRIBUTE_H__
+
+#define EFI_BLUETOOTH_ATTRIBUTE_SERVICE_BINDING_PROTOCOL_GUID \
+ { \
+ 0x5639867a, 0x8c8e, 0x408d, { 0xac, 0x2f, 0x4b, 0x61, 0xbd, 0xc0, 0xbb, 0xbb } \
+ }
+
+#define EFI_BLUETOOTH_ATTRIBUTE_PROTOCOL_GUID \
+ { \
+ 0x898890e9, 0x84b2, 0x4f3a, { 0x8c, 0x58, 0xd8, 0x57, 0x78, 0x13, 0xe0, 0xac } \
+ }
+
+typedef struct _EFI_BLUETOOTH_ATTRIBUTE_PROTOCOL EFI_BLUETOOTH_ATTRIBUTE_PROTOCOL;
+
+#pragma pack(1)
+
+//
+// Bluetooth UUID
+//
+typedef struct {
+ UINT8 Length;
+ union {
+ UINT16 Uuid16;
+ UINT32 Uuid32;
+ UINT8 Uuid128[16];
+ } Data;
+} EFI_BLUETOOTH_UUID;
+
+#define UUID_16BIT_TYPE_LEN 2
+#define UUID_32BIT_TYPE_LEN 4
+#define UUID_128BIT_TYPE_LEN 16
+
+#define BLUETOOTH_IS_ATTRIBUTE_OF_TYPE(a, t) ((a)->Type.Length == UUID_16BIT_TYPE_LEN && (a)->Type.Data.Uuid16 == (t))
+
+//
+// Bluetooth Attribute Permission
+//
+typedef union {
+ struct {
+ UINT16 Readable : 1;
+ UINT16 ReadEncryption : 1;
+ UINT16 ReadAuthentication : 1;
+ UINT16 ReadAuthorization : 1;
+ UINT16 ReadKeySize : 5;
+ UINT16 Reserved1 : 7;
+ UINT16 Writeable : 1;
+ UINT16 WriteEncryption : 1;
+ UINT16 WriteAuthentication : 1;
+ UINT16 WriteAuthorization : 1;
+ UINT16 WriteKeySize : 5;
+ UINT16 Reserved2 : 7;
+ } Permission;
+ UINT32 Data32;
+} EFI_BLUETOOTH_ATTRIBUTE_PERMISSION;
+
+typedef struct {
+ EFI_BLUETOOTH_UUID Type;
+ UINT16 Length;
+ UINT16 AttributeHandle;
+ EFI_BLUETOOTH_ATTRIBUTE_PERMISSION AttributePermission;
+} EFI_BLUETOOTH_ATTRIBUTE_HEADER;
+
+typedef struct {
+ EFI_BLUETOOTH_ATTRIBUTE_HEADER Header;
+ UINT16 EndGroupHandle;
+ EFI_BLUETOOTH_UUID ServiceUuid;
+} EFI_BLUETOOTH_GATT_PRIMARY_SERVICE_INFO;
+
+typedef struct {
+ EFI_BLUETOOTH_ATTRIBUTE_HEADER Header;
+ UINT16 StartGroupHandle;
+ UINT16 EndGroupHandle;
+ EFI_BLUETOOTH_UUID ServiceUuid;
+} EFI_BLUETOOTH_GATT_INCLUDE_SERVICE_INFO;
+
+typedef struct {
+ EFI_BLUETOOTH_ATTRIBUTE_HEADER Header;
+ UINT8 CharacteristicProperties;
+ UINT16 CharacteristicValueHandle;
+ EFI_BLUETOOTH_UUID CharacteristicUuid;
+} EFI_BLUETOOTH_GATT_CHARACTERISTIC_INFO;
+
+typedef struct {
+ EFI_BLUETOOTH_ATTRIBUTE_HEADER Header;
+ EFI_BLUETOOTH_UUID CharacteristicDescriptorUuid;
+} EFI_BLUETOOTH_GATT_CHARACTERISTIC_DESCRIPTOR_INFO;
+
+#pragma pack()
+
+typedef struct {
+ UINT16 AttributeHandle;
+} EFI_BLUETOOTH_ATTRIBUTE_CALLBACK_PARAMETER_NOTIFICATION;
+
+typedef struct {
+ UINT16 AttributeHandle;
+} EFI_BLUETOOTH_ATTRIBUTE_CALLBACK_PARAMETER_INDICATION;
+
+typedef struct {
+ UINT32 Version;
+ UINT8 AttributeOpCode;
+ union {
+ EFI_BLUETOOTH_ATTRIBUTE_CALLBACK_PARAMETER_NOTIFICATION Notification;
+ EFI_BLUETOOTH_ATTRIBUTE_CALLBACK_PARAMETER_INDICATION Indication;
+ } Parameter;
+} EFI_BLUETOOTH_ATTRIBUTE_CALLBACK_PARAMETER;
+
+typedef struct {
+ UINT32 Version;
+ BLUETOOTH_LE_ADDRESS BD_ADDR;
+ BLUETOOTH_LE_ADDRESS DirectAddress;
+ UINT8 RSSI;
+ UINTN AdvertisementDataSize;
+ VOID *AdvertisementData;
+} EFI_BLUETOOTH_LE_DEVICE_INFO;
+
+/**
+ The callback function to send request.
+
+ @param[in] This Pointer to the EFI_BLUETOOTH_ATTRIBUTE_PROTOCOL instance.
+ @param[in] Data Data received. The first byte is the attribute opcode, followed by opcode specific
+ fields. See Bluetooth specification, Vol 3, Part F, Attribute Protocol. It might be a
+ normal RESPONSE message, or ERROR RESPONSE messag
+ @param[in] DataLength The length of Data in bytes.
+ @param[in] Context The context passed from the callback registration request.
+
+ @retval EFI_SUCCESS The callback function complete successfully.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_BLUETOOTH_ATTRIBUTE_CALLBACK_FUNCTION)(
+ IN EFI_BLUETOOTH_ATTRIBUTE_PROTOCOL *This,
+ IN VOID *Data,
+ IN UINTN DataLength,
+ IN VOID *Context
+ );
+
+/**
+ Send a "REQUEST" or "COMMAND" message to remote server and receive a "RESPONSE" message
+ for "REQUEST" from remote server according to Bluetooth attribute protocol data unit(PDU).
+
+ @param[in] This Pointer to the EFI_BLUETOOTH_ATTRIBUTE_PROTOCOL instance.
+ @param[in] Data Data of a REQUEST or COMMAND message. The first byte is the attribute PDU
+ related opcode, followed by opcode specific fields. See Bluetooth specification,
+ Vol 3, Part F, Attribute Protocol.
+ @param[in] DataLength The length of Data in bytes.
+ @param[in] Callback Callback function to notify the RESPONSE is received to the caller, with the
+ response buffer. Caller must check the response buffer content to know if the
+ request action is success or fail. It may be NULL if the data is a COMMAND.
+ @param[in] Context Data passed into Callback function. It is optional parameter and may be NULL.
+
+ @retval EFI_SUCCESS The request is sent successfully.
+ @retval EFI_INVALID_PARAMETER One or more parameters are invalid due to following conditions:
+ - The Buffer is NULL.
+ - The BufferLength is 0.
+ - The opcode in Buffer is not a valid OPCODE according to Bluetooth specification.
+ - The Callback is NULL.
+ @retval EFI_DEVICE_ERROR Sending the request failed due to the host controller or the device error.
+ @retval EFI_NOT_READY A GATT operation is already underway for this device.
+ @retval EFI_UNSUPPORTED The attribute does not support the corresponding operation.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_BLUETOOTH_ATTRIBUTE_SEND_REQUEST)(
+ IN EFI_BLUETOOTH_ATTRIBUTE_PROTOCOL *This,
+ IN VOID *Data,
+ IN UINTN DataLength,
+ IN EFI_BLUETOOTH_ATTRIBUTE_CALLBACK_FUNCTION Callback,
+ IN VOID *Context
+ );
+
+/**
+ Register or unregister a server initiated message, such as NOTIFICATION or INDICATION, on a
+ characteristic value on remote server.
+
+ @param[in] This Pointer to the EFI_BLUETOOTH_ATTRIBUTE_PROTOCOL instance.
+ @param[in] CallbackParameter The parameter of the callback.
+ @param[in] Callback Callback function for server initiated attribute protocol. NULL callback
+ function means unregister the server initiated callback.
+ @param[in] Context Data passed into Callback function. It is optional parameter and may be NULL.
+
+ @retval EFI_SUCCESS The callback function is registered or unregistered successfully
+ @retval EFI_INVALID_PARAMETER The attribute opcode is not server initiated message opcode. See
+ Bluetooth specification, Vol 3, Part F, Attribute Protocol.
+ @retval EFI_ALREADY_STARTED A callback function is already registered on the same attribute
+ opcode and attribute handle, when the Callback is not NULL.
+ @retval EFI_NOT_STARTED A callback function is not registered on the same attribute opcode
+ and attribute handle, when the Callback is NULL.
+ @retval EFI_NOT_READY A GATT operation is already underway for this device.
+ @retval EFI_UNSUPPORTED The attribute does not support notification.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_BLUETOOTH_ATTRIBUTE_REGISTER_FOR_SERVER_NOTIFICATION)(
+ IN EFI_BLUETOOTH_ATTRIBUTE_PROTOCOL *This,
+ IN EFI_BLUETOOTH_ATTRIBUTE_CALLBACK_PARAMETER *CallbackParameter,
+ IN EFI_BLUETOOTH_ATTRIBUTE_CALLBACK_FUNCTION Callback,
+ IN VOID *Context
+ );
+
+/**
+ Get Bluetooth discovered service information.
+
+ @param[in] This Pointer to the EFI_BLUETOOTH_ATTRIBUTE_PROTOCOL instance.
+ @param[out] ServiceInfoSize A pointer to the size, in bytes, of the ServiceInfo buffer.
+ @param[out] ServiceInfo A pointer to a callee allocated buffer that returns Bluetooth
+ discovered service information. Callee allocates this buffer by
+ using EFI Boot Service AllocatePool().
+
+ @retval EFI_SUCCESS The Bluetooth discovered service information is returned successfully.
+ @retval EFI_DEVICE_ERROR A hardware error occurred trying to retrieve the Bluetooth discovered
+ service information.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_BLUETOOTH_ATTRIBUTE_GET_SERVICE_INFO)(
+ IN EFI_BLUETOOTH_ATTRIBUTE_PROTOCOL *This,
+ OUT UINTN *ServiceInfoSize,
+ OUT VOID **ServiceInfo
+ );
+
+/**
+ Get Bluetooth device information.
+
+ @param[in] This Pointer to the EFI_BLUETOOTH_ATTRIBUTE_PROTOCOL instance.
+ @param[out] DeviceInfoSize A pointer to the size, in bytes, of the DeviceInfo buffer.
+ @param[out] DeviceInfo A pointer to a callee allocated buffer that returns Bluetooth
+ device information. Callee allocates this buffer by using EFI Boot
+ Service AllocatePool(). If this device is Bluetooth classic
+ device, EFI_BLUETOOTH_DEVICE_INFO should be used. If
+ this device is Bluetooth LE device, EFI_BLUETOOTH_LE_DEVICE_INFO
+ should be used.
+
+ @retval EFI_SUCCESS The Bluetooth device information is returned successfully.
+ @retval EFI_DEVICE_ERROR A hardware error occurred trying to retrieve the Bluetooth device
+ information
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_BLUETOOTH_ATTRIBUTE_GET_DEVICE_INFO)(
+ IN EFI_BLUETOOTH_ATTRIBUTE_PROTOCOL *This,
+ OUT UINTN *DeviceInfoSize,
+ OUT VOID **DeviceInfo
+ );
+
+struct _EFI_BLUETOOTH_ATTRIBUTE_PROTOCOL {
+ EFI_BLUETOOTH_ATTRIBUTE_SEND_REQUEST SendRequest;
+ EFI_BLUETOOTH_ATTRIBUTE_REGISTER_FOR_SERVER_NOTIFICATION RegisterForServerNotification;
+ EFI_BLUETOOTH_ATTRIBUTE_GET_SERVICE_INFO GetServiceInfo;
+ EFI_BLUETOOTH_ATTRIBUTE_GET_DEVICE_INFO GetDeviceInfo;
+};
+
+extern EFI_GUID gEfiBluetoothAttributeProtocolGuid;
+extern EFI_GUID gEfiBluetoothAttributeServiceBindingProtocolGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/BluetoothConfig.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/BluetoothConfig.h
new file mode 100644
index 0000000000..55e621cd6a
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/BluetoothConfig.h
@@ -0,0 +1,522 @@
+/** @file
+ EFI Bluetooth Configuration Protocol as defined in UEFI 2.7.
+ This protocol abstracts user interface configuration for Bluetooth device.
+
+ Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Revision Reference:
+ This Protocol is introduced in UEFI Specification 2.7
+
+**/
+
+#ifndef __EFI_BLUETOOTH_CONFIG_PROTOCOL_H__
+#define __EFI_BLUETOOTH_CONFIG_PROTOCOL_H__
+
+#include
+
+#define EFI_BLUETOOTH_CONFIG_PROTOCOL_GUID \
+ { \
+ 0x62960cf3, 0x40ff, 0x4263, { 0xa7, 0x7c, 0xdf, 0xde, 0xbd, 0x19, 0x1b, 0x4b } \
+ }
+
+typedef struct _EFI_BLUETOOTH_CONFIG_PROTOCOL EFI_BLUETOOTH_CONFIG_PROTOCOL;
+
+typedef UINT32 EFI_BLUETOOTH_CONFIG_REMOTE_DEVICE_STATE_TYPE;
+#define EFI_BLUETOOTH_CONFIG_REMOTE_DEVICE_STATE_CONNECTED 0x1
+#define EFI_BLUETOOTH_CONFIG_REMOTE_DEVICE_STATE_PAIRED 0x2
+
+///
+/// EFI_BLUETOOTH_SCAN_CALLBACK_INFORMATION
+///
+typedef struct {
+ ///
+ /// 48bit Bluetooth device address.
+ ///
+ BLUETOOTH_ADDRESS BDAddr;
+ ///
+ /// State of the remote deive
+ ///
+ UINT8 RemoteDeviceState;
+ ///
+ /// Bluetooth ClassOfDevice. See Bluetooth specification for detail.
+ ///
+ BLUETOOTH_CLASS_OF_DEVICE ClassOfDevice;
+ ///
+ /// Remote device name
+ ///
+ UINT8 RemoteDeviceName[BLUETOOTH_HCI_COMMAND_LOCAL_READABLE_NAME_MAX_SIZE];
+} EFI_BLUETOOTH_SCAN_CALLBACK_INFORMATION;
+
+///
+/// EFI_BLUETOOTH_CONFIG_DATA_TYPE
+///
+typedef enum {
+ ///
+ /// Local/Remote Bluetooth device name. Data structure is zero terminated CHAR8[].
+ ///
+ EfiBluetoothConfigDataTypeDeviceName,
+ ///
+ /// Local/Remote Bluetooth device ClassOfDevice. Data structure is BLUETOOTH_CLASS_OF_DEVICE.
+ ///
+ EfiBluetoothConfigDataTypeClassOfDevice,
+ ///
+ /// Remote Bluetooth device state. Data structure is EFI_BLUETOOTH_CONFIG_REMOTE_DEVICE_STATE_TYPE.
+ ///
+ EfiBluetoothConfigDataTypeRemoteDeviceState, /* Relevant for LE*/
+ ///
+ /// Local/Remote Bluetooth device SDP information. Data structure is UINT8[].
+ ///
+ EfiBluetoothConfigDataTypeSdpInfo,
+ ///
+ /// Local Bluetooth device address. Data structure is BLUETOOTH_ADDRESS.
+ ///
+ EfiBluetoothConfigDataTypeBDADDR, /* Relevant for LE*/
+ ///
+ /// Local Bluetooth discoverable state. Data structure is UINT8. (Page scan and/or Inquiry scan)
+ ///
+ EfiBluetoothConfigDataTypeDiscoverable, /* Relevant for LE*/
+ ///
+ /// Local Bluetooth controller stored paired device list. Data structure is BLUETOOTH_ADDRESS[].
+ ///
+ EfiBluetoothConfigDataTypeControllerStoredPairedDeviceList,
+ ///
+ /// Local available device list. Data structure is BLUETOOTH_ADDRESS[].
+ ///
+ EfiBluetoothConfigDataTypeAvailableDeviceList,
+ EfiBluetoothConfigDataTypeRandomAddress, /* Relevant for LE*/
+ EfiBluetoothConfigDataTypeRSSI, /* Relevant for LE*/
+ ///
+ /// Advertisement report. Data structure is UNIT8[].
+ ///
+ EfiBluetoothConfigDataTypeAdvertisementData, /* Relevant for LE*/
+ EfiBluetoothConfigDataTypeIoCapability, /* Relevant for LE*/
+ EfiBluetoothConfigDataTypeOOBDataFlag, /* Relevant for LE*/
+ ///
+ /// KeyType of Authentication Requirements flag of local
+ /// device as UINT8, indicating requested security properties.
+ /// See Bluetooth specification 3.H.3.5.1. BIT0: MITM, BIT1:SC.
+ ///
+ EfiBluetoothConfigDataTypeKeyType, /* Relevant for LE*/
+ EfiBluetoothConfigDataTypeEncKeySize, /* Relevant for LE*/
+ EfiBluetoothConfigDataTypeMax,
+} EFI_BLUETOOTH_CONFIG_DATA_TYPE;
+
+///
+/// EFI_BLUETOOTH_PIN_CALLBACK_TYPE.
+///
+typedef enum {
+ ///
+ /// For SSP - passkey entry. Input buffer is Passkey (4 bytes). No output buffer.
+ /// See Bluetooth HCI command for detail.
+ ///
+ EfiBluetoothCallbackTypeUserPasskeyNotification,
+ ///
+ /// For SSP - just work and numeric comparison. Input buffer is numeric value (4 bytes).
+ /// Output buffer is BOOLEAN (1 byte). See Bluetooth HCI command for detail.
+ ///
+ EfiBluetoothCallbackTypeUserConfirmationRequest,
+ ///
+ /// For SSP - OOB. See Bluetooth HCI command for detail.
+ ///
+ EfiBluetoothCallbackTypeOOBDataRequest,
+ ///
+ /// For legacy paring. No input buffer. Output buffer is PIN code( <= 16 bytes).
+ /// See Bluetooth HCI command for detail.
+ ///
+ EfiBluetoothCallbackTypePinCodeRequest,
+ EfiBluetoothCallbackTypeMax
+} EFI_BLUETOOTH_PIN_CALLBACK_TYPE;
+
+///
+/// EFI_BLUETOOTH_CONNECT_COMPLETE_CALLBACK_TYPE.
+///
+typedef enum {
+ ///
+ /// This callback is called when Bluetooth receive Disconnection_Complete event. Input buffer is Event
+ /// Parameters of Disconnection_Complete Event defined in Bluetooth specification.
+ ///
+ EfiBluetoothConnCallbackTypeDisconnected,
+ ///
+ /// This callback is called when Bluetooth receive Connection_Complete event. Input buffer is Event
+ /// Parameters of Connection_Complete Event defined in Bluetooth specification.
+ ///
+ EfiBluetoothConnCallbackTypeConnected,
+ ///
+ /// This callback is called when Bluetooth receive Authentication_Complete event. Input buffer is Event
+ /// Parameters of Authentication_Complete Event defined in Bluetooth specification.
+ ///
+ EfiBluetoothConnCallbackTypeAuthenticated,
+ ///
+ /// This callback is called when Bluetooth receive Encryption_Change event. Input buffer is Event
+ /// Parameters of Encryption_Change Event defined in Bluetooth specification.
+ ///
+ EfiBluetoothConnCallbackTypeEncrypted
+} EFI_BLUETOOTH_CONNECT_COMPLETE_CALLBACK_TYPE;
+
+/**
+ Initialize Bluetooth host controller and local device.
+
+ @param This Pointer to the EFI_BLUETOOTH_CONFIG_PROTOCOL instance.
+
+ @retval EFI_SUCCESS The Bluetooth host controller and local device is initialized successfully.
+ @retval EFI_DEVICE_ERROR A hardware error occurred trying to initialize the Bluetooth host controller
+ and local device.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_BLUETOOTH_CONFIG_INIT)(
+ IN EFI_BLUETOOTH_CONFIG_PROTOCOL *This
+ );
+
+/**
+ Callback function, it is called if a Bluetooth device is found during scan process.
+
+ @param This Pointer to the EFI_BLUETOOTH_CONFIG_PROTOCOL instance.
+ @param Context Context passed from scan request.
+ @param CallbackInfo Data related to scan result. NULL CallbackInfo means scan complete.
+
+ @retval EFI_SUCCESS The callback function complete successfully.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_BLUETOOTH_CONFIG_SCAN_CALLBACK_FUNCTION)(
+ IN EFI_BLUETOOTH_CONFIG_PROTOCOL *This,
+ IN VOID *Context,
+ IN EFI_BLUETOOTH_SCAN_CALLBACK_INFORMATION *CallbackInfo
+ );
+
+/**
+ Scan Bluetooth device.
+
+ @param This Pointer to the EFI_BLUETOOTH_CONFIG_PROTOCOL instance.
+ @param ReScan If TRUE, a new scan request is submitted no matter there is scan result before.
+ If FALSE and there is scan result, the previous scan result is returned and no scan request
+ is submitted.
+ @param ScanType Bluetooth scan type, Inquiry and/or Page. See Bluetooth specification for detail.
+ @param Callback The callback function. This function is called if a Bluetooth device is found during scan
+ process.
+ @param Context Data passed into Callback function. This is optional parameter and may be NULL.
+
+ @retval EFI_SUCCESS The Bluetooth scan request is submitted.
+ @retval EFI_DEVICE_ERROR A hardware error occurred trying to scan the Bluetooth device.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_BLUETOOTH_CONFIG_SCAN)(
+ IN EFI_BLUETOOTH_CONFIG_PROTOCOL *This,
+ IN BOOLEAN ReScan,
+ IN UINT8 ScanType,
+ IN EFI_BLUETOOTH_CONFIG_SCAN_CALLBACK_FUNCTION Callback,
+ IN VOID *Context
+ );
+
+/**
+ Connect a Bluetooth device.
+
+ @param This Pointer to the EFI_BLUETOOTH_CONFIG_PROTOCOL instance.
+ @param BD_ADDR The address of Bluetooth device to be connected.
+
+ @retval EFI_SUCCESS The Bluetooth device is connected successfully.
+ @retval EFI_ALREADY_STARTED The Bluetooth device is already connected.
+ @retval EFI_NOT_FOUND The Bluetooth device is not found.
+ @retval EFI_DEVICE_ERROR A hardware error occurred trying to connect the Bluetooth device.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_BLUETOOTH_CONFIG_CONNECT)(
+ IN EFI_BLUETOOTH_CONFIG_PROTOCOL *This,
+ IN BLUETOOTH_ADDRESS *BD_ADDR
+ );
+
+/**
+ Disconnect a Bluetooth device.
+
+ @param This Pointer to the EFI_BLUETOOTH_CONFIG_PROTOCOL instance.
+ @param BD_ADDR The address of Bluetooth device to be connected.
+ @param Reason Bluetooth disconnect reason. See Bluetooth specification for detail.
+
+ @retval EFI_SUCCESS The Bluetooth device is disconnected successfully.
+ @retval EFI_NOT_STARTED The Bluetooth device is not connected.
+ @retval EFI_NOT_FOUND The Bluetooth device is not found.
+ @retval EFI_DEVICE_ERROR A hardware error occurred trying to disconnect the Bluetooth device.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_BLUETOOTH_CONFIG_DISCONNECT)(
+ IN EFI_BLUETOOTH_CONFIG_PROTOCOL *This,
+ IN BLUETOOTH_ADDRESS *BD_ADDR,
+ IN UINT8 Reason
+ );
+
+/**
+ Get Bluetooth configuration data.
+
+ @param This Pointer to the EFI_BLUETOOTH_CONFIG_PROTOCOL instance.
+ @param DataType Configuration data type.
+ @param DataSize On input, indicates the size, in bytes, of the data buffer specified by Data.
+ On output, indicates the amount of data actually returned.
+ @param Data A pointer to the buffer of data that will be returned.
+
+ @retval EFI_SUCCESS The Bluetooth configuration data is returned successfully.
+ @retval EFI_INVALID_PARAMETER One or more of the following conditions is TRUE:
+ - DataSize is NULL.
+ - *DataSize is not 0 and Data is NULL.
+ @retval EFI_UNSUPPORTED The DataType is unsupported.
+ @retval EFI_NOT_FOUND The DataType is not found.
+ @retval EFI_BUFFER_TOO_SMALL The buffer is too small to hold the buffer.
+ *DataSize has been updated with the size needed to complete the request.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_BLUETOOTH_CONFIG_GET_DATA)(
+ IN EFI_BLUETOOTH_CONFIG_PROTOCOL *This,
+ IN EFI_BLUETOOTH_CONFIG_DATA_TYPE DataType,
+ IN OUT UINTN *DataSize,
+ IN OUT VOID *Data
+ );
+
+/**
+ Set Bluetooth configuration data.
+
+ @param This Pointer to the EFI_BLUETOOTH_CONFIG_PROTOCOL instance.
+ @param DataType Configuration data type.
+ @param DataSize Indicates the size, in bytes, of the data buffer specified by Data.
+ @param Data A pointer to the buffer of data that will be set.
+
+ @retval EFI_SUCCESS The Bluetooth configuration data is set successfully.
+ @retval EFI_INVALID_PARAMETER One or more of the following conditions is TRUE:
+ - DataSize is 0.
+ - Data is NULL.
+ @retval EFI_UNSUPPORTED The DataType is unsupported.
+ @retval EFI_BUFFER_TOO_SMALL Cannot set configuration data.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_BLUETOOTH_CONFIG_SET_DATA)(
+ IN EFI_BLUETOOTH_CONFIG_PROTOCOL *This,
+ IN EFI_BLUETOOTH_CONFIG_DATA_TYPE DataType,
+ IN UINTN DataSize,
+ IN VOID *Data
+ );
+
+/**
+ Get remove Bluetooth device configuration data.
+
+ @param This Pointer to the EFI_BLUETOOTH_CONFIG_PROTOCOL instance.
+ @param DataType Configuration data type.
+ @param BDAddr Remote Bluetooth device address.
+ @param DataSize On input, indicates the size, in bytes, of the data buffer specified by Data.
+ On output, indicates the amount of data actually returned.
+ @param Data A pointer to the buffer of data that will be returned.
+
+ @retval EFI_SUCCESS The remote Bluetooth device configuration data is returned successfully.
+ @retval EFI_INVALID_PARAMETER One or more of the following conditions is TRUE:
+ - DataSize is NULL.
+ - *DataSize is not 0 and Data is NULL.
+ @retval EFI_UNSUPPORTED The DataType is unsupported.
+ @retval EFI_NOT_FOUND The DataType is not found.
+ @retval EFI_BUFFER_TOO_SMALL The buffer is too small to hold the buffer.
+ *DataSize has been updated with the size needed to complete the request.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_BLUETOOTH_CONFIG_GET_REMOTE_DATA)(
+ IN EFI_BLUETOOTH_CONFIG_PROTOCOL *This,
+ IN EFI_BLUETOOTH_CONFIG_DATA_TYPE DataType,
+ IN BLUETOOTH_ADDRESS *BDAddr,
+ IN OUT UINTN *DataSize,
+ IN OUT VOID *Data
+ );
+
+/**
+ The callback function for PIN code.
+
+ @param This Pointer to the EFI_BLUETOOTH_CONFIG_PROTOCOL instance.
+ @param Context Context passed from registration.
+ @param CallbackType Callback type in EFI_BLUETOOTH_PIN_CALLBACK_TYPE.
+ @param InputBuffer A pointer to the buffer of data that is input from callback caller.
+ @param InputBufferSize Indicates the size, in bytes, of the data buffer specified by InputBuffer.
+ @param OutputBuffer A pointer to the buffer of data that will be output from callback callee.
+ Callee allocates this buffer by using EFI Boot Service AllocatePool().
+ @param OutputBufferSize Indicates the size, in bytes, of the data buffer specified by OutputBuffer.
+
+ @retval EFI_SUCCESS The callback function complete successfully.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_BLUETOOTH_CONFIG_REGISTER_PIN_CALLBACK_FUNCTION)(
+ IN EFI_BLUETOOTH_CONFIG_PROTOCOL *This,
+ IN VOID *Context,
+ IN EFI_BLUETOOTH_PIN_CALLBACK_TYPE CallbackType,
+ IN VOID *InputBuffer,
+ IN UINTN InputBufferSize,
+ OUT VOID **OutputBuffer,
+ OUT UINTN *OutputBufferSize
+ );
+
+/**
+ Register PIN callback function.
+
+ @param This Pointer to the EFI_BLUETOOTH_CONFIG_PROTOCOL instance.
+ @param Callback The callback function. NULL means unregister.
+ @param Context Data passed into Callback function. This is optional parameter and may be NULL.
+
+ @retval EFI_SUCCESS The PIN callback function is registered successfully.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_BLUETOOTH_CONFIG_REGISTER_PIN_CALLBACK)(
+ IN EFI_BLUETOOTH_CONFIG_PROTOCOL *This,
+ IN EFI_BLUETOOTH_CONFIG_REGISTER_PIN_CALLBACK_FUNCTION Callback,
+ IN VOID *Context
+ );
+
+/**
+ The callback function to get link key.
+
+ @param This Pointer to the EFI_BLUETOOTH_CONFIG_PROTOCOL instance.
+ @param Context Context passed from registration.
+ @param BDAddr A pointer to Bluetooth device address.
+ @param LinkKey A pointer to the buffer of link key.
+
+ @retval EFI_SUCCESS The callback function complete successfully.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_BLUETOOTH_CONFIG_REGISTER_GET_LINK_KEY_CALLBACK_FUNCTION)(
+ IN EFI_BLUETOOTH_CONFIG_PROTOCOL *This,
+ IN VOID *Context,
+ IN BLUETOOTH_ADDRESS *BDAddr,
+ OUT UINT8 LinkKey[BLUETOOTH_HCI_LINK_KEY_SIZE]
+ );
+
+/**
+ Register get link key callback function.
+
+ @param This Pointer to the EFI_BLUETOOTH_CONFIG_PROTOCOL instance.
+ @param Callback The callback function. NULL means unregister.
+ @param Context Data passed into Callback function. This is optional parameter and may be NULL.
+
+ @retval EFI_SUCCESS The link key callback function is registered successfully.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_BLUETOOTH_CONFIG_REGISTER_GET_LINK_KEY_CALLBACK)(
+ IN EFI_BLUETOOTH_CONFIG_PROTOCOL *This,
+ IN EFI_BLUETOOTH_CONFIG_REGISTER_GET_LINK_KEY_CALLBACK_FUNCTION Callback,
+ IN VOID *Context
+ );
+
+/**
+ The callback function to set link key.
+
+ @param This Pointer to the EFI_BLUETOOTH_CONFIG_PROTOCOL instance.
+ @param Context Context passed from registration.
+ @param BDAddr A pointer to Bluetooth device address.
+ @param LinkKey A pointer to the buffer of link key.
+
+ @retval EFI_SUCCESS The callback function complete successfully.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_BLUETOOTH_CONFIG_REGISTER_SET_LINK_KEY_CALLBACK_FUNCTION)(
+ IN EFI_BLUETOOTH_CONFIG_PROTOCOL *This,
+ IN VOID *Context,
+ IN BLUETOOTH_ADDRESS *BDAddr,
+ IN UINT8 LinkKey[BLUETOOTH_HCI_LINK_KEY_SIZE]
+ );
+
+/**
+ Register set link key callback function.
+
+ @param This Pointer to the EFI_BLUETOOTH_CONFIG_PROTOCOL instance.
+ @param Callback The callback function. NULL means unregister.
+ @param Context Data passed into Callback function. This is optional parameter and may be NULL.
+
+ @retval EFI_SUCCESS The link key callback function is registered successfully.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_BLUETOOTH_CONFIG_REGISTER_SET_LINK_KEY_CALLBACK)(
+ IN EFI_BLUETOOTH_CONFIG_PROTOCOL *This,
+ IN EFI_BLUETOOTH_CONFIG_REGISTER_SET_LINK_KEY_CALLBACK_FUNCTION Callback,
+ IN VOID *Context
+ );
+
+/**
+ The callback function. It is called after connect completed.
+
+ @param This Pointer to the EFI_BLUETOOTH_CONFIG_PROTOCOL instance.
+ @param Context Context passed from registration.
+ @param CallbackType Callback type in EFI_BLUETOOTH_CONNECT_COMPLETE_CALLBACK_TYPE.
+ @param BDAddr A pointer to Bluetooth device address.
+ @param InputBuffer A pointer to the buffer of data that is input from callback caller.
+ @param InputBufferSize Indicates the size, in bytes, of the data buffer specified by InputBuffer.
+
+ @retval EFI_SUCCESS The callback function complete successfully.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_BLUETOOTH_CONFIG_REGISTER_CONNECT_COMPLETE_CALLBACK_FUNCTION)(
+ IN EFI_BLUETOOTH_CONFIG_PROTOCOL *This,
+ IN VOID *Context,
+ IN EFI_BLUETOOTH_CONNECT_COMPLETE_CALLBACK_TYPE CallbackType,
+ IN BLUETOOTH_ADDRESS *BDAddr,
+ IN VOID *InputBuffer,
+ IN UINTN InputBufferSize
+ );
+
+/**
+ Register link connect complete callback function.
+
+ @param This Pointer to the EFI_BLUETOOTH_CONFIG_PROTOCOL instance.
+ @param Callback The callback function. NULL means unregister.
+ @param Context Data passed into Callback function. This is optional parameter and may be NULL.
+
+ @retval EFI_SUCCESS The link connect complete callback function is registered successfully.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_BLUETOOTH_CONFIG_REGISTER_CONNECT_COMPLETE_CALLBACK)(
+ IN EFI_BLUETOOTH_CONFIG_PROTOCOL *This,
+ IN EFI_BLUETOOTH_CONFIG_REGISTER_CONNECT_COMPLETE_CALLBACK_FUNCTION Callback,
+ IN VOID *Context
+ );
+
+///
+/// This protocol abstracts user interface configuration for Bluetooth device.
+///
+struct _EFI_BLUETOOTH_CONFIG_PROTOCOL {
+ EFI_BLUETOOTH_CONFIG_INIT Init;
+ EFI_BLUETOOTH_CONFIG_SCAN Scan;
+ EFI_BLUETOOTH_CONFIG_CONNECT Connect;
+ EFI_BLUETOOTH_CONFIG_DISCONNECT Disconnect;
+ EFI_BLUETOOTH_CONFIG_GET_DATA GetData;
+ EFI_BLUETOOTH_CONFIG_SET_DATA SetData;
+ EFI_BLUETOOTH_CONFIG_GET_REMOTE_DATA GetRemoteData;
+ EFI_BLUETOOTH_CONFIG_REGISTER_PIN_CALLBACK RegisterPinCallback;
+ EFI_BLUETOOTH_CONFIG_REGISTER_GET_LINK_KEY_CALLBACK RegisterGetLinkKeyCallback;
+ EFI_BLUETOOTH_CONFIG_REGISTER_SET_LINK_KEY_CALLBACK RegisterSetLinkKeyCallback;
+ EFI_BLUETOOTH_CONFIG_REGISTER_CONNECT_COMPLETE_CALLBACK RegisterLinkConnectCompleteCallback;
+};
+
+extern EFI_GUID gEfiBluetoothConfigProtocolGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/BluetoothHc.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/BluetoothHc.h
new file mode 100644
index 0000000000..4a2eaeffd4
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/BluetoothHc.h
@@ -0,0 +1,417 @@
+/** @file
+ EFI Bluetooth Host Controller Protocol as defined in UEFI 2.5.
+ This protocol abstracts the Bluetooth host controller layer message transmit and receive.
+
+ Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Revision Reference:
+ This Protocol is introduced in UEFI Specification 2.5
+
+**/
+
+#ifndef __EFI_BLUETOOTH_HC_PROTOCOL_H__
+#define __EFI_BLUETOOTH_HC_PROTOCOL_H__
+
+#define EFI_BLUETOOTH_HC_PROTOCOL_GUID \
+ { \
+ 0xb3930571, 0xbeba, 0x4fc5, { 0x92, 0x3, 0x94, 0x27, 0x24, 0x2e, 0x6a, 0x43 } \
+ }
+
+typedef struct _EFI_BLUETOOTH_HC_PROTOCOL EFI_BLUETOOTH_HC_PROTOCOL;
+
+/**
+ Send HCI command packet.
+
+ The SendCommand() function sends HCI command packet. Buffer holds the whole HCI
+ command packet, including OpCode, OCF, OGF, parameter length, and parameters. When
+ this function is returned, it just means the HCI command packet is sent, it does not mean
+ the command is success or complete. Caller might need to wait a command status event
+ to know the command status, or wait a command complete event to know if the
+ command is completed.
+
+ @param[in] This Pointer to the EFI_BLUETOOTH_HC_PROTOCOL instance.
+ @param[in,out] BufferSize On input, indicates the size, in bytes, of the data buffer
+ specified by Buffer. On output, indicates the amount of
+ data actually transferred.
+ @param[in] Buffer A pointer to the buffer of data that will be transmitted to
+ Bluetooth host controller.
+ @param[in] Timeout Indicating the transfer should be completed within this
+ time frame. The units are in milliseconds. If Timeout is 0,
+ then the caller must wait for the function to be completed
+ until EFI_SUCCESS or EFI_DEVICE_ERROR is returned.
+
+ @retval EFI_SUCCESS The HCI command packet is sent successfully.
+ @retval EFI_INVALID_PARAMETER One or more of the following conditions is TRUE:
+ BufferSize is NULL.
+ *BufferSize is 0.
+ Buffer is NULL.
+ @retval EFI_TIMEOUT Sending HCI command packet fail due to timeout.
+ @retval EFI_DEVICE_ERROR Sending HCI command packet fail due to host controller or device
+ error.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_BLUETOOTH_HC_SEND_COMMAND)(
+ IN EFI_BLUETOOTH_HC_PROTOCOL *This,
+ IN OUT UINTN *BufferSize,
+ IN VOID *Buffer,
+ IN UINTN Timeout
+ );
+
+/**
+ Receive HCI event packet.
+
+ The ReceiveEvent() function receives HCI event packet. Buffer holds the whole HCI event
+ packet, including EventCode, parameter length, and parameters.
+
+ @param[in] This Pointer to the EFI_BLUETOOTH_HC_PROTOCOL instance.
+ @param[in,out] BufferSize On input, indicates the size, in bytes, of the data buffer
+ specified by Buffer. On output, indicates the amount of
+ data actually transferred.
+ @param[out] Buffer A pointer to the buffer of data that will be received from
+ Bluetooth host controller.
+ @param[in] Timeout Indicating the transfer should be completed within this
+ time frame. The units are in milliseconds. If Timeout is 0,
+ then the caller must wait for the function to be completed
+ until EFI_SUCCESS or EFI_DEVICE_ERROR is returned.
+
+ @retval EFI_SUCCESS The HCI event packet is received successfully.
+ @retval EFI_INVALID_PARAMETER One or more of the following conditions is TRUE:
+ BufferSize is NULL.
+ *BufferSize is 0.
+ Buffer is NULL.
+ @retval EFI_TIMEOUT Receiving HCI event packet fail due to timeout.
+ @retval EFI_DEVICE_ERROR Receiving HCI event packet fail due to host controller or device
+ error.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_BLUETOOTH_HC_RECEIVE_EVENT)(
+ IN EFI_BLUETOOTH_HC_PROTOCOL *This,
+ IN OUT UINTN *BufferSize,
+ OUT VOID *Buffer,
+ IN UINTN Timeout
+ );
+
+/**
+ The async callback of AsyncReceiveEvent().
+
+ @param[in] Data Data received via asynchronous transfer.
+ @param[in] DataLength The length of Data in bytes, received via asynchronous
+ transfer.
+ @param[in] Context Context passed from asynchronous transfer request.
+
+ @retval EFI_SUCCESS The callback does execute successfully.
+ @retval Others The callback doesn't execute successfully.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_BLUETOOTH_HC_ASYNC_FUNC_CALLBACK)(
+ IN VOID *Data,
+ IN UINTN DataLength,
+ IN VOID *Context
+ );
+
+/**
+ Receive HCI event packet in non-blocking way.
+
+ The AsyncReceiveEvent() function receives HCI event packet in non-blocking way. Data
+ in Callback function holds the whole HCI event packet, including EventCode, parameter
+ length, and parameters.
+
+ @param[in] This Pointer to the EFI_BLUETOOTH_HC_PROTOCOL instance.
+ @param[in] IsNewTransfer If TRUE, a new transfer will be submitted. If FALSE, the
+ request is deleted.
+ @param[in] PollingInterval Indicates the periodic rate, in milliseconds, that the
+ transfer is to be executed.
+ @param[in] DataLength Specifies the length, in bytes, of the data to be received.
+ @param[in] Callback The callback function. This function is called if the
+ asynchronous transfer is completed.
+ @param[in] Context Data passed into Callback function. This is optional
+ parameter and may be NULL.
+
+ @retval EFI_SUCCESS The HCI asynchronous receive request is submitted successfully.
+ @retval EFI_INVALID_PARAMETER One or more of the following conditions is TRUE:
+ DataLength is 0.
+ If IsNewTransfer is TRUE, and an asynchronous receive
+ request already exists.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_BLUETOOTH_HC_ASYNC_RECEIVE_EVENT)(
+ IN EFI_BLUETOOTH_HC_PROTOCOL *This,
+ IN BOOLEAN IsNewTransfer,
+ IN UINTN PollingInterval,
+ IN UINTN DataLength,
+ IN EFI_BLUETOOTH_HC_ASYNC_FUNC_CALLBACK Callback,
+ IN VOID *Context
+ );
+
+/**
+ Send HCI ACL data packet.
+
+ The SendACLData() function sends HCI ACL data packet. Buffer holds the whole HCI ACL
+ data packet, including Handle, PB flag, BC flag, data length, and data.
+
+ The SendACLData() function and ReceiveACLData() function just send and receive data
+ payload from application layer. In order to protect the payload data, the Bluetooth bus is
+ required to call HCI_Set_Connection_Encryption command to enable hardware based
+ encryption after authentication completed, according to pairing mode and host
+ capability.
+
+ @param[in] This Pointer to the EFI_BLUETOOTH_HC_PROTOCOL instance.
+ @param[in, out] BufferSize On input, indicates the size, in bytes, of the data buffer
+ specified by Buffer. On output, indicates the amount of
+ data actually transferred.
+ @param[in] Buffer A pointer to the buffer of data that will be transmitted to
+ Bluetooth host controller.
+ @param[in] Timeout Indicating the transfer should be completed within this
+ time frame. The units are in milliseconds. If Timeout is 0,
+ then the caller must wait for the function to be completed
+ until EFI_SUCCESS or EFI_DEVICE_ERROR is returned.
+
+ @retval EFI_SUCCESS The HCI ACL data packet is sent successfully.
+ @retval EFI_INVALID_PARAMETER One or more of the following conditions is TRUE:
+ BufferSize is NULL.
+ *BufferSize is 0.
+ Buffer is NULL.
+ @retval EFI_TIMEOUT Sending HCI ACL data packet fail due to timeout.
+ @retval EFI_DEVICE_ERROR Sending HCI ACL data packet fail due to host controller or device
+ error.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_BLUETOOTH_HC_SEND_ACL_DATA)(
+ IN EFI_BLUETOOTH_HC_PROTOCOL *This,
+ IN OUT UINTN *BufferSize,
+ IN VOID *Buffer,
+ IN UINTN Timeout
+ );
+
+/**
+ Receive HCI ACL data packet.
+
+ The ReceiveACLData() function receives HCI ACL data packet. Buffer holds the whole HCI
+ ACL data packet, including Handle, PB flag, BC flag, data length, and data.
+
+ @param[in] This Pointer to the EFI_BLUETOOTH_HC_PROTOCOL instance.
+ @param[in, out] BufferSize On input, indicates the size, in bytes, of the data buffer
+ specified by Buffer. On output, indicates the amount of
+ data actually transferred.
+ @param[out] Buffer A pointer to the buffer of data that will be received from
+ Bluetooth host controller.
+ @param[in] Timeout Indicating the transfer should be completed within this
+ time frame. The units are in milliseconds. If Timeout is 0,
+ then the caller must wait for the function to be completed
+ until EFI_SUCCESS or EFI_DEVICE_ERROR is returned.
+
+ @retval EFI_SUCCESS The HCI ACL data packet is received successfully.
+ @retval EFI_INVALID_PARAMETER One or more of the following conditions is TRUE:
+ BufferSize is NULL.
+ *BufferSize is 0.
+ Buffer is NULL.
+ @retval EFI_TIMEOUT Receiving HCI ACL data packet fail due to timeout.
+ @retval EFI_DEVICE_ERROR Receiving HCI ACL data packet fail due to host controller or device
+ error.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_BLUETOOTH_HC_RECEIVE_ACL_DATA)(
+ IN EFI_BLUETOOTH_HC_PROTOCOL *This,
+ IN OUT UINTN *BufferSize,
+ OUT VOID *Buffer,
+ IN UINTN Timeout
+ );
+
+/**
+ Receive HCI ACL data packet in non-blocking way.
+
+ The AsyncReceiveACLData() function receives HCI ACL data packet in non-blocking way.
+ Data in Callback holds the whole HCI ACL data packet, including Handle, PB flag, BC flag,
+ data length, and data.
+
+ @param[in] This Pointer to the EFI_BLUETOOTH_HC_PROTOCOL instance.
+ @param[in] IsNewTransfer If TRUE, a new transfer will be submitted. If FALSE, the
+ request is deleted.
+ @param[in] PollingInterval Indicates the periodic rate, in milliseconds, that the
+ transfer is to be executed.
+ @param[in] DataLength Specifies the length, in bytes, of the data to be received.
+ @param[in] Callback The callback function. This function is called if the
+ asynchronous transfer is completed.
+ @param[in] Context Data passed into Callback function. This is optional
+ parameter and may be NULL.
+
+ @retval EFI_SUCCESS The HCI asynchronous receive request is submitted successfully.
+ @retval EFI_INVALID_PARAMETER One or more of the following conditions is TRUE:
+ DataLength is 0.
+ If IsNewTransfer is TRUE, and an asynchronous receive
+ request already exists.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_BLUETOOTH_HC_ASYNC_RECEIVE_ACL_DATA)(
+ IN EFI_BLUETOOTH_HC_PROTOCOL *This,
+ IN BOOLEAN IsNewTransfer,
+ IN UINTN PollingInterval,
+ IN UINTN DataLength,
+ IN EFI_BLUETOOTH_HC_ASYNC_FUNC_CALLBACK Callback,
+ IN VOID *Context
+ );
+
+/**
+ Send HCI SCO data packet.
+
+ The SendSCOData() function sends HCI SCO data packet. Buffer holds the whole HCI SCO
+ data packet, including ConnectionHandle, PacketStatus flag, data length, and data.
+
+ @param[in] This Pointer to the EFI_BLUETOOTH_HC_PROTOCOL instance.
+ @param[in,out] BufferSize On input, indicates the size, in bytes, of the data buffer
+ specified by Buffer. On output, indicates the amount of
+ data actually transferred.
+ @param[in] Buffer A pointer to the buffer of data that will be transmitted to
+ Bluetooth host controller.
+ @param[in] Timeout Indicating the transfer should be completed within this
+ time frame. The units are in milliseconds. If Timeout is 0,
+ then the caller must wait for the function to be completed
+ until EFI_SUCCESS or EFI_DEVICE_ERROR is returned.
+
+ @retval EFI_SUCCESS The HCI SCO data packet is sent successfully.
+ @retval EFI_UNSUPPORTED The implementation does not support HCI SCO transfer.
+ @retval EFI_INVALID_PARAMETER One or more of the following conditions is TRUE:
+ BufferSize is NULL.
+ *BufferSize is 0.
+ Buffer is NULL.
+ @retval EFI_TIMEOUT Sending HCI SCO data packet fail due to timeout.
+ @retval EFI_DEVICE_ERROR Sending HCI SCO data packet fail due to host controller or device
+ error.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_BLUETOOTH_HC_SEND_SCO_DATA)(
+ IN EFI_BLUETOOTH_HC_PROTOCOL *This,
+ IN OUT UINTN *BufferSize,
+ IN VOID *Buffer,
+ IN UINTN Timeout
+ );
+
+/**
+ Receive HCI SCO data packet.
+
+ The ReceiveSCOData() function receives HCI SCO data packet. Buffer holds the whole HCI
+ SCO data packet, including ConnectionHandle, PacketStatus flag, data length, and data.
+
+ @param[in] This Pointer to the EFI_BLUETOOTH_HC_PROTOCOL instance.
+ @param[in,out] BufferSize On input, indicates the size, in bytes, of the data buffer
+ specified by Buffer. On output, indicates the amount of
+ data actually transferred.
+ @param[out] Buffer A pointer to the buffer of data that will be received from
+ Bluetooth host controller.
+ @param[in] Timeout Indicating the transfer should be completed within this
+ time frame. The units are in milliseconds. If Timeout is 0,
+ then the caller must wait for the function to be completed
+ until EFI_SUCCESS or EFI_DEVICE_ERROR is returned.
+
+ @retval EFI_SUCCESS The HCI SCO data packet is received successfully.
+ @retval EFI_INVALID_PARAMETER One or more of the following conditions is TRUE:
+ BufferSize is NULL.
+ *BufferSize is 0.
+ Buffer is NULL.
+ @retval EFI_TIMEOUT Receiving HCI SCO data packet fail due to timeout.
+ @retval EFI_DEVICE_ERROR Receiving HCI SCO data packet fail due to host controller or device
+ error.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_BLUETOOTH_HC_RECEIVE_SCO_DATA)(
+ IN EFI_BLUETOOTH_HC_PROTOCOL *This,
+ IN OUT UINTN *BufferSize,
+ OUT VOID *Buffer,
+ IN UINTN Timeout
+ );
+
+/**
+ Receive HCI SCO data packet in non-blocking way.
+
+ The AsyncReceiveSCOData() function receives HCI SCO data packet in non-blocking way.
+ Data in Callback holds the whole HCI SCO data packet, including ConnectionHandle,
+ PacketStatus flag, data length, and data.
+
+ @param[in] This Pointer to the EFI_BLUETOOTH_HC_PROTOCOL instance.
+ @param[in] IsNewTransfer If TRUE, a new transfer will be submitted. If FALSE, the
+ request is deleted.
+ @param[in] PollingInterval Indicates the periodic rate, in milliseconds, that the
+ transfer is to be executed.
+ @param[in] DataLength Specifies the length, in bytes, of the data to be received.
+ @param[in] Callback The callback function. This function is called if the
+ asynchronous transfer is completed.
+ @param[in] Context Data passed into Callback function. This is optional
+ parameter and may be NULL.
+
+ @retval EFI_SUCCESS The HCI asynchronous receive request is submitted successfully.
+ @retval EFI_INVALID_PARAMETER One or more of the following conditions is TRUE:
+ DataLength is 0.
+ If IsNewTransfer is TRUE, and an asynchronous receive
+ request already exists.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_BLUETOOTH_HC_ASYNC_RECEIVE_SCO_DATA)(
+ IN EFI_BLUETOOTH_HC_PROTOCOL *This,
+ IN BOOLEAN IsNewTransfer,
+ IN UINTN PollingInterval,
+ IN UINTN DataLength,
+ IN EFI_BLUETOOTH_HC_ASYNC_FUNC_CALLBACK Callback,
+ IN VOID *Context
+ );
+
+//
+// The EFI_BLUETOOTH_HC_PROTOCOL is used to transmit or receive HCI layer data packets.
+//
+struct _EFI_BLUETOOTH_HC_PROTOCOL {
+ //
+ // Send HCI command packet.
+ //
+ EFI_BLUETOOTH_HC_SEND_COMMAND SendCommand;
+ //
+ // Receive HCI event packets.
+ //
+ EFI_BLUETOOTH_HC_RECEIVE_EVENT ReceiveEvent;
+ //
+ // Non-blocking receive HCI event packets.
+ //
+ EFI_BLUETOOTH_HC_ASYNC_RECEIVE_EVENT AsyncReceiveEvent;
+ //
+ // Send HCI ACL (asynchronous connection-oriented) data packets.
+ //
+ EFI_BLUETOOTH_HC_SEND_ACL_DATA SendACLData;
+ //
+ // Receive HCI ACL data packets.
+ //
+ EFI_BLUETOOTH_HC_RECEIVE_ACL_DATA ReceiveACLData;
+ //
+ // Non-blocking receive HCI ACL data packets.
+ //
+ EFI_BLUETOOTH_HC_ASYNC_RECEIVE_ACL_DATA AsyncReceiveACLData;
+ //
+ // Send HCI synchronous (SCO and eSCO) data packets.
+ //
+ EFI_BLUETOOTH_HC_SEND_SCO_DATA SendSCOData;
+ //
+ // Receive HCI synchronous data packets.
+ //
+ EFI_BLUETOOTH_HC_RECEIVE_SCO_DATA ReceiveSCOData;
+ //
+ // Non-blocking receive HCI synchronous data packets.
+ //
+ EFI_BLUETOOTH_HC_ASYNC_RECEIVE_SCO_DATA AsyncReceiveSCOData;
+};
+
+extern EFI_GUID gEfiBluetoothHcProtocolGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/BluetoothIo.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/BluetoothIo.h
new file mode 100644
index 0000000000..f2e56fb9ff
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/BluetoothIo.h
@@ -0,0 +1,411 @@
+/** @file
+ EFI Bluetooth IO Service Binding Protocol as defined in UEFI 2.5.
+ EFI Bluetooth IO Protocol as defined in UEFI 2.5.
+ The EFI Bluetooth IO Service Binding Protocol is used to locate EFI Bluetooth IO Protocol drivers to
+ create and destroy child of the driver to communicate with other Bluetooth device by using Bluetooth IO protocol.
+
+ Copyright (c) 2015 - 2017, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Revision Reference:
+ This Protocol is introduced in UEFI Specification 2.5
+
+**/
+
+#ifndef __EFI_BLUETOOTH_IO_PROTOCOL_H__
+#define __EFI_BLUETOOTH_IO_PROTOCOL_H__
+
+#include
+
+#define EFI_BLUETOOTH_IO_SERVICE_BINDING_PROTOCOL_GUID \
+ { \
+ 0x388278d3, 0x7b85, 0x42f0, { 0xab, 0xa9, 0xfb, 0x4b, 0xfd, 0x69, 0xf5, 0xab } \
+ }
+
+#define EFI_BLUETOOTH_IO_PROTOCOL_GUID \
+ { \
+ 0x467313de, 0x4e30, 0x43f1, { 0x94, 0x3e, 0x32, 0x3f, 0x89, 0x84, 0x5d, 0xb5 } \
+ }
+
+typedef struct _EFI_BLUETOOTH_IO_PROTOCOL EFI_BLUETOOTH_IO_PROTOCOL;
+
+///
+/// EFI_BLUETOOTH_DEVICE_INFO
+///
+typedef struct {
+ ///
+ /// The version of the structure
+ ///
+ UINT32 Version;
+ ///
+ /// 48bit Bluetooth device address.
+ ///
+ BLUETOOTH_ADDRESS BD_ADDR;
+ ///
+ /// Bluetooth PageScanRepetitionMode. See Bluetooth specification for detail.
+ ///
+ UINT8 PageScanRepetitionMode;
+ ///
+ /// Bluetooth ClassOfDevice. See Bluetooth specification for detail.
+ ///
+ BLUETOOTH_CLASS_OF_DEVICE ClassOfDevice;
+ ///
+ /// Bluetooth CloseOffset. See Bluetooth specification for detail.
+ ///
+ UINT16 ClockOffset;
+ ///
+ /// Bluetooth RSSI. See Bluetooth specification for detail.
+ ///
+ UINT8 RSSI;
+ ///
+ /// Bluetooth ExtendedInquiryResponse. See Bluetooth specification for detail.
+ ///
+ UINT8 ExtendedInquiryResponse[240];
+} EFI_BLUETOOTH_DEVICE_INFO;
+
+/**
+ Get Bluetooth device information.
+
+ @param[in] This Pointer to the EFI_BLUETOOTH_IO_PROTOCOL instance.
+ @param[out] DeviceInfoSize A pointer to the size, in bytes, of the DeviceInfo buffer.
+ @param[out] DeviceInfo A pointer to a callee allocated buffer that returns Bluetooth device information.
+
+ @retval EFI_SUCCESS The Bluetooth device information is returned successfully.
+ @retval EFI_DEVICE_ERROR A hardware error occurred trying to retrieve the Bluetooth device information.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_BLUETOOTH_IO_GET_DEVICE_INFO)(
+ IN EFI_BLUETOOTH_IO_PROTOCOL *This,
+ OUT UINTN *DeviceInfoSize,
+ OUT VOID **DeviceInfo
+ );
+
+/**
+ Get Bluetooth SDP information.
+
+ @param[in] This Pointer to the EFI_BLUETOOTH_IO_PROTOCOL instance.
+ @param[out] SdpInfoSize A pointer to the size, in bytes, of the SdpInfo buffer.
+ @param[out] SdpInfo A pointer to a callee allocated buffer that returns Bluetooth SDP information.
+
+ @retval EFI_SUCCESS The Bluetooth device information is returned successfully.
+ @retval EFI_DEVICE_ERROR A hardware error occurred trying to retrieve the Bluetooth SDP information.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_BLUETOOTH_IO_GET_SDP_INFO)(
+ IN EFI_BLUETOOTH_IO_PROTOCOL *This,
+ OUT UINTN *SdpInfoSize,
+ OUT VOID **SdpInfo
+ );
+
+/**
+ Send L2CAP message (including L2CAP header).
+
+ @param[in] This Pointer to the EFI_BLUETOOTH_IO_PROTOCOL instance.
+ @param[in, out] BufferSize On input, indicates the size, in bytes, of the data buffer specified by Buffer.
+ On output, indicates the amount of data actually transferred.
+ @param[in] Buffer A pointer to the buffer of data that will be transmitted to Bluetooth L2CAP layer.
+ @param[in] Timeout Indicating the transfer should be completed within this time frame. The units are in
+ milliseconds. If Timeout is 0, then the caller must wait for the function to be completed
+ until EFI_SUCCESS or EFI_DEVICE_ERROR is returned.
+
+ @retval EFI_SUCCESS The L2CAP message is sent successfully.
+ @retval EFI_INVALID_PARAMETER One or more of the following conditions is TRUE:
+ - BufferSize is NULL.
+ - *BufferSize is 0.
+ - Buffer is NULL.
+ @retval EFI_TIMEOUT Sending L2CAP message fail due to timeout.
+ @retval EFI_DEVICE_ERROR Sending L2CAP message fail due to host controller or device error.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_BLUETOOTH_IO_L2CAP_RAW_SEND)(
+ IN EFI_BLUETOOTH_IO_PROTOCOL *This,
+ IN OUT UINTN *BufferSize,
+ IN VOID *Buffer,
+ IN UINTN Timeout
+ );
+
+/**
+ Receive L2CAP message (including L2CAP header).
+
+ @param[in] This Pointer to the EFI_BLUETOOTH_IO_PROTOCOL instance.
+ @param[in] BufferSize On input, indicates the size, in bytes, of the data buffer specified by Buffer.
+ On output, indicates the amount of data actually transferred.
+ @param[out] Buffer A pointer to the buffer of data that will be received from Bluetooth L2CAP layer.
+ @param[in] Timeout Indicating the transfer should be completed within this time frame. The units are in
+ milliseconds. If Timeout is 0, then the caller must wait for the function to be completed
+ until EFI_SUCCESS or EFI_DEVICE_ERROR is returned.
+
+ @retval EFI_SUCCESS The L2CAP message is received successfully.
+ @retval EFI_INVALID_PARAMETER One or more of the following conditions is TRUE:
+ - BufferSize is NULL.
+ - *BufferSize is 0.
+ - Buffer is NULL.
+ @retval EFI_TIMEOUT Receiving L2CAP message fail due to timeout.
+ @retval EFI_DEVICE_ERROR Receiving L2CAP message fail due to host controller or device error.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_BLUETOOTH_IO_L2CAP_RAW_RECEIVE)(
+ IN EFI_BLUETOOTH_IO_PROTOCOL *This,
+ IN OUT UINTN *BufferSize,
+ OUT VOID *Buffer,
+ IN UINTN Timeout
+ );
+
+/**
+ Callback function, it is called when asynchronous transfer is completed.
+
+ @param[in] ChannelID Bluetooth L2CAP message channel ID.
+ @param[in] Data Data received via asynchronous transfer.
+ @param[in] DataLength The length of Data in bytes, received via asynchronous transfer.
+ @param[in] Context Context passed from asynchronous transfer request.
+
+ @retval EFI_SUCCESS The callback function complete successfully.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_BLUETOOTH_IO_ASYNC_FUNC_CALLBACK)(
+ IN UINT16 ChannelID,
+ IN VOID *Data,
+ IN UINTN DataLength,
+ IN VOID *Context
+ );
+
+/**
+ Receive L2CAP message (including L2CAP header) in non-blocking way.
+
+ @param[in] This Pointer to the EFI_BLUETOOTH_IO_PROTOCOL instance.
+ @param[in] IsNewTransfer If TRUE, a new transfer will be submitted. If FALSE, the request is deleted.
+ @param[in] PollingInterval Indicates the periodic rate, in milliseconds, that the transfer is to be executed.
+ @param[in] DataLength Specifies the length, in bytes, of the data to be received.
+ @param[in] Callback The callback function. This function is called if the asynchronous transfer is
+ completed.
+ @param[in] Context Data passed into Callback function. This is optional parameter and may be NULL.
+
+ @retval EFI_SUCCESS The L2CAP asynchronous receive request is submitted successfully.
+ @retval EFI_INVALID_PARAMETER One or more of the following conditions is TRUE:
+ - DataLength is 0.
+ - If IsNewTransfer is TRUE, and an asynchronous receive request already exists.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_BLUETOOTH_IO_L2CAP_RAW_ASYNC_RECEIVE)(
+ IN EFI_BLUETOOTH_IO_PROTOCOL *This,
+ IN BOOLEAN IsNewTransfer,
+ IN UINTN PollingInterval,
+ IN UINTN DataLength,
+ IN EFI_BLUETOOTH_IO_ASYNC_FUNC_CALLBACK Callback,
+ IN VOID *Context
+ );
+
+/**
+ Send L2CAP message (excluding L2CAP header) to a specific channel.
+
+ @param[in] This Pointer to the EFI_BLUETOOTH_IO_PROTOCOL instance.
+ @param[in] Handle A handle created by EFI_BLUETOOTH_IO_PROTOCOL.L2CapConnect indicates which channel to send.
+ @param[in, out] BufferSize On input, indicates the size, in bytes, of the data buffer specified by Buffer.
+ On output, indicates the amount of data actually transferred.
+ @param[in] Buffer A pointer to the buffer of data that will be transmitted to Bluetooth L2CAP layer.
+ @param[in] Timeout Indicating the transfer should be completed within this time frame. The units are in
+ milliseconds. If Timeout is 0, then the caller must wait for the function to be completed
+ until EFI_SUCCESS or EFI_DEVICE_ERROR is returned.
+
+ @retval EFI_SUCCESS The L2CAP message is sent successfully.
+ @retval EFI_NOT_FOUND Handle is invalid or not found.
+ @retval EFI_INVALID_PARAMETER One or more of the following conditions is TRUE:
+ - BufferSize is NULL.
+ - *BufferSize is 0.
+ - Buffer is NULL.
+ @retval EFI_TIMEOUT Sending L2CAP message fail due to timeout.
+ @retval EFI_DEVICE_ERROR Sending L2CAP message fail due to host controller or device error.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_BLUETOOTH_IO_L2CAP_SEND)(
+ IN EFI_BLUETOOTH_IO_PROTOCOL *This,
+ IN EFI_HANDLE Handle,
+ IN OUT UINTN *BufferSize,
+ IN VOID *Buffer,
+ IN UINTN Timeout
+ );
+
+/**
+ Receive L2CAP message (excluding L2CAP header) from a specific channel.
+
+ @param[in] This Pointer to the EFI_BLUETOOTH_IO_PROTOCOL instance.
+ @param[in] Handle A handle created by EFI_BLUETOOTH_IO_PROTOCOL.L2CapConnect indicates which channel to receive.
+ @param[out] BufferSize Indicates the size, in bytes, of the data buffer specified by Buffer.
+ @param[out] Buffer A pointer to the buffer of data that will be received from Bluetooth L2CAP layer.
+ @param[in] Timeout Indicating the transfer should be completed within this time frame. The units are in
+ milliseconds. If Timeout is 0, then the caller must wait for the function to be completed
+ until EFI_SUCCESS or EFI_DEVICE_ERROR is returned.
+
+ @retval EFI_SUCCESS The L2CAP message is received successfully.
+ @retval EFI_NOT_FOUND Handle is invalid or not found.
+ @retval EFI_INVALID_PARAMETER One or more of the following conditions is TRUE:
+ - BufferSize is NULL.
+ - *BufferSize is 0.
+ - Buffer is NULL.
+ @retval EFI_TIMEOUT Receiving L2CAP message fail due to timeout.
+ @retval EFI_DEVICE_ERROR Receiving L2CAP message fail due to host controller or device error.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_BLUETOOTH_IO_L2CAP_RECEIVE)(
+ IN EFI_BLUETOOTH_IO_PROTOCOL *This,
+ IN EFI_HANDLE Handle,
+ OUT UINTN *BufferSize,
+ OUT VOID **Buffer,
+ IN UINTN Timeout
+ );
+
+/**
+ Callback function, it is called when asynchronous transfer is completed.
+
+ @param[in] Data Data received via asynchronous transfer.
+ @param[in] DataLength The length of Data in bytes, received via asynchronous transfer.
+ @param[in] Context Context passed from asynchronous transfer request.
+
+ @retval EFI_SUCCESS The callback function complete successfully.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_BLUETOOTH_IO_CHANNEL_SERVICE_CALLBACK)(
+ IN VOID *Data,
+ IN UINTN DataLength,
+ IN VOID *Context
+ );
+
+/**
+ Receive L2CAP message (excluding L2CAP header) in non-blocking way from a specific channel.
+
+ @param[in] This Pointer to the EFI_BLUETOOTH_IO_PROTOCOL instance.
+ @param[in] Handel A handle created by EFI_BLUETOOTH_IO_PROTOCOL.L2CapConnect indicates which channel
+ to receive.
+ @param[in] Callback The callback function. This function is called if the asynchronous transfer is
+ completed.
+ @param[in] Context Data passed into Callback function. This is optional parameter and may be NULL.
+
+ @retval EFI_SUCCESS The L2CAP asynchronous receive request is submitted successfully.
+ @retval EFI_NOT_FOUND Handle is invalid or not found.
+ @retval EFI_INVALID_PARAMETER One or more of the following conditions is TRUE:
+ - DataLength is 0.
+ - If an asynchronous receive request already exists on same Handle.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_BLUETOOTH_IO_L2CAP_ASYNC_RECEIVE)(
+ IN EFI_BLUETOOTH_IO_PROTOCOL *This,
+ IN EFI_HANDLE Handle,
+ IN EFI_BLUETOOTH_IO_CHANNEL_SERVICE_CALLBACK Callback,
+ IN VOID *Context
+ );
+
+/**
+ Do L2CAP connection.
+
+ @param[in] This Pointer to the EFI_BLUETOOTH_IO_PROTOCOL instance.
+ @param[out] Handel A handle to indicate this L2CAP connection.
+ @param[in] Psm Bluetooth PSM. See Bluetooth specification for detail.
+ @param[in] Mtu Bluetooth MTU. See Bluetooth specification for detail.
+ @param[in] Callback The callback function. This function is called whenever there is message received
+ in this channel.
+ @param[in] Context Data passed into Callback function. This is optional parameter and may be NULL.
+
+ @retval EFI_SUCCESS The Bluetooth L2CAP layer connection is created successfully.
+ @retval EFI_INVALID_PARAMETER One or more of the following conditions is TRUE:
+ - Handle is NULL.
+ @retval EFI_DEVICE_ERROR A hardware error occurred trying to do Bluetooth L2CAP connection.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_BLUETOOTH_IO_L2CAP_CONNECT)(
+ IN EFI_BLUETOOTH_IO_PROTOCOL *This,
+ OUT EFI_HANDLE *Handle,
+ IN UINT16 Psm,
+ IN UINT16 Mtu,
+ IN EFI_BLUETOOTH_IO_CHANNEL_SERVICE_CALLBACK Callback,
+ IN VOID *Context
+ );
+
+/**
+ Do L2CAP disconnection.
+
+ @param[in] This Pointer to the EFI_BLUETOOTH_IO_PROTOCOL instance.
+ @param[in] Handel A handle to indicate this L2CAP connection.
+
+ @retval EFI_SUCCESS The Bluetooth L2CAP layer is disconnected successfully.
+ @retval EFI_NOT_FOUND Handle is invalid or not found.
+ @retval EFI_DEVICE_ERROR A hardware error occurred trying to do Bluetooth L2CAP disconnection.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_BLUETOOTH_IO_L2CAP_DISCONNECT)(
+ IN EFI_BLUETOOTH_IO_PROTOCOL *This,
+ IN EFI_HANDLE Handle
+ );
+
+/**
+ Register L2CAP callback function for special channel.
+
+ @param[in] This Pointer to the EFI_BLUETOOTH_IO_PROTOCOL instance.
+ @param[out] Handel A handle to indicate this L2CAP connection.
+ @param[in] Psm Bluetooth PSM. See Bluetooth specification for detail.
+ @param[in] Mtu Bluetooth MTU. See Bluetooth specification for detail.
+ @param[in] Callback The callback function. This function is called whenever there is message received
+ in this channel. NULL means unregister.
+ @param[in] Context Data passed into Callback function. This is optional parameter and may be NULL.
+
+ @retval EFI_SUCCESS The Bluetooth L2CAP callback function is registered successfully.
+ @retval EFI_ALREADY_STARTED The callback function already exists when register.
+ @retval EFI_NOT_FOUND The callback function does not exist when unregister.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_BLUETOOTH_IO_L2CAP_REGISTER_SERVICE)(
+ IN EFI_BLUETOOTH_IO_PROTOCOL *This,
+ OUT EFI_HANDLE *Handle,
+ IN UINT16 Psm,
+ IN UINT16 Mtu,
+ IN EFI_BLUETOOTH_IO_CHANNEL_SERVICE_CALLBACK Callback,
+ IN VOID *Context
+ );
+
+///
+/// This protocol provides service for Bluetooth L2CAP (Logical Link Control and Adaptation Protocol)
+/// and SDP (Service Discovery Protocol).
+///
+struct _EFI_BLUETOOTH_IO_PROTOCOL {
+ EFI_BLUETOOTH_IO_GET_DEVICE_INFO GetDeviceInfo;
+ EFI_BLUETOOTH_IO_GET_SDP_INFO GetSdpInfo;
+ EFI_BLUETOOTH_IO_L2CAP_RAW_SEND L2CapRawSend;
+ EFI_BLUETOOTH_IO_L2CAP_RAW_RECEIVE L2CapRawReceive;
+ EFI_BLUETOOTH_IO_L2CAP_RAW_ASYNC_RECEIVE L2CapRawAsyncReceive;
+ EFI_BLUETOOTH_IO_L2CAP_SEND L2CapSend;
+ EFI_BLUETOOTH_IO_L2CAP_RECEIVE L2CapReceive;
+ EFI_BLUETOOTH_IO_L2CAP_ASYNC_RECEIVE L2CapAsyncReceive;
+ EFI_BLUETOOTH_IO_L2CAP_CONNECT L2CapConnect;
+ EFI_BLUETOOTH_IO_L2CAP_DISCONNECT L2CapDisconnect;
+ EFI_BLUETOOTH_IO_L2CAP_REGISTER_SERVICE L2CapRegisterService;
+};
+
+extern EFI_GUID gEfiBluetoothIoServiceBindingProtocolGuid;
+extern EFI_GUID gEfiBluetoothIoProtocolGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/BluetoothLeConfig.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/BluetoothLeConfig.h
new file mode 100644
index 0000000000..ae3f485c6b
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/BluetoothLeConfig.h
@@ -0,0 +1,629 @@
+/** @file
+ EFI Bluetooth LE Config Protocol as defined in UEFI 2.7.
+ This protocol abstracts user interface configuration for BluetoothLe device.
+
+ Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Revision Reference:
+ This Protocol is introduced in UEFI Specification 2.7
+
+**/
+
+#ifndef __EFI_BLUETOOTH_LE_CONFIG_H__
+#define __EFI_BLUETOOTH_LE_CONFIG_H__
+
+#include
+#include
+
+#define EFI_BLUETOOTH_LE_CONFIG_PROTOCOL_GUID \
+ { \
+ 0x8f76da58, 0x1f99, 0x4275, { 0xa4, 0xec, 0x47, 0x56, 0x51, 0x5b, 0x1c, 0xe8 } \
+ }
+
+typedef struct _EFI_BLUETOOTH_LE_CONFIG_PROTOCOL EFI_BLUETOOTH_LE_CONFIG_PROTOCOL;
+
+/**
+ Initialize BluetoothLE host controller and local device.
+
+ The Init() function initializes BluetoothLE host controller and local device.
+
+ @param[in] This Pointer to the EFI_BLUETOOTH_LE_CONFIG_PROTOCOL instance.
+
+ @retval EFI_SUCCESS The BluetoothLE host controller and local device is initialized successfully.
+ @retval EFI_DEVICE_ERROR A hardware error occurred trying to initialize the BluetoothLE host controller
+ and local device.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_BLUETOOTH_LE_CONFIG_INIT)(
+ IN EFI_BLUETOOTH_LE_CONFIG_PROTOCOL *This
+ );
+
+typedef struct {
+ ///
+ /// The version of the structure. A value of zero represents the EFI_BLUETOOTH_LE_CONFIG_SCAN_PARAMETER
+ /// structure as defined here. Future version of this specification may extend this data structure in a
+ /// backward compatible way and increase the value of Version.
+ ///
+ UINT32 Version;
+ ///
+ /// Passive scanning or active scanning. See Bluetooth specification.
+ ///
+ UINT8 ScanType;
+ ///
+ /// Recommended scan interval to be used while performing scan.
+ ///
+ UINT16 ScanInterval;
+ ///
+ /// Recommended scan window to be used while performing a scan.
+ ///
+ UINT16 ScanWindow;
+ ///
+ /// Recommended scanning filter policy to be used while performing a scan.
+ ///
+ UINT8 ScanningFilterPolicy;
+ ///
+ /// This is one byte flag to serve as a filter to remove unneeded scan
+ /// result. For example, set BIT0 means scan in LE Limited Discoverable
+ /// Mode. Set BIT1 means scan in LE General Discoverable Mode.
+ ///
+ UINT8 AdvertisementFlagFilter;
+} EFI_BLUETOOTH_LE_CONFIG_SCAN_PARAMETER;
+
+typedef struct {
+ BLUETOOTH_LE_ADDRESS BDAddr;
+ BLUETOOTH_LE_ADDRESS DirectAddress;
+ UINT8 RemoteDeviceState;
+ INT8 RSSI;
+ UINTN AdvertisementDataSize;
+ VOID *AdvertisementData;
+} EFI_BLUETOOTH_LE_SCAN_CALLBACK_INFORMATION;
+
+/**
+ Callback function, it is called if a BluetoothLE device is found during scan process.
+
+ @param[in] This Pointer to the EFI_BLUETOOTH_LE_CONFIG_PROTOCOL instance.
+ @param[in] Context Context passed from scan request.
+ @param[in] CallbackInfo Data related to scan result. NULL CallbackInfo means scan complete.
+
+ @retval EFI_SUCCESS The callback function complete successfully.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_BLUETOOTH_LE_CONFIG_SCAN_CALLBACK_FUNCTION)(
+ IN EFI_BLUETOOTH_LE_CONFIG_PROTOCOL *This,
+ IN VOID *Context,
+ IN EFI_BLUETOOTH_LE_SCAN_CALLBACK_INFORMATION *CallbackInfo
+ );
+
+/**
+ Scan BluetoothLE device.
+
+ The Scan() function scans BluetoothLE device. When this function is returned, it just means scan
+ request is submitted. It does not mean scan process is started or finished. Whenever there is a
+ BluetoothLE device is found, the Callback function will be called. Callback function might be
+ called before this function returns or after this function returns
+
+ @param[in] This Pointer to the EFI_BLUETOOTH_LE_CONFIG_PROTOCOL instance.
+ @param[in] ReScan If TRUE, a new scan request is submitted no matter there is scan result before.
+ If FALSE and there is scan result, the previous scan result is returned and no scan request
+ is submitted.
+ @param[in] Timeout Duration in milliseconds for which to scan.
+ @param[in] ScanParameter If it is not NULL, the ScanParameter is used to perform a scan by the BluetoothLE bus driver.
+ If it is NULL, the default parameter is used.
+ @param[in] Callback The callback function. This function is called if a BluetoothLE device is found during
+ scan process.
+ @param[in] Context Data passed into Callback function. This is optional parameter and may be NULL.
+
+ @retval EFI_SUCCESS The Bluetooth scan request is submitted.
+ @retval EFI_DEVICE_ERROR A hardware error occurred trying to scan the BluetoothLE device.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_BLUETOOTH_LE_CONFIG_SCAN)(
+ IN EFI_BLUETOOTH_LE_CONFIG_PROTOCOL *This,
+ IN BOOLEAN ReScan,
+ IN UINT32 Timeout,
+ IN EFI_BLUETOOTH_LE_CONFIG_SCAN_PARAMETER *ScanParameter OPTIONAL,
+ IN EFI_BLUETOOTH_LE_CONFIG_SCAN_CALLBACK_FUNCTION Callback,
+ IN VOID *Context
+ );
+
+typedef struct {
+ ///
+ /// The version of the structure. A value of zero represents the
+ /// EFI_BLUETOOTH_LE_CONFIG_CONNECT_PARAMETER
+ /// structure as defined here. Future version of this specification may
+ /// extend this data structure in a backward compatible way and
+ /// increase the value of Version.
+ ///
+ UINT32 Version;
+ ///
+ /// Recommended scan interval to be used while performing scan before connect.
+ ///
+ UINT16 ScanInterval;
+ ///
+ /// Recommended scan window to be used while performing a connection
+ ///
+ UINT16 ScanWindow;
+ ///
+ /// Minimum allowed connection interval. Shall be less than or equal to ConnIntervalMax.
+ ///
+ UINT16 ConnIntervalMin;
+ ///
+ /// Maximum allowed connection interval. Shall be greater than or equal to ConnIntervalMin.
+ ///
+ UINT16 ConnIntervalMax;
+ ///
+ /// Slave latency for the connection in number of connection events.
+ ///
+ UINT16 ConnLatency;
+ ///
+ /// Link supervision timeout for the connection.
+ ///
+ UINT16 SupervisionTimeout;
+} EFI_BLUETOOTH_LE_CONFIG_CONNECT_PARAMETER;
+
+/**
+ Connect a BluetoothLE device.
+
+ The Connect() function connects a Bluetooth device. When this function is returned successfully,
+ a new EFI_BLUETOOTH_IO_PROTOCOL is created.
+
+ @param[in] This Pointer to the EFI_BLUETOOTH_LE_CONFIG_PROTOCOL instance.
+ @param[in] AutoReconnect If TRUE, the BluetoothLE host controller needs to do an auto
+ reconnect. If FALSE, the BluetoothLE host controller does not do
+ an auto reconnect.
+ @param[in] DoBonding If TRUE, the BluetoothLE host controller needs to do a bonding.
+ If FALSE, the BluetoothLE host controller does not do a bonding.
+ @param[in] ConnectParameter If it is not NULL, the ConnectParameter is used to perform a
+ scan by the BluetoothLE bus driver. If it is NULL, the default
+ parameter is used.
+ @param[in] BD_ADDR The address of the BluetoothLE device to be connected.
+
+ @retval EFI_SUCCESS The BluetoothLE device is connected successfully.
+ @retval EFI_ALREADY_STARTED The BluetoothLE device is already connected.
+ @retval EFI_NOT_FOUND The BluetoothLE device is not found.
+ @retval EFI_DEVICE_ERROR A hardware error occurred trying to connect the BluetoothLE device.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_BLUETOOTH_LE_CONFIG_CONNECT)(
+ IN EFI_BLUETOOTH_LE_CONFIG_PROTOCOL *This,
+ IN BOOLEAN AutoReconnect,
+ IN BOOLEAN DoBonding,
+ IN EFI_BLUETOOTH_LE_CONFIG_CONNECT_PARAMETER *ConnectParameter OPTIONAL,
+ IN BLUETOOTH_LE_ADDRESS *BD_ADDR
+ );
+
+/**
+ Disconnect a BluetoothLE device.
+
+ The Disconnect() function disconnects a BluetoothLE device. When this function is returned
+ successfully, the EFI_BLUETOOTH_ATTRIBUTE_PROTOCOL associated with this device is
+ destroyed and all services associated are stopped.
+
+ @param[in] This Pointer to the EFI_BLUETOOTH_LE_CONFIG_PROTOCOL instance.
+ @param[in] BD_ADDR The address of BluetoothLE device to be connected.
+ @param[in] Reason Bluetooth disconnect reason. See Bluetooth specification for detail.
+
+ @retval EFI_SUCCESS The BluetoothLE device is disconnected successfully.
+ @retval EFI_NOT_STARTED The BluetoothLE device is not connected.
+ @retval EFI_NOT_FOUND The BluetoothLE device is not found.
+ @retval EFI_DEVICE_ERROR A hardware error occurred trying to disconnect the BluetoothLE device.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_BLUETOOTH_LE_CONFIG_DISCONNECT)(
+ IN EFI_BLUETOOTH_LE_CONFIG_PROTOCOL *This,
+ IN BLUETOOTH_LE_ADDRESS *BD_ADDR,
+ IN UINT8 Reason
+ );
+
+/**
+ Get BluetoothLE configuration data.
+
+ The GetData() function returns BluetoothLE configuration data. For remote BluetoothLE device
+ configuration data, please use GetRemoteData() function with valid BD_ADDR.
+
+ @param[in] This Pointer to the EFI_BLUETOOTH_LE_CONFIG_PROTOCOL instance.
+ @param[in] DataType Configuration data type.
+ @param[in, out] DataSize On input, indicates the size, in bytes, of the data buffer specified by Data.
+ On output, indicates the amount of data actually returned.
+ @param[in, out] Data A pointer to the buffer of data that will be returned.
+
+ @retval EFI_SUCCESS The BluetoothLE configuration data is returned successfully.
+ @retval EFI_INVALID_PARAMETER One or more of the following conditions is TRUE:
+ - DataSize is NULL.
+ - *DataSize is 0.
+ - Data is NULL.
+ @retval EFI_UNSUPPORTED The DataType is unsupported.
+ @retval EFI_NOT_FOUND The DataType is not found.
+ @retval EFI_BUFFER_TOO_SMALL The buffer is too small to hold the buffer.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_BLUETOOTH_LE_CONFIG_GET_DATA)(
+ IN EFI_BLUETOOTH_LE_CONFIG_PROTOCOL *This,
+ IN EFI_BLUETOOTH_CONFIG_DATA_TYPE DataType,
+ IN OUT UINTN *DataSize,
+ IN OUT VOID *Data OPTIONAL
+ );
+
+/**
+ Set BluetoothLE configuration data.
+
+ The SetData() function sets local BluetoothLE device configuration data. Not all DataType can be
+ set.
+
+ @param[in] This Pointer to the EFI_BLUETOOTH_LE_CONFIG_PROTOCOL instance.
+ @param[in] DataType Configuration data type.
+ @param[in] DataSize Indicates the size, in bytes, of the data buffer specified by Data.
+ @param[in] Data A pointer to the buffer of data that will be set.
+
+ @retval EFI_SUCCESS The BluetoothLE configuration data is set successfully.
+ @retval EFI_INVALID_PARAMETER One or more of the following conditions is TRUE:
+ - DataSize is 0.
+ - Data is NULL.
+ @retval EFI_UNSUPPORTED The DataType is unsupported.
+ @retval EFI_WRITE_PROTECTED Cannot set configuration data.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_BLUETOOTH_LE_CONFIG_SET_DATA)(
+ IN EFI_BLUETOOTH_LE_CONFIG_PROTOCOL *This,
+ IN EFI_BLUETOOTH_CONFIG_DATA_TYPE DataType,
+ IN UINTN DataSize,
+ IN VOID *Data
+ );
+
+/**
+ Get remove BluetoothLE device configuration data.
+
+ The GetRemoteData() function returns remote BluetoothLE device configuration data.
+
+ @param[in] This Pointer to the EFI_BLUETOOTH_LE_CONFIG_PROTOCOL instance.
+ @param[in] DataType Configuration data type.
+ @param[in] BDAddr Remote BluetoothLE device address.
+ @param[in, out] DataSize On input, indicates the size, in bytes, of the data buffer specified by Data.
+ On output, indicates the amount of data actually returned.
+ @param[in, out] Data A pointer to the buffer of data that will be returned.
+
+ @retval EFI_SUCCESS The remote BluetoothLE device configuration data is returned successfully.
+ @retval EFI_INVALID_PARAMETER One or more of the following conditions is TRUE:
+ - DataSize is NULL.
+ - *DataSize is 0.
+ - Data is NULL.
+ @retval EFI_UNSUPPORTED The DataType is unsupported.
+ @retval EFI_NOT_FOUND The DataType is not found.
+ @retval EFI_BUFFER_TOO_SMALL The buffer is too small to hold the buffer.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_BLUETOOTH_LE_CONFIG_GET_REMOTE_DATA)(
+ IN EFI_BLUETOOTH_LE_CONFIG_PROTOCOL *This,
+ IN EFI_BLUETOOTH_CONFIG_DATA_TYPE DataType,
+ IN BLUETOOTH_LE_ADDRESS *BDAddr,
+ IN OUT UINTN *DataSize,
+ IN OUT VOID *Data
+ );
+
+typedef enum {
+ ///
+ /// It indicates an authorization request. No data is associated with the callback
+ /// input. In the output data, the application should return the authorization value.
+ /// The data structure is BOOLEAN. TRUE means YES. FALSE means NO.
+ ///
+ EfiBluetoothSmpAuthorizationRequestEvent,
+ ///
+ /// It indicates that a passkey has been generated locally by the driver, and the same
+ /// passkey should be entered at the remote device. The callback input data is the
+ /// passkey of type UINT32, to be displayed by the application. No output data
+ /// should be returned.
+ ///
+ EfiBluetoothSmpPasskeyReadyEvent,
+ ///
+ /// It indicates that the driver is requesting for the passkey has been generated at
+ /// the remote device. No data is associated with the callback input. The output data
+ /// is the passkey of type UINT32, to be entered by the user.
+ ///
+ EfiBluetoothSmpPasskeyRequestEvent,
+ ///
+ /// It indicates that the driver is requesting for the passkey that has been pre-shared
+ /// out-of-band with the remote device. No data is associated with the callback
+ /// input. The output data is the stored OOB data of type UINT8[16].
+ ///
+ EfiBluetoothSmpOOBDataRequestEvent,
+ ///
+ /// In indicates that a number have been generated locally by the bus driver, and
+ /// also at the remote device, and the bus driver wants to know if the two numbers
+ /// match. The callback input data is the number of type UINT32. The output data
+ /// is confirmation value of type BOOLEAN. TRUE means comparison pass. FALSE
+ /// means comparison fail.
+ ///
+ EfiBluetoothSmpNumericComparisonEvent,
+} EFI_BLUETOOTH_LE_SMP_EVENT_DATA_TYPE;
+
+/**
+ The callback function for SMP.
+
+ @param[in] This Pointer to the EFI_BLUETOOTH_LE_CONFIG_PROTOCOL instance.
+ @param[in] Context Data passed into callback function. This is optional parameter
+ and may be NULL.
+ @param[in] BDAddr Remote BluetoothLE device address.
+ @param[in] EventDataType Event data type in EFI_BLUETOOTH_LE_SMP_EVENT_DATA_TYPE.
+ @param[in] DataSize Indicates the size, in bytes, of the data buffer specified by Data.
+ @param[in] Data A pointer to the buffer of data.
+
+ @retval EFI_SUCCESS The callback function complete successfully.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_BLUETOOTH_LE_SMP_CALLBACK)(
+ IN EFI_BLUETOOTH_LE_CONFIG_PROTOCOL *This,
+ IN VOID *Context,
+ IN BLUETOOTH_LE_ADDRESS *BDAddr,
+ IN EFI_BLUETOOTH_LE_SMP_EVENT_DATA_TYPE EventDataType,
+ IN UINTN DataSize,
+ IN VOID *Data
+ );
+
+/**
+ Register Security Manager Protocol callback function for user authentication/authorization.
+
+ The RegisterSmpAuthCallback() function register Security Manager Protocol callback
+ function for user authentication/authorization.
+
+ @param[in] This Pointer to the EFI_BLUETOOTH_LE_CONFIG_PROTOCOL instance.
+ @param[in] Callback Callback function for user authentication/authorization.
+ @param[in] Context Data passed into Callback function. This is optional parameter and may be NULL.
+
+ @retval EFI_SUCCESS The SMP callback function is registered successfully.
+ @retval EFI_ALREADY_STARTED A callback function is already registered on the same attribute
+ opcode and attribute handle, when the Callback is not NULL.
+ @retval EFI_NOT_STARTED A callback function is not registered on the same attribute opcode
+ and attribute handle, when the Callback is NULL.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_BLUETOOTH_LE_REGISTER_SMP_AUTH_CALLBACK)(
+ IN EFI_BLUETOOTH_LE_CONFIG_PROTOCOL *This,
+ IN EFI_BLUETOOTH_LE_SMP_CALLBACK Callback,
+ IN VOID *Context
+ );
+
+/**
+ Send user authentication/authorization to remote device.
+
+ The SendSmpAuthData() function sends user authentication/authorization to remote device. It
+ should be used to send these information after the caller gets the request data from the callback
+ function by RegisterSmpAuthCallback().
+
+ @param[in] This Pointer to the EFI_BLUETOOTH_LE_CONFIG_PROTOCOL instance.
+ @param[in] BDAddr Remote BluetoothLE device address.
+ @param[in] EventDataType Event data type in EFI_BLUETOOTH_LE_SMP_EVENT_DATA_TYPE.
+ @param[in] DataSize The size of Data in bytes, of the data buffer specified by Data.
+ @param[in] Data A pointer to the buffer of data that will be sent. The data format
+ depends on the type of SMP event data being responded to.
+
+ @retval EFI_SUCCESS The SMP authorization data is sent successfully.
+ @retval EFI_NOT_READY SMP is not in the correct state to receive the auth data.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_BLUETOOTH_LE_SEND_SMP_AUTH_DATA)(
+ IN EFI_BLUETOOTH_LE_CONFIG_PROTOCOL *This,
+ IN BLUETOOTH_LE_ADDRESS *BDAddr,
+ IN EFI_BLUETOOTH_LE_SMP_EVENT_DATA_TYPE EventDataType,
+ IN UINTN DataSize,
+ IN VOID *Data
+ );
+
+typedef enum {
+ // For local device only
+ EfiBluetoothSmpLocalIR, /* If Key hierarchy is supported */
+ EfiBluetoothSmpLocalER, /* If Key hierarchy is supported */
+ EfiBluetoothSmpLocalDHK, /* If Key hierarchy is supported. OPTIONAL */
+ // For peer specific
+ EfiBluetoothSmpKeysDistributed = 0x1000,
+ EfiBluetoothSmpKeySize,
+ EfiBluetoothSmpKeyType,
+ EfiBluetoothSmpPeerLTK,
+ EfiBluetoothSmpPeerIRK,
+ EfiBluetoothSmpPeerCSRK,
+ EfiBluetoothSmpPeerRand,
+ EfiBluetoothSmpPeerEDIV,
+ EfiBluetoothSmpPeerSignCounter,
+ EfiBluetoothSmpLocalLTK, /* If Key hierarchy not supported */
+ EfiBluetoothSmpLocalIRK, /* If Key hierarchy not supported */
+ EfiBluetoothSmpLocalCSRK, /* If Key hierarchy not supported */
+ EfiBluetoothSmpLocalSignCounter,
+ EfiBluetoothSmpLocalDIV,
+ EfiBluetoothSmpPeerAddressList,
+ EfiBluetoothSmpMax,
+} EFI_BLUETOOTH_LE_SMP_DATA_TYPE;
+
+/**
+ The callback function to get SMP data.
+
+ @param[in] This Pointer to the EFI_BLUETOOTH_LE_CONFIG_PROTOCOL instance.
+ @param[in] Context Data passed into callback function. This is optional parameter
+ and may be NULL.
+ @param[in] BDAddr Remote BluetoothLE device address. For Local device setting, it
+ should be NULL.
+ @param[in] DataType Data type in EFI_BLUETOOTH_LE_SMP_DATA_TYPE.
+ @param[in, out] DataSize On input, indicates the size, in bytes, of the data buffer specified
+ by Data. On output, indicates the amount of data actually returned.
+ @param[out] Data A pointer to the buffer of data that will be returned.
+
+ @retval EFI_SUCCESS The callback function complete successfully.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_BLUETOOTH_LE_CONFIG_SMP_GET_DATA_CALLBACK)(
+ IN EFI_BLUETOOTH_LE_CONFIG_PROTOCOL *This,
+ IN VOID *Context,
+ IN BLUETOOTH_LE_ADDRESS *BDAddr,
+ IN EFI_BLUETOOTH_LE_SMP_DATA_TYPE DataType,
+ IN OUT UINTN *DataSize,
+ OUT VOID *Data
+ );
+
+/**
+ Register a callback function to get SMP related data.
+
+ The RegisterSmpGetDataCallback() function registers a callback function to get SMP related data.
+
+ @param[in] This Pointer to the EFI_BLUETOOTH_LE_CONFIG_PROTOCOL instance.
+ @param[in] Callback Callback function for SMP get data.
+ @param[in] Context Data passed into Callback function. This is optional parameter and may be NULL.
+
+ @retval EFI_SUCCESS The SMP get data callback function is registered successfully.
+ @retval EFI_ALREADY_STARTED A callback function is already registered on the same attribute
+ opcode and attribute handle, when the Callback is not NULL.
+ @retval EFI_NOT_STARTED A callback function is not registered on the same attribute opcode
+ and attribute handle, when the Callback is NULL
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_BLUETOOTH_LE_CONFIG_REGISTER_SMP_GET_DATA_CALLBACK)(
+ IN EFI_BLUETOOTH_LE_CONFIG_PROTOCOL *This,
+ IN EFI_BLUETOOTH_LE_CONFIG_SMP_GET_DATA_CALLBACK Callback,
+ IN VOID *Context
+ );
+
+/**
+ The callback function to set SMP data.
+
+ @param[in] This Pointer to the EFI_BLUETOOTH_LE_CONFIG_PROTOCOL instance.
+ @param[in] Context Data passed into callback function. This is optional parameter
+ and may be NULL.
+ @param[in] BDAddr Remote BluetoothLE device address.
+ @param[in] DataType Data type in EFI_BLUETOOTH_LE_SMP_DATA_TYPE.
+ @param[in] DataSize Indicates the size, in bytes, of the data buffer specified by Data.
+ @param[in] Data A pointer to the buffer of data.
+
+ @retval EFI_SUCCESS The callback function complete successfully.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_BLUETOOTH_LE_CONFIG_SMP_SET_DATA_CALLBACK)(
+ IN EFI_BLUETOOTH_LE_CONFIG_PROTOCOL *This,
+ IN VOID *Context,
+ IN BLUETOOTH_LE_ADDRESS *BDAddr,
+ IN EFI_BLUETOOTH_LE_SMP_DATA_TYPE Type,
+ IN UINTN DataSize,
+ IN VOID *Data
+ );
+
+/**
+ Register a callback function to set SMP related data.
+
+ The RegisterSmpSetDataCallback() function registers a callback function to set SMP related data.
+
+ @param[in] This Pointer to the EFI_BLUETOOTH_LE_CONFIG_PROTOCOL instance.
+ @param[in] Callback Callback function for SMP set data.
+ @param[in] Context Data passed into Callback function. This is optional parameter and may be NULL.
+
+ @retval EFI_SUCCESS The SMP set data callback function is registered successfully.
+ @retval EFI_ALREADY_STARTED A callback function is already registered on the same attribute
+ opcode and attribute handle, when the Callback is not NULL.
+ @retval EFI_NOT_STARTED A callback function is not registered on the same attribute opcode
+ and attribute handle, when the Callback is NULL
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_BLUETOOTH_LE_CONFIG_REGISTER_SMP_SET_DATA_CALLBACK)(
+ IN EFI_BLUETOOTH_LE_CONFIG_PROTOCOL *This,
+ IN EFI_BLUETOOTH_LE_CONFIG_SMP_SET_DATA_CALLBACK Callback,
+ IN VOID *Context
+ );
+
+/**
+ The callback function to hook connect complete event.
+
+ @param[in] This Pointer to the EFI_BLUETOOTH_LE_CONFIG_PROTOCOL instance.
+ @param[in] Context Data passed into callback function. This is optional parameter
+ and may be NULL.
+ @param[in] CallbackType The value defined in EFI_BLUETOOTH_CONNECT_COMPLETE_CALLBACK_TYPE.
+ @param[in] BDAddr Remote BluetoothLE device address.
+ @param[in] InputBuffer A pointer to the buffer of data that is input from callback caller.
+ @param[in] InputBufferSize Indicates the size, in bytes, of the data buffer specified by InputBuffer.
+
+ @retval EFI_SUCCESS The callback function complete successfully.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_BLUETOOTH_LE_CONFIG_CONNECT_COMPLETE_CALLBACK)(
+ IN EFI_BLUETOOTH_LE_CONFIG_PROTOCOL *This,
+ IN VOID *Context,
+ IN EFI_BLUETOOTH_CONNECT_COMPLETE_CALLBACK_TYPE CallbackType,
+ IN BLUETOOTH_LE_ADDRESS *BDAddr,
+ IN VOID *InputBuffer,
+ IN UINTN InputBufferSize
+ );
+
+/**
+ Register link connect complete callback function.
+
+ The RegisterLinkConnectCompleteCallback() function registers Bluetooth link connect
+ complete callback function. The Bluetooth Configuration driver may call
+ RegisterLinkConnectCompleteCallback() to register a callback function. During pairing,
+ Bluetooth bus driver must trigger this callback function to report device state, if it is registered.
+ Then Bluetooth Configuration driver will get information on device connection, according to
+ CallbackType defined by EFI_BLUETOOTH_CONNECT_COMPLETE_CALLBACK_TYPE
+
+ @param[in] This Pointer to the EFI_BLUETOOTH_LE_CONFIG_PROTOCOL instance.
+ @param[in] Callback The callback function. NULL means unregister.
+ @param[in] Context Data passed into Callback function. This is optional parameter and may be NULL.
+
+ @retval EFI_SUCCESS The link connect complete callback function is registered successfully.
+ @retval EFI_ALREADY_STARTED A callback function is already registered on the same attribute
+ opcode and attribute handle, when the Callback is not NULL.
+ @retval EFI_NOT_STARTED A callback function is not registered on the same attribute opcode
+ and attribute handle, when the Callback is NULL
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_BLUETOOTH_LE_CONFIG_REGISTER_CONNECT_COMPLETE_CALLBACK)(
+ IN EFI_BLUETOOTH_LE_CONFIG_PROTOCOL *This,
+ IN EFI_BLUETOOTH_LE_CONFIG_CONNECT_COMPLETE_CALLBACK Callback,
+ IN VOID *Context
+ );
+
+///
+/// This protocol abstracts user interface configuration for BluetoothLe device.
+///
+struct _EFI_BLUETOOTH_LE_CONFIG_PROTOCOL {
+ EFI_BLUETOOTH_LE_CONFIG_INIT Init;
+ EFI_BLUETOOTH_LE_CONFIG_SCAN Scan;
+ EFI_BLUETOOTH_LE_CONFIG_CONNECT Connect;
+ EFI_BLUETOOTH_LE_CONFIG_DISCONNECT Disconnect;
+ EFI_BLUETOOTH_LE_CONFIG_GET_DATA GetData;
+ EFI_BLUETOOTH_LE_CONFIG_SET_DATA SetData;
+ EFI_BLUETOOTH_LE_CONFIG_GET_REMOTE_DATA GetRemoteData;
+ EFI_BLUETOOTH_LE_REGISTER_SMP_AUTH_CALLBACK RegisterSmpAuthCallback;
+ EFI_BLUETOOTH_LE_SEND_SMP_AUTH_DATA SendSmpAuthData;
+ EFI_BLUETOOTH_LE_CONFIG_REGISTER_SMP_GET_DATA_CALLBACK RegisterSmpGetDataCallback;
+ EFI_BLUETOOTH_LE_CONFIG_REGISTER_SMP_SET_DATA_CALLBACK RegisterSmpSetDataCallback;
+ EFI_BLUETOOTH_LE_CONFIG_REGISTER_CONNECT_COMPLETE_CALLBACK RegisterLinkConnectCompleteCallback;
+};
+
+extern EFI_GUID gEfiBluetoothLeConfigProtocolGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/BootManagerPolicy.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/BootManagerPolicy.h
new file mode 100644
index 0000000000..dc27ccaa1d
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/BootManagerPolicy.h
@@ -0,0 +1,132 @@
+/** @file
+ Boot Manager Policy Protocol as defined in UEFI Specification.
+
+ This protocol is used by EFI Applications to request the UEFI Boot Manager
+ to connect devices using platform policy.
+
+ Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef __BOOT_MANAGER_POLICY_H__
+#define __BOOT_MANAGER_POLICY_H__
+
+#define EFI_BOOT_MANAGER_POLICY_PROTOCOL_GUID \
+ { \
+ 0xFEDF8E0C, 0xE147, 0x11E3, { 0x99, 0x03, 0xB8, 0xE8, 0x56, 0x2C, 0xBA, 0xFA } \
+ }
+
+#define EFI_BOOT_MANAGER_POLICY_CONSOLE_GUID \
+ { \
+ 0xCAB0E94C, 0xE15F, 0x11E3, { 0x91, 0x8D, 0xB8, 0xE8, 0x56, 0x2C, 0xBA, 0xFA } \
+ }
+
+#define EFI_BOOT_MANAGER_POLICY_NETWORK_GUID \
+ { \
+ 0xD04159DC, 0xE15F, 0x11E3, { 0xB2, 0x61, 0xB8, 0xE8, 0x56, 0x2C, 0xBA, 0xFA } \
+ }
+
+#define EFI_BOOT_MANAGER_POLICY_CONNECT_ALL_GUID \
+ { \
+ 0x113B2126, 0xFC8A, 0x11E3, { 0xBD, 0x6C, 0xB8, 0xE8, 0x56, 0x2C, 0xBA, 0xFA } \
+ }
+
+typedef struct _EFI_BOOT_MANAGER_POLICY_PROTOCOL EFI_BOOT_MANAGER_POLICY_PROTOCOL;
+
+#define EFI_BOOT_MANAGER_POLICY_PROTOCOL_REVISION 0x00010000
+
+/**
+ Connect a device path following the platforms EFI Boot Manager policy.
+
+ The ConnectDevicePath() function allows the caller to connect a DevicePath using the
+ same policy as the EFI Boot Manger.
+
+ @param[in] This A pointer to the EFI_BOOT_MANAGER_POLICY_PROTOCOL instance.
+ @param[in] DevicePath Points to the start of the EFI device path to connect.
+ If DevicePath is NULL then all the controllers in the
+ system will be connected using the platforms EFI Boot
+ Manager policy.
+ @param[in] Recursive If TRUE, then ConnectController() is called recursively
+ until the entire tree of controllers below the
+ controller specified by DevicePath have been created.
+ If FALSE, then the tree of controllers is only expanded
+ one level. If DevicePath is NULL then Recursive is ignored.
+
+ @retval EFI_SUCCESS The DevicePath was connected.
+ @retval EFI_NOT_FOUND The DevicePath was not found.
+ @retval EFI_NOT_FOUND No driver was connected to DevicePath.
+ @retval EFI_SECURITY_VIOLATION The user has no permission to start UEFI device
+ drivers on the DevicePath.
+ @retval EFI_UNSUPPORTED The current TPL is not TPL_APPLICATION.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_BOOT_MANAGER_POLICY_CONNECT_DEVICE_PATH)(
+ IN EFI_BOOT_MANAGER_POLICY_PROTOCOL *This,
+ IN EFI_DEVICE_PATH *DevicePath,
+ IN BOOLEAN Recursive
+ );
+
+/**
+ Connect a class of devices using the platform Boot Manager policy.
+
+ The ConnectDeviceClass() function allows the caller to request that the Boot
+ Manager connect a class of devices.
+
+ If Class is EFI_BOOT_MANAGER_POLICY_CONSOLE_GUID then the Boot Manager will
+ use platform policy to connect consoles. Some platforms may restrict the
+ number of consoles connected as they attempt to fast boot, and calling
+ ConnectDeviceClass() with a Class value of EFI_BOOT_MANAGER_POLICY_CONSOLE_GUID
+ must connect the set of consoles that follow the Boot Manager platform policy,
+ and the EFI_SIMPLE_TEXT_INPUT_PROTOCOL, EFI_SIMPLE_TEXT_INPUT_EX_PROTOCOL, and
+ the EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL are produced on the connected handles.
+ The Boot Manager may restrict which consoles get connect due to platform policy,
+ for example a security policy may require that a given console is not connected.
+
+ If Class is EFI_BOOT_MANAGER_POLICY_NETWORK_GUID then the Boot Manager will
+ connect the protocols the platforms supports for UEFI general purpose network
+ applications on one or more handles. If more than one network controller is
+ available a platform will connect, one, many, or all of the networks based
+ on platform policy. Connecting UEFI networking protocols, like EFI_DHCP4_PROTOCOL,
+ does not establish connections on the network. The UEFI general purpose network
+ application that called ConnectDeviceClass() may need to use the published
+ protocols to establish the network connection. The Boot Manager can optionally
+ have a policy to establish a network connection.
+
+ If Class is EFI_BOOT_MANAGER_POLICY_CONNECT_ALL_GUID then the Boot Manager
+ will connect all UEFI drivers using the UEFI Boot Service
+ EFI_BOOT_SERVICES.ConnectController(). If the Boot Manager has policy
+ associated with connect all UEFI drivers this policy will be used.
+
+ A platform can also define platform specific Class values as a properly generated
+ EFI_GUID would never conflict with this specification.
+
+ @param[in] This A pointer to the EFI_BOOT_MANAGER_POLICY_PROTOCOL instance.
+ @param[in] Class A pointer to an EFI_GUID that represents a class of devices
+ that will be connected using the Boot Mangers platform policy.
+
+ @retval EFI_SUCCESS At least one devices of the Class was connected.
+ @retval EFI_DEVICE_ERROR Devices were not connected due to an error.
+ @retval EFI_NOT_FOUND The Class is not supported by the platform.
+ @retval EFI_UNSUPPORTED The current TPL is not TPL_APPLICATION.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_BOOT_MANAGER_POLICY_CONNECT_DEVICE_CLASS)(
+ IN EFI_BOOT_MANAGER_POLICY_PROTOCOL *This,
+ IN EFI_GUID *Class
+ );
+
+struct _EFI_BOOT_MANAGER_POLICY_PROTOCOL {
+ UINT64 Revision;
+ EFI_BOOT_MANAGER_POLICY_CONNECT_DEVICE_PATH ConnectDevicePath;
+ EFI_BOOT_MANAGER_POLICY_CONNECT_DEVICE_CLASS ConnectDeviceClass;
+};
+
+extern EFI_GUID gEfiBootManagerPolicyProtocolGuid;
+
+extern EFI_GUID gEfiBootManagerPolicyConsoleGuid;
+extern EFI_GUID gEfiBootManagerPolicyNetworkGuid;
+extern EFI_GUID gEfiBootManagerPolicyConnectAllGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/BusSpecificDriverOverride.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/BusSpecificDriverOverride.h
new file mode 100644
index 0000000000..8d6ba1c7c8
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/BusSpecificDriverOverride.h
@@ -0,0 +1,66 @@
+/** @file
+ Bus Specific Driver Override protocol as defined in the UEFI 2.0 specification.
+
+ Bus drivers that have a bus specific algorithm for matching drivers to controllers are
+ required to produce this protocol for each controller. For example, a PCI Bus Driver will produce an
+ instance of this protocol for every PCI controller that has a PCI option ROM that contains one or
+ more UEFI drivers. The protocol instance is attached to the handle of the PCI controller.
+
+ Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _EFI_BUS_SPECIFIC_DRIVER_OVERRIDE_PROTOCOL_H_
+#define _EFI_BUS_SPECIFIC_DRIVER_OVERRIDE_PROTOCOL_H_
+
+///
+/// Global ID for the Bus Specific Driver Override Protocol
+///
+#define EFI_BUS_SPECIFIC_DRIVER_OVERRIDE_PROTOCOL_GUID \
+ { \
+ 0x3bc1b285, 0x8a15, 0x4a82, {0xaa, 0xbf, 0x4d, 0x7d, 0x13, 0xfb, 0x32, 0x65 } \
+ }
+
+typedef struct _EFI_BUS_SPECIFIC_DRIVER_OVERRIDE_PROTOCOL EFI_BUS_SPECIFIC_DRIVER_OVERRIDE_PROTOCOL;
+
+//
+// Prototypes for the Bus Specific Driver Override Protocol
+//
+
+/**
+ Uses a bus specific algorithm to retrieve a driver image handle for a controller.
+
+ @param This A pointer to the EFI_BUS_SPECIFIC_DRIVER_
+ OVERRIDE_PROTOCOL instance.
+ @param DriverImageHandle On input, a pointer to the previous driver image handle returned
+ by GetDriver(). On output, a pointer to the next driver
+ image handle. Passing in a NULL, will return the first driver
+ image handle.
+
+ @retval EFI_SUCCESS A bus specific override driver is returned in DriverImageHandle.
+ @retval EFI_NOT_FOUND The end of the list of override drivers was reached.
+ A bus specific override driver is not returned in DriverImageHandle.
+ @retval EFI_INVALID_PARAMETER DriverImageHandle is not a handle that was returned on a
+ previous call to GetDriver().
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_BUS_SPECIFIC_DRIVER_OVERRIDE_GET_DRIVER)(
+ IN EFI_BUS_SPECIFIC_DRIVER_OVERRIDE_PROTOCOL *This,
+ IN OUT EFI_HANDLE *DriverImageHandle
+ );
+
+///
+/// This protocol matches one or more drivers to a controller. This protocol is produced by a bus driver,
+/// and it is installed on the child handles of buses that require a bus specific algorithm for matching
+/// drivers to controllers.
+///
+struct _EFI_BUS_SPECIFIC_DRIVER_OVERRIDE_PROTOCOL {
+ EFI_BUS_SPECIFIC_DRIVER_OVERRIDE_GET_DRIVER GetDriver;
+};
+
+extern EFI_GUID gEfiBusSpecificDriverOverrideProtocolGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/Capsule.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/Capsule.h
new file mode 100644
index 0000000000..bc1c85ea39
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/Capsule.h
@@ -0,0 +1,29 @@
+/** @file
+ Capsule Architectural Protocol as defined in PI1.0a Specification VOLUME 2 DXE
+
+ The DXE Driver that produces this protocol must be a runtime driver.
+ The driver is responsible for initializing the CapsuleUpdate() and
+ QueryCapsuleCapabilities() fields of the UEFI Runtime Services Table.
+ After the two fields of the UEFI Runtime Services Table have been initialized,
+ the driver must install the EFI_CAPSULE_ARCH_PROTOCOL_GUID on a new handle
+ with a NULL interface pointer. The installation of this protocol informs
+ the DXE Foundation that the Capsule related services are now available and
+ that the DXE Foundation must update the 32-bit CRC of the UEFI Runtime Services Table.
+
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __ARCH_PROTOCOL_CAPSULE_ARCH_H__
+#define __ARCH_PROTOCOL_CAPSULE_ARCH_H__
+
+//
+// Global ID for the Capsule Architectural Protocol
+//
+#define EFI_CAPSULE_ARCH_PROTOCOL_GUID \
+ { 0x5053697e, 0x2cbc, 0x4819, {0x90, 0xd9, 0x05, 0x80, 0xde, 0xee, 0x57, 0x54 }}
+
+extern EFI_GUID gEfiCapsuleArchProtocolGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/CcMeasurement.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/CcMeasurement.h
new file mode 100644
index 0000000000..43d24036c5
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/CcMeasurement.h
@@ -0,0 +1,323 @@
+/** @file
+ If CC Guest firmware supports measurement and an event is created,
+ CC Guest firmware is designed to report the event log with the same
+ data structure in TCG-Platform-Firmware-Profile specification with
+ EFI_TCG2_EVENT_LOG_FORMAT_TCG_2 format.
+
+ The CC Guest firmware supports measurement, the CC Guest Firmware is
+ designed to produce EFI_CC_MEASUREMENT_PROTOCOL with new GUID
+ EFI_CC_MEASUREMENT_PROTOCOL_GUID to report event log and provides hash
+ capability.
+
+Copyright (c) 2020 - 2021, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef CC_MEASUREMENT_PROTOCOL_H_
+#define CC_MEASUREMENT_PROTOCOL_H_
+
+#include
+
+#define EFI_CC_MEASUREMENT_PROTOCOL_GUID \
+ { 0x96751a3d, 0x72f4, 0x41a6, { 0xa7, 0x94, 0xed, 0x5d, 0x0e, 0x67, 0xae, 0x6b }}
+extern EFI_GUID gEfiCcMeasurementProtocolGuid;
+
+typedef struct _EFI_CC_MEASUREMENT_PROTOCOL EFI_CC_MEASUREMENT_PROTOCOL;
+
+typedef struct {
+ UINT8 Major;
+ UINT8 Minor;
+} EFI_CC_VERSION;
+
+//
+// EFI_CC Type/SubType definition
+//
+#define EFI_CC_TYPE_NONE 0
+#define EFI_CC_TYPE_SEV 1
+#define EFI_CC_TYPE_TDX 2
+
+typedef struct {
+ UINT8 Type;
+ UINT8 SubType;
+} EFI_CC_TYPE;
+
+typedef UINT32 EFI_CC_EVENT_LOG_BITMAP;
+typedef UINT32 EFI_CC_EVENT_LOG_FORMAT;
+typedef UINT32 EFI_CC_EVENT_ALGORITHM_BITMAP;
+typedef UINT32 EFI_CC_MR_INDEX;
+
+//
+// Intel TDX measure register index
+//
+#define TDX_MR_INDEX_MRTD 0
+#define TDX_MR_INDEX_RTMR0 1
+#define TDX_MR_INDEX_RTMR1 2
+#define TDX_MR_INDEX_RTMR2 3
+#define TDX_MR_INDEX_RTMR3 4
+
+#define EFI_CC_EVENT_LOG_FORMAT_TCG_2 0x00000002
+#define EFI_CC_BOOT_HASH_ALG_SHA384 0x00000004
+
+//
+// This bit is shall be set when an event shall be extended but not logged.
+//
+#define EFI_CC_FLAG_EXTEND_ONLY 0x0000000000000001
+//
+// This bit shall be set when the intent is to measure a PE/COFF image.
+//
+#define EFI_CC_FLAG_PE_COFF_IMAGE 0x0000000000000010
+
+#pragma pack (1)
+
+#define EFI_CC_EVENT_HEADER_VERSION 1
+
+typedef struct {
+ //
+ // Size of the event header itself (sizeof(EFI_CC_EVENT_HEADER)).
+ //
+ UINT32 HeaderSize;
+ //
+ // Header version. For this version of this specification, the value shall be 1.
+ //
+ UINT16 HeaderVersion;
+ //
+ // Index of the MR (measurement register) that shall be extended.
+ //
+ EFI_CC_MR_INDEX MrIndex;
+ //
+ // Type of the event that shall be extended (and optionally logged).
+ //
+ UINT32 EventType;
+} EFI_CC_EVENT_HEADER;
+
+typedef struct {
+ //
+ // Total size of the event including the Size component, the header and the Event data.
+ //
+ UINT32 Size;
+ EFI_CC_EVENT_HEADER Header;
+ UINT8 Event[1];
+} EFI_CC_EVENT;
+
+#pragma pack()
+
+typedef struct {
+ //
+ // Allocated size of the structure
+ //
+ UINT8 Size;
+ //
+ // Version of the EFI_CC_BOOT_SERVICE_CAPABILITY structure itself.
+ // For this version of the protocol, the Major version shall be set to 1
+ // and the Minor version shall be set to 0.
+ //
+ EFI_CC_VERSION StructureVersion;
+ //
+ // Version of the EFI CC Measurement protocol.
+ // For this version of the protocol, the Major version shall be set to 1
+ // and the Minor version shall be set to 0.
+ //
+ EFI_CC_VERSION ProtocolVersion;
+ //
+ // Supported hash algorithms
+ //
+ EFI_CC_EVENT_ALGORITHM_BITMAP HashAlgorithmBitmap;
+ //
+ // Bitmap of supported event log formats
+ //
+ EFI_CC_EVENT_LOG_BITMAP SupportedEventLogs;
+
+ //
+ // Indicates the CC type
+ //
+ EFI_CC_TYPE CcType;
+} EFI_CC_BOOT_SERVICE_CAPABILITY;
+
+/**
+ The EFI_CC_MEASUREMENT_PROTOCOL GetCapability function call provides protocol
+ capability information and state information.
+
+ @param[in] This Indicates the calling context
+ @param[in, out] ProtocolCapability The caller allocates memory for a EFI_CC_BOOT_SERVICE_CAPABILITY
+ structure and sets the size field to the size of the structure allocated.
+ The callee fills in the fields with the EFI CC BOOT Service capability
+ information and the current CC information.
+
+ @retval EFI_SUCCESS Operation completed successfully.
+ @retval EFI_DEVICE_ERROR The command was unsuccessful.
+ The ProtocolCapability variable will not be populated.
+ @retval EFI_INVALID_PARAMETER One or more of the parameters are incorrect.
+ The ProtocolCapability variable will not be populated.
+ @retval EFI_BUFFER_TOO_SMALL The ProtocolCapability variable is too small to hold the full response.
+ It will be partially populated (required Size field will be set).
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_CC_GET_CAPABILITY)(
+ IN EFI_CC_MEASUREMENT_PROTOCOL *This,
+ IN OUT EFI_CC_BOOT_SERVICE_CAPABILITY *ProtocolCapability
+ );
+
+/**
+ The EFI_CC_MEASUREMENT_PROTOCOL Get Event Log function call allows a caller to
+ retrieve the address of a given event log and its last entry.
+
+ @param[in] This Indicates the calling context
+ @param[in] EventLogFormat The type of the event log for which the information is requested.
+ @param[out] EventLogLocation A pointer to the memory address of the event log.
+ @param[out] EventLogLastEntry If the Event Log contains more than one entry, this is a pointer to the
+ address of the start of the last entry in the event log in memory.
+ @param[out] EventLogTruncated If the Event Log is missing at least one entry because an event would
+ have exceeded the area allocated for events, this value is set to TRUE.
+ Otherwise, the value will be FALSE and the Event Log will be complete.
+
+ @retval EFI_SUCCESS Operation completed successfully.
+ @retval EFI_INVALID_PARAMETER One or more of the parameters are incorrect
+ (e.g. asking for an event log whose format is not supported).
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_CC_GET_EVENT_LOG)(
+ IN EFI_CC_MEASUREMENT_PROTOCOL *This,
+ IN EFI_CC_EVENT_LOG_FORMAT EventLogFormat,
+ OUT EFI_PHYSICAL_ADDRESS *EventLogLocation,
+ OUT EFI_PHYSICAL_ADDRESS *EventLogLastEntry,
+ OUT BOOLEAN *EventLogTruncated
+ );
+
+/**
+ The EFI_CC_MEASUREMENT_PROTOCOL HashLogExtendEvent function call provides
+ callers with an opportunity to extend and optionally log events without requiring
+ knowledge of actual CC commands.
+ The extend operation will occur even if this function cannot create an event
+ log entry (e.g. due to the event log being full).
+
+ @param[in] This Indicates the calling context
+ @param[in] Flags Bitmap providing additional information.
+ @param[in] DataToHash Physical address of the start of the data buffer to be hashed.
+ @param[in] DataToHashLen The length in bytes of the buffer referenced by DataToHash.
+ @param[in] EfiCcEvent Pointer to data buffer containing information about the event.
+
+ @retval EFI_SUCCESS Operation completed successfully.
+ @retval EFI_DEVICE_ERROR The command was unsuccessful.
+ @retval EFI_VOLUME_FULL The extend operation occurred, but the event could not be written to one or more event logs.
+ @retval EFI_INVALID_PARAMETER One or more of the parameters are incorrect.
+ @retval EFI_UNSUPPORTED The PE/COFF image type is not supported.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_CC_HASH_LOG_EXTEND_EVENT)(
+ IN EFI_CC_MEASUREMENT_PROTOCOL *This,
+ IN UINT64 Flags,
+ IN EFI_PHYSICAL_ADDRESS DataToHash,
+ IN UINT64 DataToHashLen,
+ IN EFI_CC_EVENT *EfiCcEvent
+ );
+
+/**
+ The EFI_CC_MEASUREMENT_PROTOCOL MapPcrToMrIndex function call provides callers
+ the info on TPM PCR <-> CC MR mapping information.
+
+ @param[in] This Indicates the calling context
+ @param[in] PcrIndex TPM PCR index.
+ @param[out] MrIndex CC MR index.
+
+ @retval EFI_SUCCESS The MrIndex is returned.
+ @retval EFI_INVALID_PARAMETER The MrIndex is NULL.
+ @retval EFI_UNSUPPORTED The PcrIndex is invalid.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_CC_MAP_PCR_TO_MR_INDEX)(
+ IN EFI_CC_MEASUREMENT_PROTOCOL *This,
+ IN TCG_PCRINDEX PcrIndex,
+ OUT EFI_CC_MR_INDEX *MrIndex
+ );
+
+struct _EFI_CC_MEASUREMENT_PROTOCOL {
+ EFI_CC_GET_CAPABILITY GetCapability;
+ EFI_CC_GET_EVENT_LOG GetEventLog;
+ EFI_CC_HASH_LOG_EXTEND_EVENT HashLogExtendEvent;
+ EFI_CC_MAP_PCR_TO_MR_INDEX MapPcrToMrIndex;
+};
+
+//
+// CC event log
+//
+
+#pragma pack(1)
+
+//
+// Crypto Agile Log Entry Format.
+// It is similar with TCG_PCR_EVENT2 except the field of MrIndex and PCRIndex.
+//
+typedef struct {
+ EFI_CC_MR_INDEX MrIndex;
+ UINT32 EventType;
+ TPML_DIGEST_VALUES Digests;
+ UINT32 EventSize;
+ UINT8 Event[1];
+} CC_EVENT;
+
+//
+// EFI CC Event Header
+// It is similar with TCG_PCR_EVENT2_HDR except the field of MrIndex and PCRIndex
+//
+typedef struct {
+ EFI_CC_MR_INDEX MrIndex;
+ UINT32 EventType;
+ TPML_DIGEST_VALUES Digests;
+ UINT32 EventSize;
+} CC_EVENT_HDR;
+
+#pragma pack()
+
+//
+// Log entries after Get Event Log service
+//
+
+#define EFI_CC_FINAL_EVENTS_TABLE_VERSION 1
+
+typedef struct {
+ //
+ // The version of this structure. It shall be set to 1.
+ //
+ UINT64 Version;
+ //
+ // Number of events recorded after invocation of GetEventLog API
+ //
+ UINT64 NumberOfEvents;
+ //
+ // List of events of type CC_EVENT.
+ //
+ // CC_EVENT Event[1];
+} EFI_CC_FINAL_EVENTS_TABLE;
+
+#define EFI_CC_FINAL_EVENTS_TABLE_GUID \
+ {0xdd4a4648, 0x2de7, 0x4665, {0x96, 0x4d, 0x21, 0xd9, 0xef, 0x5f, 0xb4, 0x46}}
+
+extern EFI_GUID gEfiCcFinalEventsTableGuid;
+
+//
+// Define the CC Measure EventLog ACPI Table
+//
+#pragma pack(1)
+
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ EFI_CC_TYPE CcType;
+ UINT16 Rsvd;
+ UINT64 Laml;
+ UINT64 Lasa;
+} EFI_CC_EVENTLOG_ACPI_TABLE;
+
+#pragma pack()
+
+//
+// Define the signature and revision of CC Measurement EventLog ACPI Table
+//
+#define EFI_CC_EVENTLOG_ACPI_TABLE_SIGNATURE SIGNATURE_32('C', 'C', 'E', 'L')
+#define EFI_CC_EVENTLOG_ACPI_TABLE_REVISION 1
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/ComponentName.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/ComponentName.h
new file mode 100644
index 0000000000..89d203c201
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/ComponentName.h
@@ -0,0 +1,121 @@
+/** @file
+ EFI Component Name Protocol as defined in the EFI 1.1 specification.
+ This protocol is used to retrieve user readable names of EFI Drivers
+ and controllers managed by EFI Drivers.
+
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __EFI_COMPONENT_NAME_H__
+#define __EFI_COMPONENT_NAME_H__
+
+///
+/// The global ID for the Component Name Protocol.
+///
+#define EFI_COMPONENT_NAME_PROTOCOL_GUID \
+ { \
+ 0x107a772c, 0xd5e1, 0x11d4, {0x9a, 0x46, 0x0, 0x90, 0x27, 0x3f, 0xc1, 0x4d } \
+ }
+
+typedef struct _EFI_COMPONENT_NAME_PROTOCOL EFI_COMPONENT_NAME_PROTOCOL;
+
+/**
+ Retrieves a Unicode string that is the user-readable name of the EFI Driver.
+
+ @param This A pointer to the EFI_COMPONENT_NAME_PROTOCOL instance.
+ @param Language A pointer to a three-character ISO 639-2 language identifier.
+ This is the language of the driver name that that the caller
+ is requesting, and it must match one of the languages specified
+ in SupportedLanguages. The number of languages supported by a
+ driver is up to the driver writer.
+ @param DriverName A pointer to the Unicode string to return. This Unicode string
+ is the name of the driver specified by This in the language
+ specified by Language.
+
+ @retval EFI_SUCCESS The Unicode string for the Driver specified by This
+ and the language specified by Language was returned
+ in DriverName.
+ @retval EFI_INVALID_PARAMETER Language is NULL.
+ @retval EFI_INVALID_PARAMETER DriverName is NULL.
+ @retval EFI_UNSUPPORTED The driver specified by This does not support the
+ language specified by Language.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_COMPONENT_NAME_GET_DRIVER_NAME)(
+ IN EFI_COMPONENT_NAME_PROTOCOL *This,
+ IN CHAR8 *Language,
+ OUT CHAR16 **DriverName
+ );
+
+/**
+ Retrieves a Unicode string that is the user readable name of the controller
+ that is being managed by an EFI Driver.
+
+ @param This A pointer to the EFI_COMPONENT_NAME_PROTOCOL instance.
+ @param ControllerHandle The handle of a controller that the driver specified by
+ This is managing. This handle specifies the controller
+ whose name is to be returned.
+ @param ChildHandle The handle of the child controller to retrieve the name
+ of. This is an optional parameter that may be NULL. It
+ will be NULL for device drivers. It will also be NULL
+ for a bus drivers that wish to retrieve the name of the
+ bus controller. It will not be NULL for a bus driver
+ that wishes to retrieve the name of a child controller.
+ @param Language A pointer to a three character ISO 639-2 language
+ identifier. This is the language of the controller name
+ that the caller is requesting, and it must match one
+ of the languages specified in SupportedLanguages. The
+ number of languages supported by a driver is up to the
+ driver writer.
+ @param ControllerName A pointer to the Unicode string to return. This Unicode
+ string is the name of the controller specified by
+ ControllerHandle and ChildHandle in the language specified
+ by Language, from the point of view of the driver specified
+ by This.
+
+ @retval EFI_SUCCESS The Unicode string for the user-readable name in the
+ language specified by Language for the driver
+ specified by This was returned in DriverName.
+ @retval EFI_INVALID_PARAMETER ControllerHandle is NULL.
+ @retval EFI_INVALID_PARAMETER ChildHandle is not NULL and it is not a valid EFI_HANDLE.
+ @retval EFI_INVALID_PARAMETER Language is NULL.
+ @retval EFI_INVALID_PARAMETER ControllerName is NULL.
+ @retval EFI_UNSUPPORTED The driver specified by This is not currently managing
+ the controller specified by ControllerHandle and
+ ChildHandle.
+ @retval EFI_UNSUPPORTED The driver specified by This does not support the
+ language specified by Language.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_COMPONENT_NAME_GET_CONTROLLER_NAME)(
+ IN EFI_COMPONENT_NAME_PROTOCOL *This,
+ IN EFI_HANDLE ControllerHandle,
+ IN EFI_HANDLE ChildHandle OPTIONAL,
+ IN CHAR8 *Language,
+ OUT CHAR16 **ControllerName
+ );
+
+///
+/// This protocol is used to retrieve user readable names of drivers
+/// and controllers managed by UEFI Drivers.
+///
+struct _EFI_COMPONENT_NAME_PROTOCOL {
+ EFI_COMPONENT_NAME_GET_DRIVER_NAME GetDriverName;
+ EFI_COMPONENT_NAME_GET_CONTROLLER_NAME GetControllerName;
+ ///
+ /// A Null-terminated ASCII string that contains one or more
+ /// ISO 639-2 language codes. This is the list of language codes
+ /// that this protocol supports.
+ ///
+ CHAR8 *SupportedLanguages;
+};
+
+extern EFI_GUID gEfiComponentNameProtocolGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/ComponentName2.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/ComponentName2.h
new file mode 100644
index 0000000000..d1d3f8df9b
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/ComponentName2.h
@@ -0,0 +1,164 @@
+/** @file
+ UEFI Component Name 2 Protocol as defined in the UEFI 2.1 specification.
+ This protocol is used to retrieve user readable names of drivers
+ and controllers managed by UEFI Drivers.
+
+ Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __EFI_COMPONENT_NAME2_H__
+#define __EFI_COMPONENT_NAME2_H__
+
+///
+/// Global ID for the Component Name Protocol
+///
+#define EFI_COMPONENT_NAME2_PROTOCOL_GUID \
+ {0x6a7a5cff, 0xe8d9, 0x4f70, { 0xba, 0xda, 0x75, 0xab, 0x30, 0x25, 0xce, 0x14 } }
+
+typedef struct _EFI_COMPONENT_NAME2_PROTOCOL EFI_COMPONENT_NAME2_PROTOCOL;
+
+/**
+ Retrieves a string that is the user readable name of
+ the EFI Driver.
+
+ @param This A pointer to the
+ EFI_COMPONENT_NAME2_PROTOCOL instance.
+
+ @param Language A pointer to a Null-terminated ASCII string
+ array indicating the language. This is the
+ language of the driver name that the caller
+ is requesting, and it must match one of the
+ languages specified in SupportedLanguages.
+ The number of languages supported by a
+ driver is up to the driver writer. Language
+ is specified in RFC 4646 language code
+ format.
+
+ @param DriverName A pointer to the string to return.
+ This string is the name of the
+ driver specified by This in the language
+ specified by Language.
+
+ @retval EFI_SUCCESS The string for the
+ Driver specified by This and the
+ language specified by Language
+ was returned in DriverName.
+
+ @retval EFI_INVALID_PARAMETER Language is NULL.
+
+ @retval EFI_INVALID_PARAMETER DriverName is NULL.
+
+ @retval EFI_UNSUPPORTED The driver specified by This
+ does not support the language
+ specified by Language.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_COMPONENT_NAME2_GET_DRIVER_NAME)(
+ IN EFI_COMPONENT_NAME2_PROTOCOL *This,
+ IN CHAR8 *Language,
+ OUT CHAR16 **DriverName
+ );
+
+/**
+ Retrieves a string that is the user readable name of
+ the controller that is being managed by an EFI Driver.
+
+ @param This A pointer to the
+ EFI_COMPONENT_NAME2_PROTOCOL instance.
+
+ @param ControllerHandle The handle of a controller that the
+ driver specified by This is managing.
+ This handle specifies the controller
+ whose name is to be returned.
+
+ @param ChildHandle The handle of the child controller to
+ retrieve the name of. This is an
+ optional parameter that may be NULL.
+ It will be NULL for device drivers.
+ It will also be NULL for bus
+ drivers that wish to retrieve the
+ name of the bus controller. It will
+ not be NULL for a bus driver that
+ wishes to retrieve the name of a
+ child controller.
+
+ @param Language A pointer to a Null-terminated ASCII
+ string array indicating the language.
+ This is the language of the driver
+ name that the caller is requesting,
+ and it must match one of the
+ languages specified in
+ SupportedLanguages. The number of
+ languages supported by a driver is up
+ to the driver writer. Language is
+ specified in RFC 4646 language code
+ format.
+
+ @param ControllerName A pointer to the string to return.
+ This string is the name of the controller
+ specified by ControllerHandle and ChildHandle
+ in the language specified by Language
+ from the point of view of the driver
+ specified by This.
+
+ @retval EFI_SUCCESS The string for the user
+ readable name in the language
+ specified by Language for the
+ driver specified by This was
+ returned in DriverName.
+
+ @retval EFI_INVALID_PARAMETER ControllerHandle is NULL.
+
+ @retval EFI_INVALID_PARAMETER ChildHandle is not NULL and it
+ is not a valid EFI_HANDLE.
+
+ @retval EFI_INVALID_PARAMETER Language is NULL.
+
+ @retval EFI_INVALID_PARAMETER ControllerName is NULL.
+
+ @retval EFI_UNSUPPORTED The driver specified by This is
+ not currently managing the
+ controller specified by
+ ControllerHandle and
+ ChildHandle.
+
+ @retval EFI_UNSUPPORTED The driver specified by This
+ does not support the language
+ specified by Language.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_COMPONENT_NAME2_GET_CONTROLLER_NAME)(
+ IN EFI_COMPONENT_NAME2_PROTOCOL *This,
+ IN EFI_HANDLE ControllerHandle,
+ IN EFI_HANDLE ChildHandle OPTIONAL,
+ IN CHAR8 *Language,
+ OUT CHAR16 **ControllerName
+ );
+
+///
+/// This protocol is used to retrieve user readable names of drivers
+/// and controllers managed by UEFI Drivers.
+///
+struct _EFI_COMPONENT_NAME2_PROTOCOL {
+ EFI_COMPONENT_NAME2_GET_DRIVER_NAME GetDriverName;
+ EFI_COMPONENT_NAME2_GET_CONTROLLER_NAME GetControllerName;
+
+ ///
+ /// A Null-terminated ASCII string array that contains one or more
+ /// supported language codes. This is the list of language codes that
+ /// this protocol supports. The number of languages supported by a
+ /// driver is up to the driver writer. SupportedLanguages is
+ /// specified in RFC 4646 format.
+ ///
+ CHAR8 *SupportedLanguages;
+};
+
+extern EFI_GUID gEfiComponentName2ProtocolGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/Cpu.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/Cpu.h
new file mode 100644
index 0000000000..a618bb9723
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/Cpu.h
@@ -0,0 +1,286 @@
+/** @file
+ CPU Architectural Protocol as defined in PI spec Volume 2 DXE
+
+ This code abstracts the DXE core from processor implementation details.
+
+ Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __ARCH_PROTOCOL_CPU_H__
+#define __ARCH_PROTOCOL_CPU_H__
+
+#include
+
+#define EFI_CPU_ARCH_PROTOCOL_GUID \
+ { 0x26baccb1, 0x6f42, 0x11d4, {0xbc, 0xe7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } }
+
+typedef struct _EFI_CPU_ARCH_PROTOCOL EFI_CPU_ARCH_PROTOCOL;
+
+///
+/// The type of flush operation
+///
+typedef enum {
+ EfiCpuFlushTypeWriteBackInvalidate,
+ EfiCpuFlushTypeWriteBack,
+ EfiCpuFlushTypeInvalidate,
+ EfiCpuMaxFlushType
+} EFI_CPU_FLUSH_TYPE;
+
+///
+/// The type of processor INIT.
+///
+typedef enum {
+ EfiCpuInit,
+ EfiCpuMaxInitType
+} EFI_CPU_INIT_TYPE;
+
+/**
+ EFI_CPU_INTERRUPT_HANDLER that is called when a processor interrupt occurs.
+
+ @param InterruptType Defines the type of interrupt or exception that
+ occurred on the processor.This parameter is processor architecture specific.
+ @param SystemContext A pointer to the processor context when
+ the interrupt occurred on the processor.
+
+ @return None
+
+**/
+typedef
+VOID
+(EFIAPI *EFI_CPU_INTERRUPT_HANDLER)(
+ IN CONST EFI_EXCEPTION_TYPE InterruptType,
+ IN CONST EFI_SYSTEM_CONTEXT SystemContext
+ );
+
+/**
+ This function flushes the range of addresses from Start to Start+Length
+ from the processor's data cache. If Start is not aligned to a cache line
+ boundary, then the bytes before Start to the preceding cache line boundary
+ are also flushed. If Start+Length is not aligned to a cache line boundary,
+ then the bytes past Start+Length to the end of the next cache line boundary
+ are also flushed. The FlushType of EfiCpuFlushTypeWriteBackInvalidate must be
+ supported. If the data cache is fully coherent with all DMA operations, then
+ this function can just return EFI_SUCCESS. If the processor does not support
+ flushing a range of the data cache, then the entire data cache can be flushed.
+
+ @param This The EFI_CPU_ARCH_PROTOCOL instance.
+ @param Start The beginning physical address to flush from the processor's data
+ cache.
+ @param Length The number of bytes to flush from the processor's data cache. This
+ function may flush more bytes than Length specifies depending upon
+ the granularity of the flush operation that the processor supports.
+ @param FlushType Specifies the type of flush operation to perform.
+
+ @retval EFI_SUCCESS The address range from Start to Start+Length was flushed from
+ the processor's data cache.
+ @retval EFI_UNSUPPORTED The processor does not support the cache flush type specified
+ by FlushType.
+ @retval EFI_DEVICE_ERROR The address range from Start to Start+Length could not be flushed
+ from the processor's data cache.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_CPU_FLUSH_DATA_CACHE)(
+ IN EFI_CPU_ARCH_PROTOCOL *This,
+ IN EFI_PHYSICAL_ADDRESS Start,
+ IN UINT64 Length,
+ IN EFI_CPU_FLUSH_TYPE FlushType
+ );
+
+/**
+ This function enables interrupt processing by the processor.
+
+ @param This The EFI_CPU_ARCH_PROTOCOL instance.
+
+ @retval EFI_SUCCESS Interrupts are enabled on the processor.
+ @retval EFI_DEVICE_ERROR Interrupts could not be enabled on the processor.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_CPU_ENABLE_INTERRUPT)(
+ IN EFI_CPU_ARCH_PROTOCOL *This
+ );
+
+/**
+ This function disables interrupt processing by the processor.
+
+ @param This The EFI_CPU_ARCH_PROTOCOL instance.
+
+ @retval EFI_SUCCESS Interrupts are disabled on the processor.
+ @retval EFI_DEVICE_ERROR Interrupts could not be disabled on the processor.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_CPU_DISABLE_INTERRUPT)(
+ IN EFI_CPU_ARCH_PROTOCOL *This
+ );
+
+/**
+ This function retrieves the processor's current interrupt state a returns it in
+ State. If interrupts are currently enabled, then TRUE is returned. If interrupts
+ are currently disabled, then FALSE is returned.
+
+ @param This The EFI_CPU_ARCH_PROTOCOL instance.
+ @param State A pointer to the processor's current interrupt state. Set to TRUE if
+ interrupts are enabled and FALSE if interrupts are disabled.
+
+ @retval EFI_SUCCESS The processor's current interrupt state was returned in State.
+ @retval EFI_INVALID_PARAMETER State is NULL.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_CPU_GET_INTERRUPT_STATE)(
+ IN EFI_CPU_ARCH_PROTOCOL *This,
+ OUT BOOLEAN *State
+ );
+
+/**
+ This function generates an INIT on the processor. If this function succeeds, then the
+ processor will be reset, and control will not be returned to the caller. If InitType is
+ not supported by this processor, or the processor cannot programmatically generate an
+ INIT without help from external hardware, then EFI_UNSUPPORTED is returned. If an error
+ occurs attempting to generate an INIT, then EFI_DEVICE_ERROR is returned.
+
+ @param This The EFI_CPU_ARCH_PROTOCOL instance.
+ @param InitType The type of processor INIT to perform.
+
+ @retval EFI_SUCCESS The processor INIT was performed. This return code should never be seen.
+ @retval EFI_UNSUPPORTED The processor INIT operation specified by InitType is not supported
+ by this processor.
+ @retval EFI_DEVICE_ERROR The processor INIT failed.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_CPU_INIT)(
+ IN EFI_CPU_ARCH_PROTOCOL *This,
+ IN EFI_CPU_INIT_TYPE InitType
+ );
+
+/**
+ This function registers and enables the handler specified by InterruptHandler for a processor
+ interrupt or exception type specified by InterruptType. If InterruptHandler is NULL, then the
+ handler for the processor interrupt or exception type specified by InterruptType is uninstalled.
+ The installed handler is called once for each processor interrupt or exception.
+
+ @param This The EFI_CPU_ARCH_PROTOCOL instance.
+ @param InterruptType A pointer to the processor's current interrupt state. Set to TRUE if interrupts
+ are enabled and FALSE if interrupts are disabled.
+ @param InterruptHandler A pointer to a function of type EFI_CPU_INTERRUPT_HANDLER that is called
+ when a processor interrupt occurs. If this parameter is NULL, then the handler
+ will be uninstalled.
+
+ @retval EFI_SUCCESS The handler for the processor interrupt was successfully installed or uninstalled.
+ @retval EFI_ALREADY_STARTED InterruptHandler is not NULL, and a handler for InterruptType was
+ previously installed.
+ @retval EFI_INVALID_PARAMETER InterruptHandler is NULL, and a handler for InterruptType was not
+ previously installed.
+ @retval EFI_UNSUPPORTED The interrupt specified by InterruptType is not supported.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_CPU_REGISTER_INTERRUPT_HANDLER)(
+ IN EFI_CPU_ARCH_PROTOCOL *This,
+ IN EFI_EXCEPTION_TYPE InterruptType,
+ IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler
+ );
+
+/**
+ This function reads the processor timer specified by TimerIndex and returns it in TimerValue.
+
+ @param This The EFI_CPU_ARCH_PROTOCOL instance.
+ @param TimerIndex Specifies which processor timer is to be returned in TimerValue. This parameter
+ must be between 0 and NumberOfTimers-1.
+ @param TimerValue Pointer to the returned timer value.
+ @param TimerPeriod A pointer to the amount of time that passes in femtoseconds for each increment
+ of TimerValue. If TimerValue does not increment at a predictable rate, then 0 is
+ returned. This parameter is optional and may be NULL.
+
+ @retval EFI_SUCCESS The processor timer value specified by TimerIndex was returned in TimerValue.
+ @retval EFI_DEVICE_ERROR An error occurred attempting to read one of the processor's timers.
+ @retval EFI_INVALID_PARAMETER TimerValue is NULL or TimerIndex is not valid.
+ @retval EFI_UNSUPPORTED The processor does not have any readable timers.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_CPU_GET_TIMER_VALUE)(
+ IN EFI_CPU_ARCH_PROTOCOL *This,
+ IN UINT32 TimerIndex,
+ OUT UINT64 *TimerValue,
+ OUT UINT64 *TimerPeriod OPTIONAL
+ );
+
+/**
+ This function modifies the attributes for the memory region specified by BaseAddress and
+ Length from their current attributes to the attributes specified by Attributes.
+
+ @param This The EFI_CPU_ARCH_PROTOCOL instance.
+ @param BaseAddress The physical address that is the start address of a memory region.
+ @param Length The size in bytes of the memory region.
+ @param Attributes The bit mask of attributes to set for the memory region.
+
+ @retval EFI_SUCCESS The attributes were set for the memory region.
+ @retval EFI_ACCESS_DENIED The attributes for the memory resource range specified by
+ BaseAddress and Length cannot be modified.
+ @retval EFI_INVALID_PARAMETER Length is zero.
+ Attributes specified an illegal combination of attributes that
+ cannot be set together.
+ @retval EFI_OUT_OF_RESOURCES There are not enough system resources to modify the attributes of
+ the memory resource range.
+ @retval EFI_UNSUPPORTED The processor does not support one or more bytes of the memory
+ resource range specified by BaseAddress and Length.
+ The bit mask of attributes is not support for the memory resource
+ range specified by BaseAddress and Length.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_CPU_SET_MEMORY_ATTRIBUTES)(
+ IN EFI_CPU_ARCH_PROTOCOL *This,
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,
+ IN UINT64 Length,
+ IN UINT64 Attributes
+ );
+
+///
+/// The EFI_CPU_ARCH_PROTOCOL is used to abstract processor-specific functions from the DXE
+/// Foundation. This includes flushing caches, enabling and disabling interrupts, hooking interrupt
+/// vectors and exception vectors, reading internal processor timers, resetting the processor, and
+/// determining the processor frequency.
+///
+struct _EFI_CPU_ARCH_PROTOCOL {
+ EFI_CPU_FLUSH_DATA_CACHE FlushDataCache;
+ EFI_CPU_ENABLE_INTERRUPT EnableInterrupt;
+ EFI_CPU_DISABLE_INTERRUPT DisableInterrupt;
+ EFI_CPU_GET_INTERRUPT_STATE GetInterruptState;
+ EFI_CPU_INIT Init;
+ EFI_CPU_REGISTER_INTERRUPT_HANDLER RegisterInterruptHandler;
+ EFI_CPU_GET_TIMER_VALUE GetTimerValue;
+ EFI_CPU_SET_MEMORY_ATTRIBUTES SetMemoryAttributes;
+ ///
+ /// The number of timers that are available in a processor. The value in this
+ /// field is a constant that must not be modified after the CPU Architectural
+ /// Protocol is installed. All consumers must treat this as a read-only field.
+ ///
+ UINT32 NumberOfTimers;
+ ///
+ /// The size, in bytes, of the alignment required for DMA buffer allocations.
+ /// This is typically the size of the largest data cache line in the platform.
+ /// The value in this field is a constant that must not be modified after the
+ /// CPU Architectural Protocol is installed. All consumers must treat this as
+ /// a read-only field.
+ ///
+ UINT32 DmaBufferAlignment;
+};
+
+extern EFI_GUID gEfiCpuArchProtocolGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/CpuIo2.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/CpuIo2.h
new file mode 100644
index 0000000000..fc8a3511d1
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/CpuIo2.h
@@ -0,0 +1,136 @@
+/** @file
+ This files describes the CPU I/O 2 Protocol.
+
+ This protocol provides an I/O abstraction for a system processor. This protocol
+ is used by a PCI root bridge I/O driver to perform memory-mapped I/O and I/O transactions.
+ The I/O or memory primitives can be used by the consumer of the protocol to materialize
+ bus-specific configuration cycles, such as the transitional configuration address and data
+ ports for PCI. Only drivers that require direct access to the entire system should use this
+ protocol.
+
+ Note: This is a boot-services only protocol and it may not be used by runtime drivers after
+ ExitBootServices(). It is different from the Framework CPU I/O Protocol, which is a runtime
+ protocol and can be used by runtime drivers after ExitBootServices().
+
+ Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Revision Reference:
+ This Protocol is defined in UEFI Platform Initialization Specification 1.2
+ Volume 5: Standards
+
+**/
+
+#ifndef __CPU_IO2_H__
+#define __CPU_IO2_H__
+
+#define EFI_CPU_IO2_PROTOCOL_GUID \
+ { \
+ 0xad61f191, 0xae5f, 0x4c0e, {0xb9, 0xfa, 0xe8, 0x69, 0xd2, 0x88, 0xc6, 0x4f} \
+ }
+
+typedef struct _EFI_CPU_IO2_PROTOCOL EFI_CPU_IO2_PROTOCOL;
+
+///
+/// Enumeration that defines the width of the I/O operation.
+///
+typedef enum {
+ EfiCpuIoWidthUint8,
+ EfiCpuIoWidthUint16,
+ EfiCpuIoWidthUint32,
+ EfiCpuIoWidthUint64,
+ EfiCpuIoWidthFifoUint8,
+ EfiCpuIoWidthFifoUint16,
+ EfiCpuIoWidthFifoUint32,
+ EfiCpuIoWidthFifoUint64,
+ EfiCpuIoWidthFillUint8,
+ EfiCpuIoWidthFillUint16,
+ EfiCpuIoWidthFillUint32,
+ EfiCpuIoWidthFillUint64,
+ EfiCpuIoWidthMaximum
+} EFI_CPU_IO_PROTOCOL_WIDTH;
+
+/**
+ Enables a driver to access registers in the PI CPU I/O space.
+
+ The Io.Read() and Io.Write() functions enable a driver to access PCI controller
+ registers in the PI CPU I/O space.
+
+ The I/O operations are carried out exactly as requested. The caller is responsible
+ for satisfying any alignment and I/O width restrictions that a PI System on a
+ platform might require. For example on some platforms, width requests of
+ EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will
+ be handled by the driver.
+
+ If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32,
+ or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for
+ each of the Count operations that is performed.
+
+ If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16,
+ EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is
+ incremented for each of the Count operations that is performed. The read or
+ write operation is performed Count times on the same Address.
+
+ If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16,
+ EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is
+ incremented for each of the Count operations that is performed. The read or
+ write operation is performed Count times from the first element of Buffer.
+
+ @param[in] This A pointer to the EFI_CPU_IO2_PROTOCOL instance.
+ @param[in] Width Signifies the width of the I/O or Memory operation.
+ @param[in] Address The base address of the I/O operation.
+ @param[in] Count The number of I/O operations to perform. The number
+ of bytes moved is Width size * Count, starting at Address.
+ @param[in, out] Buffer For read operations, the destination buffer to store the results.
+ For write operations, the source buffer from which to write data.
+
+ @retval EFI_SUCCESS The data was read from or written to the PI system.
+ @retval EFI_INVALID_PARAMETER Width is invalid for this PI system.
+ @retval EFI_INVALID_PARAMETER Buffer is NULL.
+ @retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width.
+ @retval EFI_UNSUPPORTED The address range specified by Address, Width,
+ and Count is not valid for this PI system.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_CPU_IO_PROTOCOL_IO_MEM)(
+ IN EFI_CPU_IO2_PROTOCOL *This,
+ IN EFI_CPU_IO_PROTOCOL_WIDTH Width,
+ IN UINT64 Address,
+ IN UINTN Count,
+ IN OUT VOID *Buffer
+ );
+
+///
+/// Service for read and write accesses.
+///
+typedef struct {
+ ///
+ /// This service provides the various modalities of memory and I/O read.
+ ///
+ EFI_CPU_IO_PROTOCOL_IO_MEM Read;
+ ///
+ /// This service provides the various modalities of memory and I/O write.
+ ///
+ EFI_CPU_IO_PROTOCOL_IO_MEM Write;
+} EFI_CPU_IO_PROTOCOL_ACCESS;
+
+///
+/// Provides the basic memory and I/O interfaces that are used to abstract
+/// accesses to devices in a system.
+///
+struct _EFI_CPU_IO2_PROTOCOL {
+ ///
+ /// Enables a driver to access memory-mapped registers in the EFI system memory space.
+ ///
+ EFI_CPU_IO_PROTOCOL_ACCESS Mem;
+ ///
+ /// Enables a driver to access registers in the EFI CPU I/O space.
+ ///
+ EFI_CPU_IO_PROTOCOL_ACCESS Io;
+};
+
+extern EFI_GUID gEfiCpuIo2ProtocolGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/DebugPort.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/DebugPort.h
new file mode 100644
index 0000000000..d3eebb9912
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/DebugPort.h
@@ -0,0 +1,139 @@
+/** @file
+
+ The file defines the EFI Debugport protocol.
+ This protocol is used by debug agent to communicate with the
+ remote debug host.
+
+ Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __DEBUG_PORT_H__
+#define __DEBUG_PORT_H__
+
+///
+/// DebugPortIo protocol {EBA4E8D2-3858-41EC-A281-2647BA9660D0}
+///
+#define EFI_DEBUGPORT_PROTOCOL_GUID \
+ { \
+ 0xEBA4E8D2, 0x3858, 0x41EC, {0xA2, 0x81, 0x26, 0x47, 0xBA, 0x96, 0x60, 0xD0 } \
+ }
+
+extern EFI_GUID gEfiDebugPortProtocolGuid;
+
+typedef struct _EFI_DEBUGPORT_PROTOCOL EFI_DEBUGPORT_PROTOCOL;
+
+//
+// DebugPort member functions
+//
+
+/**
+ Resets the debugport.
+
+ @param This A pointer to the EFI_DEBUGPORT_PROTOCOL instance.
+
+ @retval EFI_SUCCESS The debugport device was reset and is in usable state.
+ @retval EFI_DEVICE_ERROR The debugport device could not be reset and is unusable.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_DEBUGPORT_RESET)(
+ IN EFI_DEBUGPORT_PROTOCOL *This
+ );
+
+/**
+ Writes data to the debugport.
+
+ @param This A pointer to the EFI_DEBUGPORT_PROTOCOL instance.
+ @param Timeout The number of microseconds to wait before timing out a write operation.
+ @param BufferSize On input, the requested number of bytes of data to write. On output, the
+ number of bytes of data actually written.
+ @param Buffer A pointer to a buffer containing the data to write.
+
+ @retval EFI_SUCCESS The data was written.
+ @retval EFI_DEVICE_ERROR The device reported an error.
+ @retval EFI_TIMEOUT The data write was stopped due to a timeout.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_DEBUGPORT_WRITE)(
+ IN EFI_DEBUGPORT_PROTOCOL *This,
+ IN UINT32 Timeout,
+ IN OUT UINTN *BufferSize,
+ IN VOID *Buffer
+ );
+
+/**
+ Reads data from the debugport.
+
+ @param This A pointer to the EFI_DEBUGPORT_PROTOCOL instance.
+ @param Timeout The number of microseconds to wait before timing out a read operation.
+ @param BufferSize On input, the requested number of bytes of data to read. On output, the
+ number of bytes of data actually number of bytes
+ of data read and returned in Buffer.
+ @param Buffer A pointer to a buffer into which the data read will be saved.
+
+ @retval EFI_SUCCESS The data was read.
+ @retval EFI_DEVICE_ERROR The device reported an error.
+ @retval EFI_TIMEOUT The operation was stopped due to a timeout or overrun.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_DEBUGPORT_READ)(
+ IN EFI_DEBUGPORT_PROTOCOL *This,
+ IN UINT32 Timeout,
+ IN OUT UINTN *BufferSize,
+ OUT VOID *Buffer
+ );
+
+/**
+ Checks to see if any data is available to be read from the debugport device.
+
+ @param This A pointer to the EFI_DEBUGPORT_PROTOCOL instance.
+
+ @retval EFI_SUCCESS At least one byte of data is available to be read.
+ @retval EFI_DEVICE_ERROR The debugport device is not functioning correctly.
+ @retval EFI_NOT_READY No data is available to be read.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_DEBUGPORT_POLL)(
+ IN EFI_DEBUGPORT_PROTOCOL *This
+ );
+
+///
+/// This protocol provides the communication link between the debug agent and the remote host.
+///
+struct _EFI_DEBUGPORT_PROTOCOL {
+ EFI_DEBUGPORT_RESET Reset;
+ EFI_DEBUGPORT_WRITE Write;
+ EFI_DEBUGPORT_READ Read;
+ EFI_DEBUGPORT_POLL Poll;
+};
+
+//
+// DEBUGPORT variable definitions...
+//
+#define EFI_DEBUGPORT_VARIABLE_NAME L"DEBUGPORT"
+#define EFI_DEBUGPORT_VARIABLE_GUID EFI_DEBUGPORT_PROTOCOL_GUID
+
+extern EFI_GUID gEfiDebugPortVariableGuid;
+
+//
+// DebugPort device path definitions...
+//
+#define DEVICE_PATH_MESSAGING_DEBUGPORT EFI_DEBUGPORT_PROTOCOL_GUID
+
+extern EFI_GUID gEfiDebugPortDevicePathGuid;
+
+typedef struct {
+ EFI_DEVICE_PATH_PROTOCOL Header;
+ EFI_GUID Guid;
+} DEBUGPORT_DEVICE_PATH;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/DebugSupport.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/DebugSupport.h
new file mode 100644
index 0000000000..61808c27fe
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/DebugSupport.h
@@ -0,0 +1,915 @@
+/** @file
+ DebugSupport protocol and supporting definitions as defined in the UEFI2.4
+ specification.
+
+ The DebugSupport protocol is used by source level debuggers to abstract the
+ processor and handle context save and restore operations.
+
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.
+Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.
+
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __DEBUG_SUPPORT_H__
+#define __DEBUG_SUPPORT_H__
+
+#include
+
+typedef struct _EFI_DEBUG_SUPPORT_PROTOCOL EFI_DEBUG_SUPPORT_PROTOCOL;
+
+///
+/// Debug Support protocol {2755590C-6F3C-42FA-9EA4-A3BA543CDA25}.
+///
+#define EFI_DEBUG_SUPPORT_PROTOCOL_GUID \
+ { \
+ 0x2755590C, 0x6F3C, 0x42FA, {0x9E, 0xA4, 0xA3, 0xBA, 0x54, 0x3C, 0xDA, 0x25 } \
+ }
+
+///
+/// Processor exception to be hooked.
+/// All exception types for IA32, X64, Itanium and EBC processors are defined.
+///
+typedef INTN EFI_EXCEPTION_TYPE;
+
+///
+/// IA-32 processor exception types.
+///
+#define EXCEPT_IA32_DIVIDE_ERROR 0
+#define EXCEPT_IA32_DEBUG 1
+#define EXCEPT_IA32_NMI 2
+#define EXCEPT_IA32_BREAKPOINT 3
+#define EXCEPT_IA32_OVERFLOW 4
+#define EXCEPT_IA32_BOUND 5
+#define EXCEPT_IA32_INVALID_OPCODE 6
+#define EXCEPT_IA32_DOUBLE_FAULT 8
+#define EXCEPT_IA32_INVALID_TSS 10
+#define EXCEPT_IA32_SEG_NOT_PRESENT 11
+#define EXCEPT_IA32_STACK_FAULT 12
+#define EXCEPT_IA32_GP_FAULT 13
+#define EXCEPT_IA32_PAGE_FAULT 14
+#define EXCEPT_IA32_FP_ERROR 16
+#define EXCEPT_IA32_ALIGNMENT_CHECK 17
+#define EXCEPT_IA32_MACHINE_CHECK 18
+#define EXCEPT_IA32_SIMD 19
+
+///
+/// FXSAVE_STATE.
+/// FP / MMX / XMM registers (see fxrstor instruction definition).
+///
+typedef struct {
+ UINT16 Fcw;
+ UINT16 Fsw;
+ UINT16 Ftw;
+ UINT16 Opcode;
+ UINT32 Eip;
+ UINT16 Cs;
+ UINT16 Reserved1;
+ UINT32 DataOffset;
+ UINT16 Ds;
+ UINT8 Reserved2[10];
+ UINT8 St0Mm0[10], Reserved3[6];
+ UINT8 St1Mm1[10], Reserved4[6];
+ UINT8 St2Mm2[10], Reserved5[6];
+ UINT8 St3Mm3[10], Reserved6[6];
+ UINT8 St4Mm4[10], Reserved7[6];
+ UINT8 St5Mm5[10], Reserved8[6];
+ UINT8 St6Mm6[10], Reserved9[6];
+ UINT8 St7Mm7[10], Reserved10[6];
+ UINT8 Xmm0[16];
+ UINT8 Xmm1[16];
+ UINT8 Xmm2[16];
+ UINT8 Xmm3[16];
+ UINT8 Xmm4[16];
+ UINT8 Xmm5[16];
+ UINT8 Xmm6[16];
+ UINT8 Xmm7[16];
+ UINT8 Reserved11[14 * 16];
+} EFI_FX_SAVE_STATE_IA32;
+
+///
+/// IA-32 processor context definition.
+///
+typedef struct {
+ UINT32 ExceptionData;
+ EFI_FX_SAVE_STATE_IA32 FxSaveState;
+ UINT32 Dr0;
+ UINT32 Dr1;
+ UINT32 Dr2;
+ UINT32 Dr3;
+ UINT32 Dr6;
+ UINT32 Dr7;
+ UINT32 Cr0;
+ UINT32 Cr1; /* Reserved */
+ UINT32 Cr2;
+ UINT32 Cr3;
+ UINT32 Cr4;
+ UINT32 Eflags;
+ UINT32 Ldtr;
+ UINT32 Tr;
+ UINT32 Gdtr[2];
+ UINT32 Idtr[2];
+ UINT32 Eip;
+ UINT32 Gs;
+ UINT32 Fs;
+ UINT32 Es;
+ UINT32 Ds;
+ UINT32 Cs;
+ UINT32 Ss;
+ UINT32 Edi;
+ UINT32 Esi;
+ UINT32 Ebp;
+ UINT32 Esp;
+ UINT32 Ebx;
+ UINT32 Edx;
+ UINT32 Ecx;
+ UINT32 Eax;
+} EFI_SYSTEM_CONTEXT_IA32;
+
+///
+/// x64 processor exception types.
+///
+#define EXCEPT_X64_DIVIDE_ERROR 0
+#define EXCEPT_X64_DEBUG 1
+#define EXCEPT_X64_NMI 2
+#define EXCEPT_X64_BREAKPOINT 3
+#define EXCEPT_X64_OVERFLOW 4
+#define EXCEPT_X64_BOUND 5
+#define EXCEPT_X64_INVALID_OPCODE 6
+#define EXCEPT_X64_DOUBLE_FAULT 8
+#define EXCEPT_X64_INVALID_TSS 10
+#define EXCEPT_X64_SEG_NOT_PRESENT 11
+#define EXCEPT_X64_STACK_FAULT 12
+#define EXCEPT_X64_GP_FAULT 13
+#define EXCEPT_X64_PAGE_FAULT 14
+#define EXCEPT_X64_FP_ERROR 16
+#define EXCEPT_X64_ALIGNMENT_CHECK 17
+#define EXCEPT_X64_MACHINE_CHECK 18
+#define EXCEPT_X64_SIMD 19
+
+///
+/// FXSAVE_STATE.
+/// FP / MMX / XMM registers (see fxrstor instruction definition).
+///
+typedef struct {
+ UINT16 Fcw;
+ UINT16 Fsw;
+ UINT16 Ftw;
+ UINT16 Opcode;
+ UINT64 Rip;
+ UINT64 DataOffset;
+ UINT8 Reserved1[8];
+ UINT8 St0Mm0[10], Reserved2[6];
+ UINT8 St1Mm1[10], Reserved3[6];
+ UINT8 St2Mm2[10], Reserved4[6];
+ UINT8 St3Mm3[10], Reserved5[6];
+ UINT8 St4Mm4[10], Reserved6[6];
+ UINT8 St5Mm5[10], Reserved7[6];
+ UINT8 St6Mm6[10], Reserved8[6];
+ UINT8 St7Mm7[10], Reserved9[6];
+ UINT8 Xmm0[16];
+ UINT8 Xmm1[16];
+ UINT8 Xmm2[16];
+ UINT8 Xmm3[16];
+ UINT8 Xmm4[16];
+ UINT8 Xmm5[16];
+ UINT8 Xmm6[16];
+ UINT8 Xmm7[16];
+ //
+ // NOTE: UEFI 2.0 spec definition as follows.
+ //
+ UINT8 Reserved11[14 * 16];
+} EFI_FX_SAVE_STATE_X64;
+
+///
+/// x64 processor context definition.
+///
+typedef struct {
+ UINT64 ExceptionData;
+ EFI_FX_SAVE_STATE_X64 FxSaveState;
+ UINT64 Dr0;
+ UINT64 Dr1;
+ UINT64 Dr2;
+ UINT64 Dr3;
+ UINT64 Dr6;
+ UINT64 Dr7;
+ UINT64 Cr0;
+ UINT64 Cr1; /* Reserved */
+ UINT64 Cr2;
+ UINT64 Cr3;
+ UINT64 Cr4;
+ UINT64 Cr8;
+ UINT64 Rflags;
+ UINT64 Ldtr;
+ UINT64 Tr;
+ UINT64 Gdtr[2];
+ UINT64 Idtr[2];
+ UINT64 Rip;
+ UINT64 Gs;
+ UINT64 Fs;
+ UINT64 Es;
+ UINT64 Ds;
+ UINT64 Cs;
+ UINT64 Ss;
+ UINT64 Rdi;
+ UINT64 Rsi;
+ UINT64 Rbp;
+ UINT64 Rsp;
+ UINT64 Rbx;
+ UINT64 Rdx;
+ UINT64 Rcx;
+ UINT64 Rax;
+ UINT64 R8;
+ UINT64 R9;
+ UINT64 R10;
+ UINT64 R11;
+ UINT64 R12;
+ UINT64 R13;
+ UINT64 R14;
+ UINT64 R15;
+} EFI_SYSTEM_CONTEXT_X64;
+
+///
+/// Itanium Processor Family Exception types.
+///
+#define EXCEPT_IPF_VHTP_TRANSLATION 0
+#define EXCEPT_IPF_INSTRUCTION_TLB 1
+#define EXCEPT_IPF_DATA_TLB 2
+#define EXCEPT_IPF_ALT_INSTRUCTION_TLB 3
+#define EXCEPT_IPF_ALT_DATA_TLB 4
+#define EXCEPT_IPF_DATA_NESTED_TLB 5
+#define EXCEPT_IPF_INSTRUCTION_KEY_MISSED 6
+#define EXCEPT_IPF_DATA_KEY_MISSED 7
+#define EXCEPT_IPF_DIRTY_BIT 8
+#define EXCEPT_IPF_INSTRUCTION_ACCESS_BIT 9
+#define EXCEPT_IPF_DATA_ACCESS_BIT 10
+#define EXCEPT_IPF_BREAKPOINT 11
+#define EXCEPT_IPF_EXTERNAL_INTERRUPT 12
+//
+// 13 - 19 reserved
+//
+#define EXCEPT_IPF_PAGE_NOT_PRESENT 20
+#define EXCEPT_IPF_KEY_PERMISSION 21
+#define EXCEPT_IPF_INSTRUCTION_ACCESS_RIGHTS 22
+#define EXCEPT_IPF_DATA_ACCESS_RIGHTS 23
+#define EXCEPT_IPF_GENERAL_EXCEPTION 24
+#define EXCEPT_IPF_DISABLED_FP_REGISTER 25
+#define EXCEPT_IPF_NAT_CONSUMPTION 26
+#define EXCEPT_IPF_SPECULATION 27
+//
+// 28 reserved
+//
+#define EXCEPT_IPF_DEBUG 29
+#define EXCEPT_IPF_UNALIGNED_REFERENCE 30
+#define EXCEPT_IPF_UNSUPPORTED_DATA_REFERENCE 31
+#define EXCEPT_IPF_FP_FAULT 32
+#define EXCEPT_IPF_FP_TRAP 33
+#define EXCEPT_IPF_LOWER_PRIVILEGE_TRANSFER_TRAP 34
+#define EXCEPT_IPF_TAKEN_BRANCH 35
+#define EXCEPT_IPF_SINGLE_STEP 36
+//
+// 37 - 44 reserved
+//
+#define EXCEPT_IPF_IA32_EXCEPTION 45
+#define EXCEPT_IPF_IA32_INTERCEPT 46
+#define EXCEPT_IPF_IA32_INTERRUPT 47
+
+///
+/// IPF processor context definition.
+///
+typedef struct {
+ //
+ // The first reserved field is necessary to preserve alignment for the correct
+ // bits in UNAT and to insure F2 is 16 byte aligned.
+ //
+ UINT64 Reserved;
+ UINT64 R1;
+ UINT64 R2;
+ UINT64 R3;
+ UINT64 R4;
+ UINT64 R5;
+ UINT64 R6;
+ UINT64 R7;
+ UINT64 R8;
+ UINT64 R9;
+ UINT64 R10;
+ UINT64 R11;
+ UINT64 R12;
+ UINT64 R13;
+ UINT64 R14;
+ UINT64 R15;
+ UINT64 R16;
+ UINT64 R17;
+ UINT64 R18;
+ UINT64 R19;
+ UINT64 R20;
+ UINT64 R21;
+ UINT64 R22;
+ UINT64 R23;
+ UINT64 R24;
+ UINT64 R25;
+ UINT64 R26;
+ UINT64 R27;
+ UINT64 R28;
+ UINT64 R29;
+ UINT64 R30;
+ UINT64 R31;
+
+ UINT64 F2[2];
+ UINT64 F3[2];
+ UINT64 F4[2];
+ UINT64 F5[2];
+ UINT64 F6[2];
+ UINT64 F7[2];
+ UINT64 F8[2];
+ UINT64 F9[2];
+ UINT64 F10[2];
+ UINT64 F11[2];
+ UINT64 F12[2];
+ UINT64 F13[2];
+ UINT64 F14[2];
+ UINT64 F15[2];
+ UINT64 F16[2];
+ UINT64 F17[2];
+ UINT64 F18[2];
+ UINT64 F19[2];
+ UINT64 F20[2];
+ UINT64 F21[2];
+ UINT64 F22[2];
+ UINT64 F23[2];
+ UINT64 F24[2];
+ UINT64 F25[2];
+ UINT64 F26[2];
+ UINT64 F27[2];
+ UINT64 F28[2];
+ UINT64 F29[2];
+ UINT64 F30[2];
+ UINT64 F31[2];
+
+ UINT64 Pr;
+
+ UINT64 B0;
+ UINT64 B1;
+ UINT64 B2;
+ UINT64 B3;
+ UINT64 B4;
+ UINT64 B5;
+ UINT64 B6;
+ UINT64 B7;
+
+ //
+ // application registers
+ //
+ UINT64 ArRsc;
+ UINT64 ArBsp;
+ UINT64 ArBspstore;
+ UINT64 ArRnat;
+
+ UINT64 ArFcr;
+
+ UINT64 ArEflag;
+ UINT64 ArCsd;
+ UINT64 ArSsd;
+ UINT64 ArCflg;
+ UINT64 ArFsr;
+ UINT64 ArFir;
+ UINT64 ArFdr;
+
+ UINT64 ArCcv;
+
+ UINT64 ArUnat;
+
+ UINT64 ArFpsr;
+
+ UINT64 ArPfs;
+ UINT64 ArLc;
+ UINT64 ArEc;
+
+ //
+ // control registers
+ //
+ UINT64 CrDcr;
+ UINT64 CrItm;
+ UINT64 CrIva;
+ UINT64 CrPta;
+ UINT64 CrIpsr;
+ UINT64 CrIsr;
+ UINT64 CrIip;
+ UINT64 CrIfa;
+ UINT64 CrItir;
+ UINT64 CrIipa;
+ UINT64 CrIfs;
+ UINT64 CrIim;
+ UINT64 CrIha;
+
+ //
+ // debug registers
+ //
+ UINT64 Dbr0;
+ UINT64 Dbr1;
+ UINT64 Dbr2;
+ UINT64 Dbr3;
+ UINT64 Dbr4;
+ UINT64 Dbr5;
+ UINT64 Dbr6;
+ UINT64 Dbr7;
+
+ UINT64 Ibr0;
+ UINT64 Ibr1;
+ UINT64 Ibr2;
+ UINT64 Ibr3;
+ UINT64 Ibr4;
+ UINT64 Ibr5;
+ UINT64 Ibr6;
+ UINT64 Ibr7;
+
+ //
+ // virtual registers - nat bits for R1-R31
+ //
+ UINT64 IntNat;
+} EFI_SYSTEM_CONTEXT_IPF;
+
+///
+/// EBC processor exception types.
+///
+#define EXCEPT_EBC_UNDEFINED 0
+#define EXCEPT_EBC_DIVIDE_ERROR 1
+#define EXCEPT_EBC_DEBUG 2
+#define EXCEPT_EBC_BREAKPOINT 3
+#define EXCEPT_EBC_OVERFLOW 4
+#define EXCEPT_EBC_INVALID_OPCODE 5 ///< Opcode out of range.
+#define EXCEPT_EBC_STACK_FAULT 6
+#define EXCEPT_EBC_ALIGNMENT_CHECK 7
+#define EXCEPT_EBC_INSTRUCTION_ENCODING 8 ///< Malformed instruction.
+#define EXCEPT_EBC_BAD_BREAK 9 ///< BREAK 0 or undefined BREAK.
+#define EXCEPT_EBC_STEP 10 ///< To support debug stepping.
+///
+/// For coding convenience, define the maximum valid EBC exception.
+///
+#define MAX_EBC_EXCEPTION EXCEPT_EBC_STEP
+
+///
+/// EBC processor context definition.
+///
+typedef struct {
+ UINT64 R0;
+ UINT64 R1;
+ UINT64 R2;
+ UINT64 R3;
+ UINT64 R4;
+ UINT64 R5;
+ UINT64 R6;
+ UINT64 R7;
+ UINT64 Flags;
+ UINT64 ControlFlags;
+ UINT64 Ip;
+} EFI_SYSTEM_CONTEXT_EBC;
+
+///
+/// ARM processor exception types.
+///
+#define EXCEPT_ARM_RESET 0
+#define EXCEPT_ARM_UNDEFINED_INSTRUCTION 1
+#define EXCEPT_ARM_SOFTWARE_INTERRUPT 2
+#define EXCEPT_ARM_PREFETCH_ABORT 3
+#define EXCEPT_ARM_DATA_ABORT 4
+#define EXCEPT_ARM_RESERVED 5
+#define EXCEPT_ARM_IRQ 6
+#define EXCEPT_ARM_FIQ 7
+
+///
+/// For coding convenience, define the maximum valid ARM exception.
+///
+#define MAX_ARM_EXCEPTION EXCEPT_ARM_FIQ
+
+///
+/// ARM processor context definition.
+///
+typedef struct {
+ UINT32 R0;
+ UINT32 R1;
+ UINT32 R2;
+ UINT32 R3;
+ UINT32 R4;
+ UINT32 R5;
+ UINT32 R6;
+ UINT32 R7;
+ UINT32 R8;
+ UINT32 R9;
+ UINT32 R10;
+ UINT32 R11;
+ UINT32 R12;
+ UINT32 SP;
+ UINT32 LR;
+ UINT32 PC;
+ UINT32 CPSR;
+ UINT32 DFSR;
+ UINT32 DFAR;
+ UINT32 IFSR;
+ UINT32 IFAR;
+} EFI_SYSTEM_CONTEXT_ARM;
+
+///
+/// AARCH64 processor exception types.
+///
+#define EXCEPT_AARCH64_SYNCHRONOUS_EXCEPTIONS 0
+#define EXCEPT_AARCH64_IRQ 1
+#define EXCEPT_AARCH64_FIQ 2
+#define EXCEPT_AARCH64_SERROR 3
+
+///
+/// For coding convenience, define the maximum valid ARM exception.
+///
+#define MAX_AARCH64_EXCEPTION EXCEPT_AARCH64_SERROR
+
+typedef struct {
+ // General Purpose Registers
+ UINT64 X0;
+ UINT64 X1;
+ UINT64 X2;
+ UINT64 X3;
+ UINT64 X4;
+ UINT64 X5;
+ UINT64 X6;
+ UINT64 X7;
+ UINT64 X8;
+ UINT64 X9;
+ UINT64 X10;
+ UINT64 X11;
+ UINT64 X12;
+ UINT64 X13;
+ UINT64 X14;
+ UINT64 X15;
+ UINT64 X16;
+ UINT64 X17;
+ UINT64 X18;
+ UINT64 X19;
+ UINT64 X20;
+ UINT64 X21;
+ UINT64 X22;
+ UINT64 X23;
+ UINT64 X24;
+ UINT64 X25;
+ UINT64 X26;
+ UINT64 X27;
+ UINT64 X28;
+ UINT64 FP; // x29 - Frame pointer
+ UINT64 LR; // x30 - Link Register
+ UINT64 SP; // x31 - Stack pointer
+
+ // FP/SIMD Registers
+ UINT64 V0[2];
+ UINT64 V1[2];
+ UINT64 V2[2];
+ UINT64 V3[2];
+ UINT64 V4[2];
+ UINT64 V5[2];
+ UINT64 V6[2];
+ UINT64 V7[2];
+ UINT64 V8[2];
+ UINT64 V9[2];
+ UINT64 V10[2];
+ UINT64 V11[2];
+ UINT64 V12[2];
+ UINT64 V13[2];
+ UINT64 V14[2];
+ UINT64 V15[2];
+ UINT64 V16[2];
+ UINT64 V17[2];
+ UINT64 V18[2];
+ UINT64 V19[2];
+ UINT64 V20[2];
+ UINT64 V21[2];
+ UINT64 V22[2];
+ UINT64 V23[2];
+ UINT64 V24[2];
+ UINT64 V25[2];
+ UINT64 V26[2];
+ UINT64 V27[2];
+ UINT64 V28[2];
+ UINT64 V29[2];
+ UINT64 V30[2];
+ UINT64 V31[2];
+
+ UINT64 ELR; // Exception Link Register
+ UINT64 SPSR; // Saved Processor Status Register
+ UINT64 FPSR; // Floating Point Status Register
+ UINT64 ESR; // Exception syndrome register
+ UINT64 FAR; // Fault Address Register
+} EFI_SYSTEM_CONTEXT_AARCH64;
+
+///
+/// RISC-V processor exception types.
+///
+#define EXCEPT_RISCV_INST_MISALIGNED 0
+#define EXCEPT_RISCV_INST_ACCESS_FAULT 1
+#define EXCEPT_RISCV_ILLEGAL_INST 2
+#define EXCEPT_RISCV_BREAKPOINT 3
+#define EXCEPT_RISCV_LOAD_ADDRESS_MISALIGNED 4
+#define EXCEPT_RISCV_LOAD_ACCESS_FAULT 5
+#define EXCEPT_RISCV_STORE_AMO_ADDRESS_MISALIGNED 6
+#define EXCEPT_RISCV_STORE_AMO_ACCESS_FAULT 7
+#define EXCEPT_RISCV_ENV_CALL_FROM_UMODE 8
+#define EXCEPT_RISCV_ENV_CALL_FROM_SMODE 9
+#define EXCEPT_RISCV_ENV_CALL_FROM_HMODE 10
+#define EXCEPT_RISCV_ENV_CALL_FROM_MMODE 11
+
+#define EXCEPT_RISCV_SOFTWARE_INT 0x0
+#define EXCEPT_RISCV_TIMER_INT 0x1
+
+typedef struct {
+ UINT64 X0;
+ UINT64 X1;
+ UINT64 X2;
+ UINT64 X3;
+ UINT64 X4;
+ UINT64 X5;
+ UINT64 X6;
+ UINT64 X7;
+ UINT64 X8;
+ UINT64 X9;
+ UINT64 X10;
+ UINT64 X11;
+ UINT64 X12;
+ UINT64 X13;
+ UINT64 X14;
+ UINT64 X15;
+ UINT64 X16;
+ UINT64 X17;
+ UINT64 X18;
+ UINT64 X19;
+ UINT64 X20;
+ UINT64 X21;
+ UINT64 X22;
+ UINT64 X23;
+ UINT64 X24;
+ UINT64 X25;
+ UINT64 X26;
+ UINT64 X27;
+ UINT64 X28;
+ UINT64 X29;
+ UINT64 X30;
+ UINT64 X31;
+} EFI_SYSTEM_CONTEXT_RISCV64;
+
+//
+// LoongArch processor exception types.
+//
+#define EXCEPT_LOONGARCH_INT 0
+#define EXCEPT_LOONGARCH_PIL 1
+#define EXCEPT_LOONGARCH_PIS 2
+#define EXCEPT_LOONGARCH_PIF 3
+#define EXCEPT_LOONGARCH_PME 4
+#define EXCEPT_LOONGARCH_PNR 5
+#define EXCEPT_LOONGARCH_PNX 6
+#define EXCEPT_LOONGARCH_PPI 7
+#define EXCEPT_LOONGARCH_ADE 8
+#define EXCEPT_LOONGARCH_ALE 9
+#define EXCEPT_LOONGARCH_BCE 10
+#define EXCEPT_LOONGARCH_SYS 11
+#define EXCEPT_LOONGARCH_BRK 12
+#define EXCEPT_LOONGARCH_INE 13
+#define EXCEPT_LOONGARCH_IPE 14
+#define EXCEPT_LOONGARCH_FPD 15
+#define EXCEPT_LOONGARCH_SXD 16
+#define EXCEPT_LOONGARCH_ASXD 17
+#define EXCEPT_LOONGARCH_FPE 18
+#define EXCEPT_LOONGARCH_TBR 64 // For code only, there is no such type in the ISA spec, the TLB refill is defined for an independent exception.
+
+//
+// LoongArch processor Interrupt types.
+//
+#define EXCEPT_LOONGARCH_INT_SIP0 0
+#define EXCEPT_LOONGARCH_INT_SIP1 1
+#define EXCEPT_LOONGARCH_INT_IP0 2
+#define EXCEPT_LOONGARCH_INT_IP1 3
+#define EXCEPT_LOONGARCH_INT_IP2 4
+#define EXCEPT_LOONGARCH_INT_IP3 5
+#define EXCEPT_LOONGARCH_INT_IP4 6
+#define EXCEPT_LOONGARCH_INT_IP5 7
+#define EXCEPT_LOONGARCH_INT_IP6 8
+#define EXCEPT_LOONGARCH_INT_IP7 9
+#define EXCEPT_LOONGARCH_INT_PMC 10
+#define EXCEPT_LOONGARCH_INT_TIMER 11
+#define EXCEPT_LOONGARCH_INT_IPI 12
+
+//
+// For coding convenience, define the maximum valid
+// LoongArch interrupt.
+//
+#define MAX_LOONGARCH_INTERRUPT 14
+
+typedef struct {
+ UINT64 R0;
+ UINT64 R1;
+ UINT64 R2;
+ UINT64 R3;
+ UINT64 R4;
+ UINT64 R5;
+ UINT64 R6;
+ UINT64 R7;
+ UINT64 R8;
+ UINT64 R9;
+ UINT64 R10;
+ UINT64 R11;
+ UINT64 R12;
+ UINT64 R13;
+ UINT64 R14;
+ UINT64 R15;
+ UINT64 R16;
+ UINT64 R17;
+ UINT64 R18;
+ UINT64 R19;
+ UINT64 R20;
+ UINT64 R21;
+ UINT64 R22;
+ UINT64 R23;
+ UINT64 R24;
+ UINT64 R25;
+ UINT64 R26;
+ UINT64 R27;
+ UINT64 R28;
+ UINT64 R29;
+ UINT64 R30;
+ UINT64 R31;
+
+ UINT64 CRMD; // CuRrent MoDe information
+ UINT64 PRMD; // PRe-exception MoDe information
+ UINT64 EUEN; // Extended component Unit ENable
+ UINT64 MISC; // MISCellaneous controller
+ UINT64 ECFG; // Exception ConFiGuration
+ UINT64 ESTAT; // Exception STATus
+ UINT64 ERA; // Exception Return Address
+ UINT64 BADV; // BAD Virtual address
+ UINT64 BADI; // BAD Instruction
+} EFI_SYSTEM_CONTEXT_LOONGARCH64;
+
+///
+/// Universal EFI_SYSTEM_CONTEXT definition.
+///
+typedef union {
+ EFI_SYSTEM_CONTEXT_EBC *SystemContextEbc;
+ EFI_SYSTEM_CONTEXT_IA32 *SystemContextIa32;
+ EFI_SYSTEM_CONTEXT_X64 *SystemContextX64;
+ EFI_SYSTEM_CONTEXT_IPF *SystemContextIpf;
+ EFI_SYSTEM_CONTEXT_ARM *SystemContextArm;
+ EFI_SYSTEM_CONTEXT_AARCH64 *SystemContextAArch64;
+ EFI_SYSTEM_CONTEXT_RISCV64 *SystemContextRiscV64;
+ EFI_SYSTEM_CONTEXT_LOONGARCH64 *SystemContextLoongArch64;
+} EFI_SYSTEM_CONTEXT;
+
+//
+// DebugSupport callback function prototypes
+//
+
+/**
+ Registers and enables an exception callback function for the specified exception.
+
+ @param ExceptionType Exception types in EBC, IA-32, x64, or IPF.
+ @param SystemContext Exception content.
+
+**/
+typedef
+VOID
+(EFIAPI *EFI_EXCEPTION_CALLBACK)(
+ IN EFI_EXCEPTION_TYPE ExceptionType,
+ IN OUT EFI_SYSTEM_CONTEXT SystemContext
+ );
+
+/**
+ Registers and enables the on-target debug agent's periodic entry point.
+
+ @param SystemContext Exception content.
+
+**/
+typedef
+VOID
+(EFIAPI *EFI_PERIODIC_CALLBACK)(
+ IN OUT EFI_SYSTEM_CONTEXT SystemContext
+ );
+
+///
+/// Machine type definition
+///
+typedef enum {
+ IsaIa32 = IMAGE_FILE_MACHINE_I386, ///< 0x014C
+ IsaX64 = IMAGE_FILE_MACHINE_X64, ///< 0x8664
+ IsaIpf = IMAGE_FILE_MACHINE_IA64, ///< 0x0200
+ IsaEbc = IMAGE_FILE_MACHINE_EBC, ///< 0x0EBC
+ IsaArm = IMAGE_FILE_MACHINE_ARMTHUMB_MIXED, ///< 0x01c2
+ IsaAArch64 = IMAGE_FILE_MACHINE_ARM64 ///< 0xAA64
+} EFI_INSTRUCTION_SET_ARCHITECTURE;
+
+//
+// DebugSupport member function definitions
+//
+
+/**
+ Returns the maximum value that may be used for the ProcessorIndex parameter in
+ RegisterPeriodicCallback() and RegisterExceptionCallback().
+
+ @param This A pointer to the EFI_DEBUG_SUPPORT_PROTOCOL instance.
+ @param MaxProcessorIndex Pointer to a caller-allocated UINTN in which the maximum supported
+ processor index is returned.
+
+ @retval EFI_SUCCESS The function completed successfully.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_GET_MAXIMUM_PROCESSOR_INDEX)(
+ IN EFI_DEBUG_SUPPORT_PROTOCOL *This,
+ OUT UINTN *MaxProcessorIndex
+ );
+
+/**
+ Registers a function to be called back periodically in interrupt context.
+
+ @param This A pointer to the EFI_DEBUG_SUPPORT_PROTOCOL instance.
+ @param ProcessorIndex Specifies which processor the callback function applies to.
+ @param PeriodicCallback A pointer to a function of type PERIODIC_CALLBACK that is the main
+ periodic entry point of the debug agent.
+
+ @retval EFI_SUCCESS The function completed successfully.
+ @retval EFI_ALREADY_STARTED Non-NULL PeriodicCallback parameter when a callback
+ function was previously registered.
+ @retval EFI_OUT_OF_RESOURCES System has insufficient memory resources to register new callback
+ function.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_REGISTER_PERIODIC_CALLBACK)(
+ IN EFI_DEBUG_SUPPORT_PROTOCOL *This,
+ IN UINTN ProcessorIndex,
+ IN EFI_PERIODIC_CALLBACK PeriodicCallback
+ );
+
+/**
+ Registers a function to be called when a given processor exception occurs.
+
+ @param This A pointer to the EFI_DEBUG_SUPPORT_PROTOCOL instance.
+ @param ProcessorIndex Specifies which processor the callback function applies to.
+ @param ExceptionCallback A pointer to a function of type EXCEPTION_CALLBACK that is called
+ when the processor exception specified by ExceptionType occurs.
+ @param ExceptionType Specifies which processor exception to hook.
+
+ @retval EFI_SUCCESS The function completed successfully.
+ @retval EFI_ALREADY_STARTED Non-NULL PeriodicCallback parameter when a callback
+ function was previously registered.
+ @retval EFI_OUT_OF_RESOURCES System has insufficient memory resources to register new callback
+ function.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_REGISTER_EXCEPTION_CALLBACK)(
+ IN EFI_DEBUG_SUPPORT_PROTOCOL *This,
+ IN UINTN ProcessorIndex,
+ IN EFI_EXCEPTION_CALLBACK ExceptionCallback,
+ IN EFI_EXCEPTION_TYPE ExceptionType
+ );
+
+/**
+ Invalidates processor instruction cache for a memory range. Subsequent execution in this range
+ causes a fresh memory fetch to retrieve code to be executed.
+
+ @param This A pointer to the EFI_DEBUG_SUPPORT_PROTOCOL instance.
+ @param ProcessorIndex Specifies which processor's instruction cache is to be invalidated.
+ @param Start Specifies the physical base of the memory range to be invalidated.
+ @param Length Specifies the minimum number of bytes in the processor's instruction
+ cache to invalidate.
+
+ @retval EFI_SUCCESS The function completed successfully.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_INVALIDATE_INSTRUCTION_CACHE)(
+ IN EFI_DEBUG_SUPPORT_PROTOCOL *This,
+ IN UINTN ProcessorIndex,
+ IN VOID *Start,
+ IN UINT64 Length
+ );
+
+///
+/// This protocol provides the services to allow the debug agent to register
+/// callback functions that are called either periodically or when specific
+/// processor exceptions occur.
+///
+struct _EFI_DEBUG_SUPPORT_PROTOCOL {
+ ///
+ /// Declares the processor architecture for this instance of the EFI Debug Support protocol.
+ ///
+ EFI_INSTRUCTION_SET_ARCHITECTURE Isa;
+ EFI_GET_MAXIMUM_PROCESSOR_INDEX GetMaximumProcessorIndex;
+ EFI_REGISTER_PERIODIC_CALLBACK RegisterPeriodicCallback;
+ EFI_REGISTER_EXCEPTION_CALLBACK RegisterExceptionCallback;
+ EFI_INVALIDATE_INSTRUCTION_CACHE InvalidateInstructionCache;
+};
+
+extern EFI_GUID gEfiDebugSupportProtocolGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/Decompress.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/Decompress.h
new file mode 100644
index 0000000000..32cdb37732
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/Decompress.h
@@ -0,0 +1,116 @@
+/** @file
+ The Decompress Protocol Interface as defined in UEFI spec
+
+ Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __DECOMPRESS_H__
+#define __DECOMPRESS_H__
+
+#define EFI_DECOMPRESS_PROTOCOL_GUID \
+ { \
+ 0xd8117cfe, 0x94a6, 0x11d4, {0x9a, 0x3a, 0x0, 0x90, 0x27, 0x3f, 0xc1, 0x4d } \
+ }
+
+typedef struct _EFI_DECOMPRESS_PROTOCOL EFI_DECOMPRESS_PROTOCOL;
+
+/**
+ The GetInfo() function retrieves the size of the uncompressed buffer
+ and the temporary scratch buffer required to decompress the buffer
+ specified by Source and SourceSize. If the size of the uncompressed
+ buffer or the size of the scratch buffer cannot be determined from
+ the compressed data specified by Source and SourceData, then
+ EFI_INVALID_PARAMETER is returned. Otherwise, the size of the uncompressed
+ buffer is returned in DestinationSize, the size of the scratch buffer is
+ returned in ScratchSize, and EFI_SUCCESS is returned.
+
+ The GetInfo() function does not have a scratch buffer available to perform
+ a thorough checking of the validity of the source data. It just retrieves
+ the 'Original Size' field from the beginning bytes of the source data and
+ output it as DestinationSize. And ScratchSize is specific to the decompression
+ implementation.
+
+ @param This A pointer to the EFI_DECOMPRESS_PROTOCOL instance.
+ @param Source The source buffer containing the compressed data.
+ @param SourceSize The size, in bytes, of source buffer.
+ @param DestinationSize A pointer to the size, in bytes, of the uncompressed buffer
+ that will be generated when the compressed buffer specified
+ by Source and SourceSize is decompressed.
+ @param ScratchSize A pointer to the size, in bytes, of the scratch buffer that
+ is required to decompress the compressed buffer specified by
+ Source and SourceSize.
+
+ @retval EFI_SUCCESS The size of the uncompressed data was returned in DestinationSize
+ and the size of the scratch buffer was returned in ScratchSize.
+ @retval EFI_INVALID_PARAMETER The size of the uncompressed data or the size of the scratch
+ buffer cannot be determined from the compressed data specified by
+ Source and SourceData.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_DECOMPRESS_GET_INFO)(
+ IN EFI_DECOMPRESS_PROTOCOL *This,
+ IN VOID *Source,
+ IN UINT32 SourceSize,
+ OUT UINT32 *DestinationSize,
+ OUT UINT32 *ScratchSize
+ );
+
+/**
+ The Decompress() function extracts decompressed data to its original form.
+
+ This protocol is designed so that the decompression algorithm can be
+ implemented without using any memory services. As a result, the
+ Decompress() function is not allowed to call AllocatePool() or
+ AllocatePages() in its implementation. It is the caller's responsibility
+ to allocate and free the Destination and Scratch buffers.
+
+ If the compressed source data specified by Source and SourceSize is
+ successfully decompressed into Destination, then EFI_SUCCESS is returned.
+ If the compressed source data specified by Source and SourceSize is not in
+ a valid compressed data format, then EFI_INVALID_PARAMETER is returned.
+
+ @param This A pointer to the EFI_DECOMPRESS_PROTOCOL instance.
+ @param Source The source buffer containing the compressed data.
+ @param SourceSize The size of source data.
+ @param Destination On output, the destination buffer that contains
+ the uncompressed data.
+ @param DestinationSize The size of destination buffer. The size of destination
+ buffer needed is obtained from GetInfo().
+ @param Scratch A temporary scratch buffer that is used to perform the
+ decompression.
+ @param ScratchSize The size of scratch buffer. The size of scratch buffer needed
+ is obtained from GetInfo().
+
+ @retval EFI_SUCCESS Decompression completed successfully, and the uncompressed
+ buffer is returned in Destination.
+ @retval EFI_INVALID_PARAMETER The source buffer specified by Source and SourceSize is
+ corrupted (not in a valid compressed format).
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_DECOMPRESS_DECOMPRESS)(
+ IN EFI_DECOMPRESS_PROTOCOL *This,
+ IN VOID *Source,
+ IN UINT32 SourceSize,
+ IN OUT VOID *Destination,
+ IN UINT32 DestinationSize,
+ IN OUT VOID *Scratch,
+ IN UINT32 ScratchSize
+ );
+
+///
+/// Provides a decompression service.
+///
+struct _EFI_DECOMPRESS_PROTOCOL {
+ EFI_DECOMPRESS_GET_INFO GetInfo;
+ EFI_DECOMPRESS_DECOMPRESS Decompress;
+};
+
+extern EFI_GUID gEfiDecompressProtocolGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/DeferredImageLoad.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/DeferredImageLoad.h
new file mode 100644
index 0000000000..1fa258847a
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/DeferredImageLoad.h
@@ -0,0 +1,74 @@
+/** @file
+ UEFI 2.2 Deferred Image Load Protocol definition.
+
+ This protocol returns information about images whose load was denied because of security
+ considerations. This information can be used by the Boot Manager or another agent to reevaluate the
+ images when the current security profile has been changed, such as when the current user profile
+ changes. There can be more than one instance of this protocol installed.
+
+ Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __DEFERRED_IMAGE_LOAD_H__
+#define __DEFERRED_IMAGE_LOAD_H__
+
+///
+/// Global ID for the Deferred Image Load Protocol
+///
+#define EFI_DEFERRED_IMAGE_LOAD_PROTOCOL_GUID \
+ { \
+ 0x15853d7c, 0x3ddf, 0x43e0, { 0xa1, 0xcb, 0xeb, 0xf8, 0x5b, 0x8f, 0x87, 0x2c } \
+ };
+
+typedef struct _EFI_DEFERRED_IMAGE_LOAD_PROTOCOL EFI_DEFERRED_IMAGE_LOAD_PROTOCOL;
+
+/**
+ Returns information about a deferred image.
+
+ This function returns information about a single deferred image. The deferred images are numbered
+ consecutively, starting with 0. If there is no image which corresponds to ImageIndex, then
+ EFI_NOT_FOUND is returned. All deferred images may be returned by iteratively calling this
+ function until EFI_NOT_FOUND is returned.
+ Image may be NULL and ImageSize set to 0 if the decision to defer execution was made because
+ of the location of the executable image rather than its actual contents. record handle until
+ there are no more, at which point UserInfo will point to NULL.
+
+ @param[in] This Points to this instance of the EFI_DEFERRED_IMAGE_LOAD_PROTOCOL.
+ @param[in] ImageIndex Zero-based index of the deferred index.
+ @param[out] ImageDevicePath On return, points to a pointer to the device path of the image.
+ The device path should not be freed by the caller.
+ @param[out] Image On return, points to the first byte of the image or NULL if the
+ image is not available. The image should not be freed by the caller
+ unless LoadImage() has been called successfully.
+ @param[out] ImageSize On return, the size of the image, or 0 if the image is not available.
+ @param[out] BootOption On return, points to TRUE if the image was intended as a boot option
+ or FALSE if it was not intended as a boot option.
+
+ @retval EFI_SUCCESS Image information returned successfully.
+ @retval EFI_NOT_FOUND ImageIndex does not refer to a valid image.
+ @retval EFI_INVALID_PARAMETER ImageDevicePath is NULL or Image is NULL or ImageSize is NULL or
+ BootOption is NULL.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_DEFERRED_IMAGE_INFO)(
+ IN EFI_DEFERRED_IMAGE_LOAD_PROTOCOL *This,
+ IN UINTN ImageIndex,
+ OUT EFI_DEVICE_PATH_PROTOCOL **ImageDevicePath,
+ OUT VOID **Image,
+ OUT UINTN *ImageSize,
+ OUT BOOLEAN *BootOption
+ );
+
+///
+/// This protocol returns information about a deferred image.
+///
+struct _EFI_DEFERRED_IMAGE_LOAD_PROTOCOL {
+ EFI_DEFERRED_IMAGE_INFO GetImageInfo;
+};
+
+extern EFI_GUID gEfiDeferredImageLoadProtocolGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/DeviceIo.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/DeviceIo.h
new file mode 100644
index 0000000000..78fed75126
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/DeviceIo.h
@@ -0,0 +1,262 @@
+/** @file
+ Device IO protocol as defined in the EFI 1.10 specification.
+
+ Device IO is used to abstract hardware access to devices. It includes
+ memory mapped IO, IO, PCI Config space, and DMA.
+
+ Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __DEVICE_IO_H__
+#define __DEVICE_IO_H__
+
+#define EFI_DEVICE_IO_PROTOCOL_GUID \
+ { \
+ 0xaf6ac311, 0x84c3, 0x11d2, {0x8e, 0x3c, 0x00, 0xa0, 0xc9, 0x69, 0x72, 0x3b } \
+ }
+
+typedef struct _EFI_DEVICE_IO_PROTOCOL EFI_DEVICE_IO_PROTOCOL;
+
+///
+/// Protocol GUID name defined in EFI1.1.
+///
+#define DEVICE_IO_PROTOCOL EFI_DEVICE_IO_PROTOCOL_GUID
+
+///
+/// Protocol defined in EFI1.1.
+///
+typedef EFI_DEVICE_IO_PROTOCOL EFI_DEVICE_IO_INTERFACE;
+
+///
+/// Device IO Access Width
+///
+typedef enum {
+ IO_UINT8 = 0,
+ IO_UINT16 = 1,
+ IO_UINT32 = 2,
+ IO_UINT64 = 3,
+ //
+ // Below enumerations are added in "Extensible Firmware Interface Specification,
+ // Version 1.10, Specification Update, Version 001".
+ //
+ MMIO_COPY_UINT8 = 4,
+ MMIO_COPY_UINT16 = 5,
+ MMIO_COPY_UINT32 = 6,
+ MMIO_COPY_UINT64 = 7
+} EFI_IO_WIDTH;
+
+/**
+ Enables a driver to access device registers in the appropriate memory or I/O space.
+
+ @param This A pointer to the EFI_DEVICE_IO_INTERFACE instance.
+ @param Width Signifies the width of the I/O operations.
+ @param Address The base address of the I/O operations.
+ @param Count The number of I/O operations to perform.
+ @param Buffer For read operations, the destination buffer to store the results. For write
+ operations, the source buffer to write data from. If
+ Width is MMIO_COPY_UINT8, MMIO_COPY_UINT16,
+ MMIO_COPY_UINT32, or MMIO_COPY_UINT64, then
+ Buffer is interpreted as a base address of an I/O operation such as Address.
+
+ @retval EFI_SUCCESS The data was read from or written to the device.
+ @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
+ @retval EFI_INVALID_PARAMETER Width is invalid.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_DEVICE_IO)(
+ IN EFI_DEVICE_IO_PROTOCOL *This,
+ IN EFI_IO_WIDTH Width,
+ IN UINT64 Address,
+ IN UINTN Count,
+ IN OUT VOID *Buffer
+ );
+
+typedef struct {
+ EFI_DEVICE_IO Read;
+ EFI_DEVICE_IO Write;
+} EFI_IO_ACCESS;
+
+/**
+ Provides an EFI Device Path for a PCI device with the given PCI configuration space address.
+
+ @param This A pointer to the EFI_DEVICE_IO_INTERFACE instance.
+ @param PciAddress The PCI configuration space address of the device whose Device Path
+ is going to be returned.
+ @param PciDevicePath A pointer to the pointer for the EFI Device Path for PciAddress.
+ Memory for the Device Path is allocated from the pool.
+
+ @retval EFI_SUCCESS The PciDevicePath returns a pointer to a valid EFI Device Path.
+ @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
+ @retval EFI_UNSUPPORTED The PciAddress does not map to a valid EFI Device Path.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_PCI_DEVICE_PATH)(
+ IN EFI_DEVICE_IO_PROTOCOL *This,
+ IN UINT64 PciAddress,
+ IN OUT EFI_DEVICE_PATH_PROTOCOL **PciDevicePath
+ );
+
+typedef enum {
+ ///
+ /// A read operation from system memory by a bus master.
+ ///
+ EfiBusMasterRead,
+
+ ///
+ /// A write operation to system memory by a bus master.
+ ///
+ EfiBusMasterWrite,
+
+ ///
+ /// Provides both read and write access to system memory
+ /// by both the processor and a bus master. The buffer is
+ /// coherent from both the processor's and the bus master's
+ /// point of view.
+ ///
+ EfiBusMasterCommonBuffer
+} EFI_IO_OPERATION_TYPE;
+
+/**
+ Provides the device-specific addresses needed to access system memory.
+
+ @param This A pointer to the EFI_DEVICE_IO_INTERFACE instance.
+ @param Operation Indicates if the bus master is going to read or write to system memory.
+ @param HostAddress The system memory address to map to the device.
+ @param NumberOfBytes On input, the number of bytes to map.
+ On output, the number of bytes that were mapped.
+ @param DeviceAddress The resulting map address for the bus master device to use to access the
+ hosts HostAddress.
+ @param Mapping A resulting value to pass to Unmap().
+
+ @retval EFI_SUCCESS The range was mapped for the returned NumberOfBytes.
+ @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
+ @retval EFI_UNSUPPORTED The HostAddress cannot be mapped as a common buffer.
+ @retval EFI_INVALID_PARAMETER The Operation or HostAddress is undefined.
+ @retval EFI_DEVICE_ERROR The system hardware could not map the requested address.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_IO_MAP)(
+ IN EFI_DEVICE_IO_PROTOCOL *This,
+ IN EFI_IO_OPERATION_TYPE Operation,
+ IN EFI_PHYSICAL_ADDRESS *HostAddress,
+ IN OUT UINTN *NumberOfBytes,
+ OUT EFI_PHYSICAL_ADDRESS *DeviceAddress,
+ OUT VOID **Mapping
+ );
+
+/**
+ Completes the Map() operation and releases any corresponding resources.
+
+ @param This A pointer to the EFI_DEVICE_IO_INTERFACE instance.
+ @param Mapping A resulting value to pass to Unmap().
+
+ @retval EFI_SUCCESS The range was mapped for the returned NumberOfBytes.
+ @retval EFI_DEVICE_ERROR The system hardware could not map the requested address.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_IO_UNMAP)(
+ IN EFI_DEVICE_IO_PROTOCOL *This,
+ IN VOID *Mapping
+ );
+
+/**
+ Allocates pages that are suitable for an EFIBusMasterCommonBuffer mapping.
+
+ @param This A pointer to the EFI_DEVICE_IO_INTERFACE instance.
+ @param Type The type allocation to perform.
+ @param MemoryType The type of memory to allocate, EfiBootServicesData or
+ EfiRuntimeServicesData.
+ @param Pages The number of pages to allocate.
+ @param HostAddress A pointer to store the base address of the allocated range.
+
+ @retval EFI_SUCCESS The requested memory pages were allocated.
+ @retval EFI_OUT_OF_RESOURCES The memory pages could not be allocated.
+ @retval EFI_INVALID_PARAMETER The requested memory type is invalid.
+ @retval EFI_UNSUPPORTED The requested HostAddress is not supported on
+ this platform.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_IO_ALLOCATE_BUFFER)(
+ IN EFI_DEVICE_IO_PROTOCOL *This,
+ IN EFI_ALLOCATE_TYPE Type,
+ IN EFI_MEMORY_TYPE MemoryType,
+ IN UINTN Pages,
+ IN OUT EFI_PHYSICAL_ADDRESS *HostAddress
+ );
+
+/**
+ Flushes any posted write data to the device.
+
+ @param This A pointer to the EFI_DEVICE_IO_INTERFACE instance.
+
+ @retval EFI_SUCCESS The buffers were flushed.
+ @retval EFI_DEVICE_ERROR The buffers were not flushed due to a hardware error.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_IO_FLUSH)(
+ IN EFI_DEVICE_IO_PROTOCOL *This
+ );
+
+/**
+ Frees pages that were allocated with AllocateBuffer().
+
+ @param This A pointer to the EFI_DEVICE_IO_INTERFACE instance.
+ @param Pages The number of pages to free.
+ @param HostAddress The base address of the range to free.
+
+ @retval EFI_SUCCESS The requested memory pages were allocated.
+ @retval EFI_NOT_FOUND The requested memory pages were not allocated with
+ AllocateBuffer().
+ @retval EFI_INVALID_PARAMETER HostAddress is not page aligned or Pages is invalid.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_IO_FREE_BUFFER)(
+ IN EFI_DEVICE_IO_PROTOCOL *This,
+ IN UINTN Pages,
+ IN EFI_PHYSICAL_ADDRESS HostAddress
+ );
+
+///
+/// This protocol provides the basic Memory, I/O, and PCI interfaces that
+/// are used to abstract accesses to devices.
+///
+struct _EFI_DEVICE_IO_PROTOCOL {
+ ///
+ /// Allows reads and writes to memory mapped I/O space.
+ ///
+ EFI_IO_ACCESS Mem;
+ ///
+ /// Allows reads and writes to I/O space.
+ ///
+ EFI_IO_ACCESS Io;
+ ///
+ /// Allows reads and writes to PCI configuration space.
+ ///
+ EFI_IO_ACCESS Pci;
+ EFI_IO_MAP Map;
+ EFI_PCI_DEVICE_PATH PciDevicePath;
+ EFI_IO_UNMAP Unmap;
+ EFI_IO_ALLOCATE_BUFFER AllocateBuffer;
+ EFI_IO_FLUSH Flush;
+ EFI_IO_FREE_BUFFER FreeBuffer;
+};
+
+extern EFI_GUID gEfiDeviceIoProtocolGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/DevicePath.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/DevicePath.h
new file mode 100644
index 0000000000..b80cb6ff26
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/DevicePath.h
@@ -0,0 +1,1375 @@
+/** @file
+ The device path protocol as defined in UEFI 2.0.
+
+ The device path represents a programmatic path to a device,
+ from a software point of view. The path must persist from boot to boot, so
+ it can not contain things like PCI bus numbers that change from boot to boot.
+
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __EFI_DEVICE_PATH_PROTOCOL_H__
+#define __EFI_DEVICE_PATH_PROTOCOL_H__
+
+#include
+#include
+#include
+
+///
+/// Device Path protocol.
+///
+#define EFI_DEVICE_PATH_PROTOCOL_GUID \
+ { \
+ 0x9576e91, 0x6d3f, 0x11d2, {0x8e, 0x39, 0x0, 0xa0, 0xc9, 0x69, 0x72, 0x3b } \
+ }
+
+///
+/// Device Path guid definition for backward-compatible with EFI1.1.
+///
+#define DEVICE_PATH_PROTOCOL EFI_DEVICE_PATH_PROTOCOL_GUID
+
+#pragma pack(1)
+
+/**
+ This protocol can be used on any device handle to obtain generic path/location
+ information concerning the physical device or logical device. If the handle does
+ not logically map to a physical device, the handle may not necessarily support
+ the device path protocol. The device path describes the location of the device
+ the handle is for. The size of the Device Path can be determined from the structures
+ that make up the Device Path.
+**/
+typedef struct {
+ UINT8 Type; ///< 0x01 Hardware Device Path.
+ ///< 0x02 ACPI Device Path.
+ ///< 0x03 Messaging Device Path.
+ ///< 0x04 Media Device Path.
+ ///< 0x05 BIOS Boot Specification Device Path.
+ ///< 0x7F End of Hardware Device Path.
+
+ UINT8 SubType; ///< Varies by Type
+ ///< 0xFF End Entire Device Path, or
+ ///< 0x01 End This Instance of a Device Path and start a new
+ ///< Device Path.
+
+ UINT8 Length[2]; ///< Specific Device Path data. Type and Sub-Type define
+ ///< type of data. Size of data is included in Length.
+} EFI_DEVICE_PATH_PROTOCOL;
+
+///
+/// Device Path protocol definition for backward-compatible with EFI1.1.
+///
+typedef EFI_DEVICE_PATH_PROTOCOL EFI_DEVICE_PATH;
+
+///
+/// Hardware Device Paths.
+///
+#define HARDWARE_DEVICE_PATH 0x01
+
+///
+/// PCI Device Path SubType.
+///
+#define HW_PCI_DP 0x01
+
+///
+/// PCI Device Path.
+///
+typedef struct {
+ EFI_DEVICE_PATH_PROTOCOL Header;
+ ///
+ /// PCI Function Number.
+ ///
+ UINT8 Function;
+ ///
+ /// PCI Device Number.
+ ///
+ UINT8 Device;
+} PCI_DEVICE_PATH;
+
+///
+/// PCCARD Device Path SubType.
+///
+#define HW_PCCARD_DP 0x02
+
+///
+/// PCCARD Device Path.
+///
+typedef struct {
+ EFI_DEVICE_PATH_PROTOCOL Header;
+ ///
+ /// Function Number (0 = First Function).
+ ///
+ UINT8 FunctionNumber;
+} PCCARD_DEVICE_PATH;
+
+///
+/// Memory Mapped Device Path SubType.
+///
+#define HW_MEMMAP_DP 0x03
+
+///
+/// Memory Mapped Device Path.
+///
+typedef struct {
+ EFI_DEVICE_PATH_PROTOCOL Header;
+ ///
+ /// EFI_MEMORY_TYPE
+ ///
+ UINT32 MemoryType;
+ ///
+ /// Starting Memory Address.
+ ///
+ EFI_PHYSICAL_ADDRESS StartingAddress;
+ ///
+ /// Ending Memory Address.
+ ///
+ EFI_PHYSICAL_ADDRESS EndingAddress;
+} MEMMAP_DEVICE_PATH;
+
+///
+/// Hardware Vendor Device Path SubType.
+///
+#define HW_VENDOR_DP 0x04
+
+///
+/// The Vendor Device Path allows the creation of vendor-defined Device Paths. A vendor must
+/// allocate a Vendor GUID for a Device Path. The Vendor GUID can then be used to define the
+/// contents on the n bytes that follow in the Vendor Device Path node.
+///
+typedef struct {
+ EFI_DEVICE_PATH_PROTOCOL Header;
+ ///
+ /// Vendor-assigned GUID that defines the data that follows.
+ ///
+ EFI_GUID Guid;
+ ///
+ /// Vendor-defined variable size data.
+ ///
+} VENDOR_DEVICE_PATH;
+
+///
+/// Controller Device Path SubType.
+///
+#define HW_CONTROLLER_DP 0x05
+
+///
+/// Controller Device Path.
+///
+typedef struct {
+ EFI_DEVICE_PATH_PROTOCOL Header;
+ ///
+ /// Controller number.
+ ///
+ UINT32 ControllerNumber;
+} CONTROLLER_DEVICE_PATH;
+
+///
+/// BMC Device Path SubType.
+///
+#define HW_BMC_DP 0x06
+
+///
+/// BMC Device Path.
+///
+typedef struct {
+ EFI_DEVICE_PATH_PROTOCOL Header;
+ ///
+ /// Interface Type.
+ ///
+ UINT8 InterfaceType;
+ ///
+ /// Base Address.
+ ///
+ UINT8 BaseAddress[8];
+} BMC_DEVICE_PATH;
+
+///
+/// ACPI Device Paths.
+///
+#define ACPI_DEVICE_PATH 0x02
+
+///
+/// ACPI Device Path SubType.
+///
+#define ACPI_DP 0x01
+typedef struct {
+ EFI_DEVICE_PATH_PROTOCOL Header;
+ ///
+ /// Device's PnP hardware ID stored in a numeric 32-bit
+ /// compressed EISA-type ID. This value must match the
+ /// corresponding _HID in the ACPI name space.
+ ///
+ UINT32 HID;
+ ///
+ /// Unique ID that is required by ACPI if two devices have the
+ /// same _HID. This value must also match the corresponding
+ /// _UID/_HID pair in the ACPI name space. Only the 32-bit
+ /// numeric value type of _UID is supported. Thus, strings must
+ /// not be used for the _UID in the ACPI name space.
+ ///
+ UINT32 UID;
+} ACPI_HID_DEVICE_PATH;
+
+///
+/// Expanded ACPI Device Path SubType.
+///
+#define ACPI_EXTENDED_DP 0x02
+typedef struct {
+ EFI_DEVICE_PATH_PROTOCOL Header;
+ ///
+ /// Device's PnP hardware ID stored in a numeric 32-bit
+ /// compressed EISA-type ID. This value must match the
+ /// corresponding _HID in the ACPI name space.
+ ///
+ UINT32 HID;
+ ///
+ /// Unique ID that is required by ACPI if two devices have the
+ /// same _HID. This value must also match the corresponding
+ /// _UID/_HID pair in the ACPI name space.
+ ///
+ UINT32 UID;
+ ///
+ /// Device's compatible PnP hardware ID stored in a numeric
+ /// 32-bit compressed EISA-type ID. This value must match at
+ /// least one of the compatible device IDs returned by the
+ /// corresponding _CID in the ACPI name space.
+ ///
+ UINT32 CID;
+ ///
+ /// Optional variable length _HIDSTR.
+ /// Optional variable length _UIDSTR.
+ /// Optional variable length _CIDSTR.
+ ///
+} ACPI_EXTENDED_HID_DEVICE_PATH;
+
+//
+// EISA ID Macro
+// EISA ID Definition 32-bits
+// bits[15:0] - three character compressed ASCII EISA ID.
+// bits[31:16] - binary number
+// Compressed ASCII is 5 bits per character 0b00001 = 'A' 0b11010 = 'Z'
+//
+#define PNP_EISA_ID_CONST 0x41d0
+#define EISA_ID(_Name, _Num) ((UINT32)((_Name) | (_Num) << 16))
+#define EISA_PNP_ID(_PNPId) (EISA_ID(PNP_EISA_ID_CONST, (_PNPId)))
+#define EFI_PNP_ID(_PNPId) (EISA_ID(PNP_EISA_ID_CONST, (_PNPId)))
+
+#define PNP_EISA_ID_MASK 0xffff
+#define EISA_ID_TO_NUM(_Id) ((_Id) >> 16)
+
+///
+/// ACPI _ADR Device Path SubType.
+///
+#define ACPI_ADR_DP 0x03
+
+///
+/// The _ADR device path is used to contain video output device attributes to support the Graphics
+/// Output Protocol. The device path can contain multiple _ADR entries if multiple video output
+/// devices are displaying the same output.
+///
+typedef struct {
+ EFI_DEVICE_PATH_PROTOCOL Header;
+ ///
+ /// _ADR value. For video output devices the value of this
+ /// field comes from Table B-2 of the ACPI 3.0 specification. At
+ /// least one _ADR value is required.
+ ///
+ UINT32 ADR;
+ //
+ // This device path may optionally contain more than one _ADR entry.
+ //
+} ACPI_ADR_DEVICE_PATH;
+
+///
+/// ACPI NVDIMM Device Path SubType.
+///
+#define ACPI_NVDIMM_DP 0x04
+///
+///
+typedef struct {
+ EFI_DEVICE_PATH_PROTOCOL Header;
+ ///
+ /// NFIT Device Handle, the _ADR of the NVDIMM device.
+ /// The value of this field comes from Section 9.20.3 of the ACPI 6.2A specification.
+ ///
+ UINT32 NFITDeviceHandle;
+} ACPI_NVDIMM_DEVICE_PATH;
+
+#define ACPI_ADR_DISPLAY_TYPE_OTHER 0
+#define ACPI_ADR_DISPLAY_TYPE_VGA 1
+#define ACPI_ADR_DISPLAY_TYPE_TV 2
+#define ACPI_ADR_DISPLAY_TYPE_EXTERNAL_DIGITAL 3
+#define ACPI_ADR_DISPLAY_TYPE_INTERNAL_DIGITAL 4
+
+#define ACPI_DISPLAY_ADR(_DeviceIdScheme, _HeadId, _NonVgaOutput, _BiosCanDetect, _VendorInfo, _Type, _Port, _Index) \
+ ((UINT32)( ((UINT32)((_DeviceIdScheme) & 0x1) << 31) | \
+ (((_HeadId) & 0x7) << 18) | \
+ (((_NonVgaOutput) & 0x1) << 17) | \
+ (((_BiosCanDetect) & 0x1) << 16) | \
+ (((_VendorInfo) & 0xf) << 12) | \
+ (((_Type) & 0xf) << 8) | \
+ (((_Port) & 0xf) << 4) | \
+ ((_Index) & 0xf) ))
+
+///
+/// Messaging Device Paths.
+/// This Device Path is used to describe the connection of devices outside the resource domain of the
+/// system. This Device Path can describe physical messaging information like SCSI ID, or abstract
+/// information like networking protocol IP addresses.
+///
+#define MESSAGING_DEVICE_PATH 0x03
+
+///
+/// ATAPI Device Path SubType
+///
+#define MSG_ATAPI_DP 0x01
+typedef struct {
+ EFI_DEVICE_PATH_PROTOCOL Header;
+ ///
+ /// Set to zero for primary, or one for secondary.
+ ///
+ UINT8 PrimarySecondary;
+ ///
+ /// Set to zero for master, or one for slave mode.
+ ///
+ UINT8 SlaveMaster;
+ ///
+ /// Logical Unit Number.
+ ///
+ UINT16 Lun;
+} ATAPI_DEVICE_PATH;
+
+///
+/// SCSI Device Path SubType.
+///
+#define MSG_SCSI_DP 0x02
+typedef struct {
+ EFI_DEVICE_PATH_PROTOCOL Header;
+ ///
+ /// Target ID on the SCSI bus (PUN).
+ ///
+ UINT16 Pun;
+ ///
+ /// Logical Unit Number (LUN).
+ ///
+ UINT16 Lun;
+} SCSI_DEVICE_PATH;
+
+///
+/// Fibre Channel SubType.
+///
+#define MSG_FIBRECHANNEL_DP 0x03
+typedef struct {
+ EFI_DEVICE_PATH_PROTOCOL Header;
+ ///
+ /// Reserved for the future.
+ ///
+ UINT32 Reserved;
+ ///
+ /// Fibre Channel World Wide Number.
+ ///
+ UINT64 WWN;
+ ///
+ /// Fibre Channel Logical Unit Number.
+ ///
+ UINT64 Lun;
+} FIBRECHANNEL_DEVICE_PATH;
+
+///
+/// Fibre Channel Ex SubType.
+///
+#define MSG_FIBRECHANNELEX_DP 0x15
+typedef struct {
+ EFI_DEVICE_PATH_PROTOCOL Header;
+ ///
+ /// Reserved for the future.
+ ///
+ UINT32 Reserved;
+ ///
+ /// 8 byte array containing Fibre Channel End Device Port Name.
+ ///
+ UINT8 WWN[8];
+ ///
+ /// 8 byte array containing Fibre Channel Logical Unit Number.
+ ///
+ UINT8 Lun[8];
+} FIBRECHANNELEX_DEVICE_PATH;
+
+///
+/// 1394 Device Path SubType
+///
+#define MSG_1394_DP 0x04
+typedef struct {
+ EFI_DEVICE_PATH_PROTOCOL Header;
+ ///
+ /// Reserved for the future.
+ ///
+ UINT32 Reserved;
+ ///
+ /// 1394 Global Unique ID (GUID).
+ ///
+ UINT64 Guid;
+} F1394_DEVICE_PATH;
+
+///
+/// USB Device Path SubType.
+///
+#define MSG_USB_DP 0x05
+typedef struct {
+ EFI_DEVICE_PATH_PROTOCOL Header;
+ ///
+ /// USB Parent Port Number.
+ ///
+ UINT8 ParentPortNumber;
+ ///
+ /// USB Interface Number.
+ ///
+ UINT8 InterfaceNumber;
+} USB_DEVICE_PATH;
+
+///
+/// USB Class Device Path SubType.
+///
+#define MSG_USB_CLASS_DP 0x0f
+typedef struct {
+ EFI_DEVICE_PATH_PROTOCOL Header;
+ ///
+ /// Vendor ID assigned by USB-IF. A value of 0xFFFF will
+ /// match any Vendor ID.
+ ///
+ UINT16 VendorId;
+ ///
+ /// Product ID assigned by USB-IF. A value of 0xFFFF will
+ /// match any Product ID.
+ ///
+ UINT16 ProductId;
+ ///
+ /// The class code assigned by the USB-IF. A value of 0xFF
+ /// will match any class code.
+ ///
+ UINT8 DeviceClass;
+ ///
+ /// The subclass code assigned by the USB-IF. A value of
+ /// 0xFF will match any subclass code.
+ ///
+ UINT8 DeviceSubClass;
+ ///
+ /// The protocol code assigned by the USB-IF. A value of
+ /// 0xFF will match any protocol code.
+ ///
+ UINT8 DeviceProtocol;
+} USB_CLASS_DEVICE_PATH;
+
+///
+/// USB WWID Device Path SubType.
+///
+#define MSG_USB_WWID_DP 0x10
+
+///
+/// This device path describes a USB device using its serial number.
+///
+typedef struct {
+ EFI_DEVICE_PATH_PROTOCOL Header;
+ ///
+ /// USB interface number.
+ ///
+ UINT16 InterfaceNumber;
+ ///
+ /// USB vendor id of the device.
+ ///
+ UINT16 VendorId;
+ ///
+ /// USB product id of the device.
+ ///
+ UINT16 ProductId;
+ ///
+ /// Last 64-or-fewer UTF-16 characters of the USB
+ /// serial number. The length of the string is
+ /// determined by the Length field less the offset of the
+ /// Serial Number field (10)
+ ///
+ /// CHAR16 SerialNumber[...];
+} USB_WWID_DEVICE_PATH;
+
+///
+/// Device Logical Unit SubType.
+///
+#define MSG_DEVICE_LOGICAL_UNIT_DP 0x11
+typedef struct {
+ EFI_DEVICE_PATH_PROTOCOL Header;
+ ///
+ /// Logical Unit Number for the interface.
+ ///
+ UINT8 Lun;
+} DEVICE_LOGICAL_UNIT_DEVICE_PATH;
+
+///
+/// SATA Device Path SubType.
+///
+#define MSG_SATA_DP 0x12
+typedef struct {
+ EFI_DEVICE_PATH_PROTOCOL Header;
+ ///
+ /// The HBA port number that facilitates the connection to the
+ /// device or a port multiplier. The value 0xFFFF is reserved.
+ ///
+ UINT16 HBAPortNumber;
+ ///
+ /// The Port multiplier port number that facilitates the connection
+ /// to the device. Must be set to 0xFFFF if the device is directly
+ /// connected to the HBA.
+ ///
+ UINT16 PortMultiplierPortNumber;
+ ///
+ /// Logical Unit Number.
+ ///
+ UINT16 Lun;
+} SATA_DEVICE_PATH;
+
+///
+/// Flag for if the device is directly connected to the HBA.
+///
+#define SATA_HBA_DIRECT_CONNECT_FLAG 0x8000
+
+///
+/// I2O Device Path SubType.
+///
+#define MSG_I2O_DP 0x06
+typedef struct {
+ EFI_DEVICE_PATH_PROTOCOL Header;
+ ///
+ /// Target ID (TID) for a device.
+ ///
+ UINT32 Tid;
+} I2O_DEVICE_PATH;
+
+///
+/// MAC Address Device Path SubType.
+///
+#define MSG_MAC_ADDR_DP 0x0b
+typedef struct {
+ EFI_DEVICE_PATH_PROTOCOL Header;
+ ///
+ /// The MAC address for a network interface padded with 0s.
+ ///
+ EFI_MAC_ADDRESS MacAddress;
+ ///
+ /// Network interface type(i.e. 802.3, FDDI).
+ ///
+ UINT8 IfType;
+} MAC_ADDR_DEVICE_PATH;
+
+///
+/// IPv4 Device Path SubType
+///
+#define MSG_IPv4_DP 0x0c
+typedef struct {
+ EFI_DEVICE_PATH_PROTOCOL Header;
+ ///
+ /// The local IPv4 address.
+ ///
+ EFI_IPv4_ADDRESS LocalIpAddress;
+ ///
+ /// The remote IPv4 address.
+ ///
+ EFI_IPv4_ADDRESS RemoteIpAddress;
+ ///
+ /// The local port number.
+ ///
+ UINT16 LocalPort;
+ ///
+ /// The remote port number.
+ ///
+ UINT16 RemotePort;
+ ///
+ /// The network protocol(i.e. UDP, TCP).
+ ///
+ UINT16 Protocol;
+ ///
+ /// 0x00 - The Source IP Address was assigned though DHCP.
+ /// 0x01 - The Source IP Address is statically bound.
+ ///
+ BOOLEAN StaticIpAddress;
+ ///
+ /// The gateway IP address
+ ///
+ EFI_IPv4_ADDRESS GatewayIpAddress;
+ ///
+ /// The subnet mask
+ ///
+ EFI_IPv4_ADDRESS SubnetMask;
+} IPv4_DEVICE_PATH;
+
+///
+/// IPv6 Device Path SubType.
+///
+#define MSG_IPv6_DP 0x0d
+typedef struct {
+ EFI_DEVICE_PATH_PROTOCOL Header;
+ ///
+ /// The local IPv6 address.
+ ///
+ EFI_IPv6_ADDRESS LocalIpAddress;
+ ///
+ /// The remote IPv6 address.
+ ///
+ EFI_IPv6_ADDRESS RemoteIpAddress;
+ ///
+ /// The local port number.
+ ///
+ UINT16 LocalPort;
+ ///
+ /// The remote port number.
+ ///
+ UINT16 RemotePort;
+ ///
+ /// The network protocol(i.e. UDP, TCP).
+ ///
+ UINT16 Protocol;
+ ///
+ /// 0x00 - The Local IP Address was manually configured.
+ /// 0x01 - The Local IP Address is assigned through IPv6
+ /// stateless auto-configuration.
+ /// 0x02 - The Local IP Address is assigned through IPv6
+ /// stateful configuration.
+ ///
+ UINT8 IpAddressOrigin;
+ ///
+ /// The prefix length
+ ///
+ UINT8 PrefixLength;
+ ///
+ /// The gateway IP address
+ ///
+ EFI_IPv6_ADDRESS GatewayIpAddress;
+} IPv6_DEVICE_PATH;
+
+///
+/// InfiniBand Device Path SubType.
+///
+#define MSG_INFINIBAND_DP 0x09
+typedef struct {
+ EFI_DEVICE_PATH_PROTOCOL Header;
+ ///
+ /// Flags to help identify/manage InfiniBand device path elements:
+ /// Bit 0 - IOC/Service (0b = IOC, 1b = Service).
+ /// Bit 1 - Extend Boot Environment.
+ /// Bit 2 - Console Protocol.
+ /// Bit 3 - Storage Protocol.
+ /// Bit 4 - Network Protocol.
+ /// All other bits are reserved.
+ ///
+ UINT32 ResourceFlags;
+ ///
+ /// 128-bit Global Identifier for remote fabric port.
+ ///
+ UINT8 PortGid[16];
+ ///
+ /// 64-bit unique identifier to remote IOC or server process.
+ /// Interpretation of field specified by Resource Flags (bit 0).
+ ///
+ UINT64 ServiceId;
+ ///
+ /// 64-bit persistent ID of remote IOC port.
+ ///
+ UINT64 TargetPortId;
+ ///
+ /// 64-bit persistent ID of remote device.
+ ///
+ UINT64 DeviceId;
+} INFINIBAND_DEVICE_PATH;
+
+#define INFINIBAND_RESOURCE_FLAG_IOC_SERVICE 0x01
+#define INFINIBAND_RESOURCE_FLAG_EXTENDED_BOOT_ENVIRONMENT 0x02
+#define INFINIBAND_RESOURCE_FLAG_CONSOLE_PROTOCOL 0x04
+#define INFINIBAND_RESOURCE_FLAG_STORAGE_PROTOCOL 0x08
+#define INFINIBAND_RESOURCE_FLAG_NETWORK_PROTOCOL 0x10
+
+///
+/// UART Device Path SubType.
+///
+#define MSG_UART_DP 0x0e
+typedef struct {
+ EFI_DEVICE_PATH_PROTOCOL Header;
+ ///
+ /// Reserved.
+ ///
+ UINT32 Reserved;
+ ///
+ /// The baud rate setting for the UART style device. A value of 0
+ /// means that the device's default baud rate will be used.
+ ///
+ UINT64 BaudRate;
+ ///
+ /// The number of data bits for the UART style device. A value
+ /// of 0 means that the device's default number of data bits will be used.
+ ///
+ UINT8 DataBits;
+ ///
+ /// The parity setting for the UART style device.
+ /// Parity 0x00 - Default Parity.
+ /// Parity 0x01 - No Parity.
+ /// Parity 0x02 - Even Parity.
+ /// Parity 0x03 - Odd Parity.
+ /// Parity 0x04 - Mark Parity.
+ /// Parity 0x05 - Space Parity.
+ ///
+ UINT8 Parity;
+ ///
+ /// The number of stop bits for the UART style device.
+ /// Stop Bits 0x00 - Default Stop Bits.
+ /// Stop Bits 0x01 - 1 Stop Bit.
+ /// Stop Bits 0x02 - 1.5 Stop Bits.
+ /// Stop Bits 0x03 - 2 Stop Bits.
+ ///
+ UINT8 StopBits;
+} UART_DEVICE_PATH;
+
+///
+/// NVDIMM Namespace Device Path SubType.
+///
+#define NVDIMM_NAMESPACE_DP 0x20
+typedef struct {
+ EFI_DEVICE_PATH_PROTOCOL Header;
+ ///
+ /// Namespace unique label identifier UUID.
+ ///
+ EFI_GUID Uuid;
+} NVDIMM_NAMESPACE_DEVICE_PATH;
+
+//
+// Use VENDOR_DEVICE_PATH struct
+//
+#define MSG_VENDOR_DP 0x0a
+typedef VENDOR_DEVICE_PATH VENDOR_DEFINED_DEVICE_PATH;
+
+#define DEVICE_PATH_MESSAGING_PC_ANSI EFI_PC_ANSI_GUID
+#define DEVICE_PATH_MESSAGING_VT_100 EFI_VT_100_GUID
+#define DEVICE_PATH_MESSAGING_VT_100_PLUS EFI_VT_100_PLUS_GUID
+#define DEVICE_PATH_MESSAGING_VT_UTF8 EFI_VT_UTF8_GUID
+
+///
+/// A new device path node is defined to declare flow control characteristics.
+/// UART Flow Control Messaging Device Path
+///
+typedef struct {
+ EFI_DEVICE_PATH_PROTOCOL Header;
+ ///
+ /// DEVICE_PATH_MESSAGING_UART_FLOW_CONTROL GUID.
+ ///
+ EFI_GUID Guid;
+ ///
+ /// Bitmap of supported flow control types.
+ /// Bit 0 set indicates hardware flow control.
+ /// Bit 1 set indicates Xon/Xoff flow control.
+ /// All other bits are reserved and are clear.
+ ///
+ UINT32 FlowControlMap;
+} UART_FLOW_CONTROL_DEVICE_PATH;
+
+#define UART_FLOW_CONTROL_HARDWARE 0x00000001
+#define UART_FLOW_CONTROL_XON_XOFF 0x00000010
+
+#define DEVICE_PATH_MESSAGING_SAS EFI_SAS_DEVICE_PATH_GUID
+///
+/// Serial Attached SCSI (SAS) Device Path.
+///
+typedef struct {
+ EFI_DEVICE_PATH_PROTOCOL Header;
+ ///
+ /// DEVICE_PATH_MESSAGING_SAS GUID.
+ ///
+ EFI_GUID Guid;
+ ///
+ /// Reserved for future use.
+ ///
+ UINT32 Reserved;
+ ///
+ /// SAS Address for Serial Attached SCSI Target.
+ ///
+ UINT64 SasAddress;
+ ///
+ /// SAS Logical Unit Number.
+ ///
+ UINT64 Lun;
+ ///
+ /// More Information about the device and its interconnect.
+ ///
+ UINT16 DeviceTopology;
+ ///
+ /// Relative Target Port (RTP).
+ ///
+ UINT16 RelativeTargetPort;
+} SAS_DEVICE_PATH;
+
+///
+/// Serial Attached SCSI (SAS) Ex Device Path SubType
+///
+#define MSG_SASEX_DP 0x16
+typedef struct {
+ EFI_DEVICE_PATH_PROTOCOL Header;
+ ///
+ /// 8-byte array of the SAS Address for Serial Attached SCSI Target Port.
+ ///
+ UINT8 SasAddress[8];
+ ///
+ /// 8-byte array of the SAS Logical Unit Number.
+ ///
+ UINT8 Lun[8];
+ ///
+ /// More Information about the device and its interconnect.
+ ///
+ UINT16 DeviceTopology;
+ ///
+ /// Relative Target Port (RTP).
+ ///
+ UINT16 RelativeTargetPort;
+} SASEX_DEVICE_PATH;
+
+///
+/// NvmExpress Namespace Device Path SubType.
+///
+#define MSG_NVME_NAMESPACE_DP 0x17
+typedef struct {
+ EFI_DEVICE_PATH_PROTOCOL Header;
+ UINT32 NamespaceId;
+ UINT64 NamespaceUuid;
+} NVME_NAMESPACE_DEVICE_PATH;
+
+///
+/// DNS Device Path SubType
+///
+#define MSG_DNS_DP 0x1F
+typedef struct {
+ EFI_DEVICE_PATH_PROTOCOL Header;
+ ///
+ /// Indicates the DNS server address is IPv4 or IPv6 address.
+ ///
+ UINT8 IsIPv6;
+ ///
+ /// Instance of the DNS server address.
+ ///
+ EFI_IP_ADDRESS DnsServerIp[];
+} DNS_DEVICE_PATH;
+
+///
+/// Uniform Resource Identifiers (URI) Device Path SubType
+///
+#define MSG_URI_DP 0x18
+typedef struct {
+ EFI_DEVICE_PATH_PROTOCOL Header;
+ ///
+ /// Instance of the URI pursuant to RFC 3986.
+ ///
+ CHAR8 Uri[];
+} URI_DEVICE_PATH;
+
+///
+/// Universal Flash Storage (UFS) Device Path SubType.
+///
+#define MSG_UFS_DP 0x19
+typedef struct {
+ EFI_DEVICE_PATH_PROTOCOL Header;
+ ///
+ /// Target ID on the UFS bus (PUN).
+ ///
+ UINT8 Pun;
+ ///
+ /// Logical Unit Number (LUN).
+ ///
+ UINT8 Lun;
+} UFS_DEVICE_PATH;
+
+///
+/// SD (Secure Digital) Device Path SubType.
+///
+#define MSG_SD_DP 0x1A
+typedef struct {
+ EFI_DEVICE_PATH_PROTOCOL Header;
+ UINT8 SlotNumber;
+} SD_DEVICE_PATH;
+
+///
+/// EMMC (Embedded MMC) Device Path SubType.
+///
+#define MSG_EMMC_DP 0x1D
+typedef struct {
+ EFI_DEVICE_PATH_PROTOCOL Header;
+ UINT8 SlotNumber;
+} EMMC_DEVICE_PATH;
+
+///
+/// iSCSI Device Path SubType
+///
+#define MSG_ISCSI_DP 0x13
+typedef struct {
+ EFI_DEVICE_PATH_PROTOCOL Header;
+ ///
+ /// Network Protocol (0 = TCP, 1+ = reserved).
+ ///
+ UINT16 NetworkProtocol;
+ ///
+ /// iSCSI Login Options.
+ ///
+ UINT16 LoginOption;
+ ///
+ /// iSCSI Logical Unit Number.
+ ///
+ UINT64 Lun;
+ ///
+ /// iSCSI Target Portal group tag the initiator intends
+ /// to establish a session with.
+ ///
+ UINT16 TargetPortalGroupTag;
+ ///
+ /// iSCSI NodeTarget Name. The length of the name
+ /// is determined by subtracting the offset of this field from Length.
+ ///
+ /// CHAR8 iSCSI Target Name.
+} ISCSI_DEVICE_PATH;
+
+#define ISCSI_LOGIN_OPTION_NO_HEADER_DIGEST 0x0000
+#define ISCSI_LOGIN_OPTION_HEADER_DIGEST_USING_CRC32C 0x0002
+#define ISCSI_LOGIN_OPTION_NO_DATA_DIGEST 0x0000
+#define ISCSI_LOGIN_OPTION_DATA_DIGEST_USING_CRC32C 0x0008
+#define ISCSI_LOGIN_OPTION_AUTHMETHOD_CHAP 0x0000
+#define ISCSI_LOGIN_OPTION_AUTHMETHOD_NON 0x1000
+#define ISCSI_LOGIN_OPTION_CHAP_BI 0x0000
+#define ISCSI_LOGIN_OPTION_CHAP_UNI 0x2000
+
+///
+/// VLAN Device Path SubType.
+///
+#define MSG_VLAN_DP 0x14
+typedef struct {
+ EFI_DEVICE_PATH_PROTOCOL Header;
+ ///
+ /// VLAN identifier (0-4094).
+ ///
+ UINT16 VlanId;
+} VLAN_DEVICE_PATH;
+
+///
+/// Bluetooth Device Path SubType.
+///
+#define MSG_BLUETOOTH_DP 0x1b
+typedef struct {
+ EFI_DEVICE_PATH_PROTOCOL Header;
+ ///
+ /// 48bit Bluetooth device address.
+ ///
+ BLUETOOTH_ADDRESS BD_ADDR;
+} BLUETOOTH_DEVICE_PATH;
+
+///
+/// Wi-Fi Device Path SubType.
+///
+#define MSG_WIFI_DP 0x1C
+typedef struct {
+ EFI_DEVICE_PATH_PROTOCOL Header;
+ ///
+ /// Service set identifier. A 32-byte octets string.
+ ///
+ UINT8 SSId[32];
+} WIFI_DEVICE_PATH;
+
+///
+/// Bluetooth LE Device Path SubType.
+///
+#define MSG_BLUETOOTH_LE_DP 0x1E
+typedef struct {
+ EFI_DEVICE_PATH_PROTOCOL Header;
+ BLUETOOTH_LE_ADDRESS Address;
+} BLUETOOTH_LE_DEVICE_PATH;
+
+//
+// Media Device Path
+//
+#define MEDIA_DEVICE_PATH 0x04
+
+///
+/// Hard Drive Media Device Path SubType.
+///
+#define MEDIA_HARDDRIVE_DP 0x01
+
+///
+/// The Hard Drive Media Device Path is used to represent a partition on a hard drive.
+///
+typedef struct {
+ EFI_DEVICE_PATH_PROTOCOL Header;
+ ///
+ /// Describes the entry in a partition table, starting with entry 1.
+ /// Partition number zero represents the entire device. Valid
+ /// partition numbers for a MBR partition are [1, 4]. Valid
+ /// partition numbers for a GPT partition are [1, NumberOfPartitionEntries].
+ ///
+ UINT32 PartitionNumber;
+ ///
+ /// Starting LBA of the partition on the hard drive.
+ ///
+ UINT64 PartitionStart;
+ ///
+ /// Size of the partition in units of Logical Blocks.
+ ///
+ UINT64 PartitionSize;
+ ///
+ /// Signature unique to this partition:
+ /// If SignatureType is 0, this field has to be initialized with 16 zeros.
+ /// If SignatureType is 1, the MBR signature is stored in the first 4 bytes of this field.
+ /// The other 12 bytes are initialized with zeros.
+ /// If SignatureType is 2, this field contains a 16 byte signature.
+ ///
+ UINT8 Signature[16];
+ ///
+ /// Partition Format: (Unused values reserved).
+ /// 0x01 - PC-AT compatible legacy MBR.
+ /// 0x02 - GUID Partition Table.
+ ///
+ UINT8 MBRType;
+ ///
+ /// Type of Disk Signature: (Unused values reserved).
+ /// 0x00 - No Disk Signature.
+ /// 0x01 - 32-bit signature from address 0x1b8 of the type 0x01 MBR.
+ /// 0x02 - GUID signature.
+ ///
+ UINT8 SignatureType;
+} HARDDRIVE_DEVICE_PATH;
+
+#define MBR_TYPE_PCAT 0x01
+#define MBR_TYPE_EFI_PARTITION_TABLE_HEADER 0x02
+
+#define NO_DISK_SIGNATURE 0x00
+#define SIGNATURE_TYPE_MBR 0x01
+#define SIGNATURE_TYPE_GUID 0x02
+
+///
+/// CD-ROM Media Device Path SubType.
+///
+#define MEDIA_CDROM_DP 0x02
+
+///
+/// The CD-ROM Media Device Path is used to define a system partition that exists on a CD-ROM.
+///
+typedef struct {
+ EFI_DEVICE_PATH_PROTOCOL Header;
+ ///
+ /// Boot Entry number from the Boot Catalog. The Initial/Default entry is defined as zero.
+ ///
+ UINT32 BootEntry;
+ ///
+ /// Starting RBA of the partition on the medium. CD-ROMs use Relative logical Block Addressing.
+ ///
+ UINT64 PartitionStart;
+ ///
+ /// Size of the partition in units of Blocks, also called Sectors.
+ ///
+ UINT64 PartitionSize;
+} CDROM_DEVICE_PATH;
+
+//
+// Use VENDOR_DEVICE_PATH struct
+//
+#define MEDIA_VENDOR_DP 0x03 ///< Media vendor device path subtype.
+
+///
+/// File Path Media Device Path SubType
+///
+#define MEDIA_FILEPATH_DP 0x04
+typedef struct {
+ EFI_DEVICE_PATH_PROTOCOL Header;
+ ///
+ /// A NULL-terminated Path string including directory and file names.
+ ///
+ CHAR16 PathName[1];
+} FILEPATH_DEVICE_PATH;
+
+#define SIZE_OF_FILEPATH_DEVICE_PATH OFFSET_OF(FILEPATH_DEVICE_PATH,PathName)
+
+///
+/// Media Protocol Device Path SubType.
+///
+#define MEDIA_PROTOCOL_DP 0x05
+
+///
+/// The Media Protocol Device Path is used to denote the protocol that is being
+/// used in a device path at the location of the path specified.
+/// Many protocols are inherent to the style of device path.
+///
+typedef struct {
+ EFI_DEVICE_PATH_PROTOCOL Header;
+ ///
+ /// The ID of the protocol.
+ ///
+ EFI_GUID Protocol;
+} MEDIA_PROTOCOL_DEVICE_PATH;
+
+///
+/// PIWG Firmware File SubType.
+///
+#define MEDIA_PIWG_FW_FILE_DP 0x06
+
+///
+/// This device path is used by systems implementing the UEFI PI Specification 1.0 to describe a firmware file.
+///
+typedef struct {
+ EFI_DEVICE_PATH_PROTOCOL Header;
+ ///
+ /// Firmware file name
+ ///
+ EFI_GUID FvFileName;
+} MEDIA_FW_VOL_FILEPATH_DEVICE_PATH;
+
+///
+/// PIWG Firmware Volume Device Path SubType.
+///
+#define MEDIA_PIWG_FW_VOL_DP 0x07
+
+///
+/// This device path is used by systems implementing the UEFI PI Specification 1.0 to describe a firmware volume.
+///
+typedef struct {
+ EFI_DEVICE_PATH_PROTOCOL Header;
+ ///
+ /// Firmware volume name.
+ ///
+ EFI_GUID FvName;
+} MEDIA_FW_VOL_DEVICE_PATH;
+
+///
+/// Media relative offset range device path.
+///
+#define MEDIA_RELATIVE_OFFSET_RANGE_DP 0x08
+
+///
+/// Used to describe the offset range of media relative.
+///
+typedef struct {
+ EFI_DEVICE_PATH_PROTOCOL Header;
+ UINT32 Reserved;
+ UINT64 StartingOffset;
+ UINT64 EndingOffset;
+} MEDIA_RELATIVE_OFFSET_RANGE_DEVICE_PATH;
+
+///
+/// This GUID defines a RAM Disk supporting a raw disk format in volatile memory.
+///
+#define EFI_VIRTUAL_DISK_GUID EFI_ACPI_6_0_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_DISK_REGION_VOLATILE
+
+extern EFI_GUID gEfiVirtualDiskGuid;
+
+///
+/// This GUID defines a RAM Disk supporting an ISO image in volatile memory.
+///
+#define EFI_VIRTUAL_CD_GUID EFI_ACPI_6_0_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_CD_REGION_VOLATILE
+
+extern EFI_GUID gEfiVirtualCdGuid;
+
+///
+/// This GUID defines a RAM Disk supporting a raw disk format in persistent memory.
+///
+#define EFI_PERSISTENT_VIRTUAL_DISK_GUID EFI_ACPI_6_0_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_DISK_REGION_PERSISTENT
+
+extern EFI_GUID gEfiPersistentVirtualDiskGuid;
+
+///
+/// This GUID defines a RAM Disk supporting an ISO image in persistent memory.
+///
+#define EFI_PERSISTENT_VIRTUAL_CD_GUID EFI_ACPI_6_0_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_CD_REGION_PERSISTENT
+
+extern EFI_GUID gEfiPersistentVirtualCdGuid;
+
+///
+/// Media ram disk device path.
+///
+#define MEDIA_RAM_DISK_DP 0x09
+
+///
+/// Used to describe the ram disk device path.
+///
+typedef struct {
+ EFI_DEVICE_PATH_PROTOCOL Header;
+ ///
+ /// Starting Memory Address.
+ ///
+ UINT32 StartingAddr[2];
+ ///
+ /// Ending Memory Address.
+ ///
+ UINT32 EndingAddr[2];
+ ///
+ /// GUID that defines the type of the RAM Disk.
+ ///
+ EFI_GUID TypeGuid;
+ ///
+ /// RAM Diskinstance number, if supported. The default value is zero.
+ ///
+ UINT16 Instance;
+} MEDIA_RAM_DISK_DEVICE_PATH;
+
+///
+/// BIOS Boot Specification Device Path.
+///
+#define BBS_DEVICE_PATH 0x05
+
+///
+/// BIOS Boot Specification Device Path SubType.
+///
+#define BBS_BBS_DP 0x01
+
+///
+/// This Device Path is used to describe the booting of non-EFI-aware operating systems.
+///
+typedef struct {
+ EFI_DEVICE_PATH_PROTOCOL Header;
+ ///
+ /// Device Type as defined by the BIOS Boot Specification.
+ ///
+ UINT16 DeviceType;
+ ///
+ /// Status Flags as defined by the BIOS Boot Specification.
+ ///
+ UINT16 StatusFlag;
+ ///
+ /// Null-terminated ASCII string that describes the boot device to a user.
+ ///
+ CHAR8 String[1];
+} BBS_BBS_DEVICE_PATH;
+
+//
+// DeviceType definitions - from BBS specification
+//
+#define BBS_TYPE_FLOPPY 0x01
+#define BBS_TYPE_HARDDRIVE 0x02
+#define BBS_TYPE_CDROM 0x03
+#define BBS_TYPE_PCMCIA 0x04
+#define BBS_TYPE_USB 0x05
+#define BBS_TYPE_EMBEDDED_NETWORK 0x06
+#define BBS_TYPE_BEV 0x80
+#define BBS_TYPE_UNKNOWN 0xFF
+
+///
+/// Union of all possible Device Paths and pointers to Device Paths.
+///
+typedef union {
+ EFI_DEVICE_PATH_PROTOCOL DevPath;
+ PCI_DEVICE_PATH Pci;
+ PCCARD_DEVICE_PATH PcCard;
+ MEMMAP_DEVICE_PATH MemMap;
+ VENDOR_DEVICE_PATH Vendor;
+
+ CONTROLLER_DEVICE_PATH Controller;
+ BMC_DEVICE_PATH Bmc;
+ ACPI_HID_DEVICE_PATH Acpi;
+ ACPI_EXTENDED_HID_DEVICE_PATH ExtendedAcpi;
+ ACPI_ADR_DEVICE_PATH AcpiAdr;
+
+ ATAPI_DEVICE_PATH Atapi;
+ SCSI_DEVICE_PATH Scsi;
+ ISCSI_DEVICE_PATH Iscsi;
+ FIBRECHANNEL_DEVICE_PATH FibreChannel;
+ FIBRECHANNELEX_DEVICE_PATH FibreChannelEx;
+
+ F1394_DEVICE_PATH F1394;
+ USB_DEVICE_PATH Usb;
+ SATA_DEVICE_PATH Sata;
+ USB_CLASS_DEVICE_PATH UsbClass;
+ USB_WWID_DEVICE_PATH UsbWwid;
+ DEVICE_LOGICAL_UNIT_DEVICE_PATH LogicUnit;
+ I2O_DEVICE_PATH I2O;
+ MAC_ADDR_DEVICE_PATH MacAddr;
+ IPv4_DEVICE_PATH Ipv4;
+ IPv6_DEVICE_PATH Ipv6;
+ VLAN_DEVICE_PATH Vlan;
+ INFINIBAND_DEVICE_PATH InfiniBand;
+ UART_DEVICE_PATH Uart;
+ UART_FLOW_CONTROL_DEVICE_PATH UartFlowControl;
+ SAS_DEVICE_PATH Sas;
+ SASEX_DEVICE_PATH SasEx;
+ NVME_NAMESPACE_DEVICE_PATH NvmeNamespace;
+ DNS_DEVICE_PATH Dns;
+ URI_DEVICE_PATH Uri;
+ BLUETOOTH_DEVICE_PATH Bluetooth;
+ WIFI_DEVICE_PATH WiFi;
+ UFS_DEVICE_PATH Ufs;
+ SD_DEVICE_PATH Sd;
+ EMMC_DEVICE_PATH Emmc;
+ HARDDRIVE_DEVICE_PATH HardDrive;
+ CDROM_DEVICE_PATH CD;
+
+ FILEPATH_DEVICE_PATH FilePath;
+ MEDIA_PROTOCOL_DEVICE_PATH MediaProtocol;
+
+ MEDIA_FW_VOL_DEVICE_PATH FirmwareVolume;
+ MEDIA_FW_VOL_FILEPATH_DEVICE_PATH FirmwareFile;
+ MEDIA_RELATIVE_OFFSET_RANGE_DEVICE_PATH Offset;
+ MEDIA_RAM_DISK_DEVICE_PATH RamDisk;
+ BBS_BBS_DEVICE_PATH Bbs;
+} EFI_DEV_PATH;
+
+typedef union {
+ EFI_DEVICE_PATH_PROTOCOL *DevPath;
+ PCI_DEVICE_PATH *Pci;
+ PCCARD_DEVICE_PATH *PcCard;
+ MEMMAP_DEVICE_PATH *MemMap;
+ VENDOR_DEVICE_PATH *Vendor;
+
+ CONTROLLER_DEVICE_PATH *Controller;
+ BMC_DEVICE_PATH *Bmc;
+ ACPI_HID_DEVICE_PATH *Acpi;
+ ACPI_EXTENDED_HID_DEVICE_PATH *ExtendedAcpi;
+ ACPI_ADR_DEVICE_PATH *AcpiAdr;
+
+ ATAPI_DEVICE_PATH *Atapi;
+ SCSI_DEVICE_PATH *Scsi;
+ ISCSI_DEVICE_PATH *Iscsi;
+ FIBRECHANNEL_DEVICE_PATH *FibreChannel;
+ FIBRECHANNELEX_DEVICE_PATH *FibreChannelEx;
+
+ F1394_DEVICE_PATH *F1394;
+ USB_DEVICE_PATH *Usb;
+ SATA_DEVICE_PATH *Sata;
+ USB_CLASS_DEVICE_PATH *UsbClass;
+ USB_WWID_DEVICE_PATH *UsbWwid;
+ DEVICE_LOGICAL_UNIT_DEVICE_PATH *LogicUnit;
+ I2O_DEVICE_PATH *I2O;
+ MAC_ADDR_DEVICE_PATH *MacAddr;
+ IPv4_DEVICE_PATH *Ipv4;
+ IPv6_DEVICE_PATH *Ipv6;
+ VLAN_DEVICE_PATH *Vlan;
+ INFINIBAND_DEVICE_PATH *InfiniBand;
+ UART_DEVICE_PATH *Uart;
+ UART_FLOW_CONTROL_DEVICE_PATH *UartFlowControl;
+ SAS_DEVICE_PATH *Sas;
+ SASEX_DEVICE_PATH *SasEx;
+ NVME_NAMESPACE_DEVICE_PATH *NvmeNamespace;
+ DNS_DEVICE_PATH *Dns;
+ URI_DEVICE_PATH *Uri;
+ BLUETOOTH_DEVICE_PATH *Bluetooth;
+ WIFI_DEVICE_PATH *WiFi;
+ UFS_DEVICE_PATH *Ufs;
+ SD_DEVICE_PATH *Sd;
+ EMMC_DEVICE_PATH *Emmc;
+ HARDDRIVE_DEVICE_PATH *HardDrive;
+ CDROM_DEVICE_PATH *CD;
+
+ FILEPATH_DEVICE_PATH *FilePath;
+ MEDIA_PROTOCOL_DEVICE_PATH *MediaProtocol;
+
+ MEDIA_FW_VOL_DEVICE_PATH *FirmwareVolume;
+ MEDIA_FW_VOL_FILEPATH_DEVICE_PATH *FirmwareFile;
+ MEDIA_RELATIVE_OFFSET_RANGE_DEVICE_PATH *Offset;
+ MEDIA_RAM_DISK_DEVICE_PATH *RamDisk;
+ BBS_BBS_DEVICE_PATH *Bbs;
+ UINT8 *Raw;
+} EFI_DEV_PATH_PTR;
+
+#pragma pack()
+
+#define END_DEVICE_PATH_TYPE 0x7f
+#define END_ENTIRE_DEVICE_PATH_SUBTYPE 0xFF
+#define END_INSTANCE_DEVICE_PATH_SUBTYPE 0x01
+
+extern EFI_GUID gEfiDevicePathProtocolGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/DevicePathFromText.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/DevicePathFromText.h
new file mode 100644
index 0000000000..1357720dec
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/DevicePathFromText.h
@@ -0,0 +1,65 @@
+/** @file
+ EFI_DEVICE_PATH_FROM_TEXT_PROTOCOL as defined in UEFI 2.0.
+ This protocol provides service to convert text to device paths and device nodes.
+
+ Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __DEVICE_PATH_FROM_TEXT_PROTOCOL_H__
+#define __DEVICE_PATH_FROM_TEXT_PROTOCOL_H__
+
+///
+/// Device Path From Text protocol
+///
+#define EFI_DEVICE_PATH_FROM_TEXT_PROTOCOL_GUID \
+ { \
+ 0x5c99a21, 0xc70f, 0x4ad2, {0x8a, 0x5f, 0x35, 0xdf, 0x33, 0x43, 0xf5, 0x1e } \
+ }
+
+/**
+ Convert text to the binary representation of a device node.
+
+ @param TextDeviceNode TextDeviceNode points to the text representation of a device
+ node. Conversion starts with the first character and continues
+ until the first non-device node character.
+
+ @retval a_pointer Pointer to the EFI device node.
+ @retval NULL if TextDeviceNode is NULL or there was insufficient memory.
+
+**/
+typedef
+EFI_DEVICE_PATH_PROTOCOL *
+(EFIAPI *EFI_DEVICE_PATH_FROM_TEXT_NODE)(
+ IN CONST CHAR16 *TextDeviceNode
+ );
+
+/**
+ Convert text to the binary representation of a device node.
+
+ @param TextDeviceNode TextDevicePath points to the text representation of a device
+ path. Conversion starts with the first character and continues
+ until the first non-device path character.
+
+ @retval a_pointer Pointer to the allocated device path.
+ @retval NULL if TextDeviceNode is NULL or there was insufficient memory.
+
+**/
+typedef
+EFI_DEVICE_PATH_PROTOCOL *
+(EFIAPI *EFI_DEVICE_PATH_FROM_TEXT_PATH)(
+ IN CONST CHAR16 *TextDevicePath
+ );
+
+///
+/// This protocol converts text to device paths and device nodes.
+///
+typedef struct {
+ EFI_DEVICE_PATH_FROM_TEXT_NODE ConvertTextToDeviceNode;
+ EFI_DEVICE_PATH_FROM_TEXT_PATH ConvertTextToDevicePath;
+} EFI_DEVICE_PATH_FROM_TEXT_PROTOCOL;
+
+extern EFI_GUID gEfiDevicePathFromTextProtocolGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/DevicePathToText.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/DevicePathToText.h
new file mode 100644
index 0000000000..08fd9f3e90
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/DevicePathToText.h
@@ -0,0 +1,77 @@
+/** @file
+ EFI_DEVICE_PATH_TO_TEXT_PROTOCOL as defined in UEFI 2.0.
+ This protocol provides service to convert device nodes and paths to text.
+
+ Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __DEVICE_PATH_TO_TEXT_PROTOCOL_H__
+#define __DEVICE_PATH_TO_TEXT_PROTOCOL_H__
+
+///
+/// Device Path To Text protocol
+///
+#define EFI_DEVICE_PATH_TO_TEXT_PROTOCOL_GUID \
+ { \
+ 0x8b843e20, 0x8132, 0x4852, {0x90, 0xcc, 0x55, 0x1a, 0x4e, 0x4a, 0x7f, 0x1c } \
+ }
+
+/**
+ Convert a device node to its text representation.
+
+ @param DeviceNode Points to the device node to be converted.
+ @param DisplayOnly If DisplayOnly is TRUE, then the shorter text representation
+ of the display node is used, where applicable. If DisplayOnly
+ is FALSE, then the longer text representation of the display node
+ is used.
+ @param AllowShortcuts If AllowShortcuts is TRUE, then the shortcut forms of text
+ representation for a device node can be used, where applicable.
+
+ @retval a_pointer a pointer to the allocated text representation of the device node data
+ @retval NULL if DeviceNode is NULL or there was insufficient memory.
+
+**/
+typedef
+CHAR16 *
+(EFIAPI *EFI_DEVICE_PATH_TO_TEXT_NODE)(
+ IN CONST EFI_DEVICE_PATH_PROTOCOL *DeviceNode,
+ IN BOOLEAN DisplayOnly,
+ IN BOOLEAN AllowShortcuts
+ );
+
+/**
+ Convert a device path to its text representation.
+
+ @param DevicePath Points to the device path to be converted.
+ @param DisplayOnly If DisplayOnly is TRUE, then the shorter text representation
+ of the display node is used, where applicable. If DisplayOnly
+ is FALSE, then the longer text representation of the display node
+ is used.
+ @param AllowShortcuts The AllowShortcuts is FALSE, then the shortcut forms of
+ text representation for a device node cannot be used.
+
+ @retval a_pointer a pointer to the allocated text representation of the device node.
+ @retval NULL if DevicePath is NULL or there was insufficient memory.
+
+**/
+typedef
+CHAR16 *
+(EFIAPI *EFI_DEVICE_PATH_TO_TEXT_PATH)(
+ IN CONST EFI_DEVICE_PATH_PROTOCOL *DevicePath,
+ IN BOOLEAN DisplayOnly,
+ IN BOOLEAN AllowShortcuts
+ );
+
+///
+/// This protocol converts device paths and device nodes to text.
+///
+typedef struct {
+ EFI_DEVICE_PATH_TO_TEXT_NODE ConvertDeviceNodeToText;
+ EFI_DEVICE_PATH_TO_TEXT_PATH ConvertDevicePathToText;
+} EFI_DEVICE_PATH_TO_TEXT_PROTOCOL;
+
+extern EFI_GUID gEfiDevicePathToTextProtocolGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/DevicePathUtilities.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/DevicePathUtilities.h
new file mode 100644
index 0000000000..bcc515f9c8
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/DevicePathUtilities.h
@@ -0,0 +1,185 @@
+/** @file
+ EFI_DEVICE_PATH_UTILITIES_PROTOCOL as defined in UEFI 2.0.
+ Use to create and manipulate device paths and device nodes.
+
+ Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __DEVICE_PATH_UTILITIES_PROTOCOL_H__
+#define __DEVICE_PATH_UTILITIES_PROTOCOL_H__
+
+///
+/// Device Path Utilities protocol
+///
+#define EFI_DEVICE_PATH_UTILITIES_PROTOCOL_GUID \
+ { \
+ 0x379be4e, 0xd706, 0x437d, {0xb0, 0x37, 0xed, 0xb8, 0x2f, 0xb7, 0x72, 0xa4 } \
+ }
+
+/**
+ Returns the size of the device path, in bytes.
+
+ @param DevicePath Points to the start of the EFI device path.
+
+ @return Size Size of the specified device path, in bytes, including the end-of-path tag.
+ @retval 0 DevicePath is NULL
+
+**/
+typedef
+UINTN
+(EFIAPI *EFI_DEVICE_PATH_UTILS_GET_DEVICE_PATH_SIZE)(
+ IN CONST EFI_DEVICE_PATH_PROTOCOL *DevicePath
+ );
+
+/**
+ Create a duplicate of the specified path.
+
+ @param DevicePath Points to the source EFI device path.
+
+ @retval Pointer A pointer to the duplicate device path.
+ @retval NULL insufficient memory or DevicePath is NULL
+
+**/
+typedef
+EFI_DEVICE_PATH_PROTOCOL *
+(EFIAPI *EFI_DEVICE_PATH_UTILS_DUP_DEVICE_PATH)(
+ IN CONST EFI_DEVICE_PATH_PROTOCOL *DevicePath
+ );
+
+/**
+ Create a new path by appending the second device path to the first.
+ If Src1 is NULL and Src2 is non-NULL, then a duplicate of Src2 is returned.
+ If Src1 is non-NULL and Src2 is NULL, then a duplicate of Src1 is returned.
+ If Src1 and Src2 are both NULL, then a copy of an end-of-device-path is returned.
+
+ @param Src1 Points to the first device path.
+ @param Src2 Points to the second device path.
+
+ @retval Pointer A pointer to the newly created device path.
+ @retval NULL Memory could not be allocated
+
+**/
+typedef
+EFI_DEVICE_PATH_PROTOCOL *
+(EFIAPI *EFI_DEVICE_PATH_UTILS_APPEND_PATH)(
+ IN CONST EFI_DEVICE_PATH_PROTOCOL *Src1,
+ IN CONST EFI_DEVICE_PATH_PROTOCOL *Src2
+ );
+
+/**
+ Creates a new path by appending the device node to the device path.
+ If DeviceNode is NULL then a copy of DevicePath is returned.
+ If DevicePath is NULL then a copy of DeviceNode, followed by an end-of-device path device node is returned.
+ If both DeviceNode and DevicePath are NULL then a copy of an end-of-device-path device node is returned.
+
+ @param DevicePath Points to the device path.
+ @param DeviceNode Points to the device node.
+
+ @retval Pointer A pointer to the allocated device node.
+ @retval NULL There was insufficient memory.
+
+**/
+typedef
+EFI_DEVICE_PATH_PROTOCOL *
+(EFIAPI *EFI_DEVICE_PATH_UTILS_APPEND_NODE)(
+ IN CONST EFI_DEVICE_PATH_PROTOCOL *DevicePath,
+ IN CONST EFI_DEVICE_PATH_PROTOCOL *DeviceNode
+ );
+
+/**
+ Creates a new path by appending the specified device path instance to the specified device path.
+
+ @param DevicePath Points to the device path. If NULL, then ignored.
+ @param DevicePathInstance Points to the device path instance.
+
+ @retval Pointer A pointer to the newly created device path
+ @retval NULL Memory could not be allocated or DevicePathInstance is NULL.
+
+**/
+typedef
+EFI_DEVICE_PATH_PROTOCOL *
+(EFIAPI *EFI_DEVICE_PATH_UTILS_APPEND_INSTANCE)(
+ IN CONST EFI_DEVICE_PATH_PROTOCOL *DevicePath,
+ IN CONST EFI_DEVICE_PATH_PROTOCOL *DevicePathInstance
+ );
+
+/**
+ Creates a copy of the current device path instance and returns a pointer to the next device path
+ instance.
+
+ @param DevicePathInstance On input, this holds the pointer to the current device path
+ instance. On output, this holds the pointer to the next
+ device path instance or NULL if there are no more device
+ path instances in the device path.
+ @param DevicePathInstanceSize On output, this holds the size of the device path instance,
+ in bytes or zero, if DevicePathInstance is NULL.
+ If NULL, then the instance size is not output.
+
+ @retval Pointer A pointer to the copy of the current device path instance.
+ @retval NULL DevicePathInstace was NULL on entry or there was insufficient memory.
+
+**/
+typedef
+EFI_DEVICE_PATH_PROTOCOL *
+(EFIAPI *EFI_DEVICE_PATH_UTILS_GET_NEXT_INSTANCE)(
+ IN OUT EFI_DEVICE_PATH_PROTOCOL **DevicePathInstance,
+ OUT UINTN *DevicePathInstanceSize
+ );
+
+/**
+ Creates a device node
+
+ @param NodeType NodeType is the device node type (EFI_DEVICE_PATH.Type) for
+ the new device node.
+ @param NodeSubType NodeSubType is the device node sub-type
+ EFI_DEVICE_PATH.SubType) for the new device node.
+ @param NodeLength NodeLength is the length of the device node
+ (EFI_DEVICE_PATH.Length) for the new device node.
+
+ @retval Pointer A pointer to the newly created device node.
+ @retval NULL NodeLength is less than
+ the size of the header or there was insufficient memory.
+
+**/
+typedef
+EFI_DEVICE_PATH_PROTOCOL *
+(EFIAPI *EFI_DEVICE_PATH_UTILS_CREATE_NODE)(
+ IN UINT8 NodeType,
+ IN UINT8 NodeSubType,
+ IN UINT16 NodeLength
+ );
+
+/**
+ Returns whether a device path is multi-instance.
+
+ @param DevicePath Points to the device path. If NULL, then ignored.
+
+ @retval TRUE The device path has more than one instance
+ @retval FALSE The device path is empty or contains only a single instance.
+
+**/
+typedef
+BOOLEAN
+(EFIAPI *EFI_DEVICE_PATH_UTILS_IS_MULTI_INSTANCE)(
+ IN CONST EFI_DEVICE_PATH_PROTOCOL *DevicePath
+ );
+
+///
+/// This protocol is used to creates and manipulates device paths and device nodes.
+///
+typedef struct {
+ EFI_DEVICE_PATH_UTILS_GET_DEVICE_PATH_SIZE GetDevicePathSize;
+ EFI_DEVICE_PATH_UTILS_DUP_DEVICE_PATH DuplicateDevicePath;
+ EFI_DEVICE_PATH_UTILS_APPEND_PATH AppendDevicePath;
+ EFI_DEVICE_PATH_UTILS_APPEND_NODE AppendDeviceNode;
+ EFI_DEVICE_PATH_UTILS_APPEND_INSTANCE AppendDevicePathInstance;
+ EFI_DEVICE_PATH_UTILS_GET_NEXT_INSTANCE GetNextDevicePathInstance;
+ EFI_DEVICE_PATH_UTILS_IS_MULTI_INSTANCE IsDevicePathMultiInstance;
+ EFI_DEVICE_PATH_UTILS_CREATE_NODE CreateDeviceNode;
+} EFI_DEVICE_PATH_UTILITIES_PROTOCOL;
+
+extern EFI_GUID gEfiDevicePathUtilitiesProtocolGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/Dhcp4.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/Dhcp4.h
new file mode 100644
index 0000000000..fec8fea998
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/Dhcp4.h
@@ -0,0 +1,762 @@
+/** @file
+ EFI_DHCP4_PROTOCOL as defined in UEFI 2.0.
+ EFI_DHCP4_SERVICE_BINDING_PROTOCOL as defined in UEFI 2.0.
+ These protocols are used to collect configuration information for the EFI IPv4 Protocol
+ drivers and to provide DHCPv4 server and PXE boot server discovery services.
+
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Revision Reference:
+ This Protocol was introduced in UEFI Specification 2.0.
+
+**/
+
+#ifndef __EFI_DHCP4_PROTOCOL_H__
+#define __EFI_DHCP4_PROTOCOL_H__
+
+#define EFI_DHCP4_PROTOCOL_GUID \
+ { \
+ 0x8a219718, 0x4ef5, 0x4761, {0x91, 0xc8, 0xc0, 0xf0, 0x4b, 0xda, 0x9e, 0x56 } \
+ }
+
+#define EFI_DHCP4_SERVICE_BINDING_PROTOCOL_GUID \
+ { \
+ 0x9d9a39d8, 0xbd42, 0x4a73, {0xa4, 0xd5, 0x8e, 0xe9, 0x4b, 0xe1, 0x13, 0x80 } \
+ }
+
+typedef struct _EFI_DHCP4_PROTOCOL EFI_DHCP4_PROTOCOL;
+
+#pragma pack(1)
+typedef struct {
+ ///
+ /// DHCP option code.
+ ///
+ UINT8 OpCode;
+ ///
+ /// Length of the DHCP option data. Not present if OpCode is 0 or 255.
+ ///
+ UINT8 Length;
+ ///
+ /// Start of the DHCP option data. Not present if OpCode is 0 or 255 or if Length is zero.
+ ///
+ UINT8 Data[1];
+} EFI_DHCP4_PACKET_OPTION;
+#pragma pack()
+
+#pragma pack(1)
+///
+/// EFI_DHCP4_PACKET defines the format of DHCPv4 packets. See RFC 2131 for more information.
+///
+typedef struct {
+ UINT8 OpCode;
+ UINT8 HwType;
+ UINT8 HwAddrLen;
+ UINT8 Hops;
+ UINT32 Xid;
+ UINT16 Seconds;
+ UINT16 Reserved;
+ EFI_IPv4_ADDRESS ClientAddr; ///< Client IP address from client.
+ EFI_IPv4_ADDRESS YourAddr; ///< Client IP address from server.
+ EFI_IPv4_ADDRESS ServerAddr; ///< IP address of next server in bootstrap.
+ EFI_IPv4_ADDRESS GatewayAddr; ///< Relay agent IP address.
+ UINT8 ClientHwAddr[16]; ///< Client hardware address.
+ CHAR8 ServerName[64];
+ CHAR8 BootFileName[128];
+} EFI_DHCP4_HEADER;
+#pragma pack()
+
+#pragma pack(1)
+typedef struct {
+ ///
+ /// Size of the EFI_DHCP4_PACKET buffer.
+ ///
+ UINT32 Size;
+ ///
+ /// Length of the EFI_DHCP4_PACKET from the first byte of the Header field
+ /// to the last byte of the Option[] field.
+ ///
+ UINT32 Length;
+
+ struct {
+ ///
+ /// DHCP packet header.
+ ///
+ EFI_DHCP4_HEADER Header;
+ ///
+ /// DHCP magik cookie in network byte order.
+ ///
+ UINT32 Magik;
+ ///
+ /// Start of the DHCP packed option data.
+ ///
+ UINT8 Option[1];
+ } Dhcp4;
+} EFI_DHCP4_PACKET;
+#pragma pack()
+
+typedef enum {
+ ///
+ /// The EFI DHCPv4 Protocol driver is stopped.
+ ///
+ Dhcp4Stopped = 0x0,
+ ///
+ /// The EFI DHCPv4 Protocol driver is inactive.
+ ///
+ Dhcp4Init = 0x1,
+ ///
+ /// The EFI DHCPv4 Protocol driver is collecting DHCP offer packets from DHCP servers.
+ ///
+ Dhcp4Selecting = 0x2,
+ ///
+ /// The EFI DHCPv4 Protocol driver has sent the request to the DHCP server and is waiting for a response.
+ ///
+ Dhcp4Requesting = 0x3,
+ ///
+ /// The DHCP configuration has completed.
+ ///
+ Dhcp4Bound = 0x4,
+ ///
+ /// The DHCP configuration is being renewed and another request has
+ /// been sent out, but it has not received a response from the server yet.
+ ///
+ Dhcp4Renewing = 0x5,
+ ///
+ /// The DHCP configuration has timed out and the EFI DHCPv4
+ /// Protocol driver is trying to extend the lease time.
+ ///
+ Dhcp4Rebinding = 0x6,
+ ///
+ /// The EFI DHCPv4 Protocol driver was initialized with a previously
+ /// allocated or known IP address.
+ ///
+ Dhcp4InitReboot = 0x7,
+ ///
+ /// The EFI DHCPv4 Protocol driver is seeking to reuse the previously
+ /// allocated IP address by sending a request to the DHCP server.
+ ///
+ Dhcp4Rebooting = 0x8
+} EFI_DHCP4_STATE;
+
+typedef enum {
+ ///
+ /// The packet to start the configuration sequence is about to be sent.
+ ///
+ Dhcp4SendDiscover = 0x01,
+ ///
+ /// A reply packet was just received.
+ ///
+ Dhcp4RcvdOffer = 0x02,
+ ///
+ /// It is time for Dhcp4Callback to select an offer.
+ ///
+ Dhcp4SelectOffer = 0x03,
+ ///
+ /// A request packet is about to be sent.
+ ///
+ Dhcp4SendRequest = 0x04,
+ ///
+ /// A DHCPACK packet was received and will be passed to Dhcp4Callback.
+ ///
+ Dhcp4RcvdAck = 0x05,
+ ///
+ /// A DHCPNAK packet was received and will be passed to Dhcp4Callback.
+ ///
+ Dhcp4RcvdNak = 0x06,
+ ///
+ /// A decline packet is about to be sent.
+ ///
+ Dhcp4SendDecline = 0x07,
+ ///
+ /// The DHCP configuration process has completed. No packet is associated with this event.
+ ///
+ Dhcp4BoundCompleted = 0x08,
+ ///
+ /// It is time to enter the Dhcp4Renewing state and to contact the server
+ /// that originally issued the network address. No packet is associated with this event.
+ ///
+ Dhcp4EnterRenewing = 0x09,
+ ///
+ /// It is time to enter the Dhcp4Rebinding state and to contact any server.
+ /// No packet is associated with this event.
+ ///
+ Dhcp4EnterRebinding = 0x0a,
+ ///
+ /// The configured IP address was lost either because the lease has expired,
+ /// the user released the configuration, or a DHCPNAK packet was received in
+ /// the Dhcp4Renewing or Dhcp4Rebinding state. No packet is associated with this event.
+ ///
+ Dhcp4AddressLost = 0x0b,
+ ///
+ /// The DHCP process failed because a DHCPNAK packet was received or the user
+ /// aborted the DHCP process at a time when the configuration was not available yet.
+ /// No packet is associated with this event.
+ ///
+ Dhcp4Fail = 0x0c
+} EFI_DHCP4_EVENT;
+
+/**
+ Callback routine.
+
+ EFI_DHCP4_CALLBACK is provided by the consumer of the EFI DHCPv4 Protocol driver
+ to intercept events that occurred in the configuration process. This structure
+ provides advanced control of each state transition of the DHCP process. The
+ returned status code determines the behavior of the EFI DHCPv4 Protocol driver.
+ There are three possible returned values, which are described in the following
+ table.
+
+ @param This The pointer to the EFI DHCPv4 Protocol instance that is used to
+ configure this callback function.
+ @param Context The pointer to the context that is initialized by
+ EFI_DHCP4_PROTOCOL.Configure().
+ @param CurrentState The current operational state of the EFI DHCPv4 Protocol
+ driver.
+ @param Dhcp4Event The event that occurs in the current state, which usually means a
+ state transition.
+ @param Packet The DHCP packet that is going to be sent or already received.
+ @param NewPacket The packet that is used to replace the above Packet.
+
+ @retval EFI_SUCCESS Tells the EFI DHCPv4 Protocol driver to continue the DHCP process.
+ When it is in the Dhcp4Selecting state, it tells the EFI DHCPv4 Protocol
+ driver to stop collecting additional packets. The driver will exit
+ the Dhcp4Selecting state and enter the Dhcp4Requesting state.
+ @retval EFI_NOT_READY Only used in the Dhcp4Selecting state. The EFI DHCPv4 Protocol
+ driver will continue to wait for more packets until the retry
+ timeout expires.
+ @retval EFI_ABORTED Tells the EFI DHCPv4 Protocol driver to abort the current process and
+ return to the Dhcp4Init or Dhcp4InitReboot state.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_DHCP4_CALLBACK)(
+ IN EFI_DHCP4_PROTOCOL *This,
+ IN VOID *Context,
+ IN EFI_DHCP4_STATE CurrentState,
+ IN EFI_DHCP4_EVENT Dhcp4Event,
+ IN EFI_DHCP4_PACKET *Packet OPTIONAL,
+ OUT EFI_DHCP4_PACKET **NewPacket OPTIONAL
+ );
+
+typedef struct {
+ ///
+ /// The number of times to try sending a packet during the Dhcp4SendDiscover
+ /// event and waiting for a response during the Dhcp4RcvdOffer event.
+ /// Set to zero to use the default try counts and timeout values.
+ ///
+ UINT32 DiscoverTryCount;
+ ///
+ /// The maximum amount of time (in seconds) to wait for returned packets in each
+ /// of the retries. Timeout values of zero will default to a timeout value
+ /// of one second. Set to NULL to use default timeout values.
+ ///
+ UINT32 *DiscoverTimeout;
+ ///
+ /// The number of times to try sending a packet during the Dhcp4SendRequest event
+ /// and waiting for a response during the Dhcp4RcvdAck event before accepting
+ /// failure. Set to zero to use the default try counts and timeout values.
+ ///
+ UINT32 RequestTryCount;
+ ///
+ /// The maximum amount of time (in seconds) to wait for return packets in each of the retries.
+ /// Timeout values of zero will default to a timeout value of one second.
+ /// Set to NULL to use default timeout values.
+ ///
+ UINT32 *RequestTimeout;
+ ///
+ /// For a DHCPDISCOVER, setting this parameter to the previously allocated IP
+ /// address will cause the EFI DHCPv4 Protocol driver to enter the Dhcp4InitReboot state.
+ /// And set this field to 0.0.0.0 to enter the Dhcp4Init state.
+ /// For a DHCPINFORM this parameter should be set to the client network address
+ /// which was assigned to the client during a DHCPDISCOVER.
+ ///
+ EFI_IPv4_ADDRESS ClientAddress;
+ ///
+ /// The callback function to intercept various events that occurred in
+ /// the DHCP configuration process. Set to NULL to ignore all those events.
+ ///
+ EFI_DHCP4_CALLBACK Dhcp4Callback;
+ ///
+ /// The pointer to the context that will be passed to Dhcp4Callback when it is called.
+ ///
+ VOID *CallbackContext;
+ ///
+ /// Number of DHCP options in the OptionList.
+ ///
+ UINT32 OptionCount;
+ ///
+ /// List of DHCP options to be included in every packet that is sent during the
+ /// Dhcp4SendDiscover event. Pad options are appended automatically by DHCP driver
+ /// in outgoing DHCP packets. If OptionList itself contains pad option, they are
+ /// ignored by the driver. OptionList can be freed after EFI_DHCP4_PROTOCOL.Configure()
+ /// returns. Ignored if OptionCount is zero.
+ ///
+ EFI_DHCP4_PACKET_OPTION **OptionList;
+} EFI_DHCP4_CONFIG_DATA;
+
+typedef struct {
+ ///
+ /// The EFI DHCPv4 Protocol driver operating state.
+ ///
+ EFI_DHCP4_STATE State;
+ ///
+ /// The configuration data of the current EFI DHCPv4 Protocol driver instance.
+ ///
+ EFI_DHCP4_CONFIG_DATA ConfigData;
+ ///
+ /// The client IP address that was acquired from the DHCP server. If it is zero,
+ /// the DHCP acquisition has not completed yet and the following fields in this structure are undefined.
+ ///
+ EFI_IPv4_ADDRESS ClientAddress;
+ ///
+ /// The local hardware address.
+ ///
+ EFI_MAC_ADDRESS ClientMacAddress;
+ ///
+ /// The server IP address that is providing the DHCP service to this client.
+ ///
+ EFI_IPv4_ADDRESS ServerAddress;
+ ///
+ /// The router IP address that was acquired from the DHCP server.
+ /// May be zero if the server does not offer this address.
+ ///
+ EFI_IPv4_ADDRESS RouterAddress;
+ ///
+ /// The subnet mask of the connected network that was acquired from the DHCP server.
+ ///
+ EFI_IPv4_ADDRESS SubnetMask;
+ ///
+ /// The lease time (in 1-second units) of the configured IP address.
+ /// The value 0xFFFFFFFF means that the lease time is infinite.
+ /// A default lease of 7 days is used if the DHCP server does not provide a value.
+ ///
+ UINT32 LeaseTime;
+ ///
+ /// The cached latest DHCPACK or DHCPNAK or BOOTP REPLY packet. May be NULL if no packet is cached.
+ ///
+ EFI_DHCP4_PACKET *ReplyPacket;
+} EFI_DHCP4_MODE_DATA;
+
+typedef struct {
+ ///
+ /// Alternate listening address. It can be a unicast, multicast, or broadcast address.
+ ///
+ EFI_IPv4_ADDRESS ListenAddress;
+ ///
+ /// The subnet mask of above listening unicast/broadcast IP address.
+ /// Ignored if ListenAddress is a multicast address.
+ ///
+ EFI_IPv4_ADDRESS SubnetMask;
+ ///
+ /// Alternate station source (or listening) port number.
+ /// If zero, then the default station port number (68) will be used.
+ ///
+ UINT16 ListenPort;
+} EFI_DHCP4_LISTEN_POINT;
+
+typedef struct {
+ ///
+ /// The completion status of transmitting and receiving.
+ ///
+ EFI_STATUS Status;
+ ///
+ /// If not NULL, the event that will be signaled when the collection process
+ /// completes. If NULL, this function will busy-wait until the collection process competes.
+ ///
+ EFI_EVENT CompletionEvent;
+ ///
+ /// The pointer to the server IP address. This address may be a unicast, multicast, or broadcast address.
+ ///
+ EFI_IPv4_ADDRESS RemoteAddress;
+ ///
+ /// The server listening port number. If zero, the default server listening port number (67) will be used.
+ ///
+ UINT16 RemotePort;
+ ///
+ /// The pointer to the gateway address to override the existing setting.
+ ///
+ EFI_IPv4_ADDRESS GatewayAddress;
+ ///
+ /// The number of entries in ListenPoints. If zero, the default station address and port number 68 are used.
+ ///
+ UINT32 ListenPointCount;
+ ///
+ /// An array of station address and port number pairs that are used as receiving filters.
+ /// The first entry is also used as the source address and source port of the outgoing packet.
+ ///
+ EFI_DHCP4_LISTEN_POINT *ListenPoints;
+ ///
+ /// The number of seconds to collect responses. Zero is invalid.
+ ///
+ UINT32 TimeoutValue;
+ ///
+ /// The pointer to the packet to be transmitted.
+ ///
+ EFI_DHCP4_PACKET *Packet;
+ ///
+ /// Number of received packets.
+ ///
+ UINT32 ResponseCount;
+ ///
+ /// The pointer to the allocated list of received packets.
+ ///
+ EFI_DHCP4_PACKET *ResponseList;
+} EFI_DHCP4_TRANSMIT_RECEIVE_TOKEN;
+
+/**
+ Returns the current operating mode and cached data packet for the EFI DHCPv4 Protocol driver.
+
+ The GetModeData() function returns the current operating mode and cached data
+ packet for the EFI DHCPv4 Protocol driver.
+
+ @param This The pointer to the EFI_DHCP4_PROTOCOL instance.
+ @param Dhcp4ModeData The pointer to storage for the EFI_DHCP4_MODE_DATA structure.
+
+ @retval EFI_SUCCESS The mode data was returned.
+ @retval EFI_INVALID_PARAMETER This is NULL.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_DHCP4_GET_MODE_DATA)(
+ IN EFI_DHCP4_PROTOCOL *This,
+ OUT EFI_DHCP4_MODE_DATA *Dhcp4ModeData
+ );
+
+/**
+ Initializes, changes, or resets the operational settings for the EFI DHCPv4 Protocol driver.
+
+ The Configure() function is used to initialize, change, or reset the operational
+ settings of the EFI DHCPv4 Protocol driver for the communication device on which
+ the EFI DHCPv4 Service Binding Protocol is installed. This function can be
+ successfully called only if both of the following are true:
+ * This instance of the EFI DHCPv4 Protocol driver is in the Dhcp4Stopped, Dhcp4Init,
+ Dhcp4InitReboot, or Dhcp4Bound states.
+ * No other EFI DHCPv4 Protocol driver instance that is controlled by this EFI
+ DHCPv4 Service Binding Protocol driver instance has configured this EFI DHCPv4
+ Protocol driver.
+ When this driver is in the Dhcp4Stopped state, it can transfer into one of the
+ following two possible initial states:
+ * Dhcp4Init
+ * Dhcp4InitReboot.
+ The driver can transfer into these states by calling Configure() with a non-NULL
+ Dhcp4CfgData. The driver will transfer into the appropriate state based on the
+ supplied client network address in the ClientAddress parameter and DHCP options
+ in the OptionList parameter as described in RFC 2131.
+ When Configure() is called successfully while Dhcp4CfgData is set to NULL, the
+ default configuring data will be reset in the EFI DHCPv4 Protocol driver and
+ the state of the EFI DHCPv4 Protocol driver will not be changed. If one instance
+ wants to make it possible for another instance to configure the EFI DHCPv4 Protocol
+ driver, it must call this function with Dhcp4CfgData set to NULL.
+
+ @param This The pointer to the EFI_DHCP4_PROTOCOL instance.
+ @param Dhcp4CfgData The pointer to the EFI_DHCP4_CONFIG_DATA.
+
+ @retval EFI_SUCCESS The EFI DHCPv4 Protocol driver is now in the Dhcp4Init or
+ Dhcp4InitReboot state, if the original state of this driver
+ was Dhcp4Stopped, Dhcp4Init,Dhcp4InitReboot, or Dhcp4Bound
+ and the value of Dhcp4CfgData was not NULL.
+ Otherwise, the state was left unchanged.
+ @retval EFI_ACCESS_DENIED This instance of the EFI DHCPv4 Protocol driver was not in the
+ Dhcp4Stopped, Dhcp4Init, Dhcp4InitReboot, or Dhcp4Bound state;
+ Or onother instance of this EFI DHCPv4 Protocol driver is already
+ in a valid configured state.
+ @retval EFI_INVALID_PARAMETER One or more following conditions are TRUE:
+ This is NULL.
+ DiscoverTryCount > 0 and DiscoverTimeout is NULL
+ RequestTryCount > 0 and RequestTimeout is NULL.
+ OptionCount >0 and OptionList is NULL.
+ ClientAddress is not a valid unicast address.
+ @retval EFI_OUT_OF_RESOURCES Required system resources could not be allocated.
+ @retval EFI_DEVICE_ERROR An unexpected system or network error occurred.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_DHCP4_CONFIGURE)(
+ IN EFI_DHCP4_PROTOCOL *This,
+ IN EFI_DHCP4_CONFIG_DATA *Dhcp4CfgData OPTIONAL
+ );
+
+/**
+ Starts the DHCP configuration process.
+
+ The Start() function starts the DHCP configuration process. This function can
+ be called only when the EFI DHCPv4 Protocol driver is in the Dhcp4Init or
+ Dhcp4InitReboot state.
+ If the DHCP process completes successfully, the state of the EFI DHCPv4 Protocol
+ driver will be transferred through Dhcp4Selecting and Dhcp4Requesting to the
+ Dhcp4Bound state. The CompletionEvent will then be signaled if it is not NULL.
+ If the process aborts, either by the user or by some unexpected network error,
+ the state is restored to the Dhcp4Init state. The Start() function can be called
+ again to restart the process.
+ Refer to RFC 2131 for precise state transitions during this process. At the
+ time when each event occurs in this process, the callback function that was set
+ by EFI_DHCP4_PROTOCOL.Configure() will be called and the user can take this
+ opportunity to control the process.
+
+ @param This The pointer to the EFI_DHCP4_PROTOCOL instance.
+ @param CompletionEvent If not NULL, it indicates the event that will be signaled when the
+ EFI DHCPv4 Protocol driver is transferred into the
+ Dhcp4Bound state or when the DHCP process is aborted.
+ EFI_DHCP4_PROTOCOL.GetModeData() can be called to
+ check the completion status. If NULL,
+ EFI_DHCP4_PROTOCOL.Start() will wait until the driver
+ is transferred into the Dhcp4Bound state or the process fails.
+
+ @retval EFI_SUCCESS The DHCP configuration process has started, or it has completed
+ when CompletionEvent is NULL.
+ @retval EFI_NOT_STARTED The EFI DHCPv4 Protocol driver is in the Dhcp4Stopped
+ state. EFI_DHCP4_PROTOCOL. Configure() needs to be called.
+ @retval EFI_INVALID_PARAMETER This is NULL.
+ @retval EFI_OUT_OF_RESOURCES Required system resources could not be allocated.
+ @retval EFI_TIMEOUT The DHCP configuration process failed because no response was
+ received from the server within the specified timeout value.
+ @retval EFI_ABORTED The user aborted the DHCP process.
+ @retval EFI_ALREADY_STARTED Some other EFI DHCPv4 Protocol instance already started the
+ DHCP process.
+ @retval EFI_DEVICE_ERROR An unexpected system or network error occurred.
+ @retval EFI_NO_MEDIA There was a media error.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_DHCP4_START)(
+ IN EFI_DHCP4_PROTOCOL *This,
+ IN EFI_EVENT CompletionEvent OPTIONAL
+ );
+
+/**
+ Extends the lease time by sending a request packet.
+
+ The RenewRebind() function is used to manually extend the lease time when the
+ EFI DHCPv4 Protocol driver is in the Dhcp4Bound state, and the lease time has
+ not expired yet. This function will send a request packet to the previously
+ found server (or to any server when RebindRequest is TRUE) and transfer the
+ state into the Dhcp4Renewing state (or Dhcp4Rebinding when RebindingRequest is
+ TRUE). When a response is received, the state is returned to Dhcp4Bound.
+ If no response is received before the try count is exceeded (the RequestTryCount
+ field that is specified in EFI_DHCP4_CONFIG_DATA) but before the lease time that
+ was issued by the previous server expires, the driver will return to the Dhcp4Bound
+ state, and the previous configuration is restored. The outgoing and incoming packets
+ can be captured by the EFI_DHCP4_CALLBACK function.
+
+ @param This The pointer to the EFI_DHCP4_PROTOCOL instance.
+ @param RebindRequest If TRUE, this function broadcasts the request packets and enters
+ the Dhcp4Rebinding state. Otherwise, it sends a unicast
+ request packet and enters the Dhcp4Renewing state.
+ @param CompletionEvent If not NULL, this event is signaled when the renew/rebind phase
+ completes or some error occurs.
+ EFI_DHCP4_PROTOCOL.GetModeData() can be called to
+ check the completion status. If NULL,
+ EFI_DHCP4_PROTOCOL.RenewRebind() will busy-wait
+ until the DHCP process finishes.
+
+ @retval EFI_SUCCESS The EFI DHCPv4 Protocol driver is now in the
+ Dhcp4Renewing state or is back to the Dhcp4Bound state.
+ @retval EFI_NOT_STARTED The EFI DHCPv4 Protocol driver is in the Dhcp4Stopped
+ state. EFI_DHCP4_PROTOCOL.Configure() needs to
+ be called.
+ @retval EFI_INVALID_PARAMETER This is NULL.
+ @retval EFI_TIMEOUT There was no response from the server when the try count was
+ exceeded.
+ @retval EFI_ACCESS_DENIED The driver is not in the Dhcp4Bound state.
+ @retval EFI_DEVICE_ERROR An unexpected system or network error occurred.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_DHCP4_RENEW_REBIND)(
+ IN EFI_DHCP4_PROTOCOL *This,
+ IN BOOLEAN RebindRequest,
+ IN EFI_EVENT CompletionEvent OPTIONAL
+ );
+
+/**
+ Releases the current address configuration.
+
+ The Release() function releases the current configured IP address by doing either
+ of the following:
+ * Sending a DHCPRELEASE packet when the EFI DHCPv4 Protocol driver is in the
+ Dhcp4Bound state
+ * Setting the previously assigned IP address that was provided with the
+ EFI_DHCP4_PROTOCOL.Configure() function to 0.0.0.0 when the driver is in
+ Dhcp4InitReboot state
+ After a successful call to this function, the EFI DHCPv4 Protocol driver returns
+ to the Dhcp4Init state, and any subsequent incoming packets will be discarded silently.
+
+ @param This The pointer to the EFI_DHCP4_PROTOCOL instance.
+
+ @retval EFI_SUCCESS The EFI DHCPv4 Protocol driver is now in the Dhcp4Init phase.
+ @retval EFI_INVALID_PARAMETER This is NULL.
+ @retval EFI_ACCESS_DENIED The EFI DHCPv4 Protocol driver is not Dhcp4InitReboot state.
+ @retval EFI_DEVICE_ERROR An unexpected system or network error occurred.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_DHCP4_RELEASE)(
+ IN EFI_DHCP4_PROTOCOL *This
+ );
+
+/**
+ Stops the current address configuration.
+
+ The Stop() function is used to stop the DHCP configuration process. After this
+ function is called successfully, the EFI DHCPv4 Protocol driver is transferred
+ into the Dhcp4Stopped state. EFI_DHCP4_PROTOCOL.Configure() needs to be called
+ before DHCP configuration process can be started again. This function can be
+ called when the EFI DHCPv4 Protocol driver is in any state.
+
+ @param This The pointer to the EFI_DHCP4_PROTOCOL instance.
+
+ @retval EFI_SUCCESS The EFI DHCPv4 Protocol driver is now in the Dhcp4Stopped phase.
+ @retval EFI_INVALID_PARAMETER This is NULL.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_DHCP4_STOP)(
+ IN EFI_DHCP4_PROTOCOL *This
+ );
+
+/**
+ Builds a DHCP packet, given the options to be appended or deleted or replaced.
+
+ The Build() function is used to assemble a new packet from the original packet
+ by replacing or deleting existing options or appending new options. This function
+ does not change any state of the EFI DHCPv4 Protocol driver and can be used at
+ any time.
+
+ @param This The pointer to the EFI_DHCP4_PROTOCOL instance.
+ @param SeedPacket Initial packet to be used as a base for building new packet.
+ @param DeleteCount Number of opcodes in the DeleteList.
+ @param DeleteList List of opcodes to be deleted from the seed packet.
+ Ignored if DeleteCount is zero.
+ @param AppendCount Number of entries in the OptionList.
+ @param AppendList The pointer to a DHCP option list to be appended to SeedPacket.
+ If SeedPacket also contains options in this list, they are
+ replaced by new options (except pad option). Ignored if
+ AppendCount is zero. Type EFI_DHCP4_PACKET_OPTION
+ @param NewPacket The pointer to storage for the pointer to the new allocated packet.
+ Use the EFI Boot Service FreePool() on the resulting pointer
+ when done with the packet.
+
+ @retval EFI_SUCCESS The new packet was built.
+ @retval EFI_OUT_OF_RESOURCES Storage for the new packet could not be allocated.
+ @retval EFI_INVALID_PARAMETER One or more of the following conditions is TRUE:
+ This is NULL.
+ SeedPacket is NULL.
+ SeedPacket is not a well-formed DHCP packet.
+ AppendCount is not zero and AppendList is NULL.
+ DeleteCount is not zero and DeleteList is NULL.
+ NewPacket is NULL
+ Both DeleteCount and AppendCount are zero and
+ NewPacket is not NULL.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_DHCP4_BUILD)(
+ IN EFI_DHCP4_PROTOCOL *This,
+ IN EFI_DHCP4_PACKET *SeedPacket,
+ IN UINT32 DeleteCount,
+ IN UINT8 *DeleteList OPTIONAL,
+ IN UINT32 AppendCount,
+ IN EFI_DHCP4_PACKET_OPTION *AppendList[] OPTIONAL,
+ OUT EFI_DHCP4_PACKET **NewPacket
+ );
+
+/**
+ Transmits a DHCP formatted packet and optionally waits for responses.
+
+ The TransmitReceive() function is used to transmit a DHCP packet and optionally
+ wait for the response from servers. This function does not change the state of
+ the EFI DHCPv4 Protocol driver. It can be used at any time because of this.
+
+ @param This The pointer to the EFI_DHCP4_PROTOCOL instance.
+ @param Token The pointer to the EFI_DHCP4_TRANSMIT_RECEIVE_TOKEN structure.
+
+ @retval EFI_SUCCESS The packet was successfully queued for transmission.
+ @retval EFI_INVALID_PARAMETER One or more of the following conditions is TRUE:
+ This is NULL.
+ Token.RemoteAddress is zero.
+ Token.Packet is NULL.
+ Token.Packet is not a well-formed DHCP packet.
+ The transaction ID in Token.Packet is in use by another DHCP process.
+ @retval EFI_NOT_READY The previous call to this function has not finished yet. Try to call
+ this function after collection process completes.
+ @retval EFI_NO_MAPPING The default station address is not available yet.
+ @retval EFI_OUT_OF_RESOURCES Required system resources could not be allocated.
+ @retval EFI_UNSUPPORTED The implementation doesn't support this function
+ @retval Others Some other unexpected error occurred.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_DHCP4_TRANSMIT_RECEIVE)(
+ IN EFI_DHCP4_PROTOCOL *This,
+ IN EFI_DHCP4_TRANSMIT_RECEIVE_TOKEN *Token
+ );
+
+/**
+ Parses the packed DHCP option data.
+
+ The Parse() function is used to retrieve the option list from a DHCP packet.
+ If *OptionCount isn't zero, and there is enough space for all the DHCP options
+ in the Packet, each element of PacketOptionList is set to point to somewhere in
+ the Packet->Dhcp4.Option where a new DHCP option begins. If RFC3396 is supported,
+ the caller should reassemble the parsed DHCP options to get the final result.
+ If *OptionCount is zero or there isn't enough space for all of them, the number
+ of DHCP options in the Packet is returned in OptionCount.
+
+ @param This The pointer to the EFI_DHCP4_PROTOCOL instance.
+ @param Packet The pointer to packet to be parsed.
+ @param OptionCount On input, the number of entries in the PacketOptionList.
+ On output, the number of entries that were written into the
+ PacketOptionList.
+ @param PacketOptionList A list of packet option entries to be filled in. End option or pad
+ options are not included.
+
+ @retval EFI_SUCCESS The packet was successfully parsed.
+ @retval EFI_INVALID_PARAMETER One or more of the following conditions is TRUE:
+ This is NULL.
+ The packet is NULL.
+ The packet is not a well-formed DHCP packet.
+ OptionCount is NULL.
+ @retval EFI_BUFFER_TOO_SMALL One or more of the following conditions is TRUE:
+ 1) *OptionCount is smaller than the number of options that
+ were found in the Packet.
+ 2) PacketOptionList is NULL.
+ @retval EFI_OUT_OF_RESOURCE The packet failed to parse because of a resource shortage.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_DHCP4_PARSE)(
+ IN EFI_DHCP4_PROTOCOL *This,
+ IN EFI_DHCP4_PACKET *Packet,
+ IN OUT UINT32 *OptionCount,
+ OUT EFI_DHCP4_PACKET_OPTION *PacketOptionList[] OPTIONAL
+ );
+
+///
+/// This protocol is used to collect configuration information for the EFI IPv4 Protocol drivers
+/// and to provide DHCPv4 server and PXE boot server discovery services.
+///
+struct _EFI_DHCP4_PROTOCOL {
+ EFI_DHCP4_GET_MODE_DATA GetModeData;
+ EFI_DHCP4_CONFIGURE Configure;
+ EFI_DHCP4_START Start;
+ EFI_DHCP4_RENEW_REBIND RenewRebind;
+ EFI_DHCP4_RELEASE Release;
+ EFI_DHCP4_STOP Stop;
+ EFI_DHCP4_BUILD Build;
+ EFI_DHCP4_TRANSMIT_RECEIVE TransmitReceive;
+ EFI_DHCP4_PARSE Parse;
+};
+
+extern EFI_GUID gEfiDhcp4ProtocolGuid;
+extern EFI_GUID gEfiDhcp4ServiceBindingProtocolGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/Dhcp6.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/Dhcp6.h
new file mode 100644
index 0000000000..5672353ffd
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/Dhcp6.h
@@ -0,0 +1,780 @@
+/** @file
+ UEFI Dynamic Host Configuration Protocol 6 Definition, which is used to get IPv6
+ addresses and other configuration parameters from DHCPv6 servers.
+
+ Copyright (c) 2008 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Revision Reference:
+ This Protocol is introduced in UEFI Specification 2.2
+
+**/
+
+#ifndef __EFI_DHCP6_PROTOCOL_H__
+#define __EFI_DHCP6_PROTOCOL_H__
+
+#define EFI_DHCP6_PROTOCOL_GUID \
+ { \
+ 0x87c8bad7, 0x595, 0x4053, {0x82, 0x97, 0xde, 0xde, 0x39, 0x5f, 0x5d, 0x5b } \
+ }
+
+#define EFI_DHCP6_SERVICE_BINDING_PROTOCOL_GUID \
+ { \
+ 0x9fb9a8a1, 0x2f4a, 0x43a6, {0x88, 0x9c, 0xd0, 0xf7, 0xb6, 0xc4, 0x7a, 0xd5 } \
+ }
+
+typedef struct _EFI_DHCP6_PROTOCOL EFI_DHCP6_PROTOCOL;
+
+typedef enum {
+ ///
+ /// The EFI DHCPv6 Protocol instance is configured, and start() needs
+ /// to be called
+ ///
+ Dhcp6Init = 0x0,
+ ///
+ /// A Solicit packet is sent out to discover DHCPv6 server, and the EFI
+ /// DHCPv6 Protocol instance is collecting Advertise packets.
+ ///
+ Dhcp6Selecting = 0x1,
+ ///
+ /// A Request is sent out to the DHCPv6 server, and the EFI DHCPv6
+ /// Protocol instance is waiting for Reply packet.
+ ///
+ Dhcp6Requesting = 0x2,
+ ///
+ /// A Decline packet is sent out to indicate one or more addresses of the
+ /// configured IA are in use by another node, and the EFI DHCPv6.
+ /// Protocol instance is waiting for Reply packet.
+ ///
+ Dhcp6Declining = 0x3,
+ ///
+ /// A Confirm packet is sent out to confirm the IPv6 addresses of the
+ /// configured IA, and the EFI DHCPv6 Protocol instance is waiting for Reply packet.
+ ///
+ Dhcp6Confirming = 0x4,
+ ///
+ /// A Release packet is sent out to release one or more IPv6 addresses of
+ /// the configured IA, and the EFI DHCPv6 Protocol instance is waiting for Reply packet.
+ ///
+ Dhcp6Releasing = 0x5,
+ ///
+ /// The DHCPv6 S.A.R.R process is completed for the configured IA.
+ ///
+ Dhcp6Bound = 0x6,
+ ///
+ /// A Renew packet is sent out to extend lifetime for the IPv6 addresses of
+ /// the configured IA, and the EFI DHCPv6 Protocol instance is waiting for Reply packet.
+ ///
+ Dhcp6Renewing = 0x7,
+ ///
+ /// A Rebind packet is sent out to extend lifetime for the IPv6 addresses of
+ /// the configured IA, and the EFI DHCPv6 Protocol instance is waiting for Reply packet.
+ ///
+ Dhcp6Rebinding = 0x8
+} EFI_DHCP6_STATE;
+
+typedef enum {
+ ///
+ /// A Solicit packet is about to be sent. The packet is passed to Dhcp6Callback and
+ /// can be modified or replaced in Dhcp6Callback.
+ ///
+ Dhcp6SendSolicit = 0x0,
+ ///
+ /// An Advertise packet is received and will be passed to Dhcp6Callback.
+ ///
+ Dhcp6RcvdAdvertise = 0x1,
+ ///
+ /// It is time for Dhcp6Callback to determine whether select the default Advertise
+ /// packet by RFC 3315 policy, or overwrite it by specific user policy.
+ ///
+ Dhcp6SelectAdvertise = 0x2,
+ ///
+ /// A Request packet is about to be sent. The packet is passed to Dhcp6Callback and
+ /// can be modified or replaced in Dhcp6Callback.
+ ///
+ Dhcp6SendRequest = 0x3,
+ ///
+ /// A Reply packet is received and will be passed to Dhcp6Callback.
+ ///
+ Dhcp6RcvdReply = 0x4,
+ ///
+ /// A Reconfigure packet is received and will be passed to Dhcp6Callback.
+ ///
+ Dhcp6RcvdReconfigure = 0x5,
+ ///
+ /// A Decline packet is about to be sent. The packet is passed to Dhcp6Callback and
+ /// can be modified or replaced in Dhcp6Callback.
+ ///
+ Dhcp6SendDecline = 0x6,
+ ///
+ /// A Confirm packet is about to be sent. The packet is passed to Dhcp6Callback and
+ /// can be modified or replaced in Dhcp6Callback.
+ ///
+ Dhcp6SendConfirm = 0x7,
+ ///
+ /// A Release packet is about to be sent. The packet is passed to Dhcp6Callback and
+ /// can be modified or replaced in Dhcp6Callback.
+ ///
+ Dhcp6SendRelease = 0x8,
+ ///
+ /// A Renew packet is about to be sent. The packet is passed to Dhcp6Callback and
+ /// can be modified or replaced in Dhcp6Callback.
+ ///
+ Dhcp6EnterRenewing = 0x9,
+ ///
+ /// A Rebind packet is about to be sent. The packet is passed to Dhcp6Callback and
+ /// can be modified or replaced in Dhcp6Callback.
+ ///
+ Dhcp6EnterRebinding = 0xa
+} EFI_DHCP6_EVENT;
+
+///
+/// An IA which carries assigned not temporary address.
+///
+#define EFI_DHCP6_IA_TYPE_NA 3
+///
+/// An IA which carries assigned temporary address.
+///
+#define EFI_DHCP6_IA_TYPE_TA 4
+
+#pragma pack(1)
+///
+/// EFI_DHCP6_PACKET_OPTION
+/// defines the format of the DHCPv6 option, See RFC 3315 for more information.
+/// This data structure is used to reference option data that is packed in the DHCPv6 packet.
+///
+typedef struct {
+ ///
+ /// The DHCPv6 option code, stored in network order.
+ ///
+ UINT16 OpCode;
+ ///
+ /// Length of the DHCPv6 option data, stored in network order.
+ /// From the first byte to the last byte of the Data field.
+ ///
+ UINT16 OpLen;
+ ///
+ /// The data for the DHCPv6 option, stored in network order.
+ ///
+ UINT8 Data[1];
+} EFI_DHCP6_PACKET_OPTION;
+
+///
+/// EFI_DHCP6_HEADER
+/// defines the format of the DHCPv6 header. See RFC 3315 for more information.
+///
+typedef struct {
+ ///
+ /// The DHCPv6 transaction ID.
+ ///
+ UINT32 MessageType : 8;
+ ///
+ /// The DHCPv6 message type.
+ ///
+ UINT32 TransactionId : 24;
+} EFI_DHCP6_HEADER;
+
+///
+/// EFI_DHCP6_PACKET
+/// defines the format of the DHCPv6 packet. See RFC 3315 for more information.
+///
+typedef struct {
+ ///
+ /// Size of the EFI_DHCP6_PACKET buffer.
+ ///
+ UINT32 Size;
+ ///
+ /// Length of the EFI_DHCP6_PACKET from the first byte of the Header field to the last
+ /// byte of the Option[] field.
+ ///
+ UINT32 Length;
+ struct {
+ ///
+ /// The DHCPv6 packet header.
+ ///
+ EFI_DHCP6_HEADER Header;
+ ///
+ /// Start of the DHCPv6 packed option data.
+ ///
+ UINT8 Option[1];
+ } Dhcp6;
+} EFI_DHCP6_PACKET;
+
+#pragma pack()
+
+typedef struct {
+ ///
+ /// Length of DUID in octects.
+ ///
+ UINT16 Length;
+ ///
+ /// Array of DUID octects.
+ ///
+ UINT8 Duid[1];
+} EFI_DHCP6_DUID;
+
+typedef struct {
+ ///
+ /// Initial retransmission timeout.
+ ///
+ UINT32 Irt;
+ ///
+ /// Maximum retransmission count for one packet. If Mrc is zero, there's no upper limit
+ /// for retransmission count.
+ ///
+ UINT32 Mrc;
+ ///
+ /// Maximum retransmission timeout for each retry. It's the upper bound of the number of
+ /// retransmission timeout. If Mrt is zero, there is no upper limit for retransmission
+ /// timeout.
+ ///
+ UINT32 Mrt;
+ ///
+ /// Maximum retransmission duration for one packet. It's the upper bound of the numbers
+ /// the client may retransmit a message. If Mrd is zero, there's no upper limit for
+ /// retransmission duration.
+ ///
+ UINT32 Mrd;
+} EFI_DHCP6_RETRANSMISSION;
+
+typedef struct {
+ ///
+ /// The IPv6 address.
+ ///
+ EFI_IPv6_ADDRESS IpAddress;
+ ///
+ /// The preferred lifetime in unit of seconds for the IPv6 address.
+ ///
+ UINT32 PreferredLifetime;
+ ///
+ /// The valid lifetime in unit of seconds for the IPv6 address.
+ ///
+ UINT32 ValidLifetime;
+} EFI_DHCP6_IA_ADDRESS;
+
+typedef struct {
+ UINT16 Type; ///< Type for an IA.
+ UINT32 IaId; ///< The identifier for an IA.
+} EFI_DHCP6_IA_DESCRIPTOR;
+
+typedef struct {
+ ///
+ /// The descriptor for IA.
+ ///
+ EFI_DHCP6_IA_DESCRIPTOR Descriptor;
+ ///
+ /// The state of the configured IA.
+ ///
+ EFI_DHCP6_STATE State;
+ ///
+ /// Pointer to the cached latest Reply packet. May be NULL if no packet is cached.
+ ///
+ EFI_DHCP6_PACKET *ReplyPacket;
+ ///
+ /// Number of IPv6 addresses of the configured IA.
+ ///
+ UINT32 IaAddressCount;
+ ///
+ /// List of the IPv6 addresses of the configured IA. When the state of the configured IA is
+ /// in Dhcp6Bound, Dhcp6Renewing and Dhcp6Rebinding, the IPv6 addresses are usable.
+ ///
+ EFI_DHCP6_IA_ADDRESS IaAddress[1];
+} EFI_DHCP6_IA;
+
+typedef struct {
+ ///
+ /// Pointer to the DHCPv6 unique identifier. The caller is responsible for freeing this buffer.
+ ///
+ EFI_DHCP6_DUID *ClientId;
+ ///
+ /// Pointer to the configured IA of current instance. The caller can free this buffer after
+ /// using it.
+ ///
+ EFI_DHCP6_IA *Ia;
+} EFI_DHCP6_MODE_DATA;
+
+/**
+ EFI_DHCP6_CALLBACK is provided by the consumer of the EFI DHCPv6 Protocol instance to
+ intercept events that occurs in the DHCPv6 S.A.R.R process.
+
+ @param[in] This Pointer to the EFI_DHCP6_PROTOCOL instance that is used to configure this
+ callback function.
+ @param[in] Context Pointer to the context that is initialized by EFI_DHCP6_PROTOCOL.Configure().
+ @param[in] CurrentState The current state of the configured IA.
+ @param[in] Dhcp6Event The event that occurs in the current state, which usually means a state transition.
+ @param[in] Packet Pointer to the DHCPv6 packet that is about to be sent or has been received.
+ The EFI DHCPv6 Protocol instance is responsible for freeing the buffer.
+ @param[out] NewPacket Pointer to the new DHCPv6 packet to overwrite the Packet. NewPacket can not
+ share the buffer with Packet. If *NewPacket is not NULL, the EFI DHCPv6
+ Protocol instance is responsible for freeing the buffer.
+
+ @retval EFI_SUCCESS Tell the EFI DHCPv6 Protocol instance to continue the DHCPv6 S.A.R.R process.
+ @retval EFI_ABORTED Tell the EFI DHCPv6 Protocol instance to abort the DHCPv6 S.A.R.R process,
+ and the state of the configured IA will be transferred to Dhcp6Init.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_DHCP6_CALLBACK)(
+ IN EFI_DHCP6_PROTOCOL *This,
+ IN VOID *Context,
+ IN EFI_DHCP6_STATE CurrentState,
+ IN EFI_DHCP6_EVENT Dhcp6Event,
+ IN EFI_DHCP6_PACKET *Packet,
+ OUT EFI_DHCP6_PACKET **NewPacket OPTIONAL
+ );
+
+typedef struct {
+ ///
+ /// The callback function is to intercept various events that occur in the DHCPv6 S.A.R.R
+ /// process. Set to NULL to ignore all those events.
+ ///
+ EFI_DHCP6_CALLBACK Dhcp6Callback;
+ ///
+ /// Pointer to the context that will be passed to Dhcp6Callback.
+ ///
+ VOID *CallbackContext;
+ ///
+ /// Number of the DHCPv6 options in the OptionList.
+ ///
+ UINT32 OptionCount;
+ ///
+ /// List of the DHCPv6 options to be included in Solicit and Request packet. The buffer
+ /// can be freed after EFI_DHCP6_PROTOCOL.Configure() returns. Ignored if
+ /// OptionCount is zero. OptionList should not contain Client Identifier option
+ /// and any IA option, which will be appended by EFI DHCPv6 Protocol instance
+ /// automatically.
+ ///
+ EFI_DHCP6_PACKET_OPTION **OptionList;
+ ///
+ /// The descriptor for the IA of the EFI DHCPv6 Protocol instance.
+ ///
+ EFI_DHCP6_IA_DESCRIPTOR IaDescriptor;
+ ///
+ /// If not NULL, the event will be signaled when any IPv6 address information of the
+ /// configured IA is updated, including IPv6 address, preferred lifetime and valid
+ /// lifetime, or the DHCPv6 S.A.R.R process fails. Otherwise, Start(),
+ /// renewrebind(), decline(), release() and stop() will be blocking
+ /// operations, and they will wait for the exchange process completion or failure.
+ ///
+ EFI_EVENT IaInfoEvent;
+ ///
+ /// If TRUE, the EFI DHCPv6 Protocol instance is willing to accept Reconfigure packet.
+ /// Otherwise, it will ignore it. Reconfigure Accept option can not be specified through
+ /// OptionList parameter.
+ ///
+ BOOLEAN ReconfigureAccept;
+ ///
+ /// If TRUE, the EFI DHCPv6 Protocol instance will send Solicit packet with Rapid
+ /// Commit option. Otherwise, Rapid Commit option will not be included in Solicit
+ /// packet. Rapid Commit option can not be specified through OptionList parameter.
+ ///
+ BOOLEAN RapidCommit;
+ ///
+ /// Parameter to control Solicit packet retransmission behavior. The
+ /// buffer can be freed after EFI_DHCP6_PROTOCOL.Configure() returns.
+ ///
+ EFI_DHCP6_RETRANSMISSION *SolicitRetransmission;
+} EFI_DHCP6_CONFIG_DATA;
+
+/**
+ EFI_DHCP6_INFO_CALLBACK is provided by the consumer of the EFI DHCPv6 Protocol
+ instance to intercept events that occurs in the DHCPv6 Information Request exchange process.
+
+ @param[in] This Pointer to the EFI_DHCP6_PROTOCOL instance that is used to configure this
+ callback function.
+ @param[in] Context Pointer to the context that is initialized in the EFI_DHCP6_PROTOCOL.InfoRequest().
+ @param[in] Packet Pointer to Reply packet that has been received. The EFI DHCPv6 Protocol instance is
+ responsible for freeing the buffer.
+
+ @retval EFI_SUCCESS Tell the EFI DHCPv6 Protocol instance to finish Information Request exchange process.
+ @retval EFI_NOT_READY Tell the EFI DHCPv6 Protocol instance to continue Information Request exchange process.
+ @retval EFI_ABORTED Tell the EFI DHCPv6 Protocol instance to abort the Information Request exchange process.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_DHCP6_INFO_CALLBACK)(
+ IN EFI_DHCP6_PROTOCOL *This,
+ IN VOID *Context,
+ IN EFI_DHCP6_PACKET *Packet
+ );
+
+/**
+ Retrieve the current operating mode data and configuration data for the EFI DHCPv6 Protocol instance.
+
+ @param[in] This Pointer to the EFI_DHCP6_PROTOCOL instance.
+ @param[out] Dhcp6ModeData Pointer to the DHCPv6 mode data structure. The caller is responsible for freeing this
+ structure and each reference buffer.
+ @param[out] Dhcp6ConfigData Pointer to the DHCPv6 configuration data structure. The caller is responsible for
+ freeing this structure and each reference buffer.
+
+ @retval EFI_SUCCESS The mode data was returned.
+ @retval EFI_ACCESS_DENIED The EFI DHCPv6 Protocol instance has not been configured when Dhcp6ConfigData is not NULL.
+ @retval EFI_INVALID_PARAMETER One or more following conditions are TRUE:
+ - This is NULL.
+ - Both Dhcp6ConfigData and Dhcp6ModeData are NULL.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_DHCP6_GET_MODE_DATA)(
+ IN EFI_DHCP6_PROTOCOL *This,
+ OUT EFI_DHCP6_MODE_DATA *Dhcp6ModeData OPTIONAL,
+ OUT EFI_DHCP6_CONFIG_DATA *Dhcp6ConfigData OPTIONAL
+ );
+
+/**
+ Initialize or clean up the configuration data for the EFI DHCPv6 Protocol instance.
+
+ The Configure() function is used to initialize or clean up the configuration data of the EFI
+ DHCPv6 Protocol instance.
+ - When Dhcp6CfgData is not NULL and Configure() is called successfully, the
+ configuration data will be initialized in the EFI DHCPv6 Protocol instance and the state of the
+ configured IA will be transferred into Dhcp6Init.
+ - When Dhcp6CfgData is NULL and Configure() is called successfully, the configuration
+ data will be cleaned up and no IA will be associated with the EFI DHCPv6 Protocol instance.
+
+ To update the configuration data for an EFI DCHPv6 Protocol instance, the original data must be
+ cleaned up before setting the new configuration data.
+
+ @param[in] This Pointer to the EFI_DHCP6_PROTOCOL instance.
+ @param[in] Dhcp6CfgData Pointer to the DHCPv6 configuration data structure.
+
+ @retval EFI_SUCCESS The mode data was returned.
+ @retval EFI_INVALID_PARAMETER One or more following conditions are TRUE
+ - This is NULL.
+ - OptionCount > 0 and OptionList is NULL.
+ - OptionList is not NULL, and Client Id option, Reconfigure Accept option,
+ Rapid Commit option or any IA option is specified in the OptionList.
+ - IaDescriptor.Type is neither EFI_DHCP6_IA_TYPE_NA nor EFI_DHCP6_IA_TYPE_NA.
+ - IaDescriptor is not unique.
+ - Both IaInfoEvent and SolicitRetransimssion are NULL.
+ - SolicitRetransmission is not NULL, and both SolicitRetransimssion->Mrc and
+ SolicitRetransmission->Mrd are zero.
+ @retval EFI_ACCESS_DENIED The EFI DHCPv6 Protocol instance has been already configured
+ when Dhcp6CfgData is not NULL.
+ The EFI DHCPv6 Protocol instance has already started the
+ DHCPv6 S.A.R.R when Dhcp6CfgData is NULL.
+ @retval EFI_OUT_OF_RESOURCES Required system resources could not be allocated.
+ @retval EFI_DEVICE_ERROR An unexpected system or network error occurred.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_DHCP6_CONFIGURE)(
+ IN EFI_DHCP6_PROTOCOL *This,
+ IN EFI_DHCP6_CONFIG_DATA *Dhcp6CfgData OPTIONAL
+ );
+
+/**
+ Start the DHCPv6 S.A.R.R process.
+
+ The Start() function starts the DHCPv6 S.A.R.R process. This function can be called only when
+ the state of the configured IA is in the Dhcp6Init state. If the DHCPv6 S.A.R.R process completes
+ successfully, the state of the configured IA will be transferred through Dhcp6Selecting and
+ Dhcp6Requesting to Dhcp6Bound state. The update of the IPv6 addresses will be notified through
+ EFI_DHCP6_CONFIG_DATA.IaInfoEvent. At the time when each event occurs in this process, the
+ callback function set by EFI_DHCP6_PROTOCOL.Configure() will be called and the user can take
+ this opportunity to control the process. If EFI_DHCP6_CONFIG_DATA.IaInfoEvent is NULL, the
+ Start() function call is a blocking operation. It will return after the DHCPv6 S.A.R.R process
+ completes or aborted by users. If the process is aborted by system or network error, the state of
+ the configured IA will be transferred to Dhcp6Init. The Start() function can be called again to
+ restart the process.
+
+ @param[in] This Pointer to the EFI_DHCP6_PROTOCOL instance.
+
+ @retval EFI_SUCCESS The DHCPv6 S.A.R.R process is completed and at least one IPv6
+ address has been bound to the configured IA when
+ EFI_DHCP6_CONFIG_DATA.IaInfoEvent is NULL.
+ The DHCPv6 S.A.R.R process is started when
+ EFI_DHCP6_CONFIG_DATA.IaInfoEvent is not NULL.
+ @retval EFI_ACCESS_DENIED The EFI DHCPv6 Child instance hasn't been configured.
+ @retval EFI_INVALID_PARAMETER This is NULL.
+ @retval EFI_OUT_OF_RESOURCES Required system resources could not be allocated.
+ @retval EFI_ALREADY_STARTED The DHCPv6 S.A.R.R process has already started.
+ @retval EFI_DEVICE_ERROR An unexpected network or system error occurred.
+ @retval EFI_NO_RESPONSE The DHCPv6 S.A.R.R process failed because of no response.
+ @retval EFI_NO_MAPPING No IPv6 address has been bound to the configured IA after the
+ DHCPv6 S.A.R.R process.
+ @retval EFI_ABORTED The DHCPv6 S.A.R.R process aborted by user.
+ @retval EFI_NO_MEDIA There was a media error.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_DHCP6_START)(
+ IN EFI_DHCP6_PROTOCOL *This
+ );
+
+/**
+ Request configuration information without the assignment of any IA addresses of the client.
+
+ The InfoRequest() function is used to request configuration information without the assignment
+ of any IPv6 address of the client. Client sends out Information Request packet to obtain
+ the required configuration information, and DHCPv6 server responds with Reply packet containing
+ the information for the client. The received Reply packet will be passed to the user by
+ ReplyCallback function. If user returns EFI_NOT_READY from ReplyCallback, the EFI DHCPv6
+ Protocol instance will continue to receive other Reply packets unless timeout according to
+ the Retransmission parameter. Otherwise, the Information Request exchange process will be
+ finished successfully if user returns EFI_SUCCESS from ReplyCallback.
+
+ @param[in] This Pointer to the EFI_DHCP6_PROTOCOL instance.
+ @param[in] SendClientId If TRUE, the EFI DHCPv6 Protocol instance will build Client
+ Identifier option and include it into Information Request
+ packet. If FALSE, Client Identifier option will not be included.
+ Client Identifier option can not be specified through OptionList
+ parameter.
+ @param[in] OptionRequest Pointer to the Option Request option in the Information Request
+ packet. Option Request option can not be specified through
+ OptionList parameter.
+ @param[in] OptionCount Number of options in OptionList.
+ @param[in] OptionList List of other DHCPv6 options. These options will be appended
+ to the Option Request option. The caller is responsible for
+ freeing this buffer. Type is defined in EFI_DHCP6_PROTOCOL.GetModeData().
+ @param[in] Retransmission Parameter to control Information Request packet retransmission
+ behavior. The buffer can be freed after EFI_DHCP6_PROTOCOL.InfoRequest()
+ returns.
+ @param[in] TimeoutEvent If not NULL, this event is signaled when the information request
+ exchange aborted because of no response. If NULL, the function
+ call is a blocking operation; and it will return after the
+ information-request exchange process finish or aborted by users.
+ @param[in] ReplyCallback The callback function is to intercept various events that occur
+ in the Information Request exchange process. It should not be
+ set to NULL.
+ @param[in] CallbackContext Pointer to the context that will be passed to ReplyCallback.
+
+ @retval EFI_SUCCESS The DHCPv6 S.A.R.R process is completed and at least one IPv6
+ @retval EFI_SUCCESS The DHCPv6 information request exchange process completed
+ when TimeoutEvent is NULL. Information Request packet has been
+ sent to DHCPv6 server when TimeoutEvent is not NULL.
+ @retval EFI_INVALID_PARAMETER One or more following conditions are TRUE:
+ - This is NULL.
+ - OptionRequest is NULL or OptionRequest->OpCode is invalid.
+ - OptionCount > 0 and OptionList is NULL.
+ - OptionList is not NULL, and Client Identify option or
+ Option Request option is specified in the OptionList.
+ - Retransimssion is NULL.
+ - Both Retransimssion->Mrc and Retransmission->Mrd are zero.
+ - ReplyCallback is NULL.
+ @retval EFI_DEVICE_ERROR An unexpected network or system error occurred.
+ @retval EFI_NO_RESPONSE The DHCPv6 information request exchange process failed
+ because of no response, or not all requested-options are
+ responded by DHCPv6 servers when Timeout happened.
+ @retval EFI_ABORTED The DHCPv6 information request exchange process aborted by user.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_DHCP6_INFO_REQUEST)(
+ IN EFI_DHCP6_PROTOCOL *This,
+ IN BOOLEAN SendClientId,
+ IN EFI_DHCP6_PACKET_OPTION *OptionRequest,
+ IN UINT32 OptionCount,
+ IN EFI_DHCP6_PACKET_OPTION *OptionList[] OPTIONAL,
+ IN EFI_DHCP6_RETRANSMISSION *Retransmission,
+ IN EFI_EVENT TimeoutEvent OPTIONAL,
+ IN EFI_DHCP6_INFO_CALLBACK ReplyCallback,
+ IN VOID *CallbackContext OPTIONAL
+ );
+
+/**
+ Manually extend the valid and preferred lifetimes for the IPv6 addresses of the configured
+ IA and update other configuration parameters by sending Renew or Rebind packet.
+
+ The RenewRebind() function is used to manually extend the valid and preferred lifetimes for the
+ IPv6 addresses of the configured IA and update other configuration parameters by sending Renew or
+ Rebind packet.
+ - When RebindRequest is FALSE and the state of the configured IA is Dhcp6Bound, it
+ will send Renew packet to the previously DHCPv6 server and transfer the state of the configured
+ IA to Dhcp6Renewing. If valid Reply packet received, the state transfers to Dhcp6Bound
+ and the valid and preferred timer restarts. If fails, the state transfers to Dhcp6Bound but the
+ timer continues.
+ - When RebindRequest is TRUE and the state of the configured IA is Dhcp6Bound, it will
+ send Rebind packet. If valid Reply packet received, the state transfers to Dhcp6Bound and the
+ valid and preferred timer restarts. If fails, the state transfers to Dhcp6Init and the IA can't
+ be used.
+
+ @param[in] This Pointer to the EFI_DHCP4_PROTOCOL instance.
+ @param[in] RebindRequest If TRUE, it will send Rebind packet and enter the Dhcp6Rebinding state.
+ Otherwise, it will send Renew packet and enter the Dhcp6Renewing state.
+
+ @retval EFI_SUCCESS The DHCPv6 renew/rebind exchange process has completed and at
+ least one IPv6 address of the configured IA has been bound again
+ when EFI_DHCP6_CONFIG_DATA.IaInfoEvent is NULL.
+ The EFI DHCPv6 Protocol instance has sent Renew or Rebind packet
+ when EFI_DHCP6_CONFIG_DATA.IaInfoEvent is not NULL.
+ @retval EFI_ACCESS_DENIED The EFI DHCPv6 Child instance hasn't been configured, or the state
+ of the configured IA is not in Dhcp6Bound.
+ @retval EFI_ALREADY_STARTED The state of the configured IA has already entered Dhcp6Renewing
+ when RebindRequest is FALSE.
+ The state of the configured IA has already entered Dhcp6Rebinding
+ when RebindRequest is TRUE.
+ @retval EFI_INVALID_PARAMETER This is NULL.
+ @retval EFI_DEVICE_ERROR An unexpected system or system error occurred.
+ @retval EFI_NO_RESPONSE The DHCPv6 renew/rebind exchange process failed because of no response.
+ @retval EFI_NO_MAPPING No IPv6 address has been bound to the configured IA after the DHCPv6
+ renew/rebind exchange process.
+ @retval EFI_ABORTED The DHCPv6 renew/rebind exchange process aborted by user.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_DHCP6_RENEW_REBIND)(
+ IN EFI_DHCP6_PROTOCOL *This,
+ IN BOOLEAN RebindRequest
+ );
+
+/**
+ Inform that one or more IPv6 addresses assigned by a server are already in use by
+ another node.
+
+ The Decline() function is used to manually decline the assignment of IPv6 addresses, which
+ have been already used by another node. If all IPv6 addresses of the configured IA are declined
+ through this function, the state of the IA will switch through Dhcp6Declining to Dhcp6Init,
+ otherwise, the state of the IA will restore to Dhcp6Bound after the declining process. The
+ Decline() can only be called when the IA is in Dhcp6Bound state. If the
+ EFI_DHCP6_CONFIG_DATA.IaInfoEvent is NULL, this function is a blocking operation. It
+ will return after the declining process finishes, or aborted by user.
+
+ @param[in] This Pointer to the EFI_DHCP4_PROTOCOL instance.
+ @param[in] AddressCount Number of declining IPv6 addresses.
+ @param[in] Addresses Pointer to the buffer stored all the declining IPv6 addresses.
+
+ @retval EFI_SUCCESS The DHCPv6 decline exchange process has completed when
+ EFI_DHCP6_CONFIG_DATA.IaInfoEvent is NULL.
+ The EFI DHCPv6 Protocol instance has sent Decline packet when
+ EFI_DHCP6_CONFIG_DATA.IaInfoEvent is not NULL.
+ @retval EFI_INVALID_PARAMETER One or more following conditions are TRUE
+ - This is NULL.
+ - AddressCount is zero or Addresses is NULL.
+ @retval EFI_NOT_FOUND Any specified IPv6 address is not correlated with the configured IA
+ for this instance.
+ @retval EFI_ACCESS_DENIED The EFI DHCPv6 Child instance hasn't been configured, or the
+ state of the configured IA is not in Dhcp6Bound.
+ @retval EFI_DEVICE_ERROR An unexpected network or system error occurred.
+ @retval EFI_ABORTED The DHCPv6 decline exchange process aborted by user.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_DHCP6_DECLINE)(
+ IN EFI_DHCP6_PROTOCOL *This,
+ IN UINT32 AddressCount,
+ IN EFI_IPv6_ADDRESS *Addresses
+ );
+
+/**
+ Release one or more IPv6 addresses associated with the configured IA for current instance.
+
+ The Release() function is used to manually release the one or more IPv6 address. If AddressCount
+ is zero, it will release all IPv6 addresses of the configured IA. If all IPv6 addresses of the IA
+ are released through this function, the state of the IA will switch through Dhcp6Releasing to
+ Dhcp6Init, otherwise, the state of the IA will restore to Dhcp6Bound after the releasing process.
+ The Release() can only be called when the IA is in Dhcp6Bound state. If the
+ EFI_DHCP6_CONFIG_DATA.IaInfoEvent is NULL, the function is a blocking operation. It will return
+ after the releasing process finishes, or aborted by user.
+
+ @param[in] This Pointer to the EFI_DHCP6_PROTOCOL instance.
+ @param[in] AddressCount Number of releasing IPv6 addresses.
+ @param[in] Addresses Pointer to the buffer stored all the releasing IPv6 addresses.
+ Ignored if AddressCount is zero.
+ @retval EFI_SUCCESS The DHCPv6 release exchange process has completed when
+ EFI_DHCP6_CONFIG_DATA.IaInfoEvent is NULL.
+ The EFI DHCPv6 Protocol instance has sent Release packet when
+ EFI_DHCP6_CONFIG_DATA.IaInfoEvent is not NULL.
+ @retval EFI_INVALID_PARAMETER One or more following conditions are TRUE
+ - This is NULL.
+ - AddressCount is not zero or Addresses is NULL.
+ @retval EFI_NOT_FOUND Any specified IPv6 address is not correlated with the configured
+ IA for this instance.
+ @retval EFI_ACCESS_DENIED The EFI DHCPv6 Child instance hasn't been configured, or the
+ state of the configured IA is not in Dhcp6Bound.
+ @retval EFI_DEVICE_ERROR An unexpected network or system error occurred.
+ @retval EFI_ABORTED The DHCPv6 release exchange process aborted by user.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_DHCP6_RELEASE)(
+ IN EFI_DHCP6_PROTOCOL *This,
+ IN UINT32 AddressCount,
+ IN EFI_IPv6_ADDRESS *Addresses
+ );
+
+/**
+ Stop the DHCPv6 S.A.R.R process.
+
+ The Stop() function is used to stop the DHCPv6 S.A.R.R process. If this function is called
+ successfully, all the IPv6 addresses of the configured IA will be released and the state of
+ the configured IA will be transferred to Dhcp6Init.
+
+ @param[in] This Pointer to the EFI_DHCP6_PROTOCOL instance.
+
+ @retval EFI_SUCCESS The DHCPv6 S.A.R.R process has been stopped when
+ EFI_DHCP6_CONFIG_DATA.IaInfoEvent is NULL.
+ The EFI DHCPv6 Protocol instance has sent Release packet if
+ need release or has been stopped if needn't, when
+ EFI_DHCP6_CONFIG_DATA.IaInfoEvent is not NULL.
+ @retval EFI_INVALID_PARAMETER This is NULL.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_DHCP6_STOP)(
+ IN EFI_DHCP6_PROTOCOL *This
+ );
+
+/**
+ Parse the option data in the DHCPv6 packet.
+
+ The Parse() function is used to retrieve the option list in the DHCPv6 packet.
+
+ @param[in] This Pointer to the EFI_DHCP6_PROTOCOL instance.
+
+ @param[in] Packet Pointer to packet to be parsed.
+ @param[in] OptionCount On input, the number of entries in the PacketOptionList.
+ On output, the number of DHCPv6 options in the Packet.
+ @param[in] PacketOptionList List of pointers to the DHCPv6 options in the Packet.
+ The OpCode and OpLen in EFI_DHCP6_PACKET_OPTION are
+ both stored in network byte order.
+ @retval EFI_SUCCESS The packet was successfully parsed.
+ @retval EFI_INVALID_PARAMETER One or more following conditions are TRUE
+ - This is NULL.
+ - Packet is NULL.
+ - Packet is not a well-formed DHCPv6 packet.
+ - OptionCount is NULL.
+ - *OptionCount is not zero and PacketOptionList is NULL.
+ @retval EFI_BUFFER_TOO_SMALL *OptionCount is smaller than the number of options that were
+ found in the Packet.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_DHCP6_PARSE)(
+ IN EFI_DHCP6_PROTOCOL *This,
+ IN EFI_DHCP6_PACKET *Packet,
+ IN OUT UINT32 *OptionCount,
+ OUT EFI_DHCP6_PACKET_OPTION *PacketOptionList[] OPTIONAL
+ );
+
+///
+/// The EFI DHCPv6 Protocol is used to get IPv6 addresses and other configuration parameters
+/// from DHCPv6 servers.
+///
+struct _EFI_DHCP6_PROTOCOL {
+ EFI_DHCP6_GET_MODE_DATA GetModeData;
+ EFI_DHCP6_CONFIGURE Configure;
+ EFI_DHCP6_START Start;
+ EFI_DHCP6_INFO_REQUEST InfoRequest;
+ EFI_DHCP6_RENEW_REBIND RenewRebind;
+ EFI_DHCP6_DECLINE Decline;
+ EFI_DHCP6_RELEASE Release;
+ EFI_DHCP6_STOP Stop;
+ EFI_DHCP6_PARSE Parse;
+};
+
+extern EFI_GUID gEfiDhcp6ProtocolGuid;
+extern EFI_GUID gEfiDhcp6ServiceBindingProtocolGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/DiskInfo.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/DiskInfo.h
new file mode 100644
index 0000000000..69f559da99
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/DiskInfo.h
@@ -0,0 +1,221 @@
+/** @file
+ Provides the basic interfaces to abstract platform information regarding an
+ IDE controller.
+
+ Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Revision Reference:
+ This Protocol is defined in UEFI Platform Initialization Specification 1.6
+ Volume 5: Standards
+
+**/
+
+#ifndef __DISK_INFO_H__
+#define __DISK_INFO_H__
+
+///
+/// Global ID for EFI_DISK_INFO_PROTOCOL
+///
+#define EFI_DISK_INFO_PROTOCOL_GUID \
+ { \
+ 0xd432a67f, 0x14dc, 0x484b, {0xb3, 0xbb, 0x3f, 0x2, 0x91, 0x84, 0x93, 0x27 } \
+ }
+
+///
+/// Forward declaration for EFI_DISK_INFO_PROTOCOL
+///
+typedef struct _EFI_DISK_INFO_PROTOCOL EFI_DISK_INFO_PROTOCOL;
+
+///
+/// Global ID for an IDE interface. Used to fill in EFI_DISK_INFO_PROTOCOL.Interface
+///
+#define EFI_DISK_INFO_IDE_INTERFACE_GUID \
+ { \
+ 0x5e948fe3, 0x26d3, 0x42b5, {0xaf, 0x17, 0x61, 0x2, 0x87, 0x18, 0x8d, 0xec } \
+ }
+
+///
+/// Global ID for a SCSI interface. Used to fill in EFI_DISK_INFO_PROTOCOL.Interface
+///
+#define EFI_DISK_INFO_SCSI_INTERFACE_GUID \
+ { \
+ 0x8f74baa, 0xea36, 0x41d9, {0x95, 0x21, 0x21, 0xa7, 0xf, 0x87, 0x80, 0xbc } \
+ }
+
+///
+/// Global ID for a USB interface. Used to fill in EFI_DISK_INFO_PROTOCOL.Interface
+///
+#define EFI_DISK_INFO_USB_INTERFACE_GUID \
+ { \
+ 0xcb871572, 0xc11a, 0x47b5, {0xb4, 0x92, 0x67, 0x5e, 0xaf, 0xa7, 0x77, 0x27 } \
+ }
+
+///
+/// Global ID for an AHCI interface. Used to fill in EFI_DISK_INFO_PROTOCOL.Interface
+///
+#define EFI_DISK_INFO_AHCI_INTERFACE_GUID \
+ { \
+ 0x9e498932, 0x4abc, 0x45af, {0xa3, 0x4d, 0x2, 0x47, 0x78, 0x7b, 0xe7, 0xc6 } \
+ }
+
+///
+/// Global ID for a NVME interface. Used to fill in EFI_DISK_INFO_PROTOCOL.Interface
+///
+#define EFI_DISK_INFO_NVME_INTERFACE_GUID \
+ { \
+ 0x3ab14680, 0x5d3f, 0x4a4d, {0xbc, 0xdc, 0xcc, 0x38, 0x0, 0x18, 0xc7, 0xf7 } \
+ }
+
+///
+/// Global ID for a UFS interface. Used to fill in EFI_DISK_INFO_PROTOCOL.Interface
+///
+#define EFI_DISK_INFO_UFS_INTERFACE_GUID \
+ { \
+ 0x4b3029cc, 0x6b98, 0x47fb, { 0xbc, 0x96, 0x76, 0xdc, 0xb8, 0x4, 0x41, 0xf0 } \
+ }
+
+///
+/// Global ID for an SD/MMC interface. Used to fill in EFI_DISK_INFO_PROTOCOL.Interface
+///
+#define EFI_DISK_INFO_SD_MMC_INTERFACE_GUID \
+ { \
+ 0x8deec992, 0xd39c, 0x4a5c, { 0xab, 0x6b, 0x98, 0x6e, 0x14, 0x24, 0x2b, 0x9d } \
+ }
+
+/**
+ Provides inquiry information for the controller type.
+
+ This function is used by the IDE bus driver to get inquiry data. Data format
+ of Identify data is defined by the Interface GUID.
+
+ @param[in] This Pointer to the EFI_DISK_INFO_PROTOCOL instance.
+ @param[in,out] InquiryData Pointer to a buffer for the inquiry data.
+ @param[in,out] InquiryDataSize Pointer to the value for the inquiry data size.
+
+ @retval EFI_SUCCESS The command was accepted without any errors.
+ @retval EFI_NOT_FOUND Device does not support this data class
+ @retval EFI_DEVICE_ERROR Error reading InquiryData from device
+ @retval EFI_BUFFER_TOO_SMALL InquiryDataSize not big enough
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_DISK_INFO_INQUIRY)(
+ IN EFI_DISK_INFO_PROTOCOL *This,
+ IN OUT VOID *InquiryData,
+ IN OUT UINT32 *InquiryDataSize
+ );
+
+/**
+ Provides identify information for the controller type.
+
+ This function is used by the IDE bus driver to get identify data. Data format
+ of Identify data is defined by the Interface GUID.
+
+ @param[in] This Pointer to the EFI_DISK_INFO_PROTOCOL
+ instance.
+ @param[in,out] IdentifyData Pointer to a buffer for the identify data.
+ @param[in,out] IdentifyDataSize Pointer to the value for the identify data
+ size.
+
+ @retval EFI_SUCCESS The command was accepted without any errors.
+ @retval EFI_NOT_FOUND Device does not support this data class
+ @retval EFI_DEVICE_ERROR Error reading IdentifyData from device
+ @retval EFI_BUFFER_TOO_SMALL IdentifyDataSize not big enough
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_DISK_INFO_IDENTIFY)(
+ IN EFI_DISK_INFO_PROTOCOL *This,
+ IN OUT VOID *IdentifyData,
+ IN OUT UINT32 *IdentifyDataSize
+ );
+
+/**
+ Provides sense data information for the controller type.
+
+ This function is used by the IDE bus driver to get sense data.
+ Data format of Sense data is defined by the Interface GUID.
+
+ @param[in] This Pointer to the EFI_DISK_INFO_PROTOCOL instance.
+ @param[in,out] SenseData Pointer to the SenseData.
+ @param[in,out] SenseDataSize Size of SenseData in bytes.
+ @param[out] SenseDataNumber Pointer to the value for the sense data size.
+
+ @retval EFI_SUCCESS The command was accepted without any errors.
+ @retval EFI_NOT_FOUND Device does not support this data class.
+ @retval EFI_DEVICE_ERROR Error reading SenseData from device.
+ @retval EFI_BUFFER_TOO_SMALL SenseDataSize not big enough.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_DISK_INFO_SENSE_DATA)(
+ IN EFI_DISK_INFO_PROTOCOL *This,
+ IN OUT VOID *SenseData,
+ IN OUT UINT32 *SenseDataSize,
+ OUT UINT8 *SenseDataNumber
+ );
+
+/**
+ This function is used by the IDE bus driver to get controller information.
+
+ @param[in] This Pointer to the EFI_DISK_INFO_PROTOCOL instance.
+ @param[out] IdeChannel Pointer to the Ide Channel number. Primary or secondary.
+ @param[out] IdeDevice Pointer to the Ide Device number. Master or slave.
+
+ @retval EFI_SUCCESS IdeChannel and IdeDevice are valid.
+ @retval EFI_UNSUPPORTED This is not an IDE device.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_DISK_INFO_WHICH_IDE)(
+ IN EFI_DISK_INFO_PROTOCOL *This,
+ OUT UINT32 *IdeChannel,
+ OUT UINT32 *IdeDevice
+ );
+
+///
+/// The EFI_DISK_INFO_PROTOCOL provides controller specific information.
+///
+struct _EFI_DISK_INFO_PROTOCOL {
+ ///
+ /// A GUID that defines the format of buffers for the other member functions
+ /// of this protocol.
+ ///
+ EFI_GUID Interface;
+ ///
+ /// Return the results of the Inquiry command to a drive in InquiryData. Data
+ /// format of Inquiry data is defined by the Interface GUID.
+ ///
+ EFI_DISK_INFO_INQUIRY Inquiry;
+ ///
+ /// Return the results of the Identify command to a drive in IdentifyData. Data
+ /// format of Identify data is defined by the Interface GUID.
+ ///
+ EFI_DISK_INFO_IDENTIFY Identify;
+ ///
+ /// Return the results of the Request Sense command to a drive in SenseData. Data
+ /// format of Sense data is defined by the Interface GUID.
+ ///
+ EFI_DISK_INFO_SENSE_DATA SenseData;
+ ///
+ /// Specific controller.
+ ///
+ EFI_DISK_INFO_WHICH_IDE WhichIde;
+};
+
+extern EFI_GUID gEfiDiskInfoProtocolGuid;
+
+extern EFI_GUID gEfiDiskInfoIdeInterfaceGuid;
+extern EFI_GUID gEfiDiskInfoScsiInterfaceGuid;
+extern EFI_GUID gEfiDiskInfoUsbInterfaceGuid;
+extern EFI_GUID gEfiDiskInfoAhciInterfaceGuid;
+extern EFI_GUID gEfiDiskInfoNvmeInterfaceGuid;
+extern EFI_GUID gEfiDiskInfoUfsInterfaceGuid;
+extern EFI_GUID gEfiDiskInfoSdMmcInterfaceGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/DiskIo.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/DiskIo.h
new file mode 100644
index 0000000000..0fea8774c4
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/DiskIo.h
@@ -0,0 +1,111 @@
+/** @file
+ Disk IO protocol as defined in the UEFI 2.0 specification.
+
+ The Disk IO protocol is used to convert block oriented devices into byte
+ oriented devices. The Disk IO protocol is intended to layer on top of the
+ Block IO protocol.
+
+ Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __DISK_IO_H__
+#define __DISK_IO_H__
+
+#define EFI_DISK_IO_PROTOCOL_GUID \
+ { \
+ 0xce345171, 0xba0b, 0x11d2, {0x8e, 0x4f, 0x0, 0xa0, 0xc9, 0x69, 0x72, 0x3b } \
+ }
+
+///
+/// Protocol GUID name defined in EFI1.1.
+///
+#define DISK_IO_PROTOCOL EFI_DISK_IO_PROTOCOL_GUID
+
+typedef struct _EFI_DISK_IO_PROTOCOL EFI_DISK_IO_PROTOCOL;
+
+///
+/// Protocol defined in EFI1.1.
+///
+typedef EFI_DISK_IO_PROTOCOL EFI_DISK_IO;
+
+/**
+ Read BufferSize bytes from Offset into Buffer.
+
+ @param This Protocol instance pointer.
+ @param MediaId Id of the media, changes every time the media is replaced.
+ @param Offset The starting byte offset to read from
+ @param BufferSize Size of Buffer
+ @param Buffer Buffer containing read data
+
+ @retval EFI_SUCCESS The data was read correctly from the device.
+ @retval EFI_DEVICE_ERROR The device reported an error while performing the read.
+ @retval EFI_NO_MEDIA There is no media in the device.
+ @retval EFI_MEDIA_CHNAGED The MediaId does not matched the current device.
+ @retval EFI_INVALID_PARAMETER The read request contains device addresses that are not
+ valid for the device.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_DISK_READ)(
+ IN EFI_DISK_IO_PROTOCOL *This,
+ IN UINT32 MediaId,
+ IN UINT64 Offset,
+ IN UINTN BufferSize,
+ OUT VOID *Buffer
+ );
+
+/**
+ Writes a specified number of bytes to a device.
+
+ @param This Indicates a pointer to the calling context.
+ @param MediaId ID of the medium to be written.
+ @param Offset The starting byte offset on the logical block I/O device to write.
+ @param BufferSize The size in bytes of Buffer. The number of bytes to write to the device.
+ @param Buffer A pointer to the buffer containing the data to be written.
+
+ @retval EFI_SUCCESS The data was written correctly to the device.
+ @retval EFI_WRITE_PROTECTED The device can not be written to.
+ @retval EFI_DEVICE_ERROR The device reported an error while performing the write.
+ @retval EFI_NO_MEDIA There is no media in the device.
+ @retval EFI_MEDIA_CHNAGED The MediaId does not matched the current device.
+ @retval EFI_INVALID_PARAMETER The write request contains device addresses that are not
+ valid for the device.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_DISK_WRITE)(
+ IN EFI_DISK_IO_PROTOCOL *This,
+ IN UINT32 MediaId,
+ IN UINT64 Offset,
+ IN UINTN BufferSize,
+ IN VOID *Buffer
+ );
+
+#define EFI_DISK_IO_PROTOCOL_REVISION 0x00010000
+
+///
+/// Revision defined in EFI1.1
+///
+#define EFI_DISK_IO_INTERFACE_REVISION EFI_DISK_IO_PROTOCOL_REVISION
+
+///
+/// This protocol is used to abstract Block I/O interfaces.
+///
+struct _EFI_DISK_IO_PROTOCOL {
+ ///
+ /// The revision to which the disk I/O interface adheres. All future
+ /// revisions must be backwards compatible. If a future version is not
+ /// backwards compatible, it is not the same GUID.
+ ///
+ UINT64 Revision;
+ EFI_DISK_READ ReadDisk;
+ EFI_DISK_WRITE WriteDisk;
+};
+
+extern EFI_GUID gEfiDiskIoProtocolGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/DiskIo2.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/DiskIo2.h
new file mode 100644
index 0000000000..b209469cc6
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/DiskIo2.h
@@ -0,0 +1,166 @@
+/** @file
+ Disk I/O 2 protocol as defined in the UEFI 2.4 specification.
+
+ The Disk I/O 2 protocol defines an extension to the Disk I/O protocol to enable
+ non-blocking / asynchronous byte-oriented disk operation.
+
+ Copyright (c) 2013 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __DISK_IO2_H__
+#define __DISK_IO2_H__
+
+#define EFI_DISK_IO2_PROTOCOL_GUID \
+ { \
+ 0x151c8eae, 0x7f2c, 0x472c, 0x9e, 0x54, 0x98, 0x28, 0x19, 0x4f, 0x6a, 0x88 \
+ }
+
+typedef struct _EFI_DISK_IO2_PROTOCOL EFI_DISK_IO2_PROTOCOL;
+
+/**
+ The struct of Disk IO2 Token.
+**/
+typedef struct {
+ //
+ // If Event is NULL, then blocking I/O is performed.
+ // If Event is not NULL and non-blocking I/O is supported, then non-blocking I/O is performed,
+ // and Event will be signaled when the I/O request is completed.
+ // The caller must be prepared to handle the case where the callback associated with Event occurs
+ // before the original asynchronous I/O request call returns.
+ //
+ EFI_EVENT Event;
+
+ //
+ // Defines whether or not the signaled event encountered an error.
+ //
+ EFI_STATUS TransactionStatus;
+} EFI_DISK_IO2_TOKEN;
+
+/**
+ Terminate outstanding asynchronous requests to a device.
+
+ @param This Indicates a pointer to the calling context.
+
+ @retval EFI_SUCCESS All outstanding requests were successfully terminated.
+ @retval EFI_DEVICE_ERROR The device reported an error while performing the cancel
+ operation.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_DISK_CANCEL_EX)(
+ IN EFI_DISK_IO2_PROTOCOL *This
+ );
+
+/**
+ Reads a specified number of bytes from a device.
+
+ @param This Indicates a pointer to the calling context.
+ @param MediaId ID of the medium to be read.
+ @param Offset The starting byte offset on the logical block I/O device to read from.
+ @param Token A pointer to the token associated with the transaction.
+ If this field is NULL, synchronous/blocking IO is performed.
+ @param BufferSize The size in bytes of Buffer. The number of bytes to read from the device.
+ @param Buffer A pointer to the destination buffer for the data.
+ The caller is responsible either having implicit or explicit ownership of the buffer.
+
+ @retval EFI_SUCCESS If Event is NULL (blocking I/O): The data was read correctly from the device.
+ If Event is not NULL (asynchronous I/O): The request was successfully queued for processing.
+ Event will be signaled upon completion.
+ @retval EFI_DEVICE_ERROR The device reported an error while performing the write.
+ @retval EFI_NO_MEDIA There is no medium in the device.
+ @retval EFI_MEDIA_CHNAGED The MediaId is not for the current medium.
+ @retval EFI_INVALID_PARAMETER The read request contains device addresses that are not valid for the device.
+ @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_DISK_READ_EX)(
+ IN EFI_DISK_IO2_PROTOCOL *This,
+ IN UINT32 MediaId,
+ IN UINT64 Offset,
+ IN OUT EFI_DISK_IO2_TOKEN *Token,
+ IN UINTN BufferSize,
+ OUT VOID *Buffer
+ );
+
+/**
+ Writes a specified number of bytes to a device.
+
+ @param This Indicates a pointer to the calling context.
+ @param MediaId ID of the medium to be written.
+ @param Offset The starting byte offset on the logical block I/O device to write to.
+ @param Token A pointer to the token associated with the transaction.
+ If this field is NULL, synchronous/blocking IO is performed.
+ @param BufferSize The size in bytes of Buffer. The number of bytes to write to the device.
+ @param Buffer A pointer to the buffer containing the data to be written.
+
+ @retval EFI_SUCCESS If Event is NULL (blocking I/O): The data was written correctly to the device.
+ If Event is not NULL (asynchronous I/O): The request was successfully queued for processing.
+ Event will be signaled upon completion.
+ @retval EFI_WRITE_PROTECTED The device cannot be written to.
+ @retval EFI_DEVICE_ERROR The device reported an error while performing the write operation.
+ @retval EFI_NO_MEDIA There is no medium in the device.
+ @retval EFI_MEDIA_CHNAGED The MediaId is not for the current medium.
+ @retval EFI_INVALID_PARAMETER The write request contains device addresses that are not valid for the device.
+ @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_DISK_WRITE_EX)(
+ IN EFI_DISK_IO2_PROTOCOL *This,
+ IN UINT32 MediaId,
+ IN UINT64 Offset,
+ IN OUT EFI_DISK_IO2_TOKEN *Token,
+ IN UINTN BufferSize,
+ IN VOID *Buffer
+ );
+
+/**
+ Flushes all modified data to the physical device.
+
+ @param This Indicates a pointer to the calling context.
+ @param MediaId ID of the medium to be written.
+ @param Token A pointer to the token associated with the transaction.
+ If this field is NULL, synchronous/blocking IO is performed.
+
+ @retval EFI_SUCCESS If Event is NULL (blocking I/O): The data was flushed successfully to the device.
+ If Event is not NULL (asynchronous I/O): The request was successfully queued for processing.
+ Event will be signaled upon completion.
+ @retval EFI_WRITE_PROTECTED The device cannot be written to.
+ @retval EFI_DEVICE_ERROR The device reported an error while performing the write operation.
+ @retval EFI_NO_MEDIA There is no medium in the device.
+ @retval EFI_MEDIA_CHNAGED The MediaId is not for the current medium.
+ @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_DISK_FLUSH_EX)(
+ IN EFI_DISK_IO2_PROTOCOL *This,
+ IN OUT EFI_DISK_IO2_TOKEN *Token
+ );
+
+#define EFI_DISK_IO2_PROTOCOL_REVISION 0x00020000
+
+///
+/// This protocol is used to abstract Block I/O interfaces.
+///
+struct _EFI_DISK_IO2_PROTOCOL {
+ ///
+ /// The revision to which the disk I/O interface adheres. All future
+ /// revisions must be backwards compatible. If a future version is not
+ /// backwards compatible, it is not the same GUID.
+ ///
+ UINT64 Revision;
+ EFI_DISK_CANCEL_EX Cancel;
+ EFI_DISK_READ_EX ReadDiskEx;
+ EFI_DISK_WRITE_EX WriteDiskEx;
+ EFI_DISK_FLUSH_EX FlushDiskEx;
+};
+
+extern EFI_GUID gEfiDiskIo2ProtocolGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/Dns4.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/Dns4.h
new file mode 100644
index 0000000000..4f1739b69c
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/Dns4.h
@@ -0,0 +1,536 @@
+/** @file
+ This file defines the EFI Domain Name Service Binding Protocol interface. It is split
+ into the following two main sections:
+ DNSv4 Service Binding Protocol (DNSv4SB)
+ DNSv4 Protocol (DNSv4)
+
+ Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Revision Reference:
+ This Protocol is introduced in UEFI Specification 2.5
+
+**/
+
+#ifndef __EFI_DNS4_PROTOCOL_H__
+#define __EFI_DNS4_PROTOCOL_H__
+
+#define EFI_DNS4_SERVICE_BINDING_PROTOCOL_GUID \
+ { \
+ 0xb625b186, 0xe063, 0x44f7, {0x89, 0x5, 0x6a, 0x74, 0xdc, 0x6f, 0x52, 0xb4 } \
+ }
+
+#define EFI_DNS4_PROTOCOL_GUID \
+ { \
+ 0xae3d28cc, 0xe05b, 0x4fa1, {0xa0, 0x11, 0x7e, 0xb5, 0x5a, 0x3f, 0x14, 0x1 } \
+ }
+
+typedef struct _EFI_DNS4_PROTOCOL EFI_DNS4_PROTOCOL;
+
+///
+/// EFI_DNS4_CONFIG_DATA
+///
+typedef struct {
+ ///
+ /// Count of the DNS servers. When used with GetModeData(),
+ /// this field is the count of originally configured servers when
+ /// Configure() was called for this instance. When used with
+ /// Configure() this is the count of caller-supplied servers. If the
+ /// DnsServerListCount is zero, the DNS server configuration
+ /// will be retrieved from DHCP server automatically.
+ ///
+ UINTN DnsServerListCount;
+ ///
+ /// Pointer to DNS server list containing DnsServerListCount entries or NULL
+ /// if DnsServerListCountis 0. For Configure(), this will be NULL when there are
+ /// no caller supplied server addresses, and, the DNS instance will retrieve
+ /// DNS server from DHCP Server. The provided DNS server list is
+ /// recommended to be filled up in the sequence of preference. When
+ /// used with GetModeData(), the buffer containing the list will
+ /// be allocated by the driver implementing this protocol and must be
+ /// freed by the caller. When used with Configure(), the buffer
+ /// containing the list will be allocated and released by the caller.
+ ///
+ EFI_IPv4_ADDRESS *DnsServerList;
+ ///
+ /// Set to TRUE to use the default IP address/subnet mask and default routing table.
+ ///
+ BOOLEAN UseDefaultSetting;
+ ///
+ /// If TRUE, enable DNS cache function for this DNS instance. If FALSE, all DNS
+ /// query will not lookup local DNS cache.
+ ///
+ BOOLEAN EnableDnsCache;
+ ///
+ /// Use the protocol number defined in "Links to UEFI-Related
+ /// Documents"(http://uefi.org/uefi) under the heading "IANA
+ /// Protocol Numbers". Only TCP or UDP are supported, and other
+ /// protocol values are invalid. An implementation can choose to
+ /// support only UDP, or both TCP and UDP.
+ ///
+ UINT8 Protocol;
+ ///
+ /// If UseDefaultSetting is FALSE indicates the station address to use.
+ ///
+ EFI_IPv4_ADDRESS StationIp;
+ ///
+ /// If UseDefaultSetting is FALSE indicates the subnet mask to use.
+ ///
+ EFI_IPv4_ADDRESS SubnetMask;
+ ///
+ /// Local port number. Set to zero to use the automatically assigned port number.
+ ///
+ UINT16 LocalPort;
+ ///
+ /// Retry number if no response received after RetryInterval.
+ ///
+ UINT32 RetryCount;
+ ///
+ /// Minimum interval of retry is 2 second. If the retry interval is less than 2
+ /// seconds, then use the 2 seconds.
+ ///
+ UINT32 RetryInterval;
+} EFI_DNS4_CONFIG_DATA;
+
+///
+/// EFI_DNS4_CACHE_ENTRY
+///
+typedef struct {
+ ///
+ /// Host name.
+ ///
+ CHAR16 *HostName;
+ ///
+ /// IP address of this host.
+ ///
+ EFI_IPv4_ADDRESS *IpAddress;
+ ///
+ /// Time in second unit that this entry will remain in DNS cache. A value of zero
+ /// means that this entry is permanent. A nonzero value will override the existing
+ /// one if this entry to be added is dynamic entry. Implementations may set its
+ /// default timeout value for the dynamically created DNS cache entry after one DNS
+ /// resolve succeeds.
+ ///
+ UINT32 Timeout;
+} EFI_DNS4_CACHE_ENTRY;
+
+///
+/// EFI_DNS4_MODE_DATA
+///
+typedef struct {
+ ///
+ /// The configuration data of this instance.
+ ///
+ EFI_DNS4_CONFIG_DATA DnsConfigData;
+ ///
+ /// Number of configured DNS server. Each DNS instance has its own DNS server
+ /// configuration.
+ ///
+ UINT32 DnsServerCount;
+ ///
+ /// Pointer to common list of addresses of all configured DNS server
+ /// used by EFI_DNS4_PROTOCOL instances. List will include
+ /// DNS servers configured by this or any other EFI_DNS4_PROTOCOL instance.
+ /// The storage for this list is allocated by the driver publishing this
+ /// protocol, and must be freed by the caller.
+ ///
+ EFI_IPv4_ADDRESS *DnsServerList;
+ ///
+ /// Number of DNS Cache entries. The DNS Cache is shared among all DNS instances.
+ ///
+ UINT32 DnsCacheCount;
+ ///
+ /// Pointer to a buffer containing DnsCacheCount DNS Cache
+ /// entry structures. The storage for this list is allocated by the driver
+ /// publishing this protocol and must be freed by caller.
+ ///
+ EFI_DNS4_CACHE_ENTRY *DnsCacheList;
+} EFI_DNS4_MODE_DATA;
+
+///
+/// DNS_HOST_TO_ADDR_DATA
+///
+typedef struct {
+ ///
+ /// Number of the returned IP addresses.
+ ///
+ UINT32 IpCount;
+ ///
+ /// Pointer to the all the returned IP addresses.
+ ///
+ EFI_IPv4_ADDRESS *IpList;
+} DNS_HOST_TO_ADDR_DATA;
+
+///
+/// DNS_ADDR_TO_HOST_DATA
+///
+typedef struct {
+ ///
+ /// Pointer to the primary name for this host address. It's the caller's
+ /// responsibility to free the response memory.
+ ///
+ CHAR16 *HostName;
+} DNS_ADDR_TO_HOST_DATA;
+
+///
+/// DNS_RESOURCE_RECORD
+///
+typedef struct {
+ ///
+ /// The Owner name.
+ ///
+ CHAR8 *QName;
+ ///
+ /// The Type Code of this RR.
+ ///
+ UINT16 QType;
+ ///
+ /// The CLASS code of this RR.
+ ///
+ UINT16 QClass;
+ ///
+ /// 32 bit integer which specify the time interval that the resource record may be
+ /// cached before the source of the information should again be consulted. Zero means
+ /// this RR can not be cached.
+ ///
+ UINT32 TTL;
+ ///
+ /// 16 big integer which specify the length of RData.
+ ///
+ UINT16 DataLength;
+ ///
+ /// A string of octets that describe the resource, the format of this information
+ /// varies according to QType and QClass difference.
+ ///
+ CHAR8 *RData;
+} DNS_RESOURCE_RECORD;
+
+///
+/// DNS_GENERAL_LOOKUP_DATA
+///
+typedef struct {
+ ///
+ /// Number of returned matching RRs.
+ ///
+ UINTN RRCount;
+ ///
+ /// Pointer to the all the returned matching RRs. It's caller responsibility to free
+ /// the allocated memory to hold the returned RRs.
+ ///
+ DNS_RESOURCE_RECORD *RRList;
+} DNS_GENERAL_LOOKUP_DATA;
+
+///
+/// EFI_DNS4_COMPLETION_TOKEN
+///
+typedef struct {
+ ///
+ /// This Event will be signaled after the Status field is updated by the EFI DNS
+ /// protocol driver. The type of Event must be EFI_NOTIFY_SIGNAL.
+ ///
+ EFI_EVENT Event;
+ ///
+ /// Will be set to one of the following values:
+ /// EFI_SUCCESS: The host name to address translation completed successfully.
+ /// EFI_NOT_FOUND: No matching Resource Record (RR) is found.
+ /// EFI_TIMEOUT: No DNS server reachable, or RetryCount was exhausted without
+ /// response from all specified DNS servers.
+ /// EFI_DEVICE_ERROR: An unexpected system or network error occurred.
+ /// EFI_NO_MEDIA: There was a media error.
+ ///
+ EFI_STATUS Status;
+ ///
+ /// Retry number if no response received after RetryInterval. If zero, use the
+ /// parameter configured through Dns.Configure() interface.
+ ///
+ UINT32 RetryCount;
+ ///
+ /// Minimum interval of retry is 2 second. If the retry interval is less than 2
+ /// seconds, then use the 2 seconds. If zero, use the parameter configured through
+ /// Dns.Configure() interface.
+ UINT32 RetryInterval;
+ ///
+ /// DNSv4 completion token data
+ ///
+ union {
+ ///
+ /// When the Token is used for host name to address translation, H2AData is a pointer
+ /// to the DNS_HOST_TO_ADDR_DATA.
+ ///
+ DNS_HOST_TO_ADDR_DATA *H2AData;
+ ///
+ /// When the Token is used for host address to host name translation, A2HData is a
+ /// pointer to the DNS_ADDR_TO_HOST_DATA.
+ ///
+ DNS_ADDR_TO_HOST_DATA *A2HData;
+ ///
+ /// When the Token is used for a general lookup function, GLookupDATA is a pointer to
+ /// the DNS_GENERAL_LOOKUP_DATA.
+ ///
+ DNS_GENERAL_LOOKUP_DATA *GLookupData;
+ } RspData;
+} EFI_DNS4_COMPLETION_TOKEN;
+
+/**
+ Retrieve mode data of this DNS instance.
+
+ This function is used to retrieve DNS mode data for this DNS instance.
+
+ @param[in] This Pointer to EFI_DNS4_PROTOCOL instance.
+ @param[out] DnsModeData Point to the mode data.
+
+ @retval EFI_SUCCESS The operation completed successfully.
+ @retval EFI_NOT_STARTED When DnsConfigData is queried, no configuration data
+ is available because this instance has not been
+ configured.
+ @retval EFI_INVALID_PARAMETER This is NULL or DnsModeData is NULL.
+ @retval EFI_OUT_OF_RESOURCES Failed to allocate needed resources.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_DNS4_GET_MODE_DATA)(
+ IN EFI_DNS4_PROTOCOL *This,
+ OUT EFI_DNS4_MODE_DATA *DnsModeData
+ );
+
+/**
+ Configure this DNS instance.
+
+ This function is used to configure DNS mode data for this DNS instance.
+
+ @param[in] This Pointer to EFI_DNS4_PROTOCOL instance.
+ @param[in] DnsConfigData Point to the Configuration data.
+
+ @retval EFI_SUCCESS The operation completed successfully.
+ @retval EFI_UNSUPPORTED The designated protocol is not supported.
+ @retval EFI_INVALID_PARAMETER This is NULL.
+ The StationIp address provided in DnsConfigData is not a
+ valid unicast.
+ DnsServerList is NULL while DnsServerListCount
+ is not ZERO.
+ DnsServerListCount is ZERO while DnsServerList
+ is not NULL
+ @retval EFI_OUT_OF_RESOURCES The DNS instance data or required space could not be
+ allocated.
+ @retval EFI_DEVICE_ERROR An unexpected system or network error occurred. The
+ EFI DNSv4 Protocol instance is not configured.
+ @retval EFI_ALREADY_STARTED Second call to Configure() with DnsConfigData. To
+ reconfigure the instance the caller must call Configure()
+ with NULL first to return driver to unconfigured state.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_DNS4_CONFIGURE)(
+ IN EFI_DNS4_PROTOCOL *This,
+ IN EFI_DNS4_CONFIG_DATA *DnsConfigData
+ );
+
+/**
+ Host name to host address translation.
+
+ The HostNameToIp () function is used to translate the host name to host IP address. A
+ type A query is used to get the one or more IP addresses for this host.
+
+ @param[in] This Pointer to EFI_DNS4_PROTOCOL instance.
+ @param[in] HostName Host name.
+ @param[in] Token Point to the completion token to translate host name
+ to host address.
+
+ @retval EFI_SUCCESS The operation completed successfully.
+ @retval EFI_INVALID_PARAMETER One or more of the following conditions is TRUE:
+ This is NULL.
+ Token is NULL.
+ Token.Event is NULL.
+ HostName is NULL. HostName string is unsupported format.
+ @retval EFI_NO_MAPPING There's no source address is available for use.
+ @retval EFI_NOT_STARTED This instance has not been started.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_DNS4_HOST_NAME_TO_IP)(
+ IN EFI_DNS4_PROTOCOL *This,
+ IN CHAR16 *HostName,
+ IN EFI_DNS4_COMPLETION_TOKEN *Token
+ );
+
+/**
+ IPv4 address to host name translation also known as Reverse DNS lookup.
+
+ The IpToHostName() function is used to translate the host address to host name. A type PTR
+ query is used to get the primary name of the host. Support of this function is optional.
+
+ @param[in] This Pointer to EFI_DNS4_PROTOCOL instance.
+ @param[in] IpAddress Ip Address.
+ @param[in] Token Point to the completion token to translate host
+ address to host name.
+
+ @retval EFI_SUCCESS The operation completed successfully.
+ @retval EFI_UNSUPPORTED This function is not supported.
+ @retval EFI_INVALID_PARAMETER One or more of the following conditions is TRUE:
+ This is NULL.
+ Token is NULL.
+ Token.Event is NULL.
+ IpAddress is not valid IP address .
+ @retval EFI_NO_MAPPING There's no source address is available for use.
+ @retval EFI_ALREADY_STARTED This Token is being used in another DNS session.
+ @retval EFI_OUT_OF_RESOURCES Failed to allocate needed resources.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_DNS4_IP_TO_HOST_NAME)(
+ IN EFI_DNS4_PROTOCOL *This,
+ IN EFI_IPv4_ADDRESS IpAddress,
+ IN EFI_DNS4_COMPLETION_TOKEN *Token
+ );
+
+/**
+ Retrieve arbitrary information from the DNS server.
+
+ This GeneralLookup() function retrieves arbitrary information from the DNS. The caller
+ supplies a QNAME, QTYPE, and QCLASS, and all of the matching RRs are returned. All
+ RR content (e.g., TTL) was returned. The caller need parse the returned RR to get
+ required information. The function is optional.
+
+ @param[in] This Pointer to EFI_DNS4_PROTOCOL instance.
+ @param[in] QName Pointer to Query Name.
+ @param[in] QType Query Type.
+ @param[in] QClass Query Name.
+ @param[in] Token Point to the completion token to retrieve arbitrary
+ information.
+
+ @retval EFI_SUCCESS The operation completed successfully.
+ @retval EFI_UNSUPPORTED This function is not supported. Or the requested
+ QType is not supported
+ @retval EFI_INVALID_PARAMETER One or more of the following conditions is TRUE:
+ This is NULL.
+ Token is NULL.
+ Token.Event is NULL.
+ QName is NULL.
+ @retval EFI_NO_MAPPING There's no source address is available for use.
+ @retval EFI_ALREADY_STARTED This Token is being used in another DNS session.
+ @retval EFI_OUT_OF_RESOURCES Failed to allocate needed resources.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_DNS4_GENERAL_LOOKUP)(
+ IN EFI_DNS4_PROTOCOL *This,
+ IN CHAR8 *QName,
+ IN UINT16 QType,
+ IN UINT16 QClass,
+ IN EFI_DNS4_COMPLETION_TOKEN *Token
+ );
+
+/**
+ This function is to update the DNS Cache.
+
+ The UpdateDnsCache() function is used to add/delete/modify DNS cache entry. DNS cache
+ can be normally dynamically updated after the DNS resolve succeeds. This function
+ provided capability to manually add/delete/modify the DNS cache.
+
+ @param[in] This Pointer to EFI_DNS4_PROTOCOL instance.
+ @param[in] DeleteFlag If FALSE, this function is to add one entry to the
+ DNS Cahce. If TRUE, this function will delete
+ matching DNS Cache entry.
+ @param[in] Override If TRUE, the maching DNS cache entry will be
+ overwritten with the supplied parameter. If FALSE,
+ EFI_ACCESS_DENIED will be returned if the entry to
+ be added is already existed.
+ @param[in] DnsCacheEntry Pointer to DNS Cache entry.
+
+ @retval EFI_SUCCESS The operation completed successfully.
+ @retval EFI_INVALID_PARAMETER One or more of the following conditions is TRUE:
+ This is NULL.
+ DnsCacheEntry.HostName is NULL.
+ DnsCacheEntry.IpAddress is NULL.
+ DnsCacheEntry.Timeout is zero.
+ @retval EFI_ACCESS_DENIED The DNS cache entry already exists and Override is
+ not TRUE.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_DNS4_UPDATE_DNS_CACHE)(
+ IN EFI_DNS4_PROTOCOL *This,
+ IN BOOLEAN DeleteFlag,
+ IN BOOLEAN Override,
+ IN EFI_DNS4_CACHE_ENTRY DnsCacheEntry
+ );
+
+/**
+ Polls for incoming data packets and processes outgoing data packets.
+
+ The Poll() function can be used by network drivers and applications to increase the
+ rate that data packets are moved between the communications device and the transmit
+ and receive queues.
+ In some systems, the periodic timer event in the managed network driver may not poll
+ the underlying communications device fast enough to transmit and/or receive all data
+ packets without missing incoming packets or dropping outgoing packets. Drivers and
+ applications that are experiencing packet loss should try calling the Poll()
+ function more often.
+
+ @param[in] This Pointer to EFI_DNS4_PROTOCOL instance.
+
+ @retval EFI_SUCCESS Incoming or outgoing data was processed.
+ @retval EFI_NOT_STARTED This EFI DNS Protocol instance has not been started.
+ @retval EFI_INVALID_PARAMETER This is NULL.
+ @retval EFI_DEVICE_ERROR An unexpected system or network error occurred.
+ @retval EFI_TIMEOUT Data was dropped out of the transmit and/or receive
+ queue. Consider increasing the polling rate.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_DNS4_POLL)(
+ IN EFI_DNS4_PROTOCOL *This
+ );
+
+/**
+ Abort an asynchronous DNS operation, including translation between IP and Host, and
+ general look up behavior.
+
+ The Cancel() function is used to abort a pending resolution request. After calling
+ this function, Token.Status will be set to EFI_ABORTED and then Token.Event will be
+ signaled. If the token is not in one of the queues, which usually means that the
+ asynchronous operation has completed, this function will not signal the token and
+ EFI_NOT_FOUND is returned.
+
+ @param[in] This Pointer to EFI_DNS4_PROTOCOL instance.
+ @param[in] Token Pointer to a token that has been issued by
+ EFI_DNS4_PROTOCOL.HostNameToIp (),
+ EFI_DNS4_PROTOCOL.IpToHostName() or
+ EFI_DNS4_PROTOCOL.GeneralLookup().
+ If NULL, all pending tokens are aborted.
+
+ @retval EFI_SUCCESS Incoming or outgoing data was processed.
+ @retval EFI_NOT_STARTED This EFI DNS4 Protocol instance has not been started.
+ @retval EFI_INVALID_PARAMETER This is NULL.
+ @retval EFI_NOT_FOUND When Token is not NULL, and the asynchronous DNS
+ operation was not found in the transmit queue. It
+ was either completed or was not issued by
+ HostNameToIp(), IpToHostName() or GeneralLookup().
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_DNS4_CANCEL)(
+ IN EFI_DNS4_PROTOCOL *This,
+ IN EFI_DNS4_COMPLETION_TOKEN *Token
+ );
+
+///
+/// The EFI_DNS4_Protocol provides the function to get the host name and address
+/// mapping, also provides pass through interface to retrieve arbitrary information
+/// from DNS.
+///
+struct _EFI_DNS4_PROTOCOL {
+ EFI_DNS4_GET_MODE_DATA GetModeData;
+ EFI_DNS4_CONFIGURE Configure;
+ EFI_DNS4_HOST_NAME_TO_IP HostNameToIp;
+ EFI_DNS4_IP_TO_HOST_NAME IpToHostName;
+ EFI_DNS4_GENERAL_LOOKUP GeneralLookUp;
+ EFI_DNS4_UPDATE_DNS_CACHE UpdateDnsCache;
+ EFI_DNS4_POLL Poll;
+ EFI_DNS4_CANCEL Cancel;
+};
+
+extern EFI_GUID gEfiDns4ServiceBindingProtocolGuid;
+extern EFI_GUID gEfiDns4ProtocolGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/Dns6.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/Dns6.h
new file mode 100644
index 0000000000..71d5dc37a5
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/Dns6.h
@@ -0,0 +1,533 @@
+/** @file
+ This file defines the EFI DNSv6 (Domain Name Service version 6) Protocol. It is split
+ into the following two main sections:
+ DNSv6 Service Binding Protocol (DNSv6SB)
+ DNSv6 Protocol (DNSv6)
+
+ Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Revision Reference:
+ This Protocol is introduced in UEFI Specification 2.5
+
+**/
+
+#ifndef __EFI_DNS6_PROTOCOL_H__
+#define __EFI_DNS6_PROTOCOL_H__
+
+#define EFI_DNS6_SERVICE_BINDING_PROTOCOL_GUID \
+ { \
+ 0x7f1647c8, 0xb76e, 0x44b2, {0xa5, 0x65, 0xf7, 0xf, 0xf1, 0x9c, 0xd1, 0x9e } \
+ }
+
+#define EFI_DNS6_PROTOCOL_GUID \
+ { \
+ 0xca37bc1f, 0xa327, 0x4ae9, {0x82, 0x8a, 0x8c, 0x40, 0xd8, 0x50, 0x6a, 0x17 } \
+ }
+
+typedef struct _EFI_DNS6_PROTOCOL EFI_DNS6_PROTOCOL;
+
+///
+/// EFI_DNS6_CONFIG_DATA
+///
+typedef struct {
+ ///
+ /// If TRUE, enable DNS cache function for this DNS instance. If FALSE, all DNS query
+ /// will not lookup local DNS cache.
+ ///
+ BOOLEAN EnableDnsCache;
+ ///
+ /// Use the protocol number defined in
+ /// http://www.iana.org/assignments/protocol-numbers. Beside TCP/UDP, Other protocol
+ /// is invalid value. An implementation can choose to support UDP, or both TCP and UDP.
+ ///
+ UINT8 Protocol;
+ ///
+ /// The local IP address to use. Set to zero to let the underlying IPv6
+ /// driver choose a source address. If not zero it must be one of the
+ /// configured IP addresses in the underlying IPv6 driver.
+ ///
+ EFI_IPv6_ADDRESS StationIp;
+ ///
+ /// Local port number. Set to zero to use the automatically assigned port number.
+ ///
+ UINT16 LocalPort;
+ ///
+ /// Count of the DNS servers. When used with GetModeData(),
+ /// this field is the count of originally configured servers when
+ /// Configure() was called for this instance. When used with
+ /// Configure() this is the count of caller-supplied servers. If the
+ /// DnsServerListCount is zero, the DNS server configuration
+ /// will be retrieved from DHCP server automatically.
+ ///
+ UINT32 DnsServerCount;
+ ///
+ /// Pointer to DNS server list containing DnsServerListCount
+ /// entries or NULL if DnsServerListCount is 0. For Configure(),
+ /// this will be NULL when there are no caller supplied server addresses
+ /// and the DNS instance will retrieve DNS server from DHCP Server.
+ /// The provided DNS server list is recommended to be filled up in the sequence
+ /// of preference. When used with GetModeData(), the buffer containing the list
+ /// will be allocated by the driver implementing this protocol and must be
+ /// freed by the caller. When used with Configure(), the buffer
+ /// containing the list will be allocated and released by the caller.
+ ///
+ EFI_IPv6_ADDRESS *DnsServerList;
+ ///
+ /// Retry number if no response received after RetryInterval.
+ ///
+ UINT32 RetryCount;
+ ///
+ /// Minimum interval of retry is 2 second. If the retry interval is less than 2
+ /// seconds, then use the 2 seconds.
+ UINT32 RetryInterval;
+} EFI_DNS6_CONFIG_DATA;
+
+///
+/// EFI_DNS6_CACHE_ENTRY
+///
+typedef struct {
+ ///
+ /// Host name. This should be interpreted as Unicode characters.
+ ///
+ CHAR16 *HostName;
+ ///
+ /// IP address of this host.
+ ///
+ EFI_IPv6_ADDRESS *IpAddress;
+ ///
+ /// Time in second unit that this entry will remain in DNS cache. A value of zero means
+ /// that this entry is permanent. A nonzero value will override the existing one if
+ /// this entry to be added is dynamic entry. Implementations may set its default
+ /// timeout value for the dynamically created DNS cache entry after one DNS resolve
+ /// succeeds.
+ UINT32 Timeout;
+} EFI_DNS6_CACHE_ENTRY;
+
+///
+/// EFI_DNS6_MODE_DATA
+///
+typedef struct {
+ ///
+ /// The configuration data of this instance.
+ ///
+ EFI_DNS6_CONFIG_DATA DnsConfigData;
+ ///
+ /// Number of configured DNS6 servers.
+ ///
+ UINT32 DnsServerCount;
+ ///
+ /// Pointer to common list of addresses of all configured DNS server used by EFI_DNS6_PROTOCOL
+ /// instances. List will include DNS servers configured by this or any other EFI_DNS6_PROTOCOL
+ /// instance. The storage for this list is allocated by the driver publishing this protocol,
+ /// and must be freed by the caller.
+ ///
+ EFI_IPv6_ADDRESS *DnsServerList;
+ ///
+ /// Number of DNS Cache entries. The DNS Cache is shared among all DNS instances.
+ ///
+ UINT32 DnsCacheCount;
+ ///
+ /// Pointer to a buffer containing DnsCacheCount DNS Cache
+ /// entry structures. The storage for thislist is allocated by the driver
+ /// publishing this protocol and must be freed by caller.
+ ///
+ EFI_DNS6_CACHE_ENTRY *DnsCacheList;
+} EFI_DNS6_MODE_DATA;
+
+///
+/// DNS6_HOST_TO_ADDR_DATA
+///
+typedef struct {
+ ///
+ /// Number of the returned IP address.
+ ///
+ UINT32 IpCount;
+ ///
+ /// Pointer to the all the returned IP address.
+ ///
+ EFI_IPv6_ADDRESS *IpList;
+} DNS6_HOST_TO_ADDR_DATA;
+
+///
+/// DNS6_ADDR_TO_HOST_DATA
+///
+typedef struct {
+ ///
+ /// Pointer to the primary name for this host address. It's the caller's
+ /// responsibility to free the response memory.
+ ///
+ CHAR16 *HostName;
+} DNS6_ADDR_TO_HOST_DATA;
+
+///
+/// DNS6_RESOURCE_RECORD
+///
+typedef struct {
+ ///
+ /// The Owner name.
+ ///
+ CHAR8 *QName;
+ ///
+ /// The Type Code of this RR.
+ ///
+ UINT16 QType;
+ ///
+ /// The CLASS code of this RR.
+ ///
+ UINT16 QClass;
+ ///
+ /// 32 bit integer which specify the time interval that the resource record may be
+ /// cached before the source of the information should again be consulted. Zero means
+ /// this RR cannot be cached.
+ ///
+ UINT32 TTL;
+ ///
+ /// 16 big integer which specify the length of RData.
+ ///
+ UINT16 DataLength;
+ ///
+ /// A string of octets that describe the resource, the format of this information
+ /// varies according to QType and QClass difference.
+ ///
+ CHAR8 *RData;
+} DNS6_RESOURCE_RECORD;
+
+///
+/// DNS6_GENERAL_LOOKUP_DATA
+///
+typedef struct {
+ ///
+ /// Number of returned matching RRs.
+ ///
+ UINTN RRCount;
+ ///
+ /// Pointer to the all the returned matching RRs. It's caller responsibility to free
+ /// the allocated memory to hold the returned RRs.
+ ///
+ DNS6_RESOURCE_RECORD *RRList;
+} DNS6_GENERAL_LOOKUP_DATA;
+
+///
+/// EFI_DNS6_COMPLETION_TOKEN
+///
+typedef struct {
+ ///
+ /// This Event will be signaled after the Status field is updated by the EFI DNSv6
+ /// protocol driver. The type of Event must be EFI_NOTIFY_SIGNAL.
+ ///
+ EFI_EVENT Event;
+ ///
+ /// Will be set to one of the following values:
+ /// EFI_SUCCESS: The host name to address translation completed successfully.
+ /// EFI_NOT_FOUND: No matching Resource Record (RR) is found.
+ /// EFI_TIMEOUT: No DNS server reachable, or RetryCount was exhausted without
+ /// response from all specified DNS servers.
+ /// EFI_DEVICE_ERROR: An unexpected system or network error occurred.
+ /// EFI_NO_MEDIA: There was a media error.
+ ///
+ EFI_STATUS Status;
+ ///
+ /// The parameter configured through DNSv6.Configure() interface. Retry number if no
+ /// response received after RetryInterval.
+ ///
+ UINT32 RetryCount;
+ ///
+ /// The parameter configured through DNSv6.Configure() interface. Minimum interval of
+ /// retry is 2 seconds. If the retry interval is less than 2 seconds, then use the 2
+ /// seconds.
+ ///
+ UINT32 RetryInterval;
+ ///
+ /// DNSv6 completion token data
+ ///
+ union {
+ ///
+ /// When the Token is used for host name to address translation, H2AData is a pointer
+ /// to the DNS6_HOST_TO_ADDR_DATA.
+ ///
+ DNS6_HOST_TO_ADDR_DATA *H2AData;
+ ///
+ /// When the Token is used for host address to host name translation, A2HData is a
+ /// pointer to the DNS6_ADDR_TO_HOST_DATA.
+ ///
+ DNS6_ADDR_TO_HOST_DATA *A2HData;
+ ///
+ /// When the Token is used for a general lookup function, GLookupDATA is a pointer to
+ /// the DNS6_GENERAL_LOOKUP_DATA.
+ ///
+ DNS6_GENERAL_LOOKUP_DATA *GLookupData;
+ } RspData;
+} EFI_DNS6_COMPLETION_TOKEN;
+
+/**
+ Retrieve mode data of this DNS instance.
+
+ This function is used to retrieve DNS mode data for this DNS instance.
+
+ @param[in] This Pointer to EFI_DNS6_PROTOCOL instance.
+ @param[out] DnsModeData Pointer to the caller-allocated storage for the
+ EFI_DNS6_MODE_DATA data.
+
+ @retval EFI_SUCCESS The operation completed successfully.
+ @retval EFI_NOT_STARTED When DnsConfigData is queried, no configuration data
+ is available because this instance has not been
+ configured.
+ @retval EFI_INVALID_PARAMETER This is NULL or DnsModeData is NULL.
+ @retval EFI_OUT_OF_RESOURCE Failed to allocate needed resources.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_DNS6_GET_MODE_DATA)(
+ IN EFI_DNS6_PROTOCOL *This,
+ OUT EFI_DNS6_MODE_DATA *DnsModeData
+ );
+
+/**
+ Configure this DNS instance.
+
+ The Configure() function is used to set and change the configuration data for this
+ EFI DNSv6 Protocol driver instance. Reset the DNS instance if DnsConfigData is NULL.
+
+ @param[in] This Pointer to EFI_DNS6_PROTOCOL instance.
+ @param[in] DnsConfigData Pointer to the configuration data structure. All associated
+ storage to be allocated and released by caller.
+
+ @retval EFI_SUCCESS The operation completed successfully.
+ @retval EFI_INVALID_PARAMETER This is NULL.
+ The StationIp address provided in DnsConfigData is not zero and not a valid unicast.
+ DnsServerList is NULL while DnsServerList Count is not ZERO.
+ DnsServerList Count is ZERO while DnsServerList is not NULL.
+ @retval EFI_OUT_OF_RESOURCES The DNS instance data or required space could not be allocated.
+ @retval EFI_DEVICE_ERROR An unexpected system or network error occurred. The
+ EFI DNSv6 Protocol instance is not configured.
+ @retval EFI_UNSUPPORTED The designated protocol is not supported.
+ @retval EFI_ALREADY_STARTED Second call to Configure() with DnsConfigData. To
+ reconfigure the instance the caller must call Configure() with
+ NULL first to return driver to unconfigured state.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_DNS6_CONFIGURE)(
+ IN EFI_DNS6_PROTOCOL *This,
+ IN EFI_DNS6_CONFIG_DATA *DnsConfigData
+ );
+
+/**
+ Host name to host address translation.
+
+ The HostNameToIp () function is used to translate the host name to host IP address. A
+ type AAAA query is used to get the one or more IPv6 addresses for this host.
+
+ @param[in] This Pointer to EFI_DNS6_PROTOCOL instance.
+ @param[in] HostName Host name.
+ @param[in] Token Point to the completion token to translate host name
+ to host address.
+
+ @retval EFI_SUCCESS The operation completed successfully.
+ @retval EFI_INVALID_PARAMETER One or more of the following conditions is TRUE:
+ This is NULL.
+ Token is NULL.
+ Token.Event is NULL.
+ HostName is NULL or buffer contained unsupported characters.
+ @retval EFI_NO_MAPPING There's no source address is available for use.
+ @retval EFI_ALREADY_STARTED This Token is being used in another DNS session.
+ @retval EFI_NOT_STARTED This instance has not been started.
+ @retval EFI_OUT_OF_RESOURCES Failed to allocate needed resources.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_DNS6_HOST_NAME_TO_IP)(
+ IN EFI_DNS6_PROTOCOL *This,
+ IN CHAR16 *HostName,
+ IN EFI_DNS6_COMPLETION_TOKEN *Token
+ );
+
+/**
+ Host address to host name translation.
+
+ The IpToHostName () function is used to translate the host address to host name. A
+ type PTR query is used to get the primary name of the host. Implementation can choose
+ to support this function or not.
+
+ @param[in] This Pointer to EFI_DNS6_PROTOCOL instance.
+ @param[in] IpAddress Ip Address.
+ @param[in] Token Point to the completion token to translate host
+ address to host name.
+
+ @retval EFI_SUCCESS The operation completed successfully.
+ @retval EFI_UNSUPPORTED This function is not supported.
+ @retval EFI_INVALID_PARAMETER One or more of the following conditions is TRUE:
+ This is NULL.
+ Token is NULL.
+ Token.Event is NULL.
+ IpAddress is not valid IP address.
+ @retval EFI_NO_MAPPING There's no source address is available for use.
+ @retval EFI_NOT_STARTED This instance has not been started.
+ @retval EFI_OUT_OF_RESOURCES Failed to allocate needed resources.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_DNS6_IP_TO_HOST_NAME)(
+ IN EFI_DNS6_PROTOCOL *This,
+ IN EFI_IPv6_ADDRESS IpAddress,
+ IN EFI_DNS6_COMPLETION_TOKEN *Token
+ );
+
+/**
+ This function provides capability to retrieve arbitrary information from the DNS
+ server.
+
+ This GeneralLookup() function retrieves arbitrary information from the DNS. The caller
+ supplies a QNAME, QTYPE, and QCLASS, and all of the matching RRs are returned. All
+ RR content (e.g., TTL) was returned. The caller need parse the returned RR to get
+ required information. The function is optional. Implementation can choose to support
+ it or not.
+
+ @param[in] This Pointer to EFI_DNS6_PROTOCOL instance.
+ @param[in] QName Pointer to Query Name.
+ @param[in] QType Query Type.
+ @param[in] QClass Query Name.
+ @param[in] Token Point to the completion token to retrieve arbitrary
+ information.
+
+ @retval EFI_SUCCESS The operation completed successfully.
+ @retval EFI_UNSUPPORTED This function is not supported. Or the requested
+ QType is not supported
+ @retval EFI_INVALID_PARAMETER One or more of the following conditions is TRUE:
+ This is NULL.
+ Token is NULL.
+ Token.Event is NULL.
+ QName is NULL.
+ @retval EFI_NO_MAPPING There's no source address is available for use.
+ @retval EFI_NOT_STARTED This instance has not been started.
+ @retval EFI_OUT_OF_RESOURCES Failed to allocate needed resources.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_DNS6_GENERAL_LOOKUP)(
+ IN EFI_DNS6_PROTOCOL *This,
+ IN CHAR8 *QName,
+ IN UINT16 QType,
+ IN UINT16 QClass,
+ IN EFI_DNS6_COMPLETION_TOKEN *Token
+ );
+
+/**
+ This function is to update the DNS Cache.
+
+ The UpdateDnsCache() function is used to add/delete/modify DNS cache entry. DNS cache
+ can be normally dynamically updated after the DNS resolve succeeds. This function
+ provided capability to manually add/delete/modify the DNS cache.
+
+ @param[in] This Pointer to EFI_DNS6_PROTOCOL instance.
+ @param[in] DeleteFlag If FALSE, this function is to add one entry to the
+ DNS Cahce. If TRUE, this function will delete
+ matching DNS Cache entry.
+ @param[in] Override If TRUE, the maching DNS cache entry will be
+ overwritten with the supplied parameter. If FALSE,
+ EFI_ACCESS_DENIED will be returned if the entry to
+ be added is already existed.
+ @param[in] DnsCacheEntry Pointer to DNS Cache entry.
+
+ @retval EFI_SUCCESS The operation completed successfully.
+ @retval EFI_INVALID_PARAMETER One or more of the following conditions is TRUE:
+ This is NULL.
+ DnsCacheEntry.HostName is NULL.
+ DnsCacheEntry.IpAddress is NULL.
+ DnsCacheEntry.Timeout is zero.
+ @retval EFI_ACCESS_DENIED The DNS cache entry already exists and Override is
+ not TRUE.
+ @retval EFI_OUT_OF_RESOURCE Failed to allocate needed resources.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_DNS6_UPDATE_DNS_CACHE)(
+ IN EFI_DNS6_PROTOCOL *This,
+ IN BOOLEAN DeleteFlag,
+ IN BOOLEAN Override,
+ IN EFI_DNS6_CACHE_ENTRY DnsCacheEntry
+ );
+
+/**
+ Polls for incoming data packets and processes outgoing data packets.
+
+ The Poll() function can be used by network drivers and applications to increase the
+ rate that data packets are moved between the communications device and the transmit
+ and receive queues.
+
+ In some systems, the periodic timer event in the managed network driver may not poll
+ the underlying communications device fast enough to transmit and/or receive all data
+ packets without missing incoming packets or dropping outgoing packets. Drivers and
+ applications that are experiencing packet loss should try calling the Poll()
+ function more often.
+
+ @param[in] This Pointer to EFI_DNS6_PROTOCOL instance.
+
+ @retval EFI_SUCCESS Incoming or outgoing data was processed.
+ @retval EFI_NOT_STARTED This EFI DNS Protocol instance has not been started.
+ @retval EFI_INVALID_PARAMETER This is NULL.
+ @retval EFI_NO_MAPPING There is no source address is available for use.
+ @retval EFI_DEVICE_ERROR An unexpected system or network error occurred.
+ @retval EFI_TIMEOUT Data was dropped out of the transmit and/or receive
+ queue. Consider increasing the polling rate.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_DNS6_POLL)(
+ IN EFI_DNS6_PROTOCOL *This
+ );
+
+/**
+ Abort an asynchronous DNS operation, including translation between IP and Host, and
+ general look up behavior.
+
+ The Cancel() function is used to abort a pending resolution request. After calling
+ this function, Token.Status will be set to EFI_ABORTED and then Token.Event will be
+ signaled. If the token is not in one of the queues, which usually means that the
+ asynchronous operation has completed, this function will not signal the token and
+ EFI_NOT_FOUND is returned.
+
+ @param[in] This Pointer to EFI_DNS6_PROTOCOL instance.
+ @param[in] Token Pointer to a token that has been issued by
+ EFI_DNS6_PROTOCOL.HostNameToIp (),
+ EFI_DNS6_PROTOCOL.IpToHostName() or
+ EFI_DNS6_PROTOCOL.GeneralLookup().
+ If NULL, all pending tokens are aborted.
+
+ @retval EFI_SUCCESS Incoming or outgoing data was processed.
+ @retval EFI_NOT_STARTED This EFI DNS6 Protocol instance has not been started.
+ @retval EFI_INVALID_PARAMETER This is NULL.
+ @retval EFI_NO_MAPPING There's no source address is available for use.
+ @retval EFI_NOT_FOUND When Token is not NULL, and the asynchronous DNS
+ operation was not found in the transmit queue. It
+ was either completed or was not issued by
+ HostNameToIp(), IpToHostName() or GeneralLookup().
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_DNS6_CANCEL)(
+ IN EFI_DNS6_PROTOCOL *This,
+ IN EFI_DNS6_COMPLETION_TOKEN *Token
+ );
+
+///
+/// The EFI_DNS6_PROTOCOL provides the function to get the host name and address
+/// mapping, also provide pass through interface to retrieve arbitrary information from
+/// DNSv6.
+///
+struct _EFI_DNS6_PROTOCOL {
+ EFI_DNS6_GET_MODE_DATA GetModeData;
+ EFI_DNS6_CONFIGURE Configure;
+ EFI_DNS6_HOST_NAME_TO_IP HostNameToIp;
+ EFI_DNS6_IP_TO_HOST_NAME IpToHostName;
+ EFI_DNS6_GENERAL_LOOKUP GeneralLookUp;
+ EFI_DNS6_UPDATE_DNS_CACHE UpdateDnsCache;
+ EFI_DNS6_POLL Poll;
+ EFI_DNS6_CANCEL Cancel;
+};
+
+extern EFI_GUID gEfiDns6ServiceBindingProtocolGuid;
+extern EFI_GUID gEfiDns6ProtocolGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/DriverBinding.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/DriverBinding.h
new file mode 100644
index 0000000000..327e46d721
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/DriverBinding.h
@@ -0,0 +1,195 @@
+/** @file
+ UEFI DriverBinding Protocol is defined in UEFI specification.
+
+ This protocol is produced by every driver that follows the UEFI Driver Model,
+ and it is the central component that allows drivers and controllers to be managed.
+
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __EFI_DRIVER_BINDING_H__
+#define __EFI_DRIVER_BINDING_H__
+
+///
+/// The global ID for the ControllerHandle Driver Protocol.
+///
+#define EFI_DRIVER_BINDING_PROTOCOL_GUID \
+ { \
+ 0x18a031ab, 0xb443, 0x4d1a, {0xa5, 0xc0, 0xc, 0x9, 0x26, 0x1e, 0x9f, 0x71 } \
+ }
+
+typedef struct _EFI_DRIVER_BINDING_PROTOCOL EFI_DRIVER_BINDING_PROTOCOL;
+
+/**
+ Tests to see if this driver supports a given controller. If a child device is provided,
+ it further tests to see if this driver supports creating a handle for the specified child device.
+
+ This function checks to see if the driver specified by This supports the device specified by
+ ControllerHandle. Drivers will typically use the device path attached to
+ ControllerHandle and/or the services from the bus I/O abstraction attached to
+ ControllerHandle to determine if the driver supports ControllerHandle. This function
+ may be called many times during platform initialization. In order to reduce boot times, the tests
+ performed by this function must be very small, and take as little time as possible to execute. This
+ function must not change the state of any hardware devices, and this function must be aware that the
+ device specified by ControllerHandle may already be managed by the same driver or a
+ different driver. This function must match its calls to AllocatePages() with FreePages(),
+ AllocatePool() with FreePool(), and OpenProtocol() with CloseProtocol().
+ Because ControllerHandle may have been previously started by the same driver, if a protocol is
+ already in the opened state, then it must not be closed with CloseProtocol(). This is required
+ to guarantee the state of ControllerHandle is not modified by this function.
+
+ @param[in] This A pointer to the EFI_DRIVER_BINDING_PROTOCOL instance.
+ @param[in] ControllerHandle The handle of the controller to test. This handle
+ must support a protocol interface that supplies
+ an I/O abstraction to the driver.
+ @param[in] RemainingDevicePath A pointer to the remaining portion of a device path. This
+ parameter is ignored by device drivers, and is optional for bus
+ drivers. For bus drivers, if this parameter is not NULL, then
+ the bus driver must determine if the bus controller specified
+ by ControllerHandle and the child controller specified
+ by RemainingDevicePath are both supported by this
+ bus driver.
+
+ @retval EFI_SUCCESS The device specified by ControllerHandle and
+ RemainingDevicePath is supported by the driver specified by This.
+ @retval EFI_ALREADY_STARTED The device specified by ControllerHandle and
+ RemainingDevicePath is already being managed by the driver
+ specified by This.
+ @retval EFI_ACCESS_DENIED The device specified by ControllerHandle and
+ RemainingDevicePath is already being managed by a different
+ driver or an application that requires exclusive access.
+ Currently not implemented.
+ @retval EFI_UNSUPPORTED The device specified by ControllerHandle and
+ RemainingDevicePath is not supported by the driver specified by This.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_DRIVER_BINDING_SUPPORTED)(
+ IN EFI_DRIVER_BINDING_PROTOCOL *This,
+ IN EFI_HANDLE ControllerHandle,
+ IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath OPTIONAL
+ );
+
+/**
+ Starts a device controller or a bus controller.
+
+ The Start() function is designed to be invoked from the EFI boot service ConnectController().
+ As a result, much of the error checking on the parameters to Start() has been moved into this
+ common boot service. It is legal to call Start() from other locations,
+ but the following calling restrictions must be followed, or the system behavior will not be deterministic.
+ 1. ControllerHandle must be a valid EFI_HANDLE.
+ 2. If RemainingDevicePath is not NULL, then it must be a pointer to a naturally aligned
+ EFI_DEVICE_PATH_PROTOCOL.
+ 3. Prior to calling Start(), the Supported() function for the driver specified by This must
+ have been called with the same calling parameters, and Supported() must have returned EFI_SUCCESS.
+
+ @param[in] This A pointer to the EFI_DRIVER_BINDING_PROTOCOL instance.
+ @param[in] ControllerHandle The handle of the controller to start. This handle
+ must support a protocol interface that supplies
+ an I/O abstraction to the driver.
+ @param[in] RemainingDevicePath A pointer to the remaining portion of a device path. This
+ parameter is ignored by device drivers, and is optional for bus
+ drivers. For a bus driver, if this parameter is NULL, then handles
+ for all the children of Controller are created by this driver.
+ If this parameter is not NULL and the first Device Path Node is
+ not the End of Device Path Node, then only the handle for the
+ child device specified by the first Device Path Node of
+ RemainingDevicePath is created by this driver.
+ If the first Device Path Node of RemainingDevicePath is
+ the End of Device Path Node, no child handle is created by this
+ driver.
+
+ @retval EFI_SUCCESS The device was started.
+ @retval EFI_DEVICE_ERROR The device could not be started due to a device error.Currently not implemented.
+ @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
+ @retval Others The driver failded to start the device.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_DRIVER_BINDING_START)(
+ IN EFI_DRIVER_BINDING_PROTOCOL *This,
+ IN EFI_HANDLE ControllerHandle,
+ IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath OPTIONAL
+ );
+
+/**
+ Stops a device controller or a bus controller.
+
+ The Stop() function is designed to be invoked from the EFI boot service DisconnectController().
+ As a result, much of the error checking on the parameters to Stop() has been moved
+ into this common boot service. It is legal to call Stop() from other locations,
+ but the following calling restrictions must be followed, or the system behavior will not be deterministic.
+ 1. ControllerHandle must be a valid EFI_HANDLE that was used on a previous call to this
+ same driver's Start() function.
+ 2. The first NumberOfChildren handles of ChildHandleBuffer must all be a valid
+ EFI_HANDLE. In addition, all of these handles must have been created in this driver's
+ Start() function, and the Start() function must have called OpenProtocol() on
+ ControllerHandle with an Attribute of EFI_OPEN_PROTOCOL_BY_CHILD_CONTROLLER.
+
+ @param[in] This A pointer to the EFI_DRIVER_BINDING_PROTOCOL instance.
+ @param[in] ControllerHandle A handle to the device being stopped. The handle must
+ support a bus specific I/O protocol for the driver
+ to use to stop the device.
+ @param[in] NumberOfChildren The number of child device handles in ChildHandleBuffer.
+ @param[in] ChildHandleBuffer An array of child handles to be freed. May be NULL
+ if NumberOfChildren is 0.
+
+ @retval EFI_SUCCESS The device was stopped.
+ @retval EFI_DEVICE_ERROR The device could not be stopped due to a device error.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_DRIVER_BINDING_STOP)(
+ IN EFI_DRIVER_BINDING_PROTOCOL *This,
+ IN EFI_HANDLE ControllerHandle,
+ IN UINTN NumberOfChildren,
+ IN EFI_HANDLE *ChildHandleBuffer OPTIONAL
+ );
+
+///
+/// This protocol provides the services required to determine if a driver supports a given controller.
+/// If a controller is supported, then it also provides routines to start and stop the controller.
+///
+struct _EFI_DRIVER_BINDING_PROTOCOL {
+ EFI_DRIVER_BINDING_SUPPORTED Supported;
+ EFI_DRIVER_BINDING_START Start;
+ EFI_DRIVER_BINDING_STOP Stop;
+
+ ///
+ /// The version number of the UEFI driver that produced the
+ /// EFI_DRIVER_BINDING_PROTOCOL. This field is used by
+ /// the EFI boot service ConnectController() to determine
+ /// the order that driver's Supported() service will be used when
+ /// a controller needs to be started. EFI Driver Binding Protocol
+ /// instances with higher Version values will be used before ones
+ /// with lower Version values. The Version values of 0x0-
+ /// 0x0f and 0xfffffff0-0xffffffff are reserved for
+ /// platform/OEM specific drivers. The Version values of 0x10-
+ /// 0xffffffef are reserved for IHV-developed drivers.
+ ///
+ UINT32 Version;
+
+ ///
+ /// The image handle of the UEFI driver that produced this instance
+ /// of the EFI_DRIVER_BINDING_PROTOCOL.
+ ///
+ EFI_HANDLE ImageHandle;
+
+ ///
+ /// The handle on which this instance of the
+ /// EFI_DRIVER_BINDING_PROTOCOL is installed. In most
+ /// cases, this is the same handle as ImageHandle. However, for
+ /// UEFI drivers that produce more than one instance of the
+ /// EFI_DRIVER_BINDING_PROTOCOL, this value may not be
+ /// the same as ImageHandle.
+ ///
+ EFI_HANDLE DriverBindingHandle;
+};
+
+extern EFI_GUID gEfiDriverBindingProtocolGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/DriverConfiguration.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/DriverConfiguration.h
new file mode 100644
index 0000000000..912099161d
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/DriverConfiguration.h
@@ -0,0 +1,159 @@
+/** @file
+ EFI Driver Configuration Protocol
+
+ Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __EFI_DRIVER_CONFIGURATION_H__
+#define __EFI_DRIVER_CONFIGURATION_H__
+
+#include
+
+///
+/// Global ID for the Driver Configuration Protocol defined in EFI 1.1
+///
+#define EFI_DRIVER_CONFIGURATION_PROTOCOL_GUID \
+ { \
+ 0x107a772b, 0xd5e1, 0x11d4, {0x9a, 0x46, 0x0, 0x90, 0x27, 0x3f, 0xc1, 0x4d } \
+ }
+
+typedef struct _EFI_DRIVER_CONFIGURATION_PROTOCOL EFI_DRIVER_CONFIGURATION_PROTOCOL;
+
+/**
+ Allows the user to set controller specific options for a controller that a
+ driver is currently managing.
+
+ @param This A pointer to the EFI_DRIVER_CONFIGURATION_PROTOCOL instance.
+ @param ControllerHandle The handle of the controller to set options on.
+ @param ChildHandle The handle of the child controller to set options on. This
+ is an optional parameter that may be NULL. It will be NULL
+ for device drivers, and for bus drivers that wish to set
+ options for the bus controller. It will not be NULL for a
+ bus driver that wishes to set options for one of its child
+ controllers.
+ @param Language A pointer to a three character ISO 639-2 language identifier.
+ This is the language of the user interface that should be
+ presented to the user, and it must match one of the languages
+ specified in SupportedLanguages. The number of languages
+ supported by a driver is up to the driver writer.
+ @param ActionRequired A pointer to the action that the calling agent is required
+ to perform when this function returns. See "Related
+ Definitions" for a list of the actions that the calling
+ agent is required to perform prior to accessing
+ ControllerHandle again.
+
+ @retval EFI_SUCCESS The driver specified by This successfully set the
+ configuration options for the controller specified
+ by ControllerHandle..
+ @retval EFI_INVALID_PARAMETER ControllerHandle is not a valid EFI_HANDLE.
+ @retval EFI_INVALID_PARAMETER ChildHandle is not NULL and it is not a valid EFI_HANDLE.
+ @retval EFI_INVALID_PARAMETER ActionRequired is NULL.
+ @retval EFI_UNSUPPORTED The driver specified by This does not support setting
+ configuration options for the controller specified by
+ ControllerHandle and ChildHandle.
+ @retval EFI_UNSUPPORTED The driver specified by This does not support the
+ language specified by Language.
+ @retval EFI_DEVICE_ERROR A device error occurred while attempt to set the
+ configuration options for the controller specified
+ by ControllerHandle and ChildHandle.
+ @retval EFI_OUT_RESOURCES There are not enough resources available to set the
+ configuration options for the controller specified
+ by ControllerHandle and ChildHandle.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_DRIVER_CONFIGURATION_SET_OPTIONS)(
+ IN EFI_DRIVER_CONFIGURATION_PROTOCOL *This,
+ IN EFI_HANDLE ControllerHandle,
+ IN EFI_HANDLE ChildHandle OPTIONAL,
+ IN CHAR8 *Language,
+ OUT EFI_DRIVER_CONFIGURATION_ACTION_REQUIRED *ActionRequired
+ );
+
+/**
+ Tests to see if a controller's current configuration options are valid.
+
+ @param This A pointer to the EFI_DRIVER_CONFIGURATION_PROTOCOL instance.
+ @param ControllerHandle The handle of the controller to test if it's current
+ configuration options are valid.
+ @param ChildHandle The handle of the child controller to test if it's current
+ configuration options are valid. This is an optional
+ parameter that may be NULL. It will be NULL for device
+ drivers. It will also be NULL for bus drivers that wish
+ to test the configuration options for the bus controller.
+ It will not be NULL for a bus driver that wishes to test
+ configuration options for one of its child controllers.
+
+ @retval EFI_SUCCESS The controller specified by ControllerHandle and
+ ChildHandle that is being managed by the driver
+ specified by This has a valid set of configuration
+ options.
+ @retval EFI_INVALID_PARAMETER ControllerHandle is not a valid EFI_HANDLE.
+ @retval EFI_INVALID_PARAMETER ChildHandle is not NULL and it is not a valid EFI_HANDLE.
+ @retval EFI_UNSUPPORTED The driver specified by This is not currently
+ managing the controller specified by ControllerHandle
+ and ChildHandle.
+ @retval EFI_DEVICE_ERROR The controller specified by ControllerHandle and
+ ChildHandle that is being managed by the driver
+ specified by This has an invalid set of configuration
+ options.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_DRIVER_CONFIGURATION_OPTIONS_VALID)(
+ IN EFI_DRIVER_CONFIGURATION_PROTOCOL *This,
+ IN EFI_HANDLE ControllerHandle,
+ IN EFI_HANDLE ChildHandle OPTIONAL
+ );
+
+/**
+ Forces a driver to set the default configuration options for a controller.
+
+ @param This A pointer to the EFI_DRIVER_CONFIGURATION_PROTOCOL instance.
+ @param ControllerHandle The handle of the controller to force default configuration options on.
+ @param ChildHandle The handle of the child controller to force default configuration options on This is an optional parameter that may be NULL. It will be NULL for device drivers. It will also be NULL for bus drivers that wish to force default configuration options for the bus controller. It will not be NULL for a bus driver that wishes to force default configuration options for one of its child controllers.
+ @param DefaultType The type of default configuration options to force on the controller specified by ControllerHandle and ChildHandle. See Table 9-1 for legal values. A DefaultType of 0x00000000 must be supported by this protocol.
+ @param ActionRequired A pointer to the action that the calling agent is required to perform when this function returns. See "Related Definitions" in Section 9.1 for a list of the actions that the calling agent is required to perform prior to accessing ControllerHandle again.
+
+ @retval EFI_SUCCESS The driver specified by This successfully forced the default configuration options on the controller specified by ControllerHandle and ChildHandle.
+ @retval EFI_INVALID_PARAMETER ControllerHandle is not a valid EFI_HANDLE.
+ @retval EFI_INVALID_PARAMETER ChildHandle is not NULL and it is not a valid EFI_HANDLE.
+ @retval EFI_INVALID_PARAMETER ActionRequired is NULL.
+ @retval EFI_UNSUPPORTED The driver specified by This does not support forcing the default configuration options on the controller specified by ControllerHandle and ChildHandle.
+ @retval EFI_UNSUPPORTED The driver specified by This does not support the configuration type specified by DefaultType.
+ @retval EFI_DEVICE_ERROR A device error occurred while attempt to force the default configuration options on the controller specified by ControllerHandle and ChildHandle.
+ @retval EFI_OUT_RESOURCES There are not enough resources available to force the default configuration options on the controller specified by ControllerHandle and ChildHandle.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_DRIVER_CONFIGURATION_FORCE_DEFAULTS)(
+ IN EFI_DRIVER_CONFIGURATION_PROTOCOL *This,
+ IN EFI_HANDLE ControllerHandle,
+ IN EFI_HANDLE ChildHandle OPTIONAL,
+ IN UINT32 DefaultType,
+ OUT EFI_DRIVER_CONFIGURATION_ACTION_REQUIRED *ActionRequired
+ );
+
+///
+/// Used to set configuration options for a controller that an EFI Driver is managing.
+///
+struct _EFI_DRIVER_CONFIGURATION_PROTOCOL {
+ EFI_DRIVER_CONFIGURATION_SET_OPTIONS SetOptions;
+ EFI_DRIVER_CONFIGURATION_OPTIONS_VALID OptionsValid;
+ EFI_DRIVER_CONFIGURATION_FORCE_DEFAULTS ForceDefaults;
+ ///
+ /// A Null-terminated ASCII string that contains one or more
+ /// ISO 639-2 language codes. This is the list of language
+ /// codes that this protocol supports.
+ ///
+ CHAR8 *SupportedLanguages;
+};
+
+extern EFI_GUID gEfiDriverConfigurationProtocolGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/DriverConfiguration2.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/DriverConfiguration2.h
new file mode 100644
index 0000000000..6424b30a23
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/DriverConfiguration2.h
@@ -0,0 +1,184 @@
+/** @file
+ UEFI Driver Configuration2 Protocol
+
+ Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __EFI_DRIVER_CONFIGURATION2_H__
+#define __EFI_DRIVER_CONFIGURATION2_H__
+
+///
+/// Global ID for the Driver Configuration Protocol defined in UEFI 2.0
+///
+#define EFI_DRIVER_CONFIGURATION2_PROTOCOL_GUID \
+ { \
+ 0xbfd7dc1d, 0x24f1, 0x40d9, {0x82, 0xe7, 0x2e, 0x09, 0xbb, 0x6b, 0x4e, 0xbe } \
+ }
+
+typedef struct _EFI_DRIVER_CONFIGURATION2_PROTOCOL EFI_DRIVER_CONFIGURATION2_PROTOCOL;
+
+typedef enum {
+ ///
+ /// The controller is still in a usable state. No actions
+ /// are required before this controller can be used again.
+ ///
+ EfiDriverConfigurationActionNone = 0,
+ ///
+ /// The driver has detected that the controller is not in a
+ /// usable state, and it needs to be stopped.
+ ///
+ EfiDriverConfigurationActionStopController = 1,
+ ///
+ /// This controller needs to be stopped and restarted
+ /// before it can be used again.
+ ///
+ EfiDriverConfigurationActionRestartController = 2,
+ ///
+ /// A configuration change has been made that requires the platform to be restarted before
+ /// the controller can be used again.
+ ///
+ EfiDriverConfigurationActionRestartPlatform = 3,
+ EfiDriverConfigurationActionMaximum
+} EFI_DRIVER_CONFIGURATION_ACTION_REQUIRED;
+
+#define EFI_DRIVER_CONFIGURATION_SAFE_DEFAULTS 0x00000000
+#define EFI_DRIVER_CONFIGURATION_MANUFACTURING_DEFAULTS 0x00000001
+#define EFI_DRIVER_CONFIGURATION_CUSTOM_DEFAULTS 0x00000002
+#define EFI_DRIVER_CONFIGURATION_PERORMANCE_DEFAULTS 0x00000003
+
+/**
+ Allows the user to set controller specific options for a controller that a
+ driver is currently managing.
+
+ @param This A pointer to the EFI_DRIVER_CONFIGURATION2_PROTOCOL instance.
+ @param ControllerHandle The handle of the controller to set options on.
+ @param ChildHandle The handle of the child controller to set options on. This
+ is an optional parameter that may be NULL. It will be NULL
+ for device drivers, and for bus drivers that wish to set
+ options for the bus controller. It will not be NULL for a
+ bus driver that wishes to set options for one of its child
+ controllers.
+ @param Language A Null-terminated ASCII string that contains one or more RFC 4646
+ language codes. This is the list of language codes that this
+ protocol supports. The number of languages
+ supported by a driver is up to the driver writer.
+ @param ActionRequired A pointer to the action that the calling agent is required
+ to perform when this function returns. See "Related
+ Definitions" for a list of the actions that the calling
+ agent is required to perform prior to accessing
+ ControllerHandle again.
+
+ @retval EFI_SUCCESS The driver specified by This successfully set the
+ configuration options for the controller specified
+ by ControllerHandle.
+ @retval EFI_INVALID_PARAMETER ControllerHandle is not a valid EFI_HANDLE.
+ @retval EFI_INVALID_PARAMETER ChildHandle is not NULL and it is not a valid EFI_HANDLE.
+ @retval EFI_INVALID_PARAMETER ActionRequired is NULL.
+ @retval EFI_UNSUPPORTED The driver specified by This does not support setting
+ configuration options for the controller specified by
+ ControllerHandle and ChildHandle.
+ @retval EFI_UNSUPPORTED The driver specified by This does not support the
+ language specified by Language.
+ @retval EFI_DEVICE_ERROR A device error occurred while attempting to set the
+ configuration options for the controller specified
+ by ControllerHandle and ChildHandle.
+ @retval EFI_OUT_RESOURCES There are not enough resources available to set the
+ configuration options for the controller specified
+ by ControllerHandle and ChildHandle.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_DRIVER_CONFIGURATION2_SET_OPTIONS)(
+ IN EFI_DRIVER_CONFIGURATION2_PROTOCOL *This,
+ IN EFI_HANDLE ControllerHandle,
+ IN EFI_HANDLE ChildHandle OPTIONAL,
+ IN CHAR8 *Language,
+ OUT EFI_DRIVER_CONFIGURATION_ACTION_REQUIRED *ActionRequired
+ );
+
+/**
+ Tests to see if a controller's current configuration options are valid.
+
+ @param This A pointer to the EFI_DRIVER_CONFIGURATION2_PROTOCOL instance.
+ @param ControllerHandle The handle of the controller to test if it's current
+ configuration options are valid.
+ @param ChildHandle The handle of the child controller to test if it's current
+ configuration options are valid. This is an optional
+ parameter that may be NULL. It will be NULL for device
+ drivers. It will also be NULL for bus drivers that wish
+ to test the configuration options for the bus controller.
+ It will not be NULL for a bus driver that wishes to test
+ configuration options for one of its child controllers.
+
+ @retval EFI_SUCCESS The controller specified by ControllerHandle and
+ ChildHandle that is being managed by the driver
+ specified by This has a valid set of configuration
+ options.
+ @retval EFI_INVALID_PARAMETER ControllerHandle is not a valid EFI_HANDLE.
+ @retval EFI_INVALID_PARAMETER ChildHandle is not NULL and it is not a valid EFI_HANDLE.
+ @retval EFI_UNSUPPORTED The driver specified by This is not currently
+ managing the controller specified by ControllerHandle
+ and ChildHandle.
+ @retval EFI_DEVICE_ERROR The controller specified by ControllerHandle and
+ ChildHandle that is being managed by the driver
+ specified by This has an invalid set of configuration
+ options.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_DRIVER_CONFIGURATION2_OPTIONS_VALID)(
+ IN EFI_DRIVER_CONFIGURATION2_PROTOCOL *This,
+ IN EFI_HANDLE ControllerHandle,
+ IN EFI_HANDLE ChildHandle OPTIONAL
+ );
+
+/**
+ Forces a driver to set the default configuration options for a controller.
+
+ @param This A pointer to the EFI_DRIVER_CONFIGURATION2_PROTOCOL instance.
+ @param ControllerHandle The handle of the controller to force default configuration options on.
+ @param ChildHandle The handle of the child controller to force default configuration options on This is an optional parameter that may be NULL. It will be NULL for device drivers. It will also be NULL for bus drivers that wish to force default configuration options for the bus controller. It will not be NULL for a bus driver that wishes to force default configuration options for one of its child controllers.
+ @param DefaultType The type of default configuration options to force on the controller specified by ControllerHandle and ChildHandle. See Table 9-1 for legal values. A DefaultType of 0x00000000 must be supported by this protocol.
+ @param ActionRequired A pointer to the action that the calling agent is required to perform when this function returns. See "Related Definitions" in Section 9.1 for a list of the actions that the calling agent is required to perform prior to accessing ControllerHandle again.
+
+ @retval EFI_SUCCESS The driver specified by This successfully forced the default configuration options on the controller specified by ControllerHandle and ChildHandle.
+ @retval EFI_INVALID_PARAMETER ControllerHandle is not a valid EFI_HANDLE.
+ @retval EFI_INVALID_PARAMETER ChildHandle is not NULL and it is not a valid EFI_HANDLE.
+ @retval EFI_INVALID_PARAMETER ActionRequired is NULL.
+ @retval EFI_UNSUPPORTED The driver specified by This does not support forcing the default configuration options on the controller specified by ControllerHandle and ChildHandle.
+ @retval EFI_UNSUPPORTED The driver specified by This does not support the configuration type specified by DefaultType.
+ @retval EFI_DEVICE_ERROR A device error occurred while attempt to force the default configuration options on the controller specified by ControllerHandle and ChildHandle.
+ @retval EFI_OUT_RESOURCES There are not enough resources available to force the default configuration options on the controller specified by ControllerHandle and ChildHandle.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_DRIVER_CONFIGURATION2_FORCE_DEFAULTS)(
+ IN EFI_DRIVER_CONFIGURATION2_PROTOCOL *This,
+ IN EFI_HANDLE ControllerHandle,
+ IN EFI_HANDLE ChildHandle OPTIONAL,
+ IN UINT32 DefaultType,
+ OUT EFI_DRIVER_CONFIGURATION_ACTION_REQUIRED *ActionRequired
+ );
+
+///
+/// Used to set configuration options for a controller that an EFI Driver is managing.
+///
+struct _EFI_DRIVER_CONFIGURATION2_PROTOCOL {
+ EFI_DRIVER_CONFIGURATION2_SET_OPTIONS SetOptions;
+ EFI_DRIVER_CONFIGURATION2_OPTIONS_VALID OptionsValid;
+ EFI_DRIVER_CONFIGURATION2_FORCE_DEFAULTS ForceDefaults;
+ ///
+ /// A Null-terminated ASCII string that contains one or more RFC 4646
+ /// language codes. This is the list of language codes that this protocol supports.
+ ///
+ CHAR8 *SupportedLanguages;
+};
+
+extern EFI_GUID gEfiDriverConfiguration2ProtocolGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/DriverDiagnostics.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/DriverDiagnostics.h
new file mode 100644
index 0000000000..e628d0a2bb
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/DriverDiagnostics.h
@@ -0,0 +1,125 @@
+/** @file
+ EFI Driver Diagnostics Protocol
+
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __EFI_DRIVER_DIAGNOSTICS_H__
+#define __EFI_DRIVER_DIAGNOSTICS_H__
+
+///
+/// The global ID for the Driver Diagnostics Protocol as defined in EFI 1.1.
+///
+#define EFI_DRIVER_DIAGNOSTICS_PROTOCOL_GUID \
+ { \
+ 0x0784924f, 0xe296, 0x11d4, {0x9a, 0x49, 0x0, 0x90, 0x27, 0x3f, 0xc1, 0x4d } \
+ }
+
+typedef struct _EFI_DRIVER_DIAGNOSTICS_PROTOCOL EFI_DRIVER_DIAGNOSTICS_PROTOCOL;
+
+typedef enum {
+ ///
+ /// Performs standard diagnostics on the controller.
+ ///
+ EfiDriverDiagnosticTypeStandard = 0,
+ ///
+ /// This is an optional diagnostic type that performs diagnostics on the controller that may
+ /// take an extended amount of time to execute.
+ ///
+ EfiDriverDiagnosticTypeExtended = 1,
+ ///
+ /// This is an optional diagnostic type that performs diagnostics on the controller that are
+ /// suitable for a manufacturing and test environment.
+ ///
+ EfiDriverDiagnosticTypeManufacturing = 2,
+ ///
+ /// This is an optional diagnostic type that would only be used in the situation where an
+ /// EFI_NOT_READY had been returned by a previous call to RunDiagnostics()
+ /// and there is a desire to cancel the current running diagnostics operation.
+ ///
+ EfiDriverDiagnosticTypeCancel = 3,
+ EfiDriverDiagnosticTypeMaximum
+} EFI_DRIVER_DIAGNOSTIC_TYPE;
+
+/**
+ Runs diagnostics on a controller.
+
+ @param This A pointer to the EFI_DRIVER_DIAGNOSTICS_PROTOCOL instance.
+ @param ControllerHandle The handle of the controller to run diagnostics on.
+ @param ChildHandle The handle of the child controller to run diagnostics on
+ This is an optional parameter that may be NULL. It will
+ be NULL for device drivers. It will also be NULL for a
+ bus drivers that wish to run diagnostics on the bus
+ controller. It will not be NULL for a bus driver that
+ wishes to run diagnostics on one of its child controllers.
+ @param DiagnosticType Indicates type of diagnostics to perform on the controller
+ specified by ControllerHandle and ChildHandle. See
+ "Related Definitions" for the list of supported types.
+ @param Language A pointer to a three character ISO 639-2 language
+ identifier. This is the language in which the optional
+ error message should be returned in Buffer, and it must
+ match one of the languages specified in SupportedLanguages.
+ The number of languages supported by a driver is up to
+ the driver writer.
+ @param ErrorType A GUID that defines the format of the data returned in Buffer.
+ @param BufferSize The size, in bytes, of the data returned in Buffer.
+ @param Buffer A buffer that contains a Null-terminated string
+ plus some additional data whose format is defined by
+ ErrorType. Buffer is allocated by this function with
+ AllocatePool(), and it is the caller's responsibility
+ to free it with a call to FreePool().
+
+ @retval EFI_SUCCESS The controller specified by ControllerHandle and
+ ChildHandle passed the diagnostic.
+ @retval EFI_INVALID_PARAMETER ControllerHandle is NULL.
+ @retval EFI_INVALID_PARAMETER ChildHandle is not NULL, and it is not a valid EFI_HANDLE.
+ @retval EFI_INVALID_PARAMETER Language is NULL.
+ @retval EFI_INVALID_PARAMETER ErrorType is NULL.
+ @retval EFI_INVALID_PARAMETER BufferType is NULL.
+ @retval EFI_INVALID_PARAMETER Buffer is NULL.
+ @retval EFI_UNSUPPORTED The driver specified by This does not support
+ running diagnostics for the controller specified
+ by ControllerHandle and ChildHandle.
+ @retval EFI_UNSUPPORTED The driver specified by This does not support the
+ type of diagnostic specified by DiagnosticType.
+ @retval EFI_UNSUPPORTED The driver specified by This does not support the
+ language specified by Language.
+ @retval EFI_OUT_OF_RESOURCES There are not enough resources available to complete
+ the diagnostics.
+ @retval EFI_OUT_OF_RESOURCES There are not enough resources available to return
+ the status information in ErrorType, BufferSize,
+ and Buffer.
+ @retval EFI_DEVICE_ERROR The controller specified by ControllerHandle and
+ ChildHandle did not pass the diagnostic.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_DRIVER_DIAGNOSTICS_RUN_DIAGNOSTICS)(
+ IN EFI_DRIVER_DIAGNOSTICS_PROTOCOL *This,
+ IN EFI_HANDLE ControllerHandle,
+ IN EFI_HANDLE ChildHandle OPTIONAL,
+ IN EFI_DRIVER_DIAGNOSTIC_TYPE DiagnosticType,
+ IN CHAR8 *Language,
+ OUT EFI_GUID **ErrorType,
+ OUT UINTN *BufferSize,
+ OUT CHAR16 **Buffer
+ );
+
+///
+/// Used to perform diagnostics on a controller that an EFI Driver is managing.
+///
+struct _EFI_DRIVER_DIAGNOSTICS_PROTOCOL {
+ EFI_DRIVER_DIAGNOSTICS_RUN_DIAGNOSTICS RunDiagnostics;
+ ///
+ /// A Null-terminated ASCII string that contains one or more ISO 639-2
+ /// language codes. This is the list of language codes that this protocol supports.
+ ///
+ CHAR8 *SupportedLanguages;
+};
+
+extern EFI_GUID gEfiDriverDiagnosticsProtocolGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/DriverDiagnostics2.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/DriverDiagnostics2.h
new file mode 100644
index 0000000000..ab48b02686
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/DriverDiagnostics2.h
@@ -0,0 +1,105 @@
+/** @file
+ UEFI Driver Diagnostics2 Protocol
+
+ Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __EFI_DRIVER_DIAGNOSTICS2_H__
+#define __EFI_DRIVER_DIAGNOSTICS2_H__
+
+#include
+
+#define EFI_DRIVER_DIAGNOSTICS2_PROTOCOL_GUID \
+ { \
+ 0x4d330321, 0x025f, 0x4aac, {0x90, 0xd8, 0x5e, 0xd9, 0x00, 0x17, 0x3b, 0x63 } \
+ }
+
+typedef struct _EFI_DRIVER_DIAGNOSTICS2_PROTOCOL EFI_DRIVER_DIAGNOSTICS2_PROTOCOL;
+
+/**
+ Runs diagnostics on a controller.
+
+ @param This A pointer to the EFI_DRIVER_DIAGNOSTICS2_PROTOCOL instance.
+ @param ControllerHandle The handle of the controller to run diagnostics on.
+ @param ChildHandle The handle of the child controller to run diagnostics on
+ This is an optional parameter that may be NULL. It will
+ be NULL for device drivers. It will also be NULL for
+ bus drivers that wish to run diagnostics on the bus
+ controller. It will not be NULL for a bus driver that
+ wishes to run diagnostics on one of its child controllers.
+ @param DiagnosticType Indicates the type of diagnostics to perform on the controller
+ specified by ControllerHandle and ChildHandle. See
+ "Related Definitions" for the list of supported types.
+ @param Language A pointer to a Null-terminated ASCII string
+ array indicating the language. This is the
+ language of the driver name that the caller
+ is requesting, and it must match one of the
+ languages specified in SupportedLanguages.
+ The number of languages supported by a
+ driver is up to the driver writer. Language
+ is specified in RFC 4646 language code format.
+ @param ErrorType A GUID that defines the format of the data returned in Buffer.
+ @param BufferSize The size, in bytes, of the data returned in Buffer.
+ @param Buffer A buffer that contains a Null-terminated Unicode string
+ plus some additional data whose format is defined by
+ ErrorType. Buffer is allocated by this function with
+ AllocatePool(), and it is the caller's responsibility
+ to free it with a call to FreePool().
+
+ @retval EFI_SUCCESS The controller specified by ControllerHandle and
+ ChildHandle passed the diagnostic.
+ @retval EFI_ACCESS_DENIED The request for initiating diagnostics was unable
+ to be complete due to some underlying hardware or
+ software state.
+ @retval EFI_INVALID_PARAMETER ControllerHandle is NULL.
+ @retval EFI_INVALID_PARAMETER ChildHandle is not NULL and it is not a valid EFI_HANDLE.
+ @retval EFI_INVALID_PARAMETER Language is NULL.
+ @retval EFI_INVALID_PARAMETER ErrorType is NULL.
+ @retval EFI_INVALID_PARAMETER BufferType is NULL.
+ @retval EFI_INVALID_PARAMETER Buffer is NULL.
+ @retval EFI_UNSUPPORTED The driver specified by This does not support
+ running diagnostics for the controller specified
+ by ControllerHandle and ChildHandle.
+ @retval EFI_UNSUPPORTED The driver specified by This does not support the
+ type of diagnostic specified by DiagnosticType.
+ @retval EFI_UNSUPPORTED The driver specified by This does not support the
+ language specified by Language.
+ @retval EFI_OUT_OF_RESOURCES There are not enough resources available to complete
+ the diagnostics.
+ @retval EFI_OUT_OF_RESOURCES There are not enough resources available to return
+ the status information in ErrorType, BufferSize,
+ and Buffer.
+ @retval EFI_DEVICE_ERROR The controller specified by ControllerHandle and
+ ChildHandle did not pass the diagnostic.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_DRIVER_DIAGNOSTICS2_RUN_DIAGNOSTICS)(
+ IN EFI_DRIVER_DIAGNOSTICS2_PROTOCOL *This,
+ IN EFI_HANDLE ControllerHandle,
+ IN EFI_HANDLE ChildHandle OPTIONAL,
+ IN EFI_DRIVER_DIAGNOSTIC_TYPE DiagnosticType,
+ IN CHAR8 *Language,
+ OUT EFI_GUID **ErrorType,
+ OUT UINTN *BufferSize,
+ OUT CHAR16 **Buffer
+ );
+
+///
+/// Used to perform diagnostics on a controller that an EFI Driver is managing.
+///
+struct _EFI_DRIVER_DIAGNOSTICS2_PROTOCOL {
+ EFI_DRIVER_DIAGNOSTICS2_RUN_DIAGNOSTICS RunDiagnostics;
+ ///
+ /// A Null-terminated ASCII string that contains one or more RFC 4646
+ /// language codes. This is the list of language codes that this protocol supports.
+ ///
+ CHAR8 *SupportedLanguages;
+};
+
+extern EFI_GUID gEfiDriverDiagnostics2ProtocolGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/DriverFamilyOverride.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/DriverFamilyOverride.h
new file mode 100644
index 0000000000..828b9f8bd7
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/DriverFamilyOverride.h
@@ -0,0 +1,61 @@
+/** @file
+ UEFI Driver Family Protocol
+
+Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __EFI_DRIVER_FAMILY_OVERRIDE_H__
+#define __EFI_DRIVER_FAMILY_OVERRIDE_H__
+
+#define EFI_DRIVER_FAMILY_OVERRIDE_PROTOCOL_GUID \
+ { \
+ 0xb1ee129e, 0xda36, 0x4181, { 0x91, 0xf8, 0x4, 0xa4, 0x92, 0x37, 0x66, 0xa7 } \
+ }
+
+typedef struct _EFI_DRIVER_FAMILY_OVERRIDE_PROTOCOL EFI_DRIVER_FAMILY_OVERRIDE_PROTOCOL;
+
+//
+// Prototypes for the Driver Family Override Protocol
+//
+//
+
+/**
+ This function returns the version value associated with the driver specified by This.
+
+ Retrieves the version of the driver that is used by the EFI Boot Service ConnectController()
+ to sort the set of Driver Binding Protocols in order from highest priority to lowest priority.
+ For drivers that support the Driver Family Override Protocol, those drivers are sorted so that
+ the drivers with higher values returned by GetVersion() are higher priority than drivers that
+ return lower values from GetVersion().
+
+ @param This A pointer to the EFI_DRIVER_FAMILY_OVERRIDE_PROTOCOL instance.
+
+ @return The version value associated with the driver specified by This.
+
+**/
+typedef
+UINT32
+(EFIAPI *EFI_DRIVER_FAMILY_OVERRIDE_GET_VERSION)(
+ IN EFI_DRIVER_FAMILY_OVERRIDE_PROTOCOL *This
+ );
+
+///
+/// When installed, the Driver Family Override Protocol produces a GUID that represents
+/// a family of drivers. Drivers with the same GUID are members of the same family
+/// When drivers are connected to controllers, drivers with a higher revision value
+/// in the same driver family are connected with a higher priority than drivers
+/// with a lower revision value in the same driver family. The EFI Boot Service
+/// Connect Controller uses five rules to build a prioritized list of drivers when
+/// a request is made to connect a driver to a controller. The Driver Family Protocol
+/// rule is between the Platform Specific Driver Override Protocol and above the
+/// Bus Specific Driver Override Protocol.
+///
+struct _EFI_DRIVER_FAMILY_OVERRIDE_PROTOCOL {
+ EFI_DRIVER_FAMILY_OVERRIDE_GET_VERSION GetVersion;
+};
+
+extern EFI_GUID gEfiDriverFamilyOverrideProtocolGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/DriverHealth.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/DriverHealth.h
new file mode 100644
index 0000000000..1fab61a6bd
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/DriverHealth.h
@@ -0,0 +1,237 @@
+/** @file
+ EFI Driver Health Protocol definitions.
+
+ When installed, the Driver Health Protocol produces a collection of services that allow
+ the health status for a controller to be retrieved. If a controller is not in a usable
+ state, status messages may be reported to the user, repair operations can be invoked,
+ and the user may be asked to make software and/or hardware configuration changes.
+
+ The Driver Health Protocol is optionally produced by a driver that follows the
+ EFI Driver Model. If an EFI Driver needs to report health status to the platform,
+ provide warning or error messages to the user, perform length repair operations,
+ or request the user to make hardware or software configuration changes, then the
+ Driver Health Protocol must be produced.
+
+ A controller that is managed by driver that follows the EFI Driver Model and
+ produces the Driver Health Protocol must report the current health of the
+ controllers that the driver is currently managing. The controller can initially
+ be healthy, failed, require repair, or require configuration. If a controller
+ requires configuration, and the user make configuration changes, the controller
+ may then need to be reconnected or the system may need to be rebooted for the
+ configuration changes to take affect.
+
+ Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.
+ Copyright (c) 2014, Hewlett-Packard Development Company, L.P.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Revision Reference:
+ This Protocol is defined in UEFI Specification 2.3d
+
+**/
+
+#ifndef __EFI_DRIVER_HEALTH_H__
+#define __EFI_DRIVER_HEALTH_H__
+
+#define EFI_DRIVER_HEALTH_PROTOCOL_GUID \
+ { \
+ 0x2a534210, 0x9280, 0x41d8, { 0xae, 0x79, 0xca, 0xda, 0x1, 0xa2, 0xb1, 0x27 } \
+ }
+
+typedef struct _EFI_DRIVER_HEALTH_PROTOCOL EFI_DRIVER_HEALTH_PROTOCOL;
+
+///
+/// EFI_DRIVER_HEALTH_HEALTH_STATUS
+///
+typedef enum {
+ EfiDriverHealthStatusHealthy,
+ EfiDriverHealthStatusRepairRequired,
+ EfiDriverHealthStatusConfigurationRequired,
+ EfiDriverHealthStatusFailed,
+ EfiDriverHealthStatusReconnectRequired,
+ EfiDriverHealthStatusRebootRequired
+} EFI_DRIVER_HEALTH_STATUS;
+
+///
+/// EFI_DRIVER_HEALTH_HII_MESSAGE
+///
+typedef struct {
+ EFI_HII_HANDLE HiiHandle;
+ EFI_STRING_ID StringId;
+
+ ///
+ /// 64-bit numeric value of the warning/error specified by this message.
+ /// A value of 0x0000000000000000 is used to indicate that MessageCode is not specified.
+ /// The values 0x0000000000000001 to 0x0fffffffffffffff are reserved for allocation by the UEFI Specification.
+ /// The values 0x1000000000000000 to 0x1fffffffffffffff are reserved for IHV-developed drivers.
+ /// The values 0x8000000000000000 to 0x8fffffffffffffff is reserved for platform/OEM drivers.
+ /// All other values are reserved and should not be used.
+ ///
+ UINT64 MessageCode;
+} EFI_DRIVER_HEALTH_HII_MESSAGE;
+
+/**
+ Reports the progress of a repair operation
+
+ @param[in] Value A value between 0 and Limit that identifies the current
+ progress of the repair operation.
+
+ @param[in] Limit The maximum value of Value for the current repair operation.
+ For example, a driver that wants to specify progress in
+ percent would use a Limit value of 100.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_DRIVER_HEALTH_REPAIR_NOTIFY)(
+ IN UINTN Value,
+ IN UINTN Limit
+ );
+
+/**
+ Retrieves the health status of a controller in the platform. This function can also
+ optionally return warning messages, error messages, and a set of HII Forms that may
+ be repair a controller that is not proper configured.
+
+ @param[in] This A pointer to the EFI_DRIVER_HEALTH_PROTOCOL instance.
+
+ @param[in] ControllerHandle The handle of the controller to retrieve the health status
+ on. This is an optional parameter that may be NULL. If
+ this parameter is NULL, then the value of ChildHandle is
+ ignored, and the combined health status of all the devices
+ that the driver is managing is returned.
+
+ @param[in] ChildHandle The handle of the child controller to retrieve the health
+ status on. This is an optional parameter that may be NULL.
+ This parameter is ignored of ControllerHandle is NULL. It
+ will be NULL for device drivers. It will also be NULL for
+ bus drivers when an attempt is made to collect the health
+ status of the bus controller. If will not be NULL when an
+ attempt is made to collect the health status for a child
+ controller produced by the driver.
+
+ @param[out] HealthStatus A pointer to the health status that is returned by this
+ function. This is an optional parameter that may be NULL.
+ This parameter is ignored of ControllerHandle is NULL.
+ The health status for the controller specified by
+ ControllerHandle and ChildHandle is returned.
+
+ @param[out] MessageList A pointer to an array of warning or error messages associated
+ with the controller specified by ControllerHandle and
+ ChildHandle. This is an optional parameter that may be NULL.
+ MessageList is allocated by this function with the EFI Boot
+ Service AllocatePool(), and it is the caller's responsibility
+ to free MessageList with the EFI Boot Service FreePool().
+ Each message is specified by tuple of an EFI_HII_HANDLE and
+ an EFI_STRING_ID. The array of messages is terminated by tuple
+ containing a EFI_HII_HANDLE with a value of NULL. The
+ EFI_HII_STRING_PROTOCOL.GetString() function can be used to
+ retrieve the warning or error message as a Null-terminated
+ string in a specific language. Messages may be
+ returned for any of the HealthStatus values except
+ EfiDriverHealthStatusReconnectRequired and
+ EfiDriverHealthStatusRebootRequired.
+
+ @param[out] FormHiiHandle A pointer to the HII handle containing the HII form used when
+ configuration is required. The HII handle is associated with
+ the controller specified by ControllerHandle and ChildHandle.
+ If this is NULL, then no HII form is available. An HII handle
+ will only be returned with a HealthStatus value of
+ EfiDriverHealthStatusConfigurationRequired.
+
+ @retval EFI_SUCCESS ControllerHandle is NULL, and all the controllers
+ managed by this driver specified by This have a health
+ status of EfiDriverHealthStatusHealthy with no warning
+ messages to be returned. The ChildHandle, HealthStatus,
+ MessageList, and FormList parameters are ignored.
+
+ @retval EFI_DEVICE_ERROR ControllerHandle is NULL, and one or more of the
+ controllers managed by this driver specified by This
+ do not have a health status of EfiDriverHealthStatusHealthy.
+ The ChildHandle, HealthStatus, MessageList, and
+ FormList parameters are ignored.
+
+ @retval EFI_DEVICE_ERROR ControllerHandle is NULL, and one or more of the
+ controllers managed by this driver specified by This
+ have one or more warning and/or error messages.
+ The ChildHandle, HealthStatus, MessageList, and
+ FormList parameters are ignored.
+
+ @retval EFI_SUCCESS ControllerHandle is not NULL and the health status
+ of the controller specified by ControllerHandle and
+ ChildHandle was returned in HealthStatus. A list
+ of warning and error messages may be optionally
+ returned in MessageList, and a list of HII Forms
+ may be optionally returned in FormList.
+
+ @retval EFI_UNSUPPORTED ControllerHandle is not NULL, and the controller
+ specified by ControllerHandle and ChildHandle is not
+ currently being managed by the driver specified by This.
+
+ @retval EFI_INVALID_PARAMETER HealthStatus is NULL.
+
+ @retval EFI_OUT_OF_RESOURCES MessageList is not NULL, and there are not enough
+ resource available to allocate memory for MessageList.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_DRIVER_HEALTH_GET_HEALTH_STATUS)(
+ IN EFI_DRIVER_HEALTH_PROTOCOL *This,
+ IN EFI_HANDLE ControllerHandle OPTIONAL,
+ IN EFI_HANDLE ChildHandle OPTIONAL,
+ OUT EFI_DRIVER_HEALTH_STATUS *HealthStatus,
+ OUT EFI_DRIVER_HEALTH_HII_MESSAGE **MessageList OPTIONAL,
+ OUT EFI_HII_HANDLE *FormHiiHandle OPTIONAL
+ );
+
+/**
+ Performs a repair operation on a controller in the platform. This function can
+ optionally report repair progress information back to the platform.
+
+ @param[in] This A pointer to the EFI_DRIVER_HEALTH_PROTOCOL instance.
+ @param[in] ControllerHandle The handle of the controller to repair.
+ @param[in] ChildHandle The handle of the child controller to repair. This is
+ an optional parameter that may be NULL. It will be NULL
+ for device drivers. It will also be NULL for bus
+ drivers when an attempt is made to repair a bus controller.
+ If will not be NULL when an attempt is made to repair a
+ child controller produced by the driver.
+ @param[in] RepairNotify A notification function that may be used by a driver to
+ report the progress of the repair operation. This is
+ an optional parameter that may be NULL.
+
+
+ @retval EFI_SUCCESS An attempt to repair the controller specified by
+ ControllerHandle and ChildHandle was performed.
+ The result of the repair operation can bet
+ determined by calling GetHealthStatus().
+ @retval EFI_UNSUPPORTED The driver specified by This is not currently
+ managing the controller specified by ControllerHandle
+ and ChildHandle.
+ @retval EFI_OUT_OF_RESOURCES There are not enough resources to perform the
+ repair operation.
+
+*/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_DRIVER_HEALTH_REPAIR)(
+ IN EFI_DRIVER_HEALTH_PROTOCOL *This,
+ IN EFI_HANDLE ControllerHandle,
+ IN EFI_HANDLE ChildHandle OPTIONAL,
+ IN EFI_DRIVER_HEALTH_REPAIR_NOTIFY RepairNotify OPTIONAL
+ );
+
+///
+/// When installed, the Driver Health Protocol produces a collection of services
+/// that allow the health status for a controller to be retrieved. If a controller
+/// is not in a usable state, status messages may be reported to the user, repair
+/// operations can be invoked, and the user may be asked to make software and/or
+/// hardware configuration changes.
+///
+struct _EFI_DRIVER_HEALTH_PROTOCOL {
+ EFI_DRIVER_HEALTH_GET_HEALTH_STATUS GetHealthStatus;
+ EFI_DRIVER_HEALTH_REPAIR Repair;
+};
+
+extern EFI_GUID gEfiDriverHealthProtocolGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/DriverSupportedEfiVersion.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/DriverSupportedEfiVersion.h
new file mode 100644
index 0000000000..38410e2456
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/DriverSupportedEfiVersion.h
@@ -0,0 +1,39 @@
+/** @file
+ The protocol provides information about the version of the EFI
+ specification that a driver is following. This protocol is
+ required for EFI drivers that are on PCI and other plug-in
+ cards.
+
+ Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __DRIVER_SUPPORTED_EFI_VERSION_H__
+#define __DRIVER_SUPPORTED_EFI_VERSION_H__
+
+#define EFI_DRIVER_SUPPORTED_EFI_VERSION_PROTOCOL_GUID \
+ { 0x5c198761, 0x16a8, 0x4e69, { 0x97, 0x2c, 0x89, 0xd6, 0x79, 0x54, 0xf8, 0x1d } }
+
+///
+/// The EFI_DRIVER_SUPPORTED_EFI_VERSION_PROTOCOL provides a
+/// mechanism for an EFI driver to publish the version of the EFI
+/// specification it conforms to. This protocol must be placed on
+/// the driver's image handle when the driver's entry point is
+/// called.
+///
+typedef struct _EFI_DRIVER_SUPPORTED_EFI_VERSION_PROTOCOL {
+ ///
+ /// The size, in bytes, of the entire structure. Future versions of this
+ /// specification may grow the size of the structure.
+ ///
+ UINT32 Length;
+ ///
+ /// The latest version of the UEFI specification that this driver conforms to.
+ ///
+ UINT32 FirmwareVersion;
+} EFI_DRIVER_SUPPORTED_EFI_VERSION_PROTOCOL;
+
+extern EFI_GUID gEfiDriverSupportedEfiVersionProtocolGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/DxeMmReadyToLock.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/DxeMmReadyToLock.h
new file mode 100644
index 0000000000..5a36a1f37e
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/DxeMmReadyToLock.h
@@ -0,0 +1,19 @@
+/** @file
+ DXE MM Ready To Lock protocol introduced in the PI 1.5 specification.
+
+ Copyright (c) 2017, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _DXE_MM_READY_TO_LOCK_H_
+#define _DXE_MM_READY_TO_LOCK_H_
+
+#define EFI_DXE_MM_READY_TO_LOCK_PROTOCOL_GUID \
+ { \
+ 0x60ff8964, 0xe906, 0x41d0, { 0xaf, 0xed, 0xf2, 0x41, 0xe9, 0x74, 0xe0, 0x8e } \
+ }
+
+extern EFI_GUID gEfiDxeMmReadyToLockProtocolGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/DxeSmmReadyToLock.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/DxeSmmReadyToLock.h
new file mode 100644
index 0000000000..b3735e6494
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/DxeSmmReadyToLock.h
@@ -0,0 +1,34 @@
+/** @file
+ DXE SMM Ready To Lock protocol introduced in the PI 1.2 specification.
+
+ According to PI 1.4a specification, this UEFI protocol indicates that
+ resources and services that should not be used by the third party code
+ are about to be locked.
+ This protocol is a mandatory protocol published by PI platform code.
+ This protocol in tandem with the End of DXE Event facilitates transition
+ of the platform from the environment where all of the components are
+ under the authority of the platform manufacturer to the environment where
+ third party extensible modules such as UEFI drivers and UEFI applications
+ are executed. The protocol is published immediately after signaling of the
+ End of DXE Event. PI modules that need to lock or protect their resources
+ in anticipation of the invocation of 3rd party extensible modules should
+ register for notification on installation of this protocol and effect the
+ appropriate protections in their notification handlers. For example, PI
+ platform code may choose to use notification handler to lock SMM by invoking
+ EFI_SMM_ACCESS2_PROTOCOL.Lock() function.
+
+ Copyright (c) 2009 - 2017, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _DXE_SMM_READY_TO_LOCK_H_
+#define _DXE_SMM_READY_TO_LOCK_H_
+
+#include
+
+#define EFI_DXE_SMM_READY_TO_LOCK_PROTOCOL_GUID EFI_DXE_MM_READY_TO_LOCK_PROTOCOL_GUID
+
+extern EFI_GUID gEfiDxeSmmReadyToLockProtocolGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/Eap.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/Eap.h
new file mode 100644
index 0000000000..1b2950ae36
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/Eap.h
@@ -0,0 +1,154 @@
+/** @file
+ EFI EAP(Extended Authenticaton Protocol) Protocol Definition
+ The EFI EAP Protocol is used to abstract the ability to configure and extend the
+ EAP framework.
+ The definitions in this file are defined in UEFI Specification 2.3.1B, which have
+ not been verified by one implementation yet.
+
+ Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Revision Reference:
+ This Protocol is introduced in UEFI Specification 2.2
+
+**/
+
+#ifndef __EFI_EAP_PROTOCOL_H__
+#define __EFI_EAP_PROTOCOL_H__
+
+#define EFI_EAP_PROTOCOL_GUID \
+ { \
+ 0x5d9f96db, 0xe731, 0x4caa, {0xa0, 0xd, 0x72, 0xe1, 0x87, 0xcd, 0x77, 0x62 } \
+ }
+
+typedef struct _EFI_EAP_PROTOCOL EFI_EAP_PROTOCOL;
+
+///
+/// Type for the identification number assigned to the Port by the
+/// System in which the Port resides.
+///
+typedef VOID *EFI_PORT_HANDLE;
+
+///
+/// EAP Authentication Method Type (RFC 3748)
+///@{
+#define EFI_EAP_TYPE_TLS 13///< REQUIRED - RFC 5216
+///@}
+
+//
+// EAP_TYPE MD5, OTP and TOEKN_CARD has been removed from UEFI2.3.1B.
+// Definitions are kept for backward compatibility.
+//
+#define EFI_EAP_TYPE_MD5 4
+#define EFI_EAP_TYPE_OTP 5
+#define EFI_EAP_TYPE_TOKEN_CARD 6
+
+/**
+ One user provided EAP authentication method.
+
+ Build EAP response packet in response to the EAP request packet specified by
+ (RequestBuffer, RequestSize).
+
+ @param[in] PortNumber Specified the Port where the EAP request packet comes.
+ @param[in] RequestBuffer Pointer to the most recently received EAP- Request packet.
+ @param[in] RequestSize Packet size in bytes for the most recently received
+ EAP-Request packet.
+ @param[in] Buffer Pointer to the buffer to hold the built packet.
+ @param[in, out] BufferSize Pointer to the buffer size in bytes.
+ On input, it is the buffer size provided by the caller.
+ On output, it is the buffer size in fact needed to contain
+ the packet.
+
+ @retval EFI_SUCCESS The required EAP response packet is built successfully.
+ @retval others Failures are encountered during the packet building process.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_EAP_BUILD_RESPONSE_PACKET)(
+ IN EFI_PORT_HANDLE PortNumber,
+ IN UINT8 *RequestBuffer,
+ IN UINTN RequestSize,
+ IN UINT8 *Buffer,
+ IN OUT UINTN *BufferSize
+ );
+
+/**
+ Set the desired EAP authentication method for the Port.
+
+ The SetDesiredAuthMethod() function sets the desired EAP authentication method indicated
+ by EapAuthType for the Port.
+
+ If EapAuthType is an invalid EAP authentication type, then EFI_INVALID_PARAMETER is
+ returned.
+ If the EAP authentication method of EapAuthType is unsupported by the Ports, then it will
+ return EFI_UNSUPPORTED.
+ The cryptographic strength of EFI_EAP_TYPE_TLS shall be at least of hash strength
+ SHA-256 and RSA key length of at least 2048 bits.
+
+ @param[in] This A pointer to the EFI_EAP_PROTOCOL instance that indicates
+ the calling context.
+ @param[in] EapAuthType The type of the EAP authentication method to register. It should
+ be the type value defined by RFC. See RFC 2284 for details.
+ @param[in] Handler The handler of the EAP authentication method to register.
+
+ @retval EFI_SUCCESS The EAP authentication method of EapAuthType is
+ registered successfully.
+ @retval EFI_INVALID_PARAMETER EapAuthType is an invalid EAP authentication type.
+ @retval EFI_UNSUPPORTED The EAP authentication method of EapAuthType is
+ unsupported by the Port.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_EAP_SET_DESIRED_AUTHENTICATION_METHOD)(
+ IN EFI_EAP_PROTOCOL *This,
+ IN UINT8 EapAuthType
+ );
+
+/**
+ Register an EAP authentication method.
+
+ The RegisterAuthMethod() function registers the user provided EAP authentication method,
+ the type of which is EapAuthType and the handler of which is Handler.
+
+ If EapAuthType is an invalid EAP authentication type, then EFI_INVALID_PARAMETER is
+ returned.
+ If there is not enough system memory to perform the registration, then
+ EFI_OUT_OF_RESOURCES is returned.
+
+ @param[in] This A pointer to the EFI_EAP_PROTOCOL instance that indicates
+ the calling context.
+ @param[in] EapAuthType The type of the EAP authentication method to register. It should
+ be the type value defined by RFC. See RFC 2284 for details.
+ @param[in] Handler The handler of the EAP authentication method to register.
+
+ @retval EFI_SUCCESS The EAP authentication method of EapAuthType is
+ registered successfully.
+ @retval EFI_INVALID_PARAMETER EapAuthType is an invalid EAP authentication type.
+ @retval EFI_OUT_OF_RESOURCES There is not enough system memory to perform the registration.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_EAP_REGISTER_AUTHENTICATION_METHOD)(
+ IN EFI_EAP_PROTOCOL *This,
+ IN UINT8 EapAuthType,
+ IN EFI_EAP_BUILD_RESPONSE_PACKET Handler
+ );
+
+///
+/// EFI_EAP_PROTOCOL
+/// is used to configure the desired EAP authentication method for the EAP
+/// framework and extend the EAP framework by registering new EAP authentication
+/// method on a Port. The EAP framework is built on a per-Port basis. Herein, a
+/// Port means a NIC. For the details of EAP protocol, please refer to RFC 2284.
+///
+struct _EFI_EAP_PROTOCOL {
+ EFI_EAP_SET_DESIRED_AUTHENTICATION_METHOD SetDesiredAuthMethod;
+ EFI_EAP_REGISTER_AUTHENTICATION_METHOD RegisterAuthMethod;
+};
+
+extern EFI_GUID gEfiEapProtocolGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/EapConfiguration.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/EapConfiguration.h
new file mode 100644
index 0000000000..5751efeb67
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/EapConfiguration.h
@@ -0,0 +1,153 @@
+/** @file
+ This file defines the EFI EAP Configuration protocol.
+
+ Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Revision Reference:
+ This Protocol is introduced in UEFI Specification 2.5
+
+**/
+
+#ifndef __EFI_EAP_CONFIGURATION_PROTOCOL_H__
+#define __EFI_EAP_CONFIGURATION_PROTOCOL_H__
+
+///
+/// EFI EAP Configuration protocol provides a way to set and get EAP configuration.
+///
+#define EFI_EAP_CONFIGURATION_PROTOCOL_GUID \
+ { \
+ 0xe5b58dbb, 0x7688, 0x44b4, {0x97, 0xbf, 0x5f, 0x1d, 0x4b, 0x7c, 0xc8, 0xdb } \
+ }
+
+typedef struct _EFI_EAP_CONFIGURATION_PROTOCOL EFI_EAP_CONFIGURATION_PROTOCOL;
+
+///
+/// Make sure it not conflict with any real EapTypeXXX
+///
+#define EFI_EAP_TYPE_ATTRIBUTE 0
+
+typedef enum {
+ ///
+ /// EFI_EAP_TYPE_ATTRIBUTE
+ ///
+ EfiEapConfigEapAuthMethod,
+ EfiEapConfigEapSupportedAuthMethod,
+ ///
+ /// EapTypeIdentity
+ ///
+ EfiEapConfigIdentityString,
+ ///
+ /// EapTypeEAPTLS/EapTypePEAP
+ ///
+ EfiEapConfigEapTlsCACert,
+ EfiEapConfigEapTlsClientCert,
+ EfiEapConfigEapTlsClientPrivateKeyFile,
+ EfiEapConfigEapTlsClientPrivateKeyFilePassword, // ASCII format, Volatile
+ EfiEapConfigEapTlsCipherSuite,
+ EfiEapConfigEapTlsSupportedCipherSuite,
+ ///
+ /// EapTypeMSChapV2
+ ///
+ EfiEapConfigEapMSChapV2Password, // UNICODE format, Volatile
+ ///
+ /// EapTypePEAP
+ ///
+ EfiEapConfigEap2ndAuthMethod,
+ ///
+ /// More...
+ ///
+} EFI_EAP_CONFIG_DATA_TYPE;
+
+///
+/// EFI_EAP_TYPE
+///
+typedef UINT8 EFI_EAP_TYPE;
+#define EFI_EAP_TYPE_ATTRIBUTE 0
+#define EFI_EAP_TYPE_IDENTITY 1
+#define EFI_EAP_TYPE_NOTIFICATION 2
+#define EFI_EAP_TYPE_NAK 3
+#define EFI_EAP_TYPE_MD5CHALLENGE 4
+#define EFI_EAP_TYPE_OTP 5
+#define EFI_EAP_TYPE_GTC 6
+#define EFI_EAP_TYPE_EAPTLS 13
+#define EFI_EAP_TYPE_EAPSIM 18
+#define EFI_EAP_TYPE_TTLS 21
+#define EFI_EAP_TYPE_PEAP 25
+#define EFI_EAP_TYPE_MSCHAPV2 26
+#define EFI_EAP_TYPE_EAP_EXTENSION 33
+
+/**
+ Set EAP configuration data.
+
+ The SetData() function sets EAP configuration to non-volatile storage or volatile
+ storage.
+
+ @param[in] This Pointer to the EFI_EAP_CONFIGURATION_PROTOCOL instance.
+ @param[in] EapType EAP type.
+ @param[in] DataType Configuration data type.
+ @param[in] Data Pointer to configuration data.
+ @param[in] DataSize Total size of configuration data.
+
+ @retval EFI_SUCCESS The EAP configuration data is set successfully.
+ @retval EFI_INVALID_PARAMETER One or more of the following conditions is TRUE:
+ Data is NULL.
+ DataSize is 0.
+ @retval EFI_UNSUPPORTED The EapType or DataType is unsupported.
+ @retval EFI_OUT_OF_RESOURCES Required system resources could not be allocated.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_EAP_CONFIGURATION_SET_DATA)(
+ IN EFI_EAP_CONFIGURATION_PROTOCOL *This,
+ IN EFI_EAP_TYPE EapType,
+ IN EFI_EAP_CONFIG_DATA_TYPE DataType,
+ IN VOID *Data,
+ IN UINTN DataSize
+ );
+
+/**
+ Get EAP configuration data.
+
+ The GetData() function gets EAP configuration.
+
+ @param[in] This Pointer to the EFI_EAP_CONFIGURATION_PROTOCOL instance.
+ @param[in] EapType EAP type.
+ @param[in] DataType Configuration data type.
+ @param[in, out] Data Pointer to configuration data.
+ @param[in, out] DataSize Total size of configuration data. On input, it means
+ the size of Data buffer. On output, it means the size
+ of copied Data buffer if EFI_SUCCESS, and means the
+ size of desired Data buffer if EFI_BUFFER_TOO_SMALL.
+
+ @retval EFI_SUCCESS The EAP configuration data is got successfully.
+ @retval EFI_INVALID_PARAMETER One or more of the following conditions is TRUE:
+ Data is NULL.
+ DataSize is NULL.
+ @retval EFI_UNSUPPORTED The EapType or DataType is unsupported.
+ @retval EFI_NOT_FOUND The EAP configuration data is not found.
+ @retval EFI_BUFFER_TOO_SMALL The buffer is too small to hold the buffer.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_EAP_CONFIGURATION_GET_DATA)(
+ IN EFI_EAP_CONFIGURATION_PROTOCOL *This,
+ IN EFI_EAP_TYPE EapType,
+ IN EFI_EAP_CONFIG_DATA_TYPE DataType,
+ IN OUT VOID *Data,
+ IN OUT UINTN *DataSize
+ );
+
+///
+/// The EFI_EAP_CONFIGURATION_PROTOCOL
+/// is designed to provide a way to set and get EAP configuration, such as Certificate,
+/// private key file.
+///
+struct _EFI_EAP_CONFIGURATION_PROTOCOL {
+ EFI_EAP_CONFIGURATION_SET_DATA SetData;
+ EFI_EAP_CONFIGURATION_GET_DATA GetData;
+};
+
+extern EFI_GUID gEfiEapConfigurationProtocolGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/EapManagement.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/EapManagement.h
new file mode 100644
index 0000000000..854459a35e
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/EapManagement.h
@@ -0,0 +1,396 @@
+/** @file
+ EFI EAP Management Protocol Definition
+ The EFI EAP Management Protocol is designed to provide ease of management and
+ ease of test for EAPOL state machine. It is intended for the supplicant side.
+ It conforms to IEEE 802.1x specification.
+ The definitions in this file are defined in UEFI Specification 2.2, which have
+ not been verified by one implementation yet.
+
+ Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Revision Reference:
+ This Protocol is introduced in UEFI Specification 2.2
+
+**/
+
+#ifndef __EFI_EAP_MANAGEMENT_PROTOCOL_H__
+#define __EFI_EAP_MANAGEMENT_PROTOCOL_H__
+
+#include
+
+#define EFI_EAP_MANAGEMENT_PROTOCOL_GUID \
+ { \
+ 0xbb62e663, 0x625d, 0x40b2, {0xa0, 0x88, 0xbb, 0xe8, 0x36, 0x23, 0xa2, 0x45 } \
+ }
+
+typedef struct _EFI_EAP_MANAGEMENT_PROTOCOL EFI_EAP_MANAGEMENT_PROTOCOL;
+
+///
+/// PAE Capabilities
+///
+///@{
+#define PAE_SUPPORT_AUTHENTICATOR 0x01
+#define PAE_SUPPORT_SUPPLICANT 0x02
+///@}
+
+///
+/// EFI_EAPOL_PORT_INFO
+///
+typedef struct _EFI_EAPOL_PORT_INFO {
+ ///
+ /// The identification number assigned to the Port by the System in
+ /// which the Port resides.
+ ///
+ EFI_PORT_HANDLE PortNumber;
+ ///
+ /// The protocol version number of the EAPOL implementation
+ /// supported by the Port.
+ ///
+ UINT8 ProtocolVersion;
+ ///
+ /// The capabilities of the PAE associated with the Port. This field
+ /// indicates whether Authenticator functionality, Supplicant
+ /// functionality, both, or neither, is supported by the Port's PAE.
+ ///
+ UINT8 PaeCapabilities;
+} EFI_EAPOL_PORT_INFO;
+
+///
+/// Supplicant PAE state machine (IEEE Std 802.1X Section 8.5.10)
+///
+typedef enum _EFI_EAPOL_SUPPLICANT_PAE_STATE {
+ Logoff,
+ Disconnected,
+ Connecting,
+ Acquired,
+ Authenticating,
+ Held,
+ Authenticated,
+ MaxSupplicantPaeState
+} EFI_EAPOL_SUPPLICANT_PAE_STATE;
+
+///
+/// Definitions for ValidFieldMask
+///
+///@{
+#define AUTH_PERIOD_FIELD_VALID 0x01
+#define HELD_PERIOD_FIELD_VALID 0x02
+#define START_PERIOD_FIELD_VALID 0x04
+#define MAX_START_FIELD_VALID 0x08
+///@}
+
+///
+/// EFI_EAPOL_SUPPLICANT_PAE_CONFIGURATION
+///
+typedef struct _EFI_EAPOL_SUPPLICANT_PAE_CONFIGURATION {
+ ///
+ /// Indicates which of the following fields are valid.
+ ///
+ UINT8 ValidFieldMask;
+ ///
+ /// The initial value for the authWhile timer. Its default value is 30s.
+ ///
+ UINTN AuthPeriod;
+ ///
+ /// The initial value for the heldWhile timer. Its default value is 60s.
+ ///
+ UINTN HeldPeriod;
+ ///
+ /// The initial value for the startWhen timer. Its default value is 30s.
+ ///
+ UINTN StartPeriod;
+ ///
+ /// The maximum number of successive EAPOL-Start messages will
+ /// be sent before the Supplicant assumes that there is no
+ /// Authenticator present. Its default value is 3.
+ ///
+ UINTN MaxStart;
+} EFI_EAPOL_SUPPLICANT_PAE_CONFIGURATION;
+
+///
+/// Supplicant Statistics (IEEE Std 802.1X Section 9.5.2)
+///
+typedef struct _EFI_EAPOL_SUPPLICANT_PAE_STATISTICS {
+ ///
+ /// The number of EAPOL frames of any type that have been received by this Supplican.
+ ///
+ UINTN EapolFramesReceived;
+ ///
+ /// The number of EAPOL frames of any type that have been transmitted by this Supplicant.
+ ///
+ UINTN EapolFramesTransmitted;
+ ///
+ /// The number of EAPOL Start frames that have been transmitted by this Supplicant.
+ ///
+ UINTN EapolStartFramesTransmitted;
+ ///
+ /// The number of EAPOL Logoff frames that have been transmitted by this Supplicant.
+ ///
+ UINTN EapolLogoffFramesTransmitted;
+ ///
+ /// The number of EAP Resp/Id frames that have been transmitted by this Supplicant.
+ ///
+ UINTN EapRespIdFramesTransmitted;
+ ///
+ /// The number of valid EAP Response frames (other than Resp/Id frames) that have been
+ /// transmitted by this Supplicant.
+ ///
+ UINTN EapResponseFramesTransmitted;
+ ///
+ /// The number of EAP Req/Id frames that have been received by this Supplicant.
+ ///
+ UINTN EapReqIdFramesReceived;
+ ///
+ /// The number of EAP Request frames (other than Rq/Id frames) that have been received
+ /// by this Supplicant.
+ ///
+ UINTN EapRequestFramesReceived;
+ ///
+ /// The number of EAPOL frames that have been received by this Supplicant in which the
+ /// frame type is not recognized.
+ ///
+ UINTN InvalidEapolFramesReceived;
+ ///
+ /// The number of EAPOL frames that have been received by this Supplicant in which the
+ /// Packet Body Length field (7.5.5) is invalid.
+ ///
+ UINTN EapLengthErrorFramesReceived;
+ ///
+ /// The protocol version number carried in the most recently received EAPOL frame.
+ ///
+ UINTN LastEapolFrameVersion;
+ ///
+ /// The source MAC address carried in the most recently received EAPOL frame.
+ ///
+ UINTN LastEapolFrameSource;
+} EFI_EAPOL_SUPPLICANT_PAE_STATISTICS;
+
+/**
+ Read the system configuration information associated with the Port.
+
+ The GetSystemConfiguration() function reads the system configuration
+ information associated with the Port, including the value of the
+ SystemAuthControl parameter of the System is returned in SystemAuthControl
+ and the Port's information is returned in the buffer pointed to by PortInfo.
+ The Port's information is optional.
+ If PortInfo is NULL, then reading the Port's information is ignored.
+
+ If SystemAuthControl is NULL, then EFI_INVALID_PARAMETER is returned.
+
+ @param[in] This A pointer to the EFI_EAP_MANAGEMENT_PROTOCOL
+ instance that indicates the calling context.
+ @param[out] SystemAuthControl Returns the value of the SystemAuthControl
+ parameter of the System.
+ TRUE means Enabled. FALSE means Disabled.
+ @param[out] PortInfo Returns EFI_EAPOL_PORT_INFO structure to describe
+ the Port's information. This parameter can be NULL
+ to ignore reading the Port's information.
+
+ @retval EFI_SUCCESS The system configuration information of the
+ Port is read successfully.
+ @retval EFI_INVALID_PARAMETER SystemAuthControl is NULL.
+
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_EAP_GET_SYSTEM_CONFIGURATION)(
+ IN EFI_EAP_MANAGEMENT_PROTOCOL *This,
+ OUT BOOLEAN *SystemAuthControl,
+ OUT EFI_EAPOL_PORT_INFO *PortInfo OPTIONAL
+ );
+
+/**
+ Set the system configuration information associated with the Port.
+
+ The SetSystemConfiguration() function sets the value of the SystemAuthControl
+ parameter of the System to SystemAuthControl.
+
+ @param[in] This A pointer to the EFI_EAP_MANAGEMENT_PROTOCOL
+ instance that indicates the calling context.
+ @param[in] SystemAuthControl The desired value of the SystemAuthControl
+ parameter of the System.
+ TRUE means Enabled. FALSE means Disabled.
+
+ @retval EFI_SUCCESS The system configuration information of the
+ Port is set successfully.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_EAP_SET_SYSTEM_CONFIGURATION)(
+ IN EFI_EAP_MANAGEMENT_PROTOCOL *This,
+ IN BOOLEAN SystemAuthControl
+ );
+
+/**
+ Cause the EAPOL state machines for the Port to be initialized.
+
+ The InitializePort() function causes the EAPOL state machines for the Port.
+
+ @param[in] This A pointer to the EFI_EAP_MANAGEMENT_PROTOCOL
+ instance that indicates the calling context.
+
+ @retval EFI_SUCCESS The Port is initialized successfully.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_EAP_INITIALIZE_PORT)(
+ IN EFI_EAP_MANAGEMENT_PROTOCOL *This
+ );
+
+/**
+ Notify the EAPOL state machines for the Port that the user of the System has
+ logged on.
+
+ The UserLogon() function notifies the EAPOL state machines for the Port.
+
+ @param[in] This A pointer to the EFI_EAP_MANAGEMENT_PROTOCOL
+ instance that indicates the calling context.
+
+ @retval EFI_SUCCESS The Port is notified successfully.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_EAP_USER_LOGON)(
+ IN EFI_EAP_MANAGEMENT_PROTOCOL *This
+ );
+
+/**
+ Notify the EAPOL state machines for the Port that the user of the System has
+ logged off.
+
+ The UserLogoff() function notifies the EAPOL state machines for the Port.
+
+ @param[in] This A pointer to the EFI_EAP_MANAGEMENT_PROTOCOL
+ instance that indicates the calling context.
+
+ @retval EFI_SUCCESS The Port is notified successfully.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_EAP_USER_LOGOFF)(
+ IN EFI_EAP_MANAGEMENT_PROTOCOL *This
+ );
+
+/**
+ Read the status of the Supplicant PAE state machine for the Port, including the
+ current state and the configuration of the operational parameters.
+
+ The GetSupplicantStatus() function reads the status of the Supplicant PAE state
+ machine for the Port, including the current state CurrentState and the configuration
+ of the operational parameters Configuration. The configuration of the operational
+ parameters is optional. If Configuration is NULL, then reading the configuration
+ is ignored. The operational parameters in Configuration to be read can also be
+ specified by Configuration.ValidFieldMask.
+
+ If CurrentState is NULL, then EFI_INVALID_PARAMETER is returned.
+
+ @param[in] This A pointer to the EFI_EAP_MANAGEMENT_PROTOCOL
+ instance that indicates the calling context.
+ @param[out] CurrentState Returns the current state of the Supplicant PAE
+ state machine for the Port.
+ @param[in, out] Configuration Returns the configuration of the operational
+ parameters of the Supplicant PAE state machine
+ for the Port as required. This parameter can be
+ NULL to ignore reading the configuration.
+ On input, Configuration.ValidFieldMask specifies the
+ operational parameters to be read.
+ On output, Configuration returns the configuration
+ of the required operational parameters.
+
+ @retval EFI_SUCCESS The configuration of the operational parameter
+ of the Supplicant PAE state machine for the Port
+ is set successfully.
+ @retval EFI_INVALID_PARAMETER CurrentState is NULL.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_EAP_GET_SUPPLICANT_STATUS)(
+ IN EFI_EAP_MANAGEMENT_PROTOCOL *This,
+ OUT EFI_EAPOL_SUPPLICANT_PAE_STATE *CurrentState,
+ IN OUT EFI_EAPOL_SUPPLICANT_PAE_CONFIGURATION *Configuration OPTIONAL
+ );
+
+/**
+ Set the configuration of the operational parameter of the Supplicant PAE
+ state machine for the Port.
+
+ The SetSupplicantConfiguration() function sets the configuration of the
+ operational Parameter of the Supplicant PAE state machine for the Port to
+ Configuration. The operational parameters in Configuration to be set can be
+ specified by Configuration.ValidFieldMask.
+
+ If Configuration is NULL, then EFI_INVALID_PARAMETER is returned.
+
+ @param[in] This A pointer to the EFI_EAP_MANAGEMENT_PROTOCOL
+ instance that indicates the calling context.
+ @param[in] Configuration The desired configuration of the operational
+ parameters of the Supplicant PAE state machine
+ for the Port as required.
+
+ @retval EFI_SUCCESS The configuration of the operational parameter
+ of the Supplicant PAE state machine for the Port
+ is set successfully.
+ @retval EFI_INVALID_PARAMETER Configuration is NULL.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_EAP_SET_SUPPLICANT_CONFIGURATION)(
+ IN EFI_EAP_MANAGEMENT_PROTOCOL *This,
+ IN EFI_EAPOL_SUPPLICANT_PAE_CONFIGURATION *Configuration
+ );
+
+/**
+ Read the statistical information regarding the operation of the Supplicant
+ associated with the Port.
+
+ The GetSupplicantStatistics() function reads the statistical information
+ Statistics regarding the operation of the Supplicant associated with the Port.
+
+ If Statistics is NULL, then EFI_INVALID_PARAMETER is returned.
+
+ @param[in] This A pointer to the EFI_EAP_MANAGEMENT_PROTOCOL
+ instance that indicates the calling context.
+ @param[out] Statistics Returns the statistical information regarding the
+ operation of the Supplicant for the Port.
+
+ @retval EFI_SUCCESS The statistical information regarding the operation
+ of the Supplicant for the Port is read successfully.
+ @retval EFI_INVALID_PARAMETER Statistics is NULL.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_EAP_GET_SUPPLICANT_STATISTICS)(
+ IN EFI_EAP_MANAGEMENT_PROTOCOL *This,
+ OUT EFI_EAPOL_SUPPLICANT_PAE_STATISTICS *Statistics
+ );
+
+///
+/// EFI_EAP_MANAGEMENT_PROTOCOL
+/// is used to control, configure and monitor EAPOL state machine on
+/// a Port. EAPOL state machine is built on a per-Port basis. Herein,
+/// a Port means a NIC. For the details of EAPOL, please refer to
+/// IEEE 802.1x specification.
+///
+struct _EFI_EAP_MANAGEMENT_PROTOCOL {
+ EFI_EAP_GET_SYSTEM_CONFIGURATION GetSystemConfiguration;
+ EFI_EAP_SET_SYSTEM_CONFIGURATION SetSystemConfiguration;
+ EFI_EAP_INITIALIZE_PORT InitializePort;
+ EFI_EAP_USER_LOGON UserLogon;
+ EFI_EAP_USER_LOGOFF UserLogoff;
+ EFI_EAP_GET_SUPPLICANT_STATUS GetSupplicantStatus;
+ EFI_EAP_SET_SUPPLICANT_CONFIGURATION SetSupplicantConfiguration;
+ EFI_EAP_GET_SUPPLICANT_STATISTICS GetSupplicantStatistics;
+};
+
+extern EFI_GUID gEfiEapManagementProtocolGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/EapManagement2.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/EapManagement2.h
new file mode 100644
index 0000000000..f9c51a61a8
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/EapManagement2.h
@@ -0,0 +1,81 @@
+/** @file
+ This file defines the EFI EAP Management2 protocol.
+
+ Copyright (c) 2015, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Revision Reference:
+ This Protocol is introduced in UEFI Specification 2.5
+
+**/
+
+#ifndef __EFI_EAP_MANAGEMENT2_PROTOCOL_H__
+#define __EFI_EAP_MANAGEMENT2_PROTOCOL_H__
+
+#include
+
+///
+/// This EFI EAP Management2 protocol provides the ability to configure and control EAPOL
+/// state machine, and retrieve the information, status and the statistics information of
+/// EAPOL state machine.
+///
+#define EFI_EAP_MANAGEMENT2_PROTOCOL_GUID \
+ { \
+ 0x5e93c847, 0x456d, 0x40b3, {0xa6, 0xb4, 0x78, 0xb0, 0xc9, 0xcf, 0x7f, 0x20 } \
+ }
+
+typedef struct _EFI_EAP_MANAGEMENT2_PROTOCOL EFI_EAP_MANAGEMENT2_PROTOCOL;
+
+/**
+ Return key generated through EAP process.
+
+ The GetKey() function return the key generated through EAP process, so that the 802.11
+ MAC layer driver can use MSK to derive more keys, e.g. PMK (Pairwise Master Key).
+
+ @param[in] This Pointer to the EFI_EAP_MANAGEMENT2_PROTOCOL instance.
+ @param[in, out] Msk Pointer to MSK (Master Session Key) buffer.
+ @param[in, out] MskSize MSK buffer size.
+ @param[in, out] Emsk Pointer to EMSK (Extended Master Session Key) buffer.
+ @param[in, out] EmskSize EMSK buffer size.
+
+ @retval EFI_SUCCESS The operation completed successfully.
+ @retval EFI_INVALID_PARAMETER One or more of the following conditions is TRUE:
+ Msk is NULL.
+ MskSize is NULL.
+ Emsk is NULL.
+ EmskSize is NULL.
+ @retval EFI_NOT_READY MSK and EMSK are not generated in current session yet.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_EAP_GET_KEY)(
+ IN EFI_EAP_MANAGEMENT2_PROTOCOL *This,
+ IN OUT UINT8 *Msk,
+ IN OUT UINTN *MskSize,
+ IN OUT UINT8 *Emsk,
+ IN OUT UINT8 *EmskSize
+ );
+
+///
+/// The EFI_EAP_MANAGEMENT2_PROTOCOL
+/// is used to control, configure and monitor EAPOL state machine on a Port, and return
+/// information of the Port. EAPOL state machine is built on a per-Port basis. Herein, a
+/// Port means a NIC. For the details of EAPOL, please refer to IEEE 802.1x
+/// specification.
+///
+struct _EFI_EAP_MANAGEMENT2_PROTOCOL {
+ EFI_EAP_GET_SYSTEM_CONFIGURATION GetSystemConfiguration;
+ EFI_EAP_SET_SYSTEM_CONFIGURATION SetSystemConfiguration;
+ EFI_EAP_INITIALIZE_PORT InitializePort;
+ EFI_EAP_USER_LOGON UserLogon;
+ EFI_EAP_USER_LOGOFF UserLogoff;
+ EFI_EAP_GET_SUPPLICANT_STATUS GetSupplicantStatus;
+ EFI_EAP_SET_SUPPLICANT_CONFIGURATION SetSupplicantConfiguration;
+ EFI_EAP_GET_SUPPLICANT_STATISTICS GetSupplicantStatistics;
+ EFI_EAP_GET_KEY GetKey;
+};
+
+extern EFI_GUID gEfiEapManagement2ProtocolGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/Ebc.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/Ebc.h
new file mode 100644
index 0000000000..d21bcfcba9
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/Ebc.h
@@ -0,0 +1,308 @@
+/** @file
+ Describes the protocol interface to the EBC interpreter.
+
+ Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __EFI_EBC_PROTOCOL_H__
+#define __EFI_EBC_PROTOCOL_H__
+
+#define EFI_EBC_INTERPRETER_PROTOCOL_GUID \
+ { \
+ 0x13AC6DD1, 0x73D0, 0x11D4, {0xB0, 0x6B, 0x00, 0xAA, 0x00, 0xBD, 0x6D, 0xE7 } \
+ }
+
+//
+// Define OPCODES
+//
+#define OPCODE_BREAK 0x00
+#define OPCODE_JMP 0x01
+#define OPCODE_JMP8 0x02
+#define OPCODE_CALL 0x03
+#define OPCODE_RET 0x04
+#define OPCODE_CMPEQ 0x05
+#define OPCODE_CMPLTE 0x06
+#define OPCODE_CMPGTE 0x07
+#define OPCODE_CMPULTE 0x08
+#define OPCODE_CMPUGTE 0x09
+#define OPCODE_NOT 0x0A
+#define OPCODE_NEG 0x0B
+#define OPCODE_ADD 0x0C
+#define OPCODE_SUB 0x0D
+#define OPCODE_MUL 0x0E
+#define OPCODE_MULU 0x0F
+#define OPCODE_DIV 0x10
+#define OPCODE_DIVU 0x11
+#define OPCODE_MOD 0x12
+#define OPCODE_MODU 0x13
+#define OPCODE_AND 0x14
+#define OPCODE_OR 0x15
+#define OPCODE_XOR 0x16
+#define OPCODE_SHL 0x17
+#define OPCODE_SHR 0x18
+#define OPCODE_ASHR 0x19
+#define OPCODE_EXTNDB 0x1A
+#define OPCODE_EXTNDW 0x1B
+#define OPCODE_EXTNDD 0x1C
+#define OPCODE_MOVBW 0x1D
+#define OPCODE_MOVWW 0x1E
+#define OPCODE_MOVDW 0x1F
+#define OPCODE_MOVQW 0x20
+#define OPCODE_MOVBD 0x21
+#define OPCODE_MOVWD 0x22
+#define OPCODE_MOVDD 0x23
+#define OPCODE_MOVQD 0x24
+#define OPCODE_MOVSNW 0x25 // Move signed natural with word index
+#define OPCODE_MOVSND 0x26 // Move signed natural with dword index
+//
+// #define OPCODE_27 0x27
+//
+#define OPCODE_MOVQQ 0x28 // Does this go away?
+#define OPCODE_LOADSP 0x29
+#define OPCODE_STORESP 0x2A
+#define OPCODE_PUSH 0x2B
+#define OPCODE_POP 0x2C
+#define OPCODE_CMPIEQ 0x2D
+#define OPCODE_CMPILTE 0x2E
+#define OPCODE_CMPIGTE 0x2F
+#define OPCODE_CMPIULTE 0x30
+#define OPCODE_CMPIUGTE 0x31
+#define OPCODE_MOVNW 0x32
+#define OPCODE_MOVND 0x33
+//
+// #define OPCODE_34 0x34
+//
+#define OPCODE_PUSHN 0x35
+#define OPCODE_POPN 0x36
+#define OPCODE_MOVI 0x37
+#define OPCODE_MOVIN 0x38
+#define OPCODE_MOVREL 0x39
+
+//
+// Bit masks for opcode encodings
+//
+#define OPCODE_M_OPCODE 0x3F // bits of interest for first level decode
+#define OPCODE_M_IMMDATA 0x80
+#define OPCODE_M_IMMDATA64 0x40
+#define OPCODE_M_64BIT 0x40 // for CMP
+#define OPCODE_M_RELADDR 0x10 // for CALL instruction
+#define OPCODE_M_CMPI32_DATA 0x80 // for CMPI
+#define OPCODE_M_CMPI64 0x40 // for CMPI 32 or 64 bit comparison
+#define OPERAND_M_MOVIN_N 0x80
+#define OPERAND_M_CMPI_INDEX 0x10
+
+//
+// Masks for instructions that encode presence of indexes for operand1 and/or
+// operand2.
+//
+#define OPCODE_M_IMMED_OP1 0x80
+#define OPCODE_M_IMMED_OP2 0x40
+
+//
+// Bit masks for operand encodings
+//
+#define OPERAND_M_INDIRECT1 0x08
+#define OPERAND_M_INDIRECT2 0x80
+#define OPERAND_M_OP1 0x07
+#define OPERAND_M_OP2 0x70
+
+//
+// Masks for data manipulation instructions
+//
+#define DATAMANIP_M_64 0x40 // 64-bit width operation
+#define DATAMANIP_M_IMMDATA 0x80
+
+//
+// For MOV instructions, need a mask for the opcode when immediate
+// data applies to R2.
+//
+#define OPCODE_M_IMMED_OP2 0x40
+
+//
+// The MOVI/MOVIn instructions use bit 6 of operands byte to indicate
+// if an index is present. Then bits 4 and 5 are used to indicate the width
+// of the move.
+//
+#define MOVI_M_IMMDATA 0x40
+#define MOVI_M_DATAWIDTH 0xC0
+#define MOVI_DATAWIDTH16 0x40
+#define MOVI_DATAWIDTH32 0x80
+#define MOVI_DATAWIDTH64 0xC0
+#define MOVI_M_MOVEWIDTH 0x30
+#define MOVI_MOVEWIDTH8 0x00
+#define MOVI_MOVEWIDTH16 0x10
+#define MOVI_MOVEWIDTH32 0x20
+#define MOVI_MOVEWIDTH64 0x30
+
+//
+// Masks for CALL instruction encodings
+//
+#define OPERAND_M_RELATIVE_ADDR 0x10
+#define OPERAND_M_NATIVE_CALL 0x20
+
+//
+// Masks for decoding push/pop instructions
+//
+#define PUSHPOP_M_IMMDATA 0x80 // opcode bit indicating immediate data
+#define PUSHPOP_M_64 0x40 // opcode bit indicating 64-bit operation
+//
+// Mask for operand of JMP instruction
+//
+#define JMP_M_RELATIVE 0x10
+#define JMP_M_CONDITIONAL 0x80
+#define JMP_M_CS 0x40
+
+//
+// Macros to determine if a given operand is indirect
+//
+#define OPERAND1_INDIRECT(op) ((op) & OPERAND_M_INDIRECT1)
+#define OPERAND2_INDIRECT(op) ((op) & OPERAND_M_INDIRECT2)
+
+//
+// Macros to extract the operands from second byte of instructions
+//
+#define OPERAND1_REGNUM(op) ((op) & OPERAND_M_OP1)
+#define OPERAND2_REGNUM(op) (((op) & OPERAND_M_OP2) >> 4)
+
+#define OPERAND1_CHAR(op) ('0' + OPERAND1_REGNUM (op))
+#define OPERAND2_CHAR(op) ('0' + OPERAND2_REGNUM (op))
+
+//
+// Condition masks usually for byte 1 encodings of code
+//
+#define CONDITION_M_CONDITIONAL 0x80
+#define CONDITION_M_CS 0x40
+
+///
+/// Protocol Guid Name defined in spec.
+///
+#define EFI_EBC_PROTOCOL_GUID EFI_EBC_INTERPRETER_PROTOCOL_GUID
+
+///
+/// Define for forward reference.
+///
+typedef struct _EFI_EBC_PROTOCOL EFI_EBC_PROTOCOL;
+
+/**
+ Creates a thunk for an EBC entry point, returning the address of the thunk.
+
+ A PE32+ EBC image, like any other PE32+ image, contains an optional header that specifies the
+ entry point for image execution. However, for EBC images, this is the entry point of EBC
+ instructions, so is not directly executable by the native processor. Therefore, when an EBC image is
+ loaded, the loader must call this service to get a pointer to native code (thunk) that can be executed,
+ which will invoke the interpreter to begin execution at the original EBC entry point.
+
+ @param This A pointer to the EFI_EBC_PROTOCOL instance.
+ @param ImageHandle Handle of image for which the thunk is being created.
+ @param EbcEntryPoint Address of the actual EBC entry point or protocol service the thunk should call.
+ @param Thunk Returned pointer to a thunk created.
+
+ @retval EFI_SUCCESS The function completed successfully.
+ @retval EFI_INVALID_PARAMETER Image entry point is not 2-byte aligned.
+ @retval EFI_OUT_OF_RESOURCES Memory could not be allocated for the thunk.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_EBC_CREATE_THUNK)(
+ IN EFI_EBC_PROTOCOL *This,
+ IN EFI_HANDLE ImageHandle,
+ IN VOID *EbcEntryPoint,
+ OUT VOID **Thunk
+ );
+
+/**
+ Called prior to unloading an EBC image from memory.
+
+ This function is called after an EBC image has exited, but before the image is actually unloaded. It
+ is intended to provide the interpreter with the opportunity to perform any cleanup that may be
+ necessary as a result of loading and executing the image.
+
+ @param This A pointer to the EFI_EBC_PROTOCOL instance.
+ @param ImageHandle Image handle of the EBC image that is being unloaded from memory.
+
+ @retval EFI_SUCCESS The function completed successfully.
+ @retval EFI_INVALID_PARAMETER Image handle is not recognized as belonging
+ to an EBC image that has been executed.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_EBC_UNLOAD_IMAGE)(
+ IN EFI_EBC_PROTOCOL *This,
+ IN EFI_HANDLE ImageHandle
+ );
+
+/**
+ This is the prototype for the Flush callback routine. A pointer to a routine
+ of this type is passed to the EBC EFI_EBC_REGISTER_ICACHE_FLUSH protocol service.
+
+ @param Start The beginning physical address to flush from the processor's instruction cache.
+ @param Length The number of bytes to flush from the processor's instruction cache.
+
+ @retval EFI_SUCCESS The function completed successfully.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EBC_ICACHE_FLUSH)(
+ IN EFI_PHYSICAL_ADDRESS Start,
+ IN UINT64 Length
+ );
+
+/**
+ Registers a callback function that the EBC interpreter calls to flush
+ the processor instruction cache following creation of thunks.
+
+ @param This A pointer to the EFI_EBC_PROTOCOL instance.
+ @param Flush Pointer to a function of type EBC_ICACH_FLUSH.
+
+ @retval EFI_SUCCESS The function completed successfully.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_EBC_REGISTER_ICACHE_FLUSH)(
+ IN EFI_EBC_PROTOCOL *This,
+ IN EBC_ICACHE_FLUSH Flush
+ );
+
+/**
+ Called to get the version of the interpreter.
+
+ This function is called to get the version of the loaded EBC interpreter. The value and format of the
+ returned version is identical to that returned by the EBC BREAK 1 instruction.
+
+ @param This A pointer to the EFI_EBC_PROTOCOL instance.
+ @param Version Pointer to where to store the returned version of the interpreter.
+
+ @retval EFI_SUCCESS The function completed successfully.
+ @retval EFI_INVALID_PARAMETER Version pointer is NULL.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_EBC_GET_VERSION)(
+ IN EFI_EBC_PROTOCOL *This,
+ IN OUT UINT64 *Version
+ );
+
+///
+/// The EFI EBC protocol provides services to load and execute EBC images, which will typically be
+/// loaded into option ROMs. The image loader will load the EBC image, perform standard relocations,
+/// and invoke the CreateThunk() service to create a thunk for the EBC image's entry point. The
+/// image can then be run using the standard EFI start image services.
+///
+struct _EFI_EBC_PROTOCOL {
+ EFI_EBC_CREATE_THUNK CreateThunk;
+ EFI_EBC_UNLOAD_IMAGE UnloadImage;
+ EFI_EBC_REGISTER_ICACHE_FLUSH RegisterICacheFlush;
+ EFI_EBC_GET_VERSION GetVersion;
+};
+
+//
+// Extern the global EBC protocol GUID
+//
+extern EFI_GUID gEfiEbcProtocolGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/EdidActive.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/EdidActive.h
new file mode 100644
index 0000000000..b96f86819f
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/EdidActive.h
@@ -0,0 +1,46 @@
+/** @file
+ EDID Active Protocol from the UEFI 2.0 specification.
+
+ Placed on the video output device child handle that is actively displaying output.
+
+ Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __EDID_ACTIVE_H__
+#define __EDID_ACTIVE_H__
+
+#define EFI_EDID_ACTIVE_PROTOCOL_GUID \
+ { \
+ 0xbd8c1056, 0x9f36, 0x44ec, {0x92, 0xa8, 0xa6, 0x33, 0x7f, 0x81, 0x79, 0x86 } \
+ }
+
+///
+/// This protocol contains the EDID information for an active video output device. This is either the
+/// EDID information retrieved from the EFI_EDID_OVERRIDE_PROTOCOL if an override is
+/// available, or an identical copy of the EDID information from the
+/// EFI_EDID_DISCOVERED_PROTOCOL if no overrides are available.
+///
+typedef struct {
+ ///
+ /// The size, in bytes, of the Edid buffer. 0 if no EDID information
+ /// is available from the video output device. Otherwise, it must be a
+ /// minimum of 128 bytes.
+ ///
+ UINT32 SizeOfEdid;
+
+ ///
+ /// A pointer to a read-only array of bytes that contains the EDID
+ /// information for an active video output device. This pointer is
+ /// NULL if no EDID information is available for the video output
+ /// device. The minimum size of a valid Edid buffer is 128 bytes.
+ /// EDID information is defined in the E-EDID EEPROM
+ /// specification published by VESA (www.vesa.org).
+ ///
+ UINT8 *Edid;
+} EFI_EDID_ACTIVE_PROTOCOL;
+
+extern EFI_GUID gEfiEdidActiveProtocolGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/EdidDiscovered.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/EdidDiscovered.h
new file mode 100644
index 0000000000..9b38c82310
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/EdidDiscovered.h
@@ -0,0 +1,44 @@
+/** @file
+ EDID Discovered Protocol from the UEFI 2.0 specification.
+
+ This protocol is placed on the video output device child handle. It represents
+ the EDID information being used for the output device represented by the child handle.
+
+ Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __EDID_DISCOVERED_H__
+#define __EDID_DISCOVERED_H__
+
+#define EFI_EDID_DISCOVERED_PROTOCOL_GUID \
+ { \
+ 0x1c0c34f6, 0xd380, 0x41fa, {0xa0, 0x49, 0x8a, 0xd0, 0x6c, 0x1a, 0x66, 0xaa } \
+ }
+
+///
+/// This protocol contains the EDID information retrieved from a video output device.
+///
+typedef struct {
+ ///
+ /// The size, in bytes, of the Edid buffer. 0 if no EDID information
+ /// is available from the video output device. Otherwise, it must be a
+ /// minimum of 128 bytes.
+ ///
+ UINT32 SizeOfEdid;
+
+ ///
+ /// A pointer to a read-only array of bytes that contains the EDID
+ /// information for an active video output device. This pointer is
+ /// NULL if no EDID information is available for the video output
+ /// device. The minimum size of a valid Edid buffer is 128 bytes.
+ /// EDID information is defined in the E-EDID EEPROM
+ /// specification published by VESA (www.vesa.org).
+ ///
+ UINT8 *Edid;
+} EFI_EDID_DISCOVERED_PROTOCOL;
+
+extern EFI_GUID gEfiEdidDiscoveredProtocolGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/EdidOverride.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/EdidOverride.h
new file mode 100644
index 0000000000..c8ded12121
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/EdidOverride.h
@@ -0,0 +1,61 @@
+/** @file
+ EDID Override Protocol from the UEFI 2.0 specification.
+
+ Allow platform to provide EDID information to the producer of the Graphics Output
+ protocol.
+
+ Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __EDID_OVERRIDE_H__
+#define __EDID_OVERRIDE_H__
+
+#define EFI_EDID_OVERRIDE_PROTOCOL_GUID \
+ { \
+ 0x48ecb431, 0xfb72, 0x45c0, {0xa9, 0x22, 0xf4, 0x58, 0xfe, 0x4, 0xb, 0xd5 } \
+ }
+
+typedef struct _EFI_EDID_OVERRIDE_PROTOCOL EFI_EDID_OVERRIDE_PROTOCOL;
+
+#define EFI_EDID_OVERRIDE_DONT_OVERRIDE 0x01
+#define EFI_EDID_OVERRIDE_ENABLE_HOT_PLUG 0x02
+
+/**
+ Returns policy information and potentially a replacement EDID for the specified video output device.
+
+ @param This The EFI_EDID_OVERRIDE_PROTOCOL instance.
+ @param ChildHandle A child handle produced by the Graphics Output EFI
+ driver that represents a video output device.
+ @param Attributes The attributes associated with ChildHandle video output device.
+ @param EdidSize A pointer to the size, in bytes, of the Edid buffer.
+ @param Edid A pointer to callee allocated buffer that contains the EDID that
+ should be used for ChildHandle. A value of NULL
+ represents no EDID override for ChildHandle.
+
+ @retval EFI_SUCCESS Valid overrides returned for ChildHandle.
+ @retval EFI_UNSUPPORTED ChildHandle has no overrides.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_EDID_OVERRIDE_PROTOCOL_GET_EDID)(
+ IN EFI_EDID_OVERRIDE_PROTOCOL *This,
+ IN EFI_HANDLE *ChildHandle,
+ OUT UINT32 *Attributes,
+ OUT UINTN *EdidSize,
+ OUT UINT8 **Edid
+ );
+
+///
+/// This protocol is produced by the platform to allow the platform to provide
+/// EDID information to the producer of the Graphics Output protocol.
+///
+struct _EFI_EDID_OVERRIDE_PROTOCOL {
+ EFI_EDID_OVERRIDE_PROTOCOL_GET_EDID GetEdid;
+};
+
+extern EFI_GUID gEfiEdidOverrideProtocolGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/EraseBlock.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/EraseBlock.h
new file mode 100644
index 0000000000..226e407665
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/EraseBlock.h
@@ -0,0 +1,99 @@
+/** @file
+ This file defines the EFI Erase Block Protocol.
+
+ Copyright (c) 2016, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Revision Reference:
+ This Protocol is introduced in UEFI Specification 2.6
+
+**/
+
+#ifndef __EFI_ERASE_BLOCK_PROTOCOL_H__
+#define __EFI_ERASE_BLOCK_PROTOCOL_H__
+
+#define EFI_ERASE_BLOCK_PROTOCOL_GUID \
+ { \
+ 0x95a9a93e, 0xa86e, 0x4926, { 0xaa, 0xef, 0x99, 0x18, 0xe7, 0x72, 0xd9, 0x87 } \
+ }
+
+typedef struct _EFI_ERASE_BLOCK_PROTOCOL EFI_ERASE_BLOCK_PROTOCOL;
+
+#define EFI_ERASE_BLOCK_PROTOCOL_REVISION ((2<<16) | (60))
+
+///
+/// EFI_ERASE_BLOCK_TOKEN
+///
+typedef struct {
+ //
+ // If Event is NULL, then blocking I/O is performed. If Event is not NULL and
+ // non-blocking I/O is supported, then non-blocking I/O is performed, and
+ // Event will be signaled when the erase request is completed.
+ //
+ EFI_EVENT Event;
+ //
+ // Defines whether the signaled event encountered an error.
+ //
+ EFI_STATUS TransactionStatus;
+} EFI_ERASE_BLOCK_TOKEN;
+
+/**
+ Erase a specified number of device blocks.
+
+ @param[in] This Indicates a pointer to the calling context.
+ @param[in] MediaId The media ID that the erase request is for.
+ @param[in] LBA The starting logical block address to be
+ erased. The caller is responsible for erasing
+ only legitimate locations.
+ @param[in, out] Token A pointer to the token associated with the
+ transaction.
+ @param[in] Size The size in bytes to be erased. This must be
+ a multiple of the physical block size of the
+ device.
+
+ @retval EFI_SUCCESS The erase request was queued if Event is not
+ NULL. The data was erased correctly to the
+ device if the Event is NULL.to the device.
+ @retval EFI_WRITE_PROTECTED The device cannot be erased due to write
+ protection.
+ @retval EFI_DEVICE_ERROR The device reported an error while attempting
+ to perform the erase operation.
+ @retval EFI_INVALID_PARAMETER The erase request contains LBAs that are not
+ valid.
+ @retval EFI_NO_MEDIA There is no media in the device.
+ @retval EFI_MEDIA_CHANGED The MediaId is not for the current media.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_BLOCK_ERASE)(
+ IN EFI_ERASE_BLOCK_PROTOCOL *This,
+ IN UINT32 MediaId,
+ IN EFI_LBA LBA,
+ IN OUT EFI_ERASE_BLOCK_TOKEN *Token,
+ IN UINTN Size
+ );
+
+///
+/// The EFI Erase Block Protocol provides the ability for a device to expose
+/// erase functionality. This optional protocol is installed on the same handle
+/// as the EFI_BLOCK_IO_PROTOCOL or EFI_BLOCK_IO2_PROTOCOL.
+///
+struct _EFI_ERASE_BLOCK_PROTOCOL {
+ //
+ // The revision to which the EFI_ERASE_BLOCK_PROTOCOL adheres. All future
+ // revisions must be backwards compatible. If a future version is not
+ // backwards compatible, it is not the same GUID.
+ //
+ UINT64 Revision;
+ //
+ // Returns the erase length granularity as a number of logical blocks. A
+ // value of 1 means the erase granularity is one logical block.
+ //
+ UINT32 EraseLengthGranularity;
+ EFI_BLOCK_ERASE EraseBlocks;
+};
+
+extern EFI_GUID gEfiEraseBlockProtocolGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/FirmwareManagement.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/FirmwareManagement.h
new file mode 100644
index 0000000000..453cca57ca
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/FirmwareManagement.h
@@ -0,0 +1,558 @@
+/** @file
+ UEFI Firmware Management Protocol definition
+ Firmware Management Protocol provides an abstraction for device to provide firmware
+ management support. The base requirements for managing device firmware images include
+ identifying firmware image revision level and programming the image into the device.
+
+ GetImageInfo() is the only required function. GetImage(), SetImage(),
+ CheckImage(), GetPackageInfo(), and SetPackageInfo() shall return
+ EFI_UNSUPPORTED if not supported by the driver.
+
+ Copyright (c) 2009 - 2020, Intel Corporation. All rights reserved.
+ Copyright (c) 2013 - 2014, Hewlett-Packard Development Company, L.P.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Revision Reference:
+ This Protocol is introduced in UEFI Specification 2.3
+
+**/
+
+#ifndef __EFI_FIRMWARE_MANAGEMENT_PROTOCOL_H__
+#define __EFI_FIRMWARE_MANAGEMENT_PROTOCOL_H__
+
+#define EFI_FIRMWARE_MANAGEMENT_PROTOCOL_GUID \
+ { \
+ 0x86c77a67, 0xb97, 0x4633, {0xa1, 0x87, 0x49, 0x10, 0x4d, 0x6, 0x85, 0xc7 } \
+ }
+
+typedef struct _EFI_FIRMWARE_MANAGEMENT_PROTOCOL EFI_FIRMWARE_MANAGEMENT_PROTOCOL;
+
+///
+/// Dependency Expression Opcode
+///
+#define EFI_FMP_DEP_PUSH_GUID 0x00
+#define EFI_FMP_DEP_PUSH_VERSION 0x01
+#define EFI_FMP_DEP_VERSION_STR 0x02
+#define EFI_FMP_DEP_AND 0x03
+#define EFI_FMP_DEP_OR 0x04
+#define EFI_FMP_DEP_NOT 0x05
+#define EFI_FMP_DEP_TRUE 0x06
+#define EFI_FMP_DEP_FALSE 0x07
+#define EFI_FMP_DEP_EQ 0x08
+#define EFI_FMP_DEP_GT 0x09
+#define EFI_FMP_DEP_GTE 0x0A
+#define EFI_FMP_DEP_LT 0x0B
+#define EFI_FMP_DEP_LTE 0x0C
+#define EFI_FMP_DEP_END 0x0D
+
+///
+/// Image Attribute - Dependency
+///
+typedef struct {
+ UINT8 Dependencies[1];
+} EFI_FIRMWARE_IMAGE_DEP;
+
+///
+/// EFI_FIRMWARE_IMAGE_DESCRIPTOR
+///
+typedef struct {
+ ///
+ /// A unique number identifying the firmware image within the device. The number is
+ /// between 1 and DescriptorCount.
+ ///
+ UINT8 ImageIndex;
+ ///
+ /// A unique GUID identifying the firmware image type.
+ ///
+ EFI_GUID ImageTypeId;
+ ///
+ /// A unique number identifying the firmware image.
+ ///
+ UINT64 ImageId;
+ ///
+ /// A pointer to a null-terminated string representing the firmware image name.
+ ///
+ CHAR16 *ImageIdName;
+ ///
+ /// Identifies the version of the device firmware. The format is vendor specific and new
+ /// version must have a greater value than an old version.
+ ///
+ UINT32 Version;
+ ///
+ /// A pointer to a null-terminated string representing the firmware image version name.
+ ///
+ CHAR16 *VersionName;
+ ///
+ /// Size of the image in bytes. If size=0, then only ImageIndex and ImageTypeId are valid.
+ ///
+ UINTN Size;
+ ///
+ /// Image attributes that are supported by this device. See 'Image Attribute Definitions'
+ /// for possible returned values of this parameter. A value of 1 indicates the attribute is
+ /// supported and the current setting value is indicated in AttributesSetting. A
+ /// value of 0 indicates the attribute is not supported and the current setting value in
+ /// AttributesSetting is meaningless.
+ ///
+ UINT64 AttributesSupported;
+ ///
+ /// Image attributes. See 'Image Attribute Definitions' for possible returned values of
+ /// this parameter.
+ ///
+ UINT64 AttributesSetting;
+ ///
+ /// Image compatibilities. See 'Image Compatibility Definitions' for possible returned
+ /// values of this parameter.
+ ///
+ UINT64 Compatibilities;
+ ///
+ /// Describes the lowest ImageDescriptor version that the device will accept. Only
+ /// present in version 2 or higher.
+ ///
+ UINT32 LowestSupportedImageVersion;
+ ///
+ /// Describes the version that was last attempted to update. If no update attempted the
+ /// value will be 0. If the update attempted was improperly formatted and no version
+ /// number was available then the value will be zero. Only present in version 3 or higher.
+ UINT32 LastAttemptVersion;
+ ///
+ /// Describes the status that was last attempted to update. If no update has been attempted
+ /// the value will be LAST_ATTEMPT_STATUS_SUCCESS. Only present in version 3 or higher.
+ ///
+ UINT32 LastAttemptStatus;
+ ///
+ /// An optional number to identify the unique hardware instance within the system for
+ /// devices that may have multiple instances (Example: a plug in pci network card). This
+ /// number must be unique within the namespace of the ImageTypeId GUID and
+ /// ImageIndex. For FMP instances that have multiple descriptors for a single
+ /// hardware instance, all descriptors must have the same HardwareInstance value.
+ /// This number must be consistent between boots and should be based on some sort of
+ /// hardware identified unique id (serial number, etc) whenever possible. If a hardware
+ /// based number is not available the FMP provider may use some other characteristic
+ /// such as device path, bus/dev/function, slot num, etc for generating the
+ /// HardwareInstance. For implementations that will never have more than one
+ /// instance a zero can be used. A zero means the FMP provider is not able to determine a
+ /// unique hardware instance number or a hardware instance number is not needed. Only
+ /// present in version 3 or higher.
+ ///
+ UINT64 HardwareInstance;
+ EFI_FIRMWARE_IMAGE_DEP *Dependencies;
+} EFI_FIRMWARE_IMAGE_DESCRIPTOR;
+
+//
+// Image Attribute Definitions
+//
+///
+/// The attribute IMAGE_ATTRIBUTE_IMAGE_UPDATABLE indicates this device supports firmware
+/// image update.
+///
+#define IMAGE_ATTRIBUTE_IMAGE_UPDATABLE 0x0000000000000001
+///
+/// The attribute IMAGE_ATTRIBUTE_RESET_REQUIRED indicates a reset of the device is required
+/// for the new firmware image to take effect after a firmware update. The device is the device hosting
+/// the firmware image.
+///
+#define IMAGE_ATTRIBUTE_RESET_REQUIRED 0x0000000000000002
+///
+/// The attribute IMAGE_ATTRIBUTE_AUTHENTICATION_REQUIRED indicates authentication is
+/// required to perform the following image operations: GetImage(), SetImage(), and
+/// CheckImage(). See 'Image Attribute - Authentication'.
+///
+#define IMAGE_ATTRIBUTE_AUTHENTICATION_REQUIRED 0x0000000000000004
+///
+/// The attribute IMAGE_ATTRIBUTE_IN_USE indicates the current state of the firmware image.
+/// This distinguishes firmware images in a device that supports redundant images.
+///
+#define IMAGE_ATTRIBUTE_IN_USE 0x0000000000000008
+///
+/// The attribute IMAGE_ATTRIBUTE_UEFI_IMAGE indicates that this image is an EFI compatible image.
+///
+#define IMAGE_ATTRIBUTE_UEFI_IMAGE 0x0000000000000010
+///
+/// The attribute IMAGE_ATTRIBUTE_DEPENDENCY indicates that there is an EFI_FIRMWARE_IMAGE_DEP
+/// section associated with the image.
+///
+#define IMAGE_ATTRIBUTE_DEPENDENCY 0x0000000000000020
+
+//
+// Image Compatibility Definitions
+//
+///
+/// Values from 0x0000000000000002 thru 0x000000000000FFFF are reserved for future assignments.
+/// Values from 0x0000000000010000 thru 0xFFFFFFFFFFFFFFFF are used by firmware vendor for
+/// compatibility check.
+///
+#define IMAGE_COMPATIBILITY_CHECK_SUPPORTED 0x0000000000000001
+
+///
+/// Descriptor Version exposed by GetImageInfo() function
+///
+#define EFI_FIRMWARE_IMAGE_DESCRIPTOR_VERSION 4
+
+///
+/// Image Attribute - Authentication Required
+///
+typedef struct {
+ ///
+ /// It is included in the signature of AuthInfo. It is used to ensure freshness/no replay.
+ /// It is incremented during each firmware image operation.
+ ///
+ UINT64 MonotonicCount;
+ ///
+ /// Provides the authorization for the firmware image operations. It is a signature across
+ /// the image data and the Monotonic Count value. Caller uses the private key that is
+ /// associated with a public key that has been provisioned via the key exchange.
+ /// Because this is defined as a signature, WIN_CERTIFICATE_UEFI_GUID.CertType must
+ /// be EFI_CERT_TYPE_PKCS7_GUID.
+ ///
+ WIN_CERTIFICATE_UEFI_GUID AuthInfo;
+} EFI_FIRMWARE_IMAGE_AUTHENTICATION;
+
+//
+// ImageUpdatable Definitions
+//
+///
+/// IMAGE_UPDATABLE_VALID indicates SetImage() will accept the new image and update the
+/// device with the new image. The version of the new image could be higher or lower than
+/// the current image. SetImage VendorCode is optional but can be used for vendor
+/// specific action.
+///
+#define IMAGE_UPDATABLE_VALID 0x0000000000000001
+///
+/// IMAGE_UPDATABLE_INVALID indicates SetImage() will reject the new image. No additional
+/// information is provided for the rejection.
+///
+#define IMAGE_UPDATABLE_INVALID 0x0000000000000002
+///
+/// IMAGE_UPDATABLE_INVALID_TYPE indicates SetImage() will reject the new image. The
+/// rejection is due to the new image is not a firmware image recognized for this device.
+///
+#define IMAGE_UPDATABLE_INVALID_TYPE 0x0000000000000004
+///
+/// IMAGE_UPDATABLE_INVALID_OLD indicates SetImage() will reject the new image. The
+/// rejection is due to the new image version is older than the current firmware image
+/// version in the device. The device firmware update policy does not support firmware
+/// version downgrade.
+///
+#define IMAGE_UPDATABLE_INVALID_OLD 0x0000000000000008
+///
+/// IMAGE_UPDATABLE_VALID_WITH_VENDOR_CODE indicates SetImage() will accept and update
+/// the new image only if a correct VendorCode is provided or else image would be
+/// rejected and SetImage will return appropriate error.
+///
+#define IMAGE_UPDATABLE_VALID_WITH_VENDOR_CODE 0x0000000000000010
+
+//
+// Package Attribute Definitions
+//
+///
+/// The attribute PACKAGE_ATTRIBUTE_VERSION_UPDATABLE indicates this device supports the
+/// update of the firmware package version.
+///
+#define PACKAGE_ATTRIBUTE_VERSION_UPDATABLE 0x0000000000000001
+///
+/// The attribute PACKAGE_ATTRIBUTE_RESET_REQUIRED indicates a reset of the device is
+/// required for the new package info to take effect after an update.
+///
+#define PACKAGE_ATTRIBUTE_RESET_REQUIRED 0x0000000000000002
+///
+/// The attribute PACKAGE_ATTRIBUTE_AUTHENTICATION_REQUIRED indicates authentication
+/// is required to update the package info.
+///
+#define PACKAGE_ATTRIBUTE_AUTHENTICATION_REQUIRED 0x0000000000000004
+
+/**
+ Callback function to report the process of the firmware updating.
+
+ @param[in] Completion A value between 1 and 100 indicating the current completion
+ progress of the firmware update. Completion progress is
+ reported as from 1 to 100 percent. A value of 0 is used by
+ the driver to indicate that progress reporting is not supported.
+
+ @retval EFI_SUCCESS SetImage() continues to do the callback if supported.
+ @retval other SetImage() discontinues the callback and completes
+ the update and returns.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_FIRMWARE_MANAGEMENT_UPDATE_IMAGE_PROGRESS)(
+ IN UINTN Completion
+ );
+
+/**
+ Returns information about the current firmware image(s) of the device.
+
+ This function allows a copy of the current firmware image to be created and saved.
+ The saved copy could later been used, for example, in firmware image recovery or rollback.
+
+ @param[in] This A pointer to the EFI_FIRMWARE_MANAGEMENT_PROTOCOL instance.
+ @param[in, out] ImageInfoSize A pointer to the size, in bytes, of the ImageInfo buffer.
+ On input, this is the size of the buffer allocated by the caller.
+ On output, it is the size of the buffer returned by the firmware
+ if the buffer was large enough, or the size of the buffer needed
+ to contain the image(s) information if the buffer was too small.
+ @param[in, out] ImageInfo A pointer to the buffer in which firmware places the current image(s)
+ information. The information is an array of EFI_FIRMWARE_IMAGE_DESCRIPTORs.
+ @param[out] DescriptorVersion A pointer to the location in which firmware returns the version number
+ associated with the EFI_FIRMWARE_IMAGE_DESCRIPTOR.
+ @param[out] DescriptorCount A pointer to the location in which firmware returns the number of
+ descriptors or firmware images within this device.
+ @param[out] DescriptorSize A pointer to the location in which firmware returns the size, in bytes,
+ of an individual EFI_FIRMWARE_IMAGE_DESCRIPTOR.
+ @param[out] PackageVersion A version number that represents all the firmware images in the device.
+ The format is vendor specific and new version must have a greater value
+ than the old version. If PackageVersion is not supported, the value is
+ 0xFFFFFFFF. A value of 0xFFFFFFFE indicates that package version comparison
+ is to be performed using PackageVersionName. A value of 0xFFFFFFFD indicates
+ that package version update is in progress.
+ @param[out] PackageVersionName A pointer to a pointer to a null-terminated string representing the
+ package version name. The buffer is allocated by this function with
+ AllocatePool(), and it is the caller's responsibility to free it with a call
+ to FreePool().
+
+ @retval EFI_SUCCESS The device was successfully updated with the new image.
+ @retval EFI_BUFFER_TOO_SMALL The ImageInfo buffer was too small. The current buffer size
+ needed to hold the image(s) information is returned in ImageInfoSize.
+ @retval EFI_INVALID_PARAMETER ImageInfoSize is NULL.
+ @retval EFI_DEVICE_ERROR Valid information could not be returned. Possible corrupted image.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_FIRMWARE_MANAGEMENT_PROTOCOL_GET_IMAGE_INFO)(
+ IN EFI_FIRMWARE_MANAGEMENT_PROTOCOL *This,
+ IN OUT UINTN *ImageInfoSize,
+ IN OUT EFI_FIRMWARE_IMAGE_DESCRIPTOR *ImageInfo,
+ OUT UINT32 *DescriptorVersion,
+ OUT UINT8 *DescriptorCount,
+ OUT UINTN *DescriptorSize,
+ OUT UINT32 *PackageVersion,
+ OUT CHAR16 **PackageVersionName
+ );
+
+/**
+ Retrieves a copy of the current firmware image of the device.
+
+ This function allows a copy of the current firmware image to be created and saved.
+ The saved copy could later been used, for example, in firmware image recovery or rollback.
+
+ @param[in] This A pointer to the EFI_FIRMWARE_MANAGEMENT_PROTOCOL instance.
+ @param[in] ImageIndex A unique number identifying the firmware image(s) within the device.
+ The number is between 1 and DescriptorCount.
+ @param[out] Image Points to the buffer where the current image is copied to.
+ @param[in, out] ImageSize On entry, points to the size of the buffer pointed to by Image, in bytes.
+ On return, points to the length of the image, in bytes.
+
+ @retval EFI_SUCCESS The device was successfully updated with the new image.
+ @retval EFI_BUFFER_TOO_SMALL The buffer specified by ImageSize is too small to hold the
+ image. The current buffer size needed to hold the image is returned
+ in ImageSize.
+ @retval EFI_INVALID_PARAMETER The Image was NULL.
+ @retval EFI_NOT_FOUND The current image is not copied to the buffer.
+ @retval EFI_UNSUPPORTED The operation is not supported.
+ @retval EFI_SECURITY_VIOLATION The operation could not be performed due to an authentication failure.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_FIRMWARE_MANAGEMENT_PROTOCOL_GET_IMAGE)(
+ IN EFI_FIRMWARE_MANAGEMENT_PROTOCOL *This,
+ IN UINT8 ImageIndex,
+ OUT VOID *Image,
+ IN OUT UINTN *ImageSize
+ );
+
+/**
+ Updates the firmware image of the device.
+
+ This function updates the hardware with the new firmware image.
+ This function returns EFI_UNSUPPORTED if the firmware image is not updatable.
+ If the firmware image is updatable, the function should perform the following minimal validations
+ before proceeding to do the firmware image update.
+ - Validate the image authentication if image has attribute
+ IMAGE_ATTRIBUTE_AUTHENTICATION_REQUIRED. The function returns
+ EFI_SECURITY_VIOLATION if the validation fails.
+ - Validate the image is a supported image for this device. The function returns EFI_ABORTED if
+ the image is unsupported. The function can optionally provide more detailed information on
+ why the image is not a supported image.
+ - Validate the data from VendorCode if not null. Image validation must be performed before
+ VendorCode data validation. VendorCode data is ignored or considered invalid if image
+ validation failed. The function returns EFI_ABORTED if the data is invalid.
+
+ VendorCode enables vendor to implement vendor-specific firmware image update policy. Null if
+ the caller did not specify the policy or use the default policy. As an example, vendor can implement
+ a policy to allow an option to force a firmware image update when the abort reason is due to the new
+ firmware image version is older than the current firmware image version or bad image checksum.
+ Sensitive operations such as those wiping the entire firmware image and render the device to be
+ non-functional should be encoded in the image itself rather than passed with the VendorCode.
+ AbortReason enables vendor to have the option to provide a more detailed description of the abort
+ reason to the caller.
+
+ @param[in] This A pointer to the EFI_FIRMWARE_MANAGEMENT_PROTOCOL instance.
+ @param[in] ImageIndex A unique number identifying the firmware image(s) within the device.
+ The number is between 1 and DescriptorCount.
+ @param[in] Image Points to the new image.
+ @param[in] ImageSize Size of the new image in bytes.
+ @param[in] VendorCode This enables vendor to implement vendor-specific firmware image update policy.
+ Null indicates the caller did not specify the policy or use the default policy.
+ @param[in] Progress A function used by the driver to report the progress of the firmware update.
+ @param[out] AbortReason A pointer to a pointer to a null-terminated string providing more
+ details for the aborted operation. The buffer is allocated by this function
+ with AllocatePool(), and it is the caller's responsibility to free it with a
+ call to FreePool().
+
+ @retval EFI_SUCCESS The device was successfully updated with the new image.
+ @retval EFI_ABORTED The operation is aborted.
+ @retval EFI_INVALID_PARAMETER The Image was NULL.
+ @retval EFI_UNSUPPORTED The operation is not supported.
+ @retval EFI_SECURITY_VIOLATION The operation could not be performed due to an authentication failure.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_FIRMWARE_MANAGEMENT_PROTOCOL_SET_IMAGE)(
+ IN EFI_FIRMWARE_MANAGEMENT_PROTOCOL *This,
+ IN UINT8 ImageIndex,
+ IN CONST VOID *Image,
+ IN UINTN ImageSize,
+ IN CONST VOID *VendorCode,
+ IN EFI_FIRMWARE_MANAGEMENT_UPDATE_IMAGE_PROGRESS Progress,
+ OUT CHAR16 **AbortReason
+ );
+
+/**
+ Checks if the firmware image is valid for the device.
+
+ This function allows firmware update application to validate the firmware image without
+ invoking the SetImage() first.
+
+ @param[in] This A pointer to the EFI_FIRMWARE_MANAGEMENT_PROTOCOL instance.
+ @param[in] ImageIndex A unique number identifying the firmware image(s) within the device.
+ The number is between 1 and DescriptorCount.
+ @param[in] Image Points to the new image.
+ @param[in] ImageSize Size of the new image in bytes.
+ @param[out] ImageUpdatable Indicates if the new image is valid for update. It also provides,
+ if available, additional information if the image is invalid.
+
+ @retval EFI_SUCCESS The image was successfully checked.
+ @retval EFI_INVALID_PARAMETER The Image was NULL.
+ @retval EFI_UNSUPPORTED The operation is not supported.
+ @retval EFI_SECURITY_VIOLATION The operation could not be performed due to an authentication failure.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_FIRMWARE_MANAGEMENT_PROTOCOL_CHECK_IMAGE)(
+ IN EFI_FIRMWARE_MANAGEMENT_PROTOCOL *This,
+ IN UINT8 ImageIndex,
+ IN CONST VOID *Image,
+ IN UINTN ImageSize,
+ OUT UINT32 *ImageUpdatable
+ );
+
+/**
+ Returns information about the firmware package.
+
+ This function returns package information.
+
+ @param[in] This A pointer to the EFI_FIRMWARE_MANAGEMENT_PROTOCOL instance.
+ @param[out] PackageVersion A version number that represents all the firmware images in the device.
+ The format is vendor specific and new version must have a greater value
+ than the old version. If PackageVersion is not supported, the value is
+ 0xFFFFFFFF. A value of 0xFFFFFFFE indicates that package version
+ comparison is to be performed using PackageVersionName. A value of
+ 0xFFFFFFFD indicates that package version update is in progress.
+ @param[out] PackageVersionName A pointer to a pointer to a null-terminated string representing
+ the package version name. The buffer is allocated by this function with
+ AllocatePool(), and it is the caller's responsibility to free it with a
+ call to FreePool().
+ @param[out] PackageVersionNameMaxLen The maximum length of package version name if device supports update of
+ package version name. A value of 0 indicates the device does not support
+ update of package version name. Length is the number of Unicode characters,
+ including the terminating null character.
+ @param[out] AttributesSupported Package attributes that are supported by this device. See 'Package Attribute
+ Definitions' for possible returned values of this parameter. A value of 1
+ indicates the attribute is supported and the current setting value is
+ indicated in AttributesSetting. A value of 0 indicates the attribute is not
+ supported and the current setting value in AttributesSetting is meaningless.
+ @param[out] AttributesSetting Package attributes. See 'Package Attribute Definitions' for possible returned
+ values of this parameter
+
+ @retval EFI_SUCCESS The package information was successfully returned.
+ @retval EFI_UNSUPPORTED The operation is not supported.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_FIRMWARE_MANAGEMENT_PROTOCOL_GET_PACKAGE_INFO)(
+ IN EFI_FIRMWARE_MANAGEMENT_PROTOCOL *This,
+ OUT UINT32 *PackageVersion,
+ OUT CHAR16 **PackageVersionName,
+ OUT UINT32 *PackageVersionNameMaxLen,
+ OUT UINT64 *AttributesSupported,
+ OUT UINT64 *AttributesSetting
+ );
+
+/**
+ Updates information about the firmware package.
+
+ This function updates package information.
+ This function returns EFI_UNSUPPORTED if the package information is not updatable.
+ VendorCode enables vendor to implement vendor-specific package information update policy.
+ Null if the caller did not specify this policy or use the default policy.
+
+ @param[in] This A pointer to the EFI_FIRMWARE_MANAGEMENT_PROTOCOL instance.
+ @param[in] Image Points to the authentication image.
+ Null if authentication is not required.
+ @param[in] ImageSize Size of the authentication image in bytes.
+ 0 if authentication is not required.
+ @param[in] VendorCode This enables vendor to implement vendor-specific firmware
+ image update policy.
+ Null indicates the caller did not specify this policy or use
+ the default policy.
+ @param[in] PackageVersion The new package version.
+ @param[in] PackageVersionName A pointer to the new null-terminated Unicode string representing
+ the package version name.
+ The string length is equal to or less than the value returned in
+ PackageVersionNameMaxLen.
+
+ @retval EFI_SUCCESS The device was successfully updated with the new package
+ information.
+ @retval EFI_INVALID_PARAMETER The PackageVersionName length is longer than the value
+ returned in PackageVersionNameMaxLen.
+ @retval EFI_UNSUPPORTED The operation is not supported.
+ @retval EFI_SECURITY_VIOLATION The operation could not be performed due to an authentication failure.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_FIRMWARE_MANAGEMENT_PROTOCOL_SET_PACKAGE_INFO)(
+ IN EFI_FIRMWARE_MANAGEMENT_PROTOCOL *This,
+ IN CONST VOID *Image,
+ IN UINTN ImageSize,
+ IN CONST VOID *VendorCode,
+ IN UINT32 PackageVersion,
+ IN CONST CHAR16 *PackageVersionName
+ );
+
+///
+/// EFI_FIRMWARE_MANAGEMENT_PROTOCOL
+/// The protocol for managing firmware provides the following services.
+/// - Get the attributes of the current firmware image. Attributes include revision level.
+/// - Get a copy of the current firmware image. As an example, this service could be used by a
+/// management application to facilitate a firmware roll-back.
+/// - Program the device with a firmware image supplied by the user.
+/// - Label all the firmware images within a device with a single version.
+///
+struct _EFI_FIRMWARE_MANAGEMENT_PROTOCOL {
+ EFI_FIRMWARE_MANAGEMENT_PROTOCOL_GET_IMAGE_INFO GetImageInfo;
+ EFI_FIRMWARE_MANAGEMENT_PROTOCOL_GET_IMAGE GetImage;
+ EFI_FIRMWARE_MANAGEMENT_PROTOCOL_SET_IMAGE SetImage;
+ EFI_FIRMWARE_MANAGEMENT_PROTOCOL_CHECK_IMAGE CheckImage;
+ EFI_FIRMWARE_MANAGEMENT_PROTOCOL_GET_PACKAGE_INFO GetPackageInfo;
+ EFI_FIRMWARE_MANAGEMENT_PROTOCOL_SET_PACKAGE_INFO SetPackageInfo;
+};
+
+extern EFI_GUID gEfiFirmwareManagementProtocolGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/FirmwareVolume2.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/FirmwareVolume2.h
new file mode 100644
index 0000000000..2b6c01b051
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/FirmwareVolume2.h
@@ -0,0 +1,747 @@
+/** @file
+ The Firmware Volume Protocol provides file-level access to the firmware volume.
+ Each firmware volume driver must produce an instance of the
+ Firmware Volume Protocol if the firmware volume is to be visible to
+ the system during the DXE phase. The Firmware Volume Protocol also provides
+ mechanisms for determining and modifying some attributes of the firmware volume.
+
+ Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Revision Reference: PI
+ Version 1.00.
+
+**/
+
+#ifndef __FIRMWARE_VOLUME2_H__
+#define __FIRMWARE_VOLUME2_H__
+
+#define EFI_FIRMWARE_VOLUME2_PROTOCOL_GUID \
+ { 0x220e73b6, 0x6bdb, 0x4413, { 0x84, 0x5, 0xb9, 0x74, 0xb1, 0x8, 0x61, 0x9a } }
+
+typedef struct _EFI_FIRMWARE_VOLUME2_PROTOCOL EFI_FIRMWARE_VOLUME2_PROTOCOL;
+
+///
+/// EFI_FV_ATTRIBUTES
+///
+typedef UINT64 EFI_FV_ATTRIBUTES;
+
+//
+// EFI_FV_ATTRIBUTES bit definitions
+//
+// EFI_FV_ATTRIBUTES bit semantics
+#define EFI_FV2_READ_DISABLE_CAP 0x0000000000000001ULL
+#define EFI_FV2_READ_ENABLE_CAP 0x0000000000000002ULL
+#define EFI_FV2_READ_STATUS 0x0000000000000004ULL
+#define EFI_FV2_WRITE_DISABLE_CAP 0x0000000000000008ULL
+#define EFI_FV2_WRITE_ENABLE_CAP 0x0000000000000010ULL
+#define EFI_FV2_WRITE_STATUS 0x0000000000000020ULL
+#define EFI_FV2_LOCK_CAP 0x0000000000000040ULL
+#define EFI_FV2_LOCK_STATUS 0x0000000000000080ULL
+#define EFI_FV2_WRITE_POLICY_RELIABLE 0x0000000000000100ULL
+#define EFI_FV2_READ_LOCK_CAP 0x0000000000001000ULL
+#define EFI_FV2_READ_LOCK_STATUS 0x0000000000002000ULL
+#define EFI_FV2_WRITE_LOCK_CAP 0x0000000000004000ULL
+#define EFI_FV2_WRITE_LOCK_STATUS 0x0000000000008000ULL
+#define EFI_FV2_ALIGNMENT 0x00000000001F0000ULL
+#define EFI_FV2_ALIGNMENT_1 0x0000000000000000ULL
+#define EFI_FV2_ALIGNMENT_2 0x0000000000010000ULL
+#define EFI_FV2_ALIGNMENT_4 0x0000000000020000ULL
+#define EFI_FV2_ALIGNMENT_8 0x0000000000030000ULL
+#define EFI_FV2_ALIGNMENT_16 0x0000000000040000ULL
+#define EFI_FV2_ALIGNMENT_32 0x0000000000050000ULL
+#define EFI_FV2_ALIGNMENT_64 0x0000000000060000ULL
+#define EFI_FV2_ALIGNMENT_128 0x0000000000070000ULL
+#define EFI_FV2_ALIGNMENT_256 0x0000000000080000ULL
+#define EFI_FV2_ALIGNMENT_512 0x0000000000090000ULL
+#define EFI_FV2_ALIGNMENT_1K 0x00000000000A0000ULL
+#define EFI_FV2_ALIGNMENT_2K 0x00000000000B0000ULL
+#define EFI_FV2_ALIGNMENT_4K 0x00000000000C0000ULL
+#define EFI_FV2_ALIGNMENT_8K 0x00000000000D0000ULL
+#define EFI_FV2_ALIGNMENT_16K 0x00000000000E0000ULL
+#define EFI_FV2_ALIGNMENT_32K 0x00000000000F0000ULL
+#define EFI_FV2_ALIGNMENT_64K 0x0000000000100000ULL
+#define EFI_FV2_ALIGNMENT_128K 0x0000000000110000ULL
+#define EFI_FV2_ALIGNMENT_256K 0x0000000000120000ULL
+#define EFI_FV2_ALIGNMENT_512K 0x0000000000130000ULL
+#define EFI_FV2_ALIGNMENT_1M 0x0000000000140000ULL
+#define EFI_FV2_ALIGNMENT_2M 0x0000000000150000ULL
+#define EFI_FV2_ALIGNMENT_4M 0x0000000000160000ULL
+#define EFI_FV2_ALIGNMENT_8M 0x0000000000170000ULL
+#define EFI_FV2_ALIGNMENT_16M 0x0000000000180000ULL
+#define EFI_FV2_ALIGNMENT_32M 0x0000000000190000ULL
+#define EFI_FV2_ALIGNMENT_64M 0x00000000001A0000ULL
+#define EFI_FV2_ALIGNMENT_128M 0x00000000001B0000ULL
+#define EFI_FV2_ALIGNMENT_256M 0x00000000001C0000ULL
+#define EFI_FV2_ALIGNMENT_512M 0x00000000001D0000ULL
+#define EFI_FV2_ALIGNMENT_1G 0x00000000001E0000ULL
+#define EFI_FV2_ALIGNMENT_2G 0x00000000001F0000ULL
+
+/**
+ Returns the attributes and current settings of the firmware volume.
+
+ Because of constraints imposed by the underlying firmware
+ storage, an instance of the Firmware Volume Protocol may not
+ be to able to support all possible variations of this
+ architecture. These constraints and the current state of the
+ firmware volume are exposed to the caller using the
+ GetVolumeAttributes() function. GetVolumeAttributes() is
+ callable only from TPL_NOTIFY and below. Behavior of
+ GetVolumeAttributes() at any EFI_TPL above TPL_NOTIFY is
+ undefined.
+
+ @param This Indicates the EFI_FIRMWARE_VOLUME2_PROTOCOL instance.
+
+ @param FvAttributes Pointer to an EFI_FV_ATTRIBUTES in which
+ the attributes and current settings are
+ returned.
+
+
+ @retval EFI_SUCCESS The firmware volume attributes were
+ returned.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_FV_GET_ATTRIBUTES)(
+ IN CONST EFI_FIRMWARE_VOLUME2_PROTOCOL *This,
+ OUT EFI_FV_ATTRIBUTES *FvAttributes
+ );
+
+/**
+ Modifies the current settings of the firmware volume according to the input parameter.
+
+ The SetVolumeAttributes() function is used to set configurable
+ firmware volume attributes. Only EFI_FV_READ_STATUS,
+ EFI_FV_WRITE_STATUS, and EFI_FV_LOCK_STATUS may be modified, and
+ then only in accordance with the declared capabilities. All
+ other bits of FvAttributes are ignored on input. On successful
+ return, all bits of *FvAttributes are valid and it contains the
+ completed EFI_FV_ATTRIBUTES for the volume. To modify an
+ attribute, the corresponding status bit in the EFI_FV_ATTRIBUTES
+ is set to the desired value on input. The EFI_FV_LOCK_STATUS bit
+ does not affect the ability to read or write the firmware
+ volume. Rather, once the EFI_FV_LOCK_STATUS bit is set, it
+ prevents further modification to all the attribute bits.
+ SetVolumeAttributes() is callable only from TPL_NOTIFY and
+ below. Behavior of SetVolumeAttributes() at any EFI_TPL above
+ TPL_NOTIFY is undefined.
+
+ @param This Indicates the EFI_FIRMWARE_VOLUME2_PROTOCOL instance.
+
+ @param FvAttributes On input, FvAttributes is a pointer to
+ an EFI_FV_ATTRIBUTES containing the
+ desired firmware volume settings. On
+ successful return, it contains the new
+ settings of the firmware volume. On
+ unsuccessful return, FvAttributes is not
+ modified and the firmware volume
+ settings are not changed.
+
+ @retval EFI_SUCCESS The requested firmware volume attributes
+ were set and the resulting
+ EFI_FV_ATTRIBUTES is returned in
+ FvAttributes.
+
+ @retval EFI_INVALID_PARAMETER FvAttributes:EFI_FV_READ_STATUS
+ is set to 1 on input, but the
+ device does not support enabling
+ reads
+ (FvAttributes:EFI_FV_READ_ENABLE
+ is clear on return from
+ GetVolumeAttributes()). Actual
+ volume attributes are unchanged.
+
+ @retval EFI_INVALID_PARAMETER FvAttributes:EFI_FV_READ_STATUS
+ is cleared to 0 on input, but
+ the device does not support
+ disabling reads
+ (FvAttributes:EFI_FV_READ_DISABL
+ is clear on return from
+ GetVolumeAttributes()). Actual
+ volume attributes are unchanged.
+
+ @retval EFI_INVALID_PARAMETER FvAttributes:EFI_FV_WRITE_STATUS
+ is set to 1 on input, but the
+ device does not support enabling
+ writes
+ (FvAttributes:EFI_FV_WRITE_ENABL
+ is clear on return from
+ GetVolumeAttributes()). Actual
+ volume attributes are unchanged.
+
+ @retval EFI_INVALID_PARAMETER FvAttributes:EFI_FV_WRITE_STATUS
+ is cleared to 0 on input, but
+ the device does not support
+ disabling writes
+ (FvAttributes:EFI_FV_WRITE_DISAB
+ is clear on return from
+ GetVolumeAttributes()). Actual
+ volume attributes are unchanged.
+
+ @retval EFI_INVALID_PARAMETER FvAttributes:EFI_FV_LOCK_STATUS
+ is set on input, but the device
+ does not support locking
+ (FvAttributes:EFI_FV_LOCK_CAP is
+ clear on return from
+ GetVolumeAttributes()). Actual
+ volume attributes are unchanged.
+
+ @retval EFI_ACCESS_DENIED Device is locked and does not
+ allow attribute modification
+ (FvAttributes:EFI_FV_LOCK_STATUS
+ is set on return from
+ GetVolumeAttributes()). Actual
+ volume attributes are unchanged.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_FV_SET_ATTRIBUTES)(
+ IN CONST EFI_FIRMWARE_VOLUME2_PROTOCOL *This,
+ IN OUT EFI_FV_ATTRIBUTES *FvAttributes
+ );
+
+/**
+ Retrieves a file and/or file information from the firmware volume.
+
+ ReadFile() is used to retrieve any file from a firmware volume
+ during the DXE phase. The actual binary encoding of the file in
+ the firmware volume media may be in any arbitrary format as long
+ as it does the following: It is accessed using the Firmware
+ Volume Protocol. The image that is returned follows the image
+ format defined in Code Definitions: PI Firmware File Format.
+ If the input value of Buffer==NULL, it indicates the caller is
+ requesting only that the type, attributes, and size of the
+ file be returned and that there is no output buffer. In this
+ case, the following occurs:
+ - BufferSize is returned with the size that is required to
+ successfully complete the read.
+ - The output parameters FoundType and *FileAttributes are
+ returned with valid values.
+ - The returned value of *AuthenticationStatus is undefined.
+
+ If the input value of Buffer!=NULL, the output buffer is
+ specified by a double indirection of the Buffer parameter. The
+ input value of *Buffer is used to determine if the output
+ buffer is caller allocated or is dynamically allocated by
+ ReadFile(). If the input value of *Buffer!=NULL, it indicates
+ the output buffer is caller allocated. In this case, the input
+ value of *BufferSize indicates the size of the
+ caller-allocated output buffer. If the output buffer is not
+ large enough to contain the entire requested output, it is
+ filled up to the point that the output buffer is exhausted and
+ EFI_WARN_BUFFER_TOO_SMALL is returned, and then BufferSize is
+ returned with the size required to successfully complete the
+ read. All other output parameters are returned with valid
+ values. If the input value of *Buffer==NULL, it indicates the
+ output buffer is to be allocated by ReadFile(). In this case,
+ ReadFile() will allocate an appropriately sized buffer from
+ boot services pool memory, which will be returned in Buffer.
+ The size of the new buffer is returned in BufferSize and all
+ other output parameters are returned with valid values.
+ ReadFile() is callable only from TPL_NOTIFY and below.
+ Behavior of ReadFile() at any EFI_TPL above TPL_NOTIFY is
+ undefined.
+
+ @param This Indicates the EFI_FIRMWARE_VOLUME2_PROTOCOL instance.
+
+ @param NameGuid Pointer to an EFI_GUID, which is the file
+ name. All firmware file names are EFI_GUIDs.
+ A single firmware volume must not have two
+ valid files with the same file name
+ EFI_GUID.
+
+ @param Buffer Pointer to a pointer to a buffer in which the
+ file contents are returned, not including the
+ file header.
+
+ @param BufferSize Pointer to a caller-allocated UINTN. It
+ indicates the size of the memory
+ represented by Buffer.
+
+ @param FoundType Pointer to a caller-allocated EFI_FV_FILETYPE.
+
+ @param FileAttributes Pointer to a caller-allocated
+ EFI_FV_FILE_ATTRIBUTES.
+
+ @param AuthenticationStatus Pointer to a caller-allocated
+ UINT32 in which the
+ authentication status is
+ returned.
+
+ @retval EFI_SUCCESS The call completed successfully.
+
+ @retval EFI_WARN_BUFFER_TOO_SMALL The buffer is too small to
+ contain the requested
+ output. The buffer is
+ filled and the output is
+ truncated.
+
+ @retval EFI_OUT_OF_RESOURCES An allocation failure occurred.
+
+ @retval EFI_NOT_FOUND Name was not found in the firmware volume.
+
+ @retval EFI_DEVICE_ERROR A hardware error occurred when
+ attempting to access the firmware volume.
+
+ @retval EFI_ACCESS_DENIED The firmware volume is configured to
+ disallow reads.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_FV_READ_FILE)(
+ IN CONST EFI_FIRMWARE_VOLUME2_PROTOCOL *This,
+ IN CONST EFI_GUID *NameGuid,
+ IN OUT VOID **Buffer,
+ IN OUT UINTN *BufferSize,
+ OUT EFI_FV_FILETYPE *FoundType,
+ OUT EFI_FV_FILE_ATTRIBUTES *FileAttributes,
+ OUT UINT32 *AuthenticationStatus
+ );
+
+/**
+ Locates the requested section within a file and returns it in a buffer.
+
+ ReadSection() is used to retrieve a specific section from a file
+ within a firmware volume. The section returned is determined
+ using a depth-first, left-to-right search algorithm through all
+ sections found in the specified file. The output buffer is specified by a double indirection
+ of the Buffer parameter. The input value of Buffer is used to
+ determine if the output buffer is caller allocated or is
+ dynamically allocated by ReadSection(). If the input value of
+ Buffer!=NULL, it indicates that the output buffer is caller
+ allocated. In this case, the input value of *BufferSize
+ indicates the size of the caller-allocated output buffer. If
+ the output buffer is not large enough to contain the entire
+ requested output, it is filled up to the point that the output
+ buffer is exhausted and EFI_WARN_BUFFER_TOO_SMALL is returned,
+ and then BufferSize is returned with the size that is required
+ to successfully complete the read. All other
+ output parameters are returned with valid values. If the input
+ value of *Buffer==NULL, it indicates the output buffer is to
+ be allocated by ReadSection(). In this case, ReadSection()
+ will allocate an appropriately sized buffer from boot services
+ pool memory, which will be returned in *Buffer. The size of
+ the new buffer is returned in *BufferSize and all other output
+ parameters are returned with valid values. ReadSection() is
+ callable only from TPL_NOTIFY and below. Behavior of
+ ReadSection() at any EFI_TPL above TPL_NOTIFY is
+ undefined.
+
+ @param This Indicates the EFI_FIRMWARE_VOLUME2_PROTOCOL instance.
+
+ @param NameGuid Pointer to an EFI_GUID, which indicates the
+ file name from which the requested section
+ will be read.
+
+ @param SectionType Indicates the section type to return.
+ SectionType in conjunction with
+ SectionInstance indicates which section to
+ return.
+
+ @param SectionInstance Indicates which instance of sections
+ with a type of SectionType to return.
+ SectionType in conjunction with
+ SectionInstance indicates which
+ section to return. SectionInstance is
+ zero based.
+
+ @param Buffer Pointer to a pointer to a buffer in which the
+ section contents are returned, not including
+ the section header.
+
+ @param BufferSize Pointer to a caller-allocated UINTN. It
+ indicates the size of the memory
+ represented by Buffer.
+
+ @param AuthenticationStatus Pointer to a caller-allocated
+ UINT32 in which the authentication
+ status is returned.
+
+
+ @retval EFI_SUCCESS The call completed successfully.
+
+ @retval EFI_WARN_BUFFER_TOO_SMALL The caller-allocated
+ buffer is too small to
+ contain the requested
+ output. The buffer is
+ filled and the output is
+ truncated.
+
+ @retval EFI_OUT_OF_RESOURCES An allocation failure occurred.
+
+ @retval EFI_NOT_FOUND The requested file was not found in
+ the firmware volume. EFI_NOT_FOUND The
+ requested section was not found in the
+ specified file.
+
+ @retval EFI_DEVICE_ERROR A hardware error occurred when
+ attempting to access the firmware
+ volume.
+
+ @retval EFI_ACCESS_DENIED The firmware volume is configured to
+ disallow reads. EFI_PROTOCOL_ERROR
+ The requested section was not found,
+ but the file could not be fully
+ parsed because a required
+ GUIDED_SECTION_EXTRACTION_PROTOCOL
+ was not found. It is possible the
+ requested section exists within the
+ file and could be successfully
+ extracted once the required
+ GUIDED_SECTION_EXTRACTION_PROTOCOL
+ is published.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_FV_READ_SECTION)(
+ IN CONST EFI_FIRMWARE_VOLUME2_PROTOCOL *This,
+ IN CONST EFI_GUID *NameGuid,
+ IN EFI_SECTION_TYPE SectionType,
+ IN UINTN SectionInstance,
+ IN OUT VOID **Buffer,
+ IN OUT UINTN *BufferSize,
+ OUT UINT32 *AuthenticationStatus
+ );
+
+///
+/// EFI_FV_WRITE_POLICY, two policies (unreliable write and reliable write) are defined.
+///
+typedef UINT32 EFI_FV_WRITE_POLICY;
+#define EFI_FV_UNRELIABLE_WRITE 0x00000000
+#define EFI_FV_RELIABLE_WRITE 0x00000001
+
+//
+// EFI_FV_WRITE_FILE_DATA
+//
+typedef struct {
+ ///
+ /// Pointer to a GUID, which is the file name to be written.
+ ///
+ EFI_GUID *NameGuid;
+ ///
+ /// Indicates the type of file to be written.
+ ///
+ EFI_FV_FILETYPE Type;
+ ///
+ /// Indicates the attributes for the file to be written.
+ ///
+ EFI_FV_FILE_ATTRIBUTES FileAttributes;
+ ///
+ /// Pointer to a buffer containing the file to be written.
+ ///
+ VOID *Buffer;
+ ///
+ /// Indicates the size of the file image contained in Buffer.
+ ///
+ UINT32 BufferSize;
+} EFI_FV_WRITE_FILE_DATA;
+
+/**
+ Locates the requested section within a file and returns it in a buffer.
+
+ WriteFile() is used to write one or more files to a firmware
+ volume. Each file to be written is described by an
+ EFI_FV_WRITE_FILE_DATA structure. The caller must ensure that
+ any required alignment for all files listed in the FileData
+ array is compatible with the firmware volume. Firmware volume
+ capabilities can be determined using the GetVolumeAttributes()
+ call. Similarly, if the WritePolicy is set to
+ EFI_FV_RELIABLE_WRITE, the caller must check the firmware volume
+ capabilities to ensure EFI_FV_RELIABLE_WRITE is supported by the
+ firmware volume. EFI_FV_UNRELIABLE_WRITE must always be
+ supported. Writing a file with a size of zero
+ (FileData[n].BufferSize == 0) deletes the file from the firmware
+ volume if it exists. Deleting a file must be done one at a time.
+ Deleting a file as part of a multiple file write is not allowed.
+ Platform Initialization Specification VOLUME 3 Shared
+ Architectural Elements 84 August 21, 2006 Version 1.0
+ WriteFile() is callable only from TPL_NOTIFY and below.
+ Behavior of WriteFile() at any EFI_TPL above TPL_NOTIFY is
+ undefined.
+
+ @param This Indicates the EFI_FIRMWARE_VOLUME2_PROTOCOL instance.
+
+ @param NumberOfFiles Indicates the number of elements in the array pointed to by FileData
+
+ @param WritePolicy Indicates the level of reliability for the
+ write in the event of a power failure or
+ other system failure during the write
+ operation.
+
+ @param FileData Pointer to an array of
+ EFI_FV_WRITE_FILE_DATA. Each element of
+ FileData[] represents a file to be written.
+
+
+ @retval EFI_SUCCESS The write completed successfully.
+
+ @retval EFI_OUT_OF_RESOURCES The firmware volume does not
+ have enough free space to
+ storefile(s).
+
+ @retval EFI_DEVICE_ERROR A hardware error occurred when
+ attempting to access the firmware volume.
+
+ @retval EFI_WRITE_PROTECTED The firmware volume is
+ configured to disallow writes.
+
+ @retval EFI_NOT_FOUND A delete was requested, but the
+ requested file was not found in the
+ firmware volume.
+
+ @retval EFI_INVALID_PARAMETER A delete was requested with a
+ multiple file write.
+
+ @retval EFI_INVALID_PARAMETER An unsupported WritePolicy was
+ requested.
+
+ @retval EFI_INVALID_PARAMETER An unknown file type was
+ specified.
+
+ @retval EFI_INVALID_PARAMETER A file system specific error
+ has occurred.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_FV_WRITE_FILE)(
+ IN CONST EFI_FIRMWARE_VOLUME2_PROTOCOL *This,
+ IN UINT32 NumberOfFiles,
+ IN EFI_FV_WRITE_POLICY WritePolicy,
+ IN EFI_FV_WRITE_FILE_DATA *FileData
+ );
+
+/**
+ Retrieves information about the next file in the firmware volume store
+ that matches the search criteria.
+
+ GetNextFile() is the interface that is used to search a firmware
+ volume for a particular file. It is called successively until
+ the desired file is located or the function returns
+ EFI_NOT_FOUND. To filter uninteresting files from the output,
+ the type of file to search for may be specified in FileType. For
+ example, if *FileType is EFI_FV_FILETYPE_DRIVER, only files of
+ this type will be returned in the output. If *FileType is
+ EFI_FV_FILETYPE_ALL, no filtering of file types is done. The Key
+ parameter is used to indicate a starting point of the search. If
+ the buffer *Key is completely initialized to zero, the search
+ re-initialized and starts at the beginning. Subsequent calls to
+ GetNextFile() must maintain the value of *Key returned by the
+ immediately previous call. The actual contents of *Key are
+ implementation specific and no semantic content is implied.
+ GetNextFile() is callable only from TPL_NOTIFY and below.
+ Behavior of GetNextFile() at any EFI_TPL above TPL_NOTIFY is
+ undefined.
+
+ @param This Indicates the EFI_FIRMWARE_VOLUME2_PROTOCOL instance.
+
+ @param Key Pointer to a caller-allocated buffer that contains implementation-specific data that is
+ used to track where to begin the search for the next file. The size of the buffer must be
+ at least This->KeySize bytes long. To re-initialize the search and begin from the
+ beginning of the firmware volume, the entire buffer must be cleared to zero. Other
+ than clearing the buffer to initiate a new search, the caller must not modify the data in
+ the buffer between calls to GetNextFile().
+
+ @param FileType Pointer to a caller-allocated
+ EFI_FV_FILETYPE. The GetNextFile() API can
+ filter its search for files based on the
+ value of the FileType input. A *FileType
+ input of EFI_FV_FILETYPE_ALL causes
+ GetNextFile() to search for files of all
+ types. If a file is found, the file's type
+ is returned in FileType. *FileType is not
+ modified if no file is found.
+
+ @param NameGuid Pointer to a caller-allocated EFI_GUID. If a
+ matching file is found, the file's name is
+ returned in NameGuid. If no matching file is
+ found, *NameGuid is not modified.
+
+ @param Attributes Pointer to a caller-allocated
+ EFI_FV_FILE_ATTRIBUTES. If a matching file
+ is found, the file's attributes are returned
+ in Attributes. If no matching file is found,
+ Attributes is not modified. Type
+ EFI_FV_FILE_ATTRIBUTES is defined in
+ ReadFile().
+
+ @param Size Pointer to a caller-allocated UINTN. If a
+ matching file is found, the file's size is
+ returned in *Size. If no matching file is found,
+ Size is not modified.
+
+ @retval EFI_SUCCESS The output parameters are filled with data
+ obtained from the first matching file that
+ was found.
+
+ @retval FI_NOT_FOUND No files of type FileType were found.
+
+
+ @retval EFI_DEVICE_ERROR A hardware error occurred when
+ attempting to access the firmware
+ volume.
+
+ @retval EFI_ACCESS_DENIED The firmware volume is configured to
+ disallow reads.
+
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_FV_GET_NEXT_FILE)(
+ IN CONST EFI_FIRMWARE_VOLUME2_PROTOCOL *This,
+ IN OUT VOID *Key,
+ IN OUT EFI_FV_FILETYPE *FileType,
+ OUT EFI_GUID *NameGuid,
+ OUT EFI_FV_FILE_ATTRIBUTES *Attributes,
+ OUT UINTN *Size
+ );
+
+/**
+ Return information about a firmware volume.
+
+ The GetInfo() function returns information of type
+ InformationType for the requested firmware volume. If the volume
+ does not support the requested information type, then
+ EFI_UNSUPPORTED is returned. If the buffer is not large enough
+ to hold the requested structure, EFI_BUFFER_TOO_SMALL is
+ returned and the BufferSize is set to the size of buffer that is
+ required to make the request. The information types defined by
+ this specification are required information types that all file
+ systems must support.
+
+ @param This A pointer to the EFI_FIRMWARE_VOLUME2_PROTOCOL
+ instance that is the file handle the requested
+ information is for.
+
+ @param InformationType The type identifier for the
+ information being requested.
+
+ @param BufferSize On input, the size of Buffer. On output,
+ the amount of data returned in Buffer. In
+ both cases, the size is measured in bytes.
+
+ @param Buffer A pointer to the data buffer to return. The
+ buffer's type is indicated by InformationType.
+
+
+ @retval EFI_SUCCESS The information was retrieved.
+
+ @retval EFI_UNSUPPORTED The InformationType is not known.
+
+ @retval EFI_NO_MEDIA The device has no medium.
+
+ @retval EFI_DEVICE_ERROR The device reported an error.
+
+ @retval EFI_VOLUME_CORRUPTED The file system structures are
+ corrupted.
+
+ @retval EFI_BUFFER_TOO_SMALL The BufferSize is too small to
+ read the current directory
+ entry. BufferSize has been
+ updated with the size needed to
+ complete the request.
+
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_FV_GET_INFO)(
+ IN CONST EFI_FIRMWARE_VOLUME2_PROTOCOL *This,
+ IN CONST EFI_GUID *InformationType,
+ IN OUT UINTN *BufferSize,
+ OUT VOID *Buffer
+ );
+
+/**
+ Sets information about a firmware volume.
+
+ The SetInfo() function sets information of type InformationType
+ on the requested firmware volume.
+
+
+ @param This A pointer to the EFI_FIRMWARE_VOLUME2_PROTOCOL
+ instance that is the file handle the information
+ is for.
+
+ @param InformationType The type identifier for the
+ information being set.
+
+ @param BufferSize The size, in bytes, of Buffer.
+
+ @param Buffer A pointer to the data buffer to write. The
+ buffer's type is indicated by InformationType.
+
+ @retval EFI_SUCCESS The information was set.
+
+ @retval EFI_UNSUPPORTED The InformationType is not known.
+
+ @retval EFI_NO_MEDIA The device has no medium.
+
+ @retval EFI_DEVICE_ERROR The device reported an error.
+
+ @retval EFI_VOLUME_CORRUPTED The file system structures are
+ corrupted.
+
+
+ @retval EFI_WRITE_PROTECTED The media is read only.
+
+ @retval EFI_VOLUME_FULL The volume is full.
+
+ @retval EFI_BAD_BUFFER_SIZE BufferSize is smaller than the
+ size of the type indicated by
+ InformationType.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_FV_SET_INFO)(
+ IN CONST EFI_FIRMWARE_VOLUME2_PROTOCOL *This,
+ IN CONST EFI_GUID *InformationType,
+ IN UINTN BufferSize,
+ IN CONST VOID *Buffer
+ );
+
+///
+/// The Firmware Volume Protocol contains the file-level
+/// abstraction to the firmware volume as well as some firmware
+/// volume attribute reporting and configuration services. The
+/// Firmware Volume Protocol is the interface used by all parts of
+/// DXE that are not directly involved with managing the firmware
+/// volume itself. This abstraction allows many varied types of
+/// firmware volume implementations. A firmware volume may be a
+/// flash device or it may be a file in the UEFI system partition,
+/// for example. This level of firmware volume implementation
+/// detail is not visible to the consumers of the Firmware Volume
+/// Protocol.
+///
+struct _EFI_FIRMWARE_VOLUME2_PROTOCOL {
+ EFI_FV_GET_ATTRIBUTES GetVolumeAttributes;
+ EFI_FV_SET_ATTRIBUTES SetVolumeAttributes;
+ EFI_FV_READ_FILE ReadFile;
+ EFI_FV_READ_SECTION ReadSection;
+ EFI_FV_WRITE_FILE WriteFile;
+ EFI_FV_GET_NEXT_FILE GetNextFile;
+
+ ///
+ /// Data field that indicates the size in bytes
+ /// of the Key input buffer for the
+ /// GetNextFile() API.
+ ///
+ UINT32 KeySize;
+
+ ///
+ /// Handle of the parent firmware volume.
+ ///
+ EFI_HANDLE ParentHandle;
+ EFI_FV_GET_INFO GetInfo;
+ EFI_FV_SET_INFO SetInfo;
+};
+
+extern EFI_GUID gEfiFirmwareVolume2ProtocolGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/FirmwareVolumeBlock.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/FirmwareVolumeBlock.h
new file mode 100644
index 0000000000..5bf149ed98
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/FirmwareVolumeBlock.h
@@ -0,0 +1,352 @@
+/** @file
+ This file provides control over block-oriented firmware devices.
+
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Revision Reference: PI
+ Version 1.0 and 1.2.
+
+**/
+
+#ifndef __FIRMWARE_VOLUME_BLOCK_H__
+#define __FIRMWARE_VOLUME_BLOCK_H__
+
+//
+// EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL is defined in PI 1.0 spec and its GUID value
+// is later updated to be the same as that of EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL
+// defined in PI 1.2 spec.
+//
+#define EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL_GUID \
+ { 0x8f644fa9, 0xe850, 0x4db1, {0x9c, 0xe2, 0xb, 0x44, 0x69, 0x8e, 0x8d, 0xa4 } }
+
+#define EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL_GUID \
+ { 0x8f644fa9, 0xe850, 0x4db1, {0x9c, 0xe2, 0xb, 0x44, 0x69, 0x8e, 0x8d, 0xa4 } }
+
+typedef struct _EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL;
+
+typedef EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL;
+
+/**
+ The GetAttributes() function retrieves the attributes and
+ current settings of the block.
+
+ @param This Indicates the EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL instance.
+
+ @param Attributes Pointer to EFI_FVB_ATTRIBUTES_2 in which the
+ attributes and current settings are
+ returned. Type EFI_FVB_ATTRIBUTES_2 is defined
+ in EFI_FIRMWARE_VOLUME_HEADER.
+
+ @retval EFI_SUCCESS The firmware volume attributes were
+ returned.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_FVB_GET_ATTRIBUTES)(
+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
+ OUT EFI_FVB_ATTRIBUTES_2 *Attributes
+ );
+
+/**
+ The SetAttributes() function sets configurable firmware volume
+ attributes and returns the new settings of the firmware volume.
+
+ @param This Indicates the EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL instance.
+
+ @param Attributes On input, Attributes is a pointer to
+ EFI_FVB_ATTRIBUTES_2 that contains the
+ desired firmware volume settings. On
+ successful return, it contains the new
+ settings of the firmware volume. Type
+ EFI_FVB_ATTRIBUTES_2 is defined in
+ EFI_FIRMWARE_VOLUME_HEADER.
+
+ @retval EFI_SUCCESS The firmware volume attributes were returned.
+
+ @retval EFI_INVALID_PARAMETER The attributes requested are in
+ conflict with the capabilities
+ as declared in the firmware
+ volume header.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_FVB_SET_ATTRIBUTES)(
+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
+ IN OUT EFI_FVB_ATTRIBUTES_2 *Attributes
+ );
+
+/**
+ The GetPhysicalAddress() function retrieves the base address of
+ a memory-mapped firmware volume. This function should be called
+ only for memory-mapped firmware volumes.
+
+ @param This Indicates the EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL instance.
+
+ @param Address Pointer to a caller-allocated
+ EFI_PHYSICAL_ADDRESS that, on successful
+ return from GetPhysicalAddress(), contains the
+ base address of the firmware volume.
+
+ @retval EFI_SUCCESS The firmware volume base address was returned.
+
+ @retval EFI_UNSUPPORTED The firmware volume is not memory mapped.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_FVB_GET_PHYSICAL_ADDRESS)(
+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
+ OUT EFI_PHYSICAL_ADDRESS *Address
+ );
+
+/**
+ The GetBlockSize() function retrieves the size of the requested
+ block. It also returns the number of additional blocks with
+ the identical size. The GetBlockSize() function is used to
+ retrieve the block map (see EFI_FIRMWARE_VOLUME_HEADER).
+
+
+ @param This Indicates the EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL instance.
+
+ @param Lba Indicates the block for which to return the size.
+
+ @param BlockSize Pointer to a caller-allocated UINTN in which
+ the size of the block is returned.
+
+ @param NumberOfBlocks Pointer to a caller-allocated UINTN in
+ which the number of consecutive blocks,
+ starting with Lba, is returned. All
+ blocks in this range have a size of
+ BlockSize.
+
+
+ @retval EFI_SUCCESS The firmware volume base address was returned.
+
+ @retval EFI_INVALID_PARAMETER The requested LBA is out of range.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_FVB_GET_BLOCK_SIZE)(
+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
+ IN EFI_LBA Lba,
+ OUT UINTN *BlockSize,
+ OUT UINTN *NumberOfBlocks
+ );
+
+/**
+ Reads the specified number of bytes into a buffer from the specified block.
+
+ The Read() function reads the requested number of bytes from the
+ requested block and stores them in the provided buffer.
+ Implementations should be mindful that the firmware volume
+ might be in the ReadDisabled state. If it is in this state,
+ the Read() function must return the status code
+ EFI_ACCESS_DENIED without modifying the contents of the
+ buffer. The Read() function must also prevent spanning block
+ boundaries. If a read is requested that would span a block
+ boundary, the read must read up to the boundary but not
+ beyond. The output parameter NumBytes must be set to correctly
+ indicate the number of bytes actually read. The caller must be
+ aware that a read may be partially completed.
+
+ @param This Indicates the EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL instance.
+
+ @param Lba The starting logical block index
+ from which to read.
+
+ @param Offset Offset into the block at which to begin reading.
+
+ @param NumBytes Pointer to a UINTN. At entry, *NumBytes
+ contains the total size of the buffer. At
+ exit, *NumBytes contains the total number of
+ bytes read.
+
+ @param Buffer Pointer to a caller-allocated buffer that will
+ be used to hold the data that is read.
+
+ @retval EFI_SUCCESS The firmware volume was read successfully,
+ and contents are in Buffer.
+
+ @retval EFI_BAD_BUFFER_SIZE Read attempted across an LBA
+ boundary. On output, NumBytes
+ contains the total number of bytes
+ returned in Buffer.
+
+ @retval EFI_ACCESS_DENIED The firmware volume is in the
+ ReadDisabled state.
+
+ @retval EFI_DEVICE_ERROR The block device is not
+ functioning correctly and could
+ not be read.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_FVB_READ)(
+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
+ IN EFI_LBA Lba,
+ IN UINTN Offset,
+ IN OUT UINTN *NumBytes,
+ IN OUT UINT8 *Buffer
+ );
+
+/**
+ Writes the specified number of bytes from the input buffer to the block.
+
+ The Write() function writes the specified number of bytes from
+ the provided buffer to the specified block and offset. If the
+ firmware volume is sticky write, the caller must ensure that
+ all the bits of the specified range to write are in the
+ EFI_FVB_ERASE_POLARITY state before calling the Write()
+ function, or else the result will be unpredictable. This
+ unpredictability arises because, for a sticky-write firmware
+ volume, a write may negate a bit in the EFI_FVB_ERASE_POLARITY
+ state but cannot flip it back again. Before calling the
+ Write() function, it is recommended for the caller to first call
+ the EraseBlocks() function to erase the specified block to
+ write. A block erase cycle will transition bits from the
+ (NOT)EFI_FVB_ERASE_POLARITY state back to the
+ EFI_FVB_ERASE_POLARITY state. Implementations should be
+ mindful that the firmware volume might be in the WriteDisabled
+ state. If it is in this state, the Write() function must
+ return the status code EFI_ACCESS_DENIED without modifying the
+ contents of the firmware volume. The Write() function must
+ also prevent spanning block boundaries. If a write is
+ requested that spans a block boundary, the write must store up
+ to the boundary but not beyond. The output parameter NumBytes
+ must be set to correctly indicate the number of bytes actually
+ written. The caller must be aware that a write may be
+ partially completed. All writes, partial or otherwise, must be
+ fully flushed to the hardware before the Write() service
+ returns.
+
+ @param This Indicates the EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL instance.
+
+ @param Lba The starting logical block index to write to.
+
+ @param Offset Offset into the block at which to begin writing.
+
+ @param NumBytes The pointer to a UINTN. At entry, *NumBytes
+ contains the total size of the buffer. At
+ exit, *NumBytes contains the total number of
+ bytes actually written.
+
+ @param Buffer The pointer to a caller-allocated buffer that
+ contains the source for the write.
+
+ @retval EFI_SUCCESS The firmware volume was written successfully.
+
+ @retval EFI_BAD_BUFFER_SIZE The write was attempted across an
+ LBA boundary. On output, NumBytes
+ contains the total number of bytes
+ actually written.
+
+ @retval EFI_ACCESS_DENIED The firmware volume is in the
+ WriteDisabled state.
+
+ @retval EFI_DEVICE_ERROR The block device is malfunctioning
+ and could not be written.
+
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_FVB_WRITE)(
+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
+ IN EFI_LBA Lba,
+ IN UINTN Offset,
+ IN OUT UINTN *NumBytes,
+ IN UINT8 *Buffer
+ );
+
+///
+/// EFI_LBA_LIST_TERMINATOR
+///
+#define EFI_LBA_LIST_TERMINATOR 0xFFFFFFFFFFFFFFFFULL
+
+/**
+ Erases and initializes a firmware volume block.
+
+ The EraseBlocks() function erases one or more blocks as denoted
+ by the variable argument list. The entire parameter list of
+ blocks must be verified before erasing any blocks. If a block is
+ requested that does not exist within the associated firmware
+ volume (it has a larger index than the last block of the
+ firmware volume), the EraseBlocks() function must return the
+ status code EFI_INVALID_PARAMETER without modifying the contents
+ of the firmware volume. Implementations should be mindful that
+ the firmware volume might be in the WriteDisabled state. If it
+ is in this state, the EraseBlocks() function must return the
+ status code EFI_ACCESS_DENIED without modifying the contents of
+ the firmware volume. All calls to EraseBlocks() must be fully
+ flushed to the hardware before the EraseBlocks() service
+ returns.
+
+ @param This Indicates the EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL
+ instance.
+
+ @param ... The variable argument list is a list of tuples.
+ Each tuple describes a range of LBAs to erase
+ and consists of the following:
+ - An EFI_LBA that indicates the starting LBA
+ - A UINTN that indicates the number of blocks to
+ erase.
+
+ The list is terminated with an
+ EFI_LBA_LIST_TERMINATOR. For example, the
+ following indicates that two ranges of blocks
+ (5-7 and 10-11) are to be erased: EraseBlocks
+ (This, 5, 3, 10, 2, EFI_LBA_LIST_TERMINATOR);
+
+ @retval EFI_SUCCESS The erase request successfully
+ completed.
+
+ @retval EFI_ACCESS_DENIED The firmware volume is in the
+ WriteDisabled state.
+ @retval EFI_DEVICE_ERROR The block device is not functioning
+ correctly and could not be written.
+ The firmware device may have been
+ partially erased.
+ @retval EFI_INVALID_PARAMETER One or more of the LBAs listed
+ in the variable argument list do
+ not exist in the firmware volume.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_FVB_ERASE_BLOCKS)(
+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
+ ...
+ );
+
+///
+/// The Firmware Volume Block Protocol is the low-level interface
+/// to a firmware volume. File-level access to a firmware volume
+/// should not be done using the Firmware Volume Block Protocol.
+/// Normal access to a firmware volume must use the Firmware
+/// Volume Protocol. Typically, only the file system driver that
+/// produces the Firmware Volume Protocol will bind to the
+/// Firmware Volume Block Protocol.
+///
+struct _EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL {
+ EFI_FVB_GET_ATTRIBUTES GetAttributes;
+ EFI_FVB_SET_ATTRIBUTES SetAttributes;
+ EFI_FVB_GET_PHYSICAL_ADDRESS GetPhysicalAddress;
+ EFI_FVB_GET_BLOCK_SIZE GetBlockSize;
+ EFI_FVB_READ Read;
+ EFI_FVB_WRITE Write;
+ EFI_FVB_ERASE_BLOCKS EraseBlocks;
+ ///
+ /// The handle of the parent firmware volume.
+ ///
+ EFI_HANDLE ParentHandle;
+};
+
+extern EFI_GUID gEfiFirmwareVolumeBlockProtocolGuid;
+extern EFI_GUID gEfiFirmwareVolumeBlock2ProtocolGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/FormBrowser2.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/FormBrowser2.h
new file mode 100644
index 0000000000..7208e29f82
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/FormBrowser2.h
@@ -0,0 +1,168 @@
+/** @file
+ This protocol is defined in UEFI spec.
+
+ The EFI_FORM_BROWSER2_PROTOCOL is the interface to call for drivers to
+ leverage the EFI configuration driver interface.
+
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __EFI_FORM_BROWSER2_H__
+#define __EFI_FORM_BROWSER2_H__
+
+#include
+
+#define EFI_FORM_BROWSER2_PROTOCOL_GUID \
+ {0xb9d4c360, 0xbcfb, 0x4f9b, {0x92, 0x98, 0x53, 0xc1, 0x36, 0x98, 0x22, 0x58 }}
+
+typedef struct _EFI_FORM_BROWSER2_PROTOCOL EFI_FORM_BROWSER2_PROTOCOL;
+
+/**
+
+ @param LeftColumn The value that designates the text column
+ where the browser window will begin from
+ the left-hand side of the screen
+
+ @param RightColumn The value that designates the text
+ column where the browser window will end
+ on the right-hand side of the screen.
+
+ @param TopRow The value that designates the text row from the
+ top of the screen where the browser window
+ will start.
+
+ @param BottomRow The value that designates the text row from the
+ bottom of the screen where the browser
+ window will end.
+**/
+typedef struct {
+ UINTN LeftColumn;
+ UINTN RightColumn;
+ UINTN TopRow;
+ UINTN BottomRow;
+} EFI_SCREEN_DESCRIPTOR;
+
+typedef UINTN EFI_BROWSER_ACTION_REQUEST;
+
+#define EFI_BROWSER_ACTION_REQUEST_NONE 0
+#define EFI_BROWSER_ACTION_REQUEST_RESET 1
+#define EFI_BROWSER_ACTION_REQUEST_SUBMIT 2
+#define EFI_BROWSER_ACTION_REQUEST_EXIT 3
+#define EFI_BROWSER_ACTION_REQUEST_FORM_SUBMIT_EXIT 4
+#define EFI_BROWSER_ACTION_REQUEST_FORM_DISCARD_EXIT 5
+#define EFI_BROWSER_ACTION_REQUEST_FORM_APPLY 6
+#define EFI_BROWSER_ACTION_REQUEST_FORM_DISCARD 7
+#define EFI_BROWSER_ACTION_REQUEST_RECONNECT 8
+
+/**
+ Initialize the browser to display the specified configuration forms.
+
+ This function is the primary interface to the internal forms-based browser.
+ The forms browser will display forms associated with the specified Handles.
+ The browser will select all forms in packages which have the specified Type
+ and (for EFI_HII_PACKAGE_TYPE_GUID) the specified PackageGuid.
+
+ @param This A pointer to the EFI_FORM_BROWSER2_PROTOCOL instance
+
+ @param Handles A pointer to an array of Handles. This value should correspond
+ to the value of the HII form package that is required to be displayed.
+
+ @param HandleCount The number of Handles specified in Handle.
+
+ @param FormSetGuid This field points to the EFI_GUID which must match the Guid field or one of the
+ elements of the ClassId field in the EFI_IFR_FORM_SET op-code. If
+ FormsetGuid is NULL, then this function will display the form set class
+ EFI_HII_PLATFORM_SETUP_FORMSET_GUID.
+
+ @param FormId This field specifies the identifier of the form within the form set to render as the first
+ displayable page. If this field has a value of 0x0000, then the Forms Browser will
+ render the first enabled form in the form set.
+
+ @param ScreenDimensions Points to recommended form dimensions, including any non-content area, in
+ characters.
+
+ @param ActionRequest Points to the action recommended by the form.
+
+ @retval EFI_SUCCESS The function completed successfully
+
+ @retval EFI_NOT_FOUND The variable was not found.
+
+ @retval EFI_INVALID_PARAMETER One of the parameters has an
+ invalid value.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_SEND_FORM2)(
+ IN CONST EFI_FORM_BROWSER2_PROTOCOL *This,
+ IN EFI_HII_HANDLE *Handle,
+ IN UINTN HandleCount,
+ IN EFI_GUID *FormSetGuid OPTIONAL,
+ IN EFI_FORM_ID FormId OPTIONAL,
+ IN CONST EFI_SCREEN_DESCRIPTOR *ScreenDimensions OPTIONAL,
+ OUT EFI_BROWSER_ACTION_REQUEST *ActionRequest OPTIONAL
+ );
+
+/**
+ This function is called by a callback handler to retrieve uncommitted state data from the browser.
+
+ This routine is called by a routine which was called by the
+ browser. This routine called this service in the browser to
+ retrieve or set certain uncommitted state information.
+
+ @param This A pointer to the EFI_FORM_BROWSER2_PROTOCOL instance.
+
+ @param ResultsDataSize A pointer to the size of the buffer
+ associated with ResultsData. On input, the size in
+ bytes of ResultsData. On output, the size of data
+ returned in ResultsData.
+
+ @param ResultsData A string returned from an IFR browser or
+ equivalent. The results string will have
+ no routing information in them.
+
+ @param RetrieveData A BOOLEAN field which allows an agent to
+ retrieve (if RetrieveData = TRUE) data
+ from the uncommitted browser state
+ information or set (if RetrieveData =
+ FALSE) data in the uncommitted browser
+ state information.
+
+ @param VariableGuid An optional field to indicate the target
+ variable GUID name to use.
+
+ @param VariableName An optional field to indicate the target
+ human-readable variable name.
+
+ @retval EFI_SUCCESS The results have been distributed or are
+ awaiting distribution.
+
+ @retval EFI_OUT_OF_RESOURCES The ResultsDataSize specified
+ was too small to contain the
+ results data.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_BROWSER_CALLBACK2)(
+ IN CONST EFI_FORM_BROWSER2_PROTOCOL *This,
+ IN OUT UINTN *ResultsDataSize,
+ IN OUT EFI_STRING ResultsData,
+ IN CONST BOOLEAN RetrieveData,
+ IN CONST EFI_GUID *VariableGuid OPTIONAL,
+ IN CONST CHAR16 *VariableName OPTIONAL
+ );
+
+///
+/// This interface will allow the caller to direct the configuration
+/// driver to use either the HII database or use the passed-in packet of data.
+///
+struct _EFI_FORM_BROWSER2_PROTOCOL {
+ EFI_SEND_FORM2 SendForm;
+ EFI_BROWSER_CALLBACK2 BrowserCallback;
+};
+
+extern EFI_GUID gEfiFormBrowser2ProtocolGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/Ftp4.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/Ftp4.h
new file mode 100644
index 0000000000..2ad972c273
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/Ftp4.h
@@ -0,0 +1,515 @@
+/** @file
+ EFI FTPv4 (File Transfer Protocol version 4) Protocol Definition
+ The EFI FTPv4 Protocol is used to locate communication devices that are
+ supported by an EFI FTPv4 Protocol driver and to create and destroy instances
+ of the EFI FTPv4 Protocol child protocol driver that can use the underlying
+ communication device.
+ The definitions in this file are defined in UEFI Specification 2.3, which have
+ not been verified by one implementation yet.
+
+ Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Revision Reference:
+ This Protocol is introduced in UEFI Specification 2.2
+
+**/
+
+#ifndef __EFI_FTP4_PROTOCOL_H__
+#define __EFI_FTP4_PROTOCOL_H__
+
+#define EFI_FTP4_SERVICE_BINDING_PROTOCOL_GUID \
+ { \
+ 0xfaaecb1, 0x226e, 0x4782, {0xaa, 0xce, 0x7d, 0xb9, 0xbc, 0xbf, 0x4d, 0xaf } \
+ }
+
+#define EFI_FTP4_PROTOCOL_GUID \
+ { \
+ 0xeb338826, 0x681b, 0x4295, {0xb3, 0x56, 0x2b, 0x36, 0x4c, 0x75, 0x7b, 0x9 } \
+ }
+
+typedef struct _EFI_FTP4_PROTOCOL EFI_FTP4_PROTOCOL;
+
+///
+/// EFI_FTP4_CONNECTION_TOKEN
+///
+typedef struct {
+ ///
+ /// The Event to signal after the connection is established and Status field is updated
+ /// by the EFI FTP v4 Protocol driver. The type of Event must be
+ /// EVENT_NOTIFY_SIGNAL, and its Task Priority Level (TPL) must be lower than or
+ /// equal to TPL_CALLBACK. If it is set to NULL, this function will not return until the
+ /// function completes.
+ ///
+ EFI_EVENT Event;
+ ///
+ /// The variable to receive the result of the completed operation.
+ /// EFI_SUCCESS: The FTP connection is established successfully
+ /// EFI_ACCESS_DENIED: The FTP server denied the access the user's request to access it.
+ /// EFI_CONNECTION_RESET: The connect fails because the connection is reset either by instance
+ /// itself or communication peer.
+ /// EFI_TIMEOUT: The connection establishment timer expired and no more specific
+ /// information is available.
+ /// EFI_NETWORK_UNREACHABLE: The active open fails because an ICMP network unreachable error is
+ /// received.
+ /// EFI_HOST_UNREACHABLE: The active open fails because an ICMP host unreachable error is
+ /// received.
+ /// EFI_PROTOCOL_UNREACHABLE: The active open fails because an ICMP protocol unreachable error is
+ /// received.
+ /// EFI_PORT_UNREACHABLE: The connection establishment timer times out and an ICMP port
+ /// unreachable error is received.
+ /// EFI_ICMP_ERROR: The connection establishment timer timeout and some other ICMP
+ /// error is received.
+ /// EFI_DEVICE_ERROR: An unexpected system or network error occurred.
+ ///
+ EFI_STATUS Status;
+} EFI_FTP4_CONNECTION_TOKEN;
+
+///
+/// EFI_FTP4_CONFIG_DATA
+///
+typedef struct {
+ ///
+ /// Pointer to a ASCII string that contains user name. The caller is
+ /// responsible for freeing Username after GetModeData() is called.
+ ///
+ UINT8 *Username;
+ ///
+ /// Pointer to a ASCII string that contains password. The caller is
+ /// responsible for freeing Password after GetModeData() is called.
+ ///
+ UINT8 *Password;
+ ///
+ /// Set it to TRUE to initiate an active data connection. Set it to
+ /// FALSE to initiate a passive data connection.
+ ///
+ BOOLEAN Active;
+ ///
+ /// Boolean value indicating if default network settting used.
+ ///
+ BOOLEAN UseDefaultSetting;
+ ///
+ /// IP address of station if UseDefaultSetting is FALSE.
+ ///
+ EFI_IPv4_ADDRESS StationIp;
+ ///
+ /// Subnet mask of station if UseDefaultSetting is FALSE.
+ ///
+ EFI_IPv4_ADDRESS SubnetMask;
+ ///
+ /// IP address of gateway if UseDefaultSetting is FALSE.
+ ///
+ EFI_IPv4_ADDRESS GatewayIp;
+ ///
+ /// IP address of FTPv4 server.
+ ///
+ EFI_IPv4_ADDRESS ServerIp;
+ ///
+ /// FTPv4 server port number of control connection, and the default
+ /// value is 21 as convention.
+ ///
+ UINT16 ServerPort;
+ ///
+ /// FTPv4 server port number of data connection. If it is zero, use
+ /// (ServerPort - 1) by convention.
+ ///
+ UINT16 AltDataPort;
+ ///
+ /// A byte indicate the representation type. The right 4 bit is used for
+ /// first parameter, the left 4 bit is use for second parameter
+ /// - For the first parameter, 0x0 = image, 0x1 = EBCDIC, 0x2 = ASCII, 0x3 = local
+ /// - For the second parameter, 0x0 = Non-print, 0x1 = Telnet format effectors, 0x2 =
+ /// Carriage Control.
+ /// - If it is a local type, the second parameter is the local byte byte size.
+ /// - If it is a image type, the second parameter is undefined.
+ ///
+ UINT8 RepType;
+ ///
+ /// Defines the file structure in FTP used. 0x00 = file, 0x01 = record, 0x02 = page.
+ ///
+ UINT8 FileStruct;
+ ///
+ /// Defines the transifer mode used in FTP. 0x00 = stream, 0x01 = Block, 0x02 = Compressed.
+ ///
+ UINT8 TransMode;
+} EFI_FTP4_CONFIG_DATA;
+
+typedef struct _EFI_FTP4_COMMAND_TOKEN EFI_FTP4_COMMAND_TOKEN;
+
+/**
+ Callback function when process inbound or outbound data.
+
+ If it is receiving function that leads to inbound data, the callback function
+ is called when data buffer is full. Then, old data in the data buffer should be
+ flushed and new data is stored from the beginning of data buffer.
+ If it is a transmit function that lead to outbound data and the size of
+ Data in daata buffer has been transmitted, this callback function is called to
+ supply additional data to be transmitted.
+
+ @param[in] This Pointer to the EFI_FTP4_PROTOCOL instance.
+ @param[in] Token Pointer to the token structure to provide the parameters that
+ are used in this operation.
+ @return User defined Status.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_FTP4_DATA_CALLBACK)(
+ IN EFI_FTP4_PROTOCOL *This,
+ IN EFI_FTP4_COMMAND_TOKEN *Token
+ );
+
+///
+/// EFI_FTP4_COMMAND_TOKEN
+///
+struct _EFI_FTP4_COMMAND_TOKEN {
+ ///
+ /// The Event to signal after request is finished and Status field
+ /// is updated by the EFI FTP v4 Protocol driver. The type of Event
+ /// must be EVT_NOTIFY_SIGNAL, and its Task Priority Level
+ /// (TPL) must be lower than or equal to TPL_CALLBACK. If it is
+ /// set to NULL, related function must wait until the function
+ /// completes.
+ ///
+ EFI_EVENT Event;
+ ///
+ /// Pointer to a null-terminated ASCII name string.
+ ///
+ UINT8 *Pathname;
+ ///
+ /// The size of data buffer in bytes.
+ ///
+ UINT64 DataBufferSize;
+ ///
+ /// Pointer to the data buffer. Data downloaded from FTP server
+ /// through connection is downloaded here.
+ ///
+ VOID *DataBuffer;
+ ///
+ /// Pointer to a callback function. If it is receiving function that leads
+ /// to inbound data, the callback function is called when databuffer is
+ /// full. Then, old data in the data buffer should be flushed and new
+ /// data is stored from the beginning of data buffer. If it is a transmit
+ /// function that lead to outbound data and DataBufferSize of
+ /// Data in DataBuffer has been transmitted, this callback
+ /// function is called to supply additional data to be transmitted. The
+ /// size of additional data to be transmitted is indicated in
+ /// DataBufferSize, again. If there is no data remained,
+ /// DataBufferSize should be set to 0.
+ ///
+ EFI_FTP4_DATA_CALLBACK DataCallback;
+ ///
+ /// Pointer to the parameter for DataCallback.
+ ///
+ VOID *Context;
+ ///
+ /// The variable to receive the result of the completed operation.
+ /// EFI_SUCCESS: The FTP command is completed successfully.
+ /// EFI_ACCESS_DENIED: The FTP server denied the access to the requested file.
+ /// EFI_CONNECTION_RESET: The connect fails because the connection is reset either
+ /// by instance itself or communication peer.
+ /// EFI_TIMEOUT: The connection establishment timer expired and no more
+ /// specific information is available.
+ /// EFI_NETWORK_UNREACHABLE: The active open fails because an ICMP network unreachable
+ /// error is received.
+ /// EFI_HOST_UNREACHABLE: The active open fails because an ICMP host unreachable
+ /// error is received.
+ /// EFI_PROTOCOL_UNREACHABLE: The active open fails because an ICMP protocol unreachable
+ /// error is received.
+ /// EFI_PORT_UNREACHABLE: The connection establishment timer times out and an ICMP port
+ /// unreachable error is received.
+ /// EFI_ICMP_ERROR: The connection establishment timer timeout and some other ICMP
+ /// error is received.
+ /// EFI_DEVICE_ERROR: An unexpected system or network error occurred.
+ ///
+ EFI_STATUS Status;
+};
+
+/**
+ Gets the current operational settings.
+
+ The GetModeData() function reads the current operational settings of this
+ EFI FTPv4 Protocol driver instance. EFI_FTP4_CONFIG_DATA is defined in the
+ EFI_FTP4_PROTOCOL.Configure.
+
+ @param[in] This Pointer to the EFI_FTP4_PROTOCOL instance.
+ @param[out] ModeData Pointer to storage for the EFI FTPv4 Protocol driver
+ mode data. The string buffers for Username and Password
+ in EFI_FTP4_CONFIG_DATA are allocated by the function,
+ and the caller should take the responsibility to free the
+ buffer later.
+
+ @retval EFI_SUCCESS This function is called successfully.
+ @retval EFI_INVALID_PARAMETER One or more of the following are TRUE:
+ - This is NULL.
+ - ModeData is NULL.
+ @retval EFI_NOT_STARTED The EFI FTPv4 Protocol driver has not been started
+ @retval EFI_OUT_OF_RESOURCES Could not allocate enough resource to finish the operation.
+ @retval EFI_DEVICE_ERROR An unexpected system or network error occurred.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_FTP4_GET_MODE_DATA)(
+ IN EFI_FTP4_PROTOCOL *This,
+ OUT EFI_FTP4_CONFIG_DATA *ModeData
+ );
+
+/**
+ Disconnecting a FTP connection gracefully.
+
+ The Connect() function will initiate a connection request to the remote FTP server
+ with the corresponding connection token. If this function returns EFI_SUCCESS, the
+ connection sequence is initiated successfully. If the connection succeeds or faild
+ due to any error, the Token->Event will be signaled and Token->Status will be updated
+ accordingly.
+
+ @param[in] This Pointer to the EFI_FTP4_PROTOCOL instance.
+ @param[in] Token Pointer to the token used to establish control connection.
+
+ @retval EFI_SUCCESS The connection sequence is successfully initiated.
+ @retval EFI_INVALID_PARAMETER One or more of the following are TRUE:
+ - This is NULL.
+ - Token is NULL.
+ - Token->Event is NULL.
+ @retval EFI_NOT_STARTED The EFI FTPv4 Protocol driver has not been started.
+ @retval EFI_NO_MAPPING When using a default address, configuration (DHCP, BOOTP,
+ RARP, etc.) is not finished yet.
+ @retval EFI_OUT_OF_RESOURCES Could not allocate enough resource to finish the operation.
+ @retval EFI_DEVICE_ERROR An unexpected system or network error occurred.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_FTP4_CONNECT)(
+ IN EFI_FTP4_PROTOCOL *This,
+ IN EFI_FTP4_CONNECTION_TOKEN *Token
+ );
+
+/**
+ Disconnecting a FTP connection gracefully.
+
+ The Close() function will initiate a close request to the remote FTP server with the
+ corresponding connection token. If this function returns EFI_SUCCESS, the control
+ connection with the remote FTP server is closed.
+
+ @param[in] This Pointer to the EFI_FTP4_PROTOCOL instance.
+ @param[in] Token Pointer to the token used to close control connection.
+
+ @retval EFI_SUCCESS The close request is successfully initiated.
+ @retval EFI_INVALID_PARAMETER One or more of the following are TRUE:
+ - This is NULL.
+ - Token is NULL.
+ - Token->Event is NULL.
+ @retval EFI_NOT_STARTED The EFI FTPv4 Protocol driver has not been started.
+ @retval EFI_NO_MAPPING When using a default address, configuration (DHCP, BOOTP,
+ RARP, etc.) is not finished yet.
+ @retval EFI_OUT_OF_RESOURCES Could not allocate enough resource to finish the operation.
+ @retval EFI_DEVICE_ERROR An unexpected system or network error occurred.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_FTP4_CLOSE)(
+ IN EFI_FTP4_PROTOCOL *This,
+ IN EFI_FTP4_CONNECTION_TOKEN *Token
+ );
+
+/**
+ Sets or clears the operational parameters for the FTP child driver.
+
+ The Configure() function will configure the connected FTP session with the
+ configuration setting specified in FtpConfigData. The configuration data can
+ be reset by calling Configure() with FtpConfigData set to NULL.
+
+ @param[in] This Pointer to the EFI_FTP4_PROTOCOL instance.
+ @param[in] FtpConfigData Pointer to configuration data that will be assigned to
+ the FTP child driver instance. If NULL, the FTP child
+ driver instance is reset to startup defaults and all
+ pending transmit and receive requests are flushed.
+
+ @retval EFI_SUCCESS The FTPv4 driver was configured successfully.
+ @retval EFI_INVALID_PARAMETER One or more following conditions are TRUE:
+ - This is NULL.
+ - FtpConfigData.RepType is invalid.
+ - FtpConfigData.FileStruct is invalid.
+ - FtpConfigData.TransMode is invalid.
+ - IP address in FtpConfigData is invalid.
+ @retval EFI_NO_MAPPING When using a default address, configuration (DHCP, BOOTP,
+ RARP, etc.) is not finished yet.
+ @retval EFI_UNSUPPORTED One or more of the configuration parameters are not supported
+ by this implementation.
+ @retval EFI_OUT_OF_RESOURCES The EFI FTPv4 Protocol driver instance data could not be
+ allocated.
+ @retval EFI_DEVICE_ERROR An unexpected system or network error occurred. The EFI FTPv4
+ Protocol driver instance is not configured.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_FTP4_CONFIGURE)(
+ IN EFI_FTP4_PROTOCOL *This,
+ IN EFI_FTP4_CONFIG_DATA *FtpConfigData OPTIONAL
+ );
+
+/**
+ Downloads a file from an FTPv4 server.
+
+ The ReadFile() function is used to initialize and start an FTPv4 download process
+ and optionally wait for completion. When the download operation completes, whether
+ successfully or not, the Token.Status field is updated by the EFI FTPv4 Protocol
+ driver and then Token.Event is signaled (if it is not NULL).
+
+ Data will be downloaded from the FTPv4 server into Token.DataBuffer. If the file size
+ is larger than Token.DataBufferSize, Token.DataCallback will be called to allow for
+ processing data and then new data will be placed at the beginning of Token.DataBuffer.
+
+ @param[in] This Pointer to the EFI_FTP4_PROTOCOL instance.
+ @param[in] Token Pointer to the token structure to provide the parameters that
+ are used in this operation.
+
+ @retval EFI_SUCCESS The data file is being downloaded successfully.
+ @retval EFI_INVALID_PARAMETER One or more of the parameters is not valid.
+ - This is NULL.
+ - Token is NULL.
+ - Token.Pathname is NULL.
+ - Token. DataBuffer is NULL.
+ - Token. DataBufferSize is 0.
+ @retval EFI_NOT_STARTED The EFI FTPv4 Protocol driver has not been started.
+ @retval EFI_NO_MAPPING When using a default address, configuration (DHCP, BOOTP,
+ RARP, etc.) is not finished yet.
+ @retval EFI_OUT_OF_RESOURCES Required system resources could not be allocated.
+ @retval EFI_DEVICE_ERROR An unexpected network error or system error occurred.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_FTP4_READ_FILE)(
+ IN EFI_FTP4_PROTOCOL *This,
+ IN EFI_FTP4_COMMAND_TOKEN *Token
+ );
+
+/**
+ Uploads a file from an FTPv4 server.
+
+ The WriteFile() function is used to initialize and start an FTPv4 upload process and
+ optionally wait for completion. When the upload operation completes, whether successfully
+ or not, the Token.Status field is updated by the EFI FTPv4 Protocol driver and then
+ Token.Event is signaled (if it is not NULL). Data to be uploaded to server is stored
+ into Token.DataBuffer. Token.DataBufferSize is the number bytes to be transferred.
+ If the file size is larger than Token.DataBufferSize, Token.DataCallback will be called
+ to allow for processing data and then new data will be placed at the beginning of
+ Token.DataBuffer. Token.DataBufferSize is updated to reflect the actual number of bytes
+ to be transferred. Token.DataBufferSize is set to 0 by the call back to indicate the
+ completion of data transfer.
+
+ @param[in] This Pointer to the EFI_FTP4_PROTOCOL instance.
+ @param[in] Token Pointer to the token structure to provide the parameters that
+ are used in this operation.
+
+ @retval EFI_SUCCESS TThe data file is being uploaded successfully.
+ @retval EFI_UNSUPPORTED The operation is not supported by this implementation.
+ @retval EFI_INVALID_PARAMETER One or more of the parameters is not valid.
+ - This is NULL.
+ - Token is NULL.
+ - Token.Pathname is NULL.
+ - Token. DataBuffer is NULL.
+ - Token. DataBufferSize is 0.
+ @retval EFI_NOT_STARTED The EFI FTPv4 Protocol driver has not been started.
+ @retval EFI_NO_MAPPING When using a default address, configuration (DHCP, BOOTP,
+ RARP, etc.) is not finished yet.
+ @retval EFI_OUT_OF_RESOURCES Required system resources could not be allocated.
+ @retval EFI_DEVICE_ERROR An unexpected network error or system error occurred.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_FTP4_WRITE_FILE)(
+ IN EFI_FTP4_PROTOCOL *This,
+ IN EFI_FTP4_COMMAND_TOKEN *Token
+ );
+
+/**
+ Download a data file "directory" from a FTPv4 server. May be unsupported in some EFI
+ implementations.
+
+ The ReadDirectory() function is used to return a list of files on the FTPv4 server that
+ logically (or operationally) related to Token.Pathname, and optionally wait for completion.
+ When the download operation completes, whether successfully or not, the Token.Status field
+ is updated by the EFI FTPv4 Protocol driver and then Token.Event is signaled (if it is not
+ NULL). Data will be downloaded from the FTPv4 server into Token.DataBuffer. If the file size
+ is larger than Token.DataBufferSize, Token.DataCallback will be called to allow for processing
+ data and then new data will be placed at the beginning of Token.DataBuffer.
+
+ @param[in] This Pointer to the EFI_FTP4_PROTOCOL instance.
+ @param[in] Token Pointer to the token structure to provide the parameters that
+ are used in this operation.
+
+ @retval EFI_SUCCESS The file list information is being downloaded successfully.
+ @retval EFI_UNSUPPORTED The operation is not supported by this implementation.
+ @retval EFI_INVALID_PARAMETER One or more of the parameters is not valid.
+ - This is NULL.
+ - Token is NULL.
+ - Token. DataBuffer is NULL.
+ - Token. DataBufferSize is 0.
+ @retval EFI_NOT_STARTED The EFI FTPv4 Protocol driver has not been started.
+ @retval EFI_NO_MAPPING When using a default address, configuration (DHCP, BOOTP,
+ RARP, etc.) is not finished yet.
+ @retval EFI_OUT_OF_RESOURCES Required system resources could not be allocated.
+ @retval EFI_DEVICE_ERROR An unexpected network error or system error occurred.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_FTP4_READ_DIRECTORY)(
+ IN EFI_FTP4_PROTOCOL *This,
+ IN EFI_FTP4_COMMAND_TOKEN *Token
+ );
+
+/**
+ Polls for incoming data packets and processes outgoing data packets.
+
+ The Poll() function can be used by network drivers and applications to increase the
+ rate that data packets are moved between the communications device and the transmit
+ and receive queues. In some systems, the periodic timer event in the managed network
+ driver may not poll the underlying communications device fast enough to transmit
+ and/or receive all data packets without missing incoming packets or dropping outgoing
+ packets. Drivers and applications that are experiencing packet loss should try calling
+ the Poll() function more often.
+
+ @param[in] This Pointer to the EFI_FTP4_PROTOCOL instance.
+
+ @retval EFI_SUCCESS Incoming or outgoing data was processed.
+ @retval EFI_NOT_STARTED This EFI FTPv4 Protocol instance has not been started.
+ @retval EFI_INVALID_PARAMETER This is NULL.
+ @retval EFI_DEVICE_ERROR EapAuthType An unexpected system or network error occurred.
+ @retval EFI_TIMEOUT Data was dropped out of the transmit and/or receive queue.
+ Consider increasing the polling rate.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_FTP4_POLL)(
+ IN EFI_FTP4_PROTOCOL *This
+ );
+
+///
+/// EFI_FTP4_PROTOCOL
+/// provides basic services for client-side FTP (File Transfer Protocol)
+/// operations.
+///
+struct _EFI_FTP4_PROTOCOL {
+ EFI_FTP4_GET_MODE_DATA GetModeData;
+ EFI_FTP4_CONNECT Connect;
+ EFI_FTP4_CLOSE Close;
+ EFI_FTP4_CONFIGURE Configure;
+ EFI_FTP4_READ_FILE ReadFile;
+ EFI_FTP4_WRITE_FILE WriteFile;
+ EFI_FTP4_READ_DIRECTORY ReadDirectory;
+ EFI_FTP4_POLL Poll;
+};
+
+extern EFI_GUID gEfiFtp4ServiceBindingProtocolGuid;
+extern EFI_GUID gEfiFtp4ProtocolGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/GraphicsOutput.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/GraphicsOutput.h
new file mode 100644
index 0000000000..edd5495e56
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/GraphicsOutput.h
@@ -0,0 +1,270 @@
+/** @file
+ Graphics Output Protocol from the UEFI 2.0 specification.
+
+ Abstraction of a very simple graphics device.
+
+ Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __GRAPHICS_OUTPUT_H__
+#define __GRAPHICS_OUTPUT_H__
+
+#define EFI_GRAPHICS_OUTPUT_PROTOCOL_GUID \
+ { \
+ 0x9042a9de, 0x23dc, 0x4a38, {0x96, 0xfb, 0x7a, 0xde, 0xd0, 0x80, 0x51, 0x6a } \
+ }
+
+typedef struct _EFI_GRAPHICS_OUTPUT_PROTOCOL EFI_GRAPHICS_OUTPUT_PROTOCOL;
+
+typedef struct {
+ UINT32 RedMask;
+ UINT32 GreenMask;
+ UINT32 BlueMask;
+ UINT32 ReservedMask;
+} EFI_PIXEL_BITMASK;
+
+typedef enum {
+ ///
+ /// A pixel is 32-bits and byte zero represents red, byte one represents green,
+ /// byte two represents blue, and byte three is reserved. This is the definition
+ /// for the physical frame buffer. The byte values for the red, green, and blue
+ /// components represent the color intensity. This color intensity value range
+ /// from a minimum intensity of 0 to maximum intensity of 255.
+ ///
+ PixelRedGreenBlueReserved8BitPerColor,
+ ///
+ /// A pixel is 32-bits and byte zero represents blue, byte one represents green,
+ /// byte two represents red, and byte three is reserved. This is the definition
+ /// for the physical frame buffer. The byte values for the red, green, and blue
+ /// components represent the color intensity. This color intensity value range
+ /// from a minimum intensity of 0 to maximum intensity of 255.
+ ///
+ PixelBlueGreenRedReserved8BitPerColor,
+ ///
+ /// The Pixel definition of the physical frame buffer.
+ ///
+ PixelBitMask,
+ ///
+ /// This mode does not support a physical frame buffer.
+ ///
+ PixelBltOnly,
+ ///
+ /// Valid EFI_GRAPHICS_PIXEL_FORMAT enum values are less than this value.
+ ///
+ PixelFormatMax
+} EFI_GRAPHICS_PIXEL_FORMAT;
+
+typedef struct {
+ ///
+ /// The version of this data structure. A value of zero represents the
+ /// EFI_GRAPHICS_OUTPUT_MODE_INFORMATION structure as defined in this specification.
+ ///
+ UINT32 Version;
+ ///
+ /// The size of video screen in pixels in the X dimension.
+ ///
+ UINT32 HorizontalResolution;
+ ///
+ /// The size of video screen in pixels in the Y dimension.
+ ///
+ UINT32 VerticalResolution;
+ ///
+ /// Enumeration that defines the physical format of the pixel. A value of PixelBltOnly
+ /// implies that a linear frame buffer is not available for this mode.
+ ///
+ EFI_GRAPHICS_PIXEL_FORMAT PixelFormat;
+ ///
+ /// This bit-mask is only valid if PixelFormat is set to PixelPixelBitMask.
+ /// A bit being set defines what bits are used for what purpose such as Red, Green, Blue, or Reserved.
+ ///
+ EFI_PIXEL_BITMASK PixelInformation;
+ ///
+ /// Defines the number of pixel elements per video memory line.
+ ///
+ UINT32 PixelsPerScanLine;
+} EFI_GRAPHICS_OUTPUT_MODE_INFORMATION;
+
+/**
+ Returns information for an available graphics mode that the graphics device
+ and the set of active video output devices supports.
+
+ @param This The EFI_GRAPHICS_OUTPUT_PROTOCOL instance.
+ @param ModeNumber The mode number to return information on.
+ @param SizeOfInfo A pointer to the size, in bytes, of the Info buffer.
+ @param Info A pointer to callee allocated buffer that returns information about ModeNumber.
+
+ @retval EFI_SUCCESS Valid mode information was returned.
+ @retval EFI_DEVICE_ERROR A hardware error occurred trying to retrieve the video mode.
+ @retval EFI_INVALID_PARAMETER ModeNumber is not valid.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_GRAPHICS_OUTPUT_PROTOCOL_QUERY_MODE)(
+ IN EFI_GRAPHICS_OUTPUT_PROTOCOL *This,
+ IN UINT32 ModeNumber,
+ OUT UINTN *SizeOfInfo,
+ OUT EFI_GRAPHICS_OUTPUT_MODE_INFORMATION **Info
+ );
+
+/**
+ Set the video device into the specified mode and clears the visible portions of
+ the output display to black.
+
+ @param This The EFI_GRAPHICS_OUTPUT_PROTOCOL instance.
+ @param ModeNumber Abstraction that defines the current video mode.
+
+ @retval EFI_SUCCESS The graphics mode specified by ModeNumber was selected.
+ @retval EFI_DEVICE_ERROR The device had an error and could not complete the request.
+ @retval EFI_UNSUPPORTED ModeNumber is not supported by this device.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_GRAPHICS_OUTPUT_PROTOCOL_SET_MODE)(
+ IN EFI_GRAPHICS_OUTPUT_PROTOCOL *This,
+ IN UINT32 ModeNumber
+ );
+
+typedef struct {
+ UINT8 Blue;
+ UINT8 Green;
+ UINT8 Red;
+ UINT8 Reserved;
+} EFI_GRAPHICS_OUTPUT_BLT_PIXEL;
+
+typedef union {
+ EFI_GRAPHICS_OUTPUT_BLT_PIXEL Pixel;
+ UINT32 Raw;
+} EFI_GRAPHICS_OUTPUT_BLT_PIXEL_UNION;
+
+///
+/// actions for BltOperations
+///
+typedef enum {
+ ///
+ /// Write data from the BltBuffer pixel (0, 0)
+ /// directly to every pixel of the video display rectangle
+ /// (DestinationX, DestinationY) (DestinationX + Width, DestinationY + Height).
+ /// Only one pixel will be used from the BltBuffer. Delta is NOT used.
+ ///
+ EfiBltVideoFill,
+
+ ///
+ /// Read data from the video display rectangle
+ /// (SourceX, SourceY) (SourceX + Width, SourceY + Height) and place it in
+ /// the BltBuffer rectangle (DestinationX, DestinationY )
+ /// (DestinationX + Width, DestinationY + Height). If DestinationX or
+ /// DestinationY is not zero then Delta must be set to the length in bytes
+ /// of a row in the BltBuffer.
+ ///
+ EfiBltVideoToBltBuffer,
+
+ ///
+ /// Write data from the BltBuffer rectangle
+ /// (SourceX, SourceY) (SourceX + Width, SourceY + Height) directly to the
+ /// video display rectangle (DestinationX, DestinationY)
+ /// (DestinationX + Width, DestinationY + Height). If SourceX or SourceY is
+ /// not zero then Delta must be set to the length in bytes of a row in the
+ /// BltBuffer.
+ ///
+ EfiBltBufferToVideo,
+
+ ///
+ /// Copy from the video display rectangle (SourceX, SourceY)
+ /// (SourceX + Width, SourceY + Height) to the video display rectangle
+ /// (DestinationX, DestinationY) (DestinationX + Width, DestinationY + Height).
+ /// The BltBuffer and Delta are not used in this mode.
+ ///
+ EfiBltVideoToVideo,
+
+ EfiGraphicsOutputBltOperationMax
+} EFI_GRAPHICS_OUTPUT_BLT_OPERATION;
+
+/**
+ Blt a rectangle of pixels on the graphics screen. Blt stands for BLock Transfer.
+
+ @param This Protocol instance pointer.
+ @param BltBuffer The data to transfer to the graphics screen.
+ Size is at least Width*Height*sizeof(EFI_GRAPHICS_OUTPUT_BLT_PIXEL).
+ @param BltOperation The operation to perform when copying BltBuffer on to the graphics screen.
+ @param SourceX The X coordinate of source for the BltOperation.
+ @param SourceY The Y coordinate of source for the BltOperation.
+ @param DestinationX The X coordinate of destination for the BltOperation.
+ @param DestinationY The Y coordinate of destination for the BltOperation.
+ @param Width The width of a rectangle in the blt rectangle in pixels.
+ @param Height The height of a rectangle in the blt rectangle in pixels.
+ @param Delta Not used for EfiBltVideoFill or the EfiBltVideoToVideo operation.
+ If a Delta of zero is used, the entire BltBuffer is being operated on.
+ If a subrectangle of the BltBuffer is being used then Delta
+ represents the number of bytes in a row of the BltBuffer.
+
+ @retval EFI_SUCCESS BltBuffer was drawn to the graphics screen.
+ @retval EFI_INVALID_PARAMETER BltOperation is not valid.
+ @retval EFI_DEVICE_ERROR The device had an error and could not complete the request.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_GRAPHICS_OUTPUT_PROTOCOL_BLT)(
+ IN EFI_GRAPHICS_OUTPUT_PROTOCOL *This,
+ IN EFI_GRAPHICS_OUTPUT_BLT_PIXEL *BltBuffer OPTIONAL,
+ IN EFI_GRAPHICS_OUTPUT_BLT_OPERATION BltOperation,
+ IN UINTN SourceX,
+ IN UINTN SourceY,
+ IN UINTN DestinationX,
+ IN UINTN DestinationY,
+ IN UINTN Width,
+ IN UINTN Height,
+ IN UINTN Delta OPTIONAL
+ );
+
+typedef struct {
+ ///
+ /// The number of modes supported by QueryMode() and SetMode().
+ ///
+ UINT32 MaxMode;
+ ///
+ /// Current Mode of the graphics device. Valid mode numbers are 0 to MaxMode -1.
+ ///
+ UINT32 Mode;
+ ///
+ /// Pointer to read-only EFI_GRAPHICS_OUTPUT_MODE_INFORMATION data.
+ ///
+ EFI_GRAPHICS_OUTPUT_MODE_INFORMATION *Info;
+ ///
+ /// Size of Info structure in bytes.
+ ///
+ UINTN SizeOfInfo;
+ ///
+ /// Base address of graphics linear frame buffer.
+ /// Offset zero in FrameBufferBase represents the upper left pixel of the display.
+ ///
+ EFI_PHYSICAL_ADDRESS FrameBufferBase;
+ ///
+ /// Amount of frame buffer needed to support the active mode as defined by
+ /// PixelsPerScanLine xVerticalResolution x PixelElementSize.
+ ///
+ UINTN FrameBufferSize;
+} EFI_GRAPHICS_OUTPUT_PROTOCOL_MODE;
+
+///
+/// Provides a basic abstraction to set video modes and copy pixels to and from
+/// the graphics controller's frame buffer. The linear address of the hardware
+/// frame buffer is also exposed so software can write directly to the video hardware.
+///
+struct _EFI_GRAPHICS_OUTPUT_PROTOCOL {
+ EFI_GRAPHICS_OUTPUT_PROTOCOL_QUERY_MODE QueryMode;
+ EFI_GRAPHICS_OUTPUT_PROTOCOL_SET_MODE SetMode;
+ EFI_GRAPHICS_OUTPUT_PROTOCOL_BLT Blt;
+ ///
+ /// Pointer to EFI_GRAPHICS_OUTPUT_PROTOCOL_MODE data.
+ ///
+ EFI_GRAPHICS_OUTPUT_PROTOCOL_MODE *Mode;
+};
+
+extern EFI_GUID gEfiGraphicsOutputProtocolGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/GuidedSectionExtraction.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/GuidedSectionExtraction.h
new file mode 100644
index 0000000000..d6035239b2
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/GuidedSectionExtraction.h
@@ -0,0 +1,132 @@
+/** @file
+ If a GUID-defined section is encountered when doing section
+ extraction, the section extraction driver calls the appropriate
+ instance of the GUIDed Section Extraction Protocol to extract
+ the section stream contained therein.
+
+ Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Revision Reference: PI
+ Version 1.00.
+
+**/
+
+#ifndef __GUID_SECTION_EXTRACTION_PROTOCOL_H__
+#define __GUID_SECTION_EXTRACTION_PROTOCOL_H__
+
+//
+// The protocol interface structures are identified by associating
+// them with a GUID. Each instance of a protocol with a given
+// GUID must have the same interface structure. While all instances
+// of the GUIDed Section Extraction Protocol must have the same
+// interface structure, they do not all have the same GUID. The
+// GUID that is associated with an instance of the GUIDed Section
+// Extraction Protocol is used to correlate it with the GUIDed
+// section type that it is intended to process.
+//
+
+typedef struct _EFI_GUIDED_SECTION_EXTRACTION_PROTOCOL EFI_GUIDED_SECTION_EXTRACTION_PROTOCOL;
+
+/**
+ The ExtractSection() function processes the input section and
+ allocates a buffer from the pool in which it returns the section
+ contents. If the section being extracted contains
+ authentication information (the section's
+ GuidedSectionHeader.Attributes field has the
+ EFI_GUIDED_SECTION_AUTH_STATUS_VALID bit set), the values
+ returned in AuthenticationStatus must reflect the results of
+ the authentication operation. Depending on the algorithm and
+ size of the encapsulated data, the time that is required to do
+ a full authentication may be prohibitively long for some
+ classes of systems. To indicate this, use
+ EFI_SECURITY_POLICY_PROTOCOL_GUID, which may be published by
+ the security policy driver (see the Platform Initialization
+ Driver Execution Environment Core Interface Specification for
+ more details and the GUID definition). If the
+ EFI_SECURITY_POLICY_PROTOCOL_GUID exists in the handle
+ database, then, if possible, full authentication should be
+ skipped and the section contents simply returned in the
+ OutputBuffer. In this case, the
+ EFI_AUTH_STATUS_PLATFORM_OVERRIDE bit AuthenticationStatus
+ must be set on return. ExtractSection() is callable only from
+ TPL_NOTIFY and below. Behavior of ExtractSection() at any
+ EFI_TPL above TPL_NOTIFY is undefined. Type EFI_TPL is
+ defined in RaiseTPL() in the UEFI 2.0 specification.
+
+
+ @param This Indicates the EFI_GUIDED_SECTION_EXTRACTION_PROTOCOL instance.
+
+ @param InputSection Buffer containing the input GUIDed section
+ to be processed. OutputBuffer OutputBuffer
+ is allocated from boot services pool
+ memory and contains the new section
+ stream. The caller is responsible for
+ freeing this buffer.
+
+ @param OutputSize A pointer to a caller-allocated UINTN in
+ which the size of OutputBuffer allocation
+ is stored. If the function returns
+ anything other than EFI_SUCCESS, the value
+ of OutputSize is undefined.
+
+ @param AuthenticationStatus A pointer to a caller-allocated
+ UINT32 that indicates the
+ authentication status of the
+ output buffer. If the input
+ section's
+ GuidedSectionHeader.Attributes
+ field has the
+ EFI_GUIDED_SECTION_AUTH_STATUS_VAL
+ bit as clear, AuthenticationStatus
+ must return zero. Both local bits
+ (19:16) and aggregate bits (3:0)
+ in AuthenticationStatus are
+ returned by ExtractSection().
+ These bits reflect the status of
+ the extraction operation. The bit
+ pattern in both regions must be
+ the same, as the local and
+ aggregate authentication statuses
+ have equivalent meaning at this
+ level. If the function returns
+ anything other than EFI_SUCCESS,
+ the value of AuthenticationStatus
+ is undefined.
+
+ @retval EFI_SUCCESS The InputSection was successfully
+ processed and the section contents were
+ returned.
+
+ @retval EFI_OUT_OF_RESOURCES The system has insufficient
+ resources to process the
+ request.
+
+ @retval EFI_INVALID_PARAMETER The GUID in InputSection does
+ not match this instance of the
+ GUIDed Section Extraction
+ Protocol.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_EXTRACT_GUIDED_SECTION)(
+ IN CONST EFI_GUIDED_SECTION_EXTRACTION_PROTOCOL *This,
+ IN CONST VOID *InputSection,
+ OUT VOID **OutputBuffer,
+ OUT UINTN *OutputSize,
+ OUT UINT32 *AuthenticationStatus
+ );
+
+///
+/// Typically, protocol interface structures are identified by associating them with a GUID. Each
+/// instance of a protocol with a given GUID must have the same interface structure. While all instances
+/// of the GUIDed Section Extraction Protocol must have the same interface structure, they do not all
+/// have the same GUID. The GUID that is associated with an instance of the GUIDed Section
+/// Extraction Protocol is used to correlate it with the GUIDed section type that it is intended to process.
+///
+struct _EFI_GUIDED_SECTION_EXTRACTION_PROTOCOL {
+ EFI_EXTRACT_GUIDED_SECTION ExtractSection;
+};
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/Hash.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/Hash.h
new file mode 100644
index 0000000000..cc6ee16af4
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/Hash.h
@@ -0,0 +1,169 @@
+/** @file
+ EFI_HASH_SERVICE_BINDING_PROTOCOL as defined in UEFI 2.0.
+ EFI_HASH_PROTOCOL as defined in UEFI 2.0.
+ The EFI Hash Service Binding Protocol is used to locate hashing services support
+ provided by a driver and to create and destroy instances of the EFI Hash Protocol
+ so that a multiple drivers can use the underlying hashing services.
+
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __EFI_HASH_PROTOCOL_H__
+#define __EFI_HASH_PROTOCOL_H__
+
+#define EFI_HASH_SERVICE_BINDING_PROTOCOL_GUID \
+ { \
+ 0x42881c98, 0xa4f3, 0x44b0, {0xa3, 0x9d, 0xdf, 0xa1, 0x86, 0x67, 0xd8, 0xcd } \
+ }
+
+#define EFI_HASH_PROTOCOL_GUID \
+ { \
+ 0xc5184932, 0xdba5, 0x46db, {0xa5, 0xba, 0xcc, 0x0b, 0xda, 0x9c, 0x14, 0x35 } \
+ }
+
+#define EFI_HASH_ALGORITHM_SHA1_GUID \
+ { \
+ 0x2ae9d80f, 0x3fb2, 0x4095, {0xb7, 0xb1, 0xe9, 0x31, 0x57, 0xb9, 0x46, 0xb6 } \
+ }
+
+#define EFI_HASH_ALGORITHM_SHA224_GUID \
+ { \
+ 0x8df01a06, 0x9bd5, 0x4bf7, {0xb0, 0x21, 0xdb, 0x4f, 0xd9, 0xcc, 0xf4, 0x5b } \
+ }
+
+#define EFI_HASH_ALGORITHM_SHA256_GUID \
+ { \
+ 0x51aa59de, 0xfdf2, 0x4ea3, {0xbc, 0x63, 0x87, 0x5f, 0xb7, 0x84, 0x2e, 0xe9 } \
+ }
+
+#define EFI_HASH_ALGORITHM_SHA384_GUID \
+ { \
+ 0xefa96432, 0xde33, 0x4dd2, {0xae, 0xe6, 0x32, 0x8c, 0x33, 0xdf, 0x77, 0x7a } \
+ }
+
+#define EFI_HASH_ALGORITHM_SHA512_GUID \
+ { \
+ 0xcaa4381e, 0x750c, 0x4770, {0xb8, 0x70, 0x7a, 0x23, 0xb4, 0xe4, 0x21, 0x30 } \
+ }
+
+#define EFI_HASH_ALGORTIHM_MD5_GUID \
+ { \
+ 0xaf7c79c, 0x65b5, 0x4319, {0xb0, 0xae, 0x44, 0xec, 0x48, 0x4e, 0x4a, 0xd7 } \
+ }
+
+#define EFI_HASH_ALGORITHM_SHA1_NOPAD_GUID \
+ { \
+ 0x24c5dc2f, 0x53e2, 0x40ca, {0x9e, 0xd6, 0xa5, 0xd9, 0xa4, 0x9f, 0x46, 0x3b } \
+ }
+
+#define EFI_HASH_ALGORITHM_SHA256_NOPAD_GUID \
+ { \
+ 0x8628752a, 0x6cb7, 0x4814, {0x96, 0xfc, 0x24, 0xa8, 0x15, 0xac, 0x22, 0x26 } \
+ }
+
+//
+// Note: Use of the following algorithms with EFI_HASH_PROTOCOL is deprecated.
+// EFI_HASH_ALGORITHM_SHA1_GUID
+// EFI_HASH_ALGORITHM_SHA224_GUID
+// EFI_HASH_ALGORITHM_SHA256_GUID
+// EFI_HASH_ALGORITHM_SHA384_GUID
+// EFI_HASH_ALGORITHM_SHA512_GUID
+// EFI_HASH_ALGORTIHM_MD5_GUID
+//
+
+typedef struct _EFI_HASH_PROTOCOL EFI_HASH_PROTOCOL;
+
+typedef UINT8 EFI_MD5_HASH[16];
+typedef UINT8 EFI_SHA1_HASH[20];
+typedef UINT8 EFI_SHA224_HASH[28];
+typedef UINT8 EFI_SHA256_HASH[32];
+typedef UINT8 EFI_SHA384_HASH[48];
+typedef UINT8 EFI_SHA512_HASH[64];
+
+typedef union {
+ EFI_MD5_HASH *Md5Hash;
+ EFI_SHA1_HASH *Sha1Hash;
+ EFI_SHA224_HASH *Sha224Hash;
+ EFI_SHA256_HASH *Sha256Hash;
+ EFI_SHA384_HASH *Sha384Hash;
+ EFI_SHA512_HASH *Sha512Hash;
+} EFI_HASH_OUTPUT;
+
+/**
+ Returns the size of the hash which results from a specific algorithm.
+
+ @param[in] This Points to this instance of EFI_HASH_PROTOCOL.
+ @param[in] HashAlgorithm Points to the EFI_GUID which identifies the algorithm to use.
+ @param[out] HashSize Holds the returned size of the algorithm's hash.
+
+ @retval EFI_SUCCESS Hash size returned successfully.
+ @retval EFI_INVALID_PARAMETER HashSize is NULL or HashAlgorithm is NULL.
+ @retval EFI_UNSUPPORTED The algorithm specified by HashAlgorithm is not supported
+ by this driver.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_HASH_GET_HASH_SIZE)(
+ IN CONST EFI_HASH_PROTOCOL *This,
+ IN CONST EFI_GUID *HashAlgorithm,
+ OUT UINTN *HashSize
+ );
+
+/**
+ Creates a hash for the specified message text.
+
+ @param[in] This Points to this instance of EFI_HASH_PROTOCOL.
+ @param[in] HashAlgorithm Points to the EFI_GUID which identifies the algorithm to use.
+ @param[in] Extend Specifies whether to create a new hash (FALSE) or extend the specified
+ existing hash (TRUE).
+ @param[in] Message Points to the start of the message.
+ @param[in] MessageSize The size of Message, in bytes.
+ @param[in,out] Hash On input, if Extend is TRUE, then this parameter holds a pointer
+ to a pointer to an array containing the hash to extend. If Extend
+ is FALSE, then this parameter holds a pointer to a pointer to a
+ caller-allocated array that will receive the result of the hash
+ computation. On output (regardless of the value of Extend), the
+ array will contain the result of the hash computation.
+
+ @retval EFI_SUCCESS Hash returned successfully.
+ @retval EFI_INVALID_PARAMETER Message or Hash, HashAlgorithm is NULL or MessageSize is 0.
+ MessageSize is not an integer multiple of block size.
+ @retval EFI_UNSUPPORTED The algorithm specified by HashAlgorithm is not supported by this
+ driver. Or, Extend is TRUE, and the algorithm doesn't support extending the hash.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_HASH_HASH)(
+ IN CONST EFI_HASH_PROTOCOL *This,
+ IN CONST EFI_GUID *HashAlgorithm,
+ IN BOOLEAN Extend,
+ IN CONST UINT8 *Message,
+ IN UINT64 MessageSize,
+ IN OUT EFI_HASH_OUTPUT *Hash
+ );
+
+///
+/// This protocol allows creating a hash of an arbitrary message digest
+/// using one or more hash algorithms.
+///
+struct _EFI_HASH_PROTOCOL {
+ EFI_HASH_GET_HASH_SIZE GetHashSize;
+ EFI_HASH_HASH Hash;
+};
+
+extern EFI_GUID gEfiHashServiceBindingProtocolGuid;
+extern EFI_GUID gEfiHashProtocolGuid;
+extern EFI_GUID gEfiHashAlgorithmSha1Guid;
+extern EFI_GUID gEfiHashAlgorithmSha224Guid;
+extern EFI_GUID gEfiHashAlgorithmSha256Guid;
+extern EFI_GUID gEfiHashAlgorithmSha384Guid;
+extern EFI_GUID gEfiHashAlgorithmSha512Guid;
+extern EFI_GUID gEfiHashAlgorithmMD5Guid;
+extern EFI_GUID gEfiHashAlgorithmSha1NoPadGuid;
+extern EFI_GUID gEfiHashAlgorithmSha256NoPadGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/Hash2.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/Hash2.h
new file mode 100644
index 0000000000..35bf1caea1
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/Hash2.h
@@ -0,0 +1,196 @@
+/** @file
+ EFI_HASH2_SERVICE_BINDING_PROTOCOL as defined in UEFI 2.5.
+ EFI_HASH2_PROTOCOL as defined in UEFI 2.5.
+ The EFI Hash2 Service Binding Protocol is used to locate hashing services support
+ provided by a driver and to create and destroy instances of the EFI Hash2 Protocol
+ so that a multiple drivers can use the underlying hashing services.
+ EFI_HASH2_PROTOCOL describes hashing functions for which the algorithm-required
+ message padding and finalization are performed by the supporting driver.
+
+Copyright (c) 2015, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __EFI_HASH2_PROTOCOL_H__
+#define __EFI_HASH2_PROTOCOL_H__
+
+#define EFI_HASH2_SERVICE_BINDING_PROTOCOL_GUID \
+ { \
+ 0xda836f8d, 0x217f, 0x4ca0, { 0x99, 0xc2, 0x1c, 0xa4, 0xe1, 0x60, 0x77, 0xea } \
+ }
+
+#define EFI_HASH2_PROTOCOL_GUID \
+ { \
+ 0x55b1d734, 0xc5e1, 0x49db, { 0x96, 0x47, 0xb1, 0x6a, 0xfb, 0xe, 0x30, 0x5b } \
+ }
+
+#include
+
+//
+// NOTE:
+// Algorithms EFI_HASH_ALGORITHM_SHA1_NOPAD and
+// EFI_HASH_ALGORITHM_SHA256_NOPAD_GUID are not compatible with
+// EFI_HASH2_PROTOCOL and will return EFI_UNSUPPORTED if used with any
+// EFI_HASH2_PROTOCOL function.
+//
+
+//
+// Note: SHA-1 and MD5 are included for backwards compatibility.
+// New driver implementations are encouraged to consider stronger algorithms.
+//
+
+typedef struct _EFI_HASH2_PROTOCOL EFI_HASH2_PROTOCOL;
+
+typedef UINT8 EFI_MD5_HASH2[16];
+typedef UINT8 EFI_SHA1_HASH2[20];
+typedef UINT8 EFI_SHA224_HASH2[28];
+typedef UINT8 EFI_SHA256_HASH2[32];
+typedef UINT8 EFI_SHA384_HASH2[48];
+typedef UINT8 EFI_SHA512_HASH2[64];
+
+typedef union {
+ EFI_MD5_HASH2 Md5Hash;
+ EFI_SHA1_HASH2 Sha1Hash;
+ EFI_SHA224_HASH2 Sha224Hash;
+ EFI_SHA256_HASH2 Sha256Hash;
+ EFI_SHA384_HASH2 Sha384Hash;
+ EFI_SHA512_HASH2 Sha512Hash;
+} EFI_HASH2_OUTPUT;
+
+/**
+ Returns the size of the hash which results from a specific algorithm.
+
+ @param[in] This Points to this instance of EFI_HASH2_PROTOCOL.
+ @param[in] HashAlgorithm Points to the EFI_GUID which identifies the algorithm to use.
+ @param[out] HashSize Holds the returned size of the algorithm's hash.
+
+ @retval EFI_SUCCESS Hash size returned successfully.
+ @retval EFI_INVALID_PARAMETER This or HashSize is NULL.
+ @retval EFI_UNSUPPORTED The algorithm specified by HashAlgorithm is not supported by this driver
+ or HashAlgorithm is null.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_HASH2_GET_HASH_SIZE)(
+ IN CONST EFI_HASH2_PROTOCOL *This,
+ IN CONST EFI_GUID *HashAlgorithm,
+ OUT UINTN *HashSize
+ );
+
+/**
+ Creates a hash for the specified message text. The hash is not extendable.
+ The output is final with any algorithm-required padding added by the function.
+
+ @param[in] This Points to this instance of EFI_HASH2_PROTOCOL.
+ @param[in] HashAlgorithm Points to the EFI_GUID which identifies the algorithm to use.
+ @param[in] Message Points to the start of the message.
+ @param[in] MessageSize The size of Message, in bytes.
+ @param[in,out] Hash On input, points to a caller-allocated buffer of the size
+ returned by GetHashSize() for the specified HashAlgorithm.
+ On output, the buffer holds the resulting hash computed from the message.
+
+ @retval EFI_SUCCESS Hash returned successfully.
+ @retval EFI_INVALID_PARAMETER This or Hash is NULL.
+ @retval EFI_UNSUPPORTED The algorithm specified by HashAlgorithm is not supported by this driver
+ or HashAlgorithm is Null.
+ @retval EFI_OUT_OF_RESOURCES Some resource required by the function is not available
+ or MessageSize is greater than platform maximum.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_HASH2_HASH)(
+ IN CONST EFI_HASH2_PROTOCOL *This,
+ IN CONST EFI_GUID *HashAlgorithm,
+ IN CONST UINT8 *Message,
+ IN UINTN MessageSize,
+ IN OUT EFI_HASH2_OUTPUT *Hash
+ );
+
+/**
+ This function must be called to initialize a digest calculation to be subsequently performed using the
+ EFI_HASH2_PROTOCOL functions HashUpdate() and HashFinal().
+
+ @param[in] This Points to this instance of EFI_HASH2_PROTOCOL.
+ @param[in] HashAlgorithm Points to the EFI_GUID which identifies the algorithm to use.
+
+ @retval EFI_SUCCESS Initialized successfully.
+ @retval EFI_INVALID_PARAMETER This is NULL.
+ @retval EFI_UNSUPPORTED The algorithm specified by HashAlgorithm is not supported by this driver
+ or HashAlgorithm is Null.
+ @retval EFI_OUT_OF_RESOURCES Process failed due to lack of required resource.
+ @retval EFI_ALREADY_STARTED This function is called when the operation in progress is still in processing Hash(),
+ or HashInit() is already called before and not terminated by HashFinal() yet on the same instance.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_HASH2_HASH_INIT)(
+ IN CONST EFI_HASH2_PROTOCOL *This,
+ IN CONST EFI_GUID *HashAlgorithm
+ );
+
+/**
+ Updates the hash of a computation in progress by adding a message text.
+
+ @param[in] This Points to this instance of EFI_HASH2_PROTOCOL.
+ @param[in] Message Points to the start of the message.
+ @param[in] MessageSize The size of Message, in bytes.
+
+ @retval EFI_SUCCESS Digest in progress updated successfully.
+ @retval EFI_INVALID_PARAMETER This or Hash is NULL.
+ @retval EFI_OUT_OF_RESOURCES Some resource required by the function is not available
+ or MessageSize is greater than platform maximum.
+ @retval EFI_NOT_READY This call was not preceded by a valid call to HashInit(),
+ or the operation in progress was terminated by a call to Hash() or HashFinal() on the same instance.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_HASH2_HASH_UPDATE)(
+ IN CONST EFI_HASH2_PROTOCOL *This,
+ IN CONST UINT8 *Message,
+ IN UINTN MessageSize
+ );
+
+/**
+ Finalizes a hash operation in progress and returns calculation result.
+ The output is final with any necessary padding added by the function.
+ The hash may not be further updated or extended after HashFinal().
+
+ @param[in] This Points to this instance of EFI_HASH2_PROTOCOL.
+ @param[in,out] Hash On input, points to a caller-allocated buffer of the size
+ returned by GetHashSize() for the specified HashAlgorithm specified in preceding HashInit().
+ On output, the buffer holds the resulting hash computed from the message.
+
+ @retval EFI_SUCCESS Hash returned successfully.
+ @retval EFI_INVALID_PARAMETER This or Hash is NULL.
+ @retval EFI_NOT_READY This call was not preceded by a valid call to HashInit() and at least one call to HashUpdate(),
+ or the operation in progress was canceled by a call to Hash() on the same instance.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_HASH2_HASH_FINAL)(
+ IN CONST EFI_HASH2_PROTOCOL *This,
+ IN OUT EFI_HASH2_OUTPUT *Hash
+ );
+
+///
+/// This protocol describes hashing functions for which the algorithm-required message padding and
+/// finalization are performed by the supporting driver.
+///
+struct _EFI_HASH2_PROTOCOL {
+ EFI_HASH2_GET_HASH_SIZE GetHashSize;
+ EFI_HASH2_HASH Hash;
+ EFI_HASH2_HASH_INIT HashInit;
+ EFI_HASH2_HASH_UPDATE HashUpdate;
+ EFI_HASH2_HASH_FINAL HashFinal;
+};
+
+extern EFI_GUID gEfiHash2ServiceBindingProtocolGuid;
+extern EFI_GUID gEfiHash2ProtocolGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/HiiConfigAccess.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/HiiConfigAccess.h
new file mode 100644
index 0000000000..2624bf6c55
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/HiiConfigAccess.h
@@ -0,0 +1,216 @@
+/** @file
+
+ The EFI HII results processing protocol invokes this type of protocol
+ when it needs to forward results to a driver's configuration handler.
+ This protocol is published by drivers providing and requesting
+ configuration data from HII. It may only be invoked by HII.
+
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Revision Reference:
+ This Protocol was introduced in UEFI Specification 2.1.
+
+**/
+
+#ifndef __EFI_HII_CONFIG_ACCESS_H__
+#define __EFI_HII_CONFIG_ACCESS_H__
+
+#include
+
+#define EFI_HII_CONFIG_ACCESS_PROTOCOL_GUID \
+ { 0x330d4706, 0xf2a0, 0x4e4f, { 0xa3, 0x69, 0xb6, 0x6f, 0xa8, 0xd5, 0x43, 0x85 } }
+
+typedef struct _EFI_HII_CONFIG_ACCESS_PROTOCOL EFI_HII_CONFIG_ACCESS_PROTOCOL;
+
+typedef UINTN EFI_BROWSER_ACTION;
+
+#define EFI_BROWSER_ACTION_CHANGING 0
+#define EFI_BROWSER_ACTION_CHANGED 1
+#define EFI_BROWSER_ACTION_RETRIEVE 2
+#define EFI_BROWSER_ACTION_FORM_OPEN 3
+#define EFI_BROWSER_ACTION_FORM_CLOSE 4
+#define EFI_BROWSER_ACTION_SUBMITTED 5
+#define EFI_BROWSER_ACTION_DEFAULT_STANDARD 0x1000
+#define EFI_BROWSER_ACTION_DEFAULT_MANUFACTURING 0x1001
+#define EFI_BROWSER_ACTION_DEFAULT_SAFE 0x1002
+#define EFI_BROWSER_ACTION_DEFAULT_PLATFORM 0x2000
+#define EFI_BROWSER_ACTION_DEFAULT_HARDWARE 0x3000
+#define EFI_BROWSER_ACTION_DEFAULT_FIRMWARE 0x4000
+
+/**
+
+ This function allows the caller to request the current
+ configuration for one or more named elements. The resulting
+ string is in format. Any and all alternative
+ configuration strings shall also be appended to the end of the
+ current configuration string. If they are, they must appear
+ after the current configuration. They must contain the same
+ routing (GUID, NAME, PATH) as the current configuration string.
+ They must have an additional description indicating the type of
+ alternative configuration the string represents,
+ "ALTCFG=". That (when
+ converted from Hex UNICODE to binary) is a reference to a
+ string in the associated string pack.
+
+ @param This Points to the EFI_HII_CONFIG_ACCESS_PROTOCOL.
+
+ @param Request A null-terminated Unicode string in
+ format. Note that this
+ includes the routing information as well as
+ the configurable name / value pairs. It is
+ invalid for this string to be in
+ format.
+ If a NULL is passed in for the Request field,
+ all of the settings being abstracted by this function
+ will be returned in the Results field. In addition,
+ if a ConfigHdr is passed in with no request elements,
+ all of the settings being abstracted for that particular
+ ConfigHdr reference will be returned in the Results Field.
+
+ @param Progress On return, points to a character in the
+ Request string. Points to the string's null
+ terminator if request was successful. Points
+ to the most recent "&" before the first
+ failing name / value pair (or the beginning
+ of the string if the failure is in the first
+ name / value pair) if the request was not
+ successful.
+
+ @param Results A null-terminated Unicode string in
+ format which has all values
+ filled in for the names in the Request string.
+ String to be allocated by the called function.
+
+ @retval EFI_SUCCESS The Results string is filled with the
+ values corresponding to all requested
+ names.
+
+ @retval EFI_OUT_OF_RESOURCES Not enough memory to store the
+ parts of the results that must be
+ stored awaiting possible future
+ protocols.
+
+ @retval EFI_NOT_FOUND A configuration element matching
+ the routing data is not found.
+ Progress set to the first character
+ in the routing header.
+
+ @retval EFI_INVALID_PARAMETER Illegal syntax. Progress set
+ to most recent "&" before the
+ error or the beginning of the
+ string.
+
+ @retval EFI_INVALID_PARAMETER Unknown name. Progress points
+ to the & before the name in
+ question.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_HII_ACCESS_EXTRACT_CONFIG)(
+ IN CONST EFI_HII_CONFIG_ACCESS_PROTOCOL *This,
+ IN CONST EFI_STRING Request,
+ OUT EFI_STRING *Progress,
+ OUT EFI_STRING *Results
+ );
+
+/**
+
+ This function applies changes in a driver's configuration.
+ Input is a Configuration, which has the routing data for this
+ driver followed by name / value configuration pairs. The driver
+ must apply those pairs to its configurable storage. If the
+ driver's configuration is stored in a linear block of data
+ and the driver's name / value pairs are in
+ format, it may use the ConfigToBlock helper function (above) to
+ simplify the job.
+
+ @param This Points to the EFI_HII_CONFIG_ACCESS_PROTOCOL.
+
+ @param Configuration A null-terminated Unicode string in
+ format.
+
+ @param Progress A pointer to a string filled in with the
+ offset of the most recent '&' before the
+ first failing name / value pair (or the
+ beginn ing of the string if the failure
+ is in the first name / value pair) or
+ the terminating NULL if all was
+ successful.
+
+ @retval EFI_SUCCESS The results have been distributed or are
+ awaiting distribution.
+
+ @retval EFI_OUT_OF_RESOURCES Not enough memory to store the
+ parts of the results that must be
+ stored awaiting possible future
+ protocols.
+
+ @retval EFI_INVALID_PARAMETERS Passing in a NULL for the
+ Results parameter would result
+ in this type of error.
+
+ @retval EFI_NOT_FOUND Target for the specified routing data
+ was not found
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_HII_ACCESS_ROUTE_CONFIG)(
+ IN CONST EFI_HII_CONFIG_ACCESS_PROTOCOL *This,
+ IN CONST EFI_STRING Configuration,
+ OUT EFI_STRING *Progress
+ );
+
+/**
+
+ This function is called to provide results data to the driver.
+ This data consists of a unique key that is used to identify
+ which data is either being passed back or being asked for.
+
+ @param This Points to the EFI_HII_CONFIG_ACCESS_PROTOCOL.
+ @param Action Specifies the type of action taken by the browser.
+ @param QuestionId A unique value which is sent to the original
+ exporting driver so that it can identify the type
+ of data to expect. The format of the data tends to
+ vary based on the opcode that generated the callback.
+ @param Type The type of value for the question.
+ @param Value A pointer to the data being sent to the original
+ exporting driver.
+ @param ActionRequest On return, points to the action requested by the
+ callback function.
+
+ @retval EFI_SUCCESS The callback successfully handled the action.
+ @retval EFI_OUT_OF_RESOURCES Not enough storage is available to hold the
+ variable and its data.
+ @retval EFI_DEVICE_ERROR The variable could not be saved.
+ @retval EFI_UNSUPPORTED The specified Action is not supported by the
+ callback.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_HII_ACCESS_FORM_CALLBACK)(
+ IN CONST EFI_HII_CONFIG_ACCESS_PROTOCOL *This,
+ IN EFI_BROWSER_ACTION Action,
+ IN EFI_QUESTION_ID QuestionId,
+ IN UINT8 Type,
+ IN OUT EFI_IFR_TYPE_VALUE *Value,
+ OUT EFI_BROWSER_ACTION_REQUEST *ActionRequest
+ )
+;
+
+///
+/// This protocol provides a callable interface between the HII and
+/// drivers. Only drivers which provide IFR data to HII are required
+/// to publish this protocol.
+///
+struct _EFI_HII_CONFIG_ACCESS_PROTOCOL {
+ EFI_HII_ACCESS_EXTRACT_CONFIG ExtractConfig;
+ EFI_HII_ACCESS_ROUTE_CONFIG RouteConfig;
+ EFI_HII_ACCESS_FORM_CALLBACK Callback;
+};
+
+extern EFI_GUID gEfiHiiConfigAccessProtocolGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/HiiConfigKeyword.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/HiiConfigKeyword.h
new file mode 100644
index 0000000000..f376d1d3b8
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/HiiConfigKeyword.h
@@ -0,0 +1,197 @@
+/** @file
+ The file provides the mechanism to set and get the values
+ associated with a keyword exposed through a x-UEFI- prefixed
+ configuration language namespace.
+
+Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Revision Reference:
+ This Protocol was introduced in UEFI Specification 2.5.
+
+
+**/
+
+#ifndef __EFI_CONFIG_KEYWORD_HANDLER_H__
+#define __EFI_CONFIG_KEYWORD_HANDLER_H__
+
+#define EFI_CONFIG_KEYWORD_HANDLER_PROTOCOL_GUID \
+{ \
+ 0x0a8badd5, 0x03b8, 0x4d19, {0xb1, 0x28, 0x7b, 0x8f, 0x0e, 0xda, 0xa5, 0x96 } \
+}
+
+// ***********************************************************
+// Progress Errors
+// ***********************************************************
+#define KEYWORD_HANDLER_NO_ERROR 0x00000000
+#define KEYWORD_HANDLER_NAMESPACE_ID_NOT_FOUND 0x00000001
+#define KEYWORD_HANDLER_MALFORMED_STRING 0x00000002
+#define KEYWORD_HANDLER_KEYWORD_NOT_FOUND 0x00000004
+#define KEYWORD_HANDLER_INCOMPATIBLE_VALUE_DETECTED 0x00000008
+#define KEYWORD_HANDLER_ACCESS_NOT_PERMITTED 0x00000010
+#define KEYWORD_HANDLER_UNDEFINED_PROCESSING_ERROR 0x80000000
+
+typedef struct _EFI_CONFIG_KEYWORD_HANDLER_PROTOCOL EFI_CONFIG_KEYWORD_HANDLER_PROTOCOL;
+
+/**
+
+ This function accepts a formatted string, finds the associated
+ keyword owners, creates a string from it and forwards it to the
+ EFI_HII_ROUTING_PROTOCOL.RouteConfig function.
+
+ If there is an issue in resolving the contents of the KeywordString, then the
+ function returns an error and also sets the Progress and ProgressErr with the
+ appropriate information about where the issue occurred and additional data about
+ the nature of the issue.
+
+ In the case when KeywordString containing multiple keywords, when an EFI_NOT_FOUND
+ error is generated during processing the second or later keyword element, the system
+ storage associated with earlier keywords is not modified. All elements of the
+ KeywordString must successfully pass all tests for format and access prior to making
+ any modifications to storage.
+
+ In the case when EFI_DEVICE_ERROR is returned from the processing of a KeywordString
+ containing multiple keywords, the state of storage associated with earlier keywords
+ is undefined.
+
+
+ @param This Pointer to the EFI_KEYWORD_HANDLER _PROTOCOL instance.
+
+ @param KeywordString A null-terminated string in format.
+
+ @param Progress On return, points to a character in the KeywordString.
+ Points to the string's NULL terminator if the request
+ was successful. Points to the most recent '&' before
+ the first failing name / value pair (or the beginning
+ of the string if the failure is in the first name / value
+ pair) if the request was not successful.
+
+ @param ProgressErr If during the processing of the KeywordString there was
+ a failure, this parameter gives additional information
+ about the possible source of the problem. The various
+ errors are defined in "Related Definitions" below.
+
+
+ @retval EFI_SUCCESS The specified action was completed successfully.
+
+ @retval EFI_INVALID_PARAMETER One or more of the following are TRUE:
+ 1. KeywordString is NULL.
+ 2. Parsing of the KeywordString resulted in an
+ error. See Progress and ProgressErr for more data.
+
+ @retval EFI_NOT_FOUND An element of the KeywordString was not found.
+ See ProgressErr for more data.
+
+ @retval EFI_OUT_OF_RESOURCES Required system resources could not be allocated.
+ See ProgressErr for more data.
+
+ @retval EFI_ACCESS_DENIED The action violated system policy. See ProgressErr
+ for more data.
+
+ @retval EFI_DEVICE_ERROR An unexpected system error occurred. See ProgressErr
+ for more data.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_CONFIG_KEYWORD_HANDLER_SET_DATA)(
+ IN EFI_CONFIG_KEYWORD_HANDLER_PROTOCOL *This,
+ IN CONST EFI_STRING KeywordString,
+ OUT EFI_STRING *Progress,
+ OUT UINT32 *ProgressErr
+ );
+
+/**
+
+ This function accepts a formatted string, finds the underlying
+ keyword owners, creates a string from it and forwards it to the
+ EFI_HII_ROUTING_PROTOCOL.ExtractConfig function.
+
+ If there is an issue in resolving the contents of the KeywordString, then the function
+ returns an EFI_INVALID_PARAMETER and also set the Progress and ProgressErr with the
+ appropriate information about where the issue occurred and additional data about the
+ nature of the issue.
+
+ In the case when KeywordString is NULL, or contains multiple keywords, or when
+ EFI_NOT_FOUND is generated while processing the keyword elements, the Results string
+ contains values returned for all keywords processed prior to the keyword generating the
+ error but no values for the keyword with error or any following keywords.
+
+
+ @param This Pointer to the EFI_KEYWORD_HANDLER _PROTOCOL instance.
+
+ @param NameSpaceId A null-terminated string containing the platform configuration
+ language to search through in the system. If a NULL is passed
+ in, then it is assumed that any platform configuration language
+ with the prefix of "x-UEFI-" are searched.
+
+ @param KeywordString A null-terminated string in format. If a
+ NULL is passed in the KeywordString field, all of the known
+ keywords in the system for the NameSpaceId specified are
+ returned in the Results field.
+
+ @param Progress On return, points to a character in the KeywordString. Points
+ to the string's NULL terminator if the request was successful.
+ Points to the most recent '&' before the first failing name / value
+ pair (or the beginning of the string if the failure is in the first
+ name / value pair) if the request was not successful.
+
+ @param ProgressErr If during the processing of the KeywordString there was a
+ failure, this parameter gives additional information about the
+ possible source of the problem. See the definitions in SetData()
+ for valid value definitions.
+
+ @param Results A null-terminated string in format is returned
+ which has all the values filled in for the keywords in the
+ KeywordString. This is a callee-allocated field, and must be freed
+ by the caller after being used.
+
+ @retval EFI_SUCCESS The specified action was completed successfully.
+
+ @retval EFI_INVALID_PARAMETER One or more of the following are TRUE:
+ 1.Progress, ProgressErr, or Results is NULL.
+ 2.Parsing of the KeywordString resulted in an error. See
+ Progress and ProgressErr for more data.
+
+
+ @retval EFI_NOT_FOUND An element of the KeywordString was not found. See
+ ProgressErr for more data.
+
+ @retval EFI_NOT_FOUND The NamespaceId specified was not found. See ProgressErr
+ for more data.
+
+ @retval EFI_OUT_OF_RESOURCES Required system resources could not be allocated. See
+ ProgressErr for more data.
+
+ @retval EFI_ACCESS_DENIED The action violated system policy. See ProgressErr for
+ more data.
+
+ @retval EFI_DEVICE_ERROR An unexpected system error occurred. See ProgressErr
+ for more data.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_CONFIG_KEYWORD_HANDLER_GET_DATA)(
+ IN EFI_CONFIG_KEYWORD_HANDLER_PROTOCOL *This,
+ IN CONST EFI_STRING NameSpaceId OPTIONAL,
+ IN CONST EFI_STRING KeywordString OPTIONAL,
+ OUT EFI_STRING *Progress,
+ OUT UINT32 *ProgressErr,
+ OUT EFI_STRING *Results
+ );
+
+///
+/// The EFI_CONFIG_KEYWORD_HANDLER_PROTOCOL provides the mechanism
+/// to set and get the values associated with a keyword exposed
+/// through a x-UEFI- prefixed configuration language namespace
+///
+
+struct _EFI_CONFIG_KEYWORD_HANDLER_PROTOCOL {
+ EFI_CONFIG_KEYWORD_HANDLER_SET_DATA SetData;
+ EFI_CONFIG_KEYWORD_HANDLER_GET_DATA GetData;
+};
+
+extern EFI_GUID gEfiConfigKeywordHandlerProtocolGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/HiiConfigRouting.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/HiiConfigRouting.h
new file mode 100644
index 0000000000..9083219668
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/HiiConfigRouting.h
@@ -0,0 +1,411 @@
+/** @file
+ The file provides services to manage the movement of
+ configuration data from drivers to configuration applications.
+ It then serves as the single point to receive configuration
+ information from configuration applications, routing the
+ results to the appropriate drivers.
+
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Revision Reference:
+ This Protocol was introduced in UEFI Specification 2.1.
+
+
+**/
+
+#ifndef __HII_CONFIG_ROUTING_H__
+#define __HII_CONFIG_ROUTING_H__
+
+#define EFI_HII_CONFIG_ROUTING_PROTOCOL_GUID \
+ { 0x587e72d7, 0xcc50, 0x4f79, { 0x82, 0x09, 0xca, 0x29, 0x1f, 0xc1, 0xa1, 0x0f } }
+
+typedef struct _EFI_HII_CONFIG_ROUTING_PROTOCOL EFI_HII_CONFIG_ROUTING_PROTOCOL;
+
+/**
+
+ This function allows the caller to request the current
+ configuration for one or more named elements from one or more
+ drivers. The resulting string is in the standard HII
+ configuration string format. If Successful, Results contains an
+ equivalent string with "=" and the values associated with all
+ names added in. The expected implementation is for each
+ substring in the Request to call the HII
+ Configuration Routing Protocol ExtractProtocol function for the
+ driver corresponding to the at the start of the
+ substring. The request fails if no driver
+ matches the substring. Note: Alternative
+ configuration strings may also be appended to the end of the
+ current configuration string. If they are, they must appear
+ after the current configuration. They must contain the same
+ routing (GUID, NAME, PATH) as the current configuration string.
+ They must have an additional description indicating the type of
+ alternative configuration the string represents,
+ "ALTCFG=". That (when converted from
+ hexadecimal (encoded as text) to binary) is a reference to a string in the
+ associated string pack. As an example, assume that the Request
+ string is:
+ GUID=...&NAME=00480050&PATH=...&Fred&George&Ron&Neville A result
+ might be:
+ GUID=...&NAME=00480050&PATH=...&Fred=16&George=16&Ron=12&Neville=11&
+ GUID=...&NAME=00480050&PATH=...&ALTCFG=0037&Fred=12&Neville=7
+
+ @param This Points to the EFI_HII_CONFIG_ROUTING_PROTOCOL
+ instance.
+
+ @param Request A null-terminated string in format.
+
+ @param Progress On return, points to a character in the
+ Request string. Points to the string's null
+ terminator if the request was successful. Points
+ to the most recent '&' before the first
+ failing name / value pair (or the beginning
+ of the string if the failure is in the first
+ name / value pair) if the request was not
+ successful
+
+ @param Results A null-terminated string in format
+ which has all values filled in for the names in the
+ Request string.
+
+ @retval EFI_SUCCESS The Results string is filled with the
+ values corresponding to all requested
+ names.
+
+ @retval EFI_OUT_OF_RESOURCES Not enough memory to store the
+ parts of the results that must be
+ stored awaiting possible future
+ protocols.
+
+ @retval EFI_INVALID_PARAMETER For example, passing in a NULL
+ for the Request parameter
+ would result in this type of
+ error. The Progress parameter
+ is set to NULL.
+
+ @retval EFI_NOT_FOUND Routing data doesn't match any
+ known driver. Progress set to
+ the "G" in "GUID" of the
+ routing header that doesn't
+ match. Note: There is no
+ requirement that all routing
+ data be validated before any
+ configuration extraction.
+
+ @retval EFI_INVALID_PARAMETER Illegal syntax. Progress set
+ to the most recent & before the
+ error, or the beginning of the
+ string.
+ @retval EFI_INVALID_PARAMETER The ExtractConfig function of the
+ underlying HII Configuration
+ Access Protocol returned
+ EFI_INVALID_PARAMETER. Progress
+ set to most recent & before the
+ error or the beginning of the
+ string.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_HII_EXTRACT_CONFIG)(
+ IN CONST EFI_HII_CONFIG_ROUTING_PROTOCOL *This,
+ IN CONST EFI_STRING Request,
+ OUT EFI_STRING *Progress,
+ OUT EFI_STRING *Results
+ );
+
+/**
+ This function allows the caller to request the current configuration
+ for the entirety of the current HII database and returns the data in
+ a null-terminated string.
+
+ This function allows the caller to request the current
+ configuration for all of the current HII database. The results
+ include both the current and alternate configurations as
+ described in ExtractConfig() above.
+
+ @param This Points to the EFI_HII_CONFIG_ROUTING_PROTOCOL instance.
+
+ @param Results Null-terminated Unicode string in
+ format which has all values
+ filled in for the entirety of the current HII
+ database. String to be allocated by the called
+ function. De-allocation is up to the caller.
+
+ @retval EFI_SUCCESS The Results string is filled with the
+ values corresponding to all requested
+ names.
+
+ @retval EFI_OUT_OF_RESOURCES Not enough memory to store the
+ parts of the results that must be
+ stored awaiting possible future
+ protocols.
+
+ @retval EFI_INVALID_PARAMETERS For example, passing in a NULL
+ for the Results parameter
+ would result in this type of
+ error.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_HII_EXPORT_CONFIG)(
+ IN CONST EFI_HII_CONFIG_ROUTING_PROTOCOL *This,
+ OUT EFI_STRING *Results
+ );
+
+/**
+
+ This function routes the results of processing forms to the
+ appropriate targets. It scans for within the string
+ and passes the header and subsequent body to the driver whose
+ location is described in the . Many s may
+ appear as a single request. The expected implementation is to
+ hand off the various substrings to the
+ Configuration Access Protocol RouteConfig routine corresponding
+ to the driver whose routing information is defined by the
+ in turn.
+
+ @param This Points to the EFI_HII_CONFIG_ROUTING_PROTOCOL instance.
+
+ @param Configuration A null-terminated string in format.
+
+ @param Progress A pointer to a string filled in with the
+ offset of the most recent '&' before the
+ first failing name / value pair (or the
+ beginning of the string if the failure is in
+ the first name / value pair), or the
+ terminating NULL if all was successful.
+
+ @retval EFI_SUCCESS The results have been distributed or are
+ awaiting distribution.
+
+ @retval EFI_OUT_OF_RESOURCES Not enough memory to store the
+ parts of the results that must be
+ stored awaiting possible future
+ protocols.
+
+ @retval EFI_INVALID_PARAMETERS Passing in a NULL for the
+ Results parameter would result
+ in this type of error.
+
+ @retval EFI_NOT_FOUND The target for the specified routing data
+ was not found.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_HII_ROUTE_CONFIG)(
+ IN CONST EFI_HII_CONFIG_ROUTING_PROTOCOL *This,
+ IN CONST EFI_STRING Configuration,
+ OUT EFI_STRING *Progress
+ );
+
+/**
+
+ This function extracts the current configuration from a block of
+ bytes. To do so, it requires that the ConfigRequest string
+ consists of a list of formatted names. It uses the
+ offset in the name to determine the index into the Block to
+ start the extraction and the width of each name to determine the
+ number of bytes to extract. These are mapped to a string
+ using the equivalent of the C "%x" format (with optional leading
+ spaces). The call fails if, for any (offset, width) pair in
+ ConfigRequest, offset+value >= BlockSize.
+
+ @param This Points to the EFI_HII_CONFIG_ROUTING_PROTOCOL instance.
+
+ @param ConfigRequest A null-terminated string in format.
+
+ @param Block An array of bytes defining the block's
+ configuration.
+
+ @param BlockSize The length in bytes of Block.
+
+ @param Config The filled-in configuration string. String
+ allocated by the function. Returned only if
+ call is successful. The null-terminated string
+ will be format.
+
+ @param Progress A pointer to a string filled in with the
+ offset of the most recent '&' before the
+ first failing name / value pair (or the
+ beginning of the string if the failure is in
+ the first name / value pair), or the
+ terminating NULL if all was successful.
+
+ @retval EFI_SUCCESS The request succeeded. Progress points
+ to the null terminator at the end of the
+ ConfigRequest string.
+
+ @retval EFI_OUT_OF_RESOURCES Not enough memory to allocate
+ Config. Progress points to the
+ first character of ConfigRequest.
+
+ @retval EFI_INVALID_PARAMETERS Passing in a NULL for the
+ ConfigRequest or Block
+ parameter would result in this
+ type of error. Progress points
+ to the first character of
+ ConfigRequest.
+
+ @retval EFI_NOT_FOUND The target for the specified routing data
+ was not found. Progress points to the
+ 'G' in "GUID" of the errant routing
+ data.
+ @retval EFI_DEVICE_ERROR The block is not large enough. Progress undefined.
+
+ @retval EFI_INVALID_PARAMETER Encountered non
+ formatted string. Block is
+ left updated and Progress
+ points at the '&' preceding
+ the first non-.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_HII_BLOCK_TO_CONFIG)(
+ IN CONST EFI_HII_CONFIG_ROUTING_PROTOCOL *This,
+ IN CONST EFI_STRING ConfigRequest,
+ IN CONST UINT8 *Block,
+ IN CONST UINTN BlockSize,
+ OUT EFI_STRING *Config,
+ OUT EFI_STRING *Progress
+ );
+
+/**
+ This function maps a configuration containing a series of
+ formatted name value pairs in ConfigResp into a
+ Block so it may be stored in a linear mapped storage such as a
+ UEFI Variable. If present, the function skips GUID, NAME, and
+ PATH in . It stops when it finds a non-
+ name / value pair (after skipping the routing header) or when it
+ reaches the end of the string.
+ Example Assume an existing block containing: 00 01 02 03 04 05
+ And the ConfigResp string is:
+ OFFSET=4&WIDTH=1&VALUE=7&OFFSET=0&WIDTH=2&VALUE=AA55
+ The results are
+ 55 AA 02 07 04 05
+
+ @param This Points to the EFI_HII_CONFIG_ROUTING_PROTOCOL instance.
+
+ @param ConfigResp A null-terminated string in format.
+
+ @param Block A possibly null array of bytes
+ representing the current block. Only
+ bytes referenced in the ConfigResp
+ string in the block are modified. If
+ this parameter is null or if the
+ BlockLength parameter is (on input)
+ shorter than required by the
+ Configuration string, only the BlockSize
+ parameter is updated, and an appropriate
+ status (see below) is returned.
+
+ @param BlockSize The length of the Block in units of UINT8.
+ On input, this is the size of the Block. On
+ output, if successful, contains the largest
+ index of the modified byte in the Block, or
+ the required buffer size if the Block is not
+ large enough.
+
+ @param Progress On return, points to an element of the
+ ConfigResp string filled in with the offset
+ of the most recent "&" before the first
+ failing name / value pair (or the beginning
+ of the string if the failure is in the first
+ name / value pair), or the terminating NULL
+ if all was successful.
+
+ @retval EFI_SUCCESS The request succeeded. Progress points to the null
+ terminator at the end of the ConfigResp string.
+ @retval EFI_OUT_OF_RESOURCES Not enough memory to allocate Config. Progress
+ points to the first character of ConfigResp.
+ @retval EFI_INVALID_PARAMETER Passing in a NULL for the ConfigResp or
+ Block parameter would result in this type of
+ error. Progress points to the first character of
+ ConfigResp.
+ @retval EFI_INVALID_PARAMETER Encountered non formatted name /
+ value pair. Block is left updated and
+ Progress points at the '&' preceding the first
+ non-.
+ @retval EFI_DEVICE_ERROR Block not large enough. Progress undefined.
+ @retval EFI_NOT_FOUND Target for the specified routing data was not found.
+ Progress points to the "G" in "GUID" of the errant
+ routing data.
+ @retval EFI_BUFFER_TOO_SMALL Block not large enough. Progress undefined.
+ BlockSize is updated with the required buffer size.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_HII_CONFIG_TO_BLOCK)(
+ IN CONST EFI_HII_CONFIG_ROUTING_PROTOCOL *This,
+ IN CONST EFI_STRING ConfigResp,
+ IN OUT UINT8 *Block,
+ IN OUT UINTN *BlockSize,
+ OUT EFI_STRING *Progress
+ );
+
+/**
+ This helper function is to be called by drivers to extract portions of
+ a larger configuration string.
+
+ @param This A pointer to the EFI_HII_CONFIG_ROUTING_PROTOCOL instance.
+ @param ConfigResp A null-terminated string in format.
+ @param Guid A pointer to the GUID value to search for in the
+ routing portion of the ConfigResp string when retrieving
+ the requested data. If Guid is NULL, then all GUID
+ values will be searched for.
+ @param Name A pointer to the NAME value to search for in the
+ routing portion of the ConfigResp string when retrieving
+ the requested data. If Name is NULL, then all Name
+ values will be searched for.
+ @param DevicePath A pointer to the PATH value to search for in the
+ routing portion of the ConfigResp string when retrieving
+ the requested data. If DevicePath is NULL, then all
+ DevicePath values will be searched for.
+ @param AltCfgId A pointer to the ALTCFG value to search for in the
+ routing portion of the ConfigResp string when retrieving
+ the requested data. If this parameter is NULL,
+ then the current setting will be retrieved.
+ @param AltCfgResp A pointer to a buffer which will be allocated by the
+ function which contains the retrieved string as requested.
+ This buffer is only allocated if the call was successful.
+ The null-terminated string will be format.
+
+ @retval EFI_SUCCESS The request succeeded. The requested data was extracted
+ and placed in the newly allocated AltCfgResp buffer.
+ @retval EFI_OUT_OF_RESOURCES Not enough memory to allocate AltCfgResp.
+ @retval EFI_INVALID_PARAMETER Any parameter is invalid.
+ @retval EFI_NOT_FOUND The target for the specified routing data was not found.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_HII_GET_ALT_CFG)(
+ IN CONST EFI_HII_CONFIG_ROUTING_PROTOCOL *This,
+ IN CONST EFI_STRING ConfigResp,
+ IN CONST EFI_GUID *Guid,
+ IN CONST EFI_STRING Name,
+ IN CONST EFI_DEVICE_PATH_PROTOCOL *DevicePath,
+ IN CONST UINT16 *AltCfgId,
+ OUT EFI_STRING *AltCfgResp
+ );
+
+///
+/// This protocol defines the configuration routing interfaces
+/// between external applications and the HII. There may only be one
+/// instance of this protocol in the system.
+///
+struct _EFI_HII_CONFIG_ROUTING_PROTOCOL {
+ EFI_HII_EXTRACT_CONFIG ExtractConfig;
+ EFI_HII_EXPORT_CONFIG ExportConfig;
+ EFI_HII_ROUTE_CONFIG RouteConfig;
+ EFI_HII_BLOCK_TO_CONFIG BlockToConfig;
+ EFI_HII_CONFIG_TO_BLOCK ConfigToBlock;
+ EFI_HII_GET_ALT_CFG GetAltConfig;
+};
+
+extern EFI_GUID gEfiHiiConfigRoutingProtocolGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/HiiDatabase.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/HiiDatabase.h
new file mode 100644
index 0000000000..f6d6f2c0fe
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/HiiDatabase.h
@@ -0,0 +1,518 @@
+/** @file
+ The file provides Database manager for HII-related data
+ structures.
+
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Revision Reference:
+ This Protocol was introduced in UEFI Specification 2.1.
+
+**/
+
+#ifndef __HII_DATABASE_H__
+#define __HII_DATABASE_H__
+
+#define EFI_HII_DATABASE_PROTOCOL_GUID \
+ { 0xef9fc172, 0xa1b2, 0x4693, { 0xb3, 0x27, 0x6d, 0x32, 0xfc, 0x41, 0x60, 0x42 } }
+
+typedef struct _EFI_HII_DATABASE_PROTOCOL EFI_HII_DATABASE_PROTOCOL;
+
+///
+/// EFI_HII_DATABASE_NOTIFY_TYPE.
+///
+typedef UINTN EFI_HII_DATABASE_NOTIFY_TYPE;
+
+#define EFI_HII_DATABASE_NOTIFY_NEW_PACK 0x00000001
+#define EFI_HII_DATABASE_NOTIFY_REMOVE_PACK 0x00000002
+#define EFI_HII_DATABASE_NOTIFY_EXPORT_PACK 0x00000004
+#define EFI_HII_DATABASE_NOTIFY_ADD_PACK 0x00000008
+
+/**
+
+ Functions which are registered to receive notification of
+ database events have this prototype. The actual event is encoded
+ in NotifyType. The following table describes how PackageType,
+ PackageGuid, Handle, and Package are used for each of the
+ notification types.
+
+ @param PackageType Package type of the notification.
+
+ @param PackageGuid If PackageType is
+ EFI_HII_PACKAGE_TYPE_GUID, then this is
+ the pointer to the GUID from the Guid
+ field of EFI_HII_PACKAGE_GUID_HEADER.
+ Otherwise, it must be NULL.
+
+ @param Package Points to the package referred to by the notification.
+
+ @param Handle The handle of the package
+ list which contains the specified package.
+
+ @param NotifyType The type of change concerning the
+ database. See
+ EFI_HII_DATABASE_NOTIFY_TYPE.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_HII_DATABASE_NOTIFY)(
+ IN UINT8 PackageType,
+ IN CONST EFI_GUID *PackageGuid,
+ IN CONST EFI_HII_PACKAGE_HEADER *Package,
+ IN EFI_HII_HANDLE Handle,
+ IN EFI_HII_DATABASE_NOTIFY_TYPE NotifyType
+ );
+
+/**
+
+ This function adds the packages in the package list to the
+ database and returns a handle. If there is a
+ EFI_DEVICE_PATH_PROTOCOL associated with the DriverHandle, then
+ this function will create a package of type
+ EFI_PACKAGE_TYPE_DEVICE_PATH and add it to the package list. For
+ each package in the package list, registered functions with the
+ notification type NEW_PACK and having the same package type will
+ be called. For each call to NewPackageList(), there should be a
+ corresponding call to
+ EFI_HII_DATABASE_PROTOCOL.RemovePackageList().
+
+ @param This A pointer to the EFI_HII_DATABASE_PROTOCOL instance.
+
+ @param PackageList A pointer to an EFI_HII_PACKAGE_LIST_HEADER structure.
+
+ @param DriverHandle Associate the package list with this EFI handle.
+ If a NULL is specified, this data will not be associate
+ with any drivers and cannot have a callback induced.
+
+ @param Handle A pointer to the EFI_HII_HANDLE instance.
+
+ @retval EFI_SUCCESS The package list associated with the
+ Handle was added to the HII database.
+
+ @retval EFI_OUT_OF_RESOURCES Unable to allocate necessary
+ resources for the new database
+ contents.
+
+ @retval EFI_INVALID_PARAMETER PackageList is NULL, or Handle is NULL.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_HII_DATABASE_NEW_PACK)(
+ IN CONST EFI_HII_DATABASE_PROTOCOL *This,
+ IN CONST EFI_HII_PACKAGE_LIST_HEADER *PackageList,
+ IN EFI_HANDLE DriverHandle OPTIONAL,
+ OUT EFI_HII_HANDLE *Handle
+ );
+
+/**
+
+ This function removes the package list that is associated with a
+ handle Handle from the HII database. Before removing the
+ package, any registered functions with the notification type
+ REMOVE_PACK and the same package type will be called. For each
+ call to EFI_HII_DATABASE_PROTOCOL.NewPackageList(), there should
+ be a corresponding call to RemovePackageList.
+
+ @param This A pointer to the EFI_HII_DATABASE_PROTOCOL instance.
+
+ @param Handle The handle that was registered to the data
+ that is requested for removal.
+
+ @retval EFI_SUCCESS The data associated with the Handle was
+ removed from the HII database.
+ @retval EFI_NOT_FOUND The specified Handle is not in database.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_HII_DATABASE_REMOVE_PACK)(
+ IN CONST EFI_HII_DATABASE_PROTOCOL *This,
+ IN EFI_HII_HANDLE Handle
+ );
+
+/**
+
+ This function updates the existing package list (which has the
+ specified Handle) in the HII databases, using the new package
+ list specified by PackageList. The update process has the
+ following steps: Collect all the package types in the package
+ list specified by PackageList. A package type consists of the
+ Type field of EFI_HII_PACKAGE_HEADER and, if the Type is
+ EFI_HII_PACKAGE_TYPE_GUID, the Guid field, as defined in
+ EFI_HII_PACKAGE_GUID_HEADER. Iterate through the packages within
+ the existing package list in the HII database specified by
+ Handle. If a package's type matches one of the collected types collected
+ in step 1, then perform the following steps:
+ - Call any functions registered with the notification type
+ REMOVE_PACK.
+ - Remove the package from the package list and the HII
+ database.
+ Add all of the packages within the new package list specified
+ by PackageList, using the following steps:
+ - Add the package to the package list and the HII database.
+ - Call any functions registered with the notification type
+ ADD_PACK.
+
+ @param This A pointer to the EFI_HII_DATABASE_PROTOCOL instance.
+
+ @param Handle The handle that was registered to the data
+ that is requested for removal.
+
+ @param PackageList A pointer to an EFI_HII_PACKAGE_LIST
+ package.
+
+ @retval EFI_SUCCESS The HII database was successfully updated.
+
+ @retval EFI_OUT_OF_RESOURCES Unable to allocate enough memory
+ for the updated database.
+
+ @retval EFI_INVALID_PARAMETER PackageList was NULL.
+ @retval EFI_NOT_FOUND The specified Handle is not in database.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_HII_DATABASE_UPDATE_PACK)(
+ IN CONST EFI_HII_DATABASE_PROTOCOL *This,
+ IN EFI_HII_HANDLE Handle,
+ IN CONST EFI_HII_PACKAGE_LIST_HEADER *PackageList
+ );
+
+/**
+
+ This function returns a list of the package handles of the
+ specified type that are currently active in the database. The
+ pseudo-type EFI_HII_PACKAGE_TYPE_ALL will cause all package
+ handles to be listed.
+
+ @param This A pointer to the EFI_HII_DATABASE_PROTOCOL instance.
+
+ @param PackageType Specifies the package type of the packages
+ to list or EFI_HII_PACKAGE_TYPE_ALL for
+ all packages to be listed.
+
+ @param PackageGuid If PackageType is
+ EFI_HII_PACKAGE_TYPE_GUID, then this is
+ the pointer to the GUID which must match
+ the Guid field of
+ EFI_HII_PACKAGE_GUID_HEADER. Otherwise, it
+ must be NULL.
+
+ @param HandleBufferLength On input, a pointer to the length
+ of the handle buffer. On output,
+ the length of the handle buffer
+ that is required for the handles found.
+
+ @param Handle An array of EFI_HII_HANDLE instances returned.
+
+ @retval EFI_SUCCESS The matching handles are outputted successfully.
+ HandleBufferLength is updated with the actual length.
+ @retval EFI_BUFFER_TOO_SMALL The HandleBufferLength parameter
+ indicates that Handle is too
+ small to support the number of
+ handles. HandleBufferLength is
+ updated with a value that will
+ enable the data to fit.
+ @retval EFI_NOT_FOUND No matching handle could be found in database.
+ @retval EFI_INVALID_PARAMETER HandleBufferLength was NULL.
+ @retval EFI_INVALID_PARAMETER The value referenced by HandleBufferLength was not
+ zero and Handle was NULL.
+ @retval EFI_INVALID_PARAMETER PackageType is not a EFI_HII_PACKAGE_TYPE_GUID but
+ PackageGuid is not NULL, PackageType is a EFI_HII_
+ PACKAGE_TYPE_GUID but PackageGuid is NULL.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_HII_DATABASE_LIST_PACKS)(
+ IN CONST EFI_HII_DATABASE_PROTOCOL *This,
+ IN UINT8 PackageType,
+ IN CONST EFI_GUID *PackageGuid,
+ IN OUT UINTN *HandleBufferLength,
+ OUT EFI_HII_HANDLE *Handle
+ );
+
+/**
+
+ This function will export one or all package lists in the
+ database to a buffer. For each package list exported, this
+ function will call functions registered with EXPORT_PACK and
+ then copy the package list to the buffer. The registered
+ functions may call EFI_HII_DATABASE_PROTOCOL.UpdatePackageList()
+ to modify the package list before it is copied to the buffer. If
+ the specified BufferSize is too small, then the status
+ EFI_OUT_OF_RESOURCES will be returned and the actual package
+ size will be returned in BufferSize.
+
+ @param This A pointer to the EFI_HII_DATABASE_PROTOCOL instance.
+
+
+ @param Handle An EFI_HII_HANDLE that corresponds to the
+ desired package list in the HII database to
+ export or NULL to indicate all package lists
+ should be exported.
+
+ @param BufferSize On input, a pointer to the length of the
+ buffer. On output, the length of the
+ buffer that is required for the exported
+ data.
+
+ @param Buffer A pointer to a buffer that will contain the
+ results of the export function.
+
+
+ @retval EFI_SUCCESS Package exported.
+
+ @retval EFI_OUT_OF_RESOURCES BufferSize is too small to hold the package.
+
+ @retval EFI_NOT_FOUND The specified Handle could not be found in the
+ current database.
+
+ @retval EFI_INVALID_PARAMETER BufferSize was NULL.
+
+ @retval EFI_INVALID_PARAMETER The value referenced by BufferSize was not zero
+ and Buffer was NULL.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_HII_DATABASE_EXPORT_PACKS)(
+ IN CONST EFI_HII_DATABASE_PROTOCOL *This,
+ IN EFI_HII_HANDLE Handle,
+ IN OUT UINTN *BufferSize,
+ OUT EFI_HII_PACKAGE_LIST_HEADER *Buffer
+ );
+
+/**
+
+
+ This function registers a function which will be called when
+ specified actions related to packages of the specified type
+ occur in the HII database. By registering a function, other
+ HII-related drivers are notified when specific package types
+ are added, removed or updated in the HII database. Each driver
+ or application which registers a notification should use
+ EFI_HII_DATABASE_PROTOCOL.UnregisterPackageNotify() before
+ exiting.
+
+
+ @param This A pointer to the EFI_HII_DATABASE_PROTOCOL instance.
+
+ @param PackageType The package type. See
+ EFI_HII_PACKAGE_TYPE_x in EFI_HII_PACKAGE_HEADER.
+
+ @param PackageGuid If PackageType is
+ EFI_HII_PACKAGE_TYPE_GUID, then this is
+ the pointer to the GUID which must match
+ the Guid field of
+ EFI_HII_PACKAGE_GUID_HEADER. Otherwise, it
+ must be NULL.
+
+ @param PackageNotifyFn Points to the function to be called
+ when the event specified by
+ NotificationType occurs. See
+ EFI_HII_DATABASE_NOTIFY.
+
+ @param NotifyType Describes the types of notification which
+ this function will be receiving. See
+ EFI_HII_DATABASE_NOTIFY_TYPE for a
+ list of types.
+
+ @param NotifyHandle Points to the unique handle assigned to
+ the registered notification. Can be used
+ in EFI_HII_DATABASE_PROTOCOL.UnregisterPack
+ to stop notifications.
+
+
+ @retval EFI_SUCCESS Notification registered successfully.
+
+ @retval EFI_OUT_OF_RESOURCES Unable to allocate necessary
+ data structures.
+
+ @retval EFI_INVALID_PARAMETER PackageGuid is not NULL when
+ PackageType is not
+ EFI_HII_PACKAGE_TYPE_GUID.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_HII_DATABASE_REGISTER_NOTIFY)(
+ IN CONST EFI_HII_DATABASE_PROTOCOL *This,
+ IN UINT8 PackageType,
+ IN CONST EFI_GUID *PackageGuid,
+ IN EFI_HII_DATABASE_NOTIFY PackageNotifyFn,
+ IN EFI_HII_DATABASE_NOTIFY_TYPE NotifyType,
+ OUT EFI_HANDLE *NotifyHandle
+ );
+
+/**
+
+ Removes the specified HII database package-related notification.
+
+ @param This A pointer to the EFI_HII_DATABASE_PROTOCOL instance.
+
+ @param NotificationHandle The handle of the notification
+ function being unregistered.
+
+ @retval EFI_SUCCESS Successsfully unregistered the notification.
+
+ @retval EFI_NOT_FOUND The incoming notification handle does not exist
+ in the current hii database.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_HII_DATABASE_UNREGISTER_NOTIFY)(
+ IN CONST EFI_HII_DATABASE_PROTOCOL *This,
+ IN EFI_HANDLE NotificationHandle
+ );
+
+/**
+
+ This routine retrieves an array of GUID values for each keyboard
+ layout that was previously registered in the system.
+
+ @param This A pointer to the EFI_HII_PROTOCOL instance.
+
+ @param KeyGuidBufferLength On input, a pointer to the length
+ of the keyboard GUID buffer. On
+ output, the length of the handle
+ buffer that is required for the
+ handles found.
+
+ @param KeyGuidBuffer An array of keyboard layout GUID
+ instances returned.
+
+ @retval EFI_SUCCESS KeyGuidBuffer was updated successfully.
+
+ @retval EFI_BUFFER_TOO_SMALL The KeyGuidBufferLength
+ parameter indicates that
+ KeyGuidBuffer is too small to
+ support the number of GUIDs.
+ KeyGuidBufferLength is updated
+ with a value that will enable
+ the data to fit.
+ @retval EFI_INVALID_PARAMETER The KeyGuidBufferLength is NULL.
+ @retval EFI_INVALID_PARAMETER The value referenced by
+ KeyGuidBufferLength is not
+ zero and KeyGuidBuffer is NULL.
+ @retval EFI_NOT_FOUND There was no keyboard layout.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_HII_FIND_KEYBOARD_LAYOUTS)(
+ IN CONST EFI_HII_DATABASE_PROTOCOL *This,
+ IN OUT UINT16 *KeyGuidBufferLength,
+ OUT EFI_GUID *KeyGuidBuffer
+ );
+
+/**
+
+ This routine retrieves the requested keyboard layout. The layout
+ is a physical description of the keys on a keyboard, and the
+ character(s) that are associated with a particular set of key
+ strokes.
+
+ @param This A pointer to the EFI_HII_PROTOCOL instance.
+
+ @param KeyGuid A pointer to the unique ID associated with a
+ given keyboard layout. If KeyGuid is NULL then
+ the current layout will be retrieved.
+
+ @param KeyboardLayoutLength On input, a pointer to the length of the
+ KeyboardLayout buffer. On output, the length of
+ the data placed into KeyboardLayout.
+
+ @param KeyboardLayout A pointer to a buffer containing the
+ retrieved keyboard layout.
+
+ @retval EFI_SUCCESS The keyboard layout was retrieved
+ successfully.
+
+ @retval EFI_NOT_FOUND The requested keyboard layout was not found.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_HII_GET_KEYBOARD_LAYOUT)(
+ IN CONST EFI_HII_DATABASE_PROTOCOL *This,
+ IN CONST EFI_GUID *KeyGuid,
+ IN OUT UINT16 *KeyboardLayoutLength,
+ OUT EFI_HII_KEYBOARD_LAYOUT *KeyboardLayout
+ );
+
+/**
+
+ This routine sets the default keyboard layout to the one
+ referenced by KeyGuid. When this routine is called, an event
+ will be signaled of the EFI_HII_SET_KEYBOARD_LAYOUT_EVENT_GUID
+ group type. This is so that agents which are sensitive to the
+ current keyboard layout being changed can be notified of this
+ change.
+
+ @param This A pointer to the EFI_HII_PROTOCOL instance.
+
+ @param KeyGuid A pointer to the unique ID associated with a
+ given keyboard layout.
+
+ @retval EFI_SUCCESS The current keyboard layout was successfully set.
+
+ @retval EFI_NOT_FOUND The referenced keyboard layout was not
+ found, so action was taken.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_HII_SET_KEYBOARD_LAYOUT)(
+ IN CONST EFI_HII_DATABASE_PROTOCOL *This,
+ IN CONST EFI_GUID *KeyGuid
+ );
+
+/**
+
+ Return the EFI handle associated with a package list.
+
+ @param This A pointer to the EFI_HII_PROTOCOL instance.
+
+ @param PackageListHandle An EFI_HII_HANDLE that corresponds
+ to the desired package list in the
+ HIIdatabase.
+
+ @param DriverHandle On return, contains the EFI_HANDLE which
+ was registered with the package list in
+ NewPackageList().
+
+ @retval EFI_SUCCESS The DriverHandle was returned successfully.
+
+ @retval EFI_INVALID_PARAMETER The PackageListHandle was not valid.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_HII_DATABASE_GET_PACK_HANDLE)(
+ IN CONST EFI_HII_DATABASE_PROTOCOL *This,
+ IN EFI_HII_HANDLE PackageListHandle,
+ OUT EFI_HANDLE *DriverHandle
+ );
+
+///
+/// Database manager for HII-related data structures.
+///
+struct _EFI_HII_DATABASE_PROTOCOL {
+ EFI_HII_DATABASE_NEW_PACK NewPackageList;
+ EFI_HII_DATABASE_REMOVE_PACK RemovePackageList;
+ EFI_HII_DATABASE_UPDATE_PACK UpdatePackageList;
+ EFI_HII_DATABASE_LIST_PACKS ListPackageLists;
+ EFI_HII_DATABASE_EXPORT_PACKS ExportPackageLists;
+ EFI_HII_DATABASE_REGISTER_NOTIFY RegisterPackageNotify;
+ EFI_HII_DATABASE_UNREGISTER_NOTIFY UnregisterPackageNotify;
+ EFI_HII_FIND_KEYBOARD_LAYOUTS FindKeyboardLayouts;
+ EFI_HII_GET_KEYBOARD_LAYOUT GetKeyboardLayout;
+ EFI_HII_SET_KEYBOARD_LAYOUT SetKeyboardLayout;
+ EFI_HII_DATABASE_GET_PACK_HANDLE GetPackageListHandle;
+};
+
+extern EFI_GUID gEfiHiiDatabaseProtocolGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/HiiFont.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/HiiFont.h
new file mode 100644
index 0000000000..392352d6b3
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/HiiFont.h
@@ -0,0 +1,464 @@
+/** @file
+ The file provides services to retrieve font information.
+
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Revision Reference:
+ This Protocol was introduced in UEFI Specification 2.1.
+
+**/
+
+#ifndef __HII_FONT_H__
+#define __HII_FONT_H__
+
+#include
+#include
+
+#define EFI_HII_FONT_PROTOCOL_GUID \
+{ 0xe9ca4775, 0x8657, 0x47fc, { 0x97, 0xe7, 0x7e, 0xd6, 0x5a, 0x8, 0x43, 0x24 } }
+
+typedef struct _EFI_HII_FONT_PROTOCOL EFI_HII_FONT_PROTOCOL;
+
+typedef VOID *EFI_FONT_HANDLE;
+
+///
+/// EFI_HII_OUT_FLAGS.
+///
+typedef UINT32 EFI_HII_OUT_FLAGS;
+
+#define EFI_HII_OUT_FLAG_CLIP 0x00000001
+#define EFI_HII_OUT_FLAG_WRAP 0x00000002
+#define EFI_HII_OUT_FLAG_CLIP_CLEAN_Y 0x00000004
+#define EFI_HII_OUT_FLAG_CLIP_CLEAN_X 0x00000008
+#define EFI_HII_OUT_FLAG_TRANSPARENT 0x00000010
+#define EFI_HII_IGNORE_IF_NO_GLYPH 0x00000020
+#define EFI_HII_IGNORE_LINE_BREAK 0x00000040
+#define EFI_HII_DIRECT_TO_SCREEN 0x00000080
+
+/**
+ Definition of EFI_HII_ROW_INFO.
+**/
+typedef struct _EFI_HII_ROW_INFO {
+ ///
+ /// The index of the first character in the string which is displayed on the line.
+ ///
+ UINTN StartIndex;
+ ///
+ /// The index of the last character in the string which is displayed on the line.
+ /// If this is the same as StartIndex, then no characters are displayed.
+ ///
+ UINTN EndIndex;
+ UINTN LineHeight; ///< The height of the line, in pixels.
+ UINTN LineWidth; ///< The width of the text on the line, in pixels.
+
+ ///
+ /// The font baseline offset in pixels from the bottom of the row, or 0 if none.
+ ///
+ UINTN BaselineOffset;
+} EFI_HII_ROW_INFO;
+
+///
+/// Font info flag. All flags (FONT, SIZE, STYLE, and COLOR) are defined.
+/// They are defined as EFI_FONT_INFO_***
+///
+typedef UINT32 EFI_FONT_INFO_MASK;
+
+#define EFI_FONT_INFO_SYS_FONT 0x00000001
+#define EFI_FONT_INFO_SYS_SIZE 0x00000002
+#define EFI_FONT_INFO_SYS_STYLE 0x00000004
+#define EFI_FONT_INFO_SYS_FORE_COLOR 0x00000010
+#define EFI_FONT_INFO_SYS_BACK_COLOR 0x00000020
+#define EFI_FONT_INFO_RESIZE 0x00001000
+#define EFI_FONT_INFO_RESTYLE 0x00002000
+#define EFI_FONT_INFO_ANY_FONT 0x00010000
+#define EFI_FONT_INFO_ANY_SIZE 0x00020000
+#define EFI_FONT_INFO_ANY_STYLE 0x00040000
+
+//
+// EFI_FONT_INFO
+//
+typedef struct {
+ EFI_HII_FONT_STYLE FontStyle;
+ UINT16 FontSize; ///< character cell height in pixels
+ CHAR16 FontName[1];
+} EFI_FONT_INFO;
+
+/**
+ Describes font output-related information.
+
+ This structure is used for describing the way in which a string
+ should be rendered in a particular font. FontInfo specifies the
+ basic font information and ForegroundColor and BackgroundColor
+ specify the color in which they should be displayed. The flags
+ in FontInfoMask describe where the system default should be
+ supplied instead of the specified information. The flags also
+ describe what options can be used to make a match between the
+ font requested and the font available.
+**/
+typedef struct _EFI_FONT_DISPLAY_INFO {
+ EFI_GRAPHICS_OUTPUT_BLT_PIXEL ForegroundColor;
+ EFI_GRAPHICS_OUTPUT_BLT_PIXEL BackgroundColor;
+ EFI_FONT_INFO_MASK FontInfoMask;
+ EFI_FONT_INFO FontInfo;
+} EFI_FONT_DISPLAY_INFO;
+
+/**
+
+ This function renders a string to a bitmap or the screen using
+ the specified font, color and options. It either draws the
+ string and glyphs on an existing bitmap, allocates a new bitmap,
+ or uses the screen. The strings can be clipped or wrapped.
+ Optionally, the function also returns the information about each
+ row and the character position on that row. If
+ EFI_HII_OUT_FLAG_CLIP is set, then text will be formatted only
+ based on explicit line breaks and all pixels which would lie
+ outside the bounding box specified by Width and Height are
+ ignored. The information in the RowInfoArray only describes
+ characters which are at least partially displayed. For the final
+ row, the LineHeight and BaseLine may describe pixels that are
+ outside the limit specified by Height (unless
+ EFI_HII_OUT_FLAG_CLIP_CLEAN_Y is specified) even though those
+ pixels were not drawn. The LineWidth may describe pixels which
+ are outside the limit specified by Width (unless
+ EFI_HII_OUT_FLAG_CLIP_CLEAN_X is specified) even though those
+ pixels were not drawn. If EFI_HII_OUT_FLAG_CLIP_CLEAN_X is set,
+ then it modifies the behavior of EFI_HII_OUT_FLAG_CLIP so that
+ if a character's right-most on pixel cannot fit, then it will
+ not be drawn at all. This flag requires that
+ EFI_HII_OUT_FLAG_CLIP be set. If EFI_HII_OUT_FLAG_CLIP_CLEAN_Y
+ is set, then it modifies the behavior of EFI_HII_OUT_FLAG_CLIP
+ so that if a row's bottom-most pixel cannot fit, then it will
+ not be drawn at all. This flag requires that
+ EFI_HII_OUT_FLAG_CLIP be set. If EFI_HII_OUT_FLAG_WRAP is set,
+ then text will be wrapped at the right-most line-break
+ opportunity prior to a character whose right-most extent would
+ exceed Width. If no line-break opportunity can be found, then
+ the text will behave as if EFI_HII_OUT_FLAG_CLIP_CLEAN_X is set.
+ This flag cannot be used with EFI_HII_OUT_FLAG_CLIP_CLEAN_X. If
+ EFI_HII_OUT_FLAG_TRANSPARENT is set, then BackgroundColor is
+ ignored and all 'off' pixels in the character's drawn
+ will use the pixel value from Blt. This flag cannot be used if
+ Blt is NULL upon entry. If EFI_HII_IGNORE_IF_NO_GLYPH is set,
+ then characters which have no glyphs are not drawn. Otherwise,
+ they are replaced with Unicode character code 0xFFFD (REPLACEMENT
+ CHARACTER). If EFI_HII_IGNORE_LINE_BREAK is set, then explicit
+ line break characters will be ignored. If
+ EFI_HII_DIRECT_TO_SCREEN is set, then the string will be written
+ directly to the output device specified by Screen. Otherwise the
+ string will be rendered to the bitmap specified by Bitmap.
+
+ @param This A pointer to the EFI_HII_FONT_PROTOCOL instance.
+
+ @param Flags Describes how the string is to be drawn.
+
+ @param String Points to the null-terminated string to be
+
+ @param StringInfo Points to the string output information,
+ including the color and font. If NULL, then
+ the string will be output in the default
+ system font and color.
+
+ @param Blt If this points to a non-NULL on entry, this points
+ to the image, which is Width pixels wide and
+ Height pixels high. The string will be drawn onto
+ this image and EFI_HII_OUT_FLAG_CLIP is implied.
+ If this points to a NULL on entry, then a buffer
+ will be allocated to hold the generated image and
+ the pointer updated on exit. It is the caller's
+ responsibility to free this buffer.
+
+ @param BltX, BltY Specifies the offset from the left and top
+ edge of the image of the first character
+ cell in the image.
+
+ @param RowInfoArray If this is non-NULL on entry, then on
+ exit, this will point to an allocated buffer
+ containing row information and
+ RowInfoArraySize will be updated to contain
+ the number of elements. This array describes
+ the characters that were at least partially
+ drawn and the heights of the rows. It is the
+ caller's responsibility to free this buffer.
+
+ @param RowInfoArraySize If this is non-NULL on entry, then on
+ exit it contains the number of
+ elements in RowInfoArray.
+
+ @param ColumnInfoArray If this is non-NULL, then on return it
+ will be filled with the horizontal
+ offset for each character in the
+ string on the row where it is
+ displayed. Non-printing characters
+ will have the offset ~0. The caller is
+ responsible for allocating a buffer large
+ enough so that there is one entry for
+ each character in the string, not
+ including the null-terminator. It is
+ possible when character display is
+ normalized that some character cells
+ overlap.
+
+ @retval EFI_SUCCESS The string was successfully updated.
+
+ @retval EFI_OUT_OF_RESOURCES Unable to allocate an output buffer for RowInfoArray or Blt.
+
+ @retval EFI_INVALID_PARAMETER The String or Blt was NULL.
+
+ @retval EFI_INVALID_PARAMETER Flags were invalid combination.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_HII_STRING_TO_IMAGE)(
+ IN CONST EFI_HII_FONT_PROTOCOL *This,
+ IN EFI_HII_OUT_FLAGS Flags,
+ IN CONST EFI_STRING String,
+ IN CONST EFI_FONT_DISPLAY_INFO *StringInfo,
+ IN OUT EFI_IMAGE_OUTPUT **Blt,
+ IN UINTN BltX,
+ IN UINTN BltY,
+ OUT EFI_HII_ROW_INFO **RowInfoArray OPTIONAL,
+ OUT UINTN *RowInfoArraySize OPTIONAL,
+ OUT UINTN *ColumnInfoArray OPTIONAL
+ );
+
+/**
+
+ This function renders a string as a bitmap or to the screen
+ and can clip or wrap the string. The bitmap is either supplied
+ by the caller or allocated by the function. The
+ strings are drawn with the font, size and style specified and
+ can be drawn transparently or opaquely. The function can also
+ return information about each row and each character's
+ position on the row. If EFI_HII_OUT_FLAG_CLIP is set, then
+ text will be formatted based only on explicit line breaks, and
+ all pixels that would lie outside the bounding box specified
+ by Width and Height are ignored. The information in the
+ RowInfoArray only describes characters which are at least
+ partially displayed. For the final row, the LineHeight and
+ BaseLine may describe pixels which are outside the limit
+ specified by Height (unless EFI_HII_OUT_FLAG_CLIP_CLEAN_Y is
+ specified) even though those pixels were not drawn. If
+ EFI_HII_OUT_FLAG_CLIP_CLEAN_X is set, then it modifies the
+ behavior of EFI_HII_OUT_FLAG_CLIP so that if a character's
+ right-most on pixel cannot fit, then it will not be drawn at
+ all. This flag requires that EFI_HII_OUT_FLAG_CLIP be set. If
+ EFI_HII_OUT_FLAG_CLIP_CLEAN_Y is set, then it modifies the
+ behavior of EFI_HII_OUT_FLAG_CLIP so that if a row's bottom
+ most pixel cannot fit, then it will not be drawn at all. This
+ flag requires that EFI_HII_OUT_FLAG_CLIP be set. If
+ EFI_HII_OUT_FLAG_WRAP is set, then text will be wrapped at the
+ right-most line-break opportunity prior to a character whose
+ right-most extent would exceed Width. If no line-break
+ opportunity can be found, then the text will behave as if
+ EFI_HII_OUT_FLAG_CLIP_CLEAN_X is set. This flag cannot be used
+ with EFI_HII_OUT_FLAG_CLIP_CLEAN_X. If
+ EFI_HII_OUT_FLAG_TRANSPARENT is set, then BackgroundColor is
+ ignored and all off" pixels in the character's glyph will
+ use the pixel value from Blt. This flag cannot be used if Blt
+ is NULL upon entry. If EFI_HII_IGNORE_IF_NO_GLYPH is set, then
+ characters which have no glyphs are not drawn. Otherwise, they
+ are replaced with Unicode character code 0xFFFD (REPLACEMENT
+ CHARACTER). If EFI_HII_IGNORE_LINE_BREAK is set, then explicit
+ line break characters will be ignored. If
+ EFI_HII_DIRECT_TO_SCREEN is set, then the string will be
+ written directly to the output device specified by Screen.
+ Otherwise the string will be rendered to the bitmap specified
+ by Bitmap.
+
+
+ @param This A pointer to the EFI_HII_FONT_PROTOCOL instance.
+
+ @param Flags Describes how the string is to be drawn.
+
+ @param PackageList
+ The package list in the HII database to
+ search for the specified string.
+
+ @param StringId The string's id, which is unique within
+ PackageList.
+
+ @param Language Points to the language for the retrieved
+ string. If NULL, then the current system
+ language is used.
+
+ @param StringInfo Points to the string output information,
+ including the color and font. If NULL, then
+ the string will be output in the default
+ system font and color.
+
+ @param Blt If this points to a non-NULL on entry, this points
+ to the image, which is Width pixels wide and
+ Height pixels high. The string will be drawn onto
+ this image and EFI_HII_OUT_FLAG_CLIP is implied.
+ If this points to a NULL on entry, then a buffer
+ will be allocated to hold the generated image and
+ the pointer updated on exit. It is the caller's
+ responsibility to free this buffer.
+
+ @param BltX, BltY Specifies the offset from the left and top
+ edge of the output image of the first
+ character cell in the image.
+
+ @param RowInfoArray If this is non-NULL on entry, then on
+ exit, this will point to an allocated
+ buffer containing row information and
+ RowInfoArraySize will be updated to
+ contain the number of elements. This array
+ describes the characters which were at
+ least partially drawn and the heights of
+ the rows. It is the caller's
+ responsibility to free this buffer.
+
+ @param RowInfoArraySize If this is non-NULL on entry, then on
+ exit it contains the number of
+ elements in RowInfoArray.
+
+ @param ColumnInfoArray If non-NULL, on return it is filled
+ with the horizontal offset for each
+ character in the string on the row
+ where it is displayed. Non-printing
+ characters will have the offset ~0.
+ The caller is responsible to allocate
+ a buffer large enough so that there is
+ one entry for each character in the
+ string, not including the
+ null-terminator. It is possible when
+ character display is normalized that
+ some character cells overlap.
+
+
+ @retval EFI_SUCCESS The string was successfully updated.
+
+ @retval EFI_OUT_OF_RESOURCES Unable to allocate an output
+ buffer for RowInfoArray or Blt.
+
+ @retval EFI_INVALID_PARAMETER The String, or Blt, or Height, or
+ Width was NULL.
+ @retval EFI_INVALID_PARAMETER The Blt or PackageList was NULL.
+ @retval EFI_INVALID_PARAMETER Flags were invalid combination.
+ @retval EFI_NOT_FOUND The specified PackageList is not in the Database,
+ or the stringid is not in the specified PackageList.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_HII_STRING_ID_TO_IMAGE)(
+ IN CONST EFI_HII_FONT_PROTOCOL *This,
+ IN EFI_HII_OUT_FLAGS Flags,
+ IN EFI_HII_HANDLE PackageList,
+ IN EFI_STRING_ID StringId,
+ IN CONST CHAR8 *Language,
+ IN CONST EFI_FONT_DISPLAY_INFO *StringInfo OPTIONAL,
+ IN OUT EFI_IMAGE_OUTPUT **Blt,
+ IN UINTN BltX,
+ IN UINTN BltY,
+ OUT EFI_HII_ROW_INFO **RowInfoArray OPTIONAL,
+ OUT UINTN *RowInfoArraySize OPTIONAL,
+ OUT UINTN *ColumnInfoArray OPTIONAL
+ );
+
+/**
+
+ Convert the glyph for a single character into a bitmap.
+
+ @param This A pointer to the EFI_HII_FONT_PROTOCOL instance.
+
+ @param Char The character to retrieve.
+
+ @param StringInfo Points to the string font and color
+ information or NULL if the string should use
+ the default system font and color.
+
+ @param Blt This must point to a NULL on entry. A buffer will
+ be allocated to hold the output and the pointer
+ updated on exit. It is the caller's responsibility
+ to free this buffer.
+
+ @param Baseline The number of pixels from the bottom of the bitmap
+ to the baseline.
+
+
+ @retval EFI_SUCCESS The glyph bitmap created.
+
+ @retval EFI_OUT_OF_RESOURCES Unable to allocate the output buffer Blt.
+
+ @retval EFI_WARN_UNKNOWN_GLYPH The glyph was unknown and was
+ replaced with the glyph for
+ Unicode character code 0xFFFD.
+
+ @retval EFI_INVALID_PARAMETER Blt is NULL, or Width is NULL, or
+ Height is NULL
+
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_HII_GET_GLYPH)(
+ IN CONST EFI_HII_FONT_PROTOCOL *This,
+ IN CONST CHAR16 Char,
+ IN CONST EFI_FONT_DISPLAY_INFO *StringInfo,
+ OUT EFI_IMAGE_OUTPUT **Blt,
+ OUT UINTN *Baseline OPTIONAL
+ );
+
+/**
+
+ This function iterates through fonts which match the specified
+ font, using the specified criteria. If String is non-NULL, then
+ all of the characters in the string must exist in order for a
+ candidate font to be returned.
+
+ @param This A pointer to the EFI_HII_FONT_PROTOCOL instance.
+
+ @param FontHandle On entry, points to the font handle returned
+ by a previous call to GetFontInfo() or NULL
+ to start with the first font. On return,
+ points to the returned font handle or points
+ to NULL if there are no more matching fonts.
+
+ @param StringInfoIn Upon entry, points to the font to return
+ information about. If NULL, then the information
+ about the system default font will be returned.
+
+ @param StringInfoOut Upon return, contains the matching font's information.
+ If NULL, then no information is returned. This buffer
+ is allocated with a call to the Boot Service AllocatePool().
+ It is the caller's responsibility to call the Boot
+ Service FreePool() when the caller no longer requires
+ the contents of StringInfoOut.
+
+ @param String Points to the string which will be tested to
+ determine if all characters are available. If
+ NULL, then any font is acceptable.
+
+ @retval EFI_SUCCESS Matching font returned successfully.
+
+ @retval EFI_NOT_FOUND No matching font was found.
+
+ @retval EFI_OUT_OF_RESOURCES There were insufficient resources to complete the request.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_HII_GET_FONT_INFO)(
+ IN CONST EFI_HII_FONT_PROTOCOL *This,
+ IN OUT EFI_FONT_HANDLE *FontHandle,
+ IN CONST EFI_FONT_DISPLAY_INFO *StringInfoIn OPTIONAL,
+ OUT EFI_FONT_DISPLAY_INFO **StringInfoOut,
+ IN CONST EFI_STRING String OPTIONAL
+ );
+
+///
+/// The protocol provides the service to retrieve the font informations.
+///
+struct _EFI_HII_FONT_PROTOCOL {
+ EFI_HII_STRING_TO_IMAGE StringToImage;
+ EFI_HII_STRING_ID_TO_IMAGE StringIdToImage;
+ EFI_HII_GET_GLYPH GetGlyph;
+ EFI_HII_GET_FONT_INFO GetFontInfo;
+};
+
+extern EFI_GUID gEfiHiiFontProtocolGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/HiiImage.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/HiiImage.h
new file mode 100644
index 0000000000..34e5acc1ec
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/HiiImage.h
@@ -0,0 +1,346 @@
+/** @file
+ The file provides services to access to images in the images database.
+
+ Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Revision Reference:
+ This Protocol was introduced in UEFI Specification 2.1.
+
+**/
+
+#ifndef __HII_IMAGE_H__
+#define __HII_IMAGE_H__
+
+#include
+
+#define EFI_HII_IMAGE_PROTOCOL_GUID \
+ { 0x31a6406a, 0x6bdf, 0x4e46, { 0xb2, 0xa2, 0xeb, 0xaa, 0x89, 0xc4, 0x9, 0x20 } }
+
+typedef struct _EFI_HII_IMAGE_PROTOCOL EFI_HII_IMAGE_PROTOCOL;
+
+///
+/// Flags in EFI_IMAGE_INPUT
+///
+#define EFI_IMAGE_TRANSPARENT 0x00000001
+
+/**
+
+ Definition of EFI_IMAGE_INPUT.
+
+ @param Flags Describe image characteristics. If
+ EFI_IMAGE_TRANSPARENT is set, then the image was
+ designed for transparent display.
+
+ @param Width Image width, in pixels.
+
+ @param Height Image height, in pixels.
+
+ @param Bitmap A pointer to the actual bitmap, organized left-to-right,
+ top-to-bottom. The size of the bitmap is
+ Width*Height*sizeof(EFI_GRAPHICS_OUTPUT_BLT_PIXEL).
+
+
+**/
+typedef struct _EFI_IMAGE_INPUT {
+ UINT32 Flags;
+ UINT16 Width;
+ UINT16 Height;
+ EFI_GRAPHICS_OUTPUT_BLT_PIXEL *Bitmap;
+} EFI_IMAGE_INPUT;
+
+/**
+
+ This function adds the image Image to the group of images
+ owned by PackageList, and returns a new image identifier
+ (ImageId).
+
+ @param This A pointer to the EFI_HII_IMAGE_PROTOCOL instance.
+
+ @param PackageList Handle of the package list where this image will be added.
+
+ @param ImageId On return, contains the new image id, which is
+ unique within PackageList.
+
+ @param Image Points to the image.
+
+ @retval EFI_SUCCESS The new image was added
+ successfully
+
+ @retval EFI_OUT_OF_RESOURCES Could not add the image.
+
+ @retval EFI_INVALID_PARAMETER Image is NULL or ImageId is
+ NULL.
+
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_HII_NEW_IMAGE)(
+ IN CONST EFI_HII_IMAGE_PROTOCOL *This,
+ IN EFI_HII_HANDLE PackageList,
+ OUT EFI_IMAGE_ID *ImageId,
+ IN CONST EFI_IMAGE_INPUT *Image
+ );
+
+/**
+
+ This function retrieves the image specified by ImageId which
+ is associated with the specified PackageList and copies it
+ into the buffer specified by Image. If the image specified by
+ ImageId is not present in the specified PackageList, then
+ EFI_NOT_FOUND is returned. If the buffer specified by
+ ImageSize is too small to hold the image, then
+ EFI_BUFFER_TOO_SMALL will be returned. ImageSize will be
+ updated to the size of buffer actually required to hold the
+ image.
+
+ @param This A pointer to the EFI_HII_IMAGE_PROTOCOL instance.
+
+ @param PackageList The package list in the HII database to
+ search for the specified image.
+
+ @param ImageId The image's id, which is unique within
+ PackageList.
+
+ @param Image Points to the new image.
+
+ @retval EFI_SUCCESS The image was returned successfully.
+
+ @retval EFI_NOT_FOUND The image specified by ImageId is not
+ available. Or The specified PackageList is not in the database.
+
+ @retval EFI_INVALID_PARAMETER The Image or Langugae was NULL.
+ @retval EFI_OUT_OF_RESOURCES The bitmap could not be retrieved because there was not
+ enough memory.
+
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_HII_GET_IMAGE)(
+ IN CONST EFI_HII_IMAGE_PROTOCOL *This,
+ IN EFI_HII_HANDLE PackageList,
+ IN EFI_IMAGE_ID ImageId,
+ OUT EFI_IMAGE_INPUT *Image
+ );
+
+/**
+
+ This function updates the image specified by ImageId in the
+ specified PackageListHandle to the image specified by Image.
+
+
+ @param This A pointer to the EFI_HII_IMAGE_PROTOCOL instance.
+
+ @param PackageList The package list containing the images.
+
+ @param ImageId The image id, which is unique within PackageList.
+
+ @param Image Points to the image.
+
+ @retval EFI_SUCCESS The image was successfully updated.
+
+ @retval EFI_NOT_FOUND The image specified by ImageId is not in the database.
+ The specified PackageList is not in the database.
+
+ @retval EFI_INVALID_PARAMETER The Image or Language was NULL.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_HII_SET_IMAGE)(
+ IN CONST EFI_HII_IMAGE_PROTOCOL *This,
+ IN EFI_HII_HANDLE PackageList,
+ IN EFI_IMAGE_ID ImageId,
+ IN CONST EFI_IMAGE_INPUT *Image
+ );
+
+///
+/// EFI_HII_DRAW_FLAGS describes how the image is to be drawn.
+/// These flags are defined as EFI_HII_DRAW_FLAG_***
+///
+typedef UINT32 EFI_HII_DRAW_FLAGS;
+
+#define EFI_HII_DRAW_FLAG_CLIP 0x00000001
+#define EFI_HII_DRAW_FLAG_TRANSPARENT 0x00000030
+#define EFI_HII_DRAW_FLAG_DEFAULT 0x00000000
+#define EFI_HII_DRAW_FLAG_FORCE_TRANS 0x00000010
+#define EFI_HII_DRAW_FLAG_FORCE_OPAQUE 0x00000020
+#define EFI_HII_DIRECT_TO_SCREEN 0x00000080
+
+/**
+
+ Definition of EFI_IMAGE_OUTPUT.
+
+ @param Width Width of the output image.
+
+ @param Height Height of the output image.
+
+ @param Bitmap Points to the output bitmap.
+
+ @param Screen Points to the EFI_GRAPHICS_OUTPUT_PROTOCOL which
+ describes the screen on which to draw the
+ specified image.
+
+**/
+typedef struct _EFI_IMAGE_OUTPUT {
+ UINT16 Width;
+ UINT16 Height;
+ union {
+ EFI_GRAPHICS_OUTPUT_BLT_PIXEL *Bitmap;
+ EFI_GRAPHICS_OUTPUT_PROTOCOL *Screen;
+ } Image;
+} EFI_IMAGE_OUTPUT;
+
+/**
+
+ This function renders an image to a bitmap or the screen using
+ the specified color and options. It draws the image on an
+ existing bitmap, allocates a new bitmap or uses the screen. The
+ images can be clipped. If EFI_HII_DRAW_FLAG_CLIP is set, then
+ all pixels drawn outside the bounding box specified by Width and
+ Height are ignored. If EFI_HII_DRAW_FLAG_TRANSPARENT is set,
+ then all 'off' pixels in the images drawn will use the
+ pixel value from Blt. This flag cannot be used if Blt is NULL
+ upon entry. If EFI_HII_DIRECT_TO_SCREEN is set, then the image
+ will be written directly to the output device specified by
+ Screen. Otherwise the image will be rendered to the bitmap
+ specified by Bitmap.
+
+
+ @param This A pointer to the EFI_HII_IMAGE_PROTOCOL instance.
+
+ @param Flags Describes how the image is to be drawn.
+ EFI_HII_DRAW_FLAGS is defined in Related
+ Definitions, below.
+
+ @param Image Points to the image to be displayed.
+
+ @param Blt If this points to a non-NULL on entry, this points
+ to the image, which is Width pixels wide and
+ Height pixels high. The image will be drawn onto
+ this image and EFI_HII_DRAW_FLAG_CLIP is implied.
+ If this points to a NULL on entry, then a buffer
+ will be allocated to hold the generated image and
+ the pointer updated on exit. It is the caller's
+ responsibility to free this buffer.
+
+ @param BltX, BltY Specifies the offset from the left and top
+ edge of the image of the first pixel in
+ the image.
+
+ @retval EFI_SUCCESS The image was successfully updated.
+
+ @retval EFI_OUT_OF_RESOURCES Unable to allocate an output
+ buffer for RowInfoArray or Blt.
+
+ @retval EFI_INVALID_PARAMETER The Image or Blt or Height or
+ Width was NULL.
+
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_HII_DRAW_IMAGE)(
+ IN CONST EFI_HII_IMAGE_PROTOCOL *This,
+ IN EFI_HII_DRAW_FLAGS Flags,
+ IN CONST EFI_IMAGE_INPUT *Image,
+ IN OUT EFI_IMAGE_OUTPUT **Blt,
+ IN UINTN BltX,
+ IN UINTN BltY
+ );
+
+/**
+
+ This function renders an image as a bitmap or to the screen and
+ can clip the image. The bitmap is either supplied by the caller
+ or else is allocated by the function. The images can be drawn
+ transparently or opaquely. If EFI_HII_DRAW_FLAG_CLIP is set,
+ then all pixels drawn outside the bounding box specified by
+ Width and Height are ignored. If EFI_HII_DRAW_FLAG_TRANSPARENT
+ is set, then all "off" pixels in the character's glyph will
+ use the pixel value from Blt. This flag cannot be used if Blt
+ is NULL upon entry. If EFI_HII_DIRECT_TO_SCREEN is set, then
+ the image will be written directly to the output device
+ specified by Screen. Otherwise the image will be rendered to
+ the bitmap specified by Bitmap.
+ This function renders an image to a bitmap or the screen using
+ the specified color and options. It draws the image on an
+ existing bitmap, allocates a new bitmap or uses the screen. The
+ images can be clipped. If EFI_HII_DRAW_FLAG_CLIP is set, then
+ all pixels drawn outside the bounding box specified by Width and
+ Height are ignored. The EFI_HII_DRAW_FLAG_TRANSPARENT flag
+ determines whether the image will be drawn transparent or
+ opaque. If EFI_HII_DRAW_FLAG_FORCE_TRANS is set, then the image
+ will be drawn so that all 'off' pixels in the image will
+ be drawn using the pixel value from Blt and all other pixels
+ will be copied. If EFI_HII_DRAW_FLAG_FORCE_OPAQUE is set, then
+ the image's pixels will be copied directly to the
+ destination. If EFI_HII_DRAW_FLAG_DEFAULT is set, then the image
+ will be drawn transparently or opaque, depending on the
+ image's transparency setting (see EFI_IMAGE_TRANSPARENT).
+ Images cannot be drawn transparently if Blt is NULL. If
+ EFI_HII_DIRECT_TO_SCREEN is set, then the image will be written
+ directly to the output device specified by Screen. Otherwise the
+ image will be rendered to the bitmap specified by Bitmap.
+
+ @param This A pointer to the EFI_HII_IMAGE_PROTOCOL instance.
+
+ @param Flags Describes how the image is to be drawn.
+
+ @param PackageList The package list in the HII database to
+ search for the specified image.
+
+ @param ImageId The image's id, which is unique within PackageList.
+
+ @param Blt If this points to a non-NULL on entry, this points
+ to the image, which is Width pixels wide and
+ Height pixels high. The image will be drawn onto
+ this image and EFI_HII_DRAW_FLAG_CLIP is implied.
+ If this points to a NULL on entry, then a buffer
+ will be allocated to hold the generated image and
+ the pointer updated on exit. It is the caller's
+ responsibility to free this buffer.
+
+ @param BltX, BltY Specifies the offset from the left and top
+ edge of the output image of the first
+ pixel in the image.
+
+ @retval EFI_SUCCESS The image was successfully updated.
+
+ @retval EFI_OUT_OF_RESOURCES Unable to allocate an output
+ buffer for RowInfoArray or Blt.
+
+ @retval EFI_NOT_FOUND The image specified by ImageId is not in the database.
+ Or The specified PackageList is not in the database.
+
+ @retval EFI_INVALID_PARAMETER The Blt was NULL.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_HII_DRAW_IMAGE_ID)(
+ IN CONST EFI_HII_IMAGE_PROTOCOL *This,
+ IN EFI_HII_DRAW_FLAGS Flags,
+ IN EFI_HII_HANDLE PackageList,
+ IN EFI_IMAGE_ID ImageId,
+ IN OUT EFI_IMAGE_OUTPUT **Blt,
+ IN UINTN BltX,
+ IN UINTN BltY
+ );
+
+///
+/// Services to access to images in the images database.
+///
+struct _EFI_HII_IMAGE_PROTOCOL {
+ EFI_HII_NEW_IMAGE NewImage;
+ EFI_HII_GET_IMAGE GetImage;
+ EFI_HII_SET_IMAGE SetImage;
+ EFI_HII_DRAW_IMAGE DrawImage;
+ EFI_HII_DRAW_IMAGE_ID DrawImageId;
+};
+
+extern EFI_GUID gEfiHiiImageProtocolGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/HiiImageDecoder.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/HiiImageDecoder.h
new file mode 100644
index 0000000000..e71894cfa2
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/HiiImageDecoder.h
@@ -0,0 +1,200 @@
+/** @file
+ This protocol provides generic image decoder interfaces to various image formats.
+
+(C) Copyright 2016 Hewlett Packard Enterprise Development LP
+ Copyright (c) 2016-2018, Intel Corporation. All rights reserved.
+
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Revision Reference:
+ This Protocol was introduced in UEFI Specification 2.6.
+
+**/
+
+#ifndef __HII_IMAGE_DECODER_H__
+#define __HII_IMAGE_DECODER_H__
+
+#include
+
+#define EFI_HII_IMAGE_DECODER_PROTOCOL_GUID \
+ {0x9e66f251, 0x727c, 0x418c, { 0xbf, 0xd6, 0xc2, 0xb4, 0x25, 0x28, 0x18, 0xea }}
+
+#define EFI_HII_IMAGE_DECODER_NAME_JPEG_GUID \
+ {0xefefd093, 0xd9b, 0x46eb, { 0xa8, 0x56, 0x48, 0x35, 0x7, 0x0, 0xc9, 0x8 }}
+
+#define EFI_HII_IMAGE_DECODER_NAME_PNG_GUID \
+ {0xaf060190, 0x5e3a, 0x4025, { 0xaf, 0xbd, 0xe1, 0xf9, 0x5, 0xbf, 0xaa, 0x4c }}
+
+typedef struct _EFI_HII_IMAGE_DECODER_PROTOCOL EFI_HII_IMAGE_DECODER_PROTOCOL;
+
+typedef enum {
+ EFI_HII_IMAGE_DECODER_COLOR_TYPE_RGB = 0x0,
+ EFI_HII_IMAGE_DECODER_COLOR_TYPE_RGBA = 0x1,
+ EFI_HII_IMAGE_DECODER_COLOR_TYPE_CMYK = 0x2,
+ EFI_HII_IMAGE_DECODER_COLOR_TYPE_UNKNOWN = 0xFF
+} EFI_HII_IMAGE_DECODER_COLOR_TYPE;
+
+//
+// EFI_HII_IMAGE_DECODER_IMAGE_INFO_HEADER
+//
+// DecoderName Name of the decoder
+// ImageInfoSize The size of entire image information structure in bytes
+// ImageWidth The image width
+// ImageHeight The image height
+// ColorType The color type, see EFI_HII_IMAGE_DECODER_COLOR_TYPE.
+// ColorDepthInBits The color depth in bits
+//
+typedef struct _EFI_HII_IMAGE_DECODER_IMAGE_INFO_HEADER {
+ EFI_GUID DecoderName;
+ UINT16 ImageInfoSize;
+ UINT16 ImageWidth;
+ UINT16 ImageHeight;
+ EFI_HII_IMAGE_DECODER_COLOR_TYPE ColorType;
+ UINT8 ColorDepthInBits;
+} EFI_HII_IMAGE_DECODER_IMAGE_INFO_HEADER;
+
+#define EFI_IMAGE_JPEG_SCANTYPE_PROGREESSIVE 0x01
+#define EFI_IMAGE_JPEG_SCANTYPE_INTERLACED 0x02
+
+//
+// EFI_HII_IMAGE_DECODER_JPEG_INFO
+// Header The common header
+// ScanType The scan type of JPEG image
+// Reserved Reserved
+//
+typedef struct _EFI_HII_IMAGE_DECODER_JPEG_INFO {
+ EFI_HII_IMAGE_DECODER_IMAGE_INFO_HEADER Header;
+ UINT16 ScanType;
+ UINT64 Reserved;
+} EFI_HII_IMAGE_DECODER_JPEG_INFO;
+
+//
+// EFI_HII_IMAGE_DECODER_PNG_INFO
+// Header The common header
+// Channels Number of channels in the PNG image
+// Reserved Reserved
+//
+typedef struct _EFI_HII_IMAGE_DECODER_PNG_INFO {
+ EFI_HII_IMAGE_DECODER_IMAGE_INFO_HEADER Header;
+ UINT16 Channels;
+ UINT64 Reserved;
+} EFI_HII_IMAGE_DECODER_PNG_INFO;
+
+//
+// EFI_HII_IMAGE_DECODER_OTHER_INFO
+//
+typedef struct _EFI_HII_IMAGE_DECODER_OTHER_INFO {
+ EFI_HII_IMAGE_DECODER_IMAGE_INFO_HEADER Header;
+ CHAR16 ImageExtenion[1];
+ //
+ // Variable length of image file extension name.
+ //
+} EFI_HII_IMAGE_DECODER_OTHER_INFO;
+
+/**
+ There could be more than one EFI_HII_IMAGE_DECODER_PROTOCOL instances installed
+ in the system for different image formats. This function returns the decoder
+ name which callers can use to find the proper image decoder for the image. It
+ is possible to support multiple image formats in one EFI_HII_IMAGE_DECODER_PROTOCOL.
+ The capability of the supported image formats is returned in DecoderName and
+ NumberOfDecoderName.
+
+ @param This EFI_HII_IMAGE_DECODER_PROTOCOL instance.
+ @param DecoderName Pointer to a dimension to retrieve the decoder
+ names in EFI_GUID format. The number of the
+ decoder names is returned in NumberOfDecoderName.
+ @param NumberofDecoderName Pointer to retrieve the number of decoders which
+ supported by this decoder driver.
+
+ @retval EFI_SUCCESS Get decoder name success.
+ @retval EFI_UNSUPPORTED Get decoder name fail.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_HII_IMAGE_DECODER_GET_NAME)(
+ IN EFI_HII_IMAGE_DECODER_PROTOCOL *This,
+ IN OUT EFI_GUID **DecoderName,
+ IN OUT UINT16 *NumberOfDecoderName
+ );
+
+/**
+ This function returns the image information of the given image raw data. This
+ function first checks whether the image raw data is supported by this decoder
+ or not. This function may go through the first few bytes in the image raw data
+ for the specific data structure or the image signature. If the image is not supported
+ by this image decoder, this function returns EFI_UNSUPPORTED to the caller.
+ Otherwise, this function returns the proper image information to the caller.
+ It is the caller?s responsibility to free the ImageInfo.
+
+ @param This EFI_HII_IMAGE_DECODER_PROTOCOL instance.
+ @param Image Pointer to the image raw data.
+ @param SizeOfImage Size of the entire image raw data.
+ @param ImageInfo Pointer to receive EFI_HII_IMAGE_DECODER_IMAGE_INFO_HEADER.
+
+ @retval EFI_SUCCESS Get image info success.
+ @retval EFI_UNSUPPORTED Unsupported format of image.
+ @retval EFI_INVALID_PARAMETER Incorrect parameter.
+ @retval EFI_BAD_BUFFER_SIZE Not enough memory.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_HII_IMAGE_DECODER_GET_IMAGE_INFO)(
+ IN EFI_HII_IMAGE_DECODER_PROTOCOL *This,
+ IN VOID *Image,
+ IN UINTN SizeOfImage,
+ IN OUT EFI_HII_IMAGE_DECODER_IMAGE_INFO_HEADER **ImageInfo
+ );
+
+/**
+ This function decodes the image which the image type of this image is supported
+ by this EFI_HII_IMAGE_DECODER_PROTOCOL. If **Bitmap is not NULL, the caller intends
+ to put the image in the given image buffer. That allows the caller to put an
+ image overlap on the original image. The transparency is handled by the image
+ decoder because the transparency capability depends on the image format. Callers
+ can set Transparent to FALSE to force disabling the transparency process on the
+ image. Forcing Transparent to FALSE may also improve the performance of the image
+ decoding because the image decoder can skip the transparency processing. If **Bitmap
+ is NULL, the image decoder allocates the memory buffer for the EFI_IMAGE_OUTPUT
+ and decodes the image to the image buffer. It is the caller?s responsibility to
+ free the memory for EFI_IMAGE_OUTPUT. Image decoder doesn?t have to handle the
+ transparency in this case because there is no background image given by the caller.
+ The background color in this case is all black (#00000000).
+
+ @param This EFI_HII_IMAGE_DECODER_PROTOCOL instance.
+ @param Image Pointer to the image raw data.
+ @param ImageRawDataSize Size of the entire image raw data.
+ @param Blt EFI_IMAGE_OUTPUT to receive the image or overlap
+ the image on the original buffer.
+ @param Transparent BOOLEAN value indicates whether the image decoder
+ has to handle the transparent image or not.
+
+
+ @retval EFI_SUCCESS Image decode success.
+ @retval EFI_UNSUPPORTED Unsupported format of image.
+ @retval EFI_INVALID_PARAMETER Incorrect parameter.
+ @retval EFI_BAD_BUFFER_SIZE Not enough memory.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_HII_IMAGE_DECODER_DECODE)(
+ IN EFI_HII_IMAGE_DECODER_PROTOCOL *This,
+ IN VOID *Image,
+ IN UINTN ImageRawDataSize,
+ IN OUT EFI_IMAGE_OUTPUT **Bitmap,
+ IN BOOLEAN Transparent
+ );
+
+struct _EFI_HII_IMAGE_DECODER_PROTOCOL {
+ EFI_HII_IMAGE_DECODER_GET_NAME GetImageDecoderName;
+ EFI_HII_IMAGE_DECODER_GET_IMAGE_INFO GetImageInfo;
+ EFI_HII_IMAGE_DECODER_DECODE DecodeImage;
+};
+
+extern EFI_GUID gEfiHiiImageDecoderProtocolGuid;
+extern EFI_GUID gEfiHiiImageDecoderNameJpegGuid;
+extern EFI_GUID gEfiHiiImageDecoderNamePngGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/HiiImageEx.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/HiiImageEx.h
new file mode 100644
index 0000000000..c851dd5777
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/HiiImageEx.h
@@ -0,0 +1,248 @@
+/** @file
+ Protocol which allows access to the images in the images database.
+
+(C) Copyright 2016-2018 Hewlett Packard Enterprise Development LP
+
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Revision Reference:
+ This Protocol was introduced in UEFI Specification 2.6.
+
+**/
+
+#ifndef __EFI_HII_IMAGE_EX_H__
+#define __EFI_HII_IMAGE_EX_H__
+
+#include
+
+//
+// Global ID for the Hii Image Ex Protocol.
+//
+#define EFI_HII_IMAGE_EX_PROTOCOL_GUID \
+ {0x1a1241e6, 0x8f19, 0x41a9, { 0xbc, 0xe, 0xe8, 0xef, 0x39, 0xe0, 0x65, 0x46 }}
+
+typedef struct _EFI_HII_IMAGE_EX_PROTOCOL EFI_HII_IMAGE_EX_PROTOCOL;
+
+/**
+ The prototype of this extension function is the same with EFI_HII_IMAGE_PROTOCOL.NewImage().
+ This protocol invokes EFI_HII_IMAGE_PROTOCOL.NewImage() implicitly.
+
+ @param This A pointer to the EFI_HII_IMAGE_EX_PROTOCOL instance.
+ @param PackageList Handle of the package list where this image will
+ be added.
+ @param ImageId On return, contains the new image id, which is
+ unique within PackageList.
+ @param Image Points to the image.
+
+ @retval EFI_SUCCESS The new image was added successfully.
+ @retval EFI_NOT_FOUND The specified PackageList could not be found in
+ database.
+ @retval EFI_OUT_OF_RESOURCES Could not add the image due to lack of resources.
+ @retval EFI_INVALID_PARAMETER Image is NULL or ImageId is NULL.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_HII_NEW_IMAGE_EX)(
+ IN CONST EFI_HII_IMAGE_EX_PROTOCOL *This,
+ IN EFI_HII_HANDLE PackageList,
+ OUT EFI_IMAGE_ID *ImageId,
+ IN CONST EFI_IMAGE_INPUT *Image
+ );
+
+/**
+ Return the information about the image, associated with the package list.
+ The prototype of this extension function is the same with EFI_HII_IMAGE_PROTOCOL.GetImage().
+
+ This function is similar to EFI_HII_IMAGE_PROTOCOL.GetImage().The difference is that
+ this function will locate all EFI_HII_IMAGE_DECODER_PROTOCOL instances installed in the
+ system if the decoder of the certain image type is not supported by the
+ EFI_HII_IMAGE_EX_PROTOCOL. The function will attempt to decode the image to the
+ EFI_IMAGE_INPUT using the first EFI_HII_IMAGE_DECODER_PROTOCOL instance that
+ supports the requested image type.
+
+ @param This A pointer to the EFI_HII_IMAGE_EX_PROTOCOL instance.
+ @param PackageList The package list in the HII database to search for the
+ specified image.
+ @param ImageId The image's id, which is unique within PackageList.
+ @param Image Points to the image.
+
+ @retval EFI_SUCCESS The new image was returned successfully.
+ @retval EFI_NOT_FOUND The image specified by ImageId is not available. The specified
+ PackageList is not in the Database.
+ @retval EFI_INVALID_PARAMETER Image was NULL or ImageId was 0.
+ @retval EFI_OUT_OF_RESOURCES The bitmap could not be retrieved because there
+ was not enough memory.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_HII_GET_IMAGE_EX)(
+ IN CONST EFI_HII_IMAGE_EX_PROTOCOL *This,
+ IN EFI_HII_HANDLE PackageList,
+ IN EFI_IMAGE_ID ImageId,
+ OUT EFI_IMAGE_INPUT *Image
+ );
+
+/**
+ Change the information about the image.
+
+ Same with EFI_HII_IMAGE_PROTOCOL.SetImage(),this protocol invokes
+ EFI_HII_IMAGE_PROTOCOL.SetImage()implicitly.
+
+ @param This A pointer to the EFI_HII_IMAGE_EX_PROTOCOL instance.
+ @param PackageList The package list containing the images.
+ @param ImageId The image's id, which is unique within PackageList.
+ @param Image Points to the image.
+
+ @retval EFI_SUCCESS The new image was successfully updated.
+ @retval EFI_NOT_FOUND The image specified by ImageId is not in the
+ database. The specified PackageList is not in
+ the database.
+ @retval EFI_INVALID_PARAMETER The Image was NULL, the ImageId was 0 or
+ the Image->Bitmap was NULL.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_HII_SET_IMAGE_EX)(
+ IN CONST EFI_HII_IMAGE_EX_PROTOCOL *This,
+ IN EFI_HII_HANDLE PackageList,
+ IN EFI_IMAGE_ID ImageId,
+ IN CONST EFI_IMAGE_INPUT *Image
+ );
+
+/**
+ Renders an image to a bitmap or to the display.
+
+ The prototype of this extension function is the same with
+ EFI_HII_IMAGE_PROTOCOL.DrawImage(). This protocol invokes
+ EFI_HII_IMAGE_PROTOCOL.DrawImage() implicitly.
+
+ @param This A pointer to the EFI_HII_IMAGE_EX_PROTOCOL instance.
+ @param Flags Describes how the image is to be drawn.
+ @param Image Points to the image to be displayed.
+ @param Blt If this points to a non-NULL on entry, this points
+ to the image, which is Width pixels wide and
+ Height pixels high. The image will be drawn onto
+ this image and EFI_HII_DRAW_FLAG_CLIP is implied.
+ If this points to a NULL on entry, then a buffer
+ will be allocated to hold the generated image and
+ the pointer updated on exit. It is the caller's
+ responsibility to free this buffer.
+ @param BltX Specifies the offset from the left and top edge of
+ the output image of the first pixel in the image.
+ @param BltY Specifies the offset from the left and top edge of
+ the output image of the first pixel in the image.
+
+ @retval EFI_SUCCESS The image was successfully drawn.
+ @retval EFI_OUT_OF_RESOURCES Unable to allocate an output buffer for Blt.
+ @retval EFI_INVALID_PARAMETER The Image or Blt was NULL.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_HII_DRAW_IMAGE_EX)(
+ IN CONST EFI_HII_IMAGE_EX_PROTOCOL *This,
+ IN EFI_HII_DRAW_FLAGS Flags,
+ IN CONST EFI_IMAGE_INPUT *Image,
+ IN OUT EFI_IMAGE_OUTPUT **Blt,
+ IN UINTN BltX,
+ IN UINTN BltY
+ );
+
+/**
+ Renders an image to a bitmap or the screen containing the contents of the specified
+ image.
+
+ This function is similar to EFI_HII_IMAGE_PROTOCOL.DrawImageId(). The difference is that
+ this function will locate all EFI_HII_IMAGE_DECODER_PROTOCOL instances installed in the
+ system if the decoder of the certain image type is not supported by the
+ EFI_HII_IMAGE_EX_PROTOCOL. The function will attempt to decode the image to the
+ EFI_IMAGE_INPUT using the first EFI_HII_IMAGE_DECODER_PROTOCOL instance that
+ supports the requested image type.
+
+ @param This A pointer to the EFI_HII_IMAGE_EX_PROTOCOL instance.
+ @param Flags Describes how the image is to be drawn.
+ @param PackageList The package list in the HII database to search for
+ the specified image.
+ @param ImageId The image's id, which is unique within PackageList.
+ @param Blt If this points to a non-NULL on entry, this points
+ to the image, which is Width pixels wide and
+ Height pixels high. The image will be drawn onto
+ this image and EFI_HII_DRAW_FLAG_CLIP is implied.
+ If this points to a NULL on entry, then a buffer
+ will be allocated to hold the generated image
+ and the pointer updated on exit. It is the caller's
+ responsibility to free this buffer.
+ @param BltX Specifies the offset from the left and top edge of
+ the output image of the first pixel in the image.
+ @param BltY Specifies the offset from the left and top edge of
+ the output image of the first pixel in the image.
+
+ @retval EFI_SUCCESS The image was successfully drawn.
+ @retval EFI_OUT_OF_RESOURCES Unable to allocate an output buffer for Blt.
+ @retval EFI_INVALID_PARAMETER The Blt was NULL or ImageId was 0.
+ @retval EFI_NOT_FOUND The image specified by ImageId is not in the database.
+ The specified PackageList is not in the database.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_HII_DRAW_IMAGE_ID_EX)(
+ IN CONST EFI_HII_IMAGE_EX_PROTOCOL *This,
+ IN EFI_HII_DRAW_FLAGS Flags,
+ IN EFI_HII_HANDLE PackageList,
+ IN EFI_IMAGE_ID ImageId,
+ IN OUT EFI_IMAGE_OUTPUT **Blt,
+ IN UINTN BltX,
+ IN UINTN BltY
+ );
+
+/**
+ This function returns the image information to EFI_IMAGE_OUTPUT. Only the width
+ and height are returned to the EFI_IMAGE_OUTPUT instead of decoding the image
+ to the buffer. This function is used to get the geometry of the image. This function
+ will try to locate all of the EFI_HII_IMAGE_DECODER_PROTOCOL installed on the
+ system if the decoder of image type is not supported by the EFI_HII_IMAGE_EX_PROTOCOL.
+
+ @param This A pointer to the EFI_HII_IMAGE_EX_PROTOCOL instance.
+ @param PackageList Handle of the package list where this image will
+ be searched.
+ @param ImageId The image's id, which is unique within PackageList.
+ @param Image Points to the image.
+
+ @retval EFI_SUCCESS The new image was returned successfully.
+ @retval EFI_NOT_FOUND The image specified by ImageId is not in the
+ database. The specified PackageList is not in the database.
+ @retval EFI_BUFFER_TOO_SMALL The buffer specified by ImageSize is too small to
+ hold the image.
+ @retval EFI_INVALID_PARAMETER The Image was NULL or the ImageId was 0.
+ @retval EFI_OUT_OF_RESOURCES The bitmap could not be retrieved because there
+ was not enough memory.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_HII_GET_IMAGE_INFO)(
+ IN CONST EFI_HII_IMAGE_EX_PROTOCOL *This,
+ IN EFI_HII_HANDLE PackageList,
+ IN EFI_IMAGE_ID ImageId,
+ OUT EFI_IMAGE_OUTPUT *Image
+ );
+
+///
+/// Protocol which allows access to the images in the images database.
+///
+struct _EFI_HII_IMAGE_EX_PROTOCOL {
+ EFI_HII_NEW_IMAGE_EX NewImageEx;
+ EFI_HII_GET_IMAGE_EX GetImageEx;
+ EFI_HII_SET_IMAGE_EX SetImageEx;
+ EFI_HII_DRAW_IMAGE_EX DrawImageEx;
+ EFI_HII_DRAW_IMAGE_ID_EX DrawImageIdEx;
+ EFI_HII_GET_IMAGE_INFO GetImageInfo;
+};
+
+extern EFI_GUID gEfiHiiImageExProtocolGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/HiiPackageList.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/HiiPackageList.h
new file mode 100644
index 0000000000..bfae0c97d6
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/HiiPackageList.h
@@ -0,0 +1,23 @@
+/** @file
+ EFI_HII_PACKAGE_LIST_PROTOCOL as defined in UEFI 2.1.
+ Boot service LoadImage() installs EFI_HII_PACKAGE_LIST_PROTOCOL on the handle
+ if the image contains a custom PE/COFF resource with the type 'HII'.
+ The protocol's interface pointer points to the HII package list, which is
+ contained in the resource's data.
+
+ Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __HII_PACKAGE_LIST_H__
+#define __HII_PACKAGE_LIST_H__
+
+#define EFI_HII_PACKAGE_LIST_PROTOCOL_GUID \
+ { 0x6a1ee763, 0xd47a, 0x43b4, {0xaa, 0xbe, 0xef, 0x1d, 0xe2, 0xab, 0x56, 0xfc}}
+
+typedef EFI_HII_PACKAGE_LIST_HEADER *EFI_HII_PACKAGE_LIST_PROTOCOL;
+
+extern EFI_GUID gEfiHiiPackageListProtocolGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/HiiPopup.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/HiiPopup.h
new file mode 100644
index 0000000000..0c0c588803
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/HiiPopup.h
@@ -0,0 +1,77 @@
+/** @file
+ This protocol provides services to display a popup window.
+ The protocol is typically produced by the forms browser and consumed by a driver callback handler.
+
+ Copyright (c) 2017-2021, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Revision Reference:
+ This Protocol was introduced in UEFI Specification 2.7.
+
+**/
+
+#ifndef __HII_POPUP_H__
+#define __HII_POPUP_H__
+
+#define EFI_HII_POPUP_PROTOCOL_GUID \
+ {0x4311edc0, 0x6054, 0x46d4, {0x9e, 0x40, 0x89, 0x3e, 0xa9, 0x52, 0xfc, 0xcc}}
+
+#define EFI_HII_POPUP_PROTOCOL_REVISION 1
+
+typedef struct _EFI_HII_POPUP_PROTOCOL EFI_HII_POPUP_PROTOCOL;
+
+typedef enum {
+ EfiHiiPopupStyleInfo,
+ EfiHiiPopupStyleWarning,
+ EfiHiiPopupStyleError
+} EFI_HII_POPUP_STYLE;
+
+typedef enum {
+ EfiHiiPopupTypeOk,
+ EfiHiiPopupTypeOkCancel,
+ EfiHiiPopupTypeYesNo,
+ EfiHiiPopupTypeYesNoCancel
+} EFI_HII_POPUP_TYPE;
+
+typedef enum {
+ EfiHiiPopupSelectionOk,
+ EfiHiiPopupSelectionCancel,
+ EfiHiiPopupSelectionYes,
+ EfiHiiPopupSelectionNo
+} EFI_HII_POPUP_SELECTION;
+
+/**
+ Displays a popup window.
+
+ @param This A pointer to the EFI_HII_POPUP_PROTOCOL instance.
+ @param PopupStyle Popup style to use.
+ @param PopupType Type of the popup to display.
+ @param HiiHandle HII handle of the string pack containing Message
+ @param Message A message to display in the popup box.
+ @param UserSelection User selection.
+
+ @retval EFI_SUCCESS The popup box was successfully displayed.
+ @retval EFI_INVALID_PARAMETER HiiHandle and Message do not define a valid HII string.
+ @retval EFI_INVALID_PARAMETER PopupType is not one of the values defined by this specification.
+ @retval EFI_OUT_OF_RESOURCES There are not enough resources available to display the popup box.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_HII_CREATE_POPUP)(
+ IN EFI_HII_POPUP_PROTOCOL *This,
+ IN EFI_HII_POPUP_STYLE PopupStyle,
+ IN EFI_HII_POPUP_TYPE PopupType,
+ IN EFI_HII_HANDLE HiiHandle,
+ IN EFI_STRING_ID Message,
+ OUT EFI_HII_POPUP_SELECTION *UserSelection OPTIONAL
+ );
+
+struct _EFI_HII_POPUP_PROTOCOL {
+ UINT64 Revision;
+ EFI_HII_CREATE_POPUP CreatePopup;
+};
+
+extern EFI_GUID gEfiHiiPopupProtocolGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/HiiString.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/HiiString.h
new file mode 100644
index 0000000000..6801eb4ec1
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/HiiString.h
@@ -0,0 +1,232 @@
+/** @file
+ The file provides services to manipulate string data.
+
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Revision Reference:
+ This Protocol was introduced in UEFI Specification 2.1.
+
+**/
+
+#ifndef __HII_STRING_H__
+#define __HII_STRING_H__
+
+#include
+
+#define EFI_HII_STRING_PROTOCOL_GUID \
+ { 0xfd96974, 0x23aa, 0x4cdc, { 0xb9, 0xcb, 0x98, 0xd1, 0x77, 0x50, 0x32, 0x2a } }
+
+typedef struct _EFI_HII_STRING_PROTOCOL EFI_HII_STRING_PROTOCOL;
+
+/**
+ This function adds the string String to the group of strings owned by PackageList, with the
+ specified font information StringFontInfo, and returns a new string id.
+ The new string identifier is guaranteed to be unique within the package list.
+ That new string identifier is reserved for all languages in the package list.
+
+ @param This A pointer to the EFI_HII_STRING_PROTOCOL instance.
+ @param PackageList The handle of the package list where this string will
+ be added.
+ @param StringId On return, contains the new strings id, which is
+ unique within PackageList.
+ @param Language Points to the language for the new string.
+ @param LanguageName Points to the printable language name to associate
+ with the passed in Language field.If LanguageName
+ is not NULL and the string package header's
+ LanguageName associated with a given Language is
+ not zero, the LanguageName being passed in will
+ be ignored.
+ @param String Points to the new null-terminated string.
+ @param StringFontInfo Points to the new string's font information or
+ NULL if the string should have the default system
+ font, size and style.
+
+ @retval EFI_SUCCESS The new string was added successfully.
+ @retval EFI_NOT_FOUND The specified PackageList could not be found in
+ database.
+ @retval EFI_OUT_OF_RESOURCES Could not add the string due to lack of resources.
+ @retval EFI_INVALID_PARAMETER String is NULL, or StringId is NULL, or Language is NULL.
+ @retval EFI_INVALID_PARAMETER The specified StringFontInfo does not exist in
+ current database.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_HII_NEW_STRING)(
+ IN CONST EFI_HII_STRING_PROTOCOL *This,
+ IN EFI_HII_HANDLE PackageList,
+ OUT EFI_STRING_ID *StringId,
+ IN CONST CHAR8 *Language,
+ IN CONST CHAR16 *LanguageName OPTIONAL,
+ IN CONST EFI_STRING String,
+ IN CONST EFI_FONT_INFO *StringFontInfo OPTIONAL
+ );
+
+/**
+ This function retrieves the string specified by StringId which is associated
+ with the specified PackageList in the language Language and copies it into
+ the buffer specified by String.
+
+ @param This A pointer to the EFI_HII_STRING_PROTOCOL instance.
+ @param Language Points to the language for the retrieved string.
+ @param PackageList The package list in the HII database to search for
+ the specified string.
+ @param StringId The string's id, which is unique within
+ PackageList.
+ @param String Points to the new null-terminated string.
+ @param StringSize On entry, points to the size of the buffer pointed
+ to by String, in bytes. On return, points to the
+ length of the string, in bytes.
+ @param StringFontInfo If not NULL, points to the string's font
+ information. It's caller's responsibility to free
+ this buffer.
+
+ @retval EFI_SUCCESS The string was returned successfully.
+ @retval EFI_NOT_FOUND The string specified by StringId is not available.
+ The specified PackageList is not in the database.
+ @retval EFI_INVALID_LANGUAGE The string specified by StringId is available but
+ not in the specified language.
+ @retval EFI_BUFFER_TOO_SMALL The buffer specified by StringSize is too small to
+ hold the string.
+ @retval EFI_INVALID_PARAMETER The Language or StringSize was NULL.
+ @retval EFI_INVALID_PARAMETER The value referenced by StringSize was not zero and
+ String was NULL.
+ @retval EFI_OUT_OF_RESOURCES There were insufficient resources to complete the
+ request.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_HII_GET_STRING)(
+ IN CONST EFI_HII_STRING_PROTOCOL *This,
+ IN CONST CHAR8 *Language,
+ IN EFI_HII_HANDLE PackageList,
+ IN EFI_STRING_ID StringId,
+ OUT EFI_STRING String,
+ IN OUT UINTN *StringSize,
+ OUT EFI_FONT_INFO **StringFontInfo OPTIONAL
+ );
+
+/**
+ This function updates the string specified by StringId in the specified PackageList to the text
+ specified by String and, optionally, the font information specified by StringFontInfo.
+
+ @param This A pointer to the EFI_HII_STRING_PROTOCOL instance.
+ @param PackageList The package list containing the strings.
+ @param StringId The string's id, which is unique within
+ PackageList.
+ @param Language Points to the language for the updated string.
+ @param String Points to the new null-terminated string.
+ @param StringFontInfo Points to the string's font information or NULL if
+ the string font information is not changed.
+
+ @retval EFI_SUCCESS The string was updated successfully.
+ @retval EFI_NOT_FOUND The string specified by StringId is not in the
+ database.
+ @retval EFI_INVALID_PARAMETER The String or Language was NULL.
+ @retval EFI_INVALID_PARAMETER The specified StringFontInfo does not exist in
+ current database.
+ @retval EFI_OUT_OF_RESOURCES The system is out of resources to accomplish the
+ task.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_HII_SET_STRING)(
+ IN CONST EFI_HII_STRING_PROTOCOL *This,
+ IN EFI_HII_HANDLE PackageList,
+ IN EFI_STRING_ID StringId,
+ IN CONST CHAR8 *Language,
+ IN EFI_STRING String,
+ IN CONST EFI_FONT_INFO *StringFontInfo OPTIONAL
+ );
+
+/**
+ This function returns the list of supported languages.
+
+ @param This A pointer to the EFI_HII_STRING_PROTOCOL instance.
+ @param PackageList The package list to examine.
+ @param Languages Points to the buffer to hold the returned
+ null-terminated ASCII string.
+ @param LanguagesSize On entry, points to the size of the buffer pointed
+ to by Languages, in bytes. On return, points to
+ the length of Languages, in bytes.
+
+ @retval EFI_SUCCESS The languages were returned successfully.
+ @retval EFI_INVALID_PARAMETER The LanguagesSize was NULL.
+ @retval EFI_INVALID_PARAMETER The value referenced by LanguagesSize is not zero
+ and Languages is NULL.
+ @retval EFI_BUFFER_TOO_SMALL The LanguagesSize is too small to hold the list of
+ supported languages. LanguageSize is updated to
+ contain the required size.
+ @retval EFI_NOT_FOUND Could not find string package in specified
+ packagelist.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_HII_GET_LANGUAGES)(
+ IN CONST EFI_HII_STRING_PROTOCOL *This,
+ IN EFI_HII_HANDLE PackageList,
+ IN OUT CHAR8 *Languages,
+ IN OUT UINTN *LanguagesSize
+ );
+
+/**
+ Each string package has associated with it a single primary language and zero
+ or more secondary languages. This routine returns the secondary languages
+ associated with a package list.
+
+ @param This A pointer to the EFI_HII_STRING_PROTOCOL instance.
+ @param PackageList The package list to examine.
+ @param PrimaryLanguage Points to the null-terminated ASCII string that specifies
+ the primary language. Languages are specified in the
+ format specified in Appendix M of the UEFI 2.0 specification.
+ @param SecondaryLanguages Points to the buffer to hold the returned null-terminated
+ ASCII string that describes the list of
+ secondary languages for the specified
+ PrimaryLanguage. If there are no secondary
+ languages, the function returns successfully, but
+ this is set to NULL.
+ @param SecondaryLanguagesSize On entry, points to the size of the buffer pointed
+ to by SecondaryLanguages, in bytes. On return,
+ points to the length of SecondaryLanguages in bytes.
+
+ @retval EFI_SUCCESS Secondary languages were correctly returned.
+ @retval EFI_INVALID_PARAMETER PrimaryLanguage or SecondaryLanguagesSize was NULL.
+ @retval EFI_INVALID_PARAMETER The value referenced by SecondaryLanguagesSize is not
+ zero and SecondaryLanguages is NULL.
+ @retval EFI_BUFFER_TOO_SMALL The buffer specified by SecondaryLanguagesSize is
+ too small to hold the returned information.
+ SecondaryLanguageSize is updated to hold the size of
+ the buffer required.
+ @retval EFI_INVALID_LANGUAGE The language specified by PrimaryLanguage is not
+ present in the specified package list.
+ @retval EFI_NOT_FOUND The specified PackageList is not in the Database.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_HII_GET_2ND_LANGUAGES)(
+ IN CONST EFI_HII_STRING_PROTOCOL *This,
+ IN EFI_HII_HANDLE PackageList,
+ IN CONST CHAR8 *PrimaryLanguage,
+ IN OUT CHAR8 *SecondaryLanguages,
+ IN OUT UINTN *SecondaryLanguagesSize
+ );
+
+///
+/// Services to manipulate the string.
+///
+struct _EFI_HII_STRING_PROTOCOL {
+ EFI_HII_NEW_STRING NewString;
+ EFI_HII_GET_STRING GetString;
+ EFI_HII_SET_STRING SetString;
+ EFI_HII_GET_LANGUAGES GetLanguages;
+ EFI_HII_GET_2ND_LANGUAGES GetSecondaryLanguages;
+};
+
+extern EFI_GUID gEfiHiiStringProtocolGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/Http.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/Http.h
new file mode 100644
index 0000000000..984f6b8a0a
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/Http.h
@@ -0,0 +1,514 @@
+/** @file
+ This file defines the EFI HTTP Protocol interface. It is split into
+ the following two main sections:
+ HTTP Service Binding Protocol (HTTPSB)
+ HTTP Protocol (HTTP)
+
+ Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.
+ (C) Copyright 2015-2017 Hewlett Packard Enterprise Development LP
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Revision Reference:
+ This Protocol is introduced in UEFI Specification 2.5
+
+**/
+
+#ifndef __EFI_HTTP_PROTOCOL_H__
+#define __EFI_HTTP_PROTOCOL_H__
+
+#define EFI_HTTP_SERVICE_BINDING_PROTOCOL_GUID \
+ { \
+ 0xbdc8e6af, 0xd9bc, 0x4379, {0xa7, 0x2a, 0xe0, 0xc4, 0xe7, 0x5d, 0xae, 0x1c } \
+ }
+
+#define EFI_HTTP_PROTOCOL_GUID \
+ { \
+ 0x7a59b29b, 0x910b, 0x4171, {0x82, 0x42, 0xa8, 0x5a, 0x0d, 0xf2, 0x5b, 0x5b } \
+ }
+
+typedef struct _EFI_HTTP_PROTOCOL EFI_HTTP_PROTOCOL;
+
+///
+/// EFI_HTTP_VERSION
+///
+typedef enum {
+ HttpVersion10,
+ HttpVersion11,
+ HttpVersionUnsupported
+} EFI_HTTP_VERSION;
+
+///
+/// EFI_HTTP_METHOD
+///
+typedef enum {
+ HttpMethodGet,
+ HttpMethodPost,
+ HttpMethodPatch,
+ HttpMethodOptions,
+ HttpMethodConnect,
+ HttpMethodHead,
+ HttpMethodPut,
+ HttpMethodDelete,
+ HttpMethodTrace,
+ HttpMethodMax
+} EFI_HTTP_METHOD;
+
+///
+/// EFI_HTTP_STATUS_CODE
+///
+typedef enum {
+ HTTP_STATUS_UNSUPPORTED_STATUS = 0,
+ HTTP_STATUS_100_CONTINUE,
+ HTTP_STATUS_101_SWITCHING_PROTOCOLS,
+ HTTP_STATUS_200_OK,
+ HTTP_STATUS_201_CREATED,
+ HTTP_STATUS_202_ACCEPTED,
+ HTTP_STATUS_203_NON_AUTHORITATIVE_INFORMATION,
+ HTTP_STATUS_204_NO_CONTENT,
+ HTTP_STATUS_205_RESET_CONTENT,
+ HTTP_STATUS_206_PARTIAL_CONTENT,
+ HTTP_STATUS_300_MULTIPLE_CHOICES,
+ HTTP_STATUS_301_MOVED_PERMANENTLY,
+ HTTP_STATUS_302_FOUND,
+ HTTP_STATUS_303_SEE_OTHER,
+ HTTP_STATUS_304_NOT_MODIFIED,
+ HTTP_STATUS_305_USE_PROXY,
+ HTTP_STATUS_307_TEMPORARY_REDIRECT,
+ HTTP_STATUS_400_BAD_REQUEST,
+ HTTP_STATUS_401_UNAUTHORIZED,
+ HTTP_STATUS_402_PAYMENT_REQUIRED,
+ HTTP_STATUS_403_FORBIDDEN,
+ HTTP_STATUS_404_NOT_FOUND,
+ HTTP_STATUS_405_METHOD_NOT_ALLOWED,
+ HTTP_STATUS_406_NOT_ACCEPTABLE,
+ HTTP_STATUS_407_PROXY_AUTHENTICATION_REQUIRED,
+ HTTP_STATUS_408_REQUEST_TIME_OUT,
+ HTTP_STATUS_409_CONFLICT,
+ HTTP_STATUS_410_GONE,
+ HTTP_STATUS_411_LENGTH_REQUIRED,
+ HTTP_STATUS_412_PRECONDITION_FAILED,
+ HTTP_STATUS_413_REQUEST_ENTITY_TOO_LARGE,
+ HTTP_STATUS_414_REQUEST_URI_TOO_LARGE,
+ HTTP_STATUS_415_UNSUPPORTED_MEDIA_TYPE,
+ HTTP_STATUS_416_REQUESTED_RANGE_NOT_SATISFIED,
+ HTTP_STATUS_417_EXPECTATION_FAILED,
+ HTTP_STATUS_500_INTERNAL_SERVER_ERROR,
+ HTTP_STATUS_501_NOT_IMPLEMENTED,
+ HTTP_STATUS_502_BAD_GATEWAY,
+ HTTP_STATUS_503_SERVICE_UNAVAILABLE,
+ HTTP_STATUS_504_GATEWAY_TIME_OUT,
+ HTTP_STATUS_505_HTTP_VERSION_NOT_SUPPORTED,
+ HTTP_STATUS_308_PERMANENT_REDIRECT
+} EFI_HTTP_STATUS_CODE;
+
+///
+/// EFI_HTTPv4_ACCESS_POINT
+///
+typedef struct {
+ ///
+ /// Set to TRUE to instruct the EFI HTTP instance to use the default address
+ /// information in every TCP connection made by this instance. In addition, when set
+ /// to TRUE, LocalAddress and LocalSubnet are ignored.
+ ///
+ BOOLEAN UseDefaultAddress;
+ ///
+ /// If UseDefaultAddress is set to FALSE, this defines the local IP address to be
+ /// used in every TCP connection opened by this instance.
+ ///
+ EFI_IPv4_ADDRESS LocalAddress;
+ ///
+ /// If UseDefaultAddress is set to FALSE, this defines the local subnet to be used
+ /// in every TCP connection opened by this instance.
+ ///
+ EFI_IPv4_ADDRESS LocalSubnet;
+ ///
+ /// This defines the local port to be used in
+ /// every TCP connection opened by this instance.
+ ///
+ UINT16 LocalPort;
+} EFI_HTTPv4_ACCESS_POINT;
+
+///
+/// EFI_HTTPv6_ACCESS_POINT
+///
+typedef struct {
+ ///
+ /// Local IP address to be used in every TCP connection opened by this instance.
+ ///
+ EFI_IPv6_ADDRESS LocalAddress;
+ ///
+ /// Local port to be used in every TCP connection opened by this instance.
+ ///
+ UINT16 LocalPort;
+} EFI_HTTPv6_ACCESS_POINT;
+
+///
+/// EFI_HTTP_CONFIG_DATA_ACCESS_POINT
+///
+
+typedef struct {
+ ///
+ /// HTTP version that this instance will support.
+ ///
+ EFI_HTTP_VERSION HttpVersion;
+ ///
+ /// Time out (in milliseconds) when blocking for requests.
+ ///
+ UINT32 TimeOutMillisec;
+ ///
+ /// Defines behavior of EFI DNS and TCP protocols consumed by this instance. If
+ /// FALSE, this instance will use EFI_DNS4_PROTOCOL and EFI_TCP4_PROTOCOL. If TRUE,
+ /// this instance will use EFI_DNS6_PROTOCOL and EFI_TCP6_PROTOCOL.
+ ///
+ BOOLEAN LocalAddressIsIPv6;
+
+ union {
+ ///
+ /// When LocalAddressIsIPv6 is FALSE, this points to the local address, subnet, and
+ /// port used by the underlying TCP protocol.
+ ///
+ EFI_HTTPv4_ACCESS_POINT *IPv4Node;
+ ///
+ /// When LocalAddressIsIPv6 is TRUE, this points to the local IPv6 address and port
+ /// used by the underlying TCP protocol.
+ ///
+ EFI_HTTPv6_ACCESS_POINT *IPv6Node;
+ } AccessPoint;
+} EFI_HTTP_CONFIG_DATA;
+
+///
+/// EFI_HTTP_REQUEST_DATA
+///
+typedef struct {
+ ///
+ /// The HTTP method (e.g. GET, POST) for this HTTP Request.
+ ///
+ EFI_HTTP_METHOD Method;
+ ///
+ /// The URI of a remote host. From the information in this field, the HTTP instance
+ /// will be able to determine whether to use HTTP or HTTPS and will also be able to
+ /// determine the port number to use. If no port number is specified, port 80 (HTTP)
+ /// is assumed. See RFC 3986 for more details on URI syntax.
+ ///
+ CHAR16 *Url;
+} EFI_HTTP_REQUEST_DATA;
+
+///
+/// EFI_HTTP_RESPONSE_DATA
+///
+typedef struct {
+ ///
+ /// Response status code returned by the remote host.
+ ///
+ EFI_HTTP_STATUS_CODE StatusCode;
+} EFI_HTTP_RESPONSE_DATA;
+
+///
+/// EFI_HTTP_HEADER
+///
+typedef struct {
+ ///
+ /// Null terminated string which describes a field name. See RFC 2616 Section 14 for
+ /// detailed information about field names.
+ ///
+ CHAR8 *FieldName;
+ ///
+ /// Null terminated string which describes the corresponding field value. See RFC 2616
+ /// Section 14 for detailed information about field values.
+ ///
+ CHAR8 *FieldValue;
+} EFI_HTTP_HEADER;
+
+///
+/// EFI_HTTP_MESSAGE
+///
+typedef struct {
+ ///
+ /// HTTP message data.
+ ///
+ union {
+ ///
+ /// When the token is used to send a HTTP request, Request is a pointer to storage that
+ /// contains such data as URL and HTTP method.
+ ///
+ EFI_HTTP_REQUEST_DATA *Request;
+ ///
+ /// When used to await a response, Response points to storage containing HTTP response
+ /// status code.
+ ///
+ EFI_HTTP_RESPONSE_DATA *Response;
+ } Data;
+ ///
+ /// Number of HTTP header structures in Headers list. On request, this count is
+ /// provided by the caller. On response, this count is provided by the HTTP driver.
+ ///
+ UINTN HeaderCount;
+ ///
+ /// Array containing list of HTTP headers. On request, this array is populated by the
+ /// caller. On response, this array is allocated and populated by the HTTP driver. It
+ /// is the responsibility of the caller to free this memory on both request and
+ /// response.
+ ///
+ EFI_HTTP_HEADER *Headers;
+ ///
+ /// Length in bytes of the HTTP body. This can be zero depending on the HttpMethod type.
+ ///
+ UINTN BodyLength;
+ ///
+ /// Body associated with the HTTP request or response. This can be NULL depending on
+ /// the HttpMethod type.
+ ///
+ VOID *Body;
+} EFI_HTTP_MESSAGE;
+
+///
+/// EFI_HTTP_TOKEN
+///
+typedef struct {
+ ///
+ /// This Event will be signaled after the Status field is updated by the EFI HTTP
+ /// Protocol driver. The type of Event must be EFI_NOTIFY_SIGNAL. The Task Priority
+ /// Level (TPL) of Event must be lower than or equal to TPL_CALLBACK.
+ ///
+ EFI_EVENT Event;
+ ///
+ /// Status will be set to one of the following value if the HTTP request is
+ /// successfully sent or if an unexpected error occurs:
+ /// EFI_SUCCESS: The HTTP request was successfully sent to the remote host.
+ /// EFI_HTTP_ERROR: The response message was successfully received but contains a
+ /// HTTP error. The response status code is returned in token.
+ /// EFI_ABORTED: The HTTP request was cancelled by the caller and removed from
+ /// the transmit queue.
+ /// EFI_TIMEOUT: The HTTP request timed out before reaching the remote host.
+ /// EFI_DEVICE_ERROR: An unexpected system or network error occurred.
+ ///
+ EFI_STATUS Status;
+ ///
+ /// Pointer to storage containing HTTP message data.
+ ///
+ EFI_HTTP_MESSAGE *Message;
+} EFI_HTTP_TOKEN;
+
+/**
+ Returns the operational parameters for the current HTTP child instance.
+
+ The GetModeData() function is used to read the current mode data (operational
+ parameters) for this HTTP protocol instance.
+
+ @param[in] This Pointer to EFI_HTTP_PROTOCOL instance.
+ @param[out] HttpConfigData Point to buffer for operational parameters of this
+ HTTP instance. It is the responsibility of the caller
+ to allocate the memory for HttpConfigData and
+ HttpConfigData->AccessPoint.IPv6Node/IPv4Node. In fact,
+ it is recommended to allocate sufficient memory to record
+ IPv6Node since it is big enough for all possibilities.
+
+ @retval EFI_SUCCESS Operation succeeded.
+ @retval EFI_INVALID_PARAMETER This is NULL.
+ HttpConfigData is NULL.
+ HttpConfigData->AccessPoint.IPv4Node or
+ HttpConfigData->AccessPoint.IPv6Node is NULL.
+ @retval EFI_NOT_STARTED This EFI HTTP Protocol instance has not been started.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_HTTP_GET_MODE_DATA)(
+ IN EFI_HTTP_PROTOCOL *This,
+ OUT EFI_HTTP_CONFIG_DATA *HttpConfigData
+ );
+
+/**
+ Initialize or brutally reset the operational parameters for this EFI HTTP instance.
+
+ The Configure() function does the following:
+ When HttpConfigData is not NULL Initialize this EFI HTTP instance by configuring
+ timeout, local address, port, etc.
+ When HttpConfigData is NULL, reset this EFI HTTP instance by closing all active
+ connections with remote hosts, canceling all asynchronous tokens, and flush request
+ and response buffers without informing the appropriate hosts.
+
+ No other EFI HTTP function can be executed by this instance until the Configure()
+ function is executed and returns successfully.
+
+ @param[in] This Pointer to EFI_HTTP_PROTOCOL instance.
+ @param[in] HttpConfigData Pointer to the configure data to configure the instance.
+
+ @retval EFI_SUCCESS Operation succeeded.
+ @retval EFI_INVALID_PARAMETER One or more of the following conditions is TRUE:
+ This is NULL.
+ HttpConfigData->LocalAddressIsIPv6 is FALSE and
+ HttpConfigData->AccessPoint.IPv4Node is NULL.
+ HttpConfigData->LocalAddressIsIPv6 is TRUE and
+ HttpConfigData->AccessPoint.IPv6Node is NULL.
+ @retval EFI_ALREADY_STARTED Reinitialize this HTTP instance without calling
+ Configure() with NULL to reset it.
+ @retval EFI_DEVICE_ERROR An unexpected system or network error occurred.
+ @retval EFI_OUT_OF_RESOURCES Could not allocate enough system resources when
+ executing Configure().
+ @retval EFI_UNSUPPORTED One or more options in ConfigData are not supported
+ in the implementation.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_HTTP_CONFIGURE)(
+ IN EFI_HTTP_PROTOCOL *This,
+ IN EFI_HTTP_CONFIG_DATA *HttpConfigData OPTIONAL
+ );
+
+/**
+ The Request() function queues an HTTP request to this HTTP instance,
+ similar to Transmit() function in the EFI TCP driver. When the HTTP request is sent
+ successfully, or if there is an error, Status in token will be updated and Event will
+ be signaled.
+
+ @param[in] This Pointer to EFI_HTTP_PROTOCOL instance.
+ @param[in] Token Pointer to storage containing HTTP request token.
+
+ @retval EFI_SUCCESS Outgoing data was processed.
+ @retval EFI_NOT_STARTED This EFI HTTP Protocol instance has not been started.
+ @retval EFI_DEVICE_ERROR An unexpected system or network error occurred.
+ @retval EFI_TIMEOUT Data was dropped out of the transmit or receive queue.
+ @retval EFI_INVALID_PARAMETER One or more of the following conditions is TRUE:
+ This is NULL.
+ Token is NULL.
+ Token->Message is NULL.
+ Token->Message->Body is not NULL,
+ Token->Message->BodyLength is non-zero, and
+ Token->Message->Data is NULL, but a previous call to
+ Request()has not been completed successfully.
+ @retval EFI_OUT_OF_RESOURCES Could not allocate enough system resources.
+ @retval EFI_UNSUPPORTED The HTTP method is not supported in current implementation.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_HTTP_REQUEST)(
+ IN EFI_HTTP_PROTOCOL *This,
+ IN EFI_HTTP_TOKEN *Token
+ );
+
+/**
+ Abort an asynchronous HTTP request or response token.
+
+ The Cancel() function aborts a pending HTTP request or response transaction. If
+ Token is not NULL and the token is in transmit or receive queues when it is being
+ cancelled, its Token->Status will be set to EFI_ABORTED and then Token->Event will
+ be signaled. If the token is not in one of the queues, which usually means that the
+ asynchronous operation has completed, EFI_NOT_FOUND is returned. If Token is NULL,
+ all asynchronous tokens issued by Request() or Response() will be aborted.
+
+ @param[in] This Pointer to EFI_HTTP_PROTOCOL instance.
+ @param[in] Token Point to storage containing HTTP request or response
+ token.
+
+ @retval EFI_SUCCESS Request and Response queues are successfully flushed.
+ @retval EFI_INVALID_PARAMETER This is NULL.
+ @retval EFI_NOT_STARTED This instance hasn't been configured.
+ @retval EFI_NOT_FOUND The asynchronous request or response token is not
+ found.
+ @retval EFI_UNSUPPORTED The implementation does not support this function.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_HTTP_CANCEL)(
+ IN EFI_HTTP_PROTOCOL *This,
+ IN EFI_HTTP_TOKEN *Token
+ );
+
+/**
+ The Response() function queues an HTTP response to this HTTP instance, similar to
+ Receive() function in the EFI TCP driver. When the HTTP Response is received successfully,
+ or if there is an error, Status in token will be updated and Event will be signaled.
+
+ The HTTP driver will queue a receive token to the underlying TCP instance. When data
+ is received in the underlying TCP instance, the data will be parsed and Token will
+ be populated with the response data. If the data received from the remote host
+ contains an incomplete or invalid HTTP header, the HTTP driver will continue waiting
+ (asynchronously) for more data to be sent from the remote host before signaling
+ Event in Token.
+
+ It is the responsibility of the caller to allocate a buffer for Body and specify the
+ size in BodyLength. If the remote host provides a response that contains a content
+ body, up to BodyLength bytes will be copied from the receive buffer into Body and
+ BodyLength will be updated with the amount of bytes received and copied to Body. This
+ allows the client to download a large file in chunks instead of into one contiguous
+ block of memory. Similar to HTTP request, if Body is not NULL and BodyLength is
+ non-zero and all other fields are NULL or 0, the HTTP driver will queue a receive
+ token to underlying TCP instance. If data arrives in the receive buffer, up to
+ BodyLength bytes of data will be copied to Body. The HTTP driver will then update
+ BodyLength with the amount of bytes received and copied to Body.
+
+ If the HTTP driver does not have an open underlying TCP connection with the host
+ specified in the response URL, Request() will return EFI_ACCESS_DENIED. This is
+ consistent with RFC 2616 recommendation that HTTP clients should attempt to maintain
+ an open TCP connection between client and host.
+
+ @param[in] This Pointer to EFI_HTTP_PROTOCOL instance.
+ @param[in] Token Pointer to storage containing HTTP response token.
+
+ @retval EFI_SUCCESS Allocation succeeded.
+ @retval EFI_NOT_STARTED This EFI HTTP Protocol instance has not been
+ initialized.
+ @retval EFI_INVALID_PARAMETER One or more of the following conditions is TRUE:
+ This is NULL.
+ Token is NULL.
+ Token->Message->Headers is NULL.
+ Token->Message is NULL.
+ Token->Message->Body is not NULL,
+ Token->Message->BodyLength is non-zero, and
+ Token->Message->Data is NULL, but a previous call to
+ Response() has not been completed successfully.
+ @retval EFI_OUT_OF_RESOURCES Could not allocate enough system resources.
+ @retval EFI_ACCESS_DENIED An open TCP connection is not present with the host
+ specified by response URL.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_HTTP_RESPONSE)(
+ IN EFI_HTTP_PROTOCOL *This,
+ IN EFI_HTTP_TOKEN *Token
+ );
+
+/**
+ The Poll() function can be used by network drivers and applications to increase the
+ rate that data packets are moved between the communication devices and the transmit
+ and receive queues.
+
+ In some systems, the periodic timer event in the managed network driver may not poll
+ the underlying communications device fast enough to transmit and/or receive all data
+ packets without missing incoming packets or dropping outgoing packets. Drivers and
+ applications that are experiencing packet loss should try calling the Poll() function
+ more often.
+
+ @param[in] This Pointer to EFI_HTTP_PROTOCOL instance.
+
+ @retval EFI_SUCCESS Incoming or outgoing data was processed..
+ @retval EFI_DEVICE_ERROR An unexpected system or network error occurred
+ @retval EFI_INVALID_PARAMETER This is NULL.
+ @retval EFI_NOT_READY No incoming or outgoing data is processed.
+ @retval EFI_NOT_STARTED This EFI HTTP Protocol instance has not been started.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_HTTP_POLL)(
+ IN EFI_HTTP_PROTOCOL *This
+ );
+
+///
+/// The EFI HTTP protocol is designed to be used by EFI drivers and applications to
+/// create and transmit HTTP Requests, as well as handle HTTP responses that are
+/// returned by a remote host. This EFI protocol uses and relies on an underlying EFI
+/// TCP protocol.
+///
+struct _EFI_HTTP_PROTOCOL {
+ EFI_HTTP_GET_MODE_DATA GetModeData;
+ EFI_HTTP_CONFIGURE Configure;
+ EFI_HTTP_REQUEST Request;
+ EFI_HTTP_CANCEL Cancel;
+ EFI_HTTP_RESPONSE Response;
+ EFI_HTTP_POLL Poll;
+};
+
+extern EFI_GUID gEfiHttpServiceBindingProtocolGuid;
+extern EFI_GUID gEfiHttpProtocolGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/HttpBootCallback.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/HttpBootCallback.h
new file mode 100644
index 0000000000..d25600831b
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/HttpBootCallback.h
@@ -0,0 +1,98 @@
+/** @file
+ This file defines the EFI HTTP Boot Callback Protocol interface.
+
+ Copyright (c) 2017 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Revision Reference:
+ This Protocol is introduced in UEFI Specification 2.7
+
+**/
+
+#ifndef __EFI_HTTP_BOOT_CALLBACK_H__
+#define __EFI_HTTP_BOOT_CALLBACK_H__
+
+#define EFI_HTTP_BOOT_CALLBACK_PROTOCOL_GUID \
+ { \
+ 0xba23b311, 0x343d, 0x11e6, {0x91, 0x85, 0x58, 0x20, 0xb1, 0xd6, 0x52, 0x99} \
+ }
+
+typedef struct _EFI_HTTP_BOOT_CALLBACK_PROTOCOL EFI_HTTP_BOOT_CALLBACK_PROTOCOL;
+
+///
+/// EFI_HTTP_BOOT_CALLBACK_DATA_TYPE
+///
+typedef enum {
+ ///
+ /// Data points to a DHCP4 packet which is about to transmit or has received.
+ ///
+ HttpBootDhcp4,
+ ///
+ /// Data points to a DHCP6 packet which is about to be transmit or has received.
+ ///
+ HttpBootDhcp6,
+ ///
+ /// Data points to an EFI_HTTP_MESSAGE structure, which contains a HTTP request message
+ /// to be transmitted.
+ ///
+ HttpBootHttpRequest,
+ ///
+ /// Data points to an EFI_HTTP_MESSAGE structure, which contians a received HTTP
+ /// response message.
+ ///
+ HttpBootHttpResponse,
+ ///
+ /// Part of the entity body has been received from the HTTP server. Data points to the
+ /// buffer of the entity body data.
+ ///
+ HttpBootHttpEntityBody,
+ ///
+ /// Data points to the authentication information to provide to the HTTP server.
+ ///
+ HttpBootHttpAuthInfo,
+ HttpBootTypeMax
+} EFI_HTTP_BOOT_CALLBACK_DATA_TYPE;
+
+/**
+ Callback function that is invoked when the HTTP Boot driver is about to transmit or has received a
+ packet.
+
+ This function is invoked when the HTTP Boot driver is about to transmit or has received packet.
+ Parameters DataType and Received specify the type of event and the format of the buffer pointed
+ to by Data. Due to the polling nature of UEFI device drivers, this callback function should not
+ execute for more than 5 ms.
+ The returned status code determines the behavior of the HTTP Boot driver.
+
+ @param[in] This Pointer to the EFI_HTTP_BOOT_CALLBACK_PROTOCOL instance.
+ @param[in] DataType The event that occurs in the current state.
+ @param[in] Received TRUE if the callback is being invoked due to a receive event.
+ FALSE if the callback is being invoked due to a transmit event.
+ @param[in] DataLength The length in bytes of the buffer pointed to by Data.
+ @param[in] Data A pointer to the buffer of data, the data type is specified by
+ DataType.
+
+ @retval EFI_SUCCESS Tells the HTTP Boot driver to continue the HTTP Boot process.
+ @retval EFI_ABORTED Tells the HTTP Boot driver to abort the current HTTP Boot process.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_HTTP_BOOT_CALLBACK)(
+ IN EFI_HTTP_BOOT_CALLBACK_PROTOCOL *This,
+ IN EFI_HTTP_BOOT_CALLBACK_DATA_TYPE DataType,
+ IN BOOLEAN Received,
+ IN UINT32 DataLength,
+ IN VOID *Data OPTIONAL
+ );
+
+///
+/// EFI HTTP Boot Callback Protocol is invoked when the HTTP Boot driver is about to transmit or
+/// has received a packet. The EFI HTTP Boot Callback Protocol must be installed on the same handle
+/// as the Load File Protocol for the HTTP Boot.
+///
+struct _EFI_HTTP_BOOT_CALLBACK_PROTOCOL {
+ EFI_HTTP_BOOT_CALLBACK Callback;
+};
+
+extern EFI_GUID gEfiHttpBootCallbackProtocolGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/HttpUtilities.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/HttpUtilities.h
new file mode 100644
index 0000000000..42ba2e98ca
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/HttpUtilities.h
@@ -0,0 +1,116 @@
+/** @file
+ EFI HTTP Utilities protocol provides a platform independent abstraction for HTTP
+ message comprehension.
+
+ Copyright (c) 2015, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Revision Reference:
+ This Protocol is introduced in UEFI Specification 2.5
+
+**/
+
+#ifndef __EFI_HTTP_UTILITIES_PROTOCOL_H__
+#define __EFI_HTTP_UTILITIES_PROTOCOL_H__
+
+#include
+
+#define EFI_HTTP_UTILITIES_PROTOCOL_GUID \
+ { \
+ 0x3e35c163, 0x4074, 0x45dd, {0x43, 0x1e, 0x23, 0x98, 0x9d, 0xd8, 0x6b, 0x32 } \
+ }
+
+typedef struct _EFI_HTTP_UTILITIES_PROTOCOL EFI_HTTP_UTILITIES_PROTOCOL;
+
+/**
+ Create HTTP header based on a combination of seed header, fields
+ to delete, and fields to append.
+
+ The Build() function is used to manage the headers portion of an
+ HTTP message by providing the ability to add, remove, or replace
+ HTTP headers.
+
+ @param[in] This Pointer to EFI_HTTP_UTILITIES_PROTOCOL instance.
+ @param[in] SeedMessageSize Size of the initial HTTP header. This can be zero.
+ @param[in] SeedMessage Initial HTTP header to be used as a base for
+ building a new HTTP header. If NULL,
+ SeedMessageSize is ignored.
+ @param[in] DeleteCount Number of null-terminated HTTP header field names
+ in DeleteList.
+ @param[in] DeleteList List of null-terminated HTTP header field names to
+ remove from SeedMessage. Only the field names are
+ in this list because the field values are irrelevant
+ to this operation.
+ @param[in] AppendCount Number of header fields in AppendList.
+ @param[in] AppendList List of HTTP headers to populate NewMessage with.
+ If SeedMessage is not NULL, AppendList will be
+ appended to the existing list from SeedMessage in
+ NewMessage.
+ @param[out] NewMessageSize Pointer to number of header fields in NewMessage.
+ @param[out] NewMessage Pointer to a new list of HTTP headers based on.
+
+ @retval EFI_SUCCESS Add, remove, and replace operations succeeded.
+ @retval EFI_OUT_OF_RESOURCES Could not allocate memory for NewMessage.
+ @retval EFI_INVALID_PARAMETER One or more of the following conditions is TRUE:
+ This is NULL.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_HTTP_UTILS_BUILD)(
+ IN EFI_HTTP_UTILITIES_PROTOCOL *This,
+ IN UINTN SeedMessageSize,
+ IN VOID *SeedMessage OPTIONAL,
+ IN UINTN DeleteCount,
+ IN CHAR8 *DeleteList[] OPTIONAL,
+ IN UINTN AppendCount,
+ IN EFI_HTTP_HEADER *AppendList[] OPTIONAL,
+ OUT UINTN *NewMessageSize,
+ OUT VOID **NewMessage
+ );
+
+/**
+ Parses HTTP header and produces an array of key/value pairs.
+
+ The Parse() function is used to transform data stored in HttpHeader
+ into a list of fields paired with their corresponding values.
+
+ @param[in] This Pointer to EFI_HTTP_UTILITIES_PROTOCOL instance.
+ @param[in] HttpMessage Contains raw unformatted HTTP header string.
+ @param[in] HttpMessageSize Size of HTTP header.
+ @param[out] HeaderFields Array of key/value header pairs.
+ @param[out] FieldCount Number of headers in HeaderFields.
+
+ @retval EFI_SUCCESS Allocation succeeded.
+ @retval EFI_NOT_STARTED This EFI HTTP Protocol instance has not been
+ initialized.
+ @retval EFI_INVALID_PARAMETER One or more of the following conditions is TRUE:
+ This is NULL.
+ HttpMessage is NULL.
+ HeaderFields is NULL.
+ FieldCount is NULL.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_HTTP_UTILS_PARSE)(
+ IN EFI_HTTP_UTILITIES_PROTOCOL *This,
+ IN CHAR8 *HttpMessage,
+ IN UINTN HttpMessageSize,
+ OUT EFI_HTTP_HEADER **HeaderFields,
+ OUT UINTN *FieldCount
+ );
+
+///
+/// EFI_HTTP_UTILITIES_PROTOCOL
+/// designed to be used by EFI drivers and applications to parse HTTP
+/// headers from a byte stream. This driver is neither dependent on
+/// network connectivity, nor the existence of an underlying network
+/// infrastructure.
+///
+struct _EFI_HTTP_UTILITIES_PROTOCOL {
+ EFI_HTTP_UTILS_BUILD Build;
+ EFI_HTTP_UTILS_PARSE Parse;
+};
+
+extern EFI_GUID gEfiHttpUtilitiesProtocolGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/I2cBusConfigurationManagement.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/I2cBusConfigurationManagement.h
new file mode 100644
index 0000000000..76523bedea
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/I2cBusConfigurationManagement.h
@@ -0,0 +1,164 @@
+/** @file
+ I2C Bus Configuration Management Protocol as defined in the PI 1.3 specification.
+
+ The EFI I2C bus configuration management protocol provides platform specific
+ services that allow the I2C host protocol to reconfigure the switches and multiplexers
+ and set the clock frequency for the I2C bus. This protocol also enables the I2C host protocol
+ to reset an I2C device which may be locking up the I2C bus by holding the clock or data line low.
+
+ Copyright (c) 2013 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Revision Reference:
+ This protocol is from PI Version 1.3.
+
+**/
+
+#ifndef __I2C_BUS_CONFIGURATION_MANAGEMENT_H__
+#define __I2C_BUS_CONFIGURATION_MANAGEMENT_H__
+
+#define EFI_I2C_BUS_CONFIGURATION_MANAGEMENT_PROTOCOL_GUID \
+ { 0x55b71fb5, 0x17c6, 0x410e, { 0xb5, 0xbd, 0x5f, 0xa2, 0xe3, 0xd4, 0x46, 0x6b }}
+
+///
+/// I2C bus configuration management protocol
+///
+/// The EFI I2C bus configuration management protocol provides platform
+/// specific services that allow the I2C host protocol to reconfigure the
+/// switches and multiplexers and set the clock frequency for the I2C bus.
+/// This protocol also enables the I2C host protocol to reset an I2C device
+/// which may be locking up the I2C bus by holding the clock or data line
+/// low.
+///
+/// The I2C protocol stack uses the concept of an I2C bus configuration as
+/// a way to describe a particular state of the switches and multiplexers
+/// in the I2C bus.
+///
+/// A simple I2C bus does not have any multiplexers or switches is described
+/// to the I2C protocol stack with a single I2C bus configuration which
+/// specifies the I2C bus frequency.
+///
+/// An I2C bus with switches and multiplexers use an I2C bus configuration
+/// to describe each of the unique settings for the switches and multiplexers
+/// and the I2C bus frequency. However the I2C bus configuration management
+/// protocol only needs to define the I2C bus configurations that the software
+/// uses, which may be a subset of the total.
+///
+/// The I2C bus configuration description includes a list of I2C devices
+/// which may be accessed when this I2C bus configuration is enabled. I2C
+/// devices before a switch or multiplexer must be included in one I2C bus
+/// configuration while I2C devices after a switch or multiplexer are on
+/// another I2C bus configuration.
+///
+/// The I2C bus configuration management protocol is an optional protocol.
+/// When the I2C bus configuration protocol is not defined the I2C host
+/// protocol does not start and the I2C master protocol may be used for
+/// other purposes such as SMBus traffic. When the I2C bus configuration
+/// protocol is available, the I2C host protocol uses the I2C bus
+/// configuration protocol to call into the platform specific code to set
+/// the switches and multiplexers and set the maximum I2C bus frequency.
+///
+/// The platform designers determine the maximum I2C bus frequency by
+/// selecting a frequency which supports all of the I2C devices on the
+/// I2C bus for the setting of switches and multiplexers. The platform
+/// designers must validate this against the I2C device data sheets and
+/// any limits of the I2C controller or bus length.
+///
+/// During I2C device enumeration, the I2C bus driver retrieves the I2C
+/// bus configuration that must be used to perform I2C transactions to
+/// each I2C device. This I2C bus configuration value is passed into
+/// the I2C host protocol to identify the I2C bus configuration required
+/// to access a specific I2C device. The I2C host protocol calls
+/// EnableBusConfiguration() to set the switches and multiplexers in the
+/// I2C bus and the I2C clock frequency. The I2C host protocol may
+/// optimize calls to EnableBusConfiguration() by only making the call
+/// when the I2C bus configuration value changes between I2C requests.
+///
+/// When I2C transactions are required on the same I2C bus to change the
+/// state of multiplexers or switches, the I2C master protocol must be
+/// used to perform the necessary I2C transactions.
+///
+/// It is up to the platform specific code to choose the proper I2C bus
+/// configuration when ExitBootServices() is called. Some operating systems
+/// are not able to manage the I2C bus configurations and must use the I2C
+/// bus configuration that is established by the platform firmware before
+/// ExitBootServices() returns.
+///
+typedef struct _EFI_I2C_BUS_CONFIGURATION_MANAGEMENT_PROTOCOL EFI_I2C_BUS_CONFIGURATION_MANAGEMENT_PROTOCOL;
+
+/**
+ Enable access to an I2C bus configuration.
+
+ This routine must be called at or below TPL_NOTIFY. For synchronous
+ requests this routine must be called at or below TPL_CALLBACK.
+
+ Reconfigure the switches and multiplexers in the I2C bus to enable
+ access to a specific I2C bus configuration. Also select the maximum
+ clock frequency for this I2C bus configuration.
+
+ This routine uses the I2C Master protocol to perform I2C transactions
+ on the local bus. This eliminates any recursion in the I2C stack for
+ configuration transactions on the same I2C bus. This works because the
+ local I2C bus is idle while the I2C bus configuration is being enabled.
+
+ If I2C transactions must be performed on other I2C busses, then the
+ EFI_I2C_HOST_PROTOCOL, the EFI_I2C_IO_PROTCOL, or a third party I2C
+ driver interface for a specific device must be used. This requirement
+ is because the I2C host protocol controls the flow of requests to the
+ I2C controller. Use the EFI_I2C_HOST_PROTOCOL when the I2C device is
+ not enumerated by the EFI_I2C_ENUMERATE_PROTOCOL. Use a protocol
+ produced by a third party driver when it is available or the
+ EFI_I2C_IO_PROTOCOL when the third party driver is not available but
+ the device is enumerated with the EFI_I2C_ENUMERATE_PROTOCOL.
+
+ When Event is NULL, EnableI2cBusConfiguration operates synchronously
+ and returns the I2C completion status as its return value.
+
+ @param[in] This Pointer to an EFI_I2C_BUS_CONFIGURATION_MANAGEMENT_PROTOCOL
+ structure.
+ @param[in] I2cBusConfiguration Index of an I2C bus configuration. All
+ values in the range of zero to N-1 are
+ valid where N is the total number of I2C
+ bus configurations for an I2C bus.
+ @param[in] Event Event to signal when the transaction is complete
+ @param[out] I2cStatus Buffer to receive the transaction status.
+
+ @return When Event is NULL, EnableI2cBusConfiguration operates synchrouously
+ and returns the I2C completion status as its return value. In this case it is
+ recommended to use NULL for I2cStatus. The values returned from
+ EnableI2cBusConfiguration are:
+
+ @retval EFI_SUCCESS The asynchronous bus configuration request
+ was successfully started when Event is not
+ NULL.
+ @retval EFI_SUCCESS The bus configuration request completed
+ successfully when Event is NULL.
+ @retval EFI_DEVICE_ERROR The bus configuration failed.
+ @retval EFI_NO_MAPPING Invalid I2cBusConfiguration value
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_I2C_BUS_CONFIGURATION_MANAGEMENT_PROTOCOL_ENABLE_I2C_BUS_CONFIGURATION)(
+ IN CONST EFI_I2C_BUS_CONFIGURATION_MANAGEMENT_PROTOCOL *This,
+ IN UINTN I2cBusConfiguration,
+ IN EFI_EVENT Event OPTIONAL,
+ IN EFI_STATUS *I2cStatus OPTIONAL
+ );
+
+///
+/// I2C bus configuration management protocol
+///
+struct _EFI_I2C_BUS_CONFIGURATION_MANAGEMENT_PROTOCOL {
+ ///
+ /// Enable an I2C bus configuration for use.
+ ///
+ EFI_I2C_BUS_CONFIGURATION_MANAGEMENT_PROTOCOL_ENABLE_I2C_BUS_CONFIGURATION EnableI2cBusConfiguration;
+};
+
+///
+/// Reference to variable defined in the .DEC file
+///
+extern EFI_GUID gEfiI2cBusConfigurationManagementProtocolGuid;
+
+#endif // __I2C_BUS_CONFIGURATION_MANAGEMENT_H__
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/I2cEnumerate.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/I2cEnumerate.h
new file mode 100644
index 0000000000..e49f0dfeaf
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/I2cEnumerate.h
@@ -0,0 +1,104 @@
+/** @file
+ I2C Device Enumerate Protocol as defined in the PI 1.3 specification.
+
+ This protocol supports the enumerations of device on the I2C bus.
+
+ Copyright (c) 2013 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Revision Reference:
+ This protocol is from PI Version 1.3.
+
+**/
+
+#ifndef __I2C_ENUMERATE_H__
+#define __I2C_ENUMERATE_H__
+
+#include
+
+#define EFI_I2C_ENUMERATE_PROTOCOL_GUID { 0xda8cd7c4, 0x1c00, 0x49e2, { 0x80, 0x3e, 0x52, 0x14, 0xe7, 0x01, 0x89, 0x4c }}
+
+typedef struct _EFI_I2C_ENUMERATE_PROTOCOL EFI_I2C_ENUMERATE_PROTOCOL;
+
+/**
+ Enumerate the I2C devices
+
+ This function enables the caller to traverse the set of I2C devices
+ on an I2C bus.
+
+ @param[in] This The platform data for the next device on
+ the I2C bus was returned successfully.
+ @param[in, out] Device Pointer to a buffer containing an
+ EFI_I2C_DEVICE structure. Enumeration is
+ started by setting the initial EFI_I2C_DEVICE
+ structure pointer to NULL. The buffer
+ receives an EFI_I2C_DEVICE structure pointer
+ to the next I2C device.
+
+ @retval EFI_SUCCESS The platform data for the next device on
+ the I2C bus was returned successfully.
+ @retval EFI_INVALID_PARAMETER Device is NULL
+ @retval EFI_NO_MAPPING *Device does not point to a valid
+ EFI_I2C_DEVICE structure returned in a
+ previous call Enumerate().
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_I2C_ENUMERATE_PROTOCOL_ENUMERATE)(
+ IN CONST EFI_I2C_ENUMERATE_PROTOCOL *This,
+ IN OUT CONST EFI_I2C_DEVICE **Device
+ );
+
+/**
+ Get the requested I2C bus frequency for a specified bus configuration.
+
+ This function returns the requested I2C bus clock frequency for the
+ I2cBusConfiguration. This routine is provided for diagnostic purposes
+ and is meant to be called after calling Enumerate to get the
+ I2cBusConfiguration value.
+
+ @param[in] This Pointer to an EFI_I2C_ENUMERATE_PROTOCOL
+ structure.
+ @param[in] I2cBusConfiguration I2C bus configuration to access the I2C
+ device
+ @param[out] *BusClockHertz Pointer to a buffer to receive the I2C
+ bus clock frequency in Hertz
+
+ @retval EFI_SUCCESS The I2C bus frequency was returned
+ successfully.
+ @retval EFI_INVALID_PARAMETER BusClockHertz was NULL
+ @retval EFI_NO_MAPPING Invalid I2cBusConfiguration value
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_I2C_ENUMERATE_PROTOCOL_GET_BUS_FREQUENCY)(
+ IN CONST EFI_I2C_ENUMERATE_PROTOCOL *This,
+ IN UINTN I2cBusConfiguration,
+ OUT UINTN *BusClockHertz
+ );
+
+///
+/// I2C Enumerate protocol
+///
+struct _EFI_I2C_ENUMERATE_PROTOCOL {
+ ///
+ /// Traverse the set of I2C devices on an I2C bus. This routine
+ /// returns the next I2C device on an I2C bus.
+ ///
+ EFI_I2C_ENUMERATE_PROTOCOL_ENUMERATE Enumerate;
+
+ ///
+ /// Get the requested I2C bus frequency for a specified bus
+ /// configuration.
+ ///
+ EFI_I2C_ENUMERATE_PROTOCOL_GET_BUS_FREQUENCY GetBusFrequency;
+};
+
+///
+/// Reference to variable defined in the .DEC file
+///
+extern EFI_GUID gEfiI2cEnumerateProtocolGuid;
+
+#endif // __I2C_ENUMERATE_H__
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/I2cHost.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/I2cHost.h
new file mode 100644
index 0000000000..732c8301a3
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/I2cHost.h
@@ -0,0 +1,145 @@
+/** @file
+ I2C Host Protocol as defined in the PI 1.3 specification.
+
+ This protocol provides callers with the ability to do I/O transactions
+ to all of the devices on the I2C bus.
+
+ Copyright (c) 2013 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Revision Reference:
+ This protocol is from PI Version 1.3.
+
+**/
+
+#ifndef __I2C_HOST_H__
+#define __I2C_HOST_H__
+
+#include
+
+#define EFI_I2C_HOST_PROTOCOL_GUID { 0xa5aab9e3, 0xc727, 0x48cd, { 0x8b, 0xbf, 0x42, 0x72, 0x33, 0x85, 0x49, 0x48 }}
+
+///
+/// I2C Host Protocol
+///
+/// The I2C bus driver uses the services of the EFI_I2C_HOST_PROTOCOL
+/// to produce an instance of the EFI_I2C_IO_PROTOCOL for each I2C
+/// device on an I2C bus.
+///
+/// The EFI_I2C_HOST_PROTOCOL exposes an asynchronous interface to
+/// callers to perform transactions to any device on the I2C bus.
+/// Internally, the I2C host protocol manages the flow of the I2C
+/// transactions to the host controller, keeping them in FIFO order.
+/// Prior to each transaction, the I2C host protocol ensures that the
+/// switches and multiplexers are properly configured. The I2C host
+/// protocol then starts the transaction on the host controller using
+/// the EFI_I2C_MASTER_PROTOCOL.
+///
+typedef struct _EFI_I2C_HOST_PROTOCOL EFI_I2C_HOST_PROTOCOL;
+
+/**
+ Queue an I2C transaction for execution on the I2C controller.
+
+ This routine must be called at or below TPL_NOTIFY. For
+ synchronous requests this routine must be called at or below
+ TPL_CALLBACK.
+
+ The I2C host protocol uses the concept of I2C bus configurations
+ to describe the I2C bus. An I2C bus configuration is defined as
+ a unique setting of the multiplexers and switches in the I2C bus
+ which enable access to one or more I2C devices. When using a
+ switch to divide a bus, due to bus frequency differences, the
+ I2C bus configuration management protocol defines an I2C bus
+ configuration for the I2C devices on each side of the switch.
+ When using a multiplexer, the I2C bus configuration management
+ defines an I2C bus configuration for each of the selector values
+ required to control the multiplexer. See Figure 1 in the I2C -bus
+ specification and user manual for a complex I2C bus configuration.
+
+ The I2C host protocol processes all transactions in FIFO order.
+ Prior to performing the transaction, the I2C host protocol calls
+ EnableI2cBusConfiguration to reconfigure the switches and
+ multiplexers in the I2C bus enabling access to the specified I2C
+ device. The EnableI2cBusConfiguration also selects the I2C bus
+ frequency for the I2C device. After the I2C bus is configured,
+ the I2C host protocol calls the I2C master protocol to start the
+ I2C transaction.
+
+ When Event is NULL, QueueRequest() operates synchronously and
+ returns the I2C completion status as its return value.
+
+ When Event is not NULL, QueueRequest() synchronously returns
+ EFI_SUCCESS indicating that the asynchronously I2C transaction was
+ queued. The values above are returned in the buffer pointed to by
+ I2cStatus upon the completion of the I2C transaction when I2cStatus
+ is not NULL.
+
+ @param[in] This Pointer to an EFI_I2C_HOST_PROTOCOL structure.
+ @param[in] I2cBusConfiguration I2C bus configuration to access the I2C
+ device
+ @param[in] SlaveAddress Address of the device on the I2C bus. Set
+ the I2C_ADDRESSING_10_BIT when using 10-bit
+ addresses, clear this bit for 7-bit addressing.
+ Bits 0-6 are used for 7-bit I2C slave addresses
+ and bits 0-9 are used for 10-bit I2C slave
+ addresses.
+ @param[in] Event Event to signal for asynchronous transactions,
+ NULL for synchronous transactions
+ @param[in] RequestPacket Pointer to an EFI_I2C_REQUEST_PACKET structure
+ describing the I2C transaction
+ @param[out] I2cStatus Optional buffer to receive the I2C transaction
+ completion status
+
+ @retval EFI_SUCCESS The asynchronous transaction was successfully
+ queued when Event is not NULL.
+ @retval EFI_SUCCESS The transaction completed successfully when
+ Event is NULL.
+ @retval EFI_BAD_BUFFER_SIZE The RequestPacket->LengthInBytes value is
+ too large.
+ @retval EFI_DEVICE_ERROR There was an I2C error (NACK) during the
+ transaction.
+ @retval EFI_INVALID_PARAMETER RequestPacket is NULL
+ @retval EFI_NOT_FOUND Reserved bit set in the SlaveAddress parameter
+ @retval EFI_NO_MAPPING Invalid I2cBusConfiguration value
+ @retval EFI_NO_RESPONSE The I2C device is not responding to the slave
+ address. EFI_DEVICE_ERROR will be returned
+ if the controller cannot distinguish when the
+ NACK occurred.
+ @retval EFI_OUT_OF_RESOURCES Insufficient memory for I2C transaction
+ @retval EFI_UNSUPPORTED The controller does not support the requested
+ transaction.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_I2C_HOST_PROTOCOL_QUEUE_REQUEST)(
+ IN CONST EFI_I2C_HOST_PROTOCOL *This,
+ IN UINTN I2cBusConfiguration,
+ IN UINTN SlaveAddress,
+ IN EFI_EVENT Event OPTIONAL,
+ IN EFI_I2C_REQUEST_PACKET *RequestPacket,
+ OUT EFI_STATUS *I2cStatus OPTIONAL
+ );
+
+///
+/// I2C Host Protocol
+///
+struct _EFI_I2C_HOST_PROTOCOL {
+ ///
+ /// Queue an I2C transaction for execution on the I2C bus
+ ///
+ EFI_I2C_HOST_PROTOCOL_QUEUE_REQUEST QueueRequest;
+
+ ///
+ /// Pointer to an EFI_I2C_CONTROLLER_CAPABILITIES data structure
+ /// containing the capabilities of the I2C host controller.
+ ///
+ CONST EFI_I2C_CONTROLLER_CAPABILITIES *I2cControllerCapabilities;
+};
+
+///
+/// Reference to variable defined in the .DEC file
+///
+extern EFI_GUID gEfiI2cHostProtocolGuid;
+
+#endif // __I2C_HOST_H__
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/I2cIo.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/I2cIo.h
new file mode 100644
index 0000000000..d9bfcea58a
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/I2cIo.h
@@ -0,0 +1,165 @@
+/** @file
+ I2C I/O Protocol as defined in the PI 1.3 specification.
+
+ The EFI I2C I/O protocol enables the user to manipulate a single
+ I2C device independent of the host controller and I2C design.
+
+ Copyright (c) 2013 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Revision Reference:
+ This protocol is from PI Version 1.3.
+
+**/
+
+#ifndef __I2C_IO_H__
+#define __I2C_IO_H__
+
+#include
+
+#define EFI_I2C_IO_PROTOCOL_GUID { 0xb60a3e6b, 0x18c4, 0x46e5, { 0xa2, 0x9a, 0xc9, 0xa1, 0x06, 0x65, 0xa2, 0x8e }}
+
+///
+/// I2C I/O protocol
+///
+/// The I2C IO protocol enables access to a specific device on the I2C
+/// bus.
+///
+/// Each I2C device is identified uniquely in the system by the tuple
+/// DeviceGuid:DeviceIndex. The DeviceGuid represents the manufacture
+/// and part number and is provided by the silicon vendor or the third
+/// party I2C device driver writer. The DeviceIndex identifies the part
+/// within the system by using a unique number and is created by the
+/// board designer or the writer of the EFI_I2C_ENUMERATE_PROTOCOL.
+///
+/// I2C slave addressing is abstracted to validate addresses and limit
+/// operation to the specified I2C device. The third party providing
+/// the I2C device support provides an ordered list of slave addresses
+/// for the I2C device required to implement the EFI_I2C_ENUMERATE_PROTOCOL.
+/// The order of the list must be preserved.
+///
+typedef struct _EFI_I2C_IO_PROTOCOL EFI_I2C_IO_PROTOCOL;
+
+/**
+ Queue an I2C transaction for execution on the I2C device.
+
+ This routine must be called at or below TPL_NOTIFY. For synchronous
+ requests this routine must be called at or below TPL_CALLBACK.
+
+ This routine queues an I2C transaction to the I2C controller for
+ execution on the I2C bus.
+
+ When Event is NULL, QueueRequest() operates synchronously and returns
+ the I2C completion status as its return value.
+
+ When Event is not NULL, QueueRequest() synchronously returns EFI_SUCCESS
+ indicating that the asynchronous I2C transaction was queued. The values
+ above are returned in the buffer pointed to by I2cStatus upon the
+ completion of the I2C transaction when I2cStatus is not NULL.
+
+ The upper layer driver writer provides the following to the platform
+ vendor:
+
+ 1. Vendor specific GUID for the I2C part
+ 2. Guidance on proper construction of the slave address array when the
+ I2C device uses more than one slave address. The I2C bus protocol
+ uses the SlaveAddressIndex to perform relative to physical address
+ translation to access the blocks of hardware within the I2C device.
+
+ @param[in] This Pointer to an EFI_I2C_IO_PROTOCOL structure.
+ @param[in] SlaveAddressIndex Index value into an array of slave addresses
+ for the I2C device. The values in the array
+ are specified by the board designer, with the
+ third party I2C device driver writer providing
+ the slave address order.
+
+ For devices that have a single slave address,
+ this value must be zero. If the I2C device
+ uses more than one slave address then the
+ third party (upper level) I2C driver writer
+ needs to specify the order of entries in the
+ slave address array.
+
+ \ref ThirdPartyI2cDrivers "Third Party I2C
+ Drivers" section in I2cMaster.h.
+ @param[in] Event Event to signal for asynchronous transactions,
+ NULL for synchronous transactions
+ @param[in] RequestPacket Pointer to an EFI_I2C_REQUEST_PACKET structure
+ describing the I2C transaction
+ @param[out] I2cStatus Optional buffer to receive the I2C transaction
+ completion status
+
+ @retval EFI_SUCCESS The asynchronous transaction was successfully
+ queued when Event is not NULL.
+ @retval EFI_SUCCESS The transaction completed successfully when
+ Event is NULL.
+ @retval EFI_BAD_BUFFER_SIZE The RequestPacket->LengthInBytes value is too
+ large.
+ @retval EFI_DEVICE_ERROR There was an I2C error (NACK) during the
+ transaction.
+ @retval EFI_INVALID_PARAMETER RequestPacket is NULL.
+ @retval EFI_NO_MAPPING The EFI_I2C_HOST_PROTOCOL could not set the
+ bus configuration required to access this I2C
+ device.
+ @retval EFI_NO_RESPONSE The I2C device is not responding to the slave
+ address selected by SlaveAddressIndex.
+ EFI_DEVICE_ERROR will be returned if the
+ controller cannot distinguish when the NACK
+ occurred.
+ @retval EFI_OUT_OF_RESOURCES Insufficient memory for I2C transaction
+ @retval EFI_UNSUPPORTED The controller does not support the requested
+ transaction.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_I2C_IO_PROTOCOL_QUEUE_REQUEST)(
+ IN CONST EFI_I2C_IO_PROTOCOL *This,
+ IN UINTN SlaveAddressIndex,
+ IN EFI_EVENT Event OPTIONAL,
+ IN EFI_I2C_REQUEST_PACKET *RequestPacket,
+ OUT EFI_STATUS *I2cStatus OPTIONAL
+ );
+
+///
+/// I2C I/O protocol
+///
+struct _EFI_I2C_IO_PROTOCOL {
+ ///
+ /// Queue an I2C transaction for execution on the I2C device.
+ ///
+ EFI_I2C_IO_PROTOCOL_QUEUE_REQUEST QueueRequest;
+
+ ///
+ /// Unique value assigned by the silicon manufacture or the third
+ /// party I2C driver writer for the I2C part. This value logically
+ /// combines both the manufacture name and the I2C part number into
+ /// a single value specified as a GUID.
+ ///
+ CONST EFI_GUID *DeviceGuid;
+
+ ///
+ /// Unique ID of the I2C part within the system
+ ///
+ UINT32 DeviceIndex;
+
+ ///
+ /// Hardware revision - ACPI _HRV value. See the Advanced Configuration
+ /// and Power Interface Specification, Revision 5.0 for the field format
+ /// and the Plug and play support for I2C web-page for restriction on values.
+ ///
+ UINT32 HardwareRevision;
+
+ ///
+ /// Pointer to an EFI_I2C_CONTROLLER_CAPABILITIES data structure containing
+ /// the capabilities of the I2C host controller.
+ ///
+ CONST EFI_I2C_CONTROLLER_CAPABILITIES *I2cControllerCapabilities;
+};
+
+///
+/// Reference to variable defined in the .DEC file
+///
+extern EFI_GUID gEfiI2cIoProtocolGuid;
+
+#endif // __I2C_IO_H__
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/I2cMaster.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/I2cMaster.h
new file mode 100644
index 0000000000..31737072a6
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/I2cMaster.h
@@ -0,0 +1,186 @@
+/** @file
+ I2C Master Protocol as defined in the PI 1.3 specification.
+
+ This protocol manipulates the I2C host controller to perform transactions as a master
+ on the I2C bus using the current state of any switches or multiplexers in the I2C bus.
+
+ Copyright (c) 2013 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Revision Reference:
+ This protocol is from PI Version 1.3.
+
+**/
+
+#ifndef __I2C_MASTER_H__
+#define __I2C_MASTER_H__
+
+#include
+
+#define EFI_I2C_MASTER_PROTOCOL_GUID { 0xcd72881f, 0x45b5, 0x4feb, { 0x98, 0xc8, 0x31, 0x3d, 0xa8, 0x11, 0x74, 0x62 }}
+
+typedef struct _EFI_I2C_MASTER_PROTOCOL EFI_I2C_MASTER_PROTOCOL;
+
+/**
+ Set the frequency for the I2C clock line.
+
+ This routine must be called at or below TPL_NOTIFY.
+
+ The software and controller do a best case effort of using the specified
+ frequency for the I2C bus. If the frequency does not match exactly then
+ the I2C master protocol selects the next lower frequency to avoid
+ exceeding the operating conditions for any of the I2C devices on the bus.
+ For example if 400 KHz was specified and the controller's divide network
+ only supports 402 KHz or 398 KHz then the I2C master protocol selects 398
+ KHz. If there are not lower frequencies available, then return
+ EFI_UNSUPPORTED.
+
+ @param[in] This Pointer to an EFI_I2C_MASTER_PROTOCOL structure
+ @param[in] BusClockHertz Pointer to the requested I2C bus clock frequency
+ in Hertz. Upon return this value contains the
+ actual frequency in use by the I2C controller.
+
+ @retval EFI_SUCCESS The bus frequency was set successfully.
+ @retval EFI_ALREADY_STARTED The controller is busy with another transaction.
+ @retval EFI_INVALID_PARAMETER BusClockHertz is NULL
+ @retval EFI_UNSUPPORTED The controller does not support this frequency.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_I2C_MASTER_PROTOCOL_SET_BUS_FREQUENCY)(
+ IN CONST EFI_I2C_MASTER_PROTOCOL *This,
+ IN OUT UINTN *BusClockHertz
+ );
+
+/**
+ Reset the I2C controller and configure it for use
+
+ This routine must be called at or below TPL_NOTIFY.
+
+ The I2C controller is reset. The caller must call SetBusFrequench() after
+ calling Reset().
+
+ @param[in] This Pointer to an EFI_I2C_MASTER_PROTOCOL structure.
+
+ @retval EFI_SUCCESS The reset completed successfully.
+ @retval EFI_ALREADY_STARTED The controller is busy with another transaction.
+ @retval EFI_DEVICE_ERROR The reset operation failed.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_I2C_MASTER_PROTOCOL_RESET)(
+ IN CONST EFI_I2C_MASTER_PROTOCOL *This
+ );
+
+/**
+ Start an I2C transaction on the host controller.
+
+ This routine must be called at or below TPL_NOTIFY. For synchronous
+ requests this routine must be called at or below TPL_CALLBACK.
+
+ This function initiates an I2C transaction on the controller. To
+ enable proper error handling by the I2C protocol stack, the I2C
+ master protocol does not support queuing but instead only manages
+ one I2C transaction at a time. This API requires that the I2C bus
+ is in the correct configuration for the I2C transaction.
+
+ The transaction is performed by sending a start-bit and selecting the
+ I2C device with the specified I2C slave address and then performing
+ the specified I2C operations. When multiple operations are requested
+ they are separated with a repeated start bit and the slave address.
+ The transaction is terminated with a stop bit.
+
+ When Event is NULL, StartRequest operates synchronously and returns
+ the I2C completion status as its return value.
+
+ When Event is not NULL, StartRequest synchronously returns EFI_SUCCESS
+ indicating that the I2C transaction was started asynchronously. The
+ transaction status value is returned in the buffer pointed to by
+ I2cStatus upon the completion of the I2C transaction when I2cStatus
+ is not NULL. After the transaction status is returned the Event is
+ signaled.
+
+ Note: The typical consumer of this API is the I2C host protocol.
+ Extreme care must be taken by other consumers of this API to prevent
+ confusing the third party I2C drivers due to a state change at the
+ I2C device which the third party I2C drivers did not initiate. I2C
+ platform specific code may use this API within these guidelines.
+
+ @param[in] This Pointer to an EFI_I2C_MASTER_PROTOCOL structure.
+ @param[in] SlaveAddress Address of the device on the I2C bus. Set the
+ I2C_ADDRESSING_10_BIT when using 10-bit addresses,
+ clear this bit for 7-bit addressing. Bits 0-6
+ are used for 7-bit I2C slave addresses and bits
+ 0-9 are used for 10-bit I2C slave addresses.
+ @param[in] RequestPacket Pointer to an EFI_I2C_REQUEST_PACKET
+ structure describing the I2C transaction.
+ @param[in] Event Event to signal for asynchronous transactions,
+ NULL for asynchronous transactions
+ @param[out] I2cStatus Optional buffer to receive the I2C transaction
+ completion status
+
+ @retval EFI_SUCCESS The asynchronous transaction was successfully
+ started when Event is not NULL.
+ @retval EFI_SUCCESS The transaction completed successfully when
+ Event is NULL.
+ @retval EFI_ALREADY_STARTED The controller is busy with another transaction.
+ @retval EFI_BAD_BUFFER_SIZE The RequestPacket->LengthInBytes value is too
+ large.
+ @retval EFI_DEVICE_ERROR There was an I2C error (NACK) during the
+ transaction.
+ @retval EFI_INVALID_PARAMETER RequestPacket is NULL
+ @retval EFI_NOT_FOUND Reserved bit set in the SlaveAddress parameter
+ @retval EFI_NO_RESPONSE The I2C device is not responding to the slave
+ address. EFI_DEVICE_ERROR will be returned if
+ the controller cannot distinguish when the NACK
+ occurred.
+ @retval EFI_OUT_OF_RESOURCES Insufficient memory for I2C transaction
+ @retval EFI_UNSUPPORTED The controller does not support the requested
+ transaction.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_I2C_MASTER_PROTOCOL_START_REQUEST)(
+ IN CONST EFI_I2C_MASTER_PROTOCOL *This,
+ IN UINTN SlaveAddress,
+ IN EFI_I2C_REQUEST_PACKET *RequestPacket,
+ IN EFI_EVENT Event OPTIONAL,
+ OUT EFI_STATUS *I2cStatus OPTIONAL
+ );
+
+///
+/// I2C master mode protocol
+///
+/// This protocol manipulates the I2C host controller to perform transactions as a
+/// master on the I2C bus using the current state of any switches or multiplexers
+/// in the I2C bus.
+///
+struct _EFI_I2C_MASTER_PROTOCOL {
+ ///
+ /// Set the clock frequency for the I2C bus.
+ ///
+ EFI_I2C_MASTER_PROTOCOL_SET_BUS_FREQUENCY SetBusFrequency;
+
+ ///
+ /// Reset the I2C host controller.
+ ///
+ EFI_I2C_MASTER_PROTOCOL_RESET Reset;
+
+ ///
+ /// Start an I2C transaction in master mode on the host controller.
+ ///
+ EFI_I2C_MASTER_PROTOCOL_START_REQUEST StartRequest;
+
+ ///
+ /// Pointer to an EFI_I2C_CONTROLLER_CAPABILITIES data structure containing
+ /// the capabilities of the I2C host controller.
+ ///
+ CONST EFI_I2C_CONTROLLER_CAPABILITIES *I2cControllerCapabilities;
+};
+
+extern EFI_GUID gEfiI2cMasterProtocolGuid;
+
+#endif // __I2C_MASTER_H__
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/IScsiInitiatorName.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/IScsiInitiatorName.h
new file mode 100644
index 0000000000..e0721320cc
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/IScsiInitiatorName.h
@@ -0,0 +1,78 @@
+/** @file
+ EFI_ISCSI_INITIATOR_NAME_PROTOCOL as defined in UEFI 2.0.
+ It provides the ability to get and set the iSCSI Initiator Name.
+
+ Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __ISCSI_INITIATOR_NAME_H__
+#define __ISCSI_INITIATOR_NAME_H__
+
+#define EFI_ISCSI_INITIATOR_NAME_PROTOCOL_GUID \
+{ \
+ 0x59324945, 0xec44, 0x4c0d, {0xb1, 0xcd, 0x9d, 0xb1, 0x39, 0xdf, 0x7, 0xc } \
+}
+
+typedef struct _EFI_ISCSI_INITIATOR_NAME_PROTOCOL EFI_ISCSI_INITIATOR_NAME_PROTOCOL;
+
+/**
+ Retrieves the current set value of iSCSI Initiator Name.
+
+ @param This Pointer to the EFI_ISCSI_INITIATOR_NAME_PROTOCOL instance.
+ @param BufferSize Size of the buffer in bytes pointed to by Buffer / Actual size of the
+ variable data buffer.
+ @param Buffer Pointer to the buffer for data to be read. The data is a null-terminated UTF-8 encoded string.
+ The maximum length is 223 characters, including the null-terminator.
+
+ @retval EFI_SUCCESS Data was successfully retrieved into the provided buffer and the
+ BufferSize was sufficient to handle the iSCSI initiator name
+ @retval EFI_BUFFER_TOO_SMALL BufferSize is too small for the result.
+ @retval EFI_INVALID_PARAMETER BufferSize or Buffer is NULL.
+ @retval EFI_DEVICE_ERROR The iSCSI initiator name could not be retrieved due to a hardware error.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_ISCSI_INITIATOR_NAME_GET)(
+ IN EFI_ISCSI_INITIATOR_NAME_PROTOCOL *This,
+ IN OUT UINTN *BufferSize,
+ OUT VOID *Buffer
+ );
+
+/**
+ Sets the iSCSI Initiator Name.
+
+ @param This Pointer to the EFI_ISCSI_INITIATOR_NAME_PROTOCOL instance.
+ @param BufferSize Size of the buffer in bytes pointed to by Buffer.
+ @param Buffer Pointer to the buffer for data to be written. The data is a null-terminated UTF-8 encoded string.
+ The maximum length is 223 characters, including the null-terminator.
+
+ @retval EFI_SUCCESS Data was successfully stored by the protocol.
+ @retval EFI_UNSUPPORTED Platform policies do not allow for data to be written.
+ @retval EFI_INVALID_PARAMETER BufferSize or Buffer is NULL, or BufferSize exceeds the maximum allowed limit.
+ @retval EFI_DEVICE_ERROR The data could not be stored due to a hardware error.
+ @retval EFI_OUT_OF_RESOURCES Not enough storage is available to hold the data.
+ @retval EFI_PROTOCOL_ERROR Input iSCSI initiator name does not adhere to RFC 3720
+ (and other related protocols)
+
+**/
+typedef EFI_STATUS
+(EFIAPI *EFI_ISCSI_INITIATOR_NAME_SET)(
+ IN EFI_ISCSI_INITIATOR_NAME_PROTOCOL *This,
+ IN OUT UINTN *BufferSize,
+ IN VOID *Buffer
+ );
+
+///
+/// iSCSI Initiator Name Protocol for setting and obtaining the iSCSI Initiator Name.
+///
+struct _EFI_ISCSI_INITIATOR_NAME_PROTOCOL {
+ EFI_ISCSI_INITIATOR_NAME_GET Get;
+ EFI_ISCSI_INITIATOR_NAME_SET Set;
+};
+
+extern EFI_GUID gEfiIScsiInitiatorNameProtocolGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/IdeControllerInit.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/IdeControllerInit.h
new file mode 100644
index 0000000000..a8bfa62a6e
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/IdeControllerInit.h
@@ -0,0 +1,559 @@
+/** @file
+ This file declares EFI IDE Controller Init Protocol
+
+ The EFI_IDE_CONTROLLER_INIT_PROTOCOL provides the chipset-specific information
+ to the driver entity. This protocol is mandatory for IDE controllers if the
+ IDE devices behind the controller are to be enumerated by a driver entity.
+
+ There can only be one instance of EFI_IDE_CONTROLLER_INIT_PROTOCOL for each IDE
+ controller in a system. It is installed on the handle that corresponds to the
+ IDE controller. A driver entity that wishes to manage an IDE bus and possibly
+ IDE devices in a system will have to retrieve the EFI_IDE_CONTROLLER_INIT_PROTOCOL
+ instance that is associated with the controller to be managed.
+
+ A device handle for an IDE controller must contain an EFI_DEVICE_PATH_PROTOCOL.
+
+Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Revision Reference:
+ This Protocol is defined in UEFI Platform Initialization Specification 1.2
+ Volume 5: Standards.
+
+**/
+
+#ifndef _EFI_IDE_CONTROLLER_INIT_PROTOCOL_H_
+#define _EFI_IDE_CONTROLLER_INIT_PROTOCOL_H_
+
+#include
+
+///
+/// Global ID for the EFI_IDE_CONTROLLER_INIT_PROTOCOL.
+///
+#define EFI_IDE_CONTROLLER_INIT_PROTOCOL_GUID \
+ { \
+ 0xa1e37052, 0x80d9, 0x4e65, {0xa3, 0x17, 0x3e, 0x9a, 0x55, 0xc4, 0x3e, 0xc9 } \
+ }
+
+///
+/// Forward declaration for EFI_IDE_CONTROLLER_INIT_PROTOCOL.
+///
+typedef struct _EFI_IDE_CONTROLLER_INIT_PROTOCOL EFI_IDE_CONTROLLER_INIT_PROTOCOL;
+
+///
+/// The phase of the IDE Controller enumeration.
+///
+typedef enum {
+ ///
+ /// The driver entity is about to begin enumerating the devices
+ /// behind the specified channel. This notification can be used to
+ /// perform any chipset-specific programming.
+ ///
+ EfiIdeBeforeChannelEnumeration,
+ ///
+ /// The driver entity has completed enumerating the devices
+ /// behind the specified channel. This notification can be used to
+ /// perform any chipset-specific programming.
+ ///
+ EfiIdeAfterChannelEnumeration,
+ ///
+ /// The driver entity is about to reset the devices behind the
+ /// specified channel. This notification can be used to perform any
+ /// chipset-specific programming.
+ ///
+ EfiIdeBeforeChannelReset,
+ ///
+ /// The driver entity has completed resetting the devices behind
+ /// the specified channel. This notification can be used to perform
+ /// any chipset-specific programming.
+ ///
+ EfiIdeAfterChannelReset,
+ ///
+ /// The driver entity is about to detect the presence of devices
+ /// behind the specified channel. This notification can be used to
+ /// set up the bus signals to default levels or for implementing
+ /// predelays.
+ ///
+ EfiIdeBusBeforeDevicePresenceDetection,
+ ///
+ /// The driver entity is done with detecting the presence of
+ /// devices behind the specified channel. This notification can be
+ /// used to perform any chipset-specific programming.
+ ///
+ EfiIdeBusAfterDevicePresenceDetection,
+ ///
+ /// The IDE bus is requesting the IDE controller driver to
+ /// reprogram the IDE controller hardware and thereby reset all
+ /// the mode and timing settings to default settings.
+ ///
+ EfiIdeResetMode,
+ EfiIdeBusPhaseMaximum
+} EFI_IDE_CONTROLLER_ENUM_PHASE;
+
+///
+/// This extended mode describes the SATA physical protocol.
+/// SATA physical layers can operate at different speeds.
+/// These speeds are defined below. Various PATA protocols
+/// and associated modes are not applicable to SATA devices.
+///
+typedef enum {
+ EfiAtaSataTransferProtocol
+} EFI_ATA_EXT_TRANSFER_PROTOCOL;
+
+///
+/// Automatically detects the optimum SATA speed.
+///
+#define EFI_SATA_AUTO_SPEED 0
+
+///
+/// Indicates a first-generation (Gen1) SATA speed.
+///
+#define EFI_SATA_GEN1_SPEED 1
+
+///
+/// Indicates a second-generation (Gen2) SATA speed.
+///
+#define EFI_SATA_GEN2_SPEED 2
+
+///
+/// EFI_ATA_MODE structure.
+///
+typedef struct {
+ BOOLEAN Valid; ///< TRUE if Mode is valid.
+ UINT32 Mode; ///< The actual ATA mode. This field is not a bit map.
+} EFI_ATA_MODE;
+
+///
+/// EFI_ATA_EXTENDED_MODE structure
+///
+typedef struct {
+ ///
+ /// An enumeration defining various transfer protocols other than the protocols
+ /// that exist at the time this specification was developed (i.e., PIO, single
+ /// word DMA, multiword DMA, and UDMA). Each transfer protocol is associated
+ /// with a mode. The various transfer protocols are defined by the ATA/ATAPI
+ /// specification. This enumeration makes the interface extensible because we
+ /// can support new transport protocols beyond UDMA. Type EFI_ATA_EXT_TRANSFER_PROTOCOL
+ /// is defined below.
+ ///
+ EFI_ATA_EXT_TRANSFER_PROTOCOL TransferProtocol;
+ ///
+ /// The mode for operating the transfer protocol that is identified by TransferProtocol.
+ ///
+ UINT32 Mode;
+} EFI_ATA_EXTENDED_MODE;
+
+///
+/// EFI_ATA_COLLECTIVE_MODE structure.
+///
+typedef struct {
+ ///
+ /// This field specifies the PIO mode. PIO modes are defined in the ATA/ATAPI
+ /// specification. The ATA/ATAPI specification defines the enumeration. In
+ /// other words, a value of 1 in this field means PIO mode 1. The actual meaning
+ /// of PIO mode 1 is governed by the ATA/ATAPI specification. Type EFI_ATA_MODE
+ /// is defined below.
+ ///
+ EFI_ATA_MODE PioMode;
+ ///
+ /// This field specifies the single word DMA mode. Single word DMA modes are defined
+ /// in the ATA/ATAPI specification, versions 1 and 2. Single word DMA support was
+ /// obsoleted in the ATA/ATAPI specification, version 3. Therefore, most devices and
+ /// controllers will not support this transfer mode. The ATA/ATAPI specification defines
+ /// the enumeration. In other words, a value of 1 in this field means single word DMA
+ /// mode 1. The actual meaning of single word DMA mode 1 is governed by the ATA/
+ /// ATAPI specification.
+ ///
+ EFI_ATA_MODE SingleWordDmaMode;
+ ///
+ /// This field specifies the multiword DMA mode. Various multiword DMA modes are
+ /// defined in the ATA/ATAPI specification. A value of 1 in this field means multiword
+ /// DMA mode 1. The actual meaning of multiword DMA mode 1 is governed by the
+ /// ATA/ATAPI specification.
+ ///
+ EFI_ATA_MODE MultiWordDmaMode;
+ ///
+ /// This field specifies the ultra DMA (UDMA) mode. UDMA modes are defined in the
+ /// ATA/ATAPI specification. A value of 1 in this field means UDMA mode 1. The
+ /// actual meaning of UDMA mode 1 is governed by the ATA/ATAPI specification.
+ ///
+ EFI_ATA_MODE UdmaMode;
+ ///
+ /// The number of extended-mode bitmap entries. Extended modes describe transfer
+ /// protocols beyond PIO, single word DMA, multiword DMA, and UDMA. This field
+ /// can be zero and provides extensibility.
+ ///
+ UINT32 ExtModeCount;
+ ///
+ /// ExtModeCount number of entries. Each entry represents a transfer protocol other
+ /// than the ones defined above (i.e., PIO, single word DMA, multiword DMA, and
+ /// UDMA). This field is defined for extensibility. At this time, only one extended
+ /// transfer protocol is defined to cover SATA transfers. Type
+ /// EFI_ATA_EXTENDED_MODE is defined below.
+ ///
+ EFI_ATA_EXTENDED_MODE ExtMode[1];
+} EFI_ATA_COLLECTIVE_MODE;
+
+///
+/// EFI_ATA_IDENTIFY_DATA & EFI_ATAPI_IDENTIFY_DATA structure
+///
+/// The definition of these two structures is not part of the protocol
+/// definition because the ATA/ATAPI Specification controls the definition
+/// of all the fields. The ATA/ATAPI Specification can obsolete old fields
+/// or redefine existing fields.
+typedef ATA_IDENTIFY_DATA EFI_ATA_IDENTIFY_DATA;
+typedef ATAPI_IDENTIFY_DATA EFI_ATAPI_IDENTIFY_DATA;
+
+///
+/// This flag indicates whether the IDENTIFY data is a response from an ATA device
+/// (EFI_ATA_IDENTIFY_DATA) or response from an ATAPI device
+/// (EFI_ATAPI_IDENTIFY_DATA). According to the ATA/ATAPI specification,
+/// EFI_IDENTIFY_DATA is for an ATA device if bit 15 of the Config field is zero.
+/// The Config field is common to both EFI_ATA_IDENTIFY_DATA and
+/// EFI_ATAPI_IDENTIFY_DATA.
+///
+#define EFI_ATAPI_DEVICE_IDENTIFY_DATA 0x8000
+
+///
+/// EFI_IDENTIFY_DATA structure.
+///
+typedef union {
+ ///
+ /// The data that is returned by an ATA device upon successful completion
+ /// of the ATA IDENTIFY_DEVICE command.
+ ///
+ EFI_ATA_IDENTIFY_DATA AtaData;
+ ///
+ /// The data that is returned by an ATAPI device upon successful completion
+ /// of the ATA IDENTIFY_PACKET_DEVICE command.
+ ///
+ EFI_ATAPI_IDENTIFY_DATA AtapiData;
+} EFI_IDENTIFY_DATA;
+
+/**
+ Returns the information about the specified IDE channel.
+
+ This function can be used to obtain information about a particular IDE channel.
+ The driver entity uses this information during the enumeration process.
+
+ If Enabled is set to FALSE, the driver entity will not scan the channel. Note
+ that it will not prevent an operating system driver from scanning the channel.
+
+ For most of today's controllers, MaxDevices will either be 1 or 2. For SATA
+ controllers, this value will always be 1. SATA configurations can contain SATA
+ port multipliers. SATA port multipliers behave like SATA bridges and can support
+ up to 16 devices on the other side. If a SATA port out of the IDE controller
+ is connected to a port multiplier, MaxDevices will be set to the number of SATA
+ devices that the port multiplier supports. Because today's port multipliers
+ support up to fifteen SATA devices, this number can be as large as fifteen. The IDE
+ bus driver is required to scan for the presence of port multipliers behind an SATA
+ controller and enumerate up to MaxDevices number of devices behind the port
+ multiplier.
+
+ In this context, the devices behind a port multiplier constitute a channel.
+
+ @param[in] This The pointer to the EFI_IDE_CONTROLLER_INIT_PROTOCOL instance.
+ @param[in] Channel Zero-based channel number.
+ @param[out] Enabled TRUE if this channel is enabled. Disabled channels
+ are not scanned to see if any devices are present.
+ @param[out] MaxDevices The maximum number of IDE devices that the bus driver
+ can expect on this channel. For the ATA/ATAPI
+ specification, version 6, this number will either be
+ one or two. For Serial ATA (SATA) configurations with a
+ port multiplier, this number can be as large as fifteen.
+
+ @retval EFI_SUCCESS Information was returned without any errors.
+ @retval EFI_INVALID_PARAMETER Channel is invalid (Channel >= ChannelCount).
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_IDE_CONTROLLER_GET_CHANNEL_INFO)(
+ IN EFI_IDE_CONTROLLER_INIT_PROTOCOL *This,
+ IN UINT8 Channel,
+ OUT BOOLEAN *Enabled,
+ OUT UINT8 *MaxDevices
+ );
+
+/**
+ The notifications from the driver entity that it is about to enter a certain
+ phase of the IDE channel enumeration process.
+
+ This function can be used to notify the IDE controller driver to perform
+ specific actions, including any chipset-specific initialization, so that the
+ chipset is ready to enter the next phase. Seven notification points are defined
+ at this time.
+
+ More synchronization points may be added as required in the future.
+
+ @param[in] This The pointer to the EFI_IDE_CONTROLLER_INIT_PROTOCOL instance.
+ @param[in] Phase The phase during enumeration.
+ @param[in] Channel Zero-based channel number.
+
+ @retval EFI_SUCCESS The notification was accepted without any errors.
+ @retval EFI_UNSUPPORTED Phase is not supported.
+ @retval EFI_INVALID_PARAMETER Channel is invalid (Channel >= ChannelCount).
+ @retval EFI_NOT_READY This phase cannot be entered at this time; for
+ example, an attempt was made to enter a Phase
+ without having entered one or more previous
+ Phase.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_IDE_CONTROLLER_NOTIFY_PHASE)(
+ IN EFI_IDE_CONTROLLER_INIT_PROTOCOL *This,
+ IN EFI_IDE_CONTROLLER_ENUM_PHASE Phase,
+ IN UINT8 Channel
+ );
+
+/**
+ Submits the device information to the IDE controller driver.
+
+ This function is used by the driver entity to pass detailed information about
+ a particular device to the IDE controller driver. The driver entity obtains
+ this information by issuing an ATA or ATAPI IDENTIFY_DEVICE command. IdentifyData
+ is the pointer to the response data buffer. The IdentifyData buffer is owned
+ by the driver entity, and the IDE controller driver must make a local copy
+ of the entire buffer or parts of the buffer as needed. The original IdentifyData
+ buffer pointer may not be valid when
+
+ - EFI_IDE_CONTROLLER_INIT_PROTOCOL.CalculateMode() or
+ - EFI_IDE_CONTROLLER_INIT_PROTOCOL.DisqualifyMode() is called at a later point.
+
+ The IDE controller driver may consult various fields of EFI_IDENTIFY_DATA to
+ compute the optimum mode for the device. These fields are not limited to the
+ timing information. For example, an implementation of the IDE controller driver
+ may examine the vendor and type/mode field to match known bad drives.
+
+ The driver entity may submit drive information in any order, as long as it
+ submits information for all the devices belonging to the enumeration group
+ before EFI_IDE_CONTROLLER_INIT_PROTOCOL.CalculateMode() is called for any device
+ in that enumeration group. If a device is absent, EFI_IDE_CONTROLLER_INIT_PROTOCOL.SubmitData()
+ should be called with IdentifyData set to NULL. The IDE controller driver may
+ not have any other mechanism to know whether a device is present or not. Therefore,
+ setting IdentifyData to NULL does not constitute an error condition.
+ EFI_IDE_CONTROLLER_INIT_PROTOCOL.SubmitData() can be called only once for a
+ given (Channel, Device) pair.
+
+ @param[in] This A pointer to the EFI_IDE_CONTROLLER_INIT_PROTOCOL instance.
+ @param[in] Channel Zero-based channel number.
+ @param[in] Device Zero-based device number on the Channel.
+ @param[in] IdentifyData The device's response to the ATA IDENTIFY_DEVICE command.
+
+ @retval EFI_SUCCESS The information was accepted without any errors.
+ @retval EFI_INVALID_PARAMETER Channel is invalid (Channel >= ChannelCount).
+ @retval EFI_INVALID_PARAMETER Device is invalid.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_IDE_CONTROLLER_SUBMIT_DATA)(
+ IN EFI_IDE_CONTROLLER_INIT_PROTOCOL *This,
+ IN UINT8 Channel,
+ IN UINT8 Device,
+ IN EFI_IDENTIFY_DATA *IdentifyData
+ );
+
+/**
+ Disqualifies specific modes for an IDE device.
+
+ This function allows the driver entity or other drivers (such as platform
+ drivers) to reject certain timing modes and request the IDE controller driver
+ to recalculate modes. This function allows the driver entity and the IDE
+ controller driver to negotiate the timings on a per-device basis. This function
+ is useful in the case of drives that lie about their capabilities. An example
+ is when the IDE device fails to accept the timing modes that are calculated
+ by the IDE controller driver based on the response to the Identify Drive command.
+
+ If the driver entity does not want to limit the ATA timing modes and leave that
+ decision to the IDE controller driver, it can either not call this function for
+ the given device or call this function and set the Valid flag to FALSE for all
+ modes that are listed in EFI_ATA_COLLECTIVE_MODE.
+
+ The driver entity may disqualify modes for a device in any order and any number
+ of times.
+
+ This function can be called multiple times to invalidate multiple modes of the
+ same type (e.g., Programmed Input/Output [PIO] modes 3 and 4). See the ATA/ATAPI
+ specification for more information on PIO modes.
+
+ For Serial ATA (SATA) controllers, this member function can be used to disqualify
+ a higher transfer rate mode on a given channel. For example, a platform driver
+ may inform the IDE controller driver to not use second-generation (Gen2) speeds
+ for a certain SATA drive.
+
+ @param[in] This The pointer to the EFI_IDE_CONTROLLER_INIT_PROTOCOL instance.
+ @param[in] Channel The zero-based channel number.
+ @param[in] Device The zero-based device number on the Channel.
+ @param[in] BadModes The modes that the device does not support and that
+ should be disqualified.
+
+ @retval EFI_SUCCESS The modes were accepted without any errors.
+ @retval EFI_INVALID_PARAMETER Channel is invalid (Channel >= ChannelCount).
+ @retval EFI_INVALID_PARAMETER Device is invalid.
+ @retval EFI_INVALID_PARAMETER IdentifyData is NULL.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_IDE_CONTROLLER_DISQUALIFY_MODE)(
+ IN EFI_IDE_CONTROLLER_INIT_PROTOCOL *This,
+ IN UINT8 Channel,
+ IN UINT8 Device,
+ IN EFI_ATA_COLLECTIVE_MODE *BadModes
+ );
+
+/**
+ Returns the information about the optimum modes for the specified IDE device.
+
+ This function is used by the driver entity to obtain the optimum ATA modes for
+ a specific device. The IDE controller driver takes into account the following
+ while calculating the mode:
+ - The IdentifyData inputs to EFI_IDE_CONTROLLER_INIT_PROTOCOL.SubmitData()
+ - The BadModes inputs to EFI_IDE_CONTROLLER_INIT_PROTOCOL.DisqualifyMode()
+
+ The driver entity is required to call EFI_IDE_CONTROLLER_INIT_PROTOCOL.SubmitData()
+ for all the devices that belong to an enumeration group before calling
+ EFI_IDE_CONTROLLER_INIT_PROTOCOL.CalculateMode() for any device in the same group.
+
+ The IDE controller driver will use controller- and possibly platform-specific
+ algorithms to arrive at SupportedModes. The IDE controller may base its
+ decision on user preferences and other considerations as well. This function
+ may be called multiple times because the driver entity may renegotiate the mode
+ with the IDE controller driver using EFI_IDE_CONTROLLER_INIT_PROTOCOL.DisqualifyMode().
+
+ The driver entity may collect timing information for various devices in any
+ order. The driver entity is responsible for making sure that all the dependencies
+ are satisfied. For example, the SupportedModes information for device A that
+ was previously returned may become stale after a call to
+ EFI_IDE_CONTROLLER_INIT_PROTOCOL.DisqualifyMode() for device B.
+
+ The buffer SupportedModes is allocated by the callee because the caller does
+ not necessarily know the size of the buffer. The type EFI_ATA_COLLECTIVE_MODE
+ is defined in a way that allows for future extensibility and can be of variable
+ length. This memory pool should be deallocated by the caller when it is no
+ longer necessary.
+
+ The IDE controller driver for a Serial ATA (SATA) controller can use this
+ member function to force a lower speed (first-generation [Gen1] speeds on a
+ second-generation [Gen2]-capable hardware). The IDE controller driver can
+ also allow the driver entity to stay with the speed that has been negotiated
+ by the physical layer.
+
+ @param[in] This The pointer to the EFI_IDE_CONTROLLER_INIT_PROTOCOL instance.
+ @param[in] Channel A zero-based channel number.
+ @param[in] Device A zero-based device number on the Channel.
+ @param[out] SupportedModes The optimum modes for the device.
+
+ @retval EFI_SUCCESS SupportedModes was returned.
+ @retval EFI_INVALID_PARAMETER Channel is invalid (Channel >= ChannelCount).
+ @retval EFI_INVALID_PARAMETER Device is invalid.
+ @retval EFI_INVALID_PARAMETER SupportedModes is NULL.
+ @retval EFI_NOT_READY Modes cannot be calculated due to a lack of
+ data. This error may happen if
+ EFI_IDE_CONTROLLER_INIT_PROTOCOL.SubmitData()
+ and EFI_IDE_CONTROLLER_INIT_PROTOCOL.DisqualifyData()
+ were not called for at least one drive in the
+ same enumeration group.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_IDE_CONTROLLER_CALCULATE_MODE)(
+ IN EFI_IDE_CONTROLLER_INIT_PROTOCOL *This,
+ IN UINT8 Channel,
+ IN UINT8 Device,
+ OUT EFI_ATA_COLLECTIVE_MODE **SupportedModes
+ );
+
+/**
+ Commands the IDE controller driver to program the IDE controller hardware
+ so that the specified device can operate at the specified mode.
+
+ This function is used by the driver entity to instruct the IDE controller
+ driver to program the IDE controller hardware to the specified modes. This
+ function can be called only once for a particular device. For a Serial ATA
+ (SATA) Advanced Host Controller Interface (AHCI) controller, no controller-
+ specific programming may be required.
+
+ @param[in] This Pointer to the EFI_IDE_CONTROLLER_INIT_PROTOCOL instance.
+ @param[in] Channel Zero-based channel number.
+ @param[in] Device Zero-based device number on the Channel.
+ @param[in] Modes The modes to set.
+
+ @retval EFI_SUCCESS The command was accepted without any errors.
+ @retval EFI_INVALID_PARAMETER Channel is invalid (Channel >= ChannelCount).
+ @retval EFI_INVALID_PARAMETER Device is invalid.
+ @retval EFI_NOT_READY Modes cannot be set at this time due to lack of data.
+ @retval EFI_DEVICE_ERROR Modes cannot be set due to hardware failure.
+ The driver entity should not use this device.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_IDE_CONTROLLER_SET_TIMING)(
+ IN EFI_IDE_CONTROLLER_INIT_PROTOCOL *This,
+ IN UINT8 Channel,
+ IN UINT8 Device,
+ IN EFI_ATA_COLLECTIVE_MODE *Modes
+ );
+
+///
+/// Provides the basic interfaces to abstract an IDE controller.
+///
+struct _EFI_IDE_CONTROLLER_INIT_PROTOCOL {
+ ///
+ /// Returns the information about a specific channel.
+ ///
+ EFI_IDE_CONTROLLER_GET_CHANNEL_INFO GetChannelInfo;
+
+ ///
+ /// The notification that the driver entity is about to enter the
+ /// specified phase during the enumeration process.
+ ///
+ EFI_IDE_CONTROLLER_NOTIFY_PHASE NotifyPhase;
+
+ ///
+ /// Submits the Drive Identify data that was returned by the device.
+ ///
+ EFI_IDE_CONTROLLER_SUBMIT_DATA SubmitData;
+
+ ///
+ /// Submits information about modes that should be disqualified. The specified
+ /// IDE device does not support these modes and these modes should not be
+ /// returned by EFI_IDE_CONTROLLER_INIT_PROTOCOL.CalculateMode()
+ ///
+ EFI_IDE_CONTROLLER_DISQUALIFY_MODE DisqualifyMode;
+
+ ///
+ /// Calculates and returns the optimum mode for a particular IDE device.
+ ///
+ EFI_IDE_CONTROLLER_CALCULATE_MODE CalculateMode;
+
+ ///
+ /// Programs the IDE controller hardware to the default timing or per the modes
+ /// that were returned by the last call to EFI_IDE_CONTROLLER_INIT_PROTOCOL.CalculateMode().
+ ///
+ EFI_IDE_CONTROLLER_SET_TIMING SetTiming;
+
+ ///
+ /// Set to TRUE if the enumeration group includes all the channels that are
+ /// produced by this controller. Set to FALSE if an enumeration group consists of
+ /// only one channel.
+ ///
+ BOOLEAN EnumAll;
+
+ ///
+ /// The number of channels that are produced by this controller. Parallel ATA
+ /// (PATA) controllers can support up to two channels. Advanced Host Controller
+ /// Interface (AHCI) Serial ATA (SATA) controllers can support up to 32 channels,
+ /// each of which can have up to one device. In the presence of a multiplier,
+ /// each channel can have fifteen devices.
+ ///
+ UINT8 ChannelCount;
+};
+
+extern EFI_GUID gEfiIdeControllerInitProtocolGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/IncompatiblePciDeviceSupport.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/IncompatiblePciDeviceSupport.h
new file mode 100644
index 0000000000..3092ee09e7
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/IncompatiblePciDeviceSupport.h
@@ -0,0 +1,167 @@
+/** @file
+ This file declares Incompatible PCI Device Support Protocol
+
+ Allows the PCI bus driver to support resource allocation for some PCI devices
+ that do not comply with the PCI Specification.
+
+ @par Note:
+ This protocol is optional. Only those platforms that implement this protocol
+ will have the capability to support incompatible PCI devices. The absence of
+ this protocol can cause the PCI bus driver to configure these incompatible
+ PCI devices incorrectly. As a result, these devices may not work properly.
+
+ The EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL is used by the PCI bus driver
+ to support resource allocation for some PCI devices that do not comply with the
+ PCI Specification. This protocol can find some incompatible PCI devices and
+ report their special resource requirements to the PCI bus driver. The generic
+ PCI bus driver does not have prior knowledge of any incompatible PCI devices.
+ It interfaces with the EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL to find out
+ if a device is incompatible and to obtain the special configuration requirements
+ for a specific incompatible PCI device.
+
+ This protocol is optional, and only one instance of this protocol can be present
+ in the system. If a platform supports this protocol, this protocol is produced
+ by a Driver Execution Environment (DXE) driver and must be made available before
+ the Boot Device Selection (BDS) phase. The PCI bus driver will look for the
+ presence of this protocol before it begins PCI enumeration. If this protocol
+ exists in a platform, it indicates that the platform has the capability to support
+ those incompatible PCI devices. However, final support for incompatible PCI
+ devices still depends on the implementation of the PCI bus driver. The PCI bus
+ driver may fully, partially, or not even support these incompatible devices.
+
+ During PCI bus enumeration, the PCI bus driver will probe the PCI Base Address
+ Registers (BARs) for each PCI device regardless of whether the PCI device is
+ incompatible or not to determine the resource requirements so that the PCI bus
+ driver can invoke the proper PCI resources for them. Generally, this resource
+ information includes the following:
+ - Resource type
+ - Resource length
+ - Alignment
+
+ However, some incompatible PCI devices may have special requirements. As a result,
+ the length or the alignment that is derived through BAR probing may not be exactly
+ the same as the actual resource requirement of the device. For example, there
+ are some devices that request I/O resources at a length of 0x100 from their I/O
+ BAR, but these incompatible devices will never work correctly if an odd I/O base
+ address, such as 0x100, 0x300, or 0x500, is assigned to the BAR. Instead, these
+ devices request an even base address, such as 0x200 or 0x400. The Incompatible
+ PCI Device Support Protocol can then be used to obtain these special resource
+ requirements for these incompatible PCI devices. In this way, the PCI bus driver
+ will take special consideration for these devices during PCI resource allocation
+ to ensure that they can work correctly.
+
+ This protocol may support the following incompatible PCI BAR types:
+ - I/O or memory length that is different from what the BAR reports
+ - I/O or memory alignment that is different from what the BAR reports
+ - Fixed I/O or memory base address
+
+ See the Conventional PCI Specification 3.0 for the details of how a PCI BAR
+ reports the resource length and the alignment that it requires.
+
+ Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Revision Reference:
+ This Protocol is defined in UEFI Platform Initialization Specification 1.2
+ Volume 5: Standards
+
+**/
+
+#ifndef _INCOMPATIBLE_PCI_DEVICE_SUPPORT_H_
+#define _INCOMPATIBLE_PCI_DEVICE_SUPPORT_H_
+
+///
+/// Global ID for EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL
+///
+#define EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL_GUID \
+ { \
+ 0xeb23f55a, 0x7863, 0x4ac2, {0x8d, 0x3d, 0x95, 0x65, 0x35, 0xde, 0x03, 0x75} \
+ }
+
+///
+/// Forward declaration for EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL
+///
+typedef struct _EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL;
+
+/**
+ Returns a list of ACPI resource descriptors that detail the special resource
+ configuration requirements for an incompatible PCI device.
+
+ This function returns a list of ACPI resource descriptors that detail the
+ special resource configuration requirements for an incompatible PCI device.
+
+ Prior to bus enumeration, the PCI bus driver will look for the presence
+ of the EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL. Only one instance of this
+ protocol can be present in the system. For each PCI device that the PCI bus
+ driver discovers, the PCI bus driver calls this function with the device's vendor
+ ID, device ID, revision ID, subsystem vendor ID, and subsystem device ID. If the
+ VendorId, DeviceId, RevisionId, SubsystemVendorId, or SubsystemDeviceId value is
+ set to (UINTN)-1, that field will be ignored. The ID values that are not (UINTN)-1
+ will be used to identify the current device.
+
+ This function will only return EFI_SUCCESS. However, if the device is an
+ incompatible PCI device, a list of ACPI resource descriptors will be returned
+ in Configuration. Otherwise, NULL will be returned in Configuration instead.
+ The PCI bus driver does not need to allocate memory for Configuration. However,
+ it is the PCI bus driver's responsibility to free it. The PCI bus driver then
+ can configure this device with the information that is derived from this list
+ of resource nodes, rather than the result of BAR probing.
+
+ Only the following two resource descriptor types from the ACPI Specification
+ may be used to describe the incompatible PCI device resource requirements:
+ - QWORD Address Space Descriptor (ACPI 2.0, section 6.4.3.5.1; also ACPI 3.0)
+ - End Tag (ACPI 2.0, section 6.4.2.8; also ACPI 3.0)
+
+ The QWORD Address Space Descriptor can describe memory, I/O, and bus number
+ ranges for dynamic or fixed resources. The configuration of a PCI root bridge
+ is described with one or more QWORD Address Space Descriptors, followed by an
+ End Tag. See the ACPI Specification for details on the field values.
+
+ @param[in] This Pointer to the EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL
+ instance.
+ @param[in] VendorId A unique ID to identify the manufacturer of
+ the PCI device. See the Conventional PCI
+ Specification 3.0 for details.
+ @param[in] DeviceId A unique ID to identify the particular PCI
+ device. See the Conventional PCI Specification
+ 3.0 for details.
+ @param[in] RevisionId A PCI device-specific revision identifier.
+ See the Conventional PCI Specification 3.0
+ for details.
+ @param[in] SubsystemVendorId Specifies the subsystem vendor ID. See the
+ Conventional PCI Specification 3.0 for details.
+ @param[in] SubsystemDeviceId Specifies the subsystem device ID. See the
+ Conventional PCI Specification 3.0 for details.
+ @param[out] Configuration A list of ACPI resource descriptors that detail
+ the configuration requirement.
+
+ @retval EFI_SUCCESS The function always returns EFI_SUCCESS.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_CHECK_DEVICE)(
+ IN EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL *This,
+ IN UINTN VendorId,
+ IN UINTN DeviceId,
+ IN UINTN RevisionId,
+ IN UINTN SubsystemVendorId,
+ IN UINTN SubsystemDeviceId,
+ OUT VOID **Configuration
+ );
+
+///
+/// Interface structure for the Incompatible PCI Device Support Protocol
+///
+struct _EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL {
+ ///
+ /// Returns a list of ACPI resource descriptors that detail any special
+ /// resource configuration requirements if the specified device is a recognized
+ /// incompatible PCI device.
+ ///
+ EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_CHECK_DEVICE CheckDevice;
+};
+
+extern EFI_GUID gEfiIncompatiblePciDeviceSupportProtocolGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/Ip4.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/Ip4.h
new file mode 100644
index 0000000000..9f08bee84c
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/Ip4.h
@@ -0,0 +1,602 @@
+/** @file
+ This file defines the EFI IPv4 (Internet Protocol version 4)
+ Protocol interface. It is split into the following three main
+ sections:
+ - EFI IPv4 Service Binding Protocol
+ - EFI IPv4 Variable (deprecated in UEFI 2.4B)
+ - EFI IPv4 Protocol.
+ The EFI IPv4 Protocol provides basic network IPv4 packet I/O services,
+ which includes support foR a subset of the Internet Control Message
+ Protocol (ICMP) and may include support for the Internet Group Management
+ Protocol (IGMP).
+
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Revision Reference:
+ This Protocol is introduced in UEFI Specification 2.0.
+
+**/
+
+#ifndef __EFI_IP4_PROTOCOL_H__
+#define __EFI_IP4_PROTOCOL_H__
+
+#include
+
+#define EFI_IP4_SERVICE_BINDING_PROTOCOL_GUID \
+ { \
+ 0xc51711e7, 0xb4bf, 0x404a, {0xbf, 0xb8, 0x0a, 0x04, 0x8e, 0xf1, 0xff, 0xe4 } \
+ }
+
+#define EFI_IP4_PROTOCOL_GUID \
+ { \
+ 0x41d94cd2, 0x35b6, 0x455a, {0x82, 0x58, 0xd4, 0xe5, 0x13, 0x34, 0xaa, 0xdd } \
+ }
+
+typedef struct _EFI_IP4_PROTOCOL EFI_IP4_PROTOCOL;
+
+///
+/// EFI_IP4_ADDRESS_PAIR is deprecated in the UEFI 2.4B and should not be used any more.
+/// The definition in here is only present to provide backwards compatability.
+///
+typedef struct {
+ EFI_HANDLE InstanceHandle;
+ EFI_IPv4_ADDRESS Ip4Address;
+ EFI_IPv4_ADDRESS SubnetMask;
+} EFI_IP4_ADDRESS_PAIR;
+
+///
+/// EFI_IP4_VARIABLE_DATA is deprecated in the UEFI 2.4B and should not be used any more.
+/// The definition in here is only present to provide backwards compatability.
+///
+typedef struct {
+ EFI_HANDLE DriverHandle;
+ UINT32 AddressCount;
+ EFI_IP4_ADDRESS_PAIR AddressPairs[1];
+} EFI_IP4_VARIABLE_DATA;
+
+typedef struct {
+ ///
+ /// The default IPv4 protocol packets to send and receive. Ignored
+ /// when AcceptPromiscuous is TRUE.
+ ///
+ UINT8 DefaultProtocol;
+ ///
+ /// Set to TRUE to receive all IPv4 packets that get through the receive filters.
+ /// Set to FALSE to receive only the DefaultProtocol IPv4
+ /// packets that get through the receive filters.
+ ///
+ BOOLEAN AcceptAnyProtocol;
+ ///
+ /// Set to TRUE to receive ICMP error report packets. Ignored when
+ /// AcceptPromiscuous or AcceptAnyProtocol is TRUE.
+ ///
+ BOOLEAN AcceptIcmpErrors;
+ ///
+ /// Set to TRUE to receive broadcast IPv4 packets. Ignored when
+ /// AcceptPromiscuous is TRUE.
+ /// Set to FALSE to stop receiving broadcast IPv4 packets.
+ ///
+ BOOLEAN AcceptBroadcast;
+ ///
+ /// Set to TRUE to receive all IPv4 packets that are sent to any
+ /// hardware address or any protocol address.
+ /// Set to FALSE to stop receiving all promiscuous IPv4 packets
+ ///
+ BOOLEAN AcceptPromiscuous;
+ ///
+ /// Set to TRUE to use the default IPv4 address and default routing table.
+ ///
+ BOOLEAN UseDefaultAddress;
+ ///
+ /// The station IPv4 address that will be assigned to this EFI IPv4Protocol instance.
+ ///
+ EFI_IPv4_ADDRESS StationAddress;
+ ///
+ /// The subnet address mask that is associated with the station address.
+ ///
+ EFI_IPv4_ADDRESS SubnetMask;
+ ///
+ /// TypeOfService field in transmitted IPv4 packets.
+ ///
+ UINT8 TypeOfService;
+ ///
+ /// TimeToLive field in transmitted IPv4 packets.
+ ///
+ UINT8 TimeToLive;
+ ///
+ /// State of the DoNotFragment bit in transmitted IPv4 packets.
+ ///
+ BOOLEAN DoNotFragment;
+ ///
+ /// Set to TRUE to send and receive unformatted packets. The other
+ /// IPv4 receive filters are still applied. Fragmentation is disabled for RawData mode.
+ ///
+ BOOLEAN RawData;
+ ///
+ /// The timer timeout value (number of microseconds) for the
+ /// receive timeout event to be associated with each assembled
+ /// packet. Zero means do not drop assembled packets.
+ ///
+ UINT32 ReceiveTimeout;
+ ///
+ /// The timer timeout value (number of microseconds) for the
+ /// transmit timeout event to be associated with each outgoing
+ /// packet. Zero means do not drop outgoing packets.
+ ///
+ UINT32 TransmitTimeout;
+} EFI_IP4_CONFIG_DATA;
+
+typedef struct {
+ EFI_IPv4_ADDRESS SubnetAddress;
+ EFI_IPv4_ADDRESS SubnetMask;
+ EFI_IPv4_ADDRESS GatewayAddress;
+} EFI_IP4_ROUTE_TABLE;
+
+typedef struct {
+ UINT8 Type;
+ UINT8 Code;
+} EFI_IP4_ICMP_TYPE;
+
+typedef struct {
+ ///
+ /// Set to TRUE after this EFI IPv4 Protocol instance has been successfully configured.
+ ///
+ BOOLEAN IsStarted;
+ ///
+ /// The maximum packet size, in bytes, of the packet which the upper layer driver could feed.
+ ///
+ UINT32 MaxPacketSize;
+ ///
+ /// Current configuration settings.
+ ///
+ EFI_IP4_CONFIG_DATA ConfigData;
+ ///
+ /// Set to TRUE when the EFI IPv4 Protocol instance has a station address and subnet mask.
+ ///
+ BOOLEAN IsConfigured;
+ ///
+ /// Number of joined multicast groups.
+ ///
+ UINT32 GroupCount;
+ ///
+ /// List of joined multicast group addresses.
+ ///
+ EFI_IPv4_ADDRESS *GroupTable;
+ ///
+ /// Number of entries in the routing table.
+ ///
+ UINT32 RouteCount;
+ ///
+ /// Routing table entries.
+ ///
+ EFI_IP4_ROUTE_TABLE *RouteTable;
+ ///
+ /// Number of entries in the supported ICMP types list.
+ ///
+ UINT32 IcmpTypeCount;
+ ///
+ /// Array of ICMP types and codes that are supported by this EFI IPv4 Protocol driver
+ ///
+ EFI_IP4_ICMP_TYPE *IcmpTypeList;
+} EFI_IP4_MODE_DATA;
+
+#pragma pack(1)
+
+typedef struct {
+ UINT8 HeaderLength : 4;
+ UINT8 Version : 4;
+ UINT8 TypeOfService;
+ UINT16 TotalLength;
+ UINT16 Identification;
+ UINT16 Fragmentation;
+ UINT8 TimeToLive;
+ UINT8 Protocol;
+ UINT16 Checksum;
+ EFI_IPv4_ADDRESS SourceAddress;
+ EFI_IPv4_ADDRESS DestinationAddress;
+} EFI_IP4_HEADER;
+#pragma pack()
+
+typedef struct {
+ UINT32 FragmentLength;
+ VOID *FragmentBuffer;
+} EFI_IP4_FRAGMENT_DATA;
+
+typedef struct {
+ EFI_TIME TimeStamp;
+ EFI_EVENT RecycleSignal;
+ UINT32 HeaderLength;
+ EFI_IP4_HEADER *Header;
+ UINT32 OptionsLength;
+ VOID *Options;
+ UINT32 DataLength;
+ UINT32 FragmentCount;
+ EFI_IP4_FRAGMENT_DATA FragmentTable[1];
+} EFI_IP4_RECEIVE_DATA;
+
+typedef struct {
+ EFI_IPv4_ADDRESS SourceAddress;
+ EFI_IPv4_ADDRESS GatewayAddress;
+ UINT8 Protocol;
+ UINT8 TypeOfService;
+ UINT8 TimeToLive;
+ BOOLEAN DoNotFragment;
+} EFI_IP4_OVERRIDE_DATA;
+
+typedef struct {
+ EFI_IPv4_ADDRESS DestinationAddress;
+ EFI_IP4_OVERRIDE_DATA *OverrideData; // OPTIONAL
+ UINT32 OptionsLength; // OPTIONAL
+ VOID *OptionsBuffer; // OPTIONAL
+ UINT32 TotalDataLength;
+ UINT32 FragmentCount;
+ EFI_IP4_FRAGMENT_DATA FragmentTable[1];
+} EFI_IP4_TRANSMIT_DATA;
+
+typedef struct {
+ ///
+ /// This Event will be signaled after the Status field is updated
+ /// by the EFI IPv4 Protocol driver. The type of Event must be
+ /// EFI_NOTIFY_SIGNAL. The Task Priority Level (TPL) of
+ /// Event must be lower than or equal to TPL_CALLBACK.
+ ///
+ EFI_EVENT Event;
+ ///
+ /// The status that is returned to the caller at the end of the operation
+ /// to indicate whether this operation completed successfully.
+ ///
+ EFI_STATUS Status;
+ union {
+ ///
+ /// When this token is used for receiving, RxData is a pointer to the EFI_IP4_RECEIVE_DATA.
+ ///
+ EFI_IP4_RECEIVE_DATA *RxData;
+ ///
+ /// When this token is used for transmitting, TxData is a pointer to the EFI_IP4_TRANSMIT_DATA.
+ ///
+ EFI_IP4_TRANSMIT_DATA *TxData;
+ } Packet;
+} EFI_IP4_COMPLETION_TOKEN;
+
+/**
+ Gets the current operational settings for this instance of the EFI IPv4 Protocol driver.
+
+ The GetModeData() function returns the current operational mode data for this
+ driver instance. The data fields in EFI_IP4_MODE_DATA are read only. This
+ function is used optionally to retrieve the operational mode data of underlying
+ networks or drivers.
+
+ @param This The pointer to the EFI_IP4_PROTOCOL instance.
+ @param Ip4ModeData The pointer to the EFI IPv4 Protocol mode data structure.
+ @param MnpConfigData The pointer to the managed network configuration data structure.
+ @param SnpModeData The pointer to the simple network mode data structure.
+
+ @retval EFI_SUCCESS The operation completed successfully.
+ @retval EFI_INVALID_PARAMETER This is NULL.
+ @retval EFI_OUT_OF_RESOURCES The required mode data could not be allocated.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_IP4_GET_MODE_DATA)(
+ IN CONST EFI_IP4_PROTOCOL *This,
+ OUT EFI_IP4_MODE_DATA *Ip4ModeData OPTIONAL,
+ OUT EFI_MANAGED_NETWORK_CONFIG_DATA *MnpConfigData OPTIONAL,
+ OUT EFI_SIMPLE_NETWORK_MODE *SnpModeData OPTIONAL
+ );
+
+/**
+ Assigns an IPv4 address and subnet mask to this EFI IPv4 Protocol driver instance.
+
+ The Configure() function is used to set, change, or reset the operational
+ parameters and filter settings for this EFI IPv4 Protocol instance. Until these
+ parameters have been set, no network traffic can be sent or received by this
+ instance. Once the parameters have been reset (by calling this function with
+ IpConfigData set to NULL), no more traffic can be sent or received until these
+ parameters have been set again. Each EFI IPv4 Protocol instance can be started
+ and stopped independently of each other by enabling or disabling their receive
+ filter settings with the Configure() function.
+
+ When IpConfigData.UseDefaultAddress is set to FALSE, the new station address will
+ be appended as an alias address into the addresses list in the EFI IPv4 Protocol
+ driver. While set to TRUE, Configure() will trigger the EFI_IP4_CONFIG_PROTOCOL
+ to retrieve the default IPv4 address if it is not available yet. Clients could
+ frequently call GetModeData() to check the status to ensure that the default IPv4
+ address is ready.
+
+ If operational parameters are reset or changed, any pending transmit and receive
+ requests will be cancelled. Their completion token status will be set to EFI_ABORTED
+ and their events will be signaled.
+
+ @param This The pointer to the EFI_IP4_PROTOCOL instance.
+ @param IpConfigData The pointer to the EFI IPv4 Protocol configuration data structure.
+
+ @retval EFI_SUCCESS The driver instance was successfully opened.
+ @retval EFI_NO_MAPPING When using the default address, configuration (DHCP, BOOTP,
+ RARP, etc.) is not finished yet.
+ @retval EFI_INVALID_PARAMETER One or more of the following conditions is TRUE:
+ This is NULL.
+ IpConfigData.StationAddress is not a unicast IPv4 address.
+ IpConfigData.SubnetMask is not a valid IPv4 subnet
+ @retval EFI_UNSUPPORTED One or more of the following conditions is TRUE:
+ A configuration protocol (DHCP, BOOTP, RARP, etc.) could
+ not be located when clients choose to use the default IPv4
+ address. This EFI IPv4 Protocol implementation does not
+ support this requested filter or timeout setting.
+ @retval EFI_OUT_OF_RESOURCES The EFI IPv4 Protocol driver instance data could not be allocated.
+ @retval EFI_ALREADY_STARTED The interface is already open and must be stopped before the
+ IPv4 address or subnet mask can be changed. The interface must
+ also be stopped when switching to/from raw packet mode.
+ @retval EFI_DEVICE_ERROR An unexpected system or network error occurred. The EFI IPv4
+ Protocol driver instance is not opened.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_IP4_CONFIGURE)(
+ IN EFI_IP4_PROTOCOL *This,
+ IN EFI_IP4_CONFIG_DATA *IpConfigData OPTIONAL
+ );
+
+/**
+ Joins and leaves multicast groups.
+
+ The Groups() function is used to join and leave multicast group sessions. Joining
+ a group will enable reception of matching multicast packets. Leaving a group will
+ disable the multicast packet reception.
+
+ If JoinFlag is FALSE and GroupAddress is NULL, all joined groups will be left.
+
+ @param This The pointer to the EFI_IP4_PROTOCOL instance.
+ @param JoinFlag Set to TRUE to join the multicast group session and FALSE to leave.
+ @param GroupAddress The pointer to the IPv4 multicast address.
+
+ @retval EFI_SUCCESS The operation completed successfully.
+ @retval EFI_INVALID_PARAMETER One or more of the following is TRUE:
+ - This is NULL.
+ - JoinFlag is TRUE and GroupAddress is NULL.
+ - GroupAddress is not NULL and *GroupAddress is
+ not a multicast IPv4 address.
+ @retval EFI_NOT_STARTED This instance has not been started.
+ @retval EFI_NO_MAPPING When using the default address, configuration (DHCP, BOOTP,
+ RARP, etc.) is not finished yet.
+ @retval EFI_OUT_OF_RESOURCES System resources could not be allocated.
+ @retval EFI_UNSUPPORTED This EFI IPv4 Protocol implementation does not support multicast groups.
+ @retval EFI_ALREADY_STARTED The group address is already in the group table (when
+ JoinFlag is TRUE).
+ @retval EFI_NOT_FOUND The group address is not in the group table (when JoinFlag is FALSE).
+ @retval EFI_DEVICE_ERROR An unexpected system or network error occurred.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_IP4_GROUPS)(
+ IN EFI_IP4_PROTOCOL *This,
+ IN BOOLEAN JoinFlag,
+ IN EFI_IPv4_ADDRESS *GroupAddress OPTIONAL
+ );
+
+/**
+ Adds and deletes routing table entries.
+
+ The Routes() function adds a route to or deletes a route from the routing table.
+
+ Routes are determined by comparing the SubnetAddress with the destination IPv4
+ address arithmetically AND-ed with the SubnetMask. The gateway address must be
+ on the same subnet as the configured station address.
+
+ The default route is added with SubnetAddress and SubnetMask both set to 0.0.0.0.
+ The default route matches all destination IPv4 addresses that do not match any
+ other routes.
+
+ A GatewayAddress that is zero is a nonroute. Packets are sent to the destination
+ IP address if it can be found in the ARP cache or on the local subnet. One automatic
+ nonroute entry will be inserted into the routing table for outgoing packets that
+ are addressed to a local subnet (gateway address of 0.0.0.0).
+
+ Each EFI IPv4 Protocol instance has its own independent routing table. Those EFI
+ IPv4 Protocol instances that use the default IPv4 address will also have copies
+ of the routing table that was provided by the EFI_IP4_CONFIG_PROTOCOL, and these
+ copies will be updated whenever the EIF IPv4 Protocol driver reconfigures its
+ instances. As a result, client modification to the routing table will be lost.
+
+ @param This The pointer to the EFI_IP4_PROTOCOL instance.
+ @param DeleteRoute Set to TRUE to delete this route from the routing table. Set to
+ FALSE to add this route to the routing table. SubnetAddress
+ and SubnetMask are used as the key to each route entry.
+ @param SubnetAddress The address of the subnet that needs to be routed.
+ @param SubnetMask The subnet mask of SubnetAddress.
+ @param GatewayAddress The unicast gateway IPv4 address for this route.
+
+ @retval EFI_SUCCESS The operation completed successfully.
+ @retval EFI_NOT_STARTED The driver instance has not been started.
+ @retval EFI_NO_MAPPING When using the default address, configuration (DHCP, BOOTP,
+ RARP, etc.) is not finished yet.
+ @retval EFI_INVALID_PARAMETER One or more of the following conditions is TRUE:
+ - This is NULL.
+ - SubnetAddress is NULL.
+ - SubnetMask is NULL.
+ - GatewayAddress is NULL.
+ - *SubnetAddress is not a valid subnet address.
+ - *SubnetMask is not a valid subnet mask.
+ - *GatewayAddress is not a valid unicast IPv4 address.
+ @retval EFI_OUT_OF_RESOURCES Could not add the entry to the routing table.
+ @retval EFI_NOT_FOUND This route is not in the routing table (when DeleteRoute is TRUE).
+ @retval EFI_ACCESS_DENIED The route is already defined in the routing table (when
+ DeleteRoute is FALSE).
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_IP4_ROUTES)(
+ IN EFI_IP4_PROTOCOL *This,
+ IN BOOLEAN DeleteRoute,
+ IN EFI_IPv4_ADDRESS *SubnetAddress,
+ IN EFI_IPv4_ADDRESS *SubnetMask,
+ IN EFI_IPv4_ADDRESS *GatewayAddress
+ );
+
+/**
+ Places outgoing data packets into the transmit queue.
+
+ The Transmit() function places a sending request in the transmit queue of this
+ EFI IPv4 Protocol instance. Whenever the packet in the token is sent out or some
+ errors occur, the event in the token will be signaled and the status is updated.
+
+ @param This The pointer to the EFI_IP4_PROTOCOL instance.
+ @param Token The pointer to the transmit token.
+
+ @retval EFI_SUCCESS The data has been queued for transmission.
+ @retval EFI_NOT_STARTED This instance has not been started.
+ @retval EFI_NO_MAPPING When using the default address, configuration (DHCP, BOOTP,
+ RARP, etc.) is not finished yet.
+ @retval EFI_INVALID_PARAMETER One or more pameters are invalid.
+ @retval EFI_ACCESS_DENIED The transmit completion token with the same Token.Event
+ was already in the transmit queue.
+ @retval EFI_NOT_READY The completion token could not be queued because the transmit
+ queue is full.
+ @retval EFI_NOT_FOUND Not route is found to destination address.
+ @retval EFI_OUT_OF_RESOURCES Could not queue the transmit data.
+ @retval EFI_BUFFER_TOO_SMALL Token.Packet.TxData.TotalDataLength is too
+ short to transmit.
+ @retval EFI_BAD_BUFFER_SIZE The length of the IPv4 header + option length + total data length is
+ greater than MTU (or greater than the maximum packet size if
+ Token.Packet.TxData.OverrideData.
+ DoNotFragment is TRUE.)
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_IP4_TRANSMIT)(
+ IN EFI_IP4_PROTOCOL *This,
+ IN EFI_IP4_COMPLETION_TOKEN *Token
+ );
+
+/**
+ Places a receiving request into the receiving queue.
+
+ The Receive() function places a completion token into the receive packet queue.
+ This function is always asynchronous.
+
+ The Token.Event field in the completion token must be filled in by the caller
+ and cannot be NULL. When the receive operation completes, the EFI IPv4 Protocol
+ driver updates the Token.Status and Token.Packet.RxData fields and the Token.Event
+ is signaled.
+
+ @param This The pointer to the EFI_IP4_PROTOCOL instance.
+ @param Token The pointer to a token that is associated with the receive data descriptor.
+
+ @retval EFI_SUCCESS The receive completion token was cached.
+ @retval EFI_NOT_STARTED This EFI IPv4 Protocol instance has not been started.
+ @retval EFI_NO_MAPPING When using the default address, configuration (DHCP, BOOTP, RARP, etc.)
+ is not finished yet.
+ @retval EFI_INVALID_PARAMETER One or more of the following conditions is TRUE:
+ - This is NULL.
+ - Token is NULL.
+ - Token.Event is NULL.
+ @retval EFI_OUT_OF_RESOURCES The receive completion token could not be queued due to a lack of system
+ resources (usually memory).
+ @retval EFI_DEVICE_ERROR An unexpected system or network error occurred.
+ The EFI IPv4 Protocol instance has been reset to startup defaults.
+ @retval EFI_ACCESS_DENIED The receive completion token with the same Token.Event was already
+ in the receive queue.
+ @retval EFI_NOT_READY The receive request could not be queued because the receive queue is full.
+ @retval EFI_ICMP_ERROR An ICMP error packet was received.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_IP4_RECEIVE)(
+ IN EFI_IP4_PROTOCOL *This,
+ IN EFI_IP4_COMPLETION_TOKEN *Token
+ );
+
+/**
+ Abort an asynchronous transmit or receive request.
+
+ The Cancel() function is used to abort a pending transmit or receive request.
+ If the token is in the transmit or receive request queues, after calling this
+ function, Token->Status will be set to EFI_ABORTED and then Token->Event will
+ be signaled. If the token is not in one of the queues, which usually means the
+ asynchronous operation has completed, this function will not signal the token
+ and EFI_NOT_FOUND is returned.
+
+ @param This The pointer to the EFI_IP4_PROTOCOL instance.
+ @param Token The pointer to a token that has been issued by
+ EFI_IP4_PROTOCOL.Transmit() or
+ EFI_IP4_PROTOCOL.Receive(). If NULL, all pending
+ tokens are aborted. Type EFI_IP4_COMPLETION_TOKEN is
+ defined in EFI_IP4_PROTOCOL.Transmit().
+
+ @retval EFI_SUCCESS The asynchronous I/O request was aborted and
+ Token->Event was signaled. When Token is NULL, all
+ pending requests were aborted and their events were signaled.
+ @retval EFI_INVALID_PARAMETER This is NULL.
+ @retval EFI_NOT_STARTED This instance has not been started.
+ @retval EFI_NO_MAPPING When using the default address, configuration (DHCP, BOOTP,
+ RARP, etc.) is not finished yet.
+ @retval EFI_NOT_FOUND When Token is not NULL, the asynchronous I/O request was
+ not found in the transmit or receive queue. It has either completed
+ or was not issued by Transmit() and Receive().
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_IP4_CANCEL)(
+ IN EFI_IP4_PROTOCOL *This,
+ IN EFI_IP4_COMPLETION_TOKEN *Token OPTIONAL
+ );
+
+/**
+ Polls for incoming data packets and processes outgoing data packets.
+
+ The Poll() function polls for incoming data packets and processes outgoing data
+ packets. Network drivers and applications can call the EFI_IP4_PROTOCOL.Poll()
+ function to increase the rate that data packets are moved between the communications
+ device and the transmit and receive queues.
+
+ In some systems the periodic timer event may not poll the underlying communications
+ device fast enough to transmit and/or receive all data packets without missing
+ incoming packets or dropping outgoing packets. Drivers and applications that are
+ experiencing packet loss should try calling the EFI_IP4_PROTOCOL.Poll() function
+ more often.
+
+ @param This The pointer to the EFI_IP4_PROTOCOL instance.
+
+ @retval EFI_SUCCESS Incoming or outgoing data was processed.
+ @retval EFI_NOT_STARTED This EFI IPv4 Protocol instance has not been started.
+ @retval EFI_NO_MAPPING When using the default address, configuration (DHCP, BOOTP,
+ RARP, etc.) is not finished yet.
+ @retval EFI_INVALID_PARAMETER This is NULL.
+ @retval EFI_DEVICE_ERROR An unexpected system or network error occurred.
+ @retval EFI_NOT_READY No incoming or outgoing data is processed.
+ @retval EFI_TIMEOUT Data was dropped out of the transmit and/or receive queue.
+ Consider increasing the polling rate.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_IP4_POLL)(
+ IN EFI_IP4_PROTOCOL *This
+ );
+
+///
+/// The EFI IPv4 Protocol implements a simple packet-oriented interface that can be
+/// used by drivers, daemons, and applications to transmit and receive network packets.
+///
+struct _EFI_IP4_PROTOCOL {
+ EFI_IP4_GET_MODE_DATA GetModeData;
+ EFI_IP4_CONFIGURE Configure;
+ EFI_IP4_GROUPS Groups;
+ EFI_IP4_ROUTES Routes;
+ EFI_IP4_TRANSMIT Transmit;
+ EFI_IP4_RECEIVE Receive;
+ EFI_IP4_CANCEL Cancel;
+ EFI_IP4_POLL Poll;
+};
+
+extern EFI_GUID gEfiIp4ServiceBindingProtocolGuid;
+extern EFI_GUID gEfiIp4ProtocolGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/Ip4Config.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/Ip4Config.h
new file mode 100644
index 0000000000..5a2aba05b4
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/Ip4Config.h
@@ -0,0 +1,176 @@
+/** @file
+ This file provides a definition of the EFI IPv4 Configuration
+ Protocol.
+
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Revision Reference:
+ This Protocol is introduced in UEFI Specification 2.0.
+
+**/
+
+#ifndef __EFI_IP4CONFIG_PROTOCOL_H__
+#define __EFI_IP4CONFIG_PROTOCOL_H__
+
+#include
+
+#define EFI_IP4_CONFIG_PROTOCOL_GUID \
+ { \
+ 0x3b95aa31, 0x3793, 0x434b, {0x86, 0x67, 0xc8, 0x07, 0x08, 0x92, 0xe0, 0x5e } \
+ }
+
+typedef struct _EFI_IP4_CONFIG_PROTOCOL EFI_IP4_CONFIG_PROTOCOL;
+
+#define IP4_CONFIG_VARIABLE_ATTRIBUTES \
+ (EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS)
+
+///
+/// EFI_IP4_IPCONFIG_DATA contains the minimum IPv4 configuration data
+/// that is needed to start basic network communication. The StationAddress
+/// and SubnetMask must be a valid unicast IP address and subnet mask.
+/// If RouteTableSize is not zero, then RouteTable contains a properly
+/// formatted routing table for the StationAddress/SubnetMask, with the
+/// last entry in the table being the default route.
+///
+typedef struct {
+ ///
+ /// Default station IP address, stored in network byte order.
+ ///
+ EFI_IPv4_ADDRESS StationAddress;
+ ///
+ /// Default subnet mask, stored in network byte order.
+ ///
+ EFI_IPv4_ADDRESS SubnetMask;
+ ///
+ /// Number of entries in the following RouteTable. May be zero.
+ ///
+ UINT32 RouteTableSize;
+ ///
+ /// Default routing table data (stored in network byte order).
+ /// Ignored if RouteTableSize is zero.
+ ///
+ EFI_IP4_ROUTE_TABLE *RouteTable;
+} EFI_IP4_IPCONFIG_DATA;
+
+/**
+ Starts running the configuration policy for the EFI IPv4 Protocol driver.
+
+ The Start() function is called to determine and to begin the platform
+ configuration policy by the EFI IPv4 Protocol driver. This determination may
+ be as simple as returning EFI_UNSUPPORTED if there is no EFI IPv4 Protocol
+ driver configuration policy. It may be as involved as loading some defaults
+ from nonvolatile storage, downloading dynamic data from a DHCP server, and
+ checking permissions with a site policy server.
+ Starting the configuration policy is just the beginning. It may finish almost
+ instantly or it may take several minutes before it fails to retrieve configuration
+ information from one or more servers. Once the policy is started, drivers
+ should use the DoneEvent parameter to determine when the configuration policy
+ has completed. EFI_IP4_CONFIG_PROTOCOL.GetData() must then be called to
+ determine if the configuration succeeded or failed.
+ Until the configuration completes successfully, EFI IPv4 Protocol driver instances
+ that are attempting to use default configurations must return EFI_NO_MAPPING.
+ Once the configuration is complete, the EFI IPv4 Configuration Protocol driver
+ signals DoneEvent. The configuration may need to be updated in the future.
+ Note that in this case the EFI IPv4 Configuration Protocol driver must signal
+ ReconfigEvent, and all EFI IPv4 Protocol driver instances that are using default
+ configurations must return EFI_NO_MAPPING until the configuration policy has
+ been rerun.
+
+ @param This The pointer to the EFI_IP4_CONFIG_PROTOCOL instance.
+ @param DoneEvent Event that will be signaled when the EFI IPv4
+ Protocol driver configuration policy completes
+ execution. This event must be of type EVT_NOTIFY_SIGNAL.
+ @param ReconfigEvent Event that will be signaled when the EFI IPv4
+ Protocol driver configuration needs to be updated.
+ This event must be of type EVT_NOTIFY_SIGNAL.
+
+ @retval EFI_SUCCESS The configuration policy for the EFI IPv4 Protocol
+ driver is now running.
+ @retval EFI_INVALID_PARAMETER One or more of the following parameters is NULL:
+ This
+ DoneEvent
+ ReconfigEvent
+ @retval EFI_OUT_OF_RESOURCES Required system resources could not be allocated.
+ @retval EFI_ALREADY_STARTED The configuration policy for the EFI IPv4 Protocol
+ driver was already started.
+ @retval EFI_DEVICE_ERROR An unexpected system error or network error occurred.
+ @retval EFI_UNSUPPORTED This interface does not support the EFI IPv4 Protocol
+ driver configuration.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_IP4_CONFIG_START)(
+ IN EFI_IP4_CONFIG_PROTOCOL *This,
+ IN EFI_EVENT DoneEvent,
+ IN EFI_EVENT ReconfigEvent
+ );
+
+/**
+ Stops running the configuration policy for the EFI IPv4 Protocol driver.
+
+ The Stop() function stops the configuration policy for the EFI IPv4 Protocol driver.
+ All configuration data will be lost after calling Stop().
+
+ @param This The pointer to the EFI_IP4_CONFIG_PROTOCOL instance.
+
+ @retval EFI_SUCCESS The configuration policy for the EFI IPv4 Protocol
+ driver has been stopped.
+ @retval EFI_INVALID_PARAMETER This is NULL.
+ @retval EFI_NOT_STARTED The configuration policy for the EFI IPv4 Protocol
+ driver was not started.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_IP4_CONFIG_STOP)(
+ IN EFI_IP4_CONFIG_PROTOCOL *This
+ );
+
+/**
+ Returns the default configuration data (if any) for the EFI IPv4 Protocol driver.
+
+ The GetData() function returns the current configuration data for the EFI IPv4
+ Protocol driver after the configuration policy has completed.
+
+ @param This The pointer to the EFI_IP4_CONFIG_PROTOCOL instance.
+ @param IpConfigDataSize On input, the size of the IpConfigData buffer.
+ On output, the count of bytes that were written
+ into the IpConfigData buffer.
+ @param IpConfigData The pointer to the EFI IPv4 Configuration Protocol
+ driver configuration data structure.
+ Type EFI_IP4_IPCONFIG_DATA is defined in
+ "Related Definitions" below.
+
+ @retval EFI_SUCCESS The EFI IPv4 Protocol driver configuration has been returned.
+ @retval EFI_INVALID_PARAMETER This is NULL.
+ @retval EFI_NOT_STARTED The configuration policy for the EFI IPv4 Protocol
+ driver is not running.
+ @retval EFI_NOT_READY EFI IPv4 Protocol driver configuration is still running.
+ @retval EFI_ABORTED EFI IPv4 Protocol driver configuration could not complete.
+ @retval EFI_BUFFER_TOO_SMALL *IpConfigDataSize is smaller than the configuration
+ data buffer or IpConfigData is NULL.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_IP4_CONFIG_GET_DATA)(
+ IN EFI_IP4_CONFIG_PROTOCOL *This,
+ IN OUT UINTN *IpConfigDataSize,
+ OUT EFI_IP4_IPCONFIG_DATA *IpConfigData OPTIONAL
+ );
+
+///
+/// The EFI_IP4_CONFIG_PROTOCOL driver performs platform-dependent and policy-dependent
+/// configurations for the EFI IPv4 Protocol driver.
+///
+struct _EFI_IP4_CONFIG_PROTOCOL {
+ EFI_IP4_CONFIG_START Start;
+ EFI_IP4_CONFIG_STOP Stop;
+ EFI_IP4_CONFIG_GET_DATA GetData;
+};
+
+extern EFI_GUID gEfiIp4ConfigProtocolGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/Ip4Config2.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/Ip4Config2.h
new file mode 100644
index 0000000000..407dae2290
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/Ip4Config2.h
@@ -0,0 +1,316 @@
+/** @file
+ This file provides a definition of the EFI IPv4 Configuration II
+ Protocol.
+
+Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+@par Revision Reference:
+This Protocol is introduced in UEFI Specification 2.5
+
+**/
+
+#ifndef __EFI_IP4CONFIG2_PROTOCOL_H__
+#define __EFI_IP4CONFIG2_PROTOCOL_H__
+
+#include
+
+#define EFI_IP4_CONFIG2_PROTOCOL_GUID \
+ { \
+ 0x5b446ed1, 0xe30b, 0x4faa, {0x87, 0x1a, 0x36, 0x54, 0xec, 0xa3, 0x60, 0x80 } \
+ }
+
+typedef struct _EFI_IP4_CONFIG2_PROTOCOL EFI_IP4_CONFIG2_PROTOCOL;
+
+///
+/// EFI_IP4_CONFIG2_DATA_TYPE
+///
+typedef enum {
+ ///
+ /// The interface information of the communication device this EFI
+ /// IPv4 Configuration II Protocol instance manages. This type of
+ /// data is read only. The corresponding Data is of type
+ /// EFI_IP4_CONFIG2_INTERFACE_INFO.
+ ///
+ Ip4Config2DataTypeInterfaceInfo,
+ ///
+ /// The general configuration policy for the EFI IPv4 network stack
+ /// running on the communication device this EFI IPv4
+ /// Configuration II Protocol instance manages. The policy will
+ /// affect other configuration settings. The corresponding Data is of
+ /// type EFI_IP4_CONFIG2_POLICY.
+ ///
+ Ip4Config2DataTypePolicy,
+ ///
+ /// The station addresses set manually for the EFI IPv4 network
+ /// stack. It is only configurable when the policy is
+ /// Ip4Config2PolicyStatic. The corresponding Data is of
+ /// type EFI_IP4_CONFIG2_MANUAL_ADDRESS. When DataSize
+ /// is 0 and Data is NULL, the existing configuration is cleared
+ /// from the EFI IPv4 Configuration II Protocol instance.
+ ///
+ Ip4Config2DataTypeManualAddress,
+ ///
+ /// The gateway addresses set manually for the EFI IPv4 network
+ /// stack running on the communication device this EFI IPv4
+ /// Configuration II Protocol manages. It is not configurable when
+ /// the policy is Ip4Config2PolicyDhcp. The gateway
+ /// addresses must be unicast IPv4 addresses. The corresponding
+ /// Data is a pointer to an array of EFI_IPv4_ADDRESS instances.
+ /// When DataSize is 0 and Data is NULL, the existing configuration
+ /// is cleared from the EFI IPv4 Configuration II Protocol instance.
+ ///
+ Ip4Config2DataTypeGateway,
+ ///
+ /// The DNS server list for the EFI IPv4 network stack running on
+ /// the communication device this EFI IPv4 Configuration II
+ /// Protocol manages. It is not configurable when the policy is
+ /// Ip4Config2PolicyDhcp. The DNS server addresses must be
+ /// unicast IPv4 addresses. The corresponding Data is a pointer to
+ /// an array of EFI_IPv4_ADDRESS instances. When DataSize
+ /// is 0 and Data is NULL, the existing configuration is cleared
+ /// from the EFI IPv4 Configuration II Protocol instance.
+ ///
+ Ip4Config2DataTypeDnsServer,
+ Ip4Config2DataTypeMaximum
+} EFI_IP4_CONFIG2_DATA_TYPE;
+
+///
+/// EFI_IP4_CONFIG2_INTERFACE_INFO related definitions
+///
+#define EFI_IP4_CONFIG2_INTERFACE_INFO_NAME_SIZE 32
+
+///
+/// EFI_IP4_CONFIG2_INTERFACE_INFO
+///
+typedef struct {
+ ///
+ /// The name of the interface. It is a NULL-terminated Unicode string.
+ ///
+ CHAR16 Name[EFI_IP4_CONFIG2_INTERFACE_INFO_NAME_SIZE];
+ ///
+ /// The interface type of the network interface. See RFC 1700,
+ /// section "Number Hardware Type".
+ ///
+ UINT8 IfType;
+ ///
+ /// The size, in bytes, of the network interface's hardware address.
+ ///
+ UINT32 HwAddressSize;
+ ///
+ /// The hardware address for the network interface.
+ ///
+ EFI_MAC_ADDRESS HwAddress;
+ ///
+ /// The station IPv4 address of this EFI IPv4 network stack.
+ ///
+ EFI_IPv4_ADDRESS StationAddress;
+ ///
+ /// The subnet address mask that is associated with the station address.
+ ///
+ EFI_IPv4_ADDRESS SubnetMask;
+ ///
+ /// Size of the following RouteTable, in bytes. May be zero.
+ ///
+ UINT32 RouteTableSize;
+ ///
+ /// The route table of the IPv4 network stack runs on this interface.
+ /// Set to NULL if RouteTableSize is zero. Type EFI_IP4_ROUTE_TABLE is defined in
+ /// EFI_IP4_PROTOCOL.GetModeData().
+ ///
+ EFI_IP4_ROUTE_TABLE *RouteTable OPTIONAL;
+} EFI_IP4_CONFIG2_INTERFACE_INFO;
+
+///
+/// EFI_IP4_CONFIG2_POLICY
+///
+typedef enum {
+ ///
+ /// Under this policy, the Ip4Config2DataTypeManualAddress,
+ /// Ip4Config2DataTypeGateway and Ip4Config2DataTypeDnsServer configuration
+ /// data are required to be set manually. The EFI IPv4 Protocol will get all
+ /// required configuration such as IPv4 address, subnet mask and
+ /// gateway settings from the EFI IPv4 Configuration II protocol.
+ ///
+ Ip4Config2PolicyStatic,
+ ///
+ /// Under this policy, the Ip4Config2DataTypeManualAddress,
+ /// Ip4Config2DataTypeGateway and Ip4Config2DataTypeDnsServer configuration data are
+ /// not allowed to set via SetData(). All of these configurations are retrieved from DHCP
+ /// server or other auto-configuration mechanism.
+ ///
+ Ip4Config2PolicyDhcp,
+ Ip4Config2PolicyMax
+} EFI_IP4_CONFIG2_POLICY;
+
+///
+/// EFI_IP4_CONFIG2_MANUAL_ADDRESS
+///
+typedef struct {
+ ///
+ /// The IPv4 unicast address.
+ ///
+ EFI_IPv4_ADDRESS Address;
+ ///
+ /// The subnet mask.
+ ///
+ EFI_IPv4_ADDRESS SubnetMask;
+} EFI_IP4_CONFIG2_MANUAL_ADDRESS;
+
+/**
+ Set the configuration for the EFI IPv4 network stack running on the communication device this EFI
+ IPv4 Configuration II Protocol instance manages.
+
+ This function is used to set the configuration data of type DataType for the EFI IPv4 network stack
+ running on the communication device this EFI IPv4 Configuration II Protocol instance manages.
+ The successfully configured data is valid after system reset or power-off.
+ The DataSize is used to calculate the count of structure instances in the Data for some
+ DataType that multiple structure instances are allowed.
+ This function is always non-blocking. When setting some typeof configuration data, an
+ asynchronous process is invoked to check the correctness of the data, such as doing address conflict
+ detection on the manually set local IPv4 address. EFI_NOT_READY is returned immediately to
+ indicate that such an asynchronous process is invoked and the process is not finished yet. The caller
+ willing to get the result of the asynchronous process is required to call RegisterDataNotify()
+ to register an event on the specified configuration data. Once the event is signaled, the caller can call
+ GetData()to get back the configuration data in order to know the result. For other types of
+ configuration data that do not require an asynchronous configuration process, the result of the
+ operation is immediately returned.
+
+ @param[in] This Pointer to the EFI_IP4_CONFIG2_PROTOCOL instance.
+ @param[in] DataType The type of data to set.
+ @param[in] DataSize Size of the buffer pointed to by Data in bytes.
+ @param[in] Data The data buffer to set. The type ofthe data buffer is associated
+ with the DataType.
+
+ @retval EFI_SUCCESS The specified configuration data for the EFI IPv4 network stack is set
+ successfully.
+ @retval EFI_INVALID_PARAMETER One or more of the following are TRUE:
+ This is NULL.
+ One or more fields in Data and DataSize do not match the
+ requirement of the data type indicated by DataType.
+ @retval EFI_WRITE_PROTECTED The specified configuration data is read-only or the specified configuration
+ data can not be set under the current policy.
+ @retval EFI_ACCESS_DENIED Another set operation on the specified configuration data is already in process.
+ @retval EFI_NOT_READY An asynchronous process is invoked to set the specified configuration data and
+ the process is not finished yet.
+ @retval EFI_BAD_BUFFER_SIZE The DataSize does not match the size of the type indicated by DataType.
+ @retval EFI_UNSUPPORTED This DataType is not supported.
+ @retval EFI_OUT_OF_RESOURCES Required system resources could not be allocated.
+ @retval EFI_DEVICE_ERROR An unexpected system error or network error occurred.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_IP4_CONFIG2_SET_DATA)(
+ IN EFI_IP4_CONFIG2_PROTOCOL *This,
+ IN EFI_IP4_CONFIG2_DATA_TYPE DataType,
+ IN UINTN DataSize,
+ IN VOID *Data
+ );
+
+/**
+ Get the configuration data for the EFI IPv4 network stack running on the communication device this
+ EFI IPv4 Configuration II Protocol instance manages.
+
+ This function returns the configuration data of type DataType for the EFI IPv4 network stack
+ running on the communication device this EFI IPv4 Configuration II Protocol instance manages.
+ The caller is responsible for allocating the buffer usedto return the specified configuration data and
+ the required size will be returned to the caller if the size of the buffer is too small.
+ EFI_NOT_READY is returned if the specified configuration data is not ready due to an already in
+ progress asynchronous configuration process. The caller can call RegisterDataNotify() to
+ register an event on the specified configuration data. Once the asynchronous configuration process is
+ finished, the event will be signaled and a subsequent GetData() call will return the specified
+ configuration data.
+
+ @param[in] This Pointer to the EFI_IP4_CONFIG2_PROTOCOL instance.
+ @param[in] DataType The type of data to get.
+ @param[out] DataSize On input, in bytes, the size of Data. On output, in bytes, the size
+ of buffer required to store the specified configuration data.
+ @param[in] Data The data buffer in which the configuration data is returned. The
+ type of the data buffer is associated with the DataType. Ignored
+ if DataSize is 0.
+
+ @retval EFI_SUCCESS The specified configuration data is got successfully.
+ @retval EFI_INVALID_PARAMETER One or more of the followings are TRUE:
+ This is NULL.
+ DataSize is NULL.
+ Data is NULL if *DataSizeis not zero.
+ @retval EFI_BUFFER_TOO_SMALL The size of Data is too small for the specified configuration data
+ and the required size is returned in DataSize.
+ @retval EFI_NOT_READY The specified configuration data is not ready due to an already in
+ progress asynchronous configuration process.
+ @retval EFI_NOT_FOUND The specified configuration data is not found.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_IP4_CONFIG2_GET_DATA)(
+ IN EFI_IP4_CONFIG2_PROTOCOL *This,
+ IN EFI_IP4_CONFIG2_DATA_TYPE DataType,
+ IN OUT UINTN *DataSize,
+ IN VOID *Data OPTIONAL
+ );
+
+/**
+ Register an event that is to be signaled whenever a configuration process on the specified
+ configuration data is done.
+
+ This function registers an event that is to be signaled whenever a configuration process on the
+ specified configuration data is done. An event can be registered for different DataType
+ simultaneously and the caller is responsible for determining which type of configuration data causes
+ the signaling of the event in such case.
+
+ @param[in] This Pointer to the EFI_IP4_CONFIG2_PROTOCOL instance.
+ @param[in] DataType The type of data to unregister the event for.
+ @param[in] Event The event to register.
+
+ @retval EFI_SUCCESS The notification event for the specified configuration data is
+ registered.
+ @retval EFI_INVALID_PARAMETER This is NULL or Event is NULL.
+ @retval EFI_UNSUPPORTED The configuration data type specified by DataType is not supported.
+ @retval EFI_OUT_OF_RESOURCES Required system resources could not be allocated.
+ @retval EFI_ACCESS_DENIED The Event is already registered for the DataType.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_IP4_CONFIG2_REGISTER_NOTIFY)(
+ IN EFI_IP4_CONFIG2_PROTOCOL *This,
+ IN EFI_IP4_CONFIG2_DATA_TYPE DataType,
+ IN EFI_EVENT Event
+ );
+
+/**
+ Remove a previously registered event for the specified configuration data.
+
+ This function removes a previously registeredevent for the specified configuration data.
+
+ @param[in] This Pointer to the EFI_IP4_CONFIG2_PROTOCOL instance.
+ @param[in] DataType The type of data to remove the previously registered event for.
+ @param[in] Event The event to unregister.
+
+ @retval EFI_SUCCESS The event registered for the specified configuration data is removed.
+ @retval EFI_INVALID_PARAMETER This is NULL or Event is NULL.
+ @retval EFI_NOT_FOUND The Eventhas not been registered for the specified DataType.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_IP4_CONFIG2_UNREGISTER_NOTIFY)(
+ IN EFI_IP4_CONFIG2_PROTOCOL *This,
+ IN EFI_IP4_CONFIG2_DATA_TYPE DataType,
+ IN EFI_EVENT Event
+ );
+
+///
+/// The EFI_IP4_CONFIG2_PROTOCOL is designed to be the central repository for the common
+/// configurations and the administrator configurable settings for the EFI IPv4 network stack.
+/// An EFI IPv4 Configuration II Protocol instance will be installed on each communication device that
+/// the EFI IPv4 network stack runs on.
+///
+struct _EFI_IP4_CONFIG2_PROTOCOL {
+ EFI_IP4_CONFIG2_SET_DATA SetData;
+ EFI_IP4_CONFIG2_GET_DATA GetData;
+ EFI_IP4_CONFIG2_REGISTER_NOTIFY RegisterDataNotify;
+ EFI_IP4_CONFIG2_UNREGISTER_NOTIFY UnregisterDataNotify;
+};
+
+extern EFI_GUID gEfiIp4Config2ProtocolGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/Ip6.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/Ip6.h
new file mode 100644
index 0000000000..c5e424c483
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/Ip6.h
@@ -0,0 +1,946 @@
+/** @file
+ This file defines the EFI IPv6 (Internet Protocol version 6)
+ Protocol interface. It is split into the following three main
+ sections:
+ - EFI IPv6 Service Binding Protocol
+ - EFI IPv6 Variable (deprecated in UEFI 2.4B)
+ - EFI IPv6 Protocol
+ The EFI IPv6 Protocol provides basic network IPv6 packet I/O services,
+ which includes support for Neighbor Discovery Protocol (ND), Multicast
+ Listener Discovery Protocol (MLD), and a subset of the Internet Control
+ Message Protocol (ICMPv6).
+
+ Copyright (c) 2008 - 2014, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Revision Reference:
+ This Protocol is introduced in UEFI Specification 2.2
+
+**/
+
+#ifndef __EFI_IP6_PROTOCOL_H__
+#define __EFI_IP6_PROTOCOL_H__
+
+#include
+
+#define EFI_IP6_SERVICE_BINDING_PROTOCOL_GUID \
+ { \
+ 0xec835dd3, 0xfe0f, 0x617b, {0xa6, 0x21, 0xb3, 0x50, 0xc3, 0xe1, 0x33, 0x88 } \
+ }
+
+#define EFI_IP6_PROTOCOL_GUID \
+ { \
+ 0x2c8759d5, 0x5c2d, 0x66ef, {0x92, 0x5f, 0xb6, 0x6c, 0x10, 0x19, 0x57, 0xe2 } \
+ }
+
+typedef struct _EFI_IP6_PROTOCOL EFI_IP6_PROTOCOL;
+
+///
+/// EFI_IP6_ADDRESS_PAIR is deprecated in the UEFI 2.4B and should not be used any more.
+/// The definition in here is only present to provide backwards compatability.
+///
+typedef struct {
+ ///
+ /// The EFI IPv6 Protocol instance handle that is using this address/prefix pair.
+ ///
+ EFI_HANDLE InstanceHandle;
+ ///
+ /// IPv6 address in network byte order.
+ ///
+ EFI_IPv6_ADDRESS Ip6Address;
+ ///
+ /// The length of the prefix associated with the Ip6Address.
+ ///
+ UINT8 PrefixLength;
+} EFI_IP6_ADDRESS_PAIR;
+
+///
+/// EFI_IP6_VARIABLE_DATA is deprecated in the UEFI 2.4B and should not be used any more.
+/// The definition in here is only present to provide backwards compatability.
+///
+typedef struct {
+ ///
+ /// The handle of the driver that creates this entry.
+ ///
+ EFI_HANDLE DriverHandle;
+ ///
+ /// The number of IPv6 address pairs that follow this data structure.
+ ///
+ UINT32 AddressCount;
+ ///
+ /// List of IPv6 address pairs that are currently in use.
+ ///
+ EFI_IP6_ADDRESS_PAIR AddressPairs[1];
+} EFI_IP6_VARIABLE_DATA;
+
+///
+/// ICMPv6 type definitions for error messages
+///
+///@{
+#define ICMP_V6_DEST_UNREACHABLE 0x1
+#define ICMP_V6_PACKET_TOO_BIG 0x2
+#define ICMP_V6_TIME_EXCEEDED 0x3
+#define ICMP_V6_PARAMETER_PROBLEM 0x4
+///@}
+
+///
+/// ICMPv6 type definition for informational messages
+///
+///@{
+#define ICMP_V6_ECHO_REQUEST 0x80
+#define ICMP_V6_ECHO_REPLY 0x81
+#define ICMP_V6_LISTENER_QUERY 0x82
+#define ICMP_V6_LISTENER_REPORT 0x83
+#define ICMP_V6_LISTENER_DONE 0x84
+#define ICMP_V6_ROUTER_SOLICIT 0x85
+#define ICMP_V6_ROUTER_ADVERTISE 0x86
+#define ICMP_V6_NEIGHBOR_SOLICIT 0x87
+#define ICMP_V6_NEIGHBOR_ADVERTISE 0x88
+#define ICMP_V6_REDIRECT 0x89
+#define ICMP_V6_LISTENER_REPORT_2 0x8F
+///@}
+
+///
+/// ICMPv6 code definitions for ICMP_V6_DEST_UNREACHABLE
+///
+///@{
+#define ICMP_V6_NO_ROUTE_TO_DEST 0x0
+#define ICMP_V6_COMM_PROHIBITED 0x1
+#define ICMP_V6_BEYOND_SCOPE 0x2
+#define ICMP_V6_ADDR_UNREACHABLE 0x3
+#define ICMP_V6_PORT_UNREACHABLE 0x4
+#define ICMP_V6_SOURCE_ADDR_FAILED 0x5
+#define ICMP_V6_ROUTE_REJECTED 0x6
+///@}
+
+///
+/// ICMPv6 code definitions for ICMP_V6_TIME_EXCEEDED
+///
+///@{
+#define ICMP_V6_TIMEOUT_HOP_LIMIT 0x0
+#define ICMP_V6_TIMEOUT_REASSEMBLE 0x1
+///@}
+
+///
+/// ICMPv6 code definitions for ICMP_V6_PARAMETER_PROBLEM
+///
+///@{
+#define ICMP_V6_ERRONEOUS_HEADER 0x0
+#define ICMP_V6_UNRECOGNIZE_NEXT_HDR 0x1
+#define ICMP_V6_UNRECOGNIZE_OPTION 0x2
+///@}
+
+///
+/// EFI_IP6_CONFIG_DATA
+/// is used to report and change IPv6 session parameters.
+///
+typedef struct {
+ ///
+ /// For the IPv6 packet to send and receive, this is the default value
+ /// of the 'Next Header' field in the last IPv6 extension header or in
+ /// the IPv6 header if there are no extension headers. Ignored when
+ /// AcceptPromiscuous is TRUE.
+ ///
+ UINT8 DefaultProtocol;
+ ///
+ /// Set to TRUE to receive all IPv6 packets that get through the
+ /// receive filters.
+ /// Set to FALSE to receive only the DefaultProtocol IPv6
+ /// packets that get through the receive filters. Ignored when
+ /// AcceptPromiscuous is TRUE.
+ ///
+ BOOLEAN AcceptAnyProtocol;
+ ///
+ /// Set to TRUE to receive ICMP error report packets. Ignored when
+ /// AcceptPromiscuous or AcceptAnyProtocol is TRUE.
+ ///
+ BOOLEAN AcceptIcmpErrors;
+ ///
+ /// Set to TRUE to receive all IPv6 packets that are sent to any
+ /// hardware address or any protocol address. Set to FALSE to stop
+ /// receiving all promiscuous IPv6 packets.
+ ///
+ BOOLEAN AcceptPromiscuous;
+ ///
+ /// The destination address of the packets that will be transmitted.
+ /// Ignored if it is unspecified.
+ ///
+ EFI_IPv6_ADDRESS DestinationAddress;
+ ///
+ /// The station IPv6 address that will be assigned to this EFI IPv6
+ /// Protocol instance. This field can be set and changed only when
+ /// the EFI IPv6 driver is transitioning from the stopped to the started
+ /// states. If the StationAddress is specified, the EFI IPv6 Protocol
+ /// driver will deliver only incoming IPv6 packets whose destination
+ /// matches this IPv6 address exactly. The StationAddress is required
+ /// to be one of currently configured IPv6 addresses. An address
+ /// containing all zeroes is also accepted as a special case. Under this
+ /// situation, the IPv6 driver is responsible for binding a source
+ /// address to this EFI IPv6 protocol instance according to the source
+ /// address selection algorithm. Only incoming packets destined to
+ /// the selected address will be delivered to the user. And the
+ /// selected station address can be retrieved through later
+ /// GetModeData() call. If no address is available for selecting,
+ /// EFI_NO_MAPPING will be returned, and the station address will
+ /// only be successfully bound to this EFI IPv6 protocol instance
+ /// after IP6ModeData.IsConfigured changed to TRUE.
+ ///
+ EFI_IPv6_ADDRESS StationAddress;
+ ///
+ /// TrafficClass field in transmitted IPv6 packets. Default value
+ /// is zero.
+ ///
+ UINT8 TrafficClass;
+ ///
+ /// HopLimit field in transmitted IPv6 packets.
+ ///
+ UINT8 HopLimit;
+ ///
+ /// FlowLabel field in transmitted IPv6 packets. Default value is
+ /// zero.
+ ///
+ UINT32 FlowLabel;
+ ///
+ /// The timer timeout value (number of microseconds) for the
+ /// receive timeout event to be associated with each assembled
+ /// packet. Zero means do not drop assembled packets.
+ ///
+ UINT32 ReceiveTimeout;
+ ///
+ /// The timer timeout value (number of microseconds) for the
+ /// transmit timeout event to be associated with each outgoing
+ /// packet. Zero means do not drop outgoing packets.
+ ///
+ UINT32 TransmitTimeout;
+} EFI_IP6_CONFIG_DATA;
+
+///
+/// EFI_IP6_ADDRESS_INFO
+///
+typedef struct {
+ EFI_IPv6_ADDRESS Address; ///< The IPv6 address.
+ UINT8 PrefixLength; ///< The length of the prefix associated with the Address.
+} EFI_IP6_ADDRESS_INFO;
+
+///
+/// EFI_IP6_ROUTE_TABLE
+/// is the entry structure that is used in routing tables
+///
+typedef struct {
+ ///
+ /// The IPv6 address of the gateway to be used as the next hop for
+ /// packets to this prefix. If the IPv6 address is all zeros, then the
+ /// prefix is on-link.
+ ///
+ EFI_IPv6_ADDRESS Gateway;
+ ///
+ /// The destination prefix to be routed.
+ ///
+ EFI_IPv6_ADDRESS Destination;
+ ///
+ /// The length of the prefix associated with the Destination.
+ ///
+ UINT8 PrefixLength;
+} EFI_IP6_ROUTE_TABLE;
+
+///
+/// EFI_IP6_NEIGHBOR_STATE
+///
+typedef enum {
+ ///
+ /// Address resolution is being performed on this entry. Specially,
+ /// Neighbor Solicitation has been sent to the solicited-node
+ /// multicast address of the target, but corresponding Neighbor
+ /// Advertisement has not been received.
+ ///
+ EfiNeighborInComplete,
+ ///
+ /// Positive confirmation was received that the forward path to the
+ /// neighbor was functioning properly.
+ ///
+ EfiNeighborReachable,
+ ///
+ /// Reachable Time has elapsed since the last positive confirmation
+ /// was received. In this state, the forward path to the neighbor was
+ /// functioning properly.
+ ///
+ EfiNeighborStale,
+ ///
+ /// This state is an optimization that gives upper-layer protocols
+ /// additional time to provide reachability confirmation.
+ ///
+ EfiNeighborDelay,
+ ///
+ /// A reachability confirmation is actively sought by retransmitting
+ /// Neighbor Solicitations every RetransTimer milliseconds until a
+ /// reachability confirmation is received.
+ ///
+ EfiNeighborProbe
+} EFI_IP6_NEIGHBOR_STATE;
+
+///
+/// EFI_IP6_NEIGHBOR_CACHE
+/// is the entry structure that is used in neighbor cache. It records a set
+/// of entries about individual neighbors to which traffic has been sent recently.
+///
+typedef struct {
+ EFI_IPv6_ADDRESS Neighbor; ///< The on-link unicast/anycast IP address of the neighbor.
+ EFI_MAC_ADDRESS LinkAddress; ///< Link-layer address of the neighbor.
+ EFI_IP6_NEIGHBOR_STATE State; ///< State of this neighbor cache entry.
+} EFI_IP6_NEIGHBOR_CACHE;
+
+///
+/// EFI_IP6_ICMP_TYPE
+/// is used to describe those ICMP messages that are supported by this EFI
+/// IPv6 Protocol driver.
+///
+typedef struct {
+ UINT8 Type; ///< The type of ICMP message.
+ UINT8 Code; ///< The code of the ICMP message.
+} EFI_IP6_ICMP_TYPE;
+
+///
+/// EFI_IP6_MODE_DATA
+///
+typedef struct {
+ ///
+ /// Set to TRUE after this EFI IPv6 Protocol instance is started.
+ /// All other fields in this structure are undefined until this field is TRUE.
+ /// Set to FALSE when the EFI IPv6 Protocol instance is stopped.
+ ///
+ BOOLEAN IsStarted;
+ ///
+ /// The maximum packet size, in bytes, of the packet which the upper layer driver could feed.
+ ///
+ UINT32 MaxPacketSize;
+ ///
+ /// Current configuration settings. Undefined until IsStarted is TRUE.
+ ///
+ EFI_IP6_CONFIG_DATA ConfigData;
+ ///
+ /// Set to TRUE when the EFI IPv6 Protocol instance is configured.
+ /// The instance is configured when it has a station address and
+ /// corresponding prefix length.
+ /// Set to FALSE when the EFI IPv6 Protocol instance is not configured.
+ ///
+ BOOLEAN IsConfigured;
+ ///
+ /// Number of configured IPv6 addresses on this interface.
+ ///
+ UINT32 AddressCount;
+ ///
+ /// List of currently configured IPv6 addresses and corresponding
+ /// prefix lengths assigned to this interface. It is caller's
+ /// responsibility to free this buffer.
+ ///
+ EFI_IP6_ADDRESS_INFO *AddressList;
+ ///
+ /// Number of joined multicast groups. Undefined until
+ /// IsConfigured is TRUE.
+ ///
+ UINT32 GroupCount;
+ ///
+ /// List of joined multicast group addresses. It is caller's
+ /// responsibility to free this buffer. Undefined until
+ /// IsConfigured is TRUE.
+ ///
+ EFI_IPv6_ADDRESS *GroupTable;
+ ///
+ /// Number of entries in the routing table. Undefined until
+ /// IsConfigured is TRUE.
+ ///
+ UINT32 RouteCount;
+ ///
+ /// Routing table entries. It is caller's responsibility to free this buffer.
+ ///
+ EFI_IP6_ROUTE_TABLE *RouteTable;
+ ///
+ /// Number of entries in the neighbor cache. Undefined until
+ /// IsConfigured is TRUE.
+ ///
+ UINT32 NeighborCount;
+ ///
+ /// Neighbor cache entries. It is caller's responsibility to free this
+ /// buffer. Undefined until IsConfigured is TRUE.
+ ///
+ EFI_IP6_NEIGHBOR_CACHE *NeighborCache;
+ ///
+ /// Number of entries in the prefix table. Undefined until
+ /// IsConfigured is TRUE.
+ ///
+ UINT32 PrefixCount;
+ ///
+ /// On-link Prefix table entries. It is caller's responsibility to free this
+ /// buffer. Undefined until IsConfigured is TRUE.
+ ///
+ EFI_IP6_ADDRESS_INFO *PrefixTable;
+ ///
+ /// Number of entries in the supported ICMP types list.
+ ///
+ UINT32 IcmpTypeCount;
+ ///
+ /// Array of ICMP types and codes that are supported by this EFI
+ /// IPv6 Protocol driver. It is caller's responsibility to free this
+ /// buffer.
+ ///
+ EFI_IP6_ICMP_TYPE *IcmpTypeList;
+} EFI_IP6_MODE_DATA;
+
+///
+/// EFI_IP6_HEADER
+/// The fields in the IPv6 header structure are defined in the Internet
+/// Protocol version6 specification.
+///
+#pragma pack(1)
+typedef struct _EFI_IP6_HEADER {
+ UINT8 TrafficClassH : 4;
+ UINT8 Version : 4;
+ UINT8 FlowLabelH : 4;
+ UINT8 TrafficClassL : 4;
+ UINT16 FlowLabelL;
+ UINT16 PayloadLength;
+ UINT8 NextHeader;
+ UINT8 HopLimit;
+ EFI_IPv6_ADDRESS SourceAddress;
+ EFI_IPv6_ADDRESS DestinationAddress;
+} EFI_IP6_HEADER;
+#pragma pack()
+
+///
+/// EFI_IP6_FRAGMENT_DATA
+/// describes the location and length of the IPv6 packet
+/// fragment to transmit or that has been received.
+///
+typedef struct _EFI_IP6_FRAGMENT_DATA {
+ UINT32 FragmentLength; ///< Length of fragment data. This field may not be set to zero.
+ VOID *FragmentBuffer; ///< Pointer to fragment data. This field may not be set to NULL.
+} EFI_IP6_FRAGMENT_DATA;
+
+///
+/// EFI_IP6_RECEIVE_DATA
+///
+typedef struct _EFI_IP6_RECEIVE_DATA {
+ ///
+ /// Time when the EFI IPv6 Protocol driver accepted the packet.
+ /// Ignored if it is zero.
+ ///
+ EFI_TIME TimeStamp;
+ ///
+ /// After this event is signaled, the receive data structure is released
+ /// and must not be referenced.
+ ///
+ EFI_EVENT RecycleSignal;
+ ///
+ /// Length of the IPv6 packet headers, including both the IPv6
+ /// header and any extension headers.
+ ///
+ UINT32 HeaderLength;
+ ///
+ /// Pointer to the IPv6 packet header. If the IPv6 packet was
+ /// fragmented, this argument is a pointer to the header in the first
+ /// fragment.
+ ///
+ EFI_IP6_HEADER *Header;
+ ///
+ /// Sum of the lengths of IPv6 packet buffers in FragmentTable. May
+ /// be zero.
+ ///
+ UINT32 DataLength;
+ ///
+ /// Number of IPv6 payload fragments. May be zero.
+ ///
+ UINT32 FragmentCount;
+ ///
+ /// Array of payload fragment lengths and buffer pointers.
+ ///
+ EFI_IP6_FRAGMENT_DATA FragmentTable[1];
+} EFI_IP6_RECEIVE_DATA;
+
+///
+/// EFI_IP6_OVERRIDE_DATA
+/// The information and flags in the override data structure will override
+/// default parameters or settings for one Transmit() function call.
+///
+typedef struct _EFI_IP6_OVERRIDE_DATA {
+ UINT8 Protocol; ///< Protocol type override.
+ UINT8 HopLimit; ///< Hop-Limit override.
+ UINT32 FlowLabel; ///< Flow-Label override.
+} EFI_IP6_OVERRIDE_DATA;
+
+///
+/// EFI_IP6_TRANSMIT_DATA
+///
+typedef struct _EFI_IP6_TRANSMIT_DATA {
+ ///
+ /// The destination IPv6 address. If it is unspecified,
+ /// ConfigData.DestinationAddress will be used instead.
+ ///
+ EFI_IPv6_ADDRESS DestinationAddress;
+ ///
+ /// If not NULL, the IPv6 transmission control override data.
+ ///
+ EFI_IP6_OVERRIDE_DATA *OverrideData;
+ ///
+ /// Total length in byte of the IPv6 extension headers specified in
+ /// ExtHdrs.
+ ///
+ UINT32 ExtHdrsLength;
+ ///
+ /// Pointer to the IPv6 extension headers. The IP layer will append
+ /// the required extension headers if they are not specified by
+ /// ExtHdrs. Ignored if ExtHdrsLength is zero.
+ ///
+ VOID *ExtHdrs;
+ ///
+ /// The protocol of first extension header in ExtHdrs. Ignored if
+ /// ExtHdrsLength is zero.
+ ///
+ UINT8 NextHeader;
+ ///
+ /// Total length in bytes of the FragmentTable data to transmit.
+ ///
+ UINT32 DataLength;
+ ///
+ /// Number of entries in the fragment data table.
+ ///
+ UINT32 FragmentCount;
+ ///
+ /// Start of the fragment data table.
+ ///
+ EFI_IP6_FRAGMENT_DATA FragmentTable[1];
+} EFI_IP6_TRANSMIT_DATA;
+
+///
+/// EFI_IP6_COMPLETION_TOKEN
+/// structures are used for both transmit and receive operations.
+///
+typedef struct {
+ ///
+ /// This Event will be signaled after the Status field is updated by
+ /// the EFI IPv6 Protocol driver. The type of Event must be EFI_NOTIFY_SIGNAL.
+ ///
+ EFI_EVENT Event;
+ ///
+ /// Will be set to one of the following values:
+ /// - EFI_SUCCESS: The receive or transmit completed
+ /// successfully.
+ /// - EFI_ABORTED: The receive or transmit was aborted
+ /// - EFI_TIMEOUT: The transmit timeout expired.
+ /// - EFI_ICMP_ERROR: An ICMP error packet was received.
+ /// - EFI_DEVICE_ERROR: An unexpected system or network
+ /// error occurred.
+ /// - EFI_SECURITY_VIOLATION: The transmit or receive was
+ /// failed because of an IPsec policy check.
+ /// - EFI_NO_MEDIA: There was a media error.
+ ///
+ EFI_STATUS Status;
+ union {
+ ///
+ /// When the Token is used for receiving, RxData is a pointer to the EFI_IP6_RECEIVE_DATA.
+ ///
+ EFI_IP6_RECEIVE_DATA *RxData;
+ ///
+ /// When the Token is used for transmitting, TxData is a pointer to the EFI_IP6_TRANSMIT_DATA.
+ ///
+ EFI_IP6_TRANSMIT_DATA *TxData;
+ } Packet;
+} EFI_IP6_COMPLETION_TOKEN;
+
+/**
+ Gets the current operational settings for this instance of the EFI IPv6 Protocol driver.
+
+ The GetModeData() function returns the current operational mode data for this driver instance.
+ The data fields in EFI_IP6_MODE_DATA are read only. This function is used optionally to
+ retrieve the operational mode data of underlying networks or drivers..
+
+ @param[in] This Pointer to the EFI_IP6_PROTOCOL instance.
+ @param[out] Ip6ModeData Pointer to the EFI IPv6 Protocol mode data structure.
+ @param[out] MnpConfigData Pointer to the managed network configuration data structure.
+ @param[out] SnpModeData Pointer to the simple network mode data structure.
+
+ @retval EFI_SUCCESS The operation completed successfully.
+ @retval EFI_INVALID_PARAMETER This is NULL.
+ @retval EFI_OUT_OF_RESOURCES The required mode data could not be allocated.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_IP6_GET_MODE_DATA)(
+ IN EFI_IP6_PROTOCOL *This,
+ OUT EFI_IP6_MODE_DATA *Ip6ModeData OPTIONAL,
+ OUT EFI_MANAGED_NETWORK_CONFIG_DATA *MnpConfigData OPTIONAL,
+ OUT EFI_SIMPLE_NETWORK_MODE *SnpModeData OPTIONAL
+ );
+
+/**
+ Assigns an IPv6 address and subnet mask to this EFI IPv6 Protocol driver instance.
+
+ The Configure() function is used to set, change, or reset the operational parameters and filter
+ settings for this EFI IPv6 Protocol instance. Until these parameters have been set, no network traffic
+ can be sent or received by this instance. Once the parameters have been reset (by calling this
+ function with Ip6ConfigData set to NULL), no more traffic can be sent or received until these
+ parameters have been set again. Each EFI IPv6 Protocol instance can be started and stopped
+ independently of each other by enabling or disabling their receive filter settings with the
+ Configure() function.
+
+ If Ip6ConfigData.StationAddress is a valid non-zero IPv6 unicast address, it is required
+ to be one of the currently configured IPv6 addresses list in the EFI IPv6 drivers, or else
+ EFI_INVALID_PARAMETER will be returned. If Ip6ConfigData.StationAddress is
+ unspecified, the IPv6 driver will bind a source address according to the source address selection
+ algorithm. Clients could frequently call GetModeData() to check get currently configured IPv6
+ address list in the EFI IPv6 driver. If both Ip6ConfigData.StationAddress and
+ Ip6ConfigData.Destination are unspecified, when transmitting the packet afterwards, the
+ source address filled in each outgoing IPv6 packet is decided based on the destination of this packet. .
+
+ If operational parameters are reset or changed, any pending transmit and receive requests will be
+ cancelled. Their completion token status will be set to EFI_ABORTED and their events will be
+ signaled.
+
+ @param[in] This Pointer to the EFI_IP6_PROTOCOL instance.
+ @param[in] Ip6ConfigData Pointer to the EFI IPv6 Protocol configuration data structure.
+
+ @retval EFI_SUCCESS The driver instance was successfully opened.
+ @retval EFI_INVALID_PARAMETER One or more of the following conditions is TRUE:
+ - This is NULL.
+ - Ip6ConfigData.StationAddress is neither zero nor
+ a unicast IPv6 address.
+ - Ip6ConfigData.StationAddress is neither zero nor
+ one of the configured IP addresses in the EFI IPv6 driver.
+ - Ip6ConfigData.DefaultProtocol is illegal.
+ @retval EFI_OUT_OF_RESOURCES The EFI IPv6 Protocol driver instance data could not be allocated.
+ @retval EFI_NO_MAPPING The IPv6 driver was responsible for choosing a source address for
+ this instance, but no source address was available for use.
+ @retval EFI_ALREADY_STARTED The interface is already open and must be stopped before the IPv6
+ address or prefix length can be changed.
+ @retval EFI_DEVICE_ERROR An unexpected system or network error occurred. The EFI IPv6
+ Protocol driver instance is not opened.
+ @retval EFI_UNSUPPORTED Default protocol specified through
+ Ip6ConfigData.DefaulProtocol isn't supported.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_IP6_CONFIGURE)(
+ IN EFI_IP6_PROTOCOL *This,
+ IN EFI_IP6_CONFIG_DATA *Ip6ConfigData OPTIONAL
+ );
+
+/**
+ Joins and leaves multicast groups.
+
+ The Groups() function is used to join and leave multicast group sessions. Joining a group will
+ enable reception of matching multicast packets. Leaving a group will disable reception of matching
+ multicast packets. Source-Specific Multicast isn't required to be supported.
+
+ If JoinFlag is FALSE and GroupAddress is NULL, all joined groups will be left.
+
+ @param[in] This Pointer to the EFI_IP6_PROTOCOL instance.
+ @param[in] JoinFlag Set to TRUE to join the multicast group session and FALSE to leave.
+ @param[in] GroupAddress Pointer to the IPv6 multicast address.
+
+ @retval EFI_SUCCESS The operation completed successfully.
+ @retval EFI_INVALID_PARAMETER One or more of the following is TRUE:
+ - This is NULL.
+ - JoinFlag is TRUE and GroupAddress is NULL.
+ - GroupAddress is not NULL and *GroupAddress is
+ not a multicast IPv6 address.
+ - GroupAddress is not NULL and *GroupAddress is in the
+ range of SSM destination address.
+ @retval EFI_NOT_STARTED This instance has not been started.
+ @retval EFI_OUT_OF_RESOURCES System resources could not be allocated.
+ @retval EFI_UNSUPPORTED This EFI IPv6 Protocol implementation does not support multicast groups.
+ @retval EFI_ALREADY_STARTED The group address is already in the group table (when
+ JoinFlag is TRUE).
+ @retval EFI_NOT_FOUND The group address is not in the group table (when JoinFlag is FALSE).
+ @retval EFI_DEVICE_ERROR An unexpected system or network error occurred.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_IP6_GROUPS)(
+ IN EFI_IP6_PROTOCOL *This,
+ IN BOOLEAN JoinFlag,
+ IN EFI_IPv6_ADDRESS *GroupAddress OPTIONAL
+ );
+
+/**
+ Adds and deletes routing table entries.
+
+ The Routes() function adds a route to or deletes a route from the routing table.
+
+ Routes are determined by comparing the leftmost PrefixLength bits of Destination with
+ the destination IPv6 address arithmetically. The gateway address must be on the same subnet as the
+ configured station address.
+
+ The default route is added with Destination and PrefixLegth both set to all zeros. The
+ default route matches all destination IPv6 addresses that do not match any other routes.
+
+ All EFI IPv6 Protocol instances share a routing table.
+
+ @param[in] This Pointer to the EFI_IP6_PROTOCOL instance.
+ @param[in] DeleteRoute Set to TRUE to delete this route from the routing table. Set to
+ FALSE to add this route to the routing table. Destination,
+ PrefixLength and Gateway are used as the key to each
+ route entry.
+ @param[in] Destination The address prefix of the subnet that needs to be routed.
+ @param[in] PrefixLength The prefix length of Destination. Ignored if Destination
+ is NULL.
+ @param[in] GatewayAddress The unicast gateway IPv6 address for this route.
+
+ @retval EFI_SUCCESS The operation completed successfully.
+ @retval EFI_NOT_STARTED The driver instance has not been started.
+ @retval EFI_INVALID_PARAMETER One or more of the following conditions is TRUE:
+ - This is NULL.
+ - When DeleteRoute is TRUE, both Destination and
+ GatewayAddress are NULL.
+ - When DeleteRoute is FALSE, either Destination or
+ GatewayAddress is NULL.
+ - *GatewayAddress is not a valid unicast IPv6 address.
+ - *GatewayAddress is one of the local configured IPv6
+ addresses.
+ @retval EFI_OUT_OF_RESOURCES Could not add the entry to the routing table.
+ @retval EFI_NOT_FOUND This route is not in the routing table (when DeleteRoute is TRUE).
+ @retval EFI_ACCESS_DENIED The route is already defined in the routing table (when
+ DeleteRoute is FALSE).
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_IP6_ROUTES)(
+ IN EFI_IP6_PROTOCOL *This,
+ IN BOOLEAN DeleteRoute,
+ IN EFI_IPv6_ADDRESS *Destination OPTIONAL,
+ IN UINT8 PrefixLength,
+ IN EFI_IPv6_ADDRESS *GatewayAddress OPTIONAL
+ );
+
+/**
+ Add or delete Neighbor cache entries.
+
+ The Neighbors() function is used to add, update, or delete an entry from neighbor cache.
+ IPv6 neighbor cache entries are typically inserted and updated by the network protocol driver as
+ network traffic is processed. Most neighbor cache entries will time out and be deleted if the network
+ traffic stops. Neighbor cache entries that were inserted by Neighbors() may be static (will not
+ timeout) or dynamic (will time out).
+
+ The implementation should follow the neighbor cache timeout mechanism which is defined in
+ RFC4861. The default neighbor cache timeout value should be tuned for the expected network
+ environment
+
+ @param[in] This Pointer to the EFI_IP6_PROTOCOL instance.
+ @param[in] DeleteFlag Set to TRUE to delete the specified cache entry, set to FALSE to
+ add (or update, if it already exists and Override is TRUE) the
+ specified cache entry. TargetIp6Address is used as the key
+ to find the requested cache entry.
+ @param[in] TargetIp6Address Pointer to Target IPv6 address.
+ @param[in] TargetLinkAddress Pointer to link-layer address of the target. Ignored if NULL.
+ @param[in] Timeout Time in 100-ns units that this entry will remain in the neighbor
+ cache, it will be deleted after Timeout. A value of zero means that
+ the entry is permanent. A non-zero value means that the entry is
+ dynamic.
+ @param[in] Override If TRUE, the cached link-layer address of the matching entry will
+ be overridden and updated; if FALSE, EFI_ACCESS_DENIED
+ will be returned if a corresponding cache entry already existed.
+
+ @retval EFI_SUCCESS The data has been queued for transmission.
+ @retval EFI_NOT_STARTED This instance has not been started.
+ @retval EFI_INVALID_PARAMETER One or more of the following conditions is TRUE:
+ - This is NULL.
+ - TargetIpAddress is NULL.
+ - *TargetLinkAddress is invalid when not NULL.
+ - *TargetIpAddress is not a valid unicast IPv6 address.
+ - *TargetIpAddress is one of the local configured IPv6
+ addresses.
+ @retval EFI_OUT_OF_RESOURCES Could not add the entry to the neighbor cache.
+ @retval EFI_NOT_FOUND This entry is not in the neighbor cache (when DeleteFlag is
+ TRUE or when DeleteFlag is FALSE while
+ TargetLinkAddress is NULL.).
+ @retval EFI_ACCESS_DENIED The to-be-added entry is already defined in the neighbor cache,
+ and that entry is tagged as un-overridden (when DeleteFlag
+ is FALSE).
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_IP6_NEIGHBORS)(
+ IN EFI_IP6_PROTOCOL *This,
+ IN BOOLEAN DeleteFlag,
+ IN EFI_IPv6_ADDRESS *TargetIp6Address,
+ IN EFI_MAC_ADDRESS *TargetLinkAddress,
+ IN UINT32 Timeout,
+ IN BOOLEAN Override
+ );
+
+/**
+ Places outgoing data packets into the transmit queue.
+
+ The Transmit() function places a sending request in the transmit queue of this
+ EFI IPv6 Protocol instance. Whenever the packet in the token is sent out or some
+ errors occur, the event in the token will be signaled and the status is updated.
+
+ @param[in] This Pointer to the EFI_IP6_PROTOCOL instance.
+ @param[in] Token Pointer to the transmit token.
+
+ @retval EFI_SUCCESS The data has been queued for transmission.
+ @retval EFI_NOT_STARTED This instance has not been started.
+ @retval EFI_NO_MAPPING The IPv6 driver was responsible for choosing a source address for
+ this transmission, but no source address was available for use.
+ @retval EFI_INVALID_PARAMETER One or more of the following is TRUE:
+ - This is NULL.
+ - Token is NULL.
+ - Token.Event is NULL.
+ - Token.Packet.TxData is NULL.
+ - Token.Packet.ExtHdrsLength is not zero and Token.Packet.ExtHdrs is NULL.
+ - Token.Packet.FragmentCount is zero.
+ - One or more of the Token.Packet.TxData.FragmentTable[].FragmentLength fields is zero.
+ - One or more of the Token.Packet.TxData.FragmentTable[].FragmentBuffer fields is NULL.
+ - Token.Packet.TxData.DataLength is zero or not equal to the sum of fragment lengths.
+ - Token.Packet.TxData.DestinationAddress is non-zero when DestinationAddress is configured as
+ non-zero when doing Configure() for this EFI IPv6 protocol instance.
+ - Token.Packet.TxData.DestinationAddress is unspecified when DestinationAddress is unspecified
+ when doing Configure() for this EFI IPv6 protocol instance.
+ @retval EFI_ACCESS_DENIED The transmit completion token with the same Token.Event
+ was already in the transmit queue.
+ @retval EFI_NOT_READY The completion token could not be queued because the transmit
+ queue is full.
+ @retval EFI_NOT_FOUND Not route is found to destination address.
+ @retval EFI_OUT_OF_RESOURCES Could not queue the transmit data.
+ @retval EFI_BUFFER_TOO_SMALL Token.Packet.TxData.TotalDataLength is too
+ short to transmit.
+ @retval EFI_BAD_BUFFER_SIZE If Token.Packet.TxData.DataLength is beyond the
+ maximum that which can be described through the Fragment Offset
+ field in Fragment header when performing fragmentation.
+ @retval EFI_DEVICE_ERROR An unexpected system or network error occurred.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_IP6_TRANSMIT)(
+ IN EFI_IP6_PROTOCOL *This,
+ IN EFI_IP6_COMPLETION_TOKEN *Token
+ );
+
+/**
+ Places a receiving request into the receiving queue.
+
+ The Receive() function places a completion token into the receive packet queue.
+ This function is always asynchronous.
+
+ The Token.Event field in the completion token must be filled in by the caller
+ and cannot be NULL. When the receive operation completes, the EFI IPv6 Protocol
+ driver updates the Token.Status and Token.Packet.RxData fields and the Token.Event
+ is signaled.
+
+ @param[in] This Pointer to the EFI_IP6_PROTOCOL instance.
+ @param[in] Token Pointer to a token that is associated with the receive data descriptor.
+
+ @retval EFI_SUCCESS The receive completion token was cached.
+ @retval EFI_NOT_STARTED This EFI IPv6 Protocol instance has not been started.
+ @retval EFI_NO_MAPPING When IP6 driver responsible for binding source address to this instance,
+ while no source address is available for use.
+ @retval EFI_INVALID_PARAMETER One or more of the following conditions is TRUE:
+ - This is NULL.
+ - Token is NULL.
+ - Token.Event is NULL.
+ @retval EFI_OUT_OF_RESOURCES The receive completion token could not be queued due to a lack of system
+ resources (usually memory).
+ @retval EFI_DEVICE_ERROR An unexpected system or network error occurred.
+ The EFI IPv6 Protocol instance has been reset to startup defaults.
+ @retval EFI_ACCESS_DENIED The receive completion token with the same Token.Event was already
+ in the receive queue.
+ @retval EFI_NOT_READY The receive request could not be queued because the receive queue is full.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_IP6_RECEIVE)(
+ IN EFI_IP6_PROTOCOL *This,
+ IN EFI_IP6_COMPLETION_TOKEN *Token
+ );
+
+/**
+ Abort an asynchronous transmit or receive request.
+
+ The Cancel() function is used to abort a pending transmit or receive request.
+ If the token is in the transmit or receive request queues, after calling this
+ function, Token->Status will be set to EFI_ABORTED and then Token->Event will
+ be signaled. If the token is not in one of the queues, which usually means the
+ asynchronous operation has completed, this function will not signal the token
+ and EFI_NOT_FOUND is returned.
+
+ @param[in] This Pointer to the EFI_IP6_PROTOCOL instance.
+ @param[in] Token Pointer to a token that has been issued by
+ EFI_IP6_PROTOCOL.Transmit() or
+ EFI_IP6_PROTOCOL.Receive(). If NULL, all pending
+ tokens are aborted. Type EFI_IP6_COMPLETION_TOKEN is
+ defined in EFI_IP6_PROTOCOL.Transmit().
+
+ @retval EFI_SUCCESS The asynchronous I/O request was aborted and
+ Token->Event was signaled. When Token is NULL, all
+ pending requests were aborted and their events were signaled.
+ @retval EFI_INVALID_PARAMETER This is NULL.
+ @retval EFI_NOT_STARTED This instance has not been started.
+ @retval EFI_NOT_FOUND When Token is not NULL, the asynchronous I/O request was
+ not found in the transmit or receive queue. It has either completed
+ or was not issued by Transmit() and Receive().
+ @retval EFI_DEVICE_ERROR An unexpected system or network error occurred.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_IP6_CANCEL)(
+ IN EFI_IP6_PROTOCOL *This,
+ IN EFI_IP6_COMPLETION_TOKEN *Token OPTIONAL
+ );
+
+/**
+ Polls for incoming data packets and processes outgoing data packets.
+
+ The Poll() function polls for incoming data packets and processes outgoing data
+ packets. Network drivers and applications can call the EFI_IP6_PROTOCOL.Poll()
+ function to increase the rate that data packets are moved between the communications
+ device and the transmit and receive queues.
+
+ In some systems the periodic timer event may not poll the underlying communications
+ device fast enough to transmit and/or receive all data packets without missing
+ incoming packets or dropping outgoing packets. Drivers and applications that are
+ experiencing packet loss should try calling the EFI_IP6_PROTOCOL.Poll() function
+ more often.
+
+ @param[in] This Pointer to the EFI_IP6_PROTOCOL instance.
+
+ @retval EFI_SUCCESS Incoming or outgoing data was processed.
+ @retval EFI_NOT_STARTED This EFI IPv6 Protocol instance has not been started.
+ @retval EFI_INVALID_PARAMETER This is NULL.
+ @retval EFI_DEVICE_ERROR An unexpected system or network error occurred.
+ @retval EFI_NOT_READY No incoming or outgoing data is processed.
+ @retval EFI_TIMEOUT Data was dropped out of the transmit and/or receive queue.
+ Consider increasing the polling rate.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_IP6_POLL)(
+ IN EFI_IP6_PROTOCOL *This
+ );
+
+///
+/// The EFI IPv6 Protocol implements a simple packet-oriented interface that can be
+/// used by drivers, daemons, and applications to transmit and receive network packets.
+///
+struct _EFI_IP6_PROTOCOL {
+ EFI_IP6_GET_MODE_DATA GetModeData;
+ EFI_IP6_CONFIGURE Configure;
+ EFI_IP6_GROUPS Groups;
+ EFI_IP6_ROUTES Routes;
+ EFI_IP6_NEIGHBORS Neighbors;
+ EFI_IP6_TRANSMIT Transmit;
+ EFI_IP6_RECEIVE Receive;
+ EFI_IP6_CANCEL Cancel;
+ EFI_IP6_POLL Poll;
+};
+
+extern EFI_GUID gEfiIp6ServiceBindingProtocolGuid;
+extern EFI_GUID gEfiIp6ProtocolGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/Ip6Config.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/Ip6Config.h
new file mode 100644
index 0000000000..bfc3c41f20
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/Ip6Config.h
@@ -0,0 +1,367 @@
+/** @file
+ This file provides a definition of the EFI IPv6 Configuration
+ Protocol.
+
+Copyright (c) 2008 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __EFI_IP6CONFIG_PROTOCOL_H__
+#define __EFI_IP6CONFIG_PROTOCOL_H__
+
+#include
+
+#define EFI_IP6_CONFIG_PROTOCOL_GUID \
+ { \
+ 0x937fe521, 0x95ae, 0x4d1a, {0x89, 0x29, 0x48, 0xbc, 0xd9, 0x0a, 0xd3, 0x1a } \
+ }
+
+typedef struct _EFI_IP6_CONFIG_PROTOCOL EFI_IP6_CONFIG_PROTOCOL;
+
+///
+/// EFI_IP6_CONFIG_DATA_TYPE
+///
+typedef enum {
+ ///
+ /// The interface information of the communication
+ /// device this EFI IPv6 Configuration Protocol instance manages.
+ /// This type of data is read only.The corresponding Data is of type
+ /// EFI_IP6_CONFIG_INTERFACE_INFO.
+ ///
+ Ip6ConfigDataTypeInterfaceInfo,
+ ///
+ /// The alternative interface ID for the
+ /// communication device this EFI IPv6 Configuration Protocol
+ /// instance manages if the link local IPv6 address generated from
+ /// the interfaced ID based on the default source the EFI IPv6
+ /// Protocol uses is a duplicate address. The length of the interface
+ /// ID is 64 bit. The corresponding Data is of type
+ /// EFI_IP6_CONFIG_INTERFACE_ID.
+ ///
+ Ip6ConfigDataTypeAltInterfaceId,
+ ///
+ /// The general configuration policy for the EFI IPv6 network
+ /// stack running on the communication device this EFI IPv6
+ /// Configuration Protocol instance manages. The policy will affect
+ /// other configuration settings. The corresponding Data is of type
+ /// EFI_IP6_CONFIG_POLICY.
+ ///
+ Ip6ConfigDataTypePolicy,
+ ///
+ /// The number of consecutive
+ /// Neighbor Solicitation messages sent while performing Duplicate
+ /// Address Detection on a tentative address. A value of zero
+ /// indicates that Duplicate Address Detection will not be performed
+ /// on tentative addresses. The corresponding Data is of type
+ /// EFI_IP6_CONFIG_DUP_ADDR_DETECT_TRANSMITS.
+ ///
+ Ip6ConfigDataTypeDupAddrDetectTransmits,
+ ///
+ /// The station addresses set manually for the EFI
+ /// IPv6 network stack. It is only configurable when the policy is
+ /// Ip6ConfigPolicyManual. The corresponding Data is a
+ /// pointer to an array of EFI_IPv6_ADDRESS instances. When
+ /// DataSize is 0 and Data is NULL, the existing configuration
+ /// is cleared from the EFI IPv6 Configuration Protocol instance.
+ ///
+ Ip6ConfigDataTypeManualAddress,
+ ///
+ /// The gateway addresses set manually for the EFI IPv6
+ /// network stack running on the communication device this EFI
+ /// IPv6 Configuration Protocol manages. It is not configurable when
+ /// the policy is Ip6ConfigPolicyAutomatic. The gateway
+ /// addresses must be unicast IPv6 addresses. The corresponding
+ /// Data is a pointer to an array of EFI_IPv6_ADDRESS instances.
+ /// When DataSize is 0 and Data is NULL, the existing configuration
+ /// is cleared from the EFI IPv6 Configuration Protocol instance.
+ ///
+ Ip6ConfigDataTypeGateway,
+ ///
+ /// The DNS server list for the EFI IPv6 network stack
+ /// running on the communication device this EFI IPv6
+ /// Configuration Protocol manages. It is not configurable when the
+ /// policy is Ip6ConfigPolicyAutomatic.The DNS server
+ /// addresses must be unicast IPv6 addresses. The corresponding
+ /// Data is a pointer to an array of EFI_IPv6_ADDRESS instances.
+ /// When DataSize is 0 and Data is NULL, the existing configuration
+ /// is cleared from the EFI IPv6 Configuration Protocol instance.
+ ///
+ Ip6ConfigDataTypeDnsServer,
+ ///
+ /// The number of this enumeration memebers.
+ ///
+ Ip6ConfigDataTypeMaximum
+} EFI_IP6_CONFIG_DATA_TYPE;
+
+///
+/// EFI_IP6_CONFIG_INTERFACE_INFO
+/// describes the operational state of the interface this
+/// EFI IPv6 Configuration Protocol instance manages.
+///
+typedef struct {
+ ///
+ /// The name of the interface. It is a NULL-terminated string.
+ ///
+ CHAR16 Name[32];
+ ///
+ /// The interface type of the network interface.
+ ///
+ UINT8 IfType;
+ ///
+ /// The size, in bytes, of the network interface's hardware address.
+ ///
+ UINT32 HwAddressSize;
+ ///
+ /// The hardware address for the network interface.
+ ///
+ EFI_MAC_ADDRESS HwAddress;
+ ///
+ /// Number of EFI_IP6_ADDRESS_INFO structures pointed to by AddressInfo.
+ ///
+ UINT32 AddressInfoCount;
+ ///
+ /// Pointer to an array of EFI_IP6_ADDRESS_INFO instances
+ /// which contain the local IPv6 addresses and the corresponding
+ /// prefix length information. Set to NULL if AddressInfoCount
+ /// is zero.
+ ///
+ EFI_IP6_ADDRESS_INFO *AddressInfo;
+ ///
+ /// Number of route table entries in the following RouteTable.
+ ///
+ UINT32 RouteCount;
+ ///
+ /// The route table of the IPv6 network stack runs on this interface.
+ /// Set to NULL if RouteCount is zero.
+ ///
+ EFI_IP6_ROUTE_TABLE *RouteTable;
+} EFI_IP6_CONFIG_INTERFACE_INFO;
+
+///
+/// EFI_IP6_CONFIG_INTERFACE_ID
+/// describes the 64-bit interface ID.
+///
+typedef struct {
+ UINT8 Id[8];
+} EFI_IP6_CONFIG_INTERFACE_ID;
+
+///
+/// EFI_IP6_CONFIG_POLICY
+/// defines the general configuration policy the EFI IPv6
+/// Configuration Protocol supports.
+///
+typedef enum {
+ ///
+ /// Under this policy, the IpI6ConfigDataTypeManualAddress,
+ /// Ip6ConfigDataTypeGateway and Ip6ConfigDataTypeDnsServer
+ /// configuration data are required to be set manually.
+ /// The EFI IPv6 Protocol will get all required configuration
+ /// such as address, prefix and gateway settings from the EFI
+ /// IPv6 Configuration protocol.
+ ///
+ Ip6ConfigPolicyManual,
+ ///
+ /// Under this policy, the IpI6ConfigDataTypeManualAddress,
+ /// Ip6ConfigDataTypeGateway and Ip6ConfigDataTypeDnsServer
+ /// configuration data are not allowed to set via SetData().
+ /// All of these configurations are retrieved from some auto
+ /// configuration mechanism.
+ /// The EFI IPv6 Protocol will use the IPv6 stateless address
+ /// autoconfiguration mechanism and/or the IPv6 stateful address
+ /// autoconfiguration mechanism described in the related RFCs to
+ /// get address and other configuration information
+ ///
+ Ip6ConfigPolicyAutomatic
+} EFI_IP6_CONFIG_POLICY;
+
+///
+/// EFI_IP6_CONFIG_DUP_ADDR_DETECT_TRANSMITS
+/// describes the number of consecutive Neighbor Solicitation messages sent
+/// while performing Duplicate Address Detection on a tentative address.
+/// The default value for a newly detected communication device is 1.
+///
+typedef struct {
+ UINT32 DupAddrDetectTransmits; ///< The number of consecutive Neighbor Solicitation messages sent.
+} EFI_IP6_CONFIG_DUP_ADDR_DETECT_TRANSMITS;
+
+///
+/// EFI_IP6_CONFIG_MANUAL_ADDRESS
+/// is used to set the station address information for the EFI IPv6 network
+/// stack manually when the policy is Ip6ConfigPolicyManual.
+///
+typedef struct {
+ EFI_IPv6_ADDRESS Address; ///< The IPv6 unicast address.
+ BOOLEAN IsAnycast; ///< Set to TRUE if Address is anycast.
+ UINT8 PrefixLength; ///< The length, in bits, of the prefix associated with this Address.
+} EFI_IP6_CONFIG_MANUAL_ADDRESS;
+
+/**
+ Set the configuration for the EFI IPv6 network stack running on the communication
+ device this EFI IPv6 Configuration Protocol instance manages.
+
+ This function is used to set the configuration data of type DataType for the EFI
+ IPv6 network stack running on the communication device this EFI IPv6 Configuration
+ Protocol instance manages.
+
+ The DataSize is used to calculate the count of structure instances in the Data for
+ some DataType that multiple structure instances are allowed.
+
+ This function is always non-blocking. When setting some type of configuration data,
+ an asynchronous process is invoked to check the correctness of the data, such as
+ doing Duplicate Address Detection on the manually set local IPv6 addresses.
+ EFI_NOT_READY is returned immediately to indicate that such an asynchronous process
+ is invoked and the process is not finished yet. The caller willing to get the result
+ of the asynchronous process is required to call RegisterDataNotify() to register an
+ event on the specified configuration data. Once the event is signaled, the caller
+ can call GetData() to get back the configuration data in order to know the result.
+ For other types of configuration data that do not require an asynchronous configuration
+ process, the result of the operation is immediately returned.
+
+ @param[in] This Pointer to the EFI_IP6_CONFIG_PROTOCOL instance.
+ @param[in] DataType The type of data to set.
+ @param[in] DataSize Size of the buffer pointed to by Data in bytes.
+ @param[in] Data The data buffer to set. The type of the data buffer is
+ associated with the DataType.
+
+ @retval EFI_SUCCESS The specified configuration data for the EFI IPv6
+ network stack is set successfully.
+ @retval EFI_INVALID_PARAMETER One or more of the following are TRUE:
+ - This is NULL.
+ - One or more fields in Data and DataSize do not match the
+ requirement of the data type indicated by DataType.
+ @retval EFI_WRITE_PROTECTED The specified configuration data is read-only or the specified
+ configuration data can not be set under the current policy
+ @retval EFI_ACCESS_DENIED Another set operation on the specified configuration
+ data is already in process.
+ @retval EFI_NOT_READY An asynchronous process is invoked to set the specified
+ configuration data and the process is not finished yet.
+ @retval EFI_BAD_BUFFER_SIZE The DataSize does not match the size of the type
+ indicated by DataType.
+ @retval EFI_UNSUPPORTED This DataType is not supported.
+ @retval EFI_OUT_OF_RESOURCES Required system resources could not be allocated.
+ @retval EFI_DEVICE_ERROR An unexpected system error or network error occurred.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_IP6_CONFIG_SET_DATA)(
+ IN EFI_IP6_CONFIG_PROTOCOL *This,
+ IN EFI_IP6_CONFIG_DATA_TYPE DataType,
+ IN UINTN DataSize,
+ IN VOID *Data
+ );
+
+/**
+ Get the configuration data for the EFI IPv6 network stack running on the communication
+ device this EFI IPv6 Configuration Protocol instance manages.
+
+ This function returns the configuration data of type DataType for the EFI IPv6 network
+ stack running on the communication device this EFI IPv6 Configuration Protocol instance
+ manages.
+
+ The caller is responsible for allocating the buffer used to return the specified
+ configuration data and the required size will be returned to the caller if the size of
+ the buffer is too small.
+
+ EFI_NOT_READY is returned if the specified configuration data is not ready due to an
+ already in progress asynchronous configuration process. The caller can call RegisterDataNotify()
+ to register an event on the specified configuration data. Once the asynchronous configuration
+ process is finished, the event will be signaled and a subsequent GetData() call will return
+ the specified configuration data.
+
+ @param[in] This Pointer to the EFI_IP6_CONFIG_PROTOCOL instance.
+ @param[in] DataType The type of data to get.
+ @param[in,out] DataSize On input, in bytes, the size of Data. On output, in bytes, the
+ size of buffer required to store the specified configuration data.
+ @param[in] Data The data buffer in which the configuration data is returned. The
+ type of the data buffer is associated with the DataType.
+
+ @retval EFI_SUCCESS The specified configuration data is got successfully.
+ @retval EFI_INVALID_PARAMETER One or more of the followings are TRUE:
+ - This is NULL.
+ - DataSize is NULL.
+ - Data is NULL if *DataSize is not zero.
+ @retval EFI_BUFFER_TOO_SMALL The size of Data is too small for the specified configuration data
+ and the required size is returned in DataSize.
+ @retval EFI_NOT_READY The specified configuration data is not ready due to an already in
+ progress asynchronous configuration process.
+ @retval EFI_NOT_FOUND The specified configuration data is not found.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_IP6_CONFIG_GET_DATA)(
+ IN EFI_IP6_CONFIG_PROTOCOL *This,
+ IN EFI_IP6_CONFIG_DATA_TYPE DataType,
+ IN OUT UINTN *DataSize,
+ IN VOID *Data OPTIONAL
+ );
+
+/**
+ Register an event that is to be signaled whenever a configuration process on the specified
+ configuration data is done.
+
+ This function registers an event that is to be signaled whenever a configuration process
+ on the specified configuration data is done. An event can be registered for different DataType
+ simultaneously and the caller is responsible for determining which type of configuration data
+ causes the signaling of the event in such case.
+
+ @param[in] This Pointer to the EFI_IP6_CONFIG_PROTOCOL instance.
+ @param[in] DataType The type of data to unregister the event for.
+ @param[in] Event The event to register.
+
+ @retval EFI_SUCCESS The notification event for the specified configuration data is
+ registered.
+ @retval EFI_INVALID_PARAMETER This is NULL or Event is NULL.
+ @retval EFI_UNSUPPORTED The configuration data type specified by DataType is not
+ supported.
+ @retval EFI_OUT_OF_RESOURCES Required system resources could not be allocated.
+ @retval EFI_ACCESS_DENIED The Event is already registered for the DataType.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_IP6_CONFIG_REGISTER_NOTIFY)(
+ IN EFI_IP6_CONFIG_PROTOCOL *This,
+ IN EFI_IP6_CONFIG_DATA_TYPE DataType,
+ IN EFI_EVENT Event
+ );
+
+/**
+ Remove a previously registered event for the specified configuration data.
+
+ This function removes a previously registered event for the specified configuration data.
+
+ @param[in] This Pointer to the EFI_IP6_CONFIG_PROTOCOL instance.
+ @param[in] DataType The type of data to remove the previously registered event for.
+ @param[in] Event The event to unregister.
+
+ @retval EFI_SUCCESS The event registered for the specified configuration data is removed.
+ @retval EFI_INVALID_PARAMETER This is NULL or Event is NULL.
+ @retval EFI_NOT_FOUND The Event has not been registered for the specified
+ DataType.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_IP6_CONFIG_UNREGISTER_NOTIFY)(
+ IN EFI_IP6_CONFIG_PROTOCOL *This,
+ IN EFI_IP6_CONFIG_DATA_TYPE DataType,
+ IN EFI_EVENT Event
+ );
+
+///
+/// The EFI_IP6_CONFIG_PROTOCOL provides the mechanism to set and get various
+/// types of configurations for the EFI IPv6 network stack.
+///
+struct _EFI_IP6_CONFIG_PROTOCOL {
+ EFI_IP6_CONFIG_SET_DATA SetData;
+ EFI_IP6_CONFIG_GET_DATA GetData;
+ EFI_IP6_CONFIG_REGISTER_NOTIFY RegisterDataNotify;
+ EFI_IP6_CONFIG_UNREGISTER_NOTIFY UnregisterDataNotify;
+};
+
+extern EFI_GUID gEfiIp6ConfigProtocolGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/IpSec.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/IpSec.h
new file mode 100644
index 0000000000..4552bfc484
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/IpSec.h
@@ -0,0 +1,217 @@
+/** @file
+ EFI IPSEC Protocol Definition
+ The EFI_IPSEC_PROTOCOL is used to abstract the ability to deal with the individual
+ packets sent and received by the host and provide packet-level security for IP
+ datagram.
+ The EFI_IPSEC2_PROTOCOL is used to abstract the ability to deal with the individual
+ packets sent and received by the host and provide packet-level security for IP
+ datagram. In addition, it supports the Option (extension header) processing in
+ IPsec which doesn't support in EFI_IPSEC_PROTOCOL. It is also recommended to
+ use EFI_IPSEC2_PROTOCOL instead of EFI_IPSEC_PROTOCOL especially for IPsec Tunnel
+ Mode.
+
+ Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Revision Reference:
+ The EFI_IPSEC2_PROTOCOL is introduced in UEFI Specification 2.3D.
+
+**/
+
+#ifndef __EFI_IPSEC_PROTOCOL_H__
+#define __EFI_IPSEC_PROTOCOL_H__
+
+#include
+
+#define EFI_IPSEC_PROTOCOL_GUID \
+ { \
+ 0xdfb386f7, 0xe100, 0x43ad, {0x9c, 0x9a, 0xed, 0x90, 0xd0, 0x8a, 0x5e, 0x12 } \
+ }
+
+#define EFI_IPSEC2_PROTOCOL_GUID \
+ { \
+ 0xa3979e64, 0xace8, 0x4ddc, {0xbc, 0x7, 0x4d, 0x66, 0xb8, 0xfd, 0x9, 0x77 } \
+ }
+
+typedef struct _EFI_IPSEC_PROTOCOL EFI_IPSEC_PROTOCOL;
+typedef struct _EFI_IPSEC2_PROTOCOL EFI_IPSEC2_PROTOCOL;
+
+///
+/// EFI_IPSEC_FRAGMENT_DATA
+/// defines the instances of packet fragments.
+///
+typedef struct _EFI_IPSEC_FRAGMENT_DATA {
+ UINT32 FragmentLength;
+ VOID *FragmentBuffer;
+} EFI_IPSEC_FRAGMENT_DATA;
+
+/**
+ Handles IPsec packet processing for inbound and outbound IP packets.
+
+ The EFI_IPSEC_PROCESS process routine handles each inbound or outbound packet.
+ The behavior is that it can perform one of the following actions:
+ bypass the packet, discard the packet, or protect the packet.
+
+ @param[in] This Pointer to the EFI_IPSEC_PROTOCOL instance.
+ @param[in] NicHandle Instance of the network interface.
+ @param[in] IpVer IPV4 or IPV6.
+ @param[in, out] IpHead Pointer to the IP Header.
+ @param[in] LastHead The protocol of the next layer to be processed by IPsec.
+ @param[in] OptionsBuffer Pointer to the options buffer.
+ @param[in] OptionsLength Length of the options buffer.
+ @param[in, out] FragmentTable Pointer to a list of fragments.
+ @param[in] FragmentCount Number of fragments.
+ @param[in] TrafficDirection Traffic direction.
+ @param[out] RecycleSignal Event for recycling of resources.
+
+ @retval EFI_SUCCESS The packet was bypassed and all buffers remain the same.
+ @retval EFI_SUCCESS The packet was protected.
+ @retval EFI_ACCESS_DENIED The packet was discarded.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_IPSEC_PROCESS)(
+ IN EFI_IPSEC_PROTOCOL *This,
+ IN EFI_HANDLE NicHandle,
+ IN UINT8 IpVer,
+ IN OUT VOID *IpHead,
+ IN UINT8 *LastHead,
+ IN VOID *OptionsBuffer,
+ IN UINT32 OptionsLength,
+ IN OUT EFI_IPSEC_FRAGMENT_DATA **FragmentTable,
+ IN UINT32 *FragmentCount,
+ IN EFI_IPSEC_TRAFFIC_DIR TrafficDirection,
+ OUT EFI_EVENT *RecycleSignal
+ );
+
+///
+/// EFI_IPSEC_PROTOCOL
+/// provides the ability for securing IP communications by authenticating
+/// and/or encrypting each IP packet in a data stream.
+// EFI_IPSEC_PROTOCOL can be consumed by both the IPv4 and IPv6 stack.
+// A user can employ this protocol for IPsec package handling in both IPv4
+// and IPv6 environment.
+///
+struct _EFI_IPSEC_PROTOCOL {
+ EFI_IPSEC_PROCESS Process; ///< Handle the IPsec message.
+ EFI_EVENT DisabledEvent; ///< Event signaled when the interface is disabled.
+ BOOLEAN DisabledFlag; ///< State of the interface.
+};
+
+/**
+ Handles IPsec processing for both inbound and outbound IP packets. Compare with
+ Process() in EFI_IPSEC_PROTOCOL, this interface has the capability to process
+ Option(Extension Header).
+
+ The EFI_IPSEC2_PROCESS process routine handles each inbound or outbound packet.
+ The behavior is that it can perform one of the following actions:
+ bypass the packet, discard the packet, or protect the packet.
+
+ @param[in] This Pointer to the EFI_IPSEC2_PROTOCOL instance.
+ @param[in] NicHandle Instance of the network interface.
+ @param[in] IpVer IP version.IPv4 or IPv6.
+ @param[in, out] IpHead Pointer to the IP Header it is either
+ the EFI_IP4_HEADER or EFI_IP6_HEADER.
+ On input, it contains the IP header.
+ On output, 1) in tunnel mode and the
+ traffic direction is inbound, the buffer
+ will be reset to zero by IPsec; 2) in
+ tunnel mode and the traffic direction
+ is outbound, the buffer will reset to
+ be the tunnel IP header.3) in transport
+ mode, the related fielders (like payload
+ length, Next header) in IP header will
+ be modified according to the condition.
+ @param[in, out] LastHead For IP4, it is the next protocol in IP
+ header. For IP6 it is the Next Header
+ of the last extension header.
+ @param[in, out] OptionsBuffer On input, it contains the options
+ (extensions header) to be processed by
+ IPsec. On output, 1) in tunnel mode and
+ the traffic direction is outbound, it
+ will be set to NULL, and that means this
+ contents was wrapped after inner header
+ and should not be concatenated after
+ tunnel header again; 2) in transport
+ mode and the traffic direction is inbound,
+ if there are IP options (extension headers)
+ protected by IPsec, IPsec will concatenate
+ the those options after the input options
+ (extension headers); 3) on other situations,
+ the output of contents of OptionsBuffer
+ might be same with input's. The caller
+ should take the responsibility to free
+ the buffer both on input and on output.
+ @param[in, out] OptionsLength On input, the input length of the options
+ buffer. On output, the output length of
+ the options buffer.
+ @param[in, out] FragmentTable Pointer to a list of fragments. On input,
+ these fragments contain the IP payload.
+ On output, 1) in tunnel mode and the traffic
+ direction is inbound, the fragments contain
+ the whole IP payload which is from the
+ IP inner header to the last byte of the
+ packet; 2) in tunnel mode and the traffic
+ direction is the outbound, the fragments
+ contains the whole encapsulated payload
+ which encapsulates the whole IP payload
+ between the encapsulated header and
+ encapsulated trailer fields. 3) in transport
+ mode and the traffic direction is inbound,
+ the fragments contains the IP payload
+ which is from the next layer protocol to
+ the last byte of the packet; 4) in transport
+ mode and the traffic direction is outbound,
+ the fragments contains the whole encapsulated
+ payload which encapsulates the next layer
+ protocol information between the encapsulated
+ header and encapsulated trailer fields.
+ @param[in, out] FragmentCount Number of fragments.
+ @param[in] TrafficDirection Traffic direction.
+ @param[out] RecycleSignal Event for recycling of resources.
+
+ @retval EFI_SUCCESS The packet was processed by IPsec successfully.
+ @retval EFI_ACCESS_DENIED The packet was discarded.
+ @retval EFI_NOT_READY The IKE negotiation is invoked and the packet
+ was discarded.
+ @retval EFI_INVALID_PARAMETER One or more of following are TRUE:
+ If OptionsBuffer is NULL;
+ If OptionsLength is NULL;
+ If FragmentTable is NULL;
+ If FragmentCount is NULL.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_IPSEC_PROCESSEXT)(
+ IN EFI_IPSEC2_PROTOCOL *This,
+ IN EFI_HANDLE NicHandle,
+ IN UINT8 IpVer,
+ IN OUT VOID *IpHead,
+ IN OUT UINT8 *LastHead,
+ IN OUT VOID **OptionsBuffer,
+ IN OUT UINT32 *OptionsLength,
+ IN OUT EFI_IPSEC_FRAGMENT_DATA **FragmentTable,
+ IN OUT UINT32 *FragmentCount,
+ IN EFI_IPSEC_TRAFFIC_DIR TrafficDirection,
+ OUT EFI_EVENT *RecycleSignal
+ );
+
+///
+/// EFI_IPSEC2_PROTOCOL
+/// supports the Option (extension header) processing in IPsec which doesn't support
+/// in EFI_IPSEC_PROTOCOL. It is also recommended to use EFI_IPSEC2_PROTOCOL instead
+/// of EFI_IPSEC_PROTOCOL especially for IPsec Tunnel Mode.
+/// provides the ability for securing IP communications by authenticating and/or
+/// encrypting each IP packet in a data stream.
+///
+struct _EFI_IPSEC2_PROTOCOL {
+ EFI_IPSEC_PROCESSEXT ProcessExt;
+ EFI_EVENT DisabledEvent;
+ BOOLEAN DisabledFlag;
+};
+
+extern EFI_GUID gEfiIpSecProtocolGuid;
+extern EFI_GUID gEfiIpSec2ProtocolGuid;
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/IpSecConfig.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/IpSecConfig.h
new file mode 100644
index 0000000000..d11bf7294d
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/IpSecConfig.h
@@ -0,0 +1,796 @@
+/** @file
+ EFI IPsec Configuration Protocol Definition
+ The EFI_IPSEC_CONFIG_PROTOCOL provides the mechanism to set and retrieve security and
+ policy related information for the EFI IPsec protocol driver.
+
+ Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Revision Reference:
+ This Protocol is introduced in UEFI Specification 2.2
+
+**/
+
+#ifndef __EFI_IPSE_CCONFIG_PROTOCOL_H__
+#define __EFI_IPSE_CCONFIG_PROTOCOL_H__
+
+#define EFI_IPSEC_CONFIG_PROTOCOL_GUID \
+ { \
+ 0xce5e5929, 0xc7a3, 0x4602, {0xad, 0x9e, 0xc9, 0xda, 0xf9, 0x4e, 0xbf, 0xcf } \
+ }
+
+typedef struct _EFI_IPSEC_CONFIG_PROTOCOL EFI_IPSEC_CONFIG_PROTOCOL;
+
+///
+/// EFI_IPSEC_CONFIG_DATA_TYPE
+///
+typedef enum {
+ ///
+ /// The IPsec Security Policy Database (aka SPD) setting. In IPsec,
+ /// an essential element of Security Association (SA) processing is
+ /// underlying SPD that specifies what services are to be offered to
+ /// IP datagram and in what fashion. The SPD must be consulted
+ /// during the processing of all traffic (inbound and outbound),
+ /// including traffic not protected by IPsec, that traverses the IPsec
+ /// boundary. With this DataType, SetData() function is to set
+ /// the SPD entry information, which may add one new entry, delete
+ /// one existed entry or flush the whole database according to the
+ /// parameter values. The corresponding Data is of type
+ /// EFI_IPSEC_SPD_DATA
+ ///
+ IPsecConfigDataTypeSpd,
+ ///
+ /// The IPsec Security Association Database (aka SAD) setting. A
+ /// SA is a simplex connection that affords security services to the
+ /// traffic carried by it. Security services are afforded to an SA by the
+ /// use of AH, or ESP, but not both. The corresponding Data is of
+ /// type EFI_IPSEC_SAD_DATA.
+ ///
+ IPsecConfigDataTypeSad,
+ ///
+ /// The IPsec Peer Authorization Database (aka PAD) setting, which
+ /// provides the link between the SPD and a security association
+ /// management protocol. The PAD entry specifies the
+ /// authentication protocol (e.g. IKEv1, IKEv2) method used and the
+ /// authentication data. The corresponding Data is of type
+ /// EFI_IPSEC_PAD_DATA.
+ ///
+ IPsecConfigDataTypePad,
+ IPsecConfigDataTypeMaximum
+} EFI_IPSEC_CONFIG_DATA_TYPE;
+
+///
+/// EFI_IP_ADDRESS_INFO
+///
+typedef struct _EFI_IP_ADDRESS_INFO {
+ EFI_IP_ADDRESS Address; ///< The IPv4 or IPv6 address
+ UINT8 PrefixLength; ///< The length of the prefix associated with the Address.
+} EFI_IP_ADDRESS_INFO;
+
+///
+/// EFI_IPSEC_SPD_SELECTOR
+///
+typedef struct _EFI_IPSEC_SPD_SELECTOR {
+ ///
+ /// Specifies the actual number of entries in LocalAddress.
+ ///
+ UINT32 LocalAddressCount;
+ ///
+ /// A list of ranges of IPv4 or IPv6 addresses, which refers to the
+ /// addresses being protected by IPsec policy.
+ ///
+ EFI_IP_ADDRESS_INFO *LocalAddress;
+ ///
+ /// Specifies the actual number of entries in RemoteAddress.
+ ///
+ UINT32 RemoteAddressCount;
+ ///
+ /// A list of ranges of IPv4 or IPv6 addresses, which are peer entities
+ /// to LocalAddress.
+ ///
+ EFI_IP_ADDRESS_INFO *RemoteAddress;
+ ///
+ /// Next layer protocol. Obtained from the IPv4 Protocol or the IPv6
+ /// Next Header fields. The next layer protocol is whatever comes
+ /// after any IP extension headers that are present. A zero value is a
+ /// wildcard that matches any value in NextLayerProtocol field.
+ ///
+ UINT16 NextLayerProtocol;
+ ///
+ /// Local Port if the Next Layer Protocol uses two ports (as do TCP,
+ /// UDP, and others). A zero value is a wildcard that matches any
+ /// value in LocalPort field.
+ ///
+ UINT16 LocalPort;
+ ///
+ /// A designed port range size. The start port is LocalPort, and
+ /// the total number of ports is described by LocalPortRange.
+ /// This field is ignored if NextLayerProtocol does not use
+ /// ports.
+ ///
+ UINT16 LocalPortRange;
+ ///
+ /// Remote Port if the Next Layer Protocol uses two ports. A zero
+ /// value is a wildcard that matches any value in RemotePort field.
+ ///
+ UINT16 RemotePort;
+ ///
+ /// A designed port range size. The start port is RemotePort, and
+ /// the total number of ports is described by RemotePortRange.
+ /// This field is ignored if NextLayerProtocol does not use ports.
+ ///
+ UINT16 RemotePortRange;
+} EFI_IPSEC_SPD_SELECTOR;
+
+///
+/// EFI_IPSEC_TRAFFIC_DIR
+/// represents the directionality in an SPD entry.
+///
+typedef enum {
+ ///
+ /// The EfiIPsecInBound refers to traffic entering an IPsec implementation via
+ /// the unprotected interface or emitted by the implementation on the unprotected
+ /// side of the boundary and directed towards the protected interface.
+ ///
+ EfiIPsecInBound,
+ ///
+ /// The EfiIPsecOutBound refers to traffic entering the implementation via
+ /// the protected interface, or emitted by the implementation on the protected side
+ /// of the boundary and directed toward the unprotected interface.
+ ///
+ EfiIPsecOutBound
+} EFI_IPSEC_TRAFFIC_DIR;
+
+///
+/// EFI_IPSEC_ACTION
+/// represents three possible processing choices.
+///
+typedef enum {
+ ///
+ /// Refers to traffic that is not allowed to traverse the IPsec boundary.
+ ///
+ EfiIPsecActionDiscard,
+ ///
+ /// Refers to traffic that is allowed to cross the IPsec boundary
+ /// without protection.
+ ///
+ EfiIPsecActionBypass,
+ ///
+ /// Refers to traffic that is afforded IPsec protection, and for such
+ /// traffic the SPD must specify the security protocols to be
+ /// employed, their mode, security service options, and the
+ /// cryptographic algorithms to be used.
+ ///
+ EfiIPsecActionProtect
+} EFI_IPSEC_ACTION;
+
+///
+/// EFI_IPSEC_SA_LIFETIME
+/// defines the lifetime of an SA, which represents when a SA must be
+/// replaced or terminated. A value of all 0 for each field removes
+/// the limitation of a SA lifetime.
+///
+typedef struct _EFI_IPSEC_SA_LIFETIME {
+ ///
+ /// The number of bytes to which the IPsec cryptographic algorithm
+ /// can be applied. For ESP, this is the encryption algorithm and for
+ /// AH, this is the authentication algorithm. The ByteCount
+ /// includes pad bytes for cryptographic operations.
+ ///
+ UINT64 ByteCount;
+ ///
+ /// A time interval in second that warns the implementation to
+ /// initiate action such as setting up a replacement SA.
+ ///
+ UINT64 SoftLifetime;
+ ///
+ /// A time interval in second when the current SA ends and is
+ /// destroyed.
+ ///
+ UINT64 HardLifetime;
+} EFI_IPSEC_SA_LIFETIME;
+
+///
+/// EFI_IPSEC_MODE
+/// There are two modes of IPsec operation: transport mode and tunnel mode. In
+/// EfiIPsecTransport mode, AH and ESP provide protection primarily for next layer protocols;
+/// In EfiIPsecTunnel mode, AH and ESP are applied to tunneled IP packets.
+///
+typedef enum {
+ EfiIPsecTransport,
+ EfiIPsecTunnel
+} EFI_IPSEC_MODE;
+
+///
+/// EFI_IPSEC_TUNNEL_DF_OPTION
+/// The option of copying the DF bit from an outbound package to
+/// the tunnel mode header that it emits, when traffic is carried
+/// via a tunnel mode SA. This applies to SAs where both inner and
+/// outer headers are IPv4.
+///
+typedef enum {
+ EfiIPsecTunnelClearDf, ///< Clear DF bit from inner header.
+ EfiIPsecTunnelSetDf, ///< Set DF bit from inner header.
+ EfiIPsecTunnelCopyDf ///< Copy DF bit from inner header.
+} EFI_IPSEC_TUNNEL_DF_OPTION;
+
+///
+/// EFI_IPSEC_TUNNEL_OPTION
+///
+typedef struct _EFI_IPSEC_TUNNEL_OPTION {
+ ///
+ /// Local tunnel address when IPsec mode is EfiIPsecTunnel.
+ ///
+ EFI_IP_ADDRESS LocalTunnelAddress;
+ ///
+ /// Remote tunnel address when IPsec mode is EfiIPsecTunnel.
+ ///
+ EFI_IP_ADDRESS RemoteTunnelAddress;
+ ///
+ /// The option of copying the DF bit from an outbound package
+ /// to the tunnel mode header that it emits, when traffic is
+ /// carried via a tunnel mode SA.
+ ///
+ EFI_IPSEC_TUNNEL_DF_OPTION DF;
+} EFI_IPSEC_TUNNEL_OPTION;
+
+///
+/// EFI_IPSEC_PROTOCOL_TYPE
+///
+typedef enum {
+ EfiIPsecAH, ///< IP Authentication Header protocol which is specified in RFC 4302.
+ EfiIPsecESP ///< IP Encapsulating Security Payload which is specified in RFC 4303.
+} EFI_IPSEC_PROTOCOL_TYPE;
+
+///
+/// EFI_IPSEC_PROCESS_POLICY
+/// describes a policy list for traffic processing.
+///
+typedef struct _EFI_IPSEC_PROCESS_POLICY {
+ ///
+ /// Extended Sequence Number. Is this SA using extended sequence
+ /// numbers. 64 bit counter is used if TRUE.
+ ///
+ BOOLEAN ExtSeqNum;
+ ///
+ /// A flag indicating whether overflow of the sequence number
+ /// counter should generate an auditable event and prevent
+ /// transmission of additional packets on the SA, or whether rollover
+ /// is permitted.
+ ///
+ BOOLEAN SeqOverflow;
+ ///
+ /// Is this SA using stateful fragment checking. TRUE represents
+ /// stateful fragment checking.
+ ///
+ BOOLEAN FragCheck;
+ ///
+ /// A time interval after which a SA must be replaced with a new SA
+ /// (and new SPI) or terminated.
+ ///
+ EFI_IPSEC_SA_LIFETIME SaLifetime;
+ ///
+ /// IPsec mode: tunnel or transport.
+ ///
+ EFI_IPSEC_MODE Mode;
+ ///
+ /// Tunnel Option. TunnelOption is ignored if Mode is EfiIPsecTransport.
+ ///
+ EFI_IPSEC_TUNNEL_OPTION *TunnelOption;
+ ///
+ /// IPsec protocol: AH or ESP
+ ///
+ EFI_IPSEC_PROTOCOL_TYPE Proto;
+ ///
+ /// Cryptographic algorithm type used for authentication.
+ ///
+ UINT8 AuthAlgoId;
+ ///
+ /// Cryptographic algorithm type used for encryption. EncAlgo is
+ /// NULL when IPsec protocol is AH. For ESP protocol, EncAlgo
+ /// can also be used to describe the algorithm if a combined mode
+ /// algorithm is used.
+ ///
+ UINT8 EncAlgoId;
+} EFI_IPSEC_PROCESS_POLICY;
+
+///
+/// EFI_IPSEC_SA_ID
+/// A triplet to identify an SA, consisting of the following members.
+///
+typedef struct _EFI_IPSEC_SA_ID {
+ ///
+ /// Security Parameter Index (aka SPI). An arbitrary 32-bit value
+ /// that is used by a receiver to identity the SA to which an incoming
+ /// package should be bound.
+ ///
+ UINT32 Spi;
+ ///
+ /// IPsec protocol: AH or ESP
+ ///
+ EFI_IPSEC_PROTOCOL_TYPE Proto;
+ ///
+ /// Destination IP address.
+ ///
+ EFI_IP_ADDRESS DestAddress;
+} EFI_IPSEC_SA_ID;
+
+#define MAX_PEERID_LEN 128
+
+///
+/// EFI_IPSEC_SPD_DATA
+///
+typedef struct _EFI_IPSEC_SPD_DATA {
+ ///
+ /// A null-terminated ASCII name string which is used as a symbolic
+ /// identifier for an IPsec Local or Remote address.
+ ///
+ UINT8 Name[MAX_PEERID_LEN];
+ ///
+ /// Bit-mapped list describing Populate from Packet flags. When
+ /// creating a SA, if PackageFlag bit is set to TRUE, instantiate
+ /// the selector from the corresponding field in the package that
+ /// triggered the creation of the SA, else from the value(s) in the
+ /// corresponding SPD entry. The PackageFlag bit setting for
+ /// corresponding selector field of EFI_IPSEC_SPD_SELECTOR:
+ /// Bit 0: EFI_IPSEC_SPD_SELECTOR.LocalAddress
+ /// Bit 1: EFI_IPSEC_SPD_SELECTOR.RemoteAddress
+ /// Bit 2:
+ /// EFI_IPSEC_SPD_SELECTOR.NextLayerProtocol
+ /// Bit 3: EFI_IPSEC_SPD_SELECTOR.LocalPort
+ /// Bit 4: EFI_IPSEC_SPD_SELECTOR.RemotePort
+ /// Others: Reserved.
+ ///
+ UINT32 PackageFlag;
+ ///
+ /// The traffic direction of data gram.
+ ///
+ EFI_IPSEC_TRAFFIC_DIR TrafficDirection;
+ ///
+ /// Processing choices to indicate which action is required by this
+ /// policy.
+ ///
+ EFI_IPSEC_ACTION Action;
+ ///
+ /// The policy and rule information for a SPD entry.
+ ///
+ EFI_IPSEC_PROCESS_POLICY *ProcessingPolicy;
+ ///
+ /// Specifies the actual number of entries in SaId list.
+ ///
+ UINTN SaIdCount;
+ ///
+ /// The SAD entry used for the traffic processing. The
+ /// existed SAD entry links indicate this is the manual key case.
+ ///
+ EFI_IPSEC_SA_ID SaId[1];
+} EFI_IPSEC_SPD_DATA;
+
+///
+/// EFI_IPSEC_AH_ALGO_INFO
+/// The security algorithm selection for IPsec AH authentication.
+/// The required authentication algorithm is specified in RFC 4305.
+///
+typedef struct _EFI_IPSEC_AH_ALGO_INFO {
+ UINT8 AuthAlgoId;
+ UINTN AuthKeyLength;
+ VOID *AuthKey;
+} EFI_IPSEC_AH_ALGO_INFO;
+
+///
+/// EFI_IPSEC_ESP_ALGO_INFO
+/// The security algorithm selection for IPsec ESP encryption and authentication.
+/// The required authentication algorithm is specified in RFC 4305.
+/// EncAlgoId fields can also specify an ESP combined mode algorithm
+/// (e.g. AES with CCM mode, specified in RFC 4309), which provides both
+/// confidentiality and authentication services.
+///
+typedef struct _EFI_IPSEC_ESP_ALGO_INFO {
+ UINT8 EncAlgoId;
+ UINTN EncKeyLength;
+ VOID *EncKey;
+ UINT8 AuthAlgoId;
+ UINTN AuthKeyLength;
+ VOID *AuthKey;
+} EFI_IPSEC_ESP_ALGO_INFO;
+
+///
+/// EFI_IPSEC_ALGO_INFO
+///
+typedef union {
+ EFI_IPSEC_AH_ALGO_INFO AhAlgoInfo;
+ EFI_IPSEC_ESP_ALGO_INFO EspAlgoInfo;
+} EFI_IPSEC_ALGO_INFO;
+
+///
+/// EFI_IPSEC_SA_DATA
+///
+typedef struct _EFI_IPSEC_SA_DATA {
+ ///
+ /// IPsec mode: tunnel or transport.
+ ///
+ EFI_IPSEC_MODE Mode;
+ ///
+ /// Sequence Number Counter. A 64-bit counter used to generate the
+ /// sequence number field in AH or ESP headers.
+ ///
+ UINT64 SNCount;
+ ///
+ /// Anti-Replay Window. A 64-bit counter and a bit-map used to
+ /// determine whether an inbound AH or ESP packet is a replay.
+ ///
+ UINT8 AntiReplayWindows;
+ ///
+ /// AH/ESP cryptographic algorithm, key and parameters.
+ ///
+ EFI_IPSEC_ALGO_INFO AlgoInfo;
+ ///
+ /// Lifetime of this SA.
+ ///
+ EFI_IPSEC_SA_LIFETIME SaLifetime;
+ ///
+ /// Any observed path MTU and aging variables. The Path MTU
+ /// processing is defined in section 8 of RFC 4301.
+ ///
+ UINT32 PathMTU;
+ ///
+ /// Link to one SPD entry.
+ ///
+ EFI_IPSEC_SPD_SELECTOR *SpdSelector;
+ ///
+ /// Indication of whether it's manually set or negotiated automatically.
+ /// If ManualSet is FALSE, the corresponding SA entry is inserted through
+ /// IKE protocol negotiation.
+ ///
+ BOOLEAN ManualSet;
+} EFI_IPSEC_SA_DATA;
+
+///
+/// EFI_IPSEC_SA_DATA2
+///
+typedef struct _EFI_IPSEC_SA_DATA2 {
+ ///
+ /// IPsec mode: tunnel or transport
+ ///
+ EFI_IPSEC_MODE Mode;
+ ///
+ /// Sequence Number Counter. A 64-bit counter used to generate the sequence
+ /// number field in AH or ESP headers.
+ ///
+ UINT64 SNCount;
+ ///
+ /// Anti-Replay Window. A 64-bit counter and a bit-map used to determine
+ /// whether an inbound AH or ESP packet is a replay.
+ ///
+ UINT8 AntiReplayWindows;
+ ///
+ /// AH/ESP cryptographic algorithm, key and parameters.
+ ///
+ EFI_IPSEC_ALGO_INFO AlgoInfo;
+ ///
+ /// Lifetime of this SA.
+ ///
+ EFI_IPSEC_SA_LIFETIME SaLifetime;
+ ///
+ /// Any observed path MTU and aging variables. The Path MTU processing is
+ /// defined in section 8 of RFC 4301.
+ ///
+ UINT32 PathMTU;
+ ///
+ /// Link to one SPD entry
+ ///
+ EFI_IPSEC_SPD_SELECTOR *SpdSelector;
+ ///
+ /// Indication of whether it's manually set or negotiated automatically.
+ /// If ManualSet is FALSE, the corresponding SA entry is inserted through IKE
+ /// protocol negotiation
+ ///
+ BOOLEAN ManualSet;
+ ///
+ /// The tunnel header IP source address.
+ ///
+ EFI_IP_ADDRESS TunnelSourceAddress;
+ ///
+ /// The tunnel header IP destination address.
+ ///
+ EFI_IP_ADDRESS TunnelDestinationAddress;
+} EFI_IPSEC_SA_DATA2;
+
+///
+/// EFI_IPSEC_PAD_ID
+/// specifies the identifier for PAD entry, which is also used for SPD lookup.
+/// IpAddress Pointer to the IPv4 or IPv6 address range.
+///
+typedef struct _EFI_IPSEC_PAD_ID {
+ ///
+ /// Flag to identify which type of PAD Id is used.
+ ///
+ BOOLEAN PeerIdValid;
+ union {
+ ///
+ /// Pointer to the IPv4 or IPv6 address range.
+ ///
+ EFI_IP_ADDRESS_INFO IpAddress;
+ ///
+ /// Pointer to a null terminated ASCII string
+ /// representing the symbolic names. A PeerId can be a DNS
+ /// name, Distinguished Name, RFC 822 email address or Key ID
+ /// (specified in section 4.4.3.1 of RFC 4301)
+ ///
+ UINT8 PeerId[MAX_PEERID_LEN];
+ } Id;
+} EFI_IPSEC_PAD_ID;
+
+///
+/// EFI_IPSEC_CONFIG_SELECTOR
+/// describes the expected IPsec configuration data selector
+/// of type EFI_IPSEC_CONFIG_DATA_TYPE.
+///
+typedef union {
+ EFI_IPSEC_SPD_SELECTOR SpdSelector;
+ EFI_IPSEC_SA_ID SaId;
+ EFI_IPSEC_PAD_ID PadId;
+} EFI_IPSEC_CONFIG_SELECTOR;
+
+///
+/// EFI_IPSEC_AUTH_PROTOCOL_TYPE
+/// defines the possible authentication protocol for IPsec
+/// security association management.
+///
+typedef enum {
+ EfiIPsecAuthProtocolIKEv1,
+ EfiIPsecAuthProtocolIKEv2,
+ EfiIPsecAuthProtocolMaximum
+} EFI_IPSEC_AUTH_PROTOCOL_TYPE;
+
+///
+/// EFI_IPSEC_AUTH_METHOD
+///
+typedef enum {
+ ///
+ /// Using Pre-shared Keys for manual security associations.
+ ///
+ EfiIPsecAuthMethodPreSharedSecret,
+ ///
+ /// IKE employs X.509 certificates for SA establishment.
+ ///
+ EfiIPsecAuthMethodCertificates,
+ EfiIPsecAuthMethodMaximum
+} EFI_IPSEC_AUTH_METHOD;
+
+///
+/// EFI_IPSEC_PAD_DATA
+///
+typedef struct _EFI_IPSEC_PAD_DATA {
+ ///
+ /// Authentication Protocol for IPsec security association management.
+ ///
+ EFI_IPSEC_AUTH_PROTOCOL_TYPE AuthProtocol;
+ ///
+ /// Authentication method used.
+ ///
+ EFI_IPSEC_AUTH_METHOD AuthMethod;
+ ///
+ /// The IKE ID payload will be used as a symbolic name for SPD
+ /// lookup if IkeIdFlag is TRUE. Otherwise, the remote IP
+ /// address provided in traffic selector playloads will be used.
+ ///
+ BOOLEAN IkeIdFlag;
+ ///
+ /// The size of Authentication data buffer, in bytes.
+ ///
+ UINTN AuthDataSize;
+ ///
+ /// Buffer for Authentication data, (e.g., the pre-shared secret or the
+ /// trust anchor relative to which the peer's certificate will be
+ /// validated).
+ ///
+ VOID *AuthData;
+ ///
+ /// The size of RevocationData, in bytes
+ ///
+ UINTN RevocationDataSize;
+ ///
+ /// Pointer to CRL or OCSP data, if certificates are used for
+ /// authentication method.
+ ///
+ VOID *RevocationData;
+} EFI_IPSEC_PAD_DATA;
+
+/**
+ Set the security association, security policy and peer authorization configuration
+ information for the EFI IPsec driver.
+
+ This function is used to set the IPsec configuration information of type DataType for
+ the EFI IPsec driver.
+ The IPsec configuration data has a unique selector/identifier separately to identify
+ a data entry. The selector structure depends on DataType's definition.
+ Using SetData() with a Data of NULL causes the IPsec configuration data entry identified
+ by DataType and Selector to be deleted.
+
+ @param[in] This Pointer to the EFI_IPSEC_CONFIG_PROTOCOL instance.
+ @param[in] DataType The type of data to be set.
+ @param[in] Selector Pointer to an entry selector on operated configuration data
+ specified by DataType. A NULL Selector causes the entire
+ specified-type configuration information to be flushed.
+ @param[in] Data The data buffer to be set. The structure of the data buffer is
+ associated with the DataType.
+ @param[in] InsertBefore Pointer to one entry selector which describes the expected
+ position the new data entry will be added. If InsertBefore is NULL,
+ the new entry will be appended the end of database.
+
+ @retval EFI_SUCCESS The specified configuration entry data is set successfully.
+ @retval EFI_INVALID_PARAMETER One or more of the following are TRUE:
+ - This is NULL.
+ @retval EFI_UNSUPPORTED The specified DataType is not supported.
+ @retval EFI_OUT_OF_RESOURCED The required system resource could not be allocated.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_IPSEC_CONFIG_SET_DATA)(
+ IN EFI_IPSEC_CONFIG_PROTOCOL *This,
+ IN EFI_IPSEC_CONFIG_DATA_TYPE DataType,
+ IN EFI_IPSEC_CONFIG_SELECTOR *Selector,
+ IN VOID *Data,
+ IN EFI_IPSEC_CONFIG_SELECTOR *InsertBefore OPTIONAL
+ );
+
+/**
+ Return the configuration value for the EFI IPsec driver.
+
+ This function lookup the data entry from IPsec database or IKEv2 configuration
+ information. The expected data type and unique identification are described in
+ DataType and Selector parameters.
+
+ @param[in] This Pointer to the EFI_IPSEC_CONFIG_PROTOCOL instance.
+ @param[in] DataType The type of data to retrieve.
+ @param[in] Selector Pointer to an entry selector which is an identifier of the IPsec
+ configuration data entry.
+ @param[in, out] DataSize On output the size of data returned in Data.
+ @param[out] Data The buffer to return the contents of the IPsec configuration data.
+ The type of the data buffer is associated with the DataType.
+
+ @retval EFI_SUCCESS The specified configuration data is got successfully.
+ @retval EFI_INVALID_PARAMETER One or more of the followings are TRUE:
+ - This is NULL.
+ - Selector is NULL.
+ - DataSize is NULL.
+ - Data is NULL and *DataSize is not zero
+ @retval EFI_NOT_FOUND The configuration data specified by Selector is not found.
+ @retval EFI_UNSUPPORTED The specified DataType is not supported.
+ @retval EFI_BUFFER_TOO_SMALL The DataSize is too small for the result. DataSize has been
+ updated with the size needed to complete the request.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_IPSEC_CONFIG_GET_DATA)(
+ IN EFI_IPSEC_CONFIG_PROTOCOL *This,
+ IN EFI_IPSEC_CONFIG_DATA_TYPE DataType,
+ IN EFI_IPSEC_CONFIG_SELECTOR *Selector,
+ IN OUT UINTN *DataSize,
+ OUT VOID *Data
+ );
+
+/**
+ Enumerates the current selector for IPsec configuration data entry.
+
+ This function is called multiple times to retrieve the entry Selector in IPsec
+ configuration database. On each call to GetNextSelector(), the next entry
+ Selector are retrieved into the output interface.
+
+ If the entire IPsec configuration database has been iterated, the error
+ EFI_NOT_FOUND is returned.
+ If the Selector buffer is too small for the next Selector copy, an
+ EFI_BUFFER_TOO_SMALL error is returned, and SelectorSize is updated to reflect
+ the size of buffer needed.
+
+ On the initial call to GetNextSelector() to start the IPsec configuration database
+ search, a pointer to the buffer with all zero value is passed in Selector. Calls
+ to SetData() between calls to GetNextSelector may produce unpredictable results.
+
+ @param[in] This Pointer to the EFI_IPSEC_CONFIG_PROTOCOL instance.
+ @param[in] DataType The type of IPsec configuration data to retrieve.
+ @param[in, out] SelectorSize The size of the Selector buffer.
+ @param[in, out] Selector On input, supplies the pointer to last Selector that was
+ returned by GetNextSelector().
+ On output, returns one copy of the current entry Selector
+ of a given DataType.
+
+ @retval EFI_SUCCESS The specified configuration data is got successfully.
+ @retval EFI_INVALID_PARAMETER One or more of the followings are TRUE:
+ - This is NULL.
+ - SelectorSize is NULL.
+ - Selector is NULL.
+ @retval EFI_NOT_FOUND The next configuration data entry was not found.
+ @retval EFI_UNSUPPORTED The specified DataType is not supported.
+ @retval EFI_BUFFER_TOO_SMALL The SelectorSize is too small for the result. This parameter
+ has been updated with the size needed to complete the search
+ request.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_IPSEC_CONFIG_GET_NEXT_SELECTOR)(
+ IN EFI_IPSEC_CONFIG_PROTOCOL *This,
+ IN EFI_IPSEC_CONFIG_DATA_TYPE DataType,
+ IN OUT UINTN *SelectorSize,
+ IN OUT EFI_IPSEC_CONFIG_SELECTOR *Selector
+ );
+
+/**
+ Register an event that is to be signaled whenever a configuration process on the
+ specified IPsec configuration information is done.
+
+ This function registers an event that is to be signaled whenever a configuration
+ process on the specified IPsec configuration data is done (e.g. IPsec security
+ policy database configuration is ready). An event can be registered for different
+ DataType simultaneously and the caller is responsible for determining which type
+ of configuration data causes the signaling of the event in such case.
+
+ @param[in] This Pointer to the EFI_IPSEC_CONFIG_PROTOCOL instance.
+ @param[in] DataType The type of data to be registered the event for.
+ @param[in] Event The event to be registered.
+
+ @retval EFI_SUCCESS The event is registered successfully.
+ @retval EFI_INVALID_PARAMETER This is NULL or Event is NULL.
+ @retval EFI_ACCESS_DENIED The Event is already registered for the DataType.
+ @retval EFI_UNSUPPORTED The notify registration unsupported or the specified
+ DataType is not supported.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_IPSEC_CONFIG_REGISTER_NOTIFY)(
+ IN EFI_IPSEC_CONFIG_PROTOCOL *This,
+ IN EFI_IPSEC_CONFIG_DATA_TYPE DataType,
+ IN EFI_EVENT Event
+ );
+
+/**
+ Remove the specified event that is previously registered on the specified IPsec
+ configuration data.
+
+ This function removes a previously registered event for the specified configuration data.
+
+ @param[in] This Pointer to the EFI_IPSEC_CONFIG_PROTOCOL instance.
+ @param[in] DataType The configuration data type to remove the registered event for.
+ @param[in] Event The event to be unregistered.
+
+ @retval EFI_SUCCESS The event is removed successfully.
+ @retval EFI_NOT_FOUND The Event specified by DataType could not be found in the
+ database.
+ @retval EFI_INVALID_PARAMETER This is NULL or Event is NULL.
+ @retval EFI_UNSUPPORTED The notify registration unsupported or the specified
+ DataType is not supported.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_IPSEC_CONFIG_UNREGISTER_NOTIFY)(
+ IN EFI_IPSEC_CONFIG_PROTOCOL *This,
+ IN EFI_IPSEC_CONFIG_DATA_TYPE DataType,
+ IN EFI_EVENT Event
+ );
+
+///
+/// EFI_IPSEC_CONFIG_PROTOCOL
+/// provides the ability to set and lookup the IPsec SAD (Security Association Database),
+/// SPD (Security Policy Database) data entry and configure the security association
+/// management protocol such as IKEv2. This protocol is used as the central
+/// repository of any policy-specific configuration for EFI IPsec driver.
+/// EFI_IPSEC_CONFIG_PROTOCOL can be bound to both IPv4 and IPv6 stack. User can use this
+/// protocol for IPsec configuration in both IPv4 and IPv6 environment.
+///
+struct _EFI_IPSEC_CONFIG_PROTOCOL {
+ EFI_IPSEC_CONFIG_SET_DATA SetData;
+ EFI_IPSEC_CONFIG_GET_DATA GetData;
+ EFI_IPSEC_CONFIG_GET_NEXT_SELECTOR GetNextSelector;
+ EFI_IPSEC_CONFIG_REGISTER_NOTIFY RegisterDataNotify;
+ EFI_IPSEC_CONFIG_UNREGISTER_NOTIFY UnregisterDataNotify;
+};
+
+extern EFI_GUID gEfiIpSecConfigProtocolGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/IsaHc.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/IsaHc.h
new file mode 100644
index 0000000000..e4c3077ee2
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/IsaHc.h
@@ -0,0 +1,110 @@
+/** @file
+ ISA HC Protocol as defined in the PI 1.2.1 specification.
+
+ This protocol provides registration for ISA devices on a positive- or
+ subtractive-decode ISA bus. It allows devices to be registered and also
+ handles opening and closing the apertures which are positively-decoded.
+
+ Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Revision Reference:
+ This protocol is from PI Version 1.2.1.
+
+**/
+
+#ifndef __ISA_HC_PROTOCOL_H__
+#define __ISA_HC_PROTOCOL_H__
+
+#define EFI_ISA_HC_PROTOCOL_GUID \
+ { \
+ 0xbcdaf080, 0x1bde, 0x4e22, {0xae, 0x6a, 0x43, 0x54, 0x1e, 0x12, 0x8e, 0xc4} \
+ }
+
+#define EFI_ISA_HC_SERVICE_BINDING_PROTOCOL_GUID \
+ { \
+ 0xfad7933a, 0x6c21, 0x4234, {0xa4, 0x34, 0x0a, 0x8a, 0x0d, 0x2b, 0x07, 0x81} \
+ }
+
+typedef struct _EFI_ISA_HC_PROTOCOL EFI_ISA_HC_PROTOCOL;
+typedef struct _EFI_ISA_HC_PROTOCOL *PEFI_ISA_HC_PROTOCOL;
+
+/**
+ Open I/O aperture.
+
+ This function opens an I/O aperture in a ISA Host Controller for the I/O addresses
+ specified by IoAddress to IoAddress + IoLength - 1. It may be possible that a
+ single hardware aperture may be used for more than one device. This function
+ tracks the number of times that each aperture is referenced, and does not close
+ the hardware aperture (via CloseIoAperture()) until there are no more references to it.
+
+ @param This A pointer to this instance of the EFI_ISA_HC_PROTOCOL.
+ @param IoAddress An unsigned integer that specifies the first byte of the
+ I/O space required.
+ @param IoLength An unsigned integer that specifies the number of bytes
+ of the I/O space required.
+ @param IoApertureHandle A pointer to the returned I/O aperture handle. This
+ value can be used on subsequent calls to CloseIoAperture().
+
+ @retval EFI_SUCCESS The I/O aperture was opened successfully.
+ @retval EFI_UNSUPPORTED The ISA Host Controller is a subtractive-decode controller.
+ @retval EFI_OUT_OF_RESOURCES There is no available I/O aperture.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_ISA_HC_OPEN_IO)(
+ IN CONST EFI_ISA_HC_PROTOCOL *This,
+ IN UINT16 IoAddress,
+ IN UINT16 IoLength,
+ OUT UINT64 *IoApertureHandle
+ );
+
+/**
+ Close I/O aperture.
+
+ This function closes a previously opened I/O aperture handle. If there are no
+ more I/O aperture handles that refer to the hardware I/O aperture resource,
+ then the hardware I/O aperture is closed. It may be possible that a single
+ hardware aperture may be used for more than one device. This function tracks
+ the number of times that each aperture is referenced, and does not close the
+ hardware aperture (via CloseIoAperture()) until there are no more references to it.
+
+ @param This A pointer to this instance of the EFI_ISA_HC_PROTOCOL.
+ @param IoApertureHandle The I/O aperture handle previously returned from a
+ call to OpenIoAperture().
+
+ @retval EFI_SUCCESS The IO aperture was closed successfully.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_ISA_HC_CLOSE_IO)(
+ IN CONST EFI_ISA_HC_PROTOCOL *This,
+ IN UINT64 IoApertureHandle
+ );
+
+///
+/// ISA HC Protocol
+///
+struct _EFI_ISA_HC_PROTOCOL {
+ ///
+ /// The version of this protocol. Higher version numbers are backward
+ /// compatible with lower version numbers.
+ ///
+ UINT32 Version;
+ ///
+ /// Open an I/O aperture.
+ ///
+ EFI_ISA_HC_OPEN_IO OpenIoAperture;
+ ///
+ /// Close an I/O aperture.
+ ///
+ EFI_ISA_HC_CLOSE_IO CloseIoAperture;
+};
+
+///
+/// Reference to variable defined in the .DEC file
+///
+extern EFI_GUID gEfiIsaHcProtocolGuid;
+extern EFI_GUID gEfiIsaHcServiceBindingProtocolGuid;
+
+#endif // __ISA_HC_H__
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/Kms.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/Kms.h
new file mode 100644
index 0000000000..e1b44797af
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/Kms.h
@@ -0,0 +1,1336 @@
+/** @file
+ The Key Management Service (KMS) protocol as defined in the UEFI 2.3.1 specification is to
+ provides services to generate, store, retrieve, and manage cryptographic keys.
+ The intention is to specify a simple generic protocol that could be used for many implementations.
+
+ A driver implementing the protocol may need to provide basic key service that consists of a
+ key store and cryptographic key generation capability. It may connect to an external key
+ server over the network, or to a Hardware Security Module (HSM) attached to the system it
+ runs on, or anything else that is capable of providing the key management service.
+
+ Copyright (c) 2011 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __KMS_H__
+#define __KMS_H__
+
+#define EFI_KMS_PROTOCOL_GUID \
+ { \
+ 0xEC3A978D, 0x7C4E, 0x48FA, {0x9A, 0xBE, 0x6A, 0xD9, 0x1C, 0xC8, 0xF8, 0x11 } \
+ }
+
+typedef struct _EFI_KMS_PROTOCOL EFI_KMS_PROTOCOL;
+
+//
+// Where appropriate, EFI_KMS_DATA_TYPE values may be combined using a bitwise 'OR'
+// operation to indicate support for multiple data types.
+//
+#define EFI_KMS_DATA_TYPE_NONE 0
+#define EFI_KMS_DATA_TYPE_BINARY 1
+#define EFI_KMS_DATA_TYPE_ASCII 2
+#define EFI_KMS_DATA_TYPE_UNICODE 4
+#define EFI_KMS_DATA_TYPE_UTF8 8
+
+//
+// The key formats recognized by the KMS protocol are defined by an EFI_GUID which specifies
+// a (key-algorithm, key-size) pair. The names of these GUIDs are in the format
+// EFI_KMS_KEY_(key-algorithm)_(key-size)_GUID, where the key-size is expressed in bits.
+// The key formats recognized fall into three categories, generic (no algorithm), hash algorithms,
+// and encrypted algorithms.
+//
+
+///
+/// The following GUIDs define formats that contain generic key data of a specific size in bits,
+/// but which is not associated with any specific key algorithm(s).
+///@{
+#define EFI_KMS_FORMAT_GENERIC_128_GUID \
+ { \
+ 0xec8a3d69, 0x6ddf, 0x4108, {0x94, 0x76, 0x73, 0x37, 0xfc, 0x52, 0x21, 0x36 } \
+ }
+#define EFI_KMS_FORMAT_GENERIC_160_GUID \
+ { \
+ 0xa3b3e6f8, 0xefca, 0x4bc1, {0x88, 0xfb, 0xcb, 0x87, 0x33, 0x9b, 0x25, 0x79 } \
+ }
+#define EFI_KMS_FORMAT_GENERIC_256_GUID \
+ { \
+ 0x70f64793, 0xc323, 0x4261, {0xac, 0x2c, 0xd8, 0x76, 0xf2, 0x7c, 0x53, 0x45 } \
+ }
+#define EFI_KMS_FORMAT_GENERIC_512_GUID \
+ { \
+ 0x978fe043, 0xd7af, 0x422e, {0x8a, 0x92, 0x2b, 0x48, 0xe4, 0x63, 0xbd, 0xe6 } \
+ }
+#define EFI_KMS_FORMAT_GENERIC_1024_GUID \
+ { \
+ 0x43be0b44, 0x874b, 0x4ead, {0xb0, 0x9c, 0x24, 0x1a, 0x4f, 0xbd, 0x7e, 0xb3 } \
+ }
+#define EFI_KMS_FORMAT_GENERIC_2048_GUID \
+ { \
+ 0x40093f23, 0x630c, 0x4626, {0x9c, 0x48, 0x40, 0x37, 0x3b, 0x19, 0xcb, 0xbe } \
+ }
+#define EFI_KMS_FORMAT_GENERIC_3072_GUID \
+ { \
+ 0xb9237513, 0x6c44, 0x4411, {0xa9, 0x90, 0x21, 0xe5, 0x56, 0xe0, 0x5a, 0xde } \
+ }
+#define EFI_KMS_FORMAT_GENERIC_DYNAMIC_GUID \
+ { \
+ 0x2156e996, 0x66de, 0x4b27, {0x9c, 0xc9, 0xb0, 0x9f, 0xac, 0x4d, 0x2, 0xbe } \
+ }
+///@}
+
+///
+/// These GUIDS define key data formats that contain data generated by basic hash algorithms
+/// with no cryptographic properties.
+///@{
+#define EFI_KMS_FORMAT_MD2_128_GUID \
+ { \
+ 0x78be11c4, 0xee44, 0x4a22, {0x9f, 0x05, 0x03, 0x85, 0x2e, 0xc5, 0xc9, 0x78 } \
+ }
+#define EFI_KMS_FORMAT_MDC2_128_GUID \
+ { \
+ 0xf7ad60f8, 0xefa8, 0x44a3, {0x91, 0x13, 0x23, 0x1f, 0x39, 0x9e, 0xb4, 0xc7 } \
+ }
+#define EFI_KMS_FORMAT_MD4_128_GUID \
+ { \
+ 0xd1c17aa1, 0xcac5, 0x400f, {0xbe, 0x17, 0xe2, 0xa2, 0xae, 0x06, 0x67, 0x7c } \
+ }
+#define EFI_KMS_FORMAT_MDC4_128_GUID \
+ { \
+ 0x3fa4f847, 0xd8eb, 0x4df4, {0xbd, 0x49, 0x10, 0x3a, 0x0a, 0x84, 0x7b, 0xbc } \
+ }
+#define EFI_KMS_FORMAT_MD5_128_GUID \
+ { \
+ 0xdcbc3662, 0x9cda, 0x4b52, {0xa0, 0x4c, 0x82, 0xeb, 0x1d, 0x23, 0x48, 0xc7 } \
+ }
+#define EFI_KMS_FORMAT_MD5SHA_128_GUID \
+ { \
+ 0x1c178237, 0x6897, 0x459e, {0x9d, 0x36, 0x67, 0xce, 0x8e, 0xf9, 0x4f, 0x76 } \
+ }
+#define EFI_KMS_FORMAT_SHA1_160_GUID \
+ { \
+ 0x453c5e5a, 0x482d, 0x43f0, {0x87, 0xc9, 0x59, 0x41, 0xf3, 0xa3, 0x8a, 0xc2 } \
+ }
+#define EFI_KMS_FORMAT_SHA256_256_GUID \
+ { \
+ 0x6bb4f5cd, 0x8022, 0x448d, {0xbc, 0x6d, 0x77, 0x1b, 0xae, 0x93, 0x5f, 0xc6 } \
+ }
+#define EFI_KMS_FORMAT_SHA512_512_GUID \
+ { \
+ 0x2f240e12, 0xe14d, 0x475c, {0x83, 0xb0, 0xef, 0xff, 0x22, 0xd7, 0x7b, 0xe7 } \
+ }
+///@}
+
+///
+/// These GUIDs define key data formats that contain data generated by cryptographic key algorithms.
+/// There may or may not be a separate data hashing algorithm associated with the key algorithm.
+///@{
+#define EFI_KMS_FORMAT_AESXTS_128_GUID \
+ { \
+ 0x4776e33f, 0xdb47, 0x479a, {0xa2, 0x5f, 0xa1, 0xcd, 0x0a, 0xfa, 0xb3, 0x8b } \
+ }
+#define EFI_KMS_FORMAT_AESXTS_256_GUID \
+ { \
+ 0xdc7e8613, 0xc4bb, 0x4db0, {0x84, 0x62, 0x13, 0x51, 0x13, 0x57, 0xab, 0xe2 } \
+ }
+#define EFI_KMS_FORMAT_AESCBC_128_GUID \
+ { \
+ 0xa0e8ee6a, 0x0e92, 0x44d4, {0x86, 0x1b, 0x0e, 0xaa, 0x4a, 0xca, 0x44, 0xa2 } \
+ }
+#define EFI_KMS_FORMAT_AESCBC_256_GUID \
+ { \
+ 0xd7e69789, 0x1f68, 0x45e8, {0x96, 0xef, 0x3b, 0x64, 0x07, 0xa5, 0xb2, 0xdc } \
+ }
+#define EFI_KMS_FORMAT_RSASHA1_1024_GUID \
+ { \
+ 0x56417bed, 0x6bbe, 0x4882, {0x86, 0xa0, 0x3a, 0xe8, 0xbb, 0x17, 0xf8, 0xf9 } \
+ }
+#define EFI_KMS_FORMAT_RSASHA1_2048_GUID \
+ { \
+ 0xf66447d4, 0x75a6, 0x463e, {0xa8, 0x19, 0x07, 0x7f, 0x2d, 0xda, 0x05, 0xe9 } \
+ }
+#define EFI_KMS_FORMAT_RSASHA256_2048_GUID \
+ { \
+ 0xa477af13, 0x877d, 0x4060, {0xba, 0xa1, 0x25, 0xd1, 0xbe, 0xa0, 0x8a, 0xd3 } \
+ }
+#define EFI_KMS_FORMAT_RSASHA256_3072_GUID \
+ { \
+ 0x4e1356c2, 0xeed, 0x463f, {0x81, 0x47, 0x99, 0x33, 0xab, 0xdb, 0xc7, 0xd5 } \
+ }
+///@}
+
+#define EFI_KMS_ATTRIBUTE_TYPE_NONE 0x00
+#define EFI_KMS_ATTRIBUTE_TYPE_INTEGER 0x01
+#define EFI_KMS_ATTRIBUTE_TYPE_LONG_INTEGER 0x02
+#define EFI_KMS_ATTRIBUTE_TYPE_BIG_INTEGER 0x03
+#define EFI_KMS_ATTRIBUTE_TYPE_ENUMERATION 0x04
+#define EFI_KMS_ATTRIBUTE_TYPE_BOOLEAN 0x05
+#define EFI_KMS_ATTRIBUTE_TYPE_BYTE_STRING 0x06
+#define EFI_KMS_ATTRIBUTE_TYPE_TEXT_STRING 0x07
+#define EFI_KMS_ATTRIBUTE_TYPE_DATE_TIME 0x08
+#define EFI_KMS_ATTRIBUTE_TYPE_INTERVAL 0x09
+#define EFI_KMS_ATTRIBUTE_TYPE_STRUCTURE 0x0A
+#define EFI_KMS_ATTRIBUTE_TYPE_DYNAMIC 0x0B
+
+typedef struct {
+ ///
+ /// Length in bytes of the KeyData.
+ ///
+ UINT32 KeySize;
+ ///
+ /// The data of the key.
+ ///
+ UINT8 KeyData[1];
+} EFI_KMS_FORMAT_GENERIC_DYNAMIC;
+
+typedef struct {
+ ///
+ /// The size in bytes for the client identifier.
+ ///
+ UINT16 ClientIdSize;
+ ///
+ /// Pointer to a valid client identifier.
+ ///
+ VOID *ClientId;
+ ///
+ /// The client name string type used by this client. The string type set here must be one of
+ /// the string types reported in the ClientNameStringTypes field of the KMS protocol. If the
+ /// KMS does not support client names, this field should be set to EFI_KMS_DATA_TYPE_NONE.
+ ///
+ UINT8 ClientNameType;
+ ///
+ /// The size in characters for the client name. This field will be ignored if
+ /// ClientNameStringType is set to EFI_KMS_DATA_TYPE_NONE. Otherwise, it must contain
+ /// number of characters contained in the ClientName field.
+ ///
+ UINT8 ClientNameCount;
+ ///
+ /// Pointer to a client name. This field will be ignored if ClientNameStringType is set to
+ /// EFI_KMS_DATA_TYPE_NONE. Otherwise, it must point to a valid string of the specified type.
+ ///
+ VOID *ClientName;
+} EFI_KMS_CLIENT_INFO;
+
+typedef struct {
+ ///
+ /// The size of the KeyIdentifier field in bytes. This field is limited to the range 0 to 255.
+ ///
+ UINT8 KeyIdentifierSize;
+ ///
+ /// Pointer to an array of KeyIdentifierType elements.
+ ///
+ VOID *KeyIdentifier;
+ ///
+ /// An EFI_GUID which specifies the algorithm and key value size for this key.
+ ///
+ EFI_GUID KeyFormat;
+ ///
+ /// Pointer to a key value for a key specified by the KeyFormat field. A NULL value for this
+ /// field indicates that no key is available.
+ ///
+ VOID *KeyValue;
+ ///
+ /// Specifies the results of KMS operations performed with this descriptor. This field is used
+ /// to indicate the status of individual operations when a KMS function is called with multiple
+ /// EFI_KMS_KEY_DESCRIPTOR structures.
+ /// KeyStatus codes returned for the individual key requests are:
+ /// EFI_SUCCESS Successfully processed this key.
+ /// EFI_WARN_STALE_DATA Successfully processed this key, however, the key's parameters
+ /// exceed internal policies/limits and should be replaced.
+ /// EFI_COMPROMISED_DATA Successfully processed this key, but the key may have been
+ /// compromised and must be replaced.
+ /// EFI_UNSUPPORTED Key format is not supported by the service.
+ /// EFI_OUT_OF_RESOURCES Could not allocate resources for the key processing.
+ /// EFI_TIMEOUT Timed out waiting for device or key server.
+ /// EFI_DEVICE_ERROR Device or key server error.
+ /// EFI_INVALID_PARAMETER KeyFormat is invalid.
+ /// EFI_NOT_FOUND The key does not exist on the KMS.
+ ///
+ EFI_STATUS KeyStatus;
+} EFI_KMS_KEY_DESCRIPTOR;
+
+typedef struct {
+ ///
+ /// Part of a tag-type-length triplet that identifies the KeyAttributeData formatting. The
+ /// definition of the value is outside the scope of this standard and may be defined by the KMS.
+ ///
+ UINT16 Tag;
+ ///
+ /// Part of a tag-type-length triplet that identifies the KeyAttributeData formatting. The
+ /// definition of the value is outside the scope of this standard and may be defined by the KMS.
+ ///
+ UINT16 Type;
+ ///
+ /// Length in bytes of the KeyAttributeData.
+ ///
+ UINT32 Length;
+ ///
+ /// An array of bytes to hold the attribute data associated with the KeyAttributeIdentifier.
+ ///
+ UINT8 KeyAttributeData[1];
+} EFI_KMS_DYNAMIC_FIELD;
+
+typedef struct {
+ ///
+ /// The number of members in the EFI_KMS_DYNAMIC_ATTRIBUTE structure.
+ ///
+ UINT32 FieldCount;
+ ///
+ /// An array of EFI_KMS_DYNAMIC_FIELD structures.
+ ///
+ EFI_KMS_DYNAMIC_FIELD Field[1];
+} EFI_KMS_DYNAMIC_ATTRIBUTE;
+
+typedef struct {
+ ///
+ /// The data type used for the KeyAttributeIdentifier field. Values for this field are defined
+ /// by the EFI_KMS_DATA_TYPE constants, except that EFI_KMS_DATA_TYPE_BINARY is not
+ /// valid for this field.
+ ///
+ UINT8 KeyAttributeIdentifierType;
+ ///
+ /// The length of the KeyAttributeIdentifier field in units defined by KeyAttributeIdentifierType
+ /// field. This field is limited to the range 0 to 255.
+ ///
+ UINT8 KeyAttributeIdentifierCount;
+ ///
+ /// Pointer to an array of KeyAttributeIdentifierType elements. For string types, there must
+ /// not be a null-termination element at the end of the array.
+ ///
+ VOID *KeyAttributeIdentifier;
+ ///
+ /// The instance number of this attribute. If there is only one instance, the value is set to
+ /// one. If this value is set to 0xFFFF (all binary 1's) then this field should be ignored if an
+ /// output or treated as a wild card matching any value if it is an input. If the attribute is
+ /// stored with this field, it will match any attribute request regardless of the setting of the
+ /// field in the request. If set to 0xFFFF in the request, it will match any attribute with the
+ /// same KeyAttributeIdentifier.
+ ///
+ UINT16 KeyAttributeInstance;
+ ///
+ /// The data type of the KeyAttributeValue (e.g. struct, bool, etc.). See the list of
+ /// KeyAttributeType definitions.
+ ///
+ UINT16 KeyAttributeType;
+ ///
+ /// The size in bytes of the KeyAttribute field. A value of zero for this field indicates that no
+ /// key attribute value is available.
+ ///
+ UINT16 KeyAttributeValueSize;
+ ///
+ /// Pointer to a key attribute value for the attribute specified by the KeyAttributeIdentifier
+ /// field. If the KeyAttributeValueSize field is zero, then this field must be NULL.
+ ///
+ VOID *KeyAttributeValue;
+ ///
+ /// KeyAttributeStatusSpecifies the results of KMS operations performed with this attribute.
+ /// This field is used to indicate the status of individual operations when a KMS function is
+ /// called with multiple EFI_KMS_KEY_ATTRIBUTE structures.
+ /// KeyAttributeStatus codes returned for the individual key attribute requests are:
+ /// EFI_SUCCESS Successfully processed this request.
+ /// EFI_WARN_STALE_DATA Successfully processed this request, however, the key's
+ /// parameters exceed internal policies/limits and should be replaced.
+ /// EFI_COMPROMISED_DATA Successfully processed this request, but the key may have been
+ /// compromised and must be replaced.
+ /// EFI_UNSUPPORTED Key attribute format is not supported by the service.
+ /// EFI_OUT_OF_RESOURCES Could not allocate resources for the request processing.
+ /// EFI_TIMEOUT Timed out waiting for device or key server.
+ /// EFI_DEVICE_ERROR Device or key server error.
+ /// EFI_INVALID_PARAMETER A field in the EFI_KMS_KEY_ATTRIBUTE structure is invalid.
+ /// EFI_NOT_FOUND The key attribute does not exist on the KMS.
+ ///
+ EFI_STATUS KeyAttributeStatus;
+} EFI_KMS_KEY_ATTRIBUTE;
+
+/**
+ Get the current status of the key management service.
+
+ @param[in] This Pointer to the EFI_KMS_PROTOCOL instance.
+
+ @retval EFI_SUCCESS The KMS is ready for use.
+ @retval EFI_NOT_READY No connection to the KMS is available.
+ @retval EFI_NO_MAPPING No valid connection configuration exists for the KMS.
+ @retval EFI_NO_RESPONSE No response was received from the KMS.
+ @retval EFI_DEVICE_ERROR An error occurred when attempting to access the KMS.
+ @retval EFI_INVALID_PARAMETER This is NULL.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_KMS_GET_SERVICE_STATUS)(
+ IN EFI_KMS_PROTOCOL *This
+ );
+
+/**
+ Register client information with the supported KMS.
+
+ @param[in] This Pointer to the EFI_KMS_PROTOCOL instance.
+ @param[in] Client Pointer to a valid EFI_KMS_CLIENT_INFO structure.
+ @param[in, out] ClientDataSize Pointer to the size, in bytes, of an arbitrary block of
+ data specified by the ClientData parameter. This
+ parameter may be NULL, in which case the ClientData
+ parameter will be ignored and no data will be
+ transferred to or from the KMS. If the parameter is
+ not NULL, then ClientData must be a valid pointer.
+ If the value pointed to is 0, no data will be transferred
+ to the KMS, but data may be returned by the KMS.
+ For all non-zero values *ClientData will be transferred
+ to the KMS, which may also return data to the caller.
+ In all cases, the value upon return to the caller will
+ be the size of the data block returned to the caller,
+ which will be zero if no data is returned from the KMS.
+ @param[in, out] ClientData Pointer to a pointer to an arbitrary block of data of
+ *ClientDataSize that is to be passed directly to the
+ KMS if it supports the use of client data. This
+ parameter may be NULL if and only if the
+ ClientDataSize parameter is also NULL. Upon return to
+ the caller, *ClientData points to a block of data of
+ *ClientDataSize that was returned from the KMS.
+ If the returned value for *ClientDataSize is zero,
+ then the returned value for *ClientData must be NULL
+ and should be ignored by the caller. The KMS protocol
+ consumer is responsible for freeing all valid buffers
+ used for client data regardless of whether they are
+ allocated by the caller for input to the function or by
+ the implementation for output back to the caller.
+
+ @retval EFI_SUCCESS The client information has been accepted by the KMS.
+ @retval EFI_NOT_READY No connection to the KMS is available.
+ @retval EFI_NO_RESPONSE There was no response from the device or the key server.
+ @retval EFI_ACCESS_DENIED Access was denied by the device or the key server.
+ @retval EFI_DEVICE_ERROR An error occurred when attempting to access the KMS.
+ @retval EFI_OUT_OF_RESOURCES Required resources were not available to perform the function.
+ @retval EFI_INVALID_PARAMETER This is NULL.
+ @retval EFI_UNSUPPORTED The KMS does not support the use of client identifiers.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_KMS_REGISTER_CLIENT)(
+ IN EFI_KMS_PROTOCOL *This,
+ IN EFI_KMS_CLIENT_INFO *Client,
+ IN OUT UINTN *ClientDataSize OPTIONAL,
+ IN OUT VOID **ClientData OPTIONAL
+ );
+
+/**
+ Request that the KMS generate one or more new keys and associate them with key identifiers.
+ The key value(s) is returned to the caller.
+
+ @param[in] This Pointer to the EFI_KMS_PROTOCOL instance.
+ @param[in] Client Pointer to a valid EFI_KMS_CLIENT_INFO structure.
+ @param[in, out] KeyDescriptorCount Pointer to a count of the number of key descriptors to be
+ processed by this operation. On return, this number
+ will be updated with the number of key descriptors
+ successfully processed.
+ @param[in, out] KeyDescriptors Pointer to an array of EFI_KMS_KEY_DESCRIPTOR
+ structures which describe the keys to be generated.
+ On input, the KeyIdentifierSize and the KeyIdentifier
+ may specify an identifier to be used for the key,
+ but this is not required. The KeyFormat field must
+ specify a key format GUID reported as supported by
+ the KeyFormats field of the EFI_KMS_PROTOCOL.
+ The value for this field in the first key descriptor will
+ be considered the default value for subsequent key
+ descriptors requested in this operation if those key
+ descriptors have a NULL GUID in the key format field.
+ On output, the KeyIdentifierSize and KeyIdentifier fields
+ will specify an identifier for the key which will be either
+ the original identifier if one was provided, or an identifier
+ generated either by the KMS or the KMS protocol
+ implementation. The KeyFormat field will be updated
+ with the GUID used to generate the key if it was a
+ NULL GUID, and the KeyValue field will contain a pointer
+ to memory containing the key value for the generated
+ key. Memory for both the KeyIdentifier and the KeyValue
+ fields will be allocated with the BOOT_SERVICES_DATA
+ type and must be freed by the caller when it is no longer
+ needed. Also, the KeyStatus field must reflect the result
+ of the request relative to that key.
+ @param[in, out] ClientDataSize Pointer to the size, in bytes, of an arbitrary block of
+ data specified by the ClientData parameter. This
+ parameter may be NULL, in which case the ClientData
+ parameter will be ignored and no data will be
+ transferred to or from the KMS. If the parameter is
+ not NULL, then ClientData must be a valid pointer.
+ If the value pointed to is 0, no data will be transferred
+ to the KMS, but data may be returned by the KMS.
+ For all non-zero values *ClientData will be transferred
+ to the KMS, which may also return data to the caller.
+ In all cases, the value upon return to the caller will
+ be the size of the data block returned to the caller,
+ which will be zero if no data is returned from the KMS.
+ @param[in, out] ClientData Pointer to a pointer to an arbitrary block of data of
+ *ClientDataSize that is to be passed directly to the
+ KMS if it supports the use of client data. This
+ parameter may be NULL if and only if the
+ ClientDataSize parameter is also NULL. Upon return to
+ the caller, *ClientData points to a block of data of
+ *ClientDataSize that was returned from the KMS.
+ If the returned value for *ClientDataSize is zero,
+ then the returned value for *ClientData must be NULL
+ and should be ignored by the caller. The KMS protocol
+ consumer is responsible for freeing all valid buffers
+ used for client data regardless of whether they are
+ allocated by the caller for input to the function or by
+ the implementation for output back to the caller.
+
+ @retval EFI_SUCCESS Successfully generated and retrieved all requested keys.
+ @retval EFI_UNSUPPORTED This function is not supported by the KMS. --OR--
+ One (or more) of the key requests submitted is not supported by
+ the KMS. Check individual key request(s) to see which ones
+ may have been processed.
+ @retval EFI_OUT_OF_RESOURCES Required resources were not available to perform the function.
+ @retval EFI_TIMEOUT Timed out waiting for device or key server. Check individual key
+ request(s) to see which ones may have been processed.
+ @retval EFI_ACCESS_DENIED Access was denied by the device or the key server; OR a
+ ClientId is required by the server and either no id was
+ provided or an invalid id was provided.
+ @retval EFI_DEVICE_ERROR An error occurred when attempting to access the KMS. Check
+ individual key request(s) to see which ones may have been
+ processed.
+ @retval EFI_INVALID_PARAMETER This is NULL, ClientId is required but it is NULL,
+ KeyDescriptorCount is NULL, or Keys is NULL.
+ @retval EFI_NOT_FOUND One or more EFI_KMS_KEY_DESCRIPTOR structures
+ could not be processed properly. KeyDescriptorCount
+ contains the number of structures which were successfully
+ processed. Individual structures will reflect the status of the
+ processing for that structure.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_KMS_CREATE_KEY)(
+ IN EFI_KMS_PROTOCOL *This,
+ IN EFI_KMS_CLIENT_INFO *Client,
+ IN OUT UINT16 *KeyDescriptorCount,
+ IN OUT EFI_KMS_KEY_DESCRIPTOR *KeyDescriptors,
+ IN OUT UINTN *ClientDataSize OPTIONAL,
+ IN OUT VOID **ClientData OPTIONAL
+ );
+
+/**
+ Retrieve an existing key.
+
+ @param[in] This Pointer to the EFI_KMS_PROTOCOL instance.
+ @param[in] Client Pointer to a valid EFI_KMS_CLIENT_INFO structure.
+ @param[in, out] KeyDescriptorCount Pointer to a count of the number of key descriptors to be
+ processed by this operation. On return, this number
+ will be updated with the number of key descriptors
+ successfully processed.
+ @param[in, out] KeyDescriptors Pointer to an array of EFI_KMS_KEY_DESCRIPTOR
+ structures which describe the keys to be retrieved
+ from the KMS.
+ On input, the KeyIdentifierSize and the KeyIdentifier
+ must specify an identifier to be used to retrieve a
+ specific key. All other fields in the descriptor should
+ be NULL.
+ On output, the KeyIdentifierSize and KeyIdentifier fields
+ will be unchanged, while the KeyFormat and KeyValue
+ fields will be updated values associated with this key
+ identifier. Memory for the KeyValue field will be
+ allocated with the BOOT_SERVICES_DATA type and
+ must be freed by the caller when it is no longer needed.
+ Also, the KeyStatus field will reflect the result of the
+ request relative to the individual key descriptor.
+ @param[in, out] ClientDataSize Pointer to the size, in bytes, of an arbitrary block of
+ data specified by the ClientData parameter. This
+ parameter may be NULL, in which case the ClientData
+ parameter will be ignored and no data will be
+ transferred to or from the KMS. If the parameter is
+ not NULL, then ClientData must be a valid pointer.
+ If the value pointed to is 0, no data will be transferred
+ to the KMS, but data may be returned by the KMS.
+ For all non-zero values *ClientData will be transferred
+ to the KMS, which may also return data to the caller.
+ In all cases, the value upon return to the caller will
+ be the size of the data block returned to the caller,
+ which will be zero if no data is returned from the KMS.
+ @param[in, out] ClientData Pointer to a pointer to an arbitrary block of data of
+ *ClientDataSize that is to be passed directly to the
+ KMS if it supports the use of client data. This
+ parameter may be NULL if and only if the
+ ClientDataSize parameter is also NULL. Upon return to
+ the caller, *ClientData points to a block of data of
+ *ClientDataSize that was returned from the KMS.
+ If the returned value for *ClientDataSize is zero,
+ then the returned value for *ClientData must be NULL
+ and should be ignored by the caller. The KMS protocol
+ consumer is responsible for freeing all valid buffers
+ used for client data regardless of whether they are
+ allocated by the caller for input to the function or by
+ the implementation for output back to the caller.
+
+ @retval EFI_SUCCESS Successfully retrieved all requested keys.
+ @retval EFI_OUT_OF_RESOURCES Could not allocate resources for the method processing.
+ @retval EFI_TIMEOUT Timed out waiting for device or key server. Check individual key
+ request(s) to see which ones may have been processed.
+ @retval EFI_BUFFER_TOO_SMALL If multiple keys are associated with a single identifier, and the
+ KeyValue buffer does not contain enough structures
+ (KeyDescriptorCount) to contain all the key data, then
+ the available structures will be filled and
+ KeyDescriptorCount will be updated to indicate the
+ number of keys which could not be processed.
+ @retval EFI_ACCESS_DENIED Access was denied by the device or the key server; OR a
+ ClientId is required by the server and either none or an
+ invalid id was provided.
+ @retval EFI_DEVICE_ERROR Device or key server error. Check individual key request(s) to
+ see which ones may have been processed.
+ @retval EFI_INVALID_PARAMETER This is NULL, ClientId is required but it is NULL,
+ KeyDescriptorCount is NULL, or Keys is NULL.
+ @retval EFI_NOT_FOUND One or more EFI_KMS_KEY_DESCRIPTOR structures
+ could not be processed properly. KeyDescriptorCount
+ contains the number of structures which were successfully
+ processed. Individual structures will reflect the status of the
+ processing for that structure.
+ @retval EFI_UNSUPPORTED The implementation/KMS does not support this function.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_KMS_GET_KEY)(
+ IN EFI_KMS_PROTOCOL *This,
+ IN EFI_KMS_CLIENT_INFO *Client,
+ IN OUT UINT16 *KeyDescriptorCount,
+ IN OUT EFI_KMS_KEY_DESCRIPTOR *KeyDescriptors,
+ IN OUT UINTN *ClientDataSize OPTIONAL,
+ IN OUT VOID **ClientData OPTIONAL
+ );
+
+/**
+ Add a new key.
+
+ @param[in] This Pointer to the EFI_KMS_PROTOCOL instance.
+ @param[in] Client Pointer to a valid EFI_KMS_CLIENT_INFO structure.
+ @param[in, out] KeyDescriptorCount Pointer to a count of the number of key descriptors to be
+ processed by this operation. On normal return, this
+ number will be updated with the number of key
+ descriptors successfully processed.
+ @param[in, out] KeyDescriptors Pointer to an array of EFI_KMS_KEY_DESCRIPTOR
+ structures which describe the keys to be added.
+ On input, the KeyId field for first key must contain
+ valid identifier data to be used for adding a key to
+ the KMS. The values for these fields in this key
+ definition will be considered default values for
+ subsequent keys requested in this operation. A value
+ of 0 in any subsequent KeyId field will be replaced
+ with the current default value. The KeyFormat and
+ KeyValue fields for each key to be added must contain
+ consistent values to be associated with the given KeyId.
+ On return, the KeyStatus field will reflect the result
+ of the operation for each key request.
+ @param[in, out] ClientDataSize Pointer to the size, in bytes, of an arbitrary block of
+ data specified by the ClientData parameter. This
+ parameter may be NULL, in which case the ClientData
+ parameter will be ignored and no data will be
+ transferred to or from the KMS. If the parameter is
+ not NULL, then ClientData must be a valid pointer.
+ If the value pointed to is 0, no data will be transferred
+ to the KMS, but data may be returned by the KMS.
+ For all non-zero values *ClientData will be transferred
+ to the KMS, which may also return data to the caller.
+ In all cases, the value upon return to the caller will
+ be the size of the data block returned to the caller,
+ which will be zero if no data is returned from the KMS.
+ @param[in, out] ClientData Pointer to a pointer to an arbitrary block of data of
+ *ClientDataSize that is to be passed directly to the
+ KMS if it supports the use of client data. This
+ parameter may be NULL if and only if the
+ ClientDataSize parameter is also NULL. Upon return to
+ the caller, *ClientData points to a block of data of
+ *ClientDataSize that was returned from the KMS.
+ If the returned value for *ClientDataSize is zero,
+ then the returned value for *ClientData must be NULL
+ and should be ignored by the caller. The KMS protocol
+ consumer is responsible for freeing all valid buffers
+ used for client data regardless of whether they are
+ allocated by the caller for input to the function or by
+ the implementation for output back to the caller.
+
+ @retval EFI_SUCCESS Successfully added all requested keys.
+ @retval EFI_OUT_OF_RESOURCES Could not allocate required resources.
+ @retval EFI_TIMEOUT Timed out waiting for device or key server. Check individual key
+ request(s) to see which ones may have been processed.
+ @retval EFI_BUFFER_TOO_SMALL If multiple keys are associated with a single identifier, and the
+ KeyValue buffer does not contain enough structures
+ (KeyDescriptorCount) to contain all the key data, then
+ the available structures will be filled and
+ KeyDescriptorCount will be updated to indicate the
+ number of keys which could not be processed
+ @retval EFI_ACCESS_DENIED Access was denied by the device or the key server; OR a
+ ClientId is required by the server and either none or an
+ invalid id was provided.
+ @retval EFI_DEVICE_ERROR Device or key server error. Check individual key request(s) to
+ see which ones may have been processed.
+ @retval EFI_INVALID_PARAMETER This is NULL, ClientId is required but it is NULL,
+ KeyDescriptorCount is NULL, or Keys is NULL.
+ @retval EFI_NOT_FOUND One or more EFI_KMS_KEY_DESCRIPTOR structures
+ could not be processed properly. KeyDescriptorCount
+ contains the number of structures which were successfully
+ processed. Individual structures will reflect the status of the
+ processing for that structure.
+ @retval EFI_UNSUPPORTED The implementation/KMS does not support this function.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_KMS_ADD_KEY)(
+ IN EFI_KMS_PROTOCOL *This,
+ IN EFI_KMS_CLIENT_INFO *Client,
+ IN OUT UINT16 *KeyDescriptorCount,
+ IN OUT EFI_KMS_KEY_DESCRIPTOR *KeyDescriptors,
+ IN OUT UINTN *ClientDataSize OPTIONAL,
+ IN OUT VOID **ClientData OPTIONAL
+ );
+
+/**
+ Delete an existing key from the KMS database.
+
+ @param[in] This Pointer to the EFI_KMS_PROTOCOL instance.
+ @param[in] Client Pointer to a valid EFI_KMS_CLIENT_INFO structure.
+ @param[in, out] KeyDescriptorCount Pointer to a count of the number of key descriptors to be
+ processed by this operation. On normal return, this
+ number will be updated with the number of key
+ descriptors successfully processed.
+ @param[in, out] KeyDescriptors Pointer to an array of EFI_KMS_KEY_DESCRIPTOR
+ structures which describe the keys to be deleted.
+ On input, the KeyId field for first key must contain
+ valid identifier data to be used for adding a key to
+ the KMS. The values for these fields in this key
+ definition will be considered default values for
+ subsequent keys requested in this operation. A value
+ of 0 in any subsequent KeyId field will be replaced
+ with the current default value. The KeyFormat and
+ KeyValue fields are ignored, but should be 0.
+ On return, the KeyStatus field will reflect the result
+ of the operation for each key request.
+ @param[in, out] ClientDataSize Pointer to the size, in bytes, of an arbitrary block of
+ data specified by the ClientData parameter. This
+ parameter may be NULL, in which case the ClientData
+ parameter will be ignored and no data will be
+ transferred to or from the KMS. If the parameter is
+ not NULL, then ClientData must be a valid pointer.
+ If the value pointed to is 0, no data will be transferred
+ to the KMS, but data may be returned by the KMS.
+ For all non-zero values *ClientData will be transferred
+ to the KMS, which may also return data to the caller.
+ In all cases, the value upon return to the caller will
+ be the size of the data block returned to the caller,
+ which will be zero if no data is returned from the KMS.
+ @param[in, out] ClientData Pointer to a pointer to an arbitrary block of data of
+ *ClientDataSize that is to be passed directly to the
+ KMS if it supports the use of client data. This
+ parameter may be NULL if and only if the
+ ClientDataSize parameter is also NULL. Upon return to
+ the caller, *ClientData points to a block of data of
+ *ClientDataSize that was returned from the KMS.
+ If the returned value for *ClientDataSize is zero,
+ then the returned value for *ClientData must be NULL
+ and should be ignored by the caller. The KMS protocol
+ consumer is responsible for freeing all valid buffers
+ used for client data regardless of whether they are
+ allocated by the caller for input to the function or by
+ the implementation for output back to the caller.
+
+ @retval EFI_SUCCESS Successfully deleted all requested keys.
+ @retval EFI_OUT_OF_RESOURCES Could not allocate required resources.
+ @retval EFI_TIMEOUT Timed out waiting for device or key server. Check individual key
+ request(s) to see which ones may have been processed.
+ @retval EFI_ACCESS_DENIED Access was denied by the device or the key server; OR a
+ ClientId is required by the server and either none or an
+ invalid id was provided.
+ @retval EFI_DEVICE_ERROR Device or key server error. Check individual key request(s) to
+ see which ones may have been processed.
+ @retval EFI_INVALID_PARAMETER This is NULL, ClientId is required but it is NULL,
+ KeyDescriptorCount is NULL, or Keys is NULL.
+ @retval EFI_NOT_FOUND One or more EFI_KMS_KEY_DESCRIPTOR structures
+ could not be processed properly. KeyDescriptorCount
+ contains the number of structures which were successfully
+ processed. Individual structures will reflect the status of the
+ processing for that structure.
+ @retval EFI_UNSUPPORTED The implementation/KMS does not support this function.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_KMS_DELETE_KEY)(
+ IN EFI_KMS_PROTOCOL *This,
+ IN EFI_KMS_CLIENT_INFO *Client,
+ IN OUT UINT16 *KeyDescriptorCount,
+ IN OUT EFI_KMS_KEY_DESCRIPTOR *KeyDescriptors,
+ IN OUT UINTN *ClientDataSize OPTIONAL,
+ IN OUT VOID **ClientData OPTIONAL
+ );
+
+/**
+ Get one or more attributes associated with a specified key identifier.
+ If none are found, the returned attributes count contains a value of zero.
+
+ @param[in] This Pointer to the EFI_KMS_PROTOCOL instance.
+ @param[in] Client Pointer to a valid EFI_KMS_CLIENT_INFO structure.
+ @param[in] KeyIdentifierSize Pointer to the size in bytes of the KeyIdentifier variable.
+ @param[in] KeyIdentifier Pointer to the key identifier associated with this key.
+ @param[in, out] KeyAttributesCount Pointer to the number of EFI_KMS_KEY_ATTRIBUTE
+ structures associated with the Key identifier. If none
+ are found, the count value is zero on return.
+ On input this value reflects the number of KeyAttributes
+ that may be returned.
+ On output, the value reflects the number of completed
+ KeyAttributes structures found.
+ @param[in, out] KeyAttributes Pointer to an array of EFI_KMS_KEY_ATTRIBUTE
+ structures associated with the Key Identifier.
+ On input, the fields in the structure should be NULL.
+ On output, the attribute fields will have updated values
+ for attributes associated with this key identifier.
+ @param[in, out] ClientDataSize Pointer to the size, in bytes, of an arbitrary block of
+ data specified by the ClientData parameter. This
+ parameter may be NULL, in which case the ClientData
+ parameter will be ignored and no data will be
+ transferred to or from the KMS. If the parameter is
+ not NULL, then ClientData must be a valid pointer.
+ If the value pointed to is 0, no data will be transferred
+ to the KMS, but data may be returned by the KMS.
+ For all non-zero values *ClientData will be transferred
+ to the KMS, which may also return data to the caller.
+ In all cases, the value upon return to the caller will
+ be the size of the data block returned to the caller,
+ which will be zero if no data is returned from the KMS.
+ @param[in, out] ClientData Pointer to a pointer to an arbitrary block of data of
+ *ClientDataSize that is to be passed directly to the
+ KMS if it supports the use of client data. This
+ parameter may be NULL if and only if the
+ ClientDataSize parameter is also NULL. Upon return to
+ the caller, *ClientData points to a block of data of
+ *ClientDataSize that was returned from the KMS.
+ If the returned value for *ClientDataSize is zero,
+ then the returned value for *ClientData must be NULL
+ and should be ignored by the caller. The KMS protocol
+ consumer is responsible for freeing all valid buffers
+ used for client data regardless of whether they are
+ allocated by the caller for input to the function or by
+ the implementation for output back to the caller.
+
+ @retval EFI_SUCCESS Successfully retrieved all key attributes.
+ @retval EFI_OUT_OF_RESOURCES Could not allocate resources for the method processing.
+ @retval EFI_TIMEOUT Timed out waiting for device or key server. Check individual key
+ attribute request(s) to see which ones may have been
+ processed.
+ @retval EFI_BUFFER_TOO_SMALL If multiple key attributes are associated with a single identifier,
+ and the KeyAttributes buffer does not contain enough
+ structures (KeyAttributesCount) to contain all the key
+ attributes data, then the available structures will be filled and
+ KeyAttributesCount will be updated to indicate the
+ number of key attributes which could not be processed.
+ @retval EFI_ACCESS_DENIED Access was denied by the device or the key server; OR a
+ ClientId is required by the server and either none or an
+ invalid id was provided.
+ @retval EFI_DEVICE_ERROR Device or key server error. Check individual key attribute
+ request(s) (i.e. key attribute status for each) to see which ones
+ may have been processed.
+ @retval EFI_INVALID_PARAMETER This is NULL, ClientId is required but it is NULL,
+ KeyIdentifierSize is NULL , or KeyIdentifier
+ is NULL, or KeyAttributes is NULL, or
+ KeyAttributesSize is NULL.
+ @retval EFI_NOT_FOUND The KeyIdentifier could not be found.
+ KeyAttributesCount contains zero. Individual
+ structures will reflect the status of the processing for that
+ structure.
+ @retval EFI_UNSUPPORTED The implementation/KMS does not support this function.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_KMS_GET_KEY_ATTRIBUTES)(
+ IN EFI_KMS_PROTOCOL *This,
+ IN EFI_KMS_CLIENT_INFO *Client,
+ IN UINT8 *KeyIdentifierSize,
+ IN CONST VOID *KeyIdentifier,
+ IN OUT UINT16 *KeyAttributesCount,
+ IN OUT EFI_KMS_KEY_ATTRIBUTE *KeyAttributes,
+ IN OUT UINTN *ClientDataSize OPTIONAL,
+ IN OUT VOID **ClientData OPTIONAL
+ );
+
+/**
+ Add one or more attributes to a key specified by a key identifier.
+
+ @param[in] This Pointer to the EFI_KMS_PROTOCOL instance.
+ @param[in] Client Pointer to a valid EFI_KMS_CLIENT_INFO structure.
+ @param[in] KeyIdentifierSize Pointer to the size in bytes of the KeyIdentifier variable.
+ @param[in] KeyIdentifier Pointer to the key identifier associated with this key.
+ @param[in, out] KeyAttributesCount Pointer to the number of EFI_KMS_KEY_ATTRIBUTE
+ structures to associate with the Key. On normal returns,
+ this number will be updated with the number of key
+ attributes successfully processed.
+ @param[in, out] KeyAttributes Pointer to an array of EFI_KMS_KEY_ATTRIBUTE
+ structures providing the attribute information to
+ associate with the key.
+ On input, the values for the fields in the structure
+ are completely filled in.
+ On return the KeyAttributeStatus field will reflect the
+ result of the operation for each key attribute request.
+ @param[in, out] ClientDataSize Pointer to the size, in bytes, of an arbitrary block of
+ data specified by the ClientData parameter. This
+ parameter may be NULL, in which case the ClientData
+ parameter will be ignored and no data will be
+ transferred to or from the KMS. If the parameter is
+ not NULL, then ClientData must be a valid pointer.
+ If the value pointed to is 0, no data will be transferred
+ to the KMS, but data may be returned by the KMS.
+ For all non-zero values *ClientData will be transferred
+ to the KMS, which may also return data to the caller.
+ In all cases, the value upon return to the caller will
+ be the size of the data block returned to the caller,
+ which will be zero if no data is returned from the KMS.
+ @param[in, out] ClientData Pointer to a pointer to an arbitrary block of data of
+ *ClientDataSize that is to be passed directly to the
+ KMS if it supports the use of client data. This
+ parameter may be NULL if and only if the
+ ClientDataSize parameter is also NULL. Upon return to
+ the caller, *ClientData points to a block of data of
+ *ClientDataSize that was returned from the KMS.
+ If the returned value for *ClientDataSize is zero,
+ then the returned value for *ClientData must be NULL
+ and should be ignored by the caller. The KMS protocol
+ consumer is responsible for freeing all valid buffers
+ used for client data regardless of whether they are
+ allocated by the caller for input to the function or by
+ the implementation for output back to the caller.
+
+ @retval EFI_SUCCESS Successfully added all requested key attributes.
+ @retval EFI_OUT_OF_RESOURCES Could not allocate required resources.
+ @retval EFI_TIMEOUT Timed out waiting for device or key server. Check individual key
+ attribute request(s) to see which ones may have been
+ processed.
+ @retval EFI_BUFFER_TOO_SMALL If multiple keys attributes are associated with a single key
+ identifier, and the attributes buffer does not contain
+ enough structures (KeyAttributesCount) to contain all
+ the data, then the available structures will be filled and
+ KeyAttributesCount will be updated to indicate the
+ number of key attributes which could not be processed. The
+ status of each key attribute is also updated indicating success or
+ failure for that attribute in case there are other errors for those
+ attributes that could be processed.
+ @retval EFI_ACCESS_DENIED Access was denied by the device or the key server; OR a
+ ClientId is required by the server and either none or an
+ invalid id was provided.
+ @retval EFI_DEVICE_ERROR Device or key server error. Check individual key attribute
+ request(s) (i.e. key attribute status for each) to see which ones
+ may have been processed.
+ @retval EFI_INVALID_PARAMETER This is NULL, ClientId is required but it is NULL,
+ KeyAttributesCount is NULL, or KeyAttributes
+ is NULL, or KeyIdentifierSize is NULL, or
+ KeyIdentifer is NULL.
+ @retval EFI_NOT_FOUND The KeyIdentifier could not be found. On return the
+ KeyAttributesCount contains the number of attributes
+ processed. Individual structures will reflect the status of the
+ processing for that structure.
+ @retval EFI_UNSUPPORTED The implementation/KMS does not support this function.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_KMS_ADD_KEY_ATTRIBUTES)(
+ IN EFI_KMS_PROTOCOL *This,
+ IN EFI_KMS_CLIENT_INFO *Client,
+ IN UINT8 *KeyIdentifierSize,
+ IN CONST VOID *KeyIdentifier,
+ IN OUT UINT16 *KeyAttributesCount,
+ IN OUT EFI_KMS_KEY_ATTRIBUTE *KeyAttributes,
+ IN OUT UINTN *ClientDataSize OPTIONAL,
+ IN OUT VOID **ClientData OPTIONAL
+ );
+
+/**
+ Delete attributes to a key specified by a key identifier.
+
+ @param[in] This Pointer to the EFI_KMS_PROTOCOL instance.
+ @param[in] Client Pointer to a valid EFI_KMS_CLIENT_INFO structure.
+ @param[in] KeyIdentifierSize Pointer to the size in bytes of the KeyIdentifier variable.
+ @param[in] KeyIdentifier Pointer to the key identifier associated with this key.
+ @param[in, out] KeyAttributesCount Pointer to the number of EFI_KMS_KEY_ATTRIBUTE
+ structures to associate with the Key.
+ On input, the count value is one or more.
+ On normal returns, this number will be updated with
+ the number of key attributes successfully processed.
+ @param[in, out] KeyAttributes Pointer to an array of EFI_KMS_KEY_ATTRIBUTE
+ structures providing the attribute information to
+ associate with the key.
+ On input, the values for the fields in the structure
+ are completely filled in.
+ On return the KeyAttributeStatus field will reflect the
+ result of the operation for each key attribute request.
+ @param[in, out] ClientDataSize Pointer to the size, in bytes, of an arbitrary block of
+ data specified by the ClientData parameter. This
+ parameter may be NULL, in which case the ClientData
+ parameter will be ignored and no data will be
+ transferred to or from the KMS. If the parameter is
+ not NULL, then ClientData must be a valid pointer.
+ If the value pointed to is 0, no data will be transferred
+ to the KMS, but data may be returned by the KMS.
+ For all non-zero values *ClientData will be transferred
+ to the KMS, which may also return data to the caller.
+ In all cases, the value upon return to the caller will
+ be the size of the data block returned to the caller,
+ which will be zero if no data is returned from the KMS.
+ @param[in, out] ClientData Pointer to a pointer to an arbitrary block of data of
+ *ClientDataSize that is to be passed directly to the
+ KMS if it supports the use of client data. This
+ parameter may be NULL if and only if the
+ ClientDataSize parameter is also NULL. Upon return to
+ the caller, *ClientData points to a block of data of
+ *ClientDataSize that was returned from the KMS.
+ If the returned value for *ClientDataSize is zero,
+ then the returned value for *ClientData must be NULL
+ and should be ignored by the caller. The KMS protocol
+ consumer is responsible for freeing all valid buffers
+ used for client data regardless of whether they are
+ allocated by the caller for input to the function or by
+ the implementation for output back to the caller.
+
+ @retval EFI_SUCCESS Successfully deleted all requested key attributes.
+ @retval EFI_OUT_OF_RESOURCES Could not allocate required resources.
+ @retval EFI_TIMEOUT Timed out waiting for device or key server. Check individual key
+ attribute request(s) to see which ones may have been
+ processed.
+ @retval EFI_ACCESS_DENIED Access was denied by the device or the key server; OR a
+ ClientId is required by the server and either none or an
+ invalid id was provided.
+ @retval EFI_DEVICE_ERROR Device or key server error. Check individual key attribute
+ request(s) (i.e. key attribute status for each) to see which ones
+ may have been processed.
+ @retval EFI_INVALID_PARAMETER This is NULL, ClientId is required but it is NULL,
+ KeyAttributesCount is NULL, or
+ KeyAttributes is NULL, or KeyIdentifierSize
+ is NULL, or KeyIdentifer is NULL.
+ @retval EFI_NOT_FOUND The KeyIdentifier could not be found or the attribute
+ could not be found. On return the KeyAttributesCount
+ contains the number of attributes processed. Individual
+ structures will reflect the status of the processing for that
+ structure.
+ @retval EFI_UNSUPPORTED The implementation/KMS does not support this function.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_KMS_DELETE_KEY_ATTRIBUTES)(
+ IN EFI_KMS_PROTOCOL *This,
+ IN EFI_KMS_CLIENT_INFO *Client,
+ IN UINT8 *KeyIdentifierSize,
+ IN CONST VOID *KeyIdentifier,
+ IN OUT UINT16 *KeyAttributesCount,
+ IN OUT EFI_KMS_KEY_ATTRIBUTE *KeyAttributes,
+ IN OUT UINTN *ClientDataSize OPTIONAL,
+ IN OUT VOID **ClientData OPTIONAL
+ );
+
+/**
+ Retrieve one or more key that has matched all of the specified key attributes.
+
+ @param[in] This Pointer to the EFI_KMS_PROTOCOL instance.
+ @param[in] Client Pointer to a valid EFI_KMS_CLIENT_INFO structure.
+ @param[in, out] KeyAttributesCount Pointer to a count of the number of key attribute structures
+ that must be matched for each returned key descriptor.
+ On input the count value is one or more.
+ On normal returns, this number will be updated with
+ the number of key attributes successfully processed.
+ @param[in, out] KeyAttributes Pointer to an array of EFI_KMS_KEY_ATTRIBUTE
+ structure to search for.
+ On input, the values for the fields in the structure are
+ completely filled in.
+ On return the KeyAttributeStatus field will reflect the
+ result of the operation for each key attribute request.
+ @param[in, out] KeyDescriptorCount Pointer to a count of the number of key descriptors matched
+ by this operation.
+ On entry, this number will be zero.
+ On return, this number will be updated to the number
+ of key descriptors successfully found.
+ @param[in, out] KeyDescriptors Pointer to an array of EFI_KMS_KEY_DESCRIPTOR
+ structures which describe the keys from the KMS
+ having the KeyAttribute(s) specified.
+ On input, this pointer will be NULL.
+ On output, the array will contain an
+ EFI_KMS_KEY_DESCRIPTOR structure for each key
+ meeting the search criteria. Memory for the array
+ and all KeyValue fields will be allocated with the
+ EfiBootServicesData type and must be freed by the
+ caller when it is no longer needed. Also, the KeyStatus
+ field of each descriptor will reflect the result of the
+ request relative to that key descriptor.
+ @param[in, out] ClientDataSize Pointer to the size, in bytes, of an arbitrary block of
+ data specified by the ClientData parameter. This
+ parameter may be NULL, in which case the ClientData
+ parameter will be ignored and no data will be
+ transferred to or from the KMS. If the parameter is
+ not NULL, then ClientData must be a valid pointer.
+ If the value pointed to is 0, no data will be transferred
+ to the KMS, but data may be returned by the KMS.
+ For all non-zero values *ClientData will be transferred
+ to the KMS, which may also return data to the caller.
+ In all cases, the value upon return to the caller will
+ be the size of the data block returned to the caller,
+ which will be zero if no data is returned from the KMS.
+ @param[in, out] ClientData Pointer to a pointer to an arbitrary block of data of
+ *ClientDataSize that is to be passed directly to the
+ KMS if it supports the use of client data. This
+ parameter may be NULL if and only if the
+ ClientDataSize parameter is also NULL. Upon return to
+ the caller, *ClientData points to a block of data of
+ *ClientDataSize that was returned from the KMS.
+ If the returned value for *ClientDataSize is zero,
+ then the returned value for *ClientData must be NULL
+ and should be ignored by the caller. The KMS protocol
+ consumer is responsible for freeing all valid buffers
+ used for client data regardless of whether they are
+ allocated by the caller for input to the function or by
+ the implementation for output back to the caller.
+
+ @retval EFI_SUCCESS Successfully retrieved all requested keys.
+ @retval EFI_OUT_OF_RESOURCES Could not allocate required resources.
+ @retval EFI_TIMEOUT Timed out waiting for device or key server. Check individual key
+ attribute request(s) to see which ones may have been
+ processed.
+ @retval EFI_BUFFER_TOO_SMALL If multiple keys are associated with the attribute(s), and the
+ KeyValue buffer does not contain enough structures
+ (KeyDescriptorCount) to contain all the key data, then
+ the available structures will be filled and
+ KeyDescriptorCount will be updated to indicate the
+ number of keys which could not be processed.
+ @retval EFI_ACCESS_DENIED Access was denied by the device or the key server; OR a
+ ClientId is required by the server and either none or an
+ invalid id was provided.
+ @retval EFI_DEVICE_ERROR Device or key server error. Check individual key attribute
+ request(s) (i.e. key attribute status for each) to see which ones
+ may have been processed.
+ @retval EFI_INVALID_PARAMETER This is NULL, ClientId is required but it is NULL,
+ KeyDescriptorCount is NULL, or
+ KeyDescriptors is NULL or KeyAttributes is
+ NULL, or KeyAttributesCount is NULL.
+ @retval EFI_NOT_FOUND One or more EFI_KMS_KEY_ATTRIBUTE structures could
+ not be processed properly. KeyAttributeCount contains
+ the number of structures which were successfully processed.
+ Individual structures will reflect the status of the processing for
+ that structure.
+ @retval EFI_UNSUPPORTED The implementation/KMS does not support this function.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_KMS_GET_KEY_BY_ATTRIBUTES)(
+ IN EFI_KMS_PROTOCOL *This,
+ IN EFI_KMS_CLIENT_INFO *Client,
+ IN OUT UINTN *KeyAttributeCount,
+ IN OUT EFI_KMS_KEY_ATTRIBUTE *KeyAttributes,
+ IN OUT UINTN *KeyDescriptorCount,
+ IN OUT EFI_KMS_KEY_DESCRIPTOR *KeyDescriptors,
+ IN OUT UINTN *ClientDataSize OPTIONAL,
+ IN OUT VOID **ClientData OPTIONAL
+ );
+
+///
+/// The Key Management Service (KMS) protocol provides services to generate, store, retrieve,
+/// and manage cryptographic keys.
+///
+struct _EFI_KMS_PROTOCOL {
+ ///
+ /// Get the current status of the key management service. If the implementation has not yet
+ /// connected to the KMS, then a call to this function will initiate a connection. This is the
+ /// only function that is valid for use prior to the service being marked available.
+ ///
+ EFI_KMS_GET_SERVICE_STATUS GetServiceStatus;
+ ///
+ /// Register a specific client with the KMS.
+ ///
+ EFI_KMS_REGISTER_CLIENT RegisterClient;
+ ///
+ /// Request the generation of a new key and retrieve it.
+ ///
+ EFI_KMS_CREATE_KEY CreateKey;
+ ///
+ /// Retrieve an existing key.
+ ///
+ EFI_KMS_GET_KEY GetKey;
+ ///
+ /// Add a local key to KMS database. If there is an existing key with this key identifier in the
+ /// KMS database, it will be replaced with the new key.
+ ///
+ EFI_KMS_ADD_KEY AddKey;
+ ///
+ /// Delete an existing key from the KMS database.
+ ///
+ EFI_KMS_DELETE_KEY DeleteKey;
+ ///
+ /// Get attributes for an existing key in the KMS database.
+ ///
+ EFI_KMS_GET_KEY_ATTRIBUTES GetKeyAttributes;
+ ///
+ /// Add attributes to an existing key in the KMS database.
+ ///
+ EFI_KMS_ADD_KEY_ATTRIBUTES AddKeyAttributes;
+ ///
+ /// Delete attributes for an existing key in the KMS database.
+ ///
+ EFI_KMS_DELETE_KEY_ATTRIBUTES DeleteKeyAttributes;
+ ///
+ /// Get existing key(s) with the specified attributes.
+ ///
+ EFI_KMS_GET_KEY_BY_ATTRIBUTES GetKeyByAttributes;
+ ///
+ /// The version of this EFI_KMS_PROTOCOL structure. This must be set to 0x00020040 for
+ /// the initial version of this protocol.
+ ///
+ UINT32 ProtocolVersion;
+ ///
+ /// Optional GUID used to identify a specific KMS. This GUID may be supplied by the provider,
+ /// by the implementation, or may be null. If is null, then the ServiceName must not be null.
+ ///
+ EFI_GUID ServiceId;
+ ///
+ /// Optional pointer to a unicode string which may be used to identify the KMS or provide
+ /// other information about the supplier.
+ ///
+ CHAR16 *ServiceName;
+ ///
+ /// Optional 32-bit value which may be used to indicate the version of the KMS provided by
+ /// the supplier.
+ ///
+ UINT32 ServiceVersion;
+ ///
+ /// TRUE if and only if the service is active and available for use. To avoid unnecessary
+ /// delays in POST, this protocol may be installed without connecting to the service. In this
+ /// case, the first call to the GetServiceStatus () function will cause the implementation to
+ /// connect to the supported service and mark it as available. The capabilities of this service
+ /// as defined in the reminder of this protocol are not guaranteed to be valid until the service
+ /// has been marked available.
+ ///
+ BOOLEAN ServiceAvailable;
+ ///
+ /// TRUE if and only if the service supports client identifiers. Client identifiers may be used
+ /// for auditing, access control or any other purpose specific to the implementation.
+ ///
+ BOOLEAN ClientIdSupported;
+ ///
+ /// TRUE if and only if the service requires a client identifier in order to process key requests.
+ /// FALSE otherwise.
+ ///
+ BOOLEAN ClientIdRequired;
+ ///
+ /// The maximum size in bytes for the client identifier.
+ ///
+ UINT16 ClientIdMaxSize;
+ ///
+ /// The client name string type(s) supported by the KMS service. If client names are not
+ /// supported, this field will be set the EFI_KMS_DATA_TYPE_NONE. Otherwise, it will be set
+ /// to the inclusive 'OR' of all client name formats supported. Client names may be used for
+ /// auditing, access control or any other purpose specific to the implementation.
+ ///
+ UINT8 ClientNameStringTypes;
+ ///
+ /// TRUE if only if the KMS requires a client name to be supplied to the service.
+ /// FALSE otherwise.
+ ///
+ BOOLEAN ClientNameRequired;
+ ///
+ /// The maximum number of characters allowed for the client name.
+ ///
+ UINT16 ClientNameMaxCount;
+ ///
+ /// TRUE if and only if the service supports arbitrary client data requests. The use of client
+ /// data requires the caller to have specific knowledge of the individual KMS service and
+ /// should be used only if absolutely necessary.
+ /// FALSE otherwise.
+ ///
+ BOOLEAN ClientDataSupported;
+ ///
+ /// The maximum size in bytes for the client data. If the maximum data size is not specified
+ /// by the KMS or it is not known, then this field must be filled with all ones.
+ ///
+ UINTN ClientDataMaxSize;
+ ///
+ /// TRUE if variable length key identifiers are supported.
+ /// FALSE if a fixed length key identifier is supported.
+ ///
+ BOOLEAN KeyIdVariableLenSupported;
+ ///
+ /// If KeyIdVariableLenSupported is TRUE, this is the maximum supported key identifier length
+ /// in bytes. Otherwise this is the fixed length of key identifier supported. Key ids shorter
+ /// than the fixed length will be padded on the right with blanks.
+ ///
+ UINTN KeyIdMaxSize;
+ ///
+ /// The number of key format/size GUIDs returned in the KeyFormats field.
+ ///
+ UINTN KeyFormatsCount;
+ ///
+ /// A pointer to an array of EFI_GUID values which specify key formats/sizes supported by
+ /// this KMS. Each format/size pair will be specified by a separate EFI_GUID. At least one
+ /// key format/size must be supported. All formats/sizes with the same hashing algorithm
+ /// must be contiguous in the array, and for each hashing algorithm, the key sizes must be in
+ /// ascending order. See "Related Definitions" for GUIDs which identify supported key formats/sizes.
+ /// This list of GUIDs supported by the KMS is not required to be exhaustive, and the KMS
+ /// may provide support for additional key formats/sizes. Users may request key information
+ /// using an arbitrary GUID, but any GUID not recognized by the implementation or not
+ /// supported by the KMS will return an error code of EFI_UNSUPPORTED
+ ///
+ EFI_GUID *KeyFormats;
+ ///
+ /// TRUE if key attributes are supported.
+ /// FALSE if key attributes are not supported.
+ ///
+ BOOLEAN KeyAttributesSupported;
+ ///
+ /// The key attribute identifier string type(s) supported by the KMS service. If key attributes
+ /// are not supported, this field will be set to EFI_KMS_DATA_TYPE_NONE. Otherwise, it will
+ /// be set to the inclusive 'OR' of all key attribute identifier string types supported.
+ /// EFI_KMS_DATA_TYPE_BINARY is not valid for this field.
+ ///
+ UINT8 KeyAttributeIdStringTypes;
+ UINT16 KeyAttributeIdMaxCount;
+ ///
+ /// The number of predefined KeyAttributes structures returned in the KeyAttributes
+ /// parameter. If the KMS does not support predefined key attributes, or if it does not
+ /// provide a method to obtain predefined key attributes data, then this field must be zero.
+ ///
+ UINTN KeyAttributesCount;
+ ///
+ /// A pointer to an array of KeyAttributes structures which contains the predefined
+ /// attributes supported by this KMS. Each structure must contain a valid key attribute
+ /// identifier and should provide any other information as appropriate for the attribute,
+ /// including a default value if one exists. This variable must be set to NULL if the
+ /// KeyAttributesCount variable is zero. It must point to a valid buffer if the
+ /// KeyAttributesCount variable is non-zero.
+ /// This list of predefined attributes is not required to be exhaustive, and the KMS may
+ /// provide additional predefined attributes not enumerated in this list. The implementation
+ /// does not distinguish between predefined and used defined attributes, and therefore,
+ /// predefined attributes not enumerated will still be processed to the KMS.
+ ///
+ EFI_KMS_KEY_ATTRIBUTE *KeyAttributes;
+};
+
+extern EFI_GUID gEfiKmsFormatGeneric128Guid;
+extern EFI_GUID gEfiKmsFormatGeneric160Guid;
+extern EFI_GUID gEfiKmsFormatGeneric256Guid;
+extern EFI_GUID gEfiKmsFormatGeneric512Guid;
+extern EFI_GUID gEfiKmsFormatGeneric1024Guid;
+extern EFI_GUID gEfiKmsFormatGeneric2048Guid;
+extern EFI_GUID gEfiKmsFormatGeneric3072Guid;
+extern EFI_GUID gEfiKmsFormatMd2128Guid;
+extern EFI_GUID gEfiKmsFormatMdc2128Guid;
+extern EFI_GUID gEfiKmsFormatMd4128Guid;
+extern EFI_GUID gEfiKmsFormatMdc4128Guid;
+extern EFI_GUID gEfiKmsFormatMd5128Guid;
+extern EFI_GUID gEfiKmsFormatMd5sha128Guid;
+extern EFI_GUID gEfiKmsFormatSha1160Guid;
+extern EFI_GUID gEfiKmsFormatSha256256Guid;
+extern EFI_GUID gEfiKmsFormatSha512512Guid;
+extern EFI_GUID gEfiKmsFormatAesxts128Guid;
+extern EFI_GUID gEfiKmsFormatAesxts256Guid;
+extern EFI_GUID gEfiKmsFormatAescbc128Guid;
+extern EFI_GUID gEfiKmsFormatAescbc256Guid;
+extern EFI_GUID gEfiKmsFormatRsasha11024Guid;
+extern EFI_GUID gEfiKmsFormatRsasha12048Guid;
+extern EFI_GUID gEfiKmsFormatRsasha2562048Guid;
+extern EFI_GUID gEfiKmsFormatRsasha2563072Guid;
+extern EFI_GUID gEfiKmsProtocolGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/LegacyRegion2.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/LegacyRegion2.h
new file mode 100644
index 0000000000..3985e6eaf9
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/LegacyRegion2.h
@@ -0,0 +1,225 @@
+/** @file
+ The Legacy Region Protocol controls the read, write and boot-lock attributes for
+ the region 0xC0000 to 0xFFFFF.
+
+ Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Revision Reference:
+ This Protocol is defined in UEFI Platform Initialization Specification 1.2
+ Volume 5: Standards
+
+**/
+
+#ifndef __LEGACY_REGION2_H__
+#define __LEGACY_REGION2_H__
+
+#define EFI_LEGACY_REGION2_PROTOCOL_GUID \
+{ \
+ 0x70101eaf, 0x85, 0x440c, {0xb3, 0x56, 0x8e, 0xe3, 0x6f, 0xef, 0x24, 0xf0 } \
+}
+
+typedef struct _EFI_LEGACY_REGION2_PROTOCOL EFI_LEGACY_REGION2_PROTOCOL;
+
+/**
+ Modify the hardware to allow (decode) or disallow (not decode) memory reads in a region.
+
+ If the On parameter evaluates to TRUE, this function enables memory reads in the address range
+ Start to (Start + Length - 1).
+ If the On parameter evaluates to FALSE, this function disables memory reads in the address range
+ Start to (Start + Length - 1).
+
+ @param This[in] Indicates the EFI_LEGACY_REGION2_PROTOCOL instance.
+ @param Start[in] The beginning of the physical address of the region whose attributes
+ should be modified.
+ @param Length[in] The number of bytes of memory whose attributes should be modified.
+ The actual number of bytes modified may be greater than the number
+ specified.
+ @param Granularity[out] The number of bytes in the last region affected. This may be less
+ than the total number of bytes affected if the starting address
+ was not aligned to a region's starting address or if the length
+ was greater than the number of bytes in the first region.
+ @param On[in] Decode / Non-Decode flag.
+
+ @retval EFI_SUCCESS The region's attributes were successfully modified.
+ @retval EFI_INVALID_PARAMETER If Start or Length describe an address not in the Legacy Region.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_LEGACY_REGION2_DECODE)(
+ IN EFI_LEGACY_REGION2_PROTOCOL *This,
+ IN UINT32 Start,
+ IN UINT32 Length,
+ OUT UINT32 *Granularity,
+ IN BOOLEAN *On
+ );
+
+/**
+ Modify the hardware to disallow memory writes in a region.
+
+ This function changes the attributes of a memory range to not allow writes.
+
+ @param This[in] Indicates the EFI_LEGACY_REGION2_PROTOCOL instance.
+ @param Start[in] The beginning of the physical address of the region whose
+ attributes should be modified.
+ @param Length[in] The number of bytes of memory whose attributes should be modified.
+ The actual number of bytes modified may be greater than the number
+ specified.
+ @param Granularity[out] The number of bytes in the last region affected. This may be less
+ than the total number of bytes affected if the starting address was
+ not aligned to a region's starting address or if the length was
+ greater than the number of bytes in the first region.
+
+ @retval EFI_SUCCESS The region's attributes were successfully modified.
+ @retval EFI_INVALID_PARAMETER If Start or Length describe an address not in the Legacy Region.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_LEGACY_REGION2_LOCK)(
+ IN EFI_LEGACY_REGION2_PROTOCOL *This,
+ IN UINT32 Start,
+ IN UINT32 Length,
+ OUT UINT32 *Granularity
+ );
+
+/**
+ Modify the hardware to disallow memory attribute changes in a region.
+
+ This function makes the attributes of a region read only. Once a region is boot-locked with this
+ function, the read and write attributes of that region cannot be changed until a power cycle has
+ reset the boot-lock attribute. Calls to Decode(), Lock() and Unlock() will have no effect.
+
+ @param This[in] Indicates the EFI_LEGACY_REGION2_PROTOCOL instance.
+ @param Start[in] The beginning of the physical address of the region whose
+ attributes should be modified.
+ @param Length[in] The number of bytes of memory whose attributes should be modified.
+ The actual number of bytes modified may be greater than the number
+ specified.
+ @param Granularity[out] The number of bytes in the last region affected. This may be less
+ than the total number of bytes affected if the starting address was
+ not aligned to a region's starting address or if the length was
+ greater than the number of bytes in the first region.
+
+ @retval EFI_SUCCESS The region's attributes were successfully modified.
+ @retval EFI_INVALID_PARAMETER If Start or Length describe an address not in the Legacy Region.
+ @retval EFI_UNSUPPORTED The chipset does not support locking the configuration registers in
+ a way that will not affect memory regions outside the legacy memory
+ region.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_LEGACY_REGION2_BOOT_LOCK)(
+ IN EFI_LEGACY_REGION2_PROTOCOL *This,
+ IN UINT32 Start,
+ IN UINT32 Length,
+ OUT UINT32 *Granularity OPTIONAL
+ );
+
+/**
+ Modify the hardware to allow memory writes in a region.
+
+ This function changes the attributes of a memory range to allow writes.
+
+ @param This[in] Indicates the EFI_LEGACY_REGION2_PROTOCOL instance.
+ @param Start[in] The beginning of the physical address of the region whose
+ attributes should be modified.
+ @param Length[in] The number of bytes of memory whose attributes should be modified.
+ The actual number of bytes modified may be greater than the number
+ specified.
+ @param Granularity[out] The number of bytes in the last region affected. This may be less
+ than the total number of bytes affected if the starting address was
+ not aligned to a region's starting address or if the length was
+ greater than the number of bytes in the first region.
+
+ @retval EFI_SUCCESS The region's attributes were successfully modified.
+ @retval EFI_INVALID_PARAMETER If Start or Length describe an address not in the Legacy Region.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_LEGACY_REGION2_UNLOCK)(
+ IN EFI_LEGACY_REGION2_PROTOCOL *This,
+ IN UINT32 Start,
+ IN UINT32 Length,
+ OUT UINT32 *Granularity
+ );
+
+typedef enum {
+ LegacyRegionDecoded, ///< This region is currently set to allow reads.
+ LegacyRegionNotDecoded, ///< This region is currently set to not allow reads.
+ LegacyRegionWriteEnabled, ///< This region is currently set to allow writes.
+ LegacyRegionWriteDisabled, ///< This region is currently set to write protected.
+ LegacyRegionBootLocked, ///< This region's attributes are locked, cannot be modified until
+ ///< after a power cycle.
+ LegacyRegionNotLocked ///< This region's attributes are not locked.
+} EFI_LEGACY_REGION_ATTRIBUTE;
+
+typedef struct {
+ ///
+ /// The beginning of the physical address of this
+ /// region.
+ ///
+ UINT32 Start;
+ ///
+ /// The number of bytes in this region.
+ ///
+ UINT32 Length;
+ ///
+ /// Attribute of the Legacy Region Descriptor that
+ /// describes the capabilities for that memory region.
+ ///
+ EFI_LEGACY_REGION_ATTRIBUTE Attribute;
+ ///
+ /// Describes the byte length programmability
+ /// associated with the Start address and the specified
+ /// Attribute setting.
+ UINT32 Granularity;
+} EFI_LEGACY_REGION_DESCRIPTOR;
+
+/**
+ Get region information for the attributes of the Legacy Region.
+
+ This function is used to discover the granularity of the attributes for the memory in the legacy
+ region. Each attribute may have a different granularity and the granularity may not be the same
+ for all memory ranges in the legacy region.
+
+ @param This[in] Indicates the EFI_LEGACY_REGION2_PROTOCOL instance.
+ @param DescriptorCount[out] The number of region descriptor entries returned in the Descriptor
+ buffer.
+ @param Descriptor[out] A pointer to a pointer used to return a buffer where the legacy
+ region information is deposited. This buffer will contain a list of
+ DescriptorCount number of region descriptors. This function will
+ provide the memory for the buffer.
+
+ @retval EFI_SUCCESS The information structure was returned.
+ @retval EFI_UNSUPPORTED This function is not supported.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_LEGACY_REGION_GET_INFO)(
+ IN EFI_LEGACY_REGION2_PROTOCOL *This,
+ OUT UINT32 *DescriptorCount,
+ OUT EFI_LEGACY_REGION_DESCRIPTOR **Descriptor
+ );
+
+///
+/// The EFI_LEGACY_REGION2_PROTOCOL is used to abstract the hardware control of the memory
+/// attributes of the Option ROM shadowing region, 0xC0000 to 0xFFFFF.
+/// There are three memory attributes that can be modified through this protocol: read, write and
+/// boot-lock. These protocols may be set in any combination.
+///
+struct _EFI_LEGACY_REGION2_PROTOCOL {
+ EFI_LEGACY_REGION2_DECODE Decode;
+ EFI_LEGACY_REGION2_LOCK Lock;
+ EFI_LEGACY_REGION2_BOOT_LOCK BootLock;
+ EFI_LEGACY_REGION2_UNLOCK UnLock;
+ EFI_LEGACY_REGION_GET_INFO GetInfo;
+};
+
+extern EFI_GUID gEfiLegacyRegion2ProtocolGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/LegacySpiController.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/LegacySpiController.h
new file mode 100644
index 0000000000..b282ad6a30
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/LegacySpiController.h
@@ -0,0 +1,259 @@
+/** @file
+ This file defines the Legacy SPI Controller Protocol.
+
+ Copyright (c) 2017, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Revision Reference:
+ This Protocol was introduced in UEFI PI Specification 1.6.
+
+**/
+
+#ifndef __LEGACY_SPI_CONTROLLER_PROTOCOL_H__
+#define __LEGACY_SPI_CONTROLLER_PROTOCOL_H__
+
+///
+/// Note: The UEFI PI 1.6 specification uses the character 'l' in the GUID
+/// definition. This definition assumes it was supposed to be '1'.
+///
+/// Global ID for the Legacy SPI Controller Protocol
+///
+#define EFI_LEGACY_SPI_CONTROLLER_GUID \
+ { 0x39136fc7, 0x1a11, 0x49de, \
+ { 0xbf, 0x35, 0x0e, 0x78, 0xdd, 0xb5, 0x24, 0xfc }}
+
+typedef
+ struct _EFI_LEGACY_SPI_CONTROLLER_PROTOCOL
+EFI_LEGACY_SPI_CONTROLLER_PROTOCOL;
+
+/**
+ Set the erase block opcode.
+
+ This routine must be called at or below TPL_NOTIFY.
+ The menu table contains SPI transaction opcodes which are accessible after
+ the legacy SPI flash controller's configuration is locked. The board layer
+ specifies the erase block size for the SPI NOR flash part. The SPI NOR flash
+ peripheral driver selects the erase block opcode which matches the erase
+ block size and uses this API to load the opcode into the opcode menu table.
+
+ @param[in] This Pointer to an EFI_LEGACY_SPI_CONTROLLER_PROTOCOL
+ structure.
+ @param[in] EraseBlockOpcode Erase block opcode to be placed into the opcode
+ menu table.
+
+ @retval EFI_SUCCESS The opcode menu table was updated
+ @retval EFI_ACCESS_ERROR The SPI controller is locked
+
+**/
+typedef EFI_STATUS
+(EFIAPI *EFI_LEGACY_SPI_CONTROLLER_PROTOCOL_ERASE_BLOCK_OPCODE)(
+ IN CONST EFI_LEGACY_SPI_CONTROLLER_PROTOCOL *This,
+ IN UINT8 EraseBlockOpcode
+ );
+
+/**
+ Set the write status prefix opcode.
+
+ This routine must be called at or below TPL_NOTIFY.
+ The prefix table contains SPI transaction write prefix opcodes which are
+ accessible after the legacy SPI flash controller's configuration is locked.
+ The board layer specifies the write status prefix opcode for the SPI NOR
+ flash part. The SPI NOR flash peripheral driver uses this API to load the
+ opcode into the prefix table.
+
+ @param[in] This Pointer to an
+ EFI_LEGACY_SPI_CONTROLLER_PROTOCOL structure.
+ @param[in] WriteStatusPrefix Prefix opcode for the write status command.
+
+ @retval EFI_SUCCESS The prefix table was updated
+ @retval EFI_ACCESS_ERROR The SPI controller is locked
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_LEGACY_SPI_CONTROLLER_PROTOCOL_WRITE_STATUS_PREFIX)(
+ IN CONST EFI_LEGACY_SPI_CONTROLLER_PROTOCOL *This,
+ IN UINT8 WriteStatusPrefix
+ );
+
+/**
+ Set the BIOS base address.
+
+ This routine must be called at or below TPL_NOTIFY.
+ The BIOS base address works with the protect range registers to protect
+ portions of the SPI NOR flash from erase and write operat ions. The BIOS
+ calls this API prior to passing control to the OS loader.
+
+ @param[in] This Pointer to an EFI_LEGACY_SPI_CONTROLLER_PROTOCOL
+ structure.
+ @param[in] BiosBaseAddress The BIOS base address.
+
+ @retval EFI_SUCCESS The BIOS base address was properly set
+ @retval EFI_ACCESS_ERROR The SPI controller is locked
+ @retval EFI_INVALID_PARAMETER The BIOS base address is greater than
+ This->Maxi.mumOffset
+ @retval EFI_UNSUPPORTED The BIOS base address was already set
+
+**/
+typedef EFI_STATUS
+(EFIAPI *EFI_LEGACY_SPI_CONTROLLER_PROTOCOL_BIOS_BASE_ADDRESS)(
+ IN CONST EFI_LEGACY_SPI_CONTROLLER_PROTOCOL *This,
+ IN UINT32 BiosBaseAddress
+ );
+
+/**
+ Clear the SPI protect range registers.
+
+ This routine must be called at or below TPL_NOTIFY.
+ The BIOS uses this routine to set an initial condition on the SPI protect
+ range registers.
+
+ @param[in] This Pointer to an EFI_LEGACY_SPI_CONTROLLER_PROTOCOL structure.
+
+ @retval EFI_SUCCESS The registers were successfully cleared
+ @retval EFI_ACCESS_ERROR The SPI controller is locked
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_LEGACY_SPI_CONTROLLER_PROTOCOL_CLEAR_SPI_PROTECT)(
+ IN CONST EFI_LEGACY_SPI_CONTROLLER_PROTOCOL *This
+ );
+
+/**
+ Determine if the SPI range is protected.
+
+ This routine must be called at or below TPL_NOTIFY.
+ The BIOS uses this routine to verify a range in the SPI is protected.
+
+ @param[in] This Pointer to an EFI_LEGACY_SPI_CONTROLLER_PROTOCOL
+ structure.
+ @param[in] BiosAddress Address within a 4 KiB block to start protecting.
+ @param[in] BytesToProtect The number of 4 KiB blocks to protect.
+
+ @retval TRUE The range is protected
+ @retval FALSE The range is not protected
+
+**/
+typedef
+BOOLEAN
+(EFIAPI *EFI_LEGACY_SPI_CONTROLLER_PROTOCOL_IS_RANGE_PROTECTED)(
+ IN CONST EFI_LEGACY_SPI_CONTROLLER_PROTOCOL *This,
+ IN UINT32 BiosAddress,
+ IN UINT32 BlocksToProtect
+ );
+
+/**
+ Set the next protect range register.
+
+ This routine must be called at or below TPL_NOTIFY.
+ The BIOS sets the protect range register to prevent write and erase
+ operations to a portion of the SPI NOR flash device.
+
+ @param[in] This Pointer to an EFI_LEGACY_SPI_CONTROLLER_PROTOCOL
+ structure.
+ @param[in] BiosAddress Address within a 4 KiB block to start protecting.
+ @param[in] BlocksToProtect The number of 4 KiB blocks to protect.
+
+ @retval EFI_SUCCESS The register was successfully updated
+ @retval EFI_ACCESS_ERROR The SPI controller is locked
+ @retval EFI_INVALID_PARAMETER BiosAddress < This->BiosBaseAddress, or
+ BlocksToProtect * 4 KiB
+ > This->MaximumRangeBytes, or
+ BiosAddress - This->BiosBaseAddress
+ + (BlocksToProtect * 4 KiB)
+ > This->MaximumRangeBytes
+ @retval EFI_OUT_OF_RESOURCES No protect range register available
+ @retval EFI_UNSUPPORTED Call This->SetBaseAddress because the BIOS base
+ address is not set
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_LEGACY_SPI_CONTROLLER_PROTOCOL_PROTECT_NEXT_RANGE)(
+ IN CONST EFI_LEGACY_SPI_CONTROLLER_PROTOCOL *This,
+ IN UINT32 BiosAddress,
+ IN UINT32 BlocksToProtect
+ );
+
+/**
+ Lock the SPI controller configuration.
+
+ This routine must be called at or below TPL_NOTIFY.
+ This routine locks the SPI controller's configuration so that the software
+ is no longer able to update:
+ * Prefix table
+ * Opcode menu
+ * Opcode type table
+ * BIOS base address
+ * Protect range registers
+
+ @param[in] This Pointer to an EFI_LEGACY_SPI_CONTROLLER_PROTOCOL structure.
+
+ @retval EFI_SUCCESS The SPI controller was successfully locked
+ @retval EFI_ALREADY_STARTED The SPI controller was already locked
+
+**/
+typedef EFI_STATUS
+(EFIAPI *EFI_LEGACY_SPI_CONTROLLER_PROTOCOL_LOCK_CONTROLLER)(
+ IN CONST EFI_LEGACY_SPI_CONTROLLER_PROTOCOL *This
+ );
+
+///
+/// Support the extra features of the legacy SPI flash controller.
+///
+struct _EFI_LEGACY_SPI_CONTROLLER_PROTOCOL {
+ ///
+ /// Maximum offset from the BIOS base address that is able to be protected.
+ ///
+ UINT32 MaximumOffset;
+
+ ///
+ /// Maximum number of bytes that can be protected by one range register.
+ ///
+ UINT32 MaximumRangeBytes;
+
+ ///
+ /// The number of registers available for protecting the BIOS.
+ ///
+ UINT32 RangeRegisterCount;
+
+ ///
+ /// Set the erase block opcode.
+ ///
+ EFI_LEGACY_SPI_CONTROLLER_PROTOCOL_ERASE_BLOCK_OPCODE EraseBlockOpcode;
+
+ ///
+ /// Set the write status prefix opcode.
+ ///
+ EFI_LEGACY_SPI_CONTROLLER_PROTOCOL_WRITE_STATUS_PREFIX WriteStatusPrefix;
+
+ ///
+ /// Set the BIOS base address.
+ ///
+ EFI_LEGACY_SPI_CONTROLLER_PROTOCOL_BIOS_BASE_ADDRESS BiosBaseAddress;
+
+ ///
+ /// Clear the SPI protect range registers.
+ ///
+ EFI_LEGACY_SPI_CONTROLLER_PROTOCOL_CLEAR_SPI_PROTECT ClearSpiProtect;
+
+ ///
+ /// Determine if the SPI range is protected.
+ ///
+ EFI_LEGACY_SPI_CONTROLLER_PROTOCOL_IS_RANGE_PROTECTED IsRangeProtected;
+
+ ///
+ /// Set the next protect range register.
+ ///
+ EFI_LEGACY_SPI_CONTROLLER_PROTOCOL_PROTECT_NEXT_RANGE ProtectNextRange;
+
+ ///
+ /// Lock the SPI controller configuration.
+ ///
+ EFI_LEGACY_SPI_CONTROLLER_PROTOCOL_LOCK_CONTROLLER LockController;
+};
+
+extern EFI_GUID gEfiLegacySpiControllerProtocolGuid;
+
+#endif // __LEGACY_SPI_CONTROLLER_PROTOCOL_H__
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/LegacySpiFlash.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/LegacySpiFlash.h
new file mode 100644
index 0000000000..efc18da968
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/LegacySpiFlash.h
@@ -0,0 +1,195 @@
+/** @file
+ This file defines the Legacy SPI Flash Protocol.
+
+ Copyright (c) 2017, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Revision Reference:
+ This Protocol was introduced in UEFI PI Specification 1.6.
+
+**/
+
+#ifndef __LEGACY_SPI_FLASH_PROTOCOL_H__
+#define __LEGACY_SPI_FLASH_PROTOCOL_H__
+
+#include
+
+///
+/// Global ID for the Legacy SPI Flash Protocol
+///
+#define EFI_LEGACY_SPI_FLASH_PROTOCOL_GUID \
+ { 0xf01bed57, 0x04bc, 0x4f3f, \
+ { 0x96, 0x60, 0xd6, 0xf2, 0xea, 0x22, 0x82, 0x59 }}
+
+typedef struct _EFI_LEGACY_SPI_FLASH_PROTOCOL EFI_LEGACY_SPI_FLASH_PROTOCOL;
+
+/**
+ Set the BIOS base address.
+
+ This routine must be called at or below TPL_NOTIFY.
+ The BIOS base address works with the protect range registers to protect
+ portions of the SPI NOR flash from erase and write operat ions.
+ The BIOS calls this API prior to passing control to the OS loader.
+
+ @param[in] This Pointer to an EFI_LEGACY_SPI_FLASH_PROTOCOL data
+ structure.
+ @param[in] BiosBaseAddress The BIOS base address.
+
+ @retval EFI_SUCCESS The BIOS base address was properly set
+ @retval EFI_ACCESS_ERROR The SPI controller is locked
+ @retval EFI_INVALID_PARAMETER BiosBaseAddress > This->MaximumOffset
+ @retval EFI_UNSUPPORTED The BIOS base address was already set or not a
+ legacy SPI host controller
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_LEGACY_SPI_FLASH_PROTOCOL_BIOS_BASE_ADDRESS)(
+ IN CONST EFI_LEGACY_SPI_FLASH_PROTOCOL *This,
+ IN UINT32 BiosBaseAddress
+ );
+
+/**
+ Clear the SPI protect range registers.
+
+ This routine must be called at or below TPL_NOTIFY.
+ The BIOS uses this routine to set an initial condition on the SPI protect
+ range registers.
+
+ @param[in] This Pointer to an EFI_LEGACY_SPI_FLASH_PROTOCOL data structure.
+
+ @retval EFI_SUCCESS The registers were successfully cleared
+ @retval EFI_ACCESS_ERROR The SPI controller is locked
+ @retval EFI_UNSUPPORTED Not a legacy SPI host controller
+
+**/
+typedef EFI_STATUS
+(EFIAPI *EFI_LEGACY_SPI_FLASH_PROTOCOL_CLEAR_SPI_PROTECT)(
+ IN CONST EFI_LEGACY_SPI_FLASH_PROTOCOL *This
+ );
+
+/**
+ Determine if the SPI range is protected.
+
+ This routine must be called at or below TPL_NOTIFY.
+ The BIOS uses this routine to verify a range in the SPI is protected.
+
+ @param[in] This Pointer to an EFI_LEGACY_SPI_FLASH_PROTOCOL data
+ structure.
+ @param[in] BiosAddress Address within a 4 KiB block to start protecting.
+ @param[in] BlocksToProtect The number of 4 KiB blocks to protect.
+
+ @retval TRUE The range is protected
+ @retval FALSE The range is not protected
+
+**/
+typedef
+BOOLEAN
+(EFIAPI *EFI_LEGACY_SPI_FLASH_PROTOCOL_IS_RANGE_PROTECTED)(
+ IN CONST EFI_LEGACY_SPI_FLASH_PROTOCOL *This,
+ IN UINT32 BiosAddress,
+ IN UINT32 BlocksToProtect
+ );
+
+/**
+ Set the next protect range register.
+
+ This routine must be called at or below TPL_NOTIFY.
+ The BIOS sets the protect range register to prevent write and erase
+ operations to a portion of the SPI NOR flash device.
+
+ @param[in] This Pointer to an EFI_LEGACY_SPI_FLASH_PROTOCOL data
+ structure.
+ @param[in] BiosAddress Address within a 4 KiB block to start protecting.
+ @param[in] BlocksToProtect The number of 4 KiB blocks to protect.
+
+ @retval EFI_SUCCESS The register was successfully updated
+ @retval EFI_ACCESS_ERROR The SPI controller is locked
+ @retval EFI_INVALID_PARAMETER BiosAddress < This->BiosBaseAddress, or
+ @retval EFI_INVALID_PARAMETER BlocksToProtect * 4 KiB
+ > This->MaximumRangeBytes, or
+ BiosAddress - This->BiosBaseAddress
+ + (BlocksToProtect * 4 KiB)
+ > This->MaximumRangeBytes
+ @retval EFI_OUT_OF_RESOURCES No protect range register available
+ @retval EFI_UNSUPPORTED Call This->SetBaseAddress because the BIOS
+ base address is not set Not a legacy SPI host
+ controller
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_LEGACY_SPI_FLASH_PROTOCOL_PROTECT_NEXT_RANGE)(
+ IN CONST EFI_LEGACY_SPI_FLASH_PROTOCOL *This,
+ IN UINT32 BiosAddress,
+ IN UINT32 BlocksToProtect
+ );
+
+/**
+ Lock the SPI controller configuration.
+
+ This routine must be called at or below TPL_NOTIFY.
+ This routine locks the SPI controller's configuration so that the software is
+ no longer able to update:
+ * Prefix table
+ * Opcode menu
+ * Opcode type table
+ * BIOS base address
+ * Protect range registers
+
+ @param[in] This Pointer to an EFI_LEGACY_SPI_FLASH_PROTOCOL data structure.
+
+ @retval EFI_SUCCESS The SPI controller was successfully locked
+ @retval EFI_ALREADY_STARTED The SPI controller was already locked
+ @retval EFI_UNSUPPORTED Not a legacy SPI host controller
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_LEGACY_SPI_FLASH_PROTOCOL_LOCK_CONTROLLER)(
+ IN CONST EFI_LEGACY_SPI_FLASH_PROTOCOL *This
+ );
+
+///
+/// The EFI_LEGACY_SPI_FLASH_PROTOCOL extends the EFI_SPI_NOR_FLASH_PROTOCOL
+/// with APls to support the legacy SPI flash controller.
+///
+struct _EFI_LEGACY_SPI_FLASH_PROTOCOL {
+ ///
+ /// This protocol manipulates the SPI NOR flash parts using a common set of
+ /// commands.
+ ///
+ EFI_SPI_NOR_FLASH_PROTOCOL FlashProtocol;
+
+ //
+ // Legacy flash (SPI host) controller support
+ //
+
+ ///
+ /// Set the BIOS base address.
+ ///
+ EFI_LEGACY_SPI_FLASH_PROTOCOL_BIOS_BASE_ADDRESS BiosBaseAddress;
+
+ ///
+ /// Clear the SPI protect range registers.
+ ///
+ EFI_LEGACY_SPI_FLASH_PROTOCOL_CLEAR_SPI_PROTECT ClearSpiProtect;
+
+ ///
+ /// Determine if the SPI range is protected.
+ ///
+ EFI_LEGACY_SPI_FLASH_PROTOCOL_IS_RANGE_PROTECTED IsRangeProtected;
+
+ ///
+ /// Set the next protect range register.
+ ///
+ EFI_LEGACY_SPI_FLASH_PROTOCOL_PROTECT_NEXT_RANGE ProtectNextRange;
+
+ ///
+ /// Lock the SPI controller configuration.
+ ///
+ EFI_LEGACY_SPI_FLASH_PROTOCOL_LOCK_CONTROLLER LockController;
+};
+
+extern EFI_GUID gEfiLegacySpiFlashProtocolGuid;
+
+#endif // __LEGACY_SPI_FLASH_PROTOCOL_H__
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/LegacySpiSmmController.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/LegacySpiSmmController.h
new file mode 100644
index 0000000000..3af48e0b61
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/LegacySpiSmmController.h
@@ -0,0 +1,30 @@
+/** @file
+ This file defines the Legacy SPI SMM Controler Protocol.
+
+ Copyright (c) 2017, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Revision Reference:
+ This Protocol was introduced in UEFI PI Specification 1.6.
+
+**/
+
+#ifndef __LEGACY_SPI_SMM_CONTROLLER_PROTOCOL_H__
+#define __LEGACY_SPI_SMM_CONTROLLER_PROTOCOL_H__
+
+#include
+
+///
+/// Global ID for the Legacy SPI SMM Controller Protocol
+///
+#define EFI_LEGACY_SPI_SMM_CONTROLLER_PROTOCOL_GUID \
+ { 0x62331b78, 0xd8d0, 0x4c8c, \
+ { 0x8c, 0xcb, 0xd2, 0x7d, 0xfe, 0x32, 0xdb, 0x9b }}
+
+typedef
+ struct _EFI_LEGACY_SPI_CONTROLLER_PROTOCOL
+EFI_LEGACY_SPI_SMM_CONTROLLER_PROTOCOL;
+
+extern EFI_GUID gEfiLegacySpiSmmControllerProtocolGuid;
+
+#endif // __LEGACY_SPI_SMM_CONTROLLER_PROTOCOL_H__
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/LegacySpiSmmFlash.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/LegacySpiSmmFlash.h
new file mode 100644
index 0000000000..80dfa9fa9c
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/LegacySpiSmmFlash.h
@@ -0,0 +1,30 @@
+/** @file
+ This file defines the Legacy SPI SMM Flash Protocol.
+
+ Copyright (c) 2017, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Revision Reference:
+ This Protocol was introduced in UEFI PI Specification 1.6.
+
+**/
+
+#ifndef __LEGACY_SPI_SMM_FLASH_PROTOCOL_H__
+#define __LEGACY_SPI_SMM_FLASH_PROTOCOL_H__
+
+#include
+
+///
+/// Global ID for the Legacy SPI SMM Flash Protocol
+///
+#define EFI_LEGACY_SPI_SMM_FLASH_PROTOCOL_GUID \
+ { 0x5e3848d4, 0x0db5, 0x4fc0, \
+ { 0x97, 0x29, 0x3f, 0x35, 0x3d, 0x4f, 0x87, 0x9f }}
+
+typedef
+ struct _EFI_LEGACY_SPI_FLASH_PROTOCOL
+EFI_LEGACY_SPI_SMM_FLASH_PROTOCOL;
+
+extern EFI_GUID gEfiLegacySpiSmmFlashProtocolGuid;
+
+#endif // __SPI_SMM_FLASH_PROTOCOL_H__
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/LoadFile.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/LoadFile.h
new file mode 100644
index 0000000000..5a341469a1
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/LoadFile.h
@@ -0,0 +1,82 @@
+/** @file
+ Load File protocol as defined in the UEFI 2.0 specification.
+
+ The load file protocol exists to supports the addition of new boot devices,
+ and to support booting from devices that do not map well to file system.
+ Network boot is done via a LoadFile protocol.
+
+ UEFI 2.0 can boot from any device that produces a LoadFile protocol.
+
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __EFI_LOAD_FILE_PROTOCOL_H__
+#define __EFI_LOAD_FILE_PROTOCOL_H__
+
+#define EFI_LOAD_FILE_PROTOCOL_GUID \
+ { \
+ 0x56EC3091, 0x954C, 0x11d2, {0x8E, 0x3F, 0x00, 0xA0, 0xC9, 0x69, 0x72, 0x3B } \
+ }
+
+///
+/// Protocol Guid defined by EFI1.1.
+///
+#define LOAD_FILE_PROTOCOL EFI_LOAD_FILE_PROTOCOL_GUID
+
+typedef struct _EFI_LOAD_FILE_PROTOCOL EFI_LOAD_FILE_PROTOCOL;
+
+///
+/// Backward-compatible with EFI1.1
+///
+typedef EFI_LOAD_FILE_PROTOCOL EFI_LOAD_FILE_INTERFACE;
+
+/**
+ Causes the driver to load a specified file.
+
+ @param This Protocol instance pointer.
+ @param FilePath The device specific path of the file to load.
+ @param BootPolicy If TRUE, indicates that the request originates from the
+ boot manager is attempting to load FilePath as a boot
+ selection. If FALSE, then FilePath must match as exact file
+ to be loaded.
+ @param BufferSize On input the size of Buffer in bytes. On output with a return
+ code of EFI_SUCCESS, the amount of data transferred to
+ Buffer. On output with a return code of EFI_BUFFER_TOO_SMALL,
+ the size of Buffer required to retrieve the requested file.
+ @param Buffer The memory buffer to transfer the file to. IF Buffer is NULL,
+ then the size of the requested file is returned in
+ BufferSize.
+
+ @retval EFI_SUCCESS The file was loaded.
+ @retval EFI_UNSUPPORTED The device does not support the provided BootPolicy
+ @retval EFI_INVALID_PARAMETER FilePath is not a valid device path, or
+ BufferSize is NULL.
+ @retval EFI_NO_MEDIA No medium was present to load the file.
+ @retval EFI_DEVICE_ERROR The file was not loaded due to a device error.
+ @retval EFI_NO_RESPONSE The remote system did not respond.
+ @retval EFI_NOT_FOUND The file was not found.
+ @retval EFI_ABORTED The file load process was manually cancelled.
+ @retval EFI_WARN_FILE_SYSTEM The resulting Buffer contains UEFI-compliant file system.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_LOAD_FILE)(
+ IN EFI_LOAD_FILE_PROTOCOL *This,
+ IN EFI_DEVICE_PATH_PROTOCOL *FilePath,
+ IN BOOLEAN BootPolicy,
+ IN OUT UINTN *BufferSize,
+ IN VOID *Buffer OPTIONAL
+ );
+
+///
+/// The EFI_LOAD_FILE_PROTOCOL is a simple protocol used to obtain files from arbitrary devices.
+///
+struct _EFI_LOAD_FILE_PROTOCOL {
+ EFI_LOAD_FILE LoadFile;
+};
+
+extern EFI_GUID gEfiLoadFileProtocolGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/LoadFile2.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/LoadFile2.h
new file mode 100644
index 0000000000..2d3a5fd165
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/LoadFile2.h
@@ -0,0 +1,78 @@
+/** @file
+ Load File protocol as defined in the UEFI 2.0 specification.
+
+ Load file protocol exists to supports the addition of new boot devices,
+ and to support booting from devices that do not map well to file system.
+ Network boot is done via a LoadFile protocol.
+
+ UEFI 2.0 can boot from any device that produces a LoadFile protocol.
+
+ Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __EFI_LOAD_FILE2_PROTOCOL_H__
+#define __EFI_LOAD_FILE2_PROTOCOL_H__
+
+#define EFI_LOAD_FILE2_PROTOCOL_GUID \
+ { \
+ 0x4006c0c1, 0xfcb3, 0x403e, {0x99, 0x6d, 0x4a, 0x6c, 0x87, 0x24, 0xe0, 0x6d } \
+ }
+
+///
+/// Protocol Guid defined by UEFI2.1.
+///
+#define LOAD_FILE2_PROTOCOL EFI_LOAD_FILE2_PROTOCOL_GUID
+
+typedef struct _EFI_LOAD_FILE2_PROTOCOL EFI_LOAD_FILE2_PROTOCOL;
+
+/**
+ Causes the driver to load a specified file.
+
+ @param This Protocol instance pointer.
+ @param FilePath The device specific path of the file to load.
+ @param BootPolicy Should always be FALSE.
+ @param BufferSize On input the size of Buffer in bytes. On output with a return
+ code of EFI_SUCCESS, the amount of data transferred to
+ Buffer. On output with a return code of EFI_BUFFER_TOO_SMALL,
+ the size of Buffer required to retrieve the requested file.
+ @param Buffer The memory buffer to transfer the file to. IF Buffer is NULL,
+ then no the size of the requested file is returned in
+ BufferSize.
+
+ @retval EFI_SUCCESS The file was loaded.
+ @retval EFI_UNSUPPORTED BootPolicy is TRUE.
+ @retval EFI_INVALID_PARAMETER FilePath is not a valid device path, or
+ BufferSize is NULL.
+ @retval EFI_NO_MEDIA No medium was present to load the file.
+ @retval EFI_DEVICE_ERROR The file was not loaded due to a device error.
+ @retval EFI_NO_RESPONSE The remote system did not respond.
+ @retval EFI_NOT_FOUND The file was not found
+ @retval EFI_ABORTED The file load process was manually canceled.
+ @retval EFI_BUFFER_TOO_SMALL The BufferSize is too small to read the current
+ directory entry. BufferSize has been updated with
+ the size needed to complete the request.
+
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_LOAD_FILE2)(
+ IN EFI_LOAD_FILE2_PROTOCOL *This,
+ IN EFI_DEVICE_PATH_PROTOCOL *FilePath,
+ IN BOOLEAN BootPolicy,
+ IN OUT UINTN *BufferSize,
+ IN VOID *Buffer OPTIONAL
+ );
+
+///
+/// The EFI_LOAD_FILE_PROTOCOL is a simple protocol used to obtain files from arbitrary devices.
+///
+struct _EFI_LOAD_FILE2_PROTOCOL {
+ EFI_LOAD_FILE2 LoadFile;
+};
+
+extern EFI_GUID gEfiLoadFile2ProtocolGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/LoadedImage.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/LoadedImage.h
new file mode 100644
index 0000000000..3a693a7248
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/LoadedImage.h
@@ -0,0 +1,82 @@
+/** @file
+ UEFI 2.0 Loaded image protocol definition.
+
+ Every EFI driver and application is passed an image handle when it is loaded.
+ This image handle will contain a Loaded Image Protocol.
+
+ Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __LOADED_IMAGE_PROTOCOL_H__
+#define __LOADED_IMAGE_PROTOCOL_H__
+
+#define EFI_LOADED_IMAGE_PROTOCOL_GUID \
+ { \
+ 0x5B1B31A1, 0x9562, 0x11d2, {0x8E, 0x3F, 0x00, 0xA0, 0xC9, 0x69, 0x72, 0x3B } \
+ }
+
+#define EFI_LOADED_IMAGE_DEVICE_PATH_PROTOCOL_GUID \
+ { \
+ 0xbc62157e, 0x3e33, 0x4fec, {0x99, 0x20, 0x2d, 0x3b, 0x36, 0xd7, 0x50, 0xdf } \
+ }
+
+///
+/// Protocol GUID defined in EFI1.1.
+///
+#define LOADED_IMAGE_PROTOCOL EFI_LOADED_IMAGE_PROTOCOL_GUID
+
+///
+/// EFI_SYSTEM_TABLE & EFI_IMAGE_UNLOAD are defined in EfiApi.h
+///
+#define EFI_LOADED_IMAGE_PROTOCOL_REVISION 0x1000
+
+///
+/// Revision defined in EFI1.1.
+///
+#define EFI_LOADED_IMAGE_INFORMATION_REVISION EFI_LOADED_IMAGE_PROTOCOL_REVISION
+
+///
+/// Can be used on any image handle to obtain information about the loaded image.
+///
+typedef struct {
+ UINT32 Revision; ///< Defines the revision of the EFI_LOADED_IMAGE_PROTOCOL structure.
+ ///< All future revisions will be backward compatible to the current revision.
+ EFI_HANDLE ParentHandle; ///< Parent image's image handle. NULL if the image is loaded directly from
+ ///< the firmware's boot manager.
+ EFI_SYSTEM_TABLE *SystemTable; ///< the image's EFI system table pointer.
+
+ //
+ // Source location of image
+ //
+ EFI_HANDLE DeviceHandle; ///< The device handle that the EFI Image was loaded from.
+ EFI_DEVICE_PATH_PROTOCOL *FilePath; ///< A pointer to the file path portion specific to DeviceHandle
+ ///< that the EFI Image was loaded from.
+ VOID *Reserved; ///< Reserved. DO NOT USE.
+
+ //
+ // Images load options
+ //
+ UINT32 LoadOptionsSize; ///< The size in bytes of LoadOptions.
+ VOID *LoadOptions; ///< A pointer to the image's binary load options.
+
+ //
+ // Location of where image was loaded
+ //
+ VOID *ImageBase; ///< The base address at which the image was loaded.
+ UINT64 ImageSize; ///< The size in bytes of the loaded image.
+ EFI_MEMORY_TYPE ImageCodeType; ///< The memory type that the code sections were loaded as.
+ EFI_MEMORY_TYPE ImageDataType; ///< The memory type that the data sections were loaded as.
+ EFI_IMAGE_UNLOAD Unload;
+} EFI_LOADED_IMAGE_PROTOCOL;
+
+//
+// For backward-compatible with EFI1.1.
+//
+typedef EFI_LOADED_IMAGE_PROTOCOL EFI_LOADED_IMAGE;
+
+extern EFI_GUID gEfiLoadedImageProtocolGuid;
+extern EFI_GUID gEfiLoadedImageDevicePathProtocolGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/ManagedNetwork.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/ManagedNetwork.h
new file mode 100644
index 0000000000..0230705da2
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/ManagedNetwork.h
@@ -0,0 +1,364 @@
+/** @file
+ EFI_MANAGED_NETWORK_SERVICE_BINDING_PROTOCOL as defined in UEFI 2.0.
+ EFI_MANAGED_NETWORK_PROTOCOL as defined in UEFI 2.0.
+
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Revision Reference:
+ This Protocol is introduced in UEFI Specification 2.0
+
+**/
+
+#ifndef __EFI_MANAGED_NETWORK_PROTOCOL_H__
+#define __EFI_MANAGED_NETWORK_PROTOCOL_H__
+
+#include
+
+#define EFI_MANAGED_NETWORK_SERVICE_BINDING_PROTOCOL_GUID \
+ { \
+ 0xf36ff770, 0xa7e1, 0x42cf, {0x9e, 0xd2, 0x56, 0xf0, 0xf2, 0x71, 0xf4, 0x4c } \
+ }
+
+#define EFI_MANAGED_NETWORK_PROTOCOL_GUID \
+ { \
+ 0x7ab33a91, 0xace5, 0x4326, { 0xb5, 0x72, 0xe7, 0xee, 0x33, 0xd3, 0x9f, 0x16 } \
+ }
+
+typedef struct _EFI_MANAGED_NETWORK_PROTOCOL EFI_MANAGED_NETWORK_PROTOCOL;
+
+typedef struct {
+ ///
+ /// Timeout value for a UEFI one-shot timer event. A packet that has not been removed
+ /// from the MNP receive queue will be dropped if its receive timeout expires.
+ ///
+ UINT32 ReceivedQueueTimeoutValue;
+ ///
+ /// Timeout value for a UEFI one-shot timer event. A packet that has not been removed
+ /// from the MNP transmit queue will be dropped if its receive timeout expires.
+ ///
+ UINT32 TransmitQueueTimeoutValue;
+ ///
+ /// Ethernet type II 16-bit protocol type in host byte order. Valid
+ /// values are zero and 1,500 to 65,535.
+ ///
+ UINT16 ProtocolTypeFilter;
+ ///
+ /// Set to TRUE to receive packets that are sent to the network
+ /// device MAC address. The startup default value is FALSE.
+ ///
+ BOOLEAN EnableUnicastReceive;
+ ///
+ /// Set to TRUE to receive packets that are sent to any of the
+ /// active multicast groups. The startup default value is FALSE.
+ ///
+ BOOLEAN EnableMulticastReceive;
+ ///
+ /// Set to TRUE to receive packets that are sent to the network
+ /// device broadcast address. The startup default value is FALSE.
+ ///
+ BOOLEAN EnableBroadcastReceive;
+ ///
+ /// Set to TRUE to receive packets that are sent to any MAC address.
+ /// The startup default value is FALSE.
+ ///
+ BOOLEAN EnablePromiscuousReceive;
+ ///
+ /// Set to TRUE to drop queued packets when the configuration
+ /// is changed. The startup default value is FALSE.
+ ///
+ BOOLEAN FlushQueuesOnReset;
+ ///
+ /// Set to TRUE to timestamp all packets when they are received
+ /// by the MNP. Note that timestamps may be unsupported in some
+ /// MNP implementations. The startup default value is FALSE.
+ ///
+ BOOLEAN EnableReceiveTimestamps;
+ ///
+ /// Set to TRUE to disable background polling in this MNP
+ /// instance. Note that background polling may not be supported in
+ /// all MNP implementations. The startup default value is FALSE,
+ /// unless background polling is not supported.
+ ///
+ BOOLEAN DisableBackgroundPolling;
+} EFI_MANAGED_NETWORK_CONFIG_DATA;
+
+typedef struct {
+ EFI_TIME Timestamp;
+ EFI_EVENT RecycleEvent;
+ UINT32 PacketLength;
+ UINT32 HeaderLength;
+ UINT32 AddressLength;
+ UINT32 DataLength;
+ BOOLEAN BroadcastFlag;
+ BOOLEAN MulticastFlag;
+ BOOLEAN PromiscuousFlag;
+ UINT16 ProtocolType;
+ VOID *DestinationAddress;
+ VOID *SourceAddress;
+ VOID *MediaHeader;
+ VOID *PacketData;
+} EFI_MANAGED_NETWORK_RECEIVE_DATA;
+
+typedef struct {
+ UINT32 FragmentLength;
+ VOID *FragmentBuffer;
+} EFI_MANAGED_NETWORK_FRAGMENT_DATA;
+
+typedef struct {
+ EFI_MAC_ADDRESS *DestinationAddress; // OPTIONAL
+ EFI_MAC_ADDRESS *SourceAddress; // OPTIONAL
+ UINT16 ProtocolType; // OPTIONAL
+ UINT32 DataLength;
+ UINT16 HeaderLength; // OPTIONAL
+ UINT16 FragmentCount;
+ EFI_MANAGED_NETWORK_FRAGMENT_DATA FragmentTable[1];
+} EFI_MANAGED_NETWORK_TRANSMIT_DATA;
+
+typedef struct {
+ ///
+ /// This Event will be signaled after the Status field is updated
+ /// by the MNP. The type of Event must be
+ /// EFI_NOTIFY_SIGNAL. The Task Priority Level (TPL) of
+ /// Event must be lower than or equal to TPL_CALLBACK.
+ ///
+ EFI_EVENT Event;
+ ///
+ /// The status that is returned to the caller at the end of the operation
+ /// to indicate whether this operation completed successfully.
+ ///
+ EFI_STATUS Status;
+ union {
+ ///
+ /// When this token is used for receiving, RxData is a pointer to the EFI_MANAGED_NETWORK_RECEIVE_DATA.
+ ///
+ EFI_MANAGED_NETWORK_RECEIVE_DATA *RxData;
+ ///
+ /// When this token is used for transmitting, TxData is a pointer to the EFI_MANAGED_NETWORK_TRANSMIT_DATA.
+ ///
+ EFI_MANAGED_NETWORK_TRANSMIT_DATA *TxData;
+ } Packet;
+} EFI_MANAGED_NETWORK_COMPLETION_TOKEN;
+
+/**
+ Returns the operational parameters for the current MNP child driver.
+
+ @param This The pointer to the EFI_MANAGED_NETWORK_PROTOCOL instance.
+ @param MnpConfigData The pointer to storage for MNP operational parameters.
+ @param SnpModeData The pointer to storage for SNP operational parameters.
+
+ @retval EFI_SUCCESS The operation completed successfully.
+ @retval EFI_INVALID_PARAMETER This is NULL.
+ @retval EFI_UNSUPPORTED The requested feature is unsupported in this MNP implementation.
+ @retval EFI_NOT_STARTED This MNP child driver instance has not been configured. The default
+ values are returned in MnpConfigData if it is not NULL.
+ @retval Other The mode data could not be read.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_MANAGED_NETWORK_GET_MODE_DATA)(
+ IN EFI_MANAGED_NETWORK_PROTOCOL *This,
+ OUT EFI_MANAGED_NETWORK_CONFIG_DATA *MnpConfigData OPTIONAL,
+ OUT EFI_SIMPLE_NETWORK_MODE *SnpModeData OPTIONAL
+ );
+
+/**
+ Sets or clears the operational parameters for the MNP child driver.
+
+ @param This The pointer to the EFI_MANAGED_NETWORK_PROTOCOL instance.
+ @param MnpConfigData The pointer to configuration data that will be assigned to the MNP
+ child driver instance. If NULL, the MNP child driver instance is
+ reset to startup defaults and all pending transmit and receive
+ requests are flushed.
+
+ @retval EFI_SUCCESS The operation completed successfully.
+ @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
+ @retval EFI_OUT_OF_RESOURCES Required system resources (usually memory) could not be
+ allocated.
+ @retval EFI_UNSUPPORTED The requested feature is unsupported in this [MNP]
+ implementation.
+ @retval EFI_DEVICE_ERROR An unexpected network or system error occurred.
+ @retval Other The MNP child driver instance has been reset to startup defaults.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_MANAGED_NETWORK_CONFIGURE)(
+ IN EFI_MANAGED_NETWORK_PROTOCOL *This,
+ IN EFI_MANAGED_NETWORK_CONFIG_DATA *MnpConfigData OPTIONAL
+ );
+
+/**
+ Translates an IP multicast address to a hardware (MAC) multicast address.
+
+ @param This The pointer to the EFI_MANAGED_NETWORK_PROTOCOL instance.
+ @param Ipv6Flag Set to TRUE to if IpAddress is an IPv6 multicast address.
+ Set to FALSE if IpAddress is an IPv4 multicast address.
+ @param IpAddress The pointer to the multicast IP address (in network byte order) to convert.
+ @param MacAddress The pointer to the resulting multicast MAC address.
+
+ @retval EFI_SUCCESS The operation completed successfully.
+ @retval EFI_INVALID_PARAMETER One of the following conditions is TRUE:
+ - This is NULL.
+ - IpAddress is NULL.
+ - *IpAddress is not a valid multicast IP address.
+ - MacAddress is NULL.
+ @retval EFI_NOT_STARTED This MNP child driver instance has not been configured.
+ @retval EFI_UNSUPPORTED The requested feature is unsupported in this MNP implementation.
+ @retval EFI_DEVICE_ERROR An unexpected network or system error occurred.
+ @retval Other The address could not be converted.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_MANAGED_NETWORK_MCAST_IP_TO_MAC)(
+ IN EFI_MANAGED_NETWORK_PROTOCOL *This,
+ IN BOOLEAN Ipv6Flag,
+ IN EFI_IP_ADDRESS *IpAddress,
+ OUT EFI_MAC_ADDRESS *MacAddress
+ );
+
+/**
+ Enables and disables receive filters for multicast address.
+
+ @param This The pointer to the EFI_MANAGED_NETWORK_PROTOCOL instance.
+ @param JoinFlag Set to TRUE to join this multicast group.
+ Set to FALSE to leave this multicast group.
+ @param MacAddress The pointer to the multicast MAC group (address) to join or leave.
+
+ @retval EFI_SUCCESS The requested operation completed successfully.
+ @retval EFI_INVALID_PARAMETER One or more of the following conditions is TRUE:
+ - This is NULL.
+ - JoinFlag is TRUE and MacAddress is NULL.
+ - *MacAddress is not a valid multicast MAC address.
+ @retval EFI_NOT_STARTED This MNP child driver instance has not been configured.
+ @retval EFI_ALREADY_STARTED The supplied multicast group is already joined.
+ @retval EFI_NOT_FOUND The supplied multicast group is not joined.
+ @retval EFI_DEVICE_ERROR An unexpected network or system error occurred.
+ @retval EFI_UNSUPPORTED The requested feature is unsupported in this MNP implementation.
+ @retval Other The requested operation could not be completed.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_MANAGED_NETWORK_GROUPS)(
+ IN EFI_MANAGED_NETWORK_PROTOCOL *This,
+ IN BOOLEAN JoinFlag,
+ IN EFI_MAC_ADDRESS *MacAddress OPTIONAL
+ );
+
+/**
+ Places asynchronous outgoing data packets into the transmit queue.
+
+ @param This The pointer to the EFI_MANAGED_NETWORK_PROTOCOL instance.
+ @param Token The pointer to a token associated with the transmit data descriptor.
+
+ @retval EFI_SUCCESS The transmit completion token was cached.
+ @retval EFI_NOT_STARTED This MNP child driver instance has not been configured.
+ @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
+ @retval EFI_ACCESS_DENIED The transmit completion token is already in the transmit queue.
+ @retval EFI_OUT_OF_RESOURCES The transmit data could not be queued due to a lack of system resources
+ (usually memory).
+ @retval EFI_DEVICE_ERROR An unexpected system or network error occurred.
+ @retval EFI_NOT_READY The transmit request could not be queued because the transmit queue is full.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_MANAGED_NETWORK_TRANSMIT)(
+ IN EFI_MANAGED_NETWORK_PROTOCOL *This,
+ IN EFI_MANAGED_NETWORK_COMPLETION_TOKEN *Token
+ );
+
+/**
+ Places an asynchronous receiving request into the receiving queue.
+
+ @param This The pointer to the EFI_MANAGED_NETWORK_PROTOCOL instance.
+ @param Token The pointer to a token associated with the receive data descriptor.
+
+ @retval EFI_SUCCESS The receive completion token was cached.
+ @retval EFI_NOT_STARTED This MNP child driver instance has not been configured.
+ @retval EFI_INVALID_PARAMETER One or more of the following conditions is TRUE:
+ - This is NULL.
+ - Token is NULL.
+ - Token.Event is NULL.
+ @retval EFI_OUT_OF_RESOURCES The transmit data could not be queued due to a lack of system resources
+ (usually memory).
+ @retval EFI_DEVICE_ERROR An unexpected system or network error occurred.
+ @retval EFI_ACCESS_DENIED The receive completion token was already in the receive queue.
+ @retval EFI_NOT_READY The receive request could not be queued because the receive queue is full.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_MANAGED_NETWORK_RECEIVE)(
+ IN EFI_MANAGED_NETWORK_PROTOCOL *This,
+ IN EFI_MANAGED_NETWORK_COMPLETION_TOKEN *Token
+ );
+
+/**
+ Aborts an asynchronous transmit or receive request.
+
+ @param This The pointer to the EFI_MANAGED_NETWORK_PROTOCOL instance.
+ @param Token The pointer to a token that has been issued by
+ EFI_MANAGED_NETWORK_PROTOCOL.Transmit() or
+ EFI_MANAGED_NETWORK_PROTOCOL.Receive(). If
+ NULL, all pending tokens are aborted.
+
+ @retval EFI_SUCCESS The asynchronous I/O request was aborted and Token.Event
+ was signaled. When Token is NULL, all pending requests were
+ aborted and their events were signaled.
+ @retval EFI_NOT_STARTED This MNP child driver instance has not been configured.
+ @retval EFI_INVALID_PARAMETER This is NULL.
+ @retval EFI_NOT_FOUND When Token is not NULL, the asynchronous I/O request was
+ not found in the transmit or receive queue. It has either completed
+ or was not issued by Transmit() and Receive().
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_MANAGED_NETWORK_CANCEL)(
+ IN EFI_MANAGED_NETWORK_PROTOCOL *This,
+ IN EFI_MANAGED_NETWORK_COMPLETION_TOKEN *Token OPTIONAL
+ );
+
+/**
+ Polls for incoming data packets and processes outgoing data packets.
+
+ @param This The pointer to the EFI_MANAGED_NETWORK_PROTOCOL instance.
+
+ @retval EFI_SUCCESS Incoming or outgoing data was processed.
+ @retval EFI_NOT_STARTED This MNP child driver instance has not been configured.
+ @retval EFI_DEVICE_ERROR An unexpected system or network error occurred.
+ @retval EFI_NOT_READY No incoming or outgoing data was processed. Consider increasing
+ the polling rate.
+ @retval EFI_TIMEOUT Data was dropped out of the transmit and/or receive queue.
+ Consider increasing the polling rate.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_MANAGED_NETWORK_POLL)(
+ IN EFI_MANAGED_NETWORK_PROTOCOL *This
+ );
+
+///
+/// The MNP is used by network applications (and drivers) to
+/// perform raw (unformatted) asynchronous network packet I/O.
+///
+struct _EFI_MANAGED_NETWORK_PROTOCOL {
+ EFI_MANAGED_NETWORK_GET_MODE_DATA GetModeData;
+ EFI_MANAGED_NETWORK_CONFIGURE Configure;
+ EFI_MANAGED_NETWORK_MCAST_IP_TO_MAC McastIpToMac;
+ EFI_MANAGED_NETWORK_GROUPS Groups;
+ EFI_MANAGED_NETWORK_TRANSMIT Transmit;
+ EFI_MANAGED_NETWORK_RECEIVE Receive;
+ EFI_MANAGED_NETWORK_CANCEL Cancel;
+ EFI_MANAGED_NETWORK_POLL Poll;
+};
+
+extern EFI_GUID gEfiManagedNetworkServiceBindingProtocolGuid;
+extern EFI_GUID gEfiManagedNetworkProtocolGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/MemoryAccept.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/MemoryAccept.h
new file mode 100644
index 0000000000..bc0d7878e6
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/MemoryAccept.h
@@ -0,0 +1,37 @@
+/** @file
+ The file provides the protocol to provide interface to accept memory.
+
+ Copyright (c) 2021 - 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef MEMORY_ACCEPT_H_
+#define MEMORY_ACCEPT_H_
+
+#define EDKII_MEMORY_ACCEPT_PROTOCOL_GUID \
+ { 0x38c74800, 0x5590, 0x4db4, { 0xa0, 0xf3, 0x67, 0x5d, 0x9b, 0x8e, 0x80, 0x26 } };
+
+typedef struct _EDKII_MEMORY_ACCEPT_PROTOCOL EDKII_MEMORY_ACCEPT_PROTOCOL;
+
+/**
+ @param This A pointer to a EDKII_MEMORY_ACCEPT_PROTOCOL.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EDKII_ACCEPT_MEMORY)(
+ IN EDKII_MEMORY_ACCEPT_PROTOCOL *This,
+ IN EFI_PHYSICAL_ADDRESS StartAddress,
+ IN UINTN Size
+ );
+
+///
+/// The EDKII_MEMORY_ACCEPT_PROTOCOL provides the ability for memory services
+/// to accept memory.
+///
+struct _EDKII_MEMORY_ACCEPT_PROTOCOL {
+ EDKII_ACCEPT_MEMORY AcceptMemory;
+};
+
+extern EFI_GUID gEdkiiMemoryAcceptProtocolGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/Metronome.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/Metronome.h
new file mode 100644
index 0000000000..f08c7f4d9e
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/Metronome.h
@@ -0,0 +1,74 @@
+/** @file
+ Metronome Architectural Protocol as defined in PI SPEC VOLUME 2 DXE
+
+ This code abstracts the DXE core to provide delay services.
+
+ Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __ARCH_PROTOCOL_METRONOME_H__
+#define __ARCH_PROTOCOL_METRONOME_H__
+
+///
+/// Global ID for the Metronome Architectural Protocol
+///
+#define EFI_METRONOME_ARCH_PROTOCOL_GUID \
+ { 0x26baccb2, 0x6f42, 0x11d4, {0xbc, 0xe7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } }
+
+///
+/// Declare forward reference for the Metronome Architectural Protocol
+///
+typedef struct _EFI_METRONOME_ARCH_PROTOCOL EFI_METRONOME_ARCH_PROTOCOL;
+
+/**
+ The WaitForTick() function waits for the number of ticks specified by
+ TickNumber from a known time source in the platform. If TickNumber of
+ ticks are detected, then EFI_SUCCESS is returned. The actual time passed
+ between entry of this function and the first tick is between 0 and
+ TickPeriod 100 nS units. If you want to guarantee that at least TickPeriod
+ time has elapsed, wait for two ticks. This function waits for a hardware
+ event to determine when a tick occurs. It is possible for interrupt
+ processing, or exception processing to interrupt the execution of the
+ WaitForTick() function. Depending on the hardware source for the ticks, it
+ is possible for a tick to be missed. This function cannot guarantee that
+ ticks will not be missed. If a timeout occurs waiting for the specified
+ number of ticks, then EFI_TIMEOUT is returned.
+
+ @param This The EFI_METRONOME_ARCH_PROTOCOL instance.
+ @param TickNumber Number of ticks to wait.
+
+ @retval EFI_SUCCESS The wait for the number of ticks specified by TickNumber
+ succeeded.
+ @retval EFI_TIMEOUT A timeout occurred waiting for the specified number of ticks.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_METRONOME_WAIT_FOR_TICK)(
+ IN EFI_METRONOME_ARCH_PROTOCOL *This,
+ IN UINT32 TickNumber
+ );
+
+///
+/// This protocol provides access to a known time source in the platform to the
+/// core. The core uses this known time source to produce core services that
+/// require calibrated delays.
+///
+struct _EFI_METRONOME_ARCH_PROTOCOL {
+ EFI_METRONOME_WAIT_FOR_TICK WaitForTick;
+
+ ///
+ /// The period of platform's known time source in 100 nS units.
+ /// This value on any platform must be at least 10 uS, and must not
+ /// exceed 200 uS. The value in this field is a constant that must
+ /// not be modified after the Metronome architectural protocol is
+ /// installed. All consumers must treat this as a read-only field.
+ ///
+ UINT32 TickPeriod;
+};
+
+extern EFI_GUID gEfiMetronomeArchProtocolGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/MmAccess.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/MmAccess.h
new file mode 100644
index 0000000000..a188576ec1
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/MmAccess.h
@@ -0,0 +1,125 @@
+/** @file
+ EFI MM Access Protocol as defined in the PI 1.5 specification.
+
+ This protocol is used to control the visibility of the MMRAM on the platform.
+ It abstracts the location and characteristics of MMRAM. The expectation is
+ that the north bridge or memory controller would publish this protocol.
+
+ The principal functionality found in the memory controller includes the following:
+ - Exposing the MMRAM to all non-MM agents, or the "open" state
+ - Shrouding the MMRAM to all but the MM agents, or the "closed" state
+ - Preserving the system integrity, or "locking" the MMRAM, such that the settings cannot be
+ perturbed by either boot service or runtime agents
+
+ Copyright (c) 2017, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _MM_ACCESS_H_
+#define _MM_ACCESS_H_
+
+#define EFI_MM_ACCESS_PROTOCOL_GUID \
+ { \
+ 0xc2702b74, 0x800c, 0x4131, {0x87, 0x46, 0x8f, 0xb5, 0xb8, 0x9c, 0xe4, 0xac } \
+ }
+
+typedef struct _EFI_MM_ACCESS_PROTOCOL EFI_MM_ACCESS_PROTOCOL;
+
+/**
+ Opens the MMRAM area to be accessible by a boot-service driver.
+
+ This function "opens" MMRAM so that it is visible while not inside of MM. The function should
+ return EFI_UNSUPPORTED if the hardware does not support hiding of MMRAM. The function
+ should return EFI_DEVICE_ERROR if the MMRAM configuration is locked.
+
+ @param[in] This The EFI_MM_ACCESS_PROTOCOL instance.
+
+ @retval EFI_SUCCESS The operation was successful.
+ @retval EFI_UNSUPPORTED The system does not support opening and closing of MMRAM.
+ @retval EFI_DEVICE_ERROR MMRAM cannot be opened, perhaps because it is locked.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_MM_OPEN)(
+ IN EFI_MM_ACCESS_PROTOCOL *This
+ );
+
+/**
+ Inhibits access to the MMRAM.
+
+ This function "closes" MMRAM so that it is not visible while outside of MM. The function should
+ return EFI_UNSUPPORTED if the hardware does not support hiding of MMRAM.
+
+ @param[in] This The EFI_MM_ACCESS_PROTOCOL instance.
+
+ @retval EFI_SUCCESS The operation was successful.
+ @retval EFI_UNSUPPORTED The system does not support opening and closing of MMRAM.
+ @retval EFI_DEVICE_ERROR MMRAM cannot be closed.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_MM_CLOSE)(
+ IN EFI_MM_ACCESS_PROTOCOL *This
+ );
+
+/**
+ Inhibits access to the MMRAM.
+
+ This function prohibits access to the MMRAM region. This function is usually implemented such
+ that it is a write-once operation.
+
+ @param[in] This The EFI_MM_ACCESS_PROTOCOL instance.
+
+ @retval EFI_SUCCESS The device was successfully locked.
+ @retval EFI_UNSUPPORTED The system does not support locking of MMRAM.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_MM_LOCK)(
+ IN EFI_MM_ACCESS_PROTOCOL *This
+ );
+
+/**
+ Queries the memory controller for the possible regions that will support MMRAM.
+
+ @param[in] This The EFI_MM_ACCESS_PROTOCOL instance.
+ @param[in,out] MmramMapSize A pointer to the size, in bytes, of the MmramMemoryMap buffer.
+ @param[in,out] MmramMap A pointer to the buffer in which firmware places the current memory map.
+
+ @retval EFI_SUCCESS The chipset supported the given resource.
+ @retval EFI_BUFFER_TOO_SMALL The MmramMap parameter was too small. The current buffer size
+ needed to hold the memory map is returned in MmramMapSize.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_MM_CAPABILITIES)(
+ IN CONST EFI_MM_ACCESS_PROTOCOL *This,
+ IN OUT UINTN *MmramMapSize,
+ IN OUT EFI_MMRAM_DESCRIPTOR *MmramMap
+ );
+
+///
+/// EFI MM Access Protocol is used to control the visibility of the MMRAM on the platform.
+/// It abstracts the location and characteristics of MMRAM. The platform should report all
+/// MMRAM via EFI_MM_ACCESS_PROTOCOL. The expectation is that the north bridge or memory
+/// controller would publish this protocol.
+///
+struct _EFI_MM_ACCESS_PROTOCOL {
+ EFI_MM_OPEN Open;
+ EFI_MM_CLOSE Close;
+ EFI_MM_LOCK Lock;
+ EFI_MM_CAPABILITIES GetCapabilities;
+ ///
+ /// Indicates the current state of the MMRAM. Set to TRUE if MMRAM is locked.
+ ///
+ BOOLEAN LockState;
+ ///
+ /// Indicates the current state of the MMRAM. Set to TRUE if MMRAM is open.
+ ///
+ BOOLEAN OpenState;
+};
+
+extern EFI_GUID gEfiMmAccessProtocolGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/MmBase.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/MmBase.h
new file mode 100644
index 0000000000..d9fc596f10
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/MmBase.h
@@ -0,0 +1,80 @@
+/** @file
+ EFI MM Base Protocol as defined in the PI 1.5 specification.
+
+ This protocol is utilized by all MM drivers to locate the MM infrastructure services and determine
+ whether the driver is being invoked inside MMRAM or outside of MMRAM.
+
+ Copyright (c) 2017, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _MM_BASE_H_
+#define _MM_BASE_H_
+
+#include
+
+#define EFI_MM_BASE_PROTOCOL_GUID \
+ { \
+ 0xf4ccbfb7, 0xf6e0, 0x47fd, {0x9d, 0xd4, 0x10, 0xa8, 0xf1, 0x50, 0xc1, 0x91 } \
+ }
+
+typedef struct _EFI_MM_BASE_PROTOCOL EFI_MM_BASE_PROTOCOL;
+
+/**
+ Service to indicate whether the driver is currently executing in the MM Initialization phase.
+
+ This service is used to indicate whether the driver is currently executing in the MM Initialization
+ phase. For MM drivers, this will return TRUE in InMmram while inside the driver's entry point and
+ otherwise FALSE. For combination MM/DXE drivers, this will return FALSE in the DXE launch. For the
+ MM launch, it behaves as an MM driver.
+
+ @param[in] This The EFI_MM_BASE_PROTOCOL instance.
+ @param[out] InMmram Pointer to a Boolean which, on return, indicates that the driver is
+ currently executing inside of MMRAM (TRUE) or outside of MMRAM (FALSE).
+
+ @retval EFI_SUCCESS The call returned successfully.
+ @retval EFI_INVALID_PARAMETER InMmram was NULL.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_MM_INSIDE_OUT)(
+ IN CONST EFI_MM_BASE_PROTOCOL *This,
+ OUT BOOLEAN *InMmram
+ )
+;
+
+/**
+ Returns the location of the Management Mode Service Table (MMST).
+
+ This function returns the location of the Management Mode Service Table (MMST). The use of the
+ API is such that a driver can discover the location of the MMST in its entry point and then cache it in
+ some driver global variable so that the MMST can be invoked in subsequent handlers.
+
+ @param[in] This The EFI_MM_BASE_PROTOCOL instance.
+ @param[in,out] Mmst On return, points to a pointer to the Management Mode Service Table (MMST).
+
+ @retval EFI_SUCCESS The operation was successful.
+ @retval EFI_INVALID_PARAMETER Mmst was invalid.
+ @retval EFI_UNSUPPORTED Not in MM.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_MM_GET_MMST_LOCATION)(
+ IN CONST EFI_MM_BASE_PROTOCOL *This,
+ IN OUT EFI_MM_SYSTEM_TABLE **Mmst
+ )
+;
+
+///
+/// EFI MM Base Protocol is utilized by all MM drivers to locate the MM infrastructure
+/// services and determine whether the driver is being invoked inside MMRAM or outside of MMRAM.
+///
+struct _EFI_MM_BASE_PROTOCOL {
+ EFI_MM_INSIDE_OUT InMm;
+ EFI_MM_GET_MMST_LOCATION GetMmstLocation;
+};
+
+extern EFI_GUID gEfiMmBaseProtocolGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/MmCommunication.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/MmCommunication.h
new file mode 100644
index 0000000000..ad96aa8eb5
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/MmCommunication.h
@@ -0,0 +1,86 @@
+/** @file
+ EFI MM Communication Protocol as defined in the PI 1.5 specification.
+
+ This protocol provides a means of communicating between drivers outside of MM and MMI
+ handlers inside of MM.
+
+ Copyright (c) 2017, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _MM_COMMUNICATION_H_
+#define _MM_COMMUNICATION_H_
+
+#pragma pack(1)
+
+///
+/// To avoid confusion in interpreting frames, the communication buffer should always
+/// begin with EFI_MM_COMMUNICATE_HEADER
+///
+typedef struct {
+ ///
+ /// Allows for disambiguation of the message format.
+ ///
+ EFI_GUID HeaderGuid;
+ ///
+ /// Describes the size of Data (in bytes) and does not include the size of the header.
+ ///
+ UINTN MessageLength;
+ ///
+ /// Designates an array of bytes that is MessageLength in size.
+ ///
+ UINT8 Data[1];
+} EFI_MM_COMMUNICATE_HEADER;
+
+#pragma pack()
+
+#define EFI_MM_COMMUNICATION_PROTOCOL_GUID \
+ { \
+ 0xc68ed8e2, 0x9dc6, 0x4cbd, { 0x9d, 0x94, 0xdb, 0x65, 0xac, 0xc5, 0xc3, 0x32 } \
+ }
+
+typedef struct _EFI_MM_COMMUNICATION_PROTOCOL EFI_MM_COMMUNICATION_PROTOCOL;
+
+/**
+ Communicates with a registered handler.
+
+ This function provides a service to send and receive messages from a registered UEFI service.
+
+ @param[in] This The EFI_MM_COMMUNICATION_PROTOCOL instance.
+ @param[in] CommBuffer A pointer to the buffer to convey into MMRAM.
+ @param[in] CommSize The size of the data buffer being passed in. On exit, the size of data
+ being returned. Zero if the handler does not wish to reply with any data.
+ This parameter is optional and may be NULL.
+
+ @retval EFI_SUCCESS The message was successfully posted.
+ @retval EFI_INVALID_PARAMETER The CommBuffer was NULL.
+ @retval EFI_BAD_BUFFER_SIZE The buffer is too large for the MM implementation.
+ If this error is returned, the MessageLength field
+ in the CommBuffer header or the integer pointed by
+ CommSize, are updated to reflect the maximum payload
+ size the implementation can accommodate.
+ @retval EFI_ACCESS_DENIED The CommunicateBuffer parameter or CommSize parameter,
+ if not omitted, are in address range that cannot be
+ accessed by the MM environment.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_MM_COMMUNICATE)(
+ IN CONST EFI_MM_COMMUNICATION_PROTOCOL *This,
+ IN OUT VOID *CommBuffer,
+ IN OUT UINTN *CommSize OPTIONAL
+ );
+
+///
+/// EFI MM Communication Protocol provides runtime services for communicating
+/// between DXE drivers and a registered MMI handler.
+///
+struct _EFI_MM_COMMUNICATION_PROTOCOL {
+ EFI_MM_COMMUNICATE Communicate;
+};
+
+extern EFI_GUID gEfiMmCommunicationProtocolGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/MmCommunication2.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/MmCommunication2.h
new file mode 100644
index 0000000000..b63d120c34
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/MmCommunication2.h
@@ -0,0 +1,69 @@
+/** @file
+ EFI MM Communication Protocol 2 as defined in the PI 1.7 errata A specification.
+
+ This protocol provides a means of communicating between drivers outside of MM and MMI
+ handlers inside of MM.
+
+ Copyright (c) 2017, Intel Corporation. All rights reserved.
+ Copyright (c) 2019, Arm Limited. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _MM_COMMUNICATION2_H_
+#define _MM_COMMUNICATION2_H_
+
+#include
+
+#define EFI_MM_COMMUNICATION2_PROTOCOL_GUID \
+ { \
+ 0x378daedc, 0xf06b, 0x4446, { 0x83, 0x14, 0x40, 0xab, 0x93, 0x3c, 0x87, 0xa3 } \
+ }
+
+typedef struct _EFI_MM_COMMUNICATION2_PROTOCOL EFI_MM_COMMUNICATION2_PROTOCOL;
+
+/**
+ Communicates with a registered handler.
+
+ This function provides a service to send and receive messages from a registered UEFI service.
+
+ @param[in] This The EFI_MM_COMMUNICATION_PROTOCOL instance.
+ @param[in, out] CommBufferPhysical Physical address of the MM communication buffer
+ @param[in, out] CommBufferVirtual Virtual address of the MM communication buffer
+ @param[in, out] CommSize The size of the data buffer being passed in. On exit, the
+ size of data being returned. Zero if the handler does not
+ wish to reply with any data. This parameter is optional
+ and may be NULL.
+
+ @retval EFI_SUCCESS The message was successfully posted.
+ @retval EFI_INVALID_PARAMETER CommBufferPhysical was NULL or CommBufferVirtual was NULL.
+ @retval EFI_BAD_BUFFER_SIZE The buffer is too large for the MM implementation.
+ If this error is returned, the MessageLength field
+ in the CommBuffer header or the integer pointed by
+ CommSize, are updated to reflect the maximum payload
+ size the implementation can accommodate.
+ @retval EFI_ACCESS_DENIED The CommunicateBuffer parameter or CommSize parameter,
+ if not omitted, are in address range that cannot be
+ accessed by the MM environment.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_MM_COMMUNICATE2)(
+ IN CONST EFI_MM_COMMUNICATION2_PROTOCOL *This,
+ IN OUT VOID *CommBufferPhysical,
+ IN OUT VOID *CommBufferVirtual,
+ IN OUT UINTN *CommSize OPTIONAL
+ );
+
+///
+/// EFI MM Communication Protocol provides runtime services for communicating
+/// between DXE drivers and a registered MMI handler.
+///
+struct _EFI_MM_COMMUNICATION2_PROTOCOL {
+ EFI_MM_COMMUNICATE2 Communicate;
+};
+
+extern EFI_GUID gEfiMmCommunication2ProtocolGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/MmConfiguration.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/MmConfiguration.h
new file mode 100644
index 0000000000..77ccaaa9ee
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/MmConfiguration.h
@@ -0,0 +1,63 @@
+/** @file
+ EFI MM Configuration Protocol as defined in the PI 1.5 specification.
+
+ This protocol is used to:
+ 1) report the portions of MMRAM regions which cannot be used for the MMRAM heap.
+ 2) register the MM Foundation entry point with the processor code. The entry
+ point will be invoked by the MM processor entry code.
+
+ Copyright (c) 2017, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _MM_CONFIGURATION_H_
+#define _MM_CONFIGURATION_H_
+
+#include
+
+#define EFI_MM_CONFIGURATION_PROTOCOL_GUID \
+ { \
+ 0x26eeb3de, 0xb689, 0x492e, {0x80, 0xf0, 0xbe, 0x8b, 0xd7, 0xda, 0x4b, 0xa7 } \
+ }
+
+typedef struct _EFI_MM_CONFIGURATION_PROTOCOL EFI_MM_CONFIGURATION_PROTOCOL;
+
+/**
+ Register the MM Foundation entry point.
+
+ This function registers the MM Foundation entry point with the processor code. This entry point
+ will be invoked by the MM Processor entry code.
+
+ @param[in] This The EFI_MM_CONFIGURATION_PROTOCOL instance.
+ @param[in] MmEntryPoint MM Foundation entry point.
+
+ @retval EFI_SUCCESS Success to register MM Entry Point.
+ @retval EFI_INVALID_PARAMETER MmEntryPoint is NULL.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_MM_REGISTER_MM_ENTRY)(
+ IN CONST EFI_MM_CONFIGURATION_PROTOCOL *This,
+ IN EFI_MM_ENTRY_POINT MmEntryPoint
+ );
+
+///
+/// The EFI MM Configuration Protocol is a mandatory protocol published by a DXE CPU driver to
+/// indicate which areas within MMRAM are reserved for use by the CPU for any purpose,
+/// such as stack, save state or MM entry point.
+///
+/// The RegistermmEntry() function allows the MM IPL DXE driver to register the MM
+/// Foundation entry point with the MM entry vector code.
+///
+struct _EFI_MM_CONFIGURATION_PROTOCOL {
+ ///
+ /// A pointer to an array MMRAM ranges used by the initial MM entry code.
+ ///
+ EFI_MM_RESERVED_MMRAM_REGION *MmramReservedRegions;
+ EFI_MM_REGISTER_MM_ENTRY RegisterMmEntry;
+};
+
+extern EFI_GUID gEfiMmConfigurationProtocolGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/MmControl.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/MmControl.h
new file mode 100644
index 0000000000..18b7e2324e
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/MmControl.h
@@ -0,0 +1,99 @@
+/** @file
+ EFI MM Control Protocol as defined in the PI 1.5 specification.
+
+ This protocol is used initiate synchronous MMI activations. This protocol could be published by a
+ processor driver to abstract the MMI IPI or a driver which abstracts the ASIC that is supporting the
+ APM port. Because of the possibility of performing MMI IPI transactions, the ability to generate this
+ event from a platform chipset agent is an optional capability for both IA-32 and x64-based systems.
+
+ The EFI_MM_CONTROL_PROTOCOL is produced by a runtime driver. It provides an
+ abstraction of the platform hardware that generates an MMI. There are often I/O ports that, when
+ accessed, will generate the MMI. Also, the hardware optionally supports the periodic generation of
+ these signals.
+
+ Copyright (c) 2017, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _MM_CONTROL_H_
+#define _MM_CONTROL_H_
+
+#include
+
+#define EFI_MM_CONTROL_PROTOCOL_GUID \
+ { \
+ 0x843dc720, 0xab1e, 0x42cb, {0x93, 0x57, 0x8a, 0x0, 0x78, 0xf3, 0x56, 0x1b} \
+ }
+
+typedef struct _EFI_MM_CONTROL_PROTOCOL EFI_MM_CONTROL_PROTOCOL;
+typedef UINTN EFI_MM_PERIOD;
+
+/**
+ Invokes MMI activation from either the preboot or runtime environment.
+
+ This function generates an MMI.
+
+ @param[in] This The EFI_MM_CONTROL_PROTOCOL instance.
+ @param[in,out] CommandPort The value written to the command port.
+ @param[in,out] DataPort The value written to the data port.
+ @param[in] Periodic Optional mechanism to engender a periodic stream.
+ @param[in] ActivationInterval Optional parameter to repeat at this period one
+ time or, if the Periodic Boolean is set, periodically.
+
+ @retval EFI_SUCCESS The MMI/PMI has been engendered.
+ @retval EFI_DEVICE_ERROR The timing is unsupported.
+ @retval EFI_INVALID_PARAMETER The activation period is unsupported.
+ @retval EFI_INVALID_PARAMETER The last periodic activation has not been cleared.
+ @retval EFI_NOT_STARTED The MM base service has not been initialized.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_MM_ACTIVATE)(
+ IN CONST EFI_MM_CONTROL_PROTOCOL *This,
+ IN OUT UINT8 *CommandPort OPTIONAL,
+ IN OUT UINT8 *DataPort OPTIONAL,
+ IN BOOLEAN Periodic OPTIONAL,
+ IN UINTN ActivationInterval OPTIONAL
+ );
+
+/**
+ Clears any system state that was created in response to the Trigger() call.
+
+ This function acknowledges and causes the deassertion of the MMI activation source.
+
+ @param[in] This The EFI_MM_CONTROL_PROTOCOL instance.
+ @param[in] Periodic Optional parameter to repeat at this period one time
+
+ @retval EFI_SUCCESS The MMI/PMI has been engendered.
+ @retval EFI_DEVICE_ERROR The source could not be cleared.
+ @retval EFI_INVALID_PARAMETER The service did not support the Periodic input argument.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_MM_DEACTIVATE)(
+ IN CONST EFI_MM_CONTROL_PROTOCOL *This,
+ IN BOOLEAN Periodic OPTIONAL
+ );
+
+///
+/// The EFI_MM_CONTROL_PROTOCOL is produced by a runtime driver. It provides an
+/// abstraction of the platform hardware that generates an MMI. There are often I/O ports that, when
+/// accessed, will generate the MMI. Also, the hardware optionally supports the periodic generation of
+/// these signals.
+///
+struct _EFI_MM_CONTROL_PROTOCOL {
+ EFI_MM_ACTIVATE Trigger;
+ EFI_MM_DEACTIVATE Clear;
+ ///
+ /// Minimum interval at which the platform can set the period. A maximum is not
+ /// specified in that the MM infrastructure code can emulate a maximum interval that is
+ /// greater than the hardware capabilities by using software emulation in the MM
+ /// infrastructure code.
+ ///
+ EFI_MM_PERIOD MinimumTriggerPeriod;
+};
+
+extern EFI_GUID gEfiMmControlProtocolGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/MmCpu.h b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/MmCpu.h
new file mode 100644
index 0000000000..a40ad53648
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202302/MdePkg/Include/Protocol/MmCpu.h
@@ -0,0 +1,239 @@
+/** @file
+ EFI MM CPU Protocol as defined in the PI 1.5 specification.
+
+ This protocol allows MM drivers to access architecture-standard registers from any of the CPU
+ save state areas. In some cases, difference processors provide the same information in the save state,
+ but not in the same format. These so-called pseudo-registers provide this information in a standard
+ format.
+
+ Copyright (c) 2017, Intel Corporation. All rights reserved.