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nyans: reduce code duplication in bootblock and romstages

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this change reduces the code duplication of the bootblock and the romstages for
Nyans.

BUG=none
TEST=Built Nyan, Big, and Blaze. Ran faft on Blaze.
BRANCH=none
Original-Signed-off-by: dnojiri@chromium.org (Daisuke Nojiri)
Original-Change-Id: Ieb9dac3b061a2cf46c63afb2f31eb67ab391ea1a
Original-Reviewed-on: https://chromium-review.googlesource.com/214050
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Original-Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org>
Original-Tested-by: Daisuke Nojiri <dnojiri@chromium.org>

(cherry picked from commit f3413d39458f03895fe4963a41285f71d81bcf5f)
Signed-off-by: Aaron Durbin <adurbin@chromium.org>

Change-Id: I912f63b12321aa26a7add302fc8a6c4e607330ef
Reviewed-on: http://review.coreboot.org/8880
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Daisuke Nojiri
2014-08-27 11:48:03 -07:00
committed by Aaron Durbin
parent dad16b1c58
commit 1b05d887d7
16 changed files with 460 additions and 479 deletions
Download Patch File Download Diff File Expand all files Collapse all files

79
src/soc/nvidia/tegra124/bootblock.c
View File

@@ -25,81 +25,11 @@
#include <console/console.h>
#include <soc/clock.h>
#include <soc/nvidia/tegra/apbmisc.h>
#include <soc/nvidia/tegra124/early_configs.h>
#include <vendorcode/google/chromeos/chromeos.h>
#include "pinmux.h"
#include "power.h"
#include "verstage.h"
#include <soc/addressmap.h>
#include <soc/nvidia/tegra/i2c.h>
#include <soc/nvidia/tegra124/gpio.h>
#include <vendorcode/google/chromeos/chromeos.h>
static struct clk_rst_ctlr *clk_rst = (void *)TEGRA_CLK_RST_BASE;
static void setup_pinmux(void)
{
// Write protect.
gpio_input_pullup(GPIO(R1));
// Recovery mode.
gpio_input_pullup(GPIO(Q7));
// Lid switch.
gpio_input_pullup(GPIO(R4));
// Power switch.
gpio_input_pullup(GPIO(Q0));
// Developer mode.
gpio_input_pullup(GPIO(Q6));
// EC in RW.
gpio_input_pullup(GPIO(U4));
// route PU4/5 to GMI to remove conflict w/PWM1/2.
pinmux_set_config(PINMUX_GPIO_PU4_INDEX, PINMUX_GPIO_PU4_FUNC_NOR);
pinmux_set_config(PINMUX_GPIO_PU5_INDEX, PINMUX_GPIO_PU5_FUNC_NOR);
// SOC and TPM reset GPIO, active low.
gpio_output(GPIO(I5), 1);
// SPI1 MOSI
pinmux_set_config(PINMUX_ULPI_CLK_INDEX, PINMUX_ULPI_CLK_FUNC_SPI1 |
PINMUX_PULL_NONE |
PINMUX_INPUT_ENABLE);
// SPI1 MISO
pinmux_set_config(PINMUX_ULPI_DIR_INDEX, PINMUX_ULPI_DIR_FUNC_SPI1 |
PINMUX_PULL_NONE |
PINMUX_INPUT_ENABLE);
// SPI1 SCLK
pinmux_set_config(PINMUX_ULPI_NXT_INDEX, PINMUX_ULPI_NXT_FUNC_SPI1 |
PINMUX_PULL_NONE |
PINMUX_INPUT_ENABLE);
// SPI1 CS0
pinmux_set_config(PINMUX_ULPI_STP_INDEX, PINMUX_ULPI_STP_FUNC_SPI1 |
PINMUX_PULL_NONE |
PINMUX_INPUT_ENABLE);
// I2C3 (cam) clock.
pinmux_set_config(PINMUX_CAM_I2C_SCL_INDEX,
PINMUX_CAM_I2C_SCL_FUNC_I2C3 | PINMUX_INPUT_ENABLE);
// I2C3 (cam) data.
pinmux_set_config(PINMUX_CAM_I2C_SDA_INDEX,
PINMUX_CAM_I2C_SDA_FUNC_I2C3 | PINMUX_INPUT_ENABLE);
// switch unused pin to GPIO
gpio_set_mode(GPIO(X3), GPIO_MODE_GPIO);
gpio_set_mode(GPIO(X4), GPIO_MODE_GPIO);
gpio_set_mode(GPIO(X5), GPIO_MODE_GPIO);
gpio_set_mode(GPIO(X6), GPIO_MODE_GPIO);
gpio_set_mode(GPIO(X7), GPIO_MODE_GPIO);
gpio_set_mode(GPIO(W3), GPIO_MODE_GPIO);
}
static void configure_ec_spi_bus(void)
{
clock_configure_source(sbc1, CLK_M, 3000);
}
static void configure_tpm_i2c_bus(void)
{
clock_configure_i2c_scl_freq(i2c3, PLLP, 400);
i2c_init(2);
}
void main(void)
{
@@ -144,10 +74,7 @@ void main(void)
PINMUX_INPUT_ENABLE);
if (IS_ENABLED(CONFIG_VBOOT2_VERIFY_FIRMWARE)) {
clock_enable_clear_reset(0, CLK_H_SBC1, CLK_U_I2C3, 0, 0, 0);
setup_pinmux();
configure_ec_spi_bus();
configure_tpm_i2c_bus();
early_mainboard_init();
entry = (void *)verstage_vboot_main;
} else
entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/romstage");