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nyans: reduce code duplication in bootblock and romstages

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this change reduces the code duplication of the bootblock and the romstages for
Nyans.

BUG=none
TEST=Built Nyan, Big, and Blaze. Ran faft on Blaze.
BRANCH=none
Original-Signed-off-by: dnojiri@chromium.org (Daisuke Nojiri)
Original-Change-Id: Ieb9dac3b061a2cf46c63afb2f31eb67ab391ea1a
Original-Reviewed-on: https://chromium-review.googlesource.com/214050
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Original-Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org>
Original-Tested-by: Daisuke Nojiri <dnojiri@chromium.org>

(cherry picked from commit f3413d39458f03895fe4963a41285f71d81bcf5f)
Signed-off-by: Aaron Durbin <adurbin@chromium.org>

Change-Id: I912f63b12321aa26a7add302fc8a6c4e607330ef
Reviewed-on: http://review.coreboot.org/8880
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Daisuke Nojiri
2014-08-27 11:48:03 -07:00
committed by Aaron Durbin
parent dad16b1c58
commit 1b05d887d7
16 changed files with 460 additions and 479 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/vendorcode/google/chromeos/Makefile.inc
View File

@ -101,7 +101,7 @@ VERSTAGE_LIB = $(obj)/vendorcode/google/chromeos/verstage.a
INCLUDES += -I$(VB_SOURCE)/firmware/2lib/include
INCLUDES += -I$(VB_SOURCE)/firmware/include
verstage-y += vboot_main.c fmap.c chromeos.c
verstage-y += verstage.c fmap.c chromeos.c
verstage-y += antirollback.c vbnv_ec.c
romstage-y += vboot_handoff.c

74
src/vendorcode/google/chromeos/vboot_main.c → src/vendorcode/google/chromeos/verstage.c
View File

@ -3,6 +3,7 @@
#include <antirollback.h>
#include <arch/exception.h>
#include <arch/stages.h>
#include <soc/nvidia/tegra124/cache.h>
#include <cbfs.h>
#include <console/console.h>
#include <console/vtxprintf.h>
@ -123,7 +124,7 @@ static void recovery(void)
if (entry != (void *)-1)
stage_exit(entry);
for(;;);
for (;;);
}
static int hash_body(struct vb2_context *ctx, struct vboot_region *fw_main)
@ -135,13 +136,12 @@ static int hash_body(struct vb2_context *ctx, struct vboot_region *fw_main)
int rv;
expected_size = fw_main->size;
offset= fw_main->offset_addr;
offset = fw_main->offset_addr;
/* Start the body hash */
rv = vb2api_init_hash(ctx, VB2_HASH_TAG_FW_BODY, &expected_size);
if (rv) {
if (rv)
return rv;
}
/* Extend over the body */
while (expected_size) {
@ -157,21 +157,20 @@ static int hash_body(struct vb2_context *ctx, struct vboot_region *fw_main)
return rv;
expected_size -= block_size;
offset+= block_size;
offset += block_size;
}
/* Check the result */
rv = vb2api_check_hash(ctx);
if (rv) {
if (rv)
return rv;
}
return VB2_SUCCESS;
}
static int locate_fw_components(struct vb2_context *ctx,
struct vboot_region *fw_main,
struct components *fw_info)
struct vboot_region *fw_main,
struct components *fw_info)
{
if (is_slot_a(ctx))
locate_region("FW_MAIN_A", fw_main);
@ -181,15 +180,15 @@ static int locate_fw_components(struct vb2_context *ctx,
return 1;
if (vboot_get_region(fw_main->offset_addr,
sizeof(*fw_info), fw_info) == NULL)
sizeof(*fw_info), fw_info) == NULL)
return 1;
return 0;
}
static struct cbfs_stage *load_stage(struct vb2_context *ctx,
int stage_index,
struct vboot_region *fw_main,
struct components *fw_info)
int stage_index,
struct vboot_region *fw_main,
struct components *fw_info)
{
struct cbfs_stage *stage;
uint32_t fc_addr;
@ -221,53 +220,15 @@ static void enter_stage(struct cbfs_stage *stage)
memset((void *) (uintptr_t)stage->load, 0, stage->memlen);
if (cbfs_decompress(stage->compression,
(unsigned char *)stage + sizeof(*stage),
(void *) (uintptr_t) stage->load,
stage->len))
(unsigned char *)stage + sizeof(*stage),
(void *) (uintptr_t) stage->load,
stage->len))
return;
VBDEBUG("Jumping to entry @%llx.\n", stage->entry);
stage_exit((void *)(uintptr_t)stage->entry);
}
enum {
L2CTLR_ECC_PARITY = 0x1 << 21,
L2CTLR_TAG_RAM_LATENCY_MASK = 0x7 << 6,
L2CTLR_TAG_RAM_LATENCY_CYCLES_3 = 2 << 6,
L2CTLR_DATA_RAM_LATENCY_MASK = 0x7 << 0,
L2CTLR_DATA_RAM_LATENCY_CYCLES_3 = 2 << 0
};
enum {
L2ACTLR_FORCE_L2_LOGIC_CLOCK_ENABLE_ACTIVE = 0x1 << 27,
L2ACTLR_ENABLE_HAZARD_DETECT_TIMEOUT = 0x1 << 7,
L2ACTLR_DISABLE_CLEAN_EVICT_PUSH_EXTERNAL = 0x1 << 3
};
/* Configures L2 Control Register to use 3 cycles for DATA/TAG RAM latency. */
static void configure_l2ctlr(void)
{
uint32_t val;
val = read_l2ctlr();
val &= ~(L2CTLR_DATA_RAM_LATENCY_MASK | L2CTLR_TAG_RAM_LATENCY_MASK);
val |= (L2CTLR_DATA_RAM_LATENCY_CYCLES_3 | L2CTLR_TAG_RAM_LATENCY_CYCLES_3 |
L2CTLR_ECC_PARITY);
write_l2ctlr(val);
}
/* Configures L2 Auxiliary Control Register for Cortex A15. */
static void configure_l2actlr(void)
{
uint32_t val;
val = read_l2actlr();
val |= (L2ACTLR_DISABLE_CLEAN_EVICT_PUSH_EXTERNAL |
L2ACTLR_ENABLE_HAZARD_DETECT_TIMEOUT |
L2ACTLR_FORCE_L2_LOGIC_CLOCK_ENABLE_ACTIVE);
write_l2actlr(val);
}
static void enable_cache(void)
{
mmu_init();
@ -313,8 +274,7 @@ void __attribute__((noinline)) select_firmware(void)
int rv;
/* Do minimum to enable cache and run vboot at full speed */
configure_l2ctlr();
configure_l2actlr();
configure_l2_cache();
console_init();
exception_init();
enable_cache();
@ -395,5 +355,5 @@ void __attribute__((noinline)) select_firmware(void)
/* Shouldn't reach here */
VBDEBUG("Halting\n");
for(;;);
for (;;);
}