soc/{samsung,sifive}: Fix typos

Change-Id: Ib370f04a63160e2a8a1b06620e659feb45c8f552
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39016
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>

src/soc/sifive/fu540/clock.c

@@ -104,7 +104,7 @@ static void configure_pll(u32 *reg, const struct pll_settings *s)
  * Set coreclk according to the SiFive FU540-C000 Manual
  * https://www.sifive.com/documentation/chips/freedom-u540-c000-manual/
  *
- * Section 7.1 recommends a frequency of 1.0 GHz (up to 1.5 Ghz is possible)
+ * Section 7.1 recommends a frequency of 1.0 GHz (up to 1.5 GHz is possible)
  *
  * Section 7.4.2 provides the necessary values:
  * For example, to setup COREPLL for 1 GHz operation, program divr = 0 (x1),