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include/cpu/x86/msr: introduce IA32_MC_*(x) macros

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When accessing the MCA MSRs, the MCA bank number gets multiplied by 4
and added to the IA32_MC0_* define to get the MSR number. Add a macro
that already does this calculation to avoid open coding this repeatedly.

Change-Id: I2de753b8c8ac8dcff5a94d5bba43aa13bbf94b99
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56243
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Felix Held
2021-07-13 00:54:32 +02:00
parent e3f7ef2286
commit 1b46e76df9
11 changed files with 22 additions and 19 deletions
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2
src/cpu/amd/agesa/family14/model_14_init.c
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@@ -63,7 +63,7 @@ static void model_14_init(struct device *dev)
msr.lo = 0; msr.lo = 0;
msr.hi = 0; msr.hi = 0;
for (i = 0; i < num_banks; i++) for (i = 0; i < num_banks; i++)
wrmsr(IA32_MC0_STATUS + (i * 4), msr); wrmsr(IA32_MC_STATUS(i), msr);
/* Enable the local CPU APICs */ /* Enable the local CPU APICs */
setup_lapic(); setup_lapic();

2
src/cpu/amd/agesa/family15tn/model_15_init.c
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@@ -62,7 +62,7 @@ static void model_15_init(struct device *dev)
msr.lo = 0; msr.lo = 0;
msr.hi = 0; msr.hi = 0;
for (i = 0; i < num_banks; i++) for (i = 0; i < num_banks; i++)
wrmsr(IA32_MC0_STATUS + (i * 4), msr); wrmsr(IA32_MC_STATUS(i), msr);
/* Enable the local CPU APICs */ /* Enable the local CPU APICs */
setup_lapic(); setup_lapic();

2
src/cpu/amd/agesa/family16kb/model_16_init.c
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@@ -60,7 +60,7 @@ static void model_16_init(struct device *dev)
msr.lo = 0; msr.lo = 0;
msr.hi = 0; msr.hi = 0;
for (i = 0; i < num_banks; i++) for (i = 0; i < num_banks; i++)
wrmsr(IA32_MC0_STATUS + (i * 4), msr); wrmsr(IA32_MC_STATUS(i), msr);
/* Enable the local CPU APICs */ /* Enable the local CPU APICs */
setup_lapic(); setup_lapic();

2
src/cpu/amd/pi/00730F01/model_16_init.c
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@@ -45,7 +45,7 @@ static void model_16_init(struct device *dev)
msr.lo = 0; msr.lo = 0;
msr.hi = 0; msr.hi = 0;
for (i = 0; i < num_banks; i++) for (i = 0; i < num_banks; i++)
wrmsr(IA32_MC0_STATUS + (i * 4), msr); wrmsr(IA32_MC_STATUS(i), msr);
/* Enable the local CPU APICs */ /* Enable the local CPU APICs */
setup_lapic(); setup_lapic();

4
src/cpu/intel/haswell/haswell_init.c
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@@ -528,14 +528,14 @@ static void configure_mca(void)
/* Enable all error reporting */ /* Enable all error reporting */
msr.lo = msr.hi = ~0; msr.lo = msr.hi = ~0;
for (i = 0; i < num_banks; i++) for (i = 0; i < num_banks; i++)
wrmsr(IA32_MC0_CTL + (i * 4), msr); wrmsr(IA32_MC_CTL(i), msr);
msr.lo = msr.hi = 0; msr.lo = msr.hi = 0;
/* TODO(adurbin): This should only be done on a cold boot. Also, some /* TODO(adurbin): This should only be done on a cold boot. Also, some
* of these banks are core vs package scope. For now every CPU clears * of these banks are core vs package scope. For now every CPU clears
* every bank. */ * every bank. */
for (i = 0; i < num_banks; i++) for (i = 0; i < num_banks; i++)
wrmsr(IA32_MC0_STATUS + (i * 4), msr); wrmsr(IA32_MC_STATUS(i), msr);
} }
/* All CPUs including BSP will run the following function. */ /* All CPUs including BSP will run the following function. */

2
src/cpu/intel/model_2065x/model_2065x_init.c
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@@ -81,7 +81,7 @@ static void configure_mca(void)
msr.lo = msr.hi = 0; msr.lo = msr.hi = 0;
/* This should only be done on a cold boot */ /* This should only be done on a cold boot */
for (i = 0; i < 7; i++) for (i = 0; i < 7; i++)
wrmsr(IA32_MC0_STATUS + (i * 4), msr); wrmsr(IA32_MC_STATUS(i), msr);
} }
static void model_2065x_init(struct device *cpu) static void model_2065x_init(struct device *cpu)

2
src/cpu/intel/model_206ax/model_206ax_init.c
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@@ -309,7 +309,7 @@ static void configure_mca(void)
msr.lo = msr.hi = 0; msr.lo = msr.hi = 0;
/* This should only be done on a cold boot */ /* This should only be done on a cold boot */
for (i = 0; i < num_banks; i++) for (i = 0; i < num_banks; i++)
wrmsr(IA32_MC0_STATUS + (i * 4), msr); wrmsr(IA32_MC_STATUS(i), msr);
} }
static void model_206ax_report(void) static void model_206ax_report(void)

4
src/include/cpu/x86/msr.h
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@@ -56,7 +56,9 @@
#define DCA_TYPE0_EN (1 << 0) #define DCA_TYPE0_EN (1 << 0)
#define IA32_PAT 0x277 #define IA32_PAT 0x277
#define IA32_MC0_CTL 0x400 #define IA32_MC0_CTL 0x400
#define IA32_MC_CTL(bank) (IA32_MC0_CTL + 4 * (bank))
#define IA32_MC0_STATUS 0x401 #define IA32_MC0_STATUS 0x401
#define IA32_MC_STATUS(bank) (IA32_MC0_STATUS + 4 * (bank))
#define MCA_STATUS_HI_VAL (1UL << (63 - 32)) #define MCA_STATUS_HI_VAL (1UL << (63 - 32))
#define MCA_STATUS_HI_OVERFLOW (1UL << (62 - 32)) #define MCA_STATUS_HI_OVERFLOW (1UL << (62 - 32))
#define MCA_STATUS_HI_UC (1UL << (61 - 32)) #define MCA_STATUS_HI_UC (1UL << (61 - 32))
@@ -75,7 +77,9 @@
#define MCA_STATUS_LO_ERRCODE_EXT_MASK (0x3f << MCA_STATUS_LO_ERRCODE_EXT_SH) #define MCA_STATUS_LO_ERRCODE_EXT_MASK (0x3f << MCA_STATUS_LO_ERRCODE_EXT_SH)
#define MCA_STATUS_LO_ERRCODE_MASK (0xffff << 0) #define MCA_STATUS_LO_ERRCODE_MASK (0xffff << 0)
#define IA32_MC0_ADDR 0x402 #define IA32_MC0_ADDR 0x402
#define IA32_MC_ADDR(bank) (IA32_MC0_ADDR + 4 * (bank))
#define IA32_MC0_MISC 0x403 #define IA32_MC0_MISC 0x403
#define IA32_MC_MISC(bank) (IA32_MC0_MISC + 4 * (bank))
#define IA32_VMX_BASIC_MSR 0x480 #define IA32_VMX_BASIC_MSR 0x480
#define VMX_BASIC_HI_DUAL_MONITOR (1UL << (49 - 32)) #define VMX_BASIC_HI_DUAL_MONITOR (1UL << (49 - 32))
#define IA32_VMX_MISC_MSR 0x485 #define IA32_VMX_MISC_MSR 0x485

2
src/security/intel/txt/common.c
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@@ -483,7 +483,7 @@ bool intel_txt_prepare_txt_env(void)
*/ */
size_t max_mc_msr = mca_get_bank_count(); size_t max_mc_msr = mca_get_bank_count();
for (size_t i = 0; i < max_mc_msr; i++) { for (size_t i = 0; i < max_mc_msr; i++) {
msr = rdmsr(IA32_MC0_STATUS + 4 * i); msr = rdmsr(IA32_MC_STATUS(i));
if (!(msr.hi & MCA_STATUS_HI_UC)) if (!(msr.hi & MCA_STATUS_HI_UC))
continue; continue;

15
src/soc/amd/stoneyridge/mca.c
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@@ -119,8 +119,7 @@ static void build_bert_mca_error(struct mca_bank_status *mci)
ctx = cper_new_ia32x64_context_msr(status, x86_sec, IA32_MCG_CAP, 3); ctx = cper_new_ia32x64_context_msr(status, x86_sec, IA32_MCG_CAP, 3);
if (!ctx) if (!ctx)
goto failed; goto failed;
ctx = cper_new_ia32x64_context_msr(status, x86_sec, ctx = cper_new_ia32x64_context_msr(status, x86_sec, IA32_MC_CTL(mci->bank), 4);
IA32_MC0_CTL + (mci->bank * 4), 4);
if (!ctx) if (!ctx)
goto failed; goto failed;
ctx = cper_new_ia32x64_context_msr(status, x86_sec, ctx = cper_new_ia32x64_context_msr(status, x86_sec,
@@ -152,13 +151,13 @@ static void mca_print_error(unsigned int bank)
printk(BIOS_WARNING, "#MC Error: core %u, bank %u %s\n", initial_lapicid(), bank, printk(BIOS_WARNING, "#MC Error: core %u, bank %u %s\n", initial_lapicid(), bank,
mca_bank_name[bank]); mca_bank_name[bank]);
msr = rdmsr(IA32_MC0_STATUS + (bank * 4)); msr = rdmsr(IA32_MC_STATUS(bank));
printk(BIOS_WARNING, " MC%u_STATUS = %08x_%08x\n", bank, msr.hi, msr.lo); printk(BIOS_WARNING, " MC%u_STATUS = %08x_%08x\n", bank, msr.hi, msr.lo);
msr = rdmsr(IA32_MC0_ADDR + (bank * 4)); msr = rdmsr(IA32_MC_ADDR(bank));
printk(BIOS_WARNING, " MC%u_ADDR = %08x_%08x\n", bank, msr.hi, msr.lo); printk(BIOS_WARNING, " MC%u_ADDR = %08x_%08x\n", bank, msr.hi, msr.lo);
msr = rdmsr(IA32_MC0_MISC + (bank * 4)); msr = rdmsr(IA32_MC_MISC(bank));
printk(BIOS_WARNING, " MC%u_MISC = %08x_%08x\n", bank, msr.hi, msr.lo); printk(BIOS_WARNING, " MC%u_MISC = %08x_%08x\n", bank, msr.hi, msr.lo);
msr = rdmsr(IA32_MC0_CTL + (bank * 4)); msr = rdmsr(IA32_MC_CTL(bank));
printk(BIOS_WARNING, " MC%u_CTL = %08x_%08x\n", bank, msr.hi, msr.lo); printk(BIOS_WARNING, " MC%u_CTL = %08x_%08x\n", bank, msr.hi, msr.lo);
msr = rdmsr(MC0_CTL_MASK + bank); msr = rdmsr(MC0_CTL_MASK + bank);
printk(BIOS_WARNING, " MC%u_CTL_MASK = %08x_%08x\n", bank, msr.hi, msr.lo); printk(BIOS_WARNING, " MC%u_CTL_MASK = %08x_%08x\n", bank, msr.hi, msr.lo);
@@ -177,7 +176,7 @@ static void mca_check_all_banks(void)
continue; continue;
mci.bank = i; mci.bank = i;
mci.sts = rdmsr(IA32_MC0_STATUS + (i * 4)); mci.sts = rdmsr(IA32_MC_STATUS(i));
if (mci.sts.hi || mci.sts.lo) { if (mci.sts.hi || mci.sts.lo) {
mca_print_error(i); mca_print_error(i);
@@ -194,7 +193,7 @@ static void mca_clear_errors(void)
/* Zero all machine check error status registers */ /* Zero all machine check error status registers */
for (unsigned int i = 0 ; i < num_banks ; i++) for (unsigned int i = 0 ; i < num_banks ; i++)
wrmsr(IA32_MC0_STATUS + (i * 4), msr); wrmsr(IA32_MC_STATUS(i), msr);
} }
void check_mca(void) void check_mca(void)

4
src/soc/intel/common/block/cpu/cpulib.c
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@@ -348,9 +348,9 @@ void mca_configure(void)
for (i = 0; i < num_banks; i++) { for (i = 0; i < num_banks; i++) {
/* Clear the machine check status */ /* Clear the machine check status */
wrmsr(IA32_MC0_STATUS + (i * 4), msr); wrmsr(IA32_MC_STATUS(i), msr);
/* Initialize machine checks */ /* Initialize machine checks */
wrmsr(IA32_MC0_CTL + i * 4, wrmsr(IA32_MC_CTL(i),
(msr_t) {.lo = 0xffffffff, .hi = 0xffffffff}); (msr_t) {.lo = 0xffffffff, .hi = 0xffffffff});
} }
} }