soc/intel/cannonlake: Add Pch iSCLK programming

In order to reduce BOM cost and board area for imaging solution, the
sensor requires a 19.2/24MHz reference clock from PCH. In addition to
that, having PCH to supply the sensor reference clock will prevent
dependency on CPU power management and also avoid level shifter cost.

Pch iSCLK is only required for CNP-LP with the camera sensor on the
platform.

BUG=None
TEST=Boot up into OS and read back PCH iSCLK programming through
iotools.

Change-Id: I28c97a75f2a7f5122a20c8b8f0f2671037a7eca6
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/23367
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/soc/intel/cannonlake/chip.h

@@ -263,6 +263,9 @@ struct soc_intel_cannonlake_config {
 
 	/* I2C bus configuration */
 	struct dw_i2c_bus_config i2c[CANNONLAKE_I2C_DEV_MAX];
+
+	/* Enable Pch iSCLK */
+	uint8_t pch_isclk;
 };
 
 typedef struct soc_intel_cannonlake_config config_t;