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implement usb2 termination and dpll delay setting for vt8237r

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Change-Id: I830c9a3daf5ac2e1ecd9a3e725a0b98f06509769
Signed-off-by: Florian Zumbiehl <florz@florz.de>
Reviewed-on: http://review.coreboot.org/385
Tested-by: build bot (Jenkins)
Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
This commit is contained in:
Florian Zumbiehl
2011-11-01 20:19:35 +01:00
committed by Rudolf Marek
parent 28bdd8d9eb
commit 1b940fd424
2 changed files with 37 additions and 0 deletions
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13
src/southbridge/via/vt8237r/chip.h
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@ -56,6 +56,19 @@ struct southbridge_via_vt8237r_config {
/* 1 = 80-pin cable, 0 = 40-pin cable */ /* 1 = 80-pin cable, 0 = 40-pin cable */
u8 ide0_80pin_cable; u8 ide0_80pin_cable;
u8 ide1_80pin_cable; u8 ide1_80pin_cable;
u8 usb2_termination_set;
u8 usb2_termination_a;
u8 usb2_termination_b;
u8 usb2_termination_c;
u8 usb2_termination_d;
u8 usb2_termination_e;
u8 usb2_termination_f;
u8 usb2_termination_g;
u8 usb2_termination_h;
u8 usb2_dpll_set;
u8 usb2_dpll_delay;
}; };
#endif /* SOUTHBRIDGE_VIA_VT8237R_CHIP_H */ #endif /* SOUTHBRIDGE_VIA_VT8237R_CHIP_H */

24
src/southbridge/via/vt8237r/usb.c
View File

@ -22,6 +22,7 @@
#include <device/device.h> #include <device/device.h>
#include <device/pci.h> #include <device/pci.h>
#include <device/pci_ids.h> #include <device/pci_ids.h>
#include "chip.h"
#include "vt8237r.h" #include "vt8237r.h"
#if CONFIG_EPIA_VT8237R_INIT #if CONFIG_EPIA_VT8237R_INIT
@ -94,6 +95,7 @@ static void vt8237_usb_i_read_resources(struct device *dev)
static void usb_ii_init(struct device *dev) static void usb_ii_init(struct device *dev)
{ {
struct southbridge_via_vt8237r_config *cfg;
#if CONFIG_EPIA_VT8237R_INIT #if CONFIG_EPIA_VT8237R_INIT
u8 reg8; u8 reg8;
@ -112,6 +114,28 @@ static void usb_ii_init(struct device *dev)
pci_write_config16(dev, 0x06, 0x7A10); pci_write_config16(dev, 0x06, 0x7A10);
#endif #endif
cfg = dev->chip_info;
if (cfg) {
if (cfg->usb2_termination_set) {
/* High Speed Port Pad Termination Resistor Fine Tune */
pci_write_config8(dev, 0x5a, cfg->usb2_termination_c |
(cfg->usb2_termination_d << 4));
pci_write_config8(dev, 0x5b, cfg->usb2_termination_a |
(cfg->usb2_termination_b << 4));
pci_write_config8(dev, 0x5d, cfg->usb2_termination_e |
(cfg->usb2_termination_f << 4));
pci_write_config8(dev, 0x5e, cfg->usb2_termination_g |
(cfg->usb2_termination_h << 4));
}
if (cfg->usb2_dpll_set) {
/* Delay DPLL Input Data Control */
pci_write_config8(dev, 0x5c,
(pci_read_config8(dev, 0x5c) & ~0x70) |
(cfg->usb2_dpll_delay << 4));
}
}
} }
static void vt8237_usb_ii_read_resources(struct device *dev) static void vt8237_usb_ii_read_resources(struct device *dev)