libpayload: Add USB device mode driver
Add a framework for USB device mode controllers and a driver for the ChipIdea controller which is part of the tegra platform. TODO: - fix USB detach/attach - implement zero length packet handling properly BUG=chrome-os-partner:35861 TEST=none BRANCH=none Change-Id: I8defeea78b5a3bdbf9c1b1222c2702eaf3256b81 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 542332291880c4026a05a960ceb91d37891ee018 Original-Change-Id: Ib4068d201dd63ebeda80157bd3130f3059919cdd Original-Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/243272 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8756 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Patrick Georgi
168
payloads/libpayload/drivers/udc/chipidea_priv.h
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168
payloads/libpayload/drivers/udc/chipidea_priv.h
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/*
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* This file is part of the libpayload project.
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*
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* Copyright (C) 2015 Google Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#ifndef __CHIPIDEA_PRIV_H__
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#define __CHIPIDEA_PRIV_H__
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#include <queue.h>
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struct chipidea_opreg {
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uint8_t pad0[0x130];
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uint32_t usbcmd; // 0x130
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uint32_t usbsts; // 0x134
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uint32_t pad138[3];
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uint32_t usbadr; // 0x144
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/* 31:25: address
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* 24: staging: 1 -> commit new address after
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* next ctrl-in on ep0
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*/
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uint32_t epbase; // 0x148
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uint32_t pad14c[10];
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uint32_t portsc; // 0x174
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uint32_t pad178[15];
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uint32_t devlc; // 0x1b4
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/* 25:26: host-desired usb version
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* 23: force full speed */
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uint32_t pad1b8[16];
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uint32_t usbmode; // 0x1f8
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/* 0:1: 2 -> device mode */
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uint32_t pad1fc[3];
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uint32_t epsetupstat; // 0x208
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/* 0:15: 1 -> epX received setup packet */
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uint32_t epprime; // 0x20c
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/* 0:15: 1 -> rx buffer for epX (OUT) is primed
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* (ie. ready for controller-side processing)
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* 16:31: 1 -> tx buffer for ep(X-16) (IN/INTR) is primed
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* (ie. ready for controller-side processing)
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*
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* controller will read new td from qh and process it,
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* then set the bit to 0
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*/
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uint32_t epflush; // 0x210
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/* 0:31: 1 -> flush buffer (as defined in epprime),
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* so it's uninitialized again.
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* controller resets to 0 when done
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*/
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uint32_t epstat; // 0x214
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/* 0:31: 1 -> command in epprime is done, EP is ready
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* (which may be later than epprime reset)
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*/
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uint32_t epcomplete; // 0x218
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/* 0:15: 1 -> incoming out/setup packet for epX was handled.
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* software should check QH state
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* 16:31: 1 -> incoming intr/in packet for ep(X-16) was
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* handled. software should check QH state
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*/
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uint32_t epctrl[16]; // 0x21c
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/* epctrl[0] is hardcoded as enabled control endpoint.
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* TXS/RXS for stalling can be written.
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*
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* 23: TXE tx endpoint enable
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* 22: TXR reset tx data toggle (for every configuration event)
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* 18:19: 0=ctrl, 1=isoc, 2=bulk, 3=intr endpoint
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* 16: TXS stall tx
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*
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* 7: RXE rx endpoint enable
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* 6: RXR reset rx data toggle (for every configuration event)
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* 2:3: endpoint type (like 18:19)
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* 0: RXS stall rx
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*/
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uint32_t pad25c[0x69]; // 0x25c
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uint32_t susp_ctrl; // 0x400
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};
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#define CI_PDATA(ctrl) ((struct chipidea_pdata *)((ctrl)->pdata))
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#define CI_QHELEMENTS 32
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#define QH_NO_AUTO_ZLT (1 << 29) /* no automatic ZLT handling by chipset */
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#define QH_MPS(x) ((x) << 16)
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#define QH_IOS (1 << 15) /* IRQ on setup */
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#define TD_INFO_LEN(x) ((x) << 16)
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#define TD_INFO_IOC (1 << 15)
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#define TD_INFO_ACTIVE (1 << 7)
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#define TD_TERMINATE 1
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#define USBCMD_8MICRO (8 << 16)
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#define USBCMD_RST 2
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#define USBCMD_RUN 1
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#define USBSTS_SLI (1 << 8)
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#define USBSTS_URI (1 << 6)
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#define USBSTS_PCI (1 << 2)
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#define USBSTS_UEI (1 << 1)
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#define USBSTS_UI (1 << 0)
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#define DEVLC_HOSTSPEED(x) (x << 25)
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#define DEVLC_HOSTSPEED_MASK DEVLC_HOSTSPEED(3)
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struct td {
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/* points to next td */
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uint32_t next;
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uint32_t info;
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/* page0..4 are like EHCI pages: up to 4k each
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* page0 from addr to page end, page4 to its length
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*/
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uint32_t page0;
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uint32_t page1;
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uint32_t page2;
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uint32_t page3;
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uint32_t page4;
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uint32_t res;
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};
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struct qh {
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uint32_t config;
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uint32_t current;
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struct td td;
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/* contains the data of a setup request */
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uint8_t setup_data[8];
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uint32_t res[4];
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};
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struct job {
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SIMPLEQ_ENTRY(job) queue; // linkage
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struct td *tds; // for later free()ing
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int td_count;
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void *data;
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size_t length;
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int zlp; // append zero length packet?
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int autofree; // free after processing?
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};
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SIMPLEQ_HEAD(job_queue, job);
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struct chipidea_pdata {
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struct chipidea_opreg *opreg;
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struct qh *qhlist;
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struct job_queue job_queue[16][2];
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int ep_busy[16][2];
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};
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#endif
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