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src/soc/intel/denverton_ns: Use improvement in coreboot since 4.9

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- enable microcode in cbfs (won't boot without microcode)
 - force num fit entry to 1 to avoid crash in cbfstool/fit.c
 - re-enable FSP-CAR (tested to boot, while I couldn't boot with NEM)
 - enable io driver for uart in legacy mode (ie emulating legacy port by
   configuring the pci to legacy io address and hiding the pci device)

Signed-off-by: Julien Viard de Galbert <julien@vdg.name>
Change-Id: Ibc5ce91118c6052af23642fb3461f574cd888dea
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47340
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Reviewed-by: Mariusz Szafrański <mariuszx.szafranski@intel.com>
This commit is contained in:
Julien Viard de Galbert
2020-11-07 23:40:43 +01:00
committed by Angel Pons
parent 50a6fe73c6
commit 1c33f740c4
1 changed files with 23 additions and 3 deletions
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26
src/soc/intel/denverton_ns/Kconfig
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@@ -7,6 +7,10 @@ config SOC_INTEL_DENVERTON_NS
if SOC_INTEL_DENVERTON_NS if SOC_INTEL_DENVERTON_NS
config CPU_INTEL_NUM_FIT_ENTRIES
int
default 1
config CPU_SPECIFIC_OPTIONS config CPU_SPECIFIC_OPTIONS
def_bool y def_bool y
select ARCH_ALL_STAGES_X86_32 select ARCH_ALL_STAGES_X86_32
@@ -21,6 +25,7 @@ config CPU_SPECIFIC_OPTIONS
select CACHE_MRC_SETTINGS select CACHE_MRC_SETTINGS
select PARALLEL_MP select PARALLEL_MP
select PCR_COMMON_IOSF_1_0 select PCR_COMMON_IOSF_1_0
select SUPPORT_CPU_UCODE_IN_CBFS
select INTEL_DESCRIPTOR_MODE_CAPABLE select INTEL_DESCRIPTOR_MODE_CAPABLE
select SOC_INTEL_COMMON_BLOCK select SOC_INTEL_COMMON_BLOCK
select SOC_INTEL_COMMON_BLOCK_CPU select SOC_INTEL_COMMON_BLOCK_CPU
@@ -134,6 +139,9 @@ config LEGACY_UART_MODE
bool "Legacy Mode" bool "Legacy Mode"
help help
Enable legacy UART mode Enable legacy UART mode
select CONSOLE_SERIAL
select DRIVERS_UART
select DRIVERS_UART_8250IO
endchoice endchoice
config ENABLE_HSUART config ENABLE_HSUART
@@ -153,10 +161,14 @@ config C_ENV_BOOTBLOCK_SIZE
hex hex
default 0x8000 default 0x8000
config DENVERTON_NS_CAR_NEM_ENHANCED choice
prompt "Cache-as-ram implementation"
default USE_DENVERTON_NS_CAR_NEM_ENHANCED
help
This option allows you to select how cache-as-ram (CAR) is set up.
config USE_DENVERTON_NS_CAR_NEM_ENHANCED
bool "Enhanced Non-evict mode" bool "Enhanced Non-evict mode"
depends on !FSP_CAR
default y
select SOC_INTEL_COMMON_BLOCK_CAR select SOC_INTEL_COMMON_BLOCK_CAR
select USE_CAR_NEM_ENHANCED_V1 select USE_CAR_NEM_ENHANCED_V1
help help
@@ -167,4 +179,12 @@ config DENVERTON_NS_CAR_NEM_ENHANCED
ENHANCED NEM guarantees that modified data is always ENHANCED NEM guarantees that modified data is always
kept in cache while clean data is replaced. kept in cache while clean data is replaced.
config USE_DENVERTON_NS_FSP_CAR
bool "Use FSP CAR"
select FSP_CAR
help
Use FSP APIs to initialize and tear down the Cache-As-Ram.
endchoice
endif ## SOC_INTEL_DENVERTON_NS endif ## SOC_INTEL_DENVERTON_NS