soc/intel/xeon_sp: Make NUMA support by default

TEST=Build and boot on intel/archercity CRB

Change-Id: I84f07c16e24e441a885144df8c805f1310acae29
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Co-authored-by: Ziang Wang <ziang.wang@intel.com>
Co-authored-by: Gang Chen <gang.c.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81439
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/soc/intel/xeon_sp/Makefile.mk

@@ -11,9 +11,10 @@ romstage-y += romstage.c reset.c util.c spi.c pmutil.c memmap.c ddr.c
 romstage-y += ../../../cpu/intel/car/romstage.c
 ramstage-y += uncore.c reset.c util.c lpc.c spi.c ramstage.c chip_common.c
 ramstage-y += memmap.c pch.c lockdown.c finalize.c
+ramstage-y += numa.c
 ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_PMC) += pmc.c pmutil.c
 ramstage-$(CONFIG_HAVE_ACPI_TABLES) += uncore_acpi.c acpi.c
-ramstage-$(CONFIG_SOC_INTEL_HAS_CXL) += uncore_acpi_cxl.c numa.c
+ramstage-$(CONFIG_SOC_INTEL_HAS_CXL) += uncore_acpi_cxl.c
 ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smmrelocate.c
 ramstage-$(CONFIG_XEON_SP_HAVE_IIO_IOAPIC) += iio_ioapic.c
 smm-y += smihandler.c pmutil.c

src/soc/intel/xeon_sp/cpx/soc_util.c

@@ -136,3 +136,8 @@ bool is_memtype_processor_attached(uint16_t mem_type)
 {
 	return true;
 }
+
+uint8_t get_cxl_node_count(void)
+{
+	return 0;
+}

src/soc/intel/xeon_sp/numa.c

@@ -50,7 +50,6 @@ void fill_pds(void)
 
 	/* Fill in processor domains */
 	uint8_t i, j, socket;
-	struct device *dev;
 	for (socket = 0, i = 0; i < num_sockets; socket++) {
 		if (!soc_cpu_is_enabled(socket))
 			continue;
@@ -73,6 +72,7 @@ void fill_pds(void)
 	if (num_cxlnodes == 0)
 		return;
 
+#if CONFIG(SOC_INTEL_HAS_CXL)
 	/* There are CXL nodes, fill in generic initiator domain after the processors pds */
 	uint8_t skt_id, cxl_id;
 	const CXL_NODE_SOCKET *cxl_hob = get_cxl_node();
@@ -83,7 +83,7 @@ void fill_pds(void)
 			pds.pds[i].socket_bitmap = node.SocketBitmap;
 			pds.pds[i].base = node.Address;
 			pds.pds[i].size = node.Size;
-			dev = pcie_find_dsn(node.SerialNumber, node.VendorId, 0);
+			struct device *dev = pcie_find_dsn(node.SerialNumber, node.VendorId, 0);
 			pds.pds[i].dev = dev;
 			pds.pds[i].distances = malloc(sizeof(uint8_t) * pds.num_pds);
 			if (!pds.pds[i].distances)
@@ -97,6 +97,7 @@ void fill_pds(void)
 			}
 		}
 	}
+#endif
 }
 
 /*

src/soc/intel/xeon_sp/skx/soc_util.c

@@ -209,3 +209,8 @@ bool is_memtype_processor_attached(uint16_t mem_type)
 {
 	return true;
 }
+
+uint8_t get_cxl_node_count(void)
+{
+	return 0;
+}

src/soc/intel/xeon_sp/uncore.c

@@ -338,14 +338,12 @@ static void mmapvtd_read_resources(struct device *dev)
 {
 	int index = 0;
 
-	if (CONFIG(SOC_INTEL_HAS_CXL)) {
-		static bool once;
-		if (!once) {
-			/* Construct NUMA data structure. This is needed for CXL. */
-			fill_pds();
-			dump_pds();
-			once = true;
-		}
+	static bool once;
+	if (!once) {
+		/* Construct NUMA data structure. This is needed for CXL. */
+		fill_pds();
+		dump_pds();
+		once = true;
 	}
 
 	/* Read standard PCI resources. */