Documentation: Fix sphinx warnings

This fixes the following warnings:

mainboard/starlabs/common/flashing.md::
WARNING: image file not readable:
- mainboard/starlabs/common/fwupdVersion.png
- mainboard/starlabs/common/BiosLock.jpg
- mainboard/starlabs/common/SwitchBranch.png

cbfstool/index.md::
WARNING: document isn't included in any toctree

internals/devicetree_keywords.md::
WARNING: document isn't included in any toctree

mainboard/asus/wifigo_v1.md::
WARNING: document isn't included in any toctree

mainboard/google/index.md::
WARNING: document isn't included in any toctree

mainboard/starlabs/common/flashing.md::
WARNING: document isn't included in any toctree

releases/boards_supported_on_branches.md::
WARNING: document isn't included in any toctree
WARNING: None:any reference target not found:
- releases/coreboot-4.16-relnotes
- releases/coreboot-4.15-relnotes
- releases/coreboot-4.14-relnotes
- releases/coreboot-4.13-relnotes
- releases/coreboot-4.12-relnotes
- releases/coreboot-4.11-relnotes
- releases/coreboot-4.10-relnotes
- releases/coreboot-4.9-relnotes
- releases/coreboot-4.8.1-relnotes
- releases/coreboot-4.7-relnotes
- releases/coreboot-4.6-relnotes
- releases/coreboot-4.5-relnotes
- releases/coreboot-4.4-relnotes
- releases/coreboot-4.3-relnotes
- releases/coreboot-4.2-relnotes
- releases/coreboot-4.1-relnotes
- ../../src/soc/intel/common/block/cse/cse.c

Change-Id: I22273bc1bc34b6297cef4e594c454c2316d4215a
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64576
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>

Documentation/releases/coreboot-4.16-relnotes.md

@@ -132,7 +132,7 @@ HECI based on Intel Core processors from Skylake to Alder Lake. State is
 set based on a CMOS value of `me_state`. A value of `0` will result in a
 (CS)ME state of `0` (working) and value of `1` will result in a (CS)ME
 state of `3` (disabled). For an example CMOS layout and more info, see
-[cse.c](../../src/soc/intel/common/block/cse/cse.c).
+[cse.c](https://review.coreboot.org/plugins/gitiles/coreboot/+/refs/heads/master/src/soc/intel/common/block/cse/cse.c).
 
 
 ### Add [AMD] apcb_v3_edit tool