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Documentation: Fix sphinx warnings

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This fixes the following warnings:

mainboard/starlabs/common/flashing.md::
WARNING: image file not readable:
- mainboard/starlabs/common/fwupdVersion.png
- mainboard/starlabs/common/BiosLock.jpg
- mainboard/starlabs/common/SwitchBranch.png

cbfstool/index.md::
WARNING: document isn't included in any toctree

internals/devicetree_keywords.md::
WARNING: document isn't included in any toctree

mainboard/asus/wifigo_v1.md::
WARNING: document isn't included in any toctree

mainboard/google/index.md::
WARNING: document isn't included in any toctree

mainboard/starlabs/common/flashing.md::
WARNING: document isn't included in any toctree

releases/boards_supported_on_branches.md::
WARNING: document isn't included in any toctree
WARNING: None:any reference target not found:
- releases/coreboot-4.16-relnotes
- releases/coreboot-4.15-relnotes
- releases/coreboot-4.14-relnotes
- releases/coreboot-4.13-relnotes
- releases/coreboot-4.12-relnotes
- releases/coreboot-4.11-relnotes
- releases/coreboot-4.10-relnotes
- releases/coreboot-4.9-relnotes
- releases/coreboot-4.8.1-relnotes
- releases/coreboot-4.7-relnotes
- releases/coreboot-4.6-relnotes
- releases/coreboot-4.5-relnotes
- releases/coreboot-4.4-relnotes
- releases/coreboot-4.3-relnotes
- releases/coreboot-4.2-relnotes
- releases/coreboot-4.1-relnotes
- ../../src/soc/intel/common/block/cse/cse.c

Change-Id: I22273bc1bc34b6297cef4e594c454c2316d4215a
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64576
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
This commit is contained in:
Martin Roth
2022-05-22 18:17:06 -06:00
committed by Martin L Roth
parent 8dd47aea04
commit 1c5209835f
5 changed files with 23 additions and 20 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
Documentation/index.md
View File

@@ -189,5 +189,6 @@ Contents:
* [Vendorcode](vendorcode/index.md)
* [Utilities](util.md)
* [Project infrastructure & services](infrastructure/index.md)
* [Boards supported in each release directory](releases/boards_supported_on_branches.md)
* [Release notes](releases/index.md)
* [Documentation License](documentation_license.md)

2
Documentation/mainboard/index.md
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@@ -30,6 +30,7 @@ This section contains documentation about coreboot on specific mainboards.
- [P8H77-V](asus/p8h77-v.md)
- [P8Z77-M Pro](asus/p8z77-m_pro.md)
- [P8Z77-V](asus/p8z77-v.md)
- [wifigo_v1](asus/wifigo_v1.md)
## Cavium
@@ -185,6 +186,7 @@ The boards in this section are not real mainboards, but emulators.
- [StarLite Mk III](starlabs/lite_glk.md)
- [StarLite Mk IV](starlabs/lite_glkr.md)
- [StarBook Mk V](starlabs/starbook_tgl.md)
- [Flashing devices](starlabs/common/flashing.md)
## Supermicro

6
Documentation/mainboard/starlabs/common/flashing.md
View File

@@ -16,7 +16,7 @@ fwupdmgr --version
```
This will show the version number. **1.5.6** or greater will work.
![fwupd version](fwupdVersion.png)
![fwupd version](../fwupdVersion.png)
On Ubuntu 20.04, Ubuntu 20.10, Linux Mint 20.1 and elementaryOS 6, fwupd 1.5.6 can be installed from our PPA with the below terminal commands:
```
@@ -40,7 +40,7 @@ BIOS Lock must be disabled when switching from the standard AMI (American Megatr
2\. When the BIOS settings load, use the arrow keys to navigate to the **Advanced** tab\. Here you will see **BIOS Lock**\.
3\. Press `Enter` to change this setting from **Enabled** to **Disabled**
![Disable BIOS Lock](BiosLock.jpg)
![Disable BIOS Lock](../BiosLock.jpg)
4\. Next, press the `F10` key to **Save & Exit** and then `Enter` to confirm.
@@ -61,7 +61,7 @@ fwupdmgr switch-branch
```
You can then select which branch you would like to use, by typing in the corresponding number:
![Switch Branch](SwitchBranch.png)
![Switch Branch](../SwitchBranch.png)
You will be prompted to confirm, press `y` to continue or `n` to cancel.
Once the switch has been completed, you will be prompted to restart.

32
Documentation/releases/boards_supported_on_branches.md
View File

@@ -22,25 +22,25 @@ branches as needed. The coreboot project will take care of backporting
critical security fixes, but other patches will need to handled by
anyone using that release.
## [4.16 Release](releases/coreboot-4.16-relnotes.md)
## [4.16 Release](coreboot-4.16-relnotes.md)
Branch created, builder configured
* No platforms maintained on this release
## [4.15 Release](releases/coreboot-4.15-relnotes.md)
## [4.15 Release](coreboot-4.15-relnotes.md)
Branch created, builder configured
* No platforms maintained on this release
## [4.14 Release](releases/coreboot-4.14-relnotes.md)
## [4.14 Release](coreboot-4.14-relnotes.md)
Branch created, builder configured
* No platforms maintained on this release
## [4.13 Release](releases/coreboot-4.13-relnotes.md)
## [4.13 Release](coreboot-4.13-relnotes.md)
Tag only
| Vendor/Board | Processor | Date added | Brd type |
@@ -48,7 +48,7 @@ Tag only
| intel/cannonlake_rvp | INTEL_CANNONLAKE | 2017-07-19 | eval |
## [4.12 Release](releases/coreboot-4.12-relnotes.md)
## [4.12 Release](coreboot-4.12-relnotes.md)
Branch created, builder configured
@@ -59,7 +59,7 @@ Branch created, builder configured
| ocp/sonorapass | INTEL_COOPERLAKE_SP | 2020-05-01 | server |
## [4.11 Release](releases/coreboot-4.11-relnotes.md)
## [4.11 Release](coreboot-4.11-relnotes.md)
Branch created, builder configured
@@ -114,7 +114,7 @@ Branch created, builder configured
| via/epia-m850 | VIA_VX900 | 2013-06-10 | mini |
## [4.10 Release](releases/coreboot-4.10-relnotes.md)
## [4.10 Release](coreboot-4.10-relnotes.md)
Branch created
| Vendor/Board | Processor | Date added | Brd type |
@@ -122,7 +122,7 @@ Branch created
| cubietech/cubieboard | ALLWINNER_A10 | 2014-01-08 | sbc |
## [4.9 Release](releases/coreboot-4.9-relnotes.md)
## [4.9 Release](coreboot-4.9-relnotes.md)
Tag only
| Vendor/Board | Processor | Date added | Brd type |
@@ -133,7 +133,7 @@ Tag only
| pcengines/alix2d | AMD_LX | 2010-08-31 | half |
## [4.8.1 Release](releases/coreboot-4.8.1-relnotes.md)
## [4.8.1 Release](coreboot-4.8.1-relnotes.md)
Branch created
| Vendor/Board | Processor | Date added | Brd type |
@@ -203,7 +203,7 @@ Branch created
| winnet/g170 | VIA_C7 | 2017-08-28 | mini |
## [4.7 Release](releases/coreboot-4.7-relnotes.md)
## [4.7 Release](coreboot-4.7-relnotes.md)
Tag only
| Vendor/Board | Processor | Date added | Brd type |
@@ -249,7 +249,7 @@ Tag only
| wyse/s50 | AMD_GEODE_GX2 | 2010-05-08 | settop |
## [4.6](releases/coreboot-4.6-relnotes.md)
## [4.6](coreboot-4.6-relnotes.md)
Tag only
| Vendor/Board | Processor | Date added | Brd type |
@@ -259,7 +259,7 @@ Tag only
| intel/bakersport_fsp | INTEL_FSP_BAYTRAIL | 2014-08-11 | eval |
## [4.5](releases/coreboot-4.5-relnotes.md)
## [4.5](coreboot-4.5-relnotes.md)
Tag only
| Vendor/Board | Processor | Date added | Brd type |
@@ -275,7 +275,7 @@ Tag only
| google/tidus | INTEL_BROADWELL | 2016-01-21 | half |
## [4.4](releases/coreboot-4.4-relnotes.md)
## [4.4](coreboot-4.4-relnotes.md)
Branch created
| Vendor/Board | Processor | Date added | Brd type |
@@ -287,13 +287,13 @@ Branch created
| intel/amenia | INTEL_APOLLOLAKE | 2016-04-20 | eval |
## [4.3](releases/coreboot-4.3-relnotes.md)
## [4.3](coreboot-4.3-relnotes.md)
Branch created
* No platforms maintained on this release
## [4.2](releases/coreboot-4.2-relnotes.md)
## [4.2](coreboot-4.2-relnotes.md)
Branch created
| Vendor/Board | Processor | Date added | Brd type |
@@ -320,7 +320,7 @@ Branch created
| tyan/s4882 | AMD_AMDK8 | 2009-10-08 | server |
## [4.1](releases/coreboot-4.1-relnotes.md)
## [4.1](coreboot-4.1-relnotes.md)
Branch Created
* No platforms maintained on this release

2
Documentation/releases/coreboot-4.16-relnotes.md
View File

@@ -132,7 +132,7 @@ HECI based on Intel Core processors from Skylake to Alder Lake. State is
set based on a CMOS value of `me_state`. A value of `0` will result in a
(CS)ME state of `0` (working) and value of `1` will result in a (CS)ME
state of `3` (disabled). For an example CMOS layout and more info, see
[cse.c](../../src/soc/intel/common/block/cse/cse.c).
[cse.c](https://review.coreboot.org/plugins/gitiles/coreboot/+/refs/heads/master/src/soc/intel/common/block/cse/cse.c).
### Add [AMD] apcb_v3_edit tool