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Update cml-u and whl-u with lemp9 changes

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This commit is contained in:
Jeremy Soller
2020-01-22 10:34:04 -07:00
parent 887093b627
commit 1c6cbf3a6a
38 changed files with 1442 additions and 1472 deletions
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8
src/mainboard/system76/cml-u/Kconfig
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@@ -5,7 +5,6 @@ config BOARD_SPECIFIC_OPTIONS
select ADD_FSP_BINARIES select ADD_FSP_BINARIES
select BOARD_ROMSIZE_KB_16384 select BOARD_ROMSIZE_KB_16384
select EC_ACPI select EC_ACPI
select EXCLUDE_EMMC_INTERFACE
select HAVE_ACPI_RESUME select HAVE_ACPI_RESUME
select HAVE_ACPI_TABLES select HAVE_ACPI_TABLES
select HAVE_CMOS_DEFAULT select HAVE_CMOS_DEFAULT
@@ -13,10 +12,10 @@ config BOARD_SPECIFIC_OPTIONS
select HAVE_SMI_HANDLER select HAVE_SMI_HANDLER
select INTEL_GMA_HAVE_VBT select INTEL_GMA_HAVE_VBT
select INTEL_LPSS_UART_FOR_CONSOLE select INTEL_LPSS_UART_FOR_CONSOLE
# Chip select 2 is not yet supported by intel fast_spi
# select MAINBOARD_HAS_SPI_TPM_CR50 # select MAINBOARD_HAS_SPI_TPM_CR50
# select MAINBOARD_HAS_TPM2 # select MAINBOARD_HAS_TPM2
select NO_UART_ON_SUPERIO select NO_UART_ON_SUPERIO\
select PCIE_DEBUG_INFO
select PCIEXP_HOTPLUG select PCIEXP_HOTPLUG
select SOC_INTEL_COMETLAKE select SOC_INTEL_COMETLAKE
select SOC_INTEL_COMMON_ACPI_EC_PTS_WAK select SOC_INTEL_COMMON_ACPI_EC_PTS_WAK
@@ -99,10 +98,11 @@ config POST_DEVICE
bool bool
default n default n
# Chip select 2 is not yet supported by intel fast_spi
#config DRIVER_TPM_SPI_BUS #config DRIVER_TPM_SPI_BUS
# hex # hex
# default 0x0 # default 0x0
#
#config DRIVER_TPM_SPI_CHIP #config DRIVER_TPM_SPI_CHIP
# int # int
# default 2 # default 2

3
src/mainboard/system76/cml-u/Makefile.inc
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@@ -1,2 +1,3 @@
bootblock-y += bootblock.c bootblock-y += bootblock.c
ramstage-y += ramstage.c variants/$(VARIANT_DIR)/hda_verb.c ramstage-y += ramstage.c
ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c

3
src/mainboard/system76/cml-u/bootblock.c
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@@ -17,6 +17,7 @@
#include <gpio.h> #include <gpio.h>
#include "gpio.h" #include "gpio.h"
void bootblock_mainboard_init(void) { void bootblock_mainboard_init(void)
{
gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
} }

2
src/mainboard/system76/cml-u/devicetree.cb
View File

@@ -8,7 +8,7 @@ chip soc/intel/cannonlake
register "SendVrMbxCmd" = "2" register "SendVrMbxCmd" = "2"
# ACPI (soc/intel/cannonlake/acpi.c) # ACPI (soc/intel/cannonlake/acpi.c)
# Enable s0ix # Disable s0ix
register "s0ix_enable" = "0" register "s0ix_enable" = "0"
# PM Timer Enabled # PM Timer Enabled

19
src/mainboard/system76/cml-u/dsdt.asl
View File

@@ -25,34 +25,23 @@ DefinitionBlock(
0x20110725 // OEM revision 0x20110725 // OEM revision
) )
{ {
// Some generic macros
#include <soc/intel/cannonlake/acpi/platform.asl> #include <soc/intel/cannonlake/acpi/platform.asl>
// global NVS and variables
#include <soc/intel/common/block/acpi/acpi/globalnvs.asl> #include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
// CPU
#include <cpu/intel/common/acpi/cpu.asl> #include <cpu/intel/common/acpi/cpu.asl>
Scope (\_SB) { Device (\_SB.PCI0)
Device (PCI0)
{ {
#include <soc/intel/cannonlake/acpi/northbridge.asl> #include <soc/intel/common/block/acpi/acpi/northbridge.asl>
#include <soc/intel/cannonlake/acpi/southbridge.asl> #include <soc/intel/cannonlake/acpi/southbridge.asl>
} }
}
// Chipset specific sleep states
#include <southbridge/intel/common/acpi/sleepstates.asl> #include <southbridge/intel/common/acpi/sleepstates.asl>
Scope (\_SB.PCI0.LPCB) { Scope (\_SB.PCI0.LPCB)
// PS/2 bus {
#include <drivers/pc80/pc/ps2_controller.asl> #include <drivers/pc80/pc/ps2_controller.asl>
// Embedded controller
#include "acpi/ec.asl" #include "acpi/ec.asl"
} }
// Mainboard specific
#include "acpi/mainboard.asl" #include "acpi/mainboard.asl"
} }

4
src/mainboard/system76/cml-u/ramstage.c
View File

@@ -16,6 +16,7 @@
#include <string.h> #include <string.h>
#include <arch/acpi.h> #include <arch/acpi.h>
#include <arch/acpigen.h> #include <arch/acpigen.h>
#include <arch/io.h>
#include <console/console.h> #include <console/console.h>
#include <device/device.h> #include <device/device.h>
#include <option.h> #include <option.h>
@@ -23,7 +24,8 @@
#include <soc/ramstage.h> #include <soc/ramstage.h>
#include "gpio.h" #include "gpio.h"
void mainboard_silicon_init_params(FSP_S_CONFIG *params) { void mainboard_silicon_init_params(FSP_S_CONFIG *params)
{
/* Configure pads prior to SiliconInit() in case there's any /* Configure pads prior to SiliconInit() in case there's any
* dependencies during hardware initialization. */ * dependencies during hardware initialization. */
cnl_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); cnl_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));

8
src/mainboard/system76/cml-u/romstage.c
View File

@@ -16,7 +16,6 @@
#include <soc/cnl_memcfg_init.h> #include <soc/cnl_memcfg_init.h>
#include <soc/romstage.h> #include <soc/romstage.h>
//TODO: find correct values
static const struct cnl_mb_cfg memcfg = { static const struct cnl_mb_cfg memcfg = {
/* Parameters required to access SPD for CH0D0/CH0D1/CH1D0/CH1D1. */ /* Parameters required to access SPD for CH0D0/CH0D1/CH1D0/CH1D1. */
.spd[0] = { .spd[0] = {
@@ -81,17 +80,18 @@ static const struct cnl_mb_cfg memcfg = {
.dq_pins_interleaved = 1, .dq_pins_interleaved = 1,
/* /*
* VREF_CA configuraation. * VREF_CA configuration.
* Set to 0 VREF_CA goes to both CH_A and CH_B, * Set to 0 VREF_CA goes to both CH_A and CH_B,
* set to 1 VREF_CA goes to CH_A and VREF_DQ_A goes to CH_B, * set to 1 VREF_CA goes to CH_A and VREF_DQ_A goes to CH_B,
* set to 2 VREF_CA goes to CH_A and VREF_DQ_B goes to CH_B. * set to 2 VREF_CA goes to CH_A and VREF_DQ_B goes to CH_B.
*/ */
.vref_ca_config = 2, .vref_ca_config = 2,
/* Early Command Training Enabled */ /* Early Command Training */
.ect = 0, .ect = 0,
}; };
void mainboard_memory_init_params(FSPM_UPD *memupd) { void mainboard_memory_init_params(FSPM_UPD *memupd)
{
cannonlake_memcfg_init(&memupd->FspmConfig, &memcfg); cannonlake_memcfg_init(&memupd->FspmConfig, &memcfg);
} }

10
src/mainboard/system76/cml-u/variants/darp6/hda_verb.c
View File

@@ -13,13 +13,10 @@
* GNU General Public License for more details. * GNU General Public License for more details.
*/ */
#ifndef HDA_VERB_H
#define HDA_VERB_H
#include <device/azalia_device.h> #include <device/azalia_device.h>
const u32 cim_verb_data[] = { const u32 cim_verb_data[] = {
/* Realtek, ALC293 */ /* Realtek ALC293 */
0x10ec0293, /* Vendor ID */ 0x10ec0293, /* Vendor ID */
0x15581404, /* Subsystem ID */ 0x15581404, /* Subsystem ID */
12, /* Number of entries */ 12, /* Number of entries */
@@ -35,7 +32,8 @@ const u32 cim_verb_data[] = {
AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), AZALIA_PIN_CFG(0, 0x1b, 0x411111f0),
AZALIA_PIN_CFG(0, 0x1d, 0x41738205), AZALIA_PIN_CFG(0, 0x1d, 0x41738205),
AZALIA_PIN_CFG(0, 0x1e, 0x02451130), AZALIA_PIN_CFG(0, 0x1e, 0x02451130),
/* Intel, KabylakeHDMI */
/* Intel GPU HDMI */
0x8086280b, /* Vendor ID */ 0x8086280b, /* Vendor ID */
0x80860101, /* Subsystem ID */ 0x80860101, /* Subsystem ID */
4, /* Number of entries */ 4, /* Number of entries */
@@ -48,5 +46,3 @@ const u32 cim_verb_data[] = {
const u32 pc_beep_verbs[] = {}; const u32 pc_beep_verbs[] = {};
AZALIA_ARRAY_SIZES; AZALIA_ARRAY_SIZES;
#endif

10
src/mainboard/system76/cml-u/variants/galp4/hda_verb.c
View File

@@ -13,13 +13,10 @@
* GNU General Public License for more details. * GNU General Public License for more details.
*/ */
#ifndef HDA_VERB_H
#define HDA_VERB_H
#include <device/azalia_device.h> #include <device/azalia_device.h>
const u32 cim_verb_data[] = { const u32 cim_verb_data[] = {
/* Realtek, ALC293 */ /* Realtek ALC293 */
0x10ec0293, /* Vendor ID */ 0x10ec0293, /* Vendor ID */
0x15581403, /* Subsystem ID */ 0x15581403, /* Subsystem ID */
12, /* Number of entries */ 12, /* Number of entries */
@@ -35,7 +32,8 @@ const u32 cim_verb_data[] = {
AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), AZALIA_PIN_CFG(0, 0x1b, 0x411111f0),
AZALIA_PIN_CFG(0, 0x1d, 0x41738205), AZALIA_PIN_CFG(0, 0x1d, 0x41738205),
AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), AZALIA_PIN_CFG(0, 0x1e, 0x411111f0),
/* Intel, KabylakeHDMI */
/* Intel GPU HDMI */
0x8086280b, /* Vendor ID */ 0x8086280b, /* Vendor ID */
0x80860101, /* Subsystem ID */ 0x80860101, /* Subsystem ID */
4, /* Number of entries */ 4, /* Number of entries */
@@ -48,5 +46,3 @@ const u32 cim_verb_data[] = {
const u32 pc_beep_verbs[] = {}; const u32 pc_beep_verbs[] = {};
AZALIA_ARRAY_SIZES; AZALIA_ARRAY_SIZES;
#endif

8
src/mainboard/system76/whl-u/Kconfig
View File

@@ -5,7 +5,6 @@ config BOARD_SPECIFIC_OPTIONS
select ADD_FSP_BINARIES select ADD_FSP_BINARIES
select BOARD_ROMSIZE_KB_16384 select BOARD_ROMSIZE_KB_16384
select EC_ACPI select EC_ACPI
select EXCLUDE_EMMC_INTERFACE
select HAVE_ACPI_RESUME select HAVE_ACPI_RESUME
select HAVE_ACPI_TABLES select HAVE_ACPI_TABLES
select HAVE_CMOS_DEFAULT select HAVE_CMOS_DEFAULT
@@ -13,10 +12,10 @@ config BOARD_SPECIFIC_OPTIONS
select HAVE_SMI_HANDLER select HAVE_SMI_HANDLER
select INTEL_GMA_HAVE_VBT select INTEL_GMA_HAVE_VBT
select INTEL_LPSS_UART_FOR_CONSOLE select INTEL_LPSS_UART_FOR_CONSOLE
# Chip select 2 is not yet supported by intel fast_spi
# select MAINBOARD_HAS_SPI_TPM_CR50 # select MAINBOARD_HAS_SPI_TPM_CR50
# select MAINBOARD_HAS_TPM2 # select MAINBOARD_HAS_TPM2
select NO_UART_ON_SUPERIO select NO_UART_ON_SUPERIO\
select PCIE_DEBUG_INFO
select PCIEXP_HOTPLUG select PCIEXP_HOTPLUG
select SOC_INTEL_COMMON_ACPI_EC_PTS_WAK select SOC_INTEL_COMMON_ACPI_EC_PTS_WAK
select SOC_INTEL_COMMON_BLOCK_HDA select SOC_INTEL_COMMON_BLOCK_HDA
@@ -99,10 +98,11 @@ config POST_DEVICE
bool bool
default n default n
# Chip select 2 is not yet supported by intel fast_spi
#config DRIVER_TPM_SPI_BUS #config DRIVER_TPM_SPI_BUS
# hex # hex
# default 0x0 # default 0x0
#
#config DRIVER_TPM_SPI_CHIP #config DRIVER_TPM_SPI_CHIP
# int # int
# default 2 # default 2

3
src/mainboard/system76/whl-u/Makefile.inc
View File

@@ -1,2 +1,3 @@
bootblock-y += bootblock.c bootblock-y += bootblock.c
ramstage-y += ramstage.c variants/$(VARIANT_DIR)/hda_verb.c ramstage-y += ramstage.c
ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c

3
src/mainboard/system76/whl-u/bootblock.c
View File

@@ -17,6 +17,7 @@
#include <gpio.h> #include <gpio.h>
#include "gpio.h" #include "gpio.h"
void bootblock_mainboard_init(void) { void bootblock_mainboard_init(void)
{
gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
} }

2
src/mainboard/system76/whl-u/devicetree.cb
View File

@@ -8,7 +8,7 @@ chip soc/intel/cannonlake
register "SendVrMbxCmd" = "2" register "SendVrMbxCmd" = "2"
# ACPI (soc/intel/cannonlake/acpi.c) # ACPI (soc/intel/cannonlake/acpi.c)
# Enable s0ix # Disable s0ix
register "s0ix_enable" = "0" register "s0ix_enable" = "0"
# PM Timer Enabled # PM Timer Enabled

19
src/mainboard/system76/whl-u/dsdt.asl
View File

@@ -25,34 +25,23 @@ DefinitionBlock(
0x20110725 // OEM revision 0x20110725 // OEM revision
) )
{ {
// Some generic macros
#include <soc/intel/cannonlake/acpi/platform.asl> #include <soc/intel/cannonlake/acpi/platform.asl>
// global NVS and variables
#include <soc/intel/common/block/acpi/acpi/globalnvs.asl> #include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
// CPU
#include <cpu/intel/common/acpi/cpu.asl> #include <cpu/intel/common/acpi/cpu.asl>
Scope (\_SB) { Device (\_SB.PCI0)
Device (PCI0)
{ {
#include <soc/intel/cannonlake/acpi/northbridge.asl> #include <soc/intel/common/block/acpi/acpi/northbridge.asl>
#include <soc/intel/cannonlake/acpi/southbridge.asl> #include <soc/intel/cannonlake/acpi/southbridge.asl>
} }
}
// Chipset specific sleep states
#include <southbridge/intel/common/acpi/sleepstates.asl> #include <southbridge/intel/common/acpi/sleepstates.asl>
Scope (\_SB.PCI0.LPCB) { Scope (\_SB.PCI0.LPCB)
// PS/2 bus {
#include <drivers/pc80/pc/ps2_controller.asl> #include <drivers/pc80/pc/ps2_controller.asl>
// Embedded controller
#include "acpi/ec.asl" #include "acpi/ec.asl"
} }
// Mainboard specific
#include "acpi/mainboard.asl" #include "acpi/mainboard.asl"
} }

4
src/mainboard/system76/whl-u/ramstage.c
View File

@@ -16,6 +16,7 @@
#include <string.h> #include <string.h>
#include <arch/acpi.h> #include <arch/acpi.h>
#include <arch/acpigen.h> #include <arch/acpigen.h>
#include <arch/io.h>
#include <console/console.h> #include <console/console.h>
#include <device/device.h> #include <device/device.h>
#include <option.h> #include <option.h>
@@ -23,7 +24,8 @@
#include <soc/ramstage.h> #include <soc/ramstage.h>
#include "gpio.h" #include "gpio.h"
void mainboard_silicon_init_params(FSP_S_CONFIG *params) { void mainboard_silicon_init_params(FSP_S_CONFIG *params)
{
/* Configure pads prior to SiliconInit() in case there's any /* Configure pads prior to SiliconInit() in case there's any
* dependencies during hardware initialization. */ * dependencies during hardware initialization. */
cnl_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); cnl_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));

8
src/mainboard/system76/whl-u/romstage.c
View File

@@ -16,7 +16,6 @@
#include <soc/cnl_memcfg_init.h> #include <soc/cnl_memcfg_init.h>
#include <soc/romstage.h> #include <soc/romstage.h>
//TODO: find correct values
static const struct cnl_mb_cfg memcfg = { static const struct cnl_mb_cfg memcfg = {
/* Parameters required to access SPD for CH0D0/CH0D1/CH1D0/CH1D1. */ /* Parameters required to access SPD for CH0D0/CH0D1/CH1D0/CH1D1. */
.spd[0] = { .spd[0] = {
@@ -81,17 +80,18 @@ static const struct cnl_mb_cfg memcfg = {
.dq_pins_interleaved = 1, .dq_pins_interleaved = 1,
/* /*
* VREF_CA configuraation. * VREF_CA configuration.
* Set to 0 VREF_CA goes to both CH_A and CH_B, * Set to 0 VREF_CA goes to both CH_A and CH_B,
* set to 1 VREF_CA goes to CH_A and VREF_DQ_A goes to CH_B, * set to 1 VREF_CA goes to CH_A and VREF_DQ_A goes to CH_B,
* set to 2 VREF_CA goes to CH_A and VREF_DQ_B goes to CH_B. * set to 2 VREF_CA goes to CH_A and VREF_DQ_B goes to CH_B.
*/ */
.vref_ca_config = 2, .vref_ca_config = 2,
/* Early Command Training Enabled */ /* Early Command Training */
.ect = 0, .ect = 0,
}; };
void mainboard_memory_init_params(FSPM_UPD *memupd) { void mainboard_memory_init_params(FSPM_UPD *memupd)
{
cannonlake_memcfg_init(&memupd->FspmConfig, &memcfg); cannonlake_memcfg_init(&memupd->FspmConfig, &memcfg);
} }

10
src/mainboard/system76/whl-u/variants/darp5/hda_verb.c
View File

@@ -13,13 +13,10 @@
* GNU General Public License for more details. * GNU General Public License for more details.
*/ */
#ifndef HDA_VERB_H
#define HDA_VERB_H
#include <device/azalia_device.h> #include <device/azalia_device.h>
const u32 cim_verb_data[] = { const u32 cim_verb_data[] = {
/* Realtek, ALC293 */ /* Realtek ALC293 */
0x10ec0293, /* Vendor ID */ 0x10ec0293, /* Vendor ID */
0x15581325, /* Subsystem ID */ 0x15581325, /* Subsystem ID */
12, /* Number of entries */ 12, /* Number of entries */
@@ -35,7 +32,8 @@ const u32 cim_verb_data[] = {
AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), AZALIA_PIN_CFG(0, 0x1b, 0x411111f0),
AZALIA_PIN_CFG(0, 0x1d, 0x41738205), AZALIA_PIN_CFG(0, 0x1d, 0x41738205),
AZALIA_PIN_CFG(0, 0x1e, 0x02451130), AZALIA_PIN_CFG(0, 0x1e, 0x02451130),
/* Intel, KabylakeHDMI */
/* Intel GPU HDMI */
0x8086280b, /* Vendor ID */ 0x8086280b, /* Vendor ID */
0x80860101, /* Subsystem ID */ 0x80860101, /* Subsystem ID */
4, /* Number of entries */ 4, /* Number of entries */
@@ -48,5 +46,3 @@ const u32 cim_verb_data[] = {
const u32 pc_beep_verbs[] = {}; const u32 pc_beep_verbs[] = {};
AZALIA_ARRAY_SIZES; AZALIA_ARRAY_SIZES;
#endif

10
src/mainboard/system76/whl-u/variants/galp3-c/hda_verb.c
View File

@@ -13,13 +13,10 @@
* GNU General Public License for more details. * GNU General Public License for more details.
*/ */
#ifndef HDA_VERB_H
#define HDA_VERB_H
#include <device/azalia_device.h> #include <device/azalia_device.h>
const u32 cim_verb_data[] = { const u32 cim_verb_data[] = {
/* Realtek, ALC293 */ /* Realtek ALC293 */
0x10ec0293, /* Vendor ID */ 0x10ec0293, /* Vendor ID */
0x15581323, /* Subsystem ID */ 0x15581323, /* Subsystem ID */
12, /* Number of entries */ 12, /* Number of entries */
@@ -35,7 +32,8 @@ const u32 cim_verb_data[] = {
AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), AZALIA_PIN_CFG(0, 0x1b, 0x411111f0),
AZALIA_PIN_CFG(0, 0x1d, 0x40738205), AZALIA_PIN_CFG(0, 0x1d, 0x40738205),
AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), AZALIA_PIN_CFG(0, 0x1e, 0x411111f0),
/* Intel, KabylakeHDMI */
/* Intel GPU HDMI */
0x8086280b, /* Vendor ID */ 0x8086280b, /* Vendor ID */
0x80860101, /* Subsystem ID */ 0x80860101, /* Subsystem ID */
4, /* Number of entries */ 4, /* Number of entries */
@@ -48,5 +46,3 @@ const u32 cim_verb_data[] = {
const u32 pc_beep_verbs[] = {}; const u32 pc_beep_verbs[] = {};
AZALIA_ARRAY_SIZES; AZALIA_ARRAY_SIZES;
#endif