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Clean up Geode GX2 comments, whitespace and coding style. Trivial.

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Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6208 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Nils Jacobs
2010-12-26 05:12:49 +00:00
committed by Peter Stuge
parent 88929f9bf4
commit 1c6d4e6055
7 changed files with 525 additions and 605 deletions
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102
src/cpu/amd/model_gx2/cpubug.c
View File

@ -11,46 +11,35 @@
#include <cpu/x86/msr.h> #include <cpu/x86/msr.h>
#include <cpu/x86/cache.h> #include <cpu/x86/cache.h>
#if 0 #if 0
void void bug645(void)
bug645(void){ {
msr_t msr; msr_t msr;
rdmsr(CPU_ID_CONFIG); rdmsr(CPU_ID_CONFIG);
msr.whatever |= ID_CONFIG_SERIAL_SET; msr.whatever |= ID_CONFIG_SERIAL_SET;
wrmsr(msr); wrmsr(msr);
} }
void void bug573(void)
bug573(void){ {
msr_t msr; msr_t msr;
msr = rdmsr(MC_GLD_MSR_PM); msr = rdmsr(MC_GLD_MSR_PM);
msr.eax &= 0xfff3; msr.eax &= 0xfff3;
wrmsr(MC_GLD_MSR_PM); wrmsr(MC_GLD_MSR_PM);
} }
#endif #endif
/************************************************************************** /* pcideadlock
*
* pcideadlock
* *
* Bugtool #465 and #609 * Bugtool #465 and #609
* PCI cache deadlock * PCI cache deadlock
* There is also fix code in cache and PCI functions. This bug is very is pervasive. * There is also fix code in cache and PCI functions. This bug is very is pervasive.
* */
* Entry: static void pcideadlock(void)
* Exit:
* Modified:
*
**************************************************************************/
static void
pcideadlock(void)
{ {
msr_t msr; msr_t msr;
/* /* forces serialization of all load misses. Setting this bit prevents the
* forces serialization of all load misses. Setting this bit prevents the
* DM pipe from backing up if a read request has to be held up waiting * DM pipe from backing up if a read request has to be held up waiting
* for PCI writes to complete. * for PCI writes to complete.
*/ */
@ -78,20 +67,12 @@ pcideadlock(void)
wrmsr( CPU_RCONF_E0_FF, msr); wrmsr( CPU_RCONF_E0_FF, msr);
} }
/**************************************************************************** /* CPUbug784
*
* CPUbug784
* *
* Bugtool #784 + #792 * Bugtool #784 + #792
* *
* Fix CPUID instructions for < 3.0 CPUs * Fix CPUID instructions for < 3.0 CPUs
* */
* Entry:
* Exit:
* Modified:
*
****************************************************************************/
static void bug784(void) static void bug784(void)
{ {
msr_t msr; msr_t msr;
@ -120,19 +101,14 @@ static void bug784(void)
} }
/* cpubug 1398: enable MC if we KNOW we have DDR*/ /* cpubug 1398: enable MC if we KNOW we have DDR*/
/**************************************************************************
* /* CPUbugIAENG1398
* CPUbugIAENG1398
* *
* ClearQuest #IAENG1398 * ClearQuest #IAENG1398
* The MC can not be enabled with SDR memory but can for DDR. Enable for * The MC can not be enabled with SDR memory but can for DDR. Enable for
* DDR here if the setup token is "Default" * DDR here if the setup token is "Default"
* Add this back to core by default once 2.0 CPUs are not supported. * Add this back to core by default once 2.0 CPUs are not supported.
* Entry: */
* Exit:
* Modified:
*
**************************************************************************/
static void eng1398(void) static void eng1398(void)
{ {
msr_t msr; msr_t msr;
@ -150,22 +126,14 @@ static void eng1398(void)
wrmsr(MC_GLD_MSR_PM, msr); wrmsr(MC_GLD_MSR_PM, msr);
} }
/*************************************************************************** /* CPUbugIAENG2900
*
* CPUbugIAENG2900
* *
* Clear Quest IAENG00002900, VSS 118.150 * Clear Quest IAENG00002900, VSS 118.150
* *
* BTB issue causes blue screen in windows, but the fix is required * BTB issue causes blue screen in windows, but the fix is required
* for all operating systems. * for all operating systems.
* */
* Entry: static void eng2900(void)
* Exit:
* Modified:
*
**************************************************************************/
static void
eng2900(void)
{ {
msr_t msr; msr_t msr;
@ -310,10 +278,11 @@ static void bug118339(void)
msr.lo = 0x80004000; msr.lo = 0x80004000;
wrmsr(msrnum, msr); wrmsr(msrnum, msr);
/* Code to enable FS2 even when BTB and VGTEAR SWAPSiFs are enabled */ /* Code to enable FS2 even when BTB and VGTEAR SWAPSiFs are enabled
/* As per Todd Roberts in PBz1094 and PBz1095 */ * As per Todd Roberts in PBz1094 and PBz1095
/* Moved from CPUREG to CPUBUG per Tom Sylla */ * Moved from CPUREG to CPUBUG per Tom Sylla
msrnum = 0x04C000042; /* GLCP SETMCTL Register */; */
msrnum = 0x04C000042; /* GLCP SETMCTL Register */
msr = rdmsr(msrnum); msr = rdmsr(msrnum);
msr.hi |= 8; /* Bit 35 = MCP_IN */ msr.hi |= 8; /* Bit 35 = MCP_IN */
wrmsr(msrnum, msr); wrmsr(msrnum, msr);
@ -321,33 +290,24 @@ static void bug118339(void)
/****************************************************************************/ /* DisableMemoryReorder
/***/ *
/** DisableMemoryReorder*/ * PBZ 3659:
/***/ * The MC reordered transactions incorrectly and breaks coherency.
/** PBZ 3659:*/ * Disable reording and take a potential performance hit.
/** The MC reordered transactions incorrectly and breaks coherency.*/ * This is safe to do here and not in MC init since there is nothing
/** Disable reording and take a potential performance hit.*/ * to maintain coherency with and the cache is not enabled yet.
/** This is safe to do here and not in MC init since there is nothing*/ */
/** to maintain coherency with and the cache is not enabled yet.*/
/***/
/***/
/** Entry:*/
/** Exit:*/
/** Modified:*/
/***/
/****************************************************************************/
static void disablememoryreadorder(void) static void disablememoryreadorder(void)
{ {
msr_t msr; msr_t msr;
msr = rdmsr(MC_CF8F_DATA);
msr = rdmsr(MC_CF8F_DATA);
msr.hi |= CF8F_UPPER_REORDER_DIS_SET; msr.hi |= CF8F_UPPER_REORDER_DIS_SET;
wrmsr(MC_CF8F_DATA, msr); wrmsr(MC_CF8F_DATA, msr);
} }
void void cpubug(void)
cpubug(void)
{ {
msr_t msr; msr_t msr;
int rev; int rev;

8
src/cpu/amd/model_gx2/cpureginit.c
View File

@ -5,7 +5,7 @@ void cpuRegInit (void)
int msrnum; int msrnum;
msr_t msr; msr_t msr;
/* Turn on BTM for early debug based on setup. */ /* Turn on BTM for early debug based on setup. */
/* if (getnvram( TOKEN_BTM_DIAG_MODE) & 3) { */ // if (getnvram( TOKEN_BTM_DIAG_MODE) & 3) {
/* The following is only for diagnostics mode; do not use for OLPC */ /* The following is only for diagnostics mode; do not use for OLPC */
if (0) { if (0) {
/* Set Diagnostic Mode */ /* Set Diagnostic Mode */
@ -125,7 +125,7 @@ void cpuRegInit (void)
} }
/* FPU impercise exceptions bit */ /* FPU impercise exceptions bit */
/* if (getnvram( TOKEN_FPU_IE_ENABLE) != TVALUE_DISABLE) { */ //if (getnvram( TOKEN_FPU_IE_ENABLE) != TVALUE_DISABLE) {
{ {
msrnum = CPU_FPU_MSR_MODE; msrnum = CPU_FPU_MSR_MODE;
msr = rdmsr(msrnum); msr = rdmsr(msrnum);
@ -139,7 +139,7 @@ void cpuRegInit (void)
* unless you're testing something. * unless you're testing something.
*/ */
/* Allow NVRam to override DM Setup */ /* Allow NVRam to override DM Setup */
/* if (getnvram( TOKEN_CACHE_DM_MODE) != 1) { */ //if (getnvram( TOKEN_CACHE_DM_MODE) != 1) {
{ {
msrnum = CPU_DM_CONFIG0; msrnum = CPU_DM_CONFIG0;
msr = rdmsr(msrnum); msr = rdmsr(msrnum);
@ -150,7 +150,7 @@ void cpuRegInit (void)
* this unless you're testing something. * this unless you're testing something.
*/ */
/* Allow NVRam to override IM Setup */ /* Allow NVRam to override IM Setup */
/* if (getnvram( TOKEN_CACHE_IM_MODE) ==1) { */ //if (getnvram( TOKEN_CACHE_IM_MODE) ==1) {
{ {
msrnum = CPU_IM_CONFIG; msrnum = CPU_IM_CONFIG;
msr = rdmsr(msrnum); msr = rdmsr(msrnum);

15
src/cpu/amd/model_gx2/syspreinit.c
View File

@ -1,12 +1,9 @@
/* ***************************************************************************/ /* StartTimer1
/* **/ *
/* * StartTimer1*/ * Entry: none
/* **/ * Exit: Starts Timer 1 for port 61 use
/* * Entry: none*/ * Destroys: Al,
/* * Exit: Starts Timer 1 for port 61 use*/ */
/* * Destroys: Al,*/
/* **/
/* ***************************************************************************/
static void StartTimer1(void) static void StartTimer1(void)
{ {
outb(0x56, 0x43); outb(0x56, 0x43);

41
src/include/cpu/amd/gx2def.h
View File

@ -28,7 +28,6 @@
/* GLCP_SYS_RSTPLL, Lower 32 bits */ /* GLCP_SYS_RSTPLL, Lower 32 bits */
#define GLCP_SYS_RSTPLL_SWFLAGS_SHIFT 26 #define GLCP_SYS_RSTPLL_SWFLAGS_SHIFT 26
#define GLCP_SYS_RSTPLL_SWFLAGS_MASK (0x3f << 26) #define GLCP_SYS_RSTPLL_SWFLAGS_MASK (0x3f << 26)
#define GLCP_SYS_RSTPLL_LOCKWAIT 24 #define GLCP_SYS_RSTPLL_LOCKWAIT 24
#define GLCP_SYS_RSTPLL_HOLDCOUNT 16 #define GLCP_SYS_RSTPLL_HOLDCOUNT 16
#define GLCP_SYS_RSTPLL_BYPASS 15 #define GLCP_SYS_RSTPLL_BYPASS 15
@ -106,7 +105,6 @@
#define MC_GLD_MSR_PM (MSR_MC + 0x2004) #define MC_GLD_MSR_PM (MSR_MC + 0x2004)
#define MC_CF07_DATA (MSR_MC + 0x18) #define MC_CF07_DATA (MSR_MC + 0x18)
#define CF07_UPPER_D1_SZ_SHIFT 28 #define CF07_UPPER_D1_SZ_SHIFT 28
#define CF07_UPPER_D1_MB_SHIFT 24 #define CF07_UPPER_D1_MB_SHIFT 24
#define CF07_UPPER_D1_CB_SHIFT 20 #define CF07_UPPER_D1_CB_SHIFT 20
@ -115,7 +113,6 @@
#define CF07_UPPER_D0_MB_SHIFT 8 #define CF07_UPPER_D0_MB_SHIFT 8
#define CF07_UPPER_D0_CB_SHIFT 4 #define CF07_UPPER_D0_CB_SHIFT 4
#define CF07_UPPER_D0_PSZ_SHIFT 0 #define CF07_UPPER_D0_PSZ_SHIFT 0
#define CF07_LOWER_REF_INT_SHIFT 8 #define CF07_LOWER_REF_INT_SHIFT 8
#define CF07_LOWER_LOAD_MODE_DDR_SET (1 << 28) #define CF07_LOWER_LOAD_MODE_DDR_SET (1 << 28)
#define CF07_LOWER_LOAD_MODE_DLL_RESET (1 << 27) #define CF07_LOWER_LOAD_MODE_DLL_RESET (1 << 27)
@ -125,7 +122,6 @@
#define CF07_LOWER_PROG_DRAM_SET (1 << 0) #define CF07_LOWER_PROG_DRAM_SET (1 << 0)
#define MC_CF8F_DATA (MSR_MC + 0x19) #define MC_CF8F_DATA (MSR_MC + 0x19)
#define CF8F_UPPER_XOR_BS_SHIFT 19 #define CF8F_UPPER_XOR_BS_SHIFT 19
#define CF8F_UPPER_XOR_MB0_SHIFT 18 #define CF8F_UPPER_XOR_MB0_SHIFT 18
#define CF8F_UPPER_XOR_BA1_SHIFT 17 #define CF8F_UPPER_XOR_BA1_SHIFT 17
@ -142,16 +138,13 @@
#define CF8F_UPPER_HOI_LOI_SET (1 << 1) #define CF8F_UPPER_HOI_LOI_SET (1 << 1)
#define MC_CF1017_DATA (MSR_MC + 0x1A) #define MC_CF1017_DATA (MSR_MC + 0x1A)
#define CF1017_LOWER_PM1_UP_DLY_SET (1 << 8) #define CF1017_LOWER_PM1_UP_DLY_SET (1 << 8)
#define CF1017_LOWER_WR2DAT_SHIFT 0 #define CF1017_LOWER_WR2DAT_SHIFT 0
#define MC_CFCLK_DBUG (MSR_MC + 0x1D) #define MC_CFCLK_DBUG (MSR_MC + 0x1D)
#define CFCLK_UPPER_MTST_B2B_DIS_SET (1 << 2) #define CFCLK_UPPER_MTST_B2B_DIS_SET (1 << 2)
#define CFCLK_UPPER_MTST_DQS_EN_SET (1 << 1) #define CFCLK_UPPER_MTST_DQS_EN_SET (1 << 1)
#define CFCLK_UPPER_MTEST_EN_SET (1 << 0) #define CFCLK_UPPER_MTEST_EN_SET (1 << 0)
#define CFCLK_LOWER_MASK_CKE_SET1 (1 << 9) #define CFCLK_LOWER_MASK_CKE_SET1 (1 << 9)
#define CFCLK_LOWER_MASK_CKE_SET0 (1 << 8) #define CFCLK_LOWER_MASK_CKE_SET0 (1 << 8)
#define CFCLK_LOWER_SDCLK_SET (0x0F << 0) #define CFCLK_LOWER_SDCLK_SET (0x0F << 0)
@ -161,30 +154,25 @@
/* GLIU1 GLIU0 port2 */ /* GLIU1 GLIU0 port2 */
#define GLIU1_GLD_MSR_CAP (MSR_GLIU1 + 0x2000) #define GLIU1_GLD_MSR_CAP (MSR_GLIU1 + 0x2000)
#define GLIU1_GLD_MSR_PM (MSR_GLIU1 + 0x2004) #define GLIU1_GLD_MSR_PM (MSR_GLIU1 + 0x2004)
#define GLIU1_GLD_MSR_COH (MSR_GLIU1 + 0x80) #define GLIU1_GLD_MSR_COH (MSR_GLIU1 + 0x80)
/* CPU ; does not need routing instructions since we are executing there. */ /* CPU ; does not need routing instructions since we are executing there. */
#define CPU_GLD_MSR_CAP 0x2000 #define CPU_GLD_MSR_CAP 0x2000
#define CPU_GLD_MSR_CONFIG 0x2001 #define CPU_GLD_MSR_CONFIG 0x2001
#define CPU_GLD_MSR_PM 0x2004 #define CPU_GLD_MSR_PM 0x2004
#define CPU_GLD_MSR_DIAG 0x2005 #define CPU_GLD_MSR_DIAG 0x2005
#define DIAG_SEL1_MODE_SHIFT 16 #define DIAG_SEL1_MODE_SHIFT 16
#define DIAG_SEL1_SET (1 << 31) #define DIAG_SEL1_SET (1 << 31)
#define DIAG_SEL0__MODE_SHIFT 0 #define DIAG_SEL0__MODE_SHIFT 0
#define DIAG_SET0_SET (1 << 15) #define DIAG_SET0_SET (1 << 15)
#define CPU_PF_BTB_CONF 0x1100 #define CPU_PF_BTB_CONF 0x1100
#define BTB_ENABLE_SET (1 << 0) #define BTB_ENABLE_SET (1 << 0)
#define RETURN_STACK_ENABLE_SET (1 << 4) #define RETURN_STACK_ENABLE_SET (1 << 4)
#define CPU_PF_BTBRMA_BIST 0x110C #define CPU_PF_BTBRMA_BIST 0x110C
#define CPU_XC_CONFIG 0x1210 #define CPU_XC_CONFIG 0x1210
#define XC_CONFIG_SUSP_ON_HLT (1 << 0) #define XC_CONFIG_SUSP_ON_HLT (1 << 0)
#define CPU_ID_CONFIG 0x1250 #define CPU_ID_CONFIG 0x1250
#define ID_CONFIG_SERIAL_SET (1 << 0) #define ID_CONFIG_SERIAL_SET (1 << 0)
#define CPU_AC_MSR 0x1301 #define CPU_AC_MSR 0x1301
#define CPU_EX_BIST 0x1428 #define CPU_EX_BIST 0x1428
@ -218,19 +206,16 @@
#define RCONF_DEFAULT_LOWER_DEVRC_LOW_SHIFT 28 #define RCONF_DEFAULT_LOWER_DEVRC_LOW_SHIFT 28
#define RCONF_DEFAULT_LOWER_SYSTOP_SHIFT 8 #define RCONF_DEFAULT_LOWER_SYSTOP_SHIFT 8
#define RCONF_DEFAULT_LOWER_SYSRC_SHIFT 0 #define RCONF_DEFAULT_LOWER_SYSRC_SHIFT 0
#define CPU_RCONF_BYPASS 0x180A #define CPU_RCONF_BYPASS 0x180A
#define CPU_RCONF_A0_BF 0x180B #define CPU_RCONF_A0_BF 0x180B
#define CPU_RCONF_C0_DF 0x180C #define CPU_RCONF_C0_DF 0x180C
#define CPU_RCONF_E0_FF 0x180D #define CPU_RCONF_E0_FF 0x180D
#define CPU_RCONF_SMM 0x180E #define CPU_RCONF_SMM 0x180E
#define RCONF_SMM_UPPER_SMMTOP_SHIFT 12 #define RCONF_SMM_UPPER_SMMTOP_SHIFT 12
#define RCONF_SMM_UPPER_RCSMM_SHIFT 0 #define RCONF_SMM_UPPER_RCSMM_SHIFT 0
#define RCONF_SMM_LOWER_SMMBASE_SHIFT 12 #define RCONF_SMM_LOWER_SMMBASE_SHIFT 12
#define RCONF_SMM_LOWER_RCNORM_SHIFT 0 #define RCONF_SMM_LOWER_RCNORM_SHIFT 0
#define RCONF_SMM_LOWER_EN_SET (1<<8) #define RCONF_SMM_LOWER_EN_SET (1<<8)
#define CPU_RCONF_DMM 0x180F #define CPU_RCONF_DMM 0x180F
#define RCONF_DMM_UPPER_DMMTOP_SHIFT 12 #define RCONF_DMM_UPPER_DMMTOP_SHIFT 12
#define RCONF_DMM_UPPER_RCDMM_SHIFT 0 #define RCONF_DMM_UPPER_RCDMM_SHIFT 0
@ -264,6 +249,7 @@
#define CPU_L2TB_ENTRY 0x189E #define CPU_L2TB_ENTRY 0x189E
#define CPU_L2TB_ENTRY_I 0x189F #define CPU_L2TB_ENTRY_I 0x189F
#define CPU_DM_BIST 0x18C0 #define CPU_DM_BIST 0x18C0
/* SMM */ /* SMM */
#define CPU_AC_SMM_CTL 0x1301 #define CPU_AC_SMM_CTL 0x1301
#define SMM_NMI_EN_SET (1<<0) #define SMM_NMI_EN_SET (1<<0)
@ -308,16 +294,13 @@
#define RSTPLL_UPPER_MDIV_SHIFT 9 #define RSTPLL_UPPER_MDIV_SHIFT 9
#define RSTPLL_UPPER_VDIV_SHIFT 6 #define RSTPLL_UPPER_VDIV_SHIFT 6
#define RSTPLL_UPPER_FBDIV_SHIFT 0 #define RSTPLL_UPPER_FBDIV_SHIFT 0
#define RSTPLL_LOWER_SWFLAGS_SHIFT 26 #define RSTPLL_LOWER_SWFLAGS_SHIFT 26
#define RSTPLL_LOWER_SWFLAGS_MASK (0x3F<<RSTPLL_LOWER_SWFLAGS_SHIFT) #define RSTPLL_LOWER_SWFLAGS_MASK (0x3F<<RSTPLL_LOWER_SWFLAGS_SHIFT)
#define RSTPPL_LOWER_HOLD_COUNT_SHIFT 16 #define RSTPPL_LOWER_HOLD_COUNT_SHIFT 16
#define RSTPPL_LOWER_BYPASS_SHIFT 15 #define RSTPPL_LOWER_BYPASS_SHIFT 15
#define RSTPPL_LOWER_TST_SHIFT 11 #define RSTPPL_LOWER_TST_SHIFT 11
#define RSTPPL_LOWER_SDRMODE_SHIFT 10 #define RSTPPL_LOWER_SDRMODE_SHIFT 10
#define RSTPPL_LOWER_BOOTSTRAP_SHIFT 4 #define RSTPPL_LOWER_BOOTSTRAP_SHIFT 4
#define RSTPPL_LOWER_LOCK_SET (1<<25) #define RSTPPL_LOWER_LOCK_SET (1<<25)
#define RSTPPL_LOWER_LOCKWAIT_SET (1<<24) #define RSTPPL_LOWER_LOCKWAIT_SET (1<<24)
#define RSTPPL_LOWER_BYPASS_SET (1<<15) #define RSTPPL_LOWER_BYPASS_SET (1<<15)
@ -464,20 +447,20 @@
#define DMM_OFFSET 0x0C0000000 #define DMM_OFFSET 0x0C0000000
#define DMM_SIZE 128 #define DMM_SIZE 128
#define FB_OFFSET 0x41000000 #define FB_OFFSET 0x41000000
#define PCI_MEM_TOP 0x0EFFFFFFF // Top of PCI mem allocation region #define PCI_MEM_TOP 0x0EFFFFFFF /* Top of PCI mem allocation region */
#define PCI_IO_TOP 0x0EFFF // Top of PCI I/O allocation region #define PCI_IO_TOP 0x0EFFF /* Top of PCI I/O allocation region */
#define END_OPTIONROM_SPACE 0x0DFFF // E0000 is reserved for SystemROMs. #define END_OPTIONROM_SPACE 0x0DFFF /* E0000 is reserved for SystemROMs */
#define MDD_SMBUS 0x06000 // SMBUS IO location #define MDD_SMBUS 0x06000 /* SMBUS IO location */
#define MDD_GPIO 0x06100 // GPIO & ICF IO location #define MDD_GPIO 0x06100 /* GPIO & ICF IO location */
#define MDD_MFGPT 0x06200 // General Purpose Timers IO location #define MDD_MFGPT 0x06200 /* General Purpose Timers IO location */
#define MDD_IRQ_MAPPER 0x06300 // IRQ Mapper #define MDD_IRQ_MAPPER 0x06300 /* IRQ Mapper */
#define ACPI_BASE 0x09C00 // ACPI Base #define ACPI_BASE 0x09C00 /* ACPI Base */
#define MDD_PM 0x09D00 // Power Management Logic - placed at the end of ACPI #define MDD_PM 0x09D00 /* Power Management Logic - placed at the end of ACPI */
#define CS5535_IDSEL 0x02000000 // IDSEL = AD25, device #15 #define CS5535_IDSEL 0x02000000 /* IDSEL = AD25, device #15 */
#define CHIPSET_DEV_NUM 15 #define CHIPSET_DEV_NUM 15
#define IDSEL_BASE 11 // bit 11 = device 1 #define IDSEL_BASE 11 /* bit 11 = device 1 */
/* SB LBAR IO + MEMORY MAP */ /* SB LBAR IO + MEMORY MAP */
#define SMBUS_BASE (0x6000) #define SMBUS_BASE (0x6000)

9
src/northbridge/amd/gx2/grphinit.c
View File

@ -5,13 +5,10 @@
#include "chip.h" #include "chip.h"
#include "northbridge.h" #include "northbridge.h"
// FIXME handle UMA properly. /* FIXME handle UMA properly. */
#define VIDEO_MB 8 // MB of video memory #define VIDEO_MB 8 /* MB of video memory */
/* This function mirrors the Graphics_Init routine in GeodeROM. */
/*
* This function mirrors the Graphics_Init routine in GeodeROM.
*/
void graphics_init(void) void graphics_init(void)
{ {
/* SoftVG initialization */ /* SoftVG initialization */

40
src/northbridge/amd/gx2/northbridge.c
View File

@ -22,13 +22,13 @@
/* todo: add a resource record. We don't do this here because this may be called when /* todo: add a resource record. We don't do this here because this may be called when
* very little of the platform is actually working. * very little of the platform is actually working.
*/ */
int int sizeram(void)
sizeram(void)
{ {
msr_t msr; msr_t msr;
int sizem = 0; int sizem = 0;
unsigned short dimm; unsigned short dimm;
/* Get the RAM size from the memory controller as calculated and set by auto_size_dimm() */
msr = rdmsr(0x20000018); msr = rdmsr(0x20000018);
printk(BIOS_DEBUG, "sizeram: %08x:%08x\n", msr.hi, msr.lo); printk(BIOS_DEBUG, "sizeram: %08x:%08x\n", msr.hi, msr.lo);
@ -38,7 +38,6 @@ sizeram(void)
if ((dimm & 7) != 7) if ((dimm & 7) != 7)
sizem = (1 << ((dimm >> 12)-1)) * 8; sizem = (1 << ((dimm >> 12)-1)) * 8;
/* dimm 1 */ /* dimm 1 */
dimm = msr.hi >> 16; dimm = msr.hi >> 16;
/* installed? */ /* installed? */
@ -49,7 +48,6 @@ sizeram(void)
return sizem; return sizem;
} }
/* here is programming for the various MSRs. */ /* here is programming for the various MSRs. */
#define IM_QWAIT 0x100000 #define IM_QWAIT 0x100000
@ -86,9 +84,8 @@ sizeram(void)
#define IOD_BM(msr, pdid1, bizarro, ibase, imask) {msr, {.hi=(pdid1<<29)|(bizarro<<28)|(ibase>>12), .lo=(ibase<<20)|imask}} #define IOD_BM(msr, pdid1, bizarro, ibase, imask) {msr, {.hi=(pdid1<<29)|(bizarro<<28)|(ibase>>12), .lo=(ibase<<20)|imask}}
#define IOD_SC(msr, pdid1, bizarro, en, wen, ren, ibase) {msr, {.hi=(pdid1<<29)|(bizarro<<28), .lo=(en<<24)|(wen<<21)|(ren<<20)|(ibase<<3)}} #define IOD_SC(msr, pdid1, bizarro, en, wen, ren, ibase) {msr, {.hi=(pdid1<<29)|(bizarro<<28), .lo=(en<<24)|(wen<<21)|(ren<<20)|(ibase<<3)}}
struct msr_defaults
{
struct msr_defaults {
int msr_no; int msr_no;
msr_t msr; msr_t msr;
} msr_defaults [] = { } msr_defaults [] = {
@ -121,7 +118,8 @@ struct msr_defaults {
}; };
/* note that dev is NOT used -- yet */ /* note that dev is NOT used -- yet */
static void irq_init_steering(struct device *dev, u16 irq_map) { static void irq_init_steering(struct device *dev, u16 irq_map)
{
/* Set up IRQ steering */ /* Set up IRQ steering */
u32 pciAddr = 0x80000000 | (CHIPSET_DEV_NUM << 11) | 0x5C; u32 pciAddr = 0x80000000 | (CHIPSET_DEV_NUM << 11) | 0x5C;
@ -142,16 +140,12 @@ static void irq_init_steering(struct device *dev, u16 irq_map) {
outl(irq_map, 0xCFC); outl(irq_map, 0xCFC);
} }
/* setup_gx2_cache
/*
* setup_gx2_cache
* *
* Returns the amount of memory (in KB) available to the system. This is the * Returns the amount of memory (in KB) available to the system. This is the
* total amount of memory less the amount of memory reserved for SMM use. * total amount of memory less the amount of memory reserved for SMM use.
*
*/ */
static int static int setup_gx2_cache(void)
setup_gx2_cache(void)
{ {
msr_t msr; msr_t msr;
unsigned long long val; unsigned long long val;
@ -172,7 +166,7 @@ setup_gx2_cache(void)
/* yank off memory for the SMM handler */ /* yank off memory for the SMM handler */
sizekbytes -= SMM_SIZE; sizekbytes -= SMM_SIZE;
sizereg = sizekbytes; sizereg = sizekbytes;
sizereg *= 1024; // convert to bytes sizereg *= 1024; /* convert to bytes */
sizereg >>= 12; sizereg >>= 12;
sizereg <<= 8; sizereg <<= 8;
val |= sizereg; val |= sizereg;
@ -188,10 +182,8 @@ setup_gx2_cache(void)
} }
/* we have to do this here. We have not found a nicer way to do it */ /* we have to do this here. We have not found a nicer way to do it */
static void static void setup_gx2(void)
setup_gx2(void)
{ {
unsigned long tmp, tmp2; unsigned long tmp, tmp2;
msr_t msr; msr_t msr;
unsigned long size_kb, membytes; unsigned long size_kb, membytes;
@ -205,8 +197,8 @@ setup_gx2(void)
*/ */
/* we need to set 0x10000028 and 0x40000029 */ /* we need to set 0x10000028 and 0x40000029 */
/*
* These two descriptors cover the range from 1 MB (0x100000) to /* These two descriptors cover the range from 1 MB (0x100000) to
* SYSTOP (a.k.a. TOM, or Top of Memory) * SYSTOP (a.k.a. TOM, or Top of Memory)
*/ */
@ -258,11 +250,11 @@ setup_gx2(void)
msr = rdmsr(0x1808); msr = rdmsr(0x1808);
printk(BIOS_DEBUG, "MSR 0x%x is now 0x%x:0x%x\n", 0x1808, msr.hi, msr.lo); printk(BIOS_DEBUG, "MSR 0x%x is now 0x%x:0x%x\n", 0x1808, msr.hi, msr.lo);
#endif #endif
#if 0 // SDG - don't do this #if 0 /* SDG - don't do this */
/* now do the default MSR values */ /* now do the default MSR values */
for(i = 0; msr_defaults[i].msr_no; i++) { for(i = 0; msr_defaults[i].msr_no; i++) {
msr_t msr; msr_t msr;
wrmsr(msr_defaults[i].msr_no, msr_defaults[i].msr); // MSR - see table above wrmsr(msr_defaults[i].msr_no, msr_defaults[i].msr); /* MSR - see table above */
msr = rdmsr(msr_defaults[i].msr_no); msr = rdmsr(msr_defaults[i].msr_no);
printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", msr_defaults[i].msr_no, msr.hi,msr.lo); printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", msr_defaults[i].msr_no, msr.hi,msr.lo);
} }
@ -330,8 +322,6 @@ static void set_resources(struct device *dev)
#endif #endif
} }
static struct device_operations northbridge_operations = { static struct device_operations northbridge_operations = {
.read_resources = pci_dev_read_resources, .read_resources = pci_dev_read_resources,
#if 0 #if 0
@ -350,7 +340,7 @@ static const struct pci_driver northbridge_driver __pci_driver = {
.device = PCI_DEVICE_ID_NS_GX2, .device = PCI_DEVICE_ID_NS_GX2,
}; };
// FIXME handle UMA correctly. /* FIXME handle UMA correctly. */
#define FRAMEBUFFERK 4096 #define FRAMEBUFFERK 4096
static void pci_domain_set_resources(device_t dev) static void pci_domain_set_resources(device_t dev)

67
src/northbridge/amd/gx2/northbridgeinit.c
View File

@ -15,7 +15,8 @@
/* put this here for now, we are not sure where it belongs */ /* put this here for now, we are not sure where it belongs */
struct gliutable { struct gliutable
{
unsigned long desc_name; unsigned long desc_name;
unsigned short desc_type; unsigned short desc_type;
unsigned long hi, lo; unsigned long hi, lo;
@ -46,7 +47,8 @@ struct gliutable gliu1table[] = {
struct gliutable *gliutables[] = {gliu0table, gliu1table, 0}; struct gliutable *gliutables[] = {gliu0table, gliu1table, 0};
struct msrinit { struct msrinit
{
unsigned long msrnum; unsigned long msrnum;
msr_t msr; msr_t msr;
}; };
@ -64,6 +66,7 @@ struct msrinit ClockGatingDefault [] = {
{FG_GLD_MSR_PM, {.hi=0x00,.lo=0x0000}}, /* Always on */ {FG_GLD_MSR_PM, {.hi=0x00,.lo=0x0000}}, /* Always on */
{0xffffffff, {0xffffffff, 0xffffffff}}, {0xffffffff, {0xffffffff, 0xffffffff}},
}; };
/* All On */ /* All On */
struct msrinit ClockGatingAllOn[] = { struct msrinit ClockGatingAllOn[] = {
{GLIU0_GLD_MSR_PM, {.hi=0x00,.lo=0x0FFFFFFFF}}, {GLIU0_GLD_MSR_PM, {.hi=0x00,.lo=0x0FFFFFFFF}},
@ -103,8 +106,8 @@ struct msrinit GeodeLinkPriorityTable [] = {
/* do we have dmi or not? assume NO per AMD */ /* do we have dmi or not? assume NO per AMD */
int havedmi = 0; int havedmi = 0;
static void static void writeglmsr(struct gliutable *gl)
writeglmsr(struct gliutable *gl){ {
msr_t msr; msr_t msr;
msr.lo = gl->lo; msr.lo = gl->lo;
@ -116,8 +119,7 @@ writeglmsr(struct gliutable *gl){
printk(BIOS_DEBUG, "%s: AFTER write msr 0x%08lx, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo); printk(BIOS_DEBUG, "%s: AFTER write msr 0x%08lx, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo);
} }
static void static void ShadowInit(struct gliutable *gl)
ShadowInit(struct gliutable *gl)
{ {
msr_t msr; msr_t msr;
@ -132,14 +134,12 @@ ShadowInit(struct gliutable *gl)
* CLEAN ME UP * CLEAN ME UP
*/ */
/* yes, this duplicates later code, but it seems that is how they want it done. */ /* yes, this duplicates later code, but it seems that is how they want it done. */
static void static void SysmemInit(struct gliutable *gl)
SysmemInit(struct gliutable *gl)
{ {
msr_t msr; msr_t msr;
int sizembytes, sizebytes; int sizembytes, sizebytes;
/* /* Figure out how much RAM is in the machine and alocate all to the
* Figure out how much RAM is in the machine and alocate all to the
* system. We will adjust for SMM and DMM now and Frame Buffer later. * system. We will adjust for SMM and DMM now and Frame Buffer later.
*/ */
sizembytes = sizeram(); sizembytes = sizeram();
@ -164,8 +164,8 @@ SysmemInit(struct gliutable *gl)
gl->desc_name, msr.hi, msr.lo); gl->desc_name, msr.hi, msr.lo);
} }
static void static void DMMGL0Init(struct gliutable *gl)
DMMGL0Init(struct gliutable *gl) { {
msr_t msr; msr_t msr;
int sizebytes = sizeram()<<20; int sizebytes = sizeram()<<20;
long offset; long offset;
@ -191,8 +191,8 @@ DMMGL0Init(struct gliutable *gl) {
printk(BIOS_DEBUG, "%s: AFTER write msr 0x%08lx, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo); printk(BIOS_DEBUG, "%s: AFTER write msr 0x%08lx, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo);
} }
static void static void DMMGL1Init(struct gliutable *gl)
DMMGL1Init(struct gliutable *gl) { {
msr_t msr; msr_t msr;
if (! havedmi) if (! havedmi)
@ -214,8 +214,8 @@ DMMGL1Init(struct gliutable *gl) {
printk(BIOS_DEBUG, "%s: AFTER write msr 0x%08lx, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo); printk(BIOS_DEBUG, "%s: AFTER write msr 0x%08lx, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo);
} }
static void static void SMMGL0Init(struct gliutable *gl)
SMMGL0Init(struct gliutable *gl) { {
msr_t msr; msr_t msr;
int sizebytes = sizeram()<<20; int sizebytes = sizeram()<<20;
long offset; long offset;
@ -242,8 +242,8 @@ SMMGL0Init(struct gliutable *gl) {
printk(BIOS_DEBUG, "%s: AFTER write msr 0x%08lx, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo); printk(BIOS_DEBUG, "%s: AFTER write msr 0x%08lx, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo);
} }
static void static void SMMGL1Init(struct gliutable *gl)
SMMGL1Init(struct gliutable *gl) { {
msr_t msr; msr_t msr;
printk(BIOS_DEBUG, "%s:\n", __func__ ); printk(BIOS_DEBUG, "%s:\n", __func__ );
@ -259,9 +259,8 @@ SMMGL1Init(struct gliutable *gl) {
printk(BIOS_DEBUG, "%s: AFTER write msr 0x%08lx, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo); printk(BIOS_DEBUG, "%s: AFTER write msr 0x%08lx, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo);
} }
static void static void GLIUInit(struct gliutable *gl)
GLIUInit(struct gliutable *gl){ {
while (gl->desc_type != GL_END){ while (gl->desc_type != GL_END){
switch(gl->desc_type){ switch(gl->desc_type){
default: default:
@ -295,8 +294,7 @@ GLIUInit(struct gliutable *gl){
} }
} }
/* /* Set up GLPCI settings for reads/write into memory.
* Set up GLPCI settings for reads/write into memory.
* *
* R0: 0-640KB, * R0: 0-640KB,
* R1: 1MB - Top of System Memory * R1: 1MB - Top of System Memory
@ -304,7 +302,8 @@ GLIUInit(struct gliutable *gl){
* R3: Framebuffer? - not set up yet * R3: Framebuffer? - not set up yet
* R4: ?? * R4: ??
*/ */
static void GLPCIInit(void){ static void GLPCIInit(void)
{
struct gliutable *gl = 0; struct gliutable *gl = 0;
int i; int i;
msr_t msr; msr_t msr;
@ -334,7 +333,7 @@ static void GLPCIInit(void){
* base of 1M and top of around 256M * base of 1M and top of around 256M
*/ */
/* we have to create a page-aligned (4KB page) address for base and top /* we have to create a page-aligned (4KB page) address for base and top
* So we need a high page aligned addresss (pah) and low page aligned address (pal) * so we need a high page aligned addresss (pah) and low page aligned address (pal)
* pah is from msr.hi << 12 | msr.low >> 20. pal is msr.lo << 12 * pah is from msr.hi << 12 | msr.low >> 20. pal is msr.lo << 12
*/ */
printk(BIOS_DEBUG, "GLPCI r1: system msr.lo 0x%08x msr.hi 0x%08x\n", msr.lo, msr.hi); printk(BIOS_DEBUG, "GLPCI r1: system msr.lo 0x%08x msr.hi 0x%08x\n", msr.lo, msr.hi);
@ -504,8 +503,7 @@ static void GeodeLinkPriority(void)
} }
} }
/* /* Get the GLIU0 shadow register settings.
* Get the GLIU0 shadow register settings.
* *
* If the setShadow function is used then all shadow descriptors * If the setShadow function is used then all shadow descriptors
* will stay sync'ed. * will stay sync'ed.
@ -517,8 +515,7 @@ static uint64_t getShadow(void)
return ( ( (uint64_t) msr.hi ) << 32 ) | msr.lo; return ( ( (uint64_t) msr.hi ) << 32 ) | msr.lo;
} }
/* /* Set the cache RConf registers for the memory hole.
* Set the cache RConf registers for the memory hole.
* *
* Keeps all cache shadow descriptors sync'ed. * Keeps all cache shadow descriptors sync'ed.
* This is part of the PCI lockup solution. * This is part of the PCI lockup solution.
@ -572,8 +569,7 @@ static void setShadowRCONF(uint32_t shadowHi, uint32_t shadowLo)
wrmsr(CPU_RCONF_E0_FF, msr); wrmsr(CPU_RCONF_E0_FF, msr);
} }
/* /* Set the GLPCI registers for the memory hole.
* Set the GLPCI registers for the memory hole.
* Keeps all cache shadow descriptors sync'ed. * Keeps all cache shadow descriptors sync'ed.
* Entry: EDX:EAX is the shadow settings * Entry: EDX:EAX is the shadow settings
*/ */
@ -588,8 +584,7 @@ static void setShadowGLPCI(uint32_t shadowHi, uint32_t shadowLo)
wrmsr(GLPCI_REN, msr); wrmsr(GLPCI_REN, msr);
} }
/* /* Set the GLIU SC register settings. Scans descriptor tables for SC_SHADOW.
* Set the GLIU SC register settings. Scans descriptor tables for SC_SHADOW.
* Keeps all shadow descriptors sync'ed. * Keeps all shadow descriptors sync'ed.
* Entry: EDX:EAX is the shadow settings * Entry: EDX:EAX is the shadow settings
*/ */
@ -630,8 +625,7 @@ static void shadowRom(void)
setShadow(shadowSettings); setShadow(shadowSettings);
} }
/* /* Set up RCONF_DEFAULT and any other RCONF registers needed.
* Set up RCONF_DEFAULT and any other RCONF registers needed.
* *
* DEVRC_RCONF_DEFAULT: * DEVRC_RCONF_DEFAULT:
* ROMRC(63:56) = 04h ; write protect ROMBASE * ROMRC(63:56) = 04h ; write protect ROMBASE
@ -645,8 +639,7 @@ static void shadowRom(void)
#define ROMBASE_RCONF_DEFAULT 0xFFFC0000 #define ROMBASE_RCONF_DEFAULT 0xFFFC0000
#define ROMRC_RCONF_DEFAULT 0x25 #define ROMRC_RCONF_DEFAULT 0x25
static void static void RCONFInit(void)
RCONFInit(void)
{ {
struct gliutable *gl = 0; struct gliutable *gl = 0;
int i; int i;