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Clean up Geode GX2 comments, whitespace and coding style. Trivial.

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Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6208 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Nils Jacobs
2010-12-26 05:12:49 +00:00
committed by Peter Stuge
parent 88929f9bf4
commit 1c6d4e6055
7 changed files with 525 additions and 605 deletions
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140
src/cpu/amd/model_gx2/cpubug.c
View File

@ -11,49 +11,38 @@
#include <cpu/x86/msr.h> #include <cpu/x86/msr.h>
#include <cpu/x86/cache.h> #include <cpu/x86/cache.h>
#if 0 #if 0
void void bug645(void)
bug645(void){ {
msr_t msr; msr_t msr;
rdmsr(CPU_ID_CONFIG); rdmsr(CPU_ID_CONFIG);
msr.whatever |= ID_CONFIG_SERIAL_SET; msr.whatever |= ID_CONFIG_SERIAL_SET;
wrmsr(msr); wrmsr(msr);
} }
void void bug573(void)
bug573(void){ {
msr_t msr; msr_t msr;
msr = rdmsr(MC_GLD_MSR_PM); msr = rdmsr(MC_GLD_MSR_PM);
msr.eax &= 0xfff3; msr.eax &= 0xfff3;
wrmsr(MC_GLD_MSR_PM); wrmsr(MC_GLD_MSR_PM);
} }
#endif #endif
/************************************************************************** /* pcideadlock
* *
* pcideadlock * Bugtool #465 and #609
* * PCI cache deadlock
* Bugtool #465 and #609 * There is also fix code in cache and PCI functions. This bug is very is pervasive.
* PCI cache deadlock */
* There is also fix code in cache and PCI functions. This bug is very is pervasive. static void pcideadlock(void)
*
* Entry:
* Exit:
* Modified:
*
**************************************************************************/
static void
pcideadlock(void)
{ {
msr_t msr; msr_t msr;
/* /* forces serialization of all load misses. Setting this bit prevents the
* forces serialization of all load misses. Setting this bit prevents the
* DM pipe from backing up if a read request has to be held up waiting * DM pipe from backing up if a read request has to be held up waiting
* for PCI writes to complete. * for PCI writes to complete.
*/ */
msr = rdmsr(CPU_DM_CONFIG0); msr = rdmsr(CPU_DM_CONFIG0);
msr.hi &= ~(7<<DM_CONFIG0_UPPER_WSREQ_SHIFT); msr.hi &= ~(7<<DM_CONFIG0_UPPER_WSREQ_SHIFT);
msr.hi |= (2<<DM_CONFIG0_UPPER_WSREQ_SHIFT); msr.hi |= (2<<DM_CONFIG0_UPPER_WSREQ_SHIFT);
@ -78,20 +67,12 @@ pcideadlock(void)
wrmsr( CPU_RCONF_E0_FF, msr); wrmsr( CPU_RCONF_E0_FF, msr);
} }
/**************************************************************************** /* CPUbug784
* *
* CPUbug784 * Bugtool #784 + #792
* *
* Bugtool #784 + #792 * Fix CPUID instructions for < 3.0 CPUs
* */
* Fix CPUID instructions for < 3.0 CPUs
*
* Entry:
* Exit:
* Modified:
*
****************************************************************************/
static void bug784(void) static void bug784(void)
{ {
msr_t msr; msr_t msr;
@ -120,19 +101,14 @@ static void bug784(void)
} }
/* cpubug 1398: enable MC if we KNOW we have DDR*/ /* cpubug 1398: enable MC if we KNOW we have DDR*/
/**************************************************************************
/* CPUbugIAENG1398
* *
* CPUbugIAENG1398 * ClearQuest #IAENG1398
* * The MC can not be enabled with SDR memory but can for DDR. Enable for
* ClearQuest #IAENG1398 * DDR here if the setup token is "Default"
* The MC can not be enabled with SDR memory but can for DDR. Enable for * Add this back to core by default once 2.0 CPUs are not supported.
* DDR here if the setup token is "Default" */
* Add this back to core by default once 2.0 CPUs are not supported.
* Entry:
* Exit:
* Modified:
*
**************************************************************************/
static void eng1398(void) static void eng1398(void)
{ {
msr_t msr; msr_t msr;
@ -150,22 +126,14 @@ static void eng1398(void)
wrmsr(MC_GLD_MSR_PM, msr); wrmsr(MC_GLD_MSR_PM, msr);
} }
/*************************************************************************** /* CPUbugIAENG2900
* *
* CPUbugIAENG2900 * Clear Quest IAENG00002900, VSS 118.150
* *
* Clear Quest IAENG00002900, VSS 118.150 * BTB issue causes blue screen in windows, but the fix is required
* * for all operating systems.
* BTB issue causes blue screen in windows, but the fix is required */
* for all operating systems. static void eng2900(void)
*
* Entry:
* Exit:
* Modified:
*
**************************************************************************/
static void
eng2900(void)
{ {
msr_t msr; msr_t msr;
@ -267,38 +235,38 @@ static void bug118339(void)
/* Disable enable_actions in DIAGCTL while setting up GLCP */ /* Disable enable_actions in DIAGCTL while setting up GLCP */
wrmsr(MSR_GLCP + 0x005f, msr); wrmsr(MSR_GLCP + 0x005f, msr);
/* SET2M fires if VG pri is odd (3, not 2) and Ystate=0 */ /* SET2M fires if VG pri is odd (3, not 2) and Ystate=0 */
msrnum = MSR_GLCP + 0x042; msrnum = MSR_GLCP + 0x042;
/* msr.hi = 2d6b8000h */; /* msr.hi = 2d6b8000h */;
msr.hi = 0x596b8000; msr.hi = 0x596b8000;
msr.lo = 0x00000a00; msr.lo = 0x00000a00;
wrmsr(msrnum, msr); wrmsr(msrnum, msr);
/* SET3M fires if MBUS changed and VG pri is odd */ /* SET3M fires if MBUS changed and VG pri is odd */
msrnum = MSR_GLCP + 0x043; msrnum = MSR_GLCP + 0x043;
msr.hi = 0x596b8040; msr.hi = 0x596b8040;
msr.lo = 0; msr.lo = 0;
wrmsr(msrnum, msr); wrmsr(msrnum, msr);
/* Put VG request data on lower diag bus */ /* Put VG request data on lower diag bus */
msrnum = MSR_GLIU0 + 0x2005; msrnum = MSR_GLIU0 + 0x2005;
msr.hi = 0; msr.hi = 0;
msr.lo = 0x80338041; msr.lo = 0x80338041;
wrmsr(msrnum, msr); wrmsr(msrnum, msr);
/* Increment Y state if SET3M if true */ /* Increment Y state if SET3M if true */
msrnum = MSR_GLCP + 0x074; msrnum = MSR_GLCP + 0x074;
msr.hi = 0; msr.hi = 0;
msr.lo = 0x0000c000; msr.lo = 0x0000c000;
wrmsr(msrnum, msr); wrmsr(msrnum, msr);
/* Set up MBUS action to PRI=3 read of MBIU */ /* Set up MBUS action to PRI=3 read of MBIU */
msrnum = MSR_GLCP + 0x020; msrnum = MSR_GLCP + 0x020;
msr.hi = 0x0000d863; msr.hi = 0x0000d863;
msr.lo = 0x20002000; msr.lo = 0x20002000;
wrmsr(msrnum, msr); wrmsr(msrnum, msr);
/* Trigger MBUS action if VG=pri3 and Y=0, this blocks most PCI */ /* Trigger MBUS action if VG=pri3 and Y=0, this blocks most PCI */
msrnum = MSR_GLCP + 0x071; msrnum = MSR_GLCP + 0x071;
msr.hi = 0; msr.hi = 0;
msr.lo = 0x00000c00; msr.lo = 0x00000c00;
@ -310,10 +278,11 @@ static void bug118339(void)
msr.lo = 0x80004000; msr.lo = 0x80004000;
wrmsr(msrnum, msr); wrmsr(msrnum, msr);
/* Code to enable FS2 even when BTB and VGTEAR SWAPSiFs are enabled */ /* Code to enable FS2 even when BTB and VGTEAR SWAPSiFs are enabled
/* As per Todd Roberts in PBz1094 and PBz1095 */ * As per Todd Roberts in PBz1094 and PBz1095
/* Moved from CPUREG to CPUBUG per Tom Sylla */ * Moved from CPUREG to CPUBUG per Tom Sylla
msrnum = 0x04C000042; /* GLCP SETMCTL Register */; */
msrnum = 0x04C000042; /* GLCP SETMCTL Register */
msr = rdmsr(msrnum); msr = rdmsr(msrnum);
msr.hi |= 8; /* Bit 35 = MCP_IN */ msr.hi |= 8; /* Bit 35 = MCP_IN */
wrmsr(msrnum, msr); wrmsr(msrnum, msr);
@ -321,33 +290,24 @@ static void bug118339(void)
/****************************************************************************/ /* DisableMemoryReorder
/***/ *
/** DisableMemoryReorder*/ * PBZ 3659:
/***/ * The MC reordered transactions incorrectly and breaks coherency.
/** PBZ 3659:*/ * Disable reording and take a potential performance hit.
/** The MC reordered transactions incorrectly and breaks coherency.*/ * This is safe to do here and not in MC init since there is nothing
/** Disable reording and take a potential performance hit.*/ * to maintain coherency with and the cache is not enabled yet.
/** This is safe to do here and not in MC init since there is nothing*/ */
/** to maintain coherency with and the cache is not enabled yet.*/
/***/
/***/
/** Entry:*/
/** Exit:*/
/** Modified:*/
/***/
/****************************************************************************/
static void disablememoryreadorder(void) static void disablememoryreadorder(void)
{ {
msr_t msr; msr_t msr;
msr = rdmsr(MC_CF8F_DATA);
msr = rdmsr(MC_CF8F_DATA);
msr.hi |= CF8F_UPPER_REORDER_DIS_SET; msr.hi |= CF8F_UPPER_REORDER_DIS_SET;
wrmsr(MC_CF8F_DATA, msr); wrmsr(MC_CF8F_DATA, msr);
} }
void void cpubug(void)
cpubug(void)
{ {
msr_t msr; msr_t msr;
int rev; int rev;

16
src/cpu/amd/model_gx2/cpureginit.c
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@ -5,7 +5,7 @@ void cpuRegInit (void)
int msrnum; int msrnum;
msr_t msr; msr_t msr;
/* Turn on BTM for early debug based on setup. */ /* Turn on BTM for early debug based on setup. */
/* if (getnvram( TOKEN_BTM_DIAG_MODE) & 3) { */ // if (getnvram( TOKEN_BTM_DIAG_MODE) & 3) {
/* The following is only for diagnostics mode; do not use for OLPC */ /* The following is only for diagnostics mode; do not use for OLPC */
if (0) { if (0) {
/* Set Diagnostic Mode */ /* Set Diagnostic Mode */
@ -21,8 +21,8 @@ void cpuRegInit (void)
wrmsr(msrnum, msr); /* exchange it to anything else to prevent this */ wrmsr(msrnum, msr); /* exchange it to anything else to prevent this */
/* Turn off debug clock */ /* Turn off debug clock */
msrnum = 0x04C000016; /* DBG_CLK_CTL*/ msrnum = 0x04C000016; /* DBG_CLK_CTL */
msr.lo = 0x00; /* No clock*/ msr.lo = 0x00; /* No clock */
msr.hi = 0x00; msr.hi = 0x00;
wrmsr(msrnum, msr); wrmsr(msrnum, msr);
@ -64,7 +64,7 @@ void cpuRegInit (void)
msr.hi = 0; msr.hi = 0;
wrmsr(msrnum, msr); wrmsr(msrnum, msr);
msrnum = 0x04C00000C ; /* GLCP_DBGOUT MSR */ msrnum = 0x04C00000C ; /* GLCP_DBGOUT MSR */
msr.hi = 0x0; msr.hi = 0x0;
msr.lo = 0x0; /* reset value (SCOPE_SEL = 0) causes FIFO to shift out, */ msr.lo = 0x0; /* reset value (SCOPE_SEL = 0) causes FIFO to shift out, */
wrmsr(msrnum, msr); wrmsr(msrnum, msr);
@ -97,7 +97,7 @@ void cpuRegInit (void)
msrnum = MSR_FG + 0x10; msrnum = MSR_FG + 0x10;
msr = rdmsr(msrnum); msr = rdmsr(msrnum);
msr.lo &= ~3; msr.lo &= ~3;
msr.lo |= 2; /* ModeB */ msr.lo |= 2; /* ModeB */
wrmsr(msrnum, msr); wrmsr(msrnum, msr);
#endif #endif
@ -125,7 +125,7 @@ void cpuRegInit (void)
} }
/* FPU impercise exceptions bit */ /* FPU impercise exceptions bit */
/* if (getnvram( TOKEN_FPU_IE_ENABLE) != TVALUE_DISABLE) { */ //if (getnvram( TOKEN_FPU_IE_ENABLE) != TVALUE_DISABLE) {
{ {
msrnum = CPU_FPU_MSR_MODE; msrnum = CPU_FPU_MSR_MODE;
msr = rdmsr(msrnum); msr = rdmsr(msrnum);
@ -139,7 +139,7 @@ void cpuRegInit (void)
* unless you're testing something. * unless you're testing something.
*/ */
/* Allow NVRam to override DM Setup */ /* Allow NVRam to override DM Setup */
/* if (getnvram( TOKEN_CACHE_DM_MODE) != 1) { */ //if (getnvram( TOKEN_CACHE_DM_MODE) != 1) {
{ {
msrnum = CPU_DM_CONFIG0; msrnum = CPU_DM_CONFIG0;
msr = rdmsr(msrnum); msr = rdmsr(msrnum);
@ -150,7 +150,7 @@ void cpuRegInit (void)
* this unless you're testing something. * this unless you're testing something.
*/ */
/* Allow NVRam to override IM Setup */ /* Allow NVRam to override IM Setup */
/* if (getnvram( TOKEN_CACHE_IM_MODE) ==1) { */ //if (getnvram( TOKEN_CACHE_IM_MODE) ==1) {
{ {
msrnum = CPU_IM_CONFIG; msrnum = CPU_IM_CONFIG;
msr = rdmsr(msrnum); msr = rdmsr(msrnum);

15
src/cpu/amd/model_gx2/syspreinit.c
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@ -1,12 +1,9 @@
/* ***************************************************************************/ /* StartTimer1
/* **/ *
/* * StartTimer1*/ * Entry: none
/* **/ * Exit: Starts Timer 1 for port 61 use
/* * Entry: none*/ * Destroys: Al,
/* * Exit: Starts Timer 1 for port 61 use*/ */
/* * Destroys: Al,*/
/* **/
/* ***************************************************************************/
static void StartTimer1(void) static void StartTimer1(void)
{ {
outb(0x56, 0x43); outb(0x56, 0x43);

687
src/include/cpu/amd/gx2def.h
View File

@ -1,19 +1,19 @@
#ifndef CPU_AMD_GX2DEF_H #ifndef CPU_AMD_GX2DEF_H
#define CPU_AMD_GX2DEF_H #define CPU_AMD_GX2DEF_H
#define CPU_ID_1_X 0x540 /* Stepping ID 1.x*/ #define CPU_ID_1_X 0x540 /* Stepping ID 1.x*/
#define CPU_ID_2_0 0x551 /* Stepping ID 2.0*/ #define CPU_ID_2_0 0x551 /* Stepping ID 2.0*/
#define CPU_ID_2_1 0x552 /* Stepping ID 2.1*/ #define CPU_ID_2_1 0x552 /* Stepping ID 2.1*/
#define CPU_ID_2_2 0x553 /* Stepping ID 2.2*/ #define CPU_ID_2_2 0x553 /* Stepping ID 2.2*/
#define CPU_REV_1_0 0x011 #define CPU_REV_1_0 0x011
#define CPU_REV_1_1 0x012 #define CPU_REV_1_1 0x012
#define CPU_REV_1_2 0x013 #define CPU_REV_1_2 0x013
#define CPU_REV_1_3 0x014 #define CPU_REV_1_3 0x014
#define CPU_REV_2_0 0x020 #define CPU_REV_2_0 0x020
#define CPU_REV_2_1 0x021 #define CPU_REV_2_1 0x021
#define CPU_REV_2_2 0x022 #define CPU_REV_2_2 0x022
#define CPU_REV_3_0 0x030 #define CPU_REV_3_0 0x030
/* GeodeLink Control Processor Registers, GLIU1, Port 3 */ /* GeodeLink Control Processor Registers, GLIU1, Port 3 */
#define GLCP_CLK_DIS_DELAY 0x4c000008 #define GLCP_CLK_DIS_DELAY 0x4c000008
@ -21,23 +21,22 @@
#define GLCP_CHIP_REVID 0x4c000017 #define GLCP_CHIP_REVID 0x4c000017
/* GLCP_SYS_RSTPLL, Upper 32 bits */ /* GLCP_SYS_RSTPLL, Upper 32 bits */
#define GLCP_SYS_RSTPLL_MDIV_SHIFT 9 #define GLCP_SYS_RSTPLL_MDIV_SHIFT 9
#define GLCP_SYS_RSTPLL_VDIV_SHIFT 6 #define GLCP_SYS_RSTPLL_VDIV_SHIFT 6
#define GLCP_SYS_RSTPLL_FBDIV_SHIFT 0 #define GLCP_SYS_RSTPLL_FBDIV_SHIFT 0
/* GLCP_SYS_RSTPLL, Lower 32 bits */ /* GLCP_SYS_RSTPLL, Lower 32 bits */
#define GLCP_SYS_RSTPLL_SWFLAGS_SHIFT 26 #define GLCP_SYS_RSTPLL_SWFLAGS_SHIFT 26
#define GLCP_SYS_RSTPLL_SWFLAGS_MASK (0x3f << 26) #define GLCP_SYS_RSTPLL_SWFLAGS_MASK (0x3f << 26)
#define GLCP_SYS_RSTPLL_LOCKWAIT 24
#define GLCP_SYS_RSTPLL_LOCKWAIT 24 #define GLCP_SYS_RSTPLL_HOLDCOUNT 16
#define GLCP_SYS_RSTPLL_HOLDCOUNT 16 #define GLCP_SYS_RSTPLL_BYPASS 15
#define GLCP_SYS_RSTPLL_BYPASS 15 #define GLCP_SYS_RSTPLL_PD 14
#define GLCP_SYS_RSTPLL_PD 14 #define GLCP_SYS_RSTPLL_RESETPLL 13
#define GLCP_SYS_RSTPLL_RESETPLL 13 #define GLCP_SYS_RSTPLL_DDRMODE 10
#define GLCP_SYS_RSTPLL_DDRMODE 10 #define GLCP_SYS_RSTPLL_VA_SEMI_SYNC_MODE 9
#define GLCP_SYS_RSTPLL_VA_SEMI_SYNC_MODE 9 #define GLCP_SYS_RSTPLL_PCI_SEMI_SYNC_MODE 8
#define GLCP_SYS_RSTPLL_PCI_SEMI_SYNC_MODE 8 #define GLCP_SYS_RSTPLL_CHIP_RESET 0
#define GLCP_SYS_RSTPLL_CHIP_RESET 0
/* MSR routing as follows */ /* MSR routing as follows */
/* MSB = 1 means not for CPU */ /* MSB = 1 means not for CPU */
@ -61,344 +60,328 @@
/* port4 - PCI */ /* port4 - PCI */
/* port5 - FG */ /* port5 - FG */
#define GL0_GLIU0 0 #define GL0_GLIU0 0
#define GL0_MC 1 #define GL0_MC 1
#define GL0_GLIU1 2 #define GL0_GLIU1 2
#define GL0_CPU 3 #define GL0_CPU 3
#define GL0_VG 4 #define GL0_VG 4
#define GL0_GP 5 #define GL0_GP 5
#define GL0_DF 6 #define GL0_DF 6
#define GL1_GLIU0 1 #define GL1_GLIU0 1
#define GL1_GLCP 3 #define GL1_GLCP 3
#define GL1_PCI 4 #define GL1_PCI 4
#define GL1_FG 5 #define GL1_FG 5
#define GL1_VIP 5 #define GL1_VIP 5
#define GL1_AES 6 #define GL1_AES 6
#define MSR_GLIU0 (GL0_GLIU0 << 29) + (1 << 28) /* 1000xxxx - To get on GeodeLink one bit has to be set */ #define MSR_GLIU0 (GL0_GLIU0 << 29) + (1 << 28) /* 1000xxxx - To get on GeodeLink one bit has to be set */
#define MSR_MC (GL0_MC << 29) /* 2000xxxx */ #define MSR_MC (GL0_MC << 29) /* 2000xxxx */
#define MSR_GLIU1 (GL0_GLIU1 << 29) /* 4000xxxx */ #define MSR_GLIU1 (GL0_GLIU1 << 29) /* 4000xxxx */
#define MSR_CPU (GL0_CPU << 29) /* 6000xxxx - this is not used for BIOS since code executing on CPU doesn't need to be routed */ #define MSR_CPU (GL0_CPU << 29) /* 6000xxxx - this is not used for BIOS since code executing on CPU doesn't need to be routed */
#define MSR_VG (GL0_VG << 29) /* 8000xxxx */ #define MSR_VG (GL0_VG << 29) /* 8000xxxx */
#define MSR_GP (GL0_GP << 29) /* A000xxxx */ #define MSR_GP (GL0_GP << 29) /* A000xxxx */
#define MSR_DF (GL0_DF << 29) /* C000xxxx */ #define MSR_DF (GL0_DF << 29) /* C000xxxx */
#define MSR_GLCP (GL1_GLCP << 26) + MSR_GLIU1 /* 4C00xxxx */ #define MSR_GLCP (GL1_GLCP << 26) + MSR_GLIU1 /* 4C00xxxx */
#define MSR_PCI (GL1_PCI << 26) + MSR_GLIU1 /* 5000xxxx */ #define MSR_PCI (GL1_PCI << 26) + MSR_GLIU1 /* 5000xxxx */
#define MSR_FG (GL1_FG << 26) + MSR_GLIU1 /* 5400xxxx */ #define MSR_FG (GL1_FG << 26) + MSR_GLIU1 /* 5400xxxx */
#define MSR_VIP ((GL1_VIP << 26) + MSR_GLIU1) /* 5400xxxx */ #define MSR_VIP ((GL1_VIP << 26) + MSR_GLIU1) /* 5400xxxx */
#define MSR_AES ((GL1_AES << 26) + MSR_GLIU1) /* 5800xxxx */ #define MSR_AES ((GL1_AES << 26) + MSR_GLIU1) /* 5800xxxx */
/* South Bridge */ /* South Bridge */
#define SB_PORT 2 /* port of the SouthBridge */ #define SB_PORT 2 /* port of the SouthBridge */
/* GeodeLink Interface Unit 0 (GLIU0) port0 */ /* GeodeLink Interface Unit 0 (GLIU0) port0 */
#define GLIU0_GLD_MSR_CAP (MSR_GLIU0 + 0x2000) #define GLIU0_GLD_MSR_CAP (MSR_GLIU0 + 0x2000)
#define GLIU0_GLD_MSR_PM (MSR_GLIU0 + 0x2004) #define GLIU0_GLD_MSR_PM (MSR_GLIU0 + 0x2004)
#define GLIU0_DESC_BASE (MSR_GLIU0 + 0x20) #define GLIU0_DESC_BASE (MSR_GLIU0 + 0x20)
#define GLIU0_CAP (MSR_GLIU0 + 0x86) #define GLIU0_CAP (MSR_GLIU0 + 0x86)
#define GLIU0_GLD_MSR_COH (MSR_GLIU0 + 0x80) #define GLIU0_GLD_MSR_COH (MSR_GLIU0 + 0x80)
/* Memory Controller GLIU0 port 1 */ /* Memory Controller GLIU0 port 1 */
#define MC_GLD_MSR_CAP (MSR_MC + 0x2000) #define MC_GLD_MSR_CAP (MSR_MC + 0x2000)
#define MC_GLD_MSR_PM (MSR_MC + 0x2004) #define MC_GLD_MSR_PM (MSR_MC + 0x2004)
#define MC_CF07_DATA (MSR_MC + 0x18) #define MC_CF07_DATA (MSR_MC + 0x18)
#define CF07_UPPER_D1_SZ_SHIFT 28
#define CF07_UPPER_D1_MB_SHIFT 24
#define CF07_UPPER_D1_CB_SHIFT 20
#define CF07_UPPER_D1_PSZ_SHIFT 16
#define CF07_UPPER_D0_SZ_SHIFT 12
#define CF07_UPPER_D0_MB_SHIFT 8
#define CF07_UPPER_D0_CB_SHIFT 4
#define CF07_UPPER_D0_PSZ_SHIFT 0
#define CF07_LOWER_REF_INT_SHIFT 8
#define CF07_LOWER_LOAD_MODE_DDR_SET (1 << 28)
#define CF07_LOWER_LOAD_MODE_DLL_RESET (1 << 27)
#define CF07_LOWER_EMR_QFC_SET (1 << 26)
#define CF07_LOWER_EMR_DRV_SET (1 << 25)
#define CF07_LOWER_REF_TEST_SET (1 << 3)
#define CF07_LOWER_PROG_DRAM_SET (1 << 0)
#define CF07_UPPER_D1_SZ_SHIFT 28 #define MC_CF8F_DATA (MSR_MC + 0x19)
#define CF07_UPPER_D1_MB_SHIFT 24 #define CF8F_UPPER_XOR_BS_SHIFT 19
#define CF07_UPPER_D1_CB_SHIFT 20 #define CF8F_UPPER_XOR_MB0_SHIFT 18
#define CF07_UPPER_D1_PSZ_SHIFT 16 #define CF8F_UPPER_XOR_BA1_SHIFT 17
#define CF07_UPPER_D0_SZ_SHIFT 12 #define CF8F_UPPER_XOR_BA0_SHIFT 16
#define CF07_UPPER_D0_MB_SHIFT 8 #define CF8F_UPPER_REORDER_DIS_SET (1 << 8)
#define CF07_UPPER_D0_CB_SHIFT 4 #define CF8F_UPPER_REG_DIMM_SHIFT 4
#define CF07_UPPER_D0_PSZ_SHIFT 0 #define CF8F_LOWER_CAS_LAT_SHIFT 28
#define CF8F_LOWER_REF2ACT_SHIFT 24
#define CF8F_LOWER_ACT2PRE_SHIFT 20
#define CF8F_LOWER_PRE2ACT_SHIFT 16
#define CF8F_LOWER_ACT2CMD_SHIFT 12
#define CF8F_LOWER_ACT2ACT_SHIFT 8
#define CF8F_UPPER_32BIT_SET (1 << 5)
#define CF8F_UPPER_HOI_LOI_SET (1 << 1)
#define CF07_LOWER_REF_INT_SHIFT 8 #define MC_CF1017_DATA (MSR_MC + 0x1A)
#define CF07_LOWER_LOAD_MODE_DDR_SET (1 << 28) #define CF1017_LOWER_PM1_UP_DLY_SET (1 << 8)
#define CF07_LOWER_LOAD_MODE_DLL_RESET (1 << 27) #define CF1017_LOWER_WR2DAT_SHIFT 0
#define CF07_LOWER_EMR_QFC_SET (1 << 26)
#define CF07_LOWER_EMR_DRV_SET (1 << 25)
#define CF07_LOWER_REF_TEST_SET (1 << 3)
#define CF07_LOWER_PROG_DRAM_SET (1 << 0)
#define MC_CF8F_DATA (MSR_MC + 0x19) #define MC_CFCLK_DBUG (MSR_MC + 0x1D)
#define CFCLK_UPPER_MTST_B2B_DIS_SET (1 << 2)
#define CFCLK_UPPER_MTST_DQS_EN_SET (1 << 1)
#define CFCLK_UPPER_MTEST_EN_SET (1 << 0)
#define CFCLK_LOWER_MASK_CKE_SET1 (1 << 9)
#define CFCLK_LOWER_MASK_CKE_SET0 (1 << 8)
#define CFCLK_LOWER_SDCLK_SET (0x0F << 0)
#define CF8F_UPPER_XOR_BS_SHIFT 19 #define MC_CF_RDSYNC (MSR_MC + 0x1F)
#define CF8F_UPPER_XOR_MB0_SHIFT 18
#define CF8F_UPPER_XOR_BA1_SHIFT 17
#define CF8F_UPPER_XOR_BA0_SHIFT 16
#define CF8F_UPPER_REORDER_DIS_SET (1 << 8)
#define CF8F_UPPER_REG_DIMM_SHIFT 4
#define CF8F_LOWER_CAS_LAT_SHIFT 28
#define CF8F_LOWER_REF2ACT_SHIFT 24
#define CF8F_LOWER_ACT2PRE_SHIFT 20
#define CF8F_LOWER_PRE2ACT_SHIFT 16
#define CF8F_LOWER_ACT2CMD_SHIFT 12
#define CF8F_LOWER_ACT2ACT_SHIFT 8
#define CF8F_UPPER_32BIT_SET (1 << 5)
#define CF8F_UPPER_HOI_LOI_SET (1 << 1)
#define MC_CF1017_DATA (MSR_MC + 0x1A)
#define CF1017_LOWER_PM1_UP_DLY_SET (1 << 8)
#define CF1017_LOWER_WR2DAT_SHIFT 0
#define MC_CFCLK_DBUG (MSR_MC + 0x1D)
#define CFCLK_UPPER_MTST_B2B_DIS_SET (1 << 2)
#define CFCLK_UPPER_MTST_DQS_EN_SET (1 << 1)
#define CFCLK_UPPER_MTEST_EN_SET (1 << 0)
#define CFCLK_LOWER_MASK_CKE_SET1 (1 << 9)
#define CFCLK_LOWER_MASK_CKE_SET0 (1 << 8)
#define CFCLK_LOWER_SDCLK_SET (0x0F << 0)
#define MC_CF_RDSYNC (MSR_MC + 0x1F)
/* GLIU1 GLIU0 port2 */ /* GLIU1 GLIU0 port2 */
#define GLIU1_GLD_MSR_CAP (MSR_GLIU1 + 0x2000) #define GLIU1_GLD_MSR_CAP (MSR_GLIU1 + 0x2000)
#define GLIU1_GLD_MSR_PM (MSR_GLIU1 + 0x2004) #define GLIU1_GLD_MSR_PM (MSR_GLIU1 + 0x2004)
#define GLIU1_GLD_MSR_COH (MSR_GLIU1 + 0x80) #define GLIU1_GLD_MSR_COH (MSR_GLIU1 + 0x80)
/* CPU ; does not need routing instructions since we are executing there. */ /* CPU ; does not need routing instructions since we are executing there. */
#define CPU_GLD_MSR_CAP 0x2000 #define CPU_GLD_MSR_CAP 0x2000
#define CPU_GLD_MSR_CONFIG 0x2001 #define CPU_GLD_MSR_CONFIG 0x2001
#define CPU_GLD_MSR_PM 0x2004 #define CPU_GLD_MSR_PM 0x2004
#define CPU_GLD_MSR_DIAG 0x2005
#define CPU_GLD_MSR_DIAG 0x2005 #define DIAG_SEL1_MODE_SHIFT 16
#define DIAG_SEL1_MODE_SHIFT 16 #define DIAG_SEL1_SET (1 << 31)
#define DIAG_SEL1_SET (1 << 31) #define DIAG_SEL0__MODE_SHIFT 0
#define DIAG_SEL0__MODE_SHIFT 0 #define DIAG_SET0_SET (1 << 15)
#define DIAG_SET0_SET (1 << 15) #define CPU_PF_BTB_CONF 0x1100
#define BTB_ENABLE_SET (1 << 0)
#define CPU_PF_BTB_CONF 0x1100 #define RETURN_STACK_ENABLE_SET (1 << 4)
#define BTB_ENABLE_SET (1 << 0) #define CPU_PF_BTBRMA_BIST 0x110C
#define RETURN_STACK_ENABLE_SET (1 << 4) #define CPU_XC_CONFIG 0x1210
#define CPU_PF_BTBRMA_BIST 0x110C #define XC_CONFIG_SUSP_ON_HLT (1 << 0)
#define CPU_ID_CONFIG 0x1250
#define CPU_XC_CONFIG 0x1210 #define ID_CONFIG_SERIAL_SET (1 << 0)
#define XC_CONFIG_SUSP_ON_HLT (1 << 0) #define CPU_AC_MSR 0x1301
#define CPU_ID_CONFIG 0x1250 #define CPU_EX_BIST 0x1428
#define ID_CONFIG_SERIAL_SET (1 << 0)
#define CPU_AC_MSR 0x1301
#define CPU_EX_BIST 0x1428
/* IM */ /* IM */
#define CPU_IM_CONFIG 0x1700 #define CPU_IM_CONFIG 0x1700
#define IM_CONFIG_LOWER_ICD_SET (1 << 8) #define IM_CONFIG_LOWER_ICD_SET (1 << 8)
#define IM_CONFIG_LOWER_QWT_SET (1 << 20) #define IM_CONFIG_LOWER_QWT_SET (1 << 20)
#define CPU_IC_INDEX 0x1710 #define CPU_IC_INDEX 0x1710
#define CPU_IC_DATA 0x1711 #define CPU_IC_DATA 0x1711
#define CPU_IC_TAG 0x1712 #define CPU_IC_TAG 0x1712
#define CPU_IC_TAG_I 0x1713 #define CPU_IC_TAG_I 0x1713
#define CPU_ITB_INDEX 0x1720 #define CPU_ITB_INDEX 0x1720
#define CPU_ITB_LRU 0x1721 #define CPU_ITB_LRU 0x1721
#define CPU_ITB_ENTRY 0x1722 #define CPU_ITB_ENTRY 0x1722
#define CPU_ITB_ENTRY_I 0x1723 #define CPU_ITB_ENTRY_I 0x1723
#define CPU_IM_BIST_TAG 0x1730 #define CPU_IM_BIST_TAG 0x1730
#define CPU_IM_BIST_DATA 0x1731 #define CPU_IM_BIST_DATA 0x1731
/* various CPU MSRs */ /* various CPU MSRs */
#define CPU_DM_CONFIG0 0x1800 #define CPU_DM_CONFIG0 0x1800
#define DM_CONFIG0_UPPER_WSREQ_SHIFT 12 #define DM_CONFIG0_UPPER_WSREQ_SHIFT 12
#define DM_CONFIG0_LOWER_DCDIS_SET (1<<8) #define DM_CONFIG0_LOWER_DCDIS_SET (1<<8)
#define DM_CONFIG0_LOWER_WBINVD_SET (1<<5) #define DM_CONFIG0_LOWER_WBINVD_SET (1<<5)
#define DM_CONFIG0_LOWER_MISSER_SET (1<<1) #define DM_CONFIG0_LOWER_MISSER_SET (1<<1)
/* configuration MSRs */ /* configuration MSRs */
#define CPU_RCONF_DEFAULT 0x1808 #define CPU_RCONF_DEFAULT 0x1808
#define RCONF_DEFAULT_UPPER_ROMRC_SHIFT 24 #define RCONF_DEFAULT_UPPER_ROMRC_SHIFT 24
#define RCONF_DEFAULT_UPPER_ROMBASE_SHIFT 4 #define RCONF_DEFAULT_UPPER_ROMBASE_SHIFT 4
#define RCONF_DEFAULT_UPPER_DEVRC_HI_SHIFT 0 #define RCONF_DEFAULT_UPPER_DEVRC_HI_SHIFT 0
#define RCONF_DEFAULT_LOWER_DEVRC_LOW_SHIFT 28 #define RCONF_DEFAULT_LOWER_DEVRC_LOW_SHIFT 28
#define RCONF_DEFAULT_LOWER_SYSTOP_SHIFT 8 #define RCONF_DEFAULT_LOWER_SYSTOP_SHIFT 8
#define RCONF_DEFAULT_LOWER_SYSRC_SHIFT 0 #define RCONF_DEFAULT_LOWER_SYSRC_SHIFT 0
#define CPU_RCONF_BYPASS 0x180A
#define CPU_RCONF_A0_BF 0x180B
#define CPU_RCONF_C0_DF 0x180C
#define CPU_RCONF_E0_FF 0x180D
#define CPU_RCONF_SMM 0x180E
#define RCONF_SMM_UPPER_SMMTOP_SHIFT 12
#define RCONF_SMM_UPPER_RCSMM_SHIFT 0
#define RCONF_SMM_LOWER_SMMBASE_SHIFT 12
#define RCONF_SMM_LOWER_RCNORM_SHIFT 0
#define RCONF_SMM_LOWER_EN_SET (1<<8)
#define CPU_RCONF_DMM 0x180F
#define RCONF_DMM_UPPER_DMMTOP_SHIFT 12
#define RCONF_DMM_UPPER_RCDMM_SHIFT 0
#define RCONF_DMM_LOWER_DMMBASE_SHIFT 12
#define RCONF_DMM_LOWER_RCNORM_SHIFT 0
#define RCONF_DMM_LOWER_EN_SET (1<<8)
#define CPU_RCONF_BYPASS 0x180A #define CPU_RCONF0 0x1810
#define CPU_RCONF_A0_BF 0x180B #define CPU_RCONF1 0x1811
#define CPU_RCONF_C0_DF 0x180C #define CPU_RCONF2 0x1812
#define CPU_RCONF_E0_FF 0x180D #define CPU_RCONF3 0x1813
#define CPU_RCONF4 0x1814
#define CPU_RCONF5 0x1815
#define CPU_RCONF6 0x1816
#define CPU_RCONF7 0x1817
#define CPU_CR1_MSR 0x1881
#define CPU_CR2_MSR 0x1882
#define CPU_CR3_MSR 0x1883
#define CPU_CR4_MSR 0x1884
#define CPU_DC_INDEX 0x1890
#define CPU_DC_DATA 0x1891
#define CPU_DC_TAG 0x1892
#define CPU_DC_TAG_I 0x1893
#define CPU_SNOOP 0x1894
#define CPU_DTB_INDEX 0x1898
#define CPU_DTB_LRU 0x1899
#define CPU_DTB_ENTRY 0x189A
#define CPU_DTB_ENTRY_I 0x189B
#define CPU_L2TB_INDEX 0x189C
#define CPU_L2TB_LRU 0x189D
#define CPU_L2TB_ENTRY 0x189E
#define CPU_L2TB_ENTRY_I 0x189F
#define CPU_DM_BIST 0x18C0
#define CPU_RCONF_SMM 0x180E /* SMM */
#define RCONF_SMM_UPPER_SMMTOP_SHIFT 12 #define CPU_AC_SMM_CTL 0x1301
#define RCONF_SMM_UPPER_RCSMM_SHIFT 0 #define SMM_NMI_EN_SET (1<<0)
#define RCONF_SMM_LOWER_SMMBASE_SHIFT 12 #define SMM_SUSP_EN_SET (1<<1)
#define RCONF_SMM_LOWER_RCNORM_SHIFT 0 #define NEST_SMI_EN_SET (1<<2)
#define RCONF_SMM_LOWER_EN_SET (1<<8) #define SMM_INST_EN_SET (1<<3)
#define INTL_SMI_EN_SET (1<<4)
#define EXTL_SMI_EN_SET (1<<5)
#define CPU_RCONF_DMM 0x180F #define CPU_FPU_MSR_MODE 0x1A00
#define RCONF_DMM_UPPER_DMMTOP_SHIFT 12 #define FPU_IE_SET (1<<0)
#define RCONF_DMM_UPPER_RCDMM_SHIFT 0
#define RCONF_DMM_LOWER_DMMBASE_SHIFT 12
#define RCONF_DMM_LOWER_RCNORM_SHIFT 0
#define RCONF_DMM_LOWER_EN_SET (1<<8)
#define CPU_RCONF0 0x1810 #define CPU_FP_UROM_BIST 0x1A03
#define CPU_RCONF1 0x1811
#define CPU_RCONF2 0x1812
#define CPU_RCONF3 0x1813
#define CPU_RCONF4 0x1814
#define CPU_RCONF5 0x1815
#define CPU_RCONF6 0x1816
#define CPU_RCONF7 0x1817
#define CPU_CR1_MSR 0x1881
#define CPU_CR2_MSR 0x1882
#define CPU_CR3_MSR 0x1883
#define CPU_CR4_MSR 0x1884
#define CPU_DC_INDEX 0x1890
#define CPU_DC_DATA 0x1891
#define CPU_DC_TAG 0x1892
#define CPU_DC_TAG_I 0x1893
#define CPU_SNOOP 0x1894
#define CPU_DTB_INDEX 0x1898
#define CPU_DTB_LRU 0x1899
#define CPU_DTB_ENTRY 0x189A
#define CPU_DTB_ENTRY_I 0x189B
#define CPU_L2TB_INDEX 0x189C
#define CPU_L2TB_LRU 0x189D
#define CPU_L2TB_ENTRY 0x189E
#define CPU_L2TB_ENTRY_I 0x189F
#define CPU_DM_BIST 0x18C0
/* SMM */
#define CPU_AC_SMM_CTL 0x1301
#define SMM_NMI_EN_SET (1<<0)
#define SMM_SUSP_EN_SET (1<<1)
#define NEST_SMI_EN_SET (1<<2)
#define SMM_INST_EN_SET (1<<3)
#define INTL_SMI_EN_SET (1<<4)
#define EXTL_SMI_EN_SET (1<<5)
#define CPU_FPU_MSR_MODE 0x1A00 #define CPU_BC_CONF_0 0x1900
#define FPU_IE_SET (1<<0) #define TSC_SUSP_SET (1<<5)
#define SUSP_EN_SET (1<<12)
#define CPU_FP_UROM_BIST 0x1A03
#define CPU_BC_CONF_0 0x1900
#define TSC_SUSP_SET (1<<5)
#define SUSP_EN_SET (1<<12)
/* VG GLIU0 port4 */ /* VG GLIU0 port4 */
#define VG_GLD_MSR_CAP (MSR_VG + 0x2000) #define VG_GLD_MSR_CAP (MSR_VG + 0x2000)
#define VG_GLD_MSR_CONFIG (MSR_VG + 0x2001) #define VG_GLD_MSR_CONFIG (MSR_VG + 0x2001)
#define VG_GLD_MSR_PM (MSR_VG + 0x2004) #define VG_GLD_MSR_PM (MSR_VG + 0x2004)
#define GP_GLD_MSR_CAP (MSR_GP + 0x2000) #define GP_GLD_MSR_CAP (MSR_GP + 0x2000)
#define GP_GLD_MSR_CONFIG (MSR_GP + 0x2001) #define GP_GLD_MSR_CONFIG (MSR_GP + 0x2001)
#define GP_GLD_MSR_PM (MSR_GP + 0x2004) #define GP_GLD_MSR_PM (MSR_GP + 0x2004)
/* DF GLIU0 port6 */ /* DF GLIU0 port6 */
#define DF_GLD_MSR_CAP (MSR_DF + 0x2000) #define DF_GLD_MSR_CAP (MSR_DF + 0x2000)
#define DF_GLD_MSR_MASTER_CONF (MSR_DF + 0x2001) #define DF_GLD_MSR_MASTER_CONF (MSR_DF + 0x2001)
#define DF_LOWER_LCD_SHIFT 6 #define DF_LOWER_LCD_SHIFT 6
#define DF_GLD_MSR_PM (MSR_DF + 0x2004) #define DF_GLD_MSR_PM (MSR_DF + 0x2004)
/* GeodeLink Control Processor GLIU1 port3 */ /* GeodeLink Control Processor GLIU1 port3 */
#define GLCP_GLD_MSR_CAP (MSR_GLCP + 0x2000) #define GLCP_GLD_MSR_CAP (MSR_GLCP + 0x2000)
#define GLCP_GLD_MSR_CONF (MSR_GLCP + 0x2001) #define GLCP_GLD_MSR_CONF (MSR_GLCP + 0x2001)
#define GLCP_GLD_MSR_PM (MSR_GLCP + 0x2004) #define GLCP_GLD_MSR_PM (MSR_GLCP + 0x2004)
#define GLCP_DELAY_CONTROLS (MSR_GLCP + 0x0F) #define GLCP_DELAY_CONTROLS (MSR_GLCP + 0x0F)
#define GLCP_SYS_RSTPLL (MSR_GLCP +0x14 /* R/W */) #define GLCP_SYS_RSTPLL (MSR_GLCP +0x14 /* R/W */)
#define RSTPLL_UPPER_MDIV_SHIFT 9 #define RSTPLL_UPPER_MDIV_SHIFT 9
#define RSTPLL_UPPER_VDIV_SHIFT 6 #define RSTPLL_UPPER_VDIV_SHIFT 6
#define RSTPLL_UPPER_FBDIV_SHIFT 0 #define RSTPLL_UPPER_FBDIV_SHIFT 0
#define RSTPLL_LOWER_SWFLAGS_SHIFT 26
#define RSTPLL_LOWER_SWFLAGS_MASK (0x3F<<RSTPLL_LOWER_SWFLAGS_SHIFT)
#define RSTPPL_LOWER_HOLD_COUNT_SHIFT 16
#define RSTPPL_LOWER_BYPASS_SHIFT 15
#define RSTPPL_LOWER_TST_SHIFT 11
#define RSTPPL_LOWER_SDRMODE_SHIFT 10
#define RSTPPL_LOWER_BOOTSTRAP_SHIFT 4
#define RSTPPL_LOWER_LOCK_SET (1<<25)
#define RSTPPL_LOWER_LOCKWAIT_SET (1<<24)
#define RSTPPL_LOWER_BYPASS_SET (1<<15)
#define RSTPPL_LOWER_PD_SET (1<<14)
#define RSTPPL_LOWER_PLL_RESET_SET (1<<13)
#define RSTPPL_LOWER_SDRMODE_SET (1<<10)
#define RSTPPL_LOWER_CPU_SEMI_SYNC_SET (1<<9)
#define RSTPPL_LOWER_PCI_SEMI_SYNC_SET (1<<8)
#define RSTPPL_LOWER_CHIP_RESET_SET (1<<0)
#define RSTPLL_LOWER_SWFLAGS_SHIFT 26 #define GLCP_DOTPLL (MSR_GLCP + 0x15 /* R/W */)
#define RSTPLL_LOWER_SWFLAGS_MASK (0x3F<<RSTPLL_LOWER_SWFLAGS_SHIFT) #define DOTPPL_LOWER_PD_SET (1<<14)
#define RSTPPL_LOWER_HOLD_COUNT_SHIFT 16
#define RSTPPL_LOWER_BYPASS_SHIFT 15
#define RSTPPL_LOWER_TST_SHIFT 11
#define RSTPPL_LOWER_SDRMODE_SHIFT 10
#define RSTPPL_LOWER_BOOTSTRAP_SHIFT 4
#define RSTPPL_LOWER_LOCK_SET (1<<25)
#define RSTPPL_LOWER_LOCKWAIT_SET (1<<24)
#define RSTPPL_LOWER_BYPASS_SET (1<<15)
#define RSTPPL_LOWER_PD_SET (1<<14)
#define RSTPPL_LOWER_PLL_RESET_SET (1<<13)
#define RSTPPL_LOWER_SDRMODE_SET (1<<10)
#define RSTPPL_LOWER_CPU_SEMI_SYNC_SET (1<<9)
#define RSTPPL_LOWER_PCI_SEMI_SYNC_SET (1<<8)
#define RSTPPL_LOWER_CHIP_RESET_SET (1<<0)
#define GLCP_DOTPLL (MSR_GLCP + 0x15 /* R/W */)
#define DOTPPL_LOWER_PD_SET (1<<14)
/* GLIU1 port 4 */ /* GLIU1 port 4 */
#define GLPCI_GLD_MSR_CAP (MSR_PCI + 0x2000) #define GLPCI_GLD_MSR_CAP (MSR_PCI + 0x2000)
#define GLPCI_GLD_MSR_CONFIG (MSR_PCI + 0x2001) #define GLPCI_GLD_MSR_CONFIG (MSR_PCI + 0x2001)
#define GLPCI_GLD_MSR_PM (MSR_PCI + 0x2004) #define GLPCI_GLD_MSR_PM (MSR_PCI + 0x2004)
#define GLPCI_CTRL (MSR_PCI + 0x2010) #define GLPCI_CTRL (MSR_PCI + 0x2010)
#define GLPCI_CTRL_UPPER_FTH_SHIFT 28 #define GLPCI_CTRL_UPPER_FTH_SHIFT 28
#define GLPCI_CTRL_UPPER_RTH_SHIFT 24 #define GLPCI_CTRL_UPPER_RTH_SHIFT 24
#define GLPCI_CTRL_UPPER_SBRTH_SHIFT 20 #define GLPCI_CTRL_UPPER_SBRTH_SHIFT 20
#define GLPCI_CTRL_UPPER_DTL_SHIFT 14 #define GLPCI_CTRL_UPPER_DTL_SHIFT 14
#define GLPCI_CTRL_UPPER_WTO_SHIFT 11 #define GLPCI_CTRL_UPPER_WTO_SHIFT 11
#define GLPCI_CTRL_UPPER_LAT_SHIFT 3 #define GLPCI_CTRL_UPPER_LAT_SHIFT 3
#define GLPCI_CTRL_UPPER_ILTO_SHIFT 8 #define GLPCI_CTRL_UPPER_ILTO_SHIFT 8
#define GLPCI_CTRL_LOWER_IRFT_SHIFT 18 #define GLPCI_CTRL_LOWER_IRFT_SHIFT 18
#define GLPCI_CTRL_LOWER_IRFC_SHIFT 16 #define GLPCI_CTRL_LOWER_IRFC_SHIFT 16
#define GLPCI_CTRL_LOWER_ER_SET (1<<11) #define GLPCI_CTRL_LOWER_ER_SET (1<<11)
#define GLPCI_CTRL_LOWER_LDE_SET (1<<9) #define GLPCI_CTRL_LOWER_LDE_SET (1<<9)
#define GLPCI_CTRL_LOWER_OWC_SET (1<<4) #define GLPCI_CTRL_LOWER_OWC_SET (1<<4)
#define GLPCI_CTRL_LOWER_IWC_SET (1<<3) #define GLPCI_CTRL_LOWER_IWC_SET (1<<3)
#define GLPCI_CTRL_LOWER_PCD_SET (1<<2) #define GLPCI_CTRL_LOWER_PCD_SET (1<<2)
#define GLPCI_CTRL_LOWER_ME_SET (1<<0) #define GLPCI_CTRL_LOWER_ME_SET (1<<0)
#define GLPCI_ARB (MSR_PCI + 0x2011) #define GLPCI_ARB (MSR_PCI + 0x2011)
#define GLPCI_ARB_UPPER_BM1_SET (1<<17) #define GLPCI_ARB_UPPER_BM1_SET (1<<17)
#define GLPCI_ARB_UPPER_BM0_SET (1<<16) #define GLPCI_ARB_UPPER_BM0_SET (1<<16)
#define GLPCI_ARB_UPPER_CPRE_SET (1<<15) #define GLPCI_ARB_UPPER_CPRE_SET (1<<15)
#define GLPCI_ARB_UPPER_PRE2_SET (1<<10) #define GLPCI_ARB_UPPER_PRE2_SET (1<<10)
#define GLPCI_ARB_UPPER_PRE1_SET (1<<9) #define GLPCI_ARB_UPPER_PRE1_SET (1<<9)
#define GLPCI_ARB_UPPER_PRE0_SET (1<<8) #define GLPCI_ARB_UPPER_PRE0_SET (1<<8)
#define GLPCI_ARB_UPPER_CRME_SET (1<<7) #define GLPCI_ARB_UPPER_CRME_SET (1<<7)
#define GLPCI_ARB_UPPER_RME2_SET (1<<2) #define GLPCI_ARB_UPPER_RME2_SET (1<<2)
#define GLPCI_ARB_UPPER_RME1_SET (1<<1) #define GLPCI_ARB_UPPER_RME1_SET (1<<1)
#define GLPCI_ARB_UPPER_RME0_SET (1<<0) #define GLPCI_ARB_UPPER_RME0_SET (1<<0)
#define GLPCI_ARB_LOWER_PRCM_SHIFT 24 #define GLPCI_ARB_LOWER_PRCM_SHIFT 24
#define GLPCI_ARB_LOWER_FPVEC_SHIFT 16 #define GLPCI_ARB_LOWER_FPVEC_SHIFT 16
#define GLPCI_ARB_LOWER_RMT_SHIFT 6 #define GLPCI_ARB_LOWER_RMT_SHIFT 6
#define GLPCI_ARB_LOWER_IIE_SET (1<<8) #define GLPCI_ARB_LOWER_IIE_SET (1<<8)
#define GLPCI_ARB_LOWER_PARK_SET (1<<0) #define GLPCI_ARB_LOWER_PARK_SET (1<<0)
#define GLPCI_REN (MSR_PCI + 0x2014) #define GLPCI_REN (MSR_PCI + 0x2014)
#define GLPCI_A0_BF (MSR_PCI + 0x2015) #define GLPCI_A0_BF (MSR_PCI + 0x2015)
#define GLPCI_C0_DF (MSR_PCI + 0x2016) #define GLPCI_C0_DF (MSR_PCI + 0x2016)
#define GLPCI_E0_FF (MSR_PCI + 0x2017) #define GLPCI_E0_FF (MSR_PCI + 0x2017)
#define GLPCI_RC0 (MSR_PCI + 0x2018) #define GLPCI_RC0 (MSR_PCI + 0x2018)
#define GLPCI_RC1 (MSR_PCI + 0x2019) #define GLPCI_RC1 (MSR_PCI + 0x2019)
#define GLPCI_RC2 (MSR_PCI + 0x201A) #define GLPCI_RC2 (MSR_PCI + 0x201A)
#define GLPCI_RC3 (MSR_PCI + 0x201B) #define GLPCI_RC3 (MSR_PCI + 0x201B)
#define GLPCI_RC4 (MSR_PCI + 0x201C) #define GLPCI_RC4 (MSR_PCI + 0x201C)
#define GLPCI_RC_UPPER_TOP_SHIFT 12 #define GLPCI_RC_UPPER_TOP_SHIFT 12
#define GLPCI_RC_LOWER_BASE_SHIFT 12 #define GLPCI_RC_LOWER_BASE_SHIFT 12
#define GLPCI_RC_LOWER_EN_SET (1<<8) #define GLPCI_RC_LOWER_EN_SET (1<<8)
#define GLPCI_RC_LOWER_PF_SET (1<<5) #define GLPCI_RC_LOWER_PF_SET (1<<5)
#define GLPCI_RC_LOWER_WC_SET (1<<4) #define GLPCI_RC_LOWER_WC_SET (1<<4)
#define GLPCI_RC_LOWER_WP_SET (1<<2) #define GLPCI_RC_LOWER_WP_SET (1<<2)
#define GLPCI_RC_LOWER_CD_SET (1<<0) #define GLPCI_RC_LOWER_CD_SET (1<<0)
#define GLPCI_ExtMSR (MSR_PCI + 0x201E) #define GLPCI_ExtMSR (MSR_PCI + 0x201E)
#define GLPCI_SPARE (MSR_PCI + 0x201F) #define GLPCI_SPARE (MSR_PCI + 0x201F)
#define GLPCI_SPARE_LOWER_AILTO_SET (1<<6) #define GLPCI_SPARE_LOWER_AILTO_SET (1<<6)
#define GLPCI_SPARE_LOWER_PPD_SET (1<<5) #define GLPCI_SPARE_LOWER_PPD_SET (1<<5)
#define GLPCI_SPARE_LOWER_PPC_SET (1<<4) #define GLPCI_SPARE_LOWER_PPC_SET (1<<4)
#define GLPCI_SPARE_LOWER_MPC_SET (1<<3) #define GLPCI_SPARE_LOWER_MPC_SET (1<<3)
#define GLPCI_SPARE_LOWER_MME_SET (1<<2) #define GLPCI_SPARE_LOWER_MME_SET (1<<2)
#define GLPCI_SPARE_LOWER_NSE_SET (1<<1) #define GLPCI_SPARE_LOWER_NSE_SET (1<<1)
#define GLPCI_SPARE_LOWER_SUPO_SET (1<<0) #define GLPCI_SPARE_LOWER_SUPO_SET (1<<0)
/* FooGlue GLIU1 port 5 */ /* FooGlue GLIU1 port 5 */
#define FG_GLD_MSR_CAP (MSR_FG + 0x2000) #define FG_GLD_MSR_CAP (MSR_FG + 0x2000)
#define FG_GLD_MSR_PM (MSR_FG + 0x2004) #define FG_GLD_MSR_PM (MSR_FG + 0x2004)
/* VIP GLIU1 port 5 */ /* VIP GLIU1 port 5 */
#define VIP_GLD_MSR_CAP (MSR_VIP + 0x2000) #define VIP_GLD_MSR_CAP (MSR_VIP + 0x2000)
@ -423,68 +406,68 @@
/* more fun stuff */ /* more fun stuff */
#define BM 1 /* Base Mask - map power of 2 size aligned region */ #define BM 1 /* Base Mask - map power of 2 size aligned region */
#define BMO 2 /* BM with an offset */ #define BMO 2 /* BM with an offset */
#define R 3 /* Range - 4k range minimum */ #define R 3 /* Range - 4k range minimum */
#define RO 4 /* R with offset */ #define RO 4 /* R with offset */
#define SC 5 /* Swiss 0xCeese - maps a 256K region in to 16K 0xcunks. Set W/R */ #define SC 5 /* Swiss 0xCeese - maps a 256K region in to 16K 0xcunks. Set W/R */
#define BMIO 6 /* Base Mask IO */ #define BMIO 6 /* Base Mask IO */
#define SCIO 7 /* Swiss 0xCeese IO */ #define SCIO 7 /* Swiss 0xCeese IO */
#define SC_SHADOW 8 /* Special marker for Shadow SC descriptors so setShadow proc is independant of CPU */ #define SC_SHADOW 8 /* Special marker for Shadow SC descriptors so setShadow proc is independant of CPU */
#define R_SYSMEM 9 /* Special marker for SYSMEM R descriptors so GLIUInit proc is independant of CPU */ #define R_SYSMEM 9 /* Special marker for SYSMEM R descriptors so GLIUInit proc is independant of CPU */
#define BMO_SMM 10 /* Specail marker for SMM */ #define BMO_SMM 10 /* Specail marker for SMM */
#define BM_SMM 11 /* Specail marker for SMM */ #define BM_SMM 11 /* Specail marker for SMM */
#define BMO_DMM 12 /* Specail marker for DMM */ #define BMO_DMM 12 /* Specail marker for DMM */
#define BM_DMM 13 /* Specail marker for DMM */ #define BM_DMM 13 /* Specail marker for DMM */
#define RO_FB 14 /* special for Frame buffer. */ #define RO_FB 14 /* special for Frame buffer. */
#define R_FB 15 /* special for FB. */ #define R_FB 15 /* special for FB. */
#define OTHER 0x0FE /* Special marker for other */ #define OTHER 0x0FE /* Special marker for other */
#define GL_END 0x0FF /* end */ #define GL_END 0x0FF /* end */
#define MSR_GL0 (GL1_GLIU0 << 29) #define MSR_GL0 (GL1_GLIU0 << 29)
/* Set up desc addresses from 20 - 3f */ /* Set up desc addresses from 20 - 3f */
/* This is chip specific! */ /* This is chip specific! */
#define MSR_GLIU0_BASE1 (MSR_GLIU0 + 0x20) /* BM */ #define MSR_GLIU0_BASE1 (MSR_GLIU0 + 0x20) /* BM */
#define MSR_GLIU0_BASE2 (MSR_GLIU0 + 0x21) /* BM */ #define MSR_GLIU0_BASE2 (MSR_GLIU0 + 0x21) /* BM */
#define MSR_GLIU0_SHADOW (MSR_GLIU0 + 0x2C) /* SCO should only be SC */ #define MSR_GLIU0_SHADOW (MSR_GLIU0 + 0x2C) /* SCO should only be SC */
#define MSR_GLIU0_SYSMEM (MSR_GLIU0 + 0x28) /* RO should only be R */ #define MSR_GLIU0_SYSMEM (MSR_GLIU0 + 0x28) /* RO should only be R */
#define MSR_GLIU0_SMM (MSR_GLIU0 + 0x26) /* BMO */ #define MSR_GLIU0_SMM (MSR_GLIU0 + 0x26) /* BMO */
#define MSR_GLIU0_DMM (MSR_GLIU0 + 0x27) /* BMO */ #define MSR_GLIU0_DMM (MSR_GLIU0 + 0x27) /* BMO */
#define MSR_GLIU1_BASE1 (MSR_GLIU1 + 0x20) /* BM */ #define MSR_GLIU1_BASE1 (MSR_GLIU1 + 0x20) /* BM */
#define MSR_GLIU1_BASE2 (MSR_GLIU1 + 0x21) /* BM */ #define MSR_GLIU1_BASE2 (MSR_GLIU1 + 0x21) /* BM */
#define MSR_GLIU1_SHADOW (MSR_GLIU1 + 0x2D) /* SCO should only be SC */ #define MSR_GLIU1_SHADOW (MSR_GLIU1 + 0x2D) /* SCO should only be SC */
#define MSR_GLIU1_SYSMEM (MSR_GLIU1 + 0x29) /* RO should only be R */ #define MSR_GLIU1_SYSMEM (MSR_GLIU1 + 0x29) /* RO should only be R */
#define MSR_GLIU1_SMM (MSR_GLIU1 + 0x23) /* BM */ #define MSR_GLIU1_SMM (MSR_GLIU1 + 0x23) /* BM */
#define MSR_GLIU1_DMM (MSR_GLIU1 + 0x24) /* BM */ #define MSR_GLIU1_DMM (MSR_GLIU1 + 0x24) /* BM */
#define MSR_GLIU1_FPU_TRAP (MSR_GLIU1 + 0x0E3) /* FooGlue F0 for FPU */ #define MSR_GLIU1_FPU_TRAP (MSR_GLIU1 + 0x0E3) /* FooGlue F0 for FPU */
/* definitions that are "once you are mostly up, start VSA" type things */ /* definitions that are "once you are mostly up, start VSA" type things */
#define SMM_OFFSET 0x40400000 #define SMM_OFFSET 0x40400000
#define SMM_SIZE 128 /* changed SMM_SIZE from 256 KB to 128 KB */ #define SMM_SIZE 128 /* changed SMM_SIZE from 256 KB to 128 KB */
#define DMM_OFFSET 0x0C0000000 #define DMM_OFFSET 0x0C0000000
#define DMM_SIZE 128 #define DMM_SIZE 128
#define FB_OFFSET 0x41000000 #define FB_OFFSET 0x41000000
#define PCI_MEM_TOP 0x0EFFFFFFF // Top of PCI mem allocation region #define PCI_MEM_TOP 0x0EFFFFFFF /* Top of PCI mem allocation region */
#define PCI_IO_TOP 0x0EFFF // Top of PCI I/O allocation region #define PCI_IO_TOP 0x0EFFF /* Top of PCI I/O allocation region */
#define END_OPTIONROM_SPACE 0x0DFFF // E0000 is reserved for SystemROMs. #define END_OPTIONROM_SPACE 0x0DFFF /* E0000 is reserved for SystemROMs */
#define MDD_SMBUS 0x06000 // SMBUS IO location #define MDD_SMBUS 0x06000 /* SMBUS IO location */
#define MDD_GPIO 0x06100 // GPIO & ICF IO location #define MDD_GPIO 0x06100 /* GPIO & ICF IO location */
#define MDD_MFGPT 0x06200 // General Purpose Timers IO location #define MDD_MFGPT 0x06200 /* General Purpose Timers IO location */
#define MDD_IRQ_MAPPER 0x06300 // IRQ Mapper #define MDD_IRQ_MAPPER 0x06300 /* IRQ Mapper */
#define ACPI_BASE 0x09C00 // ACPI Base #define ACPI_BASE 0x09C00 /* ACPI Base */
#define MDD_PM 0x09D00 // Power Management Logic - placed at the end of ACPI #define MDD_PM 0x09D00 /* Power Management Logic - placed at the end of ACPI */
#define CS5535_IDSEL 0x02000000 // IDSEL = AD25, device #15 #define CS5535_IDSEL 0x02000000 /* IDSEL = AD25, device #15 */
#define CHIPSET_DEV_NUM 15 #define CHIPSET_DEV_NUM 15
#define IDSEL_BASE 11 // bit 11 = device 1 #define IDSEL_BASE 11 /* bit 11 = device 1 */
/* SB LBAR IO + MEMORY MAP */ /* SB LBAR IO + MEMORY MAP */
#define SMBUS_BASE ( 0x6000) #define SMBUS_BASE (0x6000)
#define GPIO_BASE ( 0x6100) #define GPIO_BASE (0x6100)
#define MFGPT_BASE ( 0x6200) #define MFGPT_BASE (0x6200)
#define IRQMAP_BASE ( 0x6300) #define IRQMAP_BASE (0x6300)
#define PMLogic_BASE ( 0x9D00) #define PMLogic_BASE (0x9D00)
#if !defined(__ROMCC__) && !defined(ASSEMBLY) #if !defined(__ROMCC__) && !defined(ASSEMBLY)

9
src/northbridge/amd/gx2/grphinit.c
View File

@ -5,13 +5,10 @@
#include "chip.h" #include "chip.h"
#include "northbridge.h" #include "northbridge.h"
// FIXME handle UMA properly. /* FIXME handle UMA properly. */
#define VIDEO_MB 8 // MB of video memory #define VIDEO_MB 8 /* MB of video memory */
/* This function mirrors the Graphics_Init routine in GeodeROM. */
/*
* This function mirrors the Graphics_Init routine in GeodeROM.
*/
void graphics_init(void) void graphics_init(void)
{ {
/* SoftVG initialization */ /* SoftVG initialization */

146
src/northbridge/amd/gx2/northbridge.c
View File

@ -20,15 +20,15 @@
#define NORTHBRIDGE_FILE "northbridge.c" #define NORTHBRIDGE_FILE "northbridge.c"
/* todo: add a resource record. We don't do this here because this may be called when /* todo: add a resource record. We don't do this here because this may be called when
* very little of the platform is actually working. * very little of the platform is actually working.
*/ */
int int sizeram(void)
sizeram(void)
{ {
msr_t msr; msr_t msr;
int sizem = 0; int sizem = 0;
unsigned short dimm; unsigned short dimm;
/* Get the RAM size from the memory controller as calculated and set by auto_size_dimm() */
msr = rdmsr(0x20000018); msr = rdmsr(0x20000018);
printk(BIOS_DEBUG, "sizeram: %08x:%08x\n", msr.hi, msr.lo); printk(BIOS_DEBUG, "sizeram: %08x:%08x\n", msr.hi, msr.lo);
@ -38,8 +38,7 @@ sizeram(void)
if ((dimm & 7) != 7) if ((dimm & 7) != 7)
sizem = (1 << ((dimm >> 12)-1)) * 8; sizem = (1 << ((dimm >> 12)-1)) * 8;
/* dimm 1 */
/* dimm 1*/
dimm = msr.hi >> 16; dimm = msr.hi >> 16;
/* installed? */ /* installed? */
if ((dimm & 7) != 7) if ((dimm & 7) != 7)
@ -49,8 +48,7 @@ sizeram(void)
return sizem; return sizem;
} }
/* here is programming for the various MSRs. */
/* here is programming for the various MSRs.*/
#define IM_QWAIT 0x100000 #define IM_QWAIT 0x100000
#define DMCF_WRITE_SERIALIZE_REQUEST (2<<12) /* 2 outstanding */ /* in high */ #define DMCF_WRITE_SERIALIZE_REQUEST (2<<12) /* 2 outstanding */ /* in high */
@ -86,9 +84,8 @@ sizeram(void)
#define IOD_BM(msr, pdid1, bizarro, ibase, imask) {msr, {.hi=(pdid1<<29)|(bizarro<<28)|(ibase>>12), .lo=(ibase<<20)|imask}} #define IOD_BM(msr, pdid1, bizarro, ibase, imask) {msr, {.hi=(pdid1<<29)|(bizarro<<28)|(ibase>>12), .lo=(ibase<<20)|imask}}
#define IOD_SC(msr, pdid1, bizarro, en, wen, ren, ibase) {msr, {.hi=(pdid1<<29)|(bizarro<<28), .lo=(en<<24)|(wen<<21)|(ren<<20)|(ibase<<3)}} #define IOD_SC(msr, pdid1, bizarro, en, wen, ren, ibase) {msr, {.hi=(pdid1<<29)|(bizarro<<28), .lo=(en<<24)|(wen<<21)|(ren<<20)|(ibase<<3)}}
struct msr_defaults
{
struct msr_defaults {
int msr_no; int msr_no;
msr_t msr; msr_t msr;
} msr_defaults [] = { } msr_defaults [] = {
@ -121,7 +118,8 @@ struct msr_defaults {
}; };
/* note that dev is NOT used -- yet */ /* note that dev is NOT used -- yet */
static void irq_init_steering(struct device *dev, u16 irq_map) { static void irq_init_steering(struct device *dev, u16 irq_map)
{
/* Set up IRQ steering */ /* Set up IRQ steering */
u32 pciAddr = 0x80000000 | (CHIPSET_DEV_NUM << 11) | 0x5C; u32 pciAddr = 0x80000000 | (CHIPSET_DEV_NUM << 11) | 0x5C;
@ -142,16 +140,12 @@ static void irq_init_steering(struct device *dev, u16 irq_map) {
outl(irq_map, 0xCFC); outl(irq_map, 0xCFC);
} }
/* setup_gx2_cache
/*
* setup_gx2_cache
* *
* Returns the amount of memory (in KB) available to the system. This is the * Returns the amount of memory (in KB) available to the system. This is the
* total amount of memory less the amount of memory reserved for SMM use. * total amount of memory less the amount of memory reserved for SMM use.
*
*/ */
static int static int setup_gx2_cache(void)
setup_gx2_cache(void)
{ {
msr_t msr; msr_t msr;
unsigned long long val; unsigned long long val;
@ -164,7 +158,7 @@ setup_gx2_cache(void)
/* set romrp */ /* set romrp */
val = ((unsigned long long) ROM_PROPERTIES) << 56; val = ((unsigned long long) ROM_PROPERTIES) << 56;
/* make rom base useful for 1M roms */ /* make rom base useful for 1M roms */
/* Flash base address -- sized for 1M for now*/ /* Flash base address -- sized for 1M for now */
val |= ((unsigned long long) 0xfff00)<<36; val |= ((unsigned long long) 0xfff00)<<36;
/* set the devrp properties */ /* set the devrp properties */
val |= ((unsigned long long) DEVICE_PROPERTIES) << 28; val |= ((unsigned long long) DEVICE_PROPERTIES) << 28;
@ -172,7 +166,7 @@ setup_gx2_cache(void)
/* yank off memory for the SMM handler */ /* yank off memory for the SMM handler */
sizekbytes -= SMM_SIZE; sizekbytes -= SMM_SIZE;
sizereg = sizekbytes; sizereg = sizekbytes;
sizereg *= 1024; // convert to bytes sizereg *= 1024; /* convert to bytes */
sizereg >>= 12; sizereg >>= 12;
sizereg <<= 8; sizereg <<= 8;
val |= sizereg; val |= sizereg;
@ -188,10 +182,8 @@ setup_gx2_cache(void)
} }
/* we have to do this here. We have not found a nicer way to do it */ /* we have to do this here. We have not found a nicer way to do it */
static void static void setup_gx2(void)
setup_gx2(void)
{ {
unsigned long tmp, tmp2; unsigned long tmp, tmp2;
msr_t msr; msr_t msr;
unsigned long size_kb, membytes; unsigned long size_kb, membytes;
@ -200,13 +192,13 @@ setup_gx2(void)
membytes = size_kb * 1024; membytes = size_kb * 1024;
/* NOTE! setup_gx2_cache returns the SIZE OF RAM - RAMADJUST! /* NOTE! setup_gx2_cache returns the SIZE OF RAM - RAMADJUST!
* so it is safe to use. You should NOT at this point call * so it is safe to use. You should NOT at this point call
* sizeram() directly. * sizeram() directly.
*/ */
/* we need to set 0x10000028 and 0x40000029 */ /* we need to set 0x10000028 and 0x40000029 */
/*
* These two descriptors cover the range from 1 MB (0x100000) to /* These two descriptors cover the range from 1 MB (0x100000) to
* SYSTOP (a.k.a. TOM, or Top of Memory) * SYSTOP (a.k.a. TOM, or Top of Memory)
*/ */
@ -258,11 +250,11 @@ setup_gx2(void)
msr = rdmsr(0x1808); msr = rdmsr(0x1808);
printk(BIOS_DEBUG, "MSR 0x%x is now 0x%x:0x%x\n", 0x1808, msr.hi, msr.lo); printk(BIOS_DEBUG, "MSR 0x%x is now 0x%x:0x%x\n", 0x1808, msr.hi, msr.lo);
#endif #endif
#if 0 // SDG - don't do this #if 0 /* SDG - don't do this */
/* now do the default MSR values */ /* now do the default MSR values */
for(i = 0; msr_defaults[i].msr_no; i++) { for(i = 0; msr_defaults[i].msr_no; i++) {
msr_t msr; msr_t msr;
wrmsr(msr_defaults[i].msr_no, msr_defaults[i].msr); // MSR - see table above wrmsr(msr_defaults[i].msr_no, msr_defaults[i].msr); /* MSR - see table above */
msr = rdmsr(msr_defaults[i].msr_no); msr = rdmsr(msr_defaults[i].msr_no);
printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", msr_defaults[i].msr_no, msr.hi,msr.lo); printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", msr_defaults[i].msr_no, msr.hi,msr.lo);
} }
@ -297,51 +289,49 @@ static void northbridge_init(device_t dev)
static void set_resources(struct device *dev) static void set_resources(struct device *dev)
{ {
#if 0 #if 0
struct resource *res; struct resource *res;
for(res = &dev->resource_list; res; res = res->next) { for(res = &dev->resource_list; res; res = res->next) {
pci_set_resource(dev, resource); pci_set_resource(dev, resource);
} }
#endif #endif
struct bus *bus; struct bus *bus;
for(bus = dev->link_list; bus; bus = bus->next) { for(bus = dev->link_list; bus; bus = bus->next) {
if (bus->children) { if (bus->children) {
assign_resources(bus); assign_resources(bus);
} }
} }
#if 0 #if 0
/* set a default latency timer */ /* set a default latency timer */
pci_write_config8(dev, PCI_LATENCY_TIMER, 0x40); pci_write_config8(dev, PCI_LATENCY_TIMER, 0x40);
/* set a default secondary latency timer */ /* set a default secondary latency timer */
if ((dev->hdr_type & 0x7f) == PCI_HEADER_TYPE_BRIDGE) { if ((dev->hdr_type & 0x7f) == PCI_HEADER_TYPE_BRIDGE) {
pci_write_config8(dev, PCI_SEC_LATENCY_TIMER, 0x40); pci_write_config8(dev, PCI_SEC_LATENCY_TIMER, 0x40);
} }
/* zero the irq settings */ /* zero the irq settings */
u8 line = pci_read_config8(dev, PCI_INTERRUPT_PIN); u8 line = pci_read_config8(dev, PCI_INTERRUPT_PIN);
if (line) { if (line) {
pci_write_config8(dev, PCI_INTERRUPT_LINE, 0); pci_write_config8(dev, PCI_INTERRUPT_LINE, 0);
} }
/* set the cache line size, so far 64 bytes is good for everyone */ /* set the cache line size, so far 64 bytes is good for everyone */
pci_write_config8(dev, PCI_CACHE_LINE_SIZE, 64 >> 2); pci_write_config8(dev, PCI_CACHE_LINE_SIZE, 64 >> 2);
#endif #endif
} }
static struct device_operations northbridge_operations = { static struct device_operations northbridge_operations = {
.read_resources = pci_dev_read_resources, .read_resources = pci_dev_read_resources,
#if 0 #if 0
.set_resources = pci_dev_set_resources, .set_resources = pci_dev_set_resources,
#endif #endif
.set_resources = set_resources, .set_resources = set_resources,
.enable_resources = pci_dev_enable_resources, .enable_resources = pci_dev_enable_resources,
.init = northbridge_init, .init = northbridge_init,
.enable = 0, .enable = 0,
.ops_pci = 0, .ops_pci = 0,
}; };
static const struct pci_driver northbridge_driver __pci_driver = { static const struct pci_driver northbridge_driver __pci_driver = {
@ -350,16 +340,16 @@ static const struct pci_driver northbridge_driver __pci_driver = {
.device = PCI_DEVICE_ID_NS_GX2, .device = PCI_DEVICE_ID_NS_GX2,
}; };
// FIXME handle UMA correctly. /* FIXME handle UMA correctly. */
#define FRAMEBUFFERK 4096 #define FRAMEBUFFERK 4096
static void pci_domain_set_resources(device_t dev) static void pci_domain_set_resources(device_t dev)
{ {
#if 0 #if 0
device_t mc_dev; device_t mc_dev;
u32 pci_tolm; u32 pci_tolm;
pci_tolm = find_pci_tolm(dev->link_list); pci_tolm = find_pci_tolm(dev->link_list);
mc_dev = dev->link_list->children; mc_dev = dev->link_list->children;
if (mc_dev) { if (mc_dev) {
unsigned int tomk, tolmk; unsigned int tomk, tolmk;
@ -405,16 +395,16 @@ static void pci_domain_set_resources(device_t dev)
} }
static struct device_operations pci_domain_ops = { static struct device_operations pci_domain_ops = {
.read_resources = pci_domain_read_resources, .read_resources = pci_domain_read_resources,
.set_resources = pci_domain_set_resources, .set_resources = pci_domain_set_resources,
.enable_resources = NULL, .enable_resources = NULL,
.init = NULL, .init = NULL,
.scan_bus = pci_domain_scan_bus, .scan_bus = pci_domain_scan_bus,
}; };
static void cpu_bus_init(device_t dev) static void cpu_bus_init(device_t dev)
{ {
initialize_cpus(dev->link_list); initialize_cpus(dev->link_list);
} }
static void cpu_bus_noop(device_t dev) static void cpu_bus_noop(device_t dev)
@ -422,11 +412,11 @@ static void cpu_bus_noop(device_t dev)
} }
static struct device_operations cpu_bus_ops = { static struct device_operations cpu_bus_ops = {
.read_resources = cpu_bus_noop, .read_resources = cpu_bus_noop,
.set_resources = cpu_bus_noop, .set_resources = cpu_bus_noop,
.enable_resources = cpu_bus_noop, .enable_resources = cpu_bus_noop,
.init = cpu_bus_init, .init = cpu_bus_init,
.scan_bus = 0, .scan_bus = 0,
}; };
void chipsetInit (void); void chipsetInit (void);
@ -440,8 +430,8 @@ static void enable_dev(struct device *dev)
printk(BIOS_DEBUG, "gx2 north: enable_dev\n"); printk(BIOS_DEBUG, "gx2 north: enable_dev\n");
void do_vsmbios(void); void do_vsmbios(void);
/* Set the operations if it is a special bus type */ /* Set the operations if it is a special bus type */
if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) { if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
u32 tomk; u32 tomk;
printk(BIOS_DEBUG, "DEVICE_PATH_PCI_DOMAIN\n"); printk(BIOS_DEBUG, "DEVICE_PATH_PCI_DOMAIN\n");
/* cpubug MUST be called before setup_gx2(), so we force the issue here */ /* cpubug MUST be called before setup_gx2(), so we force the issue here */
@ -460,10 +450,10 @@ static void enable_dev(struct device *dev)
high_tables_size = HIGH_MEMORY_SIZE; high_tables_size = HIGH_MEMORY_SIZE;
#endif #endif
ram_resource(dev, 0, 0, tomk); ram_resource(dev, 0, 0, tomk);
} else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) { } else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
printk(BIOS_DEBUG, "DEVICE_PATH_APIC_CLUSTER\n"); printk(BIOS_DEBUG, "DEVICE_PATH_APIC_CLUSTER\n");
dev->ops = &cpu_bus_ops; dev->ops = &cpu_bus_ops;
} }
printk(BIOS_DEBUG, "gx2 north: end enable_dev\n"); printk(BIOS_DEBUG, "gx2 north: end enable_dev\n");
} }

117
src/northbridge/amd/gx2/northbridgeinit.c
View File

@ -15,38 +15,40 @@
/* put this here for now, we are not sure where it belongs */ /* put this here for now, we are not sure where it belongs */
struct gliutable { struct gliutable
{
unsigned long desc_name; unsigned long desc_name;
unsigned short desc_type; unsigned short desc_type;
unsigned long hi, lo; unsigned long hi, lo;
}; };
struct gliutable gliu0table[] = { struct gliutable gliu0table[] = {
{.desc_name=MSR_GLIU0_BASE1, .desc_type= BM,.hi= MSR_MC + 0x0,.lo= 0x0FFF80}, /* 0-7FFFF to MC */ {.desc_name=MSR_GLIU0_BASE1, .desc_type= BM,.hi= MSR_MC + 0x0,.lo= 0x0FFF80}, /* 0-7FFFF to MC */
{.desc_name=MSR_GLIU0_BASE2, .desc_type= BM,.hi= MSR_MC + 0x0,.lo=(0x80 << 20) + 0x0FFFE0}, /* 80000-9ffff to Mc */ {.desc_name=MSR_GLIU0_BASE2, .desc_type= BM,.hi= MSR_MC + 0x0,.lo=(0x80 << 20) + 0x0FFFE0}, /* 80000-9ffff to Mc */
{.desc_name=MSR_GLIU0_SHADOW, .desc_type= SC_SHADOW,.hi= MSR_MC + 0x0,.lo= 0x03}, /* C0000-Fffff split to MC and PCI (sub decode) A0000-Bffff handled by SoftVideo */ {.desc_name=MSR_GLIU0_SHADOW, .desc_type= SC_SHADOW,.hi= MSR_MC + 0x0,.lo= 0x03}, /* C0000-Fffff split to MC and PCI (sub decode) A0000-Bffff handled by SoftVideo */
{.desc_name=MSR_GLIU0_SYSMEM, .desc_type= R_SYSMEM,.hi= MSR_MC,.lo= 0x0}, /* Catch and fix dynamicly. */ {.desc_name=MSR_GLIU0_SYSMEM, .desc_type= R_SYSMEM,.hi= MSR_MC,.lo= 0x0}, /* Catch and fix dynamicly. */
{.desc_name=MSR_GLIU0_DMM, .desc_type= BMO_DMM,.hi= MSR_MC,.lo= 0x0}, /* Catch and fix dynamicly. */ {.desc_name=MSR_GLIU0_DMM, .desc_type= BMO_DMM,.hi= MSR_MC,.lo= 0x0}, /* Catch and fix dynamicly. */
{.desc_name=MSR_GLIU0_SMM, .desc_type= BMO_SMM,.hi= MSR_MC,.lo= 0x0}, /* Catch and fix dynamicly. */ {.desc_name=MSR_GLIU0_SMM, .desc_type= BMO_SMM,.hi= MSR_MC,.lo= 0x0}, /* Catch and fix dynamicly. */
{.desc_name=GLIU0_GLD_MSR_COH,.desc_type= OTHER,.hi= 0x0,.lo= GL0_CPU}, {.desc_name=GLIU0_GLD_MSR_COH,.desc_type= OTHER,.hi= 0x0,.lo= GL0_CPU},
{.desc_name=GL_END, .desc_type= GL_END,.hi= 0x0,.lo= 0x0}, {.desc_name=GL_END, .desc_type= GL_END,.hi= 0x0,.lo= 0x0},
}; };
struct gliutable gliu1table[] = { struct gliutable gliu1table[] = {
{.desc_name=MSR_GLIU1_BASE1,.desc_type= BM,.hi= MSR_GL0 + 0x0,.lo= 0x0FFF80}, /* 0-7FFFF to MC */ {.desc_name=MSR_GLIU1_BASE1,.desc_type= BM,.hi= MSR_GL0 + 0x0,.lo= 0x0FFF80}, /* 0-7FFFF to MC */
{.desc_name=MSR_GLIU1_BASE2,.desc_type= BM,.hi= MSR_GL0 + 0x0,.lo= (0x80 << 20) +0x0FFFE0}, /* 80000-9ffff to Mc */ {.desc_name=MSR_GLIU1_BASE2,.desc_type= BM,.hi= MSR_GL0 + 0x0,.lo= (0x80 << 20) +0x0FFFE0}, /* 80000-9ffff to Mc */
{.desc_name=MSR_GLIU1_SHADOW,.desc_type= SC_SHADOW,.hi= MSR_GL0 + 0x0,.lo= 0x03}, /* C0000-Fffff split to MC and PCI (sub decode) */ {.desc_name=MSR_GLIU1_SHADOW,.desc_type= SC_SHADOW,.hi= MSR_GL0 + 0x0,.lo= 0x03}, /* C0000-Fffff split to MC and PCI (sub decode) */
{.desc_name=MSR_GLIU1_SYSMEM,.desc_type= R_SYSMEM,.hi= MSR_GL0,.lo= 0x0}, /* Catch and fix dynamicly. */ {.desc_name=MSR_GLIU1_SYSMEM,.desc_type= R_SYSMEM,.hi= MSR_GL0,.lo= 0x0}, /* Catch and fix dynamicly. */
{.desc_name=MSR_GLIU1_DMM,.desc_type= BM_DMM,.hi= MSR_GL0,.lo= 0x0}, /* Catch and fix dynamicly. */ {.desc_name=MSR_GLIU1_DMM,.desc_type= BM_DMM,.hi= MSR_GL0,.lo= 0x0}, /* Catch and fix dynamicly. */
{.desc_name=MSR_GLIU1_SMM,.desc_type= BM_SMM,.hi= MSR_GL0,.lo= 0x0}, /* Catch and fix dynamicly. */ {.desc_name=MSR_GLIU1_SMM,.desc_type= BM_SMM,.hi= MSR_GL0,.lo= 0x0}, /* Catch and fix dynamicly. */
{.desc_name=GLIU1_GLD_MSR_COH,.desc_type= OTHER,.hi= 0x0,.lo= GL1_GLIU0}, {.desc_name=GLIU1_GLD_MSR_COH,.desc_type= OTHER,.hi= 0x0,.lo= GL1_GLIU0},
{.desc_name=MSR_GLIU1_FPU_TRAP,.desc_type= SCIO,.hi= (GL1_GLCP << 29) + 0x0,.lo= 0x033000F0}, /* FooGlue FPU 0xF0 */ {.desc_name=MSR_GLIU1_FPU_TRAP,.desc_type= SCIO,.hi= (GL1_GLCP << 29) + 0x0,.lo= 0x033000F0}, /* FooGlue FPU 0xF0 */
{.desc_name=GL_END,.desc_type= GL_END,.hi= 0x0,.lo= 0x0}, {.desc_name=GL_END,.desc_type= GL_END,.hi= 0x0,.lo= 0x0},
}; };
struct gliutable *gliutables[] = {gliu0table, gliu1table, 0}; struct gliutable *gliutables[] = {gliu0table, gliu1table, 0};
struct msrinit { struct msrinit
{
unsigned long msrnum; unsigned long msrnum;
msr_t msr; msr_t msr;
}; };
@ -56,15 +58,16 @@ struct msrinit ClockGatingDefault [] = {
/* MC must stay off in SDR mode. It is turned on in CPUBug??? lotus #77.142 */ /* MC must stay off in SDR mode. It is turned on in CPUBug??? lotus #77.142 */
{MC_GLD_MSR_PM, {.hi=0x00,.lo=0x0000}}, {MC_GLD_MSR_PM, {.hi=0x00,.lo=0x0000}},
{GLIU1_GLD_MSR_PM, {.hi=0x00,.lo=0x0005}}, {GLIU1_GLD_MSR_PM, {.hi=0x00,.lo=0x0005}},
{VG_GLD_MSR_PM, {.hi=0x00,.lo=0x0000}}, /* lotus #77.163 */ {VG_GLD_MSR_PM, {.hi=0x00,.lo=0x0000}}, /* lotus #77.163 */
{GP_GLD_MSR_PM, {.hi=0x00,.lo=0x0001}}, {GP_GLD_MSR_PM, {.hi=0x00,.lo=0x0001}},
{DF_GLD_MSR_PM, {.hi=0x00,.lo=0x0155}}, {DF_GLD_MSR_PM, {.hi=0x00,.lo=0x0155}},
{GLCP_GLD_MSR_PM, {.hi=0x00,.lo=0x0015}}, {GLCP_GLD_MSR_PM, {.hi=0x00,.lo=0x0015}},
{GLPCI_GLD_MSR_PM, {.hi=0x00,.lo=0x0015}}, {GLPCI_GLD_MSR_PM, {.hi=0x00,.lo=0x0015}},
{FG_GLD_MSR_PM, {.hi=0x00,.lo=0x0000}}, /* Always on */ {FG_GLD_MSR_PM, {.hi=0x00,.lo=0x0000}}, /* Always on */
{0xffffffff, {0xffffffff, 0xffffffff}}, {0xffffffff, {0xffffffff, 0xffffffff}},
}; };
/* All On */
/* All On */
struct msrinit ClockGatingAllOn[] = { struct msrinit ClockGatingAllOn[] = {
{GLIU0_GLD_MSR_PM, {.hi=0x00,.lo=0x0FFFFFFFF}}, {GLIU0_GLD_MSR_PM, {.hi=0x00,.lo=0x0FFFFFFFF}},
{MC_GLD_MSR_PM, {.hi=0x00,.lo=0x0FFFFFFFF}}, {MC_GLD_MSR_PM, {.hi=0x00,.lo=0x0FFFFFFFF}},
@ -78,16 +81,16 @@ struct msrinit ClockGatingAllOn[] = {
{0xffffffff, {0xffffffff, 0xffffffff}}, {0xffffffff, {0xffffffff, 0xffffffff}},
}; };
/* Performance */ /* Performance */
struct msrinit ClockGatingPerformance[] = { struct msrinit ClockGatingPerformance[] = {
{VG_GLD_MSR_PM, {.hi=0x00,.lo=0x0000}}, /* lotus #77.163*/ {VG_GLD_MSR_PM, {.hi=0x00,.lo=0x0000}}, /* lotus #77.163 */
{GP_GLD_MSR_PM, {.hi=0x00,.lo=0x0001}}, {GP_GLD_MSR_PM, {.hi=0x00,.lo=0x0001}},
{DF_GLD_MSR_PM, {.hi=0x00,.lo=0x0155}}, {DF_GLD_MSR_PM, {.hi=0x00,.lo=0x0155}},
{GLCP_GLD_MSR_PM, {.hi=0x00,.lo=0x0015}}, {GLCP_GLD_MSR_PM, {.hi=0x00,.lo=0x0015}},
{0xffffffff, {0xffffffff, 0xffffffff}}, {0xffffffff, {0xffffffff, 0xffffffff}},
}; };
/* SET GeodeLink PRIORITY */ /* SET GeodeLink PRIORITY */
struct msrinit GeodeLinkPriorityTable [] = { struct msrinit GeodeLinkPriorityTable [] = {
{CPU_GLD_MSR_CONFIG, {.hi=0x00,.lo=0x0220}}, /* CPU Priority. */ {CPU_GLD_MSR_CONFIG, {.hi=0x00,.lo=0x0220}}, /* CPU Priority. */
{DF_GLD_MSR_MASTER_CONF, {.hi=0x00,.lo=0x0000}}, /* DF Priority. */ {DF_GLD_MSR_MASTER_CONF, {.hi=0x00,.lo=0x0000}}, /* DF Priority. */
@ -103,8 +106,8 @@ struct msrinit GeodeLinkPriorityTable [] = {
/* do we have dmi or not? assume NO per AMD */ /* do we have dmi or not? assume NO per AMD */
int havedmi = 0; int havedmi = 0;
static void static void writeglmsr(struct gliutable *gl)
writeglmsr(struct gliutable *gl){ {
msr_t msr; msr_t msr;
msr.lo = gl->lo; msr.lo = gl->lo;
@ -116,8 +119,7 @@ writeglmsr(struct gliutable *gl){
printk(BIOS_DEBUG, "%s: AFTER write msr 0x%08lx, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo); printk(BIOS_DEBUG, "%s: AFTER write msr 0x%08lx, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo);
} }
static void static void ShadowInit(struct gliutable *gl)
ShadowInit(struct gliutable *gl)
{ {
msr_t msr; msr_t msr;
@ -132,14 +134,12 @@ ShadowInit(struct gliutable *gl)
* CLEAN ME UP * CLEAN ME UP
*/ */
/* yes, this duplicates later code, but it seems that is how they want it done. */ /* yes, this duplicates later code, but it seems that is how they want it done. */
static void static void SysmemInit(struct gliutable *gl)
SysmemInit(struct gliutable *gl)
{ {
msr_t msr; msr_t msr;
int sizembytes, sizebytes; int sizembytes, sizebytes;
/* /* Figure out how much RAM is in the machine and alocate all to the
* Figure out how much RAM is in the machine and alocate all to the
* system. We will adjust for SMM and DMM now and Frame Buffer later. * system. We will adjust for SMM and DMM now and Frame Buffer later.
*/ */
sizembytes = sizeram(); sizembytes = sizeram();
@ -164,8 +164,8 @@ SysmemInit(struct gliutable *gl)
gl->desc_name, msr.hi, msr.lo); gl->desc_name, msr.hi, msr.lo);
} }
static void static void DMMGL0Init(struct gliutable *gl)
DMMGL0Init(struct gliutable *gl) { {
msr_t msr; msr_t msr;
int sizebytes = sizeram()<<20; int sizebytes = sizeram()<<20;
long offset; long offset;
@ -191,8 +191,8 @@ DMMGL0Init(struct gliutable *gl) {
printk(BIOS_DEBUG, "%s: AFTER write msr 0x%08lx, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo); printk(BIOS_DEBUG, "%s: AFTER write msr 0x%08lx, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo);
} }
static void static void DMMGL1Init(struct gliutable *gl)
DMMGL1Init(struct gliutable *gl) { {
msr_t msr; msr_t msr;
if (! havedmi) if (! havedmi)
@ -214,8 +214,8 @@ DMMGL1Init(struct gliutable *gl) {
printk(BIOS_DEBUG, "%s: AFTER write msr 0x%08lx, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo); printk(BIOS_DEBUG, "%s: AFTER write msr 0x%08lx, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo);
} }
static void static void SMMGL0Init(struct gliutable *gl)
SMMGL0Init(struct gliutable *gl) { {
msr_t msr; msr_t msr;
int sizebytes = sizeram()<<20; int sizebytes = sizeram()<<20;
long offset; long offset;
@ -242,8 +242,8 @@ SMMGL0Init(struct gliutable *gl) {
printk(BIOS_DEBUG, "%s: AFTER write msr 0x%08lx, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo); printk(BIOS_DEBUG, "%s: AFTER write msr 0x%08lx, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo);
} }
static void static void SMMGL1Init(struct gliutable *gl)
SMMGL1Init(struct gliutable *gl) { {
msr_t msr; msr_t msr;
printk(BIOS_DEBUG, "%s:\n", __func__ ); printk(BIOS_DEBUG, "%s:\n", __func__ );
@ -259,9 +259,8 @@ SMMGL1Init(struct gliutable *gl) {
printk(BIOS_DEBUG, "%s: AFTER write msr 0x%08lx, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo); printk(BIOS_DEBUG, "%s: AFTER write msr 0x%08lx, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo);
} }
static void static void GLIUInit(struct gliutable *gl)
GLIUInit(struct gliutable *gl){ {
while (gl->desc_type != GL_END){ while (gl->desc_type != GL_END){
switch(gl->desc_type){ switch(gl->desc_type){
default: default:
@ -295,8 +294,7 @@ GLIUInit(struct gliutable *gl){
} }
} }
/* /* Set up GLPCI settings for reads/write into memory.
* Set up GLPCI settings for reads/write into memory.
* *
* R0: 0-640KB, * R0: 0-640KB,
* R1: 1MB - Top of System Memory * R1: 1MB - Top of System Memory
@ -304,7 +302,8 @@ GLIUInit(struct gliutable *gl){
* R3: Framebuffer? - not set up yet * R3: Framebuffer? - not set up yet
* R4: ?? * R4: ??
*/ */
static void GLPCIInit(void){ static void GLPCIInit(void)
{
struct gliutable *gl = 0; struct gliutable *gl = 0;
int i; int i;
msr_t msr; msr_t msr;
@ -334,7 +333,7 @@ static void GLPCIInit(void){
* base of 1M and top of around 256M * base of 1M and top of around 256M
*/ */
/* we have to create a page-aligned (4KB page) address for base and top /* we have to create a page-aligned (4KB page) address for base and top
* So we need a high page aligned addresss (pah) and low page aligned address (pal) * so we need a high page aligned addresss (pah) and low page aligned address (pal)
* pah is from msr.hi << 12 | msr.low >> 20. pal is msr.lo << 12 * pah is from msr.hi << 12 | msr.low >> 20. pal is msr.lo << 12
*/ */
printk(BIOS_DEBUG, "GLPCI r1: system msr.lo 0x%08x msr.hi 0x%08x\n", msr.lo, msr.hi); printk(BIOS_DEBUG, "GLPCI r1: system msr.lo 0x%08x msr.hi 0x%08x\n", msr.lo, msr.hi);
@ -504,8 +503,7 @@ static void GeodeLinkPriority(void)
} }
} }
/* /* Get the GLIU0 shadow register settings.
* Get the GLIU0 shadow register settings.
* *
* If the setShadow function is used then all shadow descriptors * If the setShadow function is used then all shadow descriptors
* will stay sync'ed. * will stay sync'ed.
@ -517,8 +515,7 @@ static uint64_t getShadow(void)
return ( ( (uint64_t) msr.hi ) << 32 ) | msr.lo; return ( ( (uint64_t) msr.hi ) << 32 ) | msr.lo;
} }
/* /* Set the cache RConf registers for the memory hole.
* Set the cache RConf registers for the memory hole.
* *
* Keeps all cache shadow descriptors sync'ed. * Keeps all cache shadow descriptors sync'ed.
* This is part of the PCI lockup solution. * This is part of the PCI lockup solution.
@ -536,17 +533,17 @@ static void setShadowRCONF(uint32_t shadowHi, uint32_t shadowLo)
/* load up D000 settings in edx. */ /* load up D000 settings in edx. */
for (bit = 8; (bit > 4); bit--) { for (bit = 8; (bit > 4); bit--) {
msr.hi <<= 8; msr.hi <<= 8;
msr.hi |= 1; /* cache disable PCI/Shadow memory */ msr.hi |= 1; /* cache disable PCI/Shadow memory */
if (shadowByte && (1 << bit)) if (shadowByte && (1 << bit))
msr.hi |= 0x20; /* write serialize PCI memory */ msr.hi |= 0x20; /* write serialize PCI memory */
} }
/* load up C000 settings in eax. */ /* load up C000 settings in eax. */
for ( ; bit; bit--) { for ( ; bit; bit--) {
msr.lo <<= 8; msr.lo <<= 8;
msr.lo |= 1; /* cache disable PCI/Shadow memory */ msr.lo |= 1; /* cache disable PCI/Shadow memory */
if (shadowByte && (1 << bit)) if (shadowByte && (1 << bit))
msr.lo |= 0x20; /* write serialize PCI memory */ msr.lo |= 0x20; /* write serialize PCI memory */
} }
wrmsr(CPU_RCONF_C0_DF, msr); wrmsr(CPU_RCONF_C0_DF, msr);
@ -556,24 +553,23 @@ static void setShadowRCONF(uint32_t shadowHi, uint32_t shadowLo)
/* load up F000 settings in edx. */ /* load up F000 settings in edx. */
for (bit = 8; (bit > 4); bit--) { for (bit = 8; (bit > 4); bit--) {
msr.hi <<= 8; msr.hi <<= 8;
msr.hi |= 1; /* cache disable PCI/Shadow memory */ msr.hi |= 1; /* cache disable PCI/Shadow memory */
if (shadowByte && (1 << bit)) if (shadowByte && (1 << bit))
msr.hi |= 0x20; /* write serialize PCI memory */ msr.hi |= 0x20; /* write serialize PCI memory */
} }
/* load up E000 settings in eax. */ /* load up E000 settings in eax. */
for ( ; bit; bit--) { for ( ; bit; bit--) {
msr.lo <<= 8; msr.lo <<= 8;
msr.lo |= 1; /* cache disable PCI/Shadow memory */ msr.lo |= 1; /* cache disable PCI/Shadow memory */
if (shadowByte && (1 << bit)) if (shadowByte && (1 << bit))
msr.lo |= 0x20; /* write serialize PCI memory */ msr.lo |= 0x20; /* write serialize PCI memory */
} }
wrmsr(CPU_RCONF_E0_FF, msr); wrmsr(CPU_RCONF_E0_FF, msr);
} }
/* /* Set the GLPCI registers for the memory hole.
* Set the GLPCI registers for the memory hole.
* Keeps all cache shadow descriptors sync'ed. * Keeps all cache shadow descriptors sync'ed.
* Entry: EDX:EAX is the shadow settings * Entry: EDX:EAX is the shadow settings
*/ */
@ -588,8 +584,7 @@ static void setShadowGLPCI(uint32_t shadowHi, uint32_t shadowLo)
wrmsr(GLPCI_REN, msr); wrmsr(GLPCI_REN, msr);
} }
/* /* Set the GLIU SC register settings. Scans descriptor tables for SC_SHADOW.
* Set the GLIU SC register settings. Scans descriptor tables for SC_SHADOW.
* Keeps all shadow descriptors sync'ed. * Keeps all shadow descriptors sync'ed.
* Entry: EDX:EAX is the shadow settings * Entry: EDX:EAX is the shadow settings
*/ */
@ -630,8 +625,7 @@ static void shadowRom(void)
setShadow(shadowSettings); setShadow(shadowSettings);
} }
/* /* Set up RCONF_DEFAULT and any other RCONF registers needed.
* Set up RCONF_DEFAULT and any other RCONF registers needed.
* *
* DEVRC_RCONF_DEFAULT: * DEVRC_RCONF_DEFAULT:
* ROMRC(63:56) = 04h ; write protect ROMBASE * ROMRC(63:56) = 04h ; write protect ROMBASE
@ -645,8 +639,7 @@ static void shadowRom(void)
#define ROMBASE_RCONF_DEFAULT 0xFFFC0000 #define ROMBASE_RCONF_DEFAULT 0xFFFC0000
#define ROMRC_RCONF_DEFAULT 0x25 #define ROMRC_RCONF_DEFAULT 0x25
static void static void RCONFInit(void)
RCONFInit(void)
{ {
struct gliutable *gl = 0; struct gliutable *gl = 0;
int i; int i;