soc/intel/common: pmclib: make use of the new ETR address API

Make use of the new ETR address API in the ETR3 register related
functions.

Further, disabling and locking of global reset is now done at once to
save one read-modify-write cycle, thus the function was renamed
accordingly and the now redundant disabling in soc/apl got removed.

Change-Id: I49f59efb4a7c7d3d629ac54a7922bbcc8a87714d
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36570
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

src/soc/intel/apollolake/chip.c

@@ -418,10 +418,8 @@ static void soc_init(void *data)
 
 static void soc_final(void *data)
 {
-	/* Disable global reset, just in case */
-	pmc_global_reset_enable(0);
 	/* Make sure payload/OS can't trigger global reset */
-	pmc_global_reset_lock();
+	pmc_global_reset_disable_and_lock();
 }
 
 static void disable_dev(struct device *dev, FSP_S_CONFIG *silconfig)