Use defines for some i82801ex/gx registers

Change-Id: I0069ec26278b82d61ce5bcfb94d77647dfd3254b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/2530
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

src/southbridge/intel/i82801gx/i82801gx.h

@@ -80,6 +80,7 @@ int smbus_read_byte(unsigned device, unsigned address);
 
 #define PMBASE			0x40
 #define ACPI_CNTL		0x44
+#define   ACPI_EN		(1 << 7)
 #define BIOS_CNTL		0xDC
 #define GPIO_BASE		0x48 /* LPC GPIO Base Address Register */
 #define GPIO_CNTL		0x4C /* LPC GPIO Control Register */

src/southbridge/intel/i82801gx/lpc.c

@@ -49,7 +49,7 @@ static void i82801gx_enable_apic(struct device *dev)
 	/* Enable ACPI I/O and power management.
 	 * Set SCI IRQ to IRQ9
 	 */
-	pci_write_config8(dev, ACPI_CNTL, 0x80);
+	pci_write_config8(dev, ACPI_CNTL, ACPI_EN);
 
 	*ioapic_index = 0;
 	*ioapic_data = (1 << 25);