soc/intel: Add Skylake SOC support
Add the files to support the Skylake SOC. Matches chromium tree at 927026db BRANCH=none BUG=None TEST=Build and run on a Skylake platform Change-Id: I80248f7e47eaf13b52e3c7ff951eb1976edbaa15 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10341 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Lee Leahy
@@ -2,6 +2,7 @@
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2014 Google Inc.
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* Copyright (C) 2015 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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@@ -14,7 +15,7 @@
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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* Foundation, Inc.
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*/
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#include <console/console.h>
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@@ -27,209 +28,15 @@
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#include <soc/xhci.h>
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#include <soc/cpu.h>
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#ifdef __SMM__
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static u8 *usb_xhci_mem_base(device_t dev)
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{
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u32 mem_base = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
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/* Check if the controller is disabled or not present */
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if (mem_base == 0 || mem_base == 0xffffffff)
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return 0;
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return (u8 *)(mem_base & ~0xf);
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}
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static int usb_xhci_port_count_usb3(device_t dev)
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{
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/* PCH-LP has 4 SS ports */
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return 4;
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}
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static void usb_xhci_reset_status_usb3(u8 *mem_base, int port)
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{
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u8 *portsc = mem_base + XHCI_USB3_PORTSC(port);
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u32 status = read32(portsc);
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/* Do not set Port Enabled/Disabled field */
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status &= ~XHCI_USB3_PORTSC_PED;
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/* Clear all change status bits */
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status |= XHCI_USB3_PORTSC_CHST;
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write32(portsc, status);
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}
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static void usb_xhci_reset_port_usb3(u8 *mem_base, int port)
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{
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u8 *portsc = mem_base + XHCI_USB3_PORTSC(port);
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write32(portsc, read32(portsc) | XHCI_USB3_PORTSC_WPR);
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}
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#define XHCI_RESET_DELAY_US 1000 /* 1ms */
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#define XHCI_RESET_TIMEOUT 100 /* 100ms */
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/*
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* 1) Wait until port is done polling
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* 2) If port is disconnected
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* a) Issue warm port reset
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* b) Poll for warm reset complete
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* c) Write 1 to port change status bits
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*/
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static void usb_xhci_reset_usb3(device_t dev, int all)
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{
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u32 status, port_disabled;
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int timeout, port;
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int port_count = usb_xhci_port_count_usb3(dev);
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u8 *mem_base = usb_xhci_mem_base(dev);
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if (!mem_base || !port_count)
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return;
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/* Get mask of disabled ports */
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port_disabled = pci_read_config32(dev, XHCI_USB3PDO);
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/* Wait until all enabled ports are done polling */
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for (timeout = XHCI_RESET_TIMEOUT; timeout; timeout--) {
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int complete = 1;
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for (port = 0; port < port_count; port++) {
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/* Skip disabled ports */
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if (port_disabled & (1 << port))
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continue;
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/* Read port link status field */
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status = read32(mem_base + XHCI_USB3_PORTSC(port));
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status &= XHCI_USB3_PORTSC_PLS;
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if (status == XHCI_PLSR_POLLING)
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complete = 0;
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}
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/* Exit if all ports not polling */
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if (complete)
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break;
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udelay(XHCI_RESET_DELAY_US);
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}
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/* Reset all requested ports */
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for (port = 0; port < port_count; port++) {
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u8 *portsc = mem_base + XHCI_USB3_PORTSC(port);
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/* Skip disabled ports */
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if (port_disabled & (1 << port))
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continue;
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status = read32(portsc) & XHCI_USB3_PORTSC_PLS;
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/* Reset all or only disconnected ports */
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if (all || (status == XHCI_PLSR_RXDETECT ||
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status == XHCI_PLSR_POLLING))
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usb_xhci_reset_port_usb3(mem_base, port);
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else
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port_disabled |= 1 << port;
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}
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/* Wait for warm reset complete on all reset ports */
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for (timeout = XHCI_RESET_TIMEOUT; timeout; timeout--) {
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int complete = 1;
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for (port = 0; port < port_count; port++) {
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/* Only check ports that were reset */
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if (port_disabled & (1 << port))
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continue;
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/* Check if warm reset is complete */
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status = read32(mem_base + XHCI_USB3_PORTSC(port));
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if (!(status & XHCI_USB3_PORTSC_WRC))
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complete = 0;
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}
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/* Check for warm reset complete in any port */
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if (complete)
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break;
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udelay(XHCI_RESET_DELAY_US);
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}
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/* Clear port change status bits */
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for (port = 0; port < port_count; port++)
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usb_xhci_reset_status_usb3(mem_base, port);
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}
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/* Handler for XHCI controller on entry to S3/S4/S5 */
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void usb_xhci_sleep_prepare(device_t dev, u8 slp_typ)
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{
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u16 reg16;
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u32 reg32;
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u8 *mem_base = usb_xhci_mem_base(dev);
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u8 is_broadwell = !!(cpu_family_model() == BROADWELL_FAMILY_ULT);
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if (!mem_base || slp_typ < 3)
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return;
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/* Set D0 state */
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reg16 = pci_read_config16(dev, XHCI_PWR_CTL_STS);
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reg16 &= ~XHCI_PWR_CTL_SET_MASK;
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reg16 |= XHCI_PWR_CTL_SET_D0;
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pci_write_config16(dev, XHCI_PWR_CTL_STS, reg16);
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if (!is_broadwell) {
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/* This WA is only for lpt */
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/* Clear PCI 0xB0[14:13] */
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reg32 = pci_read_config32(dev, 0xb0);
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reg32 &= ~((1 << 14) | (1 << 13));
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pci_write_config32(dev, 0xb0, reg32);
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/* Clear MMIO 0x816c[14,2] */
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reg32 = read32(mem_base + 0x816c);
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reg32 &= ~((1 << 14) | (1 << 2));
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write32(mem_base + 0x816c, reg32);
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/* Reset disconnected USB3 ports */
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usb_xhci_reset_usb3(dev, 0);
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/* Set MMIO 0x80e0[15] */
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reg32 = read32(mem_base + 0x80e0);
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reg32 |= (1 << 15);
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write32(mem_base + 0x80e0, reg32);
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} else {
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/*
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* Clear port change status bits. Clearing CSC alone seemed to
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* fix wakeup from S3 if entering USB compliance state even if
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* bit wasn't set on the port.
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*/
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int port;
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for (port = 0; port < usb_xhci_port_count_usb3(dev); port++)
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usb_xhci_reset_status_usb3(mem_base, port);
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}
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reg32 = read32(mem_base + 0x8154);
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reg32 &= ~(1 << 31);
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write32(mem_base + 0x8154, reg32);
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/* Set D3Hot state and enable PME */
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pci_or_config16(dev, XHCI_PWR_CTL_STS, XHCI_PWR_CTL_SET_D3);
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pci_or_config16(dev, XHCI_PWR_CTL_STS, XHCI_PWR_CTL_STATUS_PME);
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pci_or_config16(dev, XHCI_PWR_CTL_STS, XHCI_PWR_CTL_ENABLE_PME);
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}
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#else /* !__SMM__ */
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static void xhci_init(struct device *dev)
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{
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struct resource *res = find_resource(dev, PCI_BASE_ADDRESS_0);
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u16 reg16;
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u32 reg32;
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/* Ensure controller is in D0 state */
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reg16 = pci_read_config16(dev, XHCI_PWR_CTL_STS);
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reg16 &= ~XHCI_PWR_CTL_SET_MASK;
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reg16 |= XHCI_PWR_CTL_SET_D0;
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pci_write_config16(dev, XHCI_PWR_CTL_STS, reg16);
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/* Disable Compliance Mode Entry */
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reg32 = read32(res2mmio(res, 0x80ec, 0));
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reg32 |= (1 << 0);
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write32(res2mmio(res, 0x80ec, 0), reg32);
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}
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static struct device_operations usb_xhci_ops = {
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.read_resources = &pci_dev_read_resources,
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.set_resources = &pci_dev_set_resources,
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.enable_resources = &pci_dev_enable_resources,
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.ops_pci = &broadwell_pci_ops,
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.init = &xhci_init,
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.ops_pci = &soc_pci_ops,
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};
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static const unsigned short pci_device_ids[] = {
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0x9c31, /* LynxPoint-LP */
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0x9cb1, /* WildcatPoint */
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0x9d2f, /* SunRisePoint LP */
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0
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};
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@@ -238,4 +45,3 @@ static const struct pci_driver pch_usb_xhci __pci_driver = {
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.vendor = PCI_VENDOR_ID_INTEL,
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.devices = pci_device_ids,
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};
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#endif /* !__SMM__ */
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