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mb/google/dedede/var/awasuki: Modify DPTF parameters

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Modify DPTF parameters from thermal team.

1. Add TCHG.
2. Modify the charging limit.

BUG=b:360066326
TEST=Modify Thermal according to design requirements

Change-Id: Ia7050b552656a70da0c992e4f54b02ccb6a7c114
Signed-off-by: Wei Hualin <weihualin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83929
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar
This commit is contained in:
Wei Hualin 2024-08-15 17:41:51 +08:00 committed by Karthik Ramasubramanian
parent 62d69eb59b
commit 1d41e3d1e0
1 changed files with 12 additions and 13 deletions
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25
src/mainboard/google/dedede/variants/awasuki/overridetree.cb
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@ -55,18 +55,18 @@ chip soc/intel/jasperlake
# Power limit config # Power limit config
register "power_limits_config[JSL_N4500_6W_CORE]" = "{ register "power_limits_config[JSL_N4500_6W_CORE]" = "{
.tdp_pl1_override = 7, .tdp_pl1_override = 5,
.tdp_pl2_override = 20, .tdp_pl2_override = 15,
}" }"
register "power_limits_config[JSL_N6000_6W_CORE]" = "{ register "power_limits_config[JSL_N6000_6W_CORE]" = "{
.tdp_pl1_override = 7, .tdp_pl1_override = 5,
.tdp_pl2_override = 20, .tdp_pl2_override = 15,
}" }"
register "power_limits_config[JSL_N5100_6W_CORE]" = "{ register "power_limits_config[JSL_N5100_6W_CORE]" = "{
.tdp_pl1_override = 7, .tdp_pl1_override = 5,
.tdp_pl2_override = 20, .tdp_pl2_override = 15,
}" }"
# TCC activation offset # TCC activation offset
@ -91,7 +91,7 @@ chip soc/intel/jasperlake
## Passive Policy ## Passive Policy
register "policies.passive" = "{ register "policies.passive" = "{
[0] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 50, 5000), [0] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 50, 5000),
[1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 68, 5000), [1] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_1, 68, 5000),
[2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 68, 5000), [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 68, 5000),
[3] = DPTF_PASSIVE(CPU, TEMP_SENSOR_3, 68, 5000), [3] = DPTF_PASSIVE(CPU, TEMP_SENSOR_3, 68, 5000),
}" }"
@ -107,15 +107,15 @@ chip soc/intel/jasperlake
register "controls.power_limits.pl1" = "{ register "controls.power_limits.pl1" = "{
.min_power = 5000, .min_power = 5000,
.max_power = 7000, .max_power = 9000,
.time_window_min = 28 * MSECS_PER_SEC, .time_window_min = 28 * MSECS_PER_SEC,
.time_window_max = 28 * MSECS_PER_SEC, .time_window_max = 28 * MSECS_PER_SEC,
.granularity = 125, .granularity = 125,
}" }"
register "controls.power_limits.pl2" = "{ register "controls.power_limits.pl2" = "{
.min_power = 20000, .min_power = 15000,
.max_power = 20000, .max_power = 15000,
.time_window_min = 28 * MSECS_PER_SEC, .time_window_min = 28 * MSECS_PER_SEC,
.time_window_max = 32 * MSECS_PER_SEC, .time_window_max = 32 * MSECS_PER_SEC,
.granularity = 1000, .granularity = 1000,
@ -125,9 +125,8 @@ chip soc/intel/jasperlake
register "controls.charger_perf" = "{ register "controls.charger_perf" = "{
[0] = { 255, 3000 }, [0] = { 255, 3000 },
[1] = { 32, 2000 }, [1] = { 32, 2000 },
[2] = { 24, 1500 }, [2] = { 16, 1000 },
[3] = { 16, 1000 }, [3] = { 8, 500 }
[4] = { 8, 500 }
}" }"
device generic 0 on end device generic 0 on end
end end