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soc/intel/alderlake: Support missing CLKREQ workaround on RaptorLake FSP

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IoT variants of the RaptorLake FSP support the `PchPciePowerGating` and
`PchPcieClockGating` UPDs, so, remove the preprocessor check that only
enabled it for AlderLake FSPs.

Change-Id: I583a4b257b72f992fdb6390d00e187d04a749177
Signed-off-by: Benjamin Doron <benjamin.doron@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81803
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
This commit is contained in:
Benjamin Doron 2024-04-08 15:02:03 -04:00 committed by Felix Held
parent 09a0dc650d
commit 1dc8f0272b
1 changed files with 1 additions and 1 deletions
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src/soc/intel/alderlake/fsp_params.c
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@ -932,7 +932,7 @@ static void fill_fsps_pcie_params(FSP_S_CONFIG *s_cfg,
}
s_cfg->PcieComplianceTestMode = CONFIG(SOC_INTEL_COMPLIANCE_TEST_MODE);
#if CONFIG(FSP_TYPE_IOT) && !CONFIG(SOC_INTEL_RAPTORLAKE)
#if CONFIG(FSP_TYPE_IOT)
/*
* Intel requires that all enabled PCH PCIe ports have a CLK_REQ signal connected.
* The CLK_REQ is used to wake the silicon when link entered L1 link-state. L1