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mb/intel/d510mo: Use common ramstage driver to configure the ck505

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TESTED, the screen doesn't jiggle (caused by wrong clock on reset
default clockgen configuration)

Change-Id: Icfa22daf90f9e2eff13b4fc5994664e96903dd1e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/21222
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Arthur Heymans
2017-08-27 15:27:18 +02:00
committed by Martin Roth
parent 105e368247
commit 1dce590447
3 changed files with 14 additions and 6 deletions
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1
src/mainboard/intel/d510mo/Kconfig
View File

@@ -28,6 +28,7 @@ config BOARD_SPECIFIC_OPTIONS
select INTEL_INT15 select INTEL_INT15
select HAVE_OPTION_TABLE select HAVE_OPTION_TABLE
select HAVE_CMOS_DEFAULT select HAVE_CMOS_DEFAULT
select DRIVERS_I2C_CK505
config MAX_CPUS config MAX_CPUS
int int

14
src/mainboard/intel/d510mo/devicetree.cb
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@@ -92,7 +92,19 @@ chip northbridge/intel/pineview # Northbridge
end end
device pci 1f.1 off end device pci 1f.1 off end
device pci 1f.2 on end # SATA device pci 1f.2 on end # SATA
device pci 1f.3 on end # SMbus device pci 1f.3 on # SMbus
chip drivers/i2c/ck505 # ICS9EPRS525
register "mask" = "{ 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff,
0xff }"
register "regs" = "{ 0x61, 0xd9, 0xfe, 0xff,
0xff, 0x00, 0x00, 0x01,
0x03, 0x25, 0x83, 0x17,
0x0d }"
device i2c 69 on end
end
end
device pci 1f.4 off end device pci 1f.4 off end
device pci 1f.5 off end device pci 1f.5 off end
device pci 1f.6 off end device pci 1f.6 off end

5
src/mainboard/intel/d510mo/romstage.c
View File

@@ -102,9 +102,6 @@ static void rcba_config(void)
void mainboard_romstage_entry(unsigned long bist) void mainboard_romstage_entry(unsigned long bist)
{ {
const u8 spd_addrmap[4] = { 0x50, 0x51, 0, 0 }; const u8 spd_addrmap[4] = { 0x50, 0x51, 0, 0 };
const u8 clockgen_block[13] = { 0x61, 0xd9, 0xfe, 0xff, 0xff, 0x00,
0x00, 0x01, 0x03, 0x25, 0x83, 0x17,
0x0d };
int cbmem_was_initted; int cbmem_was_initted;
int s3resume = 0; int s3resume = 0;
int boot_path; int boot_path;
@@ -128,8 +125,6 @@ void mainboard_romstage_entry(unsigned long bist)
report_bist_failure(bist); report_bist_failure(bist);
enable_smbus(); enable_smbus();
smbus_block_write(0x69, 0, 13, clockgen_block);
pineview_early_initialization(); pineview_early_initialization();
post_code(0x30); post_code(0x30);