armv8/secmon: Disable and Enable GIC in PSCI path

Disable and enable GIC before switching off a CPU and after bringing
it up back respectively.

BUG=None
BRANCH=None
TEST=Compiles successfully and psci commands work for ryu.

Change-Id: Ib43af60e994e3d072e897a59595775d0b2dcef83
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d5271d731f0a569583c2b32ef6726dadbfa846d3
Original-Change-Id: I672945fcb0ff416008a1aad5ed625cfa91bb9cbd
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/265623
Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org>
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9926
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
This commit is contained in:
Furquan Shaikh
2015-04-13 19:57:54 -07:00
committed by Patrick Georgi
parent 54594d0e94
commit 1e2abe05a8
4 changed files with 41 additions and 0 deletions

View File

@@ -59,6 +59,11 @@ static struct gic *gic_get(void)
return &gic;
}
static inline uint32_t gic_read(uint32_t *base)
{
return read32(base);
}
static inline void gic_write(uint32_t *base, uint32_t val)
{
write32(base, val);
@@ -118,3 +123,31 @@ void gic_init(void)
/* Allow Non-secure access to everything. */
gic_write_regs(&gicd->nsacr[0], gic->num_interrupts / 16, ~0x0);
}
void gic_disable(void)
{
struct gic *gic;
struct gicc_mmio *gicc;
gic = gic_get();
gicc = gic->gicc;
/* Disable secure, non-secure interrupts. */
uint32_t val = gic_read(&gicc->ctlr);
val &= ~(ENABLE_GRP0 | ENABLE_GRP1);
gic_write(&gicc->ctlr, val);
}
void gic_enable(void)
{
struct gic *gic;
struct gicc_mmio *gicc;
gic = gic_get();
gicc = gic->gicc;
/* Enable secure, non-secure interrupts. */
uint32_t val = gic_read(&gicc->ctlr);
val |= (ENABLE_GRP0 | ENABLE_GRP1);
gic_write(&gicc->ctlr, val);
}