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soc/amd/picasso: Fix TSC frequency calculation

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Fix TSC frequency calculation per Picasso PPR. This code was copied
from Stoney and was incorrect for Picasso.

BUG=b:163423984
TEST=verify Dalboz TSC to be 1GHz
BRANCH=zork

Change-Id: Ibe3f49c7d295e7336ee042da2b94823171b6eb55
Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45055
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
This commit is contained in:
Nikolai Vyssotski
2020-09-02 17:51:09 -05:00
committed by Aaron Durbin
parent 1fa45b1460
commit 1e633e88dd
1 changed files with 17 additions and 3 deletions
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20
src/soc/amd/picasso/tsc_freq.c
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@@ -7,6 +7,10 @@
static unsigned long mhz; static unsigned long mhz;
/* Use this default TSC frequency when it can not be correctly calculated.
Higher numbers are safer as it will result in longer delays using TSC */
#define TSC_DEFAULT_FREQ_MHZ 4000
unsigned long tsc_freq_mhz(void) unsigned long tsc_freq_mhz(void)
{ {
msr_t msr; msr_t msr;
@@ -22,9 +26,19 @@ unsigned long tsc_freq_mhz(void)
if (!(msr.hi & 0x80000000)) if (!(msr.hi & 0x80000000))
die("Unknown error: cannot determine P-state 0\n"); die("Unknown error: cannot determine P-state 0\n");
cpufid = (msr.lo & 0x3f); cpufid = (msr.lo & 0xff);
cpudid = (msr.lo & 0x1c0) >> 6; cpudid = (msr.lo & 0x3f00) >> 8;
/* normally core frequency is calculated as (fid * 25) / (did / 8) */
if (!cpudid) {
mhz = TSC_DEFAULT_FREQ_MHZ;
printk(BIOS_ERR, "Invalid divisor, set TSC frequency to %ldMHz\n", mhz);
} else if ((cpudid >= 8) && (cpudid < 0x3c)) {
mhz = (200 * cpufid) / cpudid;
} else {
mhz = 25 * cpufid;
printk(BIOS_ERR, "Invalid frequency divisor 0x%x, assume 1\n", cpudid);
}
mhz = (100 * (cpufid + 0x10)) / (0x01 << cpudid);
return mhz; return mhz;
} }