src/*/post_code.h: Change post code prefix to POSTCODE
The prefix POSTCODE makes it clear that the macro is a post code. Hence, replace related macros starting with POST to POSTCODE and also replace every instance the macros are invoked with the new name. The files was changed by running the following bash script from the top level directory. header="src/soc/amd/common/block/include/amdblocks/post_codes.h \ src/include/cpu/intel/post_codes.h \ src/soc/intel/common/block/include/intelblocks/post_codes.h" array=`grep -r "#define POST_" $header | \ tr '\t' ' ' | cut -d ":" -f 2 | cut -d " " -f 2` for str in $array; do splitstr=`echo $str | cut -d '_' -f2-` grep -r $str src | cut -d ':' -f 1 | \ xargs sed -i'' -e "s/$str/POSTCODE_$splitstr/g" done Change-Id: Id2ca654126fc5b96e6b40d222bb636bbf39ab7ad Signed-off-by: Yuchen He <yuchenhe126@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76044 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
This commit is contained in:
committed by
Matt DeVillier
parent
71b8ee0da4
commit
1e67adbc73
@@ -29,7 +29,7 @@ wait_for_sipi:
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bt $12, %eax
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jc wait_for_sipi
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post_code(POST_SOC_CLEAR_FIXED_MTRRS)
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post_code(POSTCODE_SOC_CLEAR_FIXED_MTRRS)
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/* Clear/disable fixed MTRRs */
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mov $fixed_mtrr_list, %ebx
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@@ -59,7 +59,7 @@ clear_var_mtrr:
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dec %ebx
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jnz clear_var_mtrr
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post_code(POST_SOC_SET_DEF_MTRR_TYPE)
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post_code(POSTCODE_SOC_SET_DEF_MTRR_TYPE)
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/* Configure the default memory type to uncacheable. */
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movl $MTRR_DEF_TYPE_MSR, %ecx
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rdmsr
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@@ -84,7 +84,7 @@ addrsize_set_high:
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movl $MTRR_PHYS_MASK(1), %ecx
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wrmsr
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post_code(POST_SOC_SET_MTRR_BASE)
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post_code(POSTCODE_SOC_SET_MTRR_BASE)
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/* Set Cache-as-RAM base address. */
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movl $(MTRR_PHYS_BASE(0)), %ecx
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movl $_car_mtrr_start, %eax
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@@ -92,7 +92,7 @@ addrsize_set_high:
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xorl %edx, %edx
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wrmsr
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post_code(POST_SOC_SET_MTRR_MASK)
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post_code(POSTCODE_SOC_SET_MTRR_MASK)
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/* Set Cache-as-RAM mask. */
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movl $(MTRR_PHYS_MASK(0)), %ecx
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rdmsr
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@@ -100,7 +100,7 @@ addrsize_set_high:
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orl $MTRR_PHYS_MASK_VALID, %eax
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wrmsr
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post_code(POST_SOC_ENABLE_MTRRS)
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post_code(POSTCODE_SOC_ENABLE_MTRRS)
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/* Enable MTRR. */
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movl $MTRR_DEF_TYPE_MSR, %ecx
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@@ -128,7 +128,7 @@ addrsize_set_high:
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shr $2, %ecx
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rep stosl
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post_code(POST_SOC_DISABLE_CACHE)
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post_code(POSTCODE_SOC_DISABLE_CACHE)
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/* Enable Cache-as-RAM mode by disabling cache. */
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movl %cr0, %eax
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orl $CR0_CacheDisable, %eax
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@@ -147,7 +147,7 @@ addrsize_set_high:
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orl $MTRR_PHYS_MASK_VALID, %eax
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wrmsr
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post_code(POST_SOC_ENABLE_CACHE)
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post_code(POSTCODE_SOC_ENABLE_CACHE)
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/* Enable cache. */
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movl %cr0, %eax
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andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax
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@@ -181,7 +181,7 @@ addrsize_set_high:
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#endif
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before_c_entry:
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post_code(POST_BOOTBLOCK_BEFORE_C_ENTRY)
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post_code(POSTCODE_BOOTBLOCK_BEFORE_C_ENTRY)
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call bootblock_c_entry_bist
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/* Should never see this postcode */
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@@ -34,14 +34,14 @@ wait_for_sipi:
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bt $12, %eax
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jc wait_for_sipi
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post_code(POST_SOC_SET_DEF_MTRR_TYPE)
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post_code(POSTCODE_SOC_SET_DEF_MTRR_TYPE)
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/* Clean-up MTRR_DEF_TYPE_MSR. */
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movl $MTRR_DEF_TYPE_MSR, %ecx
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xorl %eax, %eax
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xorl %edx, %edx
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wrmsr
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post_code(POST_SOC_CLEAR_FIXED_MTRRS)
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post_code(POSTCODE_SOC_CLEAR_FIXED_MTRRS)
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/* Clear/disable fixed MTRRs */
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mov $fixed_mtrr_list, %ebx
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xor %eax, %eax
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@@ -88,7 +88,7 @@ addrsize_set_high:
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movl $MTRR_PHYS_MASK(1), %ecx
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wrmsr
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post_code(POST_SOC_SET_MTRR_BASE)
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post_code(POSTCODE_SOC_SET_MTRR_BASE)
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/* Set Cache-as-RAM base address. */
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movl $(MTRR_PHYS_BASE(0)), %ecx
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movl car_mtrr_start, %eax
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@@ -96,7 +96,7 @@ addrsize_set_high:
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xorl %edx, %edx
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wrmsr
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post_code(POST_SOC_SET_MTRR_MASK)
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post_code(POSTCODE_SOC_SET_MTRR_MASK)
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/* Set Cache-as-RAM mask. */
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movl $(MTRR_PHYS_MASK(0)), %ecx
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rdmsr
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@@ -117,7 +117,7 @@ addrsize_set_high:
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orl $MTRR_PHYS_MASK_VALID, %eax
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wrmsr
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post_code(POST_SOC_ENABLE_MTRRS)
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post_code(POSTCODE_SOC_ENABLE_MTRRS)
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/* Enable MTRR. */
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movl $MTRR_DEF_TYPE_MSR, %ecx
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@@ -188,7 +188,7 @@ end_microcode_update:
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orl $3, %eax
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wrmsr
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post_code(POST_SOC_DISABLE_CACHE)
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post_code(POSTCODE_SOC_DISABLE_CACHE)
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/* Enable Cache-as-RAM mode by disabling cache. */
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movl %cr0, %eax
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orl $CR0_CacheDisable, %eax
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@@ -199,7 +199,7 @@ end_microcode_update:
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orl $MTRR_PHYS_MASK_VALID, %eax
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wrmsr
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post_code(POST_SOC_ENABLE_CACHE)
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post_code(POSTCODE_SOC_ENABLE_CACHE)
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/* Enable cache. */
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movl %cr0, %eax
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andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax
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@@ -234,7 +234,7 @@ end_microcode_update:
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#endif
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before_c_entry:
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post_code(POST_BOOTBLOCK_BEFORE_C_ENTRY)
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post_code(POSTCODE_BOOTBLOCK_BEFORE_C_ENTRY)
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call bootblock_c_entry_bist
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/* Should never see this postcode */
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@@ -13,14 +13,14 @@
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chipset_teardown_car:
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pop %esp
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post_code(POST_POSTCAR_DISABLE_CACHE)
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post_code(POSTCODE_POSTCAR_DISABLE_CACHE)
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/* Disable cache. */
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movl %cr0, %eax
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orl $CR0_CacheDisable, %eax
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movl %eax, %cr0
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post_code(POST_POSTCAR_DISABLE_DEF_MTRR)
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post_code(POSTCODE_POSTCAR_DISABLE_DEF_MTRR)
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/* Disable MTRR. */
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movl $MTRR_DEF_TYPE_MSR, %ecx
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@@ -36,7 +36,7 @@ chipset_teardown_car:
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andl $~1, %eax
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wrmsr
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post_code(POST_POSTCAR_TEARDOWN_DONE)
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post_code(POSTCODE_POSTCAR_TEARDOWN_DONE)
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/* Return to caller. */
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jmp *%esp
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@@ -42,7 +42,7 @@ clear_var_mtrr:
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inc %ecx
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dec %ebx
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jnz clear_var_mtrr
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post_code(POST_SOC_SET_DEF_MTRR_TYPE)
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post_code(POSTCODE_SOC_SET_DEF_MTRR_TYPE)
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/* Configure the default memory type to uncacheable. */
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movl $MTRR_DEF_TYPE_MSR, %ecx
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@@ -50,7 +50,7 @@ clear_var_mtrr:
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andl $(~0x00000cff), %eax
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wrmsr
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post_code(POST_SOC_DETERMINE_CPU_ADDR_BITS)
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post_code(POSTCODE_SOC_DETERMINE_CPU_ADDR_BITS)
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/* Determine CPU_ADDR_BITS and load PHYSMASK high word to %edx. */
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movl $1, %eax
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@@ -68,7 +68,7 @@ addrsize_set_high:
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movl $MTRR_PHYS_MASK(1), %ecx
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wrmsr
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post_code(POST_SOC_SET_CAR_BASE)
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post_code(POSTCODE_SOC_SET_CAR_BASE)
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/* Set Cache-as-RAM base address. */
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movl $(MTRR_PHYS_BASE(0)), %ecx
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@@ -84,7 +84,7 @@ addrsize_set_high:
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orl $MTRR_PHYS_MASK_VALID, %eax
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wrmsr
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post_code(POST_SOC_ENABLE_MTRRS)
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post_code(POSTCODE_SOC_ENABLE_MTRRS)
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/* Enable MTRR. */
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movl $MTRR_DEF_TYPE_MSR, %ecx
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@@ -92,7 +92,7 @@ addrsize_set_high:
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orl $MTRR_DEF_TYPE_EN, %eax
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wrmsr
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post_code(POST_SOC_ENABLE_CACHE)
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post_code(POSTCODE_SOC_ENABLE_CACHE)
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/* Enable cache (CR0.CD = 0, CR0.NW = 0). */
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movl %cr0, %eax
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@@ -114,7 +114,7 @@ addrsize_set_high:
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xorl %eax, %eax
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rep stosl
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post_code(POST_SOC_DISABLE_CACHE)
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post_code(POSTCODE_SOC_DISABLE_CACHE)
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/* Enable Cache-as-RAM mode by disabling cache. */
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movl %cr0, %eax
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orl $CR0_CacheDisable, %eax
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@@ -133,7 +133,7 @@ addrsize_set_high:
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orl $MTRR_PHYS_MASK_VALID, %eax
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wrmsr
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post_code(POST_SOC_FILL_CACHE)
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post_code(POSTCODE_SOC_FILL_CACHE)
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/* Enable cache. */
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movl %cr0, %eax
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andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax
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@@ -156,7 +156,7 @@ addrsize_set_high:
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pushl %eax /* tsc[31:0] */
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before_c_entry:
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post_code(POST_BOOTBLOCK_BEFORE_C_ENTRY)
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post_code(POSTCODE_BOOTBLOCK_BEFORE_C_ENTRY)
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call bootblock_c_entry_bist
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/* Should never see this postcode */
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@@ -54,7 +54,7 @@ clear_var_mtrr:
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inc %ecx
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dec %ebx
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jnz clear_var_mtrr
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post_code(POST_SOC_SET_DEF_MTRR_TYPE)
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post_code(POSTCODE_SOC_SET_DEF_MTRR_TYPE)
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/* Configure the default memory type to uncacheable. */
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movl $MTRR_DEF_TYPE_MSR, %ecx
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@@ -62,7 +62,7 @@ clear_var_mtrr:
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andl $(~0x00000cff), %eax
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wrmsr
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post_code(POST_SOC_DETERMINE_CPU_ADDR_BITS)
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post_code(POSTCODE_SOC_DETERMINE_CPU_ADDR_BITS)
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/* Determine CPU_ADDR_BITS and load PHYSMASK high
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* word to %edx.
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@@ -106,7 +106,7 @@ addrsize_set_high:
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bsp_init:
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post_code(POST_SOC_BSP_INIT)
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post_code(POSTCODE_SOC_BSP_INIT)
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/* Send INIT IPI to all excluding ourself. */
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movl LAPIC(ICR), %edi
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@@ -120,7 +120,7 @@ bsp_init:
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andl $LAPIC_ICR_BUSY, %ecx
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jnz 1b
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post_code(POST_SOC_COUNT_CORES)
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post_code(POSTCODE_SOC_COUNT_CORES)
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movl $1, %eax
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cpuid
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@@ -155,7 +155,7 @@ cores_counted:
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hyper_threading_cpu:
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post_code(POST_SOC_CPU_HYPER_THREADING)
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post_code(POSTCODE_SOC_CPU_HYPER_THREADING)
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/* Send Start IPI to all excluding ourself. */
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movl LAPIC(ICR), %edi
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@@ -170,7 +170,7 @@ hyper_threading_cpu:
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andl $LAPIC_ICR_BUSY, %ecx
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jnz 1b
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post_code(POST_SOC_CPU_SIBLING_DELAY)
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post_code(POSTCODE_SOC_CPU_SIBLING_DELAY)
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/* Wait for sibling CPU to start. */
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1: movl $(MTRR_PHYS_BASE(0)), %ecx
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@@ -186,14 +186,14 @@ hyper_threading_cpu:
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ap_init:
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post_code(POST_SOC_CPU_AP_INIT)
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post_code(POSTCODE_SOC_CPU_AP_INIT)
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/* Do not disable cache (so BSP can enable it). */
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movl %cr0, %eax
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andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax
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movl %eax, %cr0
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post_code(POST_SOC_SET_MTRR_BASE)
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post_code(POSTCODE_SOC_SET_MTRR_BASE)
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/* MTRR registers are shared between HT siblings. */
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movl $(MTRR_PHYS_BASE(0)), %ecx
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@@ -201,7 +201,7 @@ ap_init:
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xorl %edx, %edx
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wrmsr
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post_code(POST_SOC_AP_HALT)
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post_code(POSTCODE_SOC_AP_HALT)
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ap_halt:
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cli
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@@ -212,7 +212,7 @@ ap_halt:
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sipi_complete:
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post_code(POST_SOC_SET_CAR_BASE)
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post_code(POSTCODE_SOC_SET_CAR_BASE)
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/* Set Cache-as-RAM base address. */
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movl $(MTRR_PHYS_BASE(0)), %ecx
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@@ -228,7 +228,7 @@ sipi_complete:
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orl $MTRR_PHYS_MASK_VALID, %eax
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wrmsr
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post_code(POST_SOC_ENABLE_MTRRS)
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post_code(POSTCODE_SOC_ENABLE_MTRRS)
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/* Enable MTRR. */
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movl $MTRR_DEF_TYPE_MSR, %ecx
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@@ -271,7 +271,7 @@ has_msr_11e:
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wrmsr
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no_msr_11e:
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post_code(POST_SOC_ENABLE_CACHE)
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post_code(POSTCODE_SOC_ENABLE_CACHE)
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/* Cache the whole rom to fetch microcode updates */
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movl $MTRR_PHYS_BASE(1), %ecx
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@@ -298,7 +298,7 @@ no_msr_11e:
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jmp update_bsp_microcode
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end_microcode_update:
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#endif
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post_code(POST_SOC_DISABLE_CACHE)
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post_code(POSTCODE_SOC_DISABLE_CACHE)
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/* Disable caching to change MTRR's. */
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movl %cr0, %eax
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orl $CR0_CacheDisable, %eax
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@@ -338,7 +338,7 @@ cache_rom:
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wrmsr
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fill_cache:
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post_code(POST_SOC_FILL_CACHE)
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post_code(POSTCODE_SOC_FILL_CACHE)
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/* Enable cache. */
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movl %cr0, %eax
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andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax
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@@ -381,7 +381,7 @@ fill_cache:
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#endif
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before_c_entry:
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post_code(POST_BOOTBLOCK_BEFORE_C_ENTRY)
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post_code(POSTCODE_BOOTBLOCK_BEFORE_C_ENTRY)
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call bootblock_c_entry_bist
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/* Should never see this postcode */
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@@ -11,14 +11,14 @@
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chipset_teardown_car:
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pop %esp
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post_code(POST_POSTCAR_DISABLE_CACHE)
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post_code(POSTCODE_POSTCAR_DISABLE_CACHE)
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/* Disable cache. */
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movl %cr0, %eax
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orl $CR0_CacheDisable, %eax
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movl %eax, %cr0
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post_code(POST_POSTCAR_DISABLE_DEF_MTRR)
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post_code(POSTCODE_POSTCAR_DISABLE_DEF_MTRR)
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/* Disable MTRR. */
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movl $MTRR_DEF_TYPE_MSR, %ecx
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@@ -26,7 +26,7 @@ chipset_teardown_car:
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andl $(~MTRR_DEF_TYPE_EN), %eax
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wrmsr
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post_code(POST_POSTCAR_TEARDOWN_DONE)
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post_code(POSTCODE_POSTCAR_TEARDOWN_DONE)
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/* Return to caller. */
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jmp *%esp
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