From 1e7386989b33cac92e63a79d2086af5ee9da5d4e Mon Sep 17 00:00:00 2001 From: Tim Crawford Date: Sun, 24 Jul 2022 16:09:41 -0600 Subject: [PATCH] mb/system76/tgl-u: Restore old FSP configs Re-add FSP-S configs from the 4.13 branch, which were not included when upstreamed. Change-Id: I5f99d088190df07213c5b615f36fde29831aad86 Signed-off-by: Tim Crawford --- src/mainboard/system76/tgl-u/Makefile.inc | 1 + src/mainboard/system76/tgl-u/ramstage.c | 6 ------ .../system76/tgl-u/variants/darp7/ramstage.c | 15 +++++++++++++++ .../system76/tgl-u/variants/galp5/ramstage.c | 15 +++++++++++++++ .../system76/tgl-u/variants/lemp10/ramstage.c | 15 +++++++++++++++ 5 files changed, 46 insertions(+), 6 deletions(-) create mode 100644 src/mainboard/system76/tgl-u/variants/darp7/ramstage.c create mode 100644 src/mainboard/system76/tgl-u/variants/galp5/ramstage.c create mode 100644 src/mainboard/system76/tgl-u/variants/lemp10/ramstage.c diff --git a/src/mainboard/system76/tgl-u/Makefile.inc b/src/mainboard/system76/tgl-u/Makefile.inc index ff90842185..0e04be08d1 100644 --- a/src/mainboard/system76/tgl-u/Makefile.inc +++ b/src/mainboard/system76/tgl-u/Makefile.inc @@ -9,5 +9,6 @@ romstage-y += variants/$(VARIANT_DIR)/romstage.c ramstage-y += ramstage.c ramstage-y += variants/$(VARIANT_DIR)/gpio.c ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c +ramstage-y += variants/$(VARIANT_DIR)/ramstage.c SPD_SOURCES = samsung-M471A1G44AB0-CWE diff --git a/src/mainboard/system76/tgl-u/ramstage.c b/src/mainboard/system76/tgl-u/ramstage.c index dd7e73c595..a3b12bb1f2 100644 --- a/src/mainboard/system76/tgl-u/ramstage.c +++ b/src/mainboard/system76/tgl-u/ramstage.c @@ -3,12 +3,6 @@ #include #include -void mainboard_silicon_init_params(FSP_S_CONFIG *params) -{ - // Disable AER to fix suspend failing with some SSDs. - params->CpuPcieRpAdvancedErrorReporting[0] = 0; -} - static void mainboard_init(void *chip_info) { mainboard_configure_gpios(); diff --git a/src/mainboard/system76/tgl-u/variants/darp7/ramstage.c b/src/mainboard/system76/tgl-u/variants/darp7/ramstage.c new file mode 100644 index 0000000000..6cf6d737b6 --- /dev/null +++ b/src/mainboard/system76/tgl-u/variants/darp7/ramstage.c @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +void mainboard_silicon_init_params(FSP_S_CONFIG *params) +{ + // CPU RP Config + params->CpuPcieRpAdvancedErrorReporting[0] = 0; + params->CpuPcieRpLtrEnable[0] = 1; + params->CpuPcieRpPtmEnabled[0] = 0; + + // IOM config + params->PchUsbOverCurrentEnable = 0; + params->PortResetMessageEnable[5] = 1; // J_TYPEC2 +} diff --git a/src/mainboard/system76/tgl-u/variants/galp5/ramstage.c b/src/mainboard/system76/tgl-u/variants/galp5/ramstage.c new file mode 100644 index 0000000000..6cf6d737b6 --- /dev/null +++ b/src/mainboard/system76/tgl-u/variants/galp5/ramstage.c @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +void mainboard_silicon_init_params(FSP_S_CONFIG *params) +{ + // CPU RP Config + params->CpuPcieRpAdvancedErrorReporting[0] = 0; + params->CpuPcieRpLtrEnable[0] = 1; + params->CpuPcieRpPtmEnabled[0] = 0; + + // IOM config + params->PchUsbOverCurrentEnable = 0; + params->PortResetMessageEnable[5] = 1; // J_TYPEC2 +} diff --git a/src/mainboard/system76/tgl-u/variants/lemp10/ramstage.c b/src/mainboard/system76/tgl-u/variants/lemp10/ramstage.c new file mode 100644 index 0000000000..393ebf292b --- /dev/null +++ b/src/mainboard/system76/tgl-u/variants/lemp10/ramstage.c @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +void mainboard_silicon_init_params(FSP_S_CONFIG *params) +{ + // CPU RP Config + params->CpuPcieRpAdvancedErrorReporting[0] = 0; + params->CpuPcieRpLtrEnable[0] = 1; + params->CpuPcieRpPtmEnabled[0] = 0; + + // IOM config + params->PchUsbOverCurrentEnable = 0; + params->PortResetMessageEnable[2] = 1; // J_TYPEC1 +}