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mb/google/volteer/var/drobit: change GPP_B2 to PLTRST

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Change GPP_B2 (EN_PP3300_SSD) to PLTRST to avoid S3 resume hang.
Add GPP_B2 to the early_gpio_table.

BUG=b:174776411
BRANCH=none
TEST=none

Change-Id: I49f7b1b69c3c3ab5593c7230d8f631a3b54c9c9d
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55440
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
Nick Vaccaro
2021-06-11 18:05:48 -07:00
parent ae10d8119e
commit 1e7582650e
1 changed files with 3 additions and 1 deletions
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4
src/mainboard/google/volteer/variants/drobit/gpio.c
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@@ -25,7 +25,7 @@ static const struct pad_config override_gpio_table[] = {
PAD_CFG_NF(GPP_A23, NONE, DEEP, NF1),
/* B2 : VRALERT# ==> EN_PP3300_SSD */
PAD_CFG_GPO(GPP_B2, 1, DEEP),
PAD_CFG_GPO(GPP_B2, 1, PLTRST),
/* B9 : I2C5_SDA ==> PCH_I2C5_TRACKPAD_SDA */
PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1),
/* B10 : I2C5_SCL ==> PCH_I2C5_TRACKPAD_SCL */
@@ -143,6 +143,8 @@ static const struct pad_config early_gpio_table[] = {
/* A17 : DDSP_HPDC ==> MEM_CH_SEL */
PAD_CFG_GPI(GPP_A17, NONE, DEEP),
/* B2 : VRALERT# ==> EN_PP3300_SSD */
PAD_CFG_GPO(GPP_B2, 1, PLTRST),
/* B11 : PMCALERT# ==> PCH_WP_OD */
PAD_CFG_GPI_GPIO_DRIVER(GPP_B11, NONE, DEEP),
/* B15 : GSPI0_CS0# ==> PCH_GSPI0_H1_TPM_CS_L */