From 4249348735d18cb2d44506090a675a29b0567e7f Mon Sep 17 00:00:00 2001 From: "Ronald G. Minnich" Date: Thu, 9 May 2019 17:09:25 +0000 Subject: [PATCH 001/331] Define ENV_PAYLOAD_LOADER We've been assuming that ENV_RAMSTAGE is always the payload loader. In order to test out different models, we need a way to mark the "stage we are in" as the payload loader. Define a new rule, ENV_PAYLOAD_LOADER. For now, it is set to ENV_RAMSTAGE. It is not used yet pending approval of this approach. Change-Id: I7d4aa71bad92987374d57ff350b9b0178ee7c12b Signed-off-by: Ronald G. Minnich Reviewed-on: https://review.coreboot.org/c/coreboot/+/32709 Tested-by: build bot (Jenkins) --- src/include/rules.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/include/rules.h b/src/include/rules.h index ea8335fb8c..ce968f0dd9 100644 --- a/src/include/rules.h +++ b/src/include/rules.h @@ -257,6 +257,10 @@ #endif +/* ENV_PAYLOAD_LOADER is set when you are in a stage that loads the payload. + * For now, that is the ramstage. */ +#define ENV_PAYLOAD_LOADER ENV_RAMSTAGE + /** * For pre-DRAM stages and post-CAR always build with simple device model, ie. * PCI, PNP and CPU functions operate without use of devicetree. The reason From 1159a163cd36318d27f8f3b71617ad4a5b781efb Mon Sep 17 00:00:00 2001 From: John Zhao Date: Mon, 22 Apr 2019 10:45:51 -0700 Subject: [PATCH 002/331] soc/intel/cnl: Enable VT-d Enable VT-d through fsp upd VtdDisable. Update remapping structure types in numerical order as all remapping structures of type 0 (DRHD) enumerated before remapping structures of type 1 (RMRR), and so forth. BUG=b:130351429 TEST=Booted to kernel and verified the DMAR table contents. Change-Id: I1d20932e417b9d324edd98c8f2195dc228d2e092 Signed-off-by: John Zhao Reviewed-on: https://review.coreboot.org/c/coreboot/+/32432 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber Reviewed-by: Pratikkumar V Prajapati --- src/soc/intel/cannonlake/acpi.c | 15 ++++++++------- src/soc/intel/cannonlake/chip.h | 3 --- src/soc/intel/cannonlake/romstage/fsp_params.c | 5 +++++ src/soc/intel/cannonlake/systemagent.c | 6 +----- 4 files changed, 14 insertions(+), 15 deletions(-) diff --git a/src/soc/intel/cannonlake/acpi.c b/src/soc/intel/cannonlake/acpi.c index 209e7c52d4..ff9da451c8 100644 --- a/src/soc/intel/cannonlake/acpi.c +++ b/src/soc/intel/cannonlake/acpi.c @@ -304,13 +304,6 @@ static unsigned long soc_fill_dmar(unsigned long current) current += acpi_create_dmar_ds_pci(current, 0, 2, 0); acpi_dmar_drhd_fixup(tmp, current); - - /* Add RMRR entry */ - tmp = current; - current += acpi_create_dmar_rmrr(current, 0, - sa_get_gsm_base(), sa_get_tolud_base() - 1); - current += acpi_create_dmar_ds_pci(current, 0, 2, 0); - acpi_dmar_rmrr_fixup(tmp, current); } struct device *const ipu_dev = dev_find_slot(0, SA_DEVFN_IPU); @@ -344,6 +337,13 @@ static unsigned long soc_fill_dmar(unsigned long current) acpi_dmar_drhd_fixup(tmp, current); } + /* Add RMRR entry */ + const unsigned long tmp = current; + current += acpi_create_dmar_rmrr(current, 0, + sa_get_gsm_base(), sa_get_tolud_base() - 1); + current += acpi_create_dmar_ds_pci(current, 0, 2, 0); + acpi_dmar_rmrr_fixup(tmp, current); + return current; } @@ -361,6 +361,7 @@ unsigned long sa_write_acpi_tables(struct device *dev, unsigned long current, printk(BIOS_DEBUG, "ACPI: * DMAR\n"); acpi_create_dmar(dmar, DMAR_INTR_REMAP, soc_fill_dmar); + current += dmar->header.length; current = acpi_align_current(current); acpi_add_table(rsdp, dmar); diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index f34528a017..2b2a51f6a0 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -344,9 +344,6 @@ struct soc_intel_cannonlake_config { /* Enable Pch iSCLK */ uint8_t pch_isclk; - /* Intel VT configuration */ - uint8_t VtdDisable; - /* * Acoustic Noise Mitigation * 0b - Disable diff --git a/src/soc/intel/cannonlake/romstage/fsp_params.c b/src/soc/intel/cannonlake/romstage/fsp_params.c index c71e4b551a..6e492bb73a 100644 --- a/src/soc/intel/cannonlake/romstage/fsp_params.c +++ b/src/soc/intel/cannonlake/romstage/fsp_params.c @@ -101,6 +101,7 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) assert(dev != NULL); const config_t *config = dev->chip_info; FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; + FSP_M_TEST_CONFIG *tconfig = &mupd->FspmTestConfig; soc_memory_init_params(m_cfg, config); @@ -113,6 +114,10 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) /* Set debug probe type */ m_cfg->PlatformDebugConsent = CONFIG_SOC_INTEL_CANNONLAKE_DEBUG_CONSENT; + + /* Configure VT-d */ + tconfig->VtdDisable = 0; + mainboard_memory_init_params(mupd); } diff --git a/src/soc/intel/cannonlake/systemagent.c b/src/soc/intel/cannonlake/systemagent.c index d850b15b34..3f01f14dcf 100644 --- a/src/soc/intel/cannonlake/systemagent.c +++ b/src/soc/intel/cannonlake/systemagent.c @@ -33,8 +33,6 @@ */ void soc_add_fixed_mmio_resources(struct device *dev, int *index) { - const struct soc_intel_cannonlake_config *const config = dev->chip_info; - static const struct sa_mmio_descriptor soc_fixed_resources[] = { { PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_SA_PCIEX_LENGTH, "PCIEXBAR" }, @@ -63,10 +61,8 @@ void soc_add_fixed_mmio_resources(struct device *dev, int *index) if ((pci_read_config32(dev, CAPID0_A) & VTD_DISABLE)) return; - if (!(config && config->VtdDisable)) { - sa_add_fixed_mmio_resources(dev, index, soc_vtd_resources, + sa_add_fixed_mmio_resources(dev, index, soc_vtd_resources, ARRAY_SIZE(soc_vtd_resources)); - } } /* From 7bc9036d160c6235d96e1bed49331696d7fa9a09 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Fri, 10 May 2019 11:58:37 +0530 Subject: [PATCH 003/331] arch/cpu: Rename mp_get_apic_id() and add_cpu_map_entry() function This patch renames mp_get_apic_id() to cpu_get_apic_id() and add_cpu_map_entry() to cpu_add_map_entry() in order access it outside CONFIG_PARALLEL_MP kconfig scope. Also make below changes - Make cpu_add_map_entry() function available externally to call it from mp_init.c and lapic_cpu_init.c. BRANCH=none BUG=b:79562868 Change-Id: I6a6c85df055bc0b5fc8c850cfa04d50859067088 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/32701 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/arch/x86/cpu.c | 29 +++++++++++++++++++++++++++++ src/cpu/x86/mp_init.c | 35 +++++++---------------------------- src/include/cpu/cpu.h | 4 ++++ src/include/cpu/x86/mp.h | 3 --- 4 files changed, 40 insertions(+), 31 deletions(-) diff --git a/src/arch/x86/cpu.c b/src/arch/x86/cpu.c index 80d4d0da4a..f19b389441 100644 --- a/src/arch/x86/cpu.c +++ b/src/arch/x86/cpu.c @@ -219,6 +219,35 @@ static void set_cpu_ops(struct device *cpu) cpu->ops = driver ? driver->ops : NULL; } +/* Keep track of default apic ids for SMM. */ +static int cpus_default_apic_id[CONFIG_MAX_CPUS]; + +/* + * When CPUID executes with EAX set to 1, additional processor identification + * information is returned to EBX register: + * Default APIC ID: EBX[31-24] - this number is the 8 bit ID that is assigned + * to the local APIC on the processor during power on. + */ +static int initial_lapicid(void) +{ + return cpuid_ebx(1) >> 24; +} + +/* Function to keep track of cpu default apic_id */ +void cpu_add_map_entry(unsigned int index) +{ + cpus_default_apic_id[index] = initial_lapicid(); +} + +/* Returns default APIC id based on logical_cpu number or < 0 on failure. */ +int cpu_get_apic_id(int logical_cpu) +{ + if (logical_cpu >= CONFIG_MAX_CPUS || logical_cpu < 0) + return -1; + + return cpus_default_apic_id[logical_cpu]; +} + void cpu_initialize(unsigned int index) { /* Because we busy wait at the printk spinlock. diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c index 9d51b3e8b5..8957515540 100644 --- a/src/cpu/x86/mp_init.c +++ b/src/cpu/x86/mp_init.c @@ -135,20 +135,8 @@ struct mp_flight_plan { static int global_num_aps; static struct mp_flight_plan mp_info; -struct cpu_map { - struct device *dev; - /* Keep track of default apic ids for SMM. */ - int default_apic_id; -}; - -/* Keep track of APIC and device structure for each CPU. */ -static struct cpu_map cpus[CONFIG_MAX_CPUS]; - -static inline void add_cpu_map_entry(const struct cpu_info *info) -{ - cpus[info->index].dev = info->cpu; - cpus[info->index].default_apic_id = cpuid_ebx(1) >> 24; -} +/* Keep track of device structure for each CPU. */ +static struct device *cpus_dev[CONFIG_MAX_CPUS]; static inline void barrier_wait(atomic_t *b) { @@ -212,9 +200,9 @@ static void asmlinkage ap_init(unsigned int cpu) info = cpu_info(); info->index = cpu; - info->cpu = cpus[cpu].dev; + info->cpu = cpus_dev[cpu]; - add_cpu_map_entry(info); + cpu_add_map_entry(info->index); thread_init_cpu_info_non_bsp(info); /* Fix up APIC id with reality. */ @@ -411,7 +399,7 @@ static int allocate_cpu_devices(struct bus *cpu_bus, struct mp_params *p) continue; } new->name = processor_name; - cpus[i].dev = new; + cpus_dev[i] = new; } return max_cpus; @@ -589,7 +577,7 @@ static void init_bsp(struct bus *cpu_bus) printk(BIOS_CRIT, "BSP index(%d) != 0!\n", info->index); /* Track BSP in cpu_map structures. */ - add_cpu_map_entry(info); + cpu_add_map_entry(info->index); } /* @@ -667,15 +655,6 @@ static void mp_initialize_cpu(void) cpu_initialize(info->index); } -/* Returns APIC id for coreboot CPU number or < 0 on failure. */ -int mp_get_apic_id(int logical_cpu) -{ - if (logical_cpu >= CONFIG_MAX_CPUS || logical_cpu < 0) - return -1; - - return cpus[logical_cpu].default_apic_id; -} - void smm_initiate_relocation_parallel(void) { if ((lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY)) { @@ -769,7 +748,7 @@ static void adjust_smm_apic_id_map(struct smm_loader_params *smm_params) struct smm_runtime *runtime = smm_params->runtime; for (i = 0; i < CONFIG_MAX_CPUS; i++) - runtime->apic_id_to_cpu[i] = mp_get_apic_id(i); + runtime->apic_id_to_cpu[i] = cpu_get_apic_id(i); } static int install_relocation_handler(int num_cpus, size_t save_state_size) diff --git a/src/include/cpu/cpu.h b/src/include/cpu/cpu.h index 60940f07d1..9a283735d3 100644 --- a/src/include/cpu/cpu.h +++ b/src/include/cpu/cpu.h @@ -5,6 +5,10 @@ #if !defined(__ROMCC__) void cpu_initialize(unsigned int cpu_index); +/* Returns default APIC id based on logical_cpu number or < 0 on failure. */ +int cpu_get_apic_id(int logical_cpu); +/* Function to keep track of cpu default apic_id */ +void cpu_add_map_entry(unsigned int index); struct bus; void initialize_cpus(struct bus *cpu_bus); asmlinkage void secondary_cpu_init(unsigned int cpu_index); diff --git a/src/include/cpu/x86/mp.h b/src/include/cpu/x86/mp.h index 9789910b46..c04252ec35 100644 --- a/src/include/cpu/x86/mp.h +++ b/src/include/cpu/x86/mp.h @@ -145,9 +145,6 @@ int mp_run_on_all_cpus(void (*func)(void *), void *arg, long expire_us); */ int mp_park_aps(void); -/* Returns APIC id for coreboot CPU number or < 0 on failure. */ -int mp_get_apic_id(int logical_cpu); - /* * SMM helpers to use with initializing CPUs. */ From 7e893a02c0cc04b8fdcfee0b4dc0ff790bfe40c5 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Mon, 6 May 2019 14:17:41 +0530 Subject: [PATCH 004/331] Kconfig: Create RAMPAYLOAD kconfig This patch enables coreboot flow to skip ramstage as individual stage to load payload. Instead it is expected to load payload from postcar stage. Change-Id: I839f2d34a93b69ca6bf3de6594e2ad9f66ee7135 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/32618 Tested-by: build bot (Jenkins) Reviewed-by: ron minnich --- src/Kconfig | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/src/Kconfig b/src/Kconfig index b4898bd456..2c9dc4ab7f 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -277,6 +277,21 @@ config BOOTSPLASH_FILE The path and filename of the file to use as graphical bootsplash screen. The file format has to be jpg. +config RAMPAYLOAD + bool "Enable coreboot flow without executing ramstage" + default n + depends on ARCH_X86 + help + If this option is enabled, coreboot flow will skip ramstage + loading and execution of ramstage to load payload. + + Instead it is expected to load payload from postcar stage itself. + + In this flow coreboot will perform basic x86 initialization + (DRAM resource allocation), MTRR programming, + Skip PCI enumeration logic and only allocate BAR for fixed devices + (bootable devices, TPM over GSPI). + endmenu menu "Mainboard" From 2d7a52c784efb6be86bac5cb7aa1f8e1bd7088a6 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Fri, 10 May 2019 17:51:31 +0530 Subject: [PATCH 005/331] lib/timestamp: Make timestamp_sync_cache_to_cbmem() in postcar This patch ensures to have correct timestamp value in postcar. Change-Id: I3ba3a54c20dfcdaf5b87818cc5da9a812f5f2edf Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/32726 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph --- src/lib/timestamp.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/lib/timestamp.c b/src/lib/timestamp.c index b6330fa258..431bce2703 100644 --- a/src/lib/timestamp.c +++ b/src/lib/timestamp.c @@ -350,6 +350,7 @@ uint32_t get_us_since_boot(void) } ROMSTAGE_CBMEM_INIT_HOOK(timestamp_sync_cache_to_cbmem) +POSTCAR_CBMEM_INIT_HOOK(timestamp_sync_cache_to_cbmem) RAMSTAGE_CBMEM_INIT_HOOK(timestamp_sync_cache_to_cbmem) /* Provide default timestamp implementation using monotonic timer. */ From 2be0b50be5783f173989a7882f3650d2a106f974 Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Thu, 9 May 2019 13:43:49 +0200 Subject: [PATCH 006/331] boot_device: Constify argument Add const qualifier to first argument. Change-Id: I6655e04401b6a7aa5cafb717ff6f46b80b96646e Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/c/coreboot/+/32703 Tested-by: build bot (Jenkins) Reviewed-by: Philipp Deppenwiese --- src/drivers/spi/boot_device_rw_nommap.c | 2 +- src/include/boot_device.h | 2 +- src/lib/boot_device.c | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/src/drivers/spi/boot_device_rw_nommap.c b/src/drivers/spi/boot_device_rw_nommap.c index d01d778ca4..cc8fbf7c5d 100644 --- a/src/drivers/spi/boot_device_rw_nommap.c +++ b/src/drivers/spi/boot_device_rw_nommap.c @@ -109,7 +109,7 @@ const struct spi_flash *boot_device_spi_flash(void) return car_get_var_ptr(&sfg); } -int boot_device_wp_region(struct region_device *rd, +int boot_device_wp_region(const struct region_device *rd, const enum bootdev_prot_type type) { uint32_t ctrlr_pr; diff --git a/src/include/boot_device.h b/src/include/boot_device.h index c882968e58..f392c10148 100644 --- a/src/include/boot_device.h +++ b/src/include/boot_device.h @@ -65,7 +65,7 @@ int boot_device_rw_subregion(const struct region *sub, * by the region device. * Returns 0 on success, < 0 on error. */ -int boot_device_wp_region(struct region_device *rd, +int boot_device_wp_region(const struct region_device *rd, const enum bootdev_prot_type type); /* diff --git a/src/lib/boot_device.c b/src/lib/boot_device.c index 429a6d8710..e91a97f461 100644 --- a/src/lib/boot_device.c +++ b/src/lib/boot_device.c @@ -20,7 +20,7 @@ void __weak boot_device_init(void) /* Provide weak do-nothing init. */ } -int __weak boot_device_wp_region(struct region_device *rd, +int __weak boot_device_wp_region(const struct region_device *rd, const enum bootdev_prot_type type) { /* return a failure, make aware WP is not implemented */ From f77eb44433c99a4b3fff5ec67300457a6a52498b Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Fri, 10 May 2019 15:38:29 +0200 Subject: [PATCH 007/331] mb/lenovo/*: Add MAINBOARD_FAMILY The Kconfig MAINBOARD_FAMILY sets the family field of SMBIOS entry 1. Match what vendor firmware does and use the same value as in the version field. Required for fwupd which uses the family field to generate a GUID. Change-Id: I0033c42c5eac6b9d47d0acd16c67467b6d419534 Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/c/coreboot/+/32727 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber Reviewed-by: Paul Menzel --- src/mainboard/lenovo/Kconfig | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/mainboard/lenovo/Kconfig b/src/mainboard/lenovo/Kconfig index a57b462529..ea1ead13e0 100644 --- a/src/mainboard/lenovo/Kconfig +++ b/src/mainboard/lenovo/Kconfig @@ -13,4 +13,8 @@ config MAINBOARD_VENDOR string default "LENOVO" +config MAINBOARD_FAMILY + string + default MAINBOARD_PART_NUMBER + endif # VENDOR_LENOVO From a029b3f4a409352c14dcb477b4291cada3275575 Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Fri, 10 May 2019 16:22:40 +0200 Subject: [PATCH 008/331] 3rdparty/libhwbase: Update to current master Beside some refactorings that don't affect coreboot, this contains bd0ed91 (Makefile: Revise support for generated sources) that fixes an issue with upcoming libgfxinit configuration changes. Change-Id: Ib47aeff8f6426ae27ddbc235a954e3bd60029072 Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/c/coreboot/+/32735 Reviewed-by: Paul Menzel Reviewed-by: Patrick Georgi Reviewed-by: Arthur Heymans Tested-by: build bot (Jenkins) --- 3rdparty/libhwbase | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/3rdparty/libhwbase b/3rdparty/libhwbase index 637f2a4f21..bd0ed91cb9 160000 --- a/3rdparty/libhwbase +++ b/3rdparty/libhwbase @@ -1 +1 @@ -Subproject commit 637f2a4f21ead8ccc45d5256834eb27ce72088db +Subproject commit bd0ed91cb985a697033edd9fd62d322aa017e791 From 47953d0ae066ad05a62e3dc5ae560e3a6796d035 Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Fri, 10 May 2019 16:26:07 +0200 Subject: [PATCH 009/331] 3rdparty/libgfxinit: Update for runtime CPU detection Beside one tiny fix for framebuffer scaling, this contains a major refactoring of libgfxinit's configuration infrastructure. With this, we are finally able to detect CPUs at runtime and only have to confi- gure a CPU/GPU generation. Change-Id: Iccf4557453878536f527e4a1902439a1961ab701 Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/c/coreboot/+/32736 Reviewed-by: Patrick Georgi Reviewed-by: Arthur Heymans Tested-by: build bot (Jenkins) --- 3rdparty/libgfxinit | 2 +- src/drivers/intel/gma/Kconfig | 19 ++++++++----------- 2 files changed, 9 insertions(+), 12 deletions(-) diff --git a/3rdparty/libgfxinit b/3rdparty/libgfxinit index f70eddafbc..b3b9fa34bb 160000 --- a/3rdparty/libgfxinit +++ b/3rdparty/libgfxinit @@ -1 +1 @@ -Subproject commit f70eddafbc2c6045a14e2f8bbb3273ee738fbaf7 +Subproject commit b3b9fa34bb99d33d0fc6a69c64966a71cebd5bd6 diff --git a/src/drivers/intel/gma/Kconfig b/src/drivers/intel/gma/Kconfig index 4f897fab13..bf7e4b65fe 100644 --- a/src/drivers/intel/gma/Kconfig +++ b/src/drivers/intel/gma/Kconfig @@ -86,22 +86,19 @@ config GFX_GMA_INTERNAL_IS_LVDS if GFX_GMA -config GFX_GMA_CPU +config GFX_GMA_DYN_CPU + def_bool y + help + Activates runtime CPU detection in libgfxinit. + +config GFX_GMA_GENERATION string default "Broxton" if SOC_INTEL_APOLLOLAKE default "Skylake" if SOC_INTEL_SKYLAKE - default "Broadwell" if SOC_INTEL_BROADWELL - default "Haswell" if NORTHBRIDGE_INTEL_HASWELL - default "Ivybridge" if NORTHBRIDGE_INTEL_IVYBRIDGE - default "Sandybridge" if NORTHBRIDGE_INTEL_SANDYBRIDGE - default "Ironlake" if NORTHBRIDGE_INTEL_NEHALEM + default "Haswell" if NORTHBRIDGE_INTEL_HASWELL || SOC_INTEL_BROADWELL + default "Ironlake" if NORTHBRIDGE_INTEL_NEHALEM || NORTHBRIDGE_INTEL_SANDYBRIDGE || NORTHBRIDGE_INTEL_IVYBRIDGE default "G45" if NORTHBRIDGE_INTEL_GM45 || NORTHBRIDGE_INTEL_X4X -config GFX_GMA_CPU_VARIANT - string - default "ULT" if (SOC_INTEL_SKYLAKE && !SKYLAKE_SOC_PCH_H) || SOC_INTEL_BROADWELL || NORTHBRIDGE_INTEL_HASWELL - default "Normal" - config GFX_GMA_INTERNAL_PORT string default "DP" if GFX_GMA_INTERNAL_IS_EDP From 772a154d39025e5f7f30102cca9f935e9b35cb1c Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Fri, 10 May 2019 16:48:14 +0200 Subject: [PATCH 010/331] nb/intel/snb: Drop NORTHBRIDGE_INTEL_IVYBRIDGE We keep the support, though. Just now that `libgfxinit` is fixed, we don't need the distinction anymore. Causally, we also don't need CPU_INTEL_MODEL_306AX any more. TEST=Played tint on kontron/ktqm77. Score 606 Change-Id: Id1e33c77f44a66baacba375cbb2aeb71effb7b76 Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/c/coreboot/+/32737 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- src/arch/x86/car.ld | 4 +--- src/cpu/intel/Makefile.inc | 1 - src/cpu/intel/model_206ax/Kconfig | 5 +---- src/drivers/intel/gma/Kconfig | 4 ++-- src/mainboard/asrock/b75pro3-m/Kconfig | 2 +- src/mainboard/asus/h61m-cs/Kconfig | 2 +- src/mainboard/asus/p8h61-m_pro/Kconfig | 2 +- src/mainboard/compulab/intense_pc/Kconfig | 2 +- src/mainboard/gigabyte/ga-b75m-d3h/Kconfig | 2 +- src/mainboard/gigabyte/ga-b75m-d3v/Kconfig | 2 +- src/mainboard/google/link/Kconfig | 2 +- src/mainboard/google/parrot/Kconfig | 2 +- src/mainboard/google/stout/Kconfig | 2 +- src/mainboard/hp/2570p/Kconfig | 2 +- src/mainboard/hp/8470p/Kconfig | 2 +- src/mainboard/hp/8770w/Kconfig | 2 +- src/mainboard/hp/folio_9470m/Kconfig | 2 +- src/mainboard/hp/revolve_810_g1/Kconfig | 2 +- src/mainboard/intel/emeraldlake2/Kconfig | 2 +- src/mainboard/kontron/ktqm77/Kconfig | 2 +- src/mainboard/lenovo/s230u/Kconfig | 2 +- src/mainboard/lenovo/t430/Kconfig | 2 +- src/mainboard/lenovo/t430s/Kconfig | 2 +- src/mainboard/lenovo/t530/Kconfig | 2 +- src/mainboard/lenovo/x1_carbon_gen1/Kconfig | 2 +- src/mainboard/lenovo/x230/Kconfig | 2 +- src/mainboard/roda/rv11/Kconfig | 2 +- src/mainboard/sapphire/pureplatinumh61/Kconfig | 2 +- src/northbridge/intel/sandybridge/Kconfig | 11 +---------- src/northbridge/intel/sandybridge/Makefile.inc | 2 +- src/southbridge/intel/common/firmware/Kconfig | 4 ++-- util/autoport/sandybridge.go | 11 +++++------ 32 files changed, 37 insertions(+), 53 deletions(-) diff --git a/src/arch/x86/car.ld b/src/arch/x86/car.ld index 7b20a14f21..29b3600bbe 100644 --- a/src/arch/x86/car.ld +++ b/src/arch/x86/car.ld @@ -91,9 +91,7 @@ _car_global_end = .; _car_relocatable_data_end = .; -#if (CONFIG(NORTHBRIDGE_INTEL_SANDYBRIDGE) || \ - CONFIG(NORTHBRIDGE_INTEL_IVYBRIDGE)) && \ - !CONFIG(USE_NATIVE_RAMINIT) +#if CONFIG(NORTHBRIDGE_INTEL_SANDYBRIDGE) && !CONFIG(USE_NATIVE_RAMINIT) . = ABSOLUTE(0xff7e1000); _mrc_pool = .; . += 0x5000; diff --git a/src/cpu/intel/Makefile.inc b/src/cpu/intel/Makefile.inc index 73a8bf8474..3f897407cf 100644 --- a/src/cpu/intel/Makefile.inc +++ b/src/cpu/intel/Makefile.inc @@ -12,7 +12,6 @@ subdirs-$(CONFIG_CPU_INTEL_SOCKET_P) += socket_p subdirs-$(CONFIG_CPU_INTEL_SOCKET_MPGA604) += socket_mPGA604 subdirs-$(CONFIG_NORTHBRIDGE_INTEL_NEHALEM) += model_2065x subdirs-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE) += model_206ax -subdirs-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE) += model_206ax subdirs-$(CONFIG_NORTHBRIDGE_INTEL_HASWELL) += haswell subdirs-$(CONFIG_NORTHBRIDGE_INTEL_FSP_RANGELEY) += fsp_model_406dx subdirs-$(CONFIG_CPU_INTEL_SLOT_1) += slot_1 diff --git a/src/cpu/intel/model_206ax/Kconfig b/src/cpu/intel/model_206ax/Kconfig index f045e9aac5..dbb8982121 100644 --- a/src/cpu/intel/model_206ax/Kconfig +++ b/src/cpu/intel/model_206ax/Kconfig @@ -1,10 +1,7 @@ config CPU_INTEL_MODEL_206AX bool -config CPU_INTEL_MODEL_306AX - bool - -if CPU_INTEL_MODEL_206AX || CPU_INTEL_MODEL_306AX +if CPU_INTEL_MODEL_206AX config CPU_SPECIFIC_OPTIONS def_bool y diff --git a/src/drivers/intel/gma/Kconfig b/src/drivers/intel/gma/Kconfig index bf7e4b65fe..59a9e8aa5b 100644 --- a/src/drivers/intel/gma/Kconfig +++ b/src/drivers/intel/gma/Kconfig @@ -67,7 +67,7 @@ config GFX_GMA def_bool y depends on NORTHBRIDGE_INTEL_GM45 || NORTHBRIDGE_INTEL_X4X \ || NORTHBRIDGE_INTEL_NEHALEM || NORTHBRIDGE_INTEL_SANDYBRIDGE \ - || NORTHBRIDGE_INTEL_IVYBRIDGE || NORTHBRIDGE_INTEL_HASWELL \ + || NORTHBRIDGE_INTEL_HASWELL \ || SOC_INTEL_BROADWELL || SOC_INTEL_SKYLAKE || SOC_INTEL_APOLLOLAKE depends on MAINBOARD_USE_LIBGFXINIT select RAMSTAGE_LIBHWBASE @@ -96,7 +96,7 @@ config GFX_GMA_GENERATION default "Broxton" if SOC_INTEL_APOLLOLAKE default "Skylake" if SOC_INTEL_SKYLAKE default "Haswell" if NORTHBRIDGE_INTEL_HASWELL || SOC_INTEL_BROADWELL - default "Ironlake" if NORTHBRIDGE_INTEL_NEHALEM || NORTHBRIDGE_INTEL_SANDYBRIDGE || NORTHBRIDGE_INTEL_IVYBRIDGE + default "Ironlake" if NORTHBRIDGE_INTEL_NEHALEM || NORTHBRIDGE_INTEL_SANDYBRIDGE default "G45" if NORTHBRIDGE_INTEL_GM45 || NORTHBRIDGE_INTEL_X4X config GFX_GMA_INTERNAL_PORT diff --git a/src/mainboard/asrock/b75pro3-m/Kconfig b/src/mainboard/asrock/b75pro3-m/Kconfig index 8db0eba763..878eaad098 100644 --- a/src/mainboard/asrock/b75pro3-m/Kconfig +++ b/src/mainboard/asrock/b75pro3-m/Kconfig @@ -22,7 +22,7 @@ config BOARD_SPECIFIC_OPTIONS select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select INTEL_INT15 - select NORTHBRIDGE_INTEL_IVYBRIDGE + select NORTHBRIDGE_INTEL_SANDYBRIDGE select SERIRQ_CONTINUOUS_MODE select SOUTHBRIDGE_INTEL_C216 select USE_NATIVE_RAMINIT diff --git a/src/mainboard/asus/h61m-cs/Kconfig b/src/mainboard/asus/h61m-cs/Kconfig index 60dafda5c7..69efa9da81 100644 --- a/src/mainboard/asus/h61m-cs/Kconfig +++ b/src/mainboard/asus/h61m-cs/Kconfig @@ -6,7 +6,7 @@ config BOARD_SPECIFIC_OPTIONS select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select INTEL_INT15 - select NORTHBRIDGE_INTEL_IVYBRIDGE + select NORTHBRIDGE_INTEL_SANDYBRIDGE select SERIRQ_CONTINUOUS_MODE select SOUTHBRIDGE_INTEL_BD82X6X select USE_NATIVE_RAMINIT diff --git a/src/mainboard/asus/p8h61-m_pro/Kconfig b/src/mainboard/asus/p8h61-m_pro/Kconfig index 93da2cdf58..14f841e649 100644 --- a/src/mainboard/asus/p8h61-m_pro/Kconfig +++ b/src/mainboard/asus/p8h61-m_pro/Kconfig @@ -21,7 +21,7 @@ config BOARD_SPECIFIC_OPTIONS select BOARD_ROMSIZE_KB_4096 select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES - select NORTHBRIDGE_INTEL_IVYBRIDGE + select NORTHBRIDGE_INTEL_SANDYBRIDGE select SERIRQ_CONTINUOUS_MODE select SOUTHBRIDGE_INTEL_BD82X6X select USE_NATIVE_RAMINIT diff --git a/src/mainboard/compulab/intense_pc/Kconfig b/src/mainboard/compulab/intense_pc/Kconfig index ff697b922f..3326b74bf6 100644 --- a/src/mainboard/compulab/intense_pc/Kconfig +++ b/src/mainboard/compulab/intense_pc/Kconfig @@ -7,7 +7,7 @@ config BOARD_SPECIFIC_OPTIONS select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select INTEL_INT15 - select NORTHBRIDGE_INTEL_IVYBRIDGE + select NORTHBRIDGE_INTEL_SANDYBRIDGE select SERIRQ_CONTINUOUS_MODE select SOUTHBRIDGE_INTEL_C216 select SYSTEM_TYPE_LAPTOP diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/Kconfig b/src/mainboard/gigabyte/ga-b75m-d3h/Kconfig index 659f47c5b0..6869bdb3f0 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/Kconfig +++ b/src/mainboard/gigabyte/ga-b75m-d3h/Kconfig @@ -3,7 +3,7 @@ if BOARD_GIGABYTE_GA_B75M_D3H config BOARD_SPECIFIC_OPTIONS def_bool y select ARCH_X86 - select NORTHBRIDGE_INTEL_IVYBRIDGE + select NORTHBRIDGE_INTEL_SANDYBRIDGE select USE_NATIVE_RAMINIT select SOUTHBRIDGE_INTEL_C216 select SUPERIO_ITE_IT8728F diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/Kconfig b/src/mainboard/gigabyte/ga-b75m-d3v/Kconfig index e01d4847ef..4048f98615 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3v/Kconfig +++ b/src/mainboard/gigabyte/ga-b75m-d3v/Kconfig @@ -3,7 +3,7 @@ if BOARD_GIGABYTE_GA_B75M_D3V config BOARD_SPECIFIC_OPTIONS def_bool y select ARCH_X86 - select NORTHBRIDGE_INTEL_IVYBRIDGE + select NORTHBRIDGE_INTEL_SANDYBRIDGE select USE_NATIVE_RAMINIT select SOUTHBRIDGE_INTEL_C216 select SUPERIO_ITE_IT8728F diff --git a/src/mainboard/google/link/Kconfig b/src/mainboard/google/link/Kconfig index fea82f6756..612a1b5987 100644 --- a/src/mainboard/google/link/Kconfig +++ b/src/mainboard/google/link/Kconfig @@ -3,7 +3,7 @@ if BOARD_GOOGLE_LINK config BOARD_SPECIFIC_OPTIONS def_bool y select SYSTEM_TYPE_LAPTOP - select NORTHBRIDGE_INTEL_IVYBRIDGE + select NORTHBRIDGE_INTEL_SANDYBRIDGE select SOUTHBRIDGE_INTEL_C216 select BOARD_ROMSIZE_KB_8192 select EC_GOOGLE_CHROMEEC diff --git a/src/mainboard/google/parrot/Kconfig b/src/mainboard/google/parrot/Kconfig index 1a31da7b55..4403d792f7 100644 --- a/src/mainboard/google/parrot/Kconfig +++ b/src/mainboard/google/parrot/Kconfig @@ -3,7 +3,7 @@ if BOARD_GOOGLE_PARROT config BOARD_SPECIFIC_OPTIONS def_bool y select SYSTEM_TYPE_LAPTOP - select NORTHBRIDGE_INTEL_IVYBRIDGE + select NORTHBRIDGE_INTEL_SANDYBRIDGE select SOUTHBRIDGE_INTEL_C216 select EC_COMPAL_ENE932 select BOARD_ROMSIZE_KB_8192 diff --git a/src/mainboard/google/stout/Kconfig b/src/mainboard/google/stout/Kconfig index 8b3eb0f030..7096d937c7 100644 --- a/src/mainboard/google/stout/Kconfig +++ b/src/mainboard/google/stout/Kconfig @@ -3,7 +3,7 @@ if BOARD_GOOGLE_STOUT config BOARD_SPECIFIC_OPTIONS def_bool y select SYSTEM_TYPE_LAPTOP - select NORTHBRIDGE_INTEL_IVYBRIDGE + select NORTHBRIDGE_INTEL_SANDYBRIDGE select SOUTHBRIDGE_INTEL_C216 select EC_QUANTA_IT8518 select BOARD_ROMSIZE_KB_8192 diff --git a/src/mainboard/hp/2570p/Kconfig b/src/mainboard/hp/2570p/Kconfig index ff91e4dafe..5e33aac2c2 100644 --- a/src/mainboard/hp/2570p/Kconfig +++ b/src/mainboard/hp/2570p/Kconfig @@ -21,7 +21,7 @@ config BOARD_SPECIFIC_OPTIONS select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select INTEL_INT15 - select NORTHBRIDGE_INTEL_IVYBRIDGE + select NORTHBRIDGE_INTEL_SANDYBRIDGE select SERIRQ_CONTINUOUS_MODE select SOUTHBRIDGE_INTEL_C216 select SYSTEM_TYPE_LAPTOP diff --git a/src/mainboard/hp/8470p/Kconfig b/src/mainboard/hp/8470p/Kconfig index f23c02faf3..5b30208b64 100644 --- a/src/mainboard/hp/8470p/Kconfig +++ b/src/mainboard/hp/8470p/Kconfig @@ -21,7 +21,7 @@ config BOARD_SPECIFIC_OPTIONS select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select INTEL_INT15 - select NORTHBRIDGE_INTEL_IVYBRIDGE + select NORTHBRIDGE_INTEL_SANDYBRIDGE select SERIRQ_CONTINUOUS_MODE select SOUTHBRIDGE_INTEL_C216 select SYSTEM_TYPE_LAPTOP diff --git a/src/mainboard/hp/8770w/Kconfig b/src/mainboard/hp/8770w/Kconfig index 6752085574..41e2ed3c6b 100644 --- a/src/mainboard/hp/8770w/Kconfig +++ b/src/mainboard/hp/8770w/Kconfig @@ -22,7 +22,7 @@ config BOARD_SPECIFIC_OPTIONS select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select INTEL_INT15 - select NORTHBRIDGE_INTEL_IVYBRIDGE + select NORTHBRIDGE_INTEL_SANDYBRIDGE select SERIRQ_CONTINUOUS_MODE select SOUTHBRIDGE_INTEL_C216 select SYSTEM_TYPE_LAPTOP diff --git a/src/mainboard/hp/folio_9470m/Kconfig b/src/mainboard/hp/folio_9470m/Kconfig index 06ca793573..d9bb68e7e1 100644 --- a/src/mainboard/hp/folio_9470m/Kconfig +++ b/src/mainboard/hp/folio_9470m/Kconfig @@ -7,7 +7,7 @@ config BOARD_SPECIFIC_OPTIONS select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select INTEL_INT15 - select NORTHBRIDGE_INTEL_IVYBRIDGE + select NORTHBRIDGE_INTEL_SANDYBRIDGE select SERIRQ_CONTINUOUS_MODE select SOUTHBRIDGE_INTEL_C216 select SYSTEM_TYPE_LAPTOP diff --git a/src/mainboard/hp/revolve_810_g1/Kconfig b/src/mainboard/hp/revolve_810_g1/Kconfig index 475e9783eb..ce7364ce5e 100644 --- a/src/mainboard/hp/revolve_810_g1/Kconfig +++ b/src/mainboard/hp/revolve_810_g1/Kconfig @@ -7,7 +7,7 @@ config BOARD_SPECIFIC_OPTIONS select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select INTEL_INT15 - select NORTHBRIDGE_INTEL_IVYBRIDGE + select NORTHBRIDGE_INTEL_SANDYBRIDGE select SERIRQ_CONTINUOUS_MODE select SOUTHBRIDGE_INTEL_C216 select SYSTEM_TYPE_LAPTOP diff --git a/src/mainboard/intel/emeraldlake2/Kconfig b/src/mainboard/intel/emeraldlake2/Kconfig index eeb441ce68..61dd1b0f3d 100644 --- a/src/mainboard/intel/emeraldlake2/Kconfig +++ b/src/mainboard/intel/emeraldlake2/Kconfig @@ -2,7 +2,7 @@ if BOARD_INTEL_EMERALDLAKE2 config BOARD_SPECIFIC_OPTIONS def_bool y - select NORTHBRIDGE_INTEL_IVYBRIDGE + select NORTHBRIDGE_INTEL_SANDYBRIDGE select SOUTHBRIDGE_INTEL_C216 select SUPERIO_SMSC_SIO1007 select BOARD_ROMSIZE_KB_8192 diff --git a/src/mainboard/kontron/ktqm77/Kconfig b/src/mainboard/kontron/ktqm77/Kconfig index 043eb019dd..c215bdf65b 100644 --- a/src/mainboard/kontron/ktqm77/Kconfig +++ b/src/mainboard/kontron/ktqm77/Kconfig @@ -2,7 +2,7 @@ if BOARD_KONTRON_KTQM77 config BOARD_SPECIFIC_OPTIONS def_bool y - select NORTHBRIDGE_INTEL_IVYBRIDGE + select NORTHBRIDGE_INTEL_SANDYBRIDGE select SOUTHBRIDGE_INTEL_C216 select SUPERIO_WINBOND_W83627DHG select EC_KONTRON_IT8516E diff --git a/src/mainboard/lenovo/s230u/Kconfig b/src/mainboard/lenovo/s230u/Kconfig index 9200ad5ed9..c7faebb429 100644 --- a/src/mainboard/lenovo/s230u/Kconfig +++ b/src/mainboard/lenovo/s230u/Kconfig @@ -3,7 +3,7 @@ if BOARD_LENOVO_S230U config BOARD_SPECIFIC_OPTIONS def_bool y select SYSTEM_TYPE_LAPTOP - select NORTHBRIDGE_INTEL_IVYBRIDGE + select NORTHBRIDGE_INTEL_SANDYBRIDGE select USE_NATIVE_RAMINIT select SOUTHBRIDGE_INTEL_C216 select EC_COMPAL_ENE932 diff --git a/src/mainboard/lenovo/t430/Kconfig b/src/mainboard/lenovo/t430/Kconfig index dbeaadb0c4..7137b5eb73 100644 --- a/src/mainboard/lenovo/t430/Kconfig +++ b/src/mainboard/lenovo/t430/Kconfig @@ -15,7 +15,7 @@ config BOARD_SPECIFIC_OPTIONS select MAINBOARD_HAS_LPC_TPM select MAINBOARD_HAS_TPM1 select INTEL_INT15 - select NORTHBRIDGE_INTEL_IVYBRIDGE + select NORTHBRIDGE_INTEL_SANDYBRIDGE select SERIRQ_CONTINUOUS_MODE select SOUTHBRIDGE_INTEL_C216 select SYSTEM_TYPE_LAPTOP diff --git a/src/mainboard/lenovo/t430s/Kconfig b/src/mainboard/lenovo/t430s/Kconfig index bad1837546..b0a22aafbf 100644 --- a/src/mainboard/lenovo/t430s/Kconfig +++ b/src/mainboard/lenovo/t430s/Kconfig @@ -3,7 +3,7 @@ if BOARD_LENOVO_T430S || BOARD_LENOVO_T431S config BOARD_SPECIFIC_OPTIONS def_bool y select SYSTEM_TYPE_LAPTOP - select NORTHBRIDGE_INTEL_IVYBRIDGE + select NORTHBRIDGE_INTEL_SANDYBRIDGE select USE_NATIVE_RAMINIT select SOUTHBRIDGE_INTEL_C216 select EC_LENOVO_PMH7 diff --git a/src/mainboard/lenovo/t530/Kconfig b/src/mainboard/lenovo/t530/Kconfig index b36460d55f..5b5b7ffa49 100644 --- a/src/mainboard/lenovo/t530/Kconfig +++ b/src/mainboard/lenovo/t530/Kconfig @@ -1,7 +1,7 @@ config BOARD_LENOVO_BASEBOARD_T530 def_bool n select SYSTEM_TYPE_LAPTOP - select NORTHBRIDGE_INTEL_IVYBRIDGE + select NORTHBRIDGE_INTEL_SANDYBRIDGE select USE_NATIVE_RAMINIT select SOUTHBRIDGE_INTEL_C216 select EC_LENOVO_PMH7 diff --git a/src/mainboard/lenovo/x1_carbon_gen1/Kconfig b/src/mainboard/lenovo/x1_carbon_gen1/Kconfig index 520853c800..a15cadf202 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/Kconfig +++ b/src/mainboard/lenovo/x1_carbon_gen1/Kconfig @@ -3,7 +3,7 @@ if BOARD_LENOVO_X1_CARBON_GEN1 config BOARD_SPECIFIC_OPTIONS def_bool y select SYSTEM_TYPE_LAPTOP - select NORTHBRIDGE_INTEL_IVYBRIDGE + select NORTHBRIDGE_INTEL_SANDYBRIDGE select USE_NATIVE_RAMINIT select SOUTHBRIDGE_INTEL_C216 select EC_LENOVO_PMH7 diff --git a/src/mainboard/lenovo/x230/Kconfig b/src/mainboard/lenovo/x230/Kconfig index 5b34b83bcd..a043efcd70 100644 --- a/src/mainboard/lenovo/x230/Kconfig +++ b/src/mainboard/lenovo/x230/Kconfig @@ -3,7 +3,7 @@ if BOARD_LENOVO_X230 config BOARD_SPECIFIC_OPTIONS def_bool y select SYSTEM_TYPE_LAPTOP - select NORTHBRIDGE_INTEL_IVYBRIDGE + select NORTHBRIDGE_INTEL_SANDYBRIDGE select USE_NATIVE_RAMINIT select SOUTHBRIDGE_INTEL_C216 select EC_LENOVO_PMH7 diff --git a/src/mainboard/roda/rv11/Kconfig b/src/mainboard/roda/rv11/Kconfig index 01fc253eac..54f04c406e 100644 --- a/src/mainboard/roda/rv11/Kconfig +++ b/src/mainboard/roda/rv11/Kconfig @@ -3,7 +3,7 @@ if BOARD_RODA_RV11 || BOARD_RODA_RW11 config BOARD_SPECIFIC_OPTIONS def_bool y select SYSTEM_TYPE_LAPTOP - select NORTHBRIDGE_INTEL_IVYBRIDGE + select NORTHBRIDGE_INTEL_SANDYBRIDGE select SOUTHBRIDGE_INTEL_C216 select BOARD_ROMSIZE_KB_16384 select HAVE_ACPI_TABLES diff --git a/src/mainboard/sapphire/pureplatinumh61/Kconfig b/src/mainboard/sapphire/pureplatinumh61/Kconfig index 13a93c5c27..6d27b3f1bd 100644 --- a/src/mainboard/sapphire/pureplatinumh61/Kconfig +++ b/src/mainboard/sapphire/pureplatinumh61/Kconfig @@ -3,7 +3,7 @@ if BOARD_SAPPHIRE_PUREPLATINUMH61 config BOARD_SPECIFIC_OPTIONS def_bool y select ARCH_X86 - select NORTHBRIDGE_INTEL_IVYBRIDGE + select NORTHBRIDGE_INTEL_SANDYBRIDGE select USE_NATIVE_RAMINIT select SOUTHBRIDGE_INTEL_BD82X6X select SUPERIO_FINTEK_F71808A diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig index b3827c0d4c..4f9da000a4 100644 --- a/src/northbridge/intel/sandybridge/Kconfig +++ b/src/northbridge/intel/sandybridge/Kconfig @@ -23,16 +23,7 @@ config NORTHBRIDGE_INTEL_SANDYBRIDGE select POSTCAR_STAGE select POSTCAR_CONSOLE -config NORTHBRIDGE_INTEL_IVYBRIDGE - bool - select CACHE_MRC_SETTINGS - select CPU_INTEL_MODEL_306AX - select HAVE_DEBUG_RAM_SETUP - select INTEL_GMA_ACPI - select POSTCAR_STAGE - select POSTCAR_CONSOLE - -if NORTHBRIDGE_INTEL_IVYBRIDGE || NORTHBRIDGE_INTEL_SANDYBRIDGE +if NORTHBRIDGE_INTEL_SANDYBRIDGE config VBOOT select VBOOT_STARTS_IN_ROMSTAGE diff --git a/src/northbridge/intel/sandybridge/Makefile.inc b/src/northbridge/intel/sandybridge/Makefile.inc index ecab18a818..cc4ddaf861 100644 --- a/src/northbridge/intel/sandybridge/Makefile.inc +++ b/src/northbridge/intel/sandybridge/Makefile.inc @@ -13,7 +13,7 @@ # GNU General Public License for more details. # -ifeq ($(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE)$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE),y) +ifeq ($(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE),y) ramstage-y += ram_calc.c ramstage-y += northbridge.c diff --git a/src/southbridge/intel/common/firmware/Kconfig b/src/southbridge/intel/common/firmware/Kconfig index c0dd43984d..eb63d34520 100644 --- a/src/southbridge/intel/common/firmware/Kconfig +++ b/src/southbridge/intel/common/firmware/Kconfig @@ -61,7 +61,7 @@ config CHECK_ME default n depends on HAVE_ME_BIN && (NORTHBRIDGE_INTEL_NEHALEM || \ NORTHBRIDGE_INTEL_SANDYBRIDGE || \ - NORTHBRIDGE_INTEL_IVYBRIDGE || NORTHBRIDGE_INTEL_HASWELL || \ + NORTHBRIDGE_INTEL_HASWELL || \ SOC_INTEL_BROADWELL || SOC_INTEL_SKYLAKE || \ SOC_INTEL_KABYLAKE || SOC_INTEL_BAYTRAIL || SOC_INTEL_BRASWELL) help @@ -73,7 +73,7 @@ config USE_ME_CLEANER bool "Strip down the Intel ME/TXE firmware" depends on HAVE_ME_BIN && (NORTHBRIDGE_INTEL_NEHALEM || \ NORTHBRIDGE_INTEL_SANDYBRIDGE || \ - NORTHBRIDGE_INTEL_IVYBRIDGE || NORTHBRIDGE_INTEL_HASWELL || \ + NORTHBRIDGE_INTEL_HASWELL || \ SOC_INTEL_BROADWELL || SOC_INTEL_SKYLAKE || \ SOC_INTEL_KABYLAKE || SOC_INTEL_BAYTRAIL || SOC_INTEL_BRASWELL) help diff --git a/util/autoport/sandybridge.go b/util/autoport/sandybridge.go index 997259815b..170d197af4 100644 --- a/util/autoport/sandybridge.go +++ b/util/autoport/sandybridge.go @@ -1,7 +1,6 @@ package main type sandybridgemc struct { - variant string } func (i sandybridgemc) Scan(ctx Context, addr PCIDevData) { @@ -106,7 +105,7 @@ func (i sandybridgemc) Scan(ctx Context, addr PCIDevData) { PutPCIDev(addr, "Host bridge") /* FIXME:XX some configs are unsupported. */ - KconfigBool["NORTHBRIDGE_INTEL_"+i.variant+"BRIDGE"] = true + KconfigBool["NORTHBRIDGE_INTEL_SANDYBRIDGE"] = true KconfigBool["USE_NATIVE_RAMINIT"] = true KconfigBool["INTEL_INT15"] = true KconfigBool["HAVE_ACPI_TABLES"] = true @@ -126,10 +125,10 @@ func (i sandybridgemc) Scan(ctx Context, addr PCIDevData) { } func init() { - RegisterPCI(0x8086, 0x0100, sandybridgemc{variant: "SANDY"}) - RegisterPCI(0x8086, 0x0104, sandybridgemc{variant: "SANDY"}) - RegisterPCI(0x8086, 0x0150, sandybridgemc{variant: "IVY"}) - RegisterPCI(0x8086, 0x0154, sandybridgemc{variant: "IVY"}) + RegisterPCI(0x8086, 0x0100, sandybridgemc{}) + RegisterPCI(0x8086, 0x0104, sandybridgemc{}) + RegisterPCI(0x8086, 0x0150, sandybridgemc{}) + RegisterPCI(0x8086, 0x0154, sandybridgemc{}) for _, id := range []uint16{ 0x0102, 0x0106, 0x010a, 0x0112, 0x0116, 0x0122, 0x0126, From a6d401c193c9bb53162df9523f9ba4ebb2a6f1a7 Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Mon, 18 Feb 2019 17:20:18 +0100 Subject: [PATCH 011/331] mb/asrock/h81m-hds: Drop now obsolete libgfxinit override CPU type is detected at runtime now. Change-Id: I5e54176e235e43ca28e4baf43dbb9860e7fc3dbd Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/c/coreboot/+/31465 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph Reviewed-by: Tristan Corrick --- src/mainboard/asrock/h81m-hds/Kconfig | 8 -------- 1 file changed, 8 deletions(-) diff --git a/src/mainboard/asrock/h81m-hds/Kconfig b/src/mainboard/asrock/h81m-hds/Kconfig index db2768d324..928a01042e 100644 --- a/src/mainboard/asrock/h81m-hds/Kconfig +++ b/src/mainboard/asrock/h81m-hds/Kconfig @@ -40,14 +40,6 @@ config CBFS_SIZE hex default 0x200000 -# -# The override of GFX_GMA_CPU_VARIANT should be removed once the patches -# for dynamic CPU detection are merged in libgfxinit. -# -config GFX_GMA_CPU_VARIANT - string - default "Normal" - config MAINBOARD_DIR string default asrock/h81m-hds From 095c931cf12924da9011b47aa64f4a6f11d89f13 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Mon, 6 May 2019 19:51:34 +0530 Subject: [PATCH 012/331] src/arch/x86: Use core apic id to get cpu_index() This cpu_index() implementation assumes that cpu_index() function might always getting called from coreboot context (ESP stack pointer will always refer to coreboot). This might not be true in case of proposed PI spec MP_SERVICES_PPI implementation, where FSP context (stack pointer refers to fsp) will request to get cpu_index(), natural alignment logic will use ESP and retrieve struct cpu_info *ci from (stack_top - 8 byte). This is not the place where cpu_index is actually stored by ramstage c_start.S Hence this patch tries to remove those dependencies while retrieving cpu_index(), rather it uses cpuid to fetch lapic id and matches with cpus_default_apic_id[] variable to return correct cpu_index(). BRANCH=none BUG=b:79562868 TEST=Ensures functions can be run on APs without any failure and cpu_index() also provides correct index number. Change-Id: I55023a3e0cf42f0496d45bc6af8ead447f402350 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/26346 Reviewed-by: Nico Huber Tested-by: build bot (Jenkins) --- src/arch/x86/cpu.c | 24 ++++++++++++++++++++++++ src/arch/x86/include/arch/cpu.h | 21 ++++++++++++++------- 2 files changed, 38 insertions(+), 7 deletions(-) diff --git a/src/arch/x86/cpu.c b/src/arch/x86/cpu.c index f19b389441..fb4c7b6cfe 100644 --- a/src/arch/x86/cpu.c +++ b/src/arch/x86/cpu.c @@ -337,3 +337,27 @@ void arch_bootstate_coreboot_exit(void) /* APs are waiting for work. Last thing to do is park them. */ mp_park_aps(); } + +/* + * Previously cpu_index() implementation assumes that cpu_index() + * function will always getting called from coreboot context + * (ESP stack pointer will always refer to coreboot). + * + * But with FSP_USES_MP_SERVICES_PPI implementation in coreboot this + * assumption might not be true, where FSP context (stack pointer refers + * to FSP) will request to get cpu_index(). + * + * Hence new logic to use cpuid to fetch lapic id and matches with + * cpus_default_apic_id[] variable to return correct cpu_index(). + */ +unsigned long cpu_index(void) +{ + int i; + int lapic_id = initial_lapicid(); + + for (i = 0; i < CONFIG_MAX_CPUS; i++) { + if (cpu_get_apic_id(i) == lapic_id) + return i; + } + return -1; +} diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h index 61b17a6d2a..481ee9d8e0 100644 --- a/src/arch/x86/include/arch/cpu.h +++ b/src/arch/x86/include/arch/cpu.h @@ -261,13 +261,6 @@ static inline struct cpu_info *cpu_info(void) ); return ci; } - -static inline unsigned long cpu_index(void) -{ - struct cpu_info *ci; - ci = cpu_info(); - return ci->index; -} #endif #ifndef __ROMCC__ // romcc is segfaulting in some cases @@ -374,4 +367,18 @@ uint32_t cpu_get_feature_flags_ecx(void); */ uint32_t cpu_get_feature_flags_edx(void); +/* + * Previously cpu_index() implementation assumes that cpu_index() + * function will always getting called from coreboot context + * (ESP stack pointer will always refer to coreboot). + * + * But with FSP_USES_MP_SERVICES_PPI implementation in coreboot this + * assumption might not be true, where FSP context (stack pointer refers + * to FSP) will request to get cpu_index(). + * + * Hence new logic to use cpuid to fetch lapic id and matches with + * cpus_default_apic_id[] variable to return correct cpu_index(). + */ +unsigned long cpu_index(void); + #endif /* ARCH_CPU_H */ From e091d0efc40581ce789fdef5f44a327b75adc999 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Fri, 10 May 2019 12:35:42 +0530 Subject: [PATCH 013/331] lapic/lapic_cpu_init: Add cpu_add_map_entry() to store default_apic_id This patch ensures start_cpu() function to store default_apic_id using common cpu_add_map_entry() function to make cpu_index() implementation generic. BRANCH=none BUG=b:79562868 Change-Id: Iac4d6e9e6e6f9ba644335b4b70da8689c405f638 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/32722 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/cpu/x86/lapic/lapic_cpu_init.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/cpu/x86/lapic/lapic_cpu_init.c b/src/cpu/x86/lapic/lapic_cpu_init.c index 3ad1f0a055..0f73e71331 100644 --- a/src/cpu/x86/lapic/lapic_cpu_init.c +++ b/src/cpu/x86/lapic/lapic_cpu_init.c @@ -291,6 +291,7 @@ int start_cpu(struct device *cpu) info = (struct cpu_info *)stack_top; info->index = index; info->cpu = cpu; + cpu_add_map_entry(info->index); thread_init_cpu_info_non_bsp(info); /* Advertise the new stack and index to start_cpu */ @@ -549,6 +550,7 @@ void initialize_cpus(struct bus *cpu_bus) /* Find the device structure for the boot CPU */ info->cpu = alloc_find_dev(cpu_bus, &cpu_path); + cpu_add_map_entry(info->index); // why here? In case some day we can start core1 in amd_sibling_init if (is_smp_boot()) From 9bb0461fbd8cdcceabde0ec266a5207bc40ea9a7 Mon Sep 17 00:00:00 2001 From: Jacob Garber Date: Wed, 8 May 2019 13:40:45 -0600 Subject: [PATCH 014/331] util/ifdtool: Add find_fd null check As the previous comment indicated, this null check is currently superfluous, but adding it in makes Coverity happy, and future-proofs the code in case someone changes the internals of 'find_fcba' later and forgets/doesn't know to update this error check. Found-by: Coverity Scan #1395066 Signed-off-by: Jacob Garber Change-Id: I594cd0098f5b36cef5b3efc4c904710d3ba9b815 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32691 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph --- util/ifdtool/ifdtool.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c index a97f352bdf..6c5e784569 100644 --- a/util/ifdtool/ifdtool.c +++ b/util/ifdtool/ifdtool.c @@ -236,7 +236,7 @@ static int get_ifd_version_from_fcba(char *image, int size) int read_freq; const fcba_t *fcba = find_fcba(image, size); const fdbar_t *fdb = find_fd(image, size); - if (!fcba) /* a valid fcba indicates a valid fdb */ + if (!fcba || !fdb) exit(EXIT_FAILURE); chipset = guess_ich_chipset(fdb); From 2be617b58b500214d45c338eda88237730524cac Mon Sep 17 00:00:00 2001 From: Jacob Garber Date: Tue, 7 May 2019 19:49:37 -0600 Subject: [PATCH 015/331] util/intelvbttool: Free file object on error path Prevents a memory leak. Found-by: Coverity Scan #1396047 Signed-off-by: Jacob Garber Change-Id: I4c72a17351d8afbe23302edfeeba74b17608aef2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32685 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph --- util/intelvbttool/intelvbttool.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/util/intelvbttool/intelvbttool.c b/util/intelvbttool/intelvbttool.c index f8e4bda0f4..715b39ad57 100644 --- a/util/intelvbttool/intelvbttool.c +++ b/util/intelvbttool/intelvbttool.c @@ -1028,8 +1028,10 @@ static int patch_vbios(struct fileobject *fo, if (old_vbt) { if (oh->vbt_offset + vbt_size(old_vbt) == fo->size) { /* Located at the end of file - reduce file size */ - if (fo->size < vbt_size(old_vbt)) + if (fo->size < vbt_size(old_vbt)) { + free_fo(old_vbt); return 1; + } fo = remalloc_fo(fo, fo->size - vbt_size(old_vbt)); if (!fo) { printerr("Failed to allocate memory\n"); From 4fbd22e38d42faf7654cf9ded1f4001652e7fd37 Mon Sep 17 00:00:00 2001 From: Jacob Garber Date: Wed, 8 May 2019 16:28:27 -0600 Subject: [PATCH 016/331] util/intelvbttool: Add error checking for memory allocation It is possible that 'malloc_fo_sub' and 'remalloc_fo' can fail, so add appropriate error checks for those cases. This incidentally fixes a possible memory leak when 'malloc_fo_sub' succeeds but 'remalloc_fo' does not. Found-by: Coverity Scan #1396050 Signed-off-by: Jacob Garber Change-Id: I944b67f5cdcfd7a687e81d8bb01a209c9dc9b0b8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32696 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph --- util/intelvbttool/intelvbttool.c | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/util/intelvbttool/intelvbttool.c b/util/intelvbttool/intelvbttool.c index 715b39ad57..2dfa0023f2 100644 --- a/util/intelvbttool/intelvbttool.c +++ b/util/intelvbttool/intelvbttool.c @@ -788,7 +788,20 @@ static void parse_vbt(const struct fileobject *fo, } /* Duplicate fo as caller is owner and remalloc frees the object */ - *vbt = remalloc_fo(malloc_fo_sub(fo, 0), head->vbt_size); + struct fileobject *dupfo = malloc_fo_sub(fo, 0); + if (!dupfo) { + printerr("malloc failed\n"); + return; + } + + struct fileobject *newfo = remalloc_fo(dupfo, head->vbt_size); + if (!newfo) { + printerr("remalloc failed\n"); + free_fo(dupfo); + return; + } + + *vbt = newfo; } /* Option ROM checksum */ From 9c90609331b33292c7aeacc944cd97fe5a2da056 Mon Sep 17 00:00:00 2001 From: Frans Hendriks Date: Fri, 10 May 2019 15:00:46 +0200 Subject: [PATCH 017/331] soc/intel/braswell: Add tsc_freq.c and pmutil.c in verstage Systems with C_EVIRONMENT_BOOTBLOCK and VBOOT enabled requires functions tsc_freq_mhz(), vbnv_cmos_failed() and vboot_platform_is_resuming() in verstage. Add tsc_freq.c and pmutil.c to verstage. BUG=NA TEST=Booting Embedded Linux on Facebook FBG-1701 + Building Google Banon Change-Id: Ia509eda6bf415aaa63be71013249493aa472289d Signed-off-by: Frans Hendriks Reviewed-on: https://review.coreboot.org/c/coreboot/+/32733 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph --- src/soc/intel/braswell/Makefile.inc | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/soc/intel/braswell/Makefile.inc b/src/soc/intel/braswell/Makefile.inc index 4e90edf15c..e2b1fe5295 100644 --- a/src/soc/intel/braswell/Makefile.inc +++ b/src/soc/intel/braswell/Makefile.inc @@ -53,6 +53,9 @@ smm-y += smihandler.c smm-y += spi.c smm-y += tsc_freq.c +verstage-y += pmutil.c +verstage-y += tsc_freq.c + CPPFLAGS_common += -I$(src)/soc/intel/braswell/ CPPFLAGS_common += -I$(src)/soc/intel/braswell/include CPPFLAGS_common += -I$(call strip_quotes,$(CONFIG_FSP_HEADER_PATH)) From 9d6f6459080e6ca1f82fabd7e05ada506c58204d Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Thu, 9 May 2019 21:04:52 +0200 Subject: [PATCH 018/331] mainboard: Remove unused include Change-Id: Id05fc39c0c0d0560e34e55f793060d29df82d026 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/32676 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks Reviewed-by: Sumeet R Pawnikar --- src/mainboard/google/cheza/mainboard.c | 1 - src/mainboard/google/mistral/bootblock.c | 1 - src/mainboard/google/mistral/mainboard.c | 1 - 3 files changed, 3 deletions(-) diff --git a/src/mainboard/google/cheza/mainboard.c b/src/mainboard/google/cheza/mainboard.c index 42adf56c79..7a19d32e9c 100644 --- a/src/mainboard/google/cheza/mainboard.c +++ b/src/mainboard/google/cheza/mainboard.c @@ -16,7 +16,6 @@ #include #include #include -#include #include static struct usb_board_data usb1_board_data = { diff --git a/src/mainboard/google/mistral/bootblock.c b/src/mainboard/google/mistral/bootblock.c index 6718d52156..4ef8fec6c3 100644 --- a/src/mainboard/google/mistral/bootblock.c +++ b/src/mainboard/google/mistral/bootblock.c @@ -14,7 +14,6 @@ */ #include -#include void bootblock_mainboard_init(void) { diff --git a/src/mainboard/google/mistral/mainboard.c b/src/mainboard/google/mistral/mainboard.c index 1d62adba5c..d50758c9e3 100644 --- a/src/mainboard/google/mistral/mainboard.c +++ b/src/mainboard/google/mistral/mainboard.c @@ -15,7 +15,6 @@ #include #include -#include #include #include From cb6f6a10b3223dce446a1ce8e01cba0357b55b91 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Thu, 9 May 2019 21:06:19 +0200 Subject: [PATCH 019/331] soc/intel/braswell: Remove unused include Change-Id: Ied645a583f78bc47c8358240acd639132fd499db Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/32711 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks Reviewed-by: Sumeet R Pawnikar --- src/soc/intel/braswell/romstage/romstage.c | 1 - 1 file changed, 1 deletion(-) diff --git a/src/soc/intel/braswell/romstage/romstage.c b/src/soc/intel/braswell/romstage/romstage.c index 342b05cf50..22b0df2a8b 100644 --- a/src/soc/intel/braswell/romstage/romstage.c +++ b/src/soc/intel/braswell/romstage/romstage.c @@ -29,7 +29,6 @@ #include #include #include -#include #include #include #include From 554e55b0f07e7913afad6b374e30661df9db617a Mon Sep 17 00:00:00 2001 From: Jacob Garber Date: Wed, 8 May 2019 09:32:00 -0600 Subject: [PATCH 020/331] util/kconfig: Use snprintf to avoid buffer overflow 'name' and 'env' are supposed to be file system paths, but could overflow the buffer if configured incorrectly. Let's avoid that entirely. Found-by: Coverity Scan #1362515 Signed-off-by: Jacob Garber Change-Id: I1aef36819d49ebcbde1c51995dc0961c85e74150 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32686 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- util/kconfig/zconf.l | 3 ++- util/kconfig/zconf.lex.c_shipped | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/util/kconfig/zconf.l b/util/kconfig/zconf.l index 0b45c19db9..f2636d2955 100644 --- a/util/kconfig/zconf.l +++ b/util/kconfig/zconf.l @@ -273,7 +273,8 @@ FILE *zconf_fopen(const char *name) if (!f && name != NULL && name[0] != '/') { env = getenv(SRCTREE); if (env) { - sprintf(fullname, "%s/%s", env, name); + snprintf(fullname, sizeof(fullname), + "%s/%s", env, name); f = fopen(fullname, "r"); } } diff --git a/util/kconfig/zconf.lex.c_shipped b/util/kconfig/zconf.lex.c_shipped index 72e3a5fca2..4133f71dd2 100644 --- a/util/kconfig/zconf.lex.c_shipped +++ b/util/kconfig/zconf.lex.c_shipped @@ -2351,7 +2351,8 @@ FILE *zconf_fopen(const char *name) if (!f && name != NULL && name[0] != '/') { env = getenv(SRCTREE); if (env) { - sprintf(fullname, "%s/%s", env, name); + snprintf(fullname, sizeof(fullname), + "%s/%s", env, name); f = fopen(fullname, "r"); } } From ac6bf7dc1259ae09dfbd123dc6dee1400b26c801 Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Fri, 10 May 2019 19:17:31 +0200 Subject: [PATCH 021/331] lib/hexdump: Drop redundant isprint() implementation Change-Id: I23e2d89274553cbc75e42f0420a1a84d4cec4340 Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/c/coreboot/+/32739 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner --- src/lib/hexdump.c | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/src/lib/hexdump.c b/src/lib/hexdump.c index 2861d6321e..ca36ddee0e 100644 --- a/src/lib/hexdump.c +++ b/src/lib/hexdump.c @@ -14,11 +14,7 @@ #include #include - -static int isprint(int c) -{ - return (c >= 32 && c <= 126); -} +#include void hexdump(const void *memory, size_t length) { From f2d173a554b82b731fceeecd00095f6c6433c7ba Mon Sep 17 00:00:00 2001 From: Jett Rink Date: Fri, 10 May 2019 09:12:02 -0600 Subject: [PATCH 022/331] mb/google/sarien: config ISH_GP6 with NF2 A12 is not current set for ISH_GP6 so the ISH_LID_CL#_TAB signal is not making it to the ISH properly. Enable the second native function instead of the first. BRANCH=none BUG=b:131785573 TEST=gpioget on ISH now shows the correct gpio level Change-Id: Ib3a654ae659037263aa9aa29d45b42ca67b7955b Signed-off-by: Jett Rink Reviewed-on: https://review.coreboot.org/c/coreboot/+/32738 Reviewed-by: Duncan Laurie Reviewed-by: Furquan Shaikh Tested-by: build bot (Jenkins) --- src/mainboard/google/sarien/variants/arcada/gpio.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/google/sarien/variants/arcada/gpio.c b/src/mainboard/google/sarien/variants/arcada/gpio.c index da95497657..ea0601b55e 100644 --- a/src/mainboard/google/sarien/variants/arcada/gpio.c +++ b/src/mainboard/google/sarien/variants/arcada/gpio.c @@ -31,7 +31,7 @@ static const struct pad_config gpio_table[] = { /* CLKOUT_LPC1 */ PAD_NC(GPP_A10, NONE), /* PME# */ PAD_NC(GPP_A11, NONE), /* ISH_LID_CL#_TAB */ -/* BM_BUSY# */ PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1), +/* ISH_GP6 */ PAD_CFG_NF(GPP_A12, NONE, DEEP, NF2), /* SUSWARN# */ PAD_NC(GPP_A13, NONE), /* ESPI_RESET# */ /* SUSACK# */ PAD_NC(GPP_A15, NONE), From a20e59da157231f0a0e41774af80f6bccde1b280 Mon Sep 17 00:00:00 2001 From: Matt Delco Date: Mon, 22 Apr 2019 13:38:13 -0700 Subject: [PATCH 023/331] libpayload: classify all keyboards Depthcharge uses the keyboard type to help determine whether it can trust the keyboard for security-sensitive confirmations. Currently it trusts anything except usb, but now there's a need to distrust ec-based ps/2 keyboards that are associated with untrusted ECs. To help facilitate this, coreboot needs to report more details about non-usb keyboards, so this change replaces the current instances of unknown with enum values that distinguish uart and gpio from ec-based keyboards. BUG=b:129471321 BRANCH=None TEST=Local compile and flash to systems with trusted and non-trusted ECs. Confirmed that security confirmation can't be performed via keyboard on a system with an untrusted EC but can still be performed on a system with a trusted EC. Change-Id: Iee6295dafadf7cb3da98b62f43b0e184b2b69b1e Signed-off-by: Matt Delco Reviewed-on: https://review.coreboot.org/c/coreboot/+/32717 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner --- payloads/libpayload/drivers/i8042/keyboard.c | 3 ++- payloads/libpayload/drivers/serial/8250.c | 3 ++- payloads/libpayload/drivers/serial/ipq40xx.c | 1 + payloads/libpayload/drivers/serial/ipq806x.c | 1 + payloads/libpayload/drivers/serial/s5p.c | 3 ++- payloads/libpayload/include/libpayload.h | 3 +++ 6 files changed, 11 insertions(+), 3 deletions(-) diff --git a/payloads/libpayload/drivers/i8042/keyboard.c b/payloads/libpayload/drivers/i8042/keyboard.c index 1035bf2791..42431c3689 100644 --- a/payloads/libpayload/drivers/i8042/keyboard.c +++ b/payloads/libpayload/drivers/i8042/keyboard.c @@ -296,7 +296,8 @@ int keyboard_set_layout(char *country) static struct console_input_driver cons = { .havekey = keyboard_havechar, - .getchar = keyboard_getchar + .getchar = keyboard_getchar, + .input_type = CONSOLE_INPUT_TYPE_EC, }; void keyboard_init(void) diff --git a/payloads/libpayload/drivers/serial/8250.c b/payloads/libpayload/drivers/serial/8250.c index f503bdb124..9502d4b147 100644 --- a/payloads/libpayload/drivers/serial/8250.c +++ b/payloads/libpayload/drivers/serial/8250.c @@ -98,7 +98,8 @@ static void serial_hardware_init(int speed, int word_bits, static struct console_input_driver consin = { .havekey = &serial_havechar, - .getchar = &serial_getchar + .getchar = &serial_getchar, + .input_type = CONSOLE_INPUT_TYPE_UART, }; static struct console_output_driver consout = { diff --git a/payloads/libpayload/drivers/serial/ipq40xx.c b/payloads/libpayload/drivers/serial/ipq40xx.c index 52d71b8ac8..7656ad73e0 100644 --- a/payloads/libpayload/drivers/serial/ipq40xx.c +++ b/payloads/libpayload/drivers/serial/ipq40xx.c @@ -560,6 +560,7 @@ void serial_console_init(void) consin.havekey = serial_havechar; consin.getchar = serial_getchar; + consin.input_type = CONSOLE_INPUT_TYPE_UART; consout.putchar = serial_putchar; diff --git a/payloads/libpayload/drivers/serial/ipq806x.c b/payloads/libpayload/drivers/serial/ipq806x.c index 912893d7e2..183ada6563 100644 --- a/payloads/libpayload/drivers/serial/ipq806x.c +++ b/payloads/libpayload/drivers/serial/ipq806x.c @@ -352,6 +352,7 @@ void serial_console_init(void) consin.havekey = serial_havechar; consin.getchar = serial_getchar; + consin.input_type = CONSOLE_INPUT_TYPE_UART; consout.putchar = serial_putchar; diff --git a/payloads/libpayload/drivers/serial/s5p.c b/payloads/libpayload/drivers/serial/s5p.c index 1d23352ec4..6ca5dc4717 100644 --- a/payloads/libpayload/drivers/serial/s5p.c +++ b/payloads/libpayload/drivers/serial/s5p.c @@ -84,7 +84,8 @@ static struct console_output_driver s5p_serial_output = static struct console_input_driver s5p_serial_input = { .havekey = &serial_havechar, - .getchar = &serial_getchar + .getchar = &serial_getchar, + .input_type = CONSOLE_INPUT_TYPE_UART, }; void serial_init(void) diff --git a/payloads/libpayload/include/libpayload.h b/payloads/libpayload/include/libpayload.h index 3a84b3b038..a578d41f28 100644 --- a/payloads/libpayload/include/libpayload.h +++ b/payloads/libpayload/include/libpayload.h @@ -350,6 +350,9 @@ int set_option_from_string(const struct nvram_accessor *nvram, struct cb_cmos_op typedef enum { CONSOLE_INPUT_TYPE_UNKNOWN = 0, CONSOLE_INPUT_TYPE_USB, + CONSOLE_INPUT_TYPE_EC, + CONSOLE_INPUT_TYPE_UART, + CONSOLE_INPUT_TYPE_GPIO, } console_input_type; void console_init(void); From 2cb399625ea04027fd02e6be834738b62d10c7d9 Mon Sep 17 00:00:00 2001 From: Matt Delco Date: Tue, 30 Apr 2019 14:59:43 -0700 Subject: [PATCH 024/331] mainboard: remove "recovery" gpio, selectively add "presence" gpio. The gpio table is only used by depthcharge, and depthcharge rarely has a need for the "recovery" gpio. On a few boards it does use the gpio as a signal for confirming physical presence, so on that boards we'll advertise the board as "presence". All these strings probably should have been #defines to help avoid typos (e.g., the "ec_in_rw" in stout seems questionable since everybody else uses "EC in RW"). Cq-Depend: chromium:1580454 BUG=b:129471321 BRANCH=None TEST=Local compile and flash (with corresponding changes to depthcharge) to 2 systems, one with a "presence" gpio and another without. Confirmed that both systems could enter dev mode. Change-Id: Id6d62d9e48d3e6646cbc1277ea53f0ca95dd849e Signed-off-by: Matt Delco Reviewed-on: https://review.coreboot.org/c/coreboot/+/32718 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie Reviewed-by: Julius Werner --- src/mainboard/google/auron/chromeos.c | 1 - src/mainboard/google/beltino/chromeos.c | 2 +- src/mainboard/google/butterfly/chromeos.c | 3 --- src/mainboard/google/cyan/chromeos.c | 1 - src/mainboard/google/daisy/chromeos.c | 3 --- src/mainboard/google/dragonegg/chromeos.c | 1 - src/mainboard/google/eve/chromeos.c | 1 - src/mainboard/google/fizz/chromeos.c | 1 - src/mainboard/google/foster/chromeos.c | 3 --- src/mainboard/google/gale/chromeos.c | 2 -- src/mainboard/google/glados/chromeos.c | 1 - src/mainboard/google/gru/chromeos.c | 1 - src/mainboard/google/hatch/chromeos.c | 1 - src/mainboard/google/jecht/chromeos.c | 2 +- src/mainboard/google/kahlee/chromeos.c | 1 - src/mainboard/google/kukui/chromeos.c | 1 - src/mainboard/google/link/chromeos.c | 4 ---- src/mainboard/google/nyan/chromeos.c | 1 - src/mainboard/google/nyan_big/chromeos.c | 1 - src/mainboard/google/nyan_blaze/chromeos.c | 1 - src/mainboard/google/oak/chromeos.c | 1 - src/mainboard/google/octopus/chromeos.c | 1 - src/mainboard/google/parrot/chromeos.c | 3 --- src/mainboard/google/peach_pit/chromeos.c | 3 --- src/mainboard/google/poppy/chromeos.c | 1 - src/mainboard/google/rambi/chromeos.c | 1 - src/mainboard/google/reef/chromeos.c | 1 - src/mainboard/google/sarien/chromeos.c | 2 -- src/mainboard/google/slippy/chromeos.c | 1 - src/mainboard/google/smaug/chromeos.c | 1 - src/mainboard/google/storm/chromeos.c | 2 +- src/mainboard/google/stout/chromeos.c | 3 --- src/mainboard/google/veyron/chromeos.c | 2 +- src/mainboard/google/veyron_mickey/chromeos.c | 2 +- src/mainboard/google/veyron_rialto/chromeos.c | 2 +- src/mainboard/intel/baskingridge/chromeos.c | 2 +- src/mainboard/intel/cannonlake_rvp/chromeos.c | 1 - src/mainboard/intel/coffeelake_rvp/chromeos.c | 1 - src/mainboard/intel/emeraldlake2/chromeos.c | 2 +- src/mainboard/intel/glkrvp/chromeos.c | 1 - src/mainboard/intel/icelake_rvp/chromeos.c | 1 - src/mainboard/intel/kblrvp/chromeos.c | 1 - src/mainboard/intel/kunimitsu/chromeos.c | 1 - src/mainboard/intel/strago/chromeos.c | 1 - src/mainboard/intel/wtm2/chromeos.c | 1 - src/mainboard/samsung/lumpy/chromeos.c | 2 +- src/mainboard/samsung/stumpy/chromeos.c | 2 +- 47 files changed, 10 insertions(+), 64 deletions(-) diff --git a/src/mainboard/google/auron/chromeos.c b/src/mainboard/google/auron/chromeos.c index 942e9dd8db..0147a317fe 100644 --- a/src/mainboard/google/auron/chromeos.c +++ b/src/mainboard/google/auron/chromeos.c @@ -27,7 +27,6 @@ void fill_lb_gpios(struct lb_gpios *gpios) struct lb_gpio chromeos_gpios[] = { {CROS_WP_GPIO, ACTIVE_HIGH, get_write_protect_state(), "write protect"}, - {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"}, {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, {-1, ACTIVE_HIGH, 0, "power"}, {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, diff --git a/src/mainboard/google/beltino/chromeos.c b/src/mainboard/google/beltino/chromeos.c index 92bb7b445a..e695ab5f08 100644 --- a/src/mainboard/google/beltino/chromeos.c +++ b/src/mainboard/google/beltino/chromeos.c @@ -36,7 +36,7 @@ void fill_lb_gpios(struct lb_gpios *gpios) {GPIO_SPI_WP, ACTIVE_HIGH, get_write_protect_state(), "write protect"}, {GPIO_REC_MODE, ACTIVE_LOW, - !get_recovery_mode_switch(), "recovery"}, + !get_recovery_mode_switch(), "presence"}, {-1, ACTIVE_HIGH, 1, "lid"}, {-1, ACTIVE_HIGH, 0, "power"}, {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, diff --git a/src/mainboard/google/butterfly/chromeos.c b/src/mainboard/google/butterfly/chromeos.c index 2301d3eec4..7f72ad24bf 100644 --- a/src/mainboard/google/butterfly/chromeos.c +++ b/src/mainboard/google/butterfly/chromeos.c @@ -40,9 +40,6 @@ void fill_lb_gpios(struct lb_gpios *gpios) {WP_GPIO, ACTIVE_LOW, !get_write_protect_state(), "write protect"}, - /* Recovery: virtual GPIO active high */ - {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"}, - /* lid switch value from EC */ {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, diff --git a/src/mainboard/google/cyan/chromeos.c b/src/mainboard/google/cyan/chromeos.c index 44101e347c..5d5bc556e5 100644 --- a/src/mainboard/google/cyan/chromeos.c +++ b/src/mainboard/google/cyan/chromeos.c @@ -35,7 +35,6 @@ void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { {-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"}, - {-1, ACTIVE_HIGH, vboot_recovery_mode_enabled(), "recovery"}, {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, {-1, ACTIVE_HIGH, 0, "power"}, {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, diff --git a/src/mainboard/google/daisy/chromeos.c b/src/mainboard/google/daisy/chromeos.c index 968f1f9d5b..974cd49f25 100644 --- a/src/mainboard/google/daisy/chromeos.c +++ b/src/mainboard/google/daisy/chromeos.c @@ -29,9 +29,6 @@ void fill_lb_gpios(struct lb_gpios *gpios) {EXYNOS5_GPD1, ACTIVE_LOW, !get_write_protect_state(), "write protect"}, - /* Recovery: active low */ - {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"}, - /* Lid: active high (LID_GPIO) */ {EXYNOS5_GPX3, ACTIVE_HIGH, gpio_get_value(GPIO_X35), "lid"}, diff --git a/src/mainboard/google/dragonegg/chromeos.c b/src/mainboard/google/dragonegg/chromeos.c index 657320cba3..7132b04698 100644 --- a/src/mainboard/google/dragonegg/chromeos.c +++ b/src/mainboard/google/dragonegg/chromeos.c @@ -28,7 +28,6 @@ void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { {-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"}, - {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"}, {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, {-1, ACTIVE_HIGH, 0, "power"}, {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, diff --git a/src/mainboard/google/eve/chromeos.c b/src/mainboard/google/eve/chromeos.c index 06a4de9d35..8c276e9ae1 100644 --- a/src/mainboard/google/eve/chromeos.c +++ b/src/mainboard/google/eve/chromeos.c @@ -27,7 +27,6 @@ void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { {-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"}, - {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"}, {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, {-1, ACTIVE_HIGH, 0, "power"}, {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, diff --git a/src/mainboard/google/fizz/chromeos.c b/src/mainboard/google/fizz/chromeos.c index 3bd5b641c0..31887c59fb 100644 --- a/src/mainboard/google/fizz/chromeos.c +++ b/src/mainboard/google/fizz/chromeos.c @@ -27,7 +27,6 @@ void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { {-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"}, - {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"}, {-1, ACTIVE_HIGH, 1, "lid"}, /* Lid switch always open */ {-1, ACTIVE_HIGH, 0, "power"}, {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, diff --git a/src/mainboard/google/foster/chromeos.c b/src/mainboard/google/foster/chromeos.c index 591cfd0025..7ce1300509 100644 --- a/src/mainboard/google/foster/chromeos.c +++ b/src/mainboard/google/foster/chromeos.c @@ -28,9 +28,6 @@ void fill_lb_gpios(struct lb_gpios *gpios) /* Write Protect: active low */ {-1, ACTIVE_LOW, !get_write_protect_state(), "write protect"}, - /* Recovery: active high */ - {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"}, - /* TODO: Power: active low / high depending on board id */ {GPIO(X5), ACTIVE_LOW, -1, "power"}, diff --git a/src/mainboard/google/gale/chromeos.c b/src/mainboard/google/gale/chromeos.c index 69c3a7a3c7..d0bdbb0940 100644 --- a/src/mainboard/google/gale/chromeos.c +++ b/src/mainboard/google/gale/chromeos.c @@ -68,8 +68,6 @@ void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { {PP_SW, ACTIVE_LOW, read_gpio(PP_SW), "presence"}, - {get_rec_sw_gpio_pin(), ACTIVE_LOW, - read_gpio(get_rec_sw_gpio_pin()), "recovery"}, {get_wp_status_gpio_pin(), ACTIVE_LOW, !get_write_protect_state(), "write protect"}, {-1, ACTIVE_LOW, 1, "power"}, diff --git a/src/mainboard/google/glados/chromeos.c b/src/mainboard/google/glados/chromeos.c index f826b55ea8..b6029dd0f9 100644 --- a/src/mainboard/google/glados/chromeos.c +++ b/src/mainboard/google/glados/chromeos.c @@ -26,7 +26,6 @@ void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { {-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"}, - {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"}, {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, {-1, ACTIVE_HIGH, 0, "power"}, {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, diff --git a/src/mainboard/google/gru/chromeos.c b/src/mainboard/google/gru/chromeos.c index 53d00fb188..c92a492310 100644 --- a/src/mainboard/google/gru/chromeos.c +++ b/src/mainboard/google/gru/chromeos.c @@ -34,7 +34,6 @@ void fill_lb_gpios(struct lb_gpios *gpios) struct lb_gpio chromeos_gpios[] = { {GPIO_WP.raw, wp_polarity, get_write_protect_state() ^ !wp_polarity, "write protect"}, - {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"}, #if CONFIG(GRU_BASEBOARD_SCARLET) {GPIO_BACKLIGHT.raw, ACTIVE_HIGH, -1, "backlight"}, #endif diff --git a/src/mainboard/google/hatch/chromeos.c b/src/mainboard/google/hatch/chromeos.c index fa54148ee8..4119670ef4 100644 --- a/src/mainboard/google/hatch/chromeos.c +++ b/src/mainboard/google/hatch/chromeos.c @@ -25,7 +25,6 @@ void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { {-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"}, - {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"}, {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, {-1, ACTIVE_HIGH, 0, "power"}, {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, diff --git a/src/mainboard/google/jecht/chromeos.c b/src/mainboard/google/jecht/chromeos.c index b3215a0ec6..2b72cae036 100644 --- a/src/mainboard/google/jecht/chromeos.c +++ b/src/mainboard/google/jecht/chromeos.c @@ -37,7 +37,7 @@ void fill_lb_gpios(struct lb_gpios *gpios) {GPIO_SPI_WP, ACTIVE_HIGH, get_write_protect_state(), "write protect"}, {GPIO_REC_MODE, ACTIVE_LOW, - !get_recovery_mode_switch(), "recovery"}, + !get_recovery_mode_switch(), "presence"}, {-1, ACTIVE_HIGH, 1, "lid"}, {-1, ACTIVE_HIGH, 0, "power"}, {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, diff --git a/src/mainboard/google/kahlee/chromeos.c b/src/mainboard/google/kahlee/chromeos.c index 3bce66bbd6..195eb94378 100644 --- a/src/mainboard/google/kahlee/chromeos.c +++ b/src/mainboard/google/kahlee/chromeos.c @@ -24,7 +24,6 @@ void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { {-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"}, - {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"}, {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, {-1, ACTIVE_HIGH, 0, "power"}, {GPIO_EC_IN_RW, ACTIVE_HIGH, gpio_get(GPIO_EC_IN_RW), diff --git a/src/mainboard/google/kukui/chromeos.c b/src/mainboard/google/kukui/chromeos.c index 35395014d6..2cef10e82b 100644 --- a/src/mainboard/google/kukui/chromeos.c +++ b/src/mainboard/google/kukui/chromeos.c @@ -35,7 +35,6 @@ void fill_lb_gpios(struct lb_gpios *gpios) struct lb_gpio chromeos_gpios[] = { {GPIO_WP.id, ACTIVE_LOW, !get_write_protect_state(), "write protect"}, - {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"}, {EC_IN_RW.id, ACTIVE_HIGH, -1, "EC in RW"}, {EC_IRQ.id, ACTIVE_LOW, -1, "EC interrupt"}, {CR50_IRQ.id, ACTIVE_HIGH, -1, "TPM interrupt"}, diff --git a/src/mainboard/google/link/chromeos.c b/src/mainboard/google/link/chromeos.c index 5156404ab7..ecd7592823 100644 --- a/src/mainboard/google/link/chromeos.c +++ b/src/mainboard/google/link/chromeos.c @@ -28,10 +28,6 @@ void fill_lb_gpios(struct lb_gpios *gpios) /* Write Protect: GPIO57 = PCH_SPI_WP_D */ {57, ACTIVE_HIGH, get_write_protect_state(), "write protect"}, - /* Recovery: the "switch" comes from the EC */ - /* -1 indicates that this is a pseudo GPIO */ - {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"}, - /* Lid: the "switch" comes from the EC */ {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, diff --git a/src/mainboard/google/nyan/chromeos.c b/src/mainboard/google/nyan/chromeos.c index ba851c76c3..e3e09e6dbd 100644 --- a/src/mainboard/google/nyan/chromeos.c +++ b/src/mainboard/google/nyan/chromeos.c @@ -22,7 +22,6 @@ void fill_lb_gpios(struct lb_gpios *gpios) struct lb_gpio chromeos_gpios[] = { {GPIO(R1), ACTIVE_LOW, !get_write_protect_state(), "write protect"}, - {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"}, {GPIO(R4), ACTIVE_HIGH, -1, "lid"}, {GPIO(Q0), ACTIVE_LOW, -1, "power"}, {GPIO(U4), ACTIVE_HIGH, -1, "EC in RW"}, diff --git a/src/mainboard/google/nyan_big/chromeos.c b/src/mainboard/google/nyan_big/chromeos.c index f2979989fa..1fbaac7234 100644 --- a/src/mainboard/google/nyan_big/chromeos.c +++ b/src/mainboard/google/nyan_big/chromeos.c @@ -22,7 +22,6 @@ void fill_lb_gpios(struct lb_gpios *gpios) struct lb_gpio chromeos_gpios[] = { {GPIO(R1), ACTIVE_LOW, !get_write_protect_state(), "write protect"}, - {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"}, {GPIO(R4), ACTIVE_HIGH, -1, "lid"}, {GPIO(Q0), ACTIVE_LOW, -1, "power"}, {GPIO(U4), ACTIVE_HIGH, -1, "EC in RW"}, diff --git a/src/mainboard/google/nyan_blaze/chromeos.c b/src/mainboard/google/nyan_blaze/chromeos.c index dbbd91f1dd..bbb274fb90 100644 --- a/src/mainboard/google/nyan_blaze/chromeos.c +++ b/src/mainboard/google/nyan_blaze/chromeos.c @@ -22,7 +22,6 @@ void fill_lb_gpios(struct lb_gpios *gpios) struct lb_gpio chromeos_gpios[] = { {GPIO(R1), ACTIVE_LOW, !get_write_protect_state(), "write protect"}, - {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"}, {GPIO(R4), ACTIVE_HIGH, -1, "lid"}, {GPIO(Q0), ACTIVE_LOW, -1, "power"}, {GPIO(U4), ACTIVE_HIGH, -1, "EC in RW"}, diff --git a/src/mainboard/google/oak/chromeos.c b/src/mainboard/google/oak/chromeos.c index 4e07236b4c..b613cc3a85 100644 --- a/src/mainboard/google/oak/chromeos.c +++ b/src/mainboard/google/oak/chromeos.c @@ -36,7 +36,6 @@ void fill_lb_gpios(struct lb_gpios *gpios) struct lb_gpio chromeos_gpios[] = { {WRITE_PROTECT.id, ACTIVE_LOW, !get_write_protect_state(), "write protect"}, - {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"}, {LID.id, ACTIVE_HIGH, -1, "lid"}, {POWER_BUTTON.id, ACTIVE_HIGH, -1, "power"}, {EC_IN_RW.id, ACTIVE_HIGH, -1, "EC in RW"}, diff --git a/src/mainboard/google/octopus/chromeos.c b/src/mainboard/google/octopus/chromeos.c index 5eb3990124..ca9f6fbeb2 100644 --- a/src/mainboard/google/octopus/chromeos.c +++ b/src/mainboard/google/octopus/chromeos.c @@ -25,7 +25,6 @@ void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { {-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"}, - {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"}, {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, {-1, ACTIVE_HIGH, 0, "power"}, {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, diff --git a/src/mainboard/google/parrot/chromeos.c b/src/mainboard/google/parrot/chromeos.c index f17b6a64e1..095d5049ed 100644 --- a/src/mainboard/google/parrot/chromeos.c +++ b/src/mainboard/google/parrot/chromeos.c @@ -39,9 +39,6 @@ void fill_lb_gpios(struct lb_gpios *gpios) /* Write Protect: GPIO70 active high */ {70, ACTIVE_LOW, !get_write_protect_state(), "write protect"}, - /* Recovery: Virtual GPIO in the EC (Servo GPIO68 active low) */ - {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"}, - /* Lid switch GPIO active high (open). */ {15, ACTIVE_HIGH, get_lid_switch(), "lid"}, diff --git a/src/mainboard/google/peach_pit/chromeos.c b/src/mainboard/google/peach_pit/chromeos.c index b2d90d9e90..8bd35bee95 100644 --- a/src/mainboard/google/peach_pit/chromeos.c +++ b/src/mainboard/google/peach_pit/chromeos.c @@ -29,9 +29,6 @@ void fill_lb_gpios(struct lb_gpios *gpios) {EXYNOS5_GPX3, ACTIVE_LOW, !get_write_protect_state(), "write protect"}, - /* Recovery: active low */ - {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"}, - /* Lid: active high (LID_GPIO) */ {EXYNOS5_GPX3, ACTIVE_HIGH, gpio_get_value(GPIO_X34), "lid"}, diff --git a/src/mainboard/google/poppy/chromeos.c b/src/mainboard/google/poppy/chromeos.c index 83b8aa0563..3879732135 100644 --- a/src/mainboard/google/poppy/chromeos.c +++ b/src/mainboard/google/poppy/chromeos.c @@ -28,7 +28,6 @@ void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { {-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"}, - {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"}, {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, {-1, ACTIVE_HIGH, 0, "power"}, {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, diff --git a/src/mainboard/google/rambi/chromeos.c b/src/mainboard/google/rambi/chromeos.c index d47a323a4f..7880154586 100644 --- a/src/mainboard/google/rambi/chromeos.c +++ b/src/mainboard/google/rambi/chromeos.c @@ -27,7 +27,6 @@ void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { {-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"}, - {-1, ACTIVE_HIGH, vboot_recovery_mode_enabled(), "recovery"}, {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, {-1, ACTIVE_HIGH, 0, "power"}, {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, diff --git a/src/mainboard/google/reef/chromeos.c b/src/mainboard/google/reef/chromeos.c index 7b7f2b8ce0..4dbbe6d581 100644 --- a/src/mainboard/google/reef/chromeos.c +++ b/src/mainboard/google/reef/chromeos.c @@ -24,7 +24,6 @@ void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { {-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"}, - {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"}, {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, {-1, ACTIVE_HIGH, 0, "power"}, {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, diff --git a/src/mainboard/google/sarien/chromeos.c b/src/mainboard/google/sarien/chromeos.c index 15670d0d8e..fafc469270 100644 --- a/src/mainboard/google/sarien/chromeos.c +++ b/src/mainboard/google/sarien/chromeos.c @@ -36,8 +36,6 @@ void fill_lb_gpios(struct lb_gpios *gpios) struct lb_gpio chromeos_gpios[] = { {GPIO_PCH_WP, ACTIVE_HIGH, get_write_protect_state(), "write protect"}, - {GPIO_REC_MODE, ACTIVE_LOW, !get_recovery_mode_switch(), - "recovery"}, {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, {-1, ACTIVE_HIGH, 0, "power"}, {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, diff --git a/src/mainboard/google/slippy/chromeos.c b/src/mainboard/google/slippy/chromeos.c index 15779ee965..f52bace271 100644 --- a/src/mainboard/google/slippy/chromeos.c +++ b/src/mainboard/google/slippy/chromeos.c @@ -25,7 +25,6 @@ void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { {58, ACTIVE_HIGH, get_write_protect_state(), "write protect"}, - {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"}, {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, {-1, ACTIVE_HIGH, 0, "power"}, {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, diff --git a/src/mainboard/google/smaug/chromeos.c b/src/mainboard/google/smaug/chromeos.c index 567a3ae253..3d36cd9dc0 100644 --- a/src/mainboard/google/smaug/chromeos.c +++ b/src/mainboard/google/smaug/chromeos.c @@ -23,7 +23,6 @@ void fill_lb_gpios(struct lb_gpios *gpios) struct lb_gpio chromeos_gpios[] = { {WRITE_PROTECT_L, ACTIVE_LOW, !get_write_protect_state(), "write protect"}, - {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"}, {POWER_BUTTON, ACTIVE_LOW, -1, "power"}, {EC_IN_RW, ACTIVE_HIGH, -1, "EC in RW"}, {AP_SYS_RESET_L, ACTIVE_LOW, -1, "reset"}, diff --git a/src/mainboard/google/storm/chromeos.c b/src/mainboard/google/storm/chromeos.c index ccc0b53e02..9587c3c384 100644 --- a/src/mainboard/google/storm/chromeos.c +++ b/src/mainboard/google/storm/chromeos.c @@ -39,7 +39,7 @@ static int read_gpio(gpio_t gpio_num) void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { - {REC_SW, ACTIVE_LOW, read_gpio(REC_SW), "recovery"}, + {DEV_SW, ACTIVE_LOW, read_gpio(REC_SW), "presence"}, {WP_SW, ACTIVE_LOW, !get_write_protect_state(), "write protect"}, {-1, ACTIVE_LOW, 1, "power"}, diff --git a/src/mainboard/google/stout/chromeos.c b/src/mainboard/google/stout/chromeos.c index 015e0aad32..60c7a09249 100644 --- a/src/mainboard/google/stout/chromeos.c +++ b/src/mainboard/google/stout/chromeos.c @@ -35,9 +35,6 @@ void fill_lb_gpios(struct lb_gpios *gpios) /* Write Protect: GPIO7 */ {7, ACTIVE_LOW, !get_write_protect_state(), "write protect"}, - /* Recovery: Virtual switch */ - {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"}, - /* Lid Switch: Virtual switch */ {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, diff --git a/src/mainboard/google/veyron/chromeos.c b/src/mainboard/google/veyron/chromeos.c index 357a7fc468..d27b4dd3d5 100644 --- a/src/mainboard/google/veyron/chromeos.c +++ b/src/mainboard/google/veyron/chromeos.c @@ -43,7 +43,7 @@ void fill_lb_gpios(struct lb_gpios *gpios) {GPIO_WP.raw, ACTIVE_LOW, !get_write_protect_state(), "write protect"}, {GPIO_RECOVERY.raw, ACTIVE_LOW, - !get_recovery_mode_switch(), "recovery"}, + !get_recovery_mode_switch(), "presence"}, {GPIO_LID.raw, ACTIVE_HIGH, -1, "lid"}, {GPIO_POWER.raw, ACTIVE_LOW, -1, "power"}, {GPIO_ECINRW.raw, ACTIVE_HIGH, -1, "EC in RW"}, diff --git a/src/mainboard/google/veyron_mickey/chromeos.c b/src/mainboard/google/veyron_mickey/chromeos.c index 46a6738b93..c549e70b51 100644 --- a/src/mainboard/google/veyron_mickey/chromeos.c +++ b/src/mainboard/google/veyron_mickey/chromeos.c @@ -34,7 +34,7 @@ void fill_lb_gpios(struct lb_gpios *gpios) {GPIO_WP.raw, ACTIVE_LOW, !get_write_protect_state(), "write protect"}, {GPIO_RECOVERY.raw, ACTIVE_LOW, - !get_recovery_mode_switch(), "recovery"}, + !get_recovery_mode_switch(), "presence"}, {GPIO_RESET.raw, ACTIVE_HIGH, -1, "reset"}, }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); diff --git a/src/mainboard/google/veyron_rialto/chromeos.c b/src/mainboard/google/veyron_rialto/chromeos.c index e86d86305f..65866f3cec 100644 --- a/src/mainboard/google/veyron_rialto/chromeos.c +++ b/src/mainboard/google/veyron_rialto/chromeos.c @@ -41,7 +41,7 @@ void fill_lb_gpios(struct lb_gpios *gpios) /* Note for early development, we want to support both servo * and pushkey recovery buttons in firmware boot stages. */ {GPIO_RECOVERY_PUSHKEY.raw, ACTIVE_LOW, - !get_recovery_mode_switch(), "recovery"}, + !get_recovery_mode_switch(), "presence"}, {GPIO_POWER.raw, ACTIVE_LOW, -1, "power"}, {GPIO_RESET.raw, ACTIVE_HIGH, -1, "reset"}, }; diff --git a/src/mainboard/intel/baskingridge/chromeos.c b/src/mainboard/intel/baskingridge/chromeos.c index f1fd3ed84c..1673622793 100644 --- a/src/mainboard/intel/baskingridge/chromeos.c +++ b/src/mainboard/intel/baskingridge/chromeos.c @@ -33,7 +33,7 @@ void fill_lb_gpios(struct lb_gpios *gpios) {0, ACTIVE_LOW, !get_write_protect_state(), "write protect"}, /* Recovery: GPIO69 - SV_DETECT - J8E3 (silkscreen: J8E2) */ - {69, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"}, + {69, ACTIVE_HIGH, get_recovery_mode_switch(), "presence"}, /* Hard code the lid switch GPIO to open. */ {-1, ACTIVE_HIGH, 1, "lid"}, diff --git a/src/mainboard/intel/cannonlake_rvp/chromeos.c b/src/mainboard/intel/cannonlake_rvp/chromeos.c index 296a3a51ea..44254bcbcb 100644 --- a/src/mainboard/intel/cannonlake_rvp/chromeos.c +++ b/src/mainboard/intel/cannonlake_rvp/chromeos.c @@ -27,7 +27,6 @@ void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { {-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"}, - {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"}, {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, {-1, ACTIVE_HIGH, 0, "power"}, {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, diff --git a/src/mainboard/intel/coffeelake_rvp/chromeos.c b/src/mainboard/intel/coffeelake_rvp/chromeos.c index 84f5f27f6a..a581217e17 100644 --- a/src/mainboard/intel/coffeelake_rvp/chromeos.c +++ b/src/mainboard/intel/coffeelake_rvp/chromeos.c @@ -26,7 +26,6 @@ void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { {-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"}, - {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"}, {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, {-1, ACTIVE_HIGH, 0, "power"}, {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, diff --git a/src/mainboard/intel/emeraldlake2/chromeos.c b/src/mainboard/intel/emeraldlake2/chromeos.c index 78610d398d..219eefb871 100644 --- a/src/mainboard/intel/emeraldlake2/chromeos.c +++ b/src/mainboard/intel/emeraldlake2/chromeos.c @@ -33,7 +33,7 @@ void fill_lb_gpios(struct lb_gpios *gpios) {48, ACTIVE_LOW, !get_write_protect_state(), "write protect"}, /* Recovery: GPIO22 */ - {22, ACTIVE_LOW, !get_recovery_mode_switch(), "recovery"}, + {22, ACTIVE_LOW, !get_recovery_mode_switch(), "presence"}, /* Hard code the lid switch GPIO to open. */ {-1, ACTIVE_HIGH, 1, "lid"}, diff --git a/src/mainboard/intel/glkrvp/chromeos.c b/src/mainboard/intel/glkrvp/chromeos.c index 07d92e96fe..4edd4a0ab4 100644 --- a/src/mainboard/intel/glkrvp/chromeos.c +++ b/src/mainboard/intel/glkrvp/chromeos.c @@ -25,7 +25,6 @@ void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { {-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"}, - {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"}, {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, {-1, ACTIVE_HIGH, 0, "power"}, {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, diff --git a/src/mainboard/intel/icelake_rvp/chromeos.c b/src/mainboard/intel/icelake_rvp/chromeos.c index 5965d95c32..ce8e5486d8 100644 --- a/src/mainboard/intel/icelake_rvp/chromeos.c +++ b/src/mainboard/intel/icelake_rvp/chromeos.c @@ -27,7 +27,6 @@ void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { {-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"}, - {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"}, {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, {-1, ACTIVE_HIGH, 0, "power"}, {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, diff --git a/src/mainboard/intel/kblrvp/chromeos.c b/src/mainboard/intel/kblrvp/chromeos.c index 51680742ad..ff93d27f22 100644 --- a/src/mainboard/intel/kblrvp/chromeos.c +++ b/src/mainboard/intel/kblrvp/chromeos.c @@ -31,7 +31,6 @@ void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { {-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"}, - {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"}, {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, {-1, ACTIVE_HIGH, 0, "power"}, {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, diff --git a/src/mainboard/intel/kunimitsu/chromeos.c b/src/mainboard/intel/kunimitsu/chromeos.c index f7a9d52ba6..64224889a5 100644 --- a/src/mainboard/intel/kunimitsu/chromeos.c +++ b/src/mainboard/intel/kunimitsu/chromeos.c @@ -27,7 +27,6 @@ void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { {-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"}, - {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"}, {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, {-1, ACTIVE_HIGH, 0, "power"}, {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, diff --git a/src/mainboard/intel/strago/chromeos.c b/src/mainboard/intel/strago/chromeos.c index 03eff1be4e..df36b38a31 100644 --- a/src/mainboard/intel/strago/chromeos.c +++ b/src/mainboard/intel/strago/chromeos.c @@ -29,7 +29,6 @@ void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { {-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"}, - {-1, ACTIVE_HIGH, vboot_recovery_mode_enabled(), "recovery"}, {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, {-1, ACTIVE_HIGH, 0, "power"}, {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, diff --git a/src/mainboard/intel/wtm2/chromeos.c b/src/mainboard/intel/wtm2/chromeos.c index 0f5cfbba35..802221446d 100644 --- a/src/mainboard/intel/wtm2/chromeos.c +++ b/src/mainboard/intel/wtm2/chromeos.c @@ -29,7 +29,6 @@ void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { {-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"}, - {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"}, {-1, ACTIVE_HIGH, 1, "lid"}, // force open {-1, ACTIVE_HIGH, 0, "power"}, {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, diff --git a/src/mainboard/samsung/lumpy/chromeos.c b/src/mainboard/samsung/lumpy/chromeos.c index 2d4fb61be8..6760f03611 100644 --- a/src/mainboard/samsung/lumpy/chromeos.c +++ b/src/mainboard/samsung/lumpy/chromeos.c @@ -47,7 +47,7 @@ void fill_lb_gpios(struct lb_gpios *gpios) /* Recovery: GPIO42 = CHP3_REC_MODE# */ {GPIO_REC_MODE, ACTIVE_LOW, !get_recovery_mode_switch(), - "recovery"}, + "presence"}, {100, ACTIVE_HIGH, lid & 1, "lid"}, diff --git a/src/mainboard/samsung/stumpy/chromeos.c b/src/mainboard/samsung/stumpy/chromeos.c index b1ad137113..9ec4218b01 100644 --- a/src/mainboard/samsung/stumpy/chromeos.c +++ b/src/mainboard/samsung/stumpy/chromeos.c @@ -43,7 +43,7 @@ void fill_lb_gpios(struct lb_gpios *gpios) /* Recovery: GPIO42 = CHP3_REC_MODE# */ {GPIO_REC_MODE, ACTIVE_LOW, !get_recovery_mode_switch(), - "recovery"}, + "presence"}, /* Hard code the lid switch GPIO to open. */ {100, ACTIVE_HIGH, 1, "lid"}, From 7528f834447de52d1d62e979cd93af0ac30d5f6f Mon Sep 17 00:00:00 2001 From: John Zhao Date: Fri, 10 May 2019 10:51:52 -0700 Subject: [PATCH 025/331] soc/intel: Geminilake Refresh feature request support Add 0x706a8 for GLK Refresh CPU stepping ID. BUG=b:132414963 BRANCH=None TEST=Image built successfully. Signed-off-by: John Zhao Change-Id: I4641d9bd4c82211e7200f617cae9043b0f2f38d1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32744 Tested-by: build bot (Jenkins) Reviewed-by: Lijian Zhao --- src/soc/intel/apollolake/cpu.c | 1 + src/soc/intel/common/block/cpu/mp_init.c | 1 + src/soc/intel/common/block/include/intelblocks/mp_init.h | 1 + 3 files changed, 3 insertions(+) diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c index 11d15e4f13..651c20e43a 100644 --- a/src/soc/intel/apollolake/cpu.c +++ b/src/soc/intel/apollolake/cpu.c @@ -119,6 +119,7 @@ static const struct cpu_device_id cpu_table[] = { { X86_VENDOR_INTEL, CPUID_APOLLOLAKE_E0 }, { X86_VENDOR_INTEL, CPUID_GLK_A0 }, { X86_VENDOR_INTEL, CPUID_GLK_B0 }, + { X86_VENDOR_INTEL, CPUID_GLK_R0 }, { 0, 0 }, }; diff --git a/src/soc/intel/common/block/cpu/mp_init.c b/src/soc/intel/common/block/cpu/mp_init.c index 0a59c56f1f..e98b5dd615 100644 --- a/src/soc/intel/common/block/cpu/mp_init.c +++ b/src/soc/intel/common/block/cpu/mp_init.c @@ -70,6 +70,7 @@ static const struct cpu_device_id cpu_table[] = { { X86_VENDOR_INTEL, CPUID_APOLLOLAKE_E0 }, { X86_VENDOR_INTEL, CPUID_GLK_A0 }, { X86_VENDOR_INTEL, CPUID_GLK_B0 }, + { X86_VENDOR_INTEL, CPUID_GLK_R0 }, { X86_VENDOR_INTEL, CPUID_WHISKEYLAKE_V0 }, { X86_VENDOR_INTEL, CPUID_WHISKEYLAKE_W0 }, { X86_VENDOR_INTEL, CPUID_COFFEELAKE_U0 }, diff --git a/src/soc/intel/common/block/include/intelblocks/mp_init.h b/src/soc/intel/common/block/include/intelblocks/mp_init.h index 3c7467da57..0f37a64345 100644 --- a/src/soc/intel/common/block/include/intelblocks/mp_init.h +++ b/src/soc/intel/common/block/include/intelblocks/mp_init.h @@ -37,6 +37,7 @@ #define CPUID_APOLLOLAKE_E0 0x506ca #define CPUID_GLK_A0 0x706a0 #define CPUID_GLK_B0 0x706a1 +#define CPUID_GLK_R0 0x706a8 #define CPUID_WHISKEYLAKE_V0 0x806ec #define CPUID_WHISKEYLAKE_W0 0x806eb #define CPUID_COFFEELAKE_D0 0x806ea From a75440739d172bea6eeefc08af2bbdefc528e912 Mon Sep 17 00:00:00 2001 From: Jacob Garber Date: Thu, 9 May 2019 14:24:02 -0600 Subject: [PATCH 026/331] util/inteltool: Use appropriate channel for printing timings At least one channel must be present, so print an error if there is not. However, we cannot always assume it will be the first channel, so make the appropriate selection when printing the timings. Found-by: Coverity Scan #1370{584,585,588,589,590-596,600} Signed-off-by: Jacob Garber Change-Id: I6b59989242e498474782876302e0850e3e4cf2d3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32713 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph --- util/inteltool/ivy_memory.c | 32 ++++++++++++++++++++------------ 1 file changed, 20 insertions(+), 12 deletions(-) diff --git a/util/inteltool/ivy_memory.c b/util/inteltool/ivy_memory.c index 8ce861127b..16c1d8920c 100644 --- a/util/inteltool/ivy_memory.c +++ b/util/inteltool/ivy_memory.c @@ -97,6 +97,11 @@ void ivybridge_dump_timings(const char *dump_spd_file) rankmap[channel] = read_mchbar32(0xc14 + 0x100 * channel) >> 24; } + if ((rankmap[0] == 0) && (rankmap[1] == 0)) { + fputs("Error: no memory channels found\n", stderr); + exit(1); + } + two_channels = rankmap[0] && rankmap[1]; mr0[0] = read_mchbar32(0x0004); @@ -172,49 +177,52 @@ void ivybridge_dump_timings(const char *dump_spd_file) printf(".reg_4004_b30 = { %d, %d },\n", reg_4004_b30[0], reg_4004_b30[1]); + + channel = (rankmap[0] != 0) ? 0 : 1; + if (two_channels && tFAW[0] != tFAW[1]) printf("/* tFAW mismatch: %d, %d */\n", tFAW[0], tFAW[1]); - print_time("tFAW", tFAW[0], tCK); + print_time("tFAW", tFAW[channel], tCK); if (two_channels && tWTR[0] != tWTR[1]) printf("/* tWTR mismatch: %d, %d */\n", tWTR[0], tWTR[1]); - print_time("tWTR", tWTR[0], tCK); + print_time("tWTR", tWTR[channel], tCK); if (two_channels && tCKE[0] != tCKE[1]) printf("/* tCKE mismatch: %d, %d */\n", tCKE[0], tCKE[1]); - print_time("tCKE", tCKE[0], tCK); + print_time("tCKE", tCKE[channel], tCK); if (two_channels && tRTP[0] != tRTP[1]) printf("/* tRTP mismatch: %d, %d */\n", tRTP[0], tRTP[1]); - print_time("tRTP", tRTP[0], tCK); + print_time("tRTP", tRTP[channel], tCK); if (two_channels && tRRD[0] != tRRD[1]) printf("/* tRRD mismatch: %d, %d */\n", tRRD[0], tRRD[1]); - print_time("tRRD", tRRD[0], tCK); + print_time("tRRD", tRRD[channel], tCK); if (two_channels && tRAS[0] != tRAS[1]) printf("/* tRAS mismatch: %d, %d */\n", tRAS[0], tRAS[1]); - print_time("tRAS", tRAS[0], tCK); + print_time("tRAS", tRAS[channel], tCK); if (two_channels && tCWL[0] != tCWL[1]) printf("/* tCWL mismatch: %d, %d */\n", tCWL[0], tCWL[1]); - print_time("tCWL", tCWL[0], tCK); + print_time("tCWL", tCWL[channel], tCK); if (two_channels && tRP[0] != tRP[1]) printf("/* tRP mismatch: %d, %d */\n", tRP[0], tRP[1]); - print_time("tRP", tRP[0], tCK); + print_time("tRP", tRP[channel], tCK); if (two_channels && tRCD[0] != tRCD[1]) printf("/* tRCD mismatch: %d, %d */\n", tRCD[0], tRCD[1]); - print_time("tRCD", tRCD[0], tCK); + print_time("tRCD", tRCD[channel], tCK); if (two_channels && tXPDLL[0] != tXPDLL[1]) printf("/* tXPDLL mismatch: %d, %d */\n", tXPDLL[0], tXPDLL[1]); - print_time("tXPDLL", tXPDLL[0], tCK); + print_time("tXPDLL", tXPDLL[channel], tCK); if (two_channels && tXP[0] != tXP[1]) printf("/* tXP mismatch: %d, %d */\n", tXP[0], tXP[1]); - print_time("tXP", tXP[0], tCK); + print_time("tXP", tXP[channel], tCK); if (two_channels && tAONPD[0] != tAONPD[1]) printf("/* tAONPD mismatch: %d, %d */\n", tAONPD[0], tAONPD[1]); - print_time("tAONPD", tAONPD[0], tCK); + print_time("tAONPD", tAONPD[channel], tCK); reg = read_mchbar32(0x4298); if (reg != read_mchbar32(0x4698) && two_channels) From dbc787d13d461bf0d96002bfc36936de4c64cea7 Mon Sep 17 00:00:00 2001 From: Jacob Garber Date: Fri, 10 May 2019 17:29:48 -0600 Subject: [PATCH 027/331] libpayload/drivers/i8042: Add fallthrough comment Ctrl-delete does nothing, so it falls through to the default case. Add a comment to make this explicit. Found-by: Coverity Scan #1260878 Signed-off-by: Jacob Garber Change-Id: I4a6f51cb04696b6ebcb554c5667a5bbea58622c1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32750 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph --- payloads/libpayload/drivers/i8042/keyboard.c | 1 + 1 file changed, 1 insertion(+) diff --git a/payloads/libpayload/drivers/i8042/keyboard.c b/payloads/libpayload/drivers/i8042/keyboard.c index 42431c3689..cded638380 100644 --- a/payloads/libpayload/drivers/i8042/keyboard.c +++ b/payloads/libpayload/drivers/i8042/keyboard.c @@ -258,6 +258,7 @@ int keyboard_getchar(void) /* vulcan nerve pinch */ if ((modifier & KB_MOD_ALT) && reset_handler) reset_handler(); + /* fallthrough */ default: ret = 0; } From ef9e85bbfdb24d228f1e6c37d916025c5d06ea53 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Fri, 10 May 2019 19:40:50 +0200 Subject: [PATCH 028/331] mb/t400/acpi: Update ATPR buffer to fit all entries Error spotted using acpica version 20190509 (Change-Id: I6779a20). Change-Id: Ic9cf16a7494667f6dab156c697fb8f8e9966051e Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/32743 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber Reviewed-by: Martin Roth --- src/mainboard/lenovo/t400/acpi/graphics.asl | 2 -- 1 file changed, 2 deletions(-) diff --git a/src/mainboard/lenovo/t400/acpi/graphics.asl b/src/mainboard/lenovo/t400/acpi/graphics.asl index 818ea93724..038774fdfd 100644 --- a/src/mainboard/lenovo/t400/acpi/graphics.asl +++ b/src/mainboard/lenovo/t400/acpi/graphics.asl @@ -63,9 +63,7 @@ Method (ATPX, 2, Serialized) { }) CreateWordField (ATPR, 0x00, SIZE) CreateWordField (ATPR, 0x02, VERS) - CreateDWordField (ATPR, 0x02, MASK) CreateDWordField (ATPR, 0x04, FUNC) - CreateDWordField (ATPR, 0x06, FLAG) /* Version request */ if (LEqual(Arg0, 0x0)) From 2f0bbbfe9f3b3d68d75eabd35280fe8aaa9d8619 Mon Sep 17 00:00:00 2001 From: Martin Roth Date: Sat, 11 May 2019 12:51:44 -0600 Subject: [PATCH 029/331] mb/lenovo/s230u: Rewrite trigger inversion ACPI code The GPIO invert registers are already defined in the PCH code, so just use the 8-bit versions of the registers instead of creating a new GPIO field for the single bits. This allows us to get rid of the Field(GPIO...) code that's causing problems with IASL version 20190509. Signed-off-by: Martin Roth Change-Id: Iac5dfb71b3a2b5a25c05a403cf5f403c7acecaaf Reviewed-on: https://review.coreboot.org/c/coreboot/+/32753 Tested-by: build bot (Jenkins) Reviewed-by: HAOUAS Elyes --- src/mainboard/lenovo/s230u/acpi/gpe.asl | 23 ++++++++++++----------- 1 file changed, 12 insertions(+), 11 deletions(-) diff --git a/src/mainboard/lenovo/s230u/acpi/gpe.asl b/src/mainboard/lenovo/s230u/acpi/gpe.asl index a69f5629b1..e6f4153aca 100644 --- a/src/mainboard/lenovo/s230u/acpi/gpe.asl +++ b/src/mainboard/lenovo/s230u/acpi/gpe.asl @@ -16,15 +16,6 @@ Scope (_GPE) { - Field(GPIO, ByteAcc, NoLock, Preserve) - { - Offset(0x2c), // GPIO Invert - , 2, - GV02, 1, - , 1, - GV04, 1, - } - Name (PDET, Zero) Method (PNOT, 2, Serialized) { ShiftLeft (Arg0, Arg1, Local0) @@ -39,10 +30,20 @@ Scope (_GPE) } } + Method (TINV, 2, Serialized) { + ShiftLeft (One, Arg1, Local0) + If (LEqual (Arg0, Zero)) { + Not (Local0, Local0) + And (GIV0, Local0, GIV0) + } Else { + Or (GIV0, Local0, GIV0) + } + } + /* Palm detect sensor 1 */ Method (_L12, 0, NotSerialized) { // Invert trigger - Store(GP02, GV02) + TINV (GP02, 2) PNOT (GP02, 0) } @@ -50,7 +51,7 @@ Scope (_GPE) /* Palm detect sensor 2 */ Method (_L14, 0, NotSerialized) { // Invert trigger - Store(GP04, GV04) + TINV (GP04, 4) PNOT (GP04, 1) } From 60ab1d8c52799d70d1956ce7261d94be439aa63a Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Fri, 10 May 2019 21:05:58 +0200 Subject: [PATCH 030/331] src/ec/lenovo/h8/acpi: Serialize Control Method IASL reports warning 'Control Method should be made Serialized'. Change-Id: I034f2c00e912e8f9ef87b9918de1db06fade38b9 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/32745 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph --- src/ec/lenovo/h8/acpi/battery.asl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/ec/lenovo/h8/acpi/battery.asl b/src/ec/lenovo/h8/acpi/battery.asl index 080f247838..5f97ed9dc5 100644 --- a/src/ec/lenovo/h8/acpi/battery.asl +++ b/src/ec/lenovo/h8/acpi/battery.asl @@ -160,7 +160,7 @@ Method(BSTA, 4, NotSerialized) Return (Arg1) } -Method(BINF, 2, NotSerialized) +Method(BINF, 2, Serialized) { Acquire(ECLK, 0xffff) ^BPAG(Or(1, Arg1)) /* Battery 0 static information */ From 44105942df5a396c5ff999d7dd8384bfd44784c0 Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Thu, 9 May 2019 17:19:23 +0200 Subject: [PATCH 031/331] nb/intel/sandybridge: Update pei_data comments Update outdated comments. Change-Id: I100f71345281a1dc52e99d2395f528d60a9a1f58 Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/c/coreboot/+/32706 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/mainboard/samsung/lumpy/romstage.c | 2 -- src/northbridge/intel/sandybridge/pei_data.h | 7 ++++--- 2 files changed, 4 insertions(+), 5 deletions(-) diff --git a/src/mainboard/samsung/lumpy/romstage.c b/src/mainboard/samsung/lumpy/romstage.c index 1080689d4a..26b9dcc813 100644 --- a/src/mainboard/samsung/lumpy/romstage.c +++ b/src/mainboard/samsung/lumpy/romstage.c @@ -148,7 +148,6 @@ static const uint8_t *locate_spd(void) die("SPD data not found."); if (spd_file_len < (spd_index + 1) * 256) die("Missing SPD data."); - // leave onboard dimm address at f0, and copy spd data there. return spd_data[spd_index]; } @@ -198,7 +197,6 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) }, }; *pei_data = pei_data_template; - // leave onboard dimm address at f0, and copy spd data there. memcpy(pei_data->spd_data[0], locate_spd(), 256); } diff --git a/src/northbridge/intel/sandybridge/pei_data.h b/src/northbridge/intel/sandybridge/pei_data.h index 0a60707136..8e98becbe3 100644 --- a/src/northbridge/intel/sandybridge/pei_data.h +++ b/src/northbridge/intel/sandybridge/pei_data.h @@ -105,9 +105,10 @@ struct pei_data uint16_t usb_port_config[16][3]; /* See the usb3 struct above for details */ pch_usb3_controller_settings usb3; - /* SPD data array for onboard RAM. Specify address 0xf0, - * 0xf1, 0xf2, 0xf3 to index one of the 4 slots in - * spd_address for a given "DIMM". + /* SPD data array for onboard RAM. + * spd_data [1..3] are ignored, instead the "dimm_channel{0,1}_disabled" + * flag and the spd_addresses are used to determine which DIMMs should + * use the SPD from spd_data[0]. */ uint8_t spd_data[4][256]; tx_byte_func tx_byte; From 59b4255c63b54739b9a095021508a13eab86c2a1 Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Wed, 8 May 2019 12:44:15 +0200 Subject: [PATCH 032/331] mb/samsung/lumpy: Move onboard SPD to second channel Move the onboard SPD to second channel as native raminit does and workaround mrc expecations in northbridge code. Required to move pei data to devicetree and to use the same code for mrc and native raminit. Tested on Lenovo T520: Other fields then spd_data[0] are ignored. Change-Id: If1910e82a4bd178c2a6c2991c91e09782122888e Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/c/coreboot/+/32682 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/mainboard/samsung/lumpy/romstage.c | 2 +- src/northbridge/intel/sandybridge/raminit_mrc.c | 13 +++++++++++++ 2 files changed, 14 insertions(+), 1 deletion(-) diff --git a/src/mainboard/samsung/lumpy/romstage.c b/src/mainboard/samsung/lumpy/romstage.c index 26b9dcc813..a77149d927 100644 --- a/src/mainboard/samsung/lumpy/romstage.c +++ b/src/mainboard/samsung/lumpy/romstage.c @@ -197,7 +197,7 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) }, }; *pei_data = pei_data_template; - memcpy(pei_data->spd_data[0], locate_spd(), 256); + memcpy(pei_data->spd_data[2], locate_spd(), 256); } const struct southbridge_usb_port mainboard_usb_ports[] = { diff --git a/src/northbridge/intel/sandybridge/raminit_mrc.c b/src/northbridge/intel/sandybridge/raminit_mrc.c index ea3590f78d..1c9e021025 100644 --- a/src/northbridge/intel/sandybridge/raminit_mrc.c +++ b/src/northbridge/intel/sandybridge/raminit_mrc.c @@ -288,6 +288,19 @@ void perform_raminit(int s3resume) mainboard_fill_pei_data(&pei_data); post_code(0x3a); + + /* Fix spd_data. MRC only uses spd_data[0] and ignores the other */ + for (size_t i = 1; i < ARRAY_SIZE(pei_data.spd_data); i++) { + if (pei_data.spd_data[i][0] && !pei_data.spd_data[0][0]) { + memcpy(pei_data.spd_data[0], pei_data.spd_data[i], + sizeof(pei_data.spd_data[0])); + } else if (pei_data.spd_data[i][0] && pei_data.spd_data[0][0]) { + if (memcmp(pei_data.spd_data[i], pei_data.spd_data[0], + sizeof(pei_data.spd_data[0])) != 0) + die("Onboard SPDs must match each other"); + } + } + pei_data.boot_mode = s3resume ? 2 : 0; timestamp_add_now(TS_BEFORE_INITRAM); sdram_initialize(&pei_data); From 5709e03613b342f9dc00a659b6474c6ee510fcc3 Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Mon, 25 Mar 2019 10:12:14 +0100 Subject: [PATCH 033/331] nb/intel/sandybridge: Migrate MRC settings to devicetree * Add more chip register to move PEI data to devicetree.cb. * Set northbridge/southbridge and runtime detectable settings. * Fill in values from devicetree. This change is still a noop as the pei structure is completely overwritten with the exsting mainboard pei structure. The followup commit will migrate to devicetree.cb. Tested on Lenovo T520, boots MRC path with the new devicetree settings. Signed-off-by: Patrick Rudolph Change-Id: Ic6d9f0fd6a2b792ac693d6016ed9ce44945c900c Reviewed-on: https://review.coreboot.org/c/coreboot/+/32069 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/northbridge/intel/sandybridge/chip.h | 66 ++++++++++++ .../intel/sandybridge/raminit_mrc.c | 100 ++++++++++++++++++ 2 files changed, 166 insertions(+) diff --git a/src/northbridge/intel/sandybridge/chip.h b/src/northbridge/intel/sandybridge/chip.h index d002824287..7dddb8abd0 100644 --- a/src/northbridge/intel/sandybridge/chip.h +++ b/src/northbridge/intel/sandybridge/chip.h @@ -52,6 +52,72 @@ struct northbridge_intel_sandybridge_config { * Maximum PCI mmio size in MiB. */ u16 pci_mmio_size; + + /* Data for RAM init */ + + /* DIMM SPD address. Use 8bit notation where BIT0 is always zero. */ + u8 spd_addresses[4]; + + /* PEI data for RAM init and early silicon init */ + u8 ts_addresses[4]; + + bool ec_present; + bool ddr3lv_support; + + /* N mode functionality. Leave this setting at 0. + * 0 Auto + * 1 1N + * 2 2N + */ + enum { + DDR_NMODE_AUTO = 0, + DDR_NMODE_1N, + DDR_NMODE_2N, + } nmode; + + /* DDR refresh rate config. JEDEC Standard No.21-C Annex K allows + * for DIMM SPD data to specify whether double-rate is required for + * extended operating temperature range. + * 0 Enable double rate based upon temperature thresholds + * 1 Normal rate + * 2 Always enable double rate + */ + enum { + DDR_REFRESH_RATE_TEMP_THRES = 0, + DDR_REFRESH_REATE_NORMAL, + DDR_REFRESH_RATE_DOUBLE, + } ddr_refresh_rate_config; + + /* + * USB Port Configuration: + * [0] = enable + * [1] = overcurrent pin + * [2] = length + * + * Ports 0-7 can be mapped to OC0-OC3 + * Ports 8-13 can be mapped to OC4-OC7 + * + * Port Length + * MOBILE: + * < 0x050 = Setting 1 (back panel, 1-5in, lowest tx amplitude) + * < 0x140 = Setting 2 (back panel, 5-14in, highest tx amplitude) + * DESKTOP: + * < 0x080 = Setting 1 (front/back panel, <8in, lowest tx amplitude) + * < 0x130 = Setting 2 (back panel, 8-13in, higher tx amplitude) + * < 0x150 = Setting 3 (back panel, 13-15in, highest tx amplitude) + */ + u16 usb_port_config[16][3]; + + struct { + /* 0: Disable, 1: Enable, 2: Auto, 3: Smart Auto */ + u8 mode : 2; + /* 4 bit mask, 1: switchable, 0: not switchable */ + u8 hs_port_switch_mask : 4; + /* 0: No xHCI preOS driver, 1: xHCI preOS driver */ + u8 preboot_support : 1; + /* 0: Disable, 1: Enable */ + u8 xhci_streams : 1; + } usb3; }; #endif /* NORTHBRIDGE_INTEL_SANDYBRIDGE_CHIP_H */ diff --git a/src/northbridge/intel/sandybridge/raminit_mrc.c b/src/northbridge/intel/sandybridge/raminit_mrc.c index 1c9e021025..a35d9d814e 100644 --- a/src/northbridge/intel/sandybridge/raminit_mrc.c +++ b/src/northbridge/intel/sandybridge/raminit_mrc.c @@ -20,6 +20,7 @@ #include #include #include +#include #include #include #include @@ -32,6 +33,7 @@ #include "raminit.h" #include "pei_data.h" #include "sandybridge.h" +#include "chip.h" #include #include @@ -275,6 +277,89 @@ struct mrc_var_data { u32 reserved[4]; } __packed; +static void northbridge_fill_pei_data(struct pei_data *pei_data) +{ + pei_data->mchbar = (uintptr_t)DEFAULT_MCHBAR; + pei_data->dmibar = (uintptr_t)DEFAULT_DMIBAR; + pei_data->epbar = DEFAULT_EPBAR; + pei_data->pciexbar = CONFIG_MMCONF_BASE_ADDRESS; + pei_data->hpet_address = CONFIG_HPET_ADDRESS; + pei_data->thermalbase = 0xfed08000; + pei_data->system_type = get_platform_type() == PLATFORM_MOBILE ? 0 : 1; + pei_data->tseg_size = CONFIG_SMM_TSEG_SIZE; + + if ((cpu_get_cpuid() & 0xffff0) == 0x306a0) { + const struct device *dev = pcidev_on_root(1, 0); + pei_data->pcie_init = dev && dev->enabled; + } else { + pei_data->pcie_init = 0; + } +} + +static void southbridge_fill_pei_data(struct pei_data *pei_data) +{ + const struct device *dev = pcidev_on_root(0x19, 0); + + pei_data->smbusbar = SMBUS_IO_BASE; + pei_data->wdbbar = 0x4000000; + pei_data->wdbsize = 0x1000; + pei_data->rcba = (uintptr_t)DEFAULT_RCBABASE; + pei_data->pmbase = DEFAULT_PMBASE; + pei_data->gpiobase = DEFAULT_GPIOBASE; + pei_data->gbe_enable = dev && dev->enabled; +} + +static void devicetree_fill_pei_data(struct pei_data *pei_data) +{ + const struct northbridge_intel_sandybridge_config *cfg; + + const struct device *dev = pcidev_on_root(0, 0); + if (!dev || !dev->chip_info) + return; + + cfg = dev->chip_info; + + switch (cfg->max_mem_clock_mhz) { + /* MRC only supports fixed numbers of frequencies */ + default: + printk(BIOS_WARNING, "RAMINIT: Limiting DDR3 clock to 800 Mhz\n"); + /* fallthrough */ + case 400: + pei_data->max_ddr3_freq = 800; + break; + case 533: + pei_data->max_ddr3_freq = 1066; + break; + case 666: + pei_data->max_ddr3_freq = 1333; + break; + case 800: + pei_data->max_ddr3_freq = 1600; + break; + + } + + memcpy(pei_data->spd_addresses, cfg->spd_addresses, + sizeof(pei_data->spd_addresses)); + + memcpy(pei_data->ts_addresses, cfg->ts_addresses, + sizeof(pei_data->ts_addresses)); + + pei_data->ec_present = cfg->ec_present; + pei_data->ddr3lv_support = cfg->ddr3lv_support; + + pei_data->nmode = cfg->nmode; + pei_data->ddr_refresh_rate_config = cfg->ddr_refresh_rate_config; + + memcpy(pei_data->usb_port_config, cfg->usb_port_config, + sizeof(pei_data->usb_port_config)); + + pei_data->usb3.mode = cfg->usb3.mode; + pei_data->usb3.hs_port_switch_mask = cfg->usb3.hs_port_switch_mask; + pei_data->usb3.preboot_support = cfg->usb3.preboot_support; + pei_data->usb3.xhci_streams = cfg->usb3.xhci_streams; +} + void perform_raminit(int s3resume) { int cbmem_was_initted; @@ -285,10 +370,25 @@ void perform_raminit(int s3resume) if (!mainboard_should_reset_usb(s3resume)) enable_usb_bar(); + memset(&pei_data, 0, sizeof(pei_data)); + pei_data.pei_version = PEI_VERSION, + + northbridge_fill_pei_data(&pei_data); + southbridge_fill_pei_data(&pei_data); + devicetree_fill_pei_data(&pei_data); mainboard_fill_pei_data(&pei_data); post_code(0x3a); + /* Fill after mainboard_fill_pei_data as it might provide spd_data */ + pei_data.dimm_channel0_disabled = + (!pei_data.spd_addresses[0] && !pei_data.spd_data[0][0]) + + (!pei_data.spd_addresses[1] && !pei_data.spd_data[1][0]) * 2; + + pei_data.dimm_channel1_disabled = + (!pei_data.spd_addresses[2] && !pei_data.spd_data[2][0]) + + (!pei_data.spd_addresses[3] && !pei_data.spd_data[3][0]) * 2; + /* Fix spd_data. MRC only uses spd_data[0] and ignores the other */ for (size_t i = 1; i < ARRAY_SIZE(pei_data.spd_data); i++) { if (pei_data.spd_data[i][0] && !pei_data.spd_data[0][0]) { From 9005071c5fb1d75b2a54aa0b3e7af47e25d2de54 Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Mon, 25 Mar 2019 09:53:23 +0100 Subject: [PATCH 034/331] nb/intel/sandybridge: Move boot_count_increment() Move boot_count_increment() to romstage.c, drop preprocessor code and only increase counter once on regular boot. Tested on Lenovo T520 (Intel Sandy Bridge). Still boots to OS, no errors visible in dmesg. Change-Id: I6aa52b75edf19953405b70284c7e7db30f607cd6 Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/c/coreboot/+/32067 Reviewed-by: HAOUAS Elyes Reviewed-by: Patrick Georgi Reviewed-by: Arthur Heymans Tested-by: build bot (Jenkins) --- src/northbridge/intel/sandybridge/early_init.c | 18 +----------------- src/northbridge/intel/sandybridge/romstage.c | 4 ++++ 2 files changed, 5 insertions(+), 17 deletions(-) diff --git a/src/northbridge/intel/sandybridge/early_init.c b/src/northbridge/intel/sandybridge/early_init.c index b923065091..34aec3851b 100644 --- a/src/northbridge/intel/sandybridge/early_init.c +++ b/src/northbridge/intel/sandybridge/early_init.c @@ -20,7 +20,6 @@ #include #include #include -#include #include #include #include "sandybridge.h" @@ -45,22 +44,7 @@ static void sandybridge_setup_bars(void) pci_write_config8(PCI_DEV(0, 0x00, 0), PAM5, 0x33); pci_write_config8(PCI_DEV(0, 0x00, 0), PAM6, 0x33); -#if CONFIG(ELOG_BOOT_COUNT) - /* Increment Boot Counter for non-S3 resume */ - if ((inw(DEFAULT_PMBASE + PM1_STS) & WAK_STS) && - ((inl(DEFAULT_PMBASE + PM1_CNT) >> 10) & 7) != SLP_TYP_S3) - boot_count_increment(); -#endif - - printk(BIOS_DEBUG, " done.\n"); - -#if CONFIG(ELOG_BOOT_COUNT) - /* Increment Boot Counter except when resuming from S3 */ - if ((inw(DEFAULT_PMBASE + PM1_STS) & WAK_STS) && - ((inl(DEFAULT_PMBASE + PM1_CNT) >> 10) & 7) == SLP_TYP_S3) - return; - boot_count_increment(); -#endif + printk(BIOS_DEBUG, " done\n"); } static void sandybridge_setup_graphics(void) diff --git a/src/northbridge/intel/sandybridge/romstage.c b/src/northbridge/intel/sandybridge/romstage.c index 43316a2f22..064d042e56 100644 --- a/src/northbridge/intel/sandybridge/romstage.c +++ b/src/northbridge/intel/sandybridge/romstage.c @@ -30,6 +30,7 @@ #include #include #include +#include static void early_pch_reset_pmcon(void) { @@ -79,6 +80,9 @@ void mainboard_romstage_entry(unsigned long bist) s3resume = southbridge_detect_s3_resume(); + if (CONFIG(ELOG_BOOT_COUNT) && !s3resume) + boot_count_increment(); + post_code(0x38); mainboard_early_init(s3resume); From 0c22d2fe46fbc59fa12fec46c21874f422b10e44 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Sat, 1 Dec 2018 12:19:52 +0100 Subject: [PATCH 035/331] {bd82x6x,i82801gx,ibexpeak,lynxpoint}: Remove dead code and use macro Use BIOS_CNTL defined macro instead of magic number. Change-Id: I0d2b555ada9c2893af4f85422128f5a8b04e2fc6 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/29990 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph --- src/soc/intel/fsp_baytrail/southcluster.c | 3 --- src/southbridge/intel/bd82x6x/lpc.c | 4 +-- src/southbridge/intel/fsp_rangeley/lpc.c | 3 --- src/southbridge/intel/i82801gx/lpc.c | 32 ----------------------- src/southbridge/intel/i82801ix/lpc.c | 32 ----------------------- src/southbridge/intel/i82801jx/lpc.c | 32 ----------------------- src/southbridge/intel/ibexpeak/lpc.c | 4 +-- src/southbridge/intel/lynxpoint/lpc.c | 4 +-- 8 files changed, 6 insertions(+), 108 deletions(-) diff --git a/src/soc/intel/fsp_baytrail/southcluster.c b/src/soc/intel/fsp_baytrail/southcluster.c index 4734e0e023..c84f4083d4 100644 --- a/src/soc/intel/fsp_baytrail/southcluster.c +++ b/src/soc/intel/fsp_baytrail/southcluster.c @@ -42,9 +42,6 @@ #include "chip.h" #include -#define ENABLE_ACPI_MODE_IN_COREBOOT 0 -#define TEST_SMM_FLASH_LOCKDOWN 0 - typedef struct soc_intel_fsp_baytrail_config config_t; static inline void diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index f7bb7e4303..773750186f 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -436,9 +436,9 @@ static void pch_disable_smm_only_flashing(struct device *dev) u8 reg8; printk(BIOS_SPEW, "Enabling BIOS updates outside of SMM... "); - reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */ + reg8 = pci_read_config8(dev, BIOS_CNTL); reg8 &= ~(1 << 5); - pci_write_config8(dev, 0xdc, reg8); + pci_write_config8(dev, BIOS_CNTL, reg8); } static void pch_fixups(struct device *dev) diff --git a/src/southbridge/intel/fsp_rangeley/lpc.c b/src/southbridge/intel/fsp_rangeley/lpc.c index 4118e5fded..ba5e04bd3c 100644 --- a/src/southbridge/intel/fsp_rangeley/lpc.c +++ b/src/southbridge/intel/fsp_rangeley/lpc.c @@ -38,9 +38,6 @@ #define NMI_OFF 0 -#define ENABLE_ACPI_MODE_IN_COREBOOT 0 -#define TEST_SMM_FLASH_LOCKDOWN 0 - typedef struct southbridge_intel_fsp_rangeley_config config_t; static void soc_enable_apic(struct device *dev) diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index 9a6c9cfefd..948b6aa7f7 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -40,7 +40,6 @@ #define NMI_OFF 0 #define ENABLE_ACPI_MODE_IN_COREBOOT 0 -#define TEST_SMM_FLASH_LOCKDOWN 0 typedef struct southbridge_intel_i82801gx_config config_t; @@ -333,10 +332,6 @@ static void enable_clock_gating(void) #if CONFIG(HAVE_SMI_HANDLER) static void i82801gx_lock_smm(struct device *dev) { -#if TEST_SMM_FLASH_LOCKDOWN - u8 reg8; -#endif - if (!acpi_is_wakeup_s3()) { #if ENABLE_ACPI_MODE_IN_COREBOOT printk(BIOS_DEBUG, "Enabling ACPI via APMC:\n"); @@ -351,33 +346,6 @@ static void i82801gx_lock_smm(struct device *dev) printk(BIOS_DEBUG, "S3 wakeup, enabling ACPI via APMC\n"); outb(APM_CNT_ACPI_ENABLE, APM_CNT); } - -#if TEST_SMM_FLASH_LOCKDOWN - /* Now try this: */ - printk(BIOS_DEBUG, "Locking BIOS to RO... "); - reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */ - printk(BIOS_DEBUG, " BLE: %s; BWE: %s\n", (reg8&2)?"on":"off", - (reg8&1)?"rw":"ro"); - reg8 &= ~(1 << 0); /* clear BIOSWE */ - pci_write_config8(dev, 0xdc, reg8); - reg8 |= (1 << 1); /* set BLE */ - pci_write_config8(dev, 0xdc, reg8); - printk(BIOS_DEBUG, "ok.\n"); - reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */ - printk(BIOS_DEBUG, " BLE: %s; BWE: %s\n", (reg8&2)?"on":"off", - (reg8&1)?"rw":"ro"); - - printk(BIOS_DEBUG, "Writing:\n"); - *(volatile u8 *)0xfff00000 = 0x00; - printk(BIOS_DEBUG, "Testing:\n"); - reg8 |= (1 << 0); /* set BIOSWE */ - pci_write_config8(dev, 0xdc, reg8); - - reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */ - printk(BIOS_DEBUG, " BLE: %s; BWE: %s\n", (reg8&2)?"on":"off", - (reg8&1)?"rw":"ro"); - printk(BIOS_DEBUG, "Done.\n"); -#endif } #endif diff --git a/src/southbridge/intel/i82801ix/lpc.c b/src/southbridge/intel/i82801ix/lpc.c index 4cc1cea02c..c7de2a14df 100644 --- a/src/southbridge/intel/i82801ix/lpc.c +++ b/src/southbridge/intel/i82801ix/lpc.c @@ -39,7 +39,6 @@ #define NMI_OFF 0 #define ENABLE_ACPI_MODE_IN_COREBOOT 0 -#define TEST_SMM_FLASH_LOCKDOWN 0 typedef struct southbridge_intel_i82801ix_config config_t; @@ -370,10 +369,6 @@ static void enable_clock_gating(void) #if CONFIG(HAVE_SMI_HANDLER) static void i82801ix_lock_smm(struct device *dev) { -#if TEST_SMM_FLASH_LOCKDOWN - u8 reg8; -#endif - if (!acpi_is_wakeup_s3()) { #if ENABLE_ACPI_MODE_IN_COREBOOT printk(BIOS_DEBUG, "Enabling ACPI via APMC:\n"); @@ -393,33 +388,6 @@ static void i82801ix_lock_smm(struct device *dev) */ if (!CONFIG(PARALLEL_MP)) smm_lock(); - -#if TEST_SMM_FLASH_LOCKDOWN - /* Now try this: */ - printk(BIOS_DEBUG, "Locking BIOS to RO... "); - reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */ - printk(BIOS_DEBUG, " BLE: %s; BWE: %s\n", (reg8&2)?"on":"off", - (reg8&1)?"rw":"ro"); - reg8 &= ~(1 << 0); /* clear BIOSWE */ - pci_write_config8(dev, 0xdc, reg8); - reg8 |= (1 << 1); /* set BLE */ - pci_write_config8(dev, 0xdc, reg8); - printk(BIOS_DEBUG, "ok.\n"); - reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */ - printk(BIOS_DEBUG, " BLE: %s; BWE: %s\n", (reg8&2)?"on":"off", - (reg8&1)?"rw":"ro"); - - printk(BIOS_DEBUG, "Writing:\n"); - *(volatile u8 *)0xfff00000 = 0x00; - printk(BIOS_DEBUG, "Testing:\n"); - reg8 |= (1 << 0); /* set BIOSWE */ - pci_write_config8(dev, 0xdc, reg8); - - reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */ - printk(BIOS_DEBUG, " BLE: %s; BWE: %s\n", (reg8&2)?"on":"off", - (reg8&1)?"rw":"ro"); - printk(BIOS_DEBUG, "Done.\n"); -#endif } #endif diff --git a/src/southbridge/intel/i82801jx/lpc.c b/src/southbridge/intel/i82801jx/lpc.c index abfe665989..5373ba2022 100644 --- a/src/southbridge/intel/i82801jx/lpc.c +++ b/src/southbridge/intel/i82801jx/lpc.c @@ -40,7 +40,6 @@ #define NMI_OFF 0 #define ENABLE_ACPI_MODE_IN_COREBOOT 0 -#define TEST_SMM_FLASH_LOCKDOWN 0 typedef struct southbridge_intel_i82801jx_config config_t; @@ -375,10 +374,6 @@ static void enable_clock_gating(void) #if CONFIG(HAVE_SMI_HANDLER) static void i82801jx_lock_smm(struct device *dev) { -#if TEST_SMM_FLASH_LOCKDOWN - u8 reg8; -#endif - if (!acpi_is_wakeup_s3()) { #if ENABLE_ACPI_MODE_IN_COREBOOT printk(BIOS_DEBUG, "Enabling ACPI via APMC:\n"); @@ -393,33 +388,6 @@ static void i82801jx_lock_smm(struct device *dev) printk(BIOS_DEBUG, "S3 wakeup, enabling ACPI via APMC\n"); outb(APM_CNT_ACPI_ENABLE, APM_CNT); } - -#if TEST_SMM_FLASH_LOCKDOWN - /* Now try this: */ - printk(BIOS_DEBUG, "Locking BIOS to RO... "); - reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */ - printk(BIOS_DEBUG, " BLE: %s; BWE: %s\n", (reg8&2)?"on":"off", - (reg8&1)?"rw":"ro"); - reg8 &= ~(1 << 0); /* clear BIOSWE */ - pci_write_config8(dev, 0xdc, reg8); - reg8 |= (1 << 1); /* set BLE */ - pci_write_config8(dev, 0xdc, reg8); - printk(BIOS_DEBUG, "ok.\n"); - reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */ - printk(BIOS_DEBUG, " BLE: %s; BWE: %s\n", (reg8&2)?"on":"off", - (reg8&1)?"rw":"ro"); - - printk(BIOS_DEBUG, "Writing:\n"); - *(volatile u8 *)0xfff00000 = 0x00; - printk(BIOS_DEBUG, "Testing:\n"); - reg8 |= (1 << 0); /* set BIOSWE */ - pci_write_config8(dev, 0xdc, reg8); - - reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */ - printk(BIOS_DEBUG, " BLE: %s; BWE: %s\n", (reg8&2)?"on":"off", - (reg8&1)?"rw":"ro"); - printk(BIOS_DEBUG, "Done.\n"); -#endif } #endif diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c index f4464f3b4d..e7162b1e04 100644 --- a/src/southbridge/intel/ibexpeak/lpc.c +++ b/src/southbridge/intel/ibexpeak/lpc.c @@ -451,9 +451,9 @@ static void pch_disable_smm_only_flashing(struct device *dev) u8 reg8; printk(BIOS_SPEW, "Enabling BIOS updates outside of SMM... "); - reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */ + reg8 = pci_read_config8(dev, BIOS_CNTL); reg8 &= ~(1 << 5); - pci_write_config8(dev, 0xdc, reg8); + pci_write_config8(dev, BIOS_CNTL, reg8); } static void pch_fixups(struct device *dev) diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index 951c69c11c..b0f57c122b 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -510,9 +510,9 @@ static void pch_disable_smm_only_flashing(struct device *dev) u8 reg8; printk(BIOS_SPEW, "Enabling BIOS updates outside of SMM... "); - reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */ + reg8 = pci_read_config8(dev, BIOS_CNTL); reg8 &= ~(1 << 5); - pci_write_config8(dev, 0xdc, reg8); + pci_write_config8(dev, BIOS_CNTL, reg8); } static void pch_fixups(struct device *dev) From 8dd518969cf02e37412019e4a6a4a5ce496da8c0 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Sun, 12 May 2019 11:27:17 +0200 Subject: [PATCH 036/331] soc/intel/{cannonlake,icelake}: Drop unused cbmem.c file Change-Id: Ib9444f7797289c9b8250cfb16eb1c12dff867ec3 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/32756 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber Reviewed-by: Subrata Banik Reviewed-by: Furquan Shaikh --- src/soc/intel/cannonlake/cbmem.c | 22 ---------------------- src/soc/intel/icelake/cbmem.c | 22 ---------------------- 2 files changed, 44 deletions(-) delete mode 100644 src/soc/intel/cannonlake/cbmem.c delete mode 100644 src/soc/intel/icelake/cbmem.c diff --git a/src/soc/intel/cannonlake/cbmem.c b/src/soc/intel/cannonlake/cbmem.c deleted file mode 100644 index 300556a45f..0000000000 --- a/src/soc/intel/cannonlake/cbmem.c +++ /dev/null @@ -1,22 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2017 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include - -void *cbmem_top(void) -{ - /* not implemented yet */ - return (void *) NULL; -} diff --git a/src/soc/intel/icelake/cbmem.c b/src/soc/intel/icelake/cbmem.c deleted file mode 100644 index 4f447773ac..0000000000 --- a/src/soc/intel/icelake/cbmem.c +++ /dev/null @@ -1,22 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2018 Intel Corp. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include - -void *cbmem_top(void) -{ - /* not implemented yet */ - return (void *) NULL; -} From 11a5b6b577d5e4c2611ac80dd0b7f761b80f942f Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Sun, 12 May 2019 09:33:14 +0200 Subject: [PATCH 037/331] i82801gx/bootblock: Use macro instead of magic number Change-Id: I2556c150f53d9580bc3b70ab49b3a2c8477c18ea Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/32755 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph --- src/southbridge/intel/i82801gx/bootblock.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/southbridge/intel/i82801gx/bootblock.c b/src/southbridge/intel/i82801gx/bootblock.c index 426973fc2f..9d94d0cd25 100644 --- a/src/southbridge/intel/i82801gx/bootblock.c +++ b/src/southbridge/intel/i82801gx/bootblock.c @@ -23,10 +23,10 @@ static void enable_spi_prefetch(void) dev = PCI_DEV(0, 0x1f, 0); - reg8 = pci_read_config8(dev, 0xdc); + reg8 = pci_read_config8(dev, BIOS_CNTL); reg8 &= ~(3 << 2); reg8 |= (2 << 2); /* Prefetching and Caching Enabled */ - pci_write_config8(dev, 0xdc, reg8); + pci_write_config8(dev, BIOS_CNTL, reg8); } static void bootblock_southbridge_init(void) From e429d86655171326db127a5ca9b8b597a291eae2 Mon Sep 17 00:00:00 2001 From: Julius Werner Date: Fri, 10 May 2019 15:21:40 -0700 Subject: [PATCH 038/331] 3rdparty: Uprev vboot submodule to upstream master This patch uprevs the vboot submodule to the new upstream HEAD commit dac763c782 Make vboot -Wtype-limits compliant Change-Id: I363e218e019b25483bc4c06315ca4e0e34599daf Signed-off-by: Julius Werner Reviewed-on: https://review.coreboot.org/c/coreboot/+/32748 Tested-by: build bot (Jenkins) Reviewed-by: Joel Kitching Reviewed-by: Patrick Georgi --- 3rdparty/vboot | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/3rdparty/vboot b/3rdparty/vboot index e7edff6653..dac763c782 160000 --- a/3rdparty/vboot +++ b/3rdparty/vboot @@ -1 +1 @@ -Subproject commit e7edff6653e16ed915c3ad12234d133d1ef4dcc9 +Subproject commit dac763c782ce05476dec02e855f349d2b6f3a910 From c15e600490fcc0e7da2a4495b233a4f9c62c8cd1 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Fri, 10 May 2019 06:56:18 +0200 Subject: [PATCH 039/331] crossgcc: Upgrade acpica to version 20190509 Changes: https://acpica.org/node/170 Change-Id: I6779a20005ffc0d4781bb60de3ba48759ef67d40 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/32721 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi Reviewed-by: Paul Menzel --- util/crossgcc/buildgcc | 2 +- ...20190215_iasl.patch => acpica-unix2-20190509_iasl.patch} | 6 +++--- util/crossgcc/sum/acpica-unix2-20190215.tar.gz.cksum | 1 - util/crossgcc/sum/acpica-unix2-20190509.tar.gz.cksum | 1 + 4 files changed, 5 insertions(+), 5 deletions(-) rename util/crossgcc/patches/{acpica-unix2-20190215_iasl.patch => acpica-unix2-20190509_iasl.patch} (73%) delete mode 100644 util/crossgcc/sum/acpica-unix2-20190215.tar.gz.cksum create mode 100644 util/crossgcc/sum/acpica-unix2-20190509.tar.gz.cksum diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index 0951fb60e4..327027a565 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -54,7 +54,7 @@ GCC_VERSION=8.3.0 GCC_AUTOCONF_VERSION=2.69 BINUTILS_VERSION=2.32 GDB_VERSION=8.2.1 -IASL_VERSION=20190215 +IASL_VERSION=20190509 PYTHON_VERSION=3.7.2 EXPAT_VERSION=2.2.6 # CLANG version number diff --git a/util/crossgcc/patches/acpica-unix2-20190215_iasl.patch b/util/crossgcc/patches/acpica-unix2-20190509_iasl.patch similarity index 73% rename from util/crossgcc/patches/acpica-unix2-20190215_iasl.patch rename to util/crossgcc/patches/acpica-unix2-20190509_iasl.patch index c4f605292b..49df22510f 100644 --- a/util/crossgcc/patches/acpica-unix2-20190215_iasl.patch +++ b/util/crossgcc/patches/acpica-unix2-20190509_iasl.patch @@ -1,6 +1,6 @@ -diff -Naur acpica-unix2-20190215_/source/compiler/asloptions.c acpica-unix2-20190215/source/compiler/asloptions.c > acpica-unix2-20190215_iasl.patch ---- acpica-unix2-20190108_/source/compiler/asloptions.c -+++ acpica-unix2-20190108/source/compiler/asloptions.c +diff -Naur acpica-unix2-20190509_/source/compiler/asloptions.c acpica-unix2-20190509/source/compiler/asloptions.c > acpica-unix2-20190509_iasl.patch +--- acpica-unix2-20190509_/source/compiler/asloptions.c ++++ acpica-unix2-20190509/source/compiler/asloptions.c @@ -126,6 +126,7 @@ if (Gbl_DoSignon) { diff --git a/util/crossgcc/sum/acpica-unix2-20190215.tar.gz.cksum b/util/crossgcc/sum/acpica-unix2-20190215.tar.gz.cksum deleted file mode 100644 index 310454d603..0000000000 --- a/util/crossgcc/sum/acpica-unix2-20190215.tar.gz.cksum +++ /dev/null @@ -1 +0,0 @@ -82d729cb09edc50ee11669651683ca5a5c0f4d5a tarballs/acpica-unix2-20190215.tar.gz diff --git a/util/crossgcc/sum/acpica-unix2-20190509.tar.gz.cksum b/util/crossgcc/sum/acpica-unix2-20190509.tar.gz.cksum new file mode 100644 index 0000000000..2f53d714fb --- /dev/null +++ b/util/crossgcc/sum/acpica-unix2-20190509.tar.gz.cksum @@ -0,0 +1 @@ +aa4d4f8051800e84a5ed5b71635594aaca749e8d tarballs/acpica-unix2-20190509.tar.gz From 795fda033656982a8aeef0e105bcfbc9a73c8c13 Mon Sep 17 00:00:00 2001 From: Julius Werner Date: Fri, 10 May 2019 15:23:22 -0700 Subject: [PATCH 040/331] Reland "Makefile.inc: Enable -Wtype-limits"" This reverts commit 99e836c843e6a8536348d5cc9581b5a17512a263. This relands commit c4ab50cdde4bfd01ec7509012b105c88bcf4c953. The issues with -Wtype-limits in the vboot submodule have been resolved now, so we can enable this flag again. Change-Id: I32e8cc88e69072e7ee66cf443b578a9a8ea0ebe2 Signed-off-by: Julius Werner Reviewed-on: https://review.coreboot.org/c/coreboot/+/32749 Tested-by: build bot (Jenkins) Reviewed-by: Joel Kitching --- Makefile.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile.inc b/Makefile.inc index a9aaaed783..9860da1b68 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -401,7 +401,7 @@ endif CFLAGS_common += -pipe -g -nostdinc -std=gnu11 CFLAGS_common += -nostdlib -Wall -Wundef -Wstrict-prototypes -Wmissing-prototypes CFLAGS_common += -Wwrite-strings -Wredundant-decls -Wno-trigraphs -CFLAGS_common += -Wstrict-aliasing -Wshadow -Wdate-time +CFLAGS_common += -Wstrict-aliasing -Wshadow -Wdate-time -Wtype-limits CFLAGS_common += -fno-common -ffreestanding -fno-builtin -fomit-frame-pointer CFLAGS_common += -ffunction-sections -fdata-sections -fno-pie ifeq ($(CONFIG_COMPILER_GCC),y) From 55cb5f8de53366c9df10ed9307cc9088c96191cf Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Mon, 13 May 2019 12:49:16 +0530 Subject: [PATCH 041/331] Remove unnecessary ENV_RAMSTAGE guard TEST=Able to build coreboot for CML. Change-Id: Ic0f473e04ffc1de50dee871af52eacf0b328b376 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/32764 Reviewed-by: Furquan Shaikh Tested-by: build bot (Jenkins) --- src/arch/x86/include/arch/acpi.h | 2 -- src/console/post.c | 2 -- src/drivers/uart/uart8250io.c | 2 -- src/drivers/uart/uart8250mem.c | 2 -- src/lib/bootmode.c | 2 -- 5 files changed, 10 deletions(-) diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h index 79feaad070..60efdd0d7a 100644 --- a/src/arch/x86/include/arch/acpi.h +++ b/src/arch/x86/include/arch/acpi.h @@ -838,14 +838,12 @@ void acpi_create_ivrs(acpi_ivrs_t *ivrs, unsigned long (*acpi_fill_ivrs)(acpi_ivrs_t *ivrs_struct, unsigned long current)); -#if ENV_RAMSTAGE && !defined(__SIMPLE_DEVICE__) void acpi_create_hpet(acpi_hpet_t *hpet); unsigned long acpi_write_hpet(struct device *device, unsigned long start, acpi_rsdp_t *rsdp); /* cpu/intel/speedstep/acpi.c */ void generate_cpu_entries(struct device *device); -#endif void acpi_create_mcfg(acpi_mcfg_t *mcfg); diff --git a/src/console/post.c b/src/console/post.c index 236aa8cdaa..b17a819d97 100644 --- a/src/console/post.c +++ b/src/console/post.c @@ -44,7 +44,6 @@ void __weak mainboard_post(uint8_t value) DECLARE_SPIN_LOCK(cmos_post_lock) -#if ENV_RAMSTAGE void cmos_post_log(void) { u8 code = 0; @@ -125,7 +124,6 @@ void post_log_clear(void) post_log_extra(0); } #endif /* CONFIG_CMOS_POST_EXTRA */ -#endif /* ENV_RAMSTAGE */ static void cmos_post_code(u8 value) { diff --git a/src/drivers/uart/uart8250io.c b/src/drivers/uart/uart8250io.c index 62671e2b6f..614a849f7a 100644 --- a/src/drivers/uart/uart8250io.c +++ b/src/drivers/uart/uart8250io.c @@ -124,7 +124,6 @@ void uart_tx_flush(int idx) uart8250_tx_flush(uart_platform_base(idx)); } -#if ENV_RAMSTAGE void uart_fill_lb(void *data) { struct lb_serial serial; @@ -138,4 +137,3 @@ void uart_fill_lb(void *data) lb_add_console(LB_TAG_CONSOLE_SERIAL8250, data); } -#endif diff --git a/src/drivers/uart/uart8250mem.c b/src/drivers/uart/uart8250mem.c index c3dff6a72c..a5aa74a332 100644 --- a/src/drivers/uart/uart8250mem.c +++ b/src/drivers/uart/uart8250mem.c @@ -147,7 +147,6 @@ void uart_tx_flush(int idx) uart8250_mem_tx_flush(base); } -#if ENV_RAMSTAGE void uart_fill_lb(void *data) { struct lb_serial serial; @@ -166,4 +165,3 @@ void uart_fill_lb(void *data) lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data); } -#endif diff --git a/src/lib/bootmode.c b/src/lib/bootmode.c index 18f6d5dcac..737dcf93d0 100644 --- a/src/lib/bootmode.c +++ b/src/lib/bootmode.c @@ -17,7 +17,6 @@ #include #include -#if ENV_RAMSTAGE static int gfx_init_done = -1; int gfx_get_init_done(void) @@ -31,7 +30,6 @@ void gfx_set_init_done(int done) { gfx_init_done = done; } -#endif int display_init_required(void) { From 57459dbeacb4759c3352206464b6c19b7add00d5 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Sun, 12 May 2019 14:11:00 +0200 Subject: [PATCH 042/331] mb/{lenovo/x201,packardbell/ms2290}: Remove superfluous TS init Timestamps are initialized in cpu/intel/car/romstage.c. Change-Id: Ia2b762667be17aa5b482cd585dd6f6198cf50d9e Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/32758 Reviewed-by: Nico Huber Reviewed-by: Alexander Couzens Tested-by: build bot (Jenkins) --- src/mainboard/lenovo/x201/romstage.c | 4 ---- src/mainboard/packardbell/ms2290/romstage.c | 4 ---- 2 files changed, 8 deletions(-) diff --git a/src/mainboard/lenovo/x201/romstage.c b/src/mainboard/lenovo/x201/romstage.c index 7e895b46f0..ae154e25b1 100644 --- a/src/mainboard/lenovo/x201/romstage.c +++ b/src/mainboard/lenovo/x201/romstage.c @@ -175,10 +175,6 @@ void mainboard_romstage_entry(unsigned long bist) int s3resume = 0; const u8 spd_addrmap[4] = { 0x50, 0, 0x51, 0 }; - timestamp_init(timestamp_get()); - - timestamp_add_now(TS_START_ROMSTAGE); - if (bist == 0) enable_lapic(); diff --git a/src/mainboard/packardbell/ms2290/romstage.c b/src/mainboard/packardbell/ms2290/romstage.c index 8442dfaee9..efaa9e423d 100644 --- a/src/mainboard/packardbell/ms2290/romstage.c +++ b/src/mainboard/packardbell/ms2290/romstage.c @@ -168,14 +168,10 @@ void mainboard_romstage_entry(unsigned long bist) int s3resume = 0; const u8 spd_addrmap[4] = { 0x50, 0, 0x52, 0 }; - timestamp_init(timestamp_get()); - /* SERR pin is confused on reset. Clear NMI. */ outb(4, 0x61); outb(0, 0x61); - timestamp_add_now(TS_START_ROMSTAGE); - if (bist == 0) enable_lapic(); From cadc70f7974db25144381b3ea26d4b660233f4dd Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Sun, 12 May 2019 13:44:22 +0200 Subject: [PATCH 043/331] soc/intel/broadwell: Move GPIO init to a common place This also links the gpio configuration instead of including it as a header. Change-Id: I9309d2b842495f6cff33fdab18aa139a82c1959c Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/32759 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber Reviewed-by: Matt DeVillier --- src/mainboard/google/auron/Makefile.inc | 2 ++ src/mainboard/google/auron/romstage.c | 5 ----- .../include/variant/gpio.h => auron_paine/gpio.c} | 7 +------ src/mainboard/google/auron/variants/auron_paine/spd/spd.c | 1 - .../include/variant/gpio.h => auron_yuna/gpio.c} | 7 +------ src/mainboard/google/auron/variants/auron_yuna/spd/spd.c | 1 - .../variants/buddy/{include/variant/gpio.h => gpio.c} | 7 +------ .../variants/gandof/{include/variant/gpio.h => gpio.c} | 7 +------ src/mainboard/google/auron/variants/gandof/spd/spd.c | 1 - .../auron/variants/lulu/{include/variant/gpio.h => gpio.c} | 7 +------ src/mainboard/google/auron/variants/lulu/spd/spd.c | 1 - .../variants/samus/{include/variant/gpio.h => gpio.c} | 7 +------ src/mainboard/google/auron/variants/samus/spd/spd.c | 1 - src/mainboard/google/jecht/Makefile.inc | 2 ++ src/mainboard/google/jecht/romstage.c | 5 ----- .../variants/guado/{include/variant/gpio.h => gpio.c} | 7 +------ .../variants/jecht/{include/variant/gpio.h => gpio.c} | 7 +------ .../variants/rikku/{include/variant/gpio.h => gpio.c} | 7 +------ .../variants/tidus/{include/variant/gpio.h => gpio.c} | 7 +------ src/mainboard/intel/wtm2/Makefile.inc | 2 ++ src/mainboard/intel/wtm2/{gpio.h => gpio.c} | 7 +------ src/mainboard/intel/wtm2/romstage.c | 4 ---- src/mainboard/purism/librem_bdw/Makefile.inc | 1 + src/mainboard/purism/librem_bdw/{gpio.h => gpio.c} | 7 +------ src/mainboard/purism/librem_bdw/romstage.c | 5 ----- src/soc/intel/broadwell/include/soc/gpio.h | 2 ++ src/soc/intel/broadwell/romstage/romstage.c | 4 ++++ 27 files changed, 25 insertions(+), 96 deletions(-) rename src/mainboard/google/auron/variants/{auron_yuna/include/variant/gpio.h => auron_paine/gpio.c} (97%) rename src/mainboard/google/auron/variants/{auron_paine/include/variant/gpio.h => auron_yuna/gpio.c} (97%) rename src/mainboard/google/auron/variants/buddy/{include/variant/gpio.h => gpio.c} (97%) rename src/mainboard/google/auron/variants/gandof/{include/variant/gpio.h => gpio.c} (97%) rename src/mainboard/google/auron/variants/lulu/{include/variant/gpio.h => gpio.c} (97%) rename src/mainboard/google/auron/variants/samus/{include/variant/gpio.h => gpio.c} (97%) rename src/mainboard/google/jecht/variants/guado/{include/variant/gpio.h => gpio.c} (97%) rename src/mainboard/google/jecht/variants/jecht/{include/variant/gpio.h => gpio.c} (97%) rename src/mainboard/google/jecht/variants/rikku/{include/variant/gpio.h => gpio.c} (97%) rename src/mainboard/google/jecht/variants/tidus/{include/variant/gpio.h => gpio.c} (97%) rename src/mainboard/intel/wtm2/{gpio.h => gpio.c} (97%) rename src/mainboard/purism/librem_bdw/{gpio.h => gpio.c} (96%) diff --git a/src/mainboard/google/auron/Makefile.inc b/src/mainboard/google/auron/Makefile.inc index 170e1686da..c81aeaf0f6 100644 --- a/src/mainboard/google/auron/Makefile.inc +++ b/src/mainboard/google/auron/Makefile.inc @@ -32,3 +32,5 @@ subdirs-y += variants/$(VARIANT_DIR) subdirs-y += variants/$(VARIANT_DIR)/spd CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include + +romstage-y += variants/$(VARIANT_DIR)/gpio.c diff --git a/src/mainboard/google/auron/romstage.c b/src/mainboard/google/auron/romstage.c index aea8e211fa..5e1a66ac24 100644 --- a/src/mainboard/google/auron/romstage.c +++ b/src/mainboard/google/auron/romstage.c @@ -17,11 +17,9 @@ #include #include #include -#include #include #include #include -#include #include #include "variant.h" @@ -35,9 +33,6 @@ void mainboard_romstage_entry(struct romstage_params *rp) post_code(0x32); - /* Initialize GPIOs */ - init_gpios(mainboard_gpio_config); - /* Fill out PEI DATA */ memset(&pei_data, 0, sizeof(pei_data)); mainboard_fill_pei_data(&pei_data); diff --git a/src/mainboard/google/auron/variants/auron_yuna/include/variant/gpio.h b/src/mainboard/google/auron/variants/auron_paine/gpio.c similarity index 97% rename from src/mainboard/google/auron/variants/auron_yuna/include/variant/gpio.h rename to src/mainboard/google/auron/variants/auron_paine/gpio.c index eca65d14fc..e8b6c065b1 100644 --- a/src/mainboard/google/auron/variants/auron_yuna/include/variant/gpio.h +++ b/src/mainboard/google/auron/variants/auron_paine/gpio.c @@ -13,12 +13,9 @@ * GNU General Public License for more details. */ -#ifndef AURON_YUNA_GPIO_H -#define AURON_YUNA_GPIO_H - #include -static const struct gpio_config mainboard_gpio_config[] = { +const struct gpio_config mainboard_gpio_config[] = { PCH_GPIO_UNUSED, /* 0: UNUSED */ PCH_GPIO_UNUSED, /* 1: UNUSED */ PCH_GPIO_UNUSED, /* 2: UNUSED */ @@ -116,5 +113,3 @@ static const struct gpio_config mainboard_gpio_config[] = { PCH_GPIO_UNUSED, /* 94: UNUSED */ PCH_GPIO_END }; - -#endif diff --git a/src/mainboard/google/auron/variants/auron_paine/spd/spd.c b/src/mainboard/google/auron/variants/auron_paine/spd/spd.c index 12c876e61b..2991d15eff 100644 --- a/src/mainboard/google/auron/variants/auron_paine/spd/spd.c +++ b/src/mainboard/google/auron/variants/auron_paine/spd/spd.c @@ -22,7 +22,6 @@ #include #include #include -#include #include static void mainboard_print_spd_info(uint8_t spd[]) diff --git a/src/mainboard/google/auron/variants/auron_paine/include/variant/gpio.h b/src/mainboard/google/auron/variants/auron_yuna/gpio.c similarity index 97% rename from src/mainboard/google/auron/variants/auron_paine/include/variant/gpio.h rename to src/mainboard/google/auron/variants/auron_yuna/gpio.c index 44b930a441..e8b6c065b1 100644 --- a/src/mainboard/google/auron/variants/auron_paine/include/variant/gpio.h +++ b/src/mainboard/google/auron/variants/auron_yuna/gpio.c @@ -13,12 +13,9 @@ * GNU General Public License for more details. */ -#ifndef AURON_PAINE_GPIO_H -#define AURON_PAINE_GPIO_H - #include -static const struct gpio_config mainboard_gpio_config[] = { +const struct gpio_config mainboard_gpio_config[] = { PCH_GPIO_UNUSED, /* 0: UNUSED */ PCH_GPIO_UNUSED, /* 1: UNUSED */ PCH_GPIO_UNUSED, /* 2: UNUSED */ @@ -116,5 +113,3 @@ static const struct gpio_config mainboard_gpio_config[] = { PCH_GPIO_UNUSED, /* 94: UNUSED */ PCH_GPIO_END }; - -#endif diff --git a/src/mainboard/google/auron/variants/auron_yuna/spd/spd.c b/src/mainboard/google/auron/variants/auron_yuna/spd/spd.c index 12c876e61b..2991d15eff 100644 --- a/src/mainboard/google/auron/variants/auron_yuna/spd/spd.c +++ b/src/mainboard/google/auron/variants/auron_yuna/spd/spd.c @@ -22,7 +22,6 @@ #include #include #include -#include #include static void mainboard_print_spd_info(uint8_t spd[]) diff --git a/src/mainboard/google/auron/variants/buddy/include/variant/gpio.h b/src/mainboard/google/auron/variants/buddy/gpio.c similarity index 97% rename from src/mainboard/google/auron/variants/buddy/include/variant/gpio.h rename to src/mainboard/google/auron/variants/buddy/gpio.c index efa720f60d..fbb682abf9 100644 --- a/src/mainboard/google/auron/variants/buddy/include/variant/gpio.h +++ b/src/mainboard/google/auron/variants/buddy/gpio.c @@ -14,12 +14,9 @@ * GNU General Public License for more details. */ -#ifndef BUDDY_GPIO_H -#define BUDDY_GPIO_H - #include -static const struct gpio_config mainboard_gpio_config[] = { +const struct gpio_config mainboard_gpio_config[] = { PCH_GPIO_UNUSED, /* 0: UNUSED */ PCH_GPIO_UNUSED, /* 1: UNUSED */ PCH_GPIO_UNUSED, /* 2: UNUSED */ @@ -117,5 +114,3 @@ static const struct gpio_config mainboard_gpio_config[] = { PCH_GPIO_UNUSED, /* 94: UNUSED */ PCH_GPIO_END }; - -#endif diff --git a/src/mainboard/google/auron/variants/gandof/include/variant/gpio.h b/src/mainboard/google/auron/variants/gandof/gpio.c similarity index 97% rename from src/mainboard/google/auron/variants/gandof/include/variant/gpio.h rename to src/mainboard/google/auron/variants/gandof/gpio.c index 68fe4a0190..3de9a0b9d7 100644 --- a/src/mainboard/google/auron/variants/gandof/include/variant/gpio.h +++ b/src/mainboard/google/auron/variants/gandof/gpio.c @@ -13,12 +13,9 @@ * GNU General Public License for more details. */ -#ifndef GANDOF_GPIO_H -#define GANDOF_GPIO_H - #include -static const struct gpio_config mainboard_gpio_config[] = { +const struct gpio_config mainboard_gpio_config[] = { PCH_GPIO_UNUSED, /* 0: UNUSED */ PCH_GPIO_UNUSED, /* 1: UNUSED */ PCH_GPIO_UNUSED, /* 2: UNUSED */ @@ -116,5 +113,3 @@ static const struct gpio_config mainboard_gpio_config[] = { PCH_GPIO_UNUSED, /* 94: UNUSED */ PCH_GPIO_END }; - -#endif diff --git a/src/mainboard/google/auron/variants/gandof/spd/spd.c b/src/mainboard/google/auron/variants/gandof/spd/spd.c index 12c876e61b..2991d15eff 100644 --- a/src/mainboard/google/auron/variants/gandof/spd/spd.c +++ b/src/mainboard/google/auron/variants/gandof/spd/spd.c @@ -22,7 +22,6 @@ #include #include #include -#include #include static void mainboard_print_spd_info(uint8_t spd[]) diff --git a/src/mainboard/google/auron/variants/lulu/include/variant/gpio.h b/src/mainboard/google/auron/variants/lulu/gpio.c similarity index 97% rename from src/mainboard/google/auron/variants/lulu/include/variant/gpio.h rename to src/mainboard/google/auron/variants/lulu/gpio.c index 726dcc755e..a46c4d4e2a 100644 --- a/src/mainboard/google/auron/variants/lulu/include/variant/gpio.h +++ b/src/mainboard/google/auron/variants/lulu/gpio.c @@ -14,12 +14,9 @@ * GNU General Public License for more details. */ -#ifndef LULU_GPIO_H -#define LULU_GPIO_H - #include -static const struct gpio_config mainboard_gpio_config[] = { +const struct gpio_config mainboard_gpio_config[] = { PCH_GPIO_UNUSED, /* 0: UNUSED */ PCH_GPIO_UNUSED, /* 1: UNUSED */ PCH_GPIO_UNUSED, /* 2: UNUSED */ @@ -117,5 +114,3 @@ static const struct gpio_config mainboard_gpio_config[] = { PCH_GPIO_UNUSED, /* 94: UNUSED */ PCH_GPIO_END }; - -#endif diff --git a/src/mainboard/google/auron/variants/lulu/spd/spd.c b/src/mainboard/google/auron/variants/lulu/spd/spd.c index ac99f5c7bc..bd76947d68 100644 --- a/src/mainboard/google/auron/variants/lulu/spd/spd.c +++ b/src/mainboard/google/auron/variants/lulu/spd/spd.c @@ -23,7 +23,6 @@ #include #include #include -#include #include static void mainboard_print_spd_info(uint8_t spd[]) diff --git a/src/mainboard/google/auron/variants/samus/include/variant/gpio.h b/src/mainboard/google/auron/variants/samus/gpio.c similarity index 97% rename from src/mainboard/google/auron/variants/samus/include/variant/gpio.h rename to src/mainboard/google/auron/variants/samus/gpio.c index 8362a4dbfb..72ddcb2259 100644 --- a/src/mainboard/google/auron/variants/samus/include/variant/gpio.h +++ b/src/mainboard/google/auron/variants/samus/gpio.c @@ -13,12 +13,9 @@ * GNU General Public License for more details. */ -#ifndef SAMUS_GPIO_H -#define SAMUS_GPIO_H - #include -static const struct gpio_config mainboard_gpio_config[] = { +const struct gpio_config mainboard_gpio_config[] = { PCH_GPIO_UNUSED, /* 0: UNUSED */ PCH_GPIO_UNUSED, /* 1: UNUSED */ PCH_GPIO_UNUSED, /* 2: UNUSED */ @@ -116,5 +113,3 @@ static const struct gpio_config mainboard_gpio_config[] = { PCH_GPIO_UNUSED, /* 94: UNUSED */ PCH_GPIO_END }; - -#endif diff --git a/src/mainboard/google/auron/variants/samus/spd/spd.c b/src/mainboard/google/auron/variants/samus/spd/spd.c index dd632f30d7..ffb90f997d 100644 --- a/src/mainboard/google/auron/variants/samus/spd/spd.c +++ b/src/mainboard/google/auron/variants/samus/spd/spd.c @@ -22,7 +22,6 @@ #include #include #include -#include #include static void mainboard_print_spd_info(uint8_t spd[]) diff --git a/src/mainboard/google/jecht/Makefile.inc b/src/mainboard/google/jecht/Makefile.inc index 01914bae7d..39e9b339e8 100644 --- a/src/mainboard/google/jecht/Makefile.inc +++ b/src/mainboard/google/jecht/Makefile.inc @@ -27,3 +27,5 @@ romstage-y += led.c subdirs-y += variants/$(VARIANT_DIR) CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include + +romstage-y += variants/$(VARIANT_DIR)/gpio.c diff --git a/src/mainboard/google/jecht/romstage.c b/src/mainboard/google/jecht/romstage.c index 3705feb28a..de0ed30575 100644 --- a/src/mainboard/google/jecht/romstage.c +++ b/src/mainboard/google/jecht/romstage.c @@ -18,14 +18,12 @@ #include #include #include -#include #include #include #include #include #include #include -#include #include "onboard.h" @@ -35,9 +33,6 @@ void mainboard_romstage_entry(struct romstage_params *rp) post_code(0x32); - /* Initialize GPIOs */ - init_gpios(mainboard_gpio_config); - /* Fill out PEI DATA */ memset(&pei_data, 0, sizeof(pei_data)); mainboard_fill_pei_data(&pei_data); diff --git a/src/mainboard/google/jecht/variants/guado/include/variant/gpio.h b/src/mainboard/google/jecht/variants/guado/gpio.c similarity index 97% rename from src/mainboard/google/jecht/variants/guado/include/variant/gpio.h rename to src/mainboard/google/jecht/variants/guado/gpio.c index 4c167e3a58..60e769dbd0 100644 --- a/src/mainboard/google/jecht/variants/guado/include/variant/gpio.h +++ b/src/mainboard/google/jecht/variants/guado/gpio.c @@ -13,12 +13,9 @@ * GNU General Public License for more details. */ -#ifndef GUADO_GPIO_H -#define GUADO_GPIO_H - #include -static const struct gpio_config mainboard_gpio_config[] = { +const struct gpio_config mainboard_gpio_config[] = { PCH_GPIO_UNUSED, /* 0: UNUSED */ PCH_GPIO_UNUSED, /* 1: UNUSED */ PCH_GPIO_UNUSED, /* 2: UNUSED */ @@ -116,5 +113,3 @@ static const struct gpio_config mainboard_gpio_config[] = { PCH_GPIO_UNUSED, /* 94: UNUSED */ PCH_GPIO_END }; - -#endif diff --git a/src/mainboard/google/jecht/variants/jecht/include/variant/gpio.h b/src/mainboard/google/jecht/variants/jecht/gpio.c similarity index 97% rename from src/mainboard/google/jecht/variants/jecht/include/variant/gpio.h rename to src/mainboard/google/jecht/variants/jecht/gpio.c index 94e6516ce7..6a2a64cd7b 100644 --- a/src/mainboard/google/jecht/variants/jecht/include/variant/gpio.h +++ b/src/mainboard/google/jecht/variants/jecht/gpio.c @@ -13,12 +13,9 @@ * GNU General Public License for more details. */ -#ifndef JECHT_GPIO_H -#define JECHT_GPIO_H - #include -static const struct gpio_config mainboard_gpio_config[] = { +const struct gpio_config mainboard_gpio_config[] = { PCH_GPIO_UNUSED, /* 0: UNUSED */ PCH_GPIO_UNUSED, /* 1: UNUSED */ PCH_GPIO_UNUSED, /* 2: UNUSED */ @@ -116,5 +113,3 @@ static const struct gpio_config mainboard_gpio_config[] = { PCH_GPIO_UNUSED, /* 94: UNUSED */ PCH_GPIO_END }; - -#endif diff --git a/src/mainboard/google/jecht/variants/rikku/include/variant/gpio.h b/src/mainboard/google/jecht/variants/rikku/gpio.c similarity index 97% rename from src/mainboard/google/jecht/variants/rikku/include/variant/gpio.h rename to src/mainboard/google/jecht/variants/rikku/gpio.c index f58ad24f67..bc065a03a1 100644 --- a/src/mainboard/google/jecht/variants/rikku/include/variant/gpio.h +++ b/src/mainboard/google/jecht/variants/rikku/gpio.c @@ -13,12 +13,9 @@ * GNU General Public License for more details. */ -#ifndef RIKKU_GPIO_H -#define RIKKU_GPIO_H - #include -static const struct gpio_config mainboard_gpio_config[] = { +const struct gpio_config mainboard_gpio_config[] = { PCH_GPIO_UNUSED, /* 0: UNUSED */ PCH_GPIO_UNUSED, /* 1: UNUSED */ PCH_GPIO_UNUSED, /* 2: UNUSED */ @@ -116,5 +113,3 @@ static const struct gpio_config mainboard_gpio_config[] = { PCH_GPIO_UNUSED, /* 94: UNUSED */ PCH_GPIO_END }; - -#endif diff --git a/src/mainboard/google/jecht/variants/tidus/include/variant/gpio.h b/src/mainboard/google/jecht/variants/tidus/gpio.c similarity index 97% rename from src/mainboard/google/jecht/variants/tidus/include/variant/gpio.h rename to src/mainboard/google/jecht/variants/tidus/gpio.c index 846fe816d4..78aa177679 100644 --- a/src/mainboard/google/jecht/variants/tidus/include/variant/gpio.h +++ b/src/mainboard/google/jecht/variants/tidus/gpio.c @@ -13,12 +13,9 @@ * GNU General Public License for more details. */ -#ifndef TIDUS_GPIO_H -#define TIDUS_GPIO_H - #include -static const struct gpio_config mainboard_gpio_config[] = { +const struct gpio_config mainboard_gpio_config[] = { PCH_GPIO_UNUSED, /* 0: UNUSED */ PCH_GPIO_UNUSED, /* 1: UNUSED */ PCH_GPIO_UNUSED, /* 2: UNUSED */ @@ -116,5 +113,3 @@ static const struct gpio_config mainboard_gpio_config[] = { PCH_GPIO_UNUSED, /* 94: UNUSED */ PCH_GPIO_END }; - -#endif diff --git a/src/mainboard/intel/wtm2/Makefile.inc b/src/mainboard/intel/wtm2/Makefile.inc index 16137462c9..4c944f2773 100644 --- a/src/mainboard/intel/wtm2/Makefile.inc +++ b/src/mainboard/intel/wtm2/Makefile.inc @@ -13,6 +13,8 @@ ## GNU General Public License for more details. ## +romstage-y += gpio.c + romstage-y += chromeos.c ramstage-y += chromeos.c diff --git a/src/mainboard/intel/wtm2/gpio.h b/src/mainboard/intel/wtm2/gpio.c similarity index 97% rename from src/mainboard/intel/wtm2/gpio.h rename to src/mainboard/intel/wtm2/gpio.c index 9e6f2e6445..c81ad10081 100644 --- a/src/mainboard/intel/wtm2/gpio.h +++ b/src/mainboard/intel/wtm2/gpio.c @@ -13,12 +13,9 @@ * GNU General Public License for more details. */ -#ifndef INTEL_WTM2_GPIO_H -#define INTEL_WTM2_GPIO_H - #include -static const struct gpio_config mainboard_gpio_config[] = { +const struct gpio_config mainboard_gpio_config[] = { PCH_GPIO_NATIVE, /* 0: LPSS_UART1_RXD */ PCH_GPIO_NATIVE, /* 1: LPSS_UART1_TXD */ PCH_GPIO_NATIVE, /* 2: LPSS_UART1_RTS_N_R */ @@ -116,5 +113,3 @@ static const struct gpio_config mainboard_gpio_config[] = { PCH_GPIO_NATIVE, /* 94: LPSS_UART0_CTS_N */ PCH_GPIO_END }; - -#endif diff --git a/src/mainboard/intel/wtm2/romstage.c b/src/mainboard/intel/wtm2/romstage.c index 3c9bb36363..de4237d222 100644 --- a/src/mainboard/intel/wtm2/romstage.c +++ b/src/mainboard/intel/wtm2/romstage.c @@ -21,7 +21,6 @@ #include #include #include -#include "gpio.h" void mainboard_romstage_entry(struct romstage_params *rp) { @@ -29,9 +28,6 @@ void mainboard_romstage_entry(struct romstage_params *rp) post_code(0x32); - /* Initialize GPIOs */ - init_gpios(mainboard_gpio_config); - /* Fill out PEI DATA */ memset(&pei_data, 0, sizeof(pei_data)); mainboard_fill_pei_data(&pei_data); diff --git a/src/mainboard/purism/librem_bdw/Makefile.inc b/src/mainboard/purism/librem_bdw/Makefile.inc index 293e186cec..16ce37a95f 100644 --- a/src/mainboard/purism/librem_bdw/Makefile.inc +++ b/src/mainboard/purism/librem_bdw/Makefile.inc @@ -13,5 +13,6 @@ ## GNU General Public License for more details. ## +romstage-y += gpio.c romstage-y += variants/$(VARIANT_DIR)/pei_data.c ramstage-y += variants/$(VARIANT_DIR)/pei_data.c diff --git a/src/mainboard/purism/librem_bdw/gpio.h b/src/mainboard/purism/librem_bdw/gpio.c similarity index 96% rename from src/mainboard/purism/librem_bdw/gpio.h rename to src/mainboard/purism/librem_bdw/gpio.c index 98b09bc45a..510299659e 100644 --- a/src/mainboard/purism/librem_bdw/gpio.h +++ b/src/mainboard/purism/librem_bdw/gpio.c @@ -13,12 +13,9 @@ * GNU General Public License for more details. */ -#ifndef MAINBOARD_GPIO_H -#define MAINBOARD_GPIO_H - #include -static const struct gpio_config mainboard_gpio_config[] = { +const struct gpio_config mainboard_gpio_config[] = { PCH_GPIO_INPUT, /* 0 */ PCH_GPIO_INPUT, /* 1 */ PCH_GPIO_INPUT, /* 2 */ @@ -116,5 +113,3 @@ static const struct gpio_config mainboard_gpio_config[] = { PCH_GPIO_INPUT, /* 94 */ PCH_GPIO_END }; - -#endif diff --git a/src/mainboard/purism/librem_bdw/romstage.c b/src/mainboard/purism/librem_bdw/romstage.c index 2e0ae85b95..6591229621 100644 --- a/src/mainboard/purism/librem_bdw/romstage.c +++ b/src/mainboard/purism/librem_bdw/romstage.c @@ -14,19 +14,14 @@ */ #include -#include #include #include #include -#include "gpio.h" void mainboard_romstage_entry(struct romstage_params *rp) { struct pei_data pei_data; - /* Initialize GPIOs */ - init_gpios(mainboard_gpio_config); - /* Fill out PEI DATA */ memset(&pei_data, 0, sizeof(pei_data)); mainboard_fill_pei_data(&pei_data); diff --git a/src/soc/intel/broadwell/include/soc/gpio.h b/src/soc/intel/broadwell/include/soc/gpio.h index 66820b2184..c0ac13497b 100644 --- a/src/soc/intel/broadwell/include/soc/gpio.h +++ b/src/soc/intel/broadwell/include/soc/gpio.h @@ -193,4 +193,6 @@ int gpio_is_native(int gpio_num); */ unsigned int get_gpios(const int *gpio_num_array); +extern const struct gpio_config mainboard_gpio_config[]; + #endif diff --git a/src/soc/intel/broadwell/romstage/romstage.c b/src/soc/intel/broadwell/romstage/romstage.c index 2531665f1f..7847829ac6 100644 --- a/src/soc/intel/broadwell/romstage/romstage.c +++ b/src/soc/intel/broadwell/romstage/romstage.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include #include @@ -100,6 +101,9 @@ static void romstage_main(uint64_t tsc, uint32_t bist) /* Set CPU frequency to maximum */ set_max_freq(); + /* Initialize GPIOs */ + init_gpios(mainboard_gpio_config); + /* Call into mainboard. */ mainboard_romstage_entry(&rp); From 325865db5683f32d846cc452504da00ec8d53710 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Sun, 12 May 2019 15:25:54 +0200 Subject: [PATCH 044/331] soc/intel/broadwell: Don't use a pointer for pei_data To improve the bootflow, the scope of the pei_data needs to be extended. Change-Id: Ic6d91692a7bf9218b81da5bb36b5b26dabac454e Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/32762 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber Reviewed-by: Matt DeVillier --- src/mainboard/google/auron/romstage.c | 8 ++------ src/mainboard/google/jecht/romstage.c | 8 ++------ src/mainboard/intel/wtm2/romstage.c | 6 +----- src/mainboard/purism/librem_bdw/romstage.c | 6 +----- src/soc/intel/broadwell/include/soc/romstage.h | 4 ++-- src/soc/intel/broadwell/romstage/romstage.c | 5 ++--- 6 files changed, 10 insertions(+), 27 deletions(-) diff --git a/src/mainboard/google/auron/romstage.c b/src/mainboard/google/auron/romstage.c index 5e1a66ac24..497489911e 100644 --- a/src/mainboard/google/auron/romstage.c +++ b/src/mainboard/google/auron/romstage.c @@ -29,15 +29,11 @@ __weak void variant_romstage_entry(struct romstage_params *rp) void mainboard_romstage_entry(struct romstage_params *rp) { - struct pei_data pei_data; - post_code(0x32); /* Fill out PEI DATA */ - memset(&pei_data, 0, sizeof(pei_data)); - mainboard_fill_pei_data(&pei_data); - mainboard_fill_spd_data(&pei_data); - rp->pei_data = &pei_data; + mainboard_fill_pei_data(&rp->pei_data); + mainboard_fill_spd_data(&rp->pei_data); /* Call into the real romstage main with this board's attributes. */ romstage_common(rp); diff --git a/src/mainboard/google/jecht/romstage.c b/src/mainboard/google/jecht/romstage.c index de0ed30575..8d1ae8aca2 100644 --- a/src/mainboard/google/jecht/romstage.c +++ b/src/mainboard/google/jecht/romstage.c @@ -29,15 +29,11 @@ void mainboard_romstage_entry(struct romstage_params *rp) { - struct pei_data pei_data; - post_code(0x32); /* Fill out PEI DATA */ - memset(&pei_data, 0, sizeof(pei_data)); - mainboard_fill_pei_data(&pei_data); - mainboard_fill_spd_data(&pei_data); - rp->pei_data = &pei_data; + mainboard_fill_pei_data(&rp->pei_data); + mainboard_fill_spd_data(&rp->pei_data); /* Call into the real romstage main with this board's attributes. */ romstage_common(rp); diff --git a/src/mainboard/intel/wtm2/romstage.c b/src/mainboard/intel/wtm2/romstage.c index de4237d222..5b8df275d8 100644 --- a/src/mainboard/intel/wtm2/romstage.c +++ b/src/mainboard/intel/wtm2/romstage.c @@ -24,14 +24,10 @@ void mainboard_romstage_entry(struct romstage_params *rp) { - struct pei_data pei_data; - post_code(0x32); /* Fill out PEI DATA */ - memset(&pei_data, 0, sizeof(pei_data)); - mainboard_fill_pei_data(&pei_data); - rp->pei_data = &pei_data; + mainboard_fill_pei_data(&rp->pei_data); romstage_common(rp); } diff --git a/src/mainboard/purism/librem_bdw/romstage.c b/src/mainboard/purism/librem_bdw/romstage.c index 6591229621..5330d191b4 100644 --- a/src/mainboard/purism/librem_bdw/romstage.c +++ b/src/mainboard/purism/librem_bdw/romstage.c @@ -20,12 +20,8 @@ void mainboard_romstage_entry(struct romstage_params *rp) { - struct pei_data pei_data; - /* Fill out PEI DATA */ - memset(&pei_data, 0, sizeof(pei_data)); - mainboard_fill_pei_data(&pei_data); - rp->pei_data = &pei_data; + mainboard_fill_pei_data(&rp->pei_data); /* Initialize memory */ romstage_common(rp); diff --git a/src/soc/intel/broadwell/include/soc/romstage.h b/src/soc/intel/broadwell/include/soc/romstage.h index 31184f9a02..46f29d62df 100644 --- a/src/soc/intel/broadwell/include/soc/romstage.h +++ b/src/soc/intel/broadwell/include/soc/romstage.h @@ -18,13 +18,13 @@ #include #include +#include struct chipset_power_state; -struct pei_data; struct romstage_params { unsigned long bist; struct chipset_power_state *power_state; - struct pei_data *pei_data; + struct pei_data pei_data; }; void mainboard_romstage_entry(struct romstage_params *params); diff --git a/src/soc/intel/broadwell/romstage/romstage.c b/src/soc/intel/broadwell/romstage/romstage.c index 7847829ac6..2a3ac8b8e6 100644 --- a/src/soc/intel/broadwell/romstage/romstage.c +++ b/src/soc/intel/broadwell/romstage/romstage.c @@ -68,7 +68,6 @@ static void romstage_main(uint64_t tsc, uint32_t bist) { struct romstage_params rp = { .bist = bist, - .pei_data = NULL, }; post_code(0x30); @@ -125,7 +124,7 @@ void romstage_common(struct romstage_params *params) timestamp_add_now(TS_BEFORE_INITRAM); - params->pei_data->boot_mode = params->power_state->prev_sleep_state; + params->pei_data.boot_mode = params->power_state->prev_sleep_state; #if CONFIG(ELOG_BOOT_COUNT) if (params->power_state->prev_sleep_state != ACPI_S3) @@ -140,7 +139,7 @@ void romstage_common(struct romstage_params *params) ¶ms->power_state->hsio_checksum); /* Initialize RAM */ - raminit(params->pei_data); + raminit(¶ms->pei_data); timestamp_add_now(TS_AFTER_INITRAM); From 97e9e5622df8b2386b2828da2671018232056035 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Sun, 12 May 2019 13:47:35 +0200 Subject: [PATCH 045/331] soc/intel/broadwell: Clean up the bootflow Call the raminit from a common location instead of from the mainboard specific code. Change-Id: I65d522237a0bb7b2c032536ede10e2cf93c134d8 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/32760 Reviewed-by: Nico Huber Reviewed-by: Matt DeVillier Tested-by: build bot (Jenkins) --- src/mainboard/google/auron/romstage.c | 9 ++- src/mainboard/google/jecht/romstage.c | 10 ++-- src/mainboard/intel/wtm2/romstage.c | 10 ++-- src/mainboard/purism/librem_bdw/romstage.c | 9 +-- .../intel/broadwell/include/soc/romstage.h | 4 +- src/soc/intel/broadwell/romstage/romstage.c | 59 +++++++++---------- 6 files changed, 48 insertions(+), 53 deletions(-) diff --git a/src/mainboard/google/auron/romstage.c b/src/mainboard/google/auron/romstage.c index 497489911e..568c4c819c 100644 --- a/src/mainboard/google/auron/romstage.c +++ b/src/mainboard/google/auron/romstage.c @@ -27,17 +27,16 @@ __weak void variant_romstage_entry(struct romstage_params *rp) { } -void mainboard_romstage_entry(struct romstage_params *rp) +void mainboard_pre_raminit(struct romstage_params *rp) { - post_code(0x32); - /* Fill out PEI DATA */ mainboard_fill_pei_data(&rp->pei_data); mainboard_fill_spd_data(&rp->pei_data); - /* Call into the real romstage main with this board's attributes. */ - romstage_common(rp); +} +void mainboard_post_raminit(struct romstage_params *rp) +{ /* Do variant-specific init */ variant_romstage_entry(rp); } diff --git a/src/mainboard/google/jecht/romstage.c b/src/mainboard/google/jecht/romstage.c index 8d1ae8aca2..86888c82f8 100644 --- a/src/mainboard/google/jecht/romstage.c +++ b/src/mainboard/google/jecht/romstage.c @@ -27,17 +27,15 @@ #include "onboard.h" -void mainboard_romstage_entry(struct romstage_params *rp) +void mainboard_pre_raminit(struct romstage_params *rp) { - post_code(0x32); - /* Fill out PEI DATA */ mainboard_fill_pei_data(&rp->pei_data); mainboard_fill_spd_data(&rp->pei_data); +} - /* Call into the real romstage main with this board's attributes. */ - romstage_common(rp); - +void mainboard_post_raminit(struct romstage_params *rp) +{ if (CONFIG(CHROMEOS)) init_bootmode_straps(); } diff --git a/src/mainboard/intel/wtm2/romstage.c b/src/mainboard/intel/wtm2/romstage.c index 5b8df275d8..f4e336694d 100644 --- a/src/mainboard/intel/wtm2/romstage.c +++ b/src/mainboard/intel/wtm2/romstage.c @@ -22,12 +22,12 @@ #include #include -void mainboard_romstage_entry(struct romstage_params *rp) +void mainboard_pre_raminit(struct romstage_params *rp) { - post_code(0x32); - /* Fill out PEI DATA */ mainboard_fill_pei_data(&rp->pei_data); - - romstage_common(rp); +} + +void mainboard_post_raminit(struct romstage_params *rp) +{ } diff --git a/src/mainboard/purism/librem_bdw/romstage.c b/src/mainboard/purism/librem_bdw/romstage.c index 5330d191b4..0e1ad885b0 100644 --- a/src/mainboard/purism/librem_bdw/romstage.c +++ b/src/mainboard/purism/librem_bdw/romstage.c @@ -18,11 +18,12 @@ #include #include -void mainboard_romstage_entry(struct romstage_params *rp) +void mainboard_pre_raminit(struct romstage_params *rp) { /* Fill out PEI DATA */ mainboard_fill_pei_data(&rp->pei_data); - - /* Initialize memory */ - romstage_common(rp); +} + +void mainboard_post_raminit(struct romstage_params *rp) +{ } diff --git a/src/soc/intel/broadwell/include/soc/romstage.h b/src/soc/intel/broadwell/include/soc/romstage.h index 46f29d62df..d65692ae23 100644 --- a/src/soc/intel/broadwell/include/soc/romstage.h +++ b/src/soc/intel/broadwell/include/soc/romstage.h @@ -27,8 +27,8 @@ struct romstage_params { struct pei_data pei_data; }; -void mainboard_romstage_entry(struct romstage_params *params); -void romstage_common(struct romstage_params *params); +void mainboard_pre_raminit(struct romstage_params *params); +void mainboard_post_raminit(struct romstage_params *params); void raminit(struct pei_data *pei_data); diff --git a/src/soc/intel/broadwell/romstage/romstage.c b/src/soc/intel/broadwell/romstage/romstage.c index 2a3ac8b8e6..acbca14a88 100644 --- a/src/soc/intel/broadwell/romstage/romstage.c +++ b/src/soc/intel/broadwell/romstage/romstage.c @@ -103,8 +103,34 @@ static void romstage_main(uint64_t tsc, uint32_t bist) /* Initialize GPIOs */ init_gpios(mainboard_gpio_config); - /* Call into mainboard. */ - mainboard_romstage_entry(&rp); + /* Fill in mainboard pei_date. */ + mainboard_pre_raminit(&rp); + + post_code(0x32); + + timestamp_add_now(TS_BEFORE_INITRAM); + + rp.pei_data.boot_mode = rp.power_state->prev_sleep_state; + + if (CONFIG(ELOG_BOOT_COUNT) + && rp.power_state->prev_sleep_state != ACPI_S3) + boot_count_increment(); + + /* Print ME state before MRC */ + intel_me_status(); + + /* Save ME HSIO version */ + intel_me_hsio_version(&rp.power_state->hsio_version, + &rp.power_state->hsio_checksum); + + /* Initialize RAM */ + raminit(&rp.pei_data); + + timestamp_add_now(TS_AFTER_INITRAM); + + romstage_handoff_init(rp.power_state->prev_sleep_state == ACPI_S3); + + mainboard_post_raminit(&rp); platform_enter_postcar(); } @@ -117,33 +143,4 @@ asmlinkage void bootblock_c_entry_bist(uint64_t base_timestamp, uint32_t bist) romstage_main(base_timestamp, bist); } -/* Entry from the mainboard. */ -void romstage_common(struct romstage_params *params) -{ - post_code(0x32); - - timestamp_add_now(TS_BEFORE_INITRAM); - - params->pei_data.boot_mode = params->power_state->prev_sleep_state; - -#if CONFIG(ELOG_BOOT_COUNT) - if (params->power_state->prev_sleep_state != ACPI_S3) - boot_count_increment(); -#endif - - /* Print ME state before MRC */ - intel_me_status(); - - /* Save ME HSIO version */ - intel_me_hsio_version(¶ms->power_state->hsio_version, - ¶ms->power_state->hsio_checksum); - - /* Initialize RAM */ - raminit(¶ms->pei_data); - - timestamp_add_now(TS_AFTER_INITRAM); - - romstage_handoff_init(params->power_state->prev_sleep_state == ACPI_S3); -} - void __weak mainboard_pre_console_init(void) {} From d1ad37847da61d243f691590005865df505dc31f Mon Sep 17 00:00:00 2001 From: Gaggery Tsai Date: Wed, 8 May 2019 12:11:21 -0700 Subject: [PATCH 046/331] mb/google/poppy/vr/atlas: Add a W/A for Samsung memory init error This patch adds a workaround for Samsung C-die 2G/4G memory chips. For unknown reasons, some boards with Samsung LP3 memory chips could not pass early CS/CMD training. MRC has to change the granularity from 16 ticks to 8 ticks, which implies bad margin with this memory chip. Another way is to enhance the drive strength for CS. This patch is to enhance the drive strength for CS and CMD. Enhancing the drive strength for CMD could gain margin abaout 3 more ticks. Root cause needs to be further investigated with memory vendor. BUG=b:131177542 BRANCH=None TEST=USE=fw_debug emerge-atlas chromeos-mrc coreboot chromeos-bootimage & check the MRC log to ensure correct Rcomp values are passed to MRC. Tested with board ID #8 and #11. Change-Id: I9ea3ceda8dc8bf781063d3c16c7c2d9b44e5ddd6 Signed-off-by: Gaggery Tsai Reviewed-on: https://review.coreboot.org/c/coreboot/+/32695 Tested-by: build bot (Jenkins) Reviewed-by: Caveh Jalali --- src/mainboard/google/poppy/variants/atlas/memory.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/src/mainboard/google/poppy/variants/atlas/memory.c b/src/mainboard/google/poppy/variants/atlas/memory.c index 0b34e72830..022b733398 100644 --- a/src/mainboard/google/poppy/variants/atlas/memory.c +++ b/src/mainboard/google/poppy/variants/atlas/memory.c @@ -13,8 +13,11 @@ * GNU General Public License for more details. */ +#include #include +#define SAMSUNG_C_DIE_2G 10 +#define SAMSUNG_C_DIE_4G 11 /* DQ byte map */ static const u8 dq_map[][12] = { { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0, @@ -34,9 +37,12 @@ static const u16 rcomp_resistor[] = { 200, 81, 162 }; /* Rcomp target */ static const u16 rcomp_target[] = { 100, 40, 40, 23, 40 }; +static const u16 rcomp_target_samsung_c_die[] = { 100, 40, 35, 18, 40 }; void variant_memory_params(struct memory_params *p) { + int spd_index; + p->type = MEMORY_LPDDR3; p->dq_map = dq_map; p->dq_map_size = sizeof(dq_map); @@ -44,6 +50,11 @@ void variant_memory_params(struct memory_params *p) p->dqs_map_size = sizeof(dqs_map); p->rcomp_resistor = rcomp_resistor; p->rcomp_resistor_size = sizeof(rcomp_resistor); - p->rcomp_target = rcomp_target; + spd_index = variant_memory_sku(); + assert(spd_index >= 0); + if (spd_index == SAMSUNG_C_DIE_2G || spd_index == SAMSUNG_C_DIE_4G) + p->rcomp_target = rcomp_target_samsung_c_die; + else + p->rcomp_target = rcomp_target; p->rcomp_target_size = sizeof(rcomp_target); } From cd51d7ced5a4996253c6dfc816ab7ef82533b2da Mon Sep 17 00:00:00 2001 From: Caveh Jalali Date: Mon, 13 May 2019 20:55:06 -0700 Subject: [PATCH 047/331] mb/google/poppy/variant/atlas: Add SPDs for Samsung D-die chips This adds the SPDs for Samsung D-die 16Gbit and 32Gbit LPDDR3-2133 chips. BUG=b:132206809 TEST=boots on atlas with C-die and D-die memory chips localhost ~ # mosys memory spd print all 0 | LPDDR3 | SO-DIMM 1 | LPDDR3 | SO-DIMM 0 | 1-78: Samsung | 00000000 | K4EBE304ED-EGCG 1 | 1-78: Samsung | 00000000 | K4EBE304ED-EGCG 0 | 8192 | 2 | 64 1 | 8192 | 2 | 64 0 | LPDDR3-800, LPDDR3-1066, LPDDR3-1333, LPDDR3-1600, LPDDR3-1866, LPDDR3-2133 1 | LPDDR3-800, LPDDR3-1066, LPDDR3-1333, LPDDR3-1600, LPDDR3-1866, LPDDR3-2133 localhost ~ # Change-Id: I8ba000aeeb77f07d7f18bda86b3c07f5b50478b8 Signed-off-by: Caveh Jalali Reviewed-on: https://review.coreboot.org/c/coreboot/+/32780 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- .../spd/samsung_dimm_K4E6E304ED-EGCG.spd.hex | 16 ++++++++++++++++ .../spd/samsung_dimm_K4EBE304ED-EGCG.spd.hex | 16 ++++++++++++++++ .../google/poppy/variants/atlas/Makefile.inc | 2 ++ 3 files changed, 34 insertions(+) create mode 100644 src/mainboard/google/poppy/spd/samsung_dimm_K4E6E304ED-EGCG.spd.hex create mode 100644 src/mainboard/google/poppy/spd/samsung_dimm_K4EBE304ED-EGCG.spd.hex diff --git a/src/mainboard/google/poppy/spd/samsung_dimm_K4E6E304ED-EGCG.spd.hex b/src/mainboard/google/poppy/spd/samsung_dimm_K4E6E304ED-EGCG.spd.hex new file mode 100644 index 0000000000..a1dc212a9f --- /dev/null +++ b/src/mainboard/google/poppy/spd/samsung_dimm_K4E6E304ED-EGCG.spd.hex @@ -0,0 +1,16 @@ +91 20 F1 03 05 19 05 0B 03 11 01 08 08 00 40 55 +78 78 90 50 90 11 50 E0 90 06 3C 3C 01 90 00 00 +00 00 C2 00 00 00 00 A8 00 08 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 80 CE 00 00 00 00 00 00 00 00 00 +4B 34 45 36 45 33 30 34 45 44 2D 45 47 43 47 20 +20 20 00 00 80 CE 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/poppy/spd/samsung_dimm_K4EBE304ED-EGCG.spd.hex b/src/mainboard/google/poppy/spd/samsung_dimm_K4EBE304ED-EGCG.spd.hex new file mode 100644 index 0000000000..e59d8286d5 --- /dev/null +++ b/src/mainboard/google/poppy/spd/samsung_dimm_K4EBE304ED-EGCG.spd.hex @@ -0,0 +1,16 @@ +91 20 F1 03 05 1A 05 0A 03 11 01 08 08 00 40 55 +78 78 90 50 90 11 50 E0 90 06 3C 3C 01 90 00 00 +00 00 C2 00 00 00 00 A8 00 08 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 80 CE 00 00 00 00 00 00 00 00 00 +4B 34 45 42 45 33 30 34 45 44 2D 45 47 43 47 20 +20 20 00 00 80 CE 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/poppy/variants/atlas/Makefile.inc b/src/mainboard/google/poppy/variants/atlas/Makefile.inc index 06776ffd4a..397ef687e9 100644 --- a/src/mainboard/google/poppy/variants/atlas/Makefile.inc +++ b/src/mainboard/google/poppy/variants/atlas/Makefile.inc @@ -12,6 +12,8 @@ SPD_SOURCES += micron_dimm_MT52L256M32D1PF-107 # 0b1001 SPD_SOURCES += samsung_dimm_K4E6E304EC-EGCF # 0b1010 SPD_SOURCES += samsung_dimm_K4EBE304EC-EGCF # 0b1011 SPD_SOURCES += nayna_dimm_NT6CL256T32CM-H1 # 0b1100 +SPD_SOURCES += samsung_dimm_K4E6E304ED-EGCG # 0b1101 +SPD_SOURCES += samsung_dimm_K4EBE304ED-EGCG # 0b1110 bootblock-y += gpio.c From 29150c83df8630a817e81eef593dd93fdb37b09f Mon Sep 17 00:00:00 2001 From: Raul E Rangel Date: Tue, 23 Apr 2019 16:02:15 -0600 Subject: [PATCH 048/331] soc/amd/stoneyridge: Add ACPI D3Cold support for SD Controller We need to support entering D3Cold from the OS to work around a bug in the SDHC where the data lines get stuck always reading zeros. BUG=b:122749418 TEST=Verified the linux kernel can transition between D3 and D0. Also verified that the device can suspend and resume and continue to have a functioning SD controller after. Change-Id: Ifbf48f20c03a752ce3ff773296b536e92db16a62 Signed-off-by: Raul E Rangel Reviewed-on: https://review.coreboot.org/c/coreboot/+/32433 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth --- src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl | 31 ++++++++++++++++++-- 1 file changed, 28 insertions(+), 3 deletions(-) diff --git a/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl b/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl index 15e4d2f122..1334df11c4 100644 --- a/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl +++ b/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl @@ -56,6 +56,16 @@ Device(SBUS) { /* 0:14.7 - SD Controller */ Device(SDCN) { Name(_ADR, 0x00140007) + + Method(_PS0) { + FDDC(24, 0) + } + Method(_PS3) { + FDDC(24, 3) + } + Method(_PSC) { + Return(SDTD) + } } /* end SDCN */ Name(CRES, ResourceTemplate() { @@ -286,8 +296,9 @@ Field( SMIC, ByteAcc, NoLock, Preserve) { offset (0x1e70), /* SD D3 Control */ SDTD, 2, , 1, + SDPD, 1, + , 1, , 1, - , 2, SDRT, 1, SDSC, 1, @@ -433,7 +444,14 @@ Method(FDDC, 2, Serialized) /* todo Case(15) { STD0()} */ /* SATA */ Case(18) { U2D0()} /* EHCI */ Case(23) { U3D0()} /* XHCI */ -/* todo Case(24) { SDD0()} */ /* SD */ + Case(24) { /* SD */ + Store(0x00, SDTD) + Store(One, SDPD) + Store(SDDS, Local0) + while(LNotEqual(Local0,0x7)) { + Store(SDDS, Local0) + } + } } } else { /* put device into D3cold */ @@ -489,7 +507,14 @@ Method(FDDC, 2, Serialized) /* todo Case(15) { STD3()} */ /* SATA */ Case(18) { U2D3()} /* EHCI */ Case(23) { U3D3()} /* XHCI */ -/* todo Case(24) { SDD3()} */ /* SD */ + Case(24) { /* SD */ + Store(Zero, SDPD) + Store(SDDS, Local0) + while(LNotEqual(Local0,0x0)) { + Store(SDDS, Local0) + } + Store(0x03, SDTD) + } } /* Turn off Power */ if(LEqual(I0TD, 3)) { From df85bf79189a0a1a682f5731f2c332acfa28055c Mon Sep 17 00:00:00 2001 From: Alan Green Date: Thu, 2 May 2019 18:50:05 +1000 Subject: [PATCH 049/331] Documentation/lessons/lesson2.md: Add reminder to check username set If username is not set, then the ssh option is not available. This was initially confusing for me. Signed-off-by: Alan Green Change-Id: I731c29a1daa9f8c298710471c7d1fe758b059d08 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32540 Tested-by: build bot (Jenkins) Reviewed-by: Lance Zhao Reviewed-by: Marshall Dawson Reviewed-by: Mike Banon --- Documentation/lessons/lesson2.md | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/lessons/lesson2.md b/Documentation/lessons/lesson2.md index d6f800c290..626e76e74a 100644 --- a/Documentation/lessons/lesson2.md +++ b/Documentation/lessons/lesson2.md @@ -68,6 +68,10 @@ If you are using SSH keys, select **ssh** from the tabs under "Project coreboot" and run the "clone with commit-msg hook" command that's provided. This should prompt you for your id_rsa passphrase, if you previously set one. +**Note:** if the **ssh** option is not showing, check that you have a username +set. Click the profile picture at the top right and select **User Settings**, +then set your username in the **Profile** section. + If you are using HTTP, instead, select **http** from the tabs under "Project coreboot" and run the command that appears From 9a8c5e7ac0f559898c4d5fcb99a51e4dc472f51f Mon Sep 17 00:00:00 2001 From: Christian Walter Date: Mon, 6 May 2019 17:50:57 +0200 Subject: [PATCH 050/331] util/inteltool: Add Kabylake E3-1200 Support Change-Id: I5c55102d7ce15dbb708e9433500ebd1ed53179ad Signed-off-by: Christian Walter Reviewed-on: https://review.coreboot.org/c/coreboot/+/32619 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph --- util/inteltool/cpu.c | 318 +++++++++++++++++++++++++++++++++++ util/inteltool/gpio.c | 1 + util/inteltool/gpio_groups.c | 1 + util/inteltool/inteltool.c | 2 + util/inteltool/inteltool.h | 1 + util/inteltool/memory.c | 1 + util/inteltool/pcie.c | 3 + util/inteltool/powermgt.c | 1 + 8 files changed, 328 insertions(+) diff --git a/util/inteltool/cpu.c b/util/inteltool/cpu.c index c40a3bd22b..ef2df3cd00 100644 --- a/util/inteltool/cpu.c +++ b/util/inteltool/cpu.c @@ -1529,6 +1529,323 @@ int print_intel_core_msrs(void) { 0x416, "MSR_MC5_ADDR" }, }; +/* + * Intel 64 and IA-32 Architectures Software Developers Manual Conbined Volumes + * Page 4668 + * + * The following two tables are for the Kaby Lake processors + * 06_9EH. + * + */ + + static const msr_entry_t model96ex_global_msrs[] = { + { 0x0000, "IA32_PLATFORM_ID"}, + { 0x0080, "MSR_TRACE_HUB_STH_ACPIBAR_BASE"}, + { 0x00CE, "MSR_PLATFORM_INFO"}, + { 0x0198, "IA32_PERF_STATUS"}, + { 0x01A2, "MSR_TEMPERATURE_TARGET"}, + { 0x01AD, "MSR_TURBO_RATIO_LIMIT"}, + { 0x0284, "IA32_MC4_CTL2"}, + { 0x02F4, "MSR_UNCORE_PRMRR_PHYS_BASE"}, + { 0x02F5, "MSR_UNCORE_PRMRR_PHYS_MASK"}, + { 0x0394, "MSR_UNC_PERF_FIXED_CTRL"}, + { 0x0395, "MSR_UNC_PERF_FIXED_CTR"}, + { 0x060A, "MSR_PKGC3_IRTL"}, + { 0x060B, "MSR_PKGC6_IRTL"}, + { 0x060D, "MSR_PKG_C2_RESIDENCY"}, + { 0x0610, "MSR_PKG_POWER_LIMIT"}, + { 0x0614, "MSR_PKG_POWER_INFO"}, + { 0x0620, "MSR_RING_RATIO_LIMIT"}, + { 0x0638, "MSR_PP0_POWER_LIMIT"}, + { 0x064F, "MSR_CORE_PERF_LIMIT_REASONS"}, + { 0x0652, "MSR_PKG_HDC_CONFIG"}, + { 0x065C, "MSR_PLATFORM_POWER_LIMIT"}, + { 0x06B0, "MSR_GRAPHICS_PERF_LIMIT_REASONS"}, + { 0x06B1, "MSR_RING_PERF_LIMIT_REASONS"}, + { 0x0770, "IA32_PM_ENABLE"}, + { 0x0DB0, "IA32_PKG_HDC_CTL"}, + { 0x03B0, "MSR_UNC_ARB_PERFCTR0"}, + { 0x03B1, "MSR_UNC_ARB_PERFCTR1"}, + { 0x03B2, "MSR_UNC_ARB_PERFEVTSEL0"}, + { 0x03B3, "MSR_UNC_ARB_PERFEVTSEL1"}, + { 0x0700, "MSR_UNC_CBO_0_PERFCTR0"}, + { 0x0701, "MSR_UNC_CBO_0_PERFCTR1"}, + { 0x0706, "MSR_UNC_CBO_0_PERFEVTSEL0"}, + { 0x0707, "MSR_UNC_CBO_0_PERFEVTSEL1"}, + { 0x0710, "MSR_UNC_CBO_1_PERFCTR0"}, + { 0x0711, "MSR_UNC_CBO_1_PERFCTR1"}, + { 0x0716, "MSR_UNC_CBO_1_PERFEVTSEL0"}, + { 0x0717, "MSR_UNC_CBO_1_PERFEVTSEL1"}, + { 0x0720, "MSR_UNC_CBO_2_PERFCTR0"}, + { 0x0721, "MSR_UNC_CBO_2_PERFCTR1"}, + { 0x0726, "MSR_UNC_CBO_2_PERFEVTSEL0"}, + { 0x0727, "MSR_UNC_CBO_2_PERFEVTSEL1"}, + { 0x0730, "MSR_UNC_CBO_3_PERFCTR0"}, + { 0x0731, "MSR_UNC_CBO_3_PERFCTR1"}, + { 0x0736, "MSR_UNC_CBO_3_PERFEVTSEL0"}, + { 0x0737, "MSR_UNC_CBO_3_PERFEVTSEL1"}, + { 0x0E01, "MSR_UNC_PERF_GLOBAL_CTRL"}, + { 0x0E02, "MSR_UNC_PERF_GLOBAL_STATUS"}, + }; + + static const msr_entry_t model96ex_per_core_msrs[] = { + /* Per core MSRs for Sandy Bridge and above */ + { 0x0000, "IA32_P5_MC_ADDR"}, + { 0x0001, "IA32_P5_MC_TYPE"}, + { 0x0006, "IA32_MONITOR_FILTER_SIZE"}, + { 0x0010, "IA32_TIME_STAMP_COUNTER"}, + { 0x001B, "IA32_APIC_BASE"}, + { 0x0034, "MSR_SMI_COUNT"}, + { 0x003A, "IA32_FEATURE_CONTROL"}, + { 0x008B, "IA32_BIOS_SIGN_ID"}, + { 0x00C1, "IA32_PMC0" }, + { 0x00C2, "IA32_PMC1" }, + { 0x00C3, "IA32_PMC2" }, + { 0x00C4, "IA32_PMC3" }, + { 0x00E2, "MSR_PKG_CST_CONFIG_CONTROL" }, + { 0x00E4, "MSR_PMG_IO_CAPTURE_BASE"}, + { 0x00E7, "IA32_MPERF"}, + { 0x00E8, "IA32_APERF"}, + { 0x00FE, "IA32_MTRRCAP"}, + { 0x013C, "MSR_FEATURE_CONFIG"}, + { 0x0174, "IA32_SYSENTER_CS"}, + { 0x0175, "IA32_SYSENTER_ESP"}, + { 0x0176, "IA32_SYSENTER_EIP"}, + { 0x0179, "IA32_MCG_CAP"}, + { 0x017A, "IA32_MCG_STATUS"}, + { 0x0186, "IA32_PERFEVTSEL0"}, + { 0x0187, "IA32_PERFEVTSEL1"}, + { 0x0188, "IA32_PERFEVTSEL2"}, + { 0x0189, "IA32_PERFEVTSEL3"}, + { 0x0199, "IA32_PERF_CTL"}, + { 0x019A, "IA32_CLOCK_MODULATION"}, + { 0x019B, "IA32_THERM_INTERRUPT"}, + { 0x019C, "IA32_THERM_STATUS"}, + { 0x01A0, "IA32_MISC_ENABLE"}, + { 0x01A4, "IA32_MISC_FEATURE_CONTROL"}, + { 0x01A6, "MSR_OFFCORE_RSP_0"}, + { 0x01A7, "MSR_OFFCORE_RSP_1"}, + { 0x01C8, "MSR_LBR_SELECT"}, + { 0x01C9, "MSR_LASTBRANCH_TOS"}, + { 0x01D9, "IA32_DEBUGCTL"}, + { 0x01DD, "MSR_LER_FROM_LIP"}, + { 0x01DE, "MSR_LER_TO_LIP"}, + { 0x01F2, "IA32_SMRR_PHYSBASE"}, + { 0x01F3, "IA32_SMRR_PHYSMASK"}, + { 0x01F4, "MSR_PRMRR_PHYS_BASE"}, + { 0x01F5, "MSR_PRMRR_PHYS_MASK"}, + { 0x01F4, "MSR_PRMRR_PHYS_BASE"}, + { 0x01FB, "MSR_PRMRR_VALID_CONFIG"}, + { 0x01FC, "MSR_POWER_CTL"}, + { 0x0200, "IA32_MTRR_PHYSBASE0"}, + { 0x0201, "IA32_MTRR_PHYSBASE0"}, + { 0x0202, "IA32_MTRR_PHYSBASE1"}, + { 0x0203, "IA32_MTRR_PHYSBASE1"}, + { 0x0204, "IA32_MTRR_PHYSBASE2"}, + { 0x0205, "IA32_MTRR_PHYSBASE2"}, + { 0x0206, "IA32_MTRR_PHYSBASE3"}, + { 0x0207, "IA32_MTRR_PHYSBASE3"}, + { 0x0208, "IA32_MTRR_PHYSBASE4"}, + { 0x0209, "IA32_MTRR_PHYSBASE4"}, + { 0x020A, "IA32_MTRR_PHYSBASE5"}, + { 0x020B, "IA32_MTRR_PHYSBASE5"}, + { 0x020C, "IA32_MTRR_PHYSBASE6"}, + { 0x020D, "IA32_MTRR_PHYSBASE6"}, + { 0x020E, "IA32_MTRR_PHYSBASE7"}, + { 0x020F, "IA32_MTRR_PHYSBASE7"}, + { 0x0210, "IA32_MTRR_PHYSBASE8"}, + { 0x0211, "IA32_MTRR_PHYSBASE8"}, + { 0x0212, "IA32_MTRR_PHYSBASE9"}, + { 0x0213, "IA32_MTRR_PHYSBASE9"}, + { 0x0250, "IA32_MTRR_FIX64K_00000"}, + { 0x0258, "IA32_MTRR_FIX16K_80000"}, + { 0x0259, "IA32_MTRR_FIX16K_A0000"}, + { 0x0268, "IA32_MTRR_FIX4K_C0000"}, + { 0x0269, "IA32_MTRR_FIX4K_C8000"}, + { 0x026A, "IA32_MTRR_FIX4K_D0000"}, + { 0x026B, "IA32_MTRR_FIX4K_D8000"}, + { 0x026C, "IA32_MTRR_FIX4K_E0000"}, + { 0x026D, "IA32_MTRR_FIX4K_E8000"}, + { 0x026E, "IA32_MTRR_FIX4K_F0000"}, + { 0x026F, "IA32_MTRR_FIX4K_F8000"}, + { 0x0277, "IA32_PAT"}, + { 0x0280, "IA32_MC0_CTL2"}, + { 0x0281, "IA32_MC1_CTL2"}, + { 0x0282, "IA32_MC2_CTL2"}, + { 0x0283, "IA32_MC3_CTL2"}, + { 0x02FF, "IA32_MTRR_DEF_TYPE"}, + { 0x0309, "IA32_FIXED_CTR0"}, + { 0x030A, "IA32_FIXED_CTR1"}, + { 0x030B, "IA32_FIXED_CTR2"}, + { 0x0345, "IA32_PERF_CAPABILITIES"}, + { 0x038D, "IA32_FIXED_CTR_CTRL"}, + { 0x038E, "IA32_PERF_GLOBAL_STATUS"}, + { 0x038F, "IA32_PERF_GLOBAL_CTRL"}, + { 0x0390, "IA32_PERF_GLOBAL_STATUS_RESET"}, + { 0x0391, "IA32_PERF_GLOBAL_STATUS_SET"}, + { 0x03F1, "MSR_PEBS_ENABLE"}, + { 0x03F6, "MSR_PEBS_LD_LAT"}, + { 0x03F7, "MSR_PEBS_FRONTEND"}, + { 0x03FC, "MSR_CORE_C3_RESIDENCY"}, + { 0x03FD, "MSR_CORE_C6_RESIDENCY"}, + { 0x03FE, "MSR_CORE_C7_RESIDENCY"}, + { 0x0400, "IA32_MC0_CTL" }, + { 0x0401, "IA32_MC0_STATUS" }, + { 0x0402, "IA32_MC0_ADDR" }, + { 0x0403, "IA32_MC0_MISC" }, + { 0x0404, "IA32_MC1_CTL" }, + { 0x0405, "IA32_MC1_STATUS" }, + { 0x0406, "IA32_MC1_ADDR" }, + { 0x0407, "IA32_MC1_MISC" }, + { 0x0408, "IA32_MC2_CTL" }, + { 0x0409, "IA32_MC2_STATUS" }, + { 0x040a, "IA32_MC2_ADDR" }, + { 0x040c, "IA32_MC3_CTL" }, + { 0x040d, "IA32_MC3_STATUS" }, + { 0x040e, "IA32_MC3_ADDR" }, + { 0x0410, "IA32_MC4_CTL" }, + { 0x0411, "IA32_MC4_STATUS" }, + { 0x0480, "IA32_VMX_BASIC" }, + { 0x0481, "IA32_VMX_PINBASED_CTLS" }, + { 0x0482, "IA32_VMX_PROCBASED_CTLS" }, + { 0x0483, "IA32_VMX_EXIT_CTLS" }, + { 0x0484, "IA32_VMX_ENTRY_CTLS" }, + { 0x0485, "IA32_VMX_MISC" }, + { 0x0486, "IA32_VMX_CR0_FIXED0" }, + { 0x0487, "IA32_VMX_CR0_FIXED1" }, + { 0x0488, "IA32_VMX_CR4_FIXED0" }, + { 0x0489, "IA32_VMX_CR4_FIXED1" }, + { 0x048a, "IA32_VMX_VMCS_ENUM" }, + { 0x048b, "IA32_VMX_PROCBASED_CTLS2" }, + { 0x048c, "IA32_VMX_EPT_VPID_ENUM" }, + { 0x048d, "IA32_VMX_TRUE_PINBASED_CTLS" }, + { 0x048e, "IA32_VMX_TRUE_PROCBASED_CTLS" }, + { 0x048f, "IA32_VMX_TRUE_EXIT_CTLS" }, + { 0x0490, "IA32_VMX_TRUE_ENTRY_CTLS" }, + { 0x04C1, "IA32_A_PMC0"}, + { 0x04C2, "IA32_A_PMC1"}, + { 0x04C3, "IA32_A_PMC2"}, + { 0x04C4, "IA32_A_PMC3"}, + { 0x0500, "IA32_SGX_SVN_STATUS"}, + { 0x0560, "IA32_RTIT_OUTPUT_BASE"}, + { 0x0561, "IA32_RTIT_OUTPUT_MASK_PTRS"}, + { 0x0570, "IA32_RTIT_CTL"}, + { 0x0571, "IA32_RTIT_STATUS"}, + { 0x0572, "IA32_RTIT_CR3_MATCH"}, + { 0x0580, "IA32_RTIT_ADDR0_A"}, + { 0x0581, "IA32_RTIT_ADDR0_B"}, + { 0x0582, "IA32_RTIT_ADDR1_A"}, + { 0x0583, "IA32_RTIT_ADDR1_B"}, + { 0x0600, "IA32_DS_AREA" }, + { 0x064E, "MSR_PPERF"}, + { 0x0653, "MSR_CORE_HDC_RESIDENCY"}, + { 0x0680, "MSR_LASTBRANCH_0_FROM_IP" }, + { 0x0681, "MSR_LASTBRANCH_1_FROM_IP" }, + { 0x0682, "MSR_LASTBRANCH_2_FROM_IP" }, + { 0x0683, "MSR_LASTBRANCH_3_FROM_IP" }, + { 0x0684, "MSR_LASTBRANCH_4_FROM_IP" }, + { 0x0685, "MSR_LASTBRANCH_5_FROM_IP" }, + { 0x0686, "MSR_LASTBRANCH_6_FROM_IP" }, + { 0x0687, "MSR_LASTBRANCH_7_FROM_IP" }, + { 0x0688, "MSR_LASTBRANCH_8_FROM_IP" }, + { 0x0689, "MSR_LASTBRANCH_9_FROM_IP" }, + { 0x068a, "MSR_LASTBRANCH_10_FROM_IP" }, + { 0x068b, "MSR_LASTBRANCH_11_FROM_IP" }, + { 0x068c, "MSR_LASTBRANCH_12_FROM_IP" }, + { 0x068d, "MSR_LASTBRANCH_13_FROM_IP" }, + { 0x068e, "MSR_LASTBRANCH_14_FROM_IP" }, + { 0x068f, "MSR_LASTBRANCH_15_FROM_IP" }, + { 0x0690, "MSR_LASTBRANCH_16_FROM_IP" }, + { 0x0691, "MSR_LASTBRANCH_17_FROM_IP" }, + { 0x0692, "MSR_LASTBRANCH_18_FROM_IP" }, + { 0x0693, "MSR_LASTBRANCH_19_FROM_IP" }, + { 0x0694, "MSR_LASTBRANCH_20_FROM_IP" }, + { 0x0695, "MSR_LASTBRANCH_21_FROM_IP" }, + { 0x0696, "MSR_LASTBRANCH_22_FROM_IP" }, + { 0x0697, "MSR_LASTBRANCH_23_FROM_IP" }, + { 0x0698, "MSR_LASTBRANCH_24_FROM_IP" }, + { 0x0699, "MSR_LASTBRANCH_25_FROM_IP" }, + { 0x069A, "MSR_LASTBRANCH_26_FROM_IP" }, + { 0x069B, "MSR_LASTBRANCH_27_FROM_IP" }, + { 0x069C, "MSR_LASTBRANCH_28_FROM_IP" }, + { 0x069D, "MSR_LASTBRANCH_29_FROM_IP" }, + { 0x069E, "MSR_LASTBRANCH_30_FROM_IP" }, + { 0x069F, "MSR_LASTBRANCH_31_FROM_IP" }, + { 0x06c0, "MSR_LASTBRANCH_0_TO_IP" }, + { 0x06c1, "MSR_LASTBRANCH_1_TO_IP" }, + { 0x06c2, "MSR_LASTBRANCH_2_TO_IP" }, + { 0x06c3, "MSR_LASTBRANCH_3_TO_IP" }, + { 0x06c4, "MSR_LASTBRANCH_4_TO_IP" }, + { 0x06c5, "MSR_LASTBRANCH_5_TO_IP" }, + { 0x06c6, "MSR_LASTBRANCH_6_TO_IP" }, + { 0x06c7, "MSR_LASTBRANCH_7_TO_IP" }, + { 0x06c8, "MSR_LASTBRANCH_8_TO_IP" }, + { 0x06c9, "MSR_LASTBRANCH_9_TO_IP" }, + { 0x06ca, "MSR_LASTBRANCH_10_TO_IP" }, + { 0x06cb, "MSR_LASTBRANCH_11_TO_IP" }, + { 0x06cc, "MSR_LASTBRANCH_12_TO_IP" }, + { 0x06cd, "MSR_LASTBRANCH_13_TO_IP" }, + { 0x06ce, "MSR_LASTBRANCH_14_TO_IP" }, + { 0x06cf, "MSR_LASTBRANCH_15_TO_IP" }, + { 0x06d0, "MSR_LASTBRANCH_16_FROM_IP" }, + { 0x06d1, "MSR_LASTBRANCH_17_FROM_IP" }, + { 0x06d2, "MSR_LASTBRANCH_18_FROM_IP" }, + { 0x06d3, "MSR_LASTBRANCH_19_FROM_IP" }, + { 0x06d4, "MSR_LASTBRANCH_20_FROM_IP" }, + { 0x06d5, "MSR_LASTBRANCH_21_FROM_IP" }, + { 0x06d6, "MSR_LASTBRANCH_22_FROM_IP" }, + { 0x06d7, "MSR_LASTBRANCH_23_FROM_IP" }, + { 0x06d8, "MSR_LASTBRANCH_24_FROM_IP" }, + { 0x06d9, "MSR_LASTBRANCH_25_FROM_IP" }, + { 0x06da, "MSR_LASTBRANCH_26_FROM_IP" }, + { 0x06db, "MSR_LASTBRANCH_27_FROM_IP" }, + { 0x06dc, "MSR_LASTBRANCH_28_FROM_IP" }, + { 0x06dd, "MSR_LASTBRANCH_29_FROM_IP" }, + { 0x06de, "MSR_LASTBRANCH_30_FROM_IP" }, + { 0x06df, "MSR_LASTBRANCH_31_FROM_IP" }, + { 0x06E0, "IA32_TSC_DEADLINE"}, + { 0x0771, "IA32_HWP_CAPABILITIES"}, + { 0x0773, "IA32_HWP_INTERRUPT"}, + { 0x0774, "IA32_HWP_REQUEST"}, + { 0x0777, "IA32_HWP_STATUS"}, + { 0x0D90, "IA32_BNDCFGS"}, + { 0x0DA0, "IA32_XSS"}, + { 0x0DB1, "IA32_PM_CTL1"}, + { 0x0DB2, "IA32_THREAD_STALL"}, + { 0x0DC0, "IA32_LBR_INFO_0"}, + { 0x0DC1, "IA32_LBR_INFO_1"}, + { 0x0DC2, "IA32_LBR_INFO_2"}, + { 0x0DC3, "IA32_LBR_INFO_3"}, + { 0x0DC4, "IA32_LBR_INFO_4"}, + { 0x0DC5, "IA32_LBR_INFO_5"}, + { 0x0DC6, "IA32_LBR_INFO_6"}, + { 0x0DC7, "IA32_LBR_INFO_7"}, + { 0x0DC8, "IA32_LBR_INFO_8"}, + { 0x0DC9, "IA32_LBR_INFO_9"}, + { 0x0DCA, "IA32_LBR_INFO_10"}, + { 0x0DCB, "IA32_LBR_INFO_11"}, + { 0x0DCC, "IA32_LBR_INFO_12"}, + { 0x0DCD, "IA32_LBR_INFO_13"}, + { 0x0DCE, "IA32_LBR_INFO_14"}, + { 0x0DCF, "IA32_LBR_INFO_15"}, + { 0x0DD0, "IA32_LBR_INFO_16"}, + { 0x0DD1, "IA32_LBR_INFO_17"}, + { 0x0DD2, "IA32_LBR_INFO_18"}, + { 0x0DD3, "IA32_LBR_INFO_19"}, + { 0x0DD4, "IA32_LBR_INFO_20"}, + { 0x0DD5, "IA32_LBR_INFO_21"}, + { 0x0DD6, "IA32_LBR_INFO_22"}, + { 0x0DD7, "IA32_LBR_INFO_23"}, + { 0x0DD8, "IA32_LBR_INFO_24"}, + { 0x0DD9, "IA32_LBR_INFO_25"}, + { 0x0DDA, "IA32_LBR_INFO_26"}, + { 0x0DDB, "IA32_LBR_INFO_27"}, + { 0x0DDC, "IA32_LBR_INFO_28"}, + { 0x0DDD, "IA32_LBR_INFO_29"}, + { 0x0DDE, "IA32_LBR_INFO_30"}, + { 0x0DDF, "IA32_LBR_INFO_31"}, + }; + typedef struct { unsigned int model; const msr_entry_t *global_msrs; @@ -1547,6 +1864,7 @@ int print_intel_core_msrs(void) { 0x00f60, modelf6x_global_msrs, ARRAY_SIZE(modelf6x_global_msrs), modelf6x_per_core_msrs, ARRAY_SIZE(modelf6x_per_core_msrs) }, { 0x106c0, model6_atom_global_msrs, ARRAY_SIZE(model6_atom_global_msrs), model6_atom_per_core_msrs, ARRAY_SIZE(model6_atom_per_core_msrs) }, { 0x20650, model20650_global_msrs, ARRAY_SIZE(model20650_global_msrs), model20650_per_core_msrs, ARRAY_SIZE(model20650_per_core_msrs) }, + { 0x906e0, model96ex_global_msrs, ARRAY_SIZE(model96ex_global_msrs), model96ex_per_core_msrs, ARRAY_SIZE(model96ex_per_core_msrs) }, { CPUID_BAYTRAIL, silvermont_global_msrs, ARRAY_SIZE(silvermont_global_msrs), silvermont_per_core_msrs, ARRAY_SIZE(silvermont_per_core_msrs) }, /* Baytrail */ diff --git a/util/inteltool/gpio.c b/util/inteltool/gpio.c index c946d5c65f..e48a2c51f5 100644 --- a/util/inteltool/gpio.c +++ b/util/inteltool/gpio.c @@ -1026,6 +1026,7 @@ int print_gpios(struct pci_dev *sb, int show_all, int show_diffs) break; case PCI_DEVICE_ID_INTEL_B150: case PCI_DEVICE_ID_INTEL_CM236: + case PCI_DEVICE_ID_INTEL_C236: case PCI_DEVICE_ID_INTEL_APL_LPC: case PCI_DEVICE_ID_INTEL_DNV_LPC: case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_PRE: diff --git a/util/inteltool/gpio_groups.c b/util/inteltool/gpio_groups.c index 21e2de93d5..3c0fedbfbf 100644 --- a/util/inteltool/gpio_groups.c +++ b/util/inteltool/gpio_groups.c @@ -1774,6 +1774,7 @@ void print_gpio_groups(struct pci_dev *const sb) switch (sb->device_id) { case PCI_DEVICE_ID_INTEL_B150: case PCI_DEVICE_ID_INTEL_CM236: + case PCI_DEVICE_ID_INTEL_C236: community_count = ARRAY_SIZE(sunrise_communities); communities = sunrise_communities; pcr_init(sb); diff --git a/util/inteltool/inteltool.c b/util/inteltool/inteltool.c index 40e7646450..7e02510752 100644 --- a/util/inteltool/inteltool.c +++ b/util/inteltool/inteltool.c @@ -135,6 +135,8 @@ static const struct { "7th generation (Kaby Lake family) Core Processor (Mobile)" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_U_Q, "7th generation (Kaby Lake family) Core Processor (Mobile)" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_E3, + "7th generation (Kaby Lake family) Core Processor Xeon E3-1200" }, /* Southbridges (LPC controllers) */ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371XX, "371AB/EB/MB" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10, "ICH10" }, diff --git a/util/inteltool/inteltool.h b/util/inteltool/inteltool.h index 6aec3879c2..483c93099e 100644 --- a/util/inteltool/inteltool.h +++ b/util/inteltool/inteltool.h @@ -275,6 +275,7 @@ static inline uint32_t inl(unsigned port) #define PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_U 0x5904 /* Kabylake (Mobile) */ #define PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_Y 0x590C /* Kabylake (Mobile) */ #define PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_U_Q 0x5914 /* Kabylake (Mobile) */ +#define PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_E3 0x5918 /* Kabylake Xeon E3 */ /* Intel GPUs */ diff --git a/util/inteltool/memory.c b/util/inteltool/memory.c index f0c756221b..222ac8afb0 100644 --- a/util/inteltool/memory.c +++ b/util/inteltool/memory.c @@ -225,6 +225,7 @@ int print_mchbar(struct pci_dev *nb, struct pci_access *pacc, const char *dump_s case PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_U: case PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_Y: case PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_U_Q: + case PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_E3: mchbar_phys = pci_read_long(nb, 0x48); mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32; mchbar_phys &= 0x0000007fffff8000UL; /* 38:15 */ diff --git a/util/inteltool/pcie.c b/util/inteltool/pcie.c index 5b35dbdde9..33644ab9db 100644 --- a/util/inteltool/pcie.c +++ b/util/inteltool/pcie.c @@ -270,6 +270,7 @@ int print_epbar(struct pci_dev *nb) case PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_U: case PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_Y: case PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_U_Q: + case PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_E3: epbar_phys = pci_read_long(nb, 0x40) & 0xfffffffe; epbar_phys |= ((uint64_t)pci_read_long(nb, 0x44)) << 32; break; @@ -395,6 +396,7 @@ int print_dmibar(struct pci_dev *nb) case PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_U: case PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_Y: case PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_U_Q: + case PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_E3: dmi_registers = skylake_dmi_registers; size = ARRAY_SIZE(skylake_dmi_registers); dmibar_phys = pci_read_long(nb, 0x68); @@ -504,6 +506,7 @@ int print_pciexbar(struct pci_dev *nb) case PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_U: case PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_Y: case PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_U_Q: + case PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_E3: pciexbar_reg = pci_read_long(nb, 0x60); pciexbar_reg |= ((uint64_t)pci_read_long(nb, 0x64)) << 32; break; diff --git a/util/inteltool/powermgt.c b/util/inteltool/powermgt.c index 675e31a1da..8da12d2826 100644 --- a/util/inteltool/powermgt.c +++ b/util/inteltool/powermgt.c @@ -836,6 +836,7 @@ int print_pmbase(struct pci_dev *sb, struct pci_access *pacc) break; case PCI_DEVICE_ID_INTEL_CM236: + case PCI_DEVICE_ID_INTEL_C236: acpi = pci_get_dev(pacc, sb->domain, sb->bus, sb->dev, 2); if (!acpi) { printf("PMC device not found.\n"); From dcfff3739be63c2d42e16860243d7bec98c7ba44 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Mon, 31 Dec 2018 10:45:19 +0100 Subject: [PATCH 051/331] src/superio/ite/common: Prepare for ITE IT8786E SuperIO MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Introduce 7bit Slope PWM registers. New ITE SuperIO may have contiguous 7bit values for PWM slope. Add option to enable External Sensor SMBus Host. Update/add registers macros for IT8786E-F which are not backwards compatible. Change-Id: I68fbfe62dfa05d0c166abaefbdc2ab873114b236 Signed-off-by: Michał Żygowski Reviewed-on: https://review.coreboot.org/c/coreboot/+/30553 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/superio/ite/common/Kconfig | 7 +++++++ src/superio/ite/common/env_ctrl.c | 17 +++++++++++++++-- src/superio/ite/common/env_ctrl.h | 19 +++++++++++++++++++ src/superio/ite/common/env_ctrl_chip.h | 5 +++++ 4 files changed, 46 insertions(+), 2 deletions(-) diff --git a/src/superio/ite/common/Kconfig b/src/superio/ite/common/Kconfig index 6c78741723..55f765004c 100644 --- a/src/superio/ite/common/Kconfig +++ b/src/superio/ite/common/Kconfig @@ -51,4 +51,11 @@ config SUPERIO_ITE_ENV_CTRL_5FANS bool help ITE FAN controller has 5 independent outputs. + +config SUPERIO_ITE_ENV_CTRL_7BIT_SLOPE_REG + bool + help + Slope PWM registers have no separate BIT6 and are set directly by + 7-bit values instead. + endif diff --git a/src/superio/ite/common/env_ctrl.c b/src/superio/ite/common/env_ctrl.c index 57896e0c01..1b93036845 100644 --- a/src/superio/ite/common/env_ctrl.c +++ b/src/superio/ite/common/env_ctrl.c @@ -4,6 +4,7 @@ * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. * Copyright (C) 2016 secunet Security Networks AG * Copyright (C) 2019 Protectli + * Copyright (C) 2019 Libretrend LDA * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -165,9 +166,14 @@ static void fan_smartconfig(const u16 base, const u8 fan, pwm_ctrl |= ITE_EC_FAN_CTL_TEMPIN(conf->tmpin); pwm_start = ITE_EC_FAN_CTL_PWM_START_DUTY(conf->pwm_start); - pwm_start |= ITE_EC_FAN_CTL_PWM_SLOPE_BIT6(conf->slope); - pwm_auto = ITE_EC_FAN_CTL_PWM_SLOPE_LOWER(conf->slope); + if (CONFIG(SUPERIO_ITE_ENV_CTRL_7BIT_SLOPE_REG)) { + pwm_auto = conf->slope & 0x7f; + } else { + pwm_start |= ITE_EC_FAN_CTL_PWM_SLOPE_BIT6(conf->slope); + pwm_auto = ITE_EC_FAN_CTL_PWM_SLOPE_LOWER(conf->slope); + } + if (conf->smoothing) pwm_auto |= ITE_EC_FAN_CTL_AUTO_SMOOTHING_EN; @@ -287,6 +293,13 @@ void ite_ec_init(const u16 base, const struct ite_ec_config *const conf) for (i = 0; i < ITE_EC_TMPIN_CNT; ++i) enable_tmpin(base, i + 1, &conf->tmpin[i]); + /* Enable External Sensor SMBus Host if configured */ + if (conf->smbus_en) { + ite_ec_write(base, ITE_EC_INTERFACE_SELECT, + ite_ec_read(base, ITE_EC_INTERFACE_SELECT) | + ITE_EC_INTERFACE_SMB_ENABLE); + } + /* Enable reading of voltage pins */ ite_ec_write(base, ITE_EC_ADC_VOLTAGE_CHANNEL_ENABLE, conf->vin_mask); diff --git a/src/superio/ite/common/env_ctrl.h b/src/superio/ite/common/env_ctrl.h index e29e33f54a..20e44ad5f1 100644 --- a/src/superio/ite/common/env_ctrl.h +++ b/src/superio/ite/common/env_ctrl.h @@ -4,6 +4,7 @@ * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. * Copyright (C) 2016 secunet Security Networks AG * Copyright (C) 2019 Protectli + * Copyright (C) 2019 Libretrend LDA * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -50,6 +51,14 @@ #define ITE_EC_FAN_PWM_SMOOTHING_256HZ (1 << 6) #define ITE_EC_FAN_PWM_SMOOTHING_64HZ (2 << 6) #define ITE_EC_FAN_PWM_SMOOTHING_16HZ (3 << 6) +/* ITE IT8786E PWM_SMOOTHING_FREQ */ +#define ITE_EC_FAN_ALT_PWM_SMOOTHING_16HZ (1 << 6) +#define ITE_EC_FAN_ALT_PWM_SMOOTHING_8HZ (2 << 6) +#define ITE_EC_FAN_ALT_PWM_SMOOTHING_4HZ (3 << 6) +#define ITE_EC_FAN_CTL5_SEL(FAN_CTLx) ((((FAN_CTLx)-1) & 3) << 2) +#define ITE_EC_FAN_CTL5_SEL_NONE (3 << 2) +#define ITE_EC_FAN_CTL4_SEL(FAN_CTLx) (((FAN_CTLx)-1) & 3) +#define ITE_EC_FAN_CTL4_SEL_NONE (3 << 0) #define ITE_EC_FAN_TAC_COUNTER_ENABLE 0x0c #define ITE_EC_FAN_TAC_16BIT_ENABLE(x) (1 << ((x)-1)) @@ -68,6 +77,14 @@ : (0x1b + ((x)-1)) \ ) +#define ITE_EC_FAN_TAC_CNTRL 0x0c +#define ITE_EC_TMPIN3_ENHANCED_INT_MODE (1 << 7) +#define ITE_EC_TMPIN2_ENHANCED_INT_MODE (1 << 6) +#define ITE_EC_FAN_TAC5_EN (1 << 5) +#define ITE_EC_FAN_TAC4_EN (1 << 4) +#define ITE_EC_TMPIN1_ENHANCED_INT_MODE (1 << 3) +#define ITE_EC_AMDTSI_ERR_EN (1 << 0) + #define ITE_EC_FAN_MAIN_CTL 0x13 #define ITE_EC_FAN_MAIN_CTL_TAC_EN(x) (1 << ((x)+3)) #define ITE_EC_FAN_MAIN_CTL_COLL_FULL_SPEED (1 << 3) @@ -185,6 +202,8 @@ static const u8 ITE_EC_TEMP_ADJUST[] = { 0x56, 0x57, 0x59 }; /* Common for ITE_EC_FAN_CTL_DELTA_TEMP */ #define ITE_EC_FAN_CTL_DELTA_TEMP_INTRVL(c) ((c) & 0x1f) +#define ITE_EC_FAN_CTL_TARGET_ZONE(x) (0x66 + ((x)-1) * 8) +#define ITE_EC_FAN_CTL_TARGET_ZONE_MASK 0x0f #define ITE_EC_EXTEMP_STATUS 0x88 #define ITE_EC_EXTEMP_STATUS_HOST_BUSY (1 << 0) diff --git a/src/superio/ite/common/env_ctrl_chip.h b/src/superio/ite/common/env_ctrl_chip.h index 923bfa3aea..f5116e6465 100644 --- a/src/superio/ite/common/env_ctrl_chip.h +++ b/src/superio/ite/common/env_ctrl_chip.h @@ -101,6 +101,11 @@ struct ite_ec_config { bool tmpin_beep; bool fan_beep; bool vin_beep; + + /* + * Enable SMBus for external thermal sensor. + */ + bool smbus_en; }; /* Some shorthands for device trees */ From 72f6fbb1bc64a68dab121231b186c803e9836ad7 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Mon, 4 Jun 2018 11:16:35 +0300 Subject: [PATCH 052/331] superio/ite: Add IT8786E-I MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Based on IT8786E-I V0.4.1 datasheet with following remark: "Please note that the IT8786E-I V0.4.1 is applicable only to the D version." Signed-off-by: Kyösti Mälkki Signed-off-by: Michał Żygowski Change-Id: I7317da6a72db64f95f9a790ef96ed7a5f93b3aea Reviewed-on: https://review.coreboot.org/c/coreboot/+/30335 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held --- src/superio/ite/Makefile.inc | 2 + src/superio/ite/it8786e/Kconfig | 23 +++ src/superio/ite/it8786e/Makefile.inc | 18 +++ src/superio/ite/it8786e/acpi/superio.asl | 171 +++++++++++++++++++++++ src/superio/ite/it8786e/chip.h | 27 ++++ src/superio/ite/it8786e/it8786e.h | 36 +++++ src/superio/ite/it8786e/superio.c | 118 ++++++++++++++++ 7 files changed, 395 insertions(+) create mode 100644 src/superio/ite/it8786e/Kconfig create mode 100644 src/superio/ite/it8786e/Makefile.inc create mode 100644 src/superio/ite/it8786e/acpi/superio.asl create mode 100644 src/superio/ite/it8786e/chip.h create mode 100644 src/superio/ite/it8786e/it8786e.h create mode 100644 src/superio/ite/it8786e/superio.c diff --git a/src/superio/ite/Makefile.inc b/src/superio/ite/Makefile.inc index 551abe9a5d..8388c7aa38 100644 --- a/src/superio/ite/Makefile.inc +++ b/src/superio/ite/Makefile.inc @@ -2,6 +2,7 @@ ## This file is part of the coreboot project. ## ## Copyright (C) 2009 Ronald G. Minnich +## Copyright (C) 2018 Libretrend LDA ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by @@ -31,3 +32,4 @@ subdirs-y += it8721f subdirs-y += it8728f subdirs-y += it8772f subdirs-y += it8783ef +subdirs-y += it8786e diff --git a/src/superio/ite/it8786e/Kconfig b/src/superio/ite/it8786e/Kconfig new file mode 100644 index 0000000000..9d3f258a5a --- /dev/null +++ b/src/superio/ite/it8786e/Kconfig @@ -0,0 +1,23 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2016 secunet Security Networks AG +## Copyright (C) 2018 Libretrend LDA +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +config SUPERIO_ITE_IT8786E + bool + select SUPERIO_ITE_COMMON_PRE_RAM + select SUPERIO_ITE_ENV_CTRL + select SUPERIO_ITE_ENV_CTRL_PWM_FREQ2 + select SUPERIO_ITE_ENV_CTRL_8BIT_PWM + select SUPERIO_ITE_ENV_CTRL_7BIT_SLOPE_REG diff --git a/src/superio/ite/it8786e/Makefile.inc b/src/superio/ite/it8786e/Makefile.inc new file mode 100644 index 0000000000..560957ffc5 --- /dev/null +++ b/src/superio/ite/it8786e/Makefile.inc @@ -0,0 +1,18 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2016 secunet Security Networks AG +## Copyright (C) 2018 Libretrend LDA +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +ramstage-$(CONFIG_SUPERIO_ITE_IT8786E) += superio.c diff --git a/src/superio/ite/it8786e/acpi/superio.asl b/src/superio/ite/it8786e/acpi/superio.asl new file mode 100644 index 0000000000..f860da643b --- /dev/null +++ b/src/superio/ite/it8786e/acpi/superio.asl @@ -0,0 +1,171 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Christoph Grenz + * Copyright (C) 2013, 2016 secunet Security Networks AG + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * Include this file into a mainboard's DSDT _SB device tree and it will + * expose the IT8786E SuperIO and some of its functionality. + * + * It allows the change of IO ports, IRQs and DMA settings on logical + * devices, disabling and reenabling logical devices. + * + * LDN State + * 0x1 UARTA Implemented, untested + * 0x2 UARTB Implemented, untested + * 0x3 PP Not implemented + * 0x4 EC Not implemented + * 0x5 KBC Implemented, untested + * 0x6 MOUSE Implemented, untested + * 0x7 GPIO Not implemented + * 0x8 UARTC Implemented, untested + * 0x9 UARTD Implemented, untested + * 0xa UARTE Not implemented + * 0xb UARTF Not implemented + * 0xc CIR Not implemented + * + * Controllable through preprocessor defines: + * SUPERIO_DEV Device identifier for this SIO (e.g. SIO0) + * SUPERIO_PNP_BASE I/O address of the first PnP configuration register + * IT8786E_SHOW_UARTA If defined, UARTA will be exposed. + * IT8786E_SHOW_UARTB If defined, UARTB will be exposed. + * IT8786E_SHOW_UARTC If defined, UARTC will be exposed. + * IT8786E_SHOW_UARTD If defined, UARTD will be exposed. + * IT8786E_SHOW_KBC If defined, the KBC will be exposed. + * IT8786E_SHOW_PS2M If defined, PS/2 mouse support will be exposed. + */ + +#undef SUPERIO_CHIP_NAME +#define SUPERIO_CHIP_NAME IT8786E +#include + +#undef PNP_DEFAULT_PSC +#define PNP_DEFAULT_PSC Return (0) /* no power management */ + +#define CONFIGURE_CONTROL CCTL + +Device (SUPERIO_DEV) { + Name (_HID, EisaId("PNP0A05")) + Name (_STR, Unicode("ITE IT8786E Super I/O")) + Name (_UID, SUPERIO_UID(SUPERIO_DEV,)) + + /* Mutex for accesses to the configuration ports */ + Mutex (CRMX, 1) + + /* SuperIO configuration ports */ + OperationRegion (CREG, SystemIO, SUPERIO_PNP_BASE, 0x02) + Field (CREG, ByteAcc, NoLock, Preserve) + { + PNP_ADDR_REG, 8, + PNP_DATA_REG, 8 + } + IndexField (ADDR, DATA, ByteAcc, NoLock, Preserve) + { + Offset (0x02), + CONFIGURE_CONTROL, 8, /* Global configure control */ + + Offset (0x07), + PNP_LOGICAL_DEVICE, 8, /* Logical device selector */ + + Offset (0x30), + PNP_DEVICE_ACTIVE, 1, /* Logical device activation */ + + Offset (0x60), + PNP_IO0_HIGH_BYTE, 8, /* First I/O port base - high byte */ + PNP_IO0_LOW_BYTE, 8, /* First I/O port base - low byte */ + Offset (0x62), + PNP_IO1_HIGH_BYTE, 8, /* Second I/O port base - high byte */ + PNP_IO1_LOW_BYTE, 8, /* Second I/O port base - low byte */ + + Offset (0x70), + PNP_IRQ0, 8, /* First IRQ */ + } + + Method (_CRS) + { + /* Announce the used i/o ports to the OS */ + Return (ResourceTemplate () { + IO (Decode16, SUPERIO_PNP_BASE, SUPERIO_PNP_BASE, + 0x01, 0x02) + }) + } + + #undef PNP_ENTER_MAGIC_1ST + #undef PNP_ENTER_MAGIC_2ND + #undef PNP_ENTER_MAGIC_3RD + #undef PNP_ENTER_MAGIC_4TH + #undef PNP_EXIT_MAGIC_1ST + #define PNP_ENTER_MAGIC_1ST 0x87 + #define PNP_ENTER_MAGIC_2ND 0x01 + #define PNP_ENTER_MAGIC_3RD 0x55 +#if SUPERIO_PNP_BASE == 0x2e + #define PNP_ENTER_MAGIC_4TH 0x55 +#else + #define PNP_ENTER_MAGIC_4TH 0xaa +#endif + #define PNP_EXIT_SPECIAL_REG CONFIGURE_CONTROL + #define PNP_EXIT_SPECIAL_VAL 0x02 + #include + +#ifdef IT8786E_SHOW_UARTA + #undef SUPERIO_UART_LDN + #undef SUPERIO_UART_DDN + #undef SUPERIO_UART_PM_REG + #undef SUPERIO_UART_PM_VAL + #undef SUPERIO_UART_PM_LDN + #define SUPERIO_UART_LDN 1 + #include +#endif + +#ifdef IT8786E_SHOW_UARTB + #undef SUPERIO_UART_LDN + #undef SUPERIO_UART_DDN + #undef SUPERIO_UART_PM_REG + #undef SUPERIO_UART_PM_VAL + #undef SUPERIO_UART_PM_LDN + #define SUPERIO_UART_LDN 2 + #include +#endif + +#ifdef IT8786E_SHOW_KBC + #undef SUPERIO_KBC_LDN + #undef SUPERIO_KBC_PS2M + #undef SUPERIO_KBC_PS2LDN + #define SUPERIO_KBC_LDN 5 +#ifdef IT8786E_SHOW_PS2M + #define SUPERIO_KBC_PS2LDN 6 +#endif + #include +#endif + +#ifdef IT8786E_SHOW_UARTC + #undef SUPERIO_UART_LDN + #undef SUPERIO_UART_DDN + #undef SUPERIO_UART_PM_REG + #undef SUPERIO_UART_PM_VAL + #undef SUPERIO_UART_PM_LDN + #define SUPERIO_UART_LDN 8 + #include +#endif + +#ifdef IT8786E_SHOW_UARTD + #undef SUPERIO_UART_LDN + #undef SUPERIO_UART_DDN + #undef SUPERIO_UART_PM_REG + #undef SUPERIO_UART_PM_VAL + #undef SUPERIO_UART_PM_LDN + #define SUPERIO_UART_LDN 9 + #include +#endif +} diff --git a/src/superio/ite/it8786e/chip.h b/src/superio/ite/it8786e/chip.h new file mode 100644 index 0000000000..4b2e811475 --- /dev/null +++ b/src/superio/ite/it8786e/chip.h @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 secunet Security Networks AG + * Copyright (C) 2019 Libretrend LDA + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SUPERIO_ITE_IT8786E_CHIP_H +#define SUPERIO_ITE_IT8786E_CHIP_H + +#include + +struct superio_ite_it8786e_config { + struct ite_ec_config ec; +}; + +#endif /* SUPERIO_ITE_IT8786E_CHIP_H */ diff --git a/src/superio/ite/it8786e/it8786e.h b/src/superio/ite/it8786e/it8786e.h new file mode 100644 index 0000000000..5f11b63690 --- /dev/null +++ b/src/superio/ite/it8786e/it8786e.h @@ -0,0 +1,36 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 secunet Security Networks AG + * Copyright (C) 2019 Libretrend LDA + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SUPERIO_ITE_IT8786E_H +#define SUPERIO_ITE_IT8786E_H + +#define IT8786E_SP1 0x01 /* COM1 */ +#define IT8786E_SP2 0x02 /* COM2 */ +#define IT8786E_PP 0x03 /* Printer port */ +#define IT8786E_EC 0x04 /* Environment controller */ +#define IT8786E_KBCK 0x05 /* Keyboard */ +#define IT8786E_KBCM 0x06 /* Mouse */ +#define IT8786E_GPIO 0x07 /* GPIO */ +#define IT8786E_SP3 0x08 /* COM3 */ +#define IT8786E_SP4 0x09 /* COM4 */ +#define IT8786E_CIR 0x0a /* Consumer IR */ +#define IT8786E_SP5 0x0b /* COM5 */ +#define IT8786E_SP6 0x0c /* COM6 */ + +#include + +#endif /* SUPERIO_ITE_IT8786E_H */ diff --git a/src/superio/ite/it8786e/superio.c b/src/superio/ite/it8786e/superio.c new file mode 100644 index 0000000000..ac9dc4bc75 --- /dev/null +++ b/src/superio/ite/it8786e/superio.c @@ -0,0 +1,118 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 secunet Security Networks AG + * Copyright (C) 2019 Libretrend LDA + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include + +#include "it8786e.h" +#include "chip.h" + +static void it8786e_init(struct device *const dev) +{ + const struct superio_ite_it8786e_config *conf; + const struct resource *res; + + if (!dev->enabled) + return; + + switch (dev->path.pnp.device) { + case IT8786E_EC: + conf = dev->chip_info; + res = find_resource(dev, PNP_IDX_IO0); + if (!conf || !res) + break; + ite_ec_init(res->base, &conf->ec); + break; + case IT8786E_KBCK: + pc_keyboard_init(NO_AUX_DEVICE); + break; + default: + break; + } +} + +static struct device_operations ops = { + .read_resources = pnp_read_resources, + .set_resources = pnp_set_resources, + .enable_resources = pnp_enable_resources, + .enable = pnp_alt_enable, + .init = it8786e_init, + .ops_pnp_mode = &pnp_conf_mode_870155_aa, +}; + +static struct pnp_info pnp_dev_info[] = { + /* Serial Port 1 */ + { NULL, IT8786E_SP1, PNP_IO0 | PNP_IRQ0 | PNP_MSC0 | PNP_MSC1 | + PNP_MSC2, + 0x0ff8, }, + /* Serial Port 2 */ + { NULL, IT8786E_SP2, PNP_IO0 | PNP_IRQ0 | PNP_MSC0 | PNP_MSC1 | + PNP_MSC2, + 0x0ff8, }, + /* Printer Port */ + { NULL, IT8786E_PP, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_DRQ0 | + PNP_MSC0, + 0x0ff8, 0x0ffc, }, + /* Environmental Controller */ + { NULL, IT8786E_EC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_MSC0 | + PNP_MSC1 | PNP_MSC2 | PNP_MSC3 | PNP_MSC4 | + PNP_MSC5 | PNP_MSC6 | PNP_MSCA | PNP_MSCB | + PNP_MSCC, + 0x0ff8, 0x0ffc, }, + /* KBC Keyboard */ + { NULL, IT8786E_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_MSC0, + 0x0fff, 0x0fff, }, + /* KBC Mouse */ + { NULL, IT8786E_KBCM, PNP_IRQ0 | PNP_MSC0, }, + /* GPIO */ + { NULL, IT8786E_GPIO, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | + PNP_MSC0 | PNP_MSC1 | PNP_MSC2 | PNP_MSC3 | + PNP_MSC4 | PNP_MSC5 | PNP_MSC6 | PNP_MSC7 | + PNP_MSC8 | PNP_MSC9 | PNP_MSCA | PNP_MSCB, + 0x0ffc, 0x0fff, }, + /* Serial Port 3 */ + { NULL, IT8786E_SP3, PNP_IO0 | PNP_IRQ0 | PNP_MSC0 | PNP_MSC1 | + PNP_MSC2, + 0x0ff8, }, + /* Serial Port 4 */ + { NULL, IT8786E_SP4, PNP_IO0 | PNP_IRQ0 | PNP_MSC0 | PNP_MSC1 | + PNP_MSC2, + 0x0ff8, }, + /* Consumer Infrared */ + { NULL, IT8786E_CIR, PNP_IO0 | PNP_IRQ0 | PNP_MSC0, 0x0ff8, }, + /* Serial Port 5 */ + { NULL, IT8786E_SP5, PNP_IO0 | PNP_IRQ0 | PNP_MSC0 | PNP_MSC1 | + PNP_MSC2, + 0x0ff8, }, + /* Serial Port 6 */ + { NULL, IT8786E_SP6, PNP_IO0 | PNP_IRQ0 | PNP_MSC0 | PNP_MSC1 | + PNP_MSC2, + 0x0ff8, }, +}; + +static void enable_dev(struct device *dev) +{ + pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); +} + +struct chip_operations superio_ite_it8786e_ops = { + CHIP_NAME("ITE IT8786E Super I/O") + .enable_dev = enable_dev, +}; From 0d4200fef396fb0d1fbf28b4ced475fbf59b5b85 Mon Sep 17 00:00:00 2001 From: Philip Chen Date: Mon, 29 Apr 2019 10:18:24 -0700 Subject: [PATCH 053/331] soc/intel/cannonlake: Support different SPD read type for each slot Also clean up cannonlake_memcfg_init. The major changes include: (1) Add enum 'mem_info_read_type' to spd_info. (2) Add per-dimm-slot spd_info to cnl_mb_cfg. (3) Setup memory config for each slot independently. (4) Squash meminit_memcfg_spd(). BUG=chromium:960581, b:124990009 BRANCH=none TEST=boot hatch, hatch_whl, and kohaku Change-Id: I686a85996858204c20fd05ef24787a0487817c34 Signed-off-by: Philip Chen Reviewed-on: https://review.coreboot.org/c/coreboot/+/32513 Reviewed-by: Paul Fagerburg Reviewed-by: Furquan Shaikh Tested-by: build bot (Jenkins) --- src/mainboard/google/hatch/romstage.c | 54 ++++++-- .../baseboard/include/baseboard/gpio.h | 7 -- .../baseboard/include/baseboard/variants.h | 3 - .../google/hatch/variants/baseboard/memory.c | 33 +---- .../google/hatch/variants/kohaku/memory.c | 29 +---- src/mainboard/google/sarien/romstage.c | 27 ++-- src/mainboard/intel/coffeelake_rvp/memory.c | 25 +++- src/mainboard/intel/coffeelake_rvp/romstage.c | 10 +- src/soc/intel/cannonlake/cnl_memcfg_init.c | 115 ++++++++++-------- .../cannonlake/include/soc/cnl_memcfg_init.h | 38 +++--- 10 files changed, 179 insertions(+), 162 deletions(-) diff --git a/src/mainboard/google/hatch/romstage.c b/src/mainboard/google/hatch/romstage.c index bdf951b016..2c630a8ce8 100644 --- a/src/mainboard/google/hatch/romstage.c +++ b/src/mainboard/google/hatch/romstage.c @@ -16,23 +16,63 @@ #include #include #include +#include #include #include #include #include +/* Memory configuration board straps */ +#define GPIO_MEM_CONFIG_0 GPP_F20 +#define GPIO_MEM_CONFIG_1 GPP_F21 +#define GPIO_MEM_CONFIG_2 GPP_F11 +#define GPIO_MEM_CONFIG_3 GPP_F22 + +/* + * GPIO_MEM_CH_SEL is set to 1 for single channel skus + * and 0 for dual channel skus. + */ +#define GPIO_MEM_CH_SEL GPP_F2 + +static int memory_sku(void) +{ + const gpio_t spd_gpios[] = { + GPIO_MEM_CONFIG_0, + GPIO_MEM_CONFIG_1, + GPIO_MEM_CONFIG_2, + GPIO_MEM_CONFIG_3, + }; + + return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios)); +} + void mainboard_memory_init_params(FSPM_UPD *memupd) { struct cnl_mb_cfg memcfg; - - const struct spd_info spd = { - .spd_by_index = true, - .spd_spec.spd_index = variant_memory_sku(), - }; + int mem_sku; + int is_single_ch_mem; variant_memory_params(&memcfg); - cannonlake_memcfg_init(&memupd->FspmConfig, - &memcfg, &spd); + mem_sku = memory_sku(); + /* + * GPP_F2 is the MEM_CH_SEL gpio, which is set to 1 for single + * channel skus and 0 for dual channel skus. + */ + is_single_ch_mem = gpio_get(GPIO_MEM_CH_SEL); + + /* + * spd[0]-spd[3] map to CH0D0, CH0D1, CH1D0, CH1D1 respectively. + * Dual-DIMM memory is not used in hatch family, so we only + * fill in spd_info for CH0D0 and CH1D0 here. + */ + memcfg.spd[0].read_type = READ_SPD_CBFS; + memcfg.spd[0].spd_spec.spd_index = mem_sku; + if (!is_single_ch_mem) { + memcfg.spd[2].read_type = READ_SPD_CBFS; + memcfg.spd[2].spd_spec.spd_index = mem_sku; + } + + cannonlake_memcfg_init(&memupd->FspmConfig, &memcfg); } void mainboard_get_dram_part_num(const char **part_num, size_t *len) diff --git a/src/mainboard/google/hatch/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/google/hatch/variants/baseboard/include/baseboard/gpio.h index 5d6311ba24..e83732cb62 100644 --- a/src/mainboard/google/hatch/variants/baseboard/include/baseboard/gpio.h +++ b/src/mainboard/google/hatch/variants/baseboard/include/baseboard/gpio.h @@ -22,13 +22,6 @@ #define GPIO_PCH_WP GPP_C20 -/* Memory configuration board straps */ -#define GPIO_MEM_CONFIG_0 GPP_F20 -#define GPIO_MEM_CONFIG_1 GPP_F21 -#define GPIO_MEM_CONFIG_2 GPP_F11 -#define GPIO_MEM_CONFIG_3 GPP_F22 - - /* EC wake pin is LAN_WAKE# */ #define GPE_EC_WAKE GPE0_LAN_WAK diff --git a/src/mainboard/google/hatch/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/hatch/variants/baseboard/include/baseboard/variants.h index d41ad536f2..17bd5df63d 100644 --- a/src/mainboard/google/hatch/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/hatch/variants/baseboard/include/baseboard/variants.h @@ -31,9 +31,6 @@ const struct pad_config *base_early_gpio_table(size_t *num); const struct pad_config *override_gpio_table(size_t *num); const struct pad_config *override_early_gpio_table(size_t *num); -/* Return memory SKU for the board. */ -int variant_memory_sku(void); - /* Return board specific memory configuration */ void variant_memory_params(struct cnl_mb_cfg *bcfg); diff --git a/src/mainboard/google/hatch/variants/baseboard/memory.c b/src/mainboard/google/hatch/variants/baseboard/memory.c index 580bdc9ab3..bcfc49f20e 100644 --- a/src/mainboard/google/hatch/variants/baseboard/memory.c +++ b/src/mainboard/google/hatch/variants/baseboard/memory.c @@ -15,16 +15,15 @@ #include #include -#include #include #include static const struct cnl_mb_cfg baseboard_memcfg = { /* Baseboard uses 121, 81 and 100 rcomp resistors */ - .rcomp_resistor = { 121, 81, 100 }, + .rcomp_resistor = {121, 81, 100}, /* Baseboard Rcomp target values */ - .rcomp_targets = { 100, 40, 20, 20, 26 }, + .rcomp_targets = {100, 40, 20, 20, 26}, /* Set CaVref config to 2 */ .vref_ca_config = 2, @@ -36,32 +35,4 @@ static const struct cnl_mb_cfg baseboard_memcfg = { void __weak variant_memory_params(struct cnl_mb_cfg *bcfg) { memcpy(bcfg, &baseboard_memcfg, sizeof(baseboard_memcfg)); - /* - * GPP_F2 is the MEM_CH_SEL gpio, which is set to 1 for single - * channel skus and 0 for dual channel skus. - */ - if (gpio_get(GPP_F2) == 1) { - /* - * Single channel config: for Hatch, Channel 0 is - * always populated. - */ - bcfg->channel_empty[0] = 0; - bcfg->channel_empty[1] = 1; - } else { - /* Dual channel config: both channels populated. */ - bcfg->channel_empty[0] = 0; - bcfg->channel_empty[1] = 0; - } -} - -int __weak variant_memory_sku(void) -{ - const gpio_t spd_gpios[] = { - GPIO_MEM_CONFIG_0, - GPIO_MEM_CONFIG_1, - GPIO_MEM_CONFIG_2, - GPIO_MEM_CONFIG_3, - }; - - return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios)); } diff --git a/src/mainboard/google/hatch/variants/kohaku/memory.c b/src/mainboard/google/hatch/variants/kohaku/memory.c index 27ae3d8fb2..490124776e 100644 --- a/src/mainboard/google/hatch/variants/kohaku/memory.c +++ b/src/mainboard/google/hatch/variants/kohaku/memory.c @@ -15,7 +15,6 @@ #include #include -#include #include #include @@ -30,8 +29,8 @@ static const struct cnl_mb_cfg baseboard_memcfg = { * the index = pin number on SoC * the value = pin number on lpddr3 part */ - .dqs_map[DDR_CH0] = { 0, 1, 3, 2, 5, 7, 6, 4 }, - .dqs_map[DDR_CH1] = { 1, 3, 2, 0, 5, 7, 6, 4 }, + .dqs_map[DDR_CH0] = {0, 1, 3, 2, 5, 7, 6, 4}, + .dqs_map[DDR_CH1] = {1, 3, 2, 0, 5, 7, 6, 4}, .dq_map[DDR_CH0] = { {0xf, 0xf0}, @@ -40,7 +39,7 @@ static const struct cnl_mb_cfg baseboard_memcfg = { {0xf, 0x0}, {0xff, 0x0}, {0xff, 0x0} - }, + }, .dq_map[DDR_CH1] = { {0xf, 0xf0}, {0x0, 0xf0}, @@ -48,13 +47,13 @@ static const struct cnl_mb_cfg baseboard_memcfg = { {0xf, 0x0}, {0xff, 0x0}, {0xff, 0x0} - }, + }, /* Kohaku uses 200, 80.6 and 162 rcomp resistors */ - .rcomp_resistor = { 200, 81, 162 }, + .rcomp_resistor = {200, 81, 162}, /* Kohaku Rcomp target values */ - .rcomp_targets = { 100, 40, 40, 23, 40 }, + .rcomp_targets = {100, 40, 40, 23, 40}, /* Set CaVref config to 0 for LPDDR3 */ .vref_ca_config = 0, @@ -66,20 +65,4 @@ static const struct cnl_mb_cfg baseboard_memcfg = { void variant_memory_params(struct cnl_mb_cfg *bcfg) { memcpy(bcfg, &baseboard_memcfg, sizeof(baseboard_memcfg)); - /* - * GPP_F2 is the MEM_CH_SEL gpio, which is set to 1 for single - * channel skus and 0 for dual channel skus. - */ - if (gpio_get(GPP_F2) == 1) { - /* - * Single channel config: for kohaku, Channel 0 is - * always populated. - */ - bcfg->channel_empty[0] = 0; - bcfg->channel_empty[1] = 1; - } else { - /* Dual channel config: both channels populated. */ - bcfg->channel_empty[0] = 0; - bcfg->channel_empty[1] = 0; - } } diff --git a/src/mainboard/google/sarien/romstage.c b/src/mainboard/google/sarien/romstage.c index e83cd4aed4..20eee7f34b 100644 --- a/src/mainboard/google/sarien/romstage.c +++ b/src/mainboard/google/sarien/romstage.c @@ -18,6 +18,18 @@ #include static const struct cnl_mb_cfg memcfg = { + /* Access memory info through SMBUS. */ + .spd[0] = { + .read_type = READ_SMBUS, + .spd_spec = {.spd_smbus_address = 0xa0}, + }, + .spd[1] = {.read_type = NOT_EXISTING}, + .spd[2] = { + .read_type = READ_SMBUS, + .spd_spec = {.spd_smbus_address = 0xa4}, + }, + .spd[3] = {.read_type = NOT_EXISTING}, + /* * The dqs_map arrays map the ddr4 pins to the SoC pins * for both channels. @@ -25,16 +37,16 @@ static const struct cnl_mb_cfg memcfg = { * the index = pin number on ddr4 part * the value = pin number on SoC */ - .dqs_map[DDR_CH0] = { 0, 1, 4, 5, 2, 3, 6, 7 }, - .dqs_map[DDR_CH1] = { 0, 1, 4, 5, 2, 3, 6, 7 }, + .dqs_map[DDR_CH0] = {0, 1, 4, 5, 2, 3, 6, 7}, + .dqs_map[DDR_CH1] = {0, 1, 4, 5, 2, 3, 6, 7}, /* Baseboard uses 121, 81 and 100 rcomp resistors */ - .rcomp_resistor = { 121, 81, 100 }, + .rcomp_resistor = {121, 81, 100}, /* * Baseboard Rcomp target values. */ - .rcomp_targets = { 100, 40, 20, 20, 26 }, + .rcomp_targets = {100, 40, 20, 20, 26}, /* Disable Early Command Training */ .ect = 0, @@ -45,12 +57,7 @@ static const struct cnl_mb_cfg memcfg = { void mainboard_memory_init_params(FSPM_UPD *memupd) { - const struct spd_info spd = { - .spd_smbus_address[0] = 0xa0, - .spd_smbus_address[2] = 0xa4 - }; - wilco_ec_romstage_init(); - cannonlake_memcfg_init(&memupd->FspmConfig, &memcfg, &spd); + cannonlake_memcfg_init(&memupd->FspmConfig, &memcfg); } diff --git a/src/mainboard/intel/coffeelake_rvp/memory.c b/src/mainboard/intel/coffeelake_rvp/memory.c index a13000cc13..b093a20d2c 100644 --- a/src/mainboard/intel/coffeelake_rvp/memory.c +++ b/src/mainboard/intel/coffeelake_rvp/memory.c @@ -20,6 +20,23 @@ #include static const struct cnl_mb_cfg baseboard_memcfg_cfg = { + /* Access memory info through SMBUS. */ + .spd[0] = { + .read_type = READ_SMBUS, + .spd_spec = {.spd_smbus_address = 0xA0} + }, + .spd[1] = { + .read_type = READ_SMBUS, + .spd_spec = {.spd_smbus_address = 0xA2} + }, + .spd[2] = { + .read_type = READ_SMBUS, + .spd_spec = {.spd_smbus_address = 0xA4} + }, + .spd[3] = { + .read_type = READ_SMBUS, + .spd_spec = {.spd_smbus_address = 0xA6} + }, /* * The dqs_map arrays map the ddr4 pins to the SoC pins * for both channels. @@ -27,16 +44,16 @@ static const struct cnl_mb_cfg baseboard_memcfg_cfg = { * the index = pin number on ddr4 part * the value = pin number on SoC */ - .dqs_map[DDR_CH0] = { 0, 1, 3, 2, 4, 5, 6, 7 }, - .dqs_map[DDR_CH1] = { 1, 0, 4, 5, 2, 3, 6, 7 }, + .dqs_map[DDR_CH0] = {0, 1, 3, 2, 4, 5, 6, 7}, + .dqs_map[DDR_CH1] = {1, 0, 4, 5, 2, 3, 6, 7}, /* Baseboard uses 121, 81 and 100 rcomp resistors */ - .rcomp_resistor = { 121, 81, 100 }, + .rcomp_resistor = {121, 81, 100}, /* * Baseboard Rcomp target values. */ - .rcomp_targets = { 100, 40, 20, 20, 26 }, + .rcomp_targets = {100, 40, 20, 20, 26}, /* Baseboard is an interleaved design */ .dq_pins_interleaved = 1, diff --git a/src/mainboard/intel/coffeelake_rvp/romstage.c b/src/mainboard/intel/coffeelake_rvp/romstage.c index 1ab2d78b5a..09ef148e36 100644 --- a/src/mainboard/intel/coffeelake_rvp/romstage.c +++ b/src/mainboard/intel/coffeelake_rvp/romstage.c @@ -20,13 +20,5 @@ void mainboard_memory_init_params(FSPM_UPD *memupd) { - const struct spd_info spd = { - .spd_smbus_address[0] = 0xA0, - .spd_smbus_address[1] = 0xA2, - .spd_smbus_address[2] = 0xA4, - .spd_smbus_address[3] = 0xA6, - }; - - cannonlake_memcfg_init(&memupd->FspmConfig, - variant_memcfg_config(), &spd); + cannonlake_memcfg_init(&memupd->FspmConfig, variant_memcfg_config()); } diff --git a/src/soc/intel/cannonlake/cnl_memcfg_init.c b/src/soc/intel/cannonlake/cnl_memcfg_init.c index db001b82ae..4ebd9978ae 100644 --- a/src/soc/intel/cannonlake/cnl_memcfg_init.c +++ b/src/soc/intel/cannonlake/cnl_memcfg_init.c @@ -20,7 +20,7 @@ #include static void meminit_memcfg(FSP_M_CONFIG *mem_cfg, - const struct cnl_mb_cfg *board_cfg) + const struct cnl_mb_cfg *board_cfg) { /* * DqByteMapChx expects 12 bytes of data, but the last 6 bytes @@ -29,47 +29,58 @@ static void meminit_memcfg(FSP_M_CONFIG *mem_cfg, */ memset(&mem_cfg->DqByteMapCh0, 0, sizeof(mem_cfg->DqByteMapCh0)); memcpy(&mem_cfg->DqByteMapCh0, &board_cfg->dq_map[DDR_CH0], - sizeof(board_cfg->dq_map[DDR_CH0])); + sizeof(board_cfg->dq_map[DDR_CH0])); memset(&mem_cfg->DqByteMapCh1, 0, sizeof(mem_cfg->DqByteMapCh1)); memcpy(&mem_cfg->DqByteMapCh1, &board_cfg->dq_map[DDR_CH1], - sizeof(board_cfg->dq_map[DDR_CH1])); + sizeof(board_cfg->dq_map[DDR_CH1])); memcpy(&mem_cfg->DqsMapCpu2DramCh0, &board_cfg->dqs_map[DDR_CH0], - sizeof(board_cfg->dqs_map[DDR_CH0])); + sizeof(board_cfg->dqs_map[DDR_CH0])); memcpy(&mem_cfg->DqsMapCpu2DramCh1, &board_cfg->dqs_map[DDR_CH1], - sizeof(board_cfg->dqs_map[DDR_CH1])); + sizeof(board_cfg->dqs_map[DDR_CH1])); memcpy(&mem_cfg->RcompResistor, &board_cfg->rcomp_resistor, - sizeof(mem_cfg->RcompResistor)); + sizeof(mem_cfg->RcompResistor)); /* Early cannonlake requires rcomp targets to be 0 */ memcpy(&mem_cfg->RcompTarget, &board_cfg->rcomp_targets, - sizeof(mem_cfg->RcompTarget)); -} - -static void meminit_memcfg_spd(FSP_M_CONFIG *mem_cfg, - const struct cnl_mb_cfg *cnl_cfg, - size_t spd_data_len, uintptr_t spd_data_ptr) -{ - mem_cfg->MemorySpdDataLen = spd_data_len; - - if (cnl_cfg->channel_empty[0] == 0) - mem_cfg->MemorySpdPtr00 = spd_data_ptr; - - if (cnl_cfg->channel_empty[1] == 0) - mem_cfg->MemorySpdPtr10 = spd_data_ptr; + sizeof(mem_cfg->RcompTarget)); } /* * Initialize default memory settings using spd data contained in a buffer. */ -static void meminit_spd_data(FSP_M_CONFIG *mem_cfg, - const struct cnl_mb_cfg *cnl_cfg, - size_t spd_data_len, uintptr_t spd_data_ptr) +static void meminit_spd_data(FSP_M_CONFIG *mem_cfg, uint8_t mem_slot, + size_t spd_data_len, uintptr_t spd_data_ptr) { - assert(spd_data_ptr && spd_data_len); - meminit_memcfg_spd(mem_cfg, cnl_cfg, spd_data_len, spd_data_ptr); + static size_t last_set_spd_data_len = 0; + + assert(spd_data_ptr != 0 && spd_data_len != 0); + + if (last_set_spd_data_len != 0 && + last_set_spd_data_len != spd_data_len) + die("spd data length disparity among slots"); + + mem_cfg->MemorySpdDataLen = spd_data_len; + last_set_spd_data_len = spd_data_len; + + switch (mem_slot) { + case 0: + mem_cfg->MemorySpdPtr00 = spd_data_ptr; + break; + case 1: + mem_cfg->MemorySpdPtr01 = spd_data_ptr; + break; + case 2: + mem_cfg->MemorySpdPtr10 = spd_data_ptr; + break; + case 3: + mem_cfg->MemorySpdPtr11 = spd_data_ptr; + break; + default: + die("nonexistent memory slot"); + } } /* @@ -78,13 +89,13 @@ static void meminit_spd_data(FSP_M_CONFIG *mem_cfg, * in spd/Makefile.inc. */ static void meminit_cbfs_spd_index(FSP_M_CONFIG *mem_cfg, - const struct cnl_mb_cfg *cnl_cfg, - int spd_index) + int spd_index, uint8_t mem_slot) { size_t spd_data_len; uintptr_t spd_data_ptr; struct region_device spd_rdev; + assert(mem_slot < NUM_DIMM_SLOT); printk(BIOS_DEBUG, "SPD INDEX = %d\n", spd_index); if (get_spd_cbfs_rdev(&spd_rdev, spd_index) < 0) die("spd.bin not found or incorrect index\n"); @@ -92,40 +103,42 @@ static void meminit_cbfs_spd_index(FSP_M_CONFIG *mem_cfg, /* Memory leak is ok since we have memory mapped boot media */ assert(CONFIG(BOOT_DEVICE_MEMORY_MAPPED)); spd_data_ptr = (uintptr_t)rdev_mmap_full(&spd_rdev); - meminit_spd_data(mem_cfg, cnl_cfg, spd_data_len, spd_data_ptr); + meminit_spd_data(mem_cfg, mem_slot, spd_data_len, spd_data_ptr); } /* Initialize onboard memory configurations for CannonLake */ void cannonlake_memcfg_init(FSP_M_CONFIG *mem_cfg, - const struct cnl_mb_cfg *cnl_cfg, - const struct spd_info *spd) + const struct cnl_mb_cfg *cnl_cfg) { - bool OnModuleSpd = false; + const struct spd_info *spdi; + /* Early Command Training Enabled */ mem_cfg->ECT = cnl_cfg->ect; mem_cfg->DqPinsInterleaved = cnl_cfg->dq_pins_interleaved; mem_cfg->CaVrefConfig = cnl_cfg->vref_ca_config; - /* Spd pointer will only be used if all smbus slave address of memory - * sockets on the platform is empty */ - for (int i = 0; i < ARRAY_SIZE(mem_cfg->SpdAddressTable); i++) { - if (spd->spd_smbus_address[i] != 0) { - mem_cfg->SpdAddressTable[i] = spd->spd_smbus_address[i]; - OnModuleSpd = true; + for (int i = 0; i < NUM_DIMM_SLOT; i++) { + spdi = &(cnl_cfg->spd[i]); + switch (spdi->read_type) { + case NOT_EXISTING: + break; + case READ_SMBUS: + mem_cfg->SpdAddressTable[i] = + spdi->spd_spec.spd_smbus_address; + break; + case READ_SPD_CBFS: + meminit_cbfs_spd_index(mem_cfg, + spdi->spd_spec.spd_index, i); + break; + case READ_SPD_MEMPTR: + meminit_spd_data(mem_cfg, i, + spdi->spd_spec.spd_data_ptr_info.spd_data_len, + spdi->spd_spec.spd_data_ptr_info.spd_data_ptr); + break; + default: + die("no valid way to read mem info"); } + + meminit_memcfg(mem_cfg, cnl_cfg); } - - if (!OnModuleSpd) { - if (spd->spd_by_index) { - meminit_cbfs_spd_index(mem_cfg, cnl_cfg, - spd->spd_spec.spd_index); - } else { - meminit_spd_data(mem_cfg, cnl_cfg, - spd->spd_spec.spd_data_ptr_info.spd_data_len, - spd->spd_spec.spd_data_ptr_info.spd_data_ptr); - } - } - - meminit_memcfg(mem_cfg, cnl_cfg); - } diff --git a/src/soc/intel/cannonlake/include/soc/cnl_memcfg_init.h b/src/soc/intel/cannonlake/include/soc/cnl_memcfg_init.h index e602a33f78..d5f6c39f24 100644 --- a/src/soc/intel/cannonlake/include/soc/cnl_memcfg_init.h +++ b/src/soc/intel/cannonlake/include/soc/cnl_memcfg_init.h @@ -23,6 +23,9 @@ /* Number of dq bits controlled per dqs */ #define DQ_BITS_PER_DQS 8 +/* Number of memory DIMM slots available on Cannonlake board */ +#define NUM_DIMM_SLOT 4 + /* * Number of memory packages, where a "package" represents a 64-bit solution. */ @@ -40,17 +43,32 @@ struct spd_by_pointer { uintptr_t spd_data_ptr; }; +enum mem_info_read_type { + NOT_EXISTING, /* No memory in this slot */ + READ_SMBUS, /* Read on-module spd by SMBUS. */ + READ_SPD_CBFS, /* Find spd file in CBFS. */ + READ_SPD_MEMPTR /* Find spd data from pointer. */ +}; + struct spd_info { - bool spd_by_index; + enum mem_info_read_type read_type; union spd_data_by { + /* To read on-module spd when read_type is READ_SMBUS. */ + uint8_t spd_smbus_address; + + /* To identify spd file when read_type is READ_SPD_CBFS. */ int spd_index; + + /* To find spd data when read_type is READ_SPD_MEMPTR. */ struct spd_by_pointer spd_data_ptr_info; } spd_spec; - uint8_t spd_smbus_address[4]; }; /* Board-specific memory dq mapping information */ struct cnl_mb_cfg { + /* Parameters required to access SPD for CH0D0/CH0D1/CH1D0/CH1D1. */ + struct spd_info spd[NUM_DIMM_SLOT]; + /* * For each channel, there are 6 sets of DQ byte mappings, * where each set has a package 0 and a package 1 value (package 0 @@ -107,26 +125,12 @@ struct cnl_mb_cfg { /* Early Command Training Enabled */ uint8_t ect; - - /* - * Flags to indicate which channels are populated. We - * currently support single or dual channel configurations. - * Set 1 to indicate that the channel is not populated Set 0 - * to indicate that the channel is populated. For example, - * dual channel memory configuration would have both - * channel_empty[0] = 0 and channel_empty[1] = 0. Note that - * this flag is only used for soldered down DRAM where we get - * SPD data from CBFS. We need the value 0 to default to - * populated in order to support existing boards. - */ - uint8_t channel_empty[2]; }; /* * Initialize default memory configurations for CannonLake. */ void cannonlake_memcfg_init(FSP_M_CONFIG *mem_cfg, - const struct cnl_mb_cfg *cnl_cfg, - const struct spd_info *spd); + const struct cnl_mb_cfg *cnl_cfg); #endif /* _SOC_CANNONLAKE_MEMCFG_INIT_H_ */ From 2968c9d6c7bff8d126aee6fba329ce92bd65c86e Mon Sep 17 00:00:00 2001 From: Kane Chen Date: Wed, 8 May 2019 13:38:29 +0800 Subject: [PATCH 054/331] mb/google/poppy/variants/rammus: Support new onboard Hynix memory Add hynix_dimm_H9CCNNNCLGALAR-NVD for new onboard memory support. BUG=b:130337306 BRANCH=firmware-rammus-11275.B TEST=emerge-rammus coreboot chromeos-ec chromeos-bootimage Flash FW to DUT, and make sure system boots up. Signed-off-by: YanRu Chen Change-Id: Ibd02953d0c6ac62fa4d7751fd8b103b74433aa73 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32674 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- .../spd/hynix_dimm_H9CCNNNCLGALAR-NVD.spd.hex | 16 ++++++++++++++++ .../google/poppy/variants/rammus/Makefile.inc | 1 + 2 files changed, 17 insertions(+) create mode 100644 src/mainboard/google/poppy/spd/hynix_dimm_H9CCNNNCLGALAR-NVD.spd.hex diff --git a/src/mainboard/google/poppy/spd/hynix_dimm_H9CCNNNCLGALAR-NVD.spd.hex b/src/mainboard/google/poppy/spd/hynix_dimm_H9CCNNNCLGALAR-NVD.spd.hex new file mode 100644 index 0000000000..ada67c9620 --- /dev/null +++ b/src/mainboard/google/poppy/spd/hynix_dimm_H9CCNNNCLGALAR-NVD.spd.hex @@ -0,0 +1,16 @@ +91 20 F1 03 05 1A 05 0A 03 11 01 08 08 00 00 15 +78 78 90 50 90 11 50 E0 90 06 3C 3C 01 90 00 00 +00 00 C2 00 00 00 00 A8 00 88 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 80 AD 01 00 00 00 00 00 00 00 00 +48 39 43 43 4E 4E 4E 43 4C 47 41 4C 41 52 2D 4E +56 44 00 00 80 AD 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/poppy/variants/rammus/Makefile.inc b/src/mainboard/google/poppy/variants/rammus/Makefile.inc index 44dd07bcde..0d835cbe88 100644 --- a/src/mainboard/google/poppy/variants/rammus/Makefile.inc +++ b/src/mainboard/google/poppy/variants/rammus/Makefile.inc @@ -3,6 +3,7 @@ SPD_SOURCES += samsung_dimm_K4E8E324EB-EGCF # 0b0001 SPD_SOURCES += micron_dimm_MT52L256M32D1PF-093 # 0b0010 SPD_SOURCES += samsung_dimm_K4E6E304EC-EGCF # 0b0011 SPD_SOURCES += micron_dimm_MT52L256M32D1PF-107 # 0b0100 +SPD_SOURCES += hynix_dimm_H9CCNNNCLGALAR-NVD # 0b0101 bootblock-y += gpio.c From 111f9a9bcd710c3ee1ac89cf81b603a2de23cc62 Mon Sep 17 00:00:00 2001 From: Puthikorn Voravootivat Date: Mon, 13 May 2019 16:24:15 -0700 Subject: [PATCH 055/331] mb/google/poppy/variants/atlas: Remove B0D4 _PSV Per Intel, the internal thermal protection is working better than putting B0D4 _PSV in dptf. BUG=b:131251533 TEST=Get ~10% better Octane score. Correct TCC and TCC offset in MSR register. Change-Id: If85afdc673687477ec85a47efcb264a7e5d6ae45 Signed-off-by: Puthikorn Voravootivat Reviewed-on: https://review.coreboot.org/c/coreboot/+/32779 Tested-by: build bot (Jenkins) Reviewed-by: Caveh Jalali --- .../google/poppy/variants/atlas/include/variant/acpi/dptf.asl | 3 --- 1 file changed, 3 deletions(-) diff --git a/src/mainboard/google/poppy/variants/atlas/include/variant/acpi/dptf.asl b/src/mainboard/google/poppy/variants/atlas/include/variant/acpi/dptf.asl index 29c1d3f38b..570fbbbdfa 100644 --- a/src/mainboard/google/poppy/variants/atlas/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/poppy/variants/atlas/include/variant/acpi/dptf.asl @@ -49,9 +49,6 @@ Name (CHPS, Package () { }) Name (DTRT, Package () { - /* CPU Throttle Effect on CPU */ - Package () { \_SB.PCI0.B0D4, \_SB.PCI0.B0D4, 100, 50, 0, 0, 0, 0 }, - /* CPU Throttle Effect on Ambient */ Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR0, 100, 200, 0, 0, 0, 0 }, From caef7f837aee60a405ad8a923e97e4a6ba3aaa9c Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Mon, 13 May 2019 20:39:26 +0200 Subject: [PATCH 056/331] mb/packardbell/ms2290/acpi: Serialize Control Method IASL reports remarks 'Control Method should be made Serialized'. Change-Id: I5606c6e435da17f7d4732148f6ddcedb1fde4ab0 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/32769 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph --- src/mainboard/packardbell/ms2290/acpi/battery.asl | 2 +- src/mainboard/packardbell/ms2290/acpi/ec.asl | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mainboard/packardbell/ms2290/acpi/battery.asl b/src/mainboard/packardbell/ms2290/acpi/battery.asl index 716c3a62de..d341ab4488 100644 --- a/src/mainboard/packardbell/ms2290/acpi/battery.asl +++ b/src/mainboard/packardbell/ms2290/acpi/battery.asl @@ -52,7 +52,7 @@ Method(BSTA, 4, NotSerialized) Return (Arg1) } -Method(BINF, 2, NotSerialized) +Method(BINF, 2, Serialized) { Acquire(ECLK, 0xffff) Store(0, PAGE) diff --git a/src/mainboard/packardbell/ms2290/acpi/ec.asl b/src/mainboard/packardbell/ms2290/acpi/ec.asl index 5fb2498a3e..4f3e5b6c16 100644 --- a/src/mainboard/packardbell/ms2290/acpi/ec.asl +++ b/src/mainboard/packardbell/ms2290/acpi/ec.asl @@ -101,7 +101,7 @@ Device(EC) BAOE, 128, /* Battery OEM info */ } - Method (_CRS, 0) + Method (_CRS, 0, Serialized) { Name (ECMD, ResourceTemplate() { From 18b51b7315bea0031f05f14dcad82857716d264e Mon Sep 17 00:00:00 2001 From: Joel Kitching Date: Fri, 10 May 2019 12:33:08 +0800 Subject: [PATCH 057/331] vboot: rename BOOT_OPROM_NEEDED to BOOT_DISPLAY_REQUEST Verified Boot OPROM code is being refactored. OPROM is being generalized into "display initialization". As such, the NVRAM request flag is being renamed from OPROM_NEEDED to DISPLAY_REQUEST. BUG=b:124141368, b:124192753, chromium:948529 TEST=make clean && make test-abuild BRANCH=none Change-Id: I74374abf7d1deb594c073f7a4a76c9de46092143 Signed-off-by: Joel Kitching Cq-Depend: chromium:1605640 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32720 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh Reviewed-by: Paul Menzel Reviewed-by: Julius Werner --- src/security/vboot/vbnv.c | 4 ++-- src/security/vboot/vbnv_layout.h | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/src/security/vboot/vbnv.c b/src/security/vboot/vbnv.c index b99941875c..78502f74ee 100644 --- a/src/security/vboot/vbnv.c +++ b/src/security/vboot/vbnv.c @@ -140,11 +140,11 @@ int get_recovery_mode_from_vbnv(void) return vbnv_data(RECOVERY_OFFSET); } -/* Read the BOOT_OPROM_NEEDED flag from VBNV. */ +/* Read the BOOT_DISPLAY_REQUEST flag from VBNV. */ int vboot_wants_oprom(void) { vbnv_setup(); - return (vbnv_data(BOOT_OFFSET) & BOOT_OPROM_NEEDED) ? 1 : 0; + return (vbnv_data(BOOT_OFFSET) & BOOT_DISPLAY_REQUEST) ? 1 : 0; } /* Read the USB Device Controller(UDC) enable flag from VBNV. */ diff --git a/src/security/vboot/vbnv_layout.h b/src/security/vboot/vbnv_layout.h index a9326e4ff4..a3c2490c0d 100644 --- a/src/security/vboot/vbnv_layout.h +++ b/src/security/vboot/vbnv_layout.h @@ -31,7 +31,7 @@ #define BOOT_OFFSET 1 #define BOOT_DEBUG_RESET_MODE 0x80 #define BOOT_DISABLE_DEV_REQUEST 0x40 -#define BOOT_OPROM_NEEDED 0x20 +#define BOOT_DISPLAY_REQUEST 0x20 #define BOOT_TRY_B_COUNT_MASK 0x0F #define RECOVERY_OFFSET 2 From 807803afa2d10cfd818d7f1585e0279f09fc1e14 Mon Sep 17 00:00:00 2001 From: Joel Kitching Date: Fri, 10 May 2019 12:58:53 +0800 Subject: [PATCH 058/331] vboot: remove OPROM-related code As of CL:1605641, vboot2 code should be used for setting and checking display init state. Remove all vboot1 OPROM-related code, and use the vboot2 display init code which has already been added in previous commits. coreboot should not be reading vboot NVRAM flags directly. Remove the function vboot_wants_oprom(), and instead rely on display_init_required(), which uses the VBOOT_WD_FLAG_DISPLAY_INIT value stored in vboot_working_data.flags, initialized during verstage. Note that this means in the case of CONFIG_VBOOT=y, the return value of display_init_required() can only be trusted after verstage has been executed. This should not be a problem assuming that all display initialization occurs in ramstage. BUG=b:124141368, b:124192753, chromium:948529 TEST=Build locally TEST=make clean && make test-abuild BRANCH=none Change-Id: Ic8f9dc5a3c7f1546a8fed82bde02be4d04568f8d Signed-off-by: Joel Kitching Cq-Depend: chromium:1605641, chromium:1605525 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32723 Reviewed-by: Furquan Shaikh Reviewed-by: Paul Menzel Reviewed-by: Julius Werner Tested-by: build bot (Jenkins) --- src/device/pci_device.c | 3 --- src/security/vboot/vbnv.c | 7 ------- src/security/vboot/vbnv.h | 1 - src/security/vboot/vboot_handoff.c | 7 ------- src/soc/intel/broadwell/igd.c | 2 +- 5 files changed, 1 insertion(+), 19 deletions(-) diff --git a/src/device/pci_device.c b/src/device/pci_device.c index b5453c7e76..31c35dc02e 100644 --- a/src/device/pci_device.c +++ b/src/device/pci_device.c @@ -780,9 +780,6 @@ static int should_run_oprom(struct device *dev) */ should_run = display_init_required(); - if (!should_run && CONFIG(VBOOT)) - should_run = vboot_wants_oprom(); - if (!should_run) printk(BIOS_DEBUG, "Not running VGA Option ROM\n"); return should_run; diff --git a/src/security/vboot/vbnv.c b/src/security/vboot/vbnv.c index 78502f74ee..0c4f33bc11 100644 --- a/src/security/vboot/vbnv.c +++ b/src/security/vboot/vbnv.c @@ -140,13 +140,6 @@ int get_recovery_mode_from_vbnv(void) return vbnv_data(RECOVERY_OFFSET); } -/* Read the BOOT_DISPLAY_REQUEST flag from VBNV. */ -int vboot_wants_oprom(void) -{ - vbnv_setup(); - return (vbnv_data(BOOT_OFFSET) & BOOT_DISPLAY_REQUEST) ? 1 : 0; -} - /* Read the USB Device Controller(UDC) enable flag from VBNV. */ int vbnv_udc_enable_flag(void) { diff --git a/src/security/vboot/vbnv.h b/src/security/vboot/vbnv.h index c8e689fa04..a2f0b4c978 100644 --- a/src/security/vboot/vbnv.h +++ b/src/security/vboot/vbnv.h @@ -25,7 +25,6 @@ int verify_vbnv(uint8_t *vbnv_copy); void regen_vbnv_crc(uint8_t *vbnv_copy); int get_recovery_mode_from_vbnv(void); void set_recovery_mode_into_vbnv(int recovery_reason); -int vboot_wants_oprom(void); /* Read the USB Device Controller(UDC) enable flag from VBNV. */ int vbnv_udc_enable_flag(void); diff --git a/src/security/vboot/vboot_handoff.c b/src/security/vboot/vboot_handoff.c index fccbdfc0b7..8a6b3d61e8 100644 --- a/src/security/vboot/vboot_handoff.c +++ b/src/security/vboot/vboot_handoff.c @@ -68,13 +68,6 @@ static void fill_vboot_handoff(struct vboot_handoff *vboot_handoff, vb_sd->flags |= VBSD_BOOT_DEV_SWITCH_ON; vb_sd->flags |= VBSD_LF_DEV_SWITCH_ON; } - /* TODO(chromium:948529): Remove these two flags after downstream - vboot code longer reads them. */ - if (vboot_wants_oprom() || vb2_sd->recovery_reason || - vb2_sd->flags & VB2_SD_FLAG_DEV_MODE_ENABLED) - vb_sd->flags |= VBSD_OPROM_LOADED; - if (CONFIG(VBOOT_MUST_REQUEST_DISPLAY)) - vb_sd->flags |= VBSD_OPROM_MATTERS; /* In vboot1, VBSD_FWB_TRIED is * set only if B is booted as explicitly requested. Therefore, if B is diff --git a/src/soc/intel/broadwell/igd.c b/src/soc/intel/broadwell/igd.c index 319549df1e..b9b42810fc 100644 --- a/src/soc/intel/broadwell/igd.c +++ b/src/soc/intel/broadwell/igd.c @@ -513,7 +513,7 @@ static void igd_init(struct device *dev) /* Wait for any configured pre-graphics delay */ if (!acpi_is_wakeup_s3()) { #if CONFIG(CHROMEOS) - if (display_init_required() || vboot_wants_oprom()) + if (display_init_required()) mdelay(CONFIG_PRE_GRAPHICS_DELAY); #else mdelay(CONFIG_PRE_GRAPHICS_DELAY); From 724c66c88fa219087f4d6a0ccce1ba1d6f93c93b Mon Sep 17 00:00:00 2001 From: Jacob Garber Date: Mon, 13 May 2019 17:04:00 -0600 Subject: [PATCH 059/331] libpayload: ahci: Prevent memory leaks when failing on init Free several resources when AHCI initialization fails. Note that it is only safe to free resources when the command engine has stopped, since otherwise they may still be used for DMA. Found-by: Coverity CID 1260719, 1260727, 1261090, 1261098 Signed-off-by: Jacob Garber Change-Id: I6826d79338b26ff9696ab6ac9eb4c59f734687d8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32778 Tested-by: build bot (Jenkins) Reviewed-by: HAOUAS Elyes Reviewed-by: Nico Huber --- payloads/libpayload/drivers/storage/ahci.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/payloads/libpayload/drivers/storage/ahci.c b/payloads/libpayload/drivers/storage/ahci.c index 40e1008cf4..f74adafd75 100644 --- a/payloads/libpayload/drivers/storage/ahci.c +++ b/payloads/libpayload/drivers/storage/ahci.c @@ -108,6 +108,9 @@ static int ahci_dev_init(hba_ctrl_t *const ctrl, const int ncs = HBA_CAPS_DECODE_NCS(ctrl->caps); + if (ahci_cmdengine_stop(port)) + return 1; + /* Allocate command list, one command table and received FIS. */ cmd_t *const cmdlist = memalign(1024, ncs * sizeof(cmd_t)); cmdtable_t *const cmdtable = memalign(128, sizeof(cmdtable_t)); @@ -121,12 +124,10 @@ static int ahci_dev_init(hba_ctrl_t *const ctrl, memset((void *)rcvd_fis, '\0', sizeof(*rcvd_fis)); /* Set command list base and received FIS base. */ - if (ahci_cmdengine_stop(port)) - return 1; port->cmdlist_base = virt_to_phys(cmdlist); port->frameinfo_base = virt_to_phys(rcvd_fis); if (ahci_cmdengine_start(port)) - return 1; + goto _cleanup_ret; /* Put port into active state. */ port->cmd_stat |= HBA_PxCMD_ICC_ACTIVE; @@ -178,6 +179,8 @@ _cleanup_ret: /* Clean up (not reached for initialized devices). */ if (dev) free(dev); + /* Only free if stopping succeeds, since otherwise the controller may + still use the resources for DMA. */ if (!ahci_cmdengine_stop(port)) { port->cmdlist_base = 0; port->frameinfo_base = 0; From 56f768774a25320d738febf99c335abdb6eeafbe Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Sun, 12 May 2019 14:01:13 +0200 Subject: [PATCH 060/331] soc/intel/broadwell: Use the common cpu/intel/car romstage entry The only functional difference is the use of stack guards. Change-Id: I95645271e0d93a97f544a1cc4e9a4320738e6a20 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/32761 Tested-by: build bot (Jenkins) Reviewed-by: Matt DeVillier Reviewed-by: Nico Huber --- src/soc/intel/broadwell/romstage/Makefile.inc | 1 + src/soc/intel/broadwell/romstage/romstage.c | 23 ++++--------------- 2 files changed, 5 insertions(+), 19 deletions(-) diff --git a/src/soc/intel/broadwell/romstage/Makefile.inc b/src/soc/intel/broadwell/romstage/Makefile.inc index 2d562d98ef..cc0a05124f 100644 --- a/src/soc/intel/broadwell/romstage/Makefile.inc +++ b/src/soc/intel/broadwell/romstage/Makefile.inc @@ -1,5 +1,6 @@ cpu_incs-y += $(src)/cpu/intel/car/non-evict/cache_as_ram.S +romstage-y += ../../../../cpu/intel/car/romstage.c romstage-y += cpu.c romstage-y += pch.c romstage-y += power_state.c diff --git a/src/soc/intel/broadwell/romstage/romstage.c b/src/soc/intel/broadwell/romstage/romstage.c index acbca14a88..25c47c62c2 100644 --- a/src/soc/intel/broadwell/romstage/romstage.c +++ b/src/soc/intel/broadwell/romstage/romstage.c @@ -21,6 +21,7 @@ #include #include #include +#include #include #include #include @@ -39,7 +40,7 @@ /* platform_enter_postcar() determines the stack to use after * cache-as-ram is torn down as well as the MTRR settings to use, * and continues execution in postcar stage. */ -static void platform_enter_postcar(void) +void platform_enter_postcar(void) { struct postcar_frame pcf; uintptr_t top_of_ram; @@ -63,8 +64,8 @@ static void platform_enter_postcar(void) run_postcar_phase(&pcf); } -/* Entry from cache-as-ram.inc. */ -static void romstage_main(uint64_t tsc, uint32_t bist) +/* Entry from cpu/intel/car/romstage.c. */ +void mainboard_romstage_entry(unsigned long bist) { struct romstage_params rp = { .bist = bist, @@ -72,12 +73,6 @@ static void romstage_main(uint64_t tsc, uint32_t bist) post_code(0x30); - /* Save initial timestamp from bootblock. */ - timestamp_init(tsc); - - /* Save romstage begin */ - timestamp_add_now(TS_START_ROMSTAGE); - /* System Agent Early Initialization */ systemagent_early_init(); @@ -131,16 +126,6 @@ static void romstage_main(uint64_t tsc, uint32_t bist) romstage_handoff_init(rp.power_state->prev_sleep_state == ACPI_S3); mainboard_post_raminit(&rp); - - platform_enter_postcar(); -} - -/* This wrapper enables easy transition towards C_ENVIRONMENT_BOOTBLOCK, - * keeping changes in cache_as_ram.S easy to manage. - */ -asmlinkage void bootblock_c_entry_bist(uint64_t base_timestamp, uint32_t bist) -{ - romstage_main(base_timestamp, bist); } void __weak mainboard_pre_console_init(void) {} From 5bb15f1a4d18bafaf51b17fd9ea6d861f2b9ebd2 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Sat, 22 Dec 2018 16:02:25 +0100 Subject: [PATCH 061/331] soc/intel/broadwell: Use C_ENVIRONMENT_BOOTBLOCK This puts the cache-as-ram init in the bootblock. Before setting up cache as ram the microcode updates are applied. This removes the possibility for a normal/fallback setup although implementing this should be quite easy. Setting up LPC in the bootblock to output console on SuperIOs is not done in this patch, therefore BOOTBLOCK_CONSOLE is not yet selected. Change-Id: I44eb6d380dea5b82e3f009a46381a0f611bb7935 Signed-off-by: Arthur Heymans Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/30383 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/soc/intel/broadwell/Kconfig | 21 +++---- src/soc/intel/broadwell/Makefile.inc | 8 +++ src/soc/intel/broadwell/bootblock/cpu.c | 63 ++----------------- src/soc/intel/broadwell/bootblock/pch.c | 3 +- .../intel/broadwell/bootblock/systemagent.c | 3 +- src/soc/intel/broadwell/romstage/Makefile.inc | 2 - src/soc/intel/broadwell/romstage/romstage.c | 4 +- 7 files changed, 26 insertions(+), 78 deletions(-) diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index 83ccf7b9d8..9dd2f4f414 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -44,6 +44,8 @@ config CPU_SPECIFIC_OPTIONS select HAVE_POWER_STATE_AFTER_FAILURE select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE select NO_FIXED_XIP_ROM_SIZE + select C_ENVIRONMENT_BOOTBLOCK + select NO_BOOTBLOCK_CONSOLE config PCIEXP_ASPM bool @@ -69,18 +71,6 @@ config VBOOT select VBOOT_MUST_REQUEST_DISPLAY select VBOOT_STARTS_IN_ROMSTAGE -config BOOTBLOCK_CPU_INIT - string - default "soc/intel/broadwell/bootblock/cpu.c" - -config BOOTBLOCK_NORTHBRIDGE_INIT - string - default "soc/intel/broadwell/bootblock/systemagent.c" - -config BOOTBLOCK_SOUTHBRIDGE_INIT - string - default "soc/intel/broadwell/bootblock/pch.c" - config MMCONF_BASE_ADDRESS hex default 0xf0000000 @@ -123,6 +113,13 @@ config DCACHE_RAM_MRC_VAR_SIZE help The amount of cache-as-ram region required by the reference code. +config DCACHE_BSP_STACK_SIZE + hex + default 0x2000 + help + The amount of anticipated stack usage in CAR by bootblock and + other stages. + config HAVE_MRC bool "Add a Memory Reference Code binary" help diff --git a/src/soc/intel/broadwell/Makefile.inc b/src/soc/intel/broadwell/Makefile.inc index 1caf67adf4..eab8b37ba2 100644 --- a/src/soc/intel/broadwell/Makefile.inc +++ b/src/soc/intel/broadwell/Makefile.inc @@ -9,6 +9,13 @@ subdirs-y += ../../../cpu/intel/microcode subdirs-y += ../../../cpu/intel/turbo subdirs-y += ../../../cpu/intel/common +bootblock-y += bootblock/cpu.c +bootblock-y += bootblock/pch.c +bootblock-y += bootblock/systemagent.c +bootblock-y += ../../../cpu/intel/car/bootblock.c +bootblock-y += ../../../cpu/intel/car/non-evict/cache_as_ram.S +bootblock-y += ../../../cpu/x86/early_reset.S + ramstage-y += acpi.c ramstage-y += adsp.c ramstage-y += chip.c @@ -58,6 +65,7 @@ ramstage-y += stage_cache.c romstage-y += stage_cache.c postcar-y += stage_cache.c ramstage-y += systemagent.c +bootblock-y += tsc_freq.c ramstage-y += tsc_freq.c romstage-y += tsc_freq.c smm-y += tsc_freq.c diff --git a/src/soc/intel/broadwell/bootblock/cpu.c b/src/soc/intel/broadwell/bootblock/cpu.c index 2f1ac51981..f3c35f3441 100644 --- a/src/soc/intel/broadwell/bootblock/cpu.c +++ b/src/soc/intel/broadwell/bootblock/cpu.c @@ -19,47 +19,10 @@ #include #include #include -#include #include #include - -static void set_var_mtrr(unsigned int reg, unsigned int base, unsigned int size, - unsigned int type) -{ - /* Bit Bit 32-35 of MTRRphysMask should be set to 1 */ - msr_t basem, maskm; - basem.lo = base | type; - basem.hi = 0; - wrmsr(MTRR_PHYS_BASE(reg), basem); - maskm.lo = ~(size - 1) | MTRR_PHYS_MASK_VALID; - maskm.hi = (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1; - wrmsr(MTRR_PHYS_MASK(reg), maskm); -} - -static void enable_rom_caching(void) -{ - msr_t msr; - - disable_cache(); - set_var_mtrr(1, CACHE_ROM_BASE, CACHE_ROM_SIZE, MTRR_TYPE_WRPROT); - enable_cache(); - - /* Enable Variable MTRRs */ - msr.hi = 0x00000000; - msr.lo = 0x00000800; - wrmsr(MTRR_DEF_TYPE_MSR, msr); -} - -static void bootblock_mdelay(int ms) -{ - u32 target = ms * 24 * 1000; - msr_t current; - msr_t start = rdmsr(MSR_COUNTER_24_MHZ); - - do { - current = rdmsr(MSR_COUNTER_24_MHZ); - } while ((current.lo - start.lo) < target); -} +#include +#include static void set_flex_ratio_to_tdp_nominal(void) { @@ -102,7 +65,7 @@ static void set_flex_ratio_to_tdp_nominal(void) RCBA32_OR(SOFT_RESET_CTRL, 1); /* Delay before reset to avoid potential TPM lockout */ - bootblock_mdelay(30); + mdelay(30); /* Issue warm reset, will be "CPU only" due to soft reset data */ outb(0x0, 0xcf9); @@ -110,26 +73,8 @@ static void set_flex_ratio_to_tdp_nominal(void) halt(); } -static void check_for_clean_reset(void) -{ - msr_t msr; - msr = rdmsr(MTRR_DEF_TYPE_MSR); - - /* Use the MTRR default type MSR as a proxy for detecting INIT#. - * Reset the system if any known bits are set in that MSR. That is - * an indication of the CPU not being properly reset. */ - if (msr.lo & (MTRR_DEF_TYPE_EN | MTRR_DEF_TYPE_FIX_EN)) { - outb(0x0, 0xcf9); - outb(0x6, 0xcf9); - halt(); - } -} - -static void bootblock_cpu_init(void) +void bootblock_early_cpu_init(void) { /* Set flex ratio and reset if needed */ set_flex_ratio_to_tdp_nominal(); - check_for_clean_reset(); - enable_rom_caching(); - intel_update_microcode_from_cbfs(); } diff --git a/src/soc/intel/broadwell/bootblock/pch.c b/src/soc/intel/broadwell/bootblock/pch.c index dc7f42a625..1301610947 100644 --- a/src/soc/intel/broadwell/bootblock/pch.c +++ b/src/soc/intel/broadwell/bootblock/pch.c @@ -19,6 +19,7 @@ #include #include #include +#include /* * Enable Prefetching and Caching. @@ -66,7 +67,7 @@ static void set_spi_speed(void) SPIBAR8(SPIBAR_SSFC + 2) = ssfc; } -static void bootblock_southbridge_init(void) +void bootblock_early_southbridge_init(void) { map_rcba(); enable_spi_prefetch(); diff --git a/src/soc/intel/broadwell/bootblock/systemagent.c b/src/soc/intel/broadwell/bootblock/systemagent.c index e618636eb2..7aaed789ac 100644 --- a/src/soc/intel/broadwell/bootblock/systemagent.c +++ b/src/soc/intel/broadwell/bootblock/systemagent.c @@ -16,8 +16,9 @@ #include #include #include +#include -static void bootblock_northbridge_init(void) +void bootblock_early_northbridge_init(void) { uint32_t reg; diff --git a/src/soc/intel/broadwell/romstage/Makefile.inc b/src/soc/intel/broadwell/romstage/Makefile.inc index cc0a05124f..ea17d67061 100644 --- a/src/soc/intel/broadwell/romstage/Makefile.inc +++ b/src/soc/intel/broadwell/romstage/Makefile.inc @@ -1,5 +1,3 @@ -cpu_incs-y += $(src)/cpu/intel/car/non-evict/cache_as_ram.S - romstage-y += ../../../../cpu/intel/car/romstage.c romstage-y += cpu.c romstage-y += pch.c diff --git a/src/soc/intel/broadwell/romstage/romstage.c b/src/soc/intel/broadwell/romstage/romstage.c index 25c47c62c2..54434a3153 100644 --- a/src/soc/intel/broadwell/romstage/romstage.c +++ b/src/soc/intel/broadwell/romstage/romstage.c @@ -67,9 +67,7 @@ void platform_enter_postcar(void) /* Entry from cpu/intel/car/romstage.c. */ void mainboard_romstage_entry(unsigned long bist) { - struct romstage_params rp = { - .bist = bist, - }; + struct romstage_params rp = { 0 }; post_code(0x30); From 4d56a0625516ba436903d59d9c0a4a13827d89be Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Sat, 22 Dec 2018 16:11:52 +0100 Subject: [PATCH 062/331] nb/intel/broadwell: Add an option for where verstage starts Previously broadwell used a romcc bootblock and starting verstage in romstage was madatory but with C_ENVIRONMENT_BOOTBLOCK it is also possible to have a separate verstage. This selects using a separate verstage by default but still keeps the option around to use verstage in romstage. With a separate verstage the romstage becomes an RW stage. The mrc.bin however is only added to the RO COREBOOT fmap region as it requires to be run at a specific offset. This means that coreboot will have to jump from a RW region to the RO region for that binary and back to that RW region after that binary is done initializing the memory. Change-Id: I900233cadb3c76da329fb98f93917570e633365f Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/30384 Reviewed-by: Nico Huber Reviewed-by: Matt DeVillier Tested-by: build bot (Jenkins) --- src/mainboard/google/auron/Makefile.inc | 1 + src/mainboard/google/jecht/Makefile.inc | 1 + src/mainboard/intel/wtm2/Makefile.inc | 1 + src/soc/intel/broadwell/Kconfig | 25 +++++++++++++++++++++- src/soc/intel/broadwell/Makefile.inc | 2 ++ src/soc/intel/broadwell/romstage/raminit.c | 7 +++++- 6 files changed, 35 insertions(+), 2 deletions(-) diff --git a/src/mainboard/google/auron/Makefile.inc b/src/mainboard/google/auron/Makefile.inc index c81aeaf0f6..d2b6d0eb9a 100644 --- a/src/mainboard/google/auron/Makefile.inc +++ b/src/mainboard/google/auron/Makefile.inc @@ -17,6 +17,7 @@ ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c romstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-$(CONFIG_CHROMEOS) += chromeos.c +bootblock-$(CONFIG_CHROMEOS) += chromeos.c smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c diff --git a/src/mainboard/google/jecht/Makefile.inc b/src/mainboard/google/jecht/Makefile.inc index 39e9b339e8..28a284e759 100644 --- a/src/mainboard/google/jecht/Makefile.inc +++ b/src/mainboard/google/jecht/Makefile.inc @@ -16,6 +16,7 @@ subdirs-y += spd romstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-$(CONFIG_CHROMEOS) += chromeos.c +verstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-y += lan.c smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c led.c diff --git a/src/mainboard/intel/wtm2/Makefile.inc b/src/mainboard/intel/wtm2/Makefile.inc index 4c944f2773..c4afb98cc5 100644 --- a/src/mainboard/intel/wtm2/Makefile.inc +++ b/src/mainboard/intel/wtm2/Makefile.inc @@ -15,6 +15,7 @@ romstage-y += gpio.c +verstage-y += chromeos.c romstage-y += chromeos.c ramstage-y += chromeos.c diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index 9dd2f4f414..b685391af9 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -67,9 +67,25 @@ config PCIEXP_L1_SUB_STATE bool default y +config BROADWELL_VBOOT_IN_BOOTBLOCK + depends on VBOOT + bool "Start verstage in bootblock" + default y + select VBOOT_STARTS_IN_BOOTBLOCK + select VBOOT_SEPARATE_VERSTAGE + help + Broadwell can either start verstage in a separate stage + right after the bootblock has run or it can start it + after romstage for compatibility reasons. + Broadwell however uses a mrc.bin to initialse memory which + needs to be located at a fixed offset. Therefore even with + a separate verstage starting after the bootblock that same + binary is used meaning a jump is made from RW to the RO region + and back to the RW region after the binary is done. + config VBOOT select VBOOT_MUST_REQUEST_DISPLAY - select VBOOT_STARTS_IN_ROMSTAGE + select VBOOT_STARTS_IN_ROMSTAGE if !BROADWELL_VBOOT_IN_BOOTBLOCK config MMCONF_BASE_ADDRESS hex @@ -141,6 +157,13 @@ config MRC_BIN_ADDRESS hex default 0xfffa0000 +# The UEFI System Agent binary needs to be at a fixed offset in the flash +# and can therefore only reside in the COREBOOT fmap region +config RO_REGION_ONLY + string + depends on VBOOT + default "mrc.bin" + endif # HAVE_MRC config PRE_GRAPHICS_DELAY diff --git a/src/soc/intel/broadwell/Makefile.inc b/src/soc/intel/broadwell/Makefile.inc index eab8b37ba2..40017eb3ec 100644 --- a/src/soc/intel/broadwell/Makefile.inc +++ b/src/soc/intel/broadwell/Makefile.inc @@ -49,6 +49,7 @@ romstage-y += pei_data.c ramstage-y += pmutil.c romstage-y += pmutil.c smm-y += pmutil.c +verstage-y += pmutil.c ramstage-y += ramstage.c ramstage-$(CONFIG_HAVE_REFCODE_BLOB) += refcode.c ramstage-y += sata.c @@ -70,6 +71,7 @@ ramstage-y += tsc_freq.c romstage-y += tsc_freq.c smm-y += tsc_freq.c postcar-y += tsc_freq.c +verstage-y += tsc_freq.c bootblock-$(CONFIG_USBDEBUG) += usb_debug.c romstage-$(CONFIG_USBDEBUG) += usb_debug.c ramstage-$(CONFIG_USBDEBUG) += usb_debug.c diff --git a/src/soc/intel/broadwell/romstage/raminit.c b/src/soc/intel/broadwell/romstage/raminit.c index 8d43907f8a..fc8b7c6984 100644 --- a/src/soc/intel/broadwell/romstage/raminit.c +++ b/src/soc/intel/broadwell/romstage/raminit.c @@ -45,6 +45,8 @@ void raminit(struct pei_data *pei_data) struct memory_info *mem_info; pei_wrapper_entry_t entry; int ret; + struct cbfsf f; + uint32_t type = CBFS_TYPE_MRC; broadwell_fill_pei_data(pei_data); @@ -77,7 +79,10 @@ void raminit(struct pei_data *pei_data) } /* Determine if mrc.bin is in the cbfs. */ - entry = cbfs_boot_map_with_leak("mrc.bin", CBFS_TYPE_MRC, NULL); + if (cbfs_locate_file_in_region(&f, "COREBOOT", "mrc.bin", &type) < 0) + die("mrc.bin not found!"); + /* We don't care about leaking the mapping */ + entry = (pei_wrapper_entry_t)rdev_mmap_full(&f.data); if (entry == NULL) { printk(BIOS_DEBUG, "Couldn't find mrc.bin\n"); return; From e43972474c0eebc478722f7c371a8c68318f24cf Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Sat, 22 Dec 2018 16:59:44 +0100 Subject: [PATCH 063/331] soc/intel/broadwell: Enable LPC/SIO setup in bootblock This allows for serial console during the bootblock and enables bootblock console by default. Change-Id: I7746e4f819486d6142c96bc4c7480076fbfdfbde Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/30385 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber Reviewed-by: Matt DeVillier --- src/mainboard/google/jecht/Makefile.inc | 4 +- src/mainboard/google/jecht/bootblock.c | 31 ++++++++++++ src/mainboard/google/jecht/romstage.c | 12 ----- src/soc/intel/broadwell/Kconfig | 1 - src/soc/intel/broadwell/bootblock/pch.c | 49 +++++++++++++++++++ .../intel/broadwell/include/soc/romstage.h | 1 - src/soc/intel/broadwell/romstage/pch.c | 41 ---------------- src/soc/intel/broadwell/romstage/romstage.c | 9 ---- 8 files changed, 83 insertions(+), 65 deletions(-) create mode 100644 src/mainboard/google/jecht/bootblock.c diff --git a/src/mainboard/google/jecht/Makefile.inc b/src/mainboard/google/jecht/Makefile.inc index 28a284e759..116792fab7 100644 --- a/src/mainboard/google/jecht/Makefile.inc +++ b/src/mainboard/google/jecht/Makefile.inc @@ -24,7 +24,9 @@ smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c led.c romstage-y += variants/$(VARIANT_DIR)/pei_data.c ramstage-y += variants/$(VARIANT_DIR)/pei_data.c -romstage-y += led.c +bootblock-y += led.c + +bootblock-y += bootblock.c subdirs-y += variants/$(VARIANT_DIR) CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include diff --git a/src/mainboard/google/jecht/bootblock.c b/src/mainboard/google/jecht/bootblock.c new file mode 100644 index 0000000000..43725cd747 --- /dev/null +++ b/src/mainboard/google/jecht/bootblock.c @@ -0,0 +1,31 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2010 coresystems GmbH + * Copyright (C) 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include "onboard.h" + +void bootblock_mainboard_early_init(void) +{ + /* Early SuperIO setup */ + it8772f_ac_resume_southbridge(IT8772F_SUPERIO_DEV); + ite_kill_watchdog(IT8772F_GPIO_DEV); + ite_enable_serial(IT8772F_SERIAL_DEV, CONFIG_TTYS0_BASE); + + /* Turn On Power LED */ + set_power_led(LED_ON); +} diff --git a/src/mainboard/google/jecht/romstage.c b/src/mainboard/google/jecht/romstage.c index 86888c82f8..4fc2ba0c93 100644 --- a/src/mainboard/google/jecht/romstage.c +++ b/src/mainboard/google/jecht/romstage.c @@ -39,15 +39,3 @@ void mainboard_post_raminit(struct romstage_params *rp) if (CONFIG(CHROMEOS)) init_bootmode_straps(); } - -void mainboard_pre_console_init(void) -{ - /* Early SuperIO setup */ - it8772f_ac_resume_southbridge(IT8772F_SUPERIO_DEV); - ite_kill_watchdog(IT8772F_GPIO_DEV); - ite_enable_serial(IT8772F_SERIAL_DEV, CONFIG_TTYS0_BASE); - - /* Turn On Power LED */ - set_power_led(LED_ON); - -} diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index b685391af9..d81ab8ac95 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -45,7 +45,6 @@ config CPU_SPECIFIC_OPTIONS select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE select NO_FIXED_XIP_ROM_SIZE select C_ENVIRONMENT_BOOTBLOCK - select NO_BOOTBLOCK_CONSOLE config PCIEXP_ASPM bool diff --git a/src/soc/intel/broadwell/bootblock/pch.c b/src/soc/intel/broadwell/bootblock/pch.c index 1301610947..590961b361 100644 --- a/src/soc/intel/broadwell/bootblock/pch.c +++ b/src/soc/intel/broadwell/bootblock/pch.c @@ -19,6 +19,9 @@ #include #include #include +#include +#include +#include #include /* @@ -67,10 +70,56 @@ static void set_spi_speed(void) SPIBAR8(SPIBAR_SSFC + 2) = ssfc; } +const struct reg_script pch_early_init_script[] = { + /* Setup southbridge BARs */ + REG_PCI_WRITE32(RCBA, RCBA_BASE_ADDRESS | 1), + REG_PCI_WRITE32(PMBASE, ACPI_BASE_ADDRESS | 1), + REG_PCI_WRITE8(ACPI_CNTL, ACPI_EN), + REG_PCI_WRITE32(GPIO_BASE, GPIO_BASE_ADDRESS | 1), + REG_PCI_WRITE8(GPIO_CNTL, GPIO_EN), + + /* Set COM1/COM2 decode range */ + REG_PCI_WRITE16(LPC_IO_DEC, 0x0010), + /* Enable legacy decode ranges */ + REG_PCI_WRITE16(LPC_EN, CNF1_LPC_EN | CNF2_LPC_EN | GAMEL_LPC_EN | + COMA_LPC_EN | KBC_LPC_EN | MC_LPC_EN), + + /* Enable IOAPIC */ + REG_MMIO_WRITE16(RCBA_BASE_ADDRESS + OIC, 0x0100), + /* Read back for posted write */ + REG_MMIO_READ16(RCBA_BASE_ADDRESS + OIC), + + /* Set HPET address and enable it */ + REG_MMIO_RMW32(RCBA_BASE_ADDRESS + HPTC, ~3, (1 << 7)), + /* Read back for posted write */ + REG_MMIO_READ32(RCBA_BASE_ADDRESS + HPTC), + /* Enable HPET to start counter */ + REG_MMIO_OR32(HPET_BASE_ADDRESS + 0x10, (1 << 0)), + + /* Disable reset */ + REG_MMIO_OR32(RCBA_BASE_ADDRESS + GCS, (1 << 5)), + /* TCO timer halt */ + REG_IO_OR16(ACPI_BASE_ADDRESS + TCO1_CNT, TCO_TMR_HLT), + + /* Enable upper 128 bytes of CMOS */ + REG_MMIO_OR32(RCBA_BASE_ADDRESS + RC, (1 << 2)), + + /* Disable unused device (always) */ + REG_MMIO_OR32(RCBA_BASE_ADDRESS + FD, PCH_DISABLE_ALWAYS), + + REG_SCRIPT_END +}; + +static void pch_early_lpc(void) +{ + reg_script_run_on_dev(PCH_DEV_LPC, pch_early_init_script); +} + void bootblock_early_southbridge_init(void) { map_rcba(); enable_spi_prefetch(); enable_port80_on_lpc(); set_spi_speed(); + pch_early_lpc(); } diff --git a/src/soc/intel/broadwell/include/soc/romstage.h b/src/soc/intel/broadwell/include/soc/romstage.h index d65692ae23..ece3cd8c5a 100644 --- a/src/soc/intel/broadwell/include/soc/romstage.h +++ b/src/soc/intel/broadwell/include/soc/romstage.h @@ -50,5 +50,4 @@ int smbus_read_byte(unsigned int device, unsigned int address); int early_spi_read(u32 offset, u32 size, u8 *buffer); int early_spi_read_wpsr(u8 *sr); -void mainboard_pre_console_init(void); #endif diff --git a/src/soc/intel/broadwell/romstage/pch.c b/src/soc/intel/broadwell/romstage/pch.c index ecdadb7f9b..ef97a1e3fa 100644 --- a/src/soc/intel/broadwell/romstage/pch.c +++ b/src/soc/intel/broadwell/romstage/pch.c @@ -27,46 +27,6 @@ #include #include -const struct reg_script pch_early_init_script[] = { - /* Setup southbridge BARs */ - REG_PCI_WRITE32(RCBA, RCBA_BASE_ADDRESS | 1), - REG_PCI_WRITE32(PMBASE, ACPI_BASE_ADDRESS | 1), - REG_PCI_WRITE8(ACPI_CNTL, ACPI_EN), - REG_PCI_WRITE32(GPIO_BASE, GPIO_BASE_ADDRESS | 1), - REG_PCI_WRITE8(GPIO_CNTL, GPIO_EN), - - /* Set COM1/COM2 decode range */ - REG_PCI_WRITE16(LPC_IO_DEC, 0x0010), - /* Enable legacy decode ranges */ - REG_PCI_WRITE16(LPC_EN, CNF1_LPC_EN | CNF2_LPC_EN | GAMEL_LPC_EN | - COMA_LPC_EN | KBC_LPC_EN | MC_LPC_EN), - - /* Enable IOAPIC */ - REG_MMIO_WRITE16(RCBA_BASE_ADDRESS + OIC, 0x0100), - /* Read back for posted write */ - REG_MMIO_READ16(RCBA_BASE_ADDRESS + OIC), - - /* Set HPET address and enable it */ - REG_MMIO_RMW32(RCBA_BASE_ADDRESS + HPTC, ~3, (1 << 7)), - /* Read back for posted write */ - REG_MMIO_READ32(RCBA_BASE_ADDRESS + HPTC), - /* Enable HPET to start counter */ - REG_MMIO_OR32(HPET_BASE_ADDRESS + 0x10, (1 << 0)), - - /* Disable reset */ - REG_MMIO_OR32(RCBA_BASE_ADDRESS + GCS, (1 << 5)), - /* TCO timer halt */ - REG_IO_OR16(ACPI_BASE_ADDRESS + TCO1_CNT, TCO_TMR_HLT), - - /* Enable upper 128 bytes of CMOS */ - REG_MMIO_OR32(RCBA_BASE_ADDRESS + RC, (1 << 2)), - - /* Disable unused device (always) */ - REG_MMIO_OR32(RCBA_BASE_ADDRESS + FD, PCH_DISABLE_ALWAYS), - - REG_SCRIPT_END -}; - const struct reg_script pch_interrupt_init_script[] = { /* * GFX INTA -> PIRQA (MSI) @@ -132,7 +92,6 @@ static void pch_enable_lpc(void) void pch_early_init(void) { - reg_script_run_on_dev(PCH_DEV_LPC, pch_early_init_script); reg_script_run_on_dev(PCH_DEV_LPC, pch_interrupt_init_script); pch_enable_lpc(); diff --git a/src/soc/intel/broadwell/romstage/romstage.c b/src/soc/intel/broadwell/romstage/romstage.c index 54434a3153..f8571678d8 100644 --- a/src/soc/intel/broadwell/romstage/romstage.c +++ b/src/soc/intel/broadwell/romstage/romstage.c @@ -77,13 +77,6 @@ void mainboard_romstage_entry(unsigned long bist) /* PCH Early Initialization */ pch_early_init(); - /* Call into mainboard pre console init. Needed to enable serial port - on IT8772 */ - mainboard_pre_console_init(); - - /* Start console drivers */ - console_init(); - /* Get power state */ rp.power_state = fill_power_state(); @@ -125,5 +118,3 @@ void mainboard_romstage_entry(unsigned long bist) mainboard_post_raminit(&rp); } - -void __weak mainboard_pre_console_init(void) {} From caae2690325256036ed371646c0ce5d2115aed29 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Sun, 12 May 2019 12:44:00 +0200 Subject: [PATCH 064/331] soc/intel/broadwell/romstage: Clean up unused bist variable Checking BIST is done in the bootblock. Change-Id: I3ea2eb6a37c038f7348f0abd2056eee5c07bdb9d Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/32757 Reviewed-by: Matt DeVillier Reviewed-by: Nico Huber Tested-by: build bot (Jenkins) --- src/soc/intel/broadwell/include/soc/romstage.h | 1 - 1 file changed, 1 deletion(-) diff --git a/src/soc/intel/broadwell/include/soc/romstage.h b/src/soc/intel/broadwell/include/soc/romstage.h index ece3cd8c5a..ac8265fb4c 100644 --- a/src/soc/intel/broadwell/include/soc/romstage.h +++ b/src/soc/intel/broadwell/include/soc/romstage.h @@ -22,7 +22,6 @@ struct chipset_power_state; struct romstage_params { - unsigned long bist; struct chipset_power_state *power_state; struct pei_data pei_data; }; From 65209de411b4f87d7ebf9a3d82e91324a841f3be Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Tue, 14 May 2019 12:57:01 +0200 Subject: [PATCH 065/331] autoport: Remove unneeded include MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I7cb4b47e2fd893274303bb20dc7fa895830b4493 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/32787 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki --- util/autoport/bd82x6x.go | 1 - 1 file changed, 1 deletion(-) diff --git a/util/autoport/bd82x6x.go b/util/autoport/bd82x6x.go index a97ff1d961..e93704ec4a 100644 --- a/util/autoport/bd82x6x.go +++ b/util/autoport/bd82x6x.go @@ -302,7 +302,6 @@ func (b bd82x6x) Scan(ctx Context, addr PCIDevData) { #include #include #include -#include #include #include #include From 5bc493a8a2f53e834ac5be98725acf7601c70dbc Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Tue, 14 May 2019 12:56:32 +0200 Subject: [PATCH 066/331] src/southbridge: Remove unneeded include MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: If358e221021466f0058bfc84a322750b34a36d5f Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/32786 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki --- src/southbridge/intel/bd82x6x/early_usb.c | 1 - 1 file changed, 1 deletion(-) diff --git a/src/southbridge/intel/bd82x6x/early_usb.c b/src/southbridge/intel/bd82x6x/early_usb.c index 955737e2a8..e5d5625cab 100644 --- a/src/southbridge/intel/bd82x6x/early_usb.c +++ b/src/southbridge/intel/bd82x6x/early_usb.c @@ -14,7 +14,6 @@ * GNU General Public License for more details. */ -#include #include #include #include From 45b79be9c06ccc925eeb3c11e821413478b903b5 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Tue, 14 May 2019 12:55:56 +0200 Subject: [PATCH 067/331] src/soc: Remove unneeded include MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I5a7b53a07fe6fd6121067dcec004e81eb284edbb Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/32785 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki --- src/soc/amd/stoneyridge/enable_usbdebug.c | 1 - src/soc/amd/stoneyridge/southbridge.c | 1 - 2 files changed, 2 deletions(-) diff --git a/src/soc/amd/stoneyridge/enable_usbdebug.c b/src/soc/amd/stoneyridge/enable_usbdebug.c index 90bd6e8f33..19b9550847 100644 --- a/src/soc/amd/stoneyridge/enable_usbdebug.c +++ b/src/soc/amd/stoneyridge/enable_usbdebug.c @@ -17,7 +17,6 @@ #define __SIMPLE_DEVICE__ #include -#include #include #include #include diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c index 8dfef8b369..b6c40b63d3 100644 --- a/src/soc/amd/stoneyridge/southbridge.c +++ b/src/soc/amd/stoneyridge/southbridge.c @@ -15,7 +15,6 @@ #include -#include #include #include #include From 274dabd7a04b18bc2f2378bb9faa7416dfd0ab83 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Tue, 14 May 2019 12:55:17 +0200 Subject: [PATCH 068/331] src/northbridge: Remove unneeded include MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I52ace93ae6f802723823955ac349ed54dc064aaa Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/32784 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki --- src/northbridge/intel/gm45/early_reset.c | 1 - src/northbridge/intel/gm45/romstage.c | 1 - src/northbridge/intel/haswell/raminit.c | 1 - src/northbridge/intel/i945/raminit.c | 1 - src/northbridge/intel/pineview/raminit.c | 1 - src/northbridge/intel/pineview/romstage.c | 1 - src/northbridge/intel/sandybridge/raminit.c | 1 - src/northbridge/intel/sandybridge/raminit_mrc.c | 1 - src/northbridge/intel/sandybridge/romstage.c | 1 - src/northbridge/intel/x4x/raminit.c | 1 - 10 files changed, 10 deletions(-) diff --git a/src/northbridge/intel/gm45/early_reset.c b/src/northbridge/intel/gm45/early_reset.c index 3f095a256f..b5aa8044be 100644 --- a/src/northbridge/intel/gm45/early_reset.c +++ b/src/northbridge/intel/gm45/early_reset.c @@ -15,7 +15,6 @@ */ #include -#include #include #include diff --git a/src/northbridge/intel/gm45/romstage.c b/src/northbridge/intel/gm45/romstage.c index 15d3c3a344..38f2d5f68f 100644 --- a/src/northbridge/intel/gm45/romstage.c +++ b/src/northbridge/intel/gm45/romstage.c @@ -18,7 +18,6 @@ #include #include #include -#include #include #include #include diff --git a/src/northbridge/intel/haswell/raminit.c b/src/northbridge/intel/haswell/raminit.c index 96dc94e7d2..050dbd1ae6 100644 --- a/src/northbridge/intel/haswell/raminit.c +++ b/src/northbridge/intel/haswell/raminit.c @@ -15,7 +15,6 @@ #include #include -#include #include #include #include diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index 74407c14ff..797ea1229d 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -18,7 +18,6 @@ #include #include #include -#include #include #include #include diff --git a/src/northbridge/intel/pineview/raminit.c b/src/northbridge/intel/pineview/raminit.c index 144905fb92..282765efcc 100644 --- a/src/northbridge/intel/pineview/raminit.c +++ b/src/northbridge/intel/pineview/raminit.c @@ -14,7 +14,6 @@ * GNU General Public License for more details. */ -#include #include #include #include diff --git a/src/northbridge/intel/pineview/romstage.c b/src/northbridge/intel/pineview/romstage.c index a3e6c39172..41fb0f6720 100644 --- a/src/northbridge/intel/pineview/romstage.c +++ b/src/northbridge/intel/pineview/romstage.c @@ -17,7 +17,6 @@ * so this one is named with prefix mainboard. */ -#include #include #include #include diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index e60c37875b..2ebeaf0dca 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -21,7 +21,6 @@ #include #include #include -#include #include #include #include diff --git a/src/northbridge/intel/sandybridge/raminit_mrc.c b/src/northbridge/intel/sandybridge/raminit_mrc.c index a35d9d814e..f032b8aefc 100644 --- a/src/northbridge/intel/sandybridge/raminit_mrc.c +++ b/src/northbridge/intel/sandybridge/raminit_mrc.c @@ -18,7 +18,6 @@ #include #include #include -#include #include #include #include diff --git a/src/northbridge/intel/sandybridge/romstage.c b/src/northbridge/intel/sandybridge/romstage.c index 064d042e56..76b3088388 100644 --- a/src/northbridge/intel/sandybridge/romstage.c +++ b/src/northbridge/intel/sandybridge/romstage.c @@ -17,7 +17,6 @@ #include #include -#include #include #include #include diff --git a/src/northbridge/intel/x4x/raminit.c b/src/northbridge/intel/x4x/raminit.c index 60d3b55531..7fed1efe26 100644 --- a/src/northbridge/intel/x4x/raminit.c +++ b/src/northbridge/intel/x4x/raminit.c @@ -14,7 +14,6 @@ * GNU General Public License for more details. */ -#include #include #include #include From 8b7a16145254deff4ba5191463707d6981017357 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Tue, 14 May 2019 12:54:30 +0200 Subject: [PATCH 069/331] src/mainboard: Remove unneeded include MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I73c557d6ef009fb2cac35fdea500dee76f525330 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/32783 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki --- src/mainboard/apple/macbook21/romstage.c | 1 - src/mainboard/asus/p5gc-mx/romstage.c | 1 - src/mainboard/asus/p5qpl-am/romstage.c | 1 - src/mainboard/ibase/mb899/romstage.c | 1 - src/mainboard/intel/baskingridge/chromeos.c | 1 - src/mainboard/intel/dcp847ske/early_southbridge.c | 1 - src/mainboard/intel/emeraldlake2/chromeos.c | 1 - src/mainboard/kontron/986lcd-m/romstage.c | 1 - src/mainboard/lenovo/x60/romstage.c | 1 - src/mainboard/lenovo/z61t/romstage.c | 1 - 10 files changed, 10 deletions(-) diff --git a/src/mainboard/apple/macbook21/romstage.c b/src/mainboard/apple/macbook21/romstage.c index 468cffb7d9..1c84c8432b 100644 --- a/src/mainboard/apple/macbook21/romstage.c +++ b/src/mainboard/apple/macbook21/romstage.c @@ -18,7 +18,6 @@ /* __PRE_RAM__ means: use "unsigned" for device, not a struct. */ #include -#include #include #include #include diff --git a/src/mainboard/asus/p5gc-mx/romstage.c b/src/mainboard/asus/p5gc-mx/romstage.c index 08379f78a1..b076b9d7fb 100644 --- a/src/mainboard/asus/p5gc-mx/romstage.c +++ b/src/mainboard/asus/p5gc-mx/romstage.c @@ -18,7 +18,6 @@ // __PRE_RAM__ means: use "unsigned" for device, not a struct. #include -#include #include #include #include diff --git a/src/mainboard/asus/p5qpl-am/romstage.c b/src/mainboard/asus/p5qpl-am/romstage.c index bd6bfc6ee7..7d028434d6 100644 --- a/src/mainboard/asus/p5qpl-am/romstage.c +++ b/src/mainboard/asus/p5qpl-am/romstage.c @@ -15,7 +15,6 @@ * GNU General Public License for more details. */ -#include #include #include #include diff --git a/src/mainboard/ibase/mb899/romstage.c b/src/mainboard/ibase/mb899/romstage.c index 9cb1144b80..c98556c30f 100644 --- a/src/mainboard/ibase/mb899/romstage.c +++ b/src/mainboard/ibase/mb899/romstage.c @@ -16,7 +16,6 @@ // __PRE_RAM__ means: use "unsigned" for device, not a struct. #include -#include #include #include #include diff --git a/src/mainboard/intel/baskingridge/chromeos.c b/src/mainboard/intel/baskingridge/chromeos.c index 1673622793..6561927d3b 100644 --- a/src/mainboard/intel/baskingridge/chromeos.c +++ b/src/mainboard/intel/baskingridge/chromeos.c @@ -15,7 +15,6 @@ #include #include -#include #include #include #include diff --git a/src/mainboard/intel/dcp847ske/early_southbridge.c b/src/mainboard/intel/dcp847ske/early_southbridge.c index 778525f320..705ace9bc6 100644 --- a/src/mainboard/intel/dcp847ske/early_southbridge.c +++ b/src/mainboard/intel/dcp847ske/early_southbridge.c @@ -17,7 +17,6 @@ */ #include -#include #include #include #include diff --git a/src/mainboard/intel/emeraldlake2/chromeos.c b/src/mainboard/intel/emeraldlake2/chromeos.c index 219eefb871..699141fc0f 100644 --- a/src/mainboard/intel/emeraldlake2/chromeos.c +++ b/src/mainboard/intel/emeraldlake2/chromeos.c @@ -15,7 +15,6 @@ #include #include -#include #include #include #include diff --git a/src/mainboard/kontron/986lcd-m/romstage.c b/src/mainboard/kontron/986lcd-m/romstage.c index b85bd6883d..85a82c5acb 100644 --- a/src/mainboard/kontron/986lcd-m/romstage.c +++ b/src/mainboard/kontron/986lcd-m/romstage.c @@ -16,7 +16,6 @@ /* __PRE_RAM__ means: use "unsigned" for device, not a struct. */ #include -#include #include #include #include diff --git a/src/mainboard/lenovo/x60/romstage.c b/src/mainboard/lenovo/x60/romstage.c index ea93707ce9..b66ef66871 100644 --- a/src/mainboard/lenovo/x60/romstage.c +++ b/src/mainboard/lenovo/x60/romstage.c @@ -18,7 +18,6 @@ // __PRE_RAM__ means: use "unsigned" for device, not a struct. #include -#include #include #include #include diff --git a/src/mainboard/lenovo/z61t/romstage.c b/src/mainboard/lenovo/z61t/romstage.c index 47a52db39b..502eac39d5 100644 --- a/src/mainboard/lenovo/z61t/romstage.c +++ b/src/mainboard/lenovo/z61t/romstage.c @@ -18,7 +18,6 @@ // __PRE_RAM__ means: use "unsigned" for device, not a struct. #include -#include #include #include #include From 7aeeb4839023867d9a6c56854fb2e8a2143bf788 Mon Sep 17 00:00:00 2001 From: Alex James Date: Thu, 9 May 2019 10:40:46 -0500 Subject: [PATCH 070/331] util/lint/check-style: Don't hardcode clang-format path Signed-off-by: Alex James Change-Id: I688cb60c98370bf74aa8554bab43594ff84c4e24 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32707 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- util/lint/check-style | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/util/lint/check-style b/util/lint/check-style index 1ac51b4d1a..2237ed6295 100755 --- a/util/lint/check-style +++ b/util/lint/check-style @@ -15,7 +15,7 @@ ################################################################## # SETTINGS # set path to clang-format binary -CLANG_FORMAT="/usr/bin/clang-format" +CLANG_FORMAT="$(command -v clang-format)" # remove any older patches from previous commits. Set to true or false. # DELETE_OLD_PATCHES=false From dce10f8f92c4e771cf54544679fcbe10f094afdf Mon Sep 17 00:00:00 2001 From: Jacob Garber Date: Sat, 6 Apr 2019 16:10:36 -0600 Subject: [PATCH 071/331] payloads/coreinfo: Remove unused variable The 'last' variable is unused, and has been for the entire history of this file. Found-by: Clang Static Analyzer Signed-off-by: Jacob Garber Change-Id: Ic86a6d8d2b47585f901f1e48ae88735534c834ba Reviewed-on: https://review.coreboot.org/c/coreboot/+/32796 Tested-by: build bot (Jenkins) Reviewed-by: HAOUAS Elyes Reviewed-by: Martin Roth --- payloads/coreinfo/pci_module.c | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/payloads/coreinfo/pci_module.c b/payloads/coreinfo/pci_module.c index ff042af65d..3060161fe0 100644 --- a/payloads/coreinfo/pci_module.c +++ b/payloads/coreinfo/pci_module.c @@ -103,15 +103,10 @@ static void show_config_space(WINDOW *win, int row, int col, int index) static int pci_module_redraw(WINDOW *win) { unsigned int bus, slot, func; - int i, last; + int i; print_module_title(win, "PCI Device List"); - last = menu_first + MENU_VISIBLE; - - if (last > devices_index) - last = devices_index; - for (i = 0; i < MENU_VISIBLE; i++) { int item = menu_first + i; From 48b6be81a5753779f036818a62dd9d61c6abc9c0 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Wed, 15 May 2019 20:08:55 +0530 Subject: [PATCH 072/331] Remove remaining unnecessary ENV_RAMSTAGE guard TEST=Able to build coreboot for CML. Change-Id: I8a6a97d59277ebfc498c83bb039436ed7c89d2cd Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/32802 Tested-by: build bot (Jenkins) Reviewed-by: ron minnich --- src/drivers/intel/fsp2_0/include/fsp/info_header.h | 2 -- 1 file changed, 2 deletions(-) diff --git a/src/drivers/intel/fsp2_0/include/fsp/info_header.h b/src/drivers/intel/fsp2_0/include/fsp/info_header.h index e0659243ba..3e86b29c8d 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/info_header.h +++ b/src/drivers/intel/fsp2_0/include/fsp/info_header.h @@ -44,7 +44,6 @@ struct fsp_header { enum cb_err fsp_identify(struct fsp_header *hdr, const void *fsp_blob); -#if ENV_RAMSTAGE /* * This is a FSP_INFO_HEADER that came from fsps.bin blob. It contains * both SiliconInit and Notify APIs. When SiliconInit is loaded the @@ -52,6 +51,5 @@ enum cb_err fsp_identify(struct fsp_header *hdr, const void *fsp_blob); * header parsing again. */ extern struct fsp_header fsps_hdr; -#endif #endif /* _FSP2_0_INFO_HEADER_H_ */ From 6644a75b0e9fec0ba104e5249f238520b6e3f7f6 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Wed, 15 May 2019 20:12:27 +0530 Subject: [PATCH 073/331] drivers/elog: Rename ramstage_elog_add_boot_count() to elog_add_boot_count() This patch removes ramstage_ prefix from ramstage_elog_add_boot_count() function. Change-Id: Ia75b2dc959ace7dc26dc974c5f4b5cb6c5a25617 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/32803 Tested-by: build bot (Jenkins) Reviewed-by: ron minnich --- src/drivers/elog/elog.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/drivers/elog/elog.c b/src/drivers/elog/elog.c index 85b79983a5..e41b55bba5 100644 --- a/src/drivers/elog/elog.c +++ b/src/drivers/elog/elog.c @@ -797,7 +797,7 @@ static bool elog_do_add_boot_count(void) #endif } -static void ramstage_elog_add_boot_count(void) +static void elog_add_boot_count(void) { if (elog_do_add_boot_count()) { elog_add_event_dword(ELOG_TYPE_BOOT, boot_count_read()); @@ -860,7 +860,7 @@ int elog_init(void) es->full_threshold, es->shrink_size); if (ENV_RAMSTAGE) - ramstage_elog_add_boot_count(); + elog_add_boot_count(); return 0; } From e1909eea5c4dcf2f67c63d13c2bb74e10d2ba8a2 Mon Sep 17 00:00:00 2001 From: Jacob Garber Date: Tue, 14 May 2019 16:14:57 -0600 Subject: [PATCH 074/331] soc/intel/skylake: Correct GPIO pointer assignment We need to store the acpi_gpio struct, not save its address. Found-by: Clang Static Analyzer Signed-off-by: Jacob Garber Change-Id: I41c8bf10ce72bec736da97ccc33f9ada49804dc1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32797 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth --- src/soc/intel/skylake/sd.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/intel/skylake/sd.c b/src/soc/intel/skylake/sd.c index 12c6abe4fd..571d3e7b44 100644 --- a/src/soc/intel/skylake/sd.c +++ b/src/soc/intel/skylake/sd.c @@ -35,7 +35,7 @@ int sd_fill_soc_gpio_info(struct acpi_gpio* gpio, struct device *dev) gpio->pin_count = 1; gpio->pins[0] = config->sdcard_cd_gpio_default; } else - gpio = &config->sdcard_cd_gpio; + *gpio = config->sdcard_cd_gpio; return 0; } From 69486cac74a0e9578c90366feae8abebce5ff834 Mon Sep 17 00:00:00 2001 From: Marshall Dawson Date: Thu, 2 May 2019 12:03:45 -0600 Subject: [PATCH 075/331] soc/amd/common: Create AcpiMmio functionality from stoneyridge Move the stoneyridge AcpiMmio code into soc/amd/common. The SB800 southbridge introduced the MMIO hardware blocks at 0xfed80000 commonly known as AcpiMmio. Implementations beginning with Mullins enable decode in PMx04. Older designs use PMx24 and allow for configuring the base address. Future work may support the older version. Comparing the documentation for AMD's RRGs and BKDGs, it is evident that the block locations have not been reassigned across products. In some cases, address locations are deprecated and new ones consumed, e.g. the early GPIO blocks were simpler at offset 0x100 and the newer GPIO banks are now at 0x1500, 0x1600, and 0x1700. Note: Do not infer the definitions within the hardware blocks are consistent across family/model products. BUG=b:131682806 Change-Id: I083b6339cd29e72289e63c9331a815c46d71600d Signed-off-by: Marshall Dawson Reviewed-on: https://review.coreboot.org/c/coreboot/+/32649 Reviewed-by: Richard Spiegel Reviewed-by: Martin Roth Tested-by: build bot (Jenkins) --- src/mainboard/google/kahlee/mainboard.c | 1 + src/soc/amd/common/block/acpi/halt.c | 1 + src/soc/amd/common/block/acpimmio/Kconfig | 6 + .../amd/common/block/acpimmio/Makefile.inc | 6 + src/soc/amd/common/block/acpimmio/mmio_util.c | 379 ++++++++++++++++++ .../common/block/include/amdblocks/acpimmio.h | 101 +++++ .../block/include/amdblocks/acpimmio_map.h | 67 ++++ src/soc/amd/stoneyridge/Kconfig | 1 + src/soc/amd/stoneyridge/acpi.c | 1 + src/soc/amd/stoneyridge/gpio.c | 4 +- src/soc/amd/stoneyridge/include/soc/iomap.h | 29 +- .../amd/stoneyridge/include/soc/southbridge.h | 59 --- src/soc/amd/stoneyridge/lpc.c | 1 + src/soc/amd/stoneyridge/pmutil.c | 1 + src/soc/amd/stoneyridge/ramtop.c | 3 +- src/soc/amd/stoneyridge/reset.c | 1 + src/soc/amd/stoneyridge/sb_util.c | 351 +--------------- src/soc/amd/stoneyridge/smbus.c | 1 + src/soc/amd/stoneyridge/smi.c | 1 + src/soc/amd/stoneyridge/smi_util.c | 1 + src/soc/amd/stoneyridge/smihandler.c | 1 + src/soc/amd/stoneyridge/southbridge.c | 13 +- src/soc/amd/stoneyridge/usb.c | 2 +- 23 files changed, 582 insertions(+), 449 deletions(-) create mode 100644 src/soc/amd/common/block/acpimmio/Kconfig create mode 100644 src/soc/amd/common/block/acpimmio/Makefile.inc create mode 100644 src/soc/amd/common/block/acpimmio/mmio_util.c create mode 100644 src/soc/amd/common/block/include/amdblocks/acpimmio.h create mode 100644 src/soc/amd/common/block/include/amdblocks/acpimmio_map.h diff --git a/src/mainboard/google/kahlee/mainboard.c b/src/mainboard/google/kahlee/mainboard.c index ad979a567f..cfd5637633 100644 --- a/src/mainboard/google/kahlee/mainboard.c +++ b/src/mainboard/google/kahlee/mainboard.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include #include diff --git a/src/soc/amd/common/block/acpi/halt.c b/src/soc/amd/common/block/acpi/halt.c index 8f36efb042..200b3c12f5 100644 --- a/src/soc/amd/common/block/acpi/halt.c +++ b/src/soc/amd/common/block/acpi/halt.c @@ -15,6 +15,7 @@ #include #include +#include #include void poweroff(void) diff --git a/src/soc/amd/common/block/acpimmio/Kconfig b/src/soc/amd/common/block/acpimmio/Kconfig new file mode 100644 index 0000000000..f14cc0c227 --- /dev/null +++ b/src/soc/amd/common/block/acpimmio/Kconfig @@ -0,0 +1,6 @@ +config SOC_AMD_COMMON_BLOCK_ACPIMMIO + bool + default n + help + Select this option to enable hardware blocks in the AcpiMmio + address space (0xfed8xxxx). diff --git a/src/soc/amd/common/block/acpimmio/Makefile.inc b/src/soc/amd/common/block/acpimmio/Makefile.inc new file mode 100644 index 0000000000..9517b10b8a --- /dev/null +++ b/src/soc/amd/common/block/acpimmio/Makefile.inc @@ -0,0 +1,6 @@ +bootblock-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPIMMIO) += mmio_util.c +verstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPIMMIO) += mmio_util.c +romstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPIMMIO) += mmio_util.c +postcar-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPIMMIO) += mmio_util.c +ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPIMMIO) += mmio_util.c +smm-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPIMMIO) += mmio_util.c diff --git a/src/soc/amd/common/block/acpimmio/mmio_util.c b/src/soc/amd/common/block/acpimmio/mmio_util.c new file mode 100644 index 0000000000..7d4c4c5df1 --- /dev/null +++ b/src/soc/amd/common/block/acpimmio/mmio_util.c @@ -0,0 +1,379 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2017 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include + +void enable_acpimmio_decode(void) +{ + uint32_t dw; + + dw = pm_io_read32(ACPIMMIO_DECODE_REGISTER); + dw |= ACPIMMIO_DECODE_EN; + pm_io_write32(ACPIMMIO_DECODE_REGISTER, dw); +} + +/* PM registers are accessed a byte at a time via CD6/CD7 */ +uint8_t pm_io_read8(uint8_t reg) +{ + outb(reg, PM_INDEX); + return inb(PM_DATA); +} + +uint16_t pm_io_read16(uint8_t reg) +{ + return (pm_io_read8(reg + sizeof(uint8_t)) << 8) | pm_io_read8(reg); +} + +uint32_t pm_io_read32(uint8_t reg) +{ + return (pm_io_read16(reg + sizeof(uint16_t)) << 16) | pm_io_read16(reg); +} + +void pm_io_write8(uint8_t reg, uint8_t value) +{ + outb(reg, PM_INDEX); + outb(value, PM_DATA); +} + +void pm_io_write16(uint8_t reg, uint16_t value) +{ + pm_io_write8(reg, value & 0xff); + value >>= 8; + pm_io_write8(reg + sizeof(uint8_t), value & 0xff); +} + +void pm_io_write32(uint8_t reg, uint32_t value) +{ + pm_io_write16(reg, value & 0xffff); + value >>= 16; + pm_io_write16(reg + sizeof(uint16_t), value & 0xffff); +} + +/* smbus pci read/write - access registers at 0xfed80000 - currently unused */ + +/* smi read/write - access registers at 0xfed80200 */ + +uint8_t smi_read8(uint8_t offset) +{ + return read8((void *)(ACPIMMIO_SMI_BASE + offset)); +} + +uint16_t smi_read16(uint8_t offset) +{ + return read16((void *)(ACPIMMIO_SMI_BASE + offset)); +} + +uint32_t smi_read32(uint8_t offset) +{ + return read32((void *)(ACPIMMIO_SMI_BASE + offset)); +} + +void smi_write8(uint8_t offset, uint8_t value) +{ + write8((void *)(ACPIMMIO_SMI_BASE + offset), value); +} + +void smi_write16(uint8_t offset, uint16_t value) +{ + write16((void *)(ACPIMMIO_SMI_BASE + offset), value); +} + +void smi_write32(uint8_t offset, uint32_t value) +{ + write32((void *)(ACPIMMIO_SMI_BASE + offset), value); +} + +/* pm read/write - access registers at 0xfed80300 */ + +u8 pm_read8(u8 reg) +{ + return read8((void *)(ACPIMMIO_PMIO_BASE + reg)); +} + +u16 pm_read16(u8 reg) +{ + return read16((void *)(ACPIMMIO_PMIO_BASE + reg)); +} + +u32 pm_read32(u8 reg) +{ + return read32((void *)(ACPIMMIO_PMIO_BASE + reg)); +} + +void pm_write8(u8 reg, u8 value) +{ + write8((void *)(ACPIMMIO_PMIO_BASE + reg), value); +} + +void pm_write16(u8 reg, u16 value) +{ + write16((void *)(ACPIMMIO_PMIO_BASE + reg), value); +} + +void pm_write32(u8 reg, u32 value) +{ + write32((void *)(ACPIMMIO_PMIO_BASE + reg), value); +} + +/* pm2 read/write - access registers at 0xfed80400 - currently unused */ + +/* biosram read/write - access registers at 0xfed80500 */ + +uint8_t biosram_read8(uint8_t offset) +{ + return read8((void *)(ACPIMMIO_BIOSRAM_BASE + offset)); +} + +uint16_t biosram_read16(uint8_t offset) /* Must be 1 byte at a time */ +{ + int i; + uint16_t value = 0; + for (i = sizeof(value) - 1 ; i >= 0 ; i--) + value = (value << 8) | biosram_read8(offset + i); + return value; +} + +uint32_t biosram_read32(uint8_t offset) +{ + uint32_t value = biosram_read16(offset + sizeof(uint16_t)) << 16; + return value | biosram_read16(offset); +} + +void biosram_write8(uint8_t offset, uint8_t value) +{ + write8((void *)(ACPIMMIO_BIOSRAM_BASE + offset), value); +} + +void biosram_write16(uint8_t offset, uint16_t value) +{ + int i; + for (i = 0 ; i < sizeof(value) ; i++) { + biosram_write8(offset + i, value & 0xff); + value >>= 8; + } +} + +void biosram_write32(uint8_t offset, uint32_t value) +{ + int i; + for (i = 0 ; i < sizeof(value) ; i++) { + biosram_write8(offset + i, value & 0xff); + value >>= 8; + } +} + +/* cmosram read/write - access registers at 0xfed80600 - currently unused */ + +/* cmos read/write - access registers at 0xfed80700 - currently unused */ + +/* acpi read/write - access registers at 0xfed80800 */ + +u8 acpi_read8(u8 reg) +{ + return read8((void *)(ACPIMMIO_ACPI_BASE + reg)); +} + +u16 acpi_read16(u8 reg) +{ + return read16((void *)(ACPIMMIO_ACPI_BASE + reg)); +} + +u32 acpi_read32(u8 reg) +{ + return read32((void *)(ACPIMMIO_ACPI_BASE + reg)); +} + +void acpi_write8(u8 reg, u8 value) +{ + write8((void *)(ACPIMMIO_ACPI_BASE + reg), value); +} + +void acpi_write16(u8 reg, u16 value) +{ + write16((void *)(ACPIMMIO_ACPI_BASE + reg), value); +} + +void acpi_write32(u8 reg, u32 value) +{ + write32((void *)(ACPIMMIO_ACPI_BASE + reg), value); +} + +/* asf read/write - access registers at 0xfed80900 - not currently used */ + +u8 asf_read8(u8 reg) +{ + return read8((void *)(ACPIMMIO_ASF_BASE + reg)); +} + +u16 asf_read16(u8 reg) +{ + return read16((void *)(ACPIMMIO_ASF_BASE + reg)); +} + +void asf_write8(u8 reg, u8 value) +{ + write8((void *)(ACPIMMIO_ASF_BASE + reg), value); +} + +void asf_write16(u8 reg, u16 value) +{ + write16((void *)(ACPIMMIO_ASF_BASE + reg), value); +} + +/* smbus read/write - access registers at 0xfed80a00 and ASF at 0xfed80900 */ + +u8 smbus_read8(u8 reg) +{ + return read8((void *)(ACPIMMIO_SMBUS_BASE + reg)); +} + +u16 smbus_read16(u8 reg) +{ + return read16((void *)(ACPIMMIO_SMBUS_BASE + reg)); +} + +void smbus_write8(u8 reg, u8 value) +{ + write8((void *)(ACPIMMIO_SMBUS_BASE + reg), value); +} + +void smbus_write16(u8 reg, u16 value) +{ + write16((void *)(ACPIMMIO_SMBUS_BASE + reg), value); +} + +/* wdt read/write - access registers at 0xfed80b00 - not currently used */ + +/* hpet read/write - access registers at 0xfed80c00 - not currently used */ + +/* iomux read/write - access registers at 0xfed80d00 */ + +u8 iomux_read8(u8 reg) +{ + return read8((void *)(ACPIMMIO_IOMUX_BASE + reg)); +} + +u16 iomux_read16(u8 reg) +{ + return read16((void *)(ACPIMMIO_IOMUX_BASE + reg)); +} + +u32 iomux_read32(u8 reg) +{ + return read32((void *)(ACPIMMIO_IOMUX_BASE + reg)); +} + +void iomux_write8(u8 reg, u8 value) +{ + write8((void *)(ACPIMMIO_IOMUX_BASE + reg), value); +} + +void iomux_write16(u8 reg, u16 value) +{ + write16((void *)(ACPIMMIO_IOMUX_BASE + reg), value); +} + +void iomux_write32(u8 reg, u32 value) +{ + write32((void *)(ACPIMMIO_IOMUX_BASE + reg), value); +} + +/* misc read/write - access registers at 0xfed80e00 */ + +u8 misc_read8(u8 reg) +{ + return read8((void *)(ACPIMMIO_MISC_BASE + reg)); +} + +u16 misc_read16(u8 reg) +{ + return read16((void *)(ACPIMMIO_MISC_BASE + reg)); +} + +u32 misc_read32(u8 reg) +{ + return read32((void *)(ACPIMMIO_MISC_BASE + reg)); +} + +void misc_write8(u8 reg, u8 value) +{ + write8((void *)(ACPIMMIO_MISC_BASE + reg), value); +} + +void misc_write16(u8 reg, u16 value) +{ + write16((void *)(ACPIMMIO_MISC_BASE + reg), value); +} + +void misc_write32(u8 reg, u32 value) +{ + write32((void *)(ACPIMMIO_MISC_BASE + reg), value); +} + +/* dpvga read/write - access registers at 0xfed81400 - not currently used */ + +/* gpio bk 0 read/write - access registers at 0xfed81500 - not currently used */ +/* gpio bk 1 read/write - access registers at 0xfed81600 - not currently used */ +/* gpio bk 2 read/write - access registers at 0xfed81700 - not currently used */ + +/* xhci_pm read/write - access registers at 0xfed81c00 */ + +uint8_t xhci_pm_read8(uint8_t reg) +{ + return read8((void *)(ACPIMMIO_XHCIPM_BASE + reg)); +} + +uint16_t xhci_pm_read16(uint8_t reg) +{ + return read16((void *)(ACPIMMIO_XHCIPM_BASE + reg)); +} + +uint32_t xhci_pm_read32(uint8_t reg) +{ + return read32((void *)(ACPIMMIO_XHCIPM_BASE + reg)); +} + +void xhci_pm_write8(uint8_t reg, uint8_t value) +{ + write8((void *)(ACPIMMIO_XHCIPM_BASE + reg), value); +} + +void xhci_pm_write16(uint8_t reg, uint16_t value) +{ + write16((void *)(ACPIMMIO_XHCIPM_BASE + reg), value); +} + +void xhci_pm_write32(uint8_t reg, uint32_t value) +{ + write32((void *)(ACPIMMIO_XHCIPM_BASE + reg), value); +} + +/* acdc_tmr read/write - access registers at 0xfed81d00 */ + +/* aoac read/write - access registers at 0xfed81e00 - not currently used */ + +u8 aoac_read8(u8 reg) +{ + return read8((void *)(ACPIMMIO_AOAC_BASE + reg)); +} + +void aoac_write8(u8 reg, u8 value) +{ + write8((void *)(ACPIMMIO_AOAC_BASE + reg), value); +} diff --git a/src/soc/amd/common/block/include/amdblocks/acpimmio.h b/src/soc/amd/common/block/include/amdblocks/acpimmio.h new file mode 100644 index 0000000000..e1cf7cbdc2 --- /dev/null +++ b/src/soc/amd/common/block/include/amdblocks/acpimmio.h @@ -0,0 +1,101 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Advanced Micro Devices, Inc. + * Copyright (C) 2014 Alexandru Gagniuc + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License, or (at your + * option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __AMDBLOCKS_ACPIMMIO_H__ +#define __AMDBLOCKS_ACPIMMIO_H__ + +void enable_acpimmio_decode(void); +uint8_t pm_io_read8(uint8_t reg); +uint16_t pm_io_read16(uint8_t reg); +uint32_t pm_io_read32(uint8_t reg); +void pm_io_write8(uint8_t reg, uint8_t value); +void pm_io_write16(uint8_t reg, uint16_t value); +void pm_io_write32(uint8_t reg, uint32_t value); +uint8_t smi_read8(uint8_t offset); +uint16_t smi_read16(uint8_t offset); +uint32_t smi_read32(uint8_t offset); +void smi_write8(uint8_t offset, uint8_t value); +void smi_write16(uint8_t offset, uint16_t value); +void smi_write32(uint8_t offset, uint32_t value); +uint8_t pm_read8(uint8_t reg); +uint16_t pm_read16(uint8_t reg); +uint32_t pm_read32(uint8_t reg); +void pm_write8(uint8_t reg, uint8_t value); +void pm_write16(uint8_t reg, uint16_t value); +void pm_write32(uint8_t reg, uint32_t value); +uint8_t pm2_read8(uint8_t reg); +uint16_t pm2_read16(uint8_t reg); +uint32_t pm2_read32(uint8_t reg); +void pm2_write8(uint8_t reg, uint8_t value); +void pm2_write16(uint8_t reg, uint16_t value); +void pm2_write32(uint8_t reg, uint32_t value); +uint8_t biosram_read8(uint8_t offset); +void biosram_write8(uint8_t offset, uint8_t value); +uint16_t biosram_read16(uint8_t offset); +uint32_t biosram_read32(uint8_t offset); +void biosram_write16(uint8_t offset, uint16_t value); +void biosram_write32(uint8_t offset, uint32_t value); +uint8_t acpi_read8(uint8_t reg); +uint16_t acpi_read16(uint8_t reg); +uint32_t acpi_read32(uint8_t reg); +void acpi_write8(uint8_t reg, uint8_t value); +void acpi_write16(uint8_t reg, uint16_t value); +void acpi_write32(uint8_t reg, uint32_t value); +uint8_t asf_read8(uint8_t reg); +uint16_t asf_read16(uint8_t reg); +uint32_t asf_read32(uint8_t reg); +void asf_write8(uint8_t reg, uint8_t value); +void asf_write16(uint8_t reg, uint16_t value); +void asf_write32(uint8_t reg, uint32_t value); +uint8_t smbus_read8(uint8_t reg); +uint16_t smbus_read16(uint8_t reg); +void smbus_write8(uint8_t reg, uint8_t value); +void smbus_write16(uint8_t reg, uint16_t value); +uint8_t wdt_read8(uint8_t reg); +uint16_t wdt_read16(uint8_t reg); +uint32_t wdt_read32(uint8_t reg); +void wdt_write8(uint8_t reg, uint8_t value); +void wdt_write16(uint8_t reg, uint16_t value); +void wdt_write32(uint8_t reg, uint32_t value); +uint8_t hpet_read8(uint8_t reg); +uint16_t hpet_read16(uint8_t reg); +uint32_t hpet_read32(uint8_t reg); +void hpet_write8(uint8_t reg, uint8_t value); +void hpet_write16(uint8_t reg, uint16_t value); +void hpet_write32(uint8_t reg, uint32_t value); +uint8_t iomux_read8(uint8_t reg); +uint16_t iomux_read16(uint8_t reg); +uint32_t iomux_read32(uint8_t reg); +void iomux_write8(uint8_t reg, uint8_t value); +void iomux_write16(uint8_t reg, uint16_t value); +void iomux_write32(uint8_t reg, uint32_t value); +uint8_t misc_read8(uint8_t reg); +uint16_t misc_read16(uint8_t reg); +uint32_t misc_read32(uint8_t reg); +void misc_write8(uint8_t reg, uint8_t value); +void misc_write16(uint8_t reg, uint16_t value); +void misc_write32(uint8_t reg, uint32_t value); +uint8_t xhci_pm_read8(uint8_t reg); +uint16_t xhci_pm_read16(uint8_t reg); +uint32_t xhci_pm_read32(uint8_t reg); +void xhci_pm_write8(uint8_t reg, uint8_t value); +void xhci_pm_write16(uint8_t reg, uint16_t value); +void xhci_pm_write32(uint8_t reg, uint32_t value); +uint8_t aoac_read8(uint8_t reg); +void aoac_write8(uint8_t reg, uint8_t value); + +#endif /* __AMDBLOCKS_ACPIMMIO_H__ */ diff --git a/src/soc/amd/common/block/include/amdblocks/acpimmio_map.h b/src/soc/amd/common/block/include/amdblocks/acpimmio_map.h new file mode 100644 index 0000000000..755af52d4f --- /dev/null +++ b/src/soc/amd/common/block/include/amdblocks/acpimmio_map.h @@ -0,0 +1,67 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Advanced Micro Devices, Inc. + * Copyright (C) 2014 Alexandru Gagniuc + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License, or (at your + * option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __AMDBLOCKS_ACPIMMIO_MAP_H__ +#define __AMDBLOCKS_ACPIMMIO_MAP_H__ + +/* IO index/data for accessing PMIO prior to enabling MMIO decode */ +#define PM_INDEX 0xcd6 +#define PM_DATA 0xcd7 + +/* TODO: In the event this is ported backward far enough, earlier devices + * enable the decode in PMx24 instead. All discrete FCHs and the Kabini + * SoC fall into this category. Kabini's successor, Mullins, uses this + * newer method. + */ +#define ACPIMMIO_DECODE_REGISTER 0x4 +#define ACPIMMIO_DECODE_EN BIT(0) + +/* MMIO register blocks are at fixed offsets from 0xfed80000 and are enabled + * in PMx24[1] (older implementations) and PMx04[1] (newer implementations). + * PM registers are also accessible via IO CD6/CD7. + * + * All products do not support all blocks below, however AMD has avoided + * redefining addresses and consumes new ranges as necessary. + * + * Definitions within each block are not guaranteed to remain consistent + * across family/model products. + */ + +#define AMD_SB_ACPI_MMIO_ADDR 0xfed80000 +#define ACPIMMIO_SM_PCI_BASE 0xfed80000 +#define ACPIMMIO_SMI_BASE 0xfed80200 +#define ACPIMMIO_PMIO_BASE 0xfed80300 +#define ACPIMMIO_PMIO2_BASE 0xfed80400 +#define ACPIMMIO_BIOSRAM_BASE 0xfed80500 +#define ACPIMMIO_CMOSRAM_BASE 0xfed80600 +#define ACPIMMIO_CMOS_BASE 0xfed80700 +#define ACPIMMIO_ACPI_BASE 0xfed80800 +#define ACPIMMIO_ASF_BASE 0xfed80900 +#define ACPIMMIO_SMBUS_BASE 0xfed80a00 +#define ACPIMMIO_WDT_BASE 0xfed80b00 +#define ACPIMMIO_HPET_BASE 0xfed80c00 +#define ACPIMMIO_IOMUX_BASE 0xfed80d00 +#define ACPIMMIO_MISC_BASE 0xfed80e00 +#define ACPIMMIO_DPVGA_BASE 0xfed81400 +#define ACPIMMIO_GPIO0_BASE 0xfed81500 +#define ACPIMMIO_GPIO1_BASE 0xfed81600 +#define ACPIMMIO_GPIO2_BASE 0xfed81700 +#define ACPIMMIO_XHCIPM_BASE 0xfed81c00 +#define ACPIMMIO_ACDCTMR_BASE 0xfed81d00 +#define ACPIMMIO_AOAC_BASE 0xfed81e00 + +#endif /* __AMDBLOCKS_ACPIMMIO_MAP_H__ */ diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig index 29ab149df9..d4e1feb251 100644 --- a/src/soc/amd/stoneyridge/Kconfig +++ b/src/soc/amd/stoneyridge/Kconfig @@ -46,6 +46,7 @@ config CPU_SPECIFIC_OPTIONS select SOC_AMD_PI select SOC_AMD_COMMON select SOC_AMD_COMMON_BLOCK + select SOC_AMD_COMMON_BLOCK_ACPIMMIO select SOC_AMD_COMMON_BLOCK_PCI select SOC_AMD_COMMON_BLOCK_PI select SOC_AMD_COMMON_BLOCK_PSP diff --git a/src/soc/amd/stoneyridge/acpi.c b/src/soc/amd/stoneyridge/acpi.c index 227fb70136..4f11ea227a 100644 --- a/src/soc/amd/stoneyridge/acpi.c +++ b/src/soc/amd/stoneyridge/acpi.c @@ -28,6 +28,7 @@ #include #include #include +#include #include #include #include diff --git a/src/soc/amd/stoneyridge/gpio.c b/src/soc/amd/stoneyridge/gpio.c index 285fedd238..01ced0880b 100644 --- a/src/soc/amd/stoneyridge/gpio.c +++ b/src/soc/amd/stoneyridge/gpio.c @@ -16,13 +16,15 @@ */ #include +#include #include #include #include +#include #include #include -#include #include +#include "chip.h" static const struct soc_amd_event gpio_event_table[] = { { GPIO_1, GEVENT_19 }, diff --git a/src/soc/amd/stoneyridge/include/soc/iomap.h b/src/soc/amd/stoneyridge/include/soc/iomap.h index e6327dc6db..7762043119 100644 --- a/src/soc/amd/stoneyridge/include/soc/iomap.h +++ b/src/soc/amd/stoneyridge/include/soc/iomap.h @@ -22,6 +22,9 @@ #define SPI_BASE_ADDRESS 0xfec10000 #define IO_APIC2_ADDR 0xfec20000 +/* AcpiMmio blocks are at fixed offsets from FED8_0000h, enabled in PMx04[1] */ +#include + /* I2C fixed address */ #define I2C_BASE_ADDRESS 0xfedc2000 #define I2C_DEVICE_SIZE 0x00001000 @@ -32,30 +35,6 @@ #endif #define HPET_BASE_ADDRESS 0xfed00000 -/* AcpiMmio blocks are at fixed offsets from FED8_0000h, enabled in PMx04[1] */ -#define AMD_SB_ACPI_MMIO_ADDR 0xfed80000 -#define ACPIMMIO_SM_PCI_BASE 0xfed80000 -#define ACPIMMIO_SMI_BASE 0xfed80200 -#define ACPIMMIO_PMIO_BASE 0xfed80300 -#define ACPIMMIO_PMIO2_BASE 0xfed80400 -#define ACPIMMIO_BIOSRAM_BASE 0xfed80500 -#define ACPIMMIO_CMOSRAM_BASE 0xfed80600 -#define ACPIMMIO_CMOS_BASE 0xfed80700 -#define ACPIMMIO_ACPI_BASE 0xfed80800 -#define ACPIMMIO_ASF_BASE 0xfed80900 -#define ACPIMMIO_SMBUS_BASE 0xfed80a00 -#define ACPIMMIO_WDT_BASE 0xfed80b00 -#define ACPIMMIO_HPET_BASE 0xfed80c00 -#define ACPIMMIO_IOMUX_BASE 0xfed80d00 -#define ACPIMMIO_MISC_BASE 0xfed80e00 -#define ACPIMMIO_DPVGA_BASE 0xfed81400 -#define ACPIMMIO_GPIO0_BASE 0xfed81500 -#define ACPIMMIO_GPIO1_BASE 0xfed81600 -#define ACPIMMIO_GPIO2_BASE 0xfed81700 -#define ACPIMMIO_XHCIPM_BASE 0xfed81c00 -#define ACPIMMIO_ACDCTMR_BASE 0xfed81d00 -#define ACPIMMIO_AOAC_BASE 0xfed81e00 - #define APU_UART0_BASE 0xfedc6000 #define APU_UART1_BASE 0xfedc8000 @@ -78,8 +57,6 @@ #define PM2_DATA 0xcd1 #define BIOSRAM_INDEX 0xcd4 #define BIOSRAM_DATA 0xcd5 -#define PM_INDEX 0xcd6 -#define PM_DATA 0xcd7 #define AB_INDX 0xcd8 #define AB_DATA (AB_INDX+4) #define SYS_RESET 0xcf9 diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h index 618a5deff7..6734efb04d 100644 --- a/src/soc/amd/stoneyridge/include/soc/southbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h @@ -483,7 +483,6 @@ void southbridge_final(void *chip_info); void southbridge_init(void *chip_info); void sb_lpc_port80(void); void sb_lpc_decode(void); -void sb_acpi_mmio_decode(void); void sb_pci_port80(void); void sb_read_mode(u32 mode); void sb_set_spi100(u16 norm, u16 fast, u16 alt, u16 tpm); @@ -491,66 +490,8 @@ void sb_tpm_decode(void); void sb_tpm_decode_spi(void); void lpc_wideio_512_window(uint16_t base); void lpc_wideio_16_window(uint16_t base); -uint8_t pm_io_read8(uint8_t reg); -uint16_t pm_io_read16(uint8_t reg); -uint32_t pm_io_read32(uint8_t reg); -void pm_io_write8(uint8_t reg, uint8_t value); -void pm_io_write16(uint8_t reg, uint16_t value); -void pm_io_write32(uint8_t reg, uint32_t value); -u8 pm_read8(u8 reg); -u16 pm_read16(u8 reg); -u32 pm_read32(u8 reg); -void pm_write8(u8 reg, u8 value); -void pm_write16(u8 reg, u16 value); -void pm_write32(u8 reg, u32 value); -u8 acpi_read8(u8 reg); -u16 acpi_read16(u8 reg); -u32 acpi_read32(u8 reg); -void acpi_write8(u8 reg, u8 value); -void acpi_write16(u8 reg, u16 value); -void acpi_write32(u8 reg, u32 value); -u8 misc_read8(u8 reg); -u16 misc_read16(u8 reg); -u32 misc_read32(u8 reg); -void misc_write8(u8 reg, u8 value); -void misc_write16(u8 reg, u16 value); -void misc_write32(u8 reg, u32 value); -uint8_t smi_read8(uint8_t offset); -uint16_t smi_read16(uint8_t offset); -uint32_t smi_read32(uint8_t offset); -void smi_write8(uint8_t offset, uint8_t value); -void smi_write16(uint8_t offset, uint16_t value); -void smi_write32(uint8_t offset, uint32_t value); -uint8_t biosram_read8(uint8_t offset); -void biosram_write8(uint8_t offset, uint8_t value); -uint16_t biosram_read16(uint8_t offset); -void biosram_write16(uint8_t offset, uint16_t value); -uint32_t biosram_read32(uint8_t offset); -void biosram_write32(uint8_t offset, uint32_t value); uint16_t pm_acpi_pm_cnt_blk(void); uint16_t pm_acpi_pm_evt_blk(void); -void xhci_pm_write8(uint8_t reg, uint8_t value); -uint8_t xhci_pm_read8(uint8_t reg); -void xhci_pm_write16(uint8_t reg, uint16_t value); -uint16_t xhci_pm_read16(uint8_t reg); -void xhci_pm_write32(uint8_t reg, uint32_t value); -uint32_t xhci_pm_read32(uint8_t reg); -u8 iomux_read8(u8 reg); -u16 iomux_read16(u8 reg); -u32 iomux_read32(u8 reg); -void iomux_write8(u8 reg, u8 value); -void iomux_write16(u8 reg, u16 value); -void iomux_write32(u8 reg, u32 value); -uint8_t asf_read8(uint8_t offset); -uint16_t asf_read16(uint8_t offset); -void asf_write8(uint8_t offset, uint8_t value); -void asf_write16(uint8_t offset, uint16_t value); -uint8_t smbus_read8(uint8_t offset); -uint16_t smbus_read16(uint8_t offset); -void smbus_write8(uint8_t offset, uint8_t value); -void smbus_write16(uint8_t offset, uint16_t value); -uint8_t aoac_read8(uint8_t reg); -void aoac_write8(uint8_t reg, uint8_t value); void bootblock_fch_early_init(void); void bootblock_fch_init(void); /** diff --git a/src/soc/amd/stoneyridge/lpc.c b/src/soc/amd/stoneyridge/lpc.c index a838146c84..3ace1fdce6 100644 --- a/src/soc/amd/stoneyridge/lpc.c +++ b/src/soc/amd/stoneyridge/lpc.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include #include diff --git a/src/soc/amd/stoneyridge/pmutil.c b/src/soc/amd/stoneyridge/pmutil.c index bfb5f424ef..7367251193 100644 --- a/src/soc/amd/stoneyridge/pmutil.c +++ b/src/soc/amd/stoneyridge/pmutil.c @@ -15,6 +15,7 @@ #include #include +#include #include #include #include diff --git a/src/soc/amd/stoneyridge/ramtop.c b/src/soc/amd/stoneyridge/ramtop.c index f43fcf37ec..7c855bb1e1 100644 --- a/src/soc/amd/stoneyridge/ramtop.c +++ b/src/soc/amd/stoneyridge/ramtop.c @@ -25,7 +25,8 @@ #include #include #include -#include +#include +#include void backup_top_of_low_cacheable(uintptr_t ramtop) { diff --git a/src/soc/amd/stoneyridge/reset.c b/src/soc/amd/stoneyridge/reset.c index 34aa576a09..ec5ee910d9 100644 --- a/src/soc/amd/stoneyridge/reset.c +++ b/src/soc/amd/stoneyridge/reset.c @@ -20,6 +20,7 @@ #include #include #include +#include #include void set_warm_reset_flag(void) diff --git a/src/soc/amd/stoneyridge/sb_util.c b/src/soc/amd/stoneyridge/sb_util.c index 524efc45ad..11bf73a723 100644 --- a/src/soc/amd/stoneyridge/sb_util.c +++ b/src/soc/amd/stoneyridge/sb_util.c @@ -16,358 +16,9 @@ #include #include #include +#include #include -/* PM registers are accessed a byte at a time via CD6/CD7 */ -uint8_t pm_io_read8(uint8_t reg) -{ - outb(reg, PM_INDEX); - return inb(PM_DATA); -} - -uint16_t pm_io_read16(uint8_t reg) -{ - return (pm_io_read8(reg + sizeof(uint8_t)) << 8) | pm_io_read8(reg); -} - -uint32_t pm_io_read32(uint8_t reg) -{ - return (pm_io_read16(reg + sizeof(uint16_t)) << 16) | pm_io_read16(reg); -} - -void pm_io_write8(uint8_t reg, uint8_t value) -{ - outb(reg, PM_INDEX); - outb(value, PM_DATA); -} - -void pm_io_write16(uint8_t reg, uint16_t value) -{ - pm_io_write8(reg, value & 0xff); - value >>= 8; - pm_io_write8(reg + sizeof(uint8_t), value & 0xff); -} - -void pm_io_write32(uint8_t reg, uint32_t value) -{ - pm_io_write16(reg, value & 0xffff); - value >>= 16; - pm_io_write16(reg + sizeof(uint16_t), value & 0xffff); -} - -/* smbus pci read/write - access registers at 0xfed80000 - currently unused */ - -/* smi read/write - access registers at 0xfed80200 */ - -uint8_t smi_read8(uint8_t offset) -{ - return read8((void *)(ACPIMMIO_SMI_BASE + offset)); -} - -uint16_t smi_read16(uint8_t offset) -{ - return read16((void *)(ACPIMMIO_SMI_BASE + offset)); -} - -uint32_t smi_read32(uint8_t offset) -{ - return read32((void *)(ACPIMMIO_SMI_BASE + offset)); -} - -void smi_write8(uint8_t offset, uint8_t value) -{ - write8((void *)(ACPIMMIO_SMI_BASE + offset), value); -} - -void smi_write16(uint8_t offset, uint16_t value) -{ - write16((void *)(ACPIMMIO_SMI_BASE + offset), value); -} - -void smi_write32(uint8_t offset, uint32_t value) -{ - write32((void *)(ACPIMMIO_SMI_BASE + offset), value); -} - -/* pm read/write - access registers at 0xfed80300 */ - -u8 pm_read8(u8 reg) -{ - return read8((void *)(ACPIMMIO_PMIO_BASE + reg)); -} - -u16 pm_read16(u8 reg) -{ - return read16((void *)(ACPIMMIO_PMIO_BASE + reg)); -} - -u32 pm_read32(u8 reg) -{ - return read32((void *)(ACPIMMIO_PMIO_BASE + reg)); -} - -void pm_write8(u8 reg, u8 value) -{ - write8((void *)(ACPIMMIO_PMIO_BASE + reg), value); -} - -void pm_write16(u8 reg, u16 value) -{ - write16((void *)(ACPIMMIO_PMIO_BASE + reg), value); -} - -void pm_write32(u8 reg, u32 value) -{ - write32((void *)(ACPIMMIO_PMIO_BASE + reg), value); -} - -/* pm2 read/write - access registers at 0xfed80400 - currently unused */ - -/* biosram read/write - access registers at 0xfed80500 */ - -uint8_t biosram_read8(uint8_t offset) -{ - return read8((void *)(ACPIMMIO_BIOSRAM_BASE + offset)); -} - -uint16_t biosram_read16(uint8_t offset) /* Must be 1 byte at a time */ -{ - int i; - uint16_t value = 0; - for (i = sizeof(value) - 1 ; i >= 0 ; i--) - value = (value << 8) | biosram_read8(offset + i); - return value; -} - -uint32_t biosram_read32(uint8_t offset) -{ - uint32_t value = biosram_read16(offset + sizeof(uint16_t)) << 16; - return value | biosram_read16(offset); -} - -void biosram_write8(uint8_t offset, uint8_t value) -{ - write8((void *)(ACPIMMIO_BIOSRAM_BASE + offset), value); -} - -void biosram_write16(uint8_t offset, uint16_t value) -{ - int i; - for (i = 0 ; i < sizeof(value) ; i++) { - biosram_write8(offset + i, value & 0xff); - value >>= 8; - } -} - -void biosram_write32(uint8_t offset, uint32_t value) -{ - int i; - for (i = 0 ; i < sizeof(value) ; i++) { - biosram_write8(offset + i, value & 0xff); - value >>= 8; - } -} - -/* cmosram read/write - access registers at 0xfed80600 - currently unused */ - -/* cmos read/write - access registers at 0xfed80700 - currently unused */ - -/* acpi read/write - access registers at 0xfed80800 */ - -u8 acpi_read8(u8 reg) -{ - return read8((void *)(ACPIMMIO_ACPI_BASE + reg)); -} - -u16 acpi_read16(u8 reg) -{ - return read16((void *)(ACPIMMIO_ACPI_BASE + reg)); -} - -u32 acpi_read32(u8 reg) -{ - return read32((void *)(ACPIMMIO_ACPI_BASE + reg)); -} - -void acpi_write8(u8 reg, u8 value) -{ - write8((void *)(ACPIMMIO_ACPI_BASE + reg), value); -} - -void acpi_write16(u8 reg, u16 value) -{ - write16((void *)(ACPIMMIO_ACPI_BASE + reg), value); -} - -void acpi_write32(u8 reg, u32 value) -{ - write32((void *)(ACPIMMIO_ACPI_BASE + reg), value); -} - -/* asf read/write - access registers at 0xfed80900 - not currently used */ - -u8 asf_read8(u8 reg) -{ - return read8((void *)(ACPIMMIO_ASF_BASE + reg)); -} - -u16 asf_read16(u8 reg) -{ - return read16((void *)(ACPIMMIO_ASF_BASE + reg)); -} - -void asf_write8(u8 reg, u8 value) -{ - write8((void *)(ACPIMMIO_ASF_BASE + reg), value); -} - -void asf_write16(u8 reg, u16 value) -{ - write16((void *)(ACPIMMIO_ASF_BASE + reg), value); -} - -/* smbus read/write - access registers at 0xfed80a00 and ASF at 0xfed80900 */ - -u8 smbus_read8(u8 reg) -{ - return read8((void *)(ACPIMMIO_SMBUS_BASE + reg)); -} - -u16 smbus_read16(u8 reg) -{ - return read16((void *)(ACPIMMIO_SMBUS_BASE + reg)); -} - -void smbus_write8(u8 reg, u8 value) -{ - write8((void *)(ACPIMMIO_SMBUS_BASE + reg), value); -} - -void smbus_write16(u8 reg, u16 value) -{ - write16((void *)(ACPIMMIO_SMBUS_BASE + reg), value); -} - -/* wdt read/write - access registers at 0xfed80b00 - not currently used */ - -/* hpet read/write - access registers at 0xfed80c00 - not currently used */ - -/* iomux read/write - access registers at 0xfed80d00 */ - -u8 iomux_read8(u8 reg) -{ - return read8((void *)(ACPIMMIO_IOMUX_BASE + reg)); -} - -u16 iomux_read16(u8 reg) -{ - return read16((void *)(ACPIMMIO_IOMUX_BASE + reg)); -} - -u32 iomux_read32(u8 reg) -{ - return read32((void *)(ACPIMMIO_IOMUX_BASE + reg)); -} - -void iomux_write8(u8 reg, u8 value) -{ - write8((void *)(ACPIMMIO_IOMUX_BASE + reg), value); -} - -void iomux_write16(u8 reg, u16 value) -{ - write16((void *)(ACPIMMIO_IOMUX_BASE + reg), value); -} - -void iomux_write32(u8 reg, u32 value) -{ - write32((void *)(ACPIMMIO_IOMUX_BASE + reg), value); -} - -/* misc read/write - access registers at 0xfed80e00 */ - -u8 misc_read8(u8 reg) -{ - return read8((void *)(ACPIMMIO_MISC_BASE + reg)); -} - -u16 misc_read16(u8 reg) -{ - return read16((void *)(ACPIMMIO_MISC_BASE + reg)); -} - -u32 misc_read32(u8 reg) -{ - return read32((void *)(ACPIMMIO_MISC_BASE + reg)); -} - -void misc_write8(u8 reg, u8 value) -{ - write8((void *)(ACPIMMIO_MISC_BASE + reg), value); -} - -void misc_write16(u8 reg, u16 value) -{ - write16((void *)(ACPIMMIO_MISC_BASE + reg), value); -} - -void misc_write32(u8 reg, u32 value) -{ - write32((void *)(ACPIMMIO_MISC_BASE + reg), value); -} - -/* dpvga read/write - access registers at 0xfed81400 - not currently used */ - -/* gpio bk 0 read/write - access registers at 0xfed81500 - not currently used */ -/* gpio bk 1 read/write - access registers at 0xfed81600 - not currently used */ -/* gpio bk 2 read/write - access registers at 0xfed81700 - not currently used */ - -/* xhci_pm read/write - access registers at 0xfed81c00 */ - -uint8_t xhci_pm_read8(uint8_t reg) -{ - return read8((void *)(ACPIMMIO_XHCIPM_BASE + reg)); -} - -uint16_t xhci_pm_read16(uint8_t reg) -{ - return read16((void *)(ACPIMMIO_XHCIPM_BASE + reg)); -} - -uint32_t xhci_pm_read32(uint8_t reg) -{ - return read32((void *)(ACPIMMIO_XHCIPM_BASE + reg)); -} - -void xhci_pm_write8(uint8_t reg, uint8_t value) -{ - write8((void *)(ACPIMMIO_XHCIPM_BASE + reg), value); -} - -void xhci_pm_write16(uint8_t reg, uint16_t value) -{ - write16((void *)(ACPIMMIO_XHCIPM_BASE + reg), value); -} - -void xhci_pm_write32(uint8_t reg, uint32_t value) -{ - write32((void *)(ACPIMMIO_XHCIPM_BASE + reg), value); -} - -/* acdc_tmr read/write - access registers at 0xfed81d00 */ - -/* aoac read/write - access registers at 0xfed81e00 - not currently used */ - -u8 aoac_read8(u8 reg) -{ - return read8((void *)(ACPIMMIO_AOAC_BASE + reg)); -} - -void aoac_write8(u8 reg, u8 value) -{ - write8((void *)(ACPIMMIO_AOAC_BASE + reg), value); -} - uint16_t pm_acpi_pm_cnt_blk(void) { return pm_read16(PM1_CNT_BLK); diff --git a/src/soc/amd/stoneyridge/smbus.c b/src/soc/amd/stoneyridge/smbus.c index 6285d793b7..df7a86edc7 100644 --- a/src/soc/amd/stoneyridge/smbus.c +++ b/src/soc/amd/stoneyridge/smbus.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include diff --git a/src/soc/amd/stoneyridge/smi.c b/src/soc/amd/stoneyridge/smi.c index 5ddc0dda62..4a0d833c7b 100644 --- a/src/soc/amd/stoneyridge/smi.c +++ b/src/soc/amd/stoneyridge/smi.c @@ -19,6 +19,7 @@ */ #include +#include #include #include diff --git a/src/soc/amd/stoneyridge/smi_util.c b/src/soc/amd/stoneyridge/smi_util.c index 91b86e284e..8759e2acb1 100644 --- a/src/soc/amd/stoneyridge/smi_util.c +++ b/src/soc/amd/stoneyridge/smi_util.c @@ -21,6 +21,7 @@ #include #include #include +#include void configure_smi(uint8_t smi_num, uint8_t mode) { diff --git a/src/soc/amd/stoneyridge/smihandler.c b/src/soc/amd/stoneyridge/smihandler.c index c3f4b675dc..c3aed578ff 100644 --- a/src/soc/amd/stoneyridge/smihandler.c +++ b/src/soc/amd/stoneyridge/smihandler.c @@ -24,6 +24,7 @@ #include #include #include +#include #include /* bits in smm_io_trap */ diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c index b6c40b63d3..bf8787c1fc 100644 --- a/src/soc/amd/stoneyridge/southbridge.c +++ b/src/soc/amd/stoneyridge/southbridge.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include #include @@ -359,16 +360,6 @@ void sb_lpc_decode(void) pci_write_config32(SOC_LPC_DEV, LPC_IO_PORT_DECODE_ENABLE, tmp); } -void sb_acpi_mmio_decode(void) -{ - uint8_t byte; - - /* Enable ACPI MMIO range 0xfed80000 - 0xfed81fff */ - byte = pm_io_read8(PM_ISA_CONTROL); - byte |= MMIO_EN; - pm_io_write8(PM_ISA_CONTROL, byte); -} - static void sb_enable_cf9_io(void) { uint32_t reg = pm_read32(PM_DECODE_EN); @@ -642,7 +633,7 @@ void bootblock_fch_early_init(void) sb_lpc_early_setup(); sb_spibase(); sb_disable_4dw_burst(); /* Must be disabled on CZ(ST) */ - sb_acpi_mmio_decode(); + enable_acpimmio_decode(); fch_smbus_init(); sb_enable_cf9_io(); setup_spread_spectrum(&reboot); diff --git a/src/soc/amd/stoneyridge/usb.c b/src/soc/amd/stoneyridge/usb.c index f2fa3ba267..00f82375e8 100644 --- a/src/soc/amd/stoneyridge/usb.c +++ b/src/soc/amd/stoneyridge/usb.c @@ -22,7 +22,7 @@ #include #include #include - +#include static void set_usb_over_current(struct device *dev) { From f42344a38963cba10604901a6934c7842db42c4d Mon Sep 17 00:00:00 2001 From: Marshall Dawson Date: Thu, 2 May 2019 12:53:00 -0600 Subject: [PATCH 076/331] soc/amd/stoneyridge: Move I2C bus clear out of gpio.c Relocate the I2C bus reset code from gpio.c to i2c.c. When it first went in, gpio.c was a natural location due to the nature of the algorithm. This is preparation for moving most of gpio.c to common code. Change-Id: I3b2d8e1b54e7c5929220d763bd99fe01b0636aaa Signed-off-by: Marshall Dawson Reviewed-on: https://review.coreboot.org/c/coreboot/+/32650 Reviewed-by: Martin Roth Reviewed-by: Richard Spiegel Tested-by: build bot (Jenkins) --- src/soc/amd/stoneyridge/chip.h | 2 +- src/soc/amd/stoneyridge/gpio.c | 97 --------------------- src/soc/amd/stoneyridge/i2c.c | 99 ++++++++++++++++++++++ src/soc/amd/stoneyridge/include/soc/gpio.h | 26 ------ src/soc/amd/stoneyridge/include/soc/i2c.h | 49 +++++++++++ 5 files changed, 149 insertions(+), 124 deletions(-) create mode 100644 src/soc/amd/stoneyridge/include/soc/i2c.h diff --git a/src/soc/amd/stoneyridge/chip.h b/src/soc/amd/stoneyridge/chip.h index 92223d1962..d1a7d30199 100644 --- a/src/soc/amd/stoneyridge/chip.h +++ b/src/soc/amd/stoneyridge/chip.h @@ -20,7 +20,7 @@ #include #include #include -#include +#include #include #define MAX_NODES 1 diff --git a/src/soc/amd/stoneyridge/gpio.c b/src/soc/amd/stoneyridge/gpio.c index 01ced0880b..7c9680582c 100644 --- a/src/soc/amd/stoneyridge/gpio.c +++ b/src/soc/amd/stoneyridge/gpio.c @@ -18,11 +18,9 @@ #include #include #include -#include #include #include #include -#include #include #include "chip.h" @@ -326,101 +324,6 @@ void sb_program_gpios(const struct soc_amd_gpio *gpio_list_ptr, size_t size) edge_level, mask); } -/* - * I2C pins are open drain with external pull up, so in order to bit bang them - * all, SCL pins must become GPIO inputs with no pull, then they need to be - * toggled between input-no-pull and output-low. This table is for the initial - * conversion of all SCL pins to input with no pull. - */ -static const struct soc_amd_gpio i2c_2_gpi[] = { - PAD_GPI(I2C0_SCL_PIN, PULL_NONE), - PAD_GPI(I2C1_SCL_PIN, PULL_NONE), - PAD_GPI(I2C2_SCL_PIN, PULL_NONE), - PAD_GPI(I2C3_SCL_PIN, PULL_NONE), -}; -#define saved_pins_count ARRAY_SIZE(i2c_2_gpi) - -/* - * To program I2C pins without destroying their programming, the registers - * that will be changed need to be saved first. - */ -static void save_i2c_pin_registers(uint8_t gpio, - struct soc_amd_i2c_save *save_table) -{ - uint32_t *gpio_ptr; - - gpio_ptr = (uint32_t *)gpio_get_address(gpio); - save_table->mux_value = iomux_read8(gpio); - save_table->control_value = read32(gpio_ptr); -} - -static void restore_i2c_pin_registers(uint8_t gpio, - struct soc_amd_i2c_save *save_table) -{ - uint32_t *gpio_ptr; - - gpio_ptr = (uint32_t *)gpio_get_address(gpio); - iomux_write8(gpio, save_table->mux_value); - iomux_read8(gpio); - write32(gpio_ptr, save_table->control_value); - read32(gpio_ptr); -} - -/* Slaves to be reset are controlled by devicetree register i2c_scl_reset */ -void sb_reset_i2c_slaves(void) -{ - const struct soc_amd_stoneyridge_config *cfg; - const struct device *dev = pcidev_path_on_root(GNB_DEVFN); - struct soc_amd_i2c_save save_table[saved_pins_count]; - uint8_t i, j, control; - - if (!dev || !dev->chip_info) - return; - cfg = dev->chip_info; - control = cfg->i2c_scl_reset & GPIO_I2C_MASK; - if (control == 0) - return; - - /* Save and reprogram I2C SCL pins */ - for (i = 0; i < saved_pins_count; i++) - save_i2c_pin_registers(i2c_2_gpi[i].gpio, &save_table[i]); - sb_program_gpios(i2c_2_gpi, saved_pins_count); - - /* - * Toggle SCL back and forth 9 times under 100KHz. A single read is - * needed after the writes to force the posted write to complete. - */ - for (j = 0; j < 9; j++) { - if (control & GPIO_I2C0_SCL) - write32((uint32_t *)GPIO_I2C0_ADDRESS, GPIO_SCL_LOW); - if (control & GPIO_I2C1_SCL) - write32((uint32_t *)GPIO_I2C1_ADDRESS, GPIO_SCL_LOW); - if (control & GPIO_I2C2_SCL) - write32((uint32_t *)GPIO_I2C2_ADDRESS, GPIO_SCL_LOW); - if (control & GPIO_I2C3_SCL) - write32((uint32_t *)GPIO_I2C3_ADDRESS, GPIO_SCL_LOW); - - read32((uint32_t *)GPIO_I2C3_ADDRESS); /* Flush posted write */ - udelay(4); /* 4usec gets 85KHz for 1 pin, 70KHz for 4 pins */ - - if (control & GPIO_I2C0_SCL) - write32((uint32_t *)GPIO_I2C0_ADDRESS, GPIO_SCL_HIGH); - if (control & GPIO_I2C1_SCL) - write32((uint32_t *)GPIO_I2C1_ADDRESS, GPIO_SCL_HIGH); - if (control & GPIO_I2C2_SCL) - write32((uint32_t *)GPIO_I2C2_ADDRESS, GPIO_SCL_HIGH); - if (control & GPIO_I2C3_SCL) - write32((uint32_t *)GPIO_I2C3_ADDRESS, GPIO_SCL_HIGH); - - read32((uint32_t *)GPIO_I2C3_ADDRESS); /* Flush posted write */ - udelay(4); - } - - /* Restore I2C pins. */ - for (i = 0; i < saved_pins_count; i++) - restore_i2c_pin_registers(i2c_2_gpi[i].gpio, &save_table[i]); -} - int gpio_interrupt_status(gpio_t gpio) { uintptr_t gpio_address = gpio_get_address(gpio); diff --git a/src/soc/amd/stoneyridge/i2c.c b/src/soc/amd/stoneyridge/i2c.c index e99f3509ff..c3e5539e19 100644 --- a/src/soc/amd/stoneyridge/i2c.c +++ b/src/soc/amd/stoneyridge/i2c.c @@ -13,12 +13,16 @@ * GNU General Public License for more details. */ +#include #include #include +#include #include +#include #include #include #include +#include #include "chip.h" #define I2C_BUS_ADDRESS(x) (I2C_BASE_ADDRESS + I2C_DEVICE_SIZE * (x)) @@ -140,3 +144,98 @@ struct device_operations stoneyridge_i2c_mmio_ops = { .acpi_name = i2c_acpi_name, .acpi_fill_ssdt_generator = dw_i2c_acpi_fill_ssdt, }; + +/* + * I2C pins are open drain with external pull up, so in order to bit bang them + * all, SCL pins must become GPIO inputs with no pull, then they need to be + * toggled between input-no-pull and output-low. This table is for the initial + * conversion of all SCL pins to input with no pull. + */ +static const struct soc_amd_gpio i2c_2_gpi[] = { + PAD_GPI(I2C0_SCL_PIN, PULL_NONE), + PAD_GPI(I2C1_SCL_PIN, PULL_NONE), + PAD_GPI(I2C2_SCL_PIN, PULL_NONE), + PAD_GPI(I2C3_SCL_PIN, PULL_NONE), +}; +#define saved_pins_count ARRAY_SIZE(i2c_2_gpi) + +/* + * To program I2C pins without destroying their programming, the registers + * that will be changed need to be saved first. + */ +static void save_i2c_pin_registers(uint8_t gpio, + struct soc_amd_i2c_save *save_table) +{ + uint32_t *gpio_ptr; + + gpio_ptr = (uint32_t *)gpio_get_address(gpio); + save_table->mux_value = iomux_read8(gpio); + save_table->control_value = read32(gpio_ptr); +} + +static void restore_i2c_pin_registers(uint8_t gpio, + struct soc_amd_i2c_save *save_table) +{ + uint32_t *gpio_ptr; + + gpio_ptr = (uint32_t *)gpio_get_address(gpio); + iomux_write8(gpio, save_table->mux_value); + iomux_read8(gpio); + write32(gpio_ptr, save_table->control_value); + read32(gpio_ptr); +} + +/* Slaves to be reset are controlled by devicetree register i2c_scl_reset */ +void sb_reset_i2c_slaves(void) +{ + const struct soc_amd_stoneyridge_config *cfg; + const struct device *dev = pcidev_path_on_root(GNB_DEVFN); + struct soc_amd_i2c_save save_table[saved_pins_count]; + uint8_t i, j, control; + + if (!dev || !dev->chip_info) + return; + cfg = dev->chip_info; + control = cfg->i2c_scl_reset & GPIO_I2C_MASK; + if (control == 0) + return; + + /* Save and reprogram I2C SCL pins */ + for (i = 0; i < saved_pins_count; i++) + save_i2c_pin_registers(i2c_2_gpi[i].gpio, &save_table[i]); + sb_program_gpios(i2c_2_gpi, saved_pins_count); + + /* + * Toggle SCL back and forth 9 times under 100KHz. A single read is + * needed after the writes to force the posted write to complete. + */ + for (j = 0; j < 9; j++) { + if (control & GPIO_I2C0_SCL) + write32((uint32_t *)GPIO_I2C0_ADDRESS, GPIO_SCL_LOW); + if (control & GPIO_I2C1_SCL) + write32((uint32_t *)GPIO_I2C1_ADDRESS, GPIO_SCL_LOW); + if (control & GPIO_I2C2_SCL) + write32((uint32_t *)GPIO_I2C2_ADDRESS, GPIO_SCL_LOW); + if (control & GPIO_I2C3_SCL) + write32((uint32_t *)GPIO_I2C3_ADDRESS, GPIO_SCL_LOW); + + read32((uint32_t *)GPIO_I2C3_ADDRESS); /* Flush posted write */ + udelay(4); /* 4usec gets 85KHz for 1 pin, 70KHz for 4 pins */ + + if (control & GPIO_I2C0_SCL) + write32((uint32_t *)GPIO_I2C0_ADDRESS, GPIO_SCL_HIGH); + if (control & GPIO_I2C1_SCL) + write32((uint32_t *)GPIO_I2C1_ADDRESS, GPIO_SCL_HIGH); + if (control & GPIO_I2C2_SCL) + write32((uint32_t *)GPIO_I2C2_ADDRESS, GPIO_SCL_HIGH); + if (control & GPIO_I2C3_SCL) + write32((uint32_t *)GPIO_I2C3_ADDRESS, GPIO_SCL_HIGH); + + read32((uint32_t *)GPIO_I2C3_ADDRESS); /* Flush posted write */ + udelay(4); + } + + /* Restore I2C pins. */ + for (i = 0; i < saved_pins_count; i++) + restore_i2c_pin_registers(i2c_2_gpi[i].gpio, &save_table[i]); +} diff --git a/src/soc/amd/stoneyridge/include/soc/gpio.h b/src/soc/amd/stoneyridge/include/soc/gpio.h index fe8240fb11..26d0336d0a 100644 --- a/src/soc/amd/stoneyridge/include/soc/gpio.h +++ b/src/soc/amd/stoneyridge/include/soc/gpio.h @@ -36,21 +36,10 @@ struct soc_amd_event { uint8_t event; }; -struct soc_amd_i2c_save { - uint32_t control_value; - uint8_t mux_value; -}; - #define GPIO_MASTER_SWITCH 0xFC #define GPIO_MASK_STS_EN BIT(28) #define GPIO_INTERRUPT_EN BIT(30) -#define GPIO_I2C0_SCL BIT(0) -#define GPIO_I2C1_SCL BIT(1) -#define GPIO_I2C2_SCL BIT(2) -#define GPIO_I2C3_SCL BIT(3) -#define GPIO_I2C_MASK (BIT(0) | BIT(1) | BIT(2) | BIT(3)) - #define GPIO_TOTAL_PINS 149 #define GPIO_PIN_IN (1 << 0) /* for byte access */ #define GPIO_PIN_OUT (1 << 6) /* for byte access */ @@ -186,15 +175,6 @@ struct soc_amd_i2c_save { #define GPIO_147 147 #define GPIO_148 148 -#define I2C0_SCL_PIN GPIO_145 -#define I2C1_SCL_PIN GPIO_147 -#define I2C2_SCL_PIN GPIO_113 -#define I2C3_SCL_PIN GPIO_19 - -#define GPIO_I2C0_ADDRESS GPIO_BANK2_CONTROL(I2C0_SCL_PIN) -#define GPIO_I2C1_ADDRESS GPIO_BANK2_CONTROL(I2C1_SCL_PIN) -#define GPIO_I2C2_ADDRESS GPIO_BANK1_CONTROL(I2C2_SCL_PIN) -#define GPIO_I2C3_ADDRESS GPIO_BANK0_CONTROL(I2C3_SCL_PIN) #define GPIO_SCL_HIGH 0 #define GPIO_SCL_LOW GPIO_OUTPUT_ENABLE @@ -373,11 +353,6 @@ struct soc_amd_i2c_save { #define GPIO_148_IOMUX_I2C1_SDA 0 #define GPIO_148_IOMUX_GPIOxx 1 -#define I2C0_SCL_PIN_IOMUX_GPIOxx GPIO_145_IOMUX_GPIOxx -#define I2C1_SCL_PIN_IOMUX_GPIOxx GPIO_147_IOMUX_GPIOxx -#define I2C2_SCL_PIN_IOMUX_GPIOxx GPIO_113_IOMUX_GPIOxx -#define I2C3_SCL_PIN_IOMUX_GPIOxx GPIO_19_IOMUX_GPIOxx - enum { GEVENT_0, GEVENT_1, @@ -599,7 +574,6 @@ uintptr_t gpio_get_address(gpio_t gpio_num); * @return none */ void sb_program_gpios(const struct soc_amd_gpio *gpio_list_ptr, size_t size); -void sb_reset_i2c_slaves(void); /* Return the interrupt status and clear if set. */ int gpio_interrupt_status(gpio_t gpio); diff --git a/src/soc/amd/stoneyridge/include/soc/i2c.h b/src/soc/amd/stoneyridge/include/soc/i2c.h new file mode 100644 index 0000000000..62575d0fb8 --- /dev/null +++ b/src/soc/amd/stoneyridge/include/soc/i2c.h @@ -0,0 +1,49 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __STONEYRIDGE_I2C_H__ +#define __STONEYRIDGE_I2C_H__ + +#include + +struct soc_amd_i2c_save { + uint32_t control_value; + uint8_t mux_value; +}; + +#define GPIO_I2C0_SCL BIT(0) +#define GPIO_I2C1_SCL BIT(1) +#define GPIO_I2C2_SCL BIT(2) +#define GPIO_I2C3_SCL BIT(3) +#define GPIO_I2C_MASK (BIT(0) | BIT(1) | BIT(2) | BIT(3)) + +#define I2C0_SCL_PIN GPIO_145 +#define I2C1_SCL_PIN GPIO_147 +#define I2C2_SCL_PIN GPIO_113 +#define I2C3_SCL_PIN GPIO_19 + +#define GPIO_I2C0_ADDRESS GPIO_BANK2_CONTROL(I2C0_SCL_PIN) +#define GPIO_I2C1_ADDRESS GPIO_BANK2_CONTROL(I2C1_SCL_PIN) +#define GPIO_I2C2_ADDRESS GPIO_BANK1_CONTROL(I2C2_SCL_PIN) +#define GPIO_I2C3_ADDRESS GPIO_BANK0_CONTROL(I2C3_SCL_PIN) + +#define I2C0_SCL_PIN_IOMUX_GPIOxx GPIO_145_IOMUX_GPIOxx +#define I2C1_SCL_PIN_IOMUX_GPIOxx GPIO_147_IOMUX_GPIOxx +#define I2C2_SCL_PIN_IOMUX_GPIOxx GPIO_113_IOMUX_GPIOxx +#define I2C3_SCL_PIN_IOMUX_GPIOxx GPIO_19_IOMUX_GPIOxx + +void sb_reset_i2c_slaves(void); + +#endif /* __STONEYRIDGE_I2C_H__ */ From ce2c1cb742b17623978f3d9a9e414552189bc819 Mon Sep 17 00:00:00 2001 From: Jett Rink Date: Wed, 15 May 2019 13:40:05 -0600 Subject: [PATCH 077/331] mb/google/sarien: leave gpio pads unlocks during fsp The FSP will lock down the configuration of GPP_A12, which makes the configuration of the GPIO pin on warm reset not work correctly. This is only needed for the Arcada variant since it is the only variant that uses ISH. BRANCH=sarien BUG=b:132719369 TEST=ISH_GP6 now works on warm resets on arcarda Change-Id: Icb3bae2c48eee053189f1a878f5975c6afe51c71 Signed-off-by: Jett Rink Reviewed-on: https://review.coreboot.org/c/coreboot/+/32831 Reviewed-by: Furquan Shaikh Reviewed-by: Duncan Laurie Tested-by: build bot (Jenkins) --- src/mainboard/google/sarien/variants/arcada/devicetree.cb | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb index 27c61f3563..b6377ba55d 100644 --- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb +++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb @@ -26,6 +26,7 @@ chip soc/intel/cannonlake register "PchPmSlpS4MinAssert" = "4" # 4s register "PchPmSlpSusMinAssert" = "4" # 4s register "PchPmSlpAMinAssert" = "4" # 2s + register "PchUnlockGpioPads" = "1" register "speed_shift_enable" = "1" register "psys_pmax" = "140" From 2e8188aa13b84f607fd3a1e95fb7b63b26ff1d89 Mon Sep 17 00:00:00 2001 From: Jacob Garber Date: Wed, 15 May 2019 09:57:49 -0600 Subject: [PATCH 078/331] Documentation/lessons: Tidy up lesson 2 - The link to create an account is now "Sign in" and not "Register" - Use monospace formatting for terminal commands and file names - Properly escape less-than and greater-than - Correct the 'make lint' example command - Reformat example commit messages - Add formatting for website links - Other whitespace fixes Signed-off-by: Jacob Garber Change-Id: I9931bef8c30387d1c08b59973d6de9b5c0419814 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32804 Tested-by: build bot (Jenkins) Reviewed-by: HAOUAS Elyes Reviewed-by: Lijian Zhao Reviewed-by: Patrick Rudolph Reviewed-by: Stefan Reinauer --- Documentation/lessons/lesson2.md | 96 +++++++++++++++++--------------- 1 file changed, 52 insertions(+), 44 deletions(-) diff --git a/Documentation/lessons/lesson2.md b/Documentation/lessons/lesson2.md index 626e76e74a..ae70c70cbc 100644 --- a/Documentation/lessons/lesson2.md +++ b/Documentation/lessons/lesson2.md @@ -5,10 +5,10 @@ If you already have an account, skip to Part 2. Otherwise, go to in your preferred web browser. -Select **Register** in the upper right corner. +Select **Sign in** in the upper right corner. Select the appropriate sign-in. For example, if you have a Google account, -select **Google OAuth2** (gerrit-oauth-provider plugin)".**Note:** Your +select **Google OAuth2** (gerrit-oauth-provider plugin). **Note:** Your username for the account will be the username of the account you used to sign-in with. (ex. your Google username). @@ -17,7 +17,7 @@ sign-in with. (ex. your Google username). If you prefer to use an HTTP password instead, skip to Part 2b. For the most up-to-date instructions on how to set up SSH keys with Gerrit go to - + and follow the instructions there. Then, skip to Part 3. Additionally, that section of the Web site provides explanation on starting @@ -35,13 +35,13 @@ doing so could overwrite an existing key. In the upper right corner, select your name and click on **Settings**. Select **SSH Public Keys** on the left-hand side. -In a terminal, run "ssh-keygen" and confirm the default path ".ssh/id_rsa". +In a terminal, run `ssh-keygen` and confirm the default path `.ssh/id_rsa`. Make a passphrase -- remember this phrase. It will be needed whenever you use this RSA Public Key. **Note:** You might want to use a short password, or forego the password altogether as you will be using it very often. -Open "id_rsa.pub", copy all contents and paste into the textbox under +Open `id_rsa.pub`, copy all contents and paste into the textbox under "Add SSH Public Key" in the https://review.coreboot.org webpage. ## Part 2b: Setting up an HTTP Password @@ -51,7 +51,7 @@ after you select your name and click on **Settings** on the left-hand side, rath than selecting **SSH Public Keys**, select **HTTP Password**. Click **Generate Password**. This should fill the "Password" box with a password. Copy -the password, and add the following to your $HOME/.netrc file: +the password, and add the following to your `$HOME/.netrc` file: machine review.coreboot.org login YourUserNameHere password YourPasswordHere @@ -61,7 +61,7 @@ just generated. ## Part 3: Clone coreboot and configure it for submitting patches On Gerrit, click on the **Browse** tab in the upper left corner and select -**Repositories**. From the listing, select the "coreboot" repo. You may have +**Repositories**. From the listing, select the "coreboot" repo. You may have to click the next page arrow at the bottom a few times to find it. If you are using SSH keys, select **ssh** from the tabs under "Project @@ -73,7 +73,7 @@ set. Click the profile picture at the top right and select **User Settings**, then set your username in the **Profile** section. If you are using HTTP, instead, select **http** from the tabs under "Project coreboot" -and run the command that appears +and run the command that appears. Now is a good time to configure your global git identity, if you haven't already. @@ -91,13 +91,13 @@ and other configurations. An easy first commit to make is fixing existing checkpatch errors and warnings in the source files. To see errors that are already present, build the files in -the repository by running 'make lint' in the coreboot directory. Alternatively, -if you want to run 'make lint' on a specific directory, run: +the repository by running `make lint` in the coreboot directory. Alternatively, +if you want to run `make lint` on a specific directory, run: - for file in $(git ls-files | grep src/amd/quadcore); do \ + for file in $(git ls-files | grep ); do \ util/lint/checkpatch.pl --file $file --terse; done -where is the filepath of the directory (ex. src/cpu/amd/car). +where `filepath` is the filepath of the directory (ex. `src/cpu/amd/car`). Any changes made to files under the src directory are made locally, and can be submitted for review. @@ -120,7 +120,7 @@ To commit the change, run git commit -s **Note:** The -s adds a signed-off-by line by the committer. Your commit should be -signed off with your name and email (i.e. **Your Name** ****, based on +signed off with your name and email (i.e. **Your Name** **\**, based on what you set with git config earlier). Running git commit first checks for any errors and warnings using lint. If @@ -134,65 +134,73 @@ The first line of your commit message is your commit summary. This is a brief one-line description of what you changed in the files using the template below: -`: Short description` -*ex. cpu/amd/pi/00630F01: Fix checkpatch warnings and errors* + : Short description + +For example, + + cpu/amd/pi/00630F01: Fix checkpatch warnings and errors **Note:** It is good practice to use present tense in your descriptions and do not punctuate your summary. Then hit Enter. The next paragraph should be a more in-depth explanation of the changes you've made to the files. Again, it is good practice to use present -tense. -*ex. Fix space prohibited between function name and open parenthesis, -line over 80 characters, unnecessary braces for single statement blocks, -space required before open brace errors and warnings.* +tense. Ex. + + Fix space prohibited between function name and open parenthesis, + line over 80 characters, unnecessary braces for single statement blocks, + space required before open brace errors and warnings. When you have finished writing your commit message, save and exit the text editor. You have finished committing your change. If, after submitting your -commit, you wish to make changes to it, running "git commit --amend" allows +commit, you wish to make changes to it, running `git commit --amend` allows you to take back your commit and amend it. -When you are done with your commit, run 'git push' to push your commit to +When you are done with your commit, run `git push` to push your commit to coreboot.org. **Note:** To submit as a draft, use -'git push origin HEAD:refs/drafts/master' Submitting as a draft means that +`git push origin HEAD:refs/drafts/master`. Submitting as a draft means that your commit will be on coreboot.org, but is only visible to those you add as reviewers. This has been a quick primer on how to submit a change to Gerrit for review -using git. You may wish to review the [Gerrit code review workflow +using git. You may wish to review the [Gerrit code review workflow documentation](https://gerrit-review.googlesource.com/Documentation/intro-user.html#code-review), especially if you plan to work on multiple changes at the same time. ## Part 4b: Using git cola to stage and submit a commit If git cola is not installed on your machine, see -https://git-cola.github.io/downloads.html for download instructions. + for download instructions. -After making some edits to src files, rather than run "git add," run -'git cola' from the command line. You should see all of the files +After making some edits to src files, rather than run `git add`, run +`git cola` from the command line. You should see all of the files edited under "Modified". In the textbox labeled "Commit summary" provide a brief one-line description of what you changed in the files according to the template below: -`: Short description` -*ex. cpu/amd/pi/00630F01: Fix checkpatch warnings and errors* + : Short description + +For example, + + cpu/amd/pi/00630F01: Fix checkpatch warnings and errors **Note:** It is good practice to use present tense in your descriptions and do not punctuate your short description. In the larger text box labeled 'Extended description...' provide a more in-depth explanation of the changes you've made to the files. Again, it -is good practice to use present tense. -*ex. Fix space prohibited between function name and open parenthesis, -line over 80 characters, unnecessary braces for single statement blocks, -space required before open brace errors and warnings.* +is good practice to use present tense. Ex. + + Fix space prohibited between function name and open parenthesis, + line over 80 characters, unnecessary braces for single statement blocks, + space required before open brace errors and warnings. Then press Enter two times to move the cursor to below your description. To the left of the text boxes, there is an icon with an downward arrow. Press the arrow and select "Sign Off." Make sure that you are signing off -with your name and email (i.e. **Your Name** ****, based on what +with your name and email (i.e. **Your Name** **\**, based on what you set with git config earlier). Now, review each of your changes and mark either individual changes or @@ -218,30 +226,30 @@ Note: Be sure to add any other changes that haven't already been explained in the extended description. When ready, select 'Commit' again. Once all errors have been satisfied -and the commit succeeds, move to the command line and run 'git push'. -**Note:** To submit as a draft, use 'git push origin HEAD:refs/drafts/master' +and the commit succeeds, move to the command line and run `git push`. +**Note:** To submit as a draft, use `git push origin HEAD:refs/drafts/master`. Submitting as a draft means that your commit will be on coreboot.org, but is only visible to those you add as reviewers. ## Part 5: Getting your commit reviewed -Your commits can now be seen on review.coreboot.org if you select “Your” -and click on “Changes” and can be reviewed by others. Your code will +Your commits can now be seen on review.coreboot.org if you select "Your" +and click on "Changes" and can be reviewed by others. Your code will first be reviewed by build bot (Jenkins), which will either give you a warning or verify a successful build; if so, your commit will receive a +1. Other -users may also give your commit +1. For a commit to be merged, it needs -to receive a +2.**Note:** A +1 and a +1 does not make a +2. Only certain users +users may also give your commit +1. For a commit to be merged, it needs +to receive a +2. **Note:** A +1 and a +1 does not make a +2. Only certain users can give a +2. ## Part 6 (optional): bash-git-prompt To help make it easier to understand the state of the git repository -without running 'git status' or 'git log', there is a way to make the +without running `git status` or `git log`, there is a way to make the command line show the status of the repository at every point. This is through bash-git-prompt. Instructions for installing this are found at: -https://github.com/magicmonty/bash-git-prompt +. **Note:** Feel free to search for different versions of git prompt, as this one is specific to bash. @@ -254,7 +262,7 @@ Run the following two commands in the command line: **Note:** cd will change your directory to your home directory, so the git clone command will be run there. -Finally, open the ~/.bashrc file and append the following two lines: +Finally, open the `~/.bashrc` file and append the following two lines: GIT_PROMPT_ONLY_IN_REPO=1 source ~/.bash-git-prompt/gitprompt.sh @@ -264,7 +272,7 @@ its state. There also are additional configurations that you can change depending on your preferences. If you wish to do so, look at the "All configs for .bashrc" section -on https://github.com/magicmonty/bash-git-prompt. Listed in that section are +on . Listed in that section are various lines that you can copy, uncomment and add to your .bashrc file to change the configurations. Example configurations include avoid fetching remote status, and supporting versions of Git older than 1.7.10. @@ -277,7 +285,7 @@ Suppose you would like to update a commit that has already been pushed to the remote repository. If the commit you wish to update is the most recent commit you have made, after making your desired changes, stage the files (either using git add or in git cola), and amend the commit. To do so, -if you are using the command line, run "git commit --amend." If you are +if you are using the command line, run `git commit --amend`. If you are using git cola, click on the gear icon located on the upper left side under **Commit** and select **Amend Last Commit** in the drop down menu. Then, stage the files you have changed, commit the changes, and run git push to push the From bc674765a93bc5c9bf2c20ce2444389dccc754e1 Mon Sep 17 00:00:00 2001 From: Jacob Garber Date: Tue, 14 May 2019 11:21:41 -0600 Subject: [PATCH 079/331] {arch,cpu}/x86, drivers/intel: Restore cpu_index error handling Previously cpu_index() always succeeded, but since commit 095c931 (src/arch/x86: Use core apic id to get cpu_index()) it is now possible for it to indicate an error by returning -1. This commit adds error handling for all calls to cpu_index(), and restores several checks that were removed in commit 7c712bb (Fix code that would trip -Wtype-limits) but are now needed. Signed-off-by: Jacob Garber Change-Id: I5436eed4cb5675f916924eb9670db04592a8b927 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32795 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- src/arch/x86/cpu.c | 2 +- src/arch/x86/exception.c | 2 +- src/arch/x86/include/arch/cpu.h | 2 +- src/cpu/x86/mp_init.c | 15 ++++++++++++++- src/cpu/x86/pae/pgtbl.c | 4 ++-- src/drivers/intel/fsp2_0/ppi/mp_service_ppi.c | 9 +++++++++ 6 files changed, 28 insertions(+), 6 deletions(-) diff --git a/src/arch/x86/cpu.c b/src/arch/x86/cpu.c index fb4c7b6cfe..e6c9435503 100644 --- a/src/arch/x86/cpu.c +++ b/src/arch/x86/cpu.c @@ -350,7 +350,7 @@ void arch_bootstate_coreboot_exit(void) * Hence new logic to use cpuid to fetch lapic id and matches with * cpus_default_apic_id[] variable to return correct cpu_index(). */ -unsigned long cpu_index(void) +int cpu_index(void) { int i; int lapic_id = initial_lapicid(); diff --git a/src/arch/x86/exception.c b/src/arch/x86/exception.c index b00777a455..b88f4a7553 100644 --- a/src/arch/x86/exception.c +++ b/src/arch/x86/exception.c @@ -502,7 +502,7 @@ void x86_exception(struct eregs *info) } #else /* !CONFIG_GDB_STUB */ #define MDUMP_SIZE 0x80 - unsigned int logical_processor = 0; + int logical_processor = 0; #if ENV_RAMSTAGE logical_processor = cpu_index(); diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h index 481ee9d8e0..078ea1748b 100644 --- a/src/arch/x86/include/arch/cpu.h +++ b/src/arch/x86/include/arch/cpu.h @@ -379,6 +379,6 @@ uint32_t cpu_get_feature_flags_edx(void); * Hence new logic to use cpuid to fetch lapic id and matches with * cpus_default_apic_id[] variable to return correct cpu_index(). */ -unsigned long cpu_index(void); +int cpu_index(void); #endif /* ARCH_CPU_H */ diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c index 8957515540..b7b8fe2afa 100644 --- a/src/cpu/x86/mp_init.c +++ b/src/cpu/x86/mp_init.c @@ -870,13 +870,20 @@ static int run_ap_work(struct mp_callback *val, long expire_us) int i; int cpus_accepted; struct stopwatch sw; - int cur_cpu = cpu_index(); + int cur_cpu; if (!CONFIG(PARALLEL_MP_AP_WORK)) { printk(BIOS_ERR, "APs already parked. PARALLEL_MP_AP_WORK not selected.\n"); return -1; } + cur_cpu = cpu_index(); + + if (cur_cpu < 0) { + printk(BIOS_ERR, "Invalid CPU index.\n"); + return -1; + } + /* Signal to all the APs to run the func. */ for (i = 0; i < ARRAY_SIZE(ap_callbacks); i++) { if (cur_cpu == i) @@ -918,6 +925,12 @@ static void ap_wait_for_instruction(void) return; cur_cpu = cpu_index(); + + if (cur_cpu < 0) { + printk(BIOS_ERR, "Invalid CPU index.\n"); + return; + } + per_cpu_slot = &ap_callbacks[cur_cpu]; while (1) { diff --git a/src/cpu/x86/pae/pgtbl.c b/src/cpu/x86/pae/pgtbl.c index 062ee402f1..9c921342f1 100644 --- a/src/cpu/x86/pae/pgtbl.c +++ b/src/cpu/x86/pae/pgtbl.c @@ -116,12 +116,12 @@ void *map_2M_page(unsigned long page) static struct pg_table pgtbl[CONFIG_MAX_CPUS] __attribute__((aligned(4096))); static unsigned long mapped_window[CONFIG_MAX_CPUS]; - unsigned long index; + int index; unsigned long window; void *result; int i; index = cpu_index(); - if (index >= CONFIG_MAX_CPUS) + if (index < 0) return MAPPING_ERROR; window = page >> 10; if (window != mapped_window[index]) { diff --git a/src/drivers/intel/fsp2_0/ppi/mp_service_ppi.c b/src/drivers/intel/fsp2_0/ppi/mp_service_ppi.c index cdc98e06de..e26701b099 100644 --- a/src/drivers/intel/fsp2_0/ppi/mp_service_ppi.c +++ b/src/drivers/intel/fsp2_0/ppi/mp_service_ppi.c @@ -45,6 +45,9 @@ static efi_return_status_t mp_get_processor_info(const efi_uintn_t processor_number, efi_processor_information *processor_info_buffer) { + if (cpu_index() < 0) + return FSP_DEVICE_ERROR; + if (processor_info_buffer == NULL) return FSP_INVALID_PARAMETER; @@ -68,6 +71,9 @@ static efi_return_status_t mp_startup_all_aps(const efi_ap_procedure procedure, efi_boolean_t ignored3, efi_uintn_t timeout_usec, void *argument) { + if (cpu_index() < 0) + return FSP_DEVICE_ERROR; + if (procedure == NULL) return FSP_INVALID_PARAMETER; @@ -85,6 +91,9 @@ static efi_return_status_t mp_startup_this_ap(const efi_ap_procedure procedure, efi_uintn_t processor_number, efi_uintn_t timeout_usec, void *argument) { + if (cpu_index() < 0) + return FSP_DEVICE_ERROR; + if (processor_number > get_cpu_count()) return FSP_NOT_FOUND; From d8cd2e9c37377eae5cf42e1778aeb7682d2256ac Mon Sep 17 00:00:00 2001 From: Patrick Georgi Date: Thu, 4 Apr 2019 18:07:52 +0200 Subject: [PATCH 080/331] libpayload: make log2 and clz work on signed values internally Needed to make libpayload build clean with -Wconversion. BUG=b:111443775 BRANCH=none TEST=make junit.xml shows fewer warnings with -Wconversion enabled Change-Id: Ie193e39854d2231b6d09a2b0deeeef2873e900ab Signed-off-by: Patrick Georgi Reviewed-on: https://review.coreboot.org/c/coreboot/+/32184 Tested-by: build bot (Jenkins) Reviewed-by: Jacob Garber Reviewed-by: Stefan Reinauer --- payloads/libpayload/include/libpayload.h | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/payloads/libpayload/include/libpayload.h b/payloads/libpayload/include/libpayload.h index a578d41f28..57a3afc6b1 100644 --- a/payloads/libpayload/include/libpayload.h +++ b/payloads/libpayload/include/libpayload.h @@ -434,9 +434,12 @@ void hexdump(const void *memory, size_t length); void fatal(const char *msg) __attribute__((noreturn)); /* Count Leading Zeroes: clz(0) == 32, clz(0xf) == 28, clz(1 << 31) == 0 */ -static inline int clz(u32 x) { return x ? __builtin_clz(x) : sizeof(x) * 8; } +static inline int clz(u32 x) +{ + return x ? __builtin_clz(x) : (int)sizeof(x) * 8; +} /* Integer binary logarithm (rounding down): log2(0) == -1, log2(5) == 2 */ -static inline int log2(u32 x) { return sizeof(x) * 8 - clz(x) - 1; } +static inline int log2(u32 x) { return (int)sizeof(x) * 8 - clz(x) - 1; } /* Find First Set: __ffs(0xf) == 0, __ffs(0) == -1, __ffs(1 << 31) == 31 */ static inline int __ffs(u32 x) { return log2(x & (u32)(-(s32)x)); } /** @} */ From f295d8f113142d72b55cc9a14d33a6de4e6a4dbc Mon Sep 17 00:00:00 2001 From: Patrick Georgi Date: Wed, 15 May 2019 21:33:05 +0200 Subject: [PATCH 081/331] mb/ocp/monolake: replace IS_ENABLED(CONFIG_*) with CONFIG() That's how we do it these days. Change-Id: I6bf6460440d0f2e6973734ba8894a4be981d03c5 Signed-off-by: Patrick Georgi Reviewed-on: https://review.coreboot.org/c/coreboot/+/32812 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner --- src/mainboard/ocp/monolake/mainboard.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mainboard/ocp/monolake/mainboard.c b/src/mainboard/ocp/monolake/mainboard.c index d457859d44..bbfeeafb3b 100644 --- a/src/mainboard/ocp/monolake/mainboard.c +++ b/src/mainboard/ocp/monolake/mainboard.c @@ -23,7 +23,7 @@ #define BMC_KCS_BASE 0xca2 #define INTERFACE_IS_IO 0x1 -#if IS_ENABLED(CONFIG_GENERATE_SMBIOS_TABLES) +#if CONFIG(GENERATE_SMBIOS_TABLES) static int mainboard_smbios_data(struct device *dev, int *handle, unsigned long *current) { @@ -50,7 +50,7 @@ static int mainboard_smbios_data(struct device *dev, int *handle, */ static void mainboard_enable(struct device *dev) { -#if IS_ENABLED(CONFIG_GENERATE_SMBIOS_TABLES) +#if CONFIG(GENERATE_SMBIOS_TABLES) dev->ops->get_smbios_data = mainboard_smbios_data; #endif From d9391837198d838d55ecf853ca70a675f9ca36aa Mon Sep 17 00:00:00 2001 From: Patrick Georgi Date: Wed, 15 May 2019 21:33:42 +0200 Subject: [PATCH 082/331] soc/qualcomm/common: replace IS_ENABLED(CONFIG_*) with CONFIG() That's how we do it these days. Change-Id: I1c088d23dff709bcdcb21310059e6a2aab84c0be Signed-off-by: Patrick Georgi Reviewed-on: https://review.coreboot.org/c/coreboot/+/32813 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner --- src/soc/qualcomm/common/qclib.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/soc/qualcomm/common/qclib.c b/src/soc/qualcomm/common/qclib.c index 1fd79b57b5..73c525001e 100644 --- a/src/soc/qualcomm/common/qclib.c +++ b/src/soc/qualcomm/common/qclib.c @@ -129,7 +129,7 @@ void qclib_load_and_run(void) memset(ddr_region, 0, sizeof(struct region)); /* output area, QCLib copies console log buffer out */ - if (IS_ENABLED(CONFIG_CONSOLE_CBMEM)) + if (CONFIG(CONSOLE_CBMEM)) qclib_add_if_table_entry(QCLIB_TE_QCLIB_LOG_BUFFER, _qclib_serial_log, REGION_SIZE(qclib_serial_log), 0); @@ -152,11 +152,11 @@ void qclib_load_and_run(void) } /* Enable QCLib serial output, based on Kconfig */ - if (IS_ENABLED(CONFIG_CONSOLE_SERIAL)) + if (CONFIG(CONSOLE_SERIAL)) qclib_cb_if_table.global_attributes = QCLIB_GA_ENABLE_UART_LOGGING; - if (IS_ENABLED(CONFIG_QC_SDI_ENABLE)) { + if (CONFIG(QC_SDI_ENABLE)) { struct prog qcsdi = PROG_INIT(PROG_REFCODE, CONFIG_CBFS_PREFIX "/qcsdi"); From 25b35d317eef9ef5d73bbecc502fdac13a478bf6 Mon Sep 17 00:00:00 2001 From: Alex James Date: Wed, 15 May 2019 20:15:47 -0500 Subject: [PATCH 083/331] mb/gigabyte/ga-b75m-d3{h,v}: Various cleanups - Enable LPC TPM support in Kconfig and add pc80/tpm to devicetree - Enable VBT support in Kconfig and add VBT files extracted from vendor firmware - Remove IGPU VBIOS entries from Kconfig - Remove unused PS2 definitions in superio.asl - Add PWRB ACPI device entry to mainboard.asl - Remove duplicate chipset register initialization from mainboard.c - Move ITE Super I/O configuration to mainboard_config_superio in romstage.c Signed-off-by: Alex James Change-Id: I2d11c55dc809b920bccf55f5f745d9f29b18bbb6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32752 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph --- src/mainboard/gigabyte/ga-b75m-d3h/Kconfig | 9 +--- .../gigabyte/ga-b75m-d3h/acpi/mainboard.asl | 2 +- .../gigabyte/ga-b75m-d3h/acpi/platform.asl | 5 +-- .../gigabyte/ga-b75m-d3h/acpi/superio.asl | 19 -------- .../gigabyte/ga-b75m-d3h/board_info.txt | 2 +- src/mainboard/gigabyte/ga-b75m-d3h/data.vbt | Bin 0 -> 3902 bytes .../gigabyte/ga-b75m-d3h/devicetree.cb | 7 ++- src/mainboard/gigabyte/ga-b75m-d3h/dsdt.asl | 2 + .../gigabyte/ga-b75m-d3h/mainboard.c | 42 +----------------- src/mainboard/gigabyte/ga-b75m-d3h/romstage.c | 29 ++++++------ src/mainboard/gigabyte/ga-b75m-d3v/Kconfig | 10 +---- .../gigabyte/ga-b75m-d3v/acpi/mainboard.asl | 23 ++++++++++ .../gigabyte/ga-b75m-d3v/acpi/platform.asl | 4 +- .../gigabyte/ga-b75m-d3v/acpi/superio.asl | 4 -- .../gigabyte/ga-b75m-d3v/board_info.txt | 4 +- src/mainboard/gigabyte/ga-b75m-d3v/data.vbt | Bin 0 -> 3902 bytes .../gigabyte/ga-b75m-d3v/devicetree.cb | 10 +++-- src/mainboard/gigabyte/ga-b75m-d3v/dsdt.asl | 2 + .../gigabyte/ga-b75m-d3v/mainboard.c | 42 +----------------- src/mainboard/gigabyte/ga-b75m-d3v/romstage.c | 31 +++++++------ 20 files changed, 81 insertions(+), 166 deletions(-) create mode 100644 src/mainboard/gigabyte/ga-b75m-d3h/data.vbt create mode 100644 src/mainboard/gigabyte/ga-b75m-d3v/acpi/mainboard.asl create mode 100644 src/mainboard/gigabyte/ga-b75m-d3v/data.vbt diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/Kconfig b/src/mainboard/gigabyte/ga-b75m-d3h/Kconfig index 6869bdb3f0..af884f62fb 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/Kconfig +++ b/src/mainboard/gigabyte/ga-b75m-d3h/Kconfig @@ -12,6 +12,7 @@ config BOARD_SPECIFIC_OPTIONS select HAVE_OPTION_TABLE select HAVE_CMOS_DEFAULT select HAVE_ACPI_RESUME + select INTEL_GMA_HAVE_VBT select INTEL_INT15 select SERIRQ_CONTINUOUS_MODE select MAINBOARD_HAS_LIBGFXINIT @@ -37,12 +38,4 @@ config MAX_CPUS int default 8 -config VGA_BIOS_ID - string - default "8086,0162" - -config VGA_BIOS_FILE - string - default "pci8086,0162.rom" - endif # BOARD_GIGABYTE_GA_B75M_D3H diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/acpi/mainboard.asl b/src/mainboard/gigabyte/ga-b75m-d3h/acpi/mainboard.asl index 34de86f976..a1c79896d7 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/acpi/mainboard.asl +++ b/src/mainboard/gigabyte/ga-b75m-d3h/acpi/mainboard.asl @@ -18,6 +18,6 @@ Scope (\_SB) { Device (PWRB) { - Name (_HID, EisaId("PNP0C0C")) + Name (_HID, EisaId ("PNP0C0C")) } } diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/acpi/platform.asl b/src/mainboard/gigabyte/ga-b75m-d3h/acpi/platform.asl index 06031646b9..10856d3394 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/acpi/platform.asl +++ b/src/mainboard/gigabyte/ga-b75m-d3h/acpi/platform.asl @@ -17,14 +17,13 @@ * entering a sleep state. The sleep state number is passed in Arg0 */ -Method(_PTS,1) +Method (_PTS, 1) { - } /* The _WAK method is called on system wakeup */ Method(_WAK,1) { - Return(Package(){0,0}) + Return (Package () {0, 0}) } diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/acpi/superio.asl b/src/mainboard/gigabyte/ga-b75m-d3h/acpi/superio.asl index 78bf687938..e69de29bb2 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/acpi/superio.asl +++ b/src/mainboard/gigabyte/ga-b75m-d3h/acpi/superio.asl @@ -1,19 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 The ChromiumOS Authors. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* mainboard configuration */ - -#define SIO_EC_ENABLE_PS2K // Enable PS/2 Keyboard -#define SIO_ENABLE_PS2M // Enable PS/2 Mouse diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/board_info.txt b/src/mainboard/gigabyte/ga-b75m-d3h/board_info.txt index 7ee7f956d8..c4fb591c0b 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/board_info.txt +++ b/src/mainboard/gigabyte/ga-b75m-d3h/board_info.txt @@ -1,5 +1,5 @@ Category: desktop -Board URL: http://www.gigabyte.com/products/product-page.aspx?pid=4150#sp +Board URL: https://www.gigabyte.com/products/product-page.aspx?pid=4150#ov ROM package: SOIC-8 ROM protocol: SPI ROM socketed: n diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/data.vbt b/src/mainboard/gigabyte/ga-b75m-d3h/data.vbt new file mode 100644 index 0000000000000000000000000000000000000000..ccbf6eed7f940d3e2de666eed4af9c9184e63c4b GIT binary patch literal 3902 zcmdT{Z){Ul6hE);_22D#tb3c#)v=r*fo|;2YngLdroMLFTu0fuwKSC&>7eCLGR7!> z0*Sbyi(pJhH3kvUG@2;x6XBDIe&CZ?j4=x_#27yi;s-;B;R7*|AoaXI9fT=+F%t2< z{O-B;^xWUO_uO;teO;T5q%b)W>5Qc#?a_hcrqpO62MRn_Ge`B(5{Zo_w?)IL@U}>N zw0{$R1}kAj&E4w&IpFG~Q1I!V*wn%NWMI4nlM_?9quUF6a=Y@KvBPEy6a6s^@7R%_ z%oipO=5v@#zYs=^R$`GudnR)@a%k`Ne4!ULF0#g8SI5RK#9**9w6Qa!1Vf0*Gre8G z-rz=wMF;vvHz#88a4I%Bf}`UYjU~g$PaY0=xV4Hwmut}Uv0BCl>8n5YH z)FkQn`}?H0oCU8}c&`q01A4LDFyN5d04iM34L&ywTsjH;fE?O112h@FG!2N~q3LM_ zSbdk?r3$N!zmt#3KxhOd)YaY7+owjNgG0md#CR&5+4@rP_-n7v`r%FqXt5ke)e265 z1RsE7ybVt9J+MJ2!>Xd`cxF&_oCjLWDlTAR$56O2`qW2#!N=r(!FDQ+HL7Gi9wI!7IS27AT%G_2*2z`zGx$ z6=q70DRrfVs#0+};cn$SA5B%D66hK4JD#BsIH?*{@XGS?Y%9 zd2}`V1SlRK_u}~!nu|0^GaFEwFK3@#t;xkwq}KfgHhbaW28$!BjRzU3`bD{{fmjE_ zbRzJszF8xTwg6O4tZ)POp?xd-Zf}R0x4>d{vnSpN|? z{6@#wS5-bJ|I1%iZlW0A^<;KwX`>fqb_GCuFtIH$F_oVjnb@1R*jY6Mxdu?fuuk!v z>^8`JN-LZh14UJ)>kLiP`OYI($NcNm%$cfY=y_Gyej%i)m#P|H0J>**!)mS1Ce@>^J-lW@U#i#u8Oc($~4 zSu2%FV>euJ7fX0`wbzwhV~lFDq6zrOsR#b@H7)M~|Bf5KaLeDg+4pX|?UqHxRx<2k z@(5!YhOaWY#MoJemzaE+v7Z>)JaWB_H~V zjUrnoVqBD87TInQPl<9_WOE`ei1Ia&-4IchCRZXd?uCy$S<(+(nu--aywXuB zXZ=m8g665z)IB4V-1=@7omN&6=qr||FFZvIt=cF6Vz8I=J4h_sXD!6T*_QIc*z6i5 z@&2ks1|B?Gn>=ZSL1|Uzv$HwHH)dRm+8lTaM~&eh#-z?584Px`u!`$`C?{~0A}amb zDBTZyiSm)=P;~a_@$m56wDlH!`+M5eO#8jP;GsrmpwB4B@_EssLbeEXS+BQN8)eJ^ zyjn}NcvJmv%r@)?$FO%jWaftF>8tjU)RhNH+Y|8SAUQJz47Nam{_D1Jr{Nd=PiOFc AjQ{`u literal 0 HcmV?d00001 diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb b/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb index 7a3568aba3..ceb9279365 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb +++ b/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb @@ -21,16 +21,15 @@ chip northbridge/intel/sandybridge device domain 0 on subsystemid 0x1458 0x5000 inherit - device pci 00.0 on # host bridge + device pci 00.0 on # Host bridge subsystemid 0x1458 0x5000 end device pci 01.0 on end # PCIe Bridge for discrete graphics - device pci 02.0 on # vga controller + device pci 02.0 on # Integrated VGA controller subsystemid 0x1458 0xd000 end chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH - # GPI routing register "alt_gp_smi_en" = "0x0000" register "gen1_dec" = "0x003c0a01" @@ -109,7 +108,7 @@ chip northbridge/intel/sandybridge end chip drivers/pc80/tpm - device pnp 0c31.0 on end + device pnp 0c31.0 on end end end device pci 1f.2 on # SATA Controller 1 diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/dsdt.asl b/src/mainboard/gigabyte/ga-b75m-d3h/dsdt.asl index 67054cc28d..c00ee30e6b 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/dsdt.asl +++ b/src/mainboard/gigabyte/ga-b75m-d3h/dsdt.asl @@ -24,7 +24,9 @@ DefinitionBlock( #include // Some generic macros + #include "acpi/mainboard.asl" #include "acpi/platform.asl" + #include "acpi/thermal.asl" #include /* global NVS and variables. */ #include diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/mainboard.c b/src/mainboard/gigabyte/ga-b75m-d3h/mainboard.c index 4e8d9f579f..cc26757914 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/mainboard.c +++ b/src/mainboard/gigabyte/ga-b75m-d3h/mainboard.c @@ -19,54 +19,16 @@ #include #include -static void mainboard_init(struct device *dev) -{ - RCBA32(0x38c8) = 0x00002005; - RCBA32(0x38c4) = 0x00802005; - RCBA32(0x2240) = 0x00330e71; - RCBA32(0x2244) = 0x003f0eb1; - RCBA32(0x2248) = 0x002102cd; - RCBA32(0x224c) = 0x00f60000; - RCBA32(0x2250) = 0x00020000; - RCBA32(0x2254) = 0x00e3004c; - RCBA32(0x2258) = 0x00e20bef; - RCBA32(0x2260) = 0x003304ed; - RCBA32(0x2278) = 0x001107c1; - RCBA32(0x227c) = 0x001d07e9; - RCBA32(0x2280) = 0x00e20000; - RCBA32(0x2284) = 0x00ee0000; - RCBA32(0x2288) = 0x005b05d3; - RCBA32(0x2318) = 0x04b8ff2e; - RCBA32(0x231c) = 0x03930f2e; - RCBA32(0x3808) = 0x005044a3; - RCBA32(0x3810) = 0x52410000; - RCBA32(0x3814) = 0x0000008a; - RCBA32(0x3818) = 0x00000006; - RCBA32(0x381c) = 0x0000072e; - RCBA32(0x3820) = 0x0000000a; - RCBA32(0x3824) = 0x00000123; - RCBA32(0x3828) = 0x00000009; - RCBA32(0x382c) = 0x00000001; - RCBA32(0x3834) = 0x0000061a; - RCBA32(0x3838) = 0x00000003; - RCBA32(0x383c) = 0x00000a76; - RCBA32(0x3840) = 0x00000004; - RCBA32(0x3844) = 0x0000e5e4; - RCBA32(0x3848) = 0x0000000e; -} - // mainboard_enable is executed as first thing after // enumerate_buses(). static void mainboard_enable(struct device *dev) { - dev->ops->init = mainboard_init; - install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_NONE, GMA_INT15_PANEL_FIT_DEFAULT, - GMA_INT15_BOOT_DISPLAY_CRT, 0); + GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); } struct chip_operations mainboard_ops = { - .enable_dev = mainboard_enable, + .enable_dev = mainboard_enable }; diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c b/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c index aa5f4840a3..49647850cd 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c +++ b/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c @@ -25,12 +25,6 @@ #define SIO_GPIO PNP_DEV(SUPERIO_BASE, IT8728F_GPIO) #define SERIAL_DEV PNP_DEV(SUPERIO_BASE, 0x01) -void mainboard_rcba_config(void) -{ - /* Enable HECI */ - RCBA32(FD2) &= ~0x2; -} - void pch_enable_lpc(void) { pci_write_config16(PCH_LPC_DEV, LPC_EN, KBC_LPC_EN | @@ -40,7 +34,10 @@ void pch_enable_lpc(void) pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10); pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000); +} +void mainboard_config_superio(void) +{ /* Initialize SuperIO */ ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); @@ -87,18 +84,20 @@ const struct southbridge_usb_port mainboard_usb_ports[] = { { 1, 5, 6 }, }; -void mainboard_get_spd(spd_raw_data *spd, bool id_only) -{ - read_spd (&spd[0], 0x50, id_only); - read_spd (&spd[1], 0x51, id_only); - read_spd (&spd[2], 0x52, id_only); - read_spd (&spd[3], 0x53, id_only); -} - void mainboard_early_init(int s3resume) { } -void mainboard_config_superio(void) +void mainboard_get_spd(spd_raw_data *spd, bool id_only) { + read_spd(&spd[0], 0x50, id_only); + read_spd(&spd[1], 0x51, id_only); + read_spd(&spd[2], 0x52, id_only); + read_spd(&spd[3], 0x53, id_only); +} + +void mainboard_rcba_config(void) +{ + /* Enable HECI */ + RCBA32(FD2) &= ~0x2; } diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/Kconfig b/src/mainboard/gigabyte/ga-b75m-d3v/Kconfig index 4048f98615..d86c742b37 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3v/Kconfig +++ b/src/mainboard/gigabyte/ga-b75m-d3v/Kconfig @@ -12,9 +12,11 @@ config BOARD_SPECIFIC_OPTIONS select HAVE_OPTION_TABLE select HAVE_CMOS_DEFAULT select HAVE_ACPI_RESUME + select INTEL_GMA_HAVE_VBT select INTEL_INT15 select SERIRQ_CONTINUOUS_MODE select MAINBOARD_HAS_LIBGFXINIT + select MAINBOARD_HAS_LPC_TPM config DRAM_RESET_GATE_GPIO int @@ -36,12 +38,4 @@ config MAX_CPUS int default 8 -config VGA_BIOS_ID - string - default "8086,0102" - -config VGA_BIOS_FILE - string - default "pci8086,0102.rom" - endif # BOARD_GIGABYTE_GA_B75M_D3V diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/acpi/mainboard.asl b/src/mainboard/gigabyte/ga-b75m-d3v/acpi/mainboard.asl new file mode 100644 index 0000000000..a1c79896d7 --- /dev/null +++ b/src/mainboard/gigabyte/ga-b75m-d3v/acpi/mainboard.asl @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Scope (\_SB) +{ + Device (PWRB) + { + Name (_HID, EisaId ("PNP0C0C")) + } +} diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/acpi/platform.asl b/src/mainboard/gigabyte/ga-b75m-d3v/acpi/platform.asl index d8d33208f8..10856d3394 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3v/acpi/platform.asl +++ b/src/mainboard/gigabyte/ga-b75m-d3v/acpi/platform.asl @@ -17,7 +17,7 @@ * entering a sleep state. The sleep state number is passed in Arg0 */ -Method(_PTS,1) +Method (_PTS, 1) { } @@ -25,5 +25,5 @@ Method(_PTS,1) Method(_WAK,1) { - Return(Package(){0,0}) + Return (Package () {0, 0}) } diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/acpi/superio.asl b/src/mainboard/gigabyte/ga-b75m-d3v/acpi/superio.asl index 4c50b6c689..e69de29bb2 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3v/acpi/superio.asl +++ b/src/mainboard/gigabyte/ga-b75m-d3v/acpi/superio.asl @@ -1,4 +0,0 @@ -/* mainboard configuration */ - -#define SIO_EC_ENABLE_PS2K // Enable PS/2 Keyboard -#define SIO_ENABLE_PS2M // Enable PS/2 Mouse diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/board_info.txt b/src/mainboard/gigabyte/ga-b75m-d3v/board_info.txt index ede1945aec..5535d9af60 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3v/board_info.txt +++ b/src/mainboard/gigabyte/ga-b75m-d3v/board_info.txt @@ -1,7 +1,7 @@ Category: desktop -Board URL: http://www.gigabyte.com/products/product-page.aspx?pid=4151#ov +Board URL: https://www.gigabyte.com/products/product-page.aspx?pid=4151#ov ROM package: SOIC-8 ROM protocol: SPI ROM socketed: n Flashrom support: y -Release date: 2012 +Release year: 2012 diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/data.vbt b/src/mainboard/gigabyte/ga-b75m-d3v/data.vbt new file mode 100644 index 0000000000000000000000000000000000000000..ccbf6eed7f940d3e2de666eed4af9c9184e63c4b GIT binary patch literal 3902 zcmdT{Z){Ul6hE);_22D#tb3c#)v=r*fo|;2YngLdroMLFTu0fuwKSC&>7eCLGR7!> z0*Sbyi(pJhH3kvUG@2;x6XBDIe&CZ?j4=x_#27yi;s-;B;R7*|AoaXI9fT=+F%t2< z{O-B;^xWUO_uO;teO;T5q%b)W>5Qc#?a_hcrqpO62MRn_Ge`B(5{Zo_w?)IL@U}>N zw0{$R1}kAj&E4w&IpFG~Q1I!V*wn%NWMI4nlM_?9quUF6a=Y@KvBPEy6a6s^@7R%_ z%oipO=5v@#zYs=^R$`GudnR)@a%k`Ne4!ULF0#g8SI5RK#9**9w6Qa!1Vf0*Gre8G z-rz=wMF;vvHz#88a4I%Bf}`UYjU~g$PaY0=xV4Hwmut}Uv0BCl>8n5YH z)FkQn`}?H0oCU8}c&`q01A4LDFyN5d04iM34L&ywTsjH;fE?O112h@FG!2N~q3LM_ zSbdk?r3$N!zmt#3KxhOd)YaY7+owjNgG0md#CR&5+4@rP_-n7v`r%FqXt5ke)e265 z1RsE7ybVt9J+MJ2!>Xd`cxF&_oCjLWDlTAR$56O2`qW2#!N=r(!FDQ+HL7Gi9wI!7IS27AT%G_2*2z`zGx$ z6=q70DRrfVs#0+};cn$SA5B%D66hK4JD#BsIH?*{@XGS?Y%9 zd2}`V1SlRK_u}~!nu|0^GaFEwFK3@#t;xkwq}KfgHhbaW28$!BjRzU3`bD{{fmjE_ zbRzJszF8xTwg6O4tZ)POp?xd-Zf}R0x4>d{vnSpN|? z{6@#wS5-bJ|I1%iZlW0A^<;KwX`>fqb_GCuFtIH$F_oVjnb@1R*jY6Mxdu?fuuk!v z>^8`JN-LZh14UJ)>kLiP`OYI($NcNm%$cfY=y_Gyej%i)m#P|H0J>**!)mS1Ce@>^J-lW@U#i#u8Oc($~4 zSu2%FV>euJ7fX0`wbzwhV~lFDq6zrOsR#b@H7)M~|Bf5KaLeDg+4pX|?UqHxRx<2k z@(5!YhOaWY#MoJemzaE+v7Z>)JaWB_H~V zjUrnoVqBD87TInQPl<9_WOE`ei1Ia&-4IchCRZXd?uCy$S<(+(nu--aywXuB zXZ=m8g665z)IB4V-1=@7omN&6=qr||FFZvIt=cF6Vz8I=J4h_sXD!6T*_QIc*z6i5 z@&2ks1|B?Gn>=ZSL1|Uzv$HwHH)dRm+8lTaM~&eh#-z?584Px`u!`$`C?{~0A}amb zDBTZyiSm)=P;~a_@$m56wDlH!`+M5eO#8jP;GsrmpwB4B@_EssLbeEXS+BQN8)eJ^ zyjn}NcvJmv%r@)?$FO%jWaftF>8tjU)RhNH+Y|8SAUQJz47Nam{_D1Jr{Nd=PiOFc AjQ{`u literal 0 HcmV?d00001 diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/devicetree.cb b/src/mainboard/gigabyte/ga-b75m-d3v/devicetree.cb index a00e2ee0c5..ceb9279365 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3v/devicetree.cb +++ b/src/mainboard/gigabyte/ga-b75m-d3v/devicetree.cb @@ -1,4 +1,5 @@ chip northbridge/intel/sandybridge + # IGD Displays register "gfx.ndid" = "3" register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410 }" @@ -20,16 +21,15 @@ chip northbridge/intel/sandybridge device domain 0 on subsystemid 0x1458 0x5000 inherit - device pci 00.0 on # host bridge + device pci 00.0 on # Host bridge subsystemid 0x1458 0x5000 end device pci 01.0 on end # PCIe Bridge for discrete graphics - device pci 02.0 on # vga controller + device pci 02.0 on # Integrated VGA controller subsystemid 0x1458 0xd000 end chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH - # GPI routing register "alt_gp_smi_en" = "0x0000" register "gen1_dec" = "0x003c0a01" @@ -106,6 +106,10 @@ chip northbridge/intel/sandybridge device pnp 2e.7 off end # GPIO device pnp 2e.a off end # IR end + + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end end device pci 1f.2 on # SATA Controller 1 subsystemid 0x1458 0xb005 diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/dsdt.asl b/src/mainboard/gigabyte/ga-b75m-d3v/dsdt.asl index 67054cc28d..c00ee30e6b 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3v/dsdt.asl +++ b/src/mainboard/gigabyte/ga-b75m-d3v/dsdt.asl @@ -24,7 +24,9 @@ DefinitionBlock( #include // Some generic macros + #include "acpi/mainboard.asl" #include "acpi/platform.asl" + #include "acpi/thermal.asl" #include /* global NVS and variables. */ #include diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/mainboard.c b/src/mainboard/gigabyte/ga-b75m-d3v/mainboard.c index 4e8d9f579f..cc26757914 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3v/mainboard.c +++ b/src/mainboard/gigabyte/ga-b75m-d3v/mainboard.c @@ -19,54 +19,16 @@ #include #include -static void mainboard_init(struct device *dev) -{ - RCBA32(0x38c8) = 0x00002005; - RCBA32(0x38c4) = 0x00802005; - RCBA32(0x2240) = 0x00330e71; - RCBA32(0x2244) = 0x003f0eb1; - RCBA32(0x2248) = 0x002102cd; - RCBA32(0x224c) = 0x00f60000; - RCBA32(0x2250) = 0x00020000; - RCBA32(0x2254) = 0x00e3004c; - RCBA32(0x2258) = 0x00e20bef; - RCBA32(0x2260) = 0x003304ed; - RCBA32(0x2278) = 0x001107c1; - RCBA32(0x227c) = 0x001d07e9; - RCBA32(0x2280) = 0x00e20000; - RCBA32(0x2284) = 0x00ee0000; - RCBA32(0x2288) = 0x005b05d3; - RCBA32(0x2318) = 0x04b8ff2e; - RCBA32(0x231c) = 0x03930f2e; - RCBA32(0x3808) = 0x005044a3; - RCBA32(0x3810) = 0x52410000; - RCBA32(0x3814) = 0x0000008a; - RCBA32(0x3818) = 0x00000006; - RCBA32(0x381c) = 0x0000072e; - RCBA32(0x3820) = 0x0000000a; - RCBA32(0x3824) = 0x00000123; - RCBA32(0x3828) = 0x00000009; - RCBA32(0x382c) = 0x00000001; - RCBA32(0x3834) = 0x0000061a; - RCBA32(0x3838) = 0x00000003; - RCBA32(0x383c) = 0x00000a76; - RCBA32(0x3840) = 0x00000004; - RCBA32(0x3844) = 0x0000e5e4; - RCBA32(0x3848) = 0x0000000e; -} - // mainboard_enable is executed as first thing after // enumerate_buses(). static void mainboard_enable(struct device *dev) { - dev->ops->init = mainboard_init; - install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_NONE, GMA_INT15_PANEL_FIT_DEFAULT, - GMA_INT15_BOOT_DISPLAY_CRT, 0); + GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); } struct chip_operations mainboard_ops = { - .enable_dev = mainboard_enable, + .enable_dev = mainboard_enable }; diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/romstage.c b/src/mainboard/gigabyte/ga-b75m-d3v/romstage.c index 035e20e2a9..eb88d366ae 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3v/romstage.c +++ b/src/mainboard/gigabyte/ga-b75m-d3v/romstage.c @@ -25,12 +25,6 @@ #define SIO_GPIO PNP_DEV(SUPERIO_BASE, IT8728F_GPIO) #define SERIAL_DEV PNP_DEV(SUPERIO_BASE, 0x01) -void mainboard_rcba_config(void) -{ - /* Enable HECI */ - RCBA32(FD2) &= ~0x2; -} - void pch_enable_lpc(void) { pci_write_config16(PCH_LPC_DEV, LPC_EN, KBC_LPC_EN | @@ -40,7 +34,10 @@ void pch_enable_lpc(void) pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10); pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000); +} +void mainboard_config_superio(void) +{ /* Initialize SuperIO */ ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); @@ -87,19 +84,21 @@ const struct southbridge_usb_port mainboard_usb_ports[] = { { 1, 5, 6 }, }; -/* FIXME: This board only has two DIMM slots! */ -void mainboard_get_spd(spd_raw_data *spd, bool id_only) -{ - read_spd (&spd[0], 0x50, id_only); - read_spd (&spd[1], 0x51, id_only); - read_spd (&spd[2], 0x52, id_only); - read_spd (&spd[3], 0x53, id_only); -} - void mainboard_early_init(int s3resume) { } -void mainboard_config_superio(void) +/* FIXME: This board only has two DIMM slots! */ +void mainboard_get_spd(spd_raw_data *spd, bool id_only) { + read_spd(&spd[0], 0x50, id_only); + read_spd(&spd[1], 0x51, id_only); + read_spd(&spd[2], 0x52, id_only); + read_spd(&spd[3], 0x53, id_only); +} + +void mainboard_rcba_config(void) +{ + /* Enable HECI */ + RCBA32(FD2) &= ~0x2; } From bf7435087eee94a6cbd5f50d816fea9168395090 Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Mon, 25 Mar 2019 17:05:20 +0100 Subject: [PATCH 084/331] sb/intel/sandybridge/early_pch: Make DMI init more readable MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add a few comments and use known register values. Based on the "2nd Generation Intel® Core™ Processor Family Mobile" datasheet and the existing serialice trace. Tested on Lenovo T520 (Intel Sandy Bridge). Still boots to GNU/Linux. Change-Id: I404515b77a22324f55581f117d79630be4ba64dd Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/c/coreboot/+/32071 Reviewed-by: Patrick Georgi Reviewed-by: HAOUAS Elyes Tested-by: build bot (Jenkins) --- .../intel/sandybridge/sandybridge.h | 15 +- src/southbridge/intel/bd82x6x/early_pch.c | 202 ++++++++++++------ src/southbridge/intel/bd82x6x/pch.h | 2 + 3 files changed, 148 insertions(+), 71 deletions(-) diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h index 92cb888a41..77f2ead74e 100644 --- a/src/northbridge/intel/sandybridge/sandybridge.h +++ b/src/northbridge/intel/sandybridge/sandybridge.h @@ -175,12 +175,23 @@ enum platform_type { #define DMIPVCCCTL 0x00c /* 16bit */ #define DMIVC0RCAP 0x010 /* 32bit */ -#define DMIVC0RCTL0 0x014 /* 32bit */ +#define DMIVC0RCTL 0x014 /* 32bit */ #define DMIVC0RSTS 0x01a /* 16bit */ +#define VC0NP 0x2 #define DMIVC1RCAP 0x01c /* 32bit */ #define DMIVC1RCTL 0x020 /* 32bit */ #define DMIVC1RSTS 0x026 /* 16bit */ +#define VC1NP 0x2 + +#define DMIVCPRCTL 0x02c /* 32bit */ + +#define DMIVCPRSTS 0x032 /* 16bit */ +#define VCPNP 0x2 + +#define DMIVCMRCTL 0x0038 /* 32 bit */ +#define DMIVCMRSTS 0x003e /* 16 bit */ +#define VCMNP 0x2 #define DMILE1D 0x050 /* 32bit */ #define DMILE1A 0x058 /* 64bit */ @@ -190,7 +201,7 @@ enum platform_type { #define DMILCAP 0x084 /* 32bit */ #define DMILCTL 0x088 /* 16bit */ #define DMILSTS 0x08a /* 16bit */ - +#define TXTRN (1 << 11) #define DMICTL1 0x0f0 /* 32bit */ #define DMICTL2 0x0fc /* 32bit */ diff --git a/src/southbridge/intel/bd82x6x/early_pch.c b/src/southbridge/intel/bd82x6x/early_pch.c index a50a159668..76ca202776 100644 --- a/src/southbridge/intel/bd82x6x/early_pch.c +++ b/src/southbridge/intel/bd82x6x/early_pch.c @@ -20,6 +20,7 @@ #include #include #include +#include /* For DMI bar. */ #include @@ -68,36 +69,29 @@ write_iobp(u32 address, u32 val) read8(DEFAULT_RCBA + IOBPS); // call wait_iobp() instead here? } - static void init_dmi (void) { + volatile u32 tmp; int i; - write32 (DEFAULT_DMIBAR + 0x0914, - read32 (DEFAULT_DMIBAR + 0x0914) | 0x80000000); - write32 (DEFAULT_DMIBAR + 0x0934, - read32 (DEFAULT_DMIBAR + 0x0934) | 0x80000000); - for (i = 0; i < 4; i++) - { - write32 (DEFAULT_DMIBAR + 0x0a00 + (i << 4), - read32 (DEFAULT_DMIBAR + 0x0a00 + (i << 4)) & 0xf3ffffff); - write32 (DEFAULT_DMIBAR + 0x0a04 + (i << 4), - read32 (DEFAULT_DMIBAR + 0x0a04 + (i << 4)) | 0x800); + DMIBAR32(0x0914) |= 0x80000000; + DMIBAR32(0x0934) |= 0x80000000; + + for (i = 0; i < 4; i++) { + DMIBAR32(0x0a00 + (i << 4)) &= 0xf3ffffff; + DMIBAR32(0x0a04 + (i << 4)) |= 0x800; } - write32 (DEFAULT_DMIBAR + 0x0c30, (read32 (DEFAULT_DMIBAR + 0x0c30) - & 0xfffffff) | 0x40000000); - for (i = 0; i < 2; i++) - { - write32 (DEFAULT_DMIBAR + 0x0904 + (i << 5), - read32 (DEFAULT_DMIBAR + 0x0904 + (i << 5)) & 0xfe3fffff); - write32 (DEFAULT_DMIBAR + 0x090c + (i << 5), - read32 (DEFAULT_DMIBAR + 0x090c + (i << 5)) & 0xfff1ffff); + DMIBAR32(0x0c30) = (DMIBAR32(0x0c30) & 0xfffffff) | 0x40000000; + + for (i = 0; i < 2; i++) { + DMIBAR32(0x0904 + (i << 5)) &= 0xfe3fffff; + DMIBAR32(0x090c + (i << 5)) &= 0xfff1ffff; } - write32 (DEFAULT_DMIBAR + 0x090c, - read32 (DEFAULT_DMIBAR + 0x090c) & 0xfe1fffff); - write32 (DEFAULT_DMIBAR + 0x092c, - read32 (DEFAULT_DMIBAR + 0x092c) & 0xfe1fffff); + + DMIBAR32(0x090c) &= 0xfe1fffff; + DMIBAR32(0x092c) &= 0xfe1fffff; + read32 (DEFAULT_DMIBAR + 0x0904); // !!! = 0x7a1842ec write32 (DEFAULT_DMIBAR + 0x0904, 0x7a1842ec); read32 (DEFAULT_DMIBAR + 0x090c); // !!! = 0x00000208 @@ -226,33 +220,54 @@ init_dmi (void) write32 (DEFAULT_DMIBAR + 0x0934, 0x98200280); read32 (DEFAULT_DMIBAR + 0x022c); // !!! = 0x00c26460 write32 (DEFAULT_DMIBAR + 0x022c, 0x00c2403c); - read8 (DEFAULT_RCBA + 0x21a4); // !!! = 0x42 - read32 (DEFAULT_RCBA + 0x21a4); // !!! = 0x00012c42 - read32 (DEFAULT_RCBA + 0x2340); // !!! = 0x0013001b - write32 (DEFAULT_RCBA + 0x2340, 0x003a001b); - read8 (DEFAULT_RCBA + 0x21b0); // !!! = 0x01 - write8 (DEFAULT_RCBA + 0x21b0, 0x02); - read32 (DEFAULT_DMIBAR + 0x0084); // !!! = 0x0041ac41 - write32 (DEFAULT_DMIBAR + 0x0084, 0x0041ac42); - read8 (DEFAULT_DMIBAR + 0x0088); // !!! = 0x00 - write8 (DEFAULT_DMIBAR + 0x0088, 0x20); - read16 (DEFAULT_DMIBAR + 0x008a); // !!! = 0x0041 - read8 (DEFAULT_DMIBAR + 0x0088); // !!! = 0x00 - write8 (DEFAULT_DMIBAR + 0x0088, 0x20); - read16 (DEFAULT_DMIBAR + 0x008a); // !!! = 0x0042 - read16 (DEFAULT_DMIBAR + 0x008a); // !!! = 0x0042 + /* Link Capabilities Register */ + RCBA32(0x21a4) = (RCBA32(0x21a4) & ~0x3fc00) | + (3 << 10) | // L0s and L1 entry supported + (2 << 12) | // L0s 128 ns to less than 256 ns + (2 << 15); // L1 2 us to less than 4 us - read32 (DEFAULT_DMIBAR + 0x0014); // !!! = 0x8000007f - write32 (DEFAULT_DMIBAR + 0x0014, 0x80000019); - read32 (DEFAULT_DMIBAR + 0x0020); // !!! = 0x01000000 - write32 (DEFAULT_DMIBAR + 0x0020, 0x81000022); - read32 (DEFAULT_DMIBAR + 0x002c); // !!! = 0x02000000 - write32 (DEFAULT_DMIBAR + 0x002c, 0x82000044); - read32 (DEFAULT_DMIBAR + 0x0038); // !!! = 0x07000080 - write32 (DEFAULT_DMIBAR + 0x0038, 0x87000080); - read8 (DEFAULT_DMIBAR + 0x0004); // !!! = 0x00 - write8 (DEFAULT_DMIBAR + 0x0004, 0x01); + RCBA32(0x2340) = (RCBA32(0x2340) & ~0xff0000) | (0x3a << 16); + RCBA8(0x21b0) = (RCBA8(0x21b0) & ~0xf) | 2; + + /* Write once settings. */ + DMIBAR32(DMILCAP) = (DMIBAR32(DMILCAP) & ~0x3f00f) | + (2 << 0) | // 5GT/s + (2 << 12) | // L0s 128 ns to less than 256 ns + (2 << 15); // L1 2 us to less than 4 us + + DMIBAR8(DMILCTL) |= 0x20; // Retrain link + while (DMIBAR16(DMILSTS) & TXTRN) + ; + + DMIBAR8(DMILCTL) |= 0x20; // Retrain link + while (DMIBAR16(DMILSTS) & TXTRN) + ; + + const u8 w = (DMIBAR16(DMILSTS) >> 4) & 0x1f; + const u16 t = (DMIBAR16(DMILSTS) & 0xf) * 2500; + + printk(BIOS_DEBUG, "DMI: Running at X%x @ %dMT/s\n", w, t); + /* + * Virtual Channel resources must match settings in RCBA! + * + * Channel Vp and Vm are documented in + * "Desktop 4th Generation Intel Core Processor Family, Desktop Intel + * Pentium Processor Family, and Desktop Intel Celeron Processor Family + * Vol. 2" + */ + + /* Channel 0: Enable, Set ID to 0, map TC0 and TC3 and TC4 to VC0. */ + DMIBAR32(DMIVC0RCTL) = (1 << 31) | (0 << 24) | (0x0c << 1) | 1; + /* Channel 1: Enable, Set ID to 1, map TC1 and TC5 to VC1. */ + DMIBAR32(DMIVC1RCTL) = (1 << 31) | (1 << 24) | (0x11 << 1); + /* Channel p: Enable, Set ID to 2, map TC2 and TC6 to VCp */ + DMIBAR32(DMIVCPRCTL) = (1 << 31) | (2 << 24) | (0x22 << 1); + /* Channel m: Enable, Set ID to 0, map TC7 to VCm */ + DMIBAR32(DMIVCMRCTL) = (1 << 31) | (7 << 24) | (0x40 << 1); + + /* Set Extended VC Count (EVCC) to 1 as Channel 1 is active. */ + DMIBAR8(DMIPVCCAP1) |= 1; read32 (DEFAULT_RCBA + 0x0050); // !!! = 0x01200654 write32 (DEFAULT_RCBA + 0x0050, 0x01200654); @@ -261,27 +276,76 @@ init_dmi (void) read32 (DEFAULT_RCBA + 0x0050); // !!! = 0x012a0654 read8 (DEFAULT_RCBA + 0x1114); // !!! = 0x00 write8 (DEFAULT_RCBA + 0x1114, 0x05); - read32 (DEFAULT_RCBA + 0x2014); // !!! = 0x80000011 - write32 (DEFAULT_RCBA + 0x2014, 0x80000019); - read32 (DEFAULT_RCBA + 0x2020); // !!! = 0x00000000 - write32 (DEFAULT_RCBA + 0x2020, 0x81000022); - read32 (DEFAULT_RCBA + 0x2020); // !!! = 0x81000022 - read32 (DEFAULT_RCBA + 0x2030); // !!! = 0x00000000 - write32 (DEFAULT_RCBA + 0x2030, 0x82000044); - read32 (DEFAULT_RCBA + 0x2030); // !!! = 0x82000044 - read32 (DEFAULT_RCBA + 0x2040); // !!! = 0x00000000 - write32 (DEFAULT_RCBA + 0x2040, 0x87000080); - read32 (DEFAULT_RCBA + 0x0050); // !!! = 0x012a0654 - write32 (DEFAULT_RCBA + 0x0050, 0x812a0654); - read32 (DEFAULT_RCBA + 0x0050); // !!! = 0x812a0654 - read16 (DEFAULT_RCBA + 0x201a); // !!! = 0x0000 - read16 (DEFAULT_RCBA + 0x2026); // !!! = 0x0000 - read16 (DEFAULT_RCBA + 0x2036); // !!! = 0x0000 - read16 (DEFAULT_RCBA + 0x2046); // !!! = 0x0000 - read16 (DEFAULT_DMIBAR + 0x001a); // !!! = 0x0000 - read16 (DEFAULT_DMIBAR + 0x0026); // !!! = 0x0000 - read16 (DEFAULT_DMIBAR + 0x0032); // !!! = 0x0000 - read16 (DEFAULT_DMIBAR + 0x003e); // !!! = 0x0000 + + /* + * Virtual Channel resources must match settings in DMIBAR! + * + * Some of the following settings are taken from + * "Intel Core i5-600, i3-500 Desktop Processor Series and Intel + * Pentium Desktop Processor 6000 Series Vol. 2" datasheet and + * serialice traces. + */ + + /* Virtual Channel 0 Resource Control Register. + * Enable channel. + * Set Virtual Channel Identifier. + * Map TC0 and TC3 and TC4 to VC0. + */ + + RCBA32(0x2014) = (1 << 31) | (0 << 24) | (0x0c << 1) | 1; + + /* Virtual Channel 1 Resource Control Register. + * Enable channel. + * Set Virtual Channel Identifier. + * Map TC1 and TC5 to VC1. + */ + RCBA32(0x2020) = (1 << 31) | (1 << 24) | (0x11 << 1); + /* Read back register */ + tmp = RCBA32(0x2020); + + /* Virtual Channel private Resource Control Register. + * Enable channel. + * Set Virtual Channel Identifier. + * Map TC2 and TC6 to VCp. + */ + RCBA32(0x2030) = (1 << 31) | (2 << 24) | (0x22 << 1); + /* Read back register */ + tmp = RCBA32(0x2030); + + /* Virtual Channel ME Resource Control Register. + * Enable channel. + * Set Virtual Channel Identifier. + * Map TC7 to VCm. + */ + RCBA32(0x2040) = (1 << 31) | (7 << 24) | (0x40 << 1); + + /* Lock Virtual Channel Resource control register. */ + RCBA32(0x0050) |= 0x80000000; + /* Read back register */ + tmp = RCBA32(0x0050); + + /* Wait for virtual channels negotiation pending */ + while (RCBA16(0x201a) & VCNEGPND) + ; + while (RCBA16(0x2026) & VCNEGPND) + ; + while (RCBA16(0x2036) & VCNEGPND) + ; + while (RCBA16(0x2046) & VCNEGPND) + ; + + /* + * BIOS Requirement: Check if DMI VC Negotiation was successful. + * Wait for virtual channels negotiation pending. + */ + while (DMIBAR16(DMIVC0RSTS) & VC0NP) + ; + while (DMIBAR16(DMIVC1RSTS) & VC1NP) + ; + while (DMIBAR16(DMIVCPRSTS) & VCPNP) + ; + while (DMIBAR16(DMIVCMRSTS) & VCMNP) + ; } void diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index 21b603108a..fb8238ad4f 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -310,6 +310,8 @@ early_usb_init (const struct southbridge_usb_port *portmap); #define IOTR2 0x1e90 /* 64bit */ #define IOTR3 0x1e98 /* 64bit */ +#define VCNEGPND 2 + #define TCTL 0x3000 /* 8bit */ #define NOINT 0 From a1e9eefa402a9ec3a008e9d0d4b3041274b8d0b7 Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Mon, 25 Mar 2019 11:47:36 +0100 Subject: [PATCH 085/331] sb/intel/bd82x6x/early_pch: Make use of RCBA and DMIBAR marcros Use RCBA and DMIBAR macros to get rid of DEFAULT_RCBA and DEFAULT_DMIBAR. Tested on Lenovo T520 (Intel Sandy Bridge). Still boots to OS, no errors visible in dmesg. Change-Id: Ic9be2240ea10b17c8cc289007dccadbb9e3f69ab Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/c/coreboot/+/32072 Tested-by: build bot (Jenkins) Reviewed-by: HAOUAS Elyes --- src/southbridge/intel/bd82x6x/early_pch.c | 326 +++++++++++----------- 1 file changed, 164 insertions(+), 162 deletions(-) diff --git a/src/southbridge/intel/bd82x6x/early_pch.c b/src/southbridge/intel/bd82x6x/early_pch.c index 76ca202776..76f1447e8a 100644 --- a/src/southbridge/intel/bd82x6x/early_pch.c +++ b/src/southbridge/intel/bd82x6x/early_pch.c @@ -20,6 +20,7 @@ #include #include #include +#include #include /* For DMI bar. */ @@ -32,41 +33,41 @@ static void wait_iobp(void) { - while (read8(DEFAULT_RCBA + IOBPS) & 1) + while (RCBA8(IOBPS) & 1) ; // implement timeout? } static u32 read_iobp(u32 address) { + volatile u32 tmp; u32 ret; - write32(DEFAULT_RCBA + IOBPIRI, address); - write16(DEFAULT_RCBA + IOBPS, (read16(DEFAULT_RCBA + IOBPS) - & 0x1ff) | 0x600); + RCBA32(IOBPIRI) = address; + RCBA16(IOBPS) = (RCBA16(IOBPS) & 0x1ff) | 0x600; wait_iobp(); - ret = read32(DEFAULT_RCBA + IOBPD); + ret = RCBA32(IOBPD); wait_iobp(); - read8(DEFAULT_RCBA + IOBPS); // call wait_iobp() instead here? + tmp = RCBA8(IOBPS); // call wait_iobp() instead here? return ret; } static void write_iobp(u32 address, u32 val) { + volatile u32 tmp; /* this function was probably pch_iobp_update with the andvalue * being 0. So either the IOBP read can be removed or this function * and the pch_iobp_update function in ramstage could be merged */ read_iobp(address); - write16(DEFAULT_RCBA + IOBPS, (read16(DEFAULT_RCBA + IOBPS) - & 0x1ff) | 0x600); + RCBA16(IOBPS) = (RCBA16(IOBPS) & 0x1ff) | 0x600; wait_iobp(); - write32(DEFAULT_RCBA + IOBPD, val); + RCBA32(IOBPD) = val; wait_iobp(); - write16(DEFAULT_RCBA + IOBPS, - (read16(DEFAULT_RCBA + IOBPS) & 0x1ff) | 0x600); - read8(DEFAULT_RCBA + IOBPS); // call wait_iobp() instead here? + RCBA16(IOBPS) = (RCBA16(IOBPS) & 0x1ff) | 0x600; + + tmp = RCBA8(IOBPS); // call wait_iobp() instead here? } static void @@ -92,134 +93,134 @@ init_dmi (void) DMIBAR32(0x090c) &= 0xfe1fffff; DMIBAR32(0x092c) &= 0xfe1fffff; - read32 (DEFAULT_DMIBAR + 0x0904); // !!! = 0x7a1842ec - write32 (DEFAULT_DMIBAR + 0x0904, 0x7a1842ec); - read32 (DEFAULT_DMIBAR + 0x090c); // !!! = 0x00000208 - write32 (DEFAULT_DMIBAR + 0x090c, 0x00000128); - read32 (DEFAULT_DMIBAR + 0x0924); // !!! = 0x7a1842ec - write32 (DEFAULT_DMIBAR + 0x0924, 0x7a1842ec); - read32 (DEFAULT_DMIBAR + 0x092c); // !!! = 0x00000208 - write32 (DEFAULT_DMIBAR + 0x092c, 0x00000128); - read32 (DEFAULT_DMIBAR + 0x0700); // !!! = 0x46139008 - write32 (DEFAULT_DMIBAR + 0x0700, 0x46139008); - read32 (DEFAULT_DMIBAR + 0x0720); // !!! = 0x46139008 - write32 (DEFAULT_DMIBAR + 0x0720, 0x46139008); - read32 (DEFAULT_DMIBAR + 0x0c04); // !!! = 0x2e680008 - write32 (DEFAULT_DMIBAR + 0x0c04, 0x2e680008); - read32 (DEFAULT_DMIBAR + 0x0904); // !!! = 0x7a1842ec - write32 (DEFAULT_DMIBAR + 0x0904, 0x3a1842ec); - read32 (DEFAULT_DMIBAR + 0x0924); // !!! = 0x7a1842ec - write32 (DEFAULT_DMIBAR + 0x0924, 0x3a1842ec); - read32 (DEFAULT_DMIBAR + 0x0910); // !!! = 0x00006300 - write32 (DEFAULT_DMIBAR + 0x0910, 0x00004300); - read32 (DEFAULT_DMIBAR + 0x0930); // !!! = 0x00006300 - write32 (DEFAULT_DMIBAR + 0x0930, 0x00004300); - read32 (DEFAULT_DMIBAR + 0x0a00); // !!! = 0x03042010 - write32 (DEFAULT_DMIBAR + 0x0a00, 0x03042018); - read32 (DEFAULT_DMIBAR + 0x0a10); // !!! = 0x03042010 - write32 (DEFAULT_DMIBAR + 0x0a10, 0x03042018); - read32 (DEFAULT_DMIBAR + 0x0a20); // !!! = 0x03042010 - write32 (DEFAULT_DMIBAR + 0x0a20, 0x03042018); - read32 (DEFAULT_DMIBAR + 0x0a30); // !!! = 0x03042010 - write32 (DEFAULT_DMIBAR + 0x0a30, 0x03042018); - read32 (DEFAULT_DMIBAR + 0x0c00); // !!! = 0x29700c08 - write32 (DEFAULT_DMIBAR + 0x0c00, 0x29700c08); - read32 (DEFAULT_DMIBAR + 0x0a04); // !!! = 0x0c0708f0 - write32 (DEFAULT_DMIBAR + 0x0a04, 0x0c0718f0); - read32 (DEFAULT_DMIBAR + 0x0a14); // !!! = 0x0c0708f0 - write32 (DEFAULT_DMIBAR + 0x0a14, 0x0c0718f0); - read32 (DEFAULT_DMIBAR + 0x0a24); // !!! = 0x0c0708f0 - write32 (DEFAULT_DMIBAR + 0x0a24, 0x0c0718f0); - read32 (DEFAULT_DMIBAR + 0x0a34); // !!! = 0x0c0708f0 - write32 (DEFAULT_DMIBAR + 0x0a34, 0x0c0718f0); - read32 (DEFAULT_DMIBAR + 0x0900); // !!! = 0x50000000 - write32 (DEFAULT_DMIBAR + 0x0900, 0x50000000); - read32 (DEFAULT_DMIBAR + 0x0920); // !!! = 0x50000000 - write32 (DEFAULT_DMIBAR + 0x0920, 0x50000000); - read32 (DEFAULT_DMIBAR + 0x0908); // !!! = 0x51ffffff - write32 (DEFAULT_DMIBAR + 0x0908, 0x51ffffff); - read32 (DEFAULT_DMIBAR + 0x0928); // !!! = 0x51ffffff - write32 (DEFAULT_DMIBAR + 0x0928, 0x51ffffff); - read32 (DEFAULT_DMIBAR + 0x0a00); // !!! = 0x03042018 - write32 (DEFAULT_DMIBAR + 0x0a00, 0x03042018); - read32 (DEFAULT_DMIBAR + 0x0a10); // !!! = 0x03042018 - write32 (DEFAULT_DMIBAR + 0x0a10, 0x03042018); - read32 (DEFAULT_DMIBAR + 0x0a20); // !!! = 0x03042018 - write32 (DEFAULT_DMIBAR + 0x0a20, 0x03042018); - read32 (DEFAULT_DMIBAR + 0x0a30); // !!! = 0x03042018 - write32 (DEFAULT_DMIBAR + 0x0a30, 0x03042018); - read32 (DEFAULT_DMIBAR + 0x0700); // !!! = 0x46139008 - write32 (DEFAULT_DMIBAR + 0x0700, 0x46139008); - read32 (DEFAULT_DMIBAR + 0x0720); // !!! = 0x46139008 - write32 (DEFAULT_DMIBAR + 0x0720, 0x46139008); - read32 (DEFAULT_DMIBAR + 0x0904); // !!! = 0x3a1842ec - write32 (DEFAULT_DMIBAR + 0x0904, 0x3a1846ec); - read32 (DEFAULT_DMIBAR + 0x0924); // !!! = 0x3a1842ec - write32 (DEFAULT_DMIBAR + 0x0924, 0x3a1846ec); - read32 (DEFAULT_DMIBAR + 0x0a00); // !!! = 0x03042018 - write32 (DEFAULT_DMIBAR + 0x0a00, 0x03042018); - read32 (DEFAULT_DMIBAR + 0x0a10); // !!! = 0x03042018 - write32 (DEFAULT_DMIBAR + 0x0a10, 0x03042018); - read32 (DEFAULT_DMIBAR + 0x0a20); // !!! = 0x03042018 - write32 (DEFAULT_DMIBAR + 0x0a20, 0x03042018); - read32 (DEFAULT_DMIBAR + 0x0a30); // !!! = 0x03042018 - write32 (DEFAULT_DMIBAR + 0x0a30, 0x03042018); - read32 (DEFAULT_DMIBAR + 0x0908); // !!! = 0x51ffffff - write32 (DEFAULT_DMIBAR + 0x0908, 0x51ffffff); - read32 (DEFAULT_DMIBAR + 0x0928); // !!! = 0x51ffffff - write32 (DEFAULT_DMIBAR + 0x0928, 0x51ffffff); - read32 (DEFAULT_DMIBAR + 0x0c00); // !!! = 0x29700c08 - write32 (DEFAULT_DMIBAR + 0x0c00, 0x29700c08); - read32 (DEFAULT_DMIBAR + 0x0c0c); // !!! = 0x16063400 - write32 (DEFAULT_DMIBAR + 0x0c0c, 0x00063400); - read32 (DEFAULT_DMIBAR + 0x0700); // !!! = 0x46139008 - write32 (DEFAULT_DMIBAR + 0x0700, 0x46339008); - read32 (DEFAULT_DMIBAR + 0x0720); // !!! = 0x46139008 - write32 (DEFAULT_DMIBAR + 0x0720, 0x46339008); - read32 (DEFAULT_DMIBAR + 0x0700); // !!! = 0x46339008 - write32 (DEFAULT_DMIBAR + 0x0700, 0x45339008); - read32 (DEFAULT_DMIBAR + 0x0720); // !!! = 0x46339008 - write32 (DEFAULT_DMIBAR + 0x0720, 0x45339008); - read32 (DEFAULT_DMIBAR + 0x0700); // !!! = 0x45339008 - write32 (DEFAULT_DMIBAR + 0x0700, 0x453b9008); - read32 (DEFAULT_DMIBAR + 0x0720); // !!! = 0x45339008 - write32 (DEFAULT_DMIBAR + 0x0720, 0x453b9008); - read32 (DEFAULT_DMIBAR + 0x0700); // !!! = 0x453b9008 - write32 (DEFAULT_DMIBAR + 0x0700, 0x45bb9008); - read32 (DEFAULT_DMIBAR + 0x0720); // !!! = 0x453b9008 - write32 (DEFAULT_DMIBAR + 0x0720, 0x45bb9008); - read32 (DEFAULT_DMIBAR + 0x0700); // !!! = 0x45bb9008 - write32 (DEFAULT_DMIBAR + 0x0700, 0x45fb9008); - read32 (DEFAULT_DMIBAR + 0x0720); // !!! = 0x45bb9008 - write32 (DEFAULT_DMIBAR + 0x0720, 0x45fb9008); - read32 (DEFAULT_DMIBAR + 0x0914); // !!! = 0x9021a080 - write32 (DEFAULT_DMIBAR + 0x0914, 0x9021a280); - read32 (DEFAULT_DMIBAR + 0x0934); // !!! = 0x9021a080 - write32 (DEFAULT_DMIBAR + 0x0934, 0x9021a280); - read32 (DEFAULT_DMIBAR + 0x0914); // !!! = 0x9021a280 - write32 (DEFAULT_DMIBAR + 0x0914, 0x9821a280); - read32 (DEFAULT_DMIBAR + 0x0934); // !!! = 0x9021a280 - write32 (DEFAULT_DMIBAR + 0x0934, 0x9821a280); - read32 (DEFAULT_DMIBAR + 0x0a00); // !!! = 0x03042018 - write32 (DEFAULT_DMIBAR + 0x0a00, 0x03242018); - read32 (DEFAULT_DMIBAR + 0x0a10); // !!! = 0x03042018 - write32 (DEFAULT_DMIBAR + 0x0a10, 0x03242018); - read32 (DEFAULT_DMIBAR + 0x0a20); // !!! = 0x03042018 - write32 (DEFAULT_DMIBAR + 0x0a20, 0x03242018); - read32 (DEFAULT_DMIBAR + 0x0a30); // !!! = 0x03042018 - write32 (DEFAULT_DMIBAR + 0x0a30, 0x03242018); - read32 (DEFAULT_DMIBAR + 0x0258); // !!! = 0x40000600 - write32 (DEFAULT_DMIBAR + 0x0258, 0x60000600); - read32 (DEFAULT_DMIBAR + 0x0904); // !!! = 0x3a1846ec - write32 (DEFAULT_DMIBAR + 0x0904, 0x2a1846ec); - read32 (DEFAULT_DMIBAR + 0x0914); // !!! = 0x9821a280 - write32 (DEFAULT_DMIBAR + 0x0914, 0x98200280); - read32 (DEFAULT_DMIBAR + 0x0924); // !!! = 0x3a1846ec - write32 (DEFAULT_DMIBAR + 0x0924, 0x2a1846ec); - read32 (DEFAULT_DMIBAR + 0x0934); // !!! = 0x9821a280 - write32 (DEFAULT_DMIBAR + 0x0934, 0x98200280); - read32 (DEFAULT_DMIBAR + 0x022c); // !!! = 0x00c26460 - write32 (DEFAULT_DMIBAR + 0x022c, 0x00c2403c); + tmp = DMIBAR32(0x0904); // !!! = 0x7a1842ec + DMIBAR32(0x0904) = 0x7a1842ec; + tmp = DMIBAR32(0x090c); // !!! = 0x00000208 + DMIBAR32(0x090c) = 0x00000128; + tmp = DMIBAR32(0x0924); // !!! = 0x7a1842ec + DMIBAR32(0x0924) = 0x7a1842ec; + tmp = DMIBAR32(0x092c); // !!! = 0x00000208 + DMIBAR32(0x092c) = 0x00000128; + tmp = DMIBAR32(0x0700); // !!! = 0x46139008 + DMIBAR32(0x0700) = 0x46139008; + tmp = DMIBAR32(0x0720); // !!! = 0x46139008 + DMIBAR32(0x0720) = 0x46139008; + tmp = DMIBAR32(0x0c04); // !!! = 0x2e680008 + DMIBAR32(0x0c04) = 0x2e680008; + tmp = DMIBAR32(0x0904); // !!! = 0x7a1842ec + DMIBAR32(0x0904) = 0x3a1842ec; + tmp = DMIBAR32(0x0924); // !!! = 0x7a1842ec + DMIBAR32(0x0924) = 0x3a1842ec; + tmp = DMIBAR32(0x0910); // !!! = 0x00006300 + DMIBAR32(0x0910) = 0x00004300; + tmp = DMIBAR32(0x0930); // !!! = 0x00006300 + DMIBAR32(0x0930) = 0x00004300; + tmp = DMIBAR32(0x0a00); // !!! = 0x03042010 + DMIBAR32(0x0a00) = 0x03042018; + tmp = DMIBAR32(0x0a10); // !!! = 0x03042010 + DMIBAR32(0x0a10) = 0x03042018; + tmp = DMIBAR32(0x0a20); // !!! = 0x03042010 + DMIBAR32(0x0a20) = 0x03042018; + tmp = DMIBAR32(0x0a30); // !!! = 0x03042010 + DMIBAR32(0x0a30) = 0x03042018; + tmp = DMIBAR32(0x0c00); // !!! = 0x29700c08 + DMIBAR32(0x0c00) = 0x29700c08; + tmp = DMIBAR32(0x0a04); // !!! = 0x0c0708f0 + DMIBAR32(0x0a04) = 0x0c0718f0; + tmp = DMIBAR32(0x0a14); // !!! = 0x0c0708f0 + DMIBAR32(0x0a14) = 0x0c0718f0; + tmp = DMIBAR32(0x0a24); // !!! = 0x0c0708f0 + DMIBAR32(0x0a24) = 0x0c0718f0; + tmp = DMIBAR32(0x0a34); // !!! = 0x0c0708f0 + DMIBAR32(0x0a34) = 0x0c0718f0; + tmp = DMIBAR32(0x0900); // !!! = 0x50000000 + DMIBAR32(0x0900) = 0x50000000; + tmp = DMIBAR32(0x0920); // !!! = 0x50000000 + DMIBAR32(0x0920) = 0x50000000; + tmp = DMIBAR32(0x0908); // !!! = 0x51ffffff + DMIBAR32(0x0908) = 0x51ffffff; + tmp = DMIBAR32(0x0928); // !!! = 0x51ffffff + DMIBAR32(0x0928) = 0x51ffffff; + tmp = DMIBAR32(0x0a00); // !!! = 0x03042018 + DMIBAR32(0x0a00) = 0x03042018; + tmp = DMIBAR32(0x0a10); // !!! = 0x03042018 + DMIBAR32(0x0a10) = 0x03042018; + tmp = DMIBAR32(0x0a20); // !!! = 0x03042018 + DMIBAR32(0x0a20) = 0x03042018; + tmp = DMIBAR32(0x0a30); // !!! = 0x03042018 + DMIBAR32(0x0a30) = 0x03042018; + tmp = DMIBAR32(0x0700); // !!! = 0x46139008 + DMIBAR32(0x0700) = 0x46139008; + tmp = DMIBAR32(0x0720); // !!! = 0x46139008 + DMIBAR32(0x0720) = 0x46139008; + tmp = DMIBAR32(0x0904); // !!! = 0x3a1842ec + DMIBAR32(0x0904) = 0x3a1846ec; + tmp = DMIBAR32(0x0924); // !!! = 0x3a1842ec + DMIBAR32(0x0924) = 0x3a1846ec; + tmp = DMIBAR32(0x0a00); // !!! = 0x03042018 + DMIBAR32(0x0a00) = 0x03042018; + tmp = DMIBAR32(0x0a10); // !!! = 0x03042018 + DMIBAR32(0x0a10) = 0x03042018; + tmp = DMIBAR32(0x0a20); // !!! = 0x03042018 + DMIBAR32(0x0a20) = 0x03042018; + tmp = DMIBAR32(0x0a30); // !!! = 0x03042018 + DMIBAR32(0x0a30) = 0x03042018; + tmp = DMIBAR32(0x0908); // !!! = 0x51ffffff + DMIBAR32(0x0908) = 0x51ffffff; + tmp = DMIBAR32(0x0928); // !!! = 0x51ffffff + DMIBAR32(0x0928) = 0x51ffffff; + tmp = DMIBAR32(0x0c00); // !!! = 0x29700c08 + DMIBAR32(0x0c00) = 0x29700c08; + tmp = DMIBAR32(0x0c0c); // !!! = 0x16063400 + DMIBAR32(0x0c0c) = 0x00063400; + tmp = DMIBAR32(0x0700); // !!! = 0x46139008 + DMIBAR32(0x0700) = 0x46339008; + tmp = DMIBAR32(0x0720); // !!! = 0x46139008 + DMIBAR32(0x0720) = 0x46339008; + tmp = DMIBAR32(0x0700); // !!! = 0x46339008 + DMIBAR32(0x0700) = 0x45339008; + tmp = DMIBAR32(0x0720); // !!! = 0x46339008 + DMIBAR32(0x0720) = 0x45339008; + tmp = DMIBAR32(0x0700); // !!! = 0x45339008 + DMIBAR32(0x0700) = 0x453b9008; + tmp = DMIBAR32(0x0720); // !!! = 0x45339008 + DMIBAR32(0x0720) = 0x453b9008; + tmp = DMIBAR32(0x0700); // !!! = 0x453b9008 + DMIBAR32(0x0700) = 0x45bb9008; + tmp = DMIBAR32(0x0720); // !!! = 0x453b9008 + DMIBAR32(0x0720) = 0x45bb9008; + tmp = DMIBAR32(0x0700); // !!! = 0x45bb9008 + DMIBAR32(0x0700) = 0x45fb9008; + tmp = DMIBAR32(0x0720); // !!! = 0x45bb9008 + DMIBAR32(0x0720) = 0x45fb9008; + tmp = DMIBAR32(0x0914); // !!! = 0x9021a080 + DMIBAR32(0x0914) = 0x9021a280; + tmp = DMIBAR32(0x0934); // !!! = 0x9021a080 + DMIBAR32(0x0934) = 0x9021a280; + tmp = DMIBAR32(0x0914); // !!! = 0x9021a280 + DMIBAR32(0x0914) = 0x9821a280; + tmp = DMIBAR32(0x0934); // !!! = 0x9021a280 + DMIBAR32(0x0934) = 0x9821a280; + tmp = DMIBAR32(0x0a00); // !!! = 0x03042018 + DMIBAR32(0x0a00) = 0x03242018; + tmp = DMIBAR32(0x0a10); // !!! = 0x03042018 + DMIBAR32(0x0a10) = 0x03242018; + tmp = DMIBAR32(0x0a20); // !!! = 0x03042018 + DMIBAR32(0x0a20) = 0x03242018; + tmp = DMIBAR32(0x0a30); // !!! = 0x03042018 + DMIBAR32(0x0a30) = 0x03242018; + tmp = DMIBAR32(0x0258); // !!! = 0x40000600 + DMIBAR32(0x0258) = 0x60000600; + tmp = DMIBAR32(0x0904); // !!! = 0x3a1846ec + DMIBAR32(0x0904) = 0x2a1846ec; + tmp = DMIBAR32(0x0914); // !!! = 0x9821a280 + DMIBAR32(0x0914) = 0x98200280; + tmp = DMIBAR32(0x0924); // !!! = 0x3a1846ec + DMIBAR32(0x0924) = 0x2a1846ec; + tmp = DMIBAR32(0x0934); // !!! = 0x9821a280 + DMIBAR32(0x0934) = 0x98200280; + tmp = DMIBAR32(0x022c); // !!! = 0x00c26460 + DMIBAR32(0x022c) = 0x00c2403c; /* Link Capabilities Register */ RCBA32(0x21a4) = (RCBA32(0x21a4) & ~0x3fc00) | @@ -269,13 +270,13 @@ init_dmi (void) /* Set Extended VC Count (EVCC) to 1 as Channel 1 is active. */ DMIBAR8(DMIPVCCAP1) |= 1; - read32 (DEFAULT_RCBA + 0x0050); // !!! = 0x01200654 - write32 (DEFAULT_RCBA + 0x0050, 0x01200654); - read32 (DEFAULT_RCBA + 0x0050); // !!! = 0x01200654 - write32 (DEFAULT_RCBA + 0x0050, 0x012a0654); - read32 (DEFAULT_RCBA + 0x0050); // !!! = 0x012a0654 - read8 (DEFAULT_RCBA + 0x1114); // !!! = 0x00 - write8 (DEFAULT_RCBA + 0x1114, 0x05); + tmp = RCBA32(0x0050); // !!! = 0x01200654 + RCBA32(0x0050) = 0x01200654; + tmp = RCBA32(0x0050); // !!! = 0x01200654 + RCBA32(0x0050) = 0x012a0654; + tmp = RCBA32(0x0050); // !!! = 0x012a0654 + tmp = RCBA8(0x1114); // !!! = 0x00 + RCBA8(0x1114) = 0x05; /* * Virtual Channel resources must match settings in DMIBAR! @@ -351,24 +352,25 @@ init_dmi (void) void early_pch_init_native (void) { + volatile u32 tmp; pci_write_config8 (SOUTHBRIDGE, 0xa6, pci_read_config8 (SOUTHBRIDGE, 0xa6) | 2); - write32 (DEFAULT_RCBA + 0x2088, 0x00109000); - read32 (DEFAULT_RCBA + 0x20ac); // !!! = 0x00000000 - write32 (DEFAULT_RCBA + 0x20ac, 0x40000000); - write32 (DEFAULT_RCBA + 0x100c, 0x01110000); - write8 (DEFAULT_RCBA + 0x2340, 0x1b); - read32 (DEFAULT_RCBA + 0x2314); // !!! = 0x0a080000 - write32 (DEFAULT_RCBA + 0x2314, 0x0a280000); - read32 (DEFAULT_RCBA + 0x2310); // !!! = 0xc809605b - write32 (DEFAULT_RCBA + 0x2310, 0xa809605b); - write32 (DEFAULT_RCBA + 0x2324, 0x00854c74); - read8 (DEFAULT_RCBA + 0x0400); // !!! = 0x00 - read32 (DEFAULT_RCBA + 0x2310); // !!! = 0xa809605b - write32 (DEFAULT_RCBA + 0x2310, 0xa809605b); - read32 (DEFAULT_RCBA + 0x2310); // !!! = 0xa809605b - write32 (DEFAULT_RCBA + 0x2310, 0xa809605b); + RCBA32(0x2088) = 0x00109000; + tmp = RCBA32(0x20ac); // !!! = 0x00000000 + RCBA32(0x20ac) = 0x40000000; + RCBA32(0x100c) = 0x01110000; + RCBA8(0x2340) = 0x1b; + tmp = RCBA32(0x2314); // !!! = 0x0a080000 + RCBA32(0x2314) = 0x0a280000; + tmp = RCBA32(0x2310); // !!! = 0xc809605b + RCBA32(0x2310) = 0xa809605b; + RCBA32(0x2324) = 0x00854c74; + tmp = RCBA8(0x0400); // !!! = 0x00 + tmp = RCBA32(0x2310); // !!! = 0xa809605b + RCBA32(0x2310) = 0xa809605b; + tmp = RCBA32(0x2310); // !!! = 0xa809605b + RCBA32(0x2310) = 0xa809605b; write_iobp(0xea007f62, 0x00590133); write_iobp(0xec007f62, 0x00590133); From 6aca7e6bec07c583de18752aa7a8639b64e9bd93 Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Tue, 26 Mar 2019 18:22:36 +0100 Subject: [PATCH 086/331] nb/intel/sandybridge: Move DMI init code Move the DMI initialization code to northbridge folder. Leave southbridge specific settings in bd82x6x folder and call it from northbridge code. Tested on Lenovo T520 (Intel Sandy Bridge). Still boots to OS, no errors visible in dmesg. Change-Id: Ib0b47391f3309f9ab0c3a3a8d525f38f8cca73c0 Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/c/coreboot/+/32073 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- .../intel/sandybridge/Makefile.inc | 1 + src/northbridge/intel/sandybridge/early_dmi.c | 226 ++++++++++++++++++ src/northbridge/intel/sandybridge/raminit.c | 1 + .../intel/sandybridge/sandybridge.h | 1 + src/southbridge/intel/bd82x6x/early_pch.c | 209 +--------------- src/southbridge/intel/bd82x6x/pch.h | 2 + 6 files changed, 236 insertions(+), 204 deletions(-) create mode 100644 src/northbridge/intel/sandybridge/early_dmi.c diff --git a/src/northbridge/intel/sandybridge/Makefile.inc b/src/northbridge/intel/sandybridge/Makefile.inc index cc4ddaf861..ba55466026 100644 --- a/src/northbridge/intel/sandybridge/Makefile.inc +++ b/src/northbridge/intel/sandybridge/Makefile.inc @@ -29,6 +29,7 @@ romstage-y += common.c smm-$(CONFIG_HAVE_SMI_HANDLER) += common.c ifeq ($(CONFIG_USE_NATIVE_RAMINIT),y) +romstage-y += early_dmi.c romstage-y += raminit.c romstage-y += raminit_common.c romstage-y += raminit_sandy.c diff --git a/src/northbridge/intel/sandybridge/early_dmi.c b/src/northbridge/intel/sandybridge/early_dmi.c new file mode 100644 index 0000000000..db49040dc1 --- /dev/null +++ b/src/northbridge/intel/sandybridge/early_dmi.c @@ -0,0 +1,226 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include + +void early_init_dmi(void) +{ + volatile u32 tmp; + int i; + + DMIBAR32(0x0914) |= 0x80000000; + DMIBAR32(0x0934) |= 0x80000000; + + for (i = 0; i < 4; i++) { + DMIBAR32(0x0a00 + (i << 4)) &= 0xf3ffffff; + DMIBAR32(0x0a04 + (i << 4)) |= 0x800; + } + DMIBAR32(0x0c30) = (DMIBAR32(0x0c30) & 0xfffffff) | 0x40000000; + + for (i = 0; i < 2; i++) { + DMIBAR32(0x0904 + (i << 5)) &= 0xfe3fffff; + DMIBAR32(0x090c + (i << 5)) &= 0xfff1ffff; + } + + DMIBAR32(0x090c) &= 0xfe1fffff; + DMIBAR32(0x092c) &= 0xfe1fffff; + + tmp = DMIBAR32(0x0904); // !!! = 0x7a1842ec + DMIBAR32(0x0904) = 0x7a1842ec; + tmp = DMIBAR32(0x090c); // !!! = 0x00000208 + DMIBAR32(0x090c) = 0x00000128; + tmp = DMIBAR32(0x0924); // !!! = 0x7a1842ec + DMIBAR32(0x0924) = 0x7a1842ec; + tmp = DMIBAR32(0x092c); // !!! = 0x00000208 + DMIBAR32(0x092c) = 0x00000128; + tmp = DMIBAR32(0x0700); // !!! = 0x46139008 + DMIBAR32(0x0700) = 0x46139008; + tmp = DMIBAR32(0x0720); // !!! = 0x46139008 + DMIBAR32(0x0720) = 0x46139008; + tmp = DMIBAR32(0x0c04); // !!! = 0x2e680008 + DMIBAR32(0x0c04) = 0x2e680008; + tmp = DMIBAR32(0x0904); // !!! = 0x7a1842ec + DMIBAR32(0x0904) = 0x3a1842ec; + tmp = DMIBAR32(0x0924); // !!! = 0x7a1842ec + DMIBAR32(0x0924) = 0x3a1842ec; + tmp = DMIBAR32(0x0910); // !!! = 0x00006300 + DMIBAR32(0x0910) = 0x00004300; + tmp = DMIBAR32(0x0930); // !!! = 0x00006300 + DMIBAR32(0x0930) = 0x00004300; + tmp = DMIBAR32(0x0a00); // !!! = 0x03042010 + DMIBAR32(0x0a00) = 0x03042018; + tmp = DMIBAR32(0x0a10); // !!! = 0x03042010 + DMIBAR32(0x0a10) = 0x03042018; + tmp = DMIBAR32(0x0a20); // !!! = 0x03042010 + DMIBAR32(0x0a20) = 0x03042018; + tmp = DMIBAR32(0x0a30); // !!! = 0x03042010 + DMIBAR32(0x0a30) = 0x03042018; + tmp = DMIBAR32(0x0c00); // !!! = 0x29700c08 + DMIBAR32(0x0c00) = 0x29700c08; + tmp = DMIBAR32(0x0a04); // !!! = 0x0c0708f0 + DMIBAR32(0x0a04) = 0x0c0718f0; + tmp = DMIBAR32(0x0a14); // !!! = 0x0c0708f0 + DMIBAR32(0x0a14) = 0x0c0718f0; + tmp = DMIBAR32(0x0a24); // !!! = 0x0c0708f0 + DMIBAR32(0x0a24) = 0x0c0718f0; + tmp = DMIBAR32(0x0a34); // !!! = 0x0c0708f0 + DMIBAR32(0x0a34) = 0x0c0718f0; + tmp = DMIBAR32(0x0900); // !!! = 0x50000000 + DMIBAR32(0x0900) = 0x50000000; + tmp = DMIBAR32(0x0920); // !!! = 0x50000000 + DMIBAR32(0x0920) = 0x50000000; + tmp = DMIBAR32(0x0908); // !!! = 0x51ffffff + DMIBAR32(0x0908) = 0x51ffffff; + tmp = DMIBAR32(0x0928); // !!! = 0x51ffffff + DMIBAR32(0x0928) = 0x51ffffff; + tmp = DMIBAR32(0x0a00); // !!! = 0x03042018 + DMIBAR32(0x0a00) = 0x03042018; + tmp = DMIBAR32(0x0a10); // !!! = 0x03042018 + DMIBAR32(0x0a10) = 0x03042018; + tmp = DMIBAR32(0x0a20); // !!! = 0x03042018 + DMIBAR32(0x0a20) = 0x03042018; + tmp = DMIBAR32(0x0a30); // !!! = 0x03042018 + DMIBAR32(0x0a30) = 0x03042018; + tmp = DMIBAR32(0x0700); // !!! = 0x46139008 + DMIBAR32(0x0700) = 0x46139008; + tmp = DMIBAR32(0x0720); // !!! = 0x46139008 + DMIBAR32(0x0720) = 0x46139008; + tmp = DMIBAR32(0x0904); // !!! = 0x3a1842ec + DMIBAR32(0x0904) = 0x3a1846ec; + tmp = DMIBAR32(0x0924); // !!! = 0x3a1842ec + DMIBAR32(0x0924) = 0x3a1846ec; + tmp = DMIBAR32(0x0a00); // !!! = 0x03042018 + DMIBAR32(0x0a00) = 0x03042018; + tmp = DMIBAR32(0x0a10); // !!! = 0x03042018 + DMIBAR32(0x0a10) = 0x03042018; + tmp = DMIBAR32(0x0a20); // !!! = 0x03042018 + DMIBAR32(0x0a20) = 0x03042018; + tmp = DMIBAR32(0x0a30); // !!! = 0x03042018 + DMIBAR32(0x0a30) = 0x03042018; + tmp = DMIBAR32(0x0908); // !!! = 0x51ffffff + DMIBAR32(0x0908) = 0x51ffffff; + tmp = DMIBAR32(0x0928); // !!! = 0x51ffffff + DMIBAR32(0x0928) = 0x51ffffff; + tmp = DMIBAR32(0x0c00); // !!! = 0x29700c08 + DMIBAR32(0x0c00) = 0x29700c08; + tmp = DMIBAR32(0x0c0c); // !!! = 0x16063400 + DMIBAR32(0x0c0c) = 0x00063400; + tmp = DMIBAR32(0x0700); // !!! = 0x46139008 + DMIBAR32(0x0700) = 0x46339008; + tmp = DMIBAR32(0x0720); // !!! = 0x46139008 + DMIBAR32(0x0720) = 0x46339008; + tmp = DMIBAR32(0x0700); // !!! = 0x46339008 + DMIBAR32(0x0700) = 0x45339008; + tmp = DMIBAR32(0x0720); // !!! = 0x46339008 + DMIBAR32(0x0720) = 0x45339008; + tmp = DMIBAR32(0x0700); // !!! = 0x45339008 + DMIBAR32(0x0700) = 0x453b9008; + tmp = DMIBAR32(0x0720); // !!! = 0x45339008 + DMIBAR32(0x0720) = 0x453b9008; + tmp = DMIBAR32(0x0700); // !!! = 0x453b9008 + DMIBAR32(0x0700) = 0x45bb9008; + tmp = DMIBAR32(0x0720); // !!! = 0x453b9008 + DMIBAR32(0x0720) = 0x45bb9008; + tmp = DMIBAR32(0x0700); // !!! = 0x45bb9008 + DMIBAR32(0x0700) = 0x45fb9008; + tmp = DMIBAR32(0x0720); // !!! = 0x45bb9008 + DMIBAR32(0x0720) = 0x45fb9008; + tmp = DMIBAR32(0x0914); // !!! = 0x9021a080 + DMIBAR32(0x0914) = 0x9021a280; + tmp = DMIBAR32(0x0934); // !!! = 0x9021a080 + DMIBAR32(0x0934) = 0x9021a280; + tmp = DMIBAR32(0x0914); // !!! = 0x9021a280 + DMIBAR32(0x0914) = 0x9821a280; + tmp = DMIBAR32(0x0934); // !!! = 0x9021a280 + DMIBAR32(0x0934) = 0x9821a280; + tmp = DMIBAR32(0x0a00); // !!! = 0x03042018 + DMIBAR32(0x0a00) = 0x03242018; + tmp = DMIBAR32(0x0a10); // !!! = 0x03042018 + DMIBAR32(0x0a10) = 0x03242018; + tmp = DMIBAR32(0x0a20); // !!! = 0x03042018 + DMIBAR32(0x0a20) = 0x03242018; + tmp = DMIBAR32(0x0a30); // !!! = 0x03042018 + DMIBAR32(0x0a30) = 0x03242018; + tmp = DMIBAR32(0x0258); // !!! = 0x40000600 + DMIBAR32(0x0258) = 0x60000600; + tmp = DMIBAR32(0x0904); // !!! = 0x3a1846ec + DMIBAR32(0x0904) = 0x2a1846ec; + tmp = DMIBAR32(0x0914); // !!! = 0x9821a280 + DMIBAR32(0x0914) = 0x98200280; + tmp = DMIBAR32(0x0924); // !!! = 0x3a1846ec + DMIBAR32(0x0924) = 0x2a1846ec; + tmp = DMIBAR32(0x0934); // !!! = 0x9821a280 + DMIBAR32(0x0934) = 0x98200280; + tmp = DMIBAR32(0x022c); // !!! = 0x00c26460 + DMIBAR32(0x022c) = 0x00c2403c; + + early_pch_init_native_dmi_pre(); + + /* Write once settings. */ + DMIBAR32(DMILCAP) = (DMIBAR32(DMILCAP) & ~0x3f00f) | + (2 << 0) | // 5GT/s + (2 << 12) | // L0s 128 ns to less than 256 ns + (2 << 15); // L1 2 us to less than 4 us + + DMIBAR8(DMILCTL) |= 0x20; // Retrain link + while (DMIBAR16(DMILSTS) & TXTRN) + ; + + DMIBAR8(DMILCTL) |= 0x20; // Retrain link + while (DMIBAR16(DMILSTS) & TXTRN) + ; + + const u8 w = (DMIBAR16(DMILSTS) >> 4) & 0x1f; + const u16 t = (DMIBAR16(DMILSTS) & 0xf) * 2500; + + printk(BIOS_DEBUG, "DMI: Running at X%x @ %dMT/s\n", w, t); + /* + * Virtual Channel resources must match settings in RCBA! + * + * Channel Vp and Vm are documented in + * "Desktop 4th Generation Intel Core Processor Family, Desktop Intel + * Pentium Processor Family, and Desktop Intel Celeron Processor Family + * Vol. 2" + */ + + /* Channel 0: Enable, Set ID to 0, map TC0 and TC3 and TC4 to VC0. */ + DMIBAR32(DMIVC0RCTL) = (1 << 31) | (0 << 24) | (0x0c << 1) | 1; + /* Channel 1: Enable, Set ID to 1, map TC1 and TC5 to VC1. */ + DMIBAR32(DMIVC1RCTL) = (1 << 31) | (1 << 24) | (0x11 << 1); + /* Channel p: Enable, Set ID to 2, map TC2 and TC6 to VCp */ + DMIBAR32(DMIVCPRCTL) = (1 << 31) | (2 << 24) | (0x22 << 1); + /* Channel m: Enable, Set ID to 0, map TC7 to VCm */ + DMIBAR32(DMIVCMRCTL) = (1 << 31) | (7 << 24) | (0x40 << 1); + + /* Set Extended VC Count (EVCC) to 1 as Channel 1 is active. */ + DMIBAR8(DMIPVCCAP1) |= 1; + + early_pch_init_native_dmi_post(); + + /* + * BIOS Requirement: Check if DMI VC Negotiation was successful. + * Wait for virtual channels negotiation pending. + */ + while (DMIBAR16(DMIVC0RSTS) & VC0NP) + ; + while (DMIBAR16(DMIVC1RSTS) & VC1NP) + ; + while (DMIBAR16(DMIVCPRSTS) & VCPNP) + ; + while (DMIBAR16(DMIVCMRSTS) & VCMNP) + ; +} diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index 2ebeaf0dca..f67d61f973 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -315,6 +315,7 @@ static void init_dram_ddr3(int min_tck, int s3resume) } early_pch_init_native(); + early_init_dmi(); early_thermal_init(); /* try to find timings in MRC cache */ diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h index 77f2ead74e..77165f6931 100644 --- a/src/northbridge/intel/sandybridge/sandybridge.h +++ b/src/northbridge/intel/sandybridge/sandybridge.h @@ -220,6 +220,7 @@ void sandybridge_early_initialization(void); void sandybridge_init_iommu(void); void sandybridge_late_initialization(void); void northbridge_romstage_finalize(int s3resume); +void early_init_dmi(void); #endif /* !__SMM__ */ diff --git a/src/southbridge/intel/bd82x6x/early_pch.c b/src/southbridge/intel/bd82x6x/early_pch.c index 76f1447e8a..e74c3043f0 100644 --- a/src/southbridge/intel/bd82x6x/early_pch.c +++ b/src/southbridge/intel/bd82x6x/early_pch.c @@ -70,158 +70,8 @@ write_iobp(u32 address, u32 val) tmp = RCBA8(IOBPS); // call wait_iobp() instead here? } -static void -init_dmi (void) +void early_pch_init_native_dmi_pre(void) { - volatile u32 tmp; - int i; - - DMIBAR32(0x0914) |= 0x80000000; - DMIBAR32(0x0934) |= 0x80000000; - - for (i = 0; i < 4; i++) { - DMIBAR32(0x0a00 + (i << 4)) &= 0xf3ffffff; - DMIBAR32(0x0a04 + (i << 4)) |= 0x800; - } - DMIBAR32(0x0c30) = (DMIBAR32(0x0c30) & 0xfffffff) | 0x40000000; - - for (i = 0; i < 2; i++) { - DMIBAR32(0x0904 + (i << 5)) &= 0xfe3fffff; - DMIBAR32(0x090c + (i << 5)) &= 0xfff1ffff; - } - - DMIBAR32(0x090c) &= 0xfe1fffff; - DMIBAR32(0x092c) &= 0xfe1fffff; - - tmp = DMIBAR32(0x0904); // !!! = 0x7a1842ec - DMIBAR32(0x0904) = 0x7a1842ec; - tmp = DMIBAR32(0x090c); // !!! = 0x00000208 - DMIBAR32(0x090c) = 0x00000128; - tmp = DMIBAR32(0x0924); // !!! = 0x7a1842ec - DMIBAR32(0x0924) = 0x7a1842ec; - tmp = DMIBAR32(0x092c); // !!! = 0x00000208 - DMIBAR32(0x092c) = 0x00000128; - tmp = DMIBAR32(0x0700); // !!! = 0x46139008 - DMIBAR32(0x0700) = 0x46139008; - tmp = DMIBAR32(0x0720); // !!! = 0x46139008 - DMIBAR32(0x0720) = 0x46139008; - tmp = DMIBAR32(0x0c04); // !!! = 0x2e680008 - DMIBAR32(0x0c04) = 0x2e680008; - tmp = DMIBAR32(0x0904); // !!! = 0x7a1842ec - DMIBAR32(0x0904) = 0x3a1842ec; - tmp = DMIBAR32(0x0924); // !!! = 0x7a1842ec - DMIBAR32(0x0924) = 0x3a1842ec; - tmp = DMIBAR32(0x0910); // !!! = 0x00006300 - DMIBAR32(0x0910) = 0x00004300; - tmp = DMIBAR32(0x0930); // !!! = 0x00006300 - DMIBAR32(0x0930) = 0x00004300; - tmp = DMIBAR32(0x0a00); // !!! = 0x03042010 - DMIBAR32(0x0a00) = 0x03042018; - tmp = DMIBAR32(0x0a10); // !!! = 0x03042010 - DMIBAR32(0x0a10) = 0x03042018; - tmp = DMIBAR32(0x0a20); // !!! = 0x03042010 - DMIBAR32(0x0a20) = 0x03042018; - tmp = DMIBAR32(0x0a30); // !!! = 0x03042010 - DMIBAR32(0x0a30) = 0x03042018; - tmp = DMIBAR32(0x0c00); // !!! = 0x29700c08 - DMIBAR32(0x0c00) = 0x29700c08; - tmp = DMIBAR32(0x0a04); // !!! = 0x0c0708f0 - DMIBAR32(0x0a04) = 0x0c0718f0; - tmp = DMIBAR32(0x0a14); // !!! = 0x0c0708f0 - DMIBAR32(0x0a14) = 0x0c0718f0; - tmp = DMIBAR32(0x0a24); // !!! = 0x0c0708f0 - DMIBAR32(0x0a24) = 0x0c0718f0; - tmp = DMIBAR32(0x0a34); // !!! = 0x0c0708f0 - DMIBAR32(0x0a34) = 0x0c0718f0; - tmp = DMIBAR32(0x0900); // !!! = 0x50000000 - DMIBAR32(0x0900) = 0x50000000; - tmp = DMIBAR32(0x0920); // !!! = 0x50000000 - DMIBAR32(0x0920) = 0x50000000; - tmp = DMIBAR32(0x0908); // !!! = 0x51ffffff - DMIBAR32(0x0908) = 0x51ffffff; - tmp = DMIBAR32(0x0928); // !!! = 0x51ffffff - DMIBAR32(0x0928) = 0x51ffffff; - tmp = DMIBAR32(0x0a00); // !!! = 0x03042018 - DMIBAR32(0x0a00) = 0x03042018; - tmp = DMIBAR32(0x0a10); // !!! = 0x03042018 - DMIBAR32(0x0a10) = 0x03042018; - tmp = DMIBAR32(0x0a20); // !!! = 0x03042018 - DMIBAR32(0x0a20) = 0x03042018; - tmp = DMIBAR32(0x0a30); // !!! = 0x03042018 - DMIBAR32(0x0a30) = 0x03042018; - tmp = DMIBAR32(0x0700); // !!! = 0x46139008 - DMIBAR32(0x0700) = 0x46139008; - tmp = DMIBAR32(0x0720); // !!! = 0x46139008 - DMIBAR32(0x0720) = 0x46139008; - tmp = DMIBAR32(0x0904); // !!! = 0x3a1842ec - DMIBAR32(0x0904) = 0x3a1846ec; - tmp = DMIBAR32(0x0924); // !!! = 0x3a1842ec - DMIBAR32(0x0924) = 0x3a1846ec; - tmp = DMIBAR32(0x0a00); // !!! = 0x03042018 - DMIBAR32(0x0a00) = 0x03042018; - tmp = DMIBAR32(0x0a10); // !!! = 0x03042018 - DMIBAR32(0x0a10) = 0x03042018; - tmp = DMIBAR32(0x0a20); // !!! = 0x03042018 - DMIBAR32(0x0a20) = 0x03042018; - tmp = DMIBAR32(0x0a30); // !!! = 0x03042018 - DMIBAR32(0x0a30) = 0x03042018; - tmp = DMIBAR32(0x0908); // !!! = 0x51ffffff - DMIBAR32(0x0908) = 0x51ffffff; - tmp = DMIBAR32(0x0928); // !!! = 0x51ffffff - DMIBAR32(0x0928) = 0x51ffffff; - tmp = DMIBAR32(0x0c00); // !!! = 0x29700c08 - DMIBAR32(0x0c00) = 0x29700c08; - tmp = DMIBAR32(0x0c0c); // !!! = 0x16063400 - DMIBAR32(0x0c0c) = 0x00063400; - tmp = DMIBAR32(0x0700); // !!! = 0x46139008 - DMIBAR32(0x0700) = 0x46339008; - tmp = DMIBAR32(0x0720); // !!! = 0x46139008 - DMIBAR32(0x0720) = 0x46339008; - tmp = DMIBAR32(0x0700); // !!! = 0x46339008 - DMIBAR32(0x0700) = 0x45339008; - tmp = DMIBAR32(0x0720); // !!! = 0x46339008 - DMIBAR32(0x0720) = 0x45339008; - tmp = DMIBAR32(0x0700); // !!! = 0x45339008 - DMIBAR32(0x0700) = 0x453b9008; - tmp = DMIBAR32(0x0720); // !!! = 0x45339008 - DMIBAR32(0x0720) = 0x453b9008; - tmp = DMIBAR32(0x0700); // !!! = 0x453b9008 - DMIBAR32(0x0700) = 0x45bb9008; - tmp = DMIBAR32(0x0720); // !!! = 0x453b9008 - DMIBAR32(0x0720) = 0x45bb9008; - tmp = DMIBAR32(0x0700); // !!! = 0x45bb9008 - DMIBAR32(0x0700) = 0x45fb9008; - tmp = DMIBAR32(0x0720); // !!! = 0x45bb9008 - DMIBAR32(0x0720) = 0x45fb9008; - tmp = DMIBAR32(0x0914); // !!! = 0x9021a080 - DMIBAR32(0x0914) = 0x9021a280; - tmp = DMIBAR32(0x0934); // !!! = 0x9021a080 - DMIBAR32(0x0934) = 0x9021a280; - tmp = DMIBAR32(0x0914); // !!! = 0x9021a280 - DMIBAR32(0x0914) = 0x9821a280; - tmp = DMIBAR32(0x0934); // !!! = 0x9021a280 - DMIBAR32(0x0934) = 0x9821a280; - tmp = DMIBAR32(0x0a00); // !!! = 0x03042018 - DMIBAR32(0x0a00) = 0x03242018; - tmp = DMIBAR32(0x0a10); // !!! = 0x03042018 - DMIBAR32(0x0a10) = 0x03242018; - tmp = DMIBAR32(0x0a20); // !!! = 0x03042018 - DMIBAR32(0x0a20) = 0x03242018; - tmp = DMIBAR32(0x0a30); // !!! = 0x03042018 - DMIBAR32(0x0a30) = 0x03242018; - tmp = DMIBAR32(0x0258); // !!! = 0x40000600 - DMIBAR32(0x0258) = 0x60000600; - tmp = DMIBAR32(0x0904); // !!! = 0x3a1846ec - DMIBAR32(0x0904) = 0x2a1846ec; - tmp = DMIBAR32(0x0914); // !!! = 0x9821a280 - DMIBAR32(0x0914) = 0x98200280; - tmp = DMIBAR32(0x0924); // !!! = 0x3a1846ec - DMIBAR32(0x0924) = 0x2a1846ec; - tmp = DMIBAR32(0x0934); // !!! = 0x9821a280 - DMIBAR32(0x0934) = 0x98200280; - tmp = DMIBAR32(0x022c); // !!! = 0x00c26460 - DMIBAR32(0x022c) = 0x00c2403c; - /* Link Capabilities Register */ RCBA32(0x21a4) = (RCBA32(0x21a4) & ~0x3fc00) | (3 << 10) | // L0s and L1 entry supported @@ -230,45 +80,11 @@ init_dmi (void) RCBA32(0x2340) = (RCBA32(0x2340) & ~0xff0000) | (0x3a << 16); RCBA8(0x21b0) = (RCBA8(0x21b0) & ~0xf) | 2; +} - /* Write once settings. */ - DMIBAR32(DMILCAP) = (DMIBAR32(DMILCAP) & ~0x3f00f) | - (2 << 0) | // 5GT/s - (2 << 12) | // L0s 128 ns to less than 256 ns - (2 << 15); // L1 2 us to less than 4 us - - DMIBAR8(DMILCTL) |= 0x20; // Retrain link - while (DMIBAR16(DMILSTS) & TXTRN) - ; - - DMIBAR8(DMILCTL) |= 0x20; // Retrain link - while (DMIBAR16(DMILSTS) & TXTRN) - ; - - const u8 w = (DMIBAR16(DMILSTS) >> 4) & 0x1f; - const u16 t = (DMIBAR16(DMILSTS) & 0xf) * 2500; - - printk(BIOS_DEBUG, "DMI: Running at X%x @ %dMT/s\n", w, t); - /* - * Virtual Channel resources must match settings in RCBA! - * - * Channel Vp and Vm are documented in - * "Desktop 4th Generation Intel Core Processor Family, Desktop Intel - * Pentium Processor Family, and Desktop Intel Celeron Processor Family - * Vol. 2" - */ - - /* Channel 0: Enable, Set ID to 0, map TC0 and TC3 and TC4 to VC0. */ - DMIBAR32(DMIVC0RCTL) = (1 << 31) | (0 << 24) | (0x0c << 1) | 1; - /* Channel 1: Enable, Set ID to 1, map TC1 and TC5 to VC1. */ - DMIBAR32(DMIVC1RCTL) = (1 << 31) | (1 << 24) | (0x11 << 1); - /* Channel p: Enable, Set ID to 2, map TC2 and TC6 to VCp */ - DMIBAR32(DMIVCPRCTL) = (1 << 31) | (2 << 24) | (0x22 << 1); - /* Channel m: Enable, Set ID to 0, map TC7 to VCm */ - DMIBAR32(DMIVCMRCTL) = (1 << 31) | (7 << 24) | (0x40 << 1); - - /* Set Extended VC Count (EVCC) to 1 as Channel 1 is active. */ - DMIBAR8(DMIPVCCAP1) |= 1; +void early_pch_init_native_dmi_post(void) +{ + volatile u32 tmp; tmp = RCBA32(0x0050); // !!! = 0x01200654 RCBA32(0x0050) = 0x01200654; @@ -334,19 +150,6 @@ init_dmi (void) ; while (RCBA16(0x2046) & VCNEGPND) ; - - /* - * BIOS Requirement: Check if DMI VC Negotiation was successful. - * Wait for virtual channels negotiation pending. - */ - while (DMIBAR16(DMIVC0RSTS) & VC0NP) - ; - while (DMIBAR16(DMIVC1RSTS) & VC1NP) - ; - while (DMIBAR16(DMIVCPRSTS) & VCPNP) - ; - while (DMIBAR16(DMIVCMRSTS) & VCMNP) - ; } void @@ -433,8 +236,6 @@ early_pch_init_native (void) write_iobp(0xec0007b2, 0x04514b5e); write_iobp(0xec00078c, 0x40000200); write_iobp(0xec000780, 0x02000020); - - init_dmi(); } static void pch_enable_bars(void) diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index fb8238ad4f..faa6822bf2 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -77,6 +77,8 @@ void southbridge_rcba_config(void); void mainboard_rcba_config(void); void early_pch_init_native(void); void early_pch_init(void); +void early_pch_init_native_dmi_pre(void); +void early_pch_init_native_dmi_post(void); struct southbridge_usb_port { From 997207d9a663a74a5b1ed4499fd7b1ce83494d78 Mon Sep 17 00:00:00 2001 From: Alan Green Date: Thu, 16 May 2019 08:52:12 +1000 Subject: [PATCH 087/331] src/include/assert.h: add noreturn attribute to dead_code() Clang does not recognize dead_code() as termination of execution. It gives this message: error: control reaches end of non-void function [-Werror,-Wreturn-type] This change adds an __attribute__((noreturn)) to ensure that clang recognises that this function will terminate execution. This change is more general solution to the problem that was addressed in the specific at https://review.coreboot.org/c/coreboot/+/32798 Signed-off-by: Alan Green Change-Id: I5ba7189559aa01545d5bbe893bced400a3aaabbb Reviewed-on: https://review.coreboot.org/c/coreboot/+/32833 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner --- src/include/assert.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/include/assert.h b/src/include/assert.h index 4575a29e44..e0db0bc05c 100644 --- a/src/include/assert.h +++ b/src/include/assert.h @@ -56,7 +56,8 @@ * bootmode.c:42: undefined reference to `dead_code_assertion_failed_at_line_42' */ #define __dead_code(line) do { \ - extern void dead_code_assertion_failed_at_line_##line(void); \ + extern void dead_code_assertion_failed_at_line_##line(void) \ + __attribute__((noreturn)); \ dead_code_assertion_failed_at_line_##line(); \ } while (0) #define _dead_code(line) __dead_code(line) From f85f2f87465a50ff9572f4e3039c01105494f60a Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Wed, 15 May 2019 19:06:58 +0200 Subject: [PATCH 088/331] soc/qualcomm/sdm845: Fix broken Kconfig This fixes the following changes, which made qualcomm Kconfig appear on all platforms: bd0b51c0be1ec2c9a5f02de3c13108c13941e2c2 7a3e46d767890f502b09771e19decc5033e27079 Use proper Kconfig logic. Change-Id: I0195fd186ac39dd4258fe0781dd6d3d1b1d1679f Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/c/coreboot/+/32805 Reviewed-by: Patrick Georgi Reviewed-by: Julius Werner Tested-by: build bot (Jenkins) --- src/soc/qualcomm/common/Kconfig | 10 ++++++++++ src/soc/qualcomm/sdm845/Kconfig | 1 + 2 files changed, 11 insertions(+) diff --git a/src/soc/qualcomm/common/Kconfig b/src/soc/qualcomm/common/Kconfig index f3d12629fb..8a1f6d62fd 100644 --- a/src/soc/qualcomm/common/Kconfig +++ b/src/soc/qualcomm/common/Kconfig @@ -1,5 +1,15 @@ +config SOC_QUALCOMM_COMMON + bool + default n + help + Selected by platforms that use the common code. + +if SOC_QUALCOMM_COMMON + config QC_SDI_ENABLE bool default n prompt "Debug Build: enable SDI" + +endif diff --git a/src/soc/qualcomm/sdm845/Kconfig b/src/soc/qualcomm/sdm845/Kconfig index ffb95cb4cd..f6268c95ba 100644 --- a/src/soc/qualcomm/sdm845/Kconfig +++ b/src/soc/qualcomm/sdm845/Kconfig @@ -10,6 +10,7 @@ config SOC_QUALCOMM_SDM845 select GENERIC_UDELAY select HAVE_MONOTONIC_TIMER select ARM64_USE_ARCH_TIMER + select SOC_QUALCOMM_COMMON if SOC_QUALCOMM_SDM845 From 9beb52a17ca2dd574e1bfd734b9af88bf57db328 Mon Sep 17 00:00:00 2001 From: Duncan Laurie Date: Fri, 17 May 2019 12:06:37 -0600 Subject: [PATCH 089/331] mb/google/sarien: Set serial number in SMBIOS Set the system serial number from the VPD key "serial_number" and the mainboard serial number from the VPD key "mlb_serial_number". BUG=b:132970635 TEST=check serial number is set in SMBIOS based on VPD, and if there is no VPD key found then it is empty. Change-Id: Ia8f1486dcb1edc968b8eb1e6d989b10c05913aca Signed-off-by: Duncan Laurie Reviewed-on: https://review.coreboot.org/c/coreboot/+/32851 Tested-by: build bot (Jenkins) Reviewed-by: Lijian Zhao Reviewed-by: Furquan Shaikh --- src/mainboard/google/sarien/ramstage.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/src/mainboard/google/sarien/ramstage.c b/src/mainboard/google/sarien/ramstage.c index d8d1c9dbe3..1d220461cf 100644 --- a/src/mainboard/google/sarien/ramstage.c +++ b/src/mainboard/google/sarien/ramstage.c @@ -14,6 +14,7 @@ */ #include +#include #include #include #include @@ -21,6 +22,26 @@ #include #if CONFIG(GENERATE_SMBIOS_TABLES) +#define VPD_KEY_SYSTEM_SERIAL "serial_number" +#define VPD_KEY_MAINBOARD_SERIAL "mlb_serial_number" +#define VPD_SERIAL_LEN 64 + +const char *smbios_system_serial_number(void) +{ + static char serial[VPD_SERIAL_LEN]; + if (vpd_gets(VPD_KEY_SYSTEM_SERIAL, serial, VPD_SERIAL_LEN, VPD_RO)) + return serial; + return ""; +} + +const char *smbios_mainboard_serial_number(void) +{ + static char serial[VPD_SERIAL_LEN]; + if (vpd_gets(VPD_KEY_MAINBOARD_SERIAL, serial, VPD_SERIAL_LEN, VPD_RO)) + return serial; + return ""; +} + /* mainboard silk screen shows DIMM-A and DIMM-B */ void smbios_fill_dimm_locator(const struct dimm_info *dimm, struct smbios_type17 *t) From 46340d076a8205946c841dd637db7fd4ebd31b15 Mon Sep 17 00:00:00 2001 From: Duncan Laurie Date: Fri, 17 May 2019 14:57:31 -0600 Subject: [PATCH 090/331] soc/intel: Fill DIMM serial number from SPD Fill the DIMM serial number field for SMBIOS from the saved SPD data that is returned by FSP. BUG=b:132970635 TEST=This was tested on sarien to ensure that SMBIOS type 17 filled the serial number from the DIMM: Handle 0x000B, DMI type 17, 40 bytes Memory Device Locator: DIMM-A Serial Number: 41164beb Change-Id: I85438bd1d581095ea3482dcf077a7f3389f1cd47 Signed-off-by: Duncan Laurie Reviewed-on: https://review.coreboot.org/c/coreboot/+/32853 Tested-by: build bot (Jenkins) Reviewed-by: Lijian Zhao --- src/soc/intel/apollolake/meminit_util_apl.c | 1 + src/soc/intel/apollolake/meminit_util_glk.c | 1 + src/soc/intel/cannonlake/romstage/romstage.c | 1 + src/soc/intel/common/smbios.c | 5 ++++- src/soc/intel/common/smbios.h | 5 ++++- src/soc/intel/icelake/romstage/romstage.c | 1 + src/soc/intel/skylake/romstage/romstage_fsp20.c | 1 + 7 files changed, 13 insertions(+), 2 deletions(-) diff --git a/src/soc/intel/apollolake/meminit_util_apl.c b/src/soc/intel/apollolake/meminit_util_apl.c index a11c5d8031..b272a99efe 100644 --- a/src/soc/intel/apollolake/meminit_util_apl.c +++ b/src/soc/intel/apollolake/meminit_util_apl.c @@ -90,6 +90,7 @@ void save_lpddr4_dimm_info_part_num(const char *dram_part_num) src_dimm->DimmId, dram_part_num, strlen(dram_part_num), + NULL, /* SPD not available */ memory_info_hob->DataWidth); index++; } diff --git a/src/soc/intel/apollolake/meminit_util_glk.c b/src/soc/intel/apollolake/meminit_util_glk.c index 9bfdf0b8a5..29dcd56767 100644 --- a/src/soc/intel/apollolake/meminit_util_glk.c +++ b/src/soc/intel/apollolake/meminit_util_glk.c @@ -96,6 +96,7 @@ void save_lpddr4_dimm_info_part_num(const char *dram_part_num) src_dimm->DimmId, dram_part_num, strlen(dram_part_num), + src_dimm->SpdSave + SPD_SAVE_OFFSET_SERIAL, memory_info_hob->DataWidth); index++; } diff --git a/src/soc/intel/cannonlake/romstage/romstage.c b/src/soc/intel/cannonlake/romstage/romstage.c index 661c98a466..98d4c006a8 100644 --- a/src/soc/intel/cannonlake/romstage/romstage.c +++ b/src/soc/intel/cannonlake/romstage/romstage.c @@ -111,6 +111,7 @@ static void save_dimm_info(void) src_dimm->DimmId, dram_part_num, dram_part_num_len, + src_dimm->SpdSave + SPD_SAVE_OFFSET_SERIAL, memory_info_hob->DataWidth); index++; } diff --git a/src/soc/intel/common/smbios.c b/src/soc/intel/common/smbios.c index 0b1be8817e..d89e9d5827 100644 --- a/src/soc/intel/common/smbios.c +++ b/src/soc/intel/common/smbios.c @@ -22,7 +22,7 @@ void dimm_info_fill(struct dimm_info *dimm, u32 dimm_capacity, u8 ddr_type, u32 frequency, u8 rank_per_dimm, u8 channel_id, u8 dimm_id, const char *module_part_num, size_t module_part_number_size, - u16 data_width) + const u8 *module_serial_num, u16 data_width) { dimm->dimm_size = dimm_capacity; dimm->ddr_type = ddr_type; @@ -34,6 +34,9 @@ void dimm_info_fill(struct dimm_info *dimm, u32 dimm_capacity, u8 ddr_type, module_part_num, min(sizeof(dimm->module_part_number), module_part_number_size)); + if (module_serial_num) + memcpy(dimm->serial, module_serial_num, + DIMM_INFO_SERIAL_SIZE); switch (data_width) { case 8: dimm->bus_width = MEMORY_BUS_WIDTH_8; diff --git a/src/soc/intel/common/smbios.h b/src/soc/intel/common/smbios.h index 33b5d0df04..5824f5d665 100644 --- a/src/soc/intel/common/smbios.h +++ b/src/soc/intel/common/smbios.h @@ -19,10 +19,13 @@ #include #include +/* Offset info DIMM_INFO SpdSave for start of serial number */ +#define SPD_SAVE_OFFSET_SERIAL 5 + /* Fill the SMBIOS memory information from FSP MEM_INFO_DATA_HOB in CBMEM.*/ void dimm_info_fill(struct dimm_info *dimm, u32 dimm_capacity, u8 ddr_type, u32 frequency, u8 rank_per_dimm, u8 channel_id, u8 dimm_id, const char *module_part_num, size_t module_part_number_size, - u16 data_width); + const u8 *module_serial_num, u16 data_width); #endif /* _COMMON_SMBIOS_H_ */ diff --git a/src/soc/intel/icelake/romstage/romstage.c b/src/soc/intel/icelake/romstage/romstage.c index 1a0c4ffaee..179d99cff6 100644 --- a/src/soc/intel/icelake/romstage/romstage.c +++ b/src/soc/intel/icelake/romstage/romstage.c @@ -96,6 +96,7 @@ static void save_dimm_info(void) src_dimm->DimmId, (const char *)src_dimm->ModulePartNum, sizeof(src_dimm->ModulePartNum), + src_dimm->SpdSave + SPD_SAVE_OFFSET_SERIAL, memory_info_hob->DataWidth); index++; } diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c index 2f75479339..96937d651d 100644 --- a/src/soc/intel/skylake/romstage/romstage_fsp20.c +++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c @@ -126,6 +126,7 @@ static void save_dimm_info(void) src_dimm->DimmId, (const char *)src_dimm->ModulePartNum, sizeof(src_dimm->ModulePartNum), + src_dimm->SpdSave + SPD_SAVE_OFFSET_SERIAL, memory_info_hob->DataWidth); index++; } From 6eaa78144cb7c5b60d3d3d8467b1a0a23ef0db70 Mon Sep 17 00:00:00 2001 From: Lijian Zhao Date: Thu, 16 May 2019 07:32:42 -0700 Subject: [PATCH 091/331] SMBIOS: Fix SPD manufacture ID decoder According to JEP106 from JEDEC, fix manufacture ID of Crucial, Super Talnet and Micron. Signed-off-by: Lijian Zhao Change-Id: I10a268a7f3bde405b95bd3a16d5d121be623c7ed Reviewed-on: https://review.coreboot.org/c/coreboot/+/32837 Tested-by: build bot (Jenkins) Reviewed-by: HAOUAS Elyes Reviewed-by: Duncan Laurie Reviewed-by: Patrick Rudolph --- src/arch/x86/smbios.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/arch/x86/smbios.c b/src/arch/x86/smbios.c index 589f4f0e30..90cd674198 100644 --- a/src/arch/x86/smbios.c +++ b/src/arch/x86/smbios.c @@ -140,7 +140,7 @@ void smbios_fill_dimm_manufacturer_from_id(uint16_t mod_id, struct smbios_type17 *t) { switch (mod_id) { - case 0x2c80: + case 0x9b85: t->manufacturer = smbios_add_string(t->eos, "Crucial"); break; @@ -172,9 +172,9 @@ void smbios_fill_dimm_manufacturer_from_id(uint16_t mod_id, t->manufacturer = smbios_add_string(t->eos, "Hynix/Hyundai"); break; - case 0xb502: + case 0x3486: t->manufacturer = smbios_add_string(t->eos, - "SuperTalent"); + "Super Talent"); break; case 0xcd04: t->manufacturer = smbios_add_string(t->eos, @@ -188,7 +188,7 @@ void smbios_fill_dimm_manufacturer_from_id(uint16_t mod_id, t->manufacturer = smbios_add_string(t->eos, "Elpida"); break; - case 0xff2c: + case 0x2c80: t->manufacturer = smbios_add_string(t->eos, "Micron"); break; From aa2157430f96c658b9629bf69d507f1f161078a7 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Thu, 16 May 2019 14:51:51 -0600 Subject: [PATCH 092/331] vendorcode/google/chromeos: Correct VPD field for MAC passthrough The VPD field name is dock_passthrough, not dock_passthru. Fix it. (I assume there is no length limit) BUG=b:132689337 TEST=check that the feature can now be controlled by the associated enterprise policy Change-Id: Icc2b070313fde74447279cd6ccaa4e3eb6d119ee Signed-off-by: Simon Glass Reviewed-on: https://review.coreboot.org/c/coreboot/+/32839 Reviewed-by: Duncan Laurie Tested-by: build bot (Jenkins) --- src/vendorcode/google/chromeos/acpi/amac.asl | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/src/vendorcode/google/chromeos/acpi/amac.asl b/src/vendorcode/google/chromeos/acpi/amac.asl index c87862f6ff..5a091ddfaa 100644 --- a/src/vendorcode/google/chromeos/acpi/amac.asl +++ b/src/vendorcode/google/chromeos/acpi/amac.asl @@ -16,16 +16,17 @@ /* * The Realtek r8152 driver in the Linux kernel supports a MAC address - * passthru feature which can result in the dock ethernet port using the - * same MAC address that is assigned to the internal NIC. This is done - * by calling an ACPI method at \_SB.AMAC() which returns a formatted - * string (as a buffer) containing the MAC address for the dock to use. + * dock pass-through feature which can result in the dock ethernet port + * using the same MAC address that is assigned to the internal NIC. This + * is done by calling an ACPI method at \_SB.AMAC() which returns a + * formatted string (as a buffer) containing the MAC address for the + * dock to use. * * The Linux kernel implementation can be found at * drivers/net/usb/r8152.c:vendor_mac_passthru_addr_read() * * For Chrome OS, the policy which controls where the dock MAC address - * comes from is written into RW_VPD property "dock_passthru": + * comes from is written into RW_VPD property "dock_passthrough": * * "dock_mac" or empty: Use MAC address from RO_VPD value "dock_mac" * "ethernet_mac0": Use MAC address from RO_VPD value "ethernet_mac0" @@ -39,8 +40,8 @@ Scope (\_SB) /* Format expected by the Linux kernel r8152 driver */ Name (MACA, "_AUXMAC_#XXXXXXXXXXXX#") - /* Get "dock_passthru" value from RW_VPD */ - Local0 = \VPD.VPDF ("RW", "dock_passthru") + /* Get "dock_passthrough" value from RW_VPD */ + Local0 = \VPD.VPDF ("RW", "dock_passthrough") Local1 = Zero Switch (ToString (Local0)) From ef179ab07b73ebe5b7dd33b260402d39daec678b Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Sat, 18 May 2019 13:47:39 -0700 Subject: [PATCH 093/331] timestamp: Update TIMESTAMP_CACHE_IN_BSS to include ENV_POSTCAR With CB:32726 ("lib/timestamp: Make timestamp_sync_cache_to_cbmem() in postcar") timestamps are synced from cache to cbmem in postcar as well. For postcar, the cache lives in BSS just like ramstage. This change updates TIMESTAMP_CACHE_IN_BSS to include both ramstage and postcar and uses this instead of ENV_RAMSTAGE to check for cache location. Ideally, it would be good to get rid of timestamp cache in postcar and ramstage completely since early cbmem init is enabled by default in coreboot and it is guaranteed that cbmem is recovered before timestamps are added in ramstage or postcar. This change is being pushed in as a temporary fix while I make the changes to remove timestamp cache from romstage and postcar completely. BUG=b:132939309 Change-Id: I2d82a96aba954df77c9386b7bd2e2ec0973881be Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/c/coreboot/+/32881 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie Reviewed-by: Subrata Banik --- src/lib/timestamp.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/src/lib/timestamp.c b/src/lib/timestamp.c index 431bce2703..38d0212845 100644 --- a/src/lib/timestamp.c +++ b/src/lib/timestamp.c @@ -47,12 +47,15 @@ DECLARE_OPTIONAL_REGION(timestamp); #define USE_TIMESTAMP_REGION 0 #endif -/* The cache location will sit in BSS when in ramstage. */ -#define TIMESTAMP_CACHE_IN_BSS ENV_RAMSTAGE +/* The cache location will sit in BSS when in ramstage/postcar. */ +#define TIMESTAMP_CACHE_IN_BSS (ENV_RAMSTAGE || ENV_POSTCAR) #define HAS_CBMEM (ENV_ROMSTAGE || ENV_RAMSTAGE || ENV_POSTCAR) -/* Storage of cache entries during ramstage prior to cbmem coming online. */ +/* + * Storage of cache entries during ramstage/postcar prior to cbmem coming + * online. + */ static struct timestamp_cache timestamp_cache; enum { @@ -220,7 +223,7 @@ void timestamp_init(uint64_t base) /* Timestamps could have already been recovered. * In those circumstances honor the cache which sits in BSS * as it has already been initialized. */ - if (ENV_RAMSTAGE && + if (TIMESTAMP_CACHE_IN_BSS && ts_cache->cache_state != TIMESTAMP_CACHE_UNINITIALIZED) return; From fc46ad8a8b99fbfaf5f2e9112abbb26221c1aeff Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Sun, 19 May 2019 11:49:27 +0200 Subject: [PATCH 094/331] src/Kconfig: Move DRAM section to src/lib/Kconfig These Kconfigs are mostly used in src/lib/. Change-Id: I7aa5436c6ff5fef53fde2081e902d793f3581c1e Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/32882 Reviewed-by: Nico Huber Reviewed-by: Furquan Shaikh Reviewed-by: Paul Menzel Tested-by: build bot (Jenkins) --- src/Kconfig | 25 ------------------------- src/lib/Kconfig | 25 +++++++++++++++++++++++++ 2 files changed, 25 insertions(+), 25 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index 2c9dc4ab7f..d30aa99f06 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -1158,31 +1158,6 @@ config GENERIC_GPIO_LIB implies configurability usually found on SoCs, particularly the ability to control internal pull resistors. -config GENERIC_SPD_BIN - bool - help - If enabled, add support for adding spd.hex files in cbfs as spd.bin - and locating it runtime to load SPD. Additionally provide provision to - fetch SPD over SMBus. - -config DIMM_MAX - int - default 4 - help - Total number of memory DIMM slots available on motherboard. - It is multiplication of number of channel to number of DIMMs per - channel - -config DIMM_SPD_SIZE - int - default 256 - help - Total SPD size that will be used for DIMM. - Ex: DDR3 256, DDR4 512. - -config SPD_READ_BY_WORD - bool - config BOOTBLOCK_CUSTOM # To be selected by arch, SoC or mainboard if it does not want use the normal # src/lib/bootblock.c#main() C entry point. diff --git a/src/lib/Kconfig b/src/lib/Kconfig index 2f10c1ccdf..cb1e4a5cc8 100644 --- a/src/lib/Kconfig +++ b/src/lib/Kconfig @@ -30,6 +30,31 @@ config FLATTENED_DEVICE_TREE Selected by features that require to parse and manipulate a flattened devicetree in ramstage. +config GENERIC_SPD_BIN + bool + help + If enabled, add support for adding spd.hex files in cbfs as spd.bin + and locating it runtime to load SPD. Additionally provide provision to + fetch SPD over SMBus. + +config DIMM_MAX + int + default 4 + help + Total number of memory DIMM slots available on motherboard. + It is multiplication of number of channel to number of DIMMs per + channel + +config DIMM_SPD_SIZE + int + default 256 + help + Total SPD size that will be used for DIMM. + Ex: DDR3 256, DDR4 512. + +config SPD_READ_BY_WORD + bool + if RAMSTAGE_LIBHWBASE config HWBASE_DYNAMIC_MMIO From 7576bd7f4299a3af220a7ba3d6c4928812c2982b Mon Sep 17 00:00:00 2001 From: Joel Kitching Date: Fri, 17 May 2019 14:26:01 +0800 Subject: [PATCH 095/331] vboot: save whether developer mode is enabled Save whether or not vboot has selected developer mode as a flag in vboot_working_data. Other coreboot code may access this flag without needing to consult vboot_handoff (which is in the process of being deprecated). BUG=b:124141368, b:124192753 TEST=make clean && make test-abuild BRANCH=none Change-Id: Ieb6ac4937c943aea78ddc762595a05387d2b8114 Signed-off-by: Joel Kitching Reviewed-on: https://review.coreboot.org/c/coreboot/+/32843 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi Reviewed-by: Julius Werner --- src/security/vboot/bootmode.c | 6 ++---- src/security/vboot/misc.h | 2 ++ src/security/vboot/vboot_common.c | 5 ----- src/security/vboot/vboot_common.h | 1 - src/security/vboot/vboot_logic.c | 7 +++++-- 5 files changed, 9 insertions(+), 12 deletions(-) diff --git a/src/security/vboot/bootmode.c b/src/security/vboot/bootmode.c index e6e53b6f33..68749f008b 100644 --- a/src/security/vboot/bootmode.c +++ b/src/security/vboot/bootmode.c @@ -164,10 +164,8 @@ int vboot_recovery_mode_memory_retrain(void) int vboot_developer_mode_enabled(void) { - if (cbmem_possibly_online() && vboot_handoff_check_developer_flag()) - return 1; - - return 0; + return cbmem_possibly_online() && + vboot_get_working_data()->flags & VBOOT_WD_FLAG_DEVELOPER_MODE; } #if CONFIG(VBOOT_NO_BOARD_SUPPORT) diff --git a/src/security/vboot/misc.h b/src/security/vboot/misc.h index 23159c8a0d..acb6dbbd02 100644 --- a/src/security/vboot/misc.h +++ b/src/security/vboot/misc.h @@ -47,6 +47,8 @@ struct vboot_working_data { */ /* vboot requests display initialization from coreboot. */ #define VBOOT_WD_FLAG_DISPLAY_INIT (1 << 0) +/* vboot has selected developer mode. */ +#define VBOOT_WD_FLAG_DEVELOPER_MODE (1 << 1) /* * Source: security/vboot/common.c diff --git a/src/security/vboot/vboot_common.c b/src/security/vboot/vboot_common.c index 14f154c438..ff8e6c896c 100644 --- a/src/security/vboot/vboot_common.c +++ b/src/security/vboot/vboot_common.c @@ -88,11 +88,6 @@ static int vboot_get_handoff_flag(uint32_t flag) return !!(vbho->out_flags & flag); } -int vboot_handoff_check_developer_flag(void) -{ - return vboot_get_handoff_flag(VB_INIT_OUT_ENABLE_DEVELOPER); -} - int vboot_handoff_check_recovery_flag(void) { return vboot_get_handoff_flag(VB_INIT_OUT_ENABLE_RECOVERY); diff --git a/src/security/vboot/vboot_common.h b/src/security/vboot/vboot_common.h index 9a02303d12..a785a8ba34 100644 --- a/src/security/vboot/vboot_common.h +++ b/src/security/vboot/vboot_common.h @@ -62,7 +62,6 @@ int vboot_get_handoff_info(void **addr, uint32_t *size); * Returns value read for other fields */ int vboot_handoff_check_recovery_flag(void); -int vboot_handoff_check_developer_flag(void); int vboot_handoff_get_recovery_reason(void); /* ============================ VBOOT REBOOT ============================== */ diff --git a/src/security/vboot/vboot_logic.c b/src/security/vboot/vboot_logic.c index df34490f98..00347c3f58 100644 --- a/src/security/vboot/vboot_logic.c +++ b/src/security/vboot/vboot_logic.c @@ -364,10 +364,13 @@ void verstage_main(void) vboot_reboot(); } - /* Is vboot declaring that display is available? If so, we should mark - it down, so that the mainboard/SoC knows to initialize display. */ + /* Jot down some information from vboot which may be required later on + in coreboot boot flow. */ if (ctx.flags & VB2_CONTEXT_DISPLAY_INIT) + /* Mainboard/SoC should initialize display. */ vboot_get_working_data()->flags |= VBOOT_WD_FLAG_DISPLAY_INIT; + if (ctx.flags & VB2_CONTEXT_DEVELOPER_MODE) + vboot_get_working_data()->flags |= VBOOT_WD_FLAG_DEVELOPER_MODE; /* Determine which firmware slot to boot (based on NVRAM) */ printk(BIOS_INFO, "Phase 2\n"); From c1b77c13911f0fb5db85bb1d6633e26334a9da71 Mon Sep 17 00:00:00 2001 From: Frans Hendriks Date: Thu, 16 May 2019 14:46:12 +0200 Subject: [PATCH 096/331] security/vboot/vboot_crtm.h: Remove ENV_ for vboot_measure_cbfs_hook() vboot_measure_cbfs_hook() is included when CONFIG_VBOOT_MEASURED_BOOT is enabled, but this function is defined as 0 in vboot_crtm.h using ENV_ Remove ENV_ for vboot_measure_cbfs_hook() function definition. This function is added to bootblock stage also. BUG=NA TEST=Build Google Banon and Google Cyan Change-Id: Ic62c18db09c119dfb85340a6b7f36bfd148aaa45 Signed-off-by: Frans Hendriks Reviewed-on: https://review.coreboot.org/c/coreboot/+/32532 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph Reviewed-by: Furquan Shaikh Reviewed-by: Julius Werner --- src/security/vboot/Makefile.inc | 1 + src/security/vboot/vboot_crtm.h | 3 +-- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/security/vboot/Makefile.inc b/src/security/vboot/Makefile.inc index 6d2096ddb0..9ce724ed54 100644 --- a/src/security/vboot/Makefile.inc +++ b/src/security/vboot/Makefile.inc @@ -70,6 +70,7 @@ ramstage-y += vboot_common.c postcar-y += vboot_common.c ifeq ($(CONFIG_VBOOT_MEASURED_BOOT),y) +bootblock-y += vboot_crtm.c verstage-y += vboot_crtm.c romstage-y += vboot_crtm.c ramstage-y += vboot_crtm.c diff --git a/src/security/vboot/vboot_crtm.h b/src/security/vboot/vboot_crtm.h index e675edbf03..64cb4f2b40 100644 --- a/src/security/vboot/vboot_crtm.h +++ b/src/security/vboot/vboot_crtm.h @@ -46,8 +46,7 @@ */ uint32_t vboot_init_crtm(void); -#if (CONFIG(VBOOT_MEASURED_BOOT) && \ -!ENV_BOOTBLOCK && !ENV_DECOMPRESSOR && !ENV_SMM) +#if CONFIG(VBOOT_MEASURED_BOOT) /* * Measures cbfs data via hook (cbfs) * fh is the cbfs file handle to measure From 232113e7cdc08c4dad7c7914af937717e9c1b144 Mon Sep 17 00:00:00 2001 From: Jamie Chen Date: Tue, 14 May 2019 17:18:52 +0800 Subject: [PATCH 097/331] mb/google/octopus: Override emmc DLL values for Casta New emmc DLL values for Casta BUG=b:122307918 TEST=Boot to OS on 12 systems Change-Id: Ie51885fb9628fa093ecc38f4a3f3157f751ca9ab Signed-off-by: Jamie Chen Reviewed-on: https://review.coreboot.org/c/coreboot/+/32799 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh Reviewed-by: Karthik Ramasubramanian --- .../octopus/variants/casta/overridetree.cb | 41 +++++++++++++++++++ 1 file changed, 41 insertions(+) diff --git a/src/mainboard/google/octopus/variants/casta/overridetree.cb b/src/mainboard/google/octopus/variants/casta/overridetree.cb index dc9c9118af..091b3027f4 100644 --- a/src/mainboard/google/octopus/variants/casta/overridetree.cb +++ b/src/mainboard/google/octopus/variants/casta/overridetree.cb @@ -1,4 +1,45 @@ chip soc/intel/apollolake + # EMMC Tx CMD Delay + # Refer to EDS-Vol2-16.32. + # [14:8] steps of delay for DDR mode, each 125ps. + # [6:0] steps of delay for SDR mode, each 125ps. + register "emmc_tx_cmd_cntl" = "0x00000505" + + # EMMC TX DATA Delay 1 + # Refer to EDS-Vol2-16.33. + # [14:8] steps of delay for HS400, each 125ps. + # [6:0] steps of delay for SDR104/HS200, each 125ps. + register "emmc_tx_data_cntl1" = "0x00000c0d" + + # EMMC TX DATA Delay 2 + # Refer to EDS-Vol2-16.34. + # [30:24] steps of delay for SDR50, each 125ps. + # [22:16] steps of delay for DDR50, each 125ps. + # [14:8] steps of delay for SDR25/HS50, each 125ps. + # [6:0] steps of delay for SDR12, each 125ps. + register "emmc_tx_data_cntl2" = "0x1c2a2a2a" + + # EMMC RX CMD/DATA Delay 1 + # Refer to EDS-Vol2-16.35. + # [30:24] steps of delay for SDR50, each 125ps. + # [22:16] steps of delay for DDR50, each 125ps. + # [14:8] steps of delay for SDR25/HS50, each 125ps. + # [6:0] steps of delay for SDR12, each 125ps. + register "emmc_rx_cmd_data_cntl1" = "0x00181b1b" + + # EMMC RX CMD/DATA Delay 2 + # Refer to EDS-Vol2-16.37. + # [17:16] stands for Rx Clock before Output Buffer + # [14:8] steps of delay for Auto Tuning Mode, each 125ps. + # [6:0] steps of delay for HS200, each 125ps. + register "emmc_rx_cmd_data_cntl2" = "0x0001000f" + + # EMMC Rx Strobe Delay + # Refer to EDS-Vol2-16.36. + # [14:8] Rx Strobe Delay DLL 1(HS400 Mode), each 125ps. + # [6:0] Rx Strobe Delay DLL 2(HS400 Mode), each 125ps. + register "emmc_rx_strobe_cntl" = "0x00000a0a" + # Override USB2 PER PORT register (PORT 4) register "usb2eye[4]" = "{ .Usb20OverrideEn = 1, From 20989630c417b1f0228f4c8eb6af7d715f5bdbcc Mon Sep 17 00:00:00 2001 From: Frans Hendriks Date: Thu, 16 May 2019 11:46:22 +0200 Subject: [PATCH 098/331] soc/intel/braswell/pmutil.c: Use GEN_PMCON1 for RTC status cbmem_find is not available in every stage. Remove usage of cbmem_find() and use GEN_PMCON1 always. BUG=NA TEST=Booting Embedded Linux on Facebook FBG-1701 Change-Id: Id97d57864b3e241e8f046d9b1caebdce199a46b1 Signed-off-by: Frans Hendriks Reviewed-on: https://review.coreboot.org/c/coreboot/+/32724 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/soc/intel/braswell/pmutil.c | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) diff --git a/src/soc/intel/braswell/pmutil.c b/src/soc/intel/braswell/pmutil.c index 271eefed08..4bc621b80e 100644 --- a/src/soc/intel/braswell/pmutil.c +++ b/src/soc/intel/braswell/pmutil.c @@ -16,9 +16,9 @@ #include #include +#include #include #include -#include #include #include #include @@ -364,15 +364,14 @@ int rtc_failure(void) { uint32_t gen_pmcon1; int rtc_fail; - struct chipset_power_state *ps = cbmem_find(CBMEM_ID_POWER_STATE); - if (ps != NULL) - gen_pmcon1 = ps->gen_pmcon1; - else - gen_pmcon1 = read32((u32 *)(PMC_BASE_ADDRESS + GEN_PMCON1)); + /* not usable in ramstage as GEN_PMCON1 gets reset */ + if (ENV_RAMSTAGE) + dead_code(); + + gen_pmcon1 = read32((u32 *)(PMC_BASE_ADDRESS + GEN_PMCON1)); rtc_fail = !!(gen_pmcon1 & RPS); - if (rtc_fail) printk(BIOS_DEBUG, "RTC failure.\n"); From 811a51ac6757b30392385009579f5eddbd9540ab Mon Sep 17 00:00:00 2001 From: Krishna Prasad Bhat Date: Tue, 14 May 2019 14:42:10 +0530 Subject: [PATCH 099/331] mb/google/hatch: Change SD_CD# reset config to PLTRST The system should boot fine to OS on pressing power button before the system enters G3. However, on hatch, we observe that the system waits for few seconds at "Starting kernel" and then resets, with SD card tray inserted and SD_CD# pad reset config set to DEEP. Hence configuring SD_CD# pad reset config to PLTRST. BUG=b:129933011 TEST=Built and verified on hatch. Change-Id: Ic4466b96332f095ff39b28d98607e95fc3d12d6a Signed-off-by: Krishna Prasad Bhat Reviewed-on: https://review.coreboot.org/c/coreboot/+/32782 Tested-by: build bot (Jenkins) Reviewed-by: Subrata Banik Reviewed-by: Paul Fagerburg Reviewed-by: Tim Wawrzynczak Reviewed-by: Furquan Shaikh --- src/mainboard/google/hatch/variants/baseboard/gpio.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/google/hatch/variants/baseboard/gpio.c b/src/mainboard/google/hatch/variants/baseboard/gpio.c index 32526cc74b..0b6607595d 100644 --- a/src/mainboard/google/hatch/variants/baseboard/gpio.c +++ b/src/mainboard/google/hatch/variants/baseboard/gpio.c @@ -339,7 +339,7 @@ static const struct pad_config gpio_table[] = { /* G4 : SD_DATA3 */ PAD_CFG_NF(GPP_G4, NONE, DEEP, NF1), /* G5 : SD_CD# */ - PAD_CFG_NF(GPP_G5, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_G5, NONE, PLTRST, NF1), /* G6 : SD_CLK */ PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1), /* G7 : SD_WP => NC */ From 2e585a12a247e7993c45aa887b9f4c22e63ccbed Mon Sep 17 00:00:00 2001 From: Paul Menzel Date: Mon, 16 Jul 2018 08:39:22 +0200 Subject: [PATCH 100/331] sb/amd/cimx/sb800: Get rid of power button device in coreboot Apply commit d7b88dcb (mb/google/x86-boards: Get rid of power button device in coreboot) to AMD Brazos boards [1]: > As per the ACPI specification, there are two types of power button > devices: > 1. Fixed hardware power button > 2. Generic hardware power button > > Fixed hardware power button is added by the OSPM if POWER_BUTTON flag > is not set in FADT by the BIOS. This device has its programming model > in PM1x_EVT_BLK. All ACPI compliant OSes are expected to add this > power button device by default if the power button FADT flag is not > set. > > On the other hand, generic hardware power button can be used by > platforms if fixed register space cannot be used for the power button > device. In order to support this, power button device object with HID > PNP0C0C is expected to be added to ACPI tables. Additionally, > POWER_BUTTON flag should be set to indicate the presence of control > method for power button. [..] > This change gets rid of the generic hardware power button from all > google mainboards and relies completely on the fixed hardware power > button. The same problem exists with the AMD Hudson devices in coreboot. For AMD Hudson (2) and Yangtze based devices this was removed in commit 44f2fab8 (AMD hudson and yangtze boards: Let mainboard declare power button) [2]. Two devices are detected. $ dmesg | grep Button [ 0.209213] input: Power Button as /devices/LNXSYSTM:00/LNXSYBUS:00/PNP0C0C:00/input/input0 [ 0.209254] ACPI: Power Button [PWRB] [ 0.209332] input: Power Button as /devices/LNXSYSTM:00/LNXPWRBN:00/input/input1 [ 0.209349] ACPI: Power Button [PWRF] $ sudo evtest No device specified, trying to scan all of /dev/input/event* Available devices: /dev/input/event0: Power Button /dev/input/event1: Power Button [..] [1]: https://review.coreboot.org/5546 [2]: https://review.coreboot.org/27272 Change-Id: I0cbecb72f7e1bf3d051d3b7656c6af4d6f43b497 Signed-off-by: Paul Menzel Reviewed-on: https://review.coreboot.org/c/coreboot/+/27496 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi Reviewed-by: Stefan Reinauer --- src/mainboard/amd/inagua/acpi/gpe.asl | 9 --------- src/mainboard/amd/persimmon/acpi/gpe.asl | 9 --------- src/mainboard/amd/south_station/acpi/gpe.asl | 9 --------- src/mainboard/amd/union_station/acpi/gpe.asl | 9 --------- src/mainboard/asrock/e350m1/acpi/gpe.asl | 9 --------- src/mainboard/elmex/pcm205400/acpi/gpe.asl | 9 --------- src/mainboard/gizmosphere/gizmo/acpi/gpe.asl | 9 --------- src/mainboard/jetway/nf81-t56n-lf/acpi/gpe.asl | 9 --------- src/mainboard/pcengines/apu1/acpi/gpe.asl | 9 --------- src/southbridge/amd/cimx/sb800/acpi/fch.asl | 9 --------- 10 files changed, 90 deletions(-) diff --git a/src/mainboard/amd/inagua/acpi/gpe.asl b/src/mainboard/amd/inagua/acpi/gpe.asl index 30e6fdcb3c..3cf38c035a 100644 --- a/src/mainboard/amd/inagua/acpi/gpe.asl +++ b/src/mainboard/amd/inagua/acpi/gpe.asl @@ -15,12 +15,6 @@ Scope(\_GPE) { /* Start Scope GPE */ - /* General event 3 */ - Method(_L03) { - /* DBGO("\\_GPE\\_L00\n") */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - /* Legacy PM event */ Method(_L08) { /* DBGO("\\_GPE\\_L08\n") */ @@ -42,7 +36,6 @@ Scope(\_GPE) { /* Start Scope GPE */ Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } /* ExtEvent0 SCI event */ @@ -63,14 +56,12 @@ Scope(\_GPE) { /* Start Scope GPE */ Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } /* Azalia SCI event */ Method(_L1B) { /* DBGO("\\_GPE\\_L1B\n") */ Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } } /* End Scope GPE */ diff --git a/src/mainboard/amd/persimmon/acpi/gpe.asl b/src/mainboard/amd/persimmon/acpi/gpe.asl index 30e6fdcb3c..3cf38c035a 100644 --- a/src/mainboard/amd/persimmon/acpi/gpe.asl +++ b/src/mainboard/amd/persimmon/acpi/gpe.asl @@ -15,12 +15,6 @@ Scope(\_GPE) { /* Start Scope GPE */ - /* General event 3 */ - Method(_L03) { - /* DBGO("\\_GPE\\_L00\n") */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - /* Legacy PM event */ Method(_L08) { /* DBGO("\\_GPE\\_L08\n") */ @@ -42,7 +36,6 @@ Scope(\_GPE) { /* Start Scope GPE */ Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } /* ExtEvent0 SCI event */ @@ -63,14 +56,12 @@ Scope(\_GPE) { /* Start Scope GPE */ Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } /* Azalia SCI event */ Method(_L1B) { /* DBGO("\\_GPE\\_L1B\n") */ Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } } /* End Scope GPE */ diff --git a/src/mainboard/amd/south_station/acpi/gpe.asl b/src/mainboard/amd/south_station/acpi/gpe.asl index 2f22758712..e7a320eda5 100644 --- a/src/mainboard/amd/south_station/acpi/gpe.asl +++ b/src/mainboard/amd/south_station/acpi/gpe.asl @@ -15,12 +15,6 @@ Scope(\_GPE) { /* Start Scope GPE */ - /* General event 3 */ - Method(_L03) { - /* DBGO("\\_GPE\\_L00\n") */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - /* Legacy PM event */ Method(_L08) { /* DBGO("\\_GPE\\_L08\n") */ @@ -42,7 +36,6 @@ Scope(\_GPE) { /* Start Scope GPE */ Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } /* ExtEvent0 SCI event */ @@ -63,14 +56,12 @@ Scope(\_GPE) { /* Start Scope GPE */ Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } /* Azalia SCI event */ Method(_L1B) { /* DBGO("\\_GPE\\_L1B\n") */ Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } } /* End Scope GPE */ diff --git a/src/mainboard/amd/union_station/acpi/gpe.asl b/src/mainboard/amd/union_station/acpi/gpe.asl index 2f22758712..e7a320eda5 100644 --- a/src/mainboard/amd/union_station/acpi/gpe.asl +++ b/src/mainboard/amd/union_station/acpi/gpe.asl @@ -15,12 +15,6 @@ Scope(\_GPE) { /* Start Scope GPE */ - /* General event 3 */ - Method(_L03) { - /* DBGO("\\_GPE\\_L00\n") */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - /* Legacy PM event */ Method(_L08) { /* DBGO("\\_GPE\\_L08\n") */ @@ -42,7 +36,6 @@ Scope(\_GPE) { /* Start Scope GPE */ Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } /* ExtEvent0 SCI event */ @@ -63,14 +56,12 @@ Scope(\_GPE) { /* Start Scope GPE */ Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } /* Azalia SCI event */ Method(_L1B) { /* DBGO("\\_GPE\\_L1B\n") */ Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } } /* End Scope GPE */ diff --git a/src/mainboard/asrock/e350m1/acpi/gpe.asl b/src/mainboard/asrock/e350m1/acpi/gpe.asl index 0ba8899a60..7994ae31a5 100644 --- a/src/mainboard/asrock/e350m1/acpi/gpe.asl +++ b/src/mainboard/asrock/e350m1/acpi/gpe.asl @@ -15,12 +15,6 @@ Scope(\_GPE) { /* Start Scope GPE */ - /* General event 3 */ - Method(_L03) { - /* DBGO("\\_GPE\\_L00\n") */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - /* Legacy PM event */ Method(_L08) { /* DBGO("\\_GPE\\_L08\n") */ @@ -42,7 +36,6 @@ Scope(\_GPE) { /* Start Scope GPE */ Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } /* ExtEvent0 SCI event */ @@ -63,14 +56,12 @@ Scope(\_GPE) { /* Start Scope GPE */ Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } /* Azalia SCI event */ Method(_L1B) { /* DBGO("\\_GPE\\_L1B\n") */ Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } } /* End Scope GPE */ diff --git a/src/mainboard/elmex/pcm205400/acpi/gpe.asl b/src/mainboard/elmex/pcm205400/acpi/gpe.asl index 30e6fdcb3c..3cf38c035a 100644 --- a/src/mainboard/elmex/pcm205400/acpi/gpe.asl +++ b/src/mainboard/elmex/pcm205400/acpi/gpe.asl @@ -15,12 +15,6 @@ Scope(\_GPE) { /* Start Scope GPE */ - /* General event 3 */ - Method(_L03) { - /* DBGO("\\_GPE\\_L00\n") */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - /* Legacy PM event */ Method(_L08) { /* DBGO("\\_GPE\\_L08\n") */ @@ -42,7 +36,6 @@ Scope(\_GPE) { /* Start Scope GPE */ Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } /* ExtEvent0 SCI event */ @@ -63,14 +56,12 @@ Scope(\_GPE) { /* Start Scope GPE */ Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } /* Azalia SCI event */ Method(_L1B) { /* DBGO("\\_GPE\\_L1B\n") */ Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } } /* End Scope GPE */ diff --git a/src/mainboard/gizmosphere/gizmo/acpi/gpe.asl b/src/mainboard/gizmosphere/gizmo/acpi/gpe.asl index 0b9250d574..e520724101 100644 --- a/src/mainboard/gizmosphere/gizmo/acpi/gpe.asl +++ b/src/mainboard/gizmosphere/gizmo/acpi/gpe.asl @@ -16,12 +16,6 @@ Scope(\_GPE) { /* Start Scope GPE */ - /* General event 3 */ - Method(_L03) { - /* DBGO("\\_GPE\\_L00\n") */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - /* Legacy PM event */ Method(_L08) { /* DBGO("\\_GPE\\_L08\n") */ @@ -43,7 +37,6 @@ Scope(\_GPE) { /* Start Scope GPE */ Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } /* ExtEvent0 SCI event */ @@ -64,14 +57,12 @@ Scope(\_GPE) { /* Start Scope GPE */ Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } /* Azalia SCI event */ Method(_L1B) { /* DBGO("\\_GPE\\_L1B\n") */ Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } } /* End Scope GPE */ diff --git a/src/mainboard/jetway/nf81-t56n-lf/acpi/gpe.asl b/src/mainboard/jetway/nf81-t56n-lf/acpi/gpe.asl index 30e6fdcb3c..3cf38c035a 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/acpi/gpe.asl +++ b/src/mainboard/jetway/nf81-t56n-lf/acpi/gpe.asl @@ -15,12 +15,6 @@ Scope(\_GPE) { /* Start Scope GPE */ - /* General event 3 */ - Method(_L03) { - /* DBGO("\\_GPE\\_L00\n") */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - /* Legacy PM event */ Method(_L08) { /* DBGO("\\_GPE\\_L08\n") */ @@ -42,7 +36,6 @@ Scope(\_GPE) { /* Start Scope GPE */ Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } /* ExtEvent0 SCI event */ @@ -63,14 +56,12 @@ Scope(\_GPE) { /* Start Scope GPE */ Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } /* Azalia SCI event */ Method(_L1B) { /* DBGO("\\_GPE\\_L1B\n") */ Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } } /* End Scope GPE */ diff --git a/src/mainboard/pcengines/apu1/acpi/gpe.asl b/src/mainboard/pcengines/apu1/acpi/gpe.asl index 30e6fdcb3c..3cf38c035a 100644 --- a/src/mainboard/pcengines/apu1/acpi/gpe.asl +++ b/src/mainboard/pcengines/apu1/acpi/gpe.asl @@ -15,12 +15,6 @@ Scope(\_GPE) { /* Start Scope GPE */ - /* General event 3 */ - Method(_L03) { - /* DBGO("\\_GPE\\_L00\n") */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - /* Legacy PM event */ Method(_L08) { /* DBGO("\\_GPE\\_L08\n") */ @@ -42,7 +36,6 @@ Scope(\_GPE) { /* Start Scope GPE */ Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } /* ExtEvent0 SCI event */ @@ -63,14 +56,12 @@ Scope(\_GPE) { /* Start Scope GPE */ Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } /* Azalia SCI event */ Method(_L1B) { /* DBGO("\\_GPE\\_L1B\n") */ Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } } /* End Scope GPE */ diff --git a/src/southbridge/amd/cimx/sb800/acpi/fch.asl b/src/southbridge/amd/cimx/sb800/acpi/fch.asl index 2dc3438c08..b837b4cfc9 100644 --- a/src/southbridge/amd/cimx/sb800/acpi/fch.asl +++ b/src/southbridge/amd/cimx/sb800/acpi/fch.asl @@ -354,12 +354,3 @@ Scope(\){ PWDA, 1, } } - -Scope(\_SB) { - Device(PWRB) { /* Start Power button device */ - Name(_HID, EISAID("PNP0C0C")) - Name(_UID, 0xAA) - Name(_PRW, Package () {3, 0x04}) /* wake from S1-S4 */ - Name(_STA, 0x0B) /* sata is invisible */ - } -} /* End Scope(_SB) */ From 1eeb94ff4acf09959794a2ac1d92e685633aab18 Mon Sep 17 00:00:00 2001 From: Jett Rink Date: Fri, 17 May 2019 07:36:47 -0600 Subject: [PATCH 101/331] util/scripts: update references to cross-repo-cherrypick It appears that the rebase.sh script was renamed to cross-repo-cherrypick and changed directories. Update comments to reflect that change. Change-Id: I863df48378feb48c9b195b1778dcaf1972a4f105 Signed-off-by: Jett Rink Reviewed-on: https://review.coreboot.org/c/coreboot/+/32849 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- util/scripts/cross-repo-cherrypick | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/util/scripts/cross-repo-cherrypick b/util/scripts/cross-repo-cherrypick index 38d4f46fe7..42b05b5131 100755 --- a/util/scripts/cross-repo-cherrypick +++ b/util/scripts/cross-repo-cherrypick @@ -1,6 +1,6 @@ #!/bin/sh -# rebase.sh - rebase helper script +# cross-repo-cherrypick - rebase helper script # # Copyright 2015, 2017 Google Inc. # @@ -22,8 +22,8 @@ BRANCH="origin/master" # git remote add ... # git checkout -b upstreaming # git cherry-pick ... -# git rebase -i --exec util/gitconfig/rebase.sh master -# Alternatively, you can run util/gitconfig/rebase.sh after every +# git rebase -i --exec util/scripts/cross-repo-cherrypick master +# Alternatively, you can run util/scripts/cross-repo-cherrypick after every # individual cherry-pick. # use $0 --cros to add a stub BUG/BRANCH/TEST block From cc8665eacc389318191aa6fe1b04b29580cc84ae Mon Sep 17 00:00:00 2001 From: Keith Short Date: Tue, 14 May 2019 13:38:56 -0600 Subject: [PATCH 102/331] console: Add new function die_with_post_code() Add a new helper function die_with_post_code() that generates a post code and an error string prior to halting the CPU. BUG=b:124401932 BRANCH=sarien TEST=build coreboot for sarien and arcada platforms Change-Id: I87551d60b253dc13ff76f7898c1f112f573a00a2 Signed-off-by: Keith Short Reviewed-on: https://review.coreboot.org/c/coreboot/+/32838 Reviewed-by: Martin Roth Reviewed-by: Aaron Durbin Reviewed-by: Furquan Shaikh Tested-by: build bot (Jenkins) --- src/console/die.c | 7 +++++++ src/include/console/console.h | 1 + 2 files changed, 8 insertions(+) diff --git a/src/console/die.c b/src/console/die.c index 769e65134f..513d1c4097 100644 --- a/src/console/die.c +++ b/src/console/die.c @@ -36,4 +36,11 @@ void __noreturn die(const char *msg) die_notify(); halt(); } + +/* Report a fatal error with a post code */ +void __noreturn die_with_post_code(uint8_t value, const char *msg) +{ + post_code(value); + die(msg); +} #endif diff --git a/src/include/console/console.h b/src/include/console/console.h index ed10807c9a..082ba29be8 100644 --- a/src/include/console/console.h +++ b/src/include/console/console.h @@ -43,6 +43,7 @@ void post_log_clear(void); /* this function is weak and can be overridden by a mainboard function. */ void mainboard_post(u8 value); void __noreturn die(const char *msg); +void __noreturn die_with_post_code(uint8_t value, const char *msg); /* * This function is weak and can be overridden to provide additional From bd96a8430046601dfa2ffbd31636dfd49a41e2ca Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Sat, 18 May 2019 06:57:07 +0200 Subject: [PATCH 103/331] util: Fix typo on plural form of index Change-Id: Idc165f8eafacf3130a29b701bc3610c1a67f69d5 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/32855 Tested-by: build bot (Jenkins) Reviewed-by: Jacob Garber --- util/romcc/romcc.c | 34 ++++++++++++++++---------------- util/romcc/tests/linux_test5.c | 6 +++--- util/romcc/tests/raminit_test6.c | 6 +++--- util/romcc/tests/raminit_test7.c | 6 +++--- util/romcc/tests/simple_test46.c | 4 ++-- util/romcc/tests/simple_test54.c | 6 +++--- util/x86/x86_page_tables.go | 8 ++++---- 7 files changed, 35 insertions(+), 35 deletions(-) diff --git a/util/romcc/romcc.c b/util/romcc/romcc.c index 43be171213..c6507dcad9 100644 --- a/util/romcc/romcc.c +++ b/util/romcc/romcc.c @@ -14111,9 +14111,9 @@ static void compute_closure_variables(struct compile_state *state, struct block *block; struct triple *old_result, *first, *ins; size_t count, idx; - unsigned long used_indicies; + unsigned long used_indices; int i, max_index; -#define MAX_INDICIES (sizeof(used_indicies)*CHAR_BIT) +#define MAX_INDICES (sizeof(used_indices)*CHAR_BIT) #define ID_BITS(X) ((X) & (TRIPLE_FLAG_LOCAL -1)) struct { unsigned id; @@ -14183,7 +14183,7 @@ static void compute_closure_variables(struct compile_state *state, * * To gurantee that stability I lookup the variables * to see where they have been used before and - * I build my final list with the assigned indicies. + * I build my final list with the assigned indices. */ vars = 0; if (enclose_triple(old_result)) { @@ -14202,8 +14202,8 @@ static void compute_closure_variables(struct compile_state *state, ordered_triple_set(&vars, set->member); } - /* Lookup the current indicies of the live varialbe */ - used_indicies = 0; + /* Lookup the current indices of the live varialbe */ + used_indices = 0; max_index = -1; for(set = vars; set ; set = set->next) { struct triple *ins; @@ -14214,14 +14214,14 @@ static void compute_closure_variables(struct compile_state *state, if (index < 0) { continue; } - if (index >= MAX_INDICIES) { + if (index >= MAX_INDICES) { internal_error(state, ins, "index unexpectedly large"); } - if (used_indicies & (1 << index)) { + if (used_indices & (1 << index)) { internal_error(state, ins, "index previously used?"); } - /* Remember which indicies have been used */ - used_indicies |= (1 << index); + /* Remember which indices have been used */ + used_indices |= (1 << index); if (index > max_index) { max_index = index; } @@ -14239,31 +14239,31 @@ static void compute_closure_variables(struct compile_state *state, continue; } /* Find the lowest unused index value */ - for(index = 0; index < MAX_INDICIES; index++) { - if (!(used_indicies & ((uint64_t)1 << index))) { + for(index = 0; index < MAX_INDICES; index++) { + if (!(used_indices & ((uint64_t)1 << index))) { break; } } - if (index == MAX_INDICIES) { - internal_error(state, ins, "no free indicies?"); + if (index == MAX_INDICES) { + internal_error(state, ins, "no free indices?"); } info[ID_BITS(ins->id)].index = index; - /* Remember which indicies have been used */ - used_indicies |= (1 << index); + /* Remember which indices have been used */ + used_indices |= (1 << index); if (index > max_index) { max_index = index; } } /* Build the return list of variables with positions matching - * their indicies. + * their indices. */ *enclose = 0; last_var = enclose; for(i = 0; i <= max_index; i++) { struct triple *var; var = 0; - if (used_indicies & (1 << i)) { + if (used_indices & (1 << i)) { for(set = vars; set; set = set->next) { int index; index = info[ID_BITS(set->member->id)].index; diff --git a/util/romcc/tests/linux_test5.c b/util/romcc/tests/linux_test5.c index cf0df46d54..e94d5d71e7 100644 --- a/util/romcc/tests/linux_test5.c +++ b/util/romcc/tests/linux_test5.c @@ -156,7 +156,7 @@ static const struct mem_param *spd_set_memclk(void) unsigned device; uint32_t value; - static const int latency_indicies[] = { 26, 23, 9 }; + static const int latency_indices[] = { 26, 23, 9 }; static const unsigned char min_cycle_times[] = { [NBCAP_MEMCLK_200MHZ] = 0x50, /* 5ns */ [NBCAP_MEMCLK_166MHZ] = 0x60, /* 6ns */ @@ -224,7 +224,7 @@ static const struct mem_param *spd_set_memclk(void) continue; } debug('D'); - value = smbus_read_byte(device, latency_indicies[index]); + value = smbus_read_byte(device, latency_indices[index]); if (value < 0) continue; debug('E'); @@ -310,7 +310,7 @@ static const struct mem_param *spd_set_memclk(void) } /* Read the min_cycle_time for this latency */ - value = smbus_read_byte(device, latency_indicies[index]); + value = smbus_read_byte(device, latency_indices[index]); /* All is good if the selected clock speed * is what I need or slower. diff --git a/util/romcc/tests/raminit_test6.c b/util/romcc/tests/raminit_test6.c index e99e355e33..8048dcee89 100644 --- a/util/romcc/tests/raminit_test6.c +++ b/util/romcc/tests/raminit_test6.c @@ -1621,7 +1621,7 @@ static const struct mem_param *spd_set_memclk(const struct mem_controller *ctrl) unsigned min_cycle_time, min_latency; int i; uint32_t value; - static const int latency_indicies[] = { 26, 23, 9 }; + static const int latency_indices[] = { 26, 23, 9 }; static const unsigned char min_cycle_times[] = { [0 ] = 0x50, [1 ] = 0x60, @@ -1651,7 +1651,7 @@ static const struct mem_param *spd_set_memclk(const struct mem_controller *ctrl) (!(latencies & (1 << latency)))) { continue; } - value = spd_read_byte(ctrl->channel0[i], latency_indicies[index]); + value = spd_read_byte(ctrl->channel0[i], latency_indices[index]); if (value < 0) { continue; } @@ -1701,7 +1701,7 @@ static const struct mem_param *spd_set_memclk(const struct mem_controller *ctrl) } - value = spd_read_byte(ctrl->channel0[i], latency_indicies[index]); + value = spd_read_byte(ctrl->channel0[i], latency_indices[index]); if (value <= min_cycle_time) { diff --git a/util/romcc/tests/raminit_test7.c b/util/romcc/tests/raminit_test7.c index 184e912fff..c768e86a3c 100644 --- a/util/romcc/tests/raminit_test7.c +++ b/util/romcc/tests/raminit_test7.c @@ -1626,7 +1626,7 @@ static const struct mem_param *spd_set_memclk(const struct mem_controller *ctrl) unsigned min_cycle_time, min_latency; int i; uint32_t value; - static const int latency_indicies[] = { 26, 23, 9 }; + static const int latency_indices[] = { 26, 23, 9 }; static const unsigned char min_cycle_times[] = { [0 ] = 0x50, [1 ] = 0x60, @@ -1656,7 +1656,7 @@ static const struct mem_param *spd_set_memclk(const struct mem_controller *ctrl) (!(latencies & (1 << latency)))) { continue; } - value = spd_read_byte(ctrl->channel0[i], latency_indicies[index]); + value = spd_read_byte(ctrl->channel0[i], latency_indices[index]); if (value < 0) { continue; } @@ -1706,7 +1706,7 @@ static const struct mem_param *spd_set_memclk(const struct mem_controller *ctrl) } - value = spd_read_byte(ctrl->channel0[i], latency_indicies[index]); + value = spd_read_byte(ctrl->channel0[i], latency_indices[index]); if (value <= min_cycle_time) { diff --git a/util/romcc/tests/simple_test46.c b/util/romcc/tests/simple_test46.c index 0b831254a1..2d3764e458 100644 --- a/util/romcc/tests/simple_test46.c +++ b/util/romcc/tests/simple_test46.c @@ -1,6 +1,6 @@ static void spd_set_memclk(void) { - static const int indicies[] = { 26, 23, 9 }; + static const int indices[] = { 26, 23, 9 }; int new_cycle_time, new_latency; int index; unsigned min_cycle_time, min_latency; @@ -15,7 +15,7 @@ static void spd_set_memclk(void) for(index = 0; index < 3; index++) { unsigned long loops; unsigned long address; - address = indicies[index]; + address = indices[index]; loops = 1000000; do { } while(--loops); diff --git a/util/romcc/tests/simple_test54.c b/util/romcc/tests/simple_test54.c index 37dce795c5..b7dee66bcf 100644 --- a/util/romcc/tests/simple_test54.c +++ b/util/romcc/tests/simple_test54.c @@ -569,7 +569,7 @@ static const struct mem_param *spd_set_memclk(void) unsigned device; uint32_t value; - static const int latency_indicies[] = { 26, 23, 9 }; + static const int latency_indices[] = { 26, 23, 9 }; static const unsigned char min_cycle_times[] = { [NBCAP_MEMCLK_200MHZ] = 0x50, /* 5ns */ [NBCAP_MEMCLK_166MHZ] = 0x60, /* 6ns */ @@ -637,7 +637,7 @@ static const struct mem_param *spd_set_memclk(void) continue; } debug('D'); - value = smbus_read_byte(device, latency_indicies[index]); + value = smbus_read_byte(device, latency_indices[index]); if (value < 0) continue; debug('E'); @@ -723,7 +723,7 @@ static const struct mem_param *spd_set_memclk(void) } /* Read the min_cycle_time for this latency */ - value = smbus_read_byte(device, latency_indicies[index]); + value = smbus_read_byte(device, latency_indices[index]); /* All is good if the selected clock speed * is what I need or slower. diff --git a/util/x86/x86_page_tables.go b/util/x86/x86_page_tables.go index 2dc0ed36ff..e477b54c5e 100644 --- a/util/x86/x86_page_tables.go +++ b/util/x86/x86_page_tables.go @@ -223,7 +223,7 @@ func (cw *cWriter) WritePageEntry(data interface{}) error { return nil } -// This map represents what the IA32_PAT MSR should be at runtime. The indicies +// This map represents what the IA32_PAT MSR should be at runtime. The indices // are what the linux kernel uses. Reserved entries are not used. // 0 WB : _PAGE_CACHE_MODE_WB // 1 WC : _PAGE_CACHE_MODE_WC @@ -523,11 +523,11 @@ func newAddrSpace(mergeFunc addrRangeMerge, metatdataBaseAddr uint64) *addressSp return as } -func (as *addressSpace) deleteEntries(indicies []int) { +func (as *addressSpace) deleteEntries(indices []int) { // deletions need to be processed in reverse order so as not // delete the wrong entries - sort.Sort(sort.Reverse(sort.IntSlice(indicies))) - for _, i := range indicies { + sort.Sort(sort.Reverse(sort.IntSlice(indices))) + for _, i := range indices { as.ranges = append(as.ranges[:i], as.ranges[i+1:]...) } } From 686b539949d9a07d3b6522c075ccae3f15a6121a Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Sat, 18 May 2019 13:36:03 +0200 Subject: [PATCH 104/331] i945: Add device identification D2:F1 Add device identification D2:F1 for desktop version. (see Intel 945G/945GZ/945GC/945P/945PL Express Chipset Family datasheet page 192) Change-Id: Ie060644d635a7031ee6f55420d63751192481091 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/32877 Tested-by: build bot (Jenkins) Reviewed-by: Lijian Zhao --- src/northbridge/intel/i945/gma.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c index 9c4f410d02..1d20533a48 100644 --- a/src/northbridge/intel/i945/gma.c +++ b/src/northbridge/intel/i945/gma.c @@ -858,6 +858,7 @@ static const unsigned short i945_gma_func0_ids[] = { }; static const unsigned short i945_gma_func1_ids[] = { + 0x2776, /* Desktop 82945G/GZ/GC */ 0x27a6, /* Mobile 945GM/GMS/GME Express Integrated Graphics Controller */ 0 }; From 8ef6732b94148a39f8203cb3b4cf3388dc103199 Mon Sep 17 00:00:00 2001 From: Keith Short Date: Fri, 10 May 2019 11:49:24 -0600 Subject: [PATCH 105/331] ec/google/wilco: Add support for KB_ERR_CODE to Wilco EC Adds support for the KB_ERR_CODE command on the Wilco EC. This command is used to drive diagnostic LEDs on the platform after a failed boot. This change also adds the Wilco EC mailbox command support to bootblock and verstage so that those stages can use the KB_ERR_CODE command. BUG=b:124401932 BRANCH=sarien TEST=build coreboot for sarien and arcada platforms Change-Id: I96d17baf57694e4e01c676d80c606f67054cd0c3 Signed-off-by: Keith Short Reviewed-on: https://review.coreboot.org/c/coreboot/+/32776 Reviewed-by: Duncan Laurie Tested-by: build bot (Jenkins) --- src/ec/google/wilco/Makefile.inc | 3 ++- src/ec/google/wilco/commands.c | 6 ++++++ src/ec/google/wilco/commands.h | 21 +++++++++++++++++++++ 3 files changed, 29 insertions(+), 1 deletion(-) diff --git a/src/ec/google/wilco/Makefile.inc b/src/ec/google/wilco/Makefile.inc index 3a7790c097..f17869ecbc 100644 --- a/src/ec/google/wilco/Makefile.inc +++ b/src/ec/google/wilco/Makefile.inc @@ -1,6 +1,7 @@ ifeq ($(CONFIG_EC_GOOGLE_WILCO),y) -bootblock-y += bootblock.c +bootblock-y += bootblock.c commands.c mailbox.c +verstage-y += commands.c mailbox.c romstage-y += commands.c mailbox.c romstage.c boardid.c ramstage-y += chip.c commands.c mailbox.c boardid.c smm-y += commands.c mailbox.c smihandler.c boardid.c diff --git a/src/ec/google/wilco/commands.c b/src/ec/google/wilco/commands.c index d0d572d569..a97a28ecce 100644 --- a/src/ec/google/wilco/commands.c +++ b/src/ec/google/wilco/commands.c @@ -181,3 +181,9 @@ int wilco_ec_signed_fw(void) CONFIG_EC_BASE_ACPI_DATA); return !!ec_read(EC_RAM_SIGNED_FW); } + +int wilco_ec_err_code(enum ec_err_code err_code) +{ + return wilco_ec_mailbox(WILCO_EC_MSG_DEFAULT, KB_ERR_CODE, + &err_code, 1, NULL, 0); +} diff --git a/src/ec/google/wilco/commands.h b/src/ec/google/wilco/commands.h index 3077eee578..fafb7fd8ba 100644 --- a/src/ec/google/wilco/commands.h +++ b/src/ec/google/wilco/commands.h @@ -50,6 +50,8 @@ enum { KB_SLP_EN = 0x64, /* Inform the EC about BIOS boot progress */ KB_BIOS_PROGRESS = 0xc2, + /* Inform the EC that a fatal error occurred */ + KB_ERR_CODE = 0x7b, }; enum ec_ram_addr { @@ -86,6 +88,12 @@ enum ec_camera { CAMERA_OFF }; +enum ec_err_code { + DLED_MEMORY = 0x03, + DLED_PANEL = 0x10, + DLED_ROM = 0x19, +}; + /** * wilco_ec_radio_control() - Control wireless radios. * @ec_radio: Wireless radio type. @@ -310,4 +318,17 @@ enum ec_acpi_wake_events { */ int wilco_ec_signed_fw(void); +/** + * wilco_ec_err_code + * + * Send an error code to the EC to indicate a failed boot. The EC flashes the + * platform LED amber and white to provide user indication of the failure type. + * + * @err_code: Error code to send to the EC + * + * Returns 0 if EC command was successful + * Returns -1 if EC command failed + */ +int wilco_ec_err_code(enum ec_err_code err_code); + #endif /* EC_GOOGLE_WILCO_COMMANDS_H */ From abdc9bc8c8605f2865b7a9cc956cbcc4402c1c43 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Tue, 14 May 2019 17:31:19 +0530 Subject: [PATCH 106/331] soc/intel/common/block/gpio: Add gpio_pm_configure() function This patch adds new function to perform gpio power management programming as per EDS. BUG=b:130764684 TEST=Able to build and boot from fixed media on ICL and CML. Change-Id: I816a70ad92595f013740a235a9799912ad51665e Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/32788 Tested-by: build bot (Jenkins) Reviewed-by: Paul Fagerburg Reviewed-by: Tim Wawrzynczak Reviewed-by: Furquan Shaikh --- src/soc/intel/common/block/gpio/gpio.c | 18 +++++++++++++++++ .../common/block/include/intelblocks/gpio.h | 20 +++++++++++++++++++ 2 files changed, 38 insertions(+) diff --git a/src/soc/intel/common/block/gpio/gpio.c b/src/soc/intel/common/block/gpio/gpio.c index 3a0594cba1..d37601ce3b 100644 --- a/src/soc/intel/common/block/gpio/gpio.c +++ b/src/soc/intel/common/block/gpio/gpio.c @@ -609,3 +609,21 @@ void gpi_clear_int_cfg(void) } } } + +/* The function performs GPIO Power Management programming. */ +void gpio_pm_configure(const uint8_t *misccfg_pm_values, size_t num) +{ + int i; + size_t gpio_communities; + uint8_t misccfg_pm_mask = MISCCFG_ENABLE_GPIO_PM_CONFIG; + const struct pad_community *comm; + + comm = soc_gpio_get_community(&gpio_communities); + if (gpio_communities != num) + die("Incorrect GPIO community count!\n"); + + /* Program GPIO_MISCCFG */ + for (i = 0; i < num; i++, comm++) + pcr_rmw8(comm->port, GPIO_MISCCFG, + misccfg_pm_mask, misccfg_pm_values[i]); +} diff --git a/src/soc/intel/common/block/include/intelblocks/gpio.h b/src/soc/intel/common/block/include/intelblocks/gpio.h index 417929329f..a2cccc7cd2 100644 --- a/src/soc/intel/common/block/include/intelblocks/gpio.h +++ b/src/soc/intel/common/block/include/intelblocks/gpio.h @@ -23,6 +23,23 @@ #ifndef __ACPI__ #include +/* GPIO community IOSF sideband clock gating */ +#define MISCCFG_GPSIDEDPCGEN (1 << 5) +/* GPIO community RCOMP clock gating */ +#define MISCCFG_GPRCOMPCDLCGEN (1 << 4) +/* GPIO community RTC clock gating */ +#define MISCCFG_GPRTCDLCGEN (1 << 3) +/* GFX controller clock gating */ +#define MISCCFG_GSXSLCGEN (1 << 2) +/* GPIO community partition clock gating */ +#define MISCCFG_GPDPCGEN (1 << 1) +/* GPIO community local clock gating */ +#define MISCCFG_GPDLCGEN (1 << 0) +/* Enable GPIO community power management configuration */ +#define MISCCFG_ENABLE_GPIO_PM_CONFIG (MISCCFG_GPSIDEDPCGEN | \ + MISCCFG_GPRCOMPCDLCGEN | MISCCFG_GPRTCDLCGEN | MISCCFG_GSXSLCGEN \ + | MISCCFG_GPDPCGEN | MISCCFG_GPDLCGEN) + /* * GPIO numbers may not be contiguous and instead will have a different * starting pin number for each pad group. @@ -215,5 +232,8 @@ uint32_t soc_gpio_pad_config_fixup(const struct pad_config *cfg, */ void gpi_clear_int_cfg(void); +/* The function performs GPIO Power Management programming. */ +void gpio_pm_configure(const uint8_t *misccfg_pm_values, size_t num); + #endif #endif /* _SOC_INTELBLOCKS_GPIO_H_ */ From dd5fa024260bf6fd19c077d640c34e27b742115b Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Wed, 15 May 2019 21:04:37 +0530 Subject: [PATCH 107/331] soc/intel/icelake: Make use of gpio_pm_configure() Provide option in chip.h to set dynamic local clock gating setting. BUG=b:130764684 TEST=Able to build and boot ICL. Change-Id: Ic30a490aadb8cc9c05a19a05533ab0196c69b7f1 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/32789 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/soc/intel/icelake/chip.c | 23 +++++++++++++++++++ src/soc/intel/icelake/chip.h | 20 ++++++++++++++++ src/soc/intel/icelake/gpio.c | 21 ++++++++++++----- .../intel/icelake/include/soc/gpio_soc_defs.h | 8 +++++++ 4 files changed, 66 insertions(+), 6 deletions(-) diff --git a/src/soc/intel/icelake/chip.c b/src/soc/intel/icelake/chip.c index 11d14de084..2616db1768 100644 --- a/src/soc/intel/icelake/chip.c +++ b/src/soc/intel/icelake/chip.c @@ -103,6 +103,27 @@ const char *soc_acpi_name(const struct device *dev) } #endif +/* SoC rotine to fill GPIO PM mask and value for GPIO_MISCCFG register */ +static void soc_fill_gpio_pm_configuration(void) +{ + uint8_t value[TOTAL_GPIO_COMM]; + const struct device *dev; + dev = pcidev_on_root(SA_DEV_SLOT_ROOT, 0); + if (!dev || !dev->chip_info) + return; + + const config_t *config = dev->chip_info; + + if (config->gpio_override_pm) + memcpy(value, config->gpio_pm, sizeof(uint8_t) * + TOTAL_GPIO_COMM); + else + memset(value, MISCCFG_ENABLE_GPIO_PM_CONFIG, sizeof(uint8_t) * + TOTAL_GPIO_COMM); + + gpio_pm_configure(value, TOTAL_GPIO_COMM); +} + void soc_init_pre_device(void *chip_info) { /* Snapshot the current GPIO IRQ polarities. FSP is setting a @@ -117,6 +138,8 @@ void soc_init_pre_device(void *chip_info) /* Restore GPIO IRQ polarities back to previous settings. */ itss_restore_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END); + + soc_fill_gpio_pm_configuration(); } static void pci_domain_set_resources(struct device *dev) diff --git a/src/soc/intel/icelake/chip.h b/src/soc/intel/icelake/chip.h index 3e2b78acd6..77611262a3 100644 --- a/src/soc/intel/icelake/chip.h +++ b/src/soc/intel/icelake/chip.h @@ -18,6 +18,7 @@ #include #include +#include #include #include #include @@ -263,6 +264,25 @@ struct soc_intel_icelake_config { FORCE_ENABLE, FORCE_DISABLE, } CnviBtAudioOffload; + + /* + * Override GPIO PM configuration: + * 0: Use FSP default GPIO PM program, + * 1: coreboot to override GPIO PM program + */ + uint8_t gpio_override_pm; + + /* + * GPIO PM configuration: 0 to disable, 1 to enable power gating + * Bit 6-7: Reserved + * Bit 5: MISCCFG_GPSIDEDPCGEN + * Bit 4: MISCCFG_GPRCOMPCDLCGEN + * Bit 3: MISCCFG_GPRTCDLCGEN + * Bit 2: MISCCFG_GSXLCGEN + * Bit 1: MISCCFG_GPDPCGEN + * Bit 0: MISCCFG_GPDLCGEN + */ + uint8_t gpio_pm[TOTAL_GPIO_COMM]; }; typedef struct soc_intel_icelake_config config_t; diff --git a/src/soc/intel/icelake/gpio.c b/src/soc/intel/icelake/gpio.c index b1c46abe29..96c5c838ad 100644 --- a/src/soc/intel/icelake/gpio.c +++ b/src/soc/intel/icelake/gpio.c @@ -76,8 +76,9 @@ static const struct pad_group icl_community5_groups[] = { INTEL_GPP_BASE(GPP_C0, GPP_S0, GPP_S7, 320), /* GPP_S */ }; -static const struct pad_community icl_communities[] = { - { /* GPP G, B, A */ +static const struct pad_community icl_communities[TOTAL_GPIO_COMM] = { + /* GPP G, B, A */ + [COMM_0] = { .port = PID_GPIOCOM0, .first_pad = GPP_G0, .last_pad = GPP_A23, @@ -95,7 +96,9 @@ static const struct pad_community icl_communities[] = { .num_reset_vals = ARRAY_SIZE(rst_map_com0), .groups = icl_community0_groups, .num_groups = ARRAY_SIZE(icl_community0_groups), - }, { /* GPP H, D, F */ + }, + /* GPP H, D, F */ + [COMM_1] = { .port = PID_GPIOCOM1, .first_pad = GPP_H0, .last_pad = GPP_F19, @@ -113,7 +116,9 @@ static const struct pad_community icl_communities[] = { .num_reset_vals = ARRAY_SIZE(rst_map), .groups = icl_community1_groups, .num_groups = ARRAY_SIZE(icl_community1_groups), - }, { /* GPD */ + }, + /* GPD */ + [COMM_2] = { .port = PID_GPIOCOM2, .first_pad = GPD0, .last_pad = GPD11, @@ -131,7 +136,9 @@ static const struct pad_community icl_communities[] = { .num_reset_vals = ARRAY_SIZE(rst_map), .groups = icl_community2_groups, .num_groups = ARRAY_SIZE(icl_community2_groups), - }, { /* GPP C, E */ + }, + /* GPP C, E */ + [COMM_3] = { .port = PID_GPIOCOM4, .first_pad = GPP_C0, .last_pad = GPP_E23, @@ -149,7 +156,9 @@ static const struct pad_community icl_communities[] = { .num_reset_vals = ARRAY_SIZE(rst_map), .groups = icl_community4_groups, .num_groups = ARRAY_SIZE(icl_community4_groups), - }, { /* GPP R, S */ + }, + /* GPP R, S */ + [COMM_4] = { .port = PID_GPIOCOM5, .first_pad = GPP_R0, .last_pad = GPP_S7, diff --git a/src/soc/intel/icelake/include/soc/gpio_soc_defs.h b/src/soc/intel/icelake/include/soc/gpio_soc_defs.h index 5a27a15bd6..887e378e07 100644 --- a/src/soc/intel/icelake/include/soc/gpio_soc_defs.h +++ b/src/soc/intel/icelake/include/soc/gpio_soc_defs.h @@ -281,4 +281,12 @@ #define NUM_GPIO_COM5_PADS (GPP_S7 - GPP_R0 + 1) #define TOTAL_PADS 205 + +#define COMM_0 0 +#define COMM_1 1 +#define COMM_2 2 +#define COMM_3 3 +#define COMM_4 4 +#define TOTAL_GPIO_COMM 5 + #endif From 76a8f9e29f3cb6aa2e971957eec7fc05abaf50b8 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Wed, 15 May 2019 21:23:18 +0530 Subject: [PATCH 108/331] soc/intel/cannonlake: Make use of gpio_pm_configure() Provide option in chip.h to set dynamic local clock gating setting. BUG=b:130764684 TEST=Able to build and boot CML. Change-Id: Iec60076398b745e11d5025e4d7a5c35374d918a4 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/32790 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/soc/intel/cannonlake/chip.c | 23 +++++++++++++++++++ src/soc/intel/cannonlake/chip.h | 19 +++++++++++++++ src/soc/intel/cannonlake/gpio.c | 21 ++++++++++++----- src/soc/intel/cannonlake/gpio_cnp_h.c | 19 +++++++++++---- .../cannonlake/include/soc/gpio_soc_defs.h | 8 +++++++ .../include/soc/gpio_soc_defs_cnp_h.h | 7 ++++++ 6 files changed, 86 insertions(+), 11 deletions(-) diff --git a/src/soc/intel/cannonlake/chip.c b/src/soc/intel/cannonlake/chip.c index 1bd34c34e0..faddbd5a24 100644 --- a/src/soc/intel/cannonlake/chip.c +++ b/src/soc/intel/cannonlake/chip.c @@ -166,6 +166,27 @@ void cnl_configure_pads(const struct pad_config *cfg, size_t num_pads) gpio_configure_pads(cfg, num_pads); } +/* SoC rotine to fill GPIO PM mask and value for GPIO_MISCCFG register */ +static void soc_fill_gpio_pm_configuration(void) +{ + uint8_t value[TOTAL_GPIO_COMM]; + const struct device *dev; + dev = pcidev_on_root(SA_DEV_SLOT_ROOT, 0); + if (!dev || !dev->chip_info) + return; + + const config_t *config = dev->chip_info; + + if (config->gpio_override_pm) + memcpy(value, config->gpio_pm, sizeof(uint8_t) * + TOTAL_GPIO_COMM); + else + memset(value, MISCCFG_ENABLE_GPIO_PM_CONFIG, sizeof(uint8_t) * + TOTAL_GPIO_COMM); + + gpio_pm_configure(value, TOTAL_GPIO_COMM); +} + void soc_init_pre_device(void *chip_info) { /* Perform silicon specific init. */ @@ -176,6 +197,8 @@ void soc_init_pre_device(void *chip_info) /* TODO(furquan): Get rid of this workaround once FSP is fixed. */ cnl_configure_pads(NULL, 0); + + soc_fill_gpio_pm_configuration(); } static void pci_domain_set_resources(struct device *dev) diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index 2b2a51f6a0..0d51c1ca5c 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -20,6 +20,7 @@ #include #include +#include #include #include #include @@ -402,6 +403,24 @@ struct soc_intel_cannonlake_config { /* Enable GBE wakeup */ uint8_t LanWakeFromDeepSx; uint8_t WolEnableOverride; + + /* + * Override GPIO PM configuration: + * 0: Use FSP default GPIO PM program, + * 1: coreboot to override GPIO PM program + */ + uint8_t gpio_override_pm; + /* + * GPIO PM configuration: 0 to disable, 1 to enable power gating + * Bit 6-7: Reserved + * Bit 5: MISCCFG_GPSIDEDPCGEN + * Bit 4: MISCCFG_GPRCOMPCDLCGEN + * Bit 3: MISCCFG_GPRTCDLCGEN + * Bit 2: MISCCFG_GSXLCGEN + * Bit 1: MISCCFG_GPDPCGEN + * Bit 0: MISCCFG_GPDLCGEN + */ + uint8_t gpio_pm[TOTAL_GPIO_COMM]; }; typedef struct soc_intel_cannonlake_config config_t; diff --git a/src/soc/intel/cannonlake/gpio.c b/src/soc/intel/cannonlake/gpio.c index dd514643d7..4036fdc073 100644 --- a/src/soc/intel/cannonlake/gpio.c +++ b/src/soc/intel/cannonlake/gpio.c @@ -77,8 +77,9 @@ static const struct pad_group cnl_community4_groups[] = { INTEL_GPP(GPP_C0, GPIO_RSVD_22, GPIO_RSVD_27), /* HVMOS */ }; -static const struct pad_community cnl_communities[] = { - { /* GPP A, B, G, SPI */ +static const struct pad_community cnl_communities[TOTAL_GPIO_COMM] = { + /* GPP A, B, G, SPI */ + [COMM_0] = { .port = PID_GPIOCOM0, .first_pad = GPP_A0, .last_pad = GPIO_RSVD_11, @@ -96,7 +97,9 @@ static const struct pad_community cnl_communities[] = { .num_reset_vals = ARRAY_SIZE(rst_map_com0), .groups = cnl_community0_groups, .num_groups = ARRAY_SIZE(cnl_community0_groups), - }, { /* GPP D, F, H, VGPIO */ + }, + /* GPP D, F, H, VGPIO */ + [COMM_1] = { .port = PID_GPIOCOM1, .first_pad = GPP_D0, .last_pad = vSD3_CD_B, @@ -114,7 +117,9 @@ static const struct pad_community cnl_communities[] = { .num_reset_vals = ARRAY_SIZE(rst_map), .groups = cnl_community1_groups, .num_groups = ARRAY_SIZE(cnl_community1_groups), - }, { /* GPD */ + }, + /* GPD */ + [COMM_2] = { .port = PID_GPIOCOM2, .first_pad = GPD0, .last_pad = GPD11, @@ -132,7 +137,9 @@ static const struct pad_community cnl_communities[] = { .num_reset_vals = ARRAY_SIZE(rst_map), .groups = cnl_community2_groups, .num_groups = ARRAY_SIZE(cnl_community2_groups), - }, { /* AZA, CPU */ + }, + /* AZA, CPU */ + [COMM_3] = { .port = PID_GPIOCOM3, .first_pad = HDA_BCLK, .last_pad = GPIO_RSVD_38, @@ -150,7 +157,9 @@ static const struct pad_community cnl_communities[] = { .num_reset_vals = ARRAY_SIZE(rst_map), .groups = cnl_community3_groups, .num_groups = ARRAY_SIZE(cnl_community3_groups), - }, { /* GPP C, E, JTAG, HVMOS */ + }, + /* GPP C, E, JTAG, HVMOS */ + [COMM_4] = { .port = PID_GPIOCOM4, .first_pad = GPP_C0, .last_pad = GPIO_RSVD_27, diff --git a/src/soc/intel/cannonlake/gpio_cnp_h.c b/src/soc/intel/cannonlake/gpio_cnp_h.c index 102444a9f8..dd9f433645 100644 --- a/src/soc/intel/cannonlake/gpio_cnp_h.c +++ b/src/soc/intel/cannonlake/gpio_cnp_h.c @@ -80,7 +80,8 @@ static const struct pad_group cnl_community4_groups[] = { }; static const struct pad_community cnl_communities[] = { - { /* GPP A, B */ + /* GPP A, B */ + [COMM_0] = { .port = PID_GPIOCOM0, .first_pad = GPP_A0, .last_pad = GPIO_RSVD_2, @@ -98,7 +99,9 @@ static const struct pad_community cnl_communities[] = { .num_reset_vals = ARRAY_SIZE(rst_map_com0), .groups = cnl_community0_groups, .num_groups = ARRAY_SIZE(cnl_community0_groups), - }, { /* GPP C, D, G */ + }, + /* GPP C, D, G */ + [COMM_1] = { .port = PID_GPIOCOM1, .first_pad = GPP_C0, .last_pad = vSSP2_RXD, @@ -116,7 +119,9 @@ static const struct pad_community cnl_communities[] = { .num_reset_vals = ARRAY_SIZE(rst_map), .groups = cnl_community1_groups, .num_groups = ARRAY_SIZE(cnl_community1_groups), - }, { /* GPD */ + }, + /* GPD */ + [COMM_2] = { .port = PID_GPIOCOM2, .first_pad = GPD0, .last_pad = GPD11, @@ -134,7 +139,9 @@ static const struct pad_community cnl_communities[] = { .num_reset_vals = ARRAY_SIZE(rst_map), .groups = cnl_community2_groups, .num_groups = ARRAY_SIZE(cnl_community2_groups), - }, { /* GPP K, H, E, F */ + }, + /* GPP K, H, E, F */ + [COMM_3] = { .port = PID_GPIOCOM3, .first_pad = GPP_K0, .last_pad = GPIO_RSVD_19, @@ -152,7 +159,9 @@ static const struct pad_community cnl_communities[] = { .num_reset_vals = ARRAY_SIZE(rst_map), .groups = cnl_community3_groups, .num_groups = ARRAY_SIZE(cnl_community3_groups), - }, { /* GPP I, J */ + }, + /* GPP I, J */ + [COMM_4] = { .port = PID_GPIOCOM4, .first_pad = GPIO_RSVD_20, .last_pad = GPP_J11, diff --git a/src/soc/intel/cannonlake/include/soc/gpio_soc_defs.h b/src/soc/intel/cannonlake/include/soc/gpio_soc_defs.h index 59901440d9..698bd2a5c7 100644 --- a/src/soc/intel/cannonlake/include/soc/gpio_soc_defs.h +++ b/src/soc/intel/cannonlake/include/soc/gpio_soc_defs.h @@ -355,4 +355,12 @@ #define TOTAL_PADS 275 #define SD_PWR_EN_PIN GPP_A17 + +#define COMM_0 0 +#define COMM_1 1 +#define COMM_2 2 +#define COMM_3 3 +#define COMM_4 4 +#define TOTAL_GPIO_COMM 5 + #endif diff --git a/src/soc/intel/cannonlake/include/soc/gpio_soc_defs_cnp_h.h b/src/soc/intel/cannonlake/include/soc/gpio_soc_defs_cnp_h.h index 1788e78989..5176ac734a 100644 --- a/src/soc/intel/cannonlake/include/soc/gpio_soc_defs_cnp_h.h +++ b/src/soc/intel/cannonlake/include/soc/gpio_soc_defs_cnp_h.h @@ -399,4 +399,11 @@ #define TOTAL_PADS (GPD11 + 1) +#define COMM_0 0 +#define COMM_1 1 +#define COMM_2 2 +#define COMM_3 3 +#define COMM_4 4 +#define TOTAL_GPIO_COMM 5 + #endif From 97ae7430a80c00b3f53465727880d74d7ebfe7aa Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Fri, 17 May 2019 14:39:36 +0530 Subject: [PATCH 109/331] mb/google/dragonegg: Override FSP default GPIO PM configuration GPIO_COMM_0/2/3/4: Enable gpio community all PM configuration. GPIO_COMM_1: Disable RCOMP clock gating due to GPP_D16 IRQ mapped for H1 TPM. BUG=b:130764684 TEST=H1 TPM interrupt working find and able to boot from fixed boot media Change-Id: I1f83f938f201c6574367960b1027555767cf6f3d Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/32847 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- .../google/dragonegg/variants/baseboard/devicetree.cb | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/src/mainboard/google/dragonegg/variants/baseboard/devicetree.cb b/src/mainboard/google/dragonegg/variants/baseboard/devicetree.cb index 257ad1dd15..f820924280 100644 --- a/src/mainboard/google/dragonegg/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dragonegg/variants/baseboard/devicetree.cb @@ -167,6 +167,16 @@ chip soc/intel/icelake }, }" + # GPIO PM programming + register "gpio_override_pm" = "1" + + # GPIO community PM configuration + register "gpio_pm[COMM_0]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG" + register "gpio_pm[COMM_1]" = "MISCCFG_GPSIDEDPCGEN | MISCCFG_GPRTCDLCGEN | MISCCFG_GSXSLCGEN | MISCCFG_GPDPCGEN | MISCCFG_GPDLCGEN" + register "gpio_pm[COMM_2]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG" + register "gpio_pm[COMM_3]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG" + register "gpio_pm[COMM_4]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG" + device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device From 0c89ed93d758d3abd82f19abf12fa66c16610a57 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Fri, 17 May 2019 14:50:48 +0530 Subject: [PATCH 110/331] mb/google/{arcada, hatch, sarien}: Override FSP default GPIO PM configuration sarien/arcada: GPIO_COMM_0/2/3/4: Enable gpio community all PM configuration GPIO_COMM_1: Disable RCOMP clock gating due to GPP_D18 IRQ mapped for H1 TPM. hatch: GPIO_COMM_0/1/2/3: Enable gpio community all PM configuration GPIO_COMM_4: Disable RCOMP clock gating due to GPP_C21 IRQ mapped for H1 TPM. BUG=b:130764684 TEST=H1 TPM interrupt working find and able to boot from fixed boot media Change-Id: Ia4d5483847a4d243b9038119d4bb5990591cc754 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/32848 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- .../google/hatch/variants/baseboard/devicetree.cb | 10 ++++++++++ .../google/sarien/variants/arcada/devicetree.cb | 10 ++++++++++ .../google/sarien/variants/sarien/devicetree.cb | 10 ++++++++++ 3 files changed, 30 insertions(+) diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index 09e004e84c..9d10cac41b 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -89,6 +89,16 @@ chip soc/intel/cannonlake register "PchHdaAudioLinkSsp1" = "1" register "PchHdaAudioLinkDmic0" = "1" + # GPIO PM programming + register "gpio_override_pm" = "1" + + # GPIO community PM configuration + register "gpio_pm[COMM_0]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG" + register "gpio_pm[COMM_1]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG" + register "gpio_pm[COMM_2]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG" + register "gpio_pm[COMM_3]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG" + register "gpio_pm[COMM_4]" = "MISCCFG_GPSIDEDPCGEN | MISCCFG_GPRTCDLCGEN | MISCCFG_GSXSLCGEN | MISCCFG_GPDPCGEN | MISCCFG_GPDLCGEN" + device cpu_cluster 0 on device lapic 0 on end end diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb index b6377ba55d..d3848a24b0 100644 --- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb +++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb @@ -201,6 +201,16 @@ chip soc/intel/cannonlake register "PcieClkSrcUsage[4]" = "12" register "PcieClkSrcClkReq[4]" = "4" + # GPIO PM programming + register "gpio_override_pm" = "1" + + # GPIO community PM configuration + register "gpio_pm[COMM_0]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG" + register "gpio_pm[COMM_1]" = "MISCCFG_GPSIDEDPCGEN | MISCCFG_GPRTCDLCGEN | MISCCFG_GSXSLCGEN | MISCCFG_GPDPCGEN | MISCCFG_GPDLCGEN" + register "gpio_pm[COMM_2]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG" + register "gpio_pm[COMM_3]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG" + register "gpio_pm[COMM_4]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG" + device cpu_cluster 0 on device lapic 0 on end end diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb index 3807047e0f..c96423c93d 100644 --- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb +++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb @@ -205,6 +205,16 @@ chip soc/intel/cannonlake register "PcieClkSrcUsage[2]" = "12" register "PcieClkSrcClkReq[2]" = "2" + # GPIO PM programming + register "gpio_override_pm" = "1" + + # GPIO community PM configuration + register "gpio_pm[COMM_0]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG" + register "gpio_pm[COMM_1]" = "MISCCFG_GPSIDEDPCGEN | MISCCFG_GPRTCDLCGEN | MISCCFG_GSXSLCGEN | MISCCFG_GPDPCGEN | MISCCFG_GPDLCGEN" + register "gpio_pm[COMM_2]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG" + register "gpio_pm[COMM_3]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG" + register "gpio_pm[COMM_4]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG" + device cpu_cluster 0 on device lapic 0 on end end From cf041d8c8375d07434908a8bd1028d4bd0d54070 Mon Sep 17 00:00:00 2001 From: Mike Banon Date: Tue, 28 Aug 2018 00:44:59 +0300 Subject: [PATCH 111/331] src/vendorcode/amd/agesa/f16kb: Update microcode to version 0x7000110 2018-02-09 This microcode update for CPU ID 0x700F01 improves system stability: in particular, fixes Xen hardware virtualization freezes. Also it attempts to patch some Spectre-related security vulnerabilities. This new microcode has been tested by multiple coreboot community members and found working perfectly. Old version: 0x700010B [2013-07-09] replaced by New version: 0x7000110 [2018-02-09] Change-Id: Iebe6e54d922378a8a1feb97f37b08ac50c8234b2 Signed-off-by: Mike Banon Reviewed-on: https://review.coreboot.org/c/coreboot/+/28370 Reviewed-by: Martin Roth Tested-by: build bot (Jenkins) --- .../0x16/KB/F16KbId7001MicrocodePatch.c | 3899 ++--------------- 1 file changed, 437 insertions(+), 3462 deletions(-) diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbId7001MicrocodePatch.c b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbId7001MicrocodePatch.c index 61876b8db5..a0a20eb3e9 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbId7001MicrocodePatch.c +++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbId7001MicrocodePatch.c @@ -4,16 +4,16 @@ * * AMD F16Kb Microcode patch. * - * F16Kb Microcode Patch rev 0700010B for 7001 or equivalent. + * F16Kb Microcode Patch rev 07000110 for 7001 or equivalent. * * @xrefitem bom "File Content Label" "Release Content" * @e project: AGESA * @e sub-project: CPU/Family/0x16/KB - * @e \$Revision: 267923 $ @e \$Date: 2013-07-15 16:49:48 -0400 (Mon, 15 Jul 2013) $ + * @e \$Revision: 334098 $ @e \$Date: 2018-02-09 14:21:15 -0400 (Fri, 09 Feb 2018) $ */ /***************************************************************************** * - * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * Copyright (c) 2008 - 2018, Advanced Micro Devices, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -64,3468 +64,443 @@ RDATA_GROUP (G3_DXE) */ -// Encrypt Patch code 0700010B for 7001 and equivalent +// Encrypt Patch code 07000110 for 7001 and equivalent CONST UINT8 ROMDATA CpuF16KbId7001MicrocodePatch [IDS_PAD_4K] = { - 0x13, - 0x20, - 0x09, - 0x07, - 0x0b, - 0x01, - 0x00, - 0x07, - 0x03, - 0x80, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x01, - 0x70, - 0x00, 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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00 }; /*---------------------------------------------------------------------------------------- From 334e8360efb03644488ce4ac8a9a9e75ef6fa6c0 Mon Sep 17 00:00:00 2001 From: Mike Banon Date: Thu, 23 Aug 2018 00:50:08 +0300 Subject: [PATCH 112/331] src/vendorcode/amd/agesa/f15tn: Update microcode to version 0x600111F 2018-03-05 This microcode update for CPU IDs 0x610F01/0x610F31 improves system stability: in particular, fixes Xen hardware virtualization freezes. Also it attempts to patch some Spectre-related security vulnerabilities. This new microcode has been tested by multiple coreboot community members and found working perfectly. Old version: 0x600110F [2012-01-11] replaced by New version: 0x600111F [2018-03-05] Change-Id: Ied5da0ff85abb63c2db2eeafd051b8e00916d961 Signed-off-by: Mike Banon Reviewed-on: https://review.coreboot.org/c/coreboot/+/28273 Reviewed-by: Martin Roth Reviewed-by: Tested-by: build bot (Jenkins) --- .../f15tn/Config/OptionFamily15hInstall.h | 4 +- .../0x15/TN/F15TnMicrocodePatch0600110F_Enc.c | 2673 ----------------- .../0x15/TN/F15TnMicrocodePatch0600111F_Enc.c | 405 +++ .../Proc/CPU/Family/0x15/TN/Makefile.inc | 2 +- 4 files changed, 408 insertions(+), 2676 deletions(-) delete mode 100644 src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnMicrocodePatch0600110F_Enc.c create mode 100644 src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnMicrocodePatch0600111F_Enc.c diff --git a/src/vendorcode/amd/agesa/f15tn/Config/OptionFamily15hInstall.h b/src/vendorcode/amd/agesa/f15tn/Config/OptionFamily15hInstall.h index f0d9194018..bd00756c43 100644 --- a/src/vendorcode/amd/agesa/f15tn/Config/OptionFamily15hInstall.h +++ b/src/vendorcode/amd/agesa/f15tn/Config/OptionFamily15hInstall.h @@ -808,9 +808,9 @@ extern F_IS_NB_PSTATE_ENABLED F15IsNbPstateEnabled; #define F15_TN_UCODE_0E #if AGESA_ENTRY_INIT_EARLY == TRUE - extern CONST UINT8 ROMDATA CpuF15TnMicrocodePatch0600110F_Enc []; + extern CONST UINT8 ROMDATA CpuF15TnMicrocodePatch0600111F_Enc []; #undef F15_TN_UCODE_10F - #define F15_TN_UCODE_10F CpuF15TnMicrocodePatch0600110F_Enc, + #define F15_TN_UCODE_10F CpuF15TnMicrocodePatch0600111F_Enc, #endif diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnMicrocodePatch0600110F_Enc.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnMicrocodePatch0600110F_Enc.c deleted file mode 100644 index 80e60f6313..0000000000 --- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnMicrocodePatch0600110F_Enc.c +++ /dev/null @@ -1,2673 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD F15Tn Microcode patch. - * - * F15Tn Microcode Patch rev 0600110F for 6101 or equivalent. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/Family/0x15/TN - * @e \$Revision: 64060 $ @e \$Date: 2012-01-15 21:36:26 -0600 (Sun, 15 Jan 2012) $ - */ -/***************************************************************************** - * - * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ***************************************************************************/ - - - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "Ids.h" -#include "cpuRegisters.h" -#include "cpuEarlyInit.h" -CODE_GROUP (G3_DXE) -RDATA_GROUP (G3_DXE) - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -// Encrypt Patch code 0600110F for 6101 and equivalent - -CONST UINT8 ROMDATA CpuF15TnMicrocodePatch0600110F_Enc [IDS_PAD_4K] = -{ - 0x12, - 0x20, - 0x11, - 0x01, - 0x0f, - 0x11, - 0x00, - 0x06, - 0x02, - 0x80, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x01, - 0x61, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0xd4, - 0x3d, - 0x97, - 0xf0, - 0xd2, - 0x1a, - 0xcf, - 0x44, - 0x1d, - 0x45, - 0x82, - 0x13, - 0xec, - 0xcd, - 0x52, - 0x24, - 0x2d, - 0x26, - 0x73, - 0x9f, - 0x0e, - 0x38, - 0x80, - 0x5b, - 0x02, - 0x6a, - 0xd3, - 0x80, - 0x97, - 0xc0, - 0xe8, - 0x08, - 0xaf, - 0x52, - 0x2e, - 0xe4, - 0x54, - 0xa6, - 0xb3, - 0xb3, - 0x9b, - 0x21, - 0xb9, - 0xe1, - 0xa8, - 0xa4, - 0xed, - 0x9a, - 0x76, - 0xf7, - 0x62, - 0x13, - 0x3b, - 0xf8, - 0x21, - 0xc4, - 0xf3, - 0xff, - 0xb5, - 0x20, - 0xbd, - 0x8c, - 0x3a, - 0x4b, - 0x7e, - 0x44, - 0x88, - 0x9e, - 0x21, - 0xf3, - 0x32, - 0xad, - 0x96, - 0xf9, - 0x1d, - 0xe4, - 0xce, - 0xdd, - 0xb7, - 0x58, - 0x6c, - 0x3c, - 0x78, - 0x00, - 0x9f, - 0x9f, - 0x76, - 0x6e, - 0x92, - 0x80, - 0xb9, - 0x6a, - 0xcf, - 0x66, - 0x2b, - 0x7e, - 0x1d, - 0xbf, - 0x2d, - 0xca, - 0xde, - 0x58, - 0x1b, - 0xc6, - 0xb8, - 0x5e, - 0x82, - 0xc3, - 0xdf, - 0x8b, - 0xd8, - 0xdb, - 0xca, - 0x43, - 0xf2, - 0x75, - 0x40, - 0xb6, - 0xbf, - 0xdb, - 0x5f, - 0xb8, - 0xd2, - 0xdd, - 0x81, - 0xeb, - 0xa6, - 0x7f, - 0x01, - 0xbc, - 0x37, - 0x07, - 0x4e, - 0x73, - 0x13, - 0xcf, - 0x08, - 0xb9, - 0xd6, - 0xda, - 0xe6, - 0x10, - 0xd7, - 0x2c, - 0xfe, - 0x49, - 0x3e, - 0x4b, - 0xa0, - 0xfa, - 0xc1, - 0x81, - 0xe9, - 0xdb, - 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0x4c, - 0x84, - 0x81, - 0x21, - 0xb0, - 0x6b, - 0x25, - 0xa8, - 0x3e, - 0xc6, - 0xa4, - 0xc2, - 0x0a, - 0x46, - 0x52, - 0x4f, - 0x72, - 0x56, - 0x06, - 0xec, - 0x76, - 0xda, - 0x7e, - 0x09, - 0x45, - 0x05, - 0x9b, - 0xdb, - 0x31, - 0x90, - 0x63, - 0xdf, - 0x98, - 0x47, - 0x4a, - 0x9e, - 0x28, - 0x3d, - 0x0d, - 0x64, - 0xfb, - 0x44, - 0xc5, - 0xfb, - 0xe2, - 0x56, - 0xe9, - 0x08, - 0x98, - 0x79, - 0x2f, - 0xaf, - 0x15, - 0xb5, - 0xea, - 0x7e, - 0x61, - 0x89, - 0x16, - 0x5e, - 0x9c, - 0x6e, - 0xca, - 0x90, - 0x90, - 0x4a, - 0x5f, - 0x14, - 0x83, - 0x67, - 0x47, - 0x44, - 0xae, - 0x0a, - 0x83, - 0xc4, - 0x95, - 0xf6, - 0x88, - 0xc2, - 0xfb, - 0xa3, - 0x9b, - 0x7a, - 0xf9, - 0x32, - 0x80, - 0x94, - 0xf4, - 0x16, - 0x5a, - 0xd4, - 0xef, - 0x39, - 0xe8, - 0x86, - 0xe1, - 0xcd, - 0x6a, - 0x7e, - 0xca, - 0x33, - 0xa1, - 0xd4, - 0xcb, - 0xe9, - 0x5a, - 0xca, - 0xc6, - 0xb0, - 0xd9, - 0x68, - 0x27, - 0x8c, - 0x93, - 0x47, - 0x3e, - 0x4f, - 0xc0, - 0xa8, - 0x86, - 0x68, - 0x4b, - 0x1a, - 0xf5, - 0x93, - 0xdd, - 0x16, - 0xed, - 0x8e, - 0x27, - 0x66, - 0x4d, - 0x59, - 0xf0, - 0x27, - 0x1b, - 0x37, - 0xa0, - 0x25, - 0x9a, - 0x62, - 0xb4, - 0x6f, - 0xbd, - 0x83, - 0x28, - 0x0b, - 0x26, - 0xa9, - 0x07, - 0xac, - 0xb5, - 0x91, - 0x93, - 0x91, -}; - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnMicrocodePatch0600111F_Enc.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnMicrocodePatch0600111F_Enc.c new file mode 100644 index 0000000000..71fb1df0a8 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnMicrocodePatch0600111F_Enc.c @@ -0,0 +1,405 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD F15Tn Microcode patch. + * + * F15Tn Microcode Patch rev 0600111F for 6101/6131 or equivalent. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU/Family/0x15/TN + * @e \$Revision: 334098 $ @e \$Date: 2018-03-05 14:21:15 -0600 (Mon, 05 Mar 2018) $ + */ +/***************************************************************************** + * + * Copyright (c) 2008 - 2018, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ***************************************************************************/ + + + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "cpuRegisters.h" +#include "cpuEarlyInit.h" +CODE_GROUP (G3_DXE) +RDATA_GROUP (G3_DXE) + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +// Encrypt Patch code 0600111F for 6101/6131 and equivalent + +CONST UINT8 ROMDATA CpuF15TnMicrocodePatch0600111F_Enc [IDS_PAD_4K] = +{ + 0x18, 0x20, 0x05, 0x03, 0x1f, 0x11, 0x00, 0x06, + 0x02, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x01, 0x61, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0xd0, 0xb7, 0x58, 0x1c, 0xca, 0xa2, 0xf2, 0x52, + 0x72, 0xa4, 0xe1, 0x1b, 0x37, 0xe0, 0x9f, 0xb3, + 0x58, 0xf4, 0x76, 0x85, 0x1a, 0x83, 0x4a, 0x89, + 0x78, 0x82, 0x4e, 0xf3, 0xa1, 0x6a, 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0xfb, 0x1b, + 0xe8, 0x4d, 0x49, 0x97, 0x23, 0xeb, 0x51, 0x38, + 0x9a, 0x22, 0xa7, 0xc0, 0xcf, 0x25, 0x3a, 0x4e, + 0x50, 0x0d, 0xff, 0x8e, 0xb5, 0x91, 0xd3, 0x85, + 0x54, 0xe9, 0x1f, 0x70, 0xea, 0x64, 0x6a, 0x77, + 0xbe, 0xd2, 0x15, 0xce, 0x9c, 0xb0, 0x70, 0x61, + 0x8b, 0x58, 0xdb, 0x9f, 0x0a, 0xe4, 0x80, 0xb3, + 0x21, 0x44, 0x0b, 0xea, 0x43, 0xab, 0x0d, 0xf0, + 0x7e, 0xbc, 0xd5, 0xde, 0x29, 0x12, 0xcd, 0xde, + 0xd9, 0xf3, 0xf3, 0x0e, 0xf4, 0xb8, 0x3d, 0xd7, + 0x4e, 0x24, 0xcf, 0x9b, 0x4b, 0xad, 0x96, 0x1e, + 0xca, 0x6d, 0x3f, 0x9c, 0xe4, 0xb8, 0x8b, 0xf5, + 0x3a, 0x43, 0xb0, 0xce, 0x16, 0x27, 0x87, 0xe3, + 0x1b, 0x54, 0xd0, 0xed, 0x3c, 0xe2, 0xb0, 0x1f, + 0x24, 0xa3, 0x6d, 0x31, 0x00, 0x7d, 0x58, 0x69, + 0xc9, 0xc6, 0x50, 0xc8, 0x87, 0xac, 0x45, 0x54, + 0x66, 0x06, 0x7f, 0xc3, 0x51, 0xb8, 0xdf, 0x51 +}; + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/Makefile.inc b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/Makefile.inc index 7d52cb6dae..e4b04247b2 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/Makefile.inc +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/Makefile.inc @@ -4,7 +4,7 @@ libagesa-y += F15TnEquivalenceTable.c libagesa-y += F15TnInitEarlyTable.c libagesa-y += F15TnIoCstate.c libagesa-y += F15TnLogicalIdTables.c -libagesa-y += F15TnMicrocodePatch0600110F_Enc.c +libagesa-y += F15TnMicrocodePatch0600111F_Enc.c libagesa-y += F15TnMicrocodePatchTables.c libagesa-y += F15TnMsrTables.c libagesa-y += F15TnPciTables.c From ddbf2c4af05b5cbd889d6a55e67734c8a041bc66 Mon Sep 17 00:00:00 2001 From: Tim Wawrzynczak Date: Wed, 15 May 2019 08:42:20 -0600 Subject: [PATCH 113/331] soc/intel/cannonlake: Configure SPI CS parameters in FSP UPD. When FSP UPD parameters are configured, also configure the GSPI CS lines appropriately. GSPI driver assumes CS0 is the CS signal to use. BUG=b:130329260 BRANCH=None TEST=Boot Kohaku, TPM communcation still functional. Change-Id: Ic816395b7d198a52c704e6cabcb56889150b741c Signed-off-by: Tim Wawrzynczak Reviewed-on: https://review.coreboot.org/c/coreboot/+/32791 Reviewed-by: Patrick Georgi Reviewed-by: Paul Fagerburg Tested-by: build bot (Jenkins) --- src/soc/intel/cannonlake/fsp_params.c | 43 +++++++++++++++++++++++++++ 1 file changed, 43 insertions(+) diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index cc01d10fe8..dd9388296d 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -119,6 +119,28 @@ static void ignore_gbe_ltr(void) write8(pmcbase + LTR_IGN, reg8); } +static void configure_gspi_cs(int idx, const config_t *config, + uint8_t *polarity, uint8_t *enable, + uint8_t *defaultcs) +{ + struct spi_cfg cfg; + + /* If speed_mhz is set, infer that the port should be configured */ + if (config->common_soc_config.gspi[idx].speed_mhz != 0) { + if (gspi_get_soc_spi_cfg(idx, &cfg) == 0) { + if (cfg.cs_polarity == SPI_POLARITY_LOW) + *polarity = 0; + else + *polarity = 1; + + if (defaultcs != NULL) + *defaultcs = 0; + if (enable != NULL) + *enable = 1; + } + } +} + /* UPD parameters to be initialized before SiliconInit */ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) { @@ -357,6 +379,27 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) /* Unlock all GPIO pads */ tconfig->PchUnlockGpioPads = config->PchUnlockGpioPads; + + /* + * GSPI Chip Select parameters + * The GSPI driver assumes that CS0 is the used chip-select line, + * therefore only CS0 is configured below. + */ +#if CONFIG(SOC_INTEL_COMETLAKE) + configure_gspi_cs(0, config, ¶ms->SerialIoSpi0CsPolarity[0], + ¶ms->SerialIoSpi0CsEnable[0], + ¶ms->SerialIoSpiDefaultCsOutput[0]); + configure_gspi_cs(1, config, ¶ms->SerialIoSpi1CsPolarity[0], + ¶ms->SerialIoSpi1CsEnable[0], + ¶ms->SerialIoSpiDefaultCsOutput[1]); + configure_gspi_cs(2, config, ¶ms->SerialIoSpi2CsPolarity[0], + ¶ms->SerialIoSpi2CsEnable[0], + ¶ms->SerialIoSpiDefaultCsOutput[2]); +#else + for (i = 0; i < CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX; i++) + configure_gspi_cs(i, config, + ¶ms->SerialIoSpiCsPolarity[0], NULL, NULL); +#endif } /* Mainboard GPIO Configuration */ From 365cb144c8622faff5043cbca8ff80751998556c Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Sun, 19 May 2019 23:31:48 +0200 Subject: [PATCH 114/331] src/drivers/intel/fsp2_0: Fix logical 'and' of equal expressions Probably a copy/paste issue. Change-Id: I0334bc1f5d145df5af0a307cf8e7c23cc0605f76 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/32886 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/drivers/intel/fsp2_0/hand_off_block.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/drivers/intel/fsp2_0/hand_off_block.c b/src/drivers/intel/fsp2_0/hand_off_block.c index 5efd59058c..c5c78cabf0 100644 --- a/src/drivers/intel/fsp2_0/hand_off_block.c +++ b/src/drivers/intel/fsp2_0/hand_off_block.c @@ -237,9 +237,9 @@ static void display_fsp_version_info_hob(const void *hob, size_t size) /* Don't show ingredient name and version if its all 0xFF */ if (fvi[index].Version.MajorVersion == 0xFF && - fvi[index].Version.MajorVersion == 0xFF && - fvi[index].Version.MajorVersion == 0xFF && - fvi[index].Version.MajorVersion == 0xFF && + fvi[index].Version.MinorVersion == 0xFF && + fvi[index].Version.Revision == 0xFF && + fvi[index].Version.BuildNumber == 0xFF && fvi[index].VersionStringIndex == 0) { str_ptr = (char *)((uintptr_t)str_ptr + cnt + sizeof(uint8_t)); From 86fa2792b98cabd0b8604342a44e099d8ade5a77 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Sun, 19 May 2019 14:41:28 +0200 Subject: [PATCH 115/331] mb/lenovo/t400: Add VBT file All variants (t400, r400, t500, w500) use the same OPROM for the IGD. Change-Id: I1b9db7b29b22809542f80f60a5e2eb3283fe1c02 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/32884 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Patrick Rudolph --- src/mainboard/lenovo/t400/Kconfig | 1 + src/mainboard/lenovo/t400/data.vbt | Bin 0 -> 3863 bytes 2 files changed, 1 insertion(+) create mode 100644 src/mainboard/lenovo/t400/data.vbt diff --git a/src/mainboard/lenovo/t400/Kconfig b/src/mainboard/lenovo/t400/Kconfig index 9f9405162c..16f1680376 100644 --- a/src/mainboard/lenovo/t400/Kconfig +++ b/src/mainboard/lenovo/t400/Kconfig @@ -25,6 +25,7 @@ config BOARD_SPECIFIC_OPTIONS select DRIVERS_LENOVO_HYBRID_GRAPHICS select MAINBOARD_HAS_LIBGFXINIT select MAINBOARD_USES_IFD_GBE_REGION + select INTEL_GMA_HAVE_VBT config MAINBOARD_DIR string diff --git a/src/mainboard/lenovo/t400/data.vbt b/src/mainboard/lenovo/t400/data.vbt new file mode 100644 index 0000000000000000000000000000000000000000..e9bfaaf65126d9ef41fcc3be62f6b9505f213828 GIT binary patch literal 3863 zcmcImZ)_Ar6o31FZ*KQ`w-kCU1*Sk?i?nP@sX$8H_A0iufwq*UK@;xaPDBc=r4UFo zU8D&liq`mrAi;hi5kizNe)5AgF@c0=)I>0f(r*Mb;e&|@#B_Z#yVp`%Xo)bFncv$t z@BQY@%$u28-qp}aQ}tUqn_sG@Vab96MFqcLJH0eCZ{4=DvA(l@XG81O)XVf^SOB+U z<97kFf?#S@8`f`VJ}{8$u{+9BnF9lR_he{Ws+rdB-ks~o^=AfhS-PzYhhjV?X*jgE zCrh^++P^E;zmYO$w5C-xm1}D#b*k4?Icut&Du>A%o#!{!Y%odV-h+KTnWJsJ{R1>} zAWIv&npe~Q-2UFfIojCSxNMzCrbnIEqs%*w$dbwbyU)2WD*q6j)AaYoI<0l$`OHxhAat+Vk%KVQ|2o# zDlvJpT%aTpqA7^zQYJzq4xL^3FhH4*fO1iXrEzH8+?Lm)lN8EI5R$|N zDlm-;KTa_a0a&oCP?W<$^TMO>*&0X~s$2?AbxrO1jdgBA5 zK2!qZZ(wMAMm$78hzS(VXp5mnwjm>nuuonOm*lJPKy{!(OF|RY-B@4KbvUeBa1!eo zte3EUtrNJ0^(U;iu>OhlZ>$g@K(MN(gnxVy(g1ow0vS;)lpu~M;?E8BjUg5yf+5PK zh-`P75Sd?Vh)G1&PZ3%F#D2-RTlnDtLjX?*F~L#r%7Skw zPl!d5j`)FiPc#s335FO)ye-ILA>tk3522Ln2Std7eu&%;k^3QXKSb__$o;r}Q2d$V zh=MBJWQY@SFz&O9aIQi8o*ob4WbwX_(Lq9mOFgV|LwZ6Pgb3@4!#{_@jxaRv*LKZIJq@+M{)yuNK(8pd}9@YPqOA4TldE{sP zf2HUZC}X#=u&ueGYHe+GMLlEgV;Uytyme8MC^i$Ne?sB{yIrOlOznsCYzFb!4CrhI zMgm&c>gjb}3~d3ngJ?=HE@fj85ca7%;EGxS1@E#G`pin?q5F3ZgT#j*juG?47Ic=- zvJNihJE|UC^hdj37w#BRVa|vs$RQ_^J*F!$Ih}Dyx6>s~ zlUEyX%aT8$3}Mfi@{#Y`hn6~Rr}I65fmRpb^meA61x08l@rxx$XXfS%VUiRzLADs& zdRXBkPliJzomFtU9URx`n-}me{&dZevG$S`ZujZDrs)OO*>$qz$!$Qm}SL z?V!R|AFu4%L1CC**eI!NFHl!(LoqzSUoi{|6oTJX-1gwNT9}kdkj1r=Ai_cBinrI~ zd1v3{AA)o(V&9KgQ9|YuJ4LMRgzO~tDPny>$OU5GAl4m1{vvi+)LI)Qo1*r+^~N$ta}EzZ`dnM3;!aeO#4mK zI&P9vrv0U9eQS~%rme)Rq8KTQ*;`{)CPr3`$n0YC*wrjSgKnwtP2>R>A;uAvf|cMP zVxhi&J>m`1u|;t`y_9JH7UQagE6Fa#kjb5iNt(hmQa~}sN~!G?PB5|O7K?$4FFh`% zsZ2AZ#b;G6CoRY`)jeW%voo!GYD@zm(-EaaX0yYX=CDrF6Po2I-w%U5J9B56eh^rm z^Rs5KTVw8fccBDE+JHC?UB#D~Wq~xzFD4A_NoMy} Date: Sun, 16 Sep 2018 18:55:28 +0200 Subject: [PATCH 116/331] mb/lenovo/r500: Add mainboard Tested: - Ethernet NIC - Wifi RFKill - USB - LVDS, VGA with libgfxinit - Booting with dock attached (COM1) - Keyboard, trackpoint - SeaBIOS 1.12 - S3 resume - Tested in descriptor mode, with vendor FD and ME - Add VBT to ACPI OPregion Untested: - SATA (likely works) - Trackpad (my cable is broken, likely works) - Displayport (likely works) - Descriptorless mode - DVD drive - Extra battery - model with ATI GPU Does not work: - Dock hotplug - Quad core CPU (hangs during AP init, probably needs hardware mod) - Hotplugging the expresscard slot (works with 'echo 1 | sudo tee /sys/bus/pci/rescan') TODO: - proper dock support - documentation note: This board was hard to flash, I had to desolder the flash. TESTED: on a R500 with an Intel iGPU, SeaBIOS 1.12, Debian 9, Linux 4.9 from USB Change-Id: I9e129b2e916acdf2b8534fa9d8d2cfc8f64f5815 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/28644 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph --- src/mainboard/lenovo/t400/Kconfig | 21 ++- src/mainboard/lenovo/t400/Kconfig.name | 3 + src/mainboard/lenovo/t400/Makefile.inc | 3 +- src/mainboard/lenovo/t400/devicetree.cb | 36 +---- src/mainboard/lenovo/t400/dsdt.asl | 1 + src/mainboard/lenovo/t400/romstage.c | 16 ++- .../lenovo/t400/variants/r500/Makefile.inc | 1 + .../lenovo/t400/variants/r500/data.vbt | Bin 0 -> 4125 bytes .../lenovo/t400/variants/r500/gpio.c | 131 ++++++++++++++++++ .../lenovo/t400/variants/r500/overridetree.cb | 45 ++++++ .../lenovo/t400/variants/t400/Makefile.inc | 1 + .../lenovo/t400/{ => variants/t400}/data.vbt | Bin .../lenovo/t400/{ => variants/t400}/gpio.c | 0 .../lenovo/t400/variants/t400/overridetree.cb | 43 ++++++ 14 files changed, 261 insertions(+), 40 deletions(-) create mode 100644 src/mainboard/lenovo/t400/variants/r500/Makefile.inc create mode 100644 src/mainboard/lenovo/t400/variants/r500/data.vbt create mode 100644 src/mainboard/lenovo/t400/variants/r500/gpio.c create mode 100644 src/mainboard/lenovo/t400/variants/r500/overridetree.cb create mode 100644 src/mainboard/lenovo/t400/variants/t400/Makefile.inc rename src/mainboard/lenovo/t400/{ => variants/t400}/data.vbt (100%) rename src/mainboard/lenovo/t400/{ => variants/t400}/gpio.c (100%) create mode 100644 src/mainboard/lenovo/t400/variants/t400/overridetree.cb diff --git a/src/mainboard/lenovo/t400/Kconfig b/src/mainboard/lenovo/t400/Kconfig index 16f1680376..2bd67c28bc 100644 --- a/src/mainboard/lenovo/t400/Kconfig +++ b/src/mainboard/lenovo/t400/Kconfig @@ -1,5 +1,5 @@ if BOARD_LENOVO_T400 || BOARD_LENOVO_T500 || BOARD_LENOVO_R400 \ - || BOARD_LENOVO_W500 + || BOARD_LENOVO_W500 || BOARD_LENOVO_R500 config BOARD_SPECIFIC_OPTIONS def_bool y @@ -11,7 +11,8 @@ config BOARD_SPECIFIC_OPTIONS select EC_LENOVO_H8 select H8_HAS_BAT_TRESHOLDS_IMPL select H8_DOCK_EARLY_INIT - select BOARD_ROMSIZE_KB_8192 + select BOARD_ROMSIZE_KB_8192 if !BOARD_LENOVO_R500 + select BOARD_ROMSIZE_KB_4096 if BOARD_LENOVO_R500 select DRIVERS_GENERIC_IOAPIC select HAVE_MP_TABLE select HAVE_ACPI_TABLES @@ -24,20 +25,31 @@ config BOARD_SPECIFIC_OPTIONS select SUPERIO_NSC_PC87384 select DRIVERS_LENOVO_HYBRID_GRAPHICS select MAINBOARD_HAS_LIBGFXINIT - select MAINBOARD_USES_IFD_GBE_REGION + select MAINBOARD_USES_IFD_GBE_REGION if !BOARD_LENOVO_R500 select INTEL_GMA_HAVE_VBT config MAINBOARD_DIR string default lenovo/t400 +config VARIANT_DIR + string + default "t400" if BOARD_LENOVO_T400 || BOARD_LENOVO_T500 \ + || BOARD_LENOVO_R400 || BOARD_LENOVO_W500 + default "r500" if BOARD_LENOVO_R500 + config MAINBOARD_PART_NUMBER string default "ThinkPad T400" if BOARD_LENOVO_T400 default "ThinkPad T500" if BOARD_LENOVO_T500 default "ThinkPad R400" if BOARD_LENOVO_R400 + default "ThinkPad R500" if BOARD_LENOVO_R500 default "ThinkPad W500" if BOARD_LENOVO_W500 +config OVERRIDE_DEVICETREE + string + default "variants/$(CONFIG_VARIANT_DIR)/overridetree.cb" + config USBDEBUG_HCD_INDEX int default 2 @@ -54,4 +66,7 @@ config ONBOARD_VGA_IS_PRIMARY bool default y +config INTEL_GMA_VBT_FILE + default "src/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/data.vbt" + endif # BOARD_LENOVO_T400 diff --git a/src/mainboard/lenovo/t400/Kconfig.name b/src/mainboard/lenovo/t400/Kconfig.name index d459ce9236..a259ddece4 100644 --- a/src/mainboard/lenovo/t400/Kconfig.name +++ b/src/mainboard/lenovo/t400/Kconfig.name @@ -7,5 +7,8 @@ config BOARD_LENOVO_T500 config BOARD_LENOVO_R400 bool "ThinkPad R400" +config BOARD_LENOVO_R500 + bool "ThinkPad R500" + config BOARD_LENOVO_W500 bool "ThinkPad W500" diff --git a/src/mainboard/lenovo/t400/Makefile.inc b/src/mainboard/lenovo/t400/Makefile.inc index 7721e0345f..d0ee1537f4 100644 --- a/src/mainboard/lenovo/t400/Makefile.inc +++ b/src/mainboard/lenovo/t400/Makefile.inc @@ -13,9 +13,10 @@ ## GNU General Public License for more details. ## -romstage-y += gpio.c romstage-y += dock.c +subdirs-y += variants/$(VARIANT_DIR)/ + ramstage-y += dock.c ramstage-y += cstates.c ramstage-y += blc.c diff --git a/src/mainboard/lenovo/t400/devicetree.cb b/src/mainboard/lenovo/t400/devicetree.cb index 475c45ebbd..b4c2ea89b1 100644 --- a/src/mainboard/lenovo/t400/devicetree.cb +++ b/src/mainboard/lenovo/t400/devicetree.cb @@ -211,46 +211,12 @@ chip northbridge/intel/gm45 io 0x60 = 0x1620 end end - - chip drivers/lenovo/hybrid_graphics - device pnp ff.f on end # dummy - - register "detect_gpio" = "21" - - register "has_panel_hybrid_gpio" = "1" - register "panel_hybrid_gpio" = "22" - register "panel_integrated_lvl" = "0" - - register "has_backlight_gpio" = "1" - register "backlight_gpio" = "19" - register "backlight_integrated_lvl" = "0" - - register "has_dgpu_power_gpio" = "1" - register "dgpu_power_gpio" = "49" - register "dgpu_power_off_lvl" = "0" - - register "has_thinker1" = "0" - end end device pci 1f.2 on # SATA/IDE 1 subsystemid 0x17aa 0x20f8 ioapic_irq 2 INTB 0x11 end - device pci 1f.3 on # SMBus - subsystemid 0x17aa 0x20f9 - ioapic_irq 2 INTC 0x12 - # eeprom, 8 virtual devices, same chip - chip drivers/i2c/at24rf08c - device i2c 54 on end - device i2c 55 on end - device i2c 56 on end - device i2c 57 on end - device i2c 5c on end - device i2c 5d on end - device i2c 5e on end - device i2c 5f on end - end - end + device pci 1f.3 on end # SMBus device pci 1f.5 off end # SATA/IDE 2 device pci 1f.6 off end # Thermal end diff --git a/src/mainboard/lenovo/t400/dsdt.asl b/src/mainboard/lenovo/t400/dsdt.asl index 75f4bce0c5..6aafec69c4 100644 --- a/src/mainboard/lenovo/t400/dsdt.asl +++ b/src/mainboard/lenovo/t400/dsdt.asl @@ -18,6 +18,7 @@ #define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB #define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB #define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 +#define EC_LENOVO_H8_ME_WORKAROUND 1 #include DefinitionBlock( diff --git a/src/mainboard/lenovo/t400/romstage.c b/src/mainboard/lenovo/t400/romstage.c index 6b03ad0ad8..43d6088788 100644 --- a/src/mainboard/lenovo/t400/romstage.c +++ b/src/mainboard/lenovo/t400/romstage.c @@ -75,7 +75,21 @@ void mb_pre_raminit_setup(sysinfo_t *sysinfo) else dock_info(); - hybrid_graphics_init(sysinfo); + if (CONFIG(BOARD_LENOVO_R500)) { + int use_integrated = get_gpio(21); + printk(BIOS_DEBUG, "R500 variant found with an %s GPU\n", + use_integrated ? "integrated" : "discrete"); + if (use_integrated) { + sysinfo->enable_igd = 1; + sysinfo->enable_peg = 0; + } else { + sysinfo->enable_igd = 0; + sysinfo->enable_peg = 1; + } + } else { + hybrid_graphics_init(sysinfo); + } + } void mb_post_raminit_setup(void) diff --git a/src/mainboard/lenovo/t400/variants/r500/Makefile.inc b/src/mainboard/lenovo/t400/variants/r500/Makefile.inc new file mode 100644 index 0000000000..3dae61e8a8 --- /dev/null +++ b/src/mainboard/lenovo/t400/variants/r500/Makefile.inc @@ -0,0 +1 @@ +romstage-y += gpio.c diff --git a/src/mainboard/lenovo/t400/variants/r500/data.vbt b/src/mainboard/lenovo/t400/variants/r500/data.vbt new file mode 100644 index 0000000000000000000000000000000000000000..799b9b687eff8bfe5c8ff610e13ce952ee8b3354 GIT binary patch literal 4125 zcmd5;Z)_Ar6o32wZg2N)Z#n4oC}oPoZo$H~Km~G!ZLeaB4YW|mMNGItFF>qN+oF(= zbd@G(6g}mGXb3q?NE8$03!nTzO-#TT4Tc0IiZ<~BQDTURevp{1Z)W$d)D~JIB+li{ z@9mp;zj-tBX66=eYw0GL=8fI$Pc)OD^nwiwj11OOOH2EvEjwD9yPJ2kbZp8zN#25a z@LO#BSAbrQ(_;;fu4roCHm?fxJi9YLu$E9~>`fY0E?cpZ5W8Wyy=r-*ZLcAuv2pDxdu>CbuD0$S?CfB&I@y}S1e5i3(iklL=tY6W2-lg$2s{$-@Oua9h|eFn+q{9u0I z`F!s(U8Q4<3Lz2sISCXFxXN(?t)eW3IhEH$fs-U%ig1cFS9)BEitELg6p!;d$D>OP z4`Bnkx0QpF${G-+hG3Ba9qT(wc61T~-R~g6m0Zx5*%bhv#NY@=Ee@>+t)>*hmrbOs z-9dS<9Rv(jtOC1nWz*`lX{V)iecOhP&duH1vQItjzWCCSkra%7h>@`wu?V>+N8qYb z4TGWuMUjUy;%c}dUW7G@4Sh-yj-tGeayk@(b0HHhpj<_{fdXL_RFnitHOf+yRVeFF z+EKQn!{r z37+Sj_dJlYd`TM(Y_3w20$UKA=Q&D$$)-4g=JI2lH-B95JR%?q({NIPuQ~Er(VOpK zD=v@hea|!r&_+EP^mGEuX z_bdi6M!>*`*5K7EXviiB$kqk z;=3woA8)VcRp6JvE*3wXX`?-YNm9`Uy_MiJ!^3v+<$x$@FM$(XU^{mI9G|87gXIUu zx>652*%Kv8+d9YIdA8AUMoX5Y1x>?(zjj*FutZlMuk5B_uD~vA)MUCBXsfiK5^mwI z5(*pv|926$-TytpO=u}(apr#xS>9QAN%@0&dCvb+qw|`nSV`bvkoCgLv3!A1L*1Jo ze4|>PYQ`h#{D{>aF}Fw5e8f5)F;7R-Pa@W}hBH!F0tMz=QUW{<8uqg(Ij=101EPPcy6%|CV3)2;fbxh|@`2*P>P=W-f@SwJ~dJ%-kJQmlQ>MKfCmW5uhbx%J6yk7H9z)h*GQ;Y(y-? z^R9&50vTIigmR0h1)v%?KS&6AzXwdtbWFk|reciXQK=%9nNg zCc8gwa2RQ<#FW0n>}FEnV0;YpfN~E*Hm}ap~Q_m$mZfrj^`g+cuY3g~V$CX_f z8om5xzjq&|px6njZIdNznQ0aX1$Mt;X!kO^!^;ZAT&mi!NpLeElUN8-R?SuJKD)`8 zX{Fs_|JjF-X(A@6z+S=I^J&@@pUgBRpXlr$!eT1r6P}i7nP$i*#-!ahCf#Sk2WIwr z_bc5yQekU$hI+FTECBm6fmv`bCsm10rFehgi taq1n!M4wO4miB#1SN)N>`0h_r{sH7tZjAr{ literal 0 HcmV?d00001 diff --git a/src/mainboard/lenovo/t400/variants/r500/gpio.c b/src/mainboard/lenovo/t400/variants/r500/gpio.c new file mode 100644 index 0000000000..a1cc4586da --- /dev/null +++ b/src/mainboard/lenovo/t400/variants/r500/gpio.c @@ -0,0 +1,131 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_GPIO, + .gpio3 = GPIO_MODE_GPIO, + .gpio4 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_GPIO, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_GPIO, + .gpio12 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_GPIO, + .gpio19 = GPIO_MODE_GPIO, + .gpio20 = GPIO_MODE_GPIO, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio24 = GPIO_MODE_GPIO, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_INPUT, + .gpio5 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_INPUT, + .gpio9 = GPIO_DIR_OUTPUT, + .gpio12 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio18 = GPIO_DIR_OUTPUT, + .gpio19 = GPIO_DIR_INPUT, + .gpio20 = GPIO_DIR_OUTPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_OUTPUT, + .gpio28 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio9 = GPIO_LEVEL_HIGH, + .gpio12 = GPIO_LEVEL_LOW, + .gpio18 = GPIO_LEVEL_HIGH, + .gpio20 = GPIO_LEVEL_HIGH, + .gpio24 = GPIO_LEVEL_HIGH, + .gpio27 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio1 = GPIO_INVERT, + .gpio8 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio41 = GPIO_MODE_GPIO, + .gpio42 = GPIO_MODE_GPIO, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio56 = GPIO_MODE_GPIO, + .gpio57 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_OUTPUT, + .gpio36 = GPIO_DIR_INPUT, + .gpio37 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio41 = GPIO_DIR_OUTPUT, + .gpio42 = GPIO_DIR_OUTPUT, + .gpio48 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_OUTPUT, + .gpio56 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio33 = GPIO_LEVEL_HIGH, + .gpio34 = GPIO_LEVEL_LOW, + .gpio41 = GPIO_LEVEL_HIGH, + .gpio42 = GPIO_LEVEL_HIGH, + .gpio49 = GPIO_LEVEL_HIGH, +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + }, +}; diff --git a/src/mainboard/lenovo/t400/variants/r500/overridetree.cb b/src/mainboard/lenovo/t400/variants/r500/overridetree.cb new file mode 100644 index 0000000000..65b9387f59 --- /dev/null +++ b/src/mainboard/lenovo/t400/variants/r500/overridetree.cb @@ -0,0 +1,45 @@ +chip northbridge/intel/gm45 + device domain 0 on + device pci 03.0 off end + chip southbridge/intel/i82801ix + register "sata_clock_request" = "1" + # Enable PCIe ports 1,2,4,5,6 as slots (Mini * PCIe). + register "pcie_slot_implemented" = "0x3b" + # Set power limits to 10 * 10^0 watts. + # Maybe we should set less for Mini PCIe. + register "pcie_power_limits" = "{ { 41, 0 }, { 41, 0 }, { 0, 0 }, { 41, 0 }, { 41, 0 }, { 41, 0 } }" + register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 1, 0, 0 }" + device pci 19.0 off end # LAN + device pci 1c.2 off end # PCIe Port #3 + device pci 1c.4 on # PCIe Port #5 + subsystemid 0x17aa 0x20f3 + end + device pci 1c.5 on # PCIe Port #6 + subsystemid 0x17aa 0x20f3 # Ethernet NIC + end + device pci 1f.0 on # LPC bridge + subsystemid 0x17aa 0x20f5 + chip ec/lenovo/h8 + register "config1" = "0x05" + register "config3" = "0x40" + register "event6_enable" = "0x87" + register "event7_enable" = "0x09" + register "event8_enable" = "0x5b" + register "eventa_enable" = "0x83" + register "eventb_enable" = "0x00" + end + end + device pci 1f.3 on # SMBus + subsystemid 0x17aa 0x20f9 + ioapic_irq 2 INTC 0x12 + # eeprom, 4 virtual devices, same chip + chip drivers/i2c/at24rf08c + device i2c 54 on end + device i2c 55 on end + device i2c 56 on end + device i2c 57 on end + end + end + end + end +end diff --git a/src/mainboard/lenovo/t400/variants/t400/Makefile.inc b/src/mainboard/lenovo/t400/variants/t400/Makefile.inc new file mode 100644 index 0000000000..3dae61e8a8 --- /dev/null +++ b/src/mainboard/lenovo/t400/variants/t400/Makefile.inc @@ -0,0 +1 @@ +romstage-y += gpio.c diff --git a/src/mainboard/lenovo/t400/data.vbt b/src/mainboard/lenovo/t400/variants/t400/data.vbt similarity index 100% rename from src/mainboard/lenovo/t400/data.vbt rename to src/mainboard/lenovo/t400/variants/t400/data.vbt diff --git a/src/mainboard/lenovo/t400/gpio.c b/src/mainboard/lenovo/t400/variants/t400/gpio.c similarity index 100% rename from src/mainboard/lenovo/t400/gpio.c rename to src/mainboard/lenovo/t400/variants/t400/gpio.c diff --git a/src/mainboard/lenovo/t400/variants/t400/overridetree.cb b/src/mainboard/lenovo/t400/variants/t400/overridetree.cb new file mode 100644 index 0000000000..64cb6db03f --- /dev/null +++ b/src/mainboard/lenovo/t400/variants/t400/overridetree.cb @@ -0,0 +1,43 @@ +chip northbridge/intel/gm45 + device domain 0 on + chip southbridge/intel/i82801ix + device pci 1f.0 on # LPC bridge + subsystemid 0x17aa 0x20f5 + chip drivers/lenovo/hybrid_graphics + device pnp ff.f on end # dummy + + register "detect_gpio" = "21" + + register "has_panel_hybrid_gpio" = "1" + register "panel_hybrid_gpio" = "22" + register "panel_integrated_lvl" = "0" + + register "has_backlight_gpio" = "1" + register "backlight_gpio" = "19" + register "backlight_integrated_lvl" = "0" + + register "has_dgpu_power_gpio" = "1" + register "dgpu_power_gpio" = "49" + register "dgpu_power_off_lvl" = "0" + + register "has_thinker1" = "0" + end + end + device pci 1f.3 on # SMBus + subsystemid 0x17aa 0x20f9 + ioapic_irq 2 INTC 0x12 + # eeprom, 8 virtual devices, same chip + chip drivers/i2c/at24rf08c + device i2c 54 on end + device i2c 55 on end + device i2c 56 on end + device i2c 57 on end + device i2c 5c on end + device i2c 5d on end + device i2c 5e on end + device i2c 5f on end + end + end + end + end +end From 7f8a57e96ae8a0ad41bc6024c9fa5a0c14282f15 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Thu, 28 Jun 2018 16:58:52 +0300 Subject: [PATCH 117/331] soc/amd/common: Refactor AmdCreateStruct() use MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit AmdCreateStruct() and AmdReleaseStruct() are equally bad when it comes to lack of correct function declarations for definitions found in vendorcode binaryPI/AGESA.c. Replace these with calls that go through the common module_dispatch() functions. Change-Id: I611bcbe2a71fb65c8eb759a9dc74cbd9cb74136e Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/31486 Reviewed-by: Richard Spiegel Reviewed-by: Paul Menzel Tested-by: build bot (Jenkins) --- src/soc/amd/common/block/pi/agesawrapper.c | 143 +++++++++--------- .../amd/pi/00670F00/binaryPI/AGESA.c | 27 ---- 2 files changed, 70 insertions(+), 100 deletions(-) diff --git a/src/soc/amd/common/block/pi/agesawrapper.c b/src/soc/amd/common/block/pi/agesawrapper.c index 5f58346625..da6de00568 100644 --- a/src/soc/amd/common/block/pi/agesawrapper.c +++ b/src/soc/amd/common/block/pi/agesawrapper.c @@ -65,41 +65,60 @@ AGESA_STATUS amd_late_run_ap_task(AP_EXE_PARAMS *ApExeParams) return module_dispatch(AMD_LATE_RUN_AP_TASK, StdHeader); } -static void *create_struct(AMD_INTERFACE_PARAMS *interface_struct) +static void *amd_create_struct(AMD_INTERFACE_PARAMS *aip, + AGESA_STRUCT_NAME func, void *buf, size_t len) { AMD_CONFIG_PARAMS *StdHeader; + AGESA_STATUS status; /* Should clone entire StdHeader here. */ - interface_struct->StdHeader.CalloutPtr = &GetBiosCallout; + memset(aip, 0, sizeof(*aip)); + aip->StdHeader.CalloutPtr = &GetBiosCallout; - AGESA_STATUS status = AmdCreateStruct(interface_struct); + /* If we provide the buffer, API expects it to have + StdHeader already filled. */ + if (buf != NULL && len >= sizeof(*StdHeader)) { + memcpy(buf, &aip->StdHeader, sizeof(*StdHeader)); + aip->AllocationMethod = ByHost; + aip->NewStructPtr = buf; + aip->NewStructSize = len; + } else { + if (ENV_ROMSTAGE) + aip->AllocationMethod = PreMemHeap; + if (ENV_RAMSTAGE) + aip->AllocationMethod = PostMemDram; + } + + aip->AgesaFunctionName = func; + status = module_dispatch(AMD_CREATE_STRUCT, &aip->StdHeader); if (status != AGESA_SUCCESS) { printk(BIOS_ERR, "Error: AmdCreateStruct() for 0x%x returned 0x%x. " "Proper system initialization may not be possible.\n", - interface_struct->AgesaFunctionName, status); + aip->AgesaFunctionName, status); } - if (!interface_struct->NewStructPtr) /* Avoid NULL pointer usage */ + if (!aip->NewStructPtr) die("No AGESA structure created"); - StdHeader = interface_struct->NewStructPtr; - StdHeader->Func = interface_struct->AgesaFunctionName; + StdHeader = aip->NewStructPtr; + StdHeader->Func = aip->AgesaFunctionName; return StdHeader; } +static AGESA_STATUS amd_release_struct(AMD_INTERFACE_PARAMS *aip) +{ + return module_dispatch(AMD_RELEASE_STRUCT, &aip->StdHeader); +} + static AGESA_STATUS amd_init_reset(void) { AGESA_STATUS status; AMD_RESET_PARAMS _ResetParams; - AMD_INTERFACE_PARAMS AmdParamStruct = { - .AgesaFunctionName = AMD_INIT_RESET, - .AllocationMethod = ByHost, - .NewStructSize = sizeof(AMD_RESET_PARAMS), - .NewStructPtr = &_ResetParams, - }; + AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_RESET_PARAMS *ResetParams = create_struct(&AmdParamStruct); + AMD_RESET_PARAMS *ResetParams = amd_create_struct(&AmdParamStruct, + AMD_INIT_RESET, &_ResetParams, sizeof(AMD_RESET_PARAMS)); SetFchResetParams(&ResetParams->FchInterface); @@ -107,19 +126,17 @@ static AGESA_STATUS amd_init_reset(void) status = amd_dispatch(ResetParams); timestamp_add_now(TS_AGESA_INIT_RESET_DONE); - AmdReleaseStruct(&AmdParamStruct); + amd_release_struct(&AmdParamStruct); return status; } static AGESA_STATUS amd_init_early(void) { AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct = { - .AgesaFunctionName = AMD_INIT_EARLY, - .AllocationMethod = PreMemHeap, - }; + AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_EARLY_PARAMS *EarlyParams = create_struct(&AmdParamStruct); + AMD_EARLY_PARAMS *EarlyParams = amd_create_struct(&AmdParamStruct, + AMD_INIT_EARLY, NULL, 0); soc_customize_init_early(EarlyParams); OemCustomizeInitEarly(EarlyParams); @@ -128,7 +145,7 @@ static AGESA_STATUS amd_init_early(void) status = amd_dispatch(EarlyParams); timestamp_add_now(TS_AGESA_INIT_EARLY_DONE); - AmdReleaseStruct(&AmdParamStruct); + amd_release_struct(&AmdParamStruct); return status; } @@ -169,12 +186,10 @@ static void print_init_post_settings(AMD_POST_PARAMS *parms) static AGESA_STATUS amd_init_post(void) { AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct = { - .AgesaFunctionName = AMD_INIT_POST, - .AllocationMethod = PreMemHeap, - }; + AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_POST_PARAMS *PostParams = create_struct(&AmdParamStruct); + AMD_POST_PARAMS *PostParams = amd_create_struct(&AmdParamStruct, + AMD_INIT_POST, NULL, 0); PostParams->MemConfig.UmaMode = CONFIG(GFXUMA) ? UMA_AUTO : UMA_NONE; PostParams->MemConfig.UmaSize = 0; @@ -214,7 +229,7 @@ static AGESA_STATUS amd_init_post(void) print_init_post_settings(PostParams); - AmdReleaseStruct(&AmdParamStruct); + amd_release_struct(&AmdParamStruct); return status; } @@ -222,12 +237,10 @@ static AGESA_STATUS amd_init_post(void) static AGESA_STATUS amd_init_env(void) { AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct = { - .AgesaFunctionName = AMD_INIT_ENV, - .AllocationMethod = PostMemDram, - }; + AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_ENV_PARAMS *EnvParams = create_struct(&AmdParamStruct); + AMD_ENV_PARAMS *EnvParams = amd_create_struct(&AmdParamStruct, + AMD_INIT_ENV, NULL, 0); SetFchEnvParams(&EnvParams->FchInterface); SetNbEnvParams(&EnvParams->GnbEnvConfiguration); @@ -236,7 +249,7 @@ static AGESA_STATUS amd_init_env(void) status = amd_dispatch(EnvParams); timestamp_add_now(TS_AGESA_INIT_ENV_DONE); - AmdReleaseStruct(&AmdParamStruct); + amd_release_struct(&AmdParamStruct); return status; } @@ -270,15 +283,13 @@ void *agesawrapper_getlateinitptr(int pick) static AGESA_STATUS amd_init_mid(void) { AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct = { - .AgesaFunctionName = AMD_INIT_MID, - .AllocationMethod = PostMemDram, - }; + AMD_INTERFACE_PARAMS AmdParamStruct; /* Enable MMIO on AMD CPU Address Map Controller */ amd_initcpuio(); - AMD_MID_PARAMS *MidParams = create_struct(&AmdParamStruct); + AMD_MID_PARAMS *MidParams = amd_create_struct(&AmdParamStruct, + AMD_INIT_MID, NULL, 0); SetFchMidParams(&MidParams->FchInterface); SetNbMidParams(&MidParams->GnbMidConfiguration); @@ -287,7 +298,7 @@ static AGESA_STATUS amd_init_mid(void) status = amd_dispatch(MidParams); timestamp_add_now(TS_AGESA_INIT_MID_DONE); - AmdReleaseStruct(&AmdParamStruct); + amd_release_struct(&AmdParamStruct); return status; } @@ -295,16 +306,14 @@ static AGESA_STATUS amd_init_mid(void) static AGESA_STATUS amd_init_late(void) { AGESA_STATUS Status; - AMD_INTERFACE_PARAMS AmdParamStruct = { - .AgesaFunctionName = AMD_INIT_LATE, - .AllocationMethod = PostMemDram, - }; + AMD_INTERFACE_PARAMS AmdParamStruct; /* * NOTE: if not call amdcreatestruct, the initializer * (AmdInitLateInitializer) would not be called. */ - AMD_LATE_PARAMS *LateParams = create_struct(&AmdParamStruct); + AMD_LATE_PARAMS *LateParams = amd_create_struct(&AmdParamStruct, + AMD_INIT_LATE, NULL, 0); const struct device *dev = pcidev_path_on_root(IOMMU_DEVFN); if (dev && dev->enabled) { @@ -333,19 +342,17 @@ static AGESA_STATUS amd_init_late(void) AcpiSlit, AcpiWheaMce, AcpiWheaCmc, AcpiAlib, AcpiIvrs, __func__); - AmdReleaseStruct(&AmdParamStruct); + amd_release_struct(&AmdParamStruct); return Status; } static AGESA_STATUS amd_init_rtb(void) { AGESA_STATUS Status; - AMD_INTERFACE_PARAMS AmdParamStruct = { - .AgesaFunctionName = AMD_INIT_RTB, - .AllocationMethod = PostMemDram, - }; + AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_RTB_PARAMS *RtbParams = create_struct(&AmdParamStruct); + AMD_RTB_PARAMS *RtbParams = amd_create_struct(&AmdParamStruct, + AMD_INIT_RTB, NULL, 0); timestamp_add_now(TS_AGESA_INIT_RTB_START); Status = amd_dispatch(RtbParams); @@ -357,7 +364,7 @@ static AGESA_STATUS amd_init_rtb(void) RtbParams->S3DataBlock.VolatileStorageSize)) printk(BIOS_ERR, "S3 data not saved, resuming impossible\n"); - AmdReleaseStruct(&AmdParamStruct); + amd_release_struct(&AmdParamStruct); return Status; } @@ -365,13 +372,11 @@ static AGESA_STATUS amd_init_rtb(void) static AGESA_STATUS amd_init_resume(void) { AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct = { - .AgesaFunctionName = AMD_INIT_RESUME, - .AllocationMethod = PreMemHeap, - }; + AMD_INTERFACE_PARAMS AmdParamStruct; size_t nv_size; - AMD_RESUME_PARAMS *InitResumeParams = create_struct(&AmdParamStruct); + AMD_RESUME_PARAMS *InitResumeParams = amd_create_struct(&AmdParamStruct, + AMD_INIT_RESUME, NULL, 0); get_s3nv_info(&InitResumeParams->S3DataBlock.NvStorage, &nv_size); InitResumeParams->S3DataBlock.NvStorageSize = nv_size; @@ -380,7 +385,7 @@ static AGESA_STATUS amd_init_resume(void) status = amd_dispatch(InitResumeParams); timestamp_add_now(TS_AGESA_INIT_RESUME_DONE); - AmdReleaseStruct(&AmdParamStruct); + amd_release_struct(&AmdParamStruct); return status; } @@ -389,17 +394,13 @@ static AGESA_STATUS amd_s3late_restore(void) { AGESA_STATUS Status; AMD_S3LATE_PARAMS _S3LateParams; - AMD_INTERFACE_PARAMS AmdParamStruct = { - .AgesaFunctionName = AMD_S3LATE_RESTORE, - .AllocationMethod = ByHost, - .NewStructSize = sizeof(AMD_S3LATE_PARAMS), - .NewStructPtr = &_S3LateParams, - }; + AMD_INTERFACE_PARAMS AmdParamStruct; size_t vol_size; amd_initcpuio(); - AMD_S3LATE_PARAMS *S3LateParams = create_struct(&AmdParamStruct); + AMD_S3LATE_PARAMS *S3LateParams = amd_create_struct(&AmdParamStruct, + AMD_S3LATE_RESTORE, &_S3LateParams, sizeof(AMD_S3LATE_PARAMS)); get_s3vol_info(&S3LateParams->S3DataBlock.VolatileStorage, &vol_size); S3LateParams->S3DataBlock.VolatileStorageSize = vol_size; @@ -408,7 +409,7 @@ static AGESA_STATUS amd_s3late_restore(void) Status = amd_dispatch(S3LateParams); timestamp_add_now(TS_AGESA_S3_LATE_DONE); - AmdReleaseStruct(&AmdParamStruct); + amd_release_struct(&AmdParamStruct); return Status; } @@ -417,15 +418,11 @@ static AGESA_STATUS amd_s3final_restore(void) { AGESA_STATUS Status; AMD_S3FINAL_PARAMS _S3FinalParams; - AMD_INTERFACE_PARAMS AmdParamStruct = { - .AgesaFunctionName = AMD_S3FINAL_RESTORE, - .AllocationMethod = ByHost, - .NewStructSize = sizeof(AMD_S3FINAL_PARAMS), - .NewStructPtr = &_S3FinalParams, - }; + AMD_INTERFACE_PARAMS AmdParamStruct; size_t vol_size; - AMD_S3FINAL_PARAMS *S3FinalParams = create_struct(&AmdParamStruct); + AMD_S3FINAL_PARAMS *S3FinalParams = amd_create_struct(&AmdParamStruct, + AMD_S3FINAL_RESTORE, &_S3FinalParams, sizeof(AMD_S3FINAL_PARAMS)); get_s3vol_info(&S3FinalParams->S3DataBlock.VolatileStorage, &vol_size); S3FinalParams->S3DataBlock.VolatileStorageSize = vol_size; @@ -434,7 +431,7 @@ static AGESA_STATUS amd_s3final_restore(void) Status = amd_dispatch(S3FinalParams); timestamp_add_now(TS_AGESA_S3_FINAL_DONE); - AmdReleaseStruct(&AmdParamStruct); + amd_release_struct(&AmdParamStruct); return Status; } diff --git a/src/vendorcode/amd/pi/00670F00/binaryPI/AGESA.c b/src/vendorcode/amd/pi/00670F00/binaryPI/AGESA.c index e17cedcb64..da89ce8e6d 100644 --- a/src/vendorcode/amd/pi/00670F00/binaryPI/AGESA.c +++ b/src/vendorcode/amd/pi/00670F00/binaryPI/AGESA.c @@ -45,30 +45,3 @@ CONST UINT32 ImageSignature = IMAGE_SIGNATURE; CONST UINT32 ModuleSignature = MODULE_SIGNATURE; CONST CHAR8 ModuleIdentifier[8] = AGESA_ID; -/********************************************************************** - * Interface call: AmdCreateStruct - **********************************************************************/ -AGESA_STATUS -AmdCreateStruct ( - IN OUT AMD_INTERFACE_PARAMS *InterfaceParams - ) -{ - MODULE_ENTRY Dispatcher = agesa_get_dispatcher(); - InterfaceParams->StdHeader.Func = AMD_CREATE_STRUCT; - if (!Dispatcher) return AGESA_UNSUPPORTED; - return Dispatcher(InterfaceParams); -} - -/********************************************************************** - * Interface call: AmdReleaseStruct - **********************************************************************/ -AGESA_STATUS -AmdReleaseStruct ( - IN OUT AMD_INTERFACE_PARAMS *InterfaceParams - ) -{ - MODULE_ENTRY Dispatcher = agesa_get_dispatcher(); - InterfaceParams->StdHeader.Func = AMD_RELEASE_STRUCT; - if (!Dispatcher) return AGESA_UNSUPPORTED; - return Dispatcher(InterfaceParams); -} From 1dda496a7419664279ec5cb4490b3a4598187a36 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Thu, 14 Jun 2018 09:38:44 +0300 Subject: [PATCH 118/331] binaryPI/00670F000: Remove AGESA.c file MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: Id48de8b2f6feb6c29d745140c872215faa32eb37 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/31487 Reviewed-by: Richard Spiegel Reviewed-by: Paul Menzel Tested-by: build bot (Jenkins) --- .../amd/pi/00670F00/binaryPI/AGESA.c | 47 ------------------- 1 file changed, 47 deletions(-) delete mode 100644 src/vendorcode/amd/pi/00670F00/binaryPI/AGESA.c diff --git a/src/vendorcode/amd/pi/00670F00/binaryPI/AGESA.c b/src/vendorcode/amd/pi/00670F00/binaryPI/AGESA.c deleted file mode 100644 index da89ce8e6d..0000000000 --- a/src/vendorcode/amd/pi/00670F00/binaryPI/AGESA.c +++ /dev/null @@ -1,47 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Agesa structures and definitions - * - * Contains AMD AGESA core interface - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Include - * @e \$Revision: 85818 $ @e \$Date: 2013-01-11 17:04:21 -0600 (Fri, 11 Jan 2013) $ - */ -/***************************************************************************** - * - * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ***************************************************************************/ -#include - -CONST UINT32 ImageSignature = IMAGE_SIGNATURE; -CONST UINT32 ModuleSignature = MODULE_SIGNATURE; -CONST CHAR8 ModuleIdentifier[8] = AGESA_ID; - From 40a85f85c68902f8e16f3088bd94ab5ab83e7749 Mon Sep 17 00:00:00 2001 From: Jacob Garber Date: Fri, 17 May 2019 14:55:04 -0600 Subject: [PATCH 119/331] util/romcc: Use 64 bit integers when shifting 'used_indices' is 64 bits wide, so use a fixed-width type to make that clear. As such, 'index' can have a value of up to 63, so use a 64 bit integer when doing the shifts to prevent overflow. Found-by: Coverity Scan CID 1287090 Signed-off-by: Jacob Garber Change-Id: Ibd089df6be60c8ea46da11e5e83cd58b2e2c54d6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32854 Reviewed-by: Patrick Georgi Tested-by: build bot (Jenkins) --- util/romcc/romcc.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/util/romcc/romcc.c b/util/romcc/romcc.c index c6507dcad9..97cc2191e7 100644 --- a/util/romcc/romcc.c +++ b/util/romcc/romcc.c @@ -14111,7 +14111,7 @@ static void compute_closure_variables(struct compile_state *state, struct block *block; struct triple *old_result, *first, *ins; size_t count, idx; - unsigned long used_indices; + uint64_t used_indices; int i, max_index; #define MAX_INDICES (sizeof(used_indices)*CHAR_BIT) #define ID_BITS(X) ((X) & (TRIPLE_FLAG_LOCAL -1)) @@ -14217,11 +14217,11 @@ static void compute_closure_variables(struct compile_state *state, if (index >= MAX_INDICES) { internal_error(state, ins, "index unexpectedly large"); } - if (used_indices & (1 << index)) { + if (used_indices & ((uint64_t)1 << index)) { internal_error(state, ins, "index previously used?"); } /* Remember which indices have been used */ - used_indices |= (1 << index); + used_indices |= ((uint64_t)1 << index); if (index > max_index) { max_index = index; } @@ -14249,7 +14249,7 @@ static void compute_closure_variables(struct compile_state *state, } info[ID_BITS(ins->id)].index = index; /* Remember which indices have been used */ - used_indices |= (1 << index); + used_indices |= ((uint64_t)1 << index); if (index > max_index) { max_index = index; } @@ -14263,7 +14263,7 @@ static void compute_closure_variables(struct compile_state *state, for(i = 0; i <= max_index; i++) { struct triple *var; var = 0; - if (used_indices & (1 << i)) { + if (used_indices & ((uint64_t)1 << i)) { for(set = vars; set; set = set->next) { int index; index = info[ID_BITS(set->member->id)].index; From b79d2dee2b2f294aac97dad849909d7bfb892c76 Mon Sep 17 00:00:00 2001 From: Jacob Garber Date: Thu, 16 May 2019 22:00:27 -0600 Subject: [PATCH 120/331] util/romcc: Free variable after it is used Free 'arg_type' after it is used to prevent a memory leak. Found-by: Coverity Scan CID 1129114 Signed-off-by: Jacob Garber Change-Id: I5e8661547bb7623463ed23fc45269049ffb8c50e Reviewed-on: https://review.coreboot.org/c/coreboot/+/32841 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- util/romcc/romcc.c | 1 + 1 file changed, 1 insertion(+) diff --git a/util/romcc/romcc.c b/util/romcc/romcc.c index 97cc2191e7..bf0510a49f 100644 --- a/util/romcc/romcc.c +++ b/util/romcc/romcc.c @@ -11236,6 +11236,7 @@ static struct triple *relational_expr(struct compile_state *state) arg_type = arithmetic_result(state, left, right); sign = is_signed(arg_type); + xfree(arg_type); op = -1; switch(tok) { case TOK_LESS: op = sign? OP_SLESS : OP_ULESS; break; From ae8301fddbb5c8456b738bbeab94b98ae3eb06b6 Mon Sep 17 00:00:00 2001 From: Jacob Garber Date: Fri, 17 May 2019 12:51:47 -0600 Subject: [PATCH 121/331] util/romcc: Fix parsing of empty string literal The corner case of an empty string literal was causing romcc to segfault. This checks if the literal is empty, and if so allocates a size one buffer for the terminating null character. A test case for this is added to ensure it doesn't happen again. Found-by: Coverity CID 1129099 Signed-off-by: Jacob Garber Change-Id: I067160a3b9998184f44e4878ef6269f372fe68bb Reviewed-on: https://review.coreboot.org/c/coreboot/+/32852 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- util/romcc/romcc.c | 9 +++++++++ util/romcc/tests/simple_test87.c | 4 ++++ 2 files changed, 13 insertions(+) create mode 100644 util/romcc/tests/simple_test87.c diff --git a/util/romcc/romcc.c b/util/romcc/romcc.c index bf0510a49f..b9ec835f6f 100644 --- a/util/romcc/romcc.c +++ b/util/romcc/romcc.c @@ -10782,6 +10782,15 @@ static struct triple *string_constant(struct compile_state *state) } while(str < end); type->elements = ptr - buf; } while(peek(state) == TOK_LIT_STRING); + + /* buf contains the allocated buffer for the string constant. However, + if buf is NULL, then the string constant is empty, but we still + need to allocate one byte for the null character. */ + if (buf == NULL) { + buf = xmalloc(1, "string_constant"); + ptr = buf; + } + *ptr = '\0'; type->elements += 1; def = triple(state, OP_BLOBCONST, type, 0, 0); diff --git a/util/romcc/tests/simple_test87.c b/util/romcc/tests/simple_test87.c new file mode 100644 index 0000000000..6a1148c46a --- /dev/null +++ b/util/romcc/tests/simple_test87.c @@ -0,0 +1,4 @@ +static void main(void) +{ + char *x = ""; +} From b7f27abb3bc4ef83e4250c9ac3480ca5fd7ec7cb Mon Sep 17 00:00:00 2001 From: Kane Chen Date: Thu, 16 May 2019 18:52:36 +0800 Subject: [PATCH 122/331] mb/google/kohaku: Set ACPI_GPIO_IRQ_EDGE_BOTH for headset INT Currently, GPP_H0 gpio input rout is set to GPI_INT. So, ACPI_GPIO_IRQ is required for GPP_H0 in devicetree This change also aligns hatch's setting. BUG=b:131742713 TEST=headset is working Change-Id: Ie1264641bc4dfa5f98b6dab2d6f2133a6f9cbdb8 Signed-off-by: Kane Chen Reviewed-on: https://review.coreboot.org/c/coreboot/+/32845 Tested-by: build bot (Jenkins) Reviewed-by: Ben Kao Reviewed-by: Furquan Shaikh Reviewed-by: Paul Fagerburg Reviewed-by: Tim Wawrzynczak --- src/mainboard/google/hatch/variants/kohaku/overridetree.cb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/google/hatch/variants/kohaku/overridetree.cb b/src/mainboard/google/hatch/variants/kohaku/overridetree.cb index 9546420e35..69875bdde2 100644 --- a/src/mainboard/google/hatch/variants/kohaku/overridetree.cb +++ b/src/mainboard/google/hatch/variants/kohaku/overridetree.cb @@ -90,7 +90,7 @@ chip soc/intel/cannonlake chip drivers/i2c/da7219 # TODO: these settings were copied from another board # with the same chip. verify the settings - register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_H0_IRQ)" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_H0)" register "btn_cfg" = "50" register "mic_det_thr" = "500" register "jack_ins_deb" = "20" From a172228b7a66454a34b331fff10d6d0bb03ab634 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Mon, 20 May 2019 07:46:18 +0200 Subject: [PATCH 123/331] src/arch/arm64: Remove variable set but not used Change-Id: I4fe5771dd1ebf3d2a981dab08e98f1c018d14133 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/32888 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner --- src/arch/arm64/boot.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/src/arch/arm64/boot.c b/src/arch/arm64/boot.c index d17a20d628..7fbc525a18 100644 --- a/src/arch/arm64/boot.c +++ b/src/arch/arm64/boot.c @@ -38,7 +38,6 @@ static void run_payload(struct prog *prog) void arch_prog_run(struct prog *prog) { void (*doit)(void *); - void *arg; if (ENV_RAMSTAGE && prog_type(prog) == PROG_PAYLOAD) { run_payload(prog); @@ -46,7 +45,6 @@ void arch_prog_run(struct prog *prog) } doit = prog_entry(prog); - arg = prog_entry_arg(prog); doit(prog_entry_arg(prog)); } From b19de28c9889675125183f350e2a35f60e142562 Mon Sep 17 00:00:00 2001 From: Kevin Chiu Date: Thu, 16 May 2019 11:16:18 +0800 Subject: [PATCH 124/331] mb/google/octopus: Create Garg variant This commit creates a garg variant for Octopus. The initial settings override the baseboard was copied from variant bobba. BUG=b:132668378 BRANCH=master TEST=emerge-octopus coreboot Change-Id: I9a36bc5dc3d2b891b1bce86015aa264894d1434b Signed-off-by: Kevin Chiu Reviewed-on: https://review.coreboot.org/c/coreboot/+/32835 Tested-by: build bot (Jenkins) Reviewed-by: Sheng-Liang Pan Reviewed-by: Justin TerAvest --- src/mainboard/google/octopus/Kconfig | 3 + src/mainboard/google/octopus/Kconfig.name | 6 + .../google/octopus/variants/garg/Makefile.inc | 3 + .../google/octopus/variants/garg/gpio.c | 37 ++++ .../garg/include/variant/acpi/dptf.asl | 16 ++ .../variants/garg/include/variant/ec.h | 24 +++ .../variants/garg/include/variant/gpio.h | 21 ++ .../octopus/variants/garg/overridetree.cb | 180 ++++++++++++++++++ 8 files changed, 290 insertions(+) create mode 100644 src/mainboard/google/octopus/variants/garg/Makefile.inc create mode 100644 src/mainboard/google/octopus/variants/garg/gpio.c create mode 100644 src/mainboard/google/octopus/variants/garg/include/variant/acpi/dptf.asl create mode 100644 src/mainboard/google/octopus/variants/garg/include/variant/ec.h create mode 100644 src/mainboard/google/octopus/variants/garg/include/variant/gpio.h create mode 100644 src/mainboard/google/octopus/variants/garg/overridetree.cb diff --git a/src/mainboard/google/octopus/Kconfig b/src/mainboard/google/octopus/Kconfig index 9c0a2f771e..48753ed4b1 100644 --- a/src/mainboard/google/octopus/Kconfig +++ b/src/mainboard/google/octopus/Kconfig @@ -59,6 +59,7 @@ config VARIANT_DIR default "casta" if BOARD_GOOGLE_CASTA default "bloog" if BOARD_GOOGLE_BLOOG default "octopus" if BOARD_GOOGLE_OCTOPUS + default "garg" if BOARD_GOOGLE_GARG config DEVICETREE string @@ -79,6 +80,7 @@ config MAINBOARD_PART_NUMBER default "Casta" if BOARD_GOOGLE_CASTA default "Bloog" if BOARD_GOOGLE_BLOOG default "Octopus" if BOARD_GOOGLE_OCTOPUS + default "Garg" if BOARD_GOOGLE_GARG config MAINBOARD_FAMILY string @@ -96,6 +98,7 @@ config GBB_HWID default "CASTA TEST 8105" if BOARD_GOOGLE_CASTA default "BLOOG TEST 2509" if BOARD_GOOGLE_BLOOG default "OCTOPUS TEST 6859" if BOARD_GOOGLE_OCTOPUS + default "GARG TEST 1337" if BOARD_GOOGLE_GARG config MAX_CPUS int diff --git a/src/mainboard/google/octopus/Kconfig.name b/src/mainboard/google/octopus/Kconfig.name index e5684e0268..b192134fb4 100644 --- a/src/mainboard/google/octopus/Kconfig.name +++ b/src/mainboard/google/octopus/Kconfig.name @@ -52,3 +52,9 @@ config BOARD_GOOGLE_BLOOG select BASEBOARD_OCTOPUS_LAPTOP select BOARD_GOOGLE_BASEBOARD_OCTOPUS select NHLT_DA7219 if INCLUDE_NHLT_BLOBS + +config BOARD_GOOGLE_GARG + bool "-> Garg" + select BASEBOARD_OCTOPUS_LAPTOP + select BOARD_GOOGLE_BASEBOARD_OCTOPUS + select NHLT_DA7219 if INCLUDE_NHLT_BLOBS diff --git a/src/mainboard/google/octopus/variants/garg/Makefile.inc b/src/mainboard/google/octopus/variants/garg/Makefile.inc new file mode 100644 index 0000000000..9fb63f5f43 --- /dev/null +++ b/src/mainboard/google/octopus/variants/garg/Makefile.inc @@ -0,0 +1,3 @@ +bootblock-y += gpio.c + +ramstage-y += gpio.c diff --git a/src/mainboard/google/octopus/variants/garg/gpio.c b/src/mainboard/google/octopus/variants/garg/gpio.c new file mode 100644 index 0000000000..a4362409b5 --- /dev/null +++ b/src/mainboard/google/octopus/variants/garg/gpio.c @@ -0,0 +1,37 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include + +static const struct pad_config default_override_table[] = { + PAD_NC(GPIO_104, UP_20K), + + /* EN_PP3300_TOUCHSCREEN */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_146, 0, DEEP, NONE, Tx0RxDCRx0, + DISPUPD), + + PAD_NC(GPIO_213, DN_20K), +}; + +const struct pad_config *variant_override_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(default_override_table); + + return default_override_table; +} diff --git a/src/mainboard/google/octopus/variants/garg/include/variant/acpi/dptf.asl b/src/mainboard/google/octopus/variants/garg/include/variant/acpi/dptf.asl new file mode 100644 index 0000000000..4f6497ab2d --- /dev/null +++ b/src/mainboard/google/octopus/variants/garg/include/variant/acpi/dptf.asl @@ -0,0 +1,16 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include diff --git a/src/mainboard/google/octopus/variants/garg/include/variant/ec.h b/src/mainboard/google/octopus/variants/garg/include/variant/ec.h new file mode 100644 index 0000000000..feb6c71655 --- /dev/null +++ b/src/mainboard/google/octopus/variants/garg/include/variant/ec.h @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef MAINBOARD_EC_H +#define MAINBOARD_EC_H + +#include + +/* Enable EC backed Keyboard Backlight in ACPI */ +#define EC_ENABLE_KEYBOARD_BACKLIGHT + +#endif diff --git a/src/mainboard/google/octopus/variants/garg/include/variant/gpio.h b/src/mainboard/google/octopus/variants/garg/include/variant/gpio.h new file mode 100644 index 0000000000..750b0d4ccc --- /dev/null +++ b/src/mainboard/google/octopus/variants/garg/include/variant/gpio.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef MAINBOARD_GPIO_H +#define MAINBOARD_GPIO_H + +#include + +#endif /* MAINBOARD_GPIO_H */ diff --git a/src/mainboard/google/octopus/variants/garg/overridetree.cb b/src/mainboard/google/octopus/variants/garg/overridetree.cb new file mode 100644 index 0000000000..0230a29a89 --- /dev/null +++ b/src/mainboard/google/octopus/variants/garg/overridetree.cb @@ -0,0 +1,180 @@ +chip soc/intel/apollolake + + # EMMC Tx CMD Delay + # Refer to EDS-Vol2-16.32. + # [14:8] steps of delay for DDR mode, each 125ps. + # [6:0] steps of delay for SDR mode, each 125ps. + register "emmc_tx_cmd_cntl" = "0x505" + + # EMMC TX DATA Delay 1 + # Refer to EDS-Vol2-16.33. + # [14:8] steps of delay for HS400, each 125ps. + # [6:0] steps of delay for SDR104/HS200, each 125ps. + register "emmc_tx_data_cntl1" = "0x0a0b" + + # EMMC TX DATA Delay 2 + # Refer to EDS-Vol2-16.34. + # [30:24] steps of delay for SDR50, each 125ps. + # [22:16] steps of delay for DDR50, each 125ps. + # [14:8] steps of delay for SDR25/HS50, each 125ps. + # [6:0] steps of delay for SDR12, each 125ps. + register "emmc_tx_data_cntl2" = "0x1c272828" + + # EMMC RX CMD/DATA Delay 1 + # Refer to EDS-Vol2-16.35. + # [30:24] steps of delay for SDR50, each 125ps. + # [22:16] steps of delay for DDR50, each 125ps. + # [14:8] steps of delay for SDR25/HS50, each 125ps. + # [6:0] steps of delay for SDR12, each 125ps. + register "emmc_rx_cmd_data_cntl1" = "0x00181b1a" + + # EMMC RX CMD/DATA Delay 2 + # Refer to EDS-Vol2-16.37. + # [17:16] stands for Rx Clock before Output Buffer + # [14:8] steps of delay for Auto Tuning Mode, each 125ps. + # [6:0] steps of delay for HS200, each 125ps. + register "emmc_rx_cmd_data_cntl2" = "0x10021" + + # EMMC Rx Strobe Delay + # Refer to EDS-Vol2-16.36. + # [14:8] Rx Strobe Delay DLL 1(HS400 Mode), each 125ps. + # [6:0] Rx Strobe Delay DLL 2(HS400 Mode), each 125ps. + register "emmc_rx_strobe_cntl" = "0x0a0a" + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| GSPI0 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| | before memory is up | + #| I2C0 | Digitizer | + #| I2C5 | Audio | + #| I2C6 | Trackpad | + #| I2C7 | Touchscreen | + #+-------------------+---------------------------+ + + register "tcc_offset" = "10" + + register "common_soc_config" = "{ + .gspi[0] = { + .speed_mhz = 1, + .early_init = 1, + }, + .i2c[0] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 88, + .fall_time_ns = 16, + }, + .i2c[5] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 104, + .fall_time_ns = 52, + }, + .i2c[6] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 66, + .fall_time_ns = 90, + .data_hold_time_ns = 350, + }, + .i2c[7] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 44, + .fall_time_ns = 90, + }, + }" + + device domain 0 on + device pci 16.0 on + chip drivers/i2c/hid + register "generic.hid" = ""WCOM50C1"" + register "generic.desc" = ""WCOM Digitizer"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_139_IRQ)" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_140)" + register "generic.reset_delay_ms" = "20" + register "generic.has_power_resource" = "1" + register "hid_desc_reg_offset" = "0x1" + device i2c 0x9 on end + end + chip drivers/generic/gpio_keys + register "name" = ""PENH"" + register "gpio" = "ACPI_GPIO_INPUT_ACTIVE_LOW(GPIO_145)" + register "key.dev_name" = ""EJCT"" + register "key.linux_code" = "SW_PEN_INSERTED" + register "key.linux_input_type" = "EV_SW" + register "key.label" = ""pen_eject"" + register "key.wake" = "GPE0_DW2_04" + register "key.wakeup_event_action" = "EV_ACT_DEASSERTED" + device generic 0 on end + end + end # - I2C 0 + device pci 17.1 on + chip drivers/i2c/da7219 + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_137_IRQ)" + register "btn_cfg" = "50" + register "mic_det_thr" = "500" + register "jack_ins_deb" = "20" + register "jack_det_rate" = ""32ms_64ms"" + register "jack_rem_deb" = "1" + register "a_d_btn_thr" = "0xa" + register "d_b_btn_thr" = "0x16" + register "b_c_btn_thr" = "0x21" + register "c_mic_btn_thr" = "0x3e" + register "btn_avg" = "4" + register "adc_1bit_rpt" = "1" + register "micbias_lvl" = "2600" + register "mic_amp_in_sel" = ""diff"" + device i2c 1a on end + end + end # - I2C 5 + device pci 17.2 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPIO_135_IRQ)" + register "wake" = "GPE0_DW3_27" + register "probed" = "1" + device i2c 15 on end + end + chip drivers/i2c/hid + register "generic.hid" = ""PNP0C50"" + register "generic.desc" = ""Synaptics Touchpad"" + register "generic.irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPIO_135_IRQ)" + register "generic.wake" = "GPE0_DW3_27" + register "generic.probed" = "1" + register "hid_desc_reg_offset" = "0x20" + device i2c 0x2c on end + end + end # - I2C 6 + device pci 17.3 on + chip drivers/i2c/generic + register "hid" = ""ELAN0001"" + register "desc" = ""ELAN Touchscreen"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPIO_212_IRQ)" + register "probed" = "1" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_105)" + register "reset_delay_ms" = "20" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_146)" + register "enable_delay_ms" = "1" + register "has_power_resource" = "1" + device i2c 10 on end + end + chip drivers/i2c/generic + register "hid" = ""RAYD0001"" + register "desc" = ""Raydium Touchscreen"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPIO_212_IRQ)" + register "probed" = "1" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_105)" + register "reset_delay_ms" = "1" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_146)" + register "enable_delay_ms" = "50" + register "has_power_resource" = "1" + device i2c 39 on end + end + end # - I2C 7 + end + + # Disable compliance mode + register "DisableComplianceMode" = "1" +end From b461865577ed57b4512c75e0becf44b6b7ed0922 Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Mon, 20 May 2019 16:28:49 +0200 Subject: [PATCH 125/331] Documentation: Add Rotundu Add information about flash and programming header. Change-Id: If34016e20dd580f92695bef5b67dd0c282b0b421 Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/c/coreboot/+/32894 Tested-by: build bot (Jenkins) Reviewed-by: Philipp Deppenwiese --- Documentation/mainboard/index.md | 1 + .../mainboard/opencellular/rotundu.md | 76 ++++++++++++++++++ .../mainboard/opencellular/rotundu_flash.jpg | Bin 0 -> 94737 bytes .../opencellular/rotundu_header2.jpg | Bin 0 -> 56605 bytes .../mainboard/opencellular/rotundu_j16.png | Bin 0 -> 20835 bytes 5 files changed, 77 insertions(+) create mode 100644 Documentation/mainboard/opencellular/rotundu.md create mode 100644 Documentation/mainboard/opencellular/rotundu_flash.jpg create mode 100644 Documentation/mainboard/opencellular/rotundu_header2.jpg create mode 100644 Documentation/mainboard/opencellular/rotundu_j16.png diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md index 9af5c80883..fb637c423b 100644 --- a/Documentation/mainboard/index.md +++ b/Documentation/mainboard/index.md @@ -44,6 +44,7 @@ The boards in this section are not real mainboards, but emulators. ## Open Cellular - [Elgon](opencellular/elgon.md) +- [Rotundu](opencellular/rotundu.md) ## HP diff --git a/Documentation/mainboard/opencellular/rotundu.md b/Documentation/mainboard/opencellular/rotundu.md new file mode 100644 index 0000000000..8773e960a3 --- /dev/null +++ b/Documentation/mainboard/opencellular/rotundu.md @@ -0,0 +1,76 @@ +# Rutundu + +This page describes how to run coreboot on the [Rotundu] compute board +from [OpenCellular]. + +## TODO + +* Configure UART +* EC interface + +## Flashing coreboot + +```eval_rst ++---------------------+------------+ +| Type | Value | ++=====================+============+ +| Socketed flash | no | ++---------------------+------------+ +| Model | W25Q128 | ++---------------------+------------+ +| Size | 16 MiB | ++---------------------+------------+ +| In circuit flashing | yes | ++---------------------+------------+ +| Package | SOIC-8 | ++---------------------+------------+ +| Write protection | No | ++---------------------+------------+ +| Dual BIOS feature | No | ++---------------------+------------+ +| Internal flashing | yes | ++---------------------+------------+ +``` + +### Internal programming + +The SPI flash can be accessed using [flashrom]. + +### External programming + +The GBCv1 board does have a pinheader to flash the SOIC-8 in circuit. +Directly connecting a Pomona test-clip on the flash is also possible. + +**Closeup view of SOIC-8 flash IC** + +![][rotundu_flash] + +[rotundu_flash]: rotundu_flash.jpg + +**SPI header** + +![][rotundu_header2] + +[rotundu_header2]: rotundu_header2.jpg + +**SPI header pinout** + +Dediprog compatible pinout. + +![][rotundu_j16] + +[rotundu_j16]: rotundu_j16.png + +## Technology + +```eval_rst ++------------------+--------------------------------------------------+ +| SoC | Intel Baytrail | ++------------------+--------------------------------------------------+ +| Coprocessor | Intel ME | ++------------------+--------------------------------------------------+ +``` + +[Rotundu]: https://github.com/Telecominfraproject/OpenCellular +[OpenCellular]: https://code.fb.com/connectivity/introducing-opencellular-an-open-source-wireless-access-platform/ +[flashrom]: https://flashrom.org/Flashrom diff --git a/Documentation/mainboard/opencellular/rotundu_flash.jpg b/Documentation/mainboard/opencellular/rotundu_flash.jpg new file mode 100644 index 0000000000000000000000000000000000000000..f14617c17aa4bb36c10923a185c1eea1ba50ed3a GIT binary patch literal 94737 zcmb5VWmH>D7dDI+FYZtzp}1>+7KdO(0|`=Gf=kfSn?i991c%}foM6S;LUAh++=@ex zq7~Y^_s8?TYrX%!J!_pGXU;lv?Q3T5*=P1X|E>J@6^}+w8?23okB^6k|IqOMTgTJD zqaq`xASb1wAg7?Frg}`z%}7s2NB@+AiV+rY@w z%v9uV-TV;(sr}r>3T+r={m-WaNJ#D=Pcq|F`@%h(}9GP(#Q~h|h~hK#NaE zi~rvc9vdDW0pb79{y!lk!ow#ZCVA*%#s9zZ|GFM@A|NCp{%;MBk`Nz{fQFFf;f{ic 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zB_-jmkkxg024*jE&Ov|>bk%isVl6C!xclL@EiGVIVX-5JL)pHiiRj^BP9%~3N=%H} ztn$ulmcr*NEB!itx9PY$r%_z!^&mbmx8j$9u~Hj*7K>F>LY;O*CJprVrWY5J!9hw$ zSXioNZ0v0FXa^sxaln?!tiv0`E@Zj^26J}m{cWwbGybj=?#QdLlLSI{fChJCC+Mw` zV*`r_n;4h8gPTTp0bCviH=04lyRD;GeGePDK01|~=W zK9a*fZ@KV9Xh9&htb79NwzSYkF1awd_3>i=wm`SeF=u6{7!}?xb6W-c3{Cw(b|p6^ zW^W@8V@rN);tT*$#ULHlU*_ez3h=hJ5%ka0+@-m^OS%m#cva}i^8DGS(Z<`ANbFaB zhLMq&XVo#F+|B{G4c?I3_5Sn=j+z^l;abouTJ!E*R+Xas`-Pw#8z+rZ|39tkod%0Y~|C&;ZJF$3DZu|H0O6VTUoE#d!@ z_P@6ODgg$)4_&*-D(v|w34%h=ip7xC8Rb!u7IkVwagFTc`27ac^?2*Yi67bWoaNZGZOc}A3I^t;J$W_ zeA9V-XU&XEI~A3cw;8{Mh2aUQ1ScJJ)7_>8FJ)Ghis*#?s1=H|z za}$4F7GK$lx4mLaEgG|wR>ANAxij67;y&hUd&nxT$_ELd<6Ix6Q>W8Y5E(r^X(M{N z!0~#q1Bbf=3+u+U2BPr!ecC@9TB{k2L8HA1@b2XBL)ksp` z+}|}fKRmysP*SaVLj@bIit}4$p$@z_4 Date: Fri, 3 May 2019 20:07:56 +0530 Subject: [PATCH 126/331] soc/intel/skylake: Remove redundant mca_configure() in ramstage This patch removes redundant mca_configure() function call from ramstage to clear machine check exception. First time it's getting called from soc_core_init() function inside cpu.c file. TEST=Build and boot SKL/KBL/AML platform without any machine-check exception. Change-Id: I7e54fd07816c6317588ab6db06365937c4300ccd Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/32553 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh Reviewed-by: Nick Vaccaro --- src/soc/intel/skylake/finalize.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/src/soc/intel/skylake/finalize.c b/src/soc/intel/skylake/finalize.c index 5d7e1e0034..34738f28f1 100644 --- a/src/soc/intel/skylake/finalize.c +++ b/src/soc/intel/skylake/finalize.c @@ -20,7 +20,6 @@ #include #include #include -#include #include #include #include @@ -142,9 +141,6 @@ static void soc_finalize(void *unused) pch_finalize_script(dev); - printk(BIOS_DEBUG, "Clearing MCA.\n"); - mp_run_on_all_cpus(mca_configure, NULL, 17 * USECS_PER_SEC); - soc_lockdown(dev); printk(BIOS_DEBUG, "Finalizing SMM.\n"); From f91344cd07a4e9a4c2e183f00431b4fee05daf33 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Mon, 6 May 2019 19:23:26 +0530 Subject: [PATCH 127/331] soc/intel: Remove unused pointer argument in mca_configure() Change-Id: Iad3982d9db07a1f17ac39e87ff9c37956e40c258 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/32616 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph Reviewed-by: David Guckian Reviewed-by: Paul Menzel --- src/soc/intel/apollolake/cpu.c | 2 +- src/soc/intel/cannonlake/cpu.c | 2 +- src/soc/intel/common/block/cpu/cpulib.c | 2 +- src/soc/intel/common/block/include/intelblocks/cpulib.h | 2 +- src/soc/intel/denverton_ns/cpu.c | 2 +- src/soc/intel/icelake/cpu.c | 2 +- src/soc/intel/skylake/cpu.c | 2 +- 7 files changed, 7 insertions(+), 7 deletions(-) diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c index 651c20e43a..aad0f6b522 100644 --- a/src/soc/intel/apollolake/cpu.c +++ b/src/soc/intel/apollolake/cpu.c @@ -76,7 +76,7 @@ void soc_core_init(struct device *cpu) scope. For now every CPU clears every bank. */ if (CONFIG(SOC_INTEL_COMMON_BLOCK_SGX) || acpi_get_sleep_type() == ACPI_S5) - mca_configure(NULL); + mca_configure(); /* Set core MSRs */ reg_script_run(core_msr_script); diff --git a/src/soc/intel/cannonlake/cpu.c b/src/soc/intel/cannonlake/cpu.c index 8552424749..d98e2f5486 100644 --- a/src/soc/intel/cannonlake/cpu.c +++ b/src/soc/intel/cannonlake/cpu.c @@ -413,7 +413,7 @@ void soc_core_init(struct device *cpu) /* TODO(adurbin): This should only be done on a cold boot. Also, some * of these banks are core vs package scope. For now every CPU clears * every bank. */ - mca_configure(NULL); + mca_configure(); /* Enable the local CPU apics */ enable_lapic_tpr(); diff --git a/src/soc/intel/common/block/cpu/cpulib.c b/src/soc/intel/common/block/cpu/cpulib.c index a7f89baafd..75e71120e0 100644 --- a/src/soc/intel/common/block/cpu/cpulib.c +++ b/src/soc/intel/common/block/cpu/cpulib.c @@ -300,7 +300,7 @@ uint32_t cpu_get_max_turbo_ratio(void) return msr.lo & 0xff; } -void mca_configure(void *unused) +void mca_configure(void) { msr_t msr; int i; diff --git a/src/soc/intel/common/block/include/intelblocks/cpulib.h b/src/soc/intel/common/block/include/intelblocks/cpulib.h index 70ad253607..8630fd1eb5 100644 --- a/src/soc/intel/common/block/include/intelblocks/cpulib.h +++ b/src/soc/intel/common/block/include/intelblocks/cpulib.h @@ -159,6 +159,6 @@ uint32_t cpu_get_power_max(void); uint32_t cpu_get_max_turbo_ratio(void); /* Configure Machine Check Architecture support */ -void mca_configure(void *unused); +void mca_configure(void); #endif /* SOC_INTEL_COMMON_BLOCK_CPULIB_H */ diff --git a/src/soc/intel/denverton_ns/cpu.c b/src/soc/intel/denverton_ns/cpu.c index ce6df68f9f..2a631718c0 100644 --- a/src/soc/intel/denverton_ns/cpu.c +++ b/src/soc/intel/denverton_ns/cpu.c @@ -58,7 +58,7 @@ static void dnv_configure_mca(void) /* TODO(adurbin): This should only be done on a cold boot. Also, some of these banks are core vs package scope. For now every CPU clears every bank. */ - mca_configure(NULL); + mca_configure(); } static void denverton_core_init(struct device *cpu) diff --git a/src/soc/intel/icelake/cpu.c b/src/soc/intel/icelake/cpu.c index b1776a09a4..527b989e1a 100644 --- a/src/soc/intel/icelake/cpu.c +++ b/src/soc/intel/icelake/cpu.c @@ -192,7 +192,7 @@ void soc_core_init(struct device *cpu) /* TODO(adurbin): This should only be done on a cold boot. Also, some * of these banks are core vs package scope. For now every CPU clears * every bank. */ - mca_configure(NULL); + mca_configure(); /* Enable the local CPU apics */ enable_lapic_tpr(); diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index 52b0e194e6..a63809bd7e 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -428,7 +428,7 @@ void soc_core_init(struct device *cpu) /* TODO(adurbin): This should only be done on a cold boot. Also, some * of these banks are core vs package scope. For now every CPU clears * every bank. */ - mca_configure(NULL); + mca_configure(); /* Enable the local CPU apics */ enable_lapic_tpr(); From be291e8abf173e4f12e6d9e5532fdf1acbcb9a67 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Sun, 6 Jan 2019 07:35:11 +0100 Subject: [PATCH 128/331] soc/intel/fsp1.1: Implement postcar stage This moves FSP1.1 to use postcar stage to tear down CAR. On platforms with USE_GENERIC_FSP_CAR_INC the FSP header is found during the postcar stage so there is no need to push to save it in CAR global variables. On FSP1.1 platforms with an open source CAR implementation (Skylake, even though it still runs the FSP-T), the soc/intel/common/blocks/cpu/car/exit_car.S code tears down CAR. This also uses common functions to set up the MTRR to use after CAR is torn down. Test: build/boot on google/celes (BSW) and google/chell (SKL) Change-Id: I2330993842aae9c1365230f0c6bd8a2449dc73a5 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/30686 Tested-by: build bot (Jenkins) Reviewed-by: Philipp Deppenwiese --- src/drivers/intel/fsp1_1/Kconfig | 2 + src/drivers/intel/fsp1_1/Makefile.inc | 8 +- src/drivers/intel/fsp1_1/after_raminit.S | 170 ------------------ src/drivers/intel/fsp1_1/cache_as_ram.inc | 6 - src/drivers/intel/fsp1_1/car.c | 128 +++++++++---- src/drivers/intel/fsp1_1/exit_car.S | 27 +++ src/drivers/intel/fsp1_1/include/fsp/car.h | 8 +- .../intel/fsp1_1/include/fsp/romstage.h | 2 +- src/drivers/intel/fsp1_1/include/fsp/util.h | 4 + src/drivers/intel/fsp1_1/romstage.c | 20 +-- src/drivers/intel/fsp1_1/stack.c | 161 ----------------- src/drivers/intel/fsp1_1/temp_ram_exit.c | 44 +++++ src/soc/intel/braswell/Makefile.inc | 2 + src/soc/intel/quark/include/soc/romstage.h | 2 +- .../intel/quark/romstage/car_stage_entry.S | 6 - src/soc/intel/quark/romstage/fsp2_0.c | 3 +- src/soc/intel/skylake/romstage/car_stage.S | 5 +- 17 files changed, 188 insertions(+), 410 deletions(-) delete mode 100644 src/drivers/intel/fsp1_1/after_raminit.S create mode 100644 src/drivers/intel/fsp1_1/exit_car.S delete mode 100644 src/drivers/intel/fsp1_1/stack.c create mode 100644 src/drivers/intel/fsp1_1/temp_ram_exit.c diff --git a/src/drivers/intel/fsp1_1/Kconfig b/src/drivers/intel/fsp1_1/Kconfig index a8658ec7e6..da9e1888e9 100644 --- a/src/drivers/intel/fsp1_1/Kconfig +++ b/src/drivers/intel/fsp1_1/Kconfig @@ -18,6 +18,8 @@ config PLATFORM_USES_FSP1_1 bool select UEFI_2_4_BINDING select INTEL_GMA_ADD_VBT if RUN_FSP_GOP + select POSTCAR_STAGE + select POSTCAR_CONSOLE help Does the code require the Intel Firmware Support Package? diff --git a/src/drivers/intel/fsp1_1/Makefile.inc b/src/drivers/intel/fsp1_1/Makefile.inc index 953d1e4ffe..93f3b59d4b 100644 --- a/src/drivers/intel/fsp1_1/Makefile.inc +++ b/src/drivers/intel/fsp1_1/Makefile.inc @@ -28,7 +28,6 @@ romstage-y += fsp_util.c romstage-y += hob.c romstage-y += raminit.c romstage-y += romstage.c -romstage-y += stack.c romstage-y += stage_cache.c romstage-$(CONFIG_MMA) += mma_core.c @@ -45,6 +44,13 @@ CPPFLAGS_common += -Isrc/drivers/intel/fsp1_1/include cpu_incs-$(CONFIG_USE_GENERIC_FSP_CAR_INC) += $(src)/drivers/intel/fsp1_1/cache_as_ram.inc +postcar-y += stage_cache.c +ifneq ($(CONFIG_SKIP_FSP_CAR),y) +postcar-y += temp_ram_exit.c +postcar-y += exit_car.S +endif +postcar-y += fsp_util.c + # Add the FSP binary to the cbfs image ifeq ($(CONFIG_HAVE_FSP_BIN),y) cbfs-files-y += fsp.bin diff --git a/src/drivers/intel/fsp1_1/after_raminit.S b/src/drivers/intel/fsp1_1/after_raminit.S deleted file mode 100644 index 3f2a7ae02f..0000000000 --- a/src/drivers/intel/fsp1_1/after_raminit.S +++ /dev/null @@ -1,170 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2000,2007 Ronald G. Minnich - * Copyright (C) 2007-2008 coresystems GmbH - * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. - * Copyright (C) 2015 Intel Corp. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include - -/* - * This is the common entry point after DRAM has been initialized. - */ - /* - * eax: New stack address - */ - - /* Switch to the stack in RAM */ - movl %eax, %esp - -#if CONFIG(SKIP_FSP_CAR) - - /* chipset_teardown_car() is expected to disable cache-as-ram. */ - call chipset_teardown_car - -#else -.extern fih_car - - post_code(POST_FSP_TEMP_RAM_EXIT) - - /* Calculate TempRamExit entry into FSP */ - movl fih_car, %ebp - mov 0x40(%ebp), %eax - add 0x1c(%ebp), %eax - - /* Build the call frame */ - pushl $0 - - /* Call TempRamExit */ - call *%eax - add $4, %esp - cmp $0, %eax - jz 1f - /* - * Failures for post code BC - failed in TempRamExit - * - * 0x00 - FSP_SUCCESS: Temp RAM Exit completed successfully. - * 0x02 - FSP_INVALID_PARAMETER: Input parameters are invalid. - * 0x03 - FSP_UNSUPPORTED: The FSP calling conditions were not met. - * 0x07 - FSP_DEVICE_ERROR: Temp RAM Exit failed. - */ - movb $0xBC, %ah - jmp .Lhlt -1: -#endif - /* Display the MTRRs */ - call display_mtrrs - - /* - * The stack contents are initialized in src/soc/intel/common/stack.c - * to be the following: - * - * * - * * - * * - * +36: MTRR mask 1 63:32 - * +32: MTRR mask 1 31:0 - * +28: MTRR base 1 63:32 - * +24: MTRR base 1 31:0 - * +20: MTRR mask 0 63:32 - * +16: MTRR mask 0 31:0 - * +12: MTRR base 0 63:32 - * +8: MTRR base 0 31:0 - * +4: Number of MTRRs to setup (described above) - * +0: Number of variable MTRRs to clear - */ - -#if CONFIG(SOC_SETS_MSRS) - push %esp - call soc_set_mtrrs - - /* eax: new top_of_stack with setup_stack_and_mtrrs data removed */ - movl %eax, %esp -#else - /* Clear all of the variable MTRRs. */ - popl %ebx - movl $MTRR_PHYS_BASE(0), %ecx - clr %eax - clr %edx - -1: - testl %ebx, %ebx - jz 1f - wrmsr /* Write MTRR base. */ - inc %ecx - wrmsr /* Write MTRR mask. */ - inc %ecx - dec %ebx - jmp 1b - -1: - /* Get number of MTRRs. */ - popl %ebx - movl $MTRR_PHYS_BASE(0), %ecx -2: - testl %ebx, %ebx - jz 2f - - /* Low 32 bits of MTRR base. */ - popl %eax - /* Upper 32 bits of MTRR base. */ - popl %edx - /* Write MTRR base. */ - wrmsr - inc %ecx - /* Low 32 bits of MTRR mask. */ - popl %eax - /* Upper 32 bits of MTRR mask. */ - popl %edx - /* Write MTRR mask. */ - wrmsr - inc %ecx - - dec %ebx - jmp 2b -2: -#endif /* CONFIG_SOC_SETS_MSRS */ - - post_code(0x39) - - /* And enable cache again after setting MTRRs. */ - movl %cr0, %eax - andl $~(CR0_CacheDisable | CR0_NoWriteThrough), %eax - movl %eax, %cr0 - - post_code(0x3a) - -#if CONFIG(SOC_SETS_MSRS) - call soc_enable_mtrrs -#else - /* Enable MTRR. */ - movl $MTRR_DEF_TYPE_MSR, %ecx - rdmsr - orl $MTRR_DEF_TYPE_EN, %eax - wrmsr -#endif /* CONFIG_SOC_SETS_MSRS */ - - post_code(0x3b) - - /* Invalidate the cache again. */ - invd - - post_code(0x3c) - -__main: - post_code(POST_PREPARE_RAMSTAGE) - cld /* Clear direction flag. */ - call after_cache_as_ram diff --git a/src/drivers/intel/fsp1_1/cache_as_ram.inc b/src/drivers/intel/fsp1_1/cache_as_ram.inc index fa5c40677b..f50641e3ae 100644 --- a/src/drivers/intel/fsp1_1/cache_as_ram.inc +++ b/src/drivers/intel/fsp1_1/cache_as_ram.inc @@ -147,12 +147,6 @@ before_romstage: /* Call cache_as_ram_main(struct cache_as_ram_params *) */ call cache_as_ram_main -/* One will never return from cache_as_ram_main() in verstage so there's - * no such thing as after RAM init. */ -#if !ENV_VERSTAGE -#include "after_raminit.S" -#endif - movb $0x69, %ah jmp .Lhlt diff --git a/src/drivers/intel/fsp1_1/car.c b/src/drivers/intel/fsp1_1/car.c index 3a41e40468..34b2518c38 100644 --- a/src/drivers/intel/fsp1_1/car.c +++ b/src/drivers/intel/fsp1_1/car.c @@ -18,35 +18,96 @@ #include #include #include +#include #include #include -FSP_INFO_HEADER *fih_car CAR_GLOBAL; +#define ROMSTAGE_RAM_STACK_SIZE 0x5000 -/* Save FSP_INFO_HEADER for TempRamExit() call in assembly. */ -static inline void set_fih_car(FSP_INFO_HEADER *fih) +/* platform_enter_postcar() determines the stack to use after + * cache-as-ram is torn down as well as the MTRR settings to use, + * and continues execution in postcar stage. */ +static void platform_enter_postcar(void) { - /* This variable is written in the raw form because it's only - * ever accessed in code that that has the cache-as-ram enabled. The - * assembly routine which tears down cache-as-ram utilizes this - * variable for determining where to find FSP. */ - fih_car = fih; + struct postcar_frame pcf; + size_t alignment; + uint32_t aligned_ram; + + if (postcar_frame_init(&pcf, ROMSTAGE_RAM_STACK_SIZE)) + die("Unable to initialize postcar frame.\n"); + /* Cache the ROM as WP just below 4GiB. */ + postcar_frame_add_mtrr(&pcf, CACHE_ROM_BASE, CACHE_ROM_SIZE, + MTRR_TYPE_WRPROT); + + /* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */ + postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK); + + /* + * +-------------------------+ Top of RAM (aligned) + * | System Management Mode | + * | code and data | Length: CONFIG_TSEG_SIZE + * | (TSEG) | + * +-------------------------+ SMM base (aligned) + * | | + * | Chipset Reserved Memory | Length: Multiple of CONFIG_TSEG_SIZE + * | | + * +-------------------------+ top_of_ram (aligned) + * | | + * | CBMEM Root | + * | | + * +-------------------------+ + * | | + * | FSP Reserved Memory | + * | | + * +-------------------------+ + * | | + * | Various CBMEM Entries | + * | | + * +-------------------------+ top_of_stack (8 byte aligned) + * | | + * | stack (CBMEM Entry) | + * | | + * +-------------------------+ + */ + + alignment = mmap_region_granularity(); + aligned_ram = ALIGN_DOWN(romstage_ram_stack_bottom(), alignment); + postcar_frame_add_mtrr(&pcf, aligned_ram, alignment, MTRR_TYPE_WRBACK); + + if (CONFIG(HAVE_SMI_HANDLER)) { + void *smm_base; + size_t smm_size; + + /* + * Cache the TSEG region at the top of ram. This region is not + * restricted to SMM mode until SMM has been relocated. By + * setting the region to cacheable it provides faster access + * when relocating the SMM handler as well as using the TSEG + * region for other purposes. + */ + smm_region(&smm_base, &smm_size); + postcar_frame_add_mtrr(&pcf, (uintptr_t)smm_base, alignment, + MTRR_TYPE_WRBACK); + } + + run_postcar_phase(&pcf); } -asmlinkage void *cache_as_ram_main(struct cache_as_ram_params *car_params) +/* This is the romstage C entry for platforms without + CONFIG_C_ENVIRONMENT_BOOTBLOCK */ +asmlinkage void cache_as_ram_main(struct cache_as_ram_params *car_params) { int i; const int num_guards = 4; const u32 stack_guard = 0xdeadbeef; u32 *stack_base; - void *ram_stack; u32 size; /* Size of unallocated CAR. */ size = _car_region_end - _car_relocatable_data_end; size = ALIGN_DOWN(size, 16); - stack_base = (u32 *) (_car_region_end - size); + stack_base = (u32 *)(_car_region_end - size); for (i = 0; i < num_guards; i++) stack_base[i] = stack_guard; @@ -66,23 +127,20 @@ asmlinkage void *cache_as_ram_main(struct cache_as_ram_params *car_params) display_mtrrs(); - if (car_params->bootloader_car_start != CONFIG_DCACHE_RAM_BASE || - car_params->bootloader_car_end != - (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE)) { + if (car_params->bootloader_car_start != CONFIG_DCACHE_RAM_BASE + || car_params->bootloader_car_end != (CONFIG_DCACHE_RAM_BASE + + CONFIG_DCACHE_RAM_SIZE)) { printk(BIOS_INFO, "CAR mismatch: %08x--%08x vs %08lx--%08lx\n", - CONFIG_DCACHE_RAM_BASE, - CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE, - (long)car_params->bootloader_car_start, - (long)car_params->bootloader_car_end); + CONFIG_DCACHE_RAM_BASE, + CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE, + (long)car_params->bootloader_car_start, + (long)car_params->bootloader_car_end); } car_soc_post_console_init(); car_mainboard_post_console_init(); - set_fih_car(car_params->fih); - - /* Return new stack value in RAM back to assembly stub. */ - ram_stack = cache_as_ram_stage_main(car_params->fih); + cache_as_ram_stage_main(car_params->fih); /* Check the stack. */ for (i = 0; i < num_guards; i++) { @@ -91,11 +149,13 @@ asmlinkage void *cache_as_ram_main(struct cache_as_ram_params *car_params) printk(BIOS_DEBUG, "Smashed stack detected in romstage!\n"); } - return ram_stack; + /* we don't return here */ + platform_enter_postcar(); } -/* Entry point taken when romstage is called after a separate verstage. */ -asmlinkage void *romstage_c_entry(void) +/* This is the romstage C entry for platforms with + CONFIG_C_ENVIRONMENT_BOOTBLOCK */ +asmlinkage void romstage_c_entry(void) { /* Need to locate the current FSP_INFO_HEADER. The cache-as-ram * is still enabled. We can directly access work buffer here. */ @@ -107,24 +167,16 @@ asmlinkage void *romstage_c_entry(void) if (prog_locate(&fsp)) { fih = NULL; printk(BIOS_ERR, "Unable to locate %s\n", prog_name(&fsp)); - } else + } else { /* This leaks a mapping which this code assumes is benign as * the flash is memory mapped CPU's address space. */ fih = find_fsp((uintptr_t)rdev_mmap_full(prog_rdev(&fsp))); + } - set_fih_car(fih); + cache_as_ram_stage_main(fih); - /* Return new stack value in RAM back to assembly stub. */ - return cache_as_ram_stage_main(fih); -} - -asmlinkage void after_cache_as_ram(void *chipset_context) -{ - timestamp_add_now(TS_FSP_TEMP_RAM_EXIT_END); - printk(BIOS_DEBUG, "FspTempRamExit returned successfully\n"); - display_mtrrs(); - - after_cache_as_ram_stage(); + /* we don't return here */ + platform_enter_postcar(); } void __weak car_mainboard_pre_console_init(void) diff --git a/src/drivers/intel/fsp1_1/exit_car.S b/src/drivers/intel/fsp1_1/exit_car.S new file mode 100644 index 0000000000..4b2822a887 --- /dev/null +++ b/src/drivers/intel/fsp1_1/exit_car.S @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +.text +.global chipset_teardown_car +chipset_teardown_car: + + pop %ebx + /* Move the stack pointer to real ram */ + movl post_car_stack_top, %esp + /* Align the stack 16 bytes */ + andl $0xfffffff0, %esp + + call chipset_teardown_car_main + + jmp *%ebx diff --git a/src/drivers/intel/fsp1_1/include/fsp/car.h b/src/drivers/intel/fsp1_1/include/fsp/car.h index 5214d73b29..0ae687a9d7 100644 --- a/src/drivers/intel/fsp1_1/include/fsp/car.h +++ b/src/drivers/intel/fsp1_1/include/fsp/car.h @@ -30,14 +30,12 @@ struct cache_as_ram_params { }; /* Entry points from the cache-as-ram assembly code. */ -asmlinkage void *cache_as_ram_main(struct cache_as_ram_params *car_params); -asmlinkage void after_cache_as_ram(void *chipset_context); -asmlinkage void *romstage_c_entry(void); +asmlinkage void cache_as_ram_main(struct cache_as_ram_params *car_params); +asmlinkage void romstage_c_entry(void); /* Per stage calls from the above two functions. The void * return from * cache_as_ram_stage_main() is the stack pointer to use in RAM after * exiting cache-as-ram mode. */ -void *cache_as_ram_stage_main(FSP_INFO_HEADER *fih); -void after_cache_as_ram_stage(void); +void cache_as_ram_stage_main(FSP_INFO_HEADER *fih); /* Mainboard and SoC initialization prior to console. */ void car_mainboard_pre_console_init(void); diff --git a/src/drivers/intel/fsp1_1/include/fsp/romstage.h b/src/drivers/intel/fsp1_1/include/fsp/romstage.h index b01f11059c..de37950887 100644 --- a/src/drivers/intel/fsp1_1/include/fsp/romstage.h +++ b/src/drivers/intel/fsp1_1/include/fsp/romstage.h @@ -87,7 +87,7 @@ void mainboard_add_dimm_info(struct romstage_params *params, void raminit(struct romstage_params *params); void report_memory_config(void); void romstage_common(struct romstage_params *params); -asmlinkage void *romstage_main(FSP_INFO_HEADER *fih); +asmlinkage void romstage_main(FSP_INFO_HEADER *fih); /* Initialize memory margin analysis settings. */ void setup_mma(MEMORY_INIT_UPD *memory_upd); void *setup_stack_and_mtrrs(void); diff --git a/src/drivers/intel/fsp1_1/include/fsp/util.h b/src/drivers/intel/fsp1_1/include/fsp/util.h index 0ad7a4117a..45b8eda243 100644 --- a/src/drivers/intel/fsp1_1/include/fsp/util.h +++ b/src/drivers/intel/fsp1_1/include/fsp/util.h @@ -17,6 +17,8 @@ #ifndef FSP1_1_UTIL_H #define FSP1_1_UTIL_H +#include +#include #include /* Current users expect to get the SoC's FSP definitions by including util.h. */ #include @@ -107,4 +109,6 @@ void *get_first_guid_hob(const EFI_GUID *guid); __attribute__((cdecl)) size_t fsp_write_line(uint8_t *buffer, size_t number_of_bytes); +asmlinkage void chipset_teardown_car_main(void); + #endif /* FSP1_1_UTIL_H */ diff --git a/src/drivers/intel/fsp1_1/romstage.c b/src/drivers/intel/fsp1_1/romstage.c index 433e16cf13..40c598877f 100644 --- a/src/drivers/intel/fsp1_1/romstage.c +++ b/src/drivers/intel/fsp1_1/romstage.c @@ -38,9 +38,8 @@ #include #include -asmlinkage void *romstage_main(FSP_INFO_HEADER *fih) +asmlinkage void romstage_main(FSP_INFO_HEADER *fih) { - void *top_of_stack; struct romstage_params params = { .chipset_context = fih, }; @@ -72,17 +71,11 @@ asmlinkage void *romstage_main(FSP_INFO_HEADER *fih) mainboard_romstage_entry(¶ms); soc_after_ram_init(¶ms); post_code(0x38); - - top_of_stack = setup_stack_and_mtrrs(); - - printk(BIOS_DEBUG, "Calling FspTempRamExit API\n"); - timestamp_add_now(TS_FSP_TEMP_RAM_EXIT_START); - return top_of_stack; } -void *cache_as_ram_stage_main(FSP_INFO_HEADER *fih) +void cache_as_ram_stage_main(FSP_INFO_HEADER *fih) { - return romstage_main(fih); + romstage_main(fih); } /* Entry from the mainboard. */ @@ -161,13 +154,6 @@ void romstage_common(struct romstage_params *params) full_reset(); } -void after_cache_as_ram_stage(void) -{ - /* Load the ramstage. */ - run_ramstage(); - die("ERROR - Failed to load ramstage!"); -} - /* Initialize the power state */ __weak struct chipset_power_state *fill_power_state(void) { diff --git a/src/drivers/intel/fsp1_1/stack.c b/src/drivers/intel/fsp1_1/stack.c deleted file mode 100644 index 88ff36a847..0000000000 --- a/src/drivers/intel/fsp1_1/stack.c +++ /dev/null @@ -1,161 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015-2016 Intel Corp. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/* - * setup_stack_and_mtrrs() determines the stack to use after - * cache-as-ram is torn down as well as the MTRR settings to use. - */ -void *setup_stack_and_mtrrs(void) -{ - size_t alignment; - uint32_t aligned_ram; - uint32_t mtrr_mask_upper; - uint32_t max_mtrrs; - uint32_t num_mtrrs; - uint32_t *slot; - - /* Display the MTRRs */ - display_mtrrs(); - - /* Top of stack needs to be aligned to a 8-byte boundary. */ - slot = (void *)romstage_ram_stack_top(); - num_mtrrs = 0; - max_mtrrs = get_var_mtrr_count(); - - /* - * The upper bits of the MTRR mask need to set according to the number - * of physical address bits. - */ - mtrr_mask_upper = (1 << ((cpuid_eax(0x80000008) & 0xff) - 32)) - 1; - alignment = mmap_region_granularity(); - aligned_ram = ALIGN_DOWN(romstage_ram_stack_bottom(), alignment); - - /* - * The order for each MTRR is value then base with upper 32-bits of - * each value coming before the lower 32-bits. The reasoning for - * this ordering is to create a stack layout like the following: - * - * +36: MTRR mask 1 63:32 - * +32: MTRR mask 1 31:0 - * +28: MTRR base 1 63:32 - * +24: MTRR base 1 31:0 - * +20: MTRR mask 0 63:32 - * +16: MTRR mask 0 31:0 - * +12: MTRR base 0 63:32 - * +8: MTRR base 0 31:0 - * +4: Number of MTRRs to setup (described above) - * +0: Number of variable MTRRs to clear - */ - - /* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */ - slot = stack_push32(slot, mtrr_mask_upper); /* upper mask */ - slot = stack_push32(slot, ~(CACHE_TMP_RAMTOP - 1) - | MTRR_PHYS_MASK_VALID); - slot = stack_push32(slot, 0); /* upper base */ - slot = stack_push32(slot, 0 | MTRR_TYPE_WRBACK); - num_mtrrs++; - - /* - * +-------------------------+ Top of RAM (aligned) - * | System Management Mode | - * | code and data | Length: CONFIG_TSEG_SIZE - * | (TSEG) | - * +-------------------------+ SMM base (aligned) - * | | - * | Chipset Reserved Memory | Length: Multiple of CONFIG_TSEG_SIZE - * | | - * +-------------------------+ top_of_ram (aligned) - * | | - * | CBMEM Root | - * | | - * +-------------------------+ - * | | - * | FSP Reserved Memory | - * | | - * +-------------------------+ - * | | - * | Various CBMEM Entries | - * | | - * +-------------------------+ top_of_stack (8 byte aligned) - * | | - * | stack (CBMEM Entry) | - * | | - * +-------------------------+ - */ - - /* - * Cache the stack and the other CBMEM entries as well as part or all - * of the FSP reserved memory region. - */ - slot = stack_push32(slot, mtrr_mask_upper); /* upper mask */ - slot = stack_push32(slot, ~(alignment - 1) | MTRR_PHYS_MASK_VALID); - slot = stack_push32(slot, 0); /* upper base */ - slot = stack_push32(slot, aligned_ram | MTRR_TYPE_WRBACK); - num_mtrrs++; - -#if CONFIG(HAVE_SMI_HANDLER) - void *smm_base; - size_t smm_size; - uint32_t tseg_base; - - /* - * Cache the TSEG region at the top of ram. This region is not - * restricted to SMM mode until SMM has been relocated. By setting - * the region to cacheable it provides faster access when relocating - * the SMM handler as well as using the TSEG region for other purposes. - */ - smm_region(&smm_base, &smm_size); - tseg_base = (uint32_t)smm_base; - slot = stack_push32(slot, mtrr_mask_upper); /* upper mask */ - slot = stack_push32(slot, ~(alignment - 1) | MTRR_PHYS_MASK_VALID); - slot = stack_push32(slot, 0); /* upper base */ - slot = stack_push32(slot, tseg_base | MTRR_TYPE_WRBACK); - num_mtrrs++; -#endif - - /* Cache the ROM as WP just below 4GiB. */ - slot = stack_push32(slot, mtrr_mask_upper); /* upper mask */ - slot = stack_push32(slot, ~(CONFIG_ROM_SIZE - 1) - | MTRR_PHYS_MASK_VALID); - slot = stack_push32(slot, 0); /* upper base */ - slot = stack_push32(slot, ~(CONFIG_ROM_SIZE - 1) | MTRR_TYPE_WRPROT); - num_mtrrs++; - - /* Validate the MTRR usage */ - if (num_mtrrs > max_mtrrs) { - printk(BIOS_ERR, "MTRRs: max = %d, used = %d, available=%d", - max_mtrrs, num_mtrrs, max_mtrrs - num_mtrrs); - die("ERROR - MTRR use count incorrect!\n"); - } - - /* - * Save the number of MTRRs to setup and clear. Return the stack - * location pointing to the number of MTRRs. - */ - slot = stack_push32(slot, num_mtrrs); - slot = stack_push32(slot, max_mtrrs); - return slot; -} diff --git a/src/drivers/intel/fsp1_1/temp_ram_exit.c b/src/drivers/intel/fsp1_1/temp_ram_exit.c new file mode 100644 index 0000000000..c1535e0bc0 --- /dev/null +++ b/src/drivers/intel/fsp1_1/temp_ram_exit.c @@ -0,0 +1,44 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include +#include + +asmlinkage void chipset_teardown_car_main(void) +{ + FSP_INFO_HEADER *fih; + uint32_t status; + FSP_TEMP_RAM_EXIT temp_ram_exit; + struct prog fsp = PROG_INIT(PROG_REFCODE, "fsp.bin"); + + if (prog_locate(&fsp)) { + die("Unable to locate fsp.bin\n"); + } else { + /* This leaks a mapping which this code assumes is benign as + * the flash is memory mapped CPU's address space. */ + + /* FIXME: the implementation of find_fsp is utter garbage + as it casts error values to FSP_INFO_HEADER pointers. + Checking for return values can only be done sanely once + that is fixed. */ + fih = find_fsp((uintptr_t)rdev_mmap_full(prog_rdev(&fsp))); + } + + temp_ram_exit = (FSP_TEMP_RAM_EXIT)(fih->TempRamExitEntryOffset + + fih->ImageBase); + printk(BIOS_DEBUG, "Calling TempRamExit: %p\n", temp_ram_exit); + status = temp_ram_exit(NULL); + + if (status != FSP_SUCCESS) { + printk(BIOS_CRIT, "TempRamExit returned 0x%08x\n", status); + die("TempRamExit returned an error!\n"); + } +} diff --git a/src/soc/intel/braswell/Makefile.inc b/src/soc/intel/braswell/Makefile.inc index e2b1fe5295..6b466c66f8 100644 --- a/src/soc/intel/braswell/Makefile.inc +++ b/src/soc/intel/braswell/Makefile.inc @@ -17,6 +17,8 @@ romstage-y += pmutil.c romstage-y += smbus.c romstage-y += tsc_freq.c +postcar-y += memmap.c +postcar-y += iosf.c postcar-y += tsc_freq.c ramstage-y += acpi.c diff --git a/src/soc/intel/quark/include/soc/romstage.h b/src/soc/intel/quark/include/soc/romstage.h index fb8a844815..c7de080146 100644 --- a/src/soc/intel/quark/include/soc/romstage.h +++ b/src/soc/intel/quark/include/soc/romstage.h @@ -25,7 +25,7 @@ #include #include -asmlinkage void *car_stage_c_entry(void); +asmlinkage void car_stage_c_entry(void); void clear_smi_and_wake_events(void); void disable_rom_shadow(void); void *locate_rmu_file(size_t *rmu_file_len); diff --git a/src/soc/intel/quark/romstage/car_stage_entry.S b/src/soc/intel/quark/romstage/car_stage_entry.S index d51587143b..c9847eaac7 100644 --- a/src/soc/intel/quark/romstage/car_stage_entry.S +++ b/src/soc/intel/quark/romstage/car_stage_entry.S @@ -29,12 +29,6 @@ car_stage_entry: /* Enter the C code */ call car_stage_c_entry -#if CONFIG(PLATFORM_USES_FSP1_1) -#if !ENV_VERSTAGE -#include "src/drivers/intel/fsp1_1/after_raminit.S" -#endif -#endif - /* The code should never reach this point */ movb $0x69, %ah jmp .Lhlt diff --git a/src/soc/intel/quark/romstage/fsp2_0.c b/src/soc/intel/quark/romstage/fsp2_0.c index 31e130a398..2ec16c9f34 100644 --- a/src/soc/intel/quark/romstage/fsp2_0.c +++ b/src/soc/intel/quark/romstage/fsp2_0.c @@ -26,7 +26,7 @@ #include #include -asmlinkage void *car_stage_c_entry(void) +asmlinkage void car_stage_c_entry(void) { struct postcar_frame pcf; bool s3wake; @@ -83,7 +83,6 @@ asmlinkage void *car_stage_c_entry(void) postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRTHROUGH); run_postcar_phase(&pcf); - return NULL; } static struct chipset_power_state power_state CAR_GLOBAL; diff --git a/src/soc/intel/skylake/romstage/car_stage.S b/src/soc/intel/skylake/romstage/car_stage.S index ee04f0272d..d8b45cb258 100644 --- a/src/soc/intel/skylake/romstage/car_stage.S +++ b/src/soc/intel/skylake/romstage/car_stage.S @@ -13,6 +13,8 @@ * GNU General Public License for more details. */ +#include + /* I/O delay between post codes on failure */ #define LHLT_DELAY 0x50000 @@ -20,9 +22,8 @@ .global car_stage_entry car_stage_entry: call romstage_c_entry - #include "src/drivers/intel/fsp1_1/after_raminit.S" - + /* we don't return here */ movb $0x69, %ah jmp .Lhlt From b6ee05692dce5df945b8363d361398ab2192d960 Mon Sep 17 00:00:00 2001 From: Eric Lai Date: Tue, 21 May 2019 16:55:14 +0800 Subject: [PATCH 129/331] vboot: determine display init before recovery check Display is required by recovery mode. Determine display init before recovery check. BUG=b:133197727,b:133175864 TEST=enter recovery mode, checked the display shows up Signed-off-by: Eric Lai Change-Id: Id6ac611f51241373bca3e2b394a94dcd52d3fde7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32906 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh Reviewed-by: Duncan Laurie --- src/security/vboot/vboot_logic.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/src/security/vboot/vboot_logic.c b/src/security/vboot/vboot_logic.c index 00347c3f58..d4ad32736b 100644 --- a/src/security/vboot/vboot_logic.c +++ b/src/security/vboot/vboot_logic.c @@ -344,6 +344,14 @@ void verstage_main(void) printk(BIOS_INFO, "Phase 1\n"); rv = vb2api_fw_phase1(&ctx); + /* Jot down some information from vboot which may be required later on + in coreboot boot flow. */ + if (ctx.flags & VB2_CONTEXT_DISPLAY_INIT) + /* Mainboard/SoC should initialize display. */ + vboot_get_working_data()->flags |= VBOOT_WD_FLAG_DISPLAY_INIT; + if (ctx.flags & VB2_CONTEXT_DEVELOPER_MODE) + vboot_get_working_data()->flags |= VBOOT_WD_FLAG_DEVELOPER_MODE; + if (rv) { /* * If vb2api_fw_phase1 fails, check for return value. @@ -364,14 +372,6 @@ void verstage_main(void) vboot_reboot(); } - /* Jot down some information from vboot which may be required later on - in coreboot boot flow. */ - if (ctx.flags & VB2_CONTEXT_DISPLAY_INIT) - /* Mainboard/SoC should initialize display. */ - vboot_get_working_data()->flags |= VBOOT_WD_FLAG_DISPLAY_INIT; - if (ctx.flags & VB2_CONTEXT_DEVELOPER_MODE) - vboot_get_working_data()->flags |= VBOOT_WD_FLAG_DEVELOPER_MODE; - /* Determine which firmware slot to boot (based on NVRAM) */ printk(BIOS_INFO, "Phase 2\n"); rv = vb2api_fw_phase2(&ctx); From 9b0d8e7a1fd18a53579d0332204d2be57ec0474b Mon Sep 17 00:00:00 2001 From: Jacob Garber Date: Mon, 20 May 2019 16:35:33 -0600 Subject: [PATCH 130/331] util/romcc: Prevent out-of-bounds read If 'class > LAST_REGC', then there will be an out-of-bounds read when accessing 'regcm_bound'. Prevent this by skipping to the next iteration of the loop. Note that this should not generally happen anyway, since 'result' represents a bitset for the indices of 'regcm_bound', and so iterations where 'class > LAST_REGC' should already be skipped by the previous continue statement (since those bits of 'result' should all be zero). Found-by: Covericy CID 1129122 Signed-off-by: Jacob Garber Change-Id: Id5f5adb0a292763251054aeecf2a5b87a11297b1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32902 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi Reviewed-by: Paul Menzel --- util/romcc/romcc.c | 1 + 1 file changed, 1 insertion(+) diff --git a/util/romcc/romcc.c b/util/romcc/romcc.c index b9ec835f6f..329cfd2433 100644 --- a/util/romcc/romcc.c +++ b/util/romcc/romcc.c @@ -22160,6 +22160,7 @@ static unsigned arch_regcm_normalize(struct compile_state *state, unsigned regcm } if (class > LAST_REGC) { result &= ~mask; + continue; } for(class2 = 0; class2 <= LAST_REGC; class2++) { if ((regcm_bound[class2].first >= regcm_bound[class].first) && From 8ef2a45bb9139a160d2562938680a73edb10e8ae Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Sat, 18 May 2019 15:51:39 -0500 Subject: [PATCH 131/331] soc/{baytrail/braswell/broadwell}: fix flashconsole on platform MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Enabling flashconsole on these platforms fails to build due to spi.c not being compiled in prior to ramstage. Include in early stages (bootblock/romstage/postcar) as needed to enable flashconsole support. Early inclusion of monotonic_timer.c is needed for Broadwell as well. Change-Id: Idae0578ca92939246021bb85e34b0dcbd41df3b5 Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/32878 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki --- src/soc/intel/baytrail/Makefile.inc | 2 ++ src/soc/intel/braswell/Makefile.inc | 2 ++ src/soc/intel/broadwell/Makefile.inc | 6 ++++++ 3 files changed, 10 insertions(+) diff --git a/src/soc/intel/baytrail/Makefile.inc b/src/soc/intel/baytrail/Makefile.inc index 0d4bac5140..6e6eb9cc44 100644 --- a/src/soc/intel/baytrail/Makefile.inc +++ b/src/soc/intel/baytrail/Makefile.inc @@ -16,6 +16,8 @@ ramstage-y += tsc_freq.c romstage-y += tsc_freq.c postcar-y += tsc_freq.c smm-y += tsc_freq.c +romstage-y += spi.c +postcar-y += spi.c ramstage-y += spi.c smm-y += spi.c ramstage-y += chip.c diff --git a/src/soc/intel/braswell/Makefile.inc b/src/soc/intel/braswell/Makefile.inc index 6b466c66f8..e479a3c5e5 100644 --- a/src/soc/intel/braswell/Makefile.inc +++ b/src/soc/intel/braswell/Makefile.inc @@ -15,10 +15,12 @@ romstage-y += lpc_init.c romstage-y += memmap.c romstage-y += pmutil.c romstage-y += smbus.c +romstage-y += spi.c romstage-y += tsc_freq.c postcar-y += memmap.c postcar-y += iosf.c +postcar-y += spi.c postcar-y += tsc_freq.c ramstage-y += acpi.c diff --git a/src/soc/intel/broadwell/Makefile.inc b/src/soc/intel/broadwell/Makefile.inc index 40017eb3ec..a79fa464a9 100644 --- a/src/soc/intel/broadwell/Makefile.inc +++ b/src/soc/intel/broadwell/Makefile.inc @@ -39,6 +39,9 @@ ramstage-y += memmap.c romstage-y += memmap.c postcar-y += memmap.c ramstage-y += minihd.c +bootblock-y += monotonic_timer.c +romstage-y += monotonic_timer.c +postcar-y += monotonic_timer.c ramstage-y += monotonic_timer.c smm-y += monotonic_timer.c ramstage-y += pch.c @@ -60,6 +63,9 @@ romstage-y += smbus_common.c ramstage-y += smi.c smm-y += smihandler.c ramstage-y += smmrelocate.c +bootblock-y += spi.c +romstage-y += spi.c +postcar-y += spi.c ramstage-y += spi.c smm-$(CONFIG_SPI_FLASH_SMM) += spi.c ramstage-y += stage_cache.c From 1caa3143d6decbb1cbb0c64cdb5a22bb46ae0053 Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Sat, 18 May 2019 15:56:14 -0500 Subject: [PATCH 132/331] soc/fsp_baytrail: fix flashconsole on platform MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Include spi.c in romstage. Since FSP 1.0 can't use NO_CAR_GLOBAL_MIGRATION, adjust global variables in spi.c to use CAR_GLOBAL. Adapted from early versions of CB:21107 Change-Id: I3487fb8ac317ce920bf1c3ef9d89590051932378 Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/32879 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki --- src/soc/intel/fsp_baytrail/Makefile.inc | 1 + src/soc/intel/fsp_baytrail/spi.c | 82 +++++++++++++------------ 2 files changed, 44 insertions(+), 39 deletions(-) diff --git a/src/soc/intel/fsp_baytrail/Makefile.inc b/src/soc/intel/fsp_baytrail/Makefile.inc index 5ed635d943..ca2b353b0f 100644 --- a/src/soc/intel/fsp_baytrail/Makefile.inc +++ b/src/soc/intel/fsp_baytrail/Makefile.inc @@ -35,6 +35,7 @@ romstage-y += tsc_freq.c postcar-y += tsc_freq.c smm-$(CONFIG_HAVE_SMI_HANDLER) += tsc_freq.c ramstage-y += spi.c +romstage-y += spi.c smm-$(CONFIG_HAVE_SMI_HANDLER) += spi.c ramstage-y += chip.c ramstage-y += iosf.c diff --git a/src/soc/intel/fsp_baytrail/spi.c b/src/soc/intel/fsp_baytrail/spi.c index 979ee573bb..9375d19547 100644 --- a/src/soc/intel/fsp_baytrail/spi.c +++ b/src/soc/intel/fsp_baytrail/spi.c @@ -15,7 +15,7 @@ */ /* This file is derived from the flashrom project. */ - +#include #include #include #include @@ -33,7 +33,7 @@ typedef struct spi_slave ich_spi_slave; -static int ichspi_lock = 0; +static int g_ichspi_lock CAR_GLOBAL = 0; typedef struct ich9_spi_regs { uint32_t bfpr; @@ -81,7 +81,7 @@ typedef struct ich_spi_controller { uint16_t *control; } ich_spi_controller; -static ich_spi_controller cntlr; +static ich_spi_controller g_cntlr CAR_GLOBAL; enum { SPIS_SCIP = 0x0001, @@ -239,18 +239,19 @@ static ich9_spi_regs *spi_regs(void) void spi_init(void) { + ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr); ich9_spi_regs *ich9_spi = spi_regs(); - ichspi_lock = readw_(&ich9_spi->hsfs) & HSFS_FLOCKDN; - cntlr.opmenu = ich9_spi->opmenu; - cntlr.menubytes = sizeof(ich9_spi->opmenu); - cntlr.optype = &ich9_spi->optype; - cntlr.addr = &ich9_spi->faddr; - cntlr.data = (uint8_t *)ich9_spi->fdata; - cntlr.databytes = sizeof(ich9_spi->fdata); - cntlr.status = &ich9_spi->ssfs; - cntlr.control = (uint16_t *)ich9_spi->ssfc; - cntlr.preop = &ich9_spi->preop; + car_set_var(g_ichspi_lock, readw_(&ich9_spi->hsfs) & HSFS_FLOCKDN); + cntlr->opmenu = ich9_spi->opmenu; + cntlr->menubytes = sizeof(ich9_spi->opmenu); + cntlr->optype = &ich9_spi->optype; + cntlr->addr = &ich9_spi->faddr; + cntlr->data = (uint8_t *)ich9_spi->fdata; + cntlr->databytes = sizeof(ich9_spi->fdata); + cntlr->status = &ich9_spi->ssfs; + cntlr->control = (uint16_t *)ich9_spi->ssfc; + cntlr->preop = &ich9_spi->preop; } typedef struct spi_transaction { @@ -311,17 +312,18 @@ static void spi_setup_type(spi_transaction *trans) static int spi_setup_opcode(spi_transaction *trans) { + ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr); uint16_t optypes; - uint8_t opmenu[cntlr.menubytes]; + uint8_t opmenu[cntlr->menubytes]; trans->opcode = trans->out[0]; spi_use_out(trans, 1); - if (!ichspi_lock) { + if (!car_get_var(g_ichspi_lock)) { /* The lock is off, so just use index 0. */ - writeb_(trans->opcode, cntlr.opmenu); - optypes = readw_(cntlr.optype); + writeb_(trans->opcode, cntlr->opmenu); + optypes = readw_(cntlr->optype); optypes = (optypes & 0xfffc) | (trans->type & 0x3); - writew_(optypes, cntlr.optype); + writew_(optypes, cntlr->optype); return 0; } else { /* The lock is on. See if what we need is on the menu. */ @@ -332,20 +334,20 @@ static int spi_setup_opcode(spi_transaction *trans) if (trans->opcode == SPI_OPCODE_WREN) return 0; - read_reg(cntlr.opmenu, opmenu, sizeof(opmenu)); - for (opcode_index = 0; opcode_index < cntlr.menubytes; + read_reg(cntlr->opmenu, opmenu, sizeof(opmenu)); + for (opcode_index = 0; opcode_index < cntlr->menubytes; opcode_index++) { if (opmenu[opcode_index] == trans->opcode) break; } - if (opcode_index == cntlr.menubytes) { + if (opcode_index == cntlr->menubytes) { printk(BIOS_DEBUG, "ICH SPI: Opcode %x not found\n", trans->opcode); return -1; } - optypes = readw_(cntlr.optype); + optypes = readw_(cntlr->optype); optype = (optypes >> (opcode_index * 2)) & 0x3; if (trans->type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS && optype == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS && @@ -391,14 +393,15 @@ static int spi_setup_offset(spi_transaction *trans) */ static int ich_status_poll(uint16_t bitmask, int wait_til_set) { + ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr); int timeout = 40000; /* This will result in 400 ms */ uint16_t status = 0; while (timeout--) { - status = readw_(cntlr.status); + status = readw_(cntlr->status); if (wait_til_set ^ ((status & bitmask) == 0)) { if (wait_til_set) - writew_((status & bitmask), cntlr.status); + writew_((status & bitmask), cntlr->status); return status; } udelay(10); @@ -412,6 +415,7 @@ static int ich_status_poll(uint16_t bitmask, int wait_til_set) static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, size_t bytesout, void *din, size_t bytesin) { + ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr); uint16_t control; int16_t opcode_index; int with_address; @@ -437,7 +441,7 @@ static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, if (ich_status_poll(SPIS_SCIP, 0) == -1) return -1; - writew_(SPIS_CDS | SPIS_FCERR, cntlr.status); + writew_(SPIS_CDS | SPIS_FCERR, cntlr->status); spi_setup_type(&trans); if ((opcode_index = spi_setup_opcode(&trans)) < 0) @@ -445,13 +449,13 @@ static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, if ((with_address = spi_setup_offset(&trans)) < 0) return -1; - if (!ichspi_lock && trans.opcode == SPI_OPCODE_WREN) { + if (!car_get_var(g_ichspi_lock) && trans.opcode == SPI_OPCODE_WREN) { /* * Treat Write Enable as Atomic Pre-Op if possible * in order to prevent the Management Engine from * issuing a transaction between WREN and DATA. */ - writew_(trans.opcode, cntlr.preop); + writew_(trans.opcode, cntlr->preop); return 0; } @@ -459,13 +463,13 @@ static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, control = SPIC_SCGO | ((opcode_index & 0x07) << 4); /* Issue atomic preop cycle if needed */ - if (readw_(cntlr.preop)) + if (readw_(cntlr->preop)) control |= SPIC_ACS; if (!trans.bytesout && !trans.bytesin) { /* SPI addresses are 24 bit only */ if (with_address) - writel_(trans.offset & 0x00FFFFFF, cntlr.addr); + writel_(trans.offset & 0x00FFFFFF, cntlr->addr); /* * This is a 'no data' command (like Write Enable), its @@ -473,7 +477,7 @@ static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, * spi_setup_opcode() above. Tell the chip to send the * command. */ - writew_(control, cntlr.control); + writew_(control, cntlr->control); /* wait for the result */ status = ich_status_poll(SPIS_CDS | SPIS_FCERR, 1); @@ -495,7 +499,7 @@ static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, * and followed by other SPI commands, and this sequence is controlled * by the SPI chip driver. */ - if (trans.bytesout > cntlr.databytes) { + if (trans.bytesout > cntlr->databytes) { printk(BIOS_DEBUG, "ICH SPI: Too much to write. Does your SPI chip driver use" " spi_crop_chunk()?\n"); return -1; @@ -509,28 +513,28 @@ static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, uint32_t data_length; /* SPI addresses are 24 bit only */ - writel_(trans.offset & 0x00FFFFFF, cntlr.addr); + writel_(trans.offset & 0x00FFFFFF, cntlr->addr); if (trans.bytesout) - data_length = min(trans.bytesout, cntlr.databytes); + data_length = min(trans.bytesout, cntlr->databytes); else - data_length = min(trans.bytesin, cntlr.databytes); + data_length = min(trans.bytesin, cntlr->databytes); /* Program data into FDATA0 to N */ if (trans.bytesout) { - write_reg(trans.out, cntlr.data, data_length); + write_reg(trans.out, cntlr->data, data_length); spi_use_out(&trans, data_length); if (with_address) trans.offset += data_length; } /* Add proper control fields' values */ - control &= ~((cntlr.databytes - 1) << 8); + control &= ~((cntlr->databytes - 1) << 8); control |= SPIC_DS; control |= (data_length - 1) << 8; /* write it */ - writew_(control, cntlr.control); + writew_(control, cntlr->control); /* Wait for Cycle Done Status or Flash Cycle Error. */ status = ich_status_poll(SPIS_CDS | SPIS_FCERR, 1); @@ -543,7 +547,7 @@ static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, } if (trans.bytesin) { - read_reg(cntlr.data, trans.in, data_length); + read_reg(cntlr->data, trans.in, data_length); spi_use_in(&trans, data_length); if (with_address) trans.offset += data_length; @@ -552,7 +556,7 @@ static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, spi_xfer_exit: /* Clear atomic preop now that xfer is done */ - writew_(0, cntlr.preop); + writew_(0, cntlr->preop); return 0; } From fa6233daeb2bfb8b75bea9032c0839e2d5bcf60d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Thu, 28 Jun 2018 16:55:29 +0300 Subject: [PATCH 133/331] soc/amd/common: Identify AGESA call pattern MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The entry to AGESA always follows pattern: amd_create_struct() amd_dispatch() amd_release_struct() Separate the create/release_struct calls from the more relevant entry point details. Change-Id: I1037c9daef3365c8672a198ac60f47fc79ffaea1 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/31488 Reviewed-by: Richard Spiegel Reviewed-by: Paul Menzel Tested-by: build bot (Jenkins) --- src/soc/amd/common/block/pi/agesawrapper.c | 138 +++++++-------------- 1 file changed, 46 insertions(+), 92 deletions(-) diff --git a/src/soc/amd/common/block/pi/agesawrapper.c b/src/soc/amd/common/block/pi/agesawrapper.c index da6de00568..a39e29ff48 100644 --- a/src/soc/amd/common/block/pi/agesawrapper.c +++ b/src/soc/amd/common/block/pi/agesawrapper.c @@ -65,10 +65,9 @@ AGESA_STATUS amd_late_run_ap_task(AP_EXE_PARAMS *ApExeParams) return module_dispatch(AMD_LATE_RUN_AP_TASK, StdHeader); } -static void *amd_create_struct(AMD_INTERFACE_PARAMS *aip, +static AGESA_STATUS amd_create_struct(AMD_INTERFACE_PARAMS *aip, AGESA_STRUCT_NAME func, void *buf, size_t len) { - AMD_CONFIG_PARAMS *StdHeader; AGESA_STATUS status; /* Should clone entire StdHeader here. */ @@ -77,8 +76,8 @@ static void *amd_create_struct(AMD_INTERFACE_PARAMS *aip, /* If we provide the buffer, API expects it to have StdHeader already filled. */ - if (buf != NULL && len >= sizeof(*StdHeader)) { - memcpy(buf, &aip->StdHeader, sizeof(*StdHeader)); + if (buf != NULL && len >= sizeof(aip->StdHeader)) { + memcpy(buf, &aip->StdHeader, sizeof(aip->StdHeader)); aip->AllocationMethod = ByHost; aip->NewStructPtr = buf; aip->NewStructSize = len; @@ -101,9 +100,7 @@ static void *amd_create_struct(AMD_INTERFACE_PARAMS *aip, if (!aip->NewStructPtr) die("No AGESA structure created"); - StdHeader = aip->NewStructPtr; - StdHeader->Func = aip->AgesaFunctionName; - return StdHeader; + return status; } static AGESA_STATUS amd_release_struct(AMD_INTERFACE_PARAMS *aip) @@ -111,14 +108,9 @@ static AGESA_STATUS amd_release_struct(AMD_INTERFACE_PARAMS *aip) return module_dispatch(AMD_RELEASE_STRUCT, &aip->StdHeader); } -static AGESA_STATUS amd_init_reset(void) +static AGESA_STATUS amd_init_reset(AMD_RESET_PARAMS *ResetParams) { AGESA_STATUS status; - AMD_RESET_PARAMS _ResetParams; - AMD_INTERFACE_PARAMS AmdParamStruct; - - AMD_RESET_PARAMS *ResetParams = amd_create_struct(&AmdParamStruct, - AMD_INIT_RESET, &_ResetParams, sizeof(AMD_RESET_PARAMS)); SetFchResetParams(&ResetParams->FchInterface); @@ -126,17 +118,12 @@ static AGESA_STATUS amd_init_reset(void) status = amd_dispatch(ResetParams); timestamp_add_now(TS_AGESA_INIT_RESET_DONE); - amd_release_struct(&AmdParamStruct); return status; } -static AGESA_STATUS amd_init_early(void) +static AGESA_STATUS amd_init_early(AMD_EARLY_PARAMS *EarlyParams) { AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; - - AMD_EARLY_PARAMS *EarlyParams = amd_create_struct(&AmdParamStruct, - AMD_INIT_EARLY, NULL, 0); soc_customize_init_early(EarlyParams); OemCustomizeInitEarly(EarlyParams); @@ -145,8 +132,6 @@ static AGESA_STATUS amd_init_early(void) status = amd_dispatch(EarlyParams); timestamp_add_now(TS_AGESA_INIT_EARLY_DONE); - amd_release_struct(&AmdParamStruct); - return status; } @@ -183,13 +168,9 @@ static void print_init_post_settings(AMD_POST_PARAMS *parms) uma_size / MiB, uma_start); } -static AGESA_STATUS amd_init_post(void) +static AGESA_STATUS amd_init_post(AMD_POST_PARAMS *PostParams) { AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; - - AMD_POST_PARAMS *PostParams = amd_create_struct(&AmdParamStruct, - AMD_INIT_POST, NULL, 0); PostParams->MemConfig.UmaMode = CONFIG(GFXUMA) ? UMA_AUTO : UMA_NONE; PostParams->MemConfig.UmaSize = 0; @@ -229,18 +210,12 @@ static AGESA_STATUS amd_init_post(void) print_init_post_settings(PostParams); - amd_release_struct(&AmdParamStruct); - return status; } -static AGESA_STATUS amd_init_env(void) +static AGESA_STATUS amd_init_env(AMD_ENV_PARAMS *EnvParams) { AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; - - AMD_ENV_PARAMS *EnvParams = amd_create_struct(&AmdParamStruct, - AMD_INIT_ENV, NULL, 0); SetFchEnvParams(&EnvParams->FchInterface); SetNbEnvParams(&EnvParams->GnbEnvConfiguration); @@ -249,8 +224,6 @@ static AGESA_STATUS amd_init_env(void) status = amd_dispatch(EnvParams); timestamp_add_now(TS_AGESA_INIT_ENV_DONE); - amd_release_struct(&AmdParamStruct); - return status; } @@ -280,17 +253,13 @@ void *agesawrapper_getlateinitptr(int pick) } } -static AGESA_STATUS amd_init_mid(void) +static AGESA_STATUS amd_init_mid(AMD_MID_PARAMS *MidParams) { AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; /* Enable MMIO on AMD CPU Address Map Controller */ amd_initcpuio(); - AMD_MID_PARAMS *MidParams = amd_create_struct(&AmdParamStruct, - AMD_INIT_MID, NULL, 0); - SetFchMidParams(&MidParams->FchInterface); SetNbMidParams(&MidParams->GnbMidConfiguration); @@ -298,22 +267,12 @@ static AGESA_STATUS amd_init_mid(void) status = amd_dispatch(MidParams); timestamp_add_now(TS_AGESA_INIT_MID_DONE); - amd_release_struct(&AmdParamStruct); - return status; } -static AGESA_STATUS amd_init_late(void) +static AGESA_STATUS amd_init_late(AMD_LATE_PARAMS *LateParams) { AGESA_STATUS Status; - AMD_INTERFACE_PARAMS AmdParamStruct; - - /* - * NOTE: if not call amdcreatestruct, the initializer - * (AmdInitLateInitializer) would not be called. - */ - AMD_LATE_PARAMS *LateParams = amd_create_struct(&AmdParamStruct, - AMD_INIT_LATE, NULL, 0); const struct device *dev = pcidev_path_on_root(IOMMU_DEVFN); if (dev && dev->enabled) { @@ -342,17 +301,12 @@ static AGESA_STATUS amd_init_late(void) AcpiSlit, AcpiWheaMce, AcpiWheaCmc, AcpiAlib, AcpiIvrs, __func__); - amd_release_struct(&AmdParamStruct); return Status; } -static AGESA_STATUS amd_init_rtb(void) +static AGESA_STATUS amd_init_rtb(AMD_RTB_PARAMS *RtbParams) { AGESA_STATUS Status; - AMD_INTERFACE_PARAMS AmdParamStruct; - - AMD_RTB_PARAMS *RtbParams = amd_create_struct(&AmdParamStruct, - AMD_INIT_RTB, NULL, 0); timestamp_add_now(TS_AGESA_INIT_RTB_START); Status = amd_dispatch(RtbParams); @@ -364,20 +318,14 @@ static AGESA_STATUS amd_init_rtb(void) RtbParams->S3DataBlock.VolatileStorageSize)) printk(BIOS_ERR, "S3 data not saved, resuming impossible\n"); - amd_release_struct(&AmdParamStruct); - return Status; } -static AGESA_STATUS amd_init_resume(void) +static AGESA_STATUS amd_init_resume(AMD_RESUME_PARAMS *InitResumeParams) { AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; size_t nv_size; - AMD_RESUME_PARAMS *InitResumeParams = amd_create_struct(&AmdParamStruct, - AMD_INIT_RESUME, NULL, 0); - get_s3nv_info(&InitResumeParams->S3DataBlock.NvStorage, &nv_size); InitResumeParams->S3DataBlock.NvStorageSize = nv_size; @@ -385,23 +333,16 @@ static AGESA_STATUS amd_init_resume(void) status = amd_dispatch(InitResumeParams); timestamp_add_now(TS_AGESA_INIT_RESUME_DONE); - amd_release_struct(&AmdParamStruct); - return status; } -static AGESA_STATUS amd_s3late_restore(void) +static AGESA_STATUS amd_s3late_restore(AMD_S3LATE_PARAMS *S3LateParams) { AGESA_STATUS Status; - AMD_S3LATE_PARAMS _S3LateParams; - AMD_INTERFACE_PARAMS AmdParamStruct; size_t vol_size; amd_initcpuio(); - AMD_S3LATE_PARAMS *S3LateParams = amd_create_struct(&AmdParamStruct, - AMD_S3LATE_RESTORE, &_S3LateParams, sizeof(AMD_S3LATE_PARAMS)); - get_s3vol_info(&S3LateParams->S3DataBlock.VolatileStorage, &vol_size); S3LateParams->S3DataBlock.VolatileStorageSize = vol_size; @@ -409,21 +350,14 @@ static AGESA_STATUS amd_s3late_restore(void) Status = amd_dispatch(S3LateParams); timestamp_add_now(TS_AGESA_S3_LATE_DONE); - amd_release_struct(&AmdParamStruct); - return Status; } -static AGESA_STATUS amd_s3final_restore(void) +static AGESA_STATUS amd_s3final_restore(AMD_S3FINAL_PARAMS *S3FinalParams) { AGESA_STATUS Status; - AMD_S3FINAL_PARAMS _S3FinalParams; - AMD_INTERFACE_PARAMS AmdParamStruct; size_t vol_size; - AMD_S3FINAL_PARAMS *S3FinalParams = amd_create_struct(&AmdParamStruct, - AMD_S3FINAL_RESTORE, &_S3FinalParams, sizeof(AMD_S3FINAL_PARAMS)); - get_s3vol_info(&S3FinalParams->S3DataBlock.VolatileStorage, &vol_size); S3FinalParams->S3DataBlock.VolatileStorageSize = vol_size; @@ -431,22 +365,22 @@ static AGESA_STATUS amd_s3final_restore(void) Status = amd_dispatch(S3FinalParams); timestamp_add_now(TS_AGESA_S3_FINAL_DONE); - amd_release_struct(&AmdParamStruct); - return Status; } static AGESA_STATUS romstage_dispatch(AMD_CONFIG_PARAMS *StdHeader) { + void *Params = StdHeader; + switch (StdHeader->Func) { case AMD_INIT_RESET: - return amd_init_reset(); + return amd_init_reset(Params); case AMD_INIT_EARLY: - return amd_init_early(); + return amd_init_early(Params); case AMD_INIT_POST: - return amd_init_post(); + return amd_init_post(Params); case AMD_INIT_RESUME: - return amd_init_resume(); + return amd_init_resume(Params); default: return AGESA_UNSUPPORTED; } @@ -454,22 +388,25 @@ static AGESA_STATUS romstage_dispatch(AMD_CONFIG_PARAMS *StdHeader) static AGESA_STATUS ramstage_dispatch(AMD_CONFIG_PARAMS *StdHeader) { + void *Params = StdHeader; + switch (StdHeader->Func) { case AMD_INIT_ENV: - return amd_init_env(); + return amd_init_env(Params); case AMD_INIT_MID: - return amd_init_mid(); + return amd_init_mid(Params); case AMD_INIT_LATE: - return amd_init_late(); + return amd_init_late(Params); case AMD_INIT_RTB: - return amd_init_rtb(); + return amd_init_rtb(Params); case AMD_S3LATE_RESTORE: - return amd_s3late_restore(); + return amd_s3late_restore(Params); case AMD_S3FINAL_RESTORE: - return amd_s3final_restore(); + return amd_s3final_restore(Params); default: return AGESA_UNSUPPORTED; } + } AGESA_STATUS agesa_execute_state(AGESA_STRUCT_NAME func) @@ -477,7 +414,23 @@ AGESA_STATUS agesa_execute_state(AGESA_STRUCT_NAME func) AGESA_STATUS status = AGESA_UNSUPPORTED; AMD_CONFIG_PARAMS template = {}; AMD_CONFIG_PARAMS *StdHeader = &template; + AMD_INTERFACE_PARAMS AmdParamStruct; + AMD_INTERFACE_PARAMS *aip = &AmdParamStruct; + union { + AMD_RESET_PARAMS ResetParams; + AMD_S3LATE_PARAMS S3LateParams; + AMD_S3FINAL_PARAMS S3FinalParams; + } sp; + if ((func == AMD_INIT_RESET) || (func == AMD_S3LATE_RESTORE) || + (func == AMD_S3FINAL_RESTORE)) { + memset(&sp, 0, sizeof(sp)); + amd_create_struct(aip, func, &sp, sizeof(sp)); + } else { + amd_create_struct(aip, func, NULL, 0); + } + + StdHeader = aip->NewStructPtr; StdHeader->Func = func; if (ENV_ROMSTAGE) @@ -485,5 +438,6 @@ AGESA_STATUS agesa_execute_state(AGESA_STRUCT_NAME func) if (ENV_RAMSTAGE) status = ramstage_dispatch(StdHeader); + amd_release_struct(aip); return status; } From d93531bcc8a216d9bc82a7f13444833943a270d7 Mon Sep 17 00:00:00 2001 From: Tim Wawrzynczak Date: Tue, 30 Apr 2019 12:52:29 -0600 Subject: [PATCH 134/331] soc/intel/cannonlake: Dump ME f/w version and status information At the end of device enable, print the ME f/w version number. Before resume or loading payload, dump the ME's Host Firmware Status registers. BUG=b:131437724 BRANCH=none TEST=Prints seemingly sane values on WHL and CML devices. Change-Id: Ibeb3a2a85cd84c9baa45f90f20a3dcf69f7d5646 Signed-off-by: Tim Wawrzynczak Reviewed-on: https://review.coreboot.org/c/coreboot/+/32527 Reviewed-by: Paul Fagerburg Reviewed-by: Furquan Shaikh Reviewed-by: Subrata Banik Reviewed-by: Paul Menzel Tested-by: build bot (Jenkins) --- src/soc/intel/cannonlake/Makefile.inc | 1 + src/soc/intel/cannonlake/finalize.c | 3 + src/soc/intel/cannonlake/include/soc/me.h | 21 ++ src/soc/intel/cannonlake/me.c | 299 ++++++++++++++++++++++ 4 files changed, 324 insertions(+) create mode 100644 src/soc/intel/cannonlake/include/soc/me.h create mode 100644 src/soc/intel/cannonlake/me.c diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc index 7ad0c7c82c..13289448b6 100644 --- a/src/soc/intel/cannonlake/Makefile.inc +++ b/src/soc/intel/cannonlake/Makefile.inc @@ -43,6 +43,7 @@ ramstage-y += gspi.c ramstage-y += i2c.c ramstage-y += lockdown.c ramstage-y += lpc.c +ramstage-y += me.c ramstage-y += memmap.c ramstage-y += nhlt.c ramstage-y += p2sb.c diff --git a/src/soc/intel/cannonlake/finalize.c b/src/soc/intel/cannonlake/finalize.c index 4dfd15bc4a..eb4c5c2c9d 100644 --- a/src/soc/intel/cannonlake/finalize.c +++ b/src/soc/intel/cannonlake/finalize.c @@ -26,6 +26,7 @@ #include #include #include +#include #include #include #include @@ -94,6 +95,8 @@ static void soc_finalize(void *unused) { printk(BIOS_DEBUG, "Finalizing chipset.\n"); + dump_me_status(); + pch_finalize(); printk(BIOS_DEBUG, "Finalizing SMM.\n"); diff --git a/src/soc/intel/cannonlake/include/soc/me.h b/src/soc/intel/cannonlake/include/soc/me.h new file mode 100644 index 0000000000..1d782c153c --- /dev/null +++ b/src/soc/intel/cannonlake/include/soc/me.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _CANNONLAKE_ME_H_ +#define _CANNONLAKE_ME_H_ + +void dump_me_status(void); + +#endif /* _CANNONLAKE_ME_H_ */ diff --git a/src/soc/intel/cannonlake/me.c b/src/soc/intel/cannonlake/me.c new file mode 100644 index 0000000000..3fedc6374e --- /dev/null +++ b/src/soc/intel/cannonlake/me.c @@ -0,0 +1,299 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Google LLC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* Miscellaneous constants */ +enum { + MKHI_GEN_GROUP_ID = 0xFF, + MKHI_GET_FW_VERSION = 0x02, + ME_OPMODE_NORMAL = 0x00, + ME_WSTATE_NORMAL = 0x05, +}; + +/* HFSTS register offsets in PCI config space */ +enum { + PCI_ME_HFSTS1 = 0x40, + PCI_ME_HFSTS2 = 0x48, + PCI_ME_HFSTS3 = 0x60, + PCI_ME_HFSTS4 = 0x64, + PCI_ME_HFSTS5 = 0x68, + PCI_ME_HFSTS6 = 0x6C, +}; + +/* Host Firmware Status Register 1 */ +union hfsts1 { + uint32_t raw; + struct { + uint32_t working_state : 4; + uint32_t mfg_mode : 1; + uint32_t fpt_bad : 1; + uint32_t operation_state : 3; + uint32_t fw_init_complete : 1; + uint32_t ft_bup_ld_flr : 1; + uint32_t fw_upd_in_progress : 1; + uint32_t error_code : 4; + uint32_t operation_mode : 4; + uint32_t reset_count : 4; + uint32_t boot_options : 1; + uint32_t rsvd0 : 1; + uint32_t bist_state : 1; + uint32_t bist_reset_req : 1; + uint32_t power_source : 2; + uint32_t reserved1 : 1; + uint32_t d0i3_support_valid : 1; + } __packed fields; +}; + +/* Host Firmware Status Register 2 */ +union hfsts2 { + uint32_t raw; + struct { + uint32_t nftp_load_failure : 1; + uint32_t icc_prog_status : 2; + uint32_t invoke_mebx : 1; + uint32_t cpu_replaced : 1; + uint32_t rsvd0 : 1; + uint32_t mfs_failure : 1; + uint32_t warm_reset_rqst : 1; + uint32_t cpu_replaced_valid : 1; + uint32_t low_power_state : 1; + uint32_t me_power_gate : 1; + uint32_t ipu_needed : 1; + uint32_t forced_safe_boot : 1; + uint32_t rsvd1 : 2; + uint32_t listener_change : 1; + uint32_t status_data : 8; + uint32_t current_pmevent : 4; + uint32_t phase : 4; + } __packed fields; +}; + +/* Host Firmware Status Register 3 */ +union hfsts3 { + uint32_t raw; +}; + +/* Host Firmware Status Register 4 */ +union hfsts4 { + uint32_t raw; + struct { + uint32_t rsvd0 : 9; + uint32_t enforcement_flow : 1; + uint32_t sx_resume_type : 1; + uint32_t rsvd1 : 1; + uint32_t tpms_disconnected : 1; + uint32_t rvsd2 : 1; + uint32_t fwsts_valid : 1; + uint32_t boot_guard_self_test : 1; + uint32_t rsvd3 : 16; + } __packed fields; +}; + +/* Host Firmware Status Register 5 */ +union hfsts5 { + uint32_t raw; + struct { + uint32_t acm_active : 1; + uint32_t valid : 1; + uint32_t result_code_source : 1; + uint32_t error_status_code : 5; + uint32_t acm_done_sts : 1; + uint32_t timeout_count : 7; + uint32_t scrtm_indicator : 1; + uint32_t inc_boot_guard_acm : 4; + uint32_t inc_key_manifest : 4; + uint32_t inc_boot_policy : 4; + uint32_t rsvd0 : 2; + uint32_t start_enforcement : 1; + } __packed fields; +}; + +/* Host Firmware Status Register 6 */ +union hfsts6 { + uint32_t raw; + struct { + uint32_t force_boot_guard_acm : 1; + uint32_t cpu_debug_disable : 1; + uint32_t bsp_init_disable : 1; + uint32_t protect_bios_env : 1; + uint32_t rsvd0 : 2; + uint32_t error_enforce_policy : 2; + uint32_t measured_boot : 1; + uint32_t verified_boot : 1; + uint32_t boot_guard_acmsvn : 4; + uint32_t kmsvn : 4; + uint32_t bpmsvn : 4; + uint32_t key_manifest_id : 4; + uint32_t boot_policy_status : 1; + uint32_t error : 1; + uint32_t boot_guard_disable : 1; + uint32_t fpf_disable : 1; + uint32_t fpf_soc_lock : 1; + uint32_t txt_support : 1; + } __packed fields; +}; + +static uint32_t me_read_config32(int offset) +{ + return pci_read_config32(PCH_DEV_CSE, offset); +} + +/* + * From reading the documentation, this should work for both WHL and CML + * platforms. Also, calling this function from dump_me_status() does not + * work, as the ME does not respond and the command times out. + */ +static void print_me_version(void *unused) +{ + struct mkhi_hdr { + uint8_t group_id; + uint8_t command :7; + uint8_t is_resp :1; + uint8_t rsvd; + uint8_t result; + } __packed; + + struct version { + uint16_t minor; + uint16_t major; + uint16_t build; + uint16_t hotfix; + } __packed; + + struct fw_ver_resp { + struct mkhi_hdr hdr; + struct version code; + struct version rec; + struct version fitc; + } __packed; + + union hfsts1 hfsts1; + const struct mkhi_hdr fw_ver_msg = { + .group_id = MKHI_GEN_GROUP_ID, + .command = MKHI_GET_FW_VERSION, + }; + struct fw_ver_resp resp; + size_t resp_size = sizeof(resp); + + /* Ignore if UART debugging is disabled */ + if (!CONFIG(CONSOLE_SERIAL)) + return; + + hfsts1.raw = me_read_config32(PCI_ME_HFSTS1); + + /* + * Prerequisites: + * 1) HFSTS1 Current Working State is Normal + * 2) HFSTS1 Current Operation Mode is Normal + * 3) It's after DRAM INIT DONE message (taken care of by calling it + * during ramstage + */ + if ((hfsts1.fields.working_state != ME_WSTATE_NORMAL) || + (hfsts1.fields.operation_mode != ME_OPMODE_NORMAL)) + goto fail; + + heci_reset(); + + if (!heci_send(&fw_ver_msg, sizeof(fw_ver_msg), BIOS_HOST_ADDR, + HECI_MKHI_ADDR)) + goto fail; + + if (!heci_receive(&resp, &resp_size)) + goto fail; + + if (resp.hdr.result) + goto fail; + + printk(BIOS_DEBUG, "ME: Version: %d.%d.%d.%d\n", resp.code.major, + resp.code.minor, resp.code.hotfix, resp.code.build); + return; + +fail: + printk(BIOS_DEBUG, "ME: Version: Unavailable\n"); +} +BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_EXIT, print_me_version, NULL); + +void dump_me_status(void) +{ + union hfsts1 hfsts1; + union hfsts2 hfsts2; + union hfsts3 hfsts3; + union hfsts4 hfsts4; + union hfsts5 hfsts5; + union hfsts6 hfsts6; + + hfsts1.raw = me_read_config32(PCI_ME_HFSTS1); + hfsts2.raw = me_read_config32(PCI_ME_HFSTS2); + hfsts3.raw = me_read_config32(PCI_ME_HFSTS3); + hfsts4.raw = me_read_config32(PCI_ME_HFSTS4); + hfsts5.raw = me_read_config32(PCI_ME_HFSTS5); + hfsts6.raw = me_read_config32(PCI_ME_HFSTS6); + + printk(BIOS_DEBUG, "ME: HFSTS1 : 0x%08X\n", + hfsts1.raw); + printk(BIOS_DEBUG, "ME: HFSTS2 : 0x%08X\n", + hfsts2.raw); + printk(BIOS_DEBUG, "ME: HFSTS3 : 0x%08X\n", + hfsts3.raw); + printk(BIOS_DEBUG, "ME: HFSTS4 : 0x%08X\n", + hfsts4.raw); + printk(BIOS_DEBUG, "ME: HFSTS5 : 0x%08X\n", + hfsts5.raw); + printk(BIOS_DEBUG, "ME: HFSTS6 : 0x%08X\n", + hfsts6.raw); + + printk(BIOS_DEBUG, "ME: Manufacturing Mode : %s\n", + hfsts1.fields.mfg_mode ? "YES" : "NO"); + printk(BIOS_DEBUG, "ME: FW Partition Table : %s\n", + hfsts1.fields.fpt_bad ? "BAD" : "OK"); + printk(BIOS_DEBUG, "ME: Bringup Loader Failure : %s\n", + hfsts1.fields.ft_bup_ld_flr ? "YES" : "NO"); + printk(BIOS_DEBUG, "ME: Firmware Init Complete : %s\n", + hfsts1.fields.fw_init_complete ? "YES" : "NO"); + printk(BIOS_DEBUG, "ME: Boot Options Present : %s\n", + hfsts1.fields.boot_options ? "YES" : "NO"); + printk(BIOS_DEBUG, "ME: Update In Progress : %s\n", + hfsts1.fields.fw_upd_in_progress ? "YES" : "NO"); + printk(BIOS_DEBUG, "ME: D0i3 Support : %s\n", + hfsts1.fields.d0i3_support_valid ? "YES" : "NO"); + printk(BIOS_DEBUG, "ME: Low Power State Enabled : %s\n", + hfsts2.fields.low_power_state ? "YES" : "NO"); + printk(BIOS_DEBUG, "ME: CPU Replaced : %s\n", + hfsts2.fields.cpu_replaced ? "YES" : "NO"); + printk(BIOS_DEBUG, "ME: CPU Replacement Valid : %s\n", + hfsts2.fields.cpu_replaced_valid ? "YES" : "NO"); + printk(BIOS_DEBUG, "ME: Current Working State : %u\n", + hfsts1.fields.working_state); + printk(BIOS_DEBUG, "ME: Current Operation State : %u\n", + hfsts1.fields.operation_state); + printk(BIOS_DEBUG, "ME: Current Operation Mode : %u\n", + hfsts1.fields.operation_mode); + printk(BIOS_DEBUG, "ME: Error Code : %u\n", + hfsts1.fields.error_code); + printk(BIOS_DEBUG, "ME: CPU Debug Disabled : %s\n", + hfsts6.fields.cpu_debug_disable ? "YES" : "NO"); + printk(BIOS_DEBUG, "ME: TXT Support : %s\n", + hfsts6.fields.txt_support ? "YES" : "NO"); +} From fa40e822700f78489a3cd8be65365a9e7249eecf Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Mon, 20 May 2019 22:26:08 +0200 Subject: [PATCH 135/331] util/sconfig: Move 'static' at beginning of declaration When using -Werror=old-style-declaration, gcc reports an error: "'static' is not at beginning of declaration" Tested on 945G-M4 board. Change-Id: I7216a4fab2d5878066c871166e6a481d1f201a9d Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/32900 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi Reviewed-by: Paul Menzel --- util/sconfig/main.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/util/sconfig/main.c b/util/sconfig/main.c index c3aa17f1a0..548063fd88 100644 --- a/util/sconfig/main.c +++ b/util/sconfig/main.c @@ -701,7 +701,7 @@ static void pass0(FILE *fil, struct device *ptr, struct device *next) return; } - fprintf(fil, "DEVTREE_CONST static struct device %s;\n", ptr->name); + fprintf(fil, "static DEVTREE_CONST struct device %s;\n", ptr->name); if (ptr->res) fprintf(fil, "DEVTREE_CONST struct resource %s_res[];\n", ptr->name); From 402fe20e3e10f0f2aa1329eb60970e56bf92986e Mon Sep 17 00:00:00 2001 From: Felix Singer Date: Tue, 12 Feb 2019 22:22:42 +0100 Subject: [PATCH 136/331] mb/up/squared: Add mainboard Works: - bootblock, romstage, ramstage - Serial console UART0, UART1 - SPI flash console - iGPU init with libgfxinit - LAN1, LAN2 - USB2, USB3 - HDMI, DisplayPort - eMMC - flashing with flashrom externally WIP: - Documentation - VGA For some reason Seabios can not find the CBFS region and therefore it can't load seavgabios, but generally it is working as soon as Linux is booted. - ACPI Works not: - Devices needs proper configuration - Seabios can't find CBFS region Untested: - GPIO pin header - 60 pin EXHAT - Camera interface - MIPI-CSI2 2-lane (2MP) - MIPI-CSI2 4-lane (8MP) - SATA3 - USB3 OTG - embedded DisplayPort - M.2 slot - mini PCIe - flashing with flashrom internally using Linux Change-Id: Ia913534ec176fc600fcd4ce3af335ebe682b0ed4 Signed-off-by: Felix Singer Reviewed-on: https://review.coreboot.org/c/coreboot/+/31378 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph --- Documentation/mainboard/index.md | 4 + Documentation/mainboard/up/squared/bottom.jpg | Bin 0 -> 38689 bytes Documentation/mainboard/up/squared/index.md | 99 +++ Documentation/mainboard/up/squared/top.jpg | Bin 0 -> 33925 bytes src/mainboard/up/Kconfig | 16 + src/mainboard/up/Kconfig.name | 2 + src/mainboard/up/squared/Kconfig | 88 ++ src/mainboard/up/squared/Kconfig.name | 2 + src/mainboard/up/squared/Makefile.inc | 7 + src/mainboard/up/squared/acpi_tables.c | 0 src/mainboard/up/squared/board_info.txt | 7 + src/mainboard/up/squared/bootblock.c | 22 + src/mainboard/up/squared/data.vbt | Bin 0 -> 6154 bytes src/mainboard/up/squared/devicetree.cb | 50 ++ src/mainboard/up/squared/dsdt.asl | 43 + src/mainboard/up/squared/gma-mainboard.ads | 32 + src/mainboard/up/squared/gpio.h | 773 ++++++++++++++++++ src/mainboard/up/squared/ramstage.c | 432 ++++++++++ src/mainboard/up/squared/romstage.c | 96 +++ src/mainboard/up/squared/upsquared.fmd | 21 + src/mainboard/up/squared/vboot-ro.fmd | 35 + src/mainboard/up/squared/vboot-roa.fmd | 40 + src/mainboard/up/squared/vboot-roab.fmd | 45 + 23 files changed, 1814 insertions(+) create mode 100644 Documentation/mainboard/up/squared/bottom.jpg create mode 100644 Documentation/mainboard/up/squared/index.md create mode 100644 Documentation/mainboard/up/squared/top.jpg create mode 100644 src/mainboard/up/Kconfig create mode 100644 src/mainboard/up/Kconfig.name create mode 100644 src/mainboard/up/squared/Kconfig create mode 100644 src/mainboard/up/squared/Kconfig.name create mode 100644 src/mainboard/up/squared/Makefile.inc create mode 100644 src/mainboard/up/squared/acpi_tables.c create mode 100644 src/mainboard/up/squared/board_info.txt create mode 100644 src/mainboard/up/squared/bootblock.c create mode 100644 src/mainboard/up/squared/data.vbt create mode 100644 src/mainboard/up/squared/devicetree.cb create mode 100644 src/mainboard/up/squared/dsdt.asl create mode 100644 src/mainboard/up/squared/gma-mainboard.ads create mode 100644 src/mainboard/up/squared/gpio.h create mode 100644 src/mainboard/up/squared/ramstage.c create mode 100644 src/mainboard/up/squared/romstage.c create mode 100644 src/mainboard/up/squared/upsquared.fmd create mode 100644 src/mainboard/up/squared/vboot-ro.fmd create mode 100644 src/mainboard/up/squared/vboot-roa.fmd create mode 100644 src/mainboard/up/squared/vboot-roab.fmd diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md index fb637c423b..eced74966e 100644 --- a/Documentation/mainboard/index.md +++ b/Documentation/mainboard/index.md @@ -82,3 +82,7 @@ The boards in this section are not real mainboards, but emulators. ## Supermicro - [X10SLM+-F](supermicro/x10slm-f.md) + +## UP + +- [Squared](up/squared/index.md) diff --git a/Documentation/mainboard/up/squared/bottom.jpg b/Documentation/mainboard/up/squared/bottom.jpg new file mode 100644 index 0000000000000000000000000000000000000000..f9aa85db50a25d26594360c1c0f7ef44c6cc6907 GIT binary patch literal 38689 zcmb5VbyyUC^glYp(%{ldDc!Nl(umS1-MKU@-6bg?ARW>vAzjjqbS@oIB2v;4f`}-0 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/dev/null +++ b/src/mainboard/up/Kconfig @@ -0,0 +1,16 @@ +if VENDOR_UP + +choice + prompt "Mainboard model" + +source "src/mainboard/up/*/Kconfig.name" + +endchoice + +source "src/mainboard/up/*/Kconfig" + +config MAINBOARD_VENDOR + string + default "UP" + +endif diff --git a/src/mainboard/up/Kconfig.name b/src/mainboard/up/Kconfig.name new file mode 100644 index 0000000000..ef694d30f9 --- /dev/null +++ b/src/mainboard/up/Kconfig.name @@ -0,0 +1,2 @@ +config VENDOR_UP + bool "UP" diff --git a/src/mainboard/up/squared/Kconfig b/src/mainboard/up/squared/Kconfig new file mode 100644 index 0000000000..fd03b7a2ae --- /dev/null +++ b/src/mainboard/up/squared/Kconfig @@ -0,0 +1,88 @@ +if BOARD_UP_SQUARED + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select USE_BLOBS + select ADD_FSP_BINARIES + select FSP_USE_REPO + select HAVE_ACPI_TABLES + select HAVE_ACPI_RESUME + select INTEL_GMA_HAVE_VBT + select INTEL_LPSS_UART_FOR_CONSOLE + select SOC_INTEL_APOLLOLAKE + select BOARD_ROMSIZE_KB_16384 + select ONBOARD_VGA_IS_PRIMARY + select MAINBOARD_HAS_LIBGFXINIT + +config VBOOT + select VBOOT_NO_BOARD_SUPPORT + select GBB_FLAG_DISABLE_LID_SHUTDOWN + select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC + select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC + select GBB_FLAG_DISABLE_FWMP + +config GBB_HWID + string + depends on VBOOT + default "UPSQUARED" + +config MAINBOARD_DIR + string + default "up/squared" + +config MAINBOARD_VENDOR + string + default "Up" + +config MAINBOARD_PART_NUMBER + string + default "Squared" + +config FMDFILE + string + default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/upsquared.fmd" if !VBOOT + default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/vboot-ro.fmd" if !VBOOT_SLOTS_RW_A + default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/vboot-roa.fmd" if VBOOT_SLOTS_RW_A && !VBOOT_SLOTS_RW_AB + default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/vboot-roab.fmd" if VBOOT_SLOTS_RW_AB + +config SUBSYSTEM_VENDOR_ID + hex + default 0x8086 + +config SUBSYSTEM_DEVICE_ID + hex + default 0x7270 + +config VGA_BIOS_ID + string + default "8086,5a85" + +config PXE_ROM_ID + string + default "10ec,8168" + +config MAX_CPUS + int + default 2 + +config UART_FOR_CONSOLE + int + default 0 + +config IFWI_FMAP_NAME + string + default "IFWI" + +config POST_IO + bool + default n + +config POST_DEVICE + bool + default n + +config CONSOLE_POST + bool + default y + +endif diff --git a/src/mainboard/up/squared/Kconfig.name b/src/mainboard/up/squared/Kconfig.name new file mode 100644 index 0000000000..4d6a59bb7c --- /dev/null +++ b/src/mainboard/up/squared/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_UP_SQUARED + bool "Squared" diff --git a/src/mainboard/up/squared/Makefile.inc b/src/mainboard/up/squared/Makefile.inc new file mode 100644 index 0000000000..af2508e8cf --- /dev/null +++ b/src/mainboard/up/squared/Makefile.inc @@ -0,0 +1,7 @@ +bootblock-y += bootblock.c + +romstage-y += romstage.c + +ramstage-y += ramstage.c + +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/up/squared/acpi_tables.c b/src/mainboard/up/squared/acpi_tables.c new file mode 100644 index 0000000000..e69de29bb2 diff --git a/src/mainboard/up/squared/board_info.txt b/src/mainboard/up/squared/board_info.txt new file mode 100644 index 0000000000..851af32a78 --- /dev/null +++ b/src/mainboard/up/squared/board_info.txt @@ -0,0 +1,7 @@ +Vendor name: Up +Board name: Squared +Category: mini +ROM protocol: SPI +ROM socketed: n +Flashrom support: n +Release year: 2017 diff --git a/src/mainboard/up/squared/bootblock.c b/src/mainboard/up/squared/bootblock.c new file mode 100644 index 0000000000..e35e8b8e7f --- /dev/null +++ b/src/mainboard/up/squared/bootblock.c @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include + +void bootblock_mainboard_init(void) +{ + lpc_configure_pads(); +} diff --git a/src/mainboard/up/squared/data.vbt b/src/mainboard/up/squared/data.vbt new file mode 100644 index 0000000000000000000000000000000000000000..a8b5550108122e4967cbade00c0bd227e15a1328 GIT binary patch literal 6154 zcmeHLZ)_Ar6o0$h`!~CLy>3y;QOoehaxKtq3mm0ZyVonF2Q9s8ORdqQ*K&t67Fyb( zMZ~VLBuxzFKBz%Mw8j_>erck9GDiHMk`SdeQNt%o&;*GjBx3XfaK72y_S$0810jm^ zUEa={nYX`r^XARW+gsIA)l91z8(Nzic2J9ApaRMH37sHZw68zjcgSBKywHUZ)l{|p{77n)0X8p6Et45j2zK`z?CpGVPe1hq z3uq~hv(CUZOs2u^-ku^F=<1@4Os9`F#{1&EPsd|LGGRa`!I{AUa5l(12^?H21#AGP z1{oS?C;(&tXgHu%%oy6Jc!1x?@z|a31bfb8KScrI1uQ)HKC4=k0blL`j|VOyHpMoF z+3o=kN6`|CH25}(TF$GM78X2qdC*i-%TT43w%cW5Sye2iW2IVWYfbN&F4O6iIpu$< zCEy&cK8x_yv^n4y0k}C8cDwRmtKfrvfrsaXGFXvu3Y;zqYg`_91UZ6y+D70zx@zm!dAT*OXjOq ztDa1{qFCjP(701ia+(FQNy+5hE=k$24fnF(tQg8Q=CTuG@GV(@0U%kp$t+T&$)GeE z7QG2}ui53OnADkF{+m5sb~r5kl^=5u7;{|VhO_^h(rlm2T~8*nESg(qq32%qKyEF3 z@6r==;sK8{y2A8C-mSGPdjfA(o&y(N_&nI~fROOgu7+9&O!F}Iaj+blYEjKpF`8;o zGYYG~2Nd5jnpozbVbz6=HlP$T`Ds9ZBl^5JaNmrM6BYp!yaK{QgtilRx;gWiJMls zm57@>?v@LAo6b*gdY0Qrbez2so;|I+WRzDp507zXVpn2ipO5t%nKSFE?XaUGqbB6sULXLk>F!D1*z!hf*6_~EgJqxuE zjzvJ#)Sm1q8(63yNdq=-S_lI);`L~rX$V}xb`uEi7Y|HCy!l$|v6Ky5!fqgF_R%zK zsIAo0j?q$0JDEbTn;DSQVoS%9yO+0|h(MlNld#r;c`{+#ooGrret51ZF%tFWX)3kW z0#`F5fjKOCQg@^?3txpk(lfde5enH`0El2q7%LeAbZR3gOI@e zXn3;BhzAzrb4N8_uIKD8Tc@?IORa?fnFazLV)ps>MS%uU9kQbyPZoR2w1Iu8pbd33 z;kI!5zIfM;_Pz1{L4{3fCark^?AuOZPJZIfJwKX7{482~9~`YgvqG4u?}RYKU@i9= zTo8&z0fwjOt`OH7r-13=4StN=1O}3^r)IhxZ +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI v2.0 and up + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 // OEM revision +) +{ + /* global NVS and variables */ + #include + + /* CPU */ + #include + + Scope (\_SB) { + Device (PCI0) + { + #include + #include + #include + } + } + + /* Chipset specific sleep states */ + #include +} diff --git a/src/mainboard/up/squared/gma-mainboard.ads b/src/mainboard/up/squared/gma-mainboard.ads new file mode 100644 index 0000000000..6865970e16 --- /dev/null +++ b/src/mainboard/up/squared/gma-mainboard.ads @@ -0,0 +1,32 @@ +-- +-- This file is part of the coreboot project. +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (DP1, + DP2, + DP3, + HDMI1, + HDMI2, + HDMI3, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/up/squared/gpio.h b/src/mainboard/up/squared/gpio.h new file mode 100644 index 0000000000..b4ac4e9b6d --- /dev/null +++ b/src/mainboard/up/squared/gpio.h @@ -0,0 +1,773 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Felix Singer + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#include + +#ifndef GPIO_H +#define GPIO_H + +static const struct pad_config gpio_table[] = { + // ******************************** + // ******* GPIO Group North ******* + // ******************************** + // *GPIO + _PAD_CFG_STRUCT(GPIO_0, 0x04000102, 0x00000000), + + // *GPIO + _PAD_CFG_STRUCT(GPIO_1, 0x04000102, 0x00000000), + + // *GPIO + _PAD_CFG_STRUCT(GPIO_2, 0x04000100, 0x00000000), + + // *GPIO + _PAD_CFG_STRUCT(GPIO_3, 0x04000100, 0x00000000), + + // *GPIO + _PAD_CFG_STRUCT(GPIO_4, 0x04000100, 0x00000000), + + // *GPIO + _PAD_CFG_STRUCT(GPIO_5, 0x44000100, 0x00000000), + + // *GPIO + _PAD_CFG_STRUCT(GPIO_6, 0x44000201, 0x00000000), + + // *GPIO + _PAD_CFG_STRUCT(GPIO_7, 0x44000201, 0x00000000), + + // *GPIO + _PAD_CFG_STRUCT(GPIO_8, 0x44000201, 0x00000000), + + // *GPIO + _PAD_CFG_STRUCT(GPIO_9, 0x44000201, 0x00000000), + + // *GPIO + _PAD_CFG_STRUCT(GPIO_10, 0x44000201, 0x00000000), + + // *GPIO + _PAD_CFG_STRUCT(GPIO_11, 0x44000201, 0x00000000), + + // *GPIO + _PAD_CFG_STRUCT(GPIO_12, 0x44000201, 0x00000000), + + // *GPIO + _PAD_CFG_STRUCT(GPIO_13, 0x44000100, 0x00000000), + + // *GPIO + _PAD_CFG_STRUCT(GPIO_14, 0x44000102, 0x00000000), + + // *GPIO + _PAD_CFG_STRUCT(GPIO_15, 0x44000102, 0x00000000), + + // *GPIO + _PAD_CFG_STRUCT(GPIO_16, 0x40880102, 0x00024000), + + // *GPIO + _PAD_CFG_STRUCT(GPIO_17, 0x44000201, 0x00000000), + + // *GPIO + _PAD_CFG_STRUCT(GPIO_18, 0x44000201, 0x00000000), + + // *GPIO + _PAD_CFG_STRUCT(GPIO_19, 0x44000201, 0x00003000), + + // *GPIO + _PAD_CFG_STRUCT(GPIO_20, 0x44000100, 0x00000000), + + // *GPIO + _PAD_CFG_STRUCT(GPIO_21, 0x44000201, 0x00000000), + + // *GPIO + _PAD_CFG_STRUCT(GPIO_22, 0x44000102, 0x00000000), + + // *GPIO + _PAD_CFG_STRUCT(GPIO_23, 0x44000100, 0x00000000), + + // *GPIO + _PAD_CFG_STRUCT(GPIO_24, 0x44000102, 0x00000000), + + // *GPIO + _PAD_CFG_STRUCT(GPIO_25, 0x44000102, 0x00000000), + + // *GPIO + _PAD_CFG_STRUCT(GPIO_26, 0x44000100, 0x00000000), + + // *GPIO + _PAD_CFG_STRUCT(GPIO_27, 0x44000201, 0x00000000), + + // *GPIO + _PAD_CFG_STRUCT(GPIO_28, 0x44000102, 0x00003000), + + // *GPIO + _PAD_CFG_STRUCT(GPIO_29, 0x44000102, 0x00003000), + + // *GPIO + _PAD_CFG_STRUCT(GPIO_30, 0x44000102, 0x00003000), + + // *GPIO + _PAD_CFG_STRUCT(GPIO_31, 0x44000102, 0x00003000), + + // *GPIO + _PAD_CFG_STRUCT(GPIO_32, 0x44000102, 0x00000000), + + // *GPIO + _PAD_CFG_STRUCT(GPIO_33, 0x44000102, 0x00000000), + + // PWM0 + _PAD_CFG_STRUCT(GPIO_34, 0x44000400, 0x00001000), + + // PWM1 + _PAD_CFG_STRUCT(GPIO_35, 0x44000400, 0x00001000), + + // *GPIO + _PAD_CFG_STRUCT(GPIO_36, 0x44000201, 0x00000000), + + // PWM3 + _PAD_CFG_STRUCT(GPIO_37, 0x04000400, 0x00001000), + + // LPSS_UART0_RXD + _PAD_CFG_STRUCT(GPIO_38, 0x44000402, 0x00023100), + + // LPSS_UART0_TXD + _PAD_CFG_STRUCT(GPIO_39, 0x44000400, 0x00003100), + + // LPSS_UART0_RTS_N + _PAD_CFG_STRUCT(GPIO_40, 0x44000400, 0x00003100), + + // LPSS_UART0_CTS_N + _PAD_CFG_STRUCT(GPIO_41, 0x44000402, 0x00023100), + + // LPSS_UART1_RXD + _PAD_CFG_STRUCT(GPIO_42, 0x44000402, 0x00023100), + + // LPSS_UART1_TXD + _PAD_CFG_STRUCT(GPIO_43, 0x44000400, 0x0001f100), + + // LPSS_UART1_RTS_N + _PAD_CFG_STRUCT(GPIO_44, 0x44000400, 0x00003100), + + // LPSS_UART1_CTS_N + _PAD_CFG_STRUCT(GPIO_45, 0x44000402, 0x0001c100), + + // *GPIO + _PAD_CFG_STRUCT(GPIO_46, 0x44000100, 0x00000000), + + // *GPIO + _PAD_CFG_STRUCT(GPIO_47, 0x44000100, 0x00000000), + + // *GPIO + _PAD_CFG_STRUCT(GPIO_48, 0x44000100, 0x00000000), + + // *GPIO + _PAD_CFG_STRUCT(GPIO_49, 0x44000100, 0x00000000), + + // *GPIO + _PAD_CFG_STRUCT(GPIO_62, 0x44000100, 0x00000000), + + // *GPIO + _PAD_CFG_STRUCT(GPIO_63, 0x44000100, 0x00000000), + + // *GPIO + _PAD_CFG_STRUCT(GPIO_64, 0x44000100, 0x00000000), + + // *GPIO + _PAD_CFG_STRUCT(GPIO_65, 0x44000100, 0x00000000), + + // *GPIO + _PAD_CFG_STRUCT(GPIO_66, 0x44000100, 0x00000000), + + // *GPIO + _PAD_CFG_STRUCT(GPIO_67, 0x44000100, 0x00000000), + + // *GPIO + _PAD_CFG_STRUCT(GPIO_68, 0x44000100, 0x00000000), + + // *GPIO + _PAD_CFG_STRUCT(GPIO_69, 0x44000100, 0x00000000), + + // *GPIO + _PAD_CFG_STRUCT(GPIO_70, 0x44000100, 0x00000000), + + // *GPIO + _PAD_CFG_STRUCT(GPIO_71, 0x44000100, 0x00000000), + + // *GPIO + _PAD_CFG_STRUCT(GPIO_72, 0x44000200, 0x00001000), + + // *GPIO + _PAD_CFG_STRUCT(GPIO_73, 0x44000200, 0x00001000), + + // *JTAG_TCK + _PAD_CFG_STRUCT(TCK, 0x44000400, 0x00c3d000), + + // *JTAG_TRST_N + _PAD_CFG_STRUCT(TRST_B, 0x44000400, 0x00c3d000), + + // *JTAG_TMS + _PAD_CFG_STRUCT(TMS, 0x44000400, 0x00c3f000), + + // *JTAG_TDI + _PAD_CFG_STRUCT(TDI, 0x44000400, 0x00c3f000), + + // *JTAG_PMODE + _PAD_CFG_STRUCT(CX_PMODE, 0x44000400, 0x00c3c000), + + // *JTAG_PREQ_N + _PAD_CFG_STRUCT(CX_PREQ_B, 0x44000402, 0x00c3f000), + + // *JTAGX + _PAD_CFG_STRUCT(JTAGX, 0x44000402, 0x00c3f000), + + // *JTAG_PRDY_N + _PAD_CFG_STRUCT(CX_PRDY_B, 0x44000402, 0x0043f000), + + // *JTAG_TDO + _PAD_CFG_STRUCT(TDO, 0x44000400, 0x0043f000), + + // GPIO + _PAD_CFG_STRUCT(CNV_BRI_DT, 0x44000201, 0x0003d000), + + // GPIO + _PAD_CFG_STRUCT(CNV_BRI_RSP, 0x44000201, 0x00002400), + + // GPIO + _PAD_CFG_STRUCT(CNV_RGI_DT, 0x44000201, 0x00000000), + + // RESERVED +// _PAD_CFG_STRUCT(CNV_RGI_RSP, 0xffffffff, 0xffffffff), + + // GPIO + _PAD_CFG_STRUCT(SVID0_ALERT_B, 0x44000100, 0x00000000), + + // GPIO + _PAD_CFG_STRUCT(SVID0_DATA, 0x44000100, 0x00000000), + + // GPIO + _PAD_CFG_STRUCT(SVID0_CLK, 0x44000100, 0x00000000), + + + // ************************************ + // ******* GPIO Group NorthWest ******* + // ************************************ + // *DDI0_DDC_SDA + _PAD_CFG_STRUCT(GPIO_187, 0x44000400, 0x0001f000), + + // *DDI0_DDC_SCL + _PAD_CFG_STRUCT(GPIO_188, 0x44000400, 0x0001f000), + + // *DDI1_DDC_SDA + _PAD_CFG_STRUCT(GPIO_189, 0x44000400, 0x00002c00), + + // *DDI1_DDC_SCL + _PAD_CFG_STRUCT(GPIO_190, 0x44000400, 0x00002c00), + + // GPIO + _PAD_CFG_STRUCT(GPIO_191, 0x44000100, 0x00000000), + + // GPIO + _PAD_CFG_STRUCT(GPIO_192, 0x44000100, 0x00000000), + + // *PNL0_VDDEN + _PAD_CFG_STRUCT(GPIO_193, 0x44000400, 0x00005000), + + // *PNL0_BKLTEN + _PAD_CFG_STRUCT(GPIO_194, 0x44000400, 0x00005000), + + // *PNL0_BKLTCTL + _PAD_CFG_STRUCT(GPIO_195, 0x44000400, 0x00005000), + + // GPIO + _PAD_CFG_STRUCT(GPIO_196, 0x44000100, 0x00000000), + + // GPIO + _PAD_CFG_STRUCT(GPIO_197, 0x44000100, 0x00000000), + + // GPIO + _PAD_CFG_STRUCT(GPIO_198, 0x44000100, 0x00000000), + + // DDI1_HPD + _PAD_CFG_STRUCT(GPIO_199, 0x44000800, 0x00003000), + + // DDI0_HPD + _PAD_CFG_STRUCT(GPIO_200, 0x44000802, 0x00003000), + + // GPIO + _PAD_CFG_STRUCT(GPIO_201, 0x44000100, 0x00000000), + + // GPIO + _PAD_CFG_STRUCT(GPIO_202, 0x44000100, 0x00000000), + + // GPIO + _PAD_CFG_STRUCT(GPIO_203, 0x44000102, 0x00000000), + + // GPIO + _PAD_CFG_STRUCT(GPIO_204, 0x44000102, 0x00000000), + + // GPIO + _PAD_CFG_STRUCT(PMC_SPI_FS0, 0x44000102, 0x00000000), + + // DDI2_HPD + _PAD_CFG_STRUCT(PMC_SPI_FS1, 0x44000802, 0x00003000), + + // GPIO + _PAD_CFG_STRUCT(PMC_SPI_FS2, 0x44000102, 0x00000000), + + // GPIO + _PAD_CFG_STRUCT(PMC_SPI_RXD, 0x44000100, 0x00000000), + + // GPIO + _PAD_CFG_STRUCT(PMC_SPI_TXD, 0x44000100, 0x00000000), + + // GPIO + _PAD_CFG_STRUCT(PMC_SPI_CLK, 0x44000100, 0x00000000), + + // GPIO + _PAD_CFG_STRUCT(PMIC_PWRGOOD, 0x44000203, 0x00002400), + + // GPIO + _PAD_CFG_STRUCT(PMIC_RESET_B, 0x44000102, 0x0003c000), + + // GPIO + _PAD_CFG_STRUCT(GPIO_213, 0x44000201, 0x00003000), + + // GPIO + _PAD_CFG_STRUCT(GPIO_214, 0x44000102, 0x00000000), + + // GPIO + _PAD_CFG_STRUCT(GPIO_215, 0x44000100, 0x00000000), + + // *THERMTRIP_N + _PAD_CFG_STRUCT(PMIC_THERMTRIP_B, 0x44000400, 0x00003000), + + // GPIO + _PAD_CFG_STRUCT(PMIC_STDBY, 0x44000201, 0x00001000), + + // *PROCHOT_N + _PAD_CFG_STRUCT(PROCHOT_B, 0x44000402, 0x00023000), + + // RESERVED +// _PAD_CFG_STRUCT(PMIC_I2C_SCL, 0xffffffff, 0xffffffff), + + // RESERVED +// _PAD_CFG_STRUCT(PMIC_I2C_SDA, 0xffffffff, 0xffffffff), + + // *GPIO + _PAD_CFG_STRUCT(GPIO_74, 0x44000100, 0x00000000), + + // *GPIO + _PAD_CFG_STRUCT(GPIO_75, 0x44000100, 0x00000000), + + // *GPIO + _PAD_CFG_STRUCT(GPIO_76, 0x44000100, 0x00000000), + + // *GPIO + _PAD_CFG_STRUCT(GPIO_77, 0x44000100, 0x00000000), + + // *GPIO + _PAD_CFG_STRUCT(GPIO_78, 0x44000100, 0x00000000), + + // AVS_DMIC_CLK_A1 + _PAD_CFG_STRUCT(GPIO_79, 0x44000400, 0x0003d000), + + // AVS_DMIC_CLK_B1 + _PAD_CFG_STRUCT(GPIO_80, 0x44000400, 0x0003d000), + + // AVS_DMIC_DATA_1 + _PAD_CFG_STRUCT(GPIO_81, 0x44000400, 0x00025200), + + // AVS_DMIC_CLK_AB2 + _PAD_CFG_STRUCT(GPIO_82, 0x44000400, 0x0003d000), + + // AVS_DMIC_DATA_2 + _PAD_CFG_STRUCT(GPIO_83, 0x44000400, 0x00025200), + + // AVS_I2S2_MCLK + _PAD_CFG_STRUCT(GPIO_84, 0x44000400, 0x00001000), + + // AVS_I2S2_BCLK + _PAD_CFG_STRUCT(GPIO_85, 0x44000400, 0x0001d200), + + // AVS_I2S2_WS_SYNC + _PAD_CFG_STRUCT(GPIO_86, 0x44000402, 0x0001d200), + + // AVS_I2S2_SDI + _PAD_CFG_STRUCT(GPIO_87, 0x44000402, 0x0001f200), + + // AVS_I2S2_SDO + _PAD_CFG_STRUCT(GPIO_88, 0x44000400, 0x0001c200), + + // *GPIO + _PAD_CFG_STRUCT(GPIO_89, 0x44000100, 0x00000000), + + // *GPIO + _PAD_CFG_STRUCT(GPIO_90, 0x44000100, 0x00000000), + + // *GPIO + _PAD_CFG_STRUCT(GPIO_91, 0x44000100, 0x00000000), + + // *GPIO + _PAD_CFG_STRUCT(GPIO_92, 0x44000100, 0x00000000), + + // *FST_SPI_CS0_N + _PAD_CFG_STRUCT(GPIO_97, 0x44000402, 0x0003fc00), + + // GPIO + _PAD_CFG_STRUCT(GPIO_98, 0x44000100, 0x00000000), + + // *FST_SPI_MOSI_IO0 + _PAD_CFG_STRUCT(GPIO_99, 0x44000400, 0x0003fc00), + + // *FST_SPI_MISO_IO1 + _PAD_CFG_STRUCT(GPIO_100, 0x44000402, 0x0003fc00), + + // GPIO + _PAD_CFG_STRUCT(GPIO_101, 0x44000100, 0x00000000), + + // GPIO + _PAD_CFG_STRUCT(GPIO_102, 0x44000100, 0x00000000), + + // *FST_SPI_CLK + _PAD_CFG_STRUCT(GPIO_103, 0x44000400, 0x0003fc00), + + // *n/a + _PAD_CFG_STRUCT(FST_SPI_CLK_FB, 0x44000400, 0x0003c000), + + // SIO_SPI_0_CLK + _PAD_CFG_STRUCT(GPIO_104, 0x44000400, 0x0001d200), + + // SIO_SPI_0_FS0 + _PAD_CFG_STRUCT(GPIO_105, 0x44000400, 0x0001f200), + + // SIO_SPI_0_FS1 + _PAD_CFG_STRUCT(GPIO_106, 0x44000400, 0x0001f200), + + // SIO_SPI_0_RXD + _PAD_CFG_STRUCT(GPIO_109, 0x44000402, 0x0001f200), + + // SIO_SPI_0_TXD + _PAD_CFG_STRUCT(GPIO_110, 0x44000400, 0x0001f200), + + // SIO_SPI_1_CLK + _PAD_CFG_STRUCT(GPIO_111, 0x44000400, 0x00001000), + + // SIO_SPI_1_FS0 + _PAD_CFG_STRUCT(GPIO_112, 0x44000400, 0x00001000), + + // SIO_SPI_1_FS1 + _PAD_CFG_STRUCT(GPIO_113, 0x44000400, 0x00001000), + + // SIO_SPI_1_RXD + _PAD_CFG_STRUCT(GPIO_116, 0x44000402, 0x0001d000), + + // SIO_SPI_1_TXD + _PAD_CFG_STRUCT(GPIO_117, 0x44000400, 0x00001000), + + // SIO_SPI_2_CLK + _PAD_CFG_STRUCT(GPIO_118, 0x44000400, 0x00001000), + + // SIO_SPI_2_FS0 + _PAD_CFG_STRUCT(GPIO_119, 0x44000400, 0x00001000), + + // SIO_SPI_2_FS1 + _PAD_CFG_STRUCT(GPIO_120, 0x44000400, 0x00001000), + + // SIO_SPI_2_FS2 + _PAD_CFG_STRUCT(GPIO_121, 0x44000400, 0x00001000), + + // SIO_SPI_2_RXD + _PAD_CFG_STRUCT(GPIO_122, 0x44000400, 0x00001000), + + // SIO_SPI_2_TXD + _PAD_CFG_STRUCT(GPIO_123, 0x44000400, 0x00001000), + + + // ******************************* + // ******* GPIO Group West ******* + // ******************************* + // LPSS_I2C0_SDA + _PAD_CFG_STRUCT(GPIO_124, 0x44000402, 0x00012700), + + // LPSS_I2C0_SCL + _PAD_CFG_STRUCT(GPIO_125, 0x44000402, 0x00012700), + + // LPSS_I2C1_SDA + _PAD_CFG_STRUCT(GPIO_126, 0x44000402, 0x00012700), + + // LPSS_I2C1_SCL + _PAD_CFG_STRUCT(GPIO_127, 0x44000402, 0x00012700), + + // LPSS_I2C2_SDA + _PAD_CFG_STRUCT(GPIO_128, 0x44000402, 0x00012700), + + // LPSS_I2C2_SCL + _PAD_CFG_STRUCT(GPIO_129, 0x44000402, 0x00012700), + + // LPSS_I2C3_SDA + _PAD_CFG_STRUCT(GPIO_130, 0x44000402, 0x00012700), + + // LPSS_I2C3_SCL + _PAD_CFG_STRUCT(GPIO_131, 0x44000402, 0x00012700), + + // LPSS_I2C4_SDA + _PAD_CFG_STRUCT(GPIO_132, 0x44000402, 0x00012700), + + // LPSS_I2C4_SCL + _PAD_CFG_STRUCT(GPIO_133, 0x44000402, 0x00012700), + + // LPSS_I2C5_SDA + _PAD_CFG_STRUCT(GPIO_134, 0x44000402, 0x0001f200), + + // LPSS_I2C5_SCL + _PAD_CFG_STRUCT(GPIO_135, 0x44000402, 0x0001f200), + + // LPSS_I2C6_SDA + _PAD_CFG_STRUCT(GPIO_136, 0x44000402, 0x0001f200), + + // LPSS_I2C6_SCL + _PAD_CFG_STRUCT(GPIO_137, 0x44000402, 0x0001f200), + + // LPSS_I2C7_SDA + _PAD_CFG_STRUCT(GPIO_138, 0x44000402, 0x00006700), + + // LPSS_I2C7_SCL + _PAD_CFG_STRUCT(GPIO_139, 0x44000402, 0x00006700), + + // AVS_I2S6_BCLK + _PAD_CFG_STRUCT(GPIO_146, 0x44000800, 0x0003d000), + + // AVS_I2S6_WS_SYNC + _PAD_CFG_STRUCT(GPIO_147, 0x44000800, 0x0003d000), + + // AVS_I2S6_SDI + _PAD_CFG_STRUCT(GPIO_148, 0x44000802, 0x0003d000), + + // AVS_I2S6_SDO + _PAD_CFG_STRUCT(GPIO_149, 0x44000800, 0x0003d000), + + // AVS_I2S5_BCLK + _PAD_CFG_STRUCT(GPIO_150, 0x44000800, 0x0001d200), + + // AVS_I2S5_WS_SYNC + _PAD_CFG_STRUCT(GPIO_151, 0x44000800, 0x0001d200), + + // AVS_I2S5_SDI + _PAD_CFG_STRUCT(GPIO_152, 0x44000802, 0x0001d200), + + // AVS_I2S5_SDO + _PAD_CFG_STRUCT(GPIO_153, 0x44000800, 0x0001c200), + + // *GPIO + _PAD_CFG_STRUCT(GPIO_154, 0x44000102, 0x00000000), + + // SPKR + _PAD_CFG_STRUCT(GPIO_155, 0x44000800, 0x0003d000), + + // *PCIE_CLKREQ0_N + _PAD_CFG_STRUCT(GPIO_209, 0x44000400, 0x00001000), + + // *PCIE_CLKREQ1_N + _PAD_CFG_STRUCT(GPIO_210, 0x44000400, 0x00001000), + + // *PCIE_CLKREQ2_N + _PAD_CFG_STRUCT(GPIO_211, 0x44000400, 0x00001000), + + // *PCIE_CLKREQ3_N + _PAD_CFG_STRUCT(GPIO_212, 0x44000400, 0x00001000), + + // *OSC_CLK_OUT_0 + _PAD_CFG_STRUCT(OSC_CLK_OUT_0, 0x44000400, 0x00001000), + + // *OSC_CLK_OUT_1 + _PAD_CFG_STRUCT(OSC_CLK_OUT_1, 0x44000400, 0x00001000), + + // *OSC_CLK_OUT_2 + _PAD_CFG_STRUCT(OSC_CLK_OUT_2, 0x44000400, 0x00001000), + + // *OSC_CLK_OUT_3 + _PAD_CFG_STRUCT(OSC_CLK_OUT_3, 0x44000400, 0x00001000), + + // GPIO + _PAD_CFG_STRUCT(OSC_CLK_OUT_4, 0x44000100, 0x00000000), + + // *GPIO + _PAD_CFG_STRUCT(PMU_AC_PRESENT, 0x44000102, 0x00000000), + + // GPIO + _PAD_CFG_STRUCT(PMU_BATLOW_B, 0x44000102, 0x00000000), + + // *PMU_PLTRST_N + _PAD_CFG_STRUCT(PMU_PLTRST_B, 0x44000400, 0x0003c000), + + // *PMU_PWRBTN_N + _PAD_CFG_STRUCT(PMU_PWRBTN_B, 0x44000402, 0x0003f000), + + // *PMU_RSTBTN_N + _PAD_CFG_STRUCT(PMU_RESETBUTTON_B, 0x44000402, 0x0003c000), + + // *PMU_SLP_S0_N + _PAD_CFG_STRUCT(PMU_SLP_S0_B, 0x44000400, 0x0003c000), + + // *PMU_SLP_S3_N + _PAD_CFG_STRUCT(PMU_SLP_S3_B, 0x44000400, 0x0003c000), + + // *PMU_SLP_S4_N + _PAD_CFG_STRUCT(PMU_SLP_S4_B, 0x44000400, 0x0003c000), + + // *PMU_SUSCLK + _PAD_CFG_STRUCT(PMU_SUSCLK, 0x44000400, 0x0003c000), + + // *GPIO + _PAD_CFG_STRUCT(PMU_WAKE_B, 0x44000201, 0x0003f000), + + // *SUS_STAT_B + _PAD_CFG_STRUCT(SUS_STAT_B, 0x44000400, 0x0003c000), + + // GPIO + _PAD_CFG_STRUCT(SUSPWRDNACK, 0x44000102, 0x00000000), + + + // ************************************ + // ******* GPIO Group SouthWest ******* + // ************************************ + // PCIE_WAKE0_N + _PAD_CFG_STRUCT(GPIO_205, 0x44000402, 0x00000000), + + // PCIE_WAKE1_N + _PAD_CFG_STRUCT(GPIO_206, 0x44000402, 0x00000000), + + // PCIE_WAKE2_N + _PAD_CFG_STRUCT(GPIO_207, 0x44000402, 0x00000000), + + // PCIE_WAKE3_N + _PAD_CFG_STRUCT(GPIO_208, 0x44000402, 0x00000000), + + // *EMMC_CLK + _PAD_CFG_STRUCT(GPIO_156, 0x44000402, 0x00005000), + + // *EMMC_D0 + _PAD_CFG_STRUCT(GPIO_157, 0x44000402, 0x00023000), + + // *EMMC_D1 + _PAD_CFG_STRUCT(GPIO_158, 0x44000402, 0x00023000), + + // *EMMC_D2 + _PAD_CFG_STRUCT(GPIO_159, 0x44000402, 0x00023000), + + // *EMMC_D3 + _PAD_CFG_STRUCT(GPIO_160, 0x44000402, 0x00023000), + + // *EMMC_D4 + _PAD_CFG_STRUCT(GPIO_161, 0x44000402, 0x00023000), + + // *EMMC_D5 + _PAD_CFG_STRUCT(GPIO_162, 0x44000402, 0x00023000), + + // *EMMC_D6 + _PAD_CFG_STRUCT(GPIO_163, 0x44000402, 0x00023000), + + // *EMMC_D7 + _PAD_CFG_STRUCT(GPIO_164, 0x44000402, 0x00023000), + + // *EMMC_CMD + _PAD_CFG_STRUCT(GPIO_165, 0x44000402, 0x00023000), + + // *GPIO + _PAD_CFG_STRUCT(GPIO_166, 0x44000300, 0x00001000), + + // *GPIO + _PAD_CFG_STRUCT(GPIO_167, 0x44000102, 0x00023000), + + // *GPIO + _PAD_CFG_STRUCT(GPIO_168, 0x44000100, 0x00023000), + + // *GPIO + _PAD_CFG_STRUCT(GPIO_169, 0x44000200, 0x00003000), + + // *GPIO + _PAD_CFG_STRUCT(GPIO_170, 0x44000201, 0x00003000), + + // *GPIO + _PAD_CFG_STRUCT(GPIO_171, 0x44000201, 0x00003000), + + // SDCARD_CLK + _PAD_CFG_STRUCT(GPIO_172, 0x44000400, 0x00021100), + + // n/a + _PAD_CFG_STRUCT(GPIO_179, 0x44000400, 0x00001000), + + // SDCARD_D0 + _PAD_CFG_STRUCT(GPIO_173, 0x44000402, 0x00023100), + + // SDCARD_D1 + _PAD_CFG_STRUCT(GPIO_174, 0x44000402, 0x00023000), + + // SDCARD_D2 + _PAD_CFG_STRUCT(GPIO_175, 0x44000402, 0x00023000), + + // SDCARD_D3 + _PAD_CFG_STRUCT(GPIO_176, 0x44000402, 0x00023000), + + // SDCARD_CD_B + _PAD_CFG_STRUCT(GPIO_177, 0x44000402, 0x00003000), + + // SDCARD_CMD + _PAD_CFG_STRUCT(GPIO_178, 0x44000402, 0x00023100), + + // SDCARD_LVL_WP + _PAD_CFG_STRUCT(GPIO_186, 0x44000402, 0x00003000), + + // *EMMC_RCLK + _PAD_CFG_STRUCT(GPIO_182, 0x44000400, 0x0001d000), + + // GPIO + _PAD_CFG_STRUCT(GPIO_183, 0x44000200, 0x00001000), + + // SMB_ALERT_N + _PAD_CFG_STRUCT(SMB_ALERTB, 0x44000402, 0x0003f000), + + // SMB_CLK + _PAD_CFG_STRUCT(SMB_CLK, 0x44000402, 0x0003f000), + + // SMB_DATA + _PAD_CFG_STRUCT(SMB_DATA, 0x44000402, 0x0003f000), + + // LPC_ILB_SERIRQ + _PAD_CFG_STRUCT(LPC_ILB_SERIRQ, 0x44000402, 0x0003f000), + + // LPC_CLKOUT0 + _PAD_CFG_STRUCT(LPC_CLKOUT0, 0x44000400, 0x00020100), + + // LPC_CLKOUT1 + _PAD_CFG_STRUCT(LPC_CLKOUT1, 0x44000400, 0x00020100), + + // LPC_AD0 + _PAD_CFG_STRUCT(LPC_AD0, 0x44000402, 0x00023100), + + // LPC_AD1 + _PAD_CFG_STRUCT(LPC_AD1, 0x44000402, 0x00023100), + + // LPC_AD2 + _PAD_CFG_STRUCT(LPC_AD2, 0x44000402, 0x00023100), + + // LPC_AD3 + _PAD_CFG_STRUCT(LPC_AD3, 0x44000402, 0x00023100), + + // LPC_CLKRUNB + _PAD_CFG_STRUCT(LPC_CLKRUNB, 0x44000400, 0x00023100), + + // LPC_FRAMEB + _PAD_CFG_STRUCT(LPC_FRAMEB, 0x44000400, 0x00023100), +}; + +#endif diff --git a/src/mainboard/up/squared/ramstage.c b/src/mainboard/up/squared/ramstage.c new file mode 100644 index 0000000000..e9fcfb2da3 --- /dev/null +++ b/src/mainboard/up/squared/ramstage.c @@ -0,0 +1,432 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Felix Singer + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include + +void mainboard_silicon_init_params(FSP_S_CONFIG *silconfig) +{ + printk(BIOS_DEBUG, "MAINBOARD: %s/%s called\n", __FILE__, __func__); + + silconfig->C1e = 0x1; // 0x0 + silconfig->PkgCStateLimit = 0xFE; // 0x2 + silconfig->CStateAutoDemotion = 0x3; // 0x0 + silconfig->CStateUnDemotion = 0x3; // 0x0 + silconfig->PkgCStateDemotion = 0x1; // 0x0 + silconfig->PkgCStateUnDemotion = 0x1; // 0x0 + silconfig->IpuEn = 0x0; // 0x1 + silconfig->Pme = 0x1; // 0x0 + silconfig->HdAudioIoBufferOwnership = 0x3; // 0x0 + silconfig->DspEndpointDmic = 0x0; // 0x1 + silconfig->DspEndpointBluetooth = 0x0; // 0x1 + silconfig->DspEndpointI2sSkp = 0x1; // 0x0 + silconfig->DspEndpointI2sHp = 0x1; // 0x0 + silconfig->HDAudioPwrGate = 0x1; // 0x0 + silconfig->HDAudioClkGate = 0x1; // 0x0 + silconfig->DspFeatureMask = 0x2A; // 0x0 + silconfig->HpetBdfValid = 0x1; // 0x0 + silconfig->HpetDeviceNumber = 0xF; // 0x1f + silconfig->IoApicBdfValid = 0x1; // 0x0 + silconfig->IoApicDeviceNumber = 0x1F; // 0xf + silconfig->IshEnable = 0x0; // 0x1 + silconfig->SpiEiss = 0x0; // 0x1 + silconfig->LPSS_S0ixEnable = 0x1; // 0x0 + silconfig->SdcardEnabled = 0x0; // 0x1 + silconfig->eMMCHostMaxSpeed = 0x2; // 0x0 + silconfig->Usb30Mode = 0x1; // 0x0 + silconfig->VtdEnable = 0x1; // 0x0 + silconfig->MonitorMwaitEnable = 0x0; // 0x1 + silconfig->HdAudioDspUaaCompliance = 0x1; // 0x0 + silconfig->InitS3Cpu = 0x1; // 0x0 + + silconfig->PortUsb20PerPortTxPeHalf[0] = 0x0; + silconfig->PortUsb20PerPortPeTxiSet[0] = 0x7; + silconfig->PortUsb20PerPortTxiSet[0] = 0x0; + silconfig->PortUsb20HsSkewSel[0] = 0x0; + silconfig->PortUsb20IUsbTxEmphasisEn[0] = 0x3; + silconfig->PortUsb20PerPortRXISet[0] = 0x0; + silconfig->PortUsb20HsNpreDrvSel[0] = 0x0; + + silconfig->PortUsb20PerPortTxPeHalf[1] = 0x0; + silconfig->PortUsb20PerPortPeTxiSet[1] = 0x6; + silconfig->PortUsb20PerPortTxiSet[1] = 0x0; + silconfig->PortUsb20HsSkewSel[1] = 0x0; + silconfig->PortUsb20IUsbTxEmphasisEn[1] = 0x3; + silconfig->PortUsb20PerPortRXISet[1] = 0x0; + silconfig->PortUsb20HsNpreDrvSel[1] = 0x0; + + silconfig->PortUsb20PerPortTxPeHalf[2] = 0x0; + silconfig->PortUsb20PerPortPeTxiSet[2] = 0x6; + silconfig->PortUsb20PerPortTxiSet[2] = 0x0; + silconfig->PortUsb20HsSkewSel[2] = 0x0; + silconfig->PortUsb20IUsbTxEmphasisEn[2] = 0x3; + silconfig->PortUsb20PerPortRXISet[2] = 0x0; + silconfig->PortUsb20HsNpreDrvSel[2] = 0x0; + + silconfig->PortUsb20PerPortTxPeHalf[3] = 0x0; + silconfig->PortUsb20PerPortPeTxiSet[3] = 0x6; + silconfig->PortUsb20PerPortTxiSet[3] = 0x0; + silconfig->PortUsb20HsSkewSel[3] = 0x0; + silconfig->PortUsb20IUsbTxEmphasisEn[3] = 0x3; + silconfig->PortUsb20PerPortRXISet[3] = 0x0; + silconfig->PortUsb20HsNpreDrvSel[3] = 0x0; + + silconfig->PortUsb20PerPortTxPeHalf[4] = 0x0; + silconfig->PortUsb20PerPortPeTxiSet[4] = 0x7; + silconfig->PortUsb20PerPortTxiSet[4] = 0x0; + silconfig->PortUsb20HsSkewSel[4] = 0x0; + silconfig->PortUsb20IUsbTxEmphasisEn[4] = 0x3; + silconfig->PortUsb20PerPortRXISet[4] = 0x0; + silconfig->PortUsb20HsNpreDrvSel[4] = 0x0; + + silconfig->PortUsb20PerPortTxPeHalf[5] = 0x0; + silconfig->PortUsb20PerPortPeTxiSet[5] = 0x7; + silconfig->PortUsb20PerPortTxiSet[5] = 0x0; + silconfig->PortUsb20HsSkewSel[5] = 0x0; + silconfig->PortUsb20IUsbTxEmphasisEn[5] = 0x3; + silconfig->PortUsb20PerPortRXISet[5] = 0x0; + silconfig->PortUsb20HsNpreDrvSel[5] = 0x0; + + silconfig->PortUsb20PerPortTxPeHalf[6] = 0x0; + silconfig->PortUsb20PerPortPeTxiSet[6] = 0x7; + silconfig->PortUsb20PerPortTxiSet[6] = 0x0; + silconfig->PortUsb20HsSkewSel[6] = 0x0; + silconfig->PortUsb20IUsbTxEmphasisEn[6] = 0x3; + silconfig->PortUsb20PerPortRXISet[6] = 0x0; + silconfig->PortUsb20HsNpreDrvSel[6] = 0x0; + + silconfig->PortUsb20PerPortTxPeHalf[7] = 0x0; + silconfig->PortUsb20PerPortPeTxiSet[7] = 0x1; + silconfig->PortUsb20PerPortTxiSet[7] = 0x3; + silconfig->PortUsb20HsSkewSel[7] = 0x1; + silconfig->PortUsb20IUsbTxEmphasisEn[7] = 0x1; + silconfig->PortUsb20PerPortRXISet[7] = 0x0; + silconfig->PortUsb20HsNpreDrvSel[7] = 0x3; + + + silconfig->WriteProtectionEnable[0] = 0x1; + silconfig->ReadProtectionEnable[0] = 0x1; + silconfig->ProtectedRangeLimit[0] = 0xFFF; + silconfig->ProtectedRangeBase[0] = 0x0; + + silconfig->IPC[0] = 0xFFFFEEF8; + silconfig->IPC[1] = 0xFFFFFFFF; + silconfig->IPC[2] = 0xFFFFFFFF; + silconfig->IPC[3] = 0xFFFFFFFF; + + silconfig->SataPortsDisableDynamicPg[0] = 0x0; + silconfig->SataPortsEnable[0] = 0x1; + silconfig->SataPortsDevSlp[0] = 0x0; + silconfig->SataPortsHotPlug[0] = 0x0; + silconfig->SataPortsInterlockSw[0] = 0x1; + silconfig->SataPortsExternal[0] = 0x0; + silconfig->SataPortsSpinUp[0] = 0x0; + silconfig->SataPortsSolidStateDrive[0] = 0x0; + silconfig->SataPortsEnableDitoConfig[0] = 0x0; + silconfig->SataPortsDmVal[0] = 0xF; + silconfig->SataPortsDitoVal[0] = 0x271; + + silconfig->SataPortsDisableDynamicPg[1] = 0x0; + silconfig->SataPortsEnable[1] = 0x1; + silconfig->SataPortsDevSlp[1] = 0x0; + silconfig->SataPortsHotPlug[1] = 0x0; + silconfig->SataPortsInterlockSw[1] = 0x1; + silconfig->SataPortsExternal[1] = 0x0; + silconfig->SataPortsSpinUp[1] = 0x0; + silconfig->SataPortsSolidStateDrive[1] = 0x0; + silconfig->SataPortsEnableDitoConfig[1] = 0x0; + silconfig->SataPortsDmVal[1] = 0xF; + silconfig->SataPortsDitoVal[1] = 0x271; + + + silconfig->PcieRootPortEn[0] = 0x1; + silconfig->PcieRpHide[0] = 0x0; + silconfig->PcieRpSlotImplemented[0] = 0x1; + silconfig->PcieRpHotPlug[0] = 0x0; + silconfig->PcieRpPmSci[0] = 0x1; + silconfig->PcieRpExtSync[0] = 0x1; + silconfig->PcieRpTransmitterHalfSwing[0] = 0x0; + silconfig->PcieRpAcsEnabled[0] = 0x1; + silconfig->PcieRpClkReqSupported[0] = 0x1; + silconfig->PcieRpClkReqNumber[0] = 0x2; + silconfig->PcieRpClkReqDetect[0] = 0x0; + silconfig->AdvancedErrorReporting[0] = 0x0; + silconfig->PmeInterrupt[0] = 0x0; + silconfig->UnsupportedRequestReport[0] = 0x0; + silconfig->FatalErrorReport[0] = 0x0; + silconfig->NoFatalErrorReport[0] = 0x0; + silconfig->CorrectableErrorReport[0] = 0x0; + silconfig->SystemErrorOnFatalError[0] = 0x0; + silconfig->SystemErrorOnNonFatalError[0] = 0x0; + silconfig->SystemErrorOnCorrectableError[0] = 0x0; + silconfig->PcieRpSpeed[0] = 0x0; + silconfig->PhysicalSlotNumber[0] = 0x0; + silconfig->PcieRpCompletionTimeout[0] = 0x0; + silconfig->PtmEnable[0] = 0x0; + silconfig->PcieRpAspm[0] = 0x4; + silconfig->PcieRpL1Substates[0] = 0x3; + silconfig->PcieRpLtrEnable[0] = 0x1; + silconfig->PcieRpLtrConfigLock[0] = 0x0; + silconfig->PcieRpSelectableDeemphasis[0] = 0x1; + silconfig->PcieRpNonSnoopLatencyOverrideValue[0] = 0x3C; + silconfig->PcieRpNonSnoopLatencyOverrideMultiplier[0] = 0x2; + silconfig->PcieRpSlotPowerLimitScale[0] = 0x0; + silconfig->PcieRpSlotPowerLimitValue[0] = 0x0; + silconfig->PcieRpLtrMaxNonSnoopLatency[0] = 0x1003; + silconfig->PcieRpNonSnoopLatencyOverrideMode[0] = 0x2; + silconfig->PcieRpLtrMaxSnoopLatency[0] = 0x1003; + silconfig->PcieRpSnoopLatencyOverrideMode[0] = 0x2; + silconfig->PcieRpSnoopLatencyOverrideValue[0] = 0x3C; + silconfig->PcieRpSnoopLatencyOverrideMultiplier[0] = 0x2; + + silconfig->PcieRootPortEn[1] = 0x1; + silconfig->PcieRpHide[1] = 0x0; + silconfig->PcieRpSlotImplemented[1] = 0x1; + silconfig->PcieRpHotPlug[1] = 0x0; + silconfig->PcieRpPmSci[1] = 0x1; + silconfig->PcieRpExtSync[1] = 0x1; + silconfig->PcieRpTransmitterHalfSwing[1] = 0x0; + silconfig->PcieRpAcsEnabled[1] = 0x1; + silconfig->PcieRpClkReqSupported[1] = 0x1; + silconfig->PcieRpClkReqNumber[1] = 0x3; + silconfig->PcieRpClkReqDetect[1] = 0x0; + silconfig->AdvancedErrorReporting[1] = 0x0; + silconfig->PmeInterrupt[1] = 0x0; + silconfig->UnsupportedRequestReport[1] = 0x0; + silconfig->FatalErrorReport[1] = 0x0; + silconfig->NoFatalErrorReport[1] = 0x0; + silconfig->CorrectableErrorReport[1] = 0x0; + silconfig->SystemErrorOnFatalError[1] = 0x0; + silconfig->SystemErrorOnNonFatalError[1] = 0x0; + silconfig->SystemErrorOnCorrectableError[1] = 0x0; + silconfig->PcieRpSpeed[1] = 0x0; + silconfig->PhysicalSlotNumber[1] = 0x1; + silconfig->PcieRpCompletionTimeout[1] = 0x0; + silconfig->PtmEnable[1] = 0x0; + silconfig->PcieRpAspm[1] = 0x4; + silconfig->PcieRpL1Substates[1] = 0x3; + silconfig->PcieRpLtrEnable[1] = 0x1; + silconfig->PcieRpLtrConfigLock[1] = 0x0; + silconfig->PcieRpSelectableDeemphasis[1] = 0x1; + silconfig->PcieRpNonSnoopLatencyOverrideValue[1] = 0x3C; + silconfig->PcieRpNonSnoopLatencyOverrideMultiplier[1] = 0x2; + silconfig->PcieRpSlotPowerLimitScale[1] = 0x0; + silconfig->PcieRpSlotPowerLimitValue[1] = 0x0; + silconfig->PcieRpLtrMaxNonSnoopLatency[1] = 0x1003; + silconfig->PcieRpNonSnoopLatencyOverrideMode[1] = 0x2; + silconfig->PcieRpLtrMaxSnoopLatency[1] = 0x1003; + silconfig->PcieRpSnoopLatencyOverrideMode[1] = 0x2; + silconfig->PcieRpSnoopLatencyOverrideValue[1] = 0x3C; + silconfig->PcieRpSnoopLatencyOverrideMultiplier[1] = 0x2; + + silconfig->PcieRootPortEn[2] = 0x1; + silconfig->PcieRpHide[2] = 0x0; + silconfig->PcieRpSlotImplemented[2] = 0x1; + silconfig->PcieRpHotPlug[2] = 0x0; + silconfig->PcieRpPmSci[2] = 0x1; + silconfig->PcieRpExtSync[2] = 0x1; + silconfig->PcieRpTransmitterHalfSwing[2] = 0x0; + silconfig->PcieRpAcsEnabled[2] = 0x1; + silconfig->PcieRpClkReqSupported[2] = 0x1; + silconfig->PcieRpClkReqNumber[2] = 0x0; + silconfig->PcieRpClkReqDetect[2] = 0x0; + silconfig->AdvancedErrorReporting[2] = 0x0; + silconfig->PmeInterrupt[2] = 0x0; + silconfig->UnsupportedRequestReport[2] = 0x0; + silconfig->FatalErrorReport[2] = 0x0; + silconfig->NoFatalErrorReport[2] = 0x0; + silconfig->CorrectableErrorReport[2] = 0x0; + silconfig->SystemErrorOnFatalError[2] = 0x0; + silconfig->SystemErrorOnNonFatalError[2] = 0x0; + silconfig->SystemErrorOnCorrectableError[2] = 0x0; + silconfig->PcieRpSpeed[2] = 0x0; + silconfig->PhysicalSlotNumber[2] = 0x2; + silconfig->PcieRpCompletionTimeout[2] = 0x0; + silconfig->PtmEnable[2] = 0x0; + silconfig->PcieRpAspm[2] = 0x4; + silconfig->PcieRpL1Substates[2] = 0x3; + silconfig->PcieRpLtrEnable[2] = 0x1; + silconfig->PcieRpLtrConfigLock[2] = 0x0; + silconfig->PcieRpSelectableDeemphasis[2] = 0x1; + silconfig->PcieRpNonSnoopLatencyOverrideValue[2] = 0x3C; + silconfig->PcieRpNonSnoopLatencyOverrideMultiplier[2] = 0x2; + silconfig->PcieRpSlotPowerLimitScale[2] = 0x0; + silconfig->PcieRpSlotPowerLimitValue[2] = 0x0; + silconfig->PcieRpLtrMaxNonSnoopLatency[2] = 0x1003; + silconfig->PcieRpNonSnoopLatencyOverrideMode[2] = 0x2; + silconfig->PcieRpLtrMaxSnoopLatency[2] = 0x1003; + silconfig->PcieRpSnoopLatencyOverrideMode[2] = 0x2; + silconfig->PcieRpSnoopLatencyOverrideValue[2] = 0x0; + silconfig->PcieRpSnoopLatencyOverrideMultiplier[2] = 0x2; + + silconfig->PcieRootPortEn[3] = 0x1; + silconfig->PcieRpHide[3] = 0x0; + silconfig->PcieRpSlotImplemented[3] = 0x1; + silconfig->PcieRpHotPlug[3] = 0x0; + silconfig->PcieRpPmSci[3] = 0x1; + silconfig->PcieRpExtSync[3] = 0x1; + silconfig->PcieRpTransmitterHalfSwing[3] = 0x0; + silconfig->PcieRpAcsEnabled[3] = 0x1; + silconfig->PcieRpClkReqSupported[3] = 0x1; + silconfig->PcieRpClkReqNumber[3] = 0x1; + silconfig->PcieRpClkReqDetect[3] = 0x0; + silconfig->AdvancedErrorReporting[3] = 0x0; + silconfig->PmeInterrupt[3] = 0x0; + silconfig->UnsupportedRequestReport[3] = 0x0; + silconfig->FatalErrorReport[3] = 0x0; + silconfig->NoFatalErrorReport[3] = 0x0; + silconfig->CorrectableErrorReport[3] = 0x0; + silconfig->SystemErrorOnFatalError[3] = 0x0; + silconfig->SystemErrorOnNonFatalError[3] = 0x0; + silconfig->SystemErrorOnCorrectableError[3] = 0x0; + silconfig->PcieRpSpeed[3] = 0x0; + silconfig->PhysicalSlotNumber[3] = 0x3; + silconfig->PcieRpCompletionTimeout[3] = 0x0; + silconfig->PtmEnable[3] = 0x0; + silconfig->PcieRpAspm[3] = 0x4; + silconfig->PcieRpL1Substates[3] = 0x3; + silconfig->PcieRpLtrEnable[3] = 0x1; + silconfig->PcieRpLtrConfigLock[3] = 0x0; + silconfig->PcieRpSelectableDeemphasis[3] = 0x1; + silconfig->PcieRpNonSnoopLatencyOverrideValue[3] = 0x3C; + silconfig->PcieRpNonSnoopLatencyOverrideMultiplier[3] = 0x2; + silconfig->PcieRpSlotPowerLimitScale[3] = 0x0; + silconfig->PcieRpSlotPowerLimitValue[3] = 0x0; + silconfig->PcieRpLtrMaxNonSnoopLatency[3] = 0x1003; + silconfig->PcieRpNonSnoopLatencyOverrideMode[3] = 0x2; + silconfig->PcieRpLtrMaxSnoopLatency[3] = 0x1003; + silconfig->PcieRpSnoopLatencyOverrideMode[3] = 0x2; + silconfig->PcieRpSnoopLatencyOverrideValue[3] = 0x3C; + silconfig->PcieRpSnoopLatencyOverrideMultiplier[3] = 0x2; + + silconfig->PcieRootPortEn[4] = 0x1; + silconfig->PcieRpHide[4] = 0x0; + silconfig->PcieRpSlotImplemented[4] = 0x1; + silconfig->PcieRpHotPlug[4] = 0x0; + silconfig->PcieRpPmSci[4] = 0x1; + silconfig->PcieRpExtSync[4] = 0x1; + silconfig->PcieRpTransmitterHalfSwing[4] = 0x0; + silconfig->PcieRpAcsEnabled[4] = 0x1; + silconfig->PcieRpClkReqSupported[4] = 0x1; + silconfig->PcieRpClkReqNumber[4] = 0x2; + silconfig->PcieRpClkReqDetect[4] = 0x0; + silconfig->AdvancedErrorReporting[4] = 0x0; + silconfig->PmeInterrupt[4] = 0x0; + silconfig->UnsupportedRequestReport[4] = 0x0; + silconfig->FatalErrorReport[4] = 0x0; + silconfig->NoFatalErrorReport[4] = 0x0; + silconfig->CorrectableErrorReport[4] = 0x0; + silconfig->SystemErrorOnFatalError[4] = 0x0; + silconfig->SystemErrorOnNonFatalError[4] = 0x0; + silconfig->SystemErrorOnCorrectableError[4] = 0x0; + silconfig->PcieRpSpeed[4] = 0x0; + silconfig->PhysicalSlotNumber[4] = 0x4; + silconfig->PcieRpCompletionTimeout[4] = 0x0; + silconfig->PtmEnable[4] = 0x0; + silconfig->PcieRpAspm[4] = 0x4; + silconfig->PcieRpL1Substates[4] = 0x3; + silconfig->PcieRpLtrEnable[4] = 0x1; + silconfig->PcieRpLtrConfigLock[4] = 0x0; + silconfig->PcieRpSelectableDeemphasis[4] = 0x1; + silconfig->PcieRpNonSnoopLatencyOverrideValue[4] = 0x3C; + silconfig->PcieRpNonSnoopLatencyOverrideMultiplier[4] = 0x2; + silconfig->PcieRpSlotPowerLimitScale[4] = 0x0; + silconfig->PcieRpSlotPowerLimitValue[4] = 0x0; + silconfig->PcieRpLtrMaxNonSnoopLatency[4] = 0x1003; + silconfig->PcieRpNonSnoopLatencyOverrideMode[4] = 0x2; + silconfig->PcieRpLtrMaxSnoopLatency[4] = 0x1003; + silconfig->PcieRpSnoopLatencyOverrideMode[4] = 0x2; + silconfig->PcieRpSnoopLatencyOverrideValue[4] = 0x3C; + silconfig->PcieRpSnoopLatencyOverrideMultiplier[4] = 0x2; + + silconfig->PcieRootPortEn[5] = 0x1; + silconfig->PcieRpHide[5] = 0x0; + silconfig->PcieRpSlotImplemented[5] = 0x1; + silconfig->PcieRpHotPlug[5] = 0x0; + silconfig->PcieRpPmSci[5] = 0x1; + silconfig->PcieRpExtSync[5] = 0x1; + silconfig->PcieRpTransmitterHalfSwing[5] = 0x0; + silconfig->PcieRpAcsEnabled[5] = 0x1; + silconfig->PcieRpClkReqSupported[5] = 0x1; + silconfig->PcieRpClkReqNumber[5] = 0x3; + silconfig->PcieRpClkReqDetect[5] = 0x0; + silconfig->AdvancedErrorReporting[5] = 0x0; + silconfig->PmeInterrupt[5] = 0x0; + silconfig->UnsupportedRequestReport[5] = 0x0; + silconfig->FatalErrorReport[5] = 0x0; + silconfig->NoFatalErrorReport[5] = 0x0; + silconfig->CorrectableErrorReport[5] = 0x0; + silconfig->SystemErrorOnFatalError[5] = 0x0; + silconfig->SystemErrorOnNonFatalError[5] = 0x0; + silconfig->SystemErrorOnCorrectableError[5] = 0x0; + silconfig->PcieRpSpeed[5] = 0x0; + silconfig->PhysicalSlotNumber[5] = 0x5; + silconfig->PcieRpCompletionTimeout[5] = 0x0; + silconfig->PtmEnable[5] = 0x0; + silconfig->PcieRpAspm[5] = 0x4; + silconfig->PcieRpL1Substates[5] = 0x3; + silconfig->PcieRpLtrEnable[5] = 0x1; + silconfig->PcieRpLtrConfigLock[5] = 0x0; + silconfig->PcieRpSelectableDeemphasis[5] = 0x1; + silconfig->PcieRpNonSnoopLatencyOverrideValue[5] = 0x3C; + silconfig->PcieRpNonSnoopLatencyOverrideMultiplier[5] = 0x2; + silconfig->PcieRpSlotPowerLimitScale[5] = 0x0; + silconfig->PcieRpSlotPowerLimitValue[5] = 0x0; + silconfig->PcieRpLtrMaxNonSnoopLatency[5] = 0x1003; + silconfig->PcieRpNonSnoopLatencyOverrideMode[5] = 0x2; + silconfig->PcieRpLtrMaxSnoopLatency[5] = 0x1003; + silconfig->PcieRpSnoopLatencyOverrideMode[5] = 0x2; + silconfig->PcieRpSnoopLatencyOverrideValue[5] = 0x3C; + silconfig->PcieRpSnoopLatencyOverrideMultiplier[5] = 0x2; + + + silconfig->SsicRate[0] = 0x1; + silconfig->SsicPortEnable[0] = 0x0; + silconfig->SsicRate[1] = 0x1; + silconfig->SsicPortEnable[1] = 0x0; + + silconfig->PortUsb30Enable[0] = 0x1; + silconfig->PortUs30bOverCurrentPin[0] = 0x0; + silconfig->PortUsb30Enable[1] = 0x1; + silconfig->PortUs30bOverCurrentPin[1] = 0x1; + silconfig->PortUsb30Enable[2] = 0x1; + silconfig->PortUs30bOverCurrentPin[2] = 0x1; + silconfig->PortUsb30Enable[3] = 0x1; + silconfig->PortUs30bOverCurrentPin[3] = 0x1; + silconfig->PortUsb30Enable[4] = 0x1; + silconfig->PortUs30bOverCurrentPin[4] = 0x1; + silconfig->PortUsb30Enable[5] = 0x1; + silconfig->PortUs30bOverCurrentPin[5] = 0x1; + + silconfig->PortUsb20Enable[0] = 0x1; + silconfig->PortUs20bOverCurrentPin[0] = 0x0; + silconfig->PortUsb20Enable[1] = 0x1; + silconfig->PortUs20bOverCurrentPin[1] = 0x1; + silconfig->PortUsb20Enable[2] = 0x1; + silconfig->PortUs20bOverCurrentPin[2] = 0x1; + silconfig->PortUsb20Enable[3] = 0x1; + silconfig->PortUs20bOverCurrentPin[3] = 0x1; + silconfig->PortUsb20Enable[4] = 0x1; + silconfig->PortUs20bOverCurrentPin[4] = 0x1; + silconfig->PortUsb20Enable[5] = 0x1; + silconfig->PortUs20bOverCurrentPin[5] = 0x1; + silconfig->PortUsb20Enable[6] = 0x1; + silconfig->PortUs20bOverCurrentPin[6] = 0x2; + silconfig->PortUsb20Enable[7] = 0x1; + silconfig->PortUs20bOverCurrentPin[7] = 0x2; +} diff --git a/src/mainboard/up/squared/romstage.c b/src/mainboard/up/squared/romstage.c new file mode 100644 index 0000000000..2cfaa0064a --- /dev/null +++ b/src/mainboard/up/squared/romstage.c @@ -0,0 +1,96 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Felix Singer + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include "gpio.h" + +static const uint8_t ch0_bit_swizzling[] = { + 0x0D, 0x0A, 0x08, 0x0B, 0x0C, 0x0F, 0x0E, 0x09, + 0x06, 0x00, 0x03, 0x04, 0x07, 0x01, 0x05, 0x02, + 0x1C, 0x1A, 0x19, 0x1B, 0x1D, 0x1F, 0x1E, 0x18, + 0x10, 0x17, 0x15, 0x16, 0x14, 0x12, 0x13, 0x11 +}; + +static const uint8_t ch1_bit_swizzling[] = { + 0x00, 0x07, 0x04, 0x05, 0x06, 0x02, 0x03, 0x01, + 0x08, 0x0F, 0x0D, 0x0B, 0x0A, 0x09, 0x0E, 0x0C, + 0x17, 0x11, 0x13, 0x12, 0x14, 0x15, 0x16, 0x10, + 0x1C, 0x1A, 0x1D, 0x1F, 0x18, 0x19, 0x1E, 0x1B +}; + +static const uint8_t ch2_bit_swizzling[] = { + 0x0D, 0x08, 0x0B, 0x0E, 0x0C, 0x0F, 0x09, 0x0A, + 0x04, 0x07, 0x01, 0x06, 0x02, 0x03, 0x00, 0x05, + 0x18, 0x19, 0x1C, 0x1A, 0x1D, 0x1E, 0x1F, 0x1B, + 0x11, 0x13, 0x15, 0x10, 0x16, 0x12, 0x17, 0x14 +}; + +static const uint8_t ch3_bit_swizzling[] = { + 0x00, 0x05, 0x04, 0x07, 0x03, 0x02, 0x06, 0x01, + 0x0A, 0x0B, 0x08, 0x09, 0x0C, 0x0E, 0x0D, 0x0F, + 0x12, 0x16, 0x14, 0x13, 0x17, 0x11, 0x15, 0x10, + 0x19, 0x1F, 0x1D, 0x1B, 0x1E, 0x18, 0x1C, 0x1A +}; + + +void mainboard_memory_init_params(FSPM_UPD *memupd) +{ + printk(BIOS_DEBUG, "MAINBOARD: %s/%s called\n", __FILE__, __func__); + + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); + + memupd->FspmConfig.Package = 0x1; // 0x0 + memupd->FspmConfig.Profile = 0xB; // 0x19 + memupd->FspmConfig.MemoryDown = 0x1; // 0x0 + memupd->FspmConfig.DDR3LPageSize = 0x0; // 0x1 + memupd->FspmConfig.DIMM0SPDAddress = 0x0; // 0xa0 + memupd->FspmConfig.DIMM1SPDAddress = 0x0; // 0xa4 + memupd->FspmConfig.RmtCheckRun = 0x3; // 0x0 + memupd->FspmConfig.RmtMarginCheckScaleHighThreshold = 0xC8; // 0x0 + memupd->FspmConfig.EnhancePort8xhDecoding = 0x0; // 0x1 + memupd->FspmConfig.NpkEn = 0x0; // 0x3 + memupd->FspmConfig.PrimaryVideoAdaptor = 0x2; // 0x0 + + memupd->FspmConfig.Ch0_RankEnable = 0x1; // 0x0 + memupd->FspmConfig.Ch0_DeviceWidth = 0x1; // 0x0 + memupd->FspmConfig.Ch0_DramDensity = 0x2; // 0x0 + memupd->FspmConfig.Ch0_Option = 0x3; // 0x0 + memupd->FspmConfig.Ch1_RankEnable = 0x1; // 0x0 + memupd->FspmConfig.Ch1_DeviceWidth = 0x1; // 0x0 + memupd->FspmConfig.Ch1_DramDensity = 0x2; // 0x0 + memupd->FspmConfig.Ch1_Option = 0x3; // 0x0 + memupd->FspmConfig.Ch2_RankEnable = 0x1; // 0x0 + memupd->FspmConfig.Ch2_DeviceWidth = 0x1; // 0x0 + memupd->FspmConfig.Ch2_DramDensity = 0x2; // 0x0 + memupd->FspmConfig.Ch2_Option = 0x3; // 0x0 + memupd->FspmConfig.Ch3_RankEnable = 0x1; // 0x0 + memupd->FspmConfig.Ch3_DeviceWidth = 0x1; // 0x0 + memupd->FspmConfig.Ch3_DramDensity = 0x2; // 0x0 + memupd->FspmConfig.Ch3_Option = 0x3; // 0x0 + memupd->FspmConfig.StartTimerTickerOfPfetAssert = 0x4E20; // 0x0 + + memcpy(memupd->FspmConfig.Ch0_Bit_swizzling, &ch0_bit_swizzling, + sizeof(ch0_bit_swizzling)); + memcpy(memupd->FspmConfig.Ch1_Bit_swizzling, &ch1_bit_swizzling, + sizeof(ch1_bit_swizzling)); + memcpy(memupd->FspmConfig.Ch2_Bit_swizzling, &ch2_bit_swizzling, + sizeof(ch2_bit_swizzling)); + memcpy(memupd->FspmConfig.Ch3_Bit_swizzling, &ch3_bit_swizzling, + sizeof(ch3_bit_swizzling)); +} diff --git a/src/mainboard/up/squared/upsquared.fmd b/src/mainboard/up/squared/upsquared.fmd new file mode 100644 index 0000000000..4ea1375e10 --- /dev/null +++ b/src/mainboard/up/squared/upsquared.fmd @@ -0,0 +1,21 @@ +FLASH 16M { + SI_DESC@0x0 0x1000 + SI_BIOS@0x1000 0xefe000 { + IFWI@0x0 0x2ff000 + OBB@0x2ff000 0xbff000 { + FMAP@0x0 0x800 + UNIFIED_MRC_CACHE@0x800 0x21000 { + RECOVERY_MRC_CACHE@0x0 0x10000 + RW_MRC_CACHE@0x10000 0x10000 + RW_VAR_MRC_CACHE@0x20000 0x1000 + } + CONSOLE@0x21800 0x20000 + COREBOOT(CBFS)@0x41800 0xb7d800 + BIOS_UNUSABLE@0xbbf000 0x40000 + } + } + SI_DEVICEEXT@0xeff000 0x101000 { + DEVICE_EXTENSION@0x0 0x100000 + UNUSED_HOLE@0x100000 0x1000 + } +} diff --git a/src/mainboard/up/squared/vboot-ro.fmd b/src/mainboard/up/squared/vboot-ro.fmd new file mode 100644 index 0000000000..72f92fe964 --- /dev/null +++ b/src/mainboard/up/squared/vboot-ro.fmd @@ -0,0 +1,35 @@ +FLASH 16M { + SI_DESC@0x0 0x1000 + SI_BIOS@0x1000 0xefe000 { + WP_RO@0x0 0xe91000 { + IFWI@0x0 0x2ff000 + FMAP@0x2ff000 0x800 + RO_VPD(PRESERVE)@0x2ff800 0x4000 + RO_SECTION@0x303800 0xb8d800 { + RO_FRID@0x0 0x40 + RO_FRID_PAD@0x40 0x7c0 + GBB@0x800 0x40000 + COREBOOT(CBFS)@0x40800 0xb4d000 + } + } + MISC_RW@0xe91000 0x2d000 { + UNIFIED_MRC_CACHE@0x0 0x21000 { + RECOVERY_MRC_CACHE@0x0 0x10000 + RW_MRC_CACHE@0x10000 0x10000 + RW_VAR_MRC_CACHE@0x20000 0x1000 + } + RW_SHARED@0x21000 0x4000 { + SHARED_DATA@0x0 0x2000 + VBLOCK_DEV@0x2000 0x2000 + } + RW_VPD(PRESERVE)@0x25000 0x2000 + RW_NVRAM(PRESERVE)@0x27000 0x5000 + FPF_STATUS@0x2c000 0x1000 + } + BIOS_UNUSABLE@0xebe000 0x40000 + } + SI_DEVICEEXT@0xeff000 0x101000 { + DEVICE_EXTENSION@0x0 0x100000 + UNUSED_HOLE@0x100000 0x1000 + } +} diff --git a/src/mainboard/up/squared/vboot-roa.fmd b/src/mainboard/up/squared/vboot-roa.fmd new file mode 100644 index 0000000000..330ce03757 --- /dev/null +++ b/src/mainboard/up/squared/vboot-roa.fmd @@ -0,0 +1,40 @@ +FLASH 16M { + SI_DESC@0x0 0x1000 + SI_BIOS@0x1000 0xefe000 { + WP_RO@0x0 0x502000 { + IFWI@0x0 0x2ff000 + FMAP@0x2ff000 0x800 + RO_VPD(PRESERVE)@0x2ff800 0x4000 + RO_SECTION@0x303800 0x1fe800 { + RO_FRID@0x0 0x40 + RO_FRID_PAD@0x40 0x7c0 + GBB@0x800 0x40000 + COREBOOT(CBFS)@0x40800 0x1be000 + } + } + MISC_RW@0x502000 0x2d000 { + UNIFIED_MRC_CACHE@0x0 0x21000 { + RECOVERY_MRC_CACHE@0x0 0x10000 + RW_MRC_CACHE@0x10000 0x10000 + RW_VAR_MRC_CACHE@0x20000 0x1000 + } + RW_SHARED@0x21000 0x4000 { + SHARED_DATA@0x0 0x2000 + VBLOCK_DEV@0x2000 0x2000 + } + RW_VPD(PRESERVE)@0x25000 0x2000 + RW_NVRAM(PRESERVE)@0x27000 0x5000 + FPF_STATUS@0x2c000 0x1000 + } + RW_SECTION_A@0x52f000 0x98f000 { + VBLOCK_A@0x0 0x10000 + FW_MAIN_A(CBFS)@0x10000 0x97efc0 + RW_FWID_A@0x98efc0 0x40 + } + BIOS_UNUSABLE@0xebe000 0x40000 + } + SI_DEVICEEXT@0xeff000 0x101000 { + DEVICE_EXTENSION@0x0 0x100000 + UNUSED_HOLE@0x100000 0x1000 + } +} diff --git a/src/mainboard/up/squared/vboot-roab.fmd b/src/mainboard/up/squared/vboot-roab.fmd new file mode 100644 index 0000000000..4ddcbc0c2e --- /dev/null +++ b/src/mainboard/up/squared/vboot-roab.fmd @@ -0,0 +1,45 @@ +FLASH 16M { + SI_DESC@0x0 0x1000 + SI_BIOS@0x1000 0xefe000 { + WP_RO@0x0 0x503000 { + IFWI@0x0 0x2ff000 + FMAP@0x2ff000 0x800 + RO_VPD(PRESERVE)@0x2ff800 0x4000 + RO_SECTION@0x303800 0x1ff800 { + RO_FRID@0x0 0x40 + RO_FRID_PAD@0x40 0x7c0 + GBB@0x800 0x40000 + COREBOOT(CBFS)@0x40800 0x1bf000 + } + } + MISC_RW@0x503000 0x2d000 { + UNIFIED_MRC_CACHE@0x0 0x21000 { + RECOVERY_MRC_CACHE@0x0 0x10000 + RW_MRC_CACHE@0x10000 0x10000 + RW_VAR_MRC_CACHE@0x20000 0x1000 + } + RW_SHARED@0x21000 0x4000 { + SHARED_DATA@0x0 0x2000 + VBLOCK_DEV@0x2000 0x2000 + } + RW_VPD(PRESERVE)@0x25000 0x2000 + RW_NVRAM(PRESERVE)@0x27000 0x5000 + FPF_STATUS@0x2c000 0x1000 + } + RW_SECTION_A@0x530000 0x4c7000 { + VBLOCK_A@0x0 0x10000 + FW_MAIN_A(CBFS)@0x10000 0x4b6fc0 + RW_FWID_A@0x4c6fc0 0x40 + } + RW_SECTION_B@0x9f7000 0x4c7000 { + VBLOCK_B@0x0 0x10000 + FW_MAIN_B(CBFS)@0x10000 0x4b6fc0 + RW_FWID_B@0x4c6fc0 0x40 + } + BIOS_UNUSABLE@0xebe000 0x40000 + } + SI_DEVICEEXT@0xeff000 0x101000 { + DEVICE_EXTENSION@0x0 0x100000 + UNUSED_HOLE@0x100000 0x1000 + } +} From ba44a27f7fcc50677e2b0789f61fce2df8f6d620 Mon Sep 17 00:00:00 2001 From: Jett Rink Date: Tue, 21 May 2019 13:48:04 -0600 Subject: [PATCH 137/331] post: during post_code, only call elog when enabled Now that we call post_code in other stages other than RAMSTAGE, we need to guard the elog calls with the appropriate condition in order to compile correctly. Change-Id: I766c276f28d46492fb05e0e3be71853e21f4e8e0 Signed-off-by: Jett Rink Reviewed-on: https://review.coreboot.org/c/coreboot/+/32914 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie --- src/console/post.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/console/post.c b/src/console/post.c index b17a819d97..0719e5e7df 100644 --- a/src/console/post.c +++ b/src/console/post.c @@ -81,7 +81,7 @@ void cmos_post_log(void) default: printk(BIOS_WARNING, "POST: Unexpected post code " "in previous boot: 0x%02x\n", code); -#if CONFIG(ELOG) +#if CONFIG(ELOG) && (ENV_RAMSTAGE || CONFIG(ELOG_PRERAM)) elog_add_event_word(ELOG_TYPE_LAST_POST_CODE, code); #if CONFIG(CMOS_POST_EXTRA) if (extra) From 7006458777483291abfca790beb48f201ba74c37 Mon Sep 17 00:00:00 2001 From: Keith Short Date: Mon, 6 May 2019 16:12:57 -0600 Subject: [PATCH 138/331] post_code: add post code for failure to load next stage Add a new post code, POST_INVALID_ROM, used when coreboot fails to locate or validate a resource that is stored in ROM. BUG=b:124401932 BRANCH=sarien TEST=build coreboot for sarien and arcada platforms Change-Id: Ie6de6590595d8fcdc57ad156237fffa03d5ead38 Signed-off-by: Keith Short Reviewed-on: https://review.coreboot.org/c/coreboot/+/32770 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin Reviewed-by: Duncan Laurie --- Documentation/POSTCODES | 1 + src/arch/x86/postcar_loader.c | 9 ++++++--- src/include/console/post_codes.h | 7 +++++++ src/lib/prog_loaders.c | 10 ++++++---- src/security/vboot/vboot_logic.c | 6 ++++-- 5 files changed, 24 insertions(+), 9 deletions(-) diff --git a/Documentation/POSTCODES b/Documentation/POSTCODES index 5d337b629d..2340fac049 100644 --- a/Documentation/POSTCODES +++ b/Documentation/POSTCODES @@ -16,6 +16,7 @@ This is an (incomplete) list of POST codes emitted by coreboot v4. 0x66 Devices have been enumerated 0x88 Devices have been configured 0x89 Devices have been enabled +0xe0 Boot media (e.g. SPI ROM) is corrupt 0xf8 Entry into elf boot 0xf3 Jumping to payload diff --git a/src/arch/x86/postcar_loader.c b/src/arch/x86/postcar_loader.c index d62487ef88..e5d0ceab4d 100644 --- a/src/arch/x86/postcar_loader.c +++ b/src/arch/x86/postcar_loader.c @@ -141,13 +141,16 @@ static void load_postcar_cbfs(struct prog *prog, struct postcar_frame *pcf) }; if (prog_locate(prog)) - die("Failed to locate after CAR program.\n"); + die_with_post_code(POST_INVALID_ROM, + "Failed to locate after CAR program.\n"); if (rmodule_stage_load(&rsl)) - die("Failed to load after CAR program.\n"); + die_with_post_code(POST_INVALID_ROM, + "Failed to load after CAR program.\n"); /* Set the stack pointer within parameters of the program loaded. */ if (rsl.params == NULL) - die("No parameters found in after CAR program.\n"); + die_with_post_code(POST_INVALID_ROM, + "No parameters found in after CAR program.\n"); finalize_load(rsl.params, pcf->stack); diff --git a/src/include/console/post_codes.h b/src/include/console/post_codes.h index f482ae9e47..775f78d603 100644 --- a/src/include/console/post_codes.h +++ b/src/include/console/post_codes.h @@ -318,6 +318,13 @@ */ #define POST_JUMPING_TO_PAYLOAD 0xf3 +/** + * \brief Invalid or corrupt ROM + * + * Set if firmware failed to find or validate a resource that is stored in ROM. + */ +#define POST_INVALID_ROM 0xe0 + /** * \brief TPM failure * diff --git a/src/lib/prog_loaders.c b/src/lib/prog_loaders.c index 3b77712550..a21663fc0f 100644 --- a/src/lib/prog_loaders.c +++ b/src/lib/prog_loaders.c @@ -69,7 +69,8 @@ void run_romstage(void) fail: if (CONFIG(BOOTBLOCK_CONSOLE)) - die("Couldn't load romstage.\n"); + die_with_post_code(POST_INVALID_ROM, + "Couldn't load romstage.\n"); halt(); } @@ -162,7 +163,7 @@ void run_ramstage(void) prog_run(&ramstage); fail: - die("Ramstage was not loaded!\n"); + die_with_post_code(POST_INVALID_ROM, "Ramstage was not loaded!\n"); } #ifdef __RAMSTAGE__ // gc-sections should take care of this @@ -195,13 +196,14 @@ void payload_load(void) break; } /* else fall-through */ default: - die("Unsupported payload type.\n"); + die_with_post_code(POST_INVALID_ROM, + "Unsupported payload type.\n"); break; } out: if (prog_entry(payload) == NULL) - die("Payload not loaded.\n"); + die_with_post_code(POST_INVALID_ROM, "Payload not loaded.\n"); } void payload_run(void) diff --git a/src/security/vboot/vboot_logic.c b/src/security/vboot/vboot_logic.c index d4ad32736b..626310010c 100644 --- a/src/security/vboot/vboot_logic.c +++ b/src/security/vboot/vboot_logic.c @@ -320,7 +320,8 @@ void verstage_main(void) if (CONFIG(VBOOT_MEASURED_BOOT) && !(ctx.flags & VB2_CONTEXT_S3_RESUME)) { if (vboot_init_crtm() != VB2_SUCCESS) - die("Initializing measured boot mode failed!"); + die_with_post_code(POST_INVALID_ROM, + "Initializing measured boot mode failed!"); } if (get_recovery_mode_switch()) { @@ -395,7 +396,8 @@ void verstage_main(void) printk(BIOS_INFO, "Phase 4\n"); rv = locate_firmware(&ctx, &fw_main); if (rv) - die("Failed to read FMAP to locate firmware"); + die_with_post_code(POST_INVALID_ROM, + "Failed to read FMAP to locate firmware"); rv = hash_body(&ctx, &fw_main); save_if_needed(&ctx); From 1835bf0fd4b77ab3eae1fb085be1667d13ed3144 Mon Sep 17 00:00:00 2001 From: Keith Short Date: Thu, 16 May 2019 11:46:27 -0600 Subject: [PATCH 139/331] post_code: add post code for critical CBFS failures Add a new post code POST_INVALID_CBFS, used when coreboot fails to locate or validate a resource that is stored in CBFS. BUG=b:124401932 BRANCH=sarien TEST=build coreboot for sarien and arcada platforms Change-Id: If1c8b92889040f9acd6250f847db02626809a987 Signed-off-by: Keith Short Reviewed-on: https://review.coreboot.org/c/coreboot/+/32771 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph --- Documentation/POSTCODES | 1 + src/include/console/post_codes.h | 7 +++++++ src/soc/intel/quark/romstage/fsp2_0.c | 3 ++- 3 files changed, 10 insertions(+), 1 deletion(-) diff --git a/Documentation/POSTCODES b/Documentation/POSTCODES index 2340fac049..162e863fed 100644 --- a/Documentation/POSTCODES +++ b/Documentation/POSTCODES @@ -17,6 +17,7 @@ This is an (incomplete) list of POST codes emitted by coreboot v4. 0x88 Devices have been configured 0x89 Devices have been enabled 0xe0 Boot media (e.g. SPI ROM) is corrupt +0xe1 Resource stored within CBFS is corrupt 0xf8 Entry into elf boot 0xf3 Jumping to payload diff --git a/src/include/console/post_codes.h b/src/include/console/post_codes.h index 775f78d603..7bd1ee0798 100644 --- a/src/include/console/post_codes.h +++ b/src/include/console/post_codes.h @@ -325,6 +325,13 @@ */ #define POST_INVALID_ROM 0xe0 +/** + * \brief Invalid or corrupt CBFS + * + * Set if firmware failed to find or validate a resource that is stored in CBFS. + */ +#define POST_INVALID_CBFS 0xe1 + /** * \brief TPM failure * diff --git a/src/soc/intel/quark/romstage/fsp2_0.c b/src/soc/intel/quark/romstage/fsp2_0.c index 2ec16c9f34..e4abcc034a 100644 --- a/src/soc/intel/quark/romstage/fsp2_0.c +++ b/src/soc/intel/quark/romstage/fsp2_0.c @@ -116,7 +116,8 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *fspm_upd, uint32_t version) /* Locate the RMU data file in flash */ rmu_data = locate_rmu_file(&rmu_data_len); if (!rmu_data) - die("Microcode file (rmu.bin) not found."); + die_with_post_code(POST_INVALID_CBFS, + "Microcode file (rmu.bin) not found."); /* Locate the configuration data from devicetree.cb */ dev = pcidev_path_on_root(LPC_DEV_FUNC); From bb41aba0d8c3c3cbfee44b0f7267e78fb7d012ee Mon Sep 17 00:00:00 2001 From: Keith Short Date: Thu, 16 May 2019 14:07:43 -0600 Subject: [PATCH 140/331] post_code: add post code for invalid vendor binary Add a new post code POST_INVALID_VENDOR_BINARY, used when coreboot fails to locate or validate a vendor supplied binary. BUG=b:124401932 BRANCH=sarien TEST=build coreboot for sarien and arcada platforms Change-Id: Ib1e359d4e8772c37922b1b779135e58c73bff6b4 Signed-off-by: Keith Short Reviewed-on: https://review.coreboot.org/c/coreboot/+/32772 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie --- Documentation/POSTCODES | 1 + src/drivers/intel/fsp1_1/raminit.c | 14 ++++++++------ src/drivers/intel/fsp2_0/memory_init.c | 6 ++++-- src/drivers/intel/fsp2_0/silicon_init.c | 3 ++- src/include/console/post_codes.h | 8 ++++++++ src/northbridge/intel/haswell/raminit.c | 3 ++- src/northbridge/intel/sandybridge/raminit_mrc.c | 3 ++- src/soc/intel/fsp_baytrail/romstage/romstage.c | 3 ++- src/soc/intel/fsp_broadwell_de/romstage/romstage.c | 3 ++- 9 files changed, 31 insertions(+), 13 deletions(-) diff --git a/Documentation/POSTCODES b/Documentation/POSTCODES index 162e863fed..855940f433 100644 --- a/Documentation/POSTCODES +++ b/Documentation/POSTCODES @@ -18,6 +18,7 @@ This is an (incomplete) list of POST codes emitted by coreboot v4. 0x89 Devices have been enabled 0xe0 Boot media (e.g. SPI ROM) is corrupt 0xe1 Resource stored within CBFS is corrupt +0xe2 Vendor binary (e.g. FSP) generated a fatal error 0xf8 Entry into elf boot 0xf3 Jumping to payload diff --git a/src/drivers/intel/fsp1_1/raminit.c b/src/drivers/intel/fsp1_1/raminit.c index 726cc26a0c..fc6f848089 100644 --- a/src/drivers/intel/fsp1_1/raminit.c +++ b/src/drivers/intel/fsp1_1/raminit.c @@ -195,9 +195,6 @@ void raminit(struct romstage_params *params) } #if CONFIG(DISPLAY_HOBS) - if (hob_list_ptr == NULL) - die("ERROR - HOB pointer is NULL!\n"); - /* * Verify that FSP is generating the required HOBs: * 7.1: FSP_BOOTLOADER_TEMP_MEMORY_HOB only produced for FSP 1.0 @@ -244,7 +241,10 @@ void raminit(struct romstage_params *params) "ERROR - Missing one or more required FSP HOBs!\n"); /* Display the HOBs */ - print_hob_type_structure(0, hob_list_ptr); + if (hob_list_ptr != NULL) + print_hob_type_structure(0, hob_list_ptr); + else + printk(BIOS_ERR, "ERROR - HOB pointer is NULL!\n"); #endif /* Get the address of the CBMEM region for the FSP reserved memory */ @@ -274,14 +274,16 @@ void raminit(struct romstage_params *params) printk(BIOS_DEBUG, "0x%08x: Chipset reserved bytes reported by FSP\n", (unsigned int)delta_bytes); - die("Please verify the chipset reserved size\n"); + die_with_post_code(POST_INVALID_VENDOR_BINARY, + "Please verify the chipset reserved size\n"); } #endif } /* Verify the FSP 1.1 HOB interface */ if (fsp_verification_failure) - die("ERROR - coreboot's requirements not met by FSP binary!\n"); + die_with_post_code(POST_INVALID_VENDOR_BINARY, + "ERROR - coreboot's requirements not met by FSP binary!\n"); /* Display the memory configuration */ report_memory_config(); diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c index b3afb98c4d..449b57d03e 100644 --- a/src/drivers/intel/fsp2_0/memory_init.c +++ b/src/drivers/intel/fsp2_0/memory_init.c @@ -277,7 +277,8 @@ static void do_fsp_memory_init(struct fsp_header *hdr, bool s3wake, upd = (FSPM_UPD *)(hdr->cfg_region_offset + hdr->image_base); if (upd->FspUpdHeader.Signature != FSPM_UPD_SIGNATURE) - die("Invalid FSPM signature!\n"); + die_with_post_code(POST_INVALID_VENDOR_BINARY, + "Invalid FSPM signature!\n"); /* Copy the default values from the UPD area */ memcpy(&fspm_upd, upd, sizeof(fspm_upd)); @@ -290,7 +291,8 @@ static void do_fsp_memory_init(struct fsp_header *hdr, bool s3wake, /* Fill common settings on behalf of chipset. */ if (fsp_fill_common_arch_params(arch_upd, s3wake, fsp_version, memmap) != CB_SUCCESS) - die("FSPM_ARCH_UPD not found!\n"); + die_with_post_code(POST_INVALID_VENDOR_BINARY, + "FSPM_ARCH_UPD not found!\n"); /* Give SoC and mainboard a chance to update the UPD */ platform_fsp_memory_init_params_cb(&fspm_upd, fsp_version); diff --git a/src/drivers/intel/fsp2_0/silicon_init.c b/src/drivers/intel/fsp2_0/silicon_init.c index 402b05d55e..b0a697d8cb 100644 --- a/src/drivers/intel/fsp2_0/silicon_init.c +++ b/src/drivers/intel/fsp2_0/silicon_init.c @@ -33,7 +33,8 @@ static void do_silicon_init(struct fsp_header *hdr) supd = (FSPS_UPD *) (hdr->cfg_region_offset + hdr->image_base); if (supd->FspUpdHeader.Signature != FSPS_UPD_SIGNATURE) - die("Invalid FSPS signature\n"); + die_with_post_code(POST_INVALID_VENDOR_BINARY, + "Invalid FSPS signature\n"); upd = xmalloc(sizeof(FSPS_UPD)); diff --git a/src/include/console/post_codes.h b/src/include/console/post_codes.h index 7bd1ee0798..478c811b4d 100644 --- a/src/include/console/post_codes.h +++ b/src/include/console/post_codes.h @@ -332,6 +332,14 @@ */ #define POST_INVALID_CBFS 0xe1 +/** + * \brief Vendor binary error + * + * Set if firmware failed to find or validate a vendor binary, or the binary + * generated a fatal error. + */ +#define POST_INVALID_VENDOR_BINARY 0xe2 + /** * \brief TPM failure * diff --git a/src/northbridge/intel/haswell/raminit.c b/src/northbridge/intel/haswell/raminit.c index 050dbd1ae6..c24bb67db7 100644 --- a/src/northbridge/intel/haswell/raminit.c +++ b/src/northbridge/intel/haswell/raminit.c @@ -166,7 +166,8 @@ void sdram_initialize(struct pei_data *pei_data) default: printk(BIOS_ERR, "MRC returned %x.\n", rv); } - die("Nonzero MRC return value.\n"); + die_with_post_code(POST_INVALID_VENDOR_BINARY, + "Nonzero MRC return value.\n"); } } else { die("UEFI PEI System Agent not found.\n"); diff --git a/src/northbridge/intel/sandybridge/raminit_mrc.c b/src/northbridge/intel/sandybridge/raminit_mrc.c index f032b8aefc..e88d356593 100644 --- a/src/northbridge/intel/sandybridge/raminit_mrc.c +++ b/src/northbridge/intel/sandybridge/raminit_mrc.c @@ -235,7 +235,8 @@ void sdram_initialize(struct pei_data *pei_data) default: printk(BIOS_ERR, "MRC returned %x.\n", rv); } - die("Nonzero MRC return value.\n"); + die_with_post_code(POST_INVALID_VENDOR_BINARY, + "Nonzero MRC return value.\n"); } } else { die("UEFI PEI System Agent not found.\n"); diff --git a/src/soc/intel/fsp_baytrail/romstage/romstage.c b/src/soc/intel/fsp_baytrail/romstage/romstage.c index c46b09ef97..030b5dfeed 100644 --- a/src/soc/intel/fsp_baytrail/romstage/romstage.c +++ b/src/soc/intel/fsp_baytrail/romstage/romstage.c @@ -208,7 +208,8 @@ void main(FSP_INFO_HEADER *fsp_info_header) post_code(0x48); printk(BIOS_DEBUG, "Starting the Intel FSP (early_init)\n"); fsp_early_init(fsp_info_header); - die("Uh Oh! fsp_early_init should not return here.\n"); + die_with_post_code(POST_INVALID_VENDOR_BINARY, + "Uh Oh! fsp_early_init should not return here.\n"); } /******************************************************************************* diff --git a/src/soc/intel/fsp_broadwell_de/romstage/romstage.c b/src/soc/intel/fsp_broadwell_de/romstage/romstage.c index a75dabd225..121cb25d61 100644 --- a/src/soc/intel/fsp_broadwell_de/romstage/romstage.c +++ b/src/soc/intel/fsp_broadwell_de/romstage/romstage.c @@ -84,7 +84,8 @@ void *asmlinkage main(FSP_INFO_HEADER *fsp_info_header) post_code(0x48); printk(BIOS_DEBUG, "Starting the Intel FSP (early_init)\n"); fsp_early_init(fsp_info_header); - die("Uh Oh! fsp_early_init should not return here.\n"); + die_with_post_code(POST_INVALID_VENDOR_BINARY, + "Uh Oh! fsp_early_init should not return here.\n"); } /******************************************************************************* From 24302633a558e545efcc84178136bd1879f6d8ee Mon Sep 17 00:00:00 2001 From: Keith Short Date: Thu, 16 May 2019 14:08:31 -0600 Subject: [PATCH 141/331] post_code: add post code for memory error Add a new post code POST_RAM_FAILURE, used when the Intel FSP code fails to initialize RAM. BUG=b:124401932 BRANCH=sarien TEST=build coreboot for sarien and arcada platforms Change-Id: Ibafefa0fc0b1c525f923929cc91731fbcc1e7533 Signed-off-by: Keith Short Reviewed-on: https://review.coreboot.org/c/coreboot/+/32773 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph --- Documentation/POSTCODES | 1 + src/drivers/intel/fsp1_1/raminit.c | 3 ++- src/drivers/intel/fsp2_0/memory_init.c | 3 ++- src/include/console/post_codes.h | 8 ++++++++ 4 files changed, 13 insertions(+), 2 deletions(-) diff --git a/Documentation/POSTCODES b/Documentation/POSTCODES index 855940f433..2a8285b27f 100644 --- a/Documentation/POSTCODES +++ b/Documentation/POSTCODES @@ -19,6 +19,7 @@ This is an (incomplete) list of POST codes emitted by coreboot v4. 0xe0 Boot media (e.g. SPI ROM) is corrupt 0xe1 Resource stored within CBFS is corrupt 0xe2 Vendor binary (e.g. FSP) generated a fatal error +0xe3 RAM could not be initialized 0xf8 Entry into elf boot 0xf3 Jumping to payload diff --git a/src/drivers/intel/fsp1_1/raminit.c b/src/drivers/intel/fsp1_1/raminit.c index fc6f848089..eff011aa62 100644 --- a/src/drivers/intel/fsp1_1/raminit.c +++ b/src/drivers/intel/fsp1_1/raminit.c @@ -130,7 +130,8 @@ void raminit(struct romstage_params *params) printk(BIOS_DEBUG, "FspMemoryInit returned 0x%08x\n", status); if (status != EFI_SUCCESS) - die("ERROR - FspMemoryInit failed to initialize memory!\n"); + die_with_post_code(POST_RAM_FAILURE, + "ERROR - FspMemoryInit failed to initialize memory!\n"); /* Locate the FSP reserved memory area */ fsp_reserved_bytes = 0; diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c index 449b57d03e..60e3310a4d 100644 --- a/src/drivers/intel/fsp2_0/memory_init.c +++ b/src/drivers/intel/fsp2_0/memory_init.c @@ -316,7 +316,8 @@ static void do_fsp_memory_init(struct fsp_header *hdr, bool s3wake, fsp_handle_reset(status); if (status != FSP_SUCCESS) { printk(BIOS_CRIT, "FspMemoryInit returned 0x%08x\n", status); - die("FspMemoryInit returned an error!\n"); + die_with_post_code(POST_RAM_FAILURE, + "FspMemoryInit returned an error!\n"); } do_fsp_post_memory_init(s3wake, fsp_version); diff --git a/src/include/console/post_codes.h b/src/include/console/post_codes.h index 478c811b4d..07927ec957 100644 --- a/src/include/console/post_codes.h +++ b/src/include/console/post_codes.h @@ -340,6 +340,14 @@ */ #define POST_INVALID_VENDOR_BINARY 0xe2 +/** + * \brief RAM failure + * + * Set if RAM could not be initialized. This includes RAM is missing, + * unsupported RAM configuration, or RAM failure. + */ +#define POST_RAM_FAILURE 0xe3 + /** * \brief TPM failure * From 15588b03b36aa875e2a2a31cc649a2d9dff7581e Mon Sep 17 00:00:00 2001 From: Keith Short Date: Thu, 9 May 2019 11:40:34 -0600 Subject: [PATCH 142/331] post_code: add post code for hardware initialization failure Add a new post code POST_HW_INIT_FAILURE, used when coreboot fails to detect or initialize a required hardware component. BUG=b:124401932 BRANCH=sarien TEST=build coreboot for sarien and arcada platforms Change-Id: I73820d24b3e1c269d9d446a78ef4f97e167e3552 Signed-off-by: Keith Short Reviewed-on: https://review.coreboot.org/c/coreboot/+/32774 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph --- Documentation/POSTCODES | 1 + src/console/Makefile.inc | 1 + src/include/console/post_codes.h | 7 +++++++ src/soc/intel/apollolake/memmap.c | 3 ++- src/soc/intel/cannonlake/bootblock/pch.c | 3 ++- src/soc/intel/cannonlake/memmap.c | 3 ++- src/soc/intel/common/block/graphics/graphics.c | 6 ++++-- src/soc/intel/common/block/p2sb/p2sb.c | 12 ++++++++---- src/soc/intel/common/block/pmc/pmc.c | 3 ++- src/soc/intel/fsp_baytrail/southcluster.c | 2 +- src/soc/intel/icelake/memmap.c | 3 ++- src/soc/intel/quark/i2c.c | 3 ++- 12 files changed, 34 insertions(+), 13 deletions(-) diff --git a/Documentation/POSTCODES b/Documentation/POSTCODES index 2a8285b27f..a9d392a9b0 100644 --- a/Documentation/POSTCODES +++ b/Documentation/POSTCODES @@ -20,6 +20,7 @@ This is an (incomplete) list of POST codes emitted by coreboot v4. 0xe1 Resource stored within CBFS is corrupt 0xe2 Vendor binary (e.g. FSP) generated a fatal error 0xe3 RAM could not be initialized +0xe4 Critical hardware component could not initialize 0xf8 Entry into elf boot 0xf3 Jumping to payload diff --git a/src/console/Makefile.inc b/src/console/Makefile.inc index d5795d7929..4f0c2ef613 100644 --- a/src/console/Makefile.inc +++ b/src/console/Makefile.inc @@ -9,6 +9,7 @@ endif smm-$(CONFIG_DEBUG_SMI) += init.c console.c vtxprintf.c printk.c smm-$(CONFIG_SMM_TSEG) += die.c +smm-$(CONFIG_SMM_TSEG) += post.c verstage-y += init.c verstage-y += printk.c diff --git a/src/include/console/post_codes.h b/src/include/console/post_codes.h index 07927ec957..ae277d82e2 100644 --- a/src/include/console/post_codes.h +++ b/src/include/console/post_codes.h @@ -348,6 +348,13 @@ */ #define POST_RAM_FAILURE 0xe3 +/** + * \brief Hardware initialization failure + * + * Set when a required hardware component was not found or is unsupported. + */ +#define POST_HW_INIT_FAILURE 0xe4 + /** * \brief TPM failure * diff --git a/src/soc/intel/apollolake/memmap.c b/src/soc/intel/apollolake/memmap.c index 4f91b8aea5..6058e34895 100644 --- a/src/soc/intel/apollolake/memmap.c +++ b/src/soc/intel/apollolake/memmap.c @@ -40,7 +40,8 @@ void *cbmem_top(void) config = dev->chip_info; if (!config) - die("Failed to get chip_info\n"); + die_with_post_code(POST_HW_INIT_FAILURE, + "Failed to get chip_info\n"); /* FSP allocates 2x PRMRR Size Memory for alignment */ if (config->sgx_enable) diff --git a/src/soc/intel/cannonlake/bootblock/pch.c b/src/soc/intel/cannonlake/bootblock/pch.c index 1c7fd7f082..c43d6d8bd1 100644 --- a/src/soc/intel/cannonlake/bootblock/pch.c +++ b/src/soc/intel/cannonlake/bootblock/pch.c @@ -120,7 +120,8 @@ static void soc_config_acpibase(void) pmc_base_reg = get_pmc_reg_base(); if (!pmc_base_reg) - die("Invalid PMC base address\n"); + die_with_post_code(POST_HW_INIT_FAILURE, + "Invalid PMC base address\n"); pmc_reg_value = pcr_read32(PID_PSF3, pmc_base_reg + PCR_PSFX_TO_SHDW_BAR4); diff --git a/src/soc/intel/cannonlake/memmap.c b/src/soc/intel/cannonlake/memmap.c index 3512e2c4b4..3cae54fadb 100644 --- a/src/soc/intel/cannonlake/memmap.c +++ b/src/soc/intel/cannonlake/memmap.c @@ -221,7 +221,8 @@ static uintptr_t calculate_dram_base(size_t *reserved_mem_size) dev = dev_find_slot(0, PCI_DEVFN(SA_DEV_SLOT_IGD, 0)); if (!dev) - die("ERROR - IGD device not found!"); + die_with_post_code(POST_HW_INIT_FAILURE, + "ERROR - IGD device not found!"); /* Read TOLUD from Host Bridge offset */ dram_base = sa_get_tolud_base(); diff --git a/src/soc/intel/common/block/graphics/graphics.c b/src/soc/intel/common/block/graphics/graphics.c index 5d3b4a15cf..4cea21b075 100644 --- a/src/soc/intel/common/block/graphics/graphics.c +++ b/src/soc/intel/common/block/graphics/graphics.c @@ -58,7 +58,8 @@ uintptr_t graphics_get_memory_base(void) */ uintptr_t memory_base = graphics_get_bar(PCI_BASE_ADDRESS_2); if (!memory_base) - die("GMADR is not programmed!"); + die_with_post_code(POST_HW_INIT_FAILURE, + "GMADR is not programmed!"); return memory_base; } @@ -74,7 +75,8 @@ static uintptr_t graphics_get_gtt_base(void) if (!gtt_base) { gtt_base = graphics_get_bar(PCI_BASE_ADDRESS_0); if (!gtt_base) - die("GTTMMADR is not programmed!"); + die_with_post_code(POST_HW_INIT_FAILURE, + "GTTMMADR is not programmed!"); } return gtt_base; } diff --git a/src/soc/intel/common/block/p2sb/p2sb.c b/src/soc/intel/common/block/p2sb/p2sb.c index 1d7c091a69..24cde1b6c9 100644 --- a/src/soc/intel/common/block/p2sb/p2sb.c +++ b/src/soc/intel/common/block/p2sb/p2sb.c @@ -36,7 +36,8 @@ static pci_devfn_t p2sb_get_device(void) pci_devfn_t dev = PCI_DEV(0, PCI_SLOT(devfn), PCI_FUNC(devfn)); if (dev == PCI_DEV_INVALID) - die("PCH_DEV_P2SB not found!\n"); + die_with_post_code(POST_HW_INIT_FAILURE, + "PCH_DEV_P2SB not found!\n"); return dev; } @@ -45,7 +46,8 @@ static struct device *p2sb_get_device(void) { struct device *dev = PCH_DEV_P2SB; if (!dev) - die("PCH_DEV_P2SB not found!\n"); + die_with_post_code(POST_HW_INIT_FAILURE, + "PCH_DEV_P2SB not found!\n"); return dev; } @@ -99,7 +101,8 @@ void p2sb_unhide(void) if (pci_read_config16(P2SB_GET_DEV, PCI_VENDOR_ID) != PCI_VENDOR_ID_INTEL) - die("Unable to unhide PCH_DEV_P2SB device !\n"); + die_with_post_code(POST_HW_INIT_FAILURE, + "Unable to unhide PCH_DEV_P2SB device !\n"); } void p2sb_hide(void) @@ -108,7 +111,8 @@ void p2sb_hide(void) if (pci_read_config16(P2SB_GET_DEV, PCI_VENDOR_ID) != 0xFFFF) - die("Unable to hide PCH_DEV_P2SB device !\n"); + die_with_post_code(POST_HW_INIT_FAILURE, + "Unable to hide PCH_DEV_P2SB device !\n"); } static void p2sb_configure_endpoints(int epmask_id, uint32_t mask) diff --git a/src/soc/intel/common/block/pmc/pmc.c b/src/soc/intel/common/block/pmc/pmc.c index 43543a1cc5..eaaf1252ea 100644 --- a/src/soc/intel/common/block/pmc/pmc.c +++ b/src/soc/intel/common/block/pmc/pmc.c @@ -91,7 +91,8 @@ static void pch_pmc_read_resources(struct device *dev) struct pmc_resource_config *config = &pmc_cfg; if (pmc_soc_get_resources(config) < 0) - die("Unable to get PMC controller resource information!"); + die_with_post_code(POST_HW_INIT_FAILURE, + "Unable to get PMC controller resource information!"); /* Get the normal PCI resources of this device. */ pci_dev_read_resources(dev); diff --git a/src/soc/intel/fsp_baytrail/southcluster.c b/src/soc/intel/fsp_baytrail/southcluster.c index c84f4083d4..356b855f3b 100644 --- a/src/soc/intel/fsp_baytrail/southcluster.c +++ b/src/soc/intel/fsp_baytrail/southcluster.c @@ -98,7 +98,7 @@ static void sc_enable_ioapic(struct device *dev) reg32 = *ioapic_data; printk(BIOS_DEBUG, "Southbridge APIC ID = %x\n", (reg32 >> 24) & 0x0f); if (reg32 != (1 << 25)) - die("APIC Error\n"); + die_with_post_code(POST_HW_INIT_FAILURE, "APIC Error\n"); printk(BIOS_SPEW, "Dumping IOAPIC registers\n"); for (i=0; i<3; i++) { diff --git a/src/soc/intel/icelake/memmap.c b/src/soc/intel/icelake/memmap.c index 7d6e4e6592..f4467084ea 100644 --- a/src/soc/intel/icelake/memmap.c +++ b/src/soc/intel/icelake/memmap.c @@ -220,7 +220,8 @@ static uintptr_t calculate_dram_base(size_t *reserved_mem_size) dev = dev_find_slot(0, PCI_DEVFN(SA_DEV_SLOT_IGD, 0)); if (!dev) - die("ERROR - IGD device not found!"); + die_with_post_code(POST_HW_INIT_FAILURE, + "ERROR - IGD device not found!"); /* Read TOLUD from Host Bridge offset */ dram_base = sa_get_tolud_base(); diff --git a/src/soc/intel/quark/i2c.c b/src/soc/intel/quark/i2c.c index 595c818593..bb1a26437f 100644 --- a/src/soc/intel/quark/i2c.c +++ b/src/soc/intel/quark/i2c.c @@ -38,7 +38,8 @@ static void i2c_disable(I2C_REGS *regs) while (status & IC_ENABLE_CONTROLLER) { udelay(1); if (--timeout == 0) - die("ERROR - I2C failed to disable!\n"); + die_with_post_code(POST_HW_INIT_FAILURE, + "ERROR - I2C failed to disable!\n"); status = regs->ic_enable_status; } From c58e3bd90a96bf01859d1c0af83926b1e17edff5 Mon Sep 17 00:00:00 2001 From: Keith Short Date: Fri, 10 May 2019 11:14:31 -0600 Subject: [PATCH 143/331] post_code: add post code for video initialization failure Add a new post code POST_VIDEO_FAILURE used when the Intel FSP silicon initialization returns an error when graphics was also initialized. BUG=b:124401932 BRANCH=sarien TEST=build coreboot for sarien and arcada platforms Change-Id: Ibc7f7defbed34038f445949010a37c8e368aae20 Signed-off-by: Keith Short Reviewed-on: https://review.coreboot.org/c/coreboot/+/32775 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph --- Documentation/POSTCODES | 1 + src/drivers/intel/fsp2_0/silicon_init.c | 14 +++++++++++++- src/include/console/post_codes.h | 7 +++++++ 3 files changed, 21 insertions(+), 1 deletion(-) diff --git a/Documentation/POSTCODES b/Documentation/POSTCODES index a9d392a9b0..0e67dd173c 100644 --- a/Documentation/POSTCODES +++ b/Documentation/POSTCODES @@ -21,6 +21,7 @@ This is an (incomplete) list of POST codes emitted by coreboot v4. 0xe2 Vendor binary (e.g. FSP) generated a fatal error 0xe3 RAM could not be initialized 0xe4 Critical hardware component could not initialize +0xe5 Video subsystem failed to initialize 0xf8 Entry into elf boot 0xf3 Jumping to payload diff --git a/src/drivers/intel/fsp2_0/silicon_init.c b/src/drivers/intel/fsp2_0/silicon_init.c index b0a697d8cb..e9c29db40e 100644 --- a/src/drivers/intel/fsp2_0/silicon_init.c +++ b/src/drivers/intel/fsp2_0/silicon_init.c @@ -18,6 +18,7 @@ #include #include #include +#include #include #include #include @@ -29,6 +30,7 @@ static void do_silicon_init(struct fsp_header *hdr) FSPS_UPD *upd, *supd; fsp_silicon_init_fn silicon_init; uint32_t status; + uint8_t postcode; supd = (FSPS_UPD *) (hdr->cfg_region_offset + hdr->image_base); @@ -59,8 +61,18 @@ static void do_silicon_init(struct fsp_header *hdr) /* Handle any errors returned by FspSiliconInit */ fsp_handle_reset(status); if (status != FSP_SUCCESS) { + if (vbt_get()) { + /* Attempted to initialize graphics. Assume failure + * is related to a video failure. + */ + postcode = POST_VIDEO_FAILURE; + } else { + /* Other silicon initialization failed */ + postcode = POST_HW_INIT_FAILURE; + } printk(BIOS_SPEW, "FspSiliconInit returned 0x%08x\n", status); - die("FspSiliconINit returned an error!\n"); + die_with_post_code(postcode, + "FspSiliconINit returned an error!\n"); } } diff --git a/src/include/console/post_codes.h b/src/include/console/post_codes.h index ae277d82e2..c1917adaff 100644 --- a/src/include/console/post_codes.h +++ b/src/include/console/post_codes.h @@ -355,6 +355,13 @@ */ #define POST_HW_INIT_FAILURE 0xe4 +/** + * \brief Video failure + * + * Video subsystem failed to initialize. + */ +#define POST_VIDEO_FAILURE 0xe5 + /** * \brief TPM failure * From f41afde6c2bbab86072b6a8cc23f91cdcd772a59 Mon Sep 17 00:00:00 2001 From: Keith Short Date: Fri, 10 May 2019 11:52:55 -0600 Subject: [PATCH 144/331] ec/google/wilco: set diagnostic LEDs on boot failure On Wilco devices, if any of the coreboot stages fails with a fatal error, set the diagnostic LEDs with the Wilco EC. The last saved post code is used to determine the error code sent to the EC. BUG=b:124401932 BRANCH=sarien TEST=build coreboot for sarien and arcada platforms TEST=Remove DIMM module, confirm diagnostic LED pattern for memory failure (2 amber, 4 white). TEST=Forced a fatal error in both bootblock and verstage to confirm diagnostic LEDs during these stages. This works on cold-boots only. Bug b:132622888 tracks the mailbox failures on warm boots. Change-Id: If865ab8203f89e499130f4677fec166b40d80174 Signed-off-by: Keith Short Signed-off-by: Duncan Laurie Reviewed-on: https://review.coreboot.org/c/coreboot/+/32777 Tested-by: build bot (Jenkins) Reviewed-by: Jett Rink Reviewed-by: Duncan Laurie Reviewed-by: Furquan Shaikh --- src/ec/google/wilco/commands.c | 43 +++++++++++++++++++++++++++++++--- src/ec/google/wilco/commands.h | 14 +++++------ 2 files changed, 46 insertions(+), 11 deletions(-) diff --git a/src/ec/google/wilco/commands.c b/src/ec/google/wilco/commands.c index a97a28ecce..9d4170f539 100644 --- a/src/ec/google/wilco/commands.c +++ b/src/ec/google/wilco/commands.c @@ -182,8 +182,45 @@ int wilco_ec_signed_fw(void) return !!ec_read(EC_RAM_SIGNED_FW); } -int wilco_ec_err_code(enum ec_err_code err_code) +struct err_code_entry { + uint8_t post_code; + enum ec_err_code ec_err; +}; + +/* + * Any post codes not listed in the post_code_err_map[] use default. + */ +static const enum ec_err_code default_ec_err = DLED_ROM; +static const struct err_code_entry post_code_err_map[] = { + { .post_code = POST_RAM_FAILURE, .ec_err = DLED_MEMORY, }, + { .post_code = POST_VIDEO_FAILURE, .ec_err = DLED_PANEL, }, +}; + +/* Records the most recent post code during boot */ +static uint8_t wilco_ec_saved_post_code; + +void wilco_ec_save_post_code(uint8_t post_code) { - return wilco_ec_mailbox(WILCO_EC_MSG_DEFAULT, KB_ERR_CODE, - &err_code, 1, NULL, 0); + wilco_ec_saved_post_code = post_code; +} + +/* Send error code to the EC based on last saved post code */ +void die_notify(void) +{ + size_t i; + enum ec_err_code err_code = default_ec_err; + + for (i = 0; i < ARRAY_SIZE(post_code_err_map); i++) { + if (post_code_err_map[i].post_code == + wilco_ec_saved_post_code) { + err_code = post_code_err_map[i].ec_err; + break; + } + } + + printk(BIOS_EMERG, "Fatal error: post_code 0x%02x, EC err 0x%02x\n", + wilco_ec_saved_post_code, err_code); + + wilco_ec_mailbox(WILCO_EC_MSG_DEFAULT, KB_ERR_CODE, + &err_code, 1, NULL, 0); } diff --git a/src/ec/google/wilco/commands.h b/src/ec/google/wilco/commands.h index fafb7fd8ba..9b7f2e5d07 100644 --- a/src/ec/google/wilco/commands.h +++ b/src/ec/google/wilco/commands.h @@ -319,16 +319,14 @@ enum ec_acpi_wake_events { int wilco_ec_signed_fw(void); /** - * wilco_ec_err_code + * wilco_ec_save_post_code * - * Send an error code to the EC to indicate a failed boot. The EC flashes the - * platform LED amber and white to provide user indication of the failure type. + * Save this post code as the most recent progress step. If the boot fails + * and calls die_notify() this post code will be used to send an error code + * to the EC indicating the failure. * - * @err_code: Error code to send to the EC - * - * Returns 0 if EC command was successful - * Returns -1 if EC command failed + * @post_code: Post code to save */ -int wilco_ec_err_code(enum ec_err_code err_code); +void wilco_ec_save_post_code(uint8_t post_code); #endif /* EC_GOOGLE_WILCO_COMMANDS_H */ From 239b13ce38e9f7edd86193a5edddb403cdac437d Mon Sep 17 00:00:00 2001 From: Duncan Laurie Date: Wed, 22 May 2019 10:14:26 -0700 Subject: [PATCH 145/331] mb/google/sarien: Send post code to the EC Use the mainboard post code hook to inform the wilco EC driver of the latest boot stage. BUG=b:124401932 BRANCH=sarien TEST=build coreboot for sarien and arcada platforms TEST=Remove DIMM module, confirm diagnostic LED pattern for memory failure (2 amber, 4 white). Change-Id: If5bf69365d8be3bdbd433f305c85848206ded7b0 Signed-off-by: Duncan Laurie Reviewed-on: https://review.coreboot.org/c/coreboot/+/32937 Reviewed-by: Jett Rink Reviewed-by: Furquan Shaikh Tested-by: build bot (Jenkins) --- src/mainboard/google/sarien/ramstage.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/src/mainboard/google/sarien/ramstage.c b/src/mainboard/google/sarien/ramstage.c index 1d220461cf..e246419373 100644 --- a/src/mainboard/google/sarien/ramstage.c +++ b/src/mainboard/google/sarien/ramstage.c @@ -15,6 +15,7 @@ #include #include +#include #include #include #include @@ -69,6 +70,11 @@ void mainboard_silicon_init_params(FSP_S_CONFIG *params) cnl_configure_pads(gpio_table, num_gpios); } +void mainboard_post(uint8_t value) +{ + wilco_ec_save_post_code(value); +} + static void mainboard_enable(struct device *dev) { dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator; From 84b8f90bba65c56c4122d0a214608ef4e882861c Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Mon, 20 May 2019 10:05:18 +0200 Subject: [PATCH 146/331] mb/asus/p8h61-m_pro: Add small fixes * Add VBT * Configure OnBoard NIC * Add documentation Change-Id: Iad739b4e1dacb41f5f63247150951df7013bbf0c Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/c/coreboot/+/32890 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Angel Pons --- Documentation/mainboard/asus/p8h61-m_pro.jpg | Bin 0 -> 69452 bytes Documentation/mainboard/asus/p8h61-m_pro.md | 103 +++++++++++++++++++ Documentation/mainboard/index.md | 1 + src/mainboard/asus/p8h61-m_pro/Kconfig | 3 + src/mainboard/asus/p8h61-m_pro/data.vbt | Bin 0 -> 3902 bytes src/mainboard/asus/p8h61-m_pro/devicetree.cb | 8 +- 6 files changed, 114 insertions(+), 1 deletion(-) create mode 100644 Documentation/mainboard/asus/p8h61-m_pro.jpg create mode 100644 Documentation/mainboard/asus/p8h61-m_pro.md create mode 100644 src/mainboard/asus/p8h61-m_pro/data.vbt diff --git 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Socketed flash | yes | ++---------------------+------------+ +| Model | W25Q32BV | ++---------------------+------------+ +| Size | 4 MiB | ++---------------------+------------+ +| Package | DIP-8 | ++---------------------+------------+ +| Write protection | no | ++---------------------+------------+ +| Dual BIOS feature | no | ++---------------------+------------+ +| Internal flashing | yes | ++---------------------+------------+ +``` + +The flash IC is located right next to one of the SATA ports: +![](p8h61-m_pro.jpg) + +### Internal programming + +The main SPI flash can be accessed using [flashrom]. By default, only +the BIOS region of the flash is writable. If you wish to change any +other region (Management Engine or flash descriptor), then an external +programmer is required. + +The following command may be used to flash coreboot: + +``` +$ sudo flashrom --noverify-all --ifd -i bios -p internal -w coreboot.rom +``` + +The use of `--noverify-all` is required since the Management Engine +region is not readable even by the host. + +## Known issues + +- There is no automatic, OS-independent fan control. This is because + the super I/O hardware monitor can only obtain valid CPU temperature + readings from the PECI agent, whose complete initialisation is not + publicly documented. The `coretemp` driver can still be used for + accurate CPU temperature readings. + +- me_cleaner breaks LPC bus and attached components! +- PS/2 mouse doesn't work + +## Untested + +- parallel port +- EHCI debug +- S/PDIF audio + +## Working + +- PS/2 keyboard +- PCIe graphics +- USB +- Gigabit Ethernet +- Integrated graphics +- SATA +- Serial port +- hardware monitor (see [Known issues](#known-issues) for caveats) +- front panel audio +- Native raminit (2 x 2GB, DDR3-1333) +- Native graphics init (libgfxinit) +- Wake-on-LAN +- TPM on TPM-header + +## Technology + +```eval_rst ++------------------+--------------------------------------------------+ +| Northbridge | :doc:`../../northbridge/intel/sandybridge/index` | ++------------------+--------------------------------------------------+ +| Southbridge | bd82x6x | ++------------------+--------------------------------------------------+ +| CPU | model_206ax | ++------------------+--------------------------------------------------+ +| Super I/O | Nuvoton NCT6776 | ++------------------+--------------------------------------------------+ +| EC | None | ++------------------+--------------------------------------------------+ +| Coprocessor | Intel Management Engine | ++------------------+--------------------------------------------------+ +``` + +## Extra resources + +- [Flash chip datasheet][W25Q32BV] + +[ASUS P8H61-M Pro]: https://www.asus.com/Motherboards/P8H61M_Pro/ +[W25Q32BV]: https://www.winbond.com/resource-files/w25q32bv_revi_100413_wo_automotive.pdf +[flashrom]: https://flashrom.org/Flashrom diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md index eced74966e..1494e06244 100644 --- a/Documentation/mainboard/index.md +++ b/Documentation/mainboard/index.md @@ -6,6 +6,7 @@ This section contains documentation about coreboot on specific mainboards. - [F2A85-M](asus/f2a85-m.md) - [P8H61-M LX](asus/p8h61-m_lx.md) +- [P8H61-M Pro](asus/p8h61-m_pro.md) ## ASRock diff --git a/src/mainboard/asus/p8h61-m_pro/Kconfig b/src/mainboard/asus/p8h61-m_pro/Kconfig index 14f841e649..e8a6f6404a 100644 --- a/src/mainboard/asus/p8h61-m_pro/Kconfig +++ b/src/mainboard/asus/p8h61-m_pro/Kconfig @@ -31,6 +31,9 @@ config BOARD_SPECIFIC_OPTIONS select HAVE_CMOS_DEFAULT select DRIVERS_ASMEDIA_ASPM_BLACKLIST select MAINBOARD_HAS_LPC_TPM + select REALTEK_8168_RESET + select RT8168_SET_LED_MODE + select INTEL_GMA_HAVE_VBT config MAINBOARD_DIR string diff --git a/src/mainboard/asus/p8h61-m_pro/data.vbt b/src/mainboard/asus/p8h61-m_pro/data.vbt new file mode 100644 index 0000000000000000000000000000000000000000..114a840660fcd06b44a58fbac5428b549c909c34 GIT binary patch literal 3902 zcmdT{U1%It6h5;v`*&w1*-T=)S<`S+OS?()Gueg^Le$yKCT7!Zc9Y#MYZ1FiciR-w zG~NEtf;CeOwjz{Oq}EzxQIy)J(kDS5`XoU`LJ<-1p%fpa6zM||EVb*oGm{@0X$Q4f z@9^Do?wNDHz4y#HcV;(aB59f$iFCv=k+$eSYHK=?%!3NgR4dr8Zjo3bwKEz{hj&Ke ziToRB)`BrpBl9$0mw<^Lq*%u_Km7ll?Io-nFYR zRVa=hD&%P@^IVuRTA4%+@14rik;D5Y3dLT^xX_z+cC~NmqO?=(=nQp))Xq+dw|cv} zdbf1RBs$Qa*p`gN!|7OJgeJylG?ogdQUlu}@#krBEHM;|#L@#%nHXE?-#>G#xOdOw zAsXy&rXf{T+YCZu$+Uleai*Pyr>5u_^EpVz3I_|tBZYjsOc=ox-Xm}va89T`p>f_n zLXgv_6q!*I9a(7|o2Oy?|FV@mJ|aJm`v^OpU*W%u5~ zCyb3)QnaLDw9!>6Za3VkeCvlw#q%^~I#>F}c)q)K)qy-B?uqxr0;-!&tYx zr*BR&ShoXIPF8t=d*8VOes{J(^&8+d&$z{3{a2;eI5})n)+|4KMKZE)acbQM;0l-n zci*D%e)(VCS+f;SSl%dR4=Wp^sdH5T@xkQIcpjxrd?UI_=C_r%bUTJx@VnW9P+4f zB_sP#bFtS5fK(rZdbopEJ(M^K<~5Hm1oLX;mbCz5dGZ@rz>{#neVaQ~`*><>U-nw1 z($Edxd-W2%w$A6ttv6>i+OY)v7}SG*`7_OL1OJwne&$ua@{;eo^p01N2w6jDA5lgK z$rAc9QA&iIBlHSUt`hPSp$<{06G@{;qoR@#Nlv7%iON}#d??a+QTb6MKZ}$|N`pi; zN;EDhFG^%mqNgRLERl;6U67RP61gc+MOHS*q+OapXuDr=3XdZpvI7g+_I-WIYQ%MzUlay0{cOad@e{RL%t& zHI-VYQe*e5Q1TkP(A{=+5$w~;Gnbx1h88vp02!Pm;~gZGopUzw;aqchVRUZ2ntXTd z5(5t+(*00LtU*qP+MLf Date: Tue, 21 May 2019 17:22:49 +0200 Subject: [PATCH 147/331] src/mainboard/google: Adopt Mainboards to changed Type41 Func Required for automatic onboard device detection in the next patch. Change-Id: I3087de779faf8d006510c460b5372b22ae54b887 Signed-off-by: Christian Walter Reviewed-on: https://review.coreboot.org/c/coreboot/+/32909 Reviewed-by: Duncan Laurie Tested-by: build bot (Jenkins) --- src/arch/x86/smbios.c | 4 ++-- src/include/smbios.h | 2 +- .../google/auron/variants/auron_paine/variant.c | 3 ++- src/mainboard/google/auron/variants/auron_yuna/variant.c | 3 ++- src/mainboard/google/auron/variants/buddy/variant.c | 3 ++- src/mainboard/google/auron/variants/gandof/variant.c | 3 ++- src/mainboard/google/auron/variants/lulu/variant.c | 6 ++++-- src/mainboard/google/butterfly/mainboard.c | 3 ++- src/mainboard/google/link/mainboard.c | 9 ++++++--- src/mainboard/google/parrot/mainboard.c | 6 ++++-- src/mainboard/google/rambi/mainboard.c | 6 ++++-- src/mainboard/google/slippy/mainboard.c | 9 ++++++--- 12 files changed, 37 insertions(+), 20 deletions(-) diff --git a/src/arch/x86/smbios.c b/src/arch/x86/smbios.c index 90cd674198..310a870da6 100644 --- a/src/arch/x86/smbios.c +++ b/src/arch/x86/smbios.c @@ -962,7 +962,7 @@ int smbios_write_type38(unsigned long *current, int *handle, int smbios_write_type41(unsigned long *current, int *handle, const char *name, u8 instance, u16 segment, - u8 bus, u8 device, u8 function) + u8 bus, u8 device, u8 function, u8 device_type) { struct smbios_type41 *t = (struct smbios_type41 *)*current; int len = sizeof(struct smbios_type41); @@ -972,7 +972,7 @@ int smbios_write_type41(unsigned long *current, int *handle, t->handle = *handle; t->length = len - 2; t->reference_designation = smbios_add_string(t->eos, name); - t->device_type = SMBIOS_DEVICE_TYPE_OTHER; + t->device_type = device_type; t->device_status = 1; t->device_type_instance = instance; t->segment_group_number = segment; diff --git a/src/include/smbios.h b/src/include/smbios.h index afe77d6ad9..017e90e742 100644 --- a/src/include/smbios.h +++ b/src/include/smbios.h @@ -44,7 +44,7 @@ int smbios_write_type38(unsigned long *current, int *handle, const u8 irq); int smbios_write_type41(unsigned long *current, int *handle, const char *name, u8 instance, u16 segment, - u8 bus, u8 device, u8 function); + u8 bus, u8 device, u8 function, u8 device_type); const char *smbios_system_manufacturer(void); const char *smbios_system_product_name(void); diff --git a/src/mainboard/google/auron/variants/auron_paine/variant.c b/src/mainboard/google/auron/variants/auron_paine/variant.c index 62d4f522f7..84e26db1b7 100644 --- a/src/mainboard/google/auron/variants/auron_paine/variant.c +++ b/src/mainboard/google/auron/variants/auron_paine/variant.c @@ -26,7 +26,8 @@ int variant_smbios_data(struct device *dev, int *handle, unsigned long *current) BOARD_TRACKPAD_I2C_BUS, /* segment */ BOARD_TRACKPAD_I2C_ADDR, /* bus */ 0, /* device */ - 0); /* function */ + 0, /* function */ + SMBIOS_DEVICE_TYPE_OTHER); /* device type */ return len; } diff --git a/src/mainboard/google/auron/variants/auron_yuna/variant.c b/src/mainboard/google/auron/variants/auron_yuna/variant.c index 62d4f522f7..84e26db1b7 100644 --- a/src/mainboard/google/auron/variants/auron_yuna/variant.c +++ b/src/mainboard/google/auron/variants/auron_yuna/variant.c @@ -26,7 +26,8 @@ int variant_smbios_data(struct device *dev, int *handle, unsigned long *current) BOARD_TRACKPAD_I2C_BUS, /* segment */ BOARD_TRACKPAD_I2C_ADDR, /* bus */ 0, /* device */ - 0); /* function */ + 0, /* function */ + SMBIOS_DEVICE_TYPE_OTHER); /* device type */ return len; } diff --git a/src/mainboard/google/auron/variants/buddy/variant.c b/src/mainboard/google/auron/variants/buddy/variant.c index 9f8188fe43..dcda04dbb6 100644 --- a/src/mainboard/google/auron/variants/buddy/variant.c +++ b/src/mainboard/google/auron/variants/buddy/variant.c @@ -35,7 +35,8 @@ int variant_smbios_data(struct device *dev, int *handle, unsigned long *current) BOARD_TOUCHSCREEN_I2C_BUS, /* segment */ BOARD_TOUCHSCREEN_I2C_ADDR, /* bus */ 0, /* device */ - 0); /* function */ + 0, /* function */ + SMBIOS_DEVICE_TYPE_OTHER); /* device type */ return len; } diff --git a/src/mainboard/google/auron/variants/gandof/variant.c b/src/mainboard/google/auron/variants/gandof/variant.c index cd7a66332d..29b298839f 100644 --- a/src/mainboard/google/auron/variants/gandof/variant.c +++ b/src/mainboard/google/auron/variants/gandof/variant.c @@ -29,7 +29,8 @@ int variant_smbios_data(struct device *dev, int *handle, unsigned long *current) BOARD_TRACKPAD_I2C_BUS, /* segment */ BOARD_TRACKPAD_I2C_ADDR, /* bus */ 0, /* device */ - 0); /* function */ + 0, /* function */ + SMBIOS_DEVICE_TYPE_OTHER); /* device type */ return len; } diff --git a/src/mainboard/google/auron/variants/lulu/variant.c b/src/mainboard/google/auron/variants/lulu/variant.c index 97302b8486..a76cc858c3 100644 --- a/src/mainboard/google/auron/variants/lulu/variant.c +++ b/src/mainboard/google/auron/variants/lulu/variant.c @@ -29,7 +29,8 @@ int variant_smbios_data(struct device *dev, int *handle, unsigned long *current) BOARD_TRACKPAD_I2C_BUS, /* segment */ BOARD_TRACKPAD_I2C_ADDR, /* bus */ 0, /* device */ - 0); /* function */ + 0, /* function */ + SMBIOS_DEVICE_TYPE_OTHER); /* device type */ len += smbios_write_type41( current, handle, @@ -38,7 +39,8 @@ int variant_smbios_data(struct device *dev, int *handle, unsigned long *current) BOARD_TOUCHSCREEN_I2C_BUS, /* segment */ BOARD_TOUCHSCREEN_I2C_ADDR, /* bus */ 0, /* device */ - 0); /* function */ + 0, /* function */ + SMBIOS_DEVICE_TYPE_OTHER); /* device type */ return len; } diff --git a/src/mainboard/google/butterfly/mainboard.c b/src/mainboard/google/butterfly/mainboard.c index 9cc13c9473..c298689639 100644 --- a/src/mainboard/google/butterfly/mainboard.c +++ b/src/mainboard/google/butterfly/mainboard.c @@ -264,7 +264,8 @@ static int butterfly_onboard_smbios_data(struct device *dev, int *handle, 0, /* segment */ BOARD_TRACKPAD_I2C_ADDR, /* bus */ 0, /* device */ - 0); /* function */ + 0, /* function */ + SMBIOS_DEVICE_TYPE_OTHER); /* device type */ return len; } diff --git a/src/mainboard/google/link/mainboard.c b/src/mainboard/google/link/mainboard.c index 410866d0fe..37d1a672cd 100644 --- a/src/mainboard/google/link/mainboard.c +++ b/src/mainboard/google/link/mainboard.c @@ -170,7 +170,8 @@ static int link_onboard_smbios_data(struct device *dev, int *handle, 0, /* segment */ BOARD_LIGHTSENSOR_I2C_ADDR, /* bus */ 0, /* device */ - 0); /* function */ + 0, /* function */ + SMBIOS_DEVICE_TYPE_OTHER); /* device type */ len += smbios_write_type41( current, handle, @@ -179,7 +180,8 @@ static int link_onboard_smbios_data(struct device *dev, int *handle, 0, /* segment */ BOARD_TRACKPAD_I2C_ADDR, /* bus */ 0, /* device */ - 0); /* function */ + 0, /* function */ + SMBIOS_DEVICE_TYPE_OTHER); /* device type */ len += smbios_write_type41( current, handle, @@ -188,7 +190,8 @@ static int link_onboard_smbios_data(struct device *dev, int *handle, 0, /* segment */ BOARD_TOUCHSCREEN_I2C_ADDR, /* bus */ 0, /* device */ - 0); /* function */ + 0, /* function */ + SMBIOS_DEVICE_TYPE_OTHER); /* device type */ return len; } diff --git a/src/mainboard/google/parrot/mainboard.c b/src/mainboard/google/parrot/mainboard.c index 52e4af3ea7..8c3ad6352e 100644 --- a/src/mainboard/google/parrot/mainboard.c +++ b/src/mainboard/google/parrot/mainboard.c @@ -57,7 +57,8 @@ static int parrot_onboard_smbios_data(struct device *dev, int *handle, 0, /* segment */ BOARD_TRACKPAD_I2C_ADDR, /* bus */ 0, /* device */ - 0); /* function */ + 0, /* function */ + SMBIOS_DEVICE_TYPE_OTHER); /* device type */ } else { len += smbios_write_type41( current, handle, @@ -66,7 +67,8 @@ static int parrot_onboard_smbios_data(struct device *dev, int *handle, 0, /* segment */ BOARD_TRACKPAD_I2C_ADDR, /* bus */ 0, /* device */ - 0); /* function */ + 0, /* function */ + SMBIOS_DEVICE_TYPE_OTHER); /* device type */ } return len; diff --git a/src/mainboard/google/rambi/mainboard.c b/src/mainboard/google/rambi/mainboard.c index 15faac9bf8..d3f6164cd3 100644 --- a/src/mainboard/google/rambi/mainboard.c +++ b/src/mainboard/google/rambi/mainboard.c @@ -142,7 +142,8 @@ static int mainboard_smbios_data(struct device *dev, int *handle, BOARD_TRACKPAD_I2C_BUS, /* segment */ BOARD_TRACKPAD_I2C_ADDR, /* bus */ 0, /* device */ - 0); /* function */ + 0, /* function */ + SMBIOS_DEVICE_TYPE_OTHER); /* device type */ #endif #ifdef BOARD_TOUCHSCREEN_NAME len += smbios_write_type41( @@ -152,7 +153,8 @@ static int mainboard_smbios_data(struct device *dev, int *handle, BOARD_TOUCHSCREEN_I2C_BUS, /* segment */ BOARD_TOUCHSCREEN_I2C_ADDR, /* bus */ 0, /* device */ - 0); /* function */ + 0, /* function */ + SMBIOS_DEVICE_TYPE_OTHER); /* device type */ #endif return len; } diff --git a/src/mainboard/google/slippy/mainboard.c b/src/mainboard/google/slippy/mainboard.c index 4bbc1d6907..b98fc8a380 100644 --- a/src/mainboard/google/slippy/mainboard.c +++ b/src/mainboard/google/slippy/mainboard.c @@ -54,7 +54,8 @@ static int mainboard_smbios_data(struct device *dev, int *handle, BOARD_LIGHTSENSOR_I2C_BUS, /* segment */ BOARD_LIGHTSENSOR_I2C_ADDR, /* bus */ 0, /* device */ - 0); /* function */ + 0, /* function */ + SMBIOS_DEVICE_TYPE_OTHER); /* device type */ len += smbios_write_type41( current, handle, @@ -63,7 +64,8 @@ static int mainboard_smbios_data(struct device *dev, int *handle, BOARD_TRACKPAD_I2C_BUS, /* segment */ BOARD_TRACKPAD_I2C_ADDR, /* bus */ 0, /* device */ - 0); /* function */ + 0, /* function */ + SMBIOS_DEVICE_TYPE_OTHER); /* device type */ len += smbios_write_type41( current, handle, @@ -72,7 +74,8 @@ static int mainboard_smbios_data(struct device *dev, int *handle, BOARD_TOUCHSCREEN_I2C_BUS, /* segment */ BOARD_TOUCHSCREEN_I2C_ADDR, /* bus */ 0, /* device */ - 0); /* function */ + 0, /* function */ + SMBIOS_DEVICE_TYPE_OTHER); /* device type */ return len; } From e8e92d60c4e2a17542a98bdfb3a533060d26a281 Mon Sep 17 00:00:00 2001 From: Julius Werner Date: Tue, 7 May 2019 17:29:21 -0700 Subject: [PATCH 148/331] endian.h: Add be32dec/be32enc family of functions Libpayload has a family of functions that can "encode" or "decode" an endian-specific integer onto a byte stream pointer. These allow writing more pretty code than a raw be32_to_cpu/cpu_to_be32 with pointer casts in many (de-)serialization scenarios, so let's add them to coreboot as well. Change-Id: I049c5665484da12b3cf977a529310b0bde177d2d Signed-off-by: Julius Werner Reviewed-on: https://review.coreboot.org/c/coreboot/+/32856 Reviewed-by: Aaron Durbin Tested-by: build bot (Jenkins) --- src/include/endian.h | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/src/include/endian.h b/src/include/endian.h index 08636f3da6..8dc18542ae 100644 --- a/src/include/endian.h +++ b/src/include/endian.h @@ -85,6 +85,32 @@ #define setbits_8(addr, set) setbits_8(addr, 0, set) #ifndef __ROMCC__ +/* be16dec/be32dec/be64dec/le16dec/le32dec/le64dec family of functions. */ +#define DEFINE_ENDIAN_DEC(endian, width) \ + static inline uint##width##_t endian##width##dec(const void *p) \ + { \ + return endian##width##_to_cpu(*(uint##width##_t *)p); \ + } +DEFINE_ENDIAN_DEC(be, 16) +DEFINE_ENDIAN_DEC(be, 32) +DEFINE_ENDIAN_DEC(be, 64) +DEFINE_ENDIAN_DEC(le, 16) +DEFINE_ENDIAN_DEC(le, 32) +DEFINE_ENDIAN_DEC(le, 64) + +/* be16enc/be32enc/be64enc/le16enc/le32enc/le64enc family of functions. */ +#define DEFINE_ENDIAN_ENC(endian, width) \ + static inline void endian##width##enc(void *p, uint##width##_t u) \ + { \ + *(uint##width##_t *)p = cpu_to_##endian##width(u); \ + } +DEFINE_ENDIAN_ENC(be, 16) +DEFINE_ENDIAN_ENC(be, 32) +DEFINE_ENDIAN_ENC(be, 64) +DEFINE_ENDIAN_ENC(le, 16) +DEFINE_ENDIAN_ENC(le, 32) +DEFINE_ENDIAN_ENC(le, 64) + /* * Portable (API) endian support that can be used in code that is shared * with userspace (man 3 endian) tools. From 2b6da7f326bf84a8eab3684edf5e5814e9c23385 Mon Sep 17 00:00:00 2001 From: Julius Werner Date: Thu, 16 May 2019 16:22:18 -0700 Subject: [PATCH 149/331] commonlib/stdlib.h: Remove printf() from coreboot coreboot should not have a definition of printf() anywhere -- it's too easy to accidentally sneak it into code otherwise. Where that is needed in code shared with userspace utilities, we should instead use printk() and define a shim for that for the userspace side. Change-Id: Iaa459df7122c88beb56695eee7c252d90bbde861 Signed-off-by: Julius Werner Reviewed-on: https://review.coreboot.org/c/coreboot/+/32857 Reviewed-by: Patrick Georgi Reviewed-by: HAOUAS Elyes Tested-by: build bot (Jenkins) --- src/commonlib/include/commonlib/stdlib.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/commonlib/include/commonlib/stdlib.h b/src/commonlib/include/commonlib/stdlib.h index 1a05eebd55..4a3671c7ab 100644 --- a/src/commonlib/include/commonlib/stdlib.h +++ b/src/commonlib/include/commonlib/stdlib.h @@ -38,11 +38,11 @@ #if CONFIG(COREBOOT_BUILD) #include #include -#define printf(...) printk(BIOS_ERR, __VA_ARGS__) #define HALT(x) halt() #else #include -#define HALT(x) +#define printk(level, ...) printf(__VA_ARGS__) +#define HALT(x) abort() #endif static inline void *xmalloc_work(size_t size, const char *file, @@ -50,7 +50,7 @@ static inline void *xmalloc_work(size_t size, const char *file, { void *ret = malloc(size); if (!ret && size) { - printf("%s/%s/line %d: Failed to malloc %zu bytes\n", + printk(BIOS_ERR, "%s/%s/line %d: Failed to malloc %zu bytes\n", file, func, line, size); while (1) HALT(1); From 66c77c2dc9b16d3b3522697ea04009aad1c8ba79 Mon Sep 17 00:00:00 2001 From: Julius Werner Date: Mon, 13 May 2019 17:45:27 -0700 Subject: [PATCH 150/331] console: Move poor-man's atoi() into string.h vtxprintf.c seems to have been written before string.h was as fleshed out as it is today -- this patch removes some custom implementation of stuff we now have globally. It also makes the skip_atoi() function globally available, because I need it somewhere else, and while we maybe don't want a huge fully-featured string parsing library in coreboot, being able to parse an integer is occasionally useful. Change-Id: Iecb2b970aecfc768540d2bf8b3023445f54853a4 Signed-off-by: Julius Werner Reviewed-on: https://review.coreboot.org/c/coreboot/+/32858 Tested-by: build bot (Jenkins) Reviewed-by: Alex Thiessen --- src/console/vtxprintf.c | 22 ++++------------------ src/include/string.h | 15 +++++++++++++++ 2 files changed, 19 insertions(+), 18 deletions(-) diff --git a/src/console/vtxprintf.c b/src/console/vtxprintf.c index f42ed6d077..c429ac79e2 100644 --- a/src/console/vtxprintf.c +++ b/src/console/vtxprintf.c @@ -24,20 +24,6 @@ #define SUPPORT_64BIT_INTS #endif -/* haha, don't need ctype.c */ -#define isdigit(c) ((c) >= '0' && (c) <= '9') -#define is_digit isdigit -#define isxdigit(c) (((c) >= '0' && (c) <= '9') || ((c) >= 'a' && (c) <= 'f') || ((c) >= 'A' && (c) <= 'F')) - -static int skip_atoi(const char **s) -{ - int i = 0; - - while (is_digit(**s)) - i = i*10 + *((*s)++) - '0'; - return i; -} - #define ZEROPAD 1 /* pad with zero */ #define SIGN 2 /* unsigned/signed long */ #define PLUS 4 /* show plus */ @@ -175,8 +161,8 @@ repeat: /* get field width */ field_width = -1; - if (is_digit(*fmt)) { - field_width = skip_atoi(&fmt); + if (isdigit(*fmt)) { + field_width = skip_atoi((char **)&fmt); } else if (*fmt == '*') { ++fmt; /* it's the next argument */ @@ -191,8 +177,8 @@ repeat: precision = -1; if (*fmt == '.') { ++fmt; - if (is_digit(*fmt)) { - precision = skip_atoi(&fmt); + if (isdigit(*fmt)) { + precision = skip_atoi((char **)&fmt); } else if (*fmt == '*') { ++fmt; /* it's the next argument */ diff --git a/src/include/string.h b/src/include/string.h index 4a2f5e9ee6..c56a760a04 100644 --- a/src/include/string.h +++ b/src/include/string.h @@ -178,4 +178,19 @@ static inline int tolower(int c) c -= 'A'-'a'; return c; } + +/* + * Parses an unsigned integer and moves the input pointer forward to the first + * character that's not a valid digit. s and *s must not be NULL. Result + * undefined if it overruns the return type size. + */ +static inline unsigned int skip_atoi(char **s) +{ + unsigned int i = 0; + + while (isdigit(**s)) + i = i*10 + *((*s)++) - '0'; + return i; +} + #endif /* STRING_H */ From b3f852fba3cfd4ebde8cd7a34df069ba4cebe7a1 Mon Sep 17 00:00:00 2001 From: Julius Werner Date: Fri, 3 May 2019 16:58:24 -0700 Subject: [PATCH 151/331] fit: Add "board-skuX" (without -rev) to allowed compatible strings In some cases we may have boards that need to differentiate SKUs but don't really want to differentiate revisions (at least for some SKUs). Let's add a compatible string match that includes only the SKU but not the revision so that kernel DTSes don't have to specify every possible revision if they want to match this. This patch was adapted from depthcharge's http://crosreview.com/1512004 Change-Id: Ib88862424b350a213761f5662fe170a1f8fccc7f Signed-off-by: Julius Werner Reviewed-on: https://review.coreboot.org/c/coreboot/+/32859 Reviewed-by: Hung-Te Lin Tested-by: build bot (Jenkins) --- src/lib/fit.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/src/lib/fit.c b/src/lib/fit.c index a8bca47bdc..3aad806f2e 100644 --- a/src/lib/fit.c +++ b/src/lib/fit.c @@ -63,6 +63,14 @@ static void fit_add_default_compat_strings(void) fit_add_compat_string(compat_string); } + if (sku_id() != UNDEFINED_STRAPPING_ID) { + snprintf(compat_string, sizeof(compat_string), "%s,%s-sku%u", + CONFIG_MAINBOARD_VENDOR, CONFIG_MAINBOARD_PART_NUMBER, + sku_id()); + + fit_add_compat_string(compat_string); + } + if (board_id() != UNDEFINED_STRAPPING_ID) { snprintf(compat_string, sizeof(compat_string), "%s,%s-rev%u", CONFIG_MAINBOARD_VENDOR, CONFIG_MAINBOARD_PART_NUMBER, From a5ea3a271bbaa10f03115ffe3f473a07ca95c5ab Mon Sep 17 00:00:00 2001 From: Julius Werner Date: Tue, 7 May 2019 17:38:12 -0700 Subject: [PATCH 152/331] device_tree: Use be32dec/be32enc where appropriate This patch rewrites some of the device tree code to use the new be32dec/be32enc helpers where they can make the code cleaner. Change-Id: I437bbd6645a556ae9a0cfe6ea14638098e4c3606 Signed-off-by: Julius Werner Reviewed-on: https://review.coreboot.org/c/coreboot/+/32860 Reviewed-by: Hung-Te Lin Tested-by: build bot (Jenkins) --- src/lib/device_tree.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/src/lib/device_tree.c b/src/lib/device_tree.c index 79561a69b8..8dbc510c10 100644 --- a/src/lib/device_tree.c +++ b/src/lib/device_tree.c @@ -56,7 +56,7 @@ int fdt_next_property(const void *blob, uint32_t offset, int fdt_node_name(const void *blob, uint32_t offset, const char **name) { uint8_t *ptr = ((uint8_t *)blob) + offset; - if (be32toh(*(uint32_t *)ptr) != FDT_TOKEN_BEGIN_NODE) + if (be32dec(ptr) != FDT_TOKEN_BEGIN_NODE) return 0; ptr += 4; @@ -358,14 +358,14 @@ static void dt_flatten_prop(struct device_tree_property *prop, uint8_t *dstruct = (uint8_t *)*struct_start; uint8_t *dstrings = (uint8_t *)*strings_start; - *((uint32_t *)dstruct) = htobe32(FDT_TOKEN_PROPERTY); + be32enc(dstruct, FDT_TOKEN_PROPERTY); dstruct += sizeof(uint32_t); - *((uint32_t *)dstruct) = htobe32(prop->prop.size); + be32enc(dstruct, prop->prop.size); dstruct += sizeof(uint32_t); uint32_t name_offset = (uintptr_t)dstrings - (uintptr_t)strings_base; - *((uint32_t *)dstruct) = htobe32(name_offset); + be32enc(dstruct, name_offset); dstruct += sizeof(uint32_t); strcpy((char *)dstrings, prop->prop.name); @@ -385,7 +385,7 @@ static void dt_flatten_node(const struct device_tree_node *node, uint8_t *dstruct = (uint8_t *)*struct_start; uint8_t *dstrings = (uint8_t *)*strings_start; - *((uint32_t *)dstruct) = htobe32(FDT_TOKEN_BEGIN_NODE); + be32enc(dstruct, FDT_TOKEN_BEGIN_NODE); dstruct += sizeof(uint32_t); strcpy((char *)dstruct, node->name); @@ -401,7 +401,7 @@ static void dt_flatten_node(const struct device_tree_node *node, dt_flatten_node(child, (void **)&dstruct, strings_base, (void **)&dstrings); - *((uint32_t *)dstruct) = htobe32(FDT_TOKEN_END_NODE); + be32enc(dstruct, FDT_TOKEN_END_NODE); dstruct += sizeof(uint32_t); *struct_start = dstruct; @@ -489,9 +489,9 @@ void dt_read_cell_props(const struct device_tree_node *node, u32 *addrcp, struct device_tree_property *prop; list_for_each(prop, node->properties, list_node) { if (addrcp && !strcmp("#address-cells", prop->prop.name)) - *addrcp = be32toh(*(u32 *)prop->prop.data); + *addrcp = be32dec(prop->prop.data); if (sizecp && !strcmp("#size-cells", prop->prop.name)) - *sizecp = be32toh(*(u32 *)prop->prop.data); + *sizecp = be32dec(prop->prop.data); } } From e0b9aea7be96f1d724a6c794dd617122125f1ba6 Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Mon, 28 Jan 2019 18:14:13 +0100 Subject: [PATCH 153/331] lib/bootblock: Sanitize CMOS after bootblock_*_early_init() CMOS isn't used that early, but the chipset initialization may be required to access it. In one instance, Intel Apollo Lake, the sanitize_cmos() function seems to hang if called before bootblock_soc_early_init(). The missing step is fast_spi_early_init(). But even without, one might expect sanitize_cmos() to return eventually (it didn't within about 20min). Change-Id: I6e1a029e4be7e109be43a3dad944bd7e05ea1f02 Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/c/coreboot/+/31349 Tested-by: build bot (Jenkins) Reviewed-by: Alex Thiessen --- src/lib/bootblock.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/lib/bootblock.c b/src/lib/bootblock.c index 43674effc7..c28a67aceb 100644 --- a/src/lib/bootblock.c +++ b/src/lib/bootblock.c @@ -42,12 +42,12 @@ asmlinkage void bootblock_main_with_timestamp(uint64_t base_timestamp, timestamps[i].entry_stamp); } - sanitize_cmos(); - cmos_post_init(); - bootblock_soc_early_init(); bootblock_mainboard_early_init(); + sanitize_cmos(); + cmos_post_init(); + if (CONFIG(BOOTBLOCK_CONSOLE)) { console_init(); exception_init(); From dedf66ecdf79edece1039fe8bd019a0a544cfccb Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Mon, 20 May 2019 12:35:48 +0200 Subject: [PATCH 154/331] cpu/amd/quadcore: Remove variable set but not used Change-Id: I73f35ea80976ab445c797c4800b1e2fd24d34fdf Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/32893 Reviewed-by: Marshall Dawson Tested-by: build bot (Jenkins) --- src/cpu/amd/quadcore/quadcore.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/cpu/amd/quadcore/quadcore.c b/src/cpu/amd/quadcore/quadcore.c index ad4a7ead6d..125876badf 100644 --- a/src/cpu/amd/quadcore/quadcore.c +++ b/src/cpu/amd/quadcore/quadcore.c @@ -95,13 +95,13 @@ void real_start_other_core(uint32_t nodeid, uint32_t cores) */ /* Wait for the first core of each compute unit to start... */ - uint32_t timeout; for (i = 1; i < cores + 1; i++) { if (!(i & 0x1)) { uint32_t ap_apicid = get_boot_apic_id(nodeid, i); - timeout = wait_cpu_state(ap_apicid, - F10_APSTATE_ASLEEP, F10_APSTATE_ASLEEP); + /* Timeout */ + wait_cpu_state(ap_apicid, F10_APSTATE_ASLEEP, + F10_APSTATE_ASLEEP); } } From 3d23890c65e4a0c08bc346e8c3c2b4161440b4c6 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Tue, 21 May 2019 21:35:02 +0200 Subject: [PATCH 155/331] soc/intel/denverton_ns: Remove variable set but not used Change-Id: Ic04231525c1aaaf3afc8c11cddc409b1f5b46743 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/32913 Reviewed-by: Patrick Georgi Reviewed-by: David Guckian Tested-by: build bot (Jenkins) --- src/soc/intel/denverton_ns/cpu.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/src/soc/intel/denverton_ns/cpu.c b/src/soc/intel/denverton_ns/cpu.c index 2a631718c0..fc1024afa7 100644 --- a/src/soc/intel/denverton_ns/cpu.c +++ b/src/soc/intel/denverton_ns/cpu.c @@ -38,7 +38,6 @@ static struct smm_relocation_attrs relo_attrs; static void dnv_configure_mca(void) { msr_t msr; - int num_banks; struct cpuid_result cpuid_regs; /* Check feature flag in CPUID.(EAX=1):EDX[7]==1 MCE @@ -48,7 +47,6 @@ static void dnv_configure_mca(void) return; msr = rdmsr(IA32_MCG_CAP); - num_banks = msr.lo & IA32_MCG_CAP_COUNT_MASK; if (msr.lo & IA32_MCG_CAP_CTL_P_MASK) { /* Enable all error logging */ msr.lo = msr.hi = 0xffffffff; From ce83f3103c9b7d0e6daa6b95544d880660d0b6e9 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Mon, 20 May 2019 18:31:38 +0200 Subject: [PATCH 156/331] nb/intel/haswell: Remove variable set but not used Change-Id: I4e7f74f67f03131fae205a93dae3d61eca9cc0c7 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/32895 Reviewed-by: Patrick Georgi Tested-by: build bot (Jenkins) --- src/northbridge/intel/haswell/raminit.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/src/northbridge/intel/haswell/raminit.c b/src/northbridge/intel/haswell/raminit.c index c24bb67db7..9beb23cc8e 100644 --- a/src/northbridge/intel/haswell/raminit.c +++ b/src/northbridge/intel/haswell/raminit.c @@ -186,7 +186,7 @@ void sdram_initialize(struct pei_data *pei_data) void setup_sdram_meminfo(struct pei_data *pei_data) { - u32 addr_decoder_common, addr_decode_ch[2]; + u32 addr_decode_ch[2]; struct memory_info* mem_info; struct dimm_info *dimm; int ddr_frequency; @@ -199,7 +199,8 @@ void setup_sdram_meminfo(struct pei_data *pei_data) die("Failed to add memory info to CBMEM.\n"); memset(mem_info, 0, sizeof(struct memory_info)); - addr_decoder_common = MCHBAR32(0x5000); + /* FIXME: Do we need to read MCHBAR32(0x5000) ? */ + MCHBAR32(0x5000); addr_decode_ch[0] = MCHBAR32(0x5004); addr_decode_ch[1] = MCHBAR32(0x5008); From 0c89c1c05e514c8c6ddc5a844f84a2b422f1bd56 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Mon, 20 May 2019 18:39:27 +0200 Subject: [PATCH 157/331] nb/intel/x4x/early_init.c: Remove variable set but not used Change-Id: I8d0ab8bdc506592ef1d731e557b2397481aed725 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/32896 Reviewed-by: Patrick Georgi Tested-by: build bot (Jenkins) --- src/northbridge/intel/x4x/early_init.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/src/northbridge/intel/x4x/early_init.c b/src/northbridge/intel/x4x/early_init.c index d019ffd7f5..a58f2ba6e9 100644 --- a/src/northbridge/intel/x4x/early_init.c +++ b/src/northbridge/intel/x4x/early_init.c @@ -150,7 +150,6 @@ static void init_egress(void) static void init_dmi(void) { u32 reg32; - u16 reg16; /* Assume IGD present */ @@ -224,9 +223,11 @@ static void init_dmi(void) /* ASPM on DMI link */ RCBA16(0x1a8) &= ~0x3; - reg16 = RCBA16(0x1a8); + /* FIXME: Do we need to read RCBA16(0x1a8)? */ + RCBA16(0x1a8); RCBA32(0x2010) = (RCBA32(0x2010) & ~(0x3 << 10)) | (1 << 10); - reg32 = RCBA32(0x2010); + /* FIXME: Do we need to read RCBA32(0x2010)? */ + RCBA32(0x2010); /* Set up VC1 max time */ RCBA32(0x1c) = (RCBA32(0x1c) & ~0x7f0000) | 0x120000; @@ -240,7 +241,8 @@ static void init_dmi(void) DMIBAR16(0x210) = (DMIBAR16(0x210) & ~(0xff7)) | 0x101; DMIBAR32(0x88) &= ~0x3; DMIBAR32(0x88) |= 0x3; - reg16 = DMIBAR16(0x88); + /* FIXME: Do we need to read RCBA16(0x88)? */ + DMIBAR16(0x88); } static void x4x_prepare_resume(int s3resume) From f00d37342c7fcabd9760ac69976227752e5c96f1 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Mon, 20 May 2019 18:52:58 +0200 Subject: [PATCH 158/331] nb/intel/pineview/early_init.c: Remove variable set but not used Change-Id: If9ca551794a52e47a3649b126c3f061a68c494e4 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/32897 Reviewed-by: Patrick Georgi Tested-by: build bot (Jenkins) --- src/northbridge/intel/pineview/early_init.c | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/src/northbridge/intel/pineview/early_init.c b/src/northbridge/intel/pineview/early_init.c index a0d5305255..509ab4ee0c 100644 --- a/src/northbridge/intel/pineview/early_init.c +++ b/src/northbridge/intel/pineview/early_init.c @@ -119,9 +119,7 @@ static void early_graphics_setup(void) static void early_misc_setup(void) { - u32 reg32; - - reg32 = MCHBAR32(0x30); + MCHBAR32(0x30); MCHBAR32(0x30) = 0x21800; DMIBAR32(0x2c) = 0x86000040; pci_write_config32(PCI_DEV(0, 0x1e, 0), 0x18, 0x00020200); @@ -129,9 +127,9 @@ static void early_misc_setup(void) early_graphics_setup(); - reg32 = MCHBAR32(0x40); + MCHBAR32(0x40); MCHBAR32(0x40) = 0x0; - reg32 = MCHBAR32(0x40); + MCHBAR32(0x40); MCHBAR32(0x40) = 0x8; pci_write_config8(LPC, 0x8, 0x1d); From 83339ab3ebcf1e0b8e4cbcd44c13d93049e161b6 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Mon, 20 May 2019 18:59:28 +0200 Subject: [PATCH 159/331] soc/intel/fsp_broadwell_de/romstage: Remove variable set but not used Change-Id: I3e304b9b19978c4100ef3486088d809c2a7fe1d7 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/32898 Reviewed-by: Patrick Rudolph Tested-by: build bot (Jenkins) --- src/soc/intel/fsp_broadwell_de/romstage/romstage.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/src/soc/intel/fsp_broadwell_de/romstage/romstage.c b/src/soc/intel/fsp_broadwell_de/romstage/romstage.c index 121cb25d61..38cd9476c5 100644 --- a/src/soc/intel/fsp_broadwell_de/romstage/romstage.c +++ b/src/soc/intel/fsp_broadwell_de/romstage/romstage.c @@ -94,7 +94,6 @@ void *asmlinkage main(FSP_INFO_HEADER *fsp_info_header) */ void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr) { - int cbmem_was_initted; void *cbmem_hob_ptr; post_code(0x4a); @@ -113,7 +112,7 @@ void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr) late_mainboard_romstage_entry(); post_code(0x4d); - cbmem_was_initted = !cbmem_recovery(0); + cbmem_recovery(0); /* Save the HOB pointer in CBMEM to be used in ramstage*/ cbmem_hob_ptr = cbmem_add(CBMEM_ID_HOB_POINTER, sizeof(*hob_list_ptr)); From 0e0c7a3dd8f93b50d4ff494639b5e2ff45ffaeaa Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Mon, 20 May 2019 19:04:09 +0200 Subject: [PATCH 160/331] soc/intel/fsp_baytrail/romstage: Remove variable set but not used Change-Id: Ic04cb7c51862bea4d01f853ee2c88cc03c414e35 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/32899 Reviewed-by: Patrick Georgi Tested-by: build bot (Jenkins) --- src/soc/intel/fsp_baytrail/romstage/romstage.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/src/soc/intel/fsp_baytrail/romstage/romstage.c b/src/soc/intel/fsp_baytrail/romstage/romstage.c index 030b5dfeed..52f4dc9d63 100644 --- a/src/soc/intel/fsp_baytrail/romstage/romstage.c +++ b/src/soc/intel/fsp_baytrail/romstage/romstage.c @@ -218,7 +218,6 @@ void main(FSP_INFO_HEADER *fsp_info_header) */ void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr) { - int cbmem_was_initted; void *cbmem_hob_ptr; uint32_t prev_sleep_state; @@ -245,7 +244,7 @@ void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr) late_mainboard_romstage_entry(); post_code(0x4c); - cbmem_was_initted = !cbmem_recovery(prev_sleep_state == ACPI_S3); + cbmem_recovery(prev_sleep_state == ACPI_S3); /* Save the HOB pointer in CBMEM to be used in ramstage*/ cbmem_hob_ptr = cbmem_add(CBMEM_ID_HOB_POINTER, sizeof(*hob_list_ptr)); From 7687617d0020b0a234d8d299a9d31ec363512436 Mon Sep 17 00:00:00 2001 From: Evgeny Zinoviev Date: Wed, 8 May 2019 13:29:03 +0300 Subject: [PATCH 161/331] util/autoport: Mention i2c-i801 module in readme.md SMBus adapter will not appear if i2c-i801 module is not loaded. Added it to the readme. Change-Id: I3de0e02f13178d78b8cc02a74a745ad66e929070 Signed-off-by: Evgeny Zinoviev Reviewed-on: https://review.coreboot.org/c/coreboot/+/32681 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph --- util/autoport/readme.md | 1 + 1 file changed, 1 insertion(+) diff --git a/util/autoport/readme.md b/util/autoport/readme.md index 4683d8dd10..cfa8c36a38 100644 --- a/util/autoport/readme.md +++ b/util/autoport/readme.md @@ -120,6 +120,7 @@ on the vendor firmware with just one module in channel 0, slot 0, and check the the EEPROM has. Under Linux, you can use these commands to see what is on SMBus: $ sudo modprobe i2c-dev + $ sudo modprobe i2c-i801 $ sudo i2cdetect -l i2c-0 i2c i915 gmbus ssc I2C adapter i2c-1 i2c i915 gmbus vga I2C adapter From 55fffa29c236f054c6b40fb971f7974f2dbd705d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Sun, 10 Jun 2018 05:18:50 +0300 Subject: [PATCH 162/331] AGESA binaryPI: Sync STRUCT_NAME definitions MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit While not implemented, copying the definitions from later AGESA/AMD.h to older helps us avoid lots of preprocessor directives. Change-Id: I34edc1ca23e9c063c4286273c53249ff0a953798 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/31510 Reviewed-by: Marshall Dawson Tested-by: build bot (Jenkins) --- src/drivers/amd/agesa/eventlog.c | 3 ++- src/vendorcode/amd/agesa/f12/AMD.h | 5 ++++- src/vendorcode/amd/agesa/f14/AMD.h | 5 ++++- src/vendorcode/amd/agesa/f15tn/AMD.h | 5 ++++- src/vendorcode/amd/agesa/f16kb/AMD.h | 4 +++- src/vendorcode/amd/pi/00630F01/AMD.h | 2 ++ src/vendorcode/amd/pi/00660F01/AMD.h | 9 +++++++++ src/vendorcode/amd/pi/00730F01/AMD.h | 3 +++ 8 files changed, 31 insertions(+), 5 deletions(-) diff --git a/src/drivers/amd/agesa/eventlog.c b/src/drivers/amd/agesa/eventlog.c index 6cfcde520b..23e31ba7d3 100644 --- a/src/drivers/amd/agesa/eventlog.c +++ b/src/drivers/amd/agesa/eventlog.c @@ -29,8 +29,9 @@ static const char undefined[] = "undefined"; static const char *AgesaFunctionNameStr[] = { "AmdInitRecovery", "AmdCreateStruct", "AmdInitEarly", "AmdInitEnv", "AmdInitLate", "AmdInitMid", "AmdInitPost", "AmdInitReset", "AmdInitResume", "AmdReleaseStruct", - "AmdS3LateRestore","AmdS3Save", "AmdGetApicId", "AmdGetPciAddress", "AmdIdentifyCore", + "AmdS3LateRestore", "AmdS3Save", "AmdGetApicId", "AmdGetPciAddress", "AmdIdentifyCore", "AmdReadEventLog", "AmdGetAvailableExeCacheSize", "AmdLateRunApTask", "AmdIdentifyDimm", + "Amd2dDataEye", "AmdS3FinalRestore", "AmdInitRtb" }; /* heapManager.h */ diff --git a/src/vendorcode/amd/agesa/f12/AMD.h b/src/vendorcode/amd/agesa/f12/AMD.h index 179c3f5da0..31c0b347a0 100644 --- a/src/vendorcode/amd/agesa/f12/AMD.h +++ b/src/vendorcode/amd/agesa/f12/AMD.h @@ -148,7 +148,10 @@ typedef enum { AMD_READ_EVENT_LOG, ///< AmdReadEventLog general service handle AMD_GET_EXECACHE_SIZE, ///< AmdGetAvailableExeCacheSize general service handle AMD_LATE_RUN_AP_TASK, ///< AmdLateRunApTask entry point handle - AMD_IDENTIFY_DIMMS ///< AmdIdentifyDimm general service handle + AMD_IDENTIFY_DIMMS, ///< AmdIdentifyDimm general service handle + AMD_GET_2D_DATA_EYE, ///< AmdGet2DDataEye general service handle + AMD_S3FINAL_RESTORE, ///< AmdS3FinalRestore entry point handle + AMD_INIT_RTB ///< AmdInitRtb entry point handle } AGESA_STRUCT_NAME; /* ResetType constant values */ diff --git a/src/vendorcode/amd/agesa/f14/AMD.h b/src/vendorcode/amd/agesa/f14/AMD.h index 9d443beb1e..c1cfaa1f32 100644 --- a/src/vendorcode/amd/agesa/f14/AMD.h +++ b/src/vendorcode/amd/agesa/f14/AMD.h @@ -147,7 +147,10 @@ typedef enum { AMD_READ_EVENT_LOG, ///< AmdReadEventLog general service handle AMD_GET_EXECACHE_SIZE, ///< AmdGetAvailableExeCacheSize general service handle AMD_LATE_RUN_AP_TASK, ///< AmdLateRunApTask entry point handle - AMD_IDENTIFY_DIMMS ///< AmdIdentifyDimm general service handle + AMD_IDENTIFY_DIMMS, ///< AmdIdentifyDimm general service handle + AMD_GET_2D_DATA_EYE, ///< AmdGet2DDataEye general service handle + AMD_S3FINAL_RESTORE, ///< AmdS3FinalRestore entry point handle + AMD_INIT_RTB ///< AmdInitRtb entry point handle } AGESA_STRUCT_NAME; /* ResetType constant values */ diff --git a/src/vendorcode/amd/agesa/f15tn/AMD.h b/src/vendorcode/amd/agesa/f15tn/AMD.h index 31d38db556..27326ecef8 100644 --- a/src/vendorcode/amd/agesa/f15tn/AMD.h +++ b/src/vendorcode/amd/agesa/f15tn/AMD.h @@ -144,7 +144,10 @@ typedef enum { AMD_READ_EVENT_LOG, ///< AmdReadEventLog general service handle AMD_GET_EXECACHE_SIZE, ///< AmdGetAvailableExeCacheSize general service handle AMD_LATE_RUN_AP_TASK, ///< AmdLateRunApTask entry point handle - AMD_IDENTIFY_DIMMS ///< AmdIdentifyDimm general service handle + AMD_IDENTIFY_DIMMS, ///< AmdIdentifyDimm general service handle + AMD_GET_2D_DATA_EYE, ///< AmdGet2DDataEye general service handle + AMD_S3FINAL_RESTORE, ///< AmdS3FinalRestore entry point handle + AMD_INIT_RTB ///< AmdInitRtb entry point handle } AGESA_STRUCT_NAME; /* ResetType constant values */ diff --git a/src/vendorcode/amd/agesa/f16kb/AMD.h b/src/vendorcode/amd/agesa/f16kb/AMD.h index bfce993bce..83d538f3e2 100644 --- a/src/vendorcode/amd/agesa/f16kb/AMD.h +++ b/src/vendorcode/amd/agesa/f16kb/AMD.h @@ -143,7 +143,9 @@ typedef enum { AMD_GET_EXECACHE_SIZE, ///< AmdGetAvailableExeCacheSize general service handle AMD_LATE_RUN_AP_TASK, ///< AmdLateRunApTask entry point handle AMD_IDENTIFY_DIMMS, ///< AmdIdentifyDimm general service handle - AMD_GET_2D_DATA_EYE ///< AmdGet2DDataEye general service handle + AMD_GET_2D_DATA_EYE, ///< AmdGet2DDataEye general service handle + AMD_S3FINAL_RESTORE, ///< AmdS3FinalRestore entry point handle + AMD_INIT_RTB ///< AmdInitRtb entry point handle } AGESA_STRUCT_NAME; /* ResetType constant values */ diff --git a/src/vendorcode/amd/pi/00630F01/AMD.h b/src/vendorcode/amd/pi/00630F01/AMD.h index 68f7c32818..f70b128508 100644 --- a/src/vendorcode/amd/pi/00630F01/AMD.h +++ b/src/vendorcode/amd/pi/00630F01/AMD.h @@ -149,6 +149,8 @@ typedef enum { AMD_IDENTIFY_DIMMS = 0x00033000, ///< AmdIdentifyDimm general service handle AMD_GET_2D_DATA_EYE = 0x00034000, ///< AmdGet2DDataEye general service handle AMD_S3FINAL_RESTORE = 0x00035000, ///< AmdS3FinalRestore entry point handle + AMD_INIT_RTB = 0x00036000, /* reserved */ + AMD_HEAP_ALLOCATE_BUFFER = 0x00038000, AMD_HEAP_DEALLOCATE_BUFFER = 0x00039000, FCH_INIT_RESET = 0x00040000, diff --git a/src/vendorcode/amd/pi/00660F01/AMD.h b/src/vendorcode/amd/pi/00660F01/AMD.h index aa68204e8d..54abf80af0 100644 --- a/src/vendorcode/amd/pi/00660F01/AMD.h +++ b/src/vendorcode/amd/pi/00660F01/AMD.h @@ -126,6 +126,11 @@ typedef enum ACCESS_WIDTH { AccessS3SaveWidth64, ///< Save 64 bits data. } ACCESS_WIDTH; +/* When AMD rolled out CarrizoPI, they made a bad choice of removing + * an entry from the middle of the enumeration list. + */ +#define AMD_S3_SAVE_REMOVED + /// AGESA struct name typedef enum { // AGESA BASIC FUNCTIONS @@ -140,6 +145,10 @@ typedef enum { AMD_INIT_RESUME = 0x00029000, ///< AmdInitResume entry point handle AMD_RELEASE_STRUCT = 0x0002A000, ///< AmdReleaseStruct handle AMD_S3LATE_RESTORE = 0x0002B000, ///< AmdS3LateRestore entry point handle +#if 0 + /* This was removed, shifting everything else up.*/ + AMD_S3_SAVE = 0x0002C000, +#endif AMD_GET_APIC_ID = 0x0002C000, ///< AmdGetApicId entry point handle AMD_GET_PCI_ADDRESS = 0x0002D000, ///< AmdGetPciAddress entry point handle AMD_IDENTIFY_CORE = 0x0002E000, ///< AmdIdentifyCore general service handle diff --git a/src/vendorcode/amd/pi/00730F01/AMD.h b/src/vendorcode/amd/pi/00730F01/AMD.h index 1b6fdb26e8..13fc29afeb 100644 --- a/src/vendorcode/amd/pi/00730F01/AMD.h +++ b/src/vendorcode/amd/pi/00730F01/AMD.h @@ -148,6 +148,9 @@ typedef enum { AMD_LATE_RUN_AP_TASK = 0x00032000, ///< AmdLateRunApTask entry point handle AMD_IDENTIFY_DIMMS = 0x00033000, ///< AmdIdentifyDimm general service handle AMD_GET_2D_DATA_EYE = 0x00034000, ///< AmdGet2DDataEye general service handle + AMD_S3FINAL_RESTORE = 0x00035000, /* reserved */ + AMD_INIT_RTB = 0x00036000, /* reserved */ + AMD_HEAP_ALLOCATE_BUFFER = 0x00038000, AMD_HEAP_DEALLOCATE_BUFFER = 0x00039000, FCH_INIT_RESET = 0x00040000, From b4222a65adcbacdb056fea88abd300c897eabfc2 Mon Sep 17 00:00:00 2001 From: Jacob Garber Date: Tue, 21 May 2019 13:41:50 -0600 Subject: [PATCH 163/331] util/romcc: Add extra NULL checks for member In each of these cases it is possible that 'member' is NULL at the beginning, which will skip the earlier while loops entirely and cause a NULL dereference later on. Add extra error checks to prevent this. Change-Id: Ib5873c0830b71397ef661976d387fc6ce33c5cd1 Signed-off-by: Jacob Garber Found-by: Coverity CID 1129147, 1129152, 1129153, 1129154 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32916 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- util/romcc/romcc.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/util/romcc/romcc.c b/util/romcc/romcc.c index 329cfd2433..571a29f94b 100644 --- a/util/romcc/romcc.c +++ b/util/romcc/romcc.c @@ -6228,6 +6228,8 @@ static size_t field_offset(struct compile_state *state, size += size_of(state, member->left); member = member->right; } + if (member == NULL) + internal_error(state, 0, "Member is NULL"); size += needed_padding(state, member, size); } else if ((type->type & TYPE_MASK) == TYPE_UNION) { @@ -6350,10 +6352,12 @@ static size_t index_offset(struct compile_state *state, i++; member = member->right; } - size += needed_padding(state, member, size); + if (member == NULL) + internal_error(state, 0, "Member is NULL"); if (i != index) { internal_error(state, 0, "Missing member index: %u", index); } + size += needed_padding(state, member, size); } else if ((type->type & TYPE_MASK) == TYPE_JOIN) { ulong_t i; @@ -6402,6 +6406,8 @@ static size_t index_reg_offset(struct compile_state *state, i++; member = member->right; } + if (member == NULL) + internal_error(state, 0, "Member is NULL"); if (i != index) { internal_error(state, 0, "Missing member index: %u", index); } @@ -6640,6 +6646,8 @@ static struct type *reg_type( offset += size; member = member->right; } + if (member == NULL) + internal_error(state, 0, "Member is NULL"); offset += reg_needed_padding(state, member, offset); member = reg_type(state, member, reg_offset - offset); break; From 4b688ab3fe6a8db4985a6e6cdad5def661f4066a Mon Sep 17 00:00:00 2001 From: Jacob Garber Date: Tue, 21 May 2019 18:55:34 -0600 Subject: [PATCH 164/331] util/romcc: Add null check for filename It is possible that 'filename' is still null in this if statement, so we add an extra check to prevent a null dereference in strcmp. Change-Id: Iaba95b63a4d552051e0c56445522de7274dfd0b3 Signed-off-by: Jacob Garber Found-by: Coverity CID 1395330 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32922 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- util/romcc/romcc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/util/romcc/romcc.c b/util/romcc/romcc.c index 571a29f94b..285b0237f4 100644 --- a/util/romcc/romcc.c +++ b/util/romcc/romcc.c @@ -1989,7 +1989,7 @@ static struct occurrence *new_occurrence(struct compile_state *state) (last->line == line) && (last->function == function) && ((last->filename == filename) || - (strcmp(last->filename, filename) == 0))) + (filename != NULL && strcmp(last->filename, filename) == 0))) { get_occurrence(last); return last; From 9742ae1d11dab3357835fab7d7e3577dde4e0480 Mon Sep 17 00:00:00 2001 From: Jacob Garber Date: Thu, 16 May 2019 22:27:45 -0600 Subject: [PATCH 165/331] util/romcc: Fix memory leak The 'new_type' function already allocates memory, so it is only necessary to clone the existing type if this function is not called. Change-Id: I47065204c5f4b6bab022bd7ccf19838c3ce1f86e Signed-off-by: Jacob Garber Found-by: Coverity Scan CID 1129106 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32921 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- util/romcc/romcc.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/util/romcc/romcc.c b/util/romcc/romcc.c index 285b0237f4..d60a9a7f83 100644 --- a/util/romcc/romcc.c +++ b/util/romcc/romcc.c @@ -12601,7 +12601,9 @@ static struct type *struct_declarator( } type = new_type(TYPE_BITFIELD, type, 0); type->elements = value->u.cval; - } + } else + type = clone_type(0, type); + return type; } @@ -12656,7 +12658,6 @@ static struct type *struct_or_union_specifier( done = 0; eat(state, TOK_COMMA); } - type = clone_type(0, type); type->field_ident = fident; if (*next) { *next = new_type(type_join, *next, type); From 298afb3140fa8f092b356ec89d8be2f5a36b530f Mon Sep 17 00:00:00 2001 From: Jacob Garber Date: Tue, 21 May 2019 14:42:24 -0600 Subject: [PATCH 166/331] util/romcc: Add extra null pointer check It is possible that 'lnode->val' is set to 0 on a previous iteration of the loop, so check that it is non-null here before dereferencing it. Change-Id: I9827dd5623eaf11240df605a8b50ff9e27a5fce0 Signed-off-by: Jacob Garber Found-by: Coverity CID 1129149 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32917 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- util/romcc/romcc.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/util/romcc/romcc.c b/util/romcc/romcc.c index d60a9a7f83..2a158e5fe0 100644 --- a/util/romcc/romcc.c +++ b/util/romcc/romcc.c @@ -20944,7 +20944,8 @@ static void scc_visit_phi(struct compile_state *state, struct scc_state *scc, } } /* meet(const, const) = const or lattice low */ - else if (!constants_equal(state, lnode->val, tmp->val)) { + else if (lnode->val != 0 && + !constants_equal(state, lnode->val, tmp->val)) { lnode->val = 0; } From c72dc05acc12c65614079bd0de25809b80456141 Mon Sep 17 00:00:00 2001 From: Evan Green Date: Tue, 21 May 2019 15:39:00 -0700 Subject: [PATCH 167/331] mb/google/hatch/variants: Fix DPTF sensor IDs There are indeed two temperature sensors hooked up to the EC, but they are indexed as 0 and 1, not 1 and 2. BUG=b:132999028 TEST=Boot hatch with hardened EC, observe no more index overflows Change-Id: Ia7f503bc1dc941635db52fce40f217bf34da6d2b Signed-off-by: Evan Green Reviewed-on: https://review.coreboot.org/c/coreboot/+/32920 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh Reviewed-by: Paul Menzel --- .../hatch/variants/baseboard/include/baseboard/acpi/dptf.asl | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mainboard/google/hatch/variants/baseboard/include/baseboard/acpi/dptf.asl b/src/mainboard/google/hatch/variants/baseboard/include/baseboard/acpi/dptf.asl index 1384ccfeb7..ff7db49334 100644 --- a/src/mainboard/google/hatch/variants/baseboard/include/baseboard/acpi/dptf.asl +++ b/src/mainboard/google/hatch/variants/baseboard/include/baseboard/acpi/dptf.asl @@ -21,7 +21,7 @@ #define DPTF_CPU_ACTIVE_AC3 80 #define DPTF_CPU_ACTIVE_AC4 75 -#define DPTF_TSR0_SENSOR_ID 1 +#define DPTF_TSR0_SENSOR_ID 0 #define DPTF_TSR0_SENSOR_NAME "Thermal Sensor 1" #define DPTF_TSR0_PASSIVE 65 #define DPTF_TSR0_CRITICAL 75 @@ -31,7 +31,7 @@ #define DPTF_TSR0_ACTIVE_AC3 42 #define DPTF_TSR0_ACTIVE_AC4 39 -#define DPTF_TSR1_SENSOR_ID 2 +#define DPTF_TSR1_SENSOR_ID 1 #define DPTF_TSR1_SENSOR_NAME "Thermal Sensor 2" #define DPTF_TSR1_PASSIVE 65 #define DPTF_TSR1_CRITICAL 75 From b7fe7a1a8e033706f39c0fded5901f0f1dce7cfb Mon Sep 17 00:00:00 2001 From: Bora Guvendik Date: Thu, 8 Mar 2018 16:32:43 -0800 Subject: [PATCH 168/331] intel/common/block/scs: Add ability to send early CMD0, CMD1 In order to improve boot time with emmc, add ability to send CMD0 and CMD1 early in romstage. This way, by the time system boots to payload, we are ready to continue with emmc setup and we don't need to send CMD0 in payload again, and wait for card to reset and be ready. BUG=b:78106689 TESTS = Boot to OS Force early_mmc_wake_hw() to return error, recover in payload Force an error in payload, make sure system can recover/boot Change-Id: I3488b077bf5100a1e0f2c879fb1436105607d25e Signed-off-by: Bora Guvendik Reviewed-on: https://review.coreboot.org/c/coreboot/+/25068 Tested-by: build bot (Jenkins) Reviewed-by: Lijian Zhao --- src/commonlib/include/commonlib/cbmem_id.h | 2 + .../block/include/intelblocks/early_mmc.h | 80 +++++++++ src/soc/intel/common/block/scs/Kconfig | 10 ++ src/soc/intel/common/block/scs/Makefile.inc | 1 + src/soc/intel/common/block/scs/early_mmc.c | 166 ++++++++++++++++++ 5 files changed, 259 insertions(+) create mode 100644 src/soc/intel/common/block/include/intelblocks/early_mmc.h create mode 100644 src/soc/intel/common/block/scs/early_mmc.c diff --git a/src/commonlib/include/commonlib/cbmem_id.h b/src/commonlib/include/commonlib/cbmem_id.h index af79a59075..535ba3394c 100644 --- a/src/commonlib/include/commonlib/cbmem_id.h +++ b/src/commonlib/include/commonlib/cbmem_id.h @@ -39,6 +39,7 @@ #define CBMEM_ID_IMD_SMALL 0x53a11439 #define CBMEM_ID_MEMINFO 0x494D454D #define CBMEM_ID_MMA_DATA 0x4D4D4144 +#define CBMEM_ID_MMC_STATUS 0x4d4d4353 #define CBMEM_ID_MPTABLE 0x534d5054 #define CBMEM_ID_MRCDATA 0x4d524344 #define CBMEM_ID_VAR_MRCDATA 0x4d524345 @@ -100,6 +101,7 @@ { CBMEM_ID_IMD_SMALL, "IMD SMALL " }, \ { CBMEM_ID_MEMINFO, "MEM INFO " }, \ { CBMEM_ID_MMA_DATA, "MMA DATA " }, \ + { CBMEM_ID_MMC_STATUS, "MMC STATUS " }, \ { CBMEM_ID_MPTABLE, "SMP TABLE " }, \ { CBMEM_ID_MRCDATA, "MRC DATA " }, \ { CBMEM_ID_VAR_MRCDATA, "VARMRC DATA" }, \ diff --git a/src/soc/intel/common/block/include/intelblocks/early_mmc.h b/src/soc/intel/common/block/include/intelblocks/early_mmc.h new file mode 100644 index 0000000000..69be40cf27 --- /dev/null +++ b/src/soc/intel/common/block/include/intelblocks/early_mmc.h @@ -0,0 +1,80 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SOC_INTEL_COMMON_BLOCK_EARLY_MMC_H +#define SOC_INTEL_COMMON_BLOCK_EARLY_MMC_H + +#include + +/* + * Following should be defined in soc/iomap.h + * PRERAM_MMC_BASE_ADDRESS - Provide an address to setup emmc controller's + PCI BAR. + */ + +/* + * Structure for the following delay registers + * emmc_tx_data_cntl1: Tx Delay Control 1 (Tx_DATA_dly_1)-Offset 824h + * emmc_tx_data_cntl2: Tx Delay Control 2 (Tx_DATA_dly_2)-Offset 828h + * emmc_rx_cmd_data_cntl1: Rx CMD Data Delay Control 1 + * (Rx_CMD_Data_dly_1)-Offset 82Ch + * emmc_rx_cmd_data_cntl2: Rx CMD Data Path Delay Control 2 + * (Rx_CMD_Data_dly_2)-Offset 834h + * emmc_rx_strobe_cntl: Rx Strobe Delay Control + * (Rx_Strobe_Ctrl_Path)-Offset 830h + * emmc_tx_cmd_cntl: Tx CMD Delay Control (Tx_CMD_dly)-Offset 820h + */ +struct mmc_dll_params { + uint32_t emmc_tx_data_cntl1; + uint32_t emmc_tx_data_cntl2; + uint32_t emmc_rx_cmd_data_cntl1; + uint32_t emmc_rx_cmd_data_cntl2; + uint32_t emmc_rx_strobe_cntl; + uint32_t emmc_tx_cmd_cntl; +}; + +/* + * SOC specific API to get mmc min max frequencies. + * returns 0, if able to get f_min, f_max; otherwise returns -1 + */ +int soc_get_mmc_frequencies(uint32_t *f_min, uint32_t *f_max); +/* + * SOC specific API to configure mmc gpios. + * returns 0, if able to configure gpios; otherwise returns -1 + */ +int soc_configure_mmc_gpios(void); +/* + * SOC specific API to get mmc delay register settings. + * returns 0, if able to get register settings; otherwise returns -1 + */ +int soc_get_mmc_dll(struct mmc_dll_params *params); + +#if IS_ENABLED(CONFIG_SOC_INTEL_COMMON_EARLY_MMC_WAKE) +/* + * Initializes sdhci / mmc controller and sends CMD0, CMD1 to emmc card. + * In case of success: It returns 0 and adds cbmem entry CBMEM_ID_MMC_STATUS + * and sets it to 1. Payload can start by sending CMD1, there is no need to + * send CMD0 and wait for the card to be ready. + * In case of failure: It returns -1 and doesn't add cbmem entry. Payload + * should do complete initialization starting with CMD0. + */ +int early_mmc_wake_hw(void); +#else +static inline int early_mmc_wake_hw(void) +{ + return -1; +} +#endif /* CONFIG_SOC_INTEL_COMMON_EARLY_MMC_WAKE */ +#endif /* SOC_INTEL_COMMON_BLOCK_EARLY_MMC_H */ diff --git a/src/soc/intel/common/block/scs/Kconfig b/src/soc/intel/common/block/scs/Kconfig index 0a402137bc..06ad8e4fa8 100644 --- a/src/soc/intel/common/block/scs/Kconfig +++ b/src/soc/intel/common/block/scs/Kconfig @@ -2,3 +2,13 @@ config SOC_INTEL_COMMON_BLOCK_SCS bool help Intel Processor common storage and communication subsystem support + +config SOC_INTEL_COMMON_EARLY_MMC_WAKE + bool + default n + select COMMONLIB_STORAGE + select COMMONLIB_STORAGE_MMC + select SDHCI_CONTROLLER + help + Send CMD1 early in romstage to improve boot time. It requires emmc + DLL tuning parameters to be added to devicetree.cb diff --git a/src/soc/intel/common/block/scs/Makefile.inc b/src/soc/intel/common/block/scs/Makefile.inc index 1c2a6c6692..1160802d03 100644 --- a/src/soc/intel/common/block/scs/Makefile.inc +++ b/src/soc/intel/common/block/scs/Makefile.inc @@ -1 +1,2 @@ ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SCS) += sd.c +romstage-$(CONFIG_SOC_INTEL_COMMON_EARLY_MMC_WAKE) += early_mmc.c diff --git a/src/soc/intel/common/block/scs/early_mmc.c b/src/soc/intel/common/block/scs/early_mmc.c new file mode 100644 index 0000000000..4b15bb48bb --- /dev/null +++ b/src/soc/intel/common/block/scs/early_mmc.c @@ -0,0 +1,166 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define EMMC_TX_CMD_CNTL_OFFSET 0x820 +#define EMMC_TX_DATA_CNTL1_OFFSET 0x824 +#define EMMC_TX_DATA_CNTL2_OFFSET 0x828 +#define EMMC_RX_CMD_DATA_CNTL1_OFFSET 0x82C +#define EMMC_RX_STROBE_CNTL_OFFSET 0x830 +#define EMMC_RX_CMD_DATA_CNTL2_OFFSET 0x834 + +void soc_sd_mmc_controller_quirks(struct sd_mmc_ctrlr *ctrlr) +{ + uint32_t f_min, f_max; + + if (soc_get_mmc_frequencies(&f_min, &f_max) < 0) { + printk(BIOS_ERR, + "MMC early init: failed to get mmc frequencies\n"); + return; + } + + ctrlr->f_min = f_min; + ctrlr->f_max = f_max; +} + +static void enable_mmc_controller_bar(void) +{ + pci_write_config32(PCH_DEV_EMMC, PCI_BASE_ADDRESS_0, + PRERAM_MMC_BASE_ADDRESS); + pci_write_config32(PCH_DEV_EMMC, PCI_COMMAND, + PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); +} + +static void disable_mmc_controller_bar(void) +{ + pci_write_config32(PCH_DEV_EMMC, PCI_BASE_ADDRESS_0, 0); + pci_write_config32(PCH_DEV_EMMC, PCI_COMMAND, + ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY)); +} + +static int set_mmc_dll(void *ioaddr) +{ + struct mmc_dll_params dll_params; + + if (soc_get_mmc_dll(&dll_params) < 0) { + printk(BIOS_ERR, + "MMC early init: failed to get mmc DLL parameters\n"); + return -1; + } + + write32(ioaddr + EMMC_TX_DATA_CNTL1_OFFSET, + dll_params.emmc_tx_data_cntl1); + write32(ioaddr + EMMC_TX_DATA_CNTL2_OFFSET, + dll_params.emmc_tx_data_cntl2); + write32(ioaddr + EMMC_RX_CMD_DATA_CNTL1_OFFSET, + dll_params.emmc_rx_cmd_data_cntl1); + write32(ioaddr + EMMC_RX_CMD_DATA_CNTL2_OFFSET, + dll_params.emmc_rx_cmd_data_cntl2); + write32(ioaddr + EMMC_RX_STROBE_CNTL_OFFSET, + dll_params.emmc_rx_strobe_cntl); + write32(ioaddr + EMMC_TX_CMD_CNTL_OFFSET, + dll_params.emmc_tx_cmd_cntl); + + return 0; +} + +static void set_early_mmc_wake_status(int32_t status) +{ + int32_t *ms_cbmem; + + ms_cbmem = cbmem_add(CBMEM_ID_MMC_STATUS, sizeof(int)); + + if (ms_cbmem == NULL) { + printk(BIOS_ERR, + "%s: Failed to add early mmc wake status to cbmem!\n", + __func__); + return; + } + + *ms_cbmem = status; +} + +int early_mmc_wake_hw(void) +{ + struct storage_media media; + struct sd_mmc_ctrlr *mmc_ctrlr; + struct sdhci_ctrlr *sdhci_ctrlr; + int err; + + if (acpi_is_wakeup_s3()) + return -1; + + /* Configure mmc gpios */ + if (soc_configure_mmc_gpios() < 0) { + printk(BIOS_ERR, + "%s: MMC early init: failed to configure mmc gpios\n", + __func__); + return -1; + } + /* Setup pci bar */ + enable_mmc_controller_bar(); + + /* Initialize sdhci */ + mmc_ctrlr = new_pci_sdhci_controller(PCH_DEV_EMMC); + if (mmc_ctrlr == NULL) + goto out_err; + + sdhci_ctrlr = container_of(mmc_ctrlr, struct sdhci_ctrlr, sd_mmc_ctrlr); + + /* set emmc DLL tuning parameters */ + if (set_mmc_dll(sdhci_ctrlr->ioaddr) < 0) + goto out_err; + + memset(&media, 0, sizeof(media)); + media.ctrlr = mmc_ctrlr; + SET_BUS_WIDTH(mmc_ctrlr, 1); + /* + * Set clock to 1 so that the driver can choose minimum frequency + * possible + */ + SET_CLOCK(mmc_ctrlr, 1); + + /* Reset emmc, send CMD0 */ + if (sd_mmc_go_idle(&media)) + goto out_err; + + /* Send CMD1 */ + err = mmc_send_op_cond(&media); + if (err != 0 && err != CARD_IN_PROGRESS) + goto out_err; + + disable_mmc_controller_bar(); + + set_early_mmc_wake_status(1); + return 0; + +out_err: + + disable_mmc_controller_bar(); + return -1; +} From ddf2bc5081e0eafc33af40a06f4217c5c851fa3f Mon Sep 17 00:00:00 2001 From: Bora Guvendik Date: Fri, 30 Mar 2018 16:03:32 -0700 Subject: [PATCH 169/331] coreboot_tables: pass the early_mmc_wake_hw status to payload Pass the return value from early_mmc_wake_hw() to the payload so that payload can skip sending CMD0 and resetting the card in case of success or in case of a failure in firmware, payload can recover by sending CMD0 and resetting the card. BUG=b:78106689 TEST=Boot to OS Change-Id: Ia4c57d05433c3966118c3642913d7017958cce55 Signed-off-by: Bora Guvendik Reviewed-on: https://review.coreboot.org/c/coreboot/+/25464 Reviewed-by: Lijian Zhao Tested-by: build bot (Jenkins) --- payloads/libpayload/include/coreboot_tables.h | 15 +++++++++++++++ payloads/libpayload/include/sysinfo.h | 1 + payloads/libpayload/libc/coreboot.c | 10 ++++++++++ .../include/commonlib/coreboot_tables.h | 15 +++++++++++++++ src/lib/coreboot_table.c | 19 +++++++++++++++++++ 5 files changed, 60 insertions(+) diff --git a/payloads/libpayload/include/coreboot_tables.h b/payloads/libpayload/include/coreboot_tables.h index 92e3f26180..705e348666 100644 --- a/payloads/libpayload/include/coreboot_tables.h +++ b/payloads/libpayload/include/coreboot_tables.h @@ -287,6 +287,21 @@ struct cb_macs { struct mac_address mac_addrs[0]; }; +#define CB_TAG_MMC_INFO 0x0034 +struct cb_mmc_info { + uint32_t tag; + uint32_t size; + /* + * Passes the early mmc status to payload to indicate if firmware + * successfully sent CMD0, CMD1 to the card or not. In case of + * success, the payload can skip the first step of the initialization + * sequence which is to send CMD0, and instead start by sending CMD1 + * as described in Jedec Standard JESD83-B1 section 6.4.3. + * passes 1 on success + */ + int32_t early_cmd1_status; +}; + #define CB_TAG_SERIALNO 0x002a #define CB_MAX_SERIALNO_LENGTH 32 diff --git a/payloads/libpayload/include/sysinfo.h b/payloads/libpayload/include/sysinfo.h index 7e6e74809d..72059adb91 100644 --- a/payloads/libpayload/include/sysinfo.h +++ b/payloads/libpayload/include/sysinfo.h @@ -129,6 +129,7 @@ struct sysinfo_t { uint64_t mtc_start; uint32_t mtc_size; void *chromeos_vpd; + int mmc_early_wake_status; }; extern struct sysinfo_t lib_sysinfo; diff --git a/payloads/libpayload/libc/coreboot.c b/payloads/libpayload/libc/coreboot.c index 3982e47ec2..26a3a48c23 100644 --- a/payloads/libpayload/libc/coreboot.c +++ b/payloads/libpayload/libc/coreboot.c @@ -102,6 +102,13 @@ static void cb_parse_vbnv(unsigned char *ptr, struct sysinfo_t *info) info->vbnv_size = vbnv->range_size; } +static void cb_parse_mmc_info(unsigned char *ptr, struct sysinfo_t *info) +{ + struct cb_mmc_info *mmc_info = (struct cb_mmc_info *)ptr; + + info->mmc_early_wake_status = mmc_info->early_cmd1_status; +} + static void cb_parse_gpios(unsigned char *ptr, struct sysinfo_t *info) { int i; @@ -399,6 +406,9 @@ int cb_parse_header(void *addr, int len, struct sysinfo_t *info) case CB_TAG_SPI_FLASH: cb_parse_spi_flash(ptr, info); break; + case CB_TAG_MMC_INFO: + cb_parse_mmc_info(ptr, info); + break; case CB_TAG_MTC: cb_parse_mtc(ptr, info); break; diff --git a/src/commonlib/include/commonlib/coreboot_tables.h b/src/commonlib/include/commonlib/coreboot_tables.h index 198ad27b87..99ab21c724 100644 --- a/src/commonlib/include/commonlib/coreboot_tables.h +++ b/src/commonlib/include/commonlib/coreboot_tables.h @@ -385,6 +385,21 @@ struct mac_address { uint8_t pad[2]; /* Pad it to 8 bytes to keep it simple. */ }; +#define LB_TAG_MMC_INFO 0x0034 +struct lb_mmc_info { + uint32_t tag; + uint32_t size; + /* + * Passes the early mmc status to payload to indicate if firmware + * successfully sent CMD0, CMD1 to the card or not. In case of + * success, the payload can skip the first step of the initialization + * sequence which is to send CMD0, and instead start by sending CMD1 + * as described in Jedec Standard JESD83-B1 section 6.4.3. + * passes 1 on success + */ + int32_t early_cmd1_status; +}; + struct lb_macs { uint32_t tag; uint32_t size; diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index 6e44f5d3d5..14cd030202 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -321,6 +321,22 @@ static void lb_sku_id(struct lb_header *header) printk(BIOS_INFO, "SKU ID: %d\n", sid); } +static void lb_mmc_info(struct lb_header *header) +{ + struct lb_mmc_info *rec; + int32_t *ms_cbmem; + + ms_cbmem = cbmem_find(CBMEM_ID_MMC_STATUS); + if (!ms_cbmem) + return; + + rec = (struct lb_mmc_info *)lb_new_record(header); + + rec->tag = LB_TAG_MMC_INFO; + rec->size = sizeof(*rec); + rec->early_cmd1_status = *ms_cbmem; +} + static void add_cbmem_pointers(struct lb_header *header) { /* @@ -559,6 +575,9 @@ static uintptr_t write_coreboot_table(uintptr_t rom_table_end) lb_ram_code(head); lb_sku_id(head); + /* Pass mmc early init status */ + lb_mmc_info(head); + /* Add SPI flash description if available */ if (CONFIG(BOOT_DEVICE_SPI_FLASH)) lb_spi_flash(head); From 2803346b27aafb0fec2e6c949e2ab9994c754604 Mon Sep 17 00:00:00 2001 From: Patrick Georgi Date: Thu, 23 May 2019 12:14:38 +0200 Subject: [PATCH 170/331] Renumber cbtable tag MMC_INFO We got another tag in the meantime, so resolve the conflict. Change-Id: I64cb5e02a9bed3d8746b75e451c13a1598341ba1 Signed-off-by: Patrick Georgi Reviewed-on: https://review.coreboot.org/c/coreboot/+/32954 Reviewed-by: Arthur Heymans Reviewed-by: Angel Pons Reviewed-by: Nico Huber Tested-by: build bot (Jenkins) --- payloads/libpayload/include/coreboot_tables.h | 2 +- src/commonlib/include/commonlib/coreboot_tables.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/payloads/libpayload/include/coreboot_tables.h b/payloads/libpayload/include/coreboot_tables.h index 705e348666..8e5cec04bf 100644 --- a/payloads/libpayload/include/coreboot_tables.h +++ b/payloads/libpayload/include/coreboot_tables.h @@ -287,7 +287,7 @@ struct cb_macs { struct mac_address mac_addrs[0]; }; -#define CB_TAG_MMC_INFO 0x0034 +#define CB_TAG_MMC_INFO 0x0035 struct cb_mmc_info { uint32_t tag; uint32_t size; diff --git a/src/commonlib/include/commonlib/coreboot_tables.h b/src/commonlib/include/commonlib/coreboot_tables.h index 99ab21c724..bbc8608266 100644 --- a/src/commonlib/include/commonlib/coreboot_tables.h +++ b/src/commonlib/include/commonlib/coreboot_tables.h @@ -385,7 +385,7 @@ struct mac_address { uint8_t pad[2]; /* Pad it to 8 bytes to keep it simple. */ }; -#define LB_TAG_MMC_INFO 0x0034 +#define LB_TAG_MMC_INFO 0x0035 struct lb_mmc_info { uint32_t tag; uint32_t size; From 3d84038d57d606945403b3a1e4759dff359a7a7d Mon Sep 17 00:00:00 2001 From: Christian Walter Date: Fri, 17 May 2019 19:37:16 +0200 Subject: [PATCH 171/331] soc/intel/skylake: Add PCI Id for Kabylake DT Change-Id: I496b3a91f765d4fa137c32c9ee1e244803fc25d8 Signed-off-by: Christian Walter Reviewed-on: https://review.coreboot.org/c/coreboot/+/32850 Reviewed-by: Lijian Zhao Tested-by: build bot (Jenkins) --- src/include/device/pci_ids.h | 1 + src/soc/intel/common/block/systemagent/systemagent.c | 1 + src/soc/intel/skylake/bootblock/report_platform.c | 1 + 3 files changed, 3 insertions(+) diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 64539510ce..553deafc8b 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -3081,6 +3081,7 @@ #define PCI_DEVICE_ID_INTEL_KBL_ID_Y 0x590c #define PCI_DEVICE_ID_INTEL_KBL_ID_H 0x5910 #define PCI_DEVICE_ID_INTEL_KBL_U_R 0x5914 +#define PCI_DEVICE_ID_INTEL_KBL_ID_DT_2 0x5918 #define PCI_DEVICE_ID_INTEL_KBL_ID_DT 0x591f #define PCI_DEVICE_ID_INTEL_CNL_ID_U 0x5A04 #define PCI_DEVICE_ID_INTEL_CNL_ID_Y 0x5A02 diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c index 0f91156566..281a7f7655 100644 --- a/src/soc/intel/common/block/systemagent/systemagent.c +++ b/src/soc/intel/common/block/systemagent/systemagent.c @@ -351,6 +351,7 @@ static const unsigned short systemagent_ids[] = { PCI_DEVICE_ID_INTEL_KBL_ID_H, PCI_DEVICE_ID_INTEL_KBL_U_R, PCI_DEVICE_ID_INTEL_KBL_ID_DT, + PCI_DEVICE_ID_INTEL_KBL_ID_DT_2, PCI_DEVICE_ID_INTEL_CFL_ID_U, PCI_DEVICE_ID_INTEL_CFL_ID_H, PCI_DEVICE_ID_INTEL_CFL_ID_S, diff --git a/src/soc/intel/skylake/bootblock/report_platform.c b/src/soc/intel/skylake/bootblock/report_platform.c index de845c7854..1e81809b4f 100644 --- a/src/soc/intel/skylake/bootblock/report_platform.c +++ b/src/soc/intel/skylake/bootblock/report_platform.c @@ -59,6 +59,7 @@ static struct { { PCI_DEVICE_ID_INTEL_KBL_ID_H, "Kabylake-H" }, { PCI_DEVICE_ID_INTEL_KBL_ID_S, "Kabylake-S" }, { PCI_DEVICE_ID_INTEL_KBL_ID_DT, "Kabylake DT" }, + { PCI_DEVICE_ID_INTEL_KBL_ID_DT_2, "Kabylake DT 2" }, }; static struct { From 2e1fea408d8c7287497f0846715ee933fa9449f0 Mon Sep 17 00:00:00 2001 From: Frans Hendriks Date: Mon, 26 Nov 2018 10:33:00 +0100 Subject: [PATCH 172/331] superio: Add ASpeed AST2400 Add support for ASpeed AST2400. This device uses write twice 0xA5 to enter config mode. BUG = N/A TEST = ASRock D1521D4U Change-Id: I58fce31f0a2483e61e9d31f38ab5a059b8cf4f83 Signed-off-by: Frans Hendriks Signed-off-by: Felix Singer Reviewed-on: https://review.coreboot.org/c/coreboot/+/23135 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held --- src/include/superio/conf_mode.h | 3 + src/superio/Makefile.inc | 2 + src/superio/aspeed/Makefile.inc | 24 ++++++++ src/superio/aspeed/ast2400/Kconfig | 21 +++++++ src/superio/aspeed/ast2400/Makefile.inc | 18 ++++++ src/superio/aspeed/ast2400/ast2400.h | 31 ++++++++++ src/superio/aspeed/ast2400/superio.c | 74 ++++++++++++++++++++++++ src/superio/aspeed/common/Kconfig | 22 +++++++ src/superio/aspeed/common/aspeed.h | 30 ++++++++++ src/superio/aspeed/common/early_serial.c | 70 ++++++++++++++++++++++ src/superio/common/conf_mode.c | 12 ++++ 11 files changed, 307 insertions(+) create mode 100644 src/superio/aspeed/Makefile.inc create mode 100644 src/superio/aspeed/ast2400/Kconfig create mode 100644 src/superio/aspeed/ast2400/Makefile.inc create mode 100644 src/superio/aspeed/ast2400/ast2400.h create mode 100644 src/superio/aspeed/ast2400/superio.c create mode 100644 src/superio/aspeed/common/Kconfig create mode 100644 src/superio/aspeed/common/aspeed.h create mode 100644 src/superio/aspeed/common/early_serial.c diff --git a/src/include/superio/conf_mode.h b/src/include/superio/conf_mode.h index ecc365df7e..8e753ea43b 100644 --- a/src/include/superio/conf_mode.h +++ b/src/include/superio/conf_mode.h @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2013 Nico Huber + * Copyright (C) 2017-2018 Eltan B.V. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -25,6 +26,7 @@ void pnp_enter_conf_mode_6767(struct device *dev); void pnp_enter_conf_mode_7777(struct device *dev); void pnp_enter_conf_mode_8787(struct device *dev); void pnp_enter_conf_mode_a0a0(struct device *dev); +void pnp_enter_conf_mode_a5a5(struct device *dev); void pnp_exit_conf_mode_aa(struct device *dev); void pnp_enter_conf_mode_870155aa(struct device *dev); void pnp_exit_conf_mode_0202(struct device *dev); @@ -34,6 +36,7 @@ extern const struct pnp_mode_ops pnp_conf_mode_6767_aa; extern const struct pnp_mode_ops pnp_conf_mode_7777_aa; extern const struct pnp_mode_ops pnp_conf_mode_8787_aa; extern const struct pnp_mode_ops pnp_conf_mode_a0a0_aa; +extern const struct pnp_mode_ops pnp_conf_mode_a5a5_aa; extern const struct pnp_mode_ops pnp_conf_mode_870155_aa; #endif /* DEVICE_PNP_CONF_MODE_H */ diff --git a/src/superio/Makefile.inc b/src/superio/Makefile.inc index 5fc0ecdd7e..ca96343858 100644 --- a/src/superio/Makefile.inc +++ b/src/superio/Makefile.inc @@ -2,6 +2,7 @@ ## This file is part of the coreboot project. ## ## Copyright (C) 2009 Ronald G. Minnich +## Copyright (C) 2018 Eltan B.V. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by @@ -13,6 +14,7 @@ ## GNU General Public License for more details. ## +subdirs-y += aspeed subdirs-y += fintek subdirs-y += intel subdirs-y += ite diff --git a/src/superio/aspeed/Makefile.inc b/src/superio/aspeed/Makefile.inc new file mode 100644 index 0000000000..6d0cc263e9 --- /dev/null +++ b/src/superio/aspeed/Makefile.inc @@ -0,0 +1,24 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2009 Ronald G. Minnich +## Copyright (C) 2018 Eltan B.V. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +## include generic fintek pre-ram stage driver +romstage-$(CONFIG_SUPERIO_ASPEED_COMMON_PRE_RAM) += common/early_serial.c +bootblock-$(CONFIG_SUPERIO_ASPEED_COMMON_PRE_RAM) += common/early_serial.c + +subdirs-y += ast2400 +subdirs-y += common + +CPPFLAGS_common += -Isrc/superio/aspeed diff --git a/src/superio/aspeed/ast2400/Kconfig b/src/superio/aspeed/ast2400/Kconfig new file mode 100644 index 0000000000..1ced5afdc2 --- /dev/null +++ b/src/superio/aspeed/ast2400/Kconfig @@ -0,0 +1,21 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2009 Ronald G. Minnich +## Copyright (C) 2014 Edward O'Callaghan +## Copyright (C) 2018 Eltan B.V. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +config SUPERIO_ASPEED_AST2400 + bool + default n + select SUPERIO_ASPEED_COMMON_PRE_RAM diff --git a/src/superio/aspeed/ast2400/Makefile.inc b/src/superio/aspeed/ast2400/Makefile.inc new file mode 100644 index 0000000000..a6f8b2003a --- /dev/null +++ b/src/superio/aspeed/ast2400/Makefile.inc @@ -0,0 +1,18 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2008 Corey Osgood +## Copyright (C) 2018 Eltan B.V. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +ramstage-$(CONFIG_SUPERIO_ASPEED_AST2400) += superio.c diff --git a/src/superio/aspeed/ast2400/ast2400.h b/src/superio/aspeed/ast2400/ast2400.h new file mode 100644 index 0000000000..aa9b0a9899 --- /dev/null +++ b/src/superio/aspeed/ast2400/ast2400.h @@ -0,0 +1,31 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Edward O'Callaghan + * Copyright (C) 2018 Eltan B.V. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SUPERIO_ASPEED_AST2400_H +#define SUPERIO_ASPEED_AST2400_H + +#define AST2400_SUART1 0x2 /* Com1 */ +#define AST2400_SUART2 0x3 /* Com2 */ +#define AST2400_SWAK 0x4 /* System Wake-Up control */ +#define AST2400_KBC 0x5 /* Keyboard controller */ +#define AST2400_GPIO 0x7 /* GPIO */ +#define AST2400_SUART3 0xB /* Com3 */ +#define AST2400_SUART4 0xC /* Com4 */ +#define AST2400_ILPC2AHB 0xD /* LPC 2 AHB */ +#define AST2400_MAILBOX 0xE /* Mailbox */ + +#endif /* SUPERIO_ASPEED_AST2400_H */ diff --git a/src/superio/aspeed/ast2400/superio.c b/src/superio/aspeed/ast2400/superio.c new file mode 100644 index 0000000000..dcb14fa668 --- /dev/null +++ b/src/superio/aspeed/ast2400/superio.c @@ -0,0 +1,74 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Corey Osgood + * Copyright (C) 2018 Eltan B.V. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include "ast2400.h" + +static void ast2400_init(struct device *dev) +{ + if (!dev->enabled) + return; + + switch (dev->path.pnp.device) { + case AST2400_KBC: + pc_keyboard_init(NO_AUX_DEVICE); + break; + } +} + +static struct device_operations ops = { + .read_resources = pnp_read_resources, + .set_resources = pnp_set_resources, + .enable_resources = pnp_enable_resources, + .enable = pnp_enable, + .init = ast2400_init, + .ops_pnp_mode = &pnp_conf_mode_a5a5_aa, +}; + +static struct pnp_info pnp_dev_info[] = { + { NULL, AST2400_SUART1, PNP_IO0 | PNP_IRQ0 | PNP_MSC0, 0xfff8, }, + { NULL, AST2400_SUART2, PNP_IO0 | PNP_IRQ0 | PNP_MSC0, 0xfff8, }, + { NULL, AST2400_SWAK, PNP_IO0 | PNP_IO1 | PNP_IO2 | PNP_IO3 + | PNP_IRQ0, 0xfff8, 0xfff8, 0xfff8, 0xfff8, }, + { NULL, AST2400_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1 + | PNP_MSC0, 0xffff, 0xffff, }, + { NULL, AST2400_GPIO, PNP_IRQ0, }, // GPIO LDN has no IO Region + { NULL, AST2400_SUART3, PNP_IO0 | PNP_IRQ0 | PNP_MSC0, 0xfff8, }, + { NULL, AST2400_SUART4, PNP_IO0 | PNP_IRQ0 | PNP_MSC0, 0xfff8, }, + { NULL, AST2400_ILPC2AHB, PNP_IRQ0 | PNP_MSC0 | PNP_MSC1 | PNP_MSC2 + | PNP_MSC3 | PNP_MSC4 | PNP_MSC5 | PNP_MSC6 | PNP_MSC7 + | PNP_MSC8 | PNP_MSC9 | PNP_MSCA | PNP_MSCB | PNP_MSCC + | PNP_MSCD | PNP_MSCE, }, + { NULL, AST2400_MAILBOX, PNP_IO0 | PNP_IRQ0, 0xfffe, }, +}; + +static void enable_dev(struct device *dev) +{ + pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), + pnp_dev_info); +} + +struct chip_operations superio_aspeed_ast2400_ops = { + CHIP_NAME("ASpeed AST2400 Super I/O") + .enable_dev = enable_dev, +}; diff --git a/src/superio/aspeed/common/Kconfig b/src/superio/aspeed/common/Kconfig new file mode 100644 index 0000000000..3f0dabb853 --- /dev/null +++ b/src/superio/aspeed/common/Kconfig @@ -0,0 +1,22 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2009 Ronald G. Minnich +## Copyright (C) 2014 Edward O'Callaghan +## Copyright (C) 2018 Eltan B.V. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +# Generic Aspeed preram driver - Just enough UART initialisation code for +# preram phase. +config SUPERIO_ASPEED_COMMON_PRE_RAM + bool + default n diff --git a/src/superio/aspeed/common/aspeed.h b/src/superio/aspeed/common/aspeed.h new file mode 100644 index 0000000000..d3774eab3e --- /dev/null +++ b/src/superio/aspeed/common/aspeed.h @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Edward O'Callaghan + * Copyright (C) 2018 Eltan B.V. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SUPERIO_ASPEED_COMMON_ROMSTAGE_H +#define SUPERIO_ASPEED_COMMON_ROMSTAGE_H + +#include +#include +#include + +void aspeed_enable_serial(pnp_devfn_t dev, uint16_t iobase); + +void pnp_enter_conf_state(pnp_devfn_t dev); +void pnp_exit_conf_state(pnp_devfn_t dev); + +#endif /* SUPERIO_ASPEED_COMMON_ROMSTAGE_H */ diff --git a/src/superio/aspeed/common/early_serial.c b/src/superio/aspeed/common/early_serial.c new file mode 100644 index 0000000000..7ac9474bcc --- /dev/null +++ b/src/superio/aspeed/common/early_serial.c @@ -0,0 +1,70 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Edward O'Callaghan + * Copyright (C) 2018 Eltan B.V. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * A generic pre-ram driver for Aspeed variant Super I/O chips. + * + * The following is derived directly from the vendor Aspeed's data-sheets: + * + * To toggle between `configuration mode` and `normal operation mode` as to + * manipulation the various LDN's in Aspeed Super I/O's we are required to + * pass magic numbers `passwords keys`. + * + * ASPEED_ENTRY_KEY := enable configuration : 0xA5 (twice!) + * ASPEED_EXIT_KEY := disable configuration : 0xAA + * + * To modify a LDN's configuration register, we use the index port to select + * the index of the LDN and then writing to the data port to alter the + * parameters. A default index, data port pair is 0x4E, 0x4F respectively, a + * user modified pair is 0x2E, 0x2F respectively. + * + */ + +#include +#include +#include +#include +#include "aspeed.h" + +#define ASPEED_ENTRY_KEY 0xA5 +#define ASPEED_EXIT_KEY 0xAA + +/* Enable configuration: pass entry key '0xA5' into index port dev. */ +void pnp_enter_conf_state(pnp_devfn_t dev) +{ + u16 port = dev >> 8; + outb(ASPEED_ENTRY_KEY, port); + outb(ASPEED_ENTRY_KEY, port); +} + +/* Disable configuration: pass exit key '0xAA' into index port dev. */ +void pnp_exit_conf_state(pnp_devfn_t dev) +{ + u16 port = dev >> 8; + outb(ASPEED_EXIT_KEY, port); +} + +/* Bring up early serial debugging output before the RAM is initialized. */ +void aspeed_enable_serial(pnp_devfn_t dev, u16 iobase) +{ + pnp_enter_conf_state(dev); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_set_iobase(dev, PNP_IDX_IO0, iobase); + pnp_set_enable(dev, 1); + pnp_exit_conf_state(dev); +} diff --git a/src/superio/common/conf_mode.c b/src/superio/common/conf_mode.c index dec630bfa4..8ba1cddba9 100644 --- a/src/superio/common/conf_mode.c +++ b/src/superio/common/conf_mode.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2013 Nico Huber + * Copyright (C) 2017-2018 Eltan B.V. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -48,6 +49,12 @@ void pnp_enter_conf_mode_a0a0(struct device *dev) outb(0xa0, dev->path.pnp.port); } +void pnp_enter_conf_mode_a5a5(struct device *dev) +{ + outb(0xa5, dev->path.pnp.port); + outb(0xa5, dev->path.pnp.port); +} + void pnp_exit_conf_mode_aa(struct device *dev) { outb(0xaa, dev->path.pnp.port); @@ -96,6 +103,11 @@ const struct pnp_mode_ops pnp_conf_mode_a0a0_aa = { .exit_conf_mode = pnp_exit_conf_mode_aa, }; +const struct pnp_mode_ops pnp_conf_mode_a5a5_aa = { + .enter_conf_mode = pnp_enter_conf_mode_a5a5, + .exit_conf_mode = pnp_exit_conf_mode_aa, +}; + const struct pnp_mode_ops pnp_conf_mode_870155_aa = { .enter_conf_mode = pnp_enter_conf_mode_870155aa, .exit_conf_mode = pnp_exit_conf_mode_0202, From fa82e0db64f67fa7adb84bb423b23887a3dfed98 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Wed, 22 May 2019 21:34:04 +0200 Subject: [PATCH 173/331] nb/amd/pi/00660F01: Remove variable set but not used Change-Id: I14c69b324de795ba6dead7932b3267887130a6df Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/32946 Tested-by: build bot (Jenkins) Reviewed-by: Marshall Dawson --- src/northbridge/amd/pi/00660F01/northbridge.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/src/northbridge/amd/pi/00660F01/northbridge.c b/src/northbridge/amd/pi/00660F01/northbridge.c index 43df7259fc..41641ee65f 100644 --- a/src/northbridge/amd/pi/00660F01/northbridge.c +++ b/src/northbridge/amd/pi/00660F01/northbridge.c @@ -678,7 +678,6 @@ static void domain_set_resources(struct device *dev) struct bus *link; #if CONFIG_HW_MEM_HOLE_SIZEK != 0 struct hw_mem_hole_info mem_hole; - u32 reset_memhole = 1; #endif pci_tolm = 0xffffffffUL; @@ -708,7 +707,6 @@ static void domain_set_resources(struct device *dev) /* Use hole_basek as mmio_basek, and we don't need to reset hole anymore */ if ((mem_hole.node_id != -1) && (mmio_basek > mem_hole.hole_startk)) { mmio_basek = mem_hole.hole_startk; - reset_memhole = 0; } #endif From 7a5d4e2b4a5acbdad42c36cb4c33aab3b95af385 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Wed, 22 May 2019 21:40:10 +0200 Subject: [PATCH 174/331] nb/amd/amdmct/mct/mctecc_d.c: Remove variable set but not used Change-Id: I309cf83a1fec16b796c72c1803d27e1b7932940f Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/32947 Tested-by: build bot (Jenkins) Reviewed-by: Marshall Dawson --- src/northbridge/amd/amdmct/mct/mctecc_d.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/src/northbridge/amd/amdmct/mct/mctecc_d.c b/src/northbridge/amd/amdmct/mct/mctecc_d.c index 7be63533a9..8eb7bf54b7 100644 --- a/src/northbridge/amd/amdmct/mct/mctecc_d.c +++ b/src/northbridge/amd/amdmct/mct/mctecc_d.c @@ -80,7 +80,6 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) u16 OB_ECCRedir; u32 LDramECC; u32 OF_ScrubCTL; - u16 OB_ChipKill; u8 MemClrECC; u32 dev; @@ -96,7 +95,7 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) OB_ECCRedir = mctGet_NVbits(NV_ECCRedir); /* ECC Redirection */ - OB_ChipKill = mctGet_NVbits(NV_ChipKill); /* ECC Chip-kill mode */ + mctGet_NVbits(NV_ChipKill); /* ECC Chip-kill mode */ OF_ScrubCTL = 0; /* Scrub CTL for Dcache, L2, and dram */ nvbits = mctGet_NVbits(NV_DCBKScrub); From f0a576595a12d0d3ba8dd0fc003027dd35d7a522 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Wed, 22 May 2019 23:24:46 +0200 Subject: [PATCH 175/331] nb/amd/amdmct/mct/mctpro_d.c: Remove variable set but not used Change-Id: Ic2f2788142329e2e4d04b531805a32d4dcaa293c Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/32949 Reviewed-by: Marshall Dawson Tested-by: build bot (Jenkins) --- src/northbridge/amd/amdmct/mct/mctpro_d.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/src/northbridge/amd/amdmct/mct/mctpro_d.c b/src/northbridge/amd/amdmct/mct/mctpro_d.c index 0acb6f4ff4..83937330f8 100644 --- a/src/northbridge/amd/amdmct/mct/mctpro_d.c +++ b/src/northbridge/amd/amdmct/mct/mctpro_d.c @@ -280,7 +280,6 @@ void mct_BeforeDramInit_D(struct DCTStatStruc *pDCTstat, u32 dct) u32 Speed; u32 ch, ch_start, ch_end; u32 index_reg; - u32 index; u32 dev; u32 val; @@ -297,7 +296,7 @@ void mct_BeforeDramInit_D(struct DCTStatStruc *pDCTstat, u32 dct) ch_end = dct+1; } dev = pDCTstat->dev_dct; - index = 0x0D00E001; + for (ch = ch_start; ch < ch_end; ch++) { index_reg = 0x98 + 0x100 * ch; val = Get_NB32_index(dev, index_reg, 0x0D00E001); From 502008d5dc4467fc03e8a2edd7a50b340a4c5529 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Wed, 22 May 2019 23:33:11 +0200 Subject: [PATCH 176/331] nb/northbridge/intel/x4x/acpi.c: Remove variable set but not used Change-Id: I715adbe3d90d0f5195b54c274fb7843945d3e6be Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/32950 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- src/northbridge/intel/x4x/acpi.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/src/northbridge/intel/x4x/acpi.c b/src/northbridge/intel/x4x/acpi.c index fb04fd8582..a91d227c7a 100644 --- a/src/northbridge/intel/x4x/acpi.c +++ b/src/northbridge/intel/x4x/acpi.c @@ -25,11 +25,9 @@ unsigned long acpi_fill_mcfg(unsigned long current) { - struct device *dev; u32 pciexbar = 0; u32 length = 0; - dev = pcidev_on_root(0, 0); if (!decode_pciebar(&pciexbar, &length)) return current; From 3dbfb2bef9cdb97ac6e34a4268cc4a26e6483013 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Wed, 22 May 2019 20:11:49 +0200 Subject: [PATCH 177/331] nb/amd/amdmct/mct/mctdqs_d.c: Remove variable set but not used Change-Id: I45f32ea1ebf59a20d475dfad2d9d0980dec6918b Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/32940 Tested-by: build bot (Jenkins) Reviewed-by: Marshall Dawson --- src/northbridge/amd/amdmct/mct/mctdqs_d.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/src/northbridge/amd/amdmct/mct/mctdqs_d.c b/src/northbridge/amd/amdmct/mct/mctdqs_d.c index e2dd56fc1a..36ee3ab332 100644 --- a/src/northbridge/amd/amdmct/mct/mctdqs_d.c +++ b/src/northbridge/amd/amdmct/mct/mctdqs_d.c @@ -1192,8 +1192,6 @@ void mct_Write1LTestPattern_D(struct MCTStatStruc *pMCTstat, void mct_Read1LTestPattern_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u32 addr) { - u32 value; - /* BIOS issues the remaining (Ntrain - 2) reads after checking that * F2x11C[PrefDramTrainMode] is cleared. These reads must be to * consecutive cache lines (i.e., 64 bytes apart) and must not cross @@ -1205,5 +1203,5 @@ void mct_Read1LTestPattern_D(struct MCTStatStruc *pMCTstat, SetUpperFSbase(addr); /* 1st move causes read fill (to exclusive or shared)*/ - value = read32_fs(addr << 8); + read32_fs(addr << 8); } From 35f9507b08aa8e062b0a1f87eb25b45694378503 Mon Sep 17 00:00:00 2001 From: Duncan Laurie Date: Thu, 23 May 2019 14:48:29 -0700 Subject: [PATCH 178/331] ec/google/wilco: Fix radio control command This command is working as written, but it is not actually correct as to what the format of the command should be. Fix this and add define the other radios. There is no change in the command send to the EC. Change-Id: Ia551b08561b673d27bec2f900d97b746699b30c4 Signed-off-by: Duncan Laurie Reviewed-on: https://review.coreboot.org/c/coreboot/+/32973 Tested-by: build bot (Jenkins) Reviewed-by: Lijian Zhao Reviewed-by: EricR Lai --- src/ec/google/wilco/commands.c | 2 +- src/ec/google/wilco/commands.h | 10 +++++++++- 2 files changed, 10 insertions(+), 2 deletions(-) diff --git a/src/ec/google/wilco/commands.c b/src/ec/google/wilco/commands.c index 9d4170f539..626f9ddc2c 100644 --- a/src/ec/google/wilco/commands.c +++ b/src/ec/google/wilco/commands.c @@ -159,7 +159,7 @@ void wilco_ec_power_off(enum ec_power_off_reason reason) int wilco_ec_radio_control(enum ec_radio radio, uint8_t state) { - uint8_t radio_control[3] = { 0, radio, state }; + uint8_t radio_control[3] = { radio, RADIO_WRITE, state }; return wilco_ec_mailbox(WILCO_EC_MSG_DEFAULT, KB_RADIO_CONTROL, radio_control, ARRAY_SIZE(radio_control), diff --git a/src/ec/google/wilco/commands.h b/src/ec/google/wilco/commands.h index 9b7f2e5d07..9a185805af 100644 --- a/src/ec/google/wilco/commands.h +++ b/src/ec/google/wilco/commands.h @@ -80,7 +80,15 @@ enum ec_audio_mute { }; enum ec_radio { - RADIO_WIFI = 0x02, + RADIO_WIFI = 0, + RADIO_WWAN, + RADIO_BT, +}; + +enum ec_radio_action { + RADIO_READ = 1, + RADIO_WRITE, + RADIO_TOGGLE, }; enum ec_camera { From c6918f99d73541246f5a7d6d0f5723c674737fbe Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Mon, 11 Jun 2018 08:52:22 +0300 Subject: [PATCH 179/331] AGESA: Move heap_status_name() implementation MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Place it within class libagesa to avoid including AGESA internal header heapManager.h in coreboot proper build CPPFLAGS. Change-Id: Iae86d6631d7a6ba6ea2588a53b292b435dfd7861 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/31511 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/drivers/amd/agesa/eventlog.c | 16 ------------- src/drivers/amd/agesa/state_machine.c | 2 ++ src/northbridge/amd/agesa/state_machine.h | 1 - src/vendorcode/amd/agesa/common/Makefile.inc | 1 + src/vendorcode/amd/agesa/common/debug_util.c | 24 ++++++++++++++++++++ src/vendorcode/amd/agesa/common/debug_util.h | 8 +++++++ src/vendorcode/amd/agesa/f12/Makefile.inc | 1 - src/vendorcode/amd/agesa/f14/Makefile.inc | 2 -- src/vendorcode/amd/agesa/f15tn/Makefile.inc | 2 -- src/vendorcode/amd/agesa/f16kb/Makefile.inc | 2 -- src/vendorcode/amd/pi/Lib/debug_util.c | 24 ++++++++++++++++++++ src/vendorcode/amd/pi/Lib/debug_util.h | 8 +++++++ 12 files changed, 67 insertions(+), 24 deletions(-) create mode 100644 src/vendorcode/amd/agesa/common/debug_util.c create mode 100644 src/vendorcode/amd/agesa/common/debug_util.h create mode 100644 src/vendorcode/amd/pi/Lib/debug_util.c create mode 100644 src/vendorcode/amd/pi/Lib/debug_util.h diff --git a/src/drivers/amd/agesa/eventlog.c b/src/drivers/amd/agesa/eventlog.c index 23e31ba7d3..df3759cf35 100644 --- a/src/drivers/amd/agesa/eventlog.c +++ b/src/drivers/amd/agesa/eventlog.c @@ -21,8 +21,6 @@ #include #include -#include - static const char undefined[] = "undefined"; /* Match order of enum AGESA_STRUCT_NAME. */ @@ -34,11 +32,6 @@ static const char *AgesaFunctionNameStr[] = { "Amd2dDataEye", "AmdS3FinalRestore", "AmdInitRtb" }; -/* heapManager.h */ -static const char *HeapStatusStr[] = { - "DoNotExistYet", "LocalCache", "TempMem", "SystemMem", "DoNotExistAnymore","S3Resume" -}; - /* This function has to match with enumeration of AGESA_STRUCT_NAME defined * inside AMD.h header file. Unfortunately those are different across * different vendorcode subtrees. @@ -64,15 +57,6 @@ const char *agesa_struct_name(int state) return AgesaFunctionNameStr[index]; } -const char *heap_status_name(int status) -{ - if ((status < HEAP_DO_NOT_EXIST_YET) || (status > HEAP_S3_RESUME)) - return undefined; - - int index = status - HEAP_DO_NOT_EXIST_YET; - return HeapStatusStr[index]; -} - /* * Possible AGESA_STATUS values: * diff --git a/src/drivers/amd/agesa/state_machine.c b/src/drivers/amd/agesa/state_machine.c index dfd64c3d52..90bf038f71 100644 --- a/src/drivers/amd/agesa/state_machine.c +++ b/src/drivers/amd/agesa/state_machine.c @@ -25,6 +25,8 @@ #include #include #include + +#include #include #if CONFIG(CPU_AMD_AGESA_OPENSOURCE) diff --git a/src/northbridge/amd/agesa/state_machine.h b/src/northbridge/amd/agesa/state_machine.h index 93625fce12..d05ae478d5 100644 --- a/src/northbridge/amd/agesa/state_machine.h +++ b/src/northbridge/amd/agesa/state_machine.h @@ -24,7 +24,6 @@ /* eventlog */ const char *agesa_struct_name(int state); -const char *heap_status_name(int status); void agesawrapper_trace(AGESA_STATUS ret, AMD_CONFIG_PARAMS *StdHeader, const char *func); AGESA_STATUS agesawrapper_amdreadeventlog(UINT8 HeapStatus); diff --git a/src/vendorcode/amd/agesa/common/Makefile.inc b/src/vendorcode/amd/agesa/common/Makefile.inc index 78dd4fc988..247969477c 100644 --- a/src/vendorcode/amd/agesa/common/Makefile.inc +++ b/src/vendorcode/amd/agesa/common/Makefile.inc @@ -30,6 +30,7 @@ romstage-y += agesa-entry.c ramstage-y += agesa-entry.c +libagesa-y += debug_util.c libagesa-y += amdlib.c # Do not optimise performance-critical low-level IO for size with -Os, diff --git a/src/vendorcode/amd/agesa/common/debug_util.c b/src/vendorcode/amd/agesa/common/debug_util.c new file mode 100644 index 0000000000..29d0841904 --- /dev/null +++ b/src/vendorcode/amd/agesa/common/debug_util.c @@ -0,0 +1,24 @@ + +#include +#include +#include + +#include "debug_util.h" + +static const char undefined[] = "undefined"; + +static const char *HeapStatusStr[] = { + "DoNotExistYet", "LocalCache", "TempMem", "SystemMem", "DoNotExistAnymore","S3Resume" +}; + +/* This function has to match with enumeration of XXXX defined + * inside heapManager.h header file. + */ +const char *heap_status_name(UINT8 HeapStatus) +{ + if ((HeapStatus < HEAP_DO_NOT_EXIST_YET) || (HeapStatus > HEAP_S3_RESUME)) + return undefined; + + int index = HeapStatus - HEAP_DO_NOT_EXIST_YET; + return HeapStatusStr[index]; +} diff --git a/src/vendorcode/amd/agesa/common/debug_util.h b/src/vendorcode/amd/agesa/common/debug_util.h new file mode 100644 index 0000000000..a8d9a33c50 --- /dev/null +++ b/src/vendorcode/amd/agesa/common/debug_util.h @@ -0,0 +1,8 @@ +#ifndef __AGESA_DEBUG_UTIL_H__ +#define __AGESA_DEBUG_UTIL_H__ + +#include "AMD.h" + +const char *heap_status_name(UINT8 HeapStatus); + +#endif diff --git a/src/vendorcode/amd/agesa/f12/Makefile.inc b/src/vendorcode/amd/agesa/f12/Makefile.inc index f925ccb5f0..dbea9c368c 100644 --- a/src/vendorcode/amd/agesa/f12/Makefile.inc +++ b/src/vendorcode/amd/agesa/f12/Makefile.inc @@ -46,7 +46,6 @@ CFLAGS_x86_64 += -march=k8-sse3 -mtune=k8-sse3 -fno-zero-initialized-in-bss -fno # These are invalid, coreboot proper should not require # use of AGESA internal header files. CPPFLAGS_x86_ANY = -CPPFLAGS_x86_ANY += -I$(AGESA_ROOT)/Proc/CPU # heapManager.h CPPFLAGS_x86_32 += $(AGESA_INC) $(CPPFLAGS_x86_ANY) CPPFLAGS_x86_64 += $(AGESA_INC) $(CPPFLAGS_x86_ANY) diff --git a/src/vendorcode/amd/agesa/f14/Makefile.inc b/src/vendorcode/amd/agesa/f14/Makefile.inc index ad2d2dc63d..bf1051c9aa 100644 --- a/src/vendorcode/amd/agesa/f14/Makefile.inc +++ b/src/vendorcode/amd/agesa/f14/Makefile.inc @@ -46,8 +46,6 @@ CFLAGS_x86_64 += -march=k8-sse3 -mtune=k8-sse3 -fno-zero-initialized-in-bss -fno # These are invalid, coreboot proper should not require # use of AGESA internal header files. CPPFLAGS_x86_ANY = -CPPFLAGS_x86_ANY += -I$(AGESA_ROOT)/Proc/CPU # heapManager.h -CPPFLAGS_x86_ANY += -I$(AGESA_ROOT)/Proc/CPU/Family CPPFLAGS_x86_32 += $(AGESA_INC) $(CPPFLAGS_x86_ANY) CPPFLAGS_x86_64 += $(AGESA_INC) $(CPPFLAGS_x86_ANY) diff --git a/src/vendorcode/amd/agesa/f15tn/Makefile.inc b/src/vendorcode/amd/agesa/f15tn/Makefile.inc index 57350d9571..1c5dc18d85 100644 --- a/src/vendorcode/amd/agesa/f15tn/Makefile.inc +++ b/src/vendorcode/amd/agesa/f15tn/Makefile.inc @@ -46,8 +46,6 @@ CFLAGS_x86_64 += -march=k8-sse3 -mtune=k8-sse3 -fno-zero-initialized-in-bss -fno # These are invalid, coreboot proper should not require # use of AGESA internal header files. CPPFLAGS_x86_ANY = -CPPFLAGS_x86_ANY += -I$(AGESA_ROOT)/Proc/CPU # heapManager.h -CPPFLAGS_x86_ANY += -I$(AGESA_ROOT)/Proc/CPU/Family CPPFLAGS_x86_ANY += -I$(AGESA_ROOT)/Proc/Fch # FchPlatform.h CPPFLAGS_x86_ANY += -I$(AGESA_ROOT)/Proc/Fch/Common # FchCommonCfg.h diff --git a/src/vendorcode/amd/agesa/f16kb/Makefile.inc b/src/vendorcode/amd/agesa/f16kb/Makefile.inc index 3115c4d996..c423cf2bab 100644 --- a/src/vendorcode/amd/agesa/f16kb/Makefile.inc +++ b/src/vendorcode/amd/agesa/f16kb/Makefile.inc @@ -46,8 +46,6 @@ CFLAGS_x86_64 += -march=k8-sse3 -mtune=k8-sse3 -fno-zero-initialized-in-bss -fno # These are invalid, coreboot proper should not require # use of AGESA internal header files. CPPFLAGS_x86_ANY = -CPPFLAGS_x86_ANY += -I$(AGESA_ROOT)/Proc/CPU # heapManager.h -CPPFLAGS_x86_ANY += -I$(AGESA_ROOT)/Proc/CPU/Family CPPFLAGS_x86_ANY += -I$(AGESA_ROOT)/Proc/Fch # FchPlatform.h CPPFLAGS_x86_ANY += -I$(AGESA_ROOT)/Proc/Fch/Common # FchCommonCfg.h diff --git a/src/vendorcode/amd/pi/Lib/debug_util.c b/src/vendorcode/amd/pi/Lib/debug_util.c new file mode 100644 index 0000000000..29d0841904 --- /dev/null +++ b/src/vendorcode/amd/pi/Lib/debug_util.c @@ -0,0 +1,24 @@ + +#include +#include +#include + +#include "debug_util.h" + +static const char undefined[] = "undefined"; + +static const char *HeapStatusStr[] = { + "DoNotExistYet", "LocalCache", "TempMem", "SystemMem", "DoNotExistAnymore","S3Resume" +}; + +/* This function has to match with enumeration of XXXX defined + * inside heapManager.h header file. + */ +const char *heap_status_name(UINT8 HeapStatus) +{ + if ((HeapStatus < HEAP_DO_NOT_EXIST_YET) || (HeapStatus > HEAP_S3_RESUME)) + return undefined; + + int index = HeapStatus - HEAP_DO_NOT_EXIST_YET; + return HeapStatusStr[index]; +} diff --git a/src/vendorcode/amd/pi/Lib/debug_util.h b/src/vendorcode/amd/pi/Lib/debug_util.h new file mode 100644 index 0000000000..a8d9a33c50 --- /dev/null +++ b/src/vendorcode/amd/pi/Lib/debug_util.h @@ -0,0 +1,8 @@ +#ifndef __AGESA_DEBUG_UTIL_H__ +#define __AGESA_DEBUG_UTIL_H__ + +#include "AMD.h" + +const char *heap_status_name(UINT8 HeapStatus); + +#endif From ec85e2f55df026e2097fa5e56ec3605ab0762256 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Thu, 14 Feb 2019 10:50:03 +0200 Subject: [PATCH 180/331] AGESA f12 f14 vendorcode: Clean up extra CFLAGS MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Extra variable is no longer required here. Change-Id: I2a6839ee0349e3019de3b2a91f9e7bb1c435603d Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/31512 Tested-by: build bot (Jenkins) Reviewed-by: Marshall Dawson --- src/vendorcode/amd/agesa/f12/Makefile.inc | 8 ++------ src/vendorcode/amd/agesa/f14/Makefile.inc | 8 ++------ 2 files changed, 4 insertions(+), 12 deletions(-) diff --git a/src/vendorcode/amd/agesa/f12/Makefile.inc b/src/vendorcode/amd/agesa/f12/Makefile.inc index dbea9c368c..9bc3c2600e 100644 --- a/src/vendorcode/amd/agesa/f12/Makefile.inc +++ b/src/vendorcode/amd/agesa/f12/Makefile.inc @@ -43,12 +43,8 @@ BUILDOPTS_INCLUDES = -I$(AGESA_ROOT)/Config $(AGESA_INC) $(AGESA_AUTOINCLUDES) CFLAGS_x86_32 += -march=k8-sse3 -mtune=k8-sse3 -fno-zero-initialized-in-bss -fno-strict-aliasing CFLAGS_x86_64 += -march=k8-sse3 -mtune=k8-sse3 -fno-zero-initialized-in-bss -fno-strict-aliasing -# These are invalid, coreboot proper should not require -# use of AGESA internal header files. -CPPFLAGS_x86_ANY = - -CPPFLAGS_x86_32 += $(AGESA_INC) $(CPPFLAGS_x86_ANY) -CPPFLAGS_x86_64 += $(AGESA_INC) $(CPPFLAGS_x86_ANY) +CPPFLAGS_x86_32 += $(AGESA_INC) +CPPFLAGS_x86_64 += $(AGESA_INC) ####################################################################### diff --git a/src/vendorcode/amd/agesa/f14/Makefile.inc b/src/vendorcode/amd/agesa/f14/Makefile.inc index bf1051c9aa..da79a39f8f 100644 --- a/src/vendorcode/amd/agesa/f14/Makefile.inc +++ b/src/vendorcode/amd/agesa/f14/Makefile.inc @@ -43,12 +43,8 @@ BUILDOPTS_INCLUDES = -I$(AGESA_ROOT)/Config $(AGESA_INC) $(AGESA_AUTOINCLUDES) CFLAGS_x86_32 += -march=k8-sse3 -mtune=k8-sse3 -fno-zero-initialized-in-bss -fno-strict-aliasing CFLAGS_x86_64 += -march=k8-sse3 -mtune=k8-sse3 -fno-zero-initialized-in-bss -fno-strict-aliasing -# These are invalid, coreboot proper should not require -# use of AGESA internal header files. -CPPFLAGS_x86_ANY = - -CPPFLAGS_x86_32 += $(AGESA_INC) $(CPPFLAGS_x86_ANY) -CPPFLAGS_x86_64 += $(AGESA_INC) $(CPPFLAGS_x86_ANY) +CPPFLAGS_x86_32 += $(AGESA_INC) +CPPFLAGS_x86_64 += $(AGESA_INC) ####################################################################### From d1d4f937ec7ecf8032911fbce2ff899b14199384 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Sun, 24 Sep 2017 08:21:00 +0300 Subject: [PATCH 181/331] AGESA: Move debug helper to eventlog file MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I2d74f934936e250886526b9c8482f500628a1158 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/31513 Reviewed-by: Marshall Dawson Tested-by: build bot (Jenkins) --- src/drivers/amd/agesa/eventlog.c | 26 ++++++++++++++- src/drivers/amd/agesa/state_machine.c | 40 ++--------------------- src/northbridge/amd/agesa/state_machine.h | 12 ++++++- 3 files changed, 39 insertions(+), 39 deletions(-) diff --git a/src/drivers/amd/agesa/eventlog.c b/src/drivers/amd/agesa/eventlog.c index df3759cf35..03cb64a8ce 100644 --- a/src/drivers/amd/agesa/eventlog.c +++ b/src/drivers/amd/agesa/eventlog.c @@ -1,6 +1,8 @@ /* * This file is part of the coreboot project. * + * Copyright (C) 2016 Kyösti Mälkki + * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. @@ -18,6 +20,7 @@ #include #include #include +#include #include #include @@ -40,7 +43,7 @@ static const char *AgesaFunctionNameStr[] = { * under vendorcode/ tree. */ -const char *agesa_struct_name(int state) +static const char *agesa_struct_name(AGESA_STRUCT_NAME state) { #if CONFIG(CPU_AMD_AGESA_OPENSOURCE) if ((state < AMD_INIT_RECOVERY) || (state > AMD_IDENTIFY_DIMMS)) @@ -57,6 +60,27 @@ const char *agesa_struct_name(int state) return AgesaFunctionNameStr[index]; } +void agesa_state_on_entry(struct agesa_state *task, AGESA_STRUCT_NAME func) +{ + task->apic_id = (u8) (cpuid_ebx(1) >> 24); + task->func = func; + task->function_name = agesa_struct_name(func); + + printk(BIOS_DEBUG, "\nAPIC %02d: ** Enter %s [%08x]\n", + task->apic_id, task->function_name, task->func); +} + +void agesa_state_on_exit(struct agesa_state *task, + AMD_CONFIG_PARAMS *StdHeader) +{ + printk(BIOS_DEBUG, "APIC %02d: Heap in %s (%d) at 0x%08x\n", + task->apic_id, heap_status_name(StdHeader->HeapStatus), + StdHeader->HeapStatus, (u32)StdHeader->HeapBasePtr); + + printk(BIOS_DEBUG, "APIC %02d: ** Exit %s [%08x]\n", + task->apic_id, task->function_name, task->func); +} + /* * Possible AGESA_STATUS values: * diff --git a/src/drivers/amd/agesa/state_machine.c b/src/drivers/amd/agesa/state_machine.c index 90bf038f71..03c658287d 100644 --- a/src/drivers/amd/agesa/state_machine.c +++ b/src/drivers/amd/agesa/state_machine.c @@ -26,7 +26,6 @@ #include #include -#include #include #if CONFIG(CPU_AMD_AGESA_OPENSOURCE) @@ -231,38 +230,6 @@ static AGESA_STATUS ramstage_dispatch(struct sysinfo *cb, return status; } -/* DEBUG trace helper */ - -struct agesa_state -{ - u8 apic_id; - - AGESA_STRUCT_NAME func; - const char *function_name; -}; - -static void state_on_entry(struct agesa_state *task, AGESA_STRUCT_NAME func, - const char *struct_name) -{ - task->apic_id = (u8) (cpuid_ebx(1) >> 24); - task->func = func; - task->function_name = struct_name; - - printk(BIOS_DEBUG, "\nAPIC %02d: ** Enter %s [%08x]\n", - task->apic_id, task->function_name, task->func); -} - -static void state_on_exit(struct agesa_state *task, - AMD_CONFIG_PARAMS *StdHeader) -{ - printk(BIOS_DEBUG, "APIC %02d: Heap in %s (%d) at 0x%08x\n", - task->apic_id, heap_status_name(StdHeader->HeapStatus), - StdHeader->HeapStatus, (u32)StdHeader->HeapBasePtr); - - printk(BIOS_DEBUG, "APIC %02d: ** Exit %s [%08x]\n", - task->apic_id, task->function_name, task->func); -} - int agesa_execute_state(struct sysinfo *cb, AGESA_STRUCT_NAME func) { AMD_INTERFACE_PARAMS aip; @@ -272,13 +239,12 @@ int agesa_execute_state(struct sysinfo *cb, AGESA_STRUCT_NAME func) } agesa_params; void *buf = NULL; size_t len = 0; - const char *state_name = agesa_struct_name(func); AGESA_STATUS status, final; struct agesa_state task; memset(&task, 0, sizeof(task)); - state_on_entry(&task, func, state_name); + agesa_state_on_entry(&task, func); aip.StdHeader = cb->StdHeader; @@ -302,13 +268,13 @@ int agesa_execute_state(struct sysinfo *cb, AGESA_STRUCT_NAME func) if (ENV_RAMSTAGE) final = ramstage_dispatch(cb, func, StdHeader); - agesawrapper_trace(final, StdHeader, state_name); + agesawrapper_trace(final, StdHeader, task.function_name); ASSERT(final < AGESA_FATAL); status = amd_release_struct(&aip); ASSERT(status == AGESA_SUCCESS); - state_on_exit(&task, &aip.StdHeader); + agesa_state_on_exit(&task, &aip.StdHeader); return (final < AGESA_FATAL) ? 0 : -1; } diff --git a/src/northbridge/amd/agesa/state_machine.h b/src/northbridge/amd/agesa/state_machine.h index d05ae478d5..74c3f61e0d 100644 --- a/src/northbridge/amd/agesa/state_machine.h +++ b/src/northbridge/amd/agesa/state_machine.h @@ -23,7 +23,6 @@ #define HAS_LEGACY_WRAPPER CONFIG(BINARYPI_LEGACY_WRAPPER) /* eventlog */ -const char *agesa_struct_name(int state); void agesawrapper_trace(AGESA_STATUS ret, AMD_CONFIG_PARAMS *StdHeader, const char *func); AGESA_STATUS agesawrapper_amdreadeventlog(UINT8 HeapStatus); @@ -54,6 +53,17 @@ void board_BeforeAgesa(struct sysinfo *cb); void platform_once(struct sysinfo *cb); void agesa_set_interface(struct sysinfo *cb); + +struct agesa_state { + u8 apic_id; + + AGESA_STRUCT_NAME func; + const char *function_name; +}; + +void agesa_state_on_entry(struct agesa_state *task, AGESA_STRUCT_NAME func); +void agesa_state_on_exit(struct agesa_state *task, + AMD_CONFIG_PARAMS *StdHeader); int agesa_execute_state(struct sysinfo *cb, AGESA_STRUCT_NAME func); /* AGESA dispatchers */ From e20d6095aee0c73e758199dfa214366104fc9a85 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Sun, 10 Jun 2018 08:20:56 +0300 Subject: [PATCH 182/331] AGESA binaryPI: Redo entrypoints namelist MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Stop assuming the list is complete with no gaps, and use a lookup-table to match AGESA_STRUCT_NAME types of the entrypoints we use with names. Change-Id: Ibef4690d8aa76ff5b47c879f5ceb9d8fc4c4c4cd Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/31514 Tested-by: build bot (Jenkins) Reviewed-by: Marshall Dawson --- src/drivers/amd/agesa/eventlog.c | 94 +++++++++++++++++++++----------- 1 file changed, 62 insertions(+), 32 deletions(-) diff --git a/src/drivers/amd/agesa/eventlog.c b/src/drivers/amd/agesa/eventlog.c index 03cb64a8ce..152011ed34 100644 --- a/src/drivers/amd/agesa/eventlog.c +++ b/src/drivers/amd/agesa/eventlog.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Kyösti Mälkki + * Copyright (C) 2016-2019 Kyösti Mälkki * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -26,45 +26,75 @@ static const char undefined[] = "undefined"; -/* Match order of enum AGESA_STRUCT_NAME. */ -static const char *AgesaFunctionNameStr[] = { - "AmdInitRecovery", "AmdCreateStruct", "AmdInitEarly", "AmdInitEnv", "AmdInitLate", - "AmdInitMid", "AmdInitPost", "AmdInitReset", "AmdInitResume", "AmdReleaseStruct", - "AmdS3LateRestore", "AmdS3Save", "AmdGetApicId", "AmdGetPciAddress", "AmdIdentifyCore", - "AmdReadEventLog", "AmdGetAvailableExeCacheSize", "AmdLateRunApTask", "AmdIdentifyDimm", - "Amd2dDataEye", "AmdS3FinalRestore", "AmdInitRtb" +struct agesa_mapping +{ + AGESA_STRUCT_NAME func; + const char *name; }; -/* This function has to match with enumeration of AGESA_STRUCT_NAME defined - * inside AMD.h header file. Unfortunately those are different across - * different vendorcode subtrees. - * - * TBD: Fix said header or move this function together with the strings above - * under vendorcode/ tree. - */ - -static const char *agesa_struct_name(AGESA_STRUCT_NAME state) -{ -#if CONFIG(CPU_AMD_AGESA_OPENSOURCE) - if ((state < AMD_INIT_RECOVERY) || (state > AMD_IDENTIFY_DIMMS)) - return undefined; - - int index = state - AMD_INIT_RECOVERY; -#else - state >>= 12; - if ((state < AMD_INIT_RECOVERY >> 12) || (state > AMD_IDENTIFY_DIMMS >> 12)) - return undefined; - - int index = state - (AMD_INIT_RECOVERY >> 12); +static const struct agesa_mapping entrypoint[] = { + { + .func = AMD_INIT_RESET, + .name = "AmdInitReset", + }, + { + .func = AMD_INIT_EARLY, + .name = "AmdInitEarly", + }, + { + .func = AMD_INIT_POST, + .name = "AmdInitPost", + }, + { + .func = AMD_INIT_RESUME, + .name = "AmdInitResume", + }, + { + .func = AMD_INIT_ENV, + .name = "AmdInitEnv", + }, + { + .func = AMD_INIT_MID, + .name = "AmdInitMid", + }, + { + .func = AMD_INIT_LATE, + .name = "AmdInitLate", + }, + { + .func = AMD_S3LATE_RESTORE, + .name = "AmdS3LateRestore", + }, +#if !defined(AMD_S3_SAVE_REMOVED) + { + .func = AMD_S3_SAVE, + .name = "AmdS3Save", + }, #endif - return AgesaFunctionNameStr[index]; -} + { + .func = AMD_S3FINAL_RESTORE, + .name = "AmdS3FinalRestore", + }, + { + .func = AMD_INIT_RTB, + .name = "AmdInitRtb", + }, +}; void agesa_state_on_entry(struct agesa_state *task, AGESA_STRUCT_NAME func) { + int i; + task->apic_id = (u8) (cpuid_ebx(1) >> 24); task->func = func; - task->function_name = agesa_struct_name(func); + task->function_name = undefined; + + for (i = 0; i < ARRAY_SIZE(entrypoint); i++) { + if (task->func == entrypoint[i].func) { + task->function_name = entrypoint[i].name; + break; + } + } printk(BIOS_DEBUG, "\nAPIC %02d: ** Enter %s [%08x]\n", task->apic_id, task->function_name, task->func); From 43f6d9d7160be96460f77993465de1570568c569 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Thu, 14 Mar 2019 14:59:31 +0200 Subject: [PATCH 183/331] AGESA binaryPI: Add AGESA entry timestamps MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The call to timestamp_rescale_table() had to be moved before TS_AGESA_INIT_{POST/RESUME}_DONE to have that timestamp appear without rescaling. Change-Id: I71e09d3bc4c8657979d447b90fb6ac7cae959479 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/31515 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/drivers/amd/agesa/eventlog.c | 27 +++++++++++++++++++++++ src/drivers/amd/agesa/romstage.c | 2 -- src/drivers/amd/agesa/state_machine.c | 20 ++++++++++++++++- src/northbridge/amd/agesa/state_machine.h | 2 ++ src/vendorcode/amd/Kconfig | 9 ++++++++ 5 files changed, 57 insertions(+), 3 deletions(-) diff --git a/src/drivers/amd/agesa/eventlog.c b/src/drivers/amd/agesa/eventlog.c index 152011ed34..887da308d4 100644 --- a/src/drivers/amd/agesa/eventlog.c +++ b/src/drivers/amd/agesa/eventlog.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include @@ -30,54 +31,78 @@ struct agesa_mapping { AGESA_STRUCT_NAME func; const char *name; + uint32_t entry_id; + uint32_t exit_id; }; static const struct agesa_mapping entrypoint[] = { { .func = AMD_INIT_RESET, .name = "AmdInitReset", + .entry_id = TS_AGESA_INIT_RESET_START, + .exit_id = TS_AGESA_INIT_RESET_DONE, }, { .func = AMD_INIT_EARLY, .name = "AmdInitEarly", + .entry_id = TS_AGESA_INIT_EARLY_START, + .exit_id = TS_AGESA_INIT_EARLY_DONE, }, { .func = AMD_INIT_POST, .name = "AmdInitPost", + .entry_id = TS_AGESA_INIT_POST_START, + .exit_id = TS_AGESA_INIT_POST_DONE, }, { .func = AMD_INIT_RESUME, .name = "AmdInitResume", + .entry_id = TS_AGESA_INIT_RESUME_START, + .exit_id = TS_AGESA_INIT_RESUME_DONE, }, { .func = AMD_INIT_ENV, .name = "AmdInitEnv", + .entry_id = TS_AGESA_INIT_ENV_START, + .exit_id = TS_AGESA_INIT_ENV_DONE, }, { .func = AMD_INIT_MID, .name = "AmdInitMid", + .entry_id = TS_AGESA_INIT_MID_START, + .exit_id = TS_AGESA_INIT_MID_DONE, }, { .func = AMD_INIT_LATE, .name = "AmdInitLate", + .entry_id = TS_AGESA_INIT_LATE_START, + .exit_id = TS_AGESA_INIT_LATE_DONE, }, { .func = AMD_S3LATE_RESTORE, .name = "AmdS3LateRestore", + .entry_id = TS_AGESA_S3_LATE_START, + .exit_id = TS_AGESA_S3_LATE_DONE, }, #if !defined(AMD_S3_SAVE_REMOVED) { .func = AMD_S3_SAVE, .name = "AmdS3Save", + .entry_id = TS_AGESA_INIT_RTB_START, + .exit_id = TS_AGESA_INIT_RTB_DONE, }, #endif { .func = AMD_S3FINAL_RESTORE, .name = "AmdS3FinalRestore", + .entry_id = TS_AGESA_S3_FINAL_START, + .exit_id = TS_AGESA_S3_FINAL_DONE, }, { .func = AMD_INIT_RTB, .name = "AmdInitRtb", + .entry_id = TS_AGESA_INIT_RTB_START, + .exit_id = TS_AGESA_INIT_RTB_DONE, }, }; @@ -92,6 +117,8 @@ void agesa_state_on_entry(struct agesa_state *task, AGESA_STRUCT_NAME func) for (i = 0; i < ARRAY_SIZE(entrypoint); i++) { if (task->func == entrypoint[i].func) { task->function_name = entrypoint[i].name; + task->ts_entry_id = entrypoint[i].entry_id; + task->ts_exit_id = entrypoint[i].exit_id; break; } } diff --git a/src/drivers/amd/agesa/romstage.c b/src/drivers/amd/agesa/romstage.c index d5b20b76f9..adf6e0d0e3 100644 --- a/src/drivers/amd/agesa/romstage.c +++ b/src/drivers/amd/agesa/romstage.c @@ -90,8 +90,6 @@ void *asmlinkage romstage_main(unsigned long bist) else agesa_execute_state(cb, AMD_INIT_RESUME); - /* FIXME: Detect if TSC frequency changed during raminit? */ - timestamp_rescale_table(1, 4); timestamp_add_now(TS_AFTER_INITRAM); /* Work around AGESA setting all memory as WB on normal diff --git a/src/drivers/amd/agesa/state_machine.c b/src/drivers/amd/agesa/state_machine.c index 03c658287d..c8529c5e04 100644 --- a/src/drivers/amd/agesa/state_machine.c +++ b/src/drivers/amd/agesa/state_machine.c @@ -20,7 +20,9 @@ #include #include #include -#include +#include +#include + #include #include #include @@ -147,6 +149,11 @@ static AGESA_STATUS romstage_dispatch(struct sysinfo *cb, platform_BeforeInitPost(cb, param); board_BeforeInitPost(cb, param); status = module_dispatch(func, StdHeader); + + /* FIXME: Detect if TSC frequency really + * changed during raminit? */ + timestamp_rescale_table(1, 4); + platform_AfterInitPost(cb, param); break; } @@ -156,6 +163,11 @@ static AGESA_STATUS romstage_dispatch(struct sysinfo *cb, AMD_RESUME_PARAMS *param = (void *)StdHeader; platform_BeforeInitResume(cb, param); status = module_dispatch(func, StdHeader); + + /* FIXME: Detect if TSC frequency really + * changed during raminit? */ + timestamp_rescale_table(1, 4); + platform_AfterInitResume(cb, param); break; } @@ -262,12 +274,18 @@ int agesa_execute_state(struct sysinfo *cb, AGESA_STRUCT_NAME func) AMD_CONFIG_PARAMS *StdHeader = aip.NewStructPtr; ASSERT(StdHeader->Func == func); + if (CONFIG(AGESA_EXTRA_TIMESTAMPS) && task.ts_entry_id) + timestamp_add_now(task.ts_entry_id); + if (ENV_ROMSTAGE) final = romstage_dispatch(cb, func, StdHeader); if (ENV_RAMSTAGE) final = ramstage_dispatch(cb, func, StdHeader); + if (CONFIG(AGESA_EXTRA_TIMESTAMPS) && task.ts_exit_id) + timestamp_add_now(task.ts_exit_id); + agesawrapper_trace(final, StdHeader, task.function_name); ASSERT(final < AGESA_FATAL); diff --git a/src/northbridge/amd/agesa/state_machine.h b/src/northbridge/amd/agesa/state_machine.h index 74c3f61e0d..7d9fe9c5ef 100644 --- a/src/northbridge/amd/agesa/state_machine.h +++ b/src/northbridge/amd/agesa/state_machine.h @@ -59,6 +59,8 @@ struct agesa_state { AGESA_STRUCT_NAME func; const char *function_name; + uint32_t ts_entry_id; + uint32_t ts_exit_id; }; void agesa_state_on_entry(struct agesa_state *task, AGESA_STRUCT_NAME func); diff --git a/src/vendorcode/amd/Kconfig b/src/vendorcode/amd/Kconfig index 3fe0c82240..44b3940fa7 100644 --- a/src/vendorcode/amd/Kconfig +++ b/src/vendorcode/amd/Kconfig @@ -47,6 +47,15 @@ if CPU_AMD_AGESA_BINARY_PI source src/vendorcode/amd/pi/Kconfig endif +config AGESA_EXTRA_TIMESTAMPS + bool "Add instrumentation for AGESA calls" + default n + depends on !BINARYPI_LEGACY_WRAPPER + depends on DRIVERS_AMD_PI + help + Insert additional timestamps around each entrypoint into + AGESA vendorcode. + endmenu endif From a6f9ee39065ecd6ec24f5f09616bddef17e894d6 Mon Sep 17 00:00:00 2001 From: Peter Lemenkov Date: Wed, 10 Oct 2018 14:28:44 +0200 Subject: [PATCH 184/331] mb/lenovo: Unify thermal threshold handling Unify thermal handling across Lenovo boards (except g505, which is different). Namely, do the following: * Move thermal levels from acpi_tables to thermal.h (and create if necessary). * Don't use board-specific ifdef guards. * Set thermal levels using dedicated acpi_update_thermal_table function as almost all Lenovo boards do. * Update list of authors in comments. Merge all author's entries. * Minor whitespace and formatting. This makes diff -ruw between the Lenovo boards smaller. Change-Id: If569f67c932b7fbf14893b890a5588df4994daeb Signed-off-by: Peter Lemenkov Reviewed-on: https://review.coreboot.org/c/coreboot/+/29659 Reviewed-by: Patrick Rudolph Reviewed-by: Philipp Deppenwiese Tested-by: build bot (Jenkins) --- src/mainboard/lenovo/l520/acpi_tables.c | 1 - src/mainboard/lenovo/l520/thermal.h | 17 ++++++----- src/mainboard/lenovo/s230u/acpi_tables.c | 10 +++++-- src/mainboard/lenovo/s230u/thermal.h | 30 +++++++++++++++++++ src/mainboard/lenovo/t400/acpi_tables.c | 11 +++++-- src/mainboard/lenovo/t400/thermal.h | 30 +++++++++++++++++++ src/mainboard/lenovo/t420/thermal.h | 16 ++++++---- src/mainboard/lenovo/t420s/thermal.h | 24 ++++++++------- src/mainboard/lenovo/t430/thermal.h | 16 ++++++---- src/mainboard/lenovo/t430s/thermal.h | 16 ++++++---- src/mainboard/lenovo/t520/acpi_tables.c | 1 - src/mainboard/lenovo/t520/thermal.h | 24 ++++++++------- src/mainboard/lenovo/t530/acpi_tables.c | 1 - src/mainboard/lenovo/t530/thermal.h | 24 ++++++++------- src/mainboard/lenovo/t60/acpi_tables.c | 11 +++++-- src/mainboard/lenovo/t60/thermal.h | 30 +++++++++++++++++++ src/mainboard/lenovo/x131e/thermal.h | 22 +++++++------- src/mainboard/lenovo/x1_carbon_gen1/thermal.h | 24 ++++++++------- src/mainboard/lenovo/x200/acpi_tables.c | 11 +++++-- src/mainboard/lenovo/x200/thermal.h | 30 +++++++++++++++++++ src/mainboard/lenovo/x201/acpi_tables.c | 11 +++++-- src/mainboard/lenovo/x201/thermal.h | 30 +++++++++++++++++++ src/mainboard/lenovo/x220/thermal.h | 24 ++++++++------- src/mainboard/lenovo/x230/thermal.h | 24 ++++++++------- src/mainboard/lenovo/x60/acpi_tables.c | 11 +++++-- src/mainboard/lenovo/x60/thermal.h | 30 +++++++++++++++++++ src/mainboard/lenovo/z61t/acpi_tables.c | 8 +++++ src/mainboard/lenovo/z61t/thermal.h | 30 +++++++++++++++++++ 28 files changed, 402 insertions(+), 115 deletions(-) create mode 100644 src/mainboard/lenovo/s230u/thermal.h create mode 100644 src/mainboard/lenovo/t400/thermal.h create mode 100644 src/mainboard/lenovo/t60/thermal.h create mode 100644 src/mainboard/lenovo/x200/thermal.h create mode 100644 src/mainboard/lenovo/x201/thermal.h create mode 100644 src/mainboard/lenovo/x60/thermal.h create mode 100644 src/mainboard/lenovo/z61t/thermal.h diff --git a/src/mainboard/lenovo/l520/acpi_tables.c b/src/mainboard/lenovo/l520/acpi_tables.c index b86186404c..31f41e7561 100644 --- a/src/mainboard/lenovo/l520/acpi_tables.c +++ b/src/mainboard/lenovo/l520/acpi_tables.c @@ -35,7 +35,6 @@ void acpi_create_gnvs(global_nvs_t *gnvs) gnvs->s5u0 = 0; gnvs->s5u1 = 0; - // the lid is open by default. gnvs->lids = 1; diff --git a/src/mainboard/lenovo/l520/thermal.h b/src/mainboard/lenovo/l520/thermal.h index a2007ffeda..72953fd2c2 100644 --- a/src/mainboard/lenovo/l520/thermal.h +++ b/src/mainboard/lenovo/l520/thermal.h @@ -2,7 +2,10 @@ * This file is part of the coreboot project. * * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. + * Copyright (C) 2014 Vladimir Serbinenko * Copyright (C) 2016 Patrick Rudolph + * Copyright (C) 2017 James Ye * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -15,13 +18,13 @@ * GNU General Public License for more details. */ -#ifndef L520_THERMAL_H -#define L520_THERMAL_H +#ifndef MAINBOARD_THERMAL_H +#define MAINBOARD_THERMAL_H - /* Temperature which OS will shutdown at */ - #define CRITICAL_TEMPERATURE 100 +/* Temperature which OS will shutdown at */ +#define CRITICAL_TEMPERATURE 100 - /* Temperature which OS will throttle CPU */ - #define PASSIVE_TEMPERATURE 90 +/* Temperature which OS will throttle CPU */ +#define PASSIVE_TEMPERATURE 90 -#endif /* L520_THERMAL_H */ +#endif /* MAINBOARD_THERMAL_H */ diff --git a/src/mainboard/lenovo/s230u/acpi_tables.c b/src/mainboard/lenovo/s230u/acpi_tables.c index 21fce85f5a..8d6d93f1c3 100644 --- a/src/mainboard/lenovo/s230u/acpi_tables.c +++ b/src/mainboard/lenovo/s230u/acpi_tables.c @@ -14,6 +14,13 @@ */ #include +#include "thermal.h" + +static void acpi_update_thermal_table(global_nvs_t *gnvs) +{ + gnvs->tcrt = CRITICAL_TEMPERATURE; + gnvs->tpsv = PASSIVE_TEMPERATURE; +} void acpi_create_gnvs(global_nvs_t *gnvs) { @@ -28,6 +35,5 @@ void acpi_create_gnvs(global_nvs_t *gnvs) /* The LID is open by default */ gnvs->lids = 1; - gnvs->tcrt = 100; - gnvs->tpsv = 90; + acpi_update_thermal_table(gnvs); } diff --git a/src/mainboard/lenovo/s230u/thermal.h b/src/mainboard/lenovo/s230u/thermal.h new file mode 100644 index 0000000000..72953fd2c2 --- /dev/null +++ b/src/mainboard/lenovo/s230u/thermal.h @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. + * Copyright (C) 2014 Vladimir Serbinenko + * Copyright (C) 2016 Patrick Rudolph + * Copyright (C) 2017 James Ye + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef MAINBOARD_THERMAL_H +#define MAINBOARD_THERMAL_H + +/* Temperature which OS will shutdown at */ +#define CRITICAL_TEMPERATURE 100 + +/* Temperature which OS will throttle CPU */ +#define PASSIVE_TEMPERATURE 90 + +#endif /* MAINBOARD_THERMAL_H */ diff --git a/src/mainboard/lenovo/t400/acpi_tables.c b/src/mainboard/lenovo/t400/acpi_tables.c index 301ca50735..8fb9056c51 100644 --- a/src/mainboard/lenovo/t400/acpi_tables.c +++ b/src/mainboard/lenovo/t400/acpi_tables.c @@ -21,6 +21,13 @@ #include #include #include +#include "thermal.h" + +static void acpi_update_thermal_table(global_nvs_t *gnvs) +{ + gnvs->tcrt = CRITICAL_TEMPERATURE; + gnvs->tpsv = PASSIVE_TEMPERATURE; +} void acpi_create_gnvs(global_nvs_t *gnvs) { @@ -32,9 +39,7 @@ void acpi_create_gnvs(global_nvs_t *gnvs) gnvs->cmap = 0x01; gnvs->cmbp = 0x01; - /* Set thermal levels */ - gnvs->tcrt = 100; - gnvs->tpsv = 90; + acpi_update_thermal_table(gnvs); } unsigned long acpi_fill_madt(unsigned long current) diff --git a/src/mainboard/lenovo/t400/thermal.h b/src/mainboard/lenovo/t400/thermal.h new file mode 100644 index 0000000000..72953fd2c2 --- /dev/null +++ b/src/mainboard/lenovo/t400/thermal.h @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. + * Copyright (C) 2014 Vladimir Serbinenko + * Copyright (C) 2016 Patrick Rudolph + * Copyright (C) 2017 James Ye + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef MAINBOARD_THERMAL_H +#define MAINBOARD_THERMAL_H + +/* Temperature which OS will shutdown at */ +#define CRITICAL_TEMPERATURE 100 + +/* Temperature which OS will throttle CPU */ +#define PASSIVE_TEMPERATURE 90 + +#endif /* MAINBOARD_THERMAL_H */ diff --git a/src/mainboard/lenovo/t420/thermal.h b/src/mainboard/lenovo/t420/thermal.h index 6ca5b2a672..72953fd2c2 100644 --- a/src/mainboard/lenovo/t420/thermal.h +++ b/src/mainboard/lenovo/t420/thermal.h @@ -1,12 +1,16 @@ /* * This file is part of the coreboot project. * + * Copyright (C) 2008-2009 coresystems GmbH * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. * Copyright (C) 2014 Vladimir Serbinenko + * Copyright (C) 2016 Patrick Rudolph + * Copyright (C) 2017 James Ye * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of @@ -14,8 +18,8 @@ * GNU General Public License for more details. */ -#ifndef T420_THERMAL_H -#define T420_THERMAL_H +#ifndef MAINBOARD_THERMAL_H +#define MAINBOARD_THERMAL_H /* Temperature which OS will shutdown at */ #define CRITICAL_TEMPERATURE 100 @@ -23,4 +27,4 @@ /* Temperature which OS will throttle CPU */ #define PASSIVE_TEMPERATURE 90 -#endif +#endif /* MAINBOARD_THERMAL_H */ diff --git a/src/mainboard/lenovo/t420s/thermal.h b/src/mainboard/lenovo/t420s/thermal.h index c7803e5c7a..72953fd2c2 100644 --- a/src/mainboard/lenovo/t420s/thermal.h +++ b/src/mainboard/lenovo/t420s/thermal.h @@ -1,12 +1,16 @@ /* * This file is part of the coreboot project. * + * Copyright (C) 2008-2009 coresystems GmbH * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. * Copyright (C) 2014 Vladimir Serbinenko + * Copyright (C) 2016 Patrick Rudolph + * Copyright (C) 2017 James Ye * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of @@ -14,13 +18,13 @@ * GNU General Public License for more details. */ -#ifndef T420S_THERMAL_H -#define T420S_THERMAL_H +#ifndef MAINBOARD_THERMAL_H +#define MAINBOARD_THERMAL_H - /* Temperature which OS will shutdown at */ - #define CRITICAL_TEMPERATURE 100 +/* Temperature which OS will shutdown at */ +#define CRITICAL_TEMPERATURE 100 - /* Temperature which OS will throttle CPU */ - #define PASSIVE_TEMPERATURE 90 +/* Temperature which OS will throttle CPU */ +#define PASSIVE_TEMPERATURE 90 -#endif +#endif /* MAINBOARD_THERMAL_H */ diff --git a/src/mainboard/lenovo/t430/thermal.h b/src/mainboard/lenovo/t430/thermal.h index e3e49f594e..edfe3bc7ce 100644 --- a/src/mainboard/lenovo/t430/thermal.h +++ b/src/mainboard/lenovo/t430/thermal.h @@ -1,12 +1,16 @@ /* * This file is part of the coreboot project. * + * Copyright (C) 2008-2009 coresystems GmbH * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. * Copyright (C) 2014 Vladimir Serbinenko + * Copyright (C) 2016 Patrick Rudolph + * Copyright (C) 2017 James Ye * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of @@ -14,8 +18,8 @@ * GNU General Public License for more details. */ -#ifndef _LENOVO_T430_THERMAL_H -#define _LENOVO_T430_THERMAL_H +#ifndef MAINBOARD_THERMAL_H +#define MAINBOARD_THERMAL_H /* Config TDP Sensor ID */ #define CTDP_SENSOR_ID 0 /* PECI */ @@ -37,4 +41,4 @@ /* Tj_max value for calculating PECI CPU temperature */ #define MAX_TEMPERATURE 105 -#endif +#endif /* MAINBOARD_THERMAL_H */ diff --git a/src/mainboard/lenovo/t430s/thermal.h b/src/mainboard/lenovo/t430s/thermal.h index 1d55584ce9..72953fd2c2 100644 --- a/src/mainboard/lenovo/t430s/thermal.h +++ b/src/mainboard/lenovo/t430s/thermal.h @@ -1,12 +1,16 @@ /* * This file is part of the coreboot project. * + * Copyright (C) 2008-2009 coresystems GmbH * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. * Copyright (C) 2014 Vladimir Serbinenko + * Copyright (C) 2016 Patrick Rudolph + * Copyright (C) 2017 James Ye * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of @@ -14,8 +18,8 @@ * GNU General Public License for more details. */ -#ifndef T430S_THERMAL_H -#define T430S_THERMAL_H +#ifndef MAINBOARD_THERMAL_H +#define MAINBOARD_THERMAL_H /* Temperature which OS will shutdown at */ #define CRITICAL_TEMPERATURE 100 @@ -23,4 +27,4 @@ /* Temperature which OS will throttle CPU */ #define PASSIVE_TEMPERATURE 90 -#endif /* T430S_THERMAL_H */ +#endif /* MAINBOARD_THERMAL_H */ diff --git a/src/mainboard/lenovo/t520/acpi_tables.c b/src/mainboard/lenovo/t520/acpi_tables.c index a3b0894bcc..279674d002 100644 --- a/src/mainboard/lenovo/t520/acpi_tables.c +++ b/src/mainboard/lenovo/t520/acpi_tables.c @@ -32,7 +32,6 @@ void acpi_create_gnvs(global_nvs_t *gnvs) gnvs->s5u0 = 0; gnvs->s5u1 = 0; - // the lid is open by default. gnvs->lids = 1; diff --git a/src/mainboard/lenovo/t520/thermal.h b/src/mainboard/lenovo/t520/thermal.h index 60721bf244..72953fd2c2 100644 --- a/src/mainboard/lenovo/t520/thermal.h +++ b/src/mainboard/lenovo/t520/thermal.h @@ -1,12 +1,16 @@ /* * This file is part of the coreboot project. * + * Copyright (C) 2008-2009 coresystems GmbH * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. * Copyright (C) 2014 Vladimir Serbinenko + * Copyright (C) 2016 Patrick Rudolph + * Copyright (C) 2017 James Ye * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of @@ -14,13 +18,13 @@ * GNU General Public License for more details. */ -#ifndef T520_THERMAL_H -#define T520_THERMAL_H +#ifndef MAINBOARD_THERMAL_H +#define MAINBOARD_THERMAL_H - /* Temperature which OS will shutdown at */ - #define CRITICAL_TEMPERATURE 100 +/* Temperature which OS will shutdown at */ +#define CRITICAL_TEMPERATURE 100 - /* Temperature which OS will throttle CPU */ - #define PASSIVE_TEMPERATURE 90 +/* Temperature which OS will throttle CPU */ +#define PASSIVE_TEMPERATURE 90 -#endif /* T520_THERMAL_H */ +#endif /* MAINBOARD_THERMAL_H */ diff --git a/src/mainboard/lenovo/t530/acpi_tables.c b/src/mainboard/lenovo/t530/acpi_tables.c index a3b0894bcc..279674d002 100644 --- a/src/mainboard/lenovo/t530/acpi_tables.c +++ b/src/mainboard/lenovo/t530/acpi_tables.c @@ -32,7 +32,6 @@ void acpi_create_gnvs(global_nvs_t *gnvs) gnvs->s5u0 = 0; gnvs->s5u1 = 0; - // the lid is open by default. gnvs->lids = 1; diff --git a/src/mainboard/lenovo/t530/thermal.h b/src/mainboard/lenovo/t530/thermal.h index 0b24ea8186..72953fd2c2 100644 --- a/src/mainboard/lenovo/t530/thermal.h +++ b/src/mainboard/lenovo/t530/thermal.h @@ -1,12 +1,16 @@ /* * This file is part of the coreboot project. * + * Copyright (C) 2008-2009 coresystems GmbH * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. * Copyright (C) 2014 Vladimir Serbinenko + * Copyright (C) 2016 Patrick Rudolph + * Copyright (C) 2017 James Ye * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of @@ -14,13 +18,13 @@ * GNU General Public License for more details. */ -#ifndef T530_THERMAL_H -#define T530_THERMAL_H +#ifndef MAINBOARD_THERMAL_H +#define MAINBOARD_THERMAL_H - /* Temperature which OS will shutdown at */ - #define CRITICAL_TEMPERATURE 100 +/* Temperature which OS will shutdown at */ +#define CRITICAL_TEMPERATURE 100 - /* Temperature which OS will throttle CPU */ - #define PASSIVE_TEMPERATURE 90 +/* Temperature which OS will throttle CPU */ +#define PASSIVE_TEMPERATURE 90 -#endif /* T530_THERMAL_H */ +#endif /* MAINBOARD_THERMAL_H */ diff --git a/src/mainboard/lenovo/t60/acpi_tables.c b/src/mainboard/lenovo/t60/acpi_tables.c index 183b7fe299..bd10a0e3fb 100644 --- a/src/mainboard/lenovo/t60/acpi_tables.c +++ b/src/mainboard/lenovo/t60/acpi_tables.c @@ -16,6 +16,13 @@ #include #include +#include "thermal.h" + +static void acpi_update_thermal_table(global_nvs_t *gnvs) +{ + gnvs->tcrt = CRITICAL_TEMPERATURE; + gnvs->tpsv = PASSIVE_TEMPERATURE; +} void acpi_create_gnvs(global_nvs_t *gnvs) { @@ -23,7 +30,5 @@ void acpi_create_gnvs(global_nvs_t *gnvs) gnvs->cmap = 0x01; gnvs->cmbp = 0x01; - /* Set thermal levels */ - gnvs->tcrt = 100; - gnvs->tpsv = 90; + acpi_update_thermal_table(gnvs); } diff --git a/src/mainboard/lenovo/t60/thermal.h b/src/mainboard/lenovo/t60/thermal.h new file mode 100644 index 0000000000..72953fd2c2 --- /dev/null +++ b/src/mainboard/lenovo/t60/thermal.h @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. + * Copyright (C) 2014 Vladimir Serbinenko + * Copyright (C) 2016 Patrick Rudolph + * Copyright (C) 2017 James Ye + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef MAINBOARD_THERMAL_H +#define MAINBOARD_THERMAL_H + +/* Temperature which OS will shutdown at */ +#define CRITICAL_TEMPERATURE 100 + +/* Temperature which OS will throttle CPU */ +#define PASSIVE_TEMPERATURE 90 + +#endif /* MAINBOARD_THERMAL_H */ diff --git a/src/mainboard/lenovo/x131e/thermal.h b/src/mainboard/lenovo/x131e/thermal.h index ff928699ae..72953fd2c2 100644 --- a/src/mainboard/lenovo/x131e/thermal.h +++ b/src/mainboard/lenovo/x131e/thermal.h @@ -1,12 +1,16 @@ /* * This file is part of the coreboot project. * + * Copyright (C) 2008-2009 coresystems GmbH * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. + * Copyright (C) 2014 Vladimir Serbinenko + * Copyright (C) 2016 Patrick Rudolph * Copyright (C) 2017 James Ye * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of @@ -14,15 +18,13 @@ * GNU General Public License for more details. */ -#ifndef X131E_THERMAL_H -#define X131E_THERMAL_H - -/* Active Thermal and fans are controlled by the EC. */ +#ifndef MAINBOARD_THERMAL_H +#define MAINBOARD_THERMAL_H /* Temperature which OS will shutdown at */ -#define CRITICAL_TEMPERATURE 100 +#define CRITICAL_TEMPERATURE 100 /* Temperature which OS will throttle CPU */ -#define PASSIVE_TEMPERATURE 90 +#define PASSIVE_TEMPERATURE 90 -#endif /* X131E_THERMAL_H */ +#endif /* MAINBOARD_THERMAL_H */ diff --git a/src/mainboard/lenovo/x1_carbon_gen1/thermal.h b/src/mainboard/lenovo/x1_carbon_gen1/thermal.h index 199c27e637..72953fd2c2 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/thermal.h +++ b/src/mainboard/lenovo/x1_carbon_gen1/thermal.h @@ -1,12 +1,16 @@ /* * This file is part of the coreboot project. * + * Copyright (C) 2008-2009 coresystems GmbH * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. * Copyright (C) 2014 Vladimir Serbinenko + * Copyright (C) 2016 Patrick Rudolph + * Copyright (C) 2017 James Ye * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of @@ -14,13 +18,13 @@ * GNU General Public License for more details. */ -#ifndef X230_THERMAL_H -#define X230_THERMAL_H +#ifndef MAINBOARD_THERMAL_H +#define MAINBOARD_THERMAL_H - /* Temperature which OS will shutdown at */ - #define CRITICAL_TEMPERATURE 100 +/* Temperature which OS will shutdown at */ +#define CRITICAL_TEMPERATURE 100 - /* Temperature which OS will throttle CPU */ - #define PASSIVE_TEMPERATURE 90 +/* Temperature which OS will throttle CPU */ +#define PASSIVE_TEMPERATURE 90 -#endif +#endif /* MAINBOARD_THERMAL_H */ diff --git a/src/mainboard/lenovo/x200/acpi_tables.c b/src/mainboard/lenovo/x200/acpi_tables.c index 301ca50735..8fb9056c51 100644 --- a/src/mainboard/lenovo/x200/acpi_tables.c +++ b/src/mainboard/lenovo/x200/acpi_tables.c @@ -21,6 +21,13 @@ #include #include #include +#include "thermal.h" + +static void acpi_update_thermal_table(global_nvs_t *gnvs) +{ + gnvs->tcrt = CRITICAL_TEMPERATURE; + gnvs->tpsv = PASSIVE_TEMPERATURE; +} void acpi_create_gnvs(global_nvs_t *gnvs) { @@ -32,9 +39,7 @@ void acpi_create_gnvs(global_nvs_t *gnvs) gnvs->cmap = 0x01; gnvs->cmbp = 0x01; - /* Set thermal levels */ - gnvs->tcrt = 100; - gnvs->tpsv = 90; + acpi_update_thermal_table(gnvs); } unsigned long acpi_fill_madt(unsigned long current) diff --git a/src/mainboard/lenovo/x200/thermal.h b/src/mainboard/lenovo/x200/thermal.h new file mode 100644 index 0000000000..72953fd2c2 --- /dev/null +++ b/src/mainboard/lenovo/x200/thermal.h @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. + * Copyright (C) 2014 Vladimir Serbinenko + * Copyright (C) 2016 Patrick Rudolph + * Copyright (C) 2017 James Ye + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef MAINBOARD_THERMAL_H +#define MAINBOARD_THERMAL_H + +/* Temperature which OS will shutdown at */ +#define CRITICAL_TEMPERATURE 100 + +/* Temperature which OS will throttle CPU */ +#define PASSIVE_TEMPERATURE 90 + +#endif /* MAINBOARD_THERMAL_H */ diff --git a/src/mainboard/lenovo/x201/acpi_tables.c b/src/mainboard/lenovo/x201/acpi_tables.c index e412503c88..82991b267b 100644 --- a/src/mainboard/lenovo/x201/acpi_tables.c +++ b/src/mainboard/lenovo/x201/acpi_tables.c @@ -17,10 +17,15 @@ #include #include +#include "thermal.h" + +static void acpi_update_thermal_table(global_nvs_t *gnvs) +{ + gnvs->tcrt = CRITICAL_TEMPERATURE; + gnvs->tpsv = PASSIVE_TEMPERATURE; +} void acpi_create_gnvs(global_nvs_t * gnvs) { - /* Set thermal levels */ - gnvs->tcrt = 100; - gnvs->tpsv = 90; + acpi_update_thermal_table(gnvs); } diff --git a/src/mainboard/lenovo/x201/thermal.h b/src/mainboard/lenovo/x201/thermal.h new file mode 100644 index 0000000000..72953fd2c2 --- /dev/null +++ b/src/mainboard/lenovo/x201/thermal.h @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. + * Copyright (C) 2014 Vladimir Serbinenko + * Copyright (C) 2016 Patrick Rudolph + * Copyright (C) 2017 James Ye + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef MAINBOARD_THERMAL_H +#define MAINBOARD_THERMAL_H + +/* Temperature which OS will shutdown at */ +#define CRITICAL_TEMPERATURE 100 + +/* Temperature which OS will throttle CPU */ +#define PASSIVE_TEMPERATURE 90 + +#endif /* MAINBOARD_THERMAL_H */ diff --git a/src/mainboard/lenovo/x220/thermal.h b/src/mainboard/lenovo/x220/thermal.h index 82df303093..72953fd2c2 100644 --- a/src/mainboard/lenovo/x220/thermal.h +++ b/src/mainboard/lenovo/x220/thermal.h @@ -1,12 +1,16 @@ /* * This file is part of the coreboot project. * + * Copyright (C) 2008-2009 coresystems GmbH * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. * Copyright (C) 2014 Vladimir Serbinenko + * Copyright (C) 2016 Patrick Rudolph + * Copyright (C) 2017 James Ye * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of @@ -14,13 +18,13 @@ * GNU General Public License for more details. */ -#ifndef X220_THERMAL_H -#define X220_THERMAL_H +#ifndef MAINBOARD_THERMAL_H +#define MAINBOARD_THERMAL_H - /* Temperature which OS will shutdown at */ - #define CRITICAL_TEMPERATURE 100 +/* Temperature which OS will shutdown at */ +#define CRITICAL_TEMPERATURE 100 - /* Temperature which OS will throttle CPU */ - #define PASSIVE_TEMPERATURE 90 +/* Temperature which OS will throttle CPU */ +#define PASSIVE_TEMPERATURE 90 -#endif +#endif /* MAINBOARD_THERMAL_H */ diff --git a/src/mainboard/lenovo/x230/thermal.h b/src/mainboard/lenovo/x230/thermal.h index 199c27e637..72953fd2c2 100644 --- a/src/mainboard/lenovo/x230/thermal.h +++ b/src/mainboard/lenovo/x230/thermal.h @@ -1,12 +1,16 @@ /* * This file is part of the coreboot project. * + * Copyright (C) 2008-2009 coresystems GmbH * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. * Copyright (C) 2014 Vladimir Serbinenko + * Copyright (C) 2016 Patrick Rudolph + * Copyright (C) 2017 James Ye * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of @@ -14,13 +18,13 @@ * GNU General Public License for more details. */ -#ifndef X230_THERMAL_H -#define X230_THERMAL_H +#ifndef MAINBOARD_THERMAL_H +#define MAINBOARD_THERMAL_H - /* Temperature which OS will shutdown at */ - #define CRITICAL_TEMPERATURE 100 +/* Temperature which OS will shutdown at */ +#define CRITICAL_TEMPERATURE 100 - /* Temperature which OS will throttle CPU */ - #define PASSIVE_TEMPERATURE 90 +/* Temperature which OS will throttle CPU */ +#define PASSIVE_TEMPERATURE 90 -#endif +#endif /* MAINBOARD_THERMAL_H */ diff --git a/src/mainboard/lenovo/x60/acpi_tables.c b/src/mainboard/lenovo/x60/acpi_tables.c index 183b7fe299..bd10a0e3fb 100644 --- a/src/mainboard/lenovo/x60/acpi_tables.c +++ b/src/mainboard/lenovo/x60/acpi_tables.c @@ -16,6 +16,13 @@ #include #include +#include "thermal.h" + +static void acpi_update_thermal_table(global_nvs_t *gnvs) +{ + gnvs->tcrt = CRITICAL_TEMPERATURE; + gnvs->tpsv = PASSIVE_TEMPERATURE; +} void acpi_create_gnvs(global_nvs_t *gnvs) { @@ -23,7 +30,5 @@ void acpi_create_gnvs(global_nvs_t *gnvs) gnvs->cmap = 0x01; gnvs->cmbp = 0x01; - /* Set thermal levels */ - gnvs->tcrt = 100; - gnvs->tpsv = 90; + acpi_update_thermal_table(gnvs); } diff --git a/src/mainboard/lenovo/x60/thermal.h b/src/mainboard/lenovo/x60/thermal.h new file mode 100644 index 0000000000..72953fd2c2 --- /dev/null +++ b/src/mainboard/lenovo/x60/thermal.h @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. + * Copyright (C) 2014 Vladimir Serbinenko + * Copyright (C) 2016 Patrick Rudolph + * Copyright (C) 2017 James Ye + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef MAINBOARD_THERMAL_H +#define MAINBOARD_THERMAL_H + +/* Temperature which OS will shutdown at */ +#define CRITICAL_TEMPERATURE 100 + +/* Temperature which OS will throttle CPU */ +#define PASSIVE_TEMPERATURE 90 + +#endif /* MAINBOARD_THERMAL_H */ diff --git a/src/mainboard/lenovo/z61t/acpi_tables.c b/src/mainboard/lenovo/z61t/acpi_tables.c index 3e9a81042e..bd10a0e3fb 100644 --- a/src/mainboard/lenovo/z61t/acpi_tables.c +++ b/src/mainboard/lenovo/z61t/acpi_tables.c @@ -16,6 +16,13 @@ #include #include +#include "thermal.h" + +static void acpi_update_thermal_table(global_nvs_t *gnvs) +{ + gnvs->tcrt = CRITICAL_TEMPERATURE; + gnvs->tpsv = PASSIVE_TEMPERATURE; +} void acpi_create_gnvs(global_nvs_t *gnvs) { @@ -23,4 +30,5 @@ void acpi_create_gnvs(global_nvs_t *gnvs) gnvs->cmap = 0x01; gnvs->cmbp = 0x01; + acpi_update_thermal_table(gnvs); } diff --git a/src/mainboard/lenovo/z61t/thermal.h b/src/mainboard/lenovo/z61t/thermal.h new file mode 100644 index 0000000000..72953fd2c2 --- /dev/null +++ b/src/mainboard/lenovo/z61t/thermal.h @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. + * Copyright (C) 2014 Vladimir Serbinenko + * Copyright (C) 2016 Patrick Rudolph + * Copyright (C) 2017 James Ye + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef MAINBOARD_THERMAL_H +#define MAINBOARD_THERMAL_H + +/* Temperature which OS will shutdown at */ +#define CRITICAL_TEMPERATURE 100 + +/* Temperature which OS will throttle CPU */ +#define PASSIVE_TEMPERATURE 90 + +#endif /* MAINBOARD_THERMAL_H */ From c752c500fbcc055e8cdfb30a2e523e8a9349b79f Mon Sep 17 00:00:00 2001 From: Iru Cai Date: Wed, 16 Jan 2019 18:31:08 +0800 Subject: [PATCH 185/331] Documentation: Add HP EliteBook 8760w Also add the HP EliteBook document from wiki. Change-Id: I189db9c279705af53d82af66d0c2e8afb6f84d73 Signed-off-by: Iru Cai Reviewed-on: https://review.coreboot.org/c/coreboot/+/30950 Reviewed-by: Patrick Georgi Tested-by: build bot (Jenkins) --- Documentation/mainboard/hp/8760w.md | 82 +++++++++++++ Documentation/mainboard/hp/8760w_flash.jpg | Bin 0 -> 55849 bytes .../mainboard/hp/elitebook_series.md | 111 ++++++++++++++++++ Documentation/mainboard/index.md | 5 + 4 files changed, 198 insertions(+) create mode 100644 Documentation/mainboard/hp/8760w.md create mode 100644 Documentation/mainboard/hp/8760w_flash.jpg create mode 100644 Documentation/mainboard/hp/elitebook_series.md diff --git a/Documentation/mainboard/hp/8760w.md b/Documentation/mainboard/hp/8760w.md new file mode 100644 index 0000000000..714745aa04 --- /dev/null +++ b/Documentation/mainboard/hp/8760w.md @@ -0,0 +1,82 @@ +# HP EliteBook 8760w + +This page describes how to run coreboot on the [HP EliteBook 8760w]. + +## Flashing coreboot + +```eval_rst ++---------------------+------------+ +| Type | Value | ++=====================+============+ +| Socketed flash | no | ++---------------------+------------+ +| Model | W25Q64.V | ++---------------------+------------+ +| Size | 8 MiB | ++---------------------+------------+ +| Package | SOIC-8 | ++---------------------+------------+ +| Write protection | no | ++---------------------+------------+ +| Dual BIOS feature | no | ++---------------------+------------+ +| In circuit flashing | yes | ++---------------------+------------+ +| Internal flashing | yes | ++---------------------+------------+ +``` + +## Required proprietary blobs + +- Intel Firmware Descriptor, ME and GbE firmware +- EC: please read [EliteBook Series](elitebook_series) + +## Flashing instructions + +HP EliteBook 8760w has an 8MB SOIC-8 flash chip on the bottom of the +mainboard. You just need to remove the service cover, and use an SOIC-8 +clip to read and flash the chip. + +![8760w_chip_location](8760w_flash.jpg) + +## Untested + +- dock: serial port, parallel port, ... +- TPM +- S3 suspend/resume +- Gigabit Ethernet + +## Working + +- i7-2630QM, 0+4G+8G+0 +- i7-3720QM, 8G+8G+8G+8G +- Arch Linux boot from SeaBIOS payload +- EHCI debug: the port is at the right side, next to the charging port +- SATA +- eSATA +- USB2 and USB3 +- keyboard, touchpad, trackpad +- WLAN +- WWAN +- EC ACPI +- Using `me_cleaner` + +## Technology + +```eval_rst ++------------------+--------------------------------------------------+ +| Northbridge | :doc:`../../northbridge/intel/sandybridge/index` | ++------------------+--------------------------------------------------+ +| Southbridge | bd82x6x | ++------------------+--------------------------------------------------+ +| CPU | model_206ax | ++------------------+--------------------------------------------------+ +| Super I/O | SMSC LPC47n217 | ++------------------+--------------------------------------------------+ +| EC | SMSC KBC1126 | ++------------------+--------------------------------------------------+ +| Coprocessor | Intel Management Engine | ++------------------+--------------------------------------------------+ +``` + +[HP EliteBook 8760w]: https://support.hp.com/us-en/product/hp-elitebook-8760w-mobile-workstation/5071180 diff --git a/Documentation/mainboard/hp/8760w_flash.jpg b/Documentation/mainboard/hp/8760w_flash.jpg new file mode 100644 index 0000000000000000000000000000000000000000..d9bbac6788a3982c01dbda568b58ab8eade72726 GIT binary patch literal 55849 zcmbTdbzB_H(=WP4V-QC@S=5Bt^^Pczp+m91|LFb~my%IXCSzq}VP@n8 zurjmo@G`UTvT%~IvhcEV^0ILO2mxt<|9FW8ZY}d)j0eW#VgGmlZV*8AFaFyrAQlz? z1!l~wtjv(H|9DIWmP7rE*})hX_m2+nZxrze|9AwJL&X2nmogYb{wvo4W7zorju!r3 zj0Wxl;a`0tuug0|1OOH+vjpR~f3YJN$N!5x!5EP9uWu~O%)p%gZWAKspHX854>jb! zSQy*^Zr(pSe@%h;u>bM%?}$Sb{38cL0ObF`(EkI&{15zB@2?#?n1;Y)3a0-x+8ku8 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100644 index 0000000000..6668928008 --- /dev/null +++ b/Documentation/mainboard/hp/elitebook_series.md @@ -0,0 +1,111 @@ +# HP EliteBook series + +This document is about HP EliteBook series laptops up to Ivy Bridge era +which use SMSC KBC1126 as embedded controller. + +## EC + +SMSC KBC1098/KBC1126 has been used in HP EliteBooks for many generations. +They use similar EC firmware that will load other code and data from the +SPI flash chip, so we need to put some firmware blobs to the coreboot image. + +The following document takes EliteBook 2760p as an example. + +First, you need to extract the blobs needed by EC firmware using util/kbc1126. +You can extract them from your backup firmware image, or firmware update +provided by HP with [unar] as follows: + +```bash +wget https://ftp.hp.com/pub/softpaq/sp79501-80000/sp79710.exe +unar sp79710.exe +${COREBOOT_DIR}/util/kbc1126/kbc1126_ec_dump sp79710/Rompaq/68SOU.BIN +mv 68SOU.BIN.fw1 ${COREBOOT_DIR}/2760p-fw1.bin +mv 68SOU.BIN.fw2 ${COREBOOT_DIR}/2760p-fw2.bin +``` + +When you config coreboot, select: + +```text +Chipset ---> + [*] Add firmware images for KBC1126 EC + (2760p-fw1.bin) KBC1126 firmware #1 path and filename + (2760p-fw2.bin) KBC1126 filename #2 path and filename +``` + +## Super I/O + +EliteBook 8000 series laptops have SMSC LPC47n217 Super I/O to provide +a serial port and a parallel port, you can debug the laptop via this +serial port. + +## porting + +To port coreboot to an HP EliteBook laptop, you need to do the following: + +- select Kconfig option `EC_HP_KBC1126` +- select Kconfig option `SUPERIO_SMSC_LPC47N217` if there is LPC47n217 Super I/O +- initialize EC and Super I/O in romstage +- add EC and Super I/O support to devicetree.cb + +To get the related values for EC in devicetree.cb, you need to extract the EFI +module EcThermalInit from the vendor UEFI firmware with [UEFITool]. Usually, +`ec_data_port`, `ec_cmd_port` and `ec_ctrl_reg` has the following values: + +- For xx60 series: 0x60, 0x64, 0xca +- For xx70 series: 0x62, 0x66, 0x81 + +You can use [radare2] and the following [r2pipe] Python script to find +these values from the EcThermalInit EFI module: + +```python +#!/usr/bin/env python + +# install radare2 and use `pip3 install --user r2pipe` to install r2pipe + +import r2pipe +import sys + +if len(sys.argv) < 2: + fn = "ecthermalinit.efi" +else: + fn = sys.argv[1] + +r2 = r2pipe.open(fn) +r2.cmd("aa") +entryf = r2.cmdj("pdfj") + +for insn in entryf["ops"]: + if "lea r8" in insn["opcode"]: + _callback = insn["ptr"] + break + +r2.cmd("af @ {}".format(_callback)) +callbackf_insns = r2.cmdj("pdfj @ {}".format(_callback))["ops"] + +def find_port(addr): + ops = r2.cmdj("pdfj @ {}".format(addr))["ops"] + for insn in ops: + if "lea r8d" in insn["opcode"]: + return insn["ptr"] + +ctrl_reg_found = False + +for i in range(0, len(callbackf_insns)): + if not ctrl_reg_found and "mov cl" in callbackf_insns[i]["opcode"]: + ctrl_reg_found = True + ctrl_reg = callbackf_insns[i]["ptr"] + print("ec_ctrl_reg = 0x%02x" % ctrl_reg) + cmd_port = find_port(callbackf_insns[i+1]["jump"]) + data_port = find_port(callbackf_insns[i+3]["jump"]) + print("ec_cmd_port = 0x%02x\nec_data_port = 0x%02x" % (cmd_port, data_port)) + + if "mov bl" in callbackf_insns[i]["opcode"]: + ctrl_value = callbackf_insns[i]["ptr"] + print("ec_fan_ctrl_value = 0x%02x" % ctrl_value) +``` + + +[unar]: https://theunarchiver.com/command-line +[UEFITool]: https://github.com/LongSoft/UEFITool +[radare2]: https://radare.org/ +[r2pipe]: https://github.com/radare/radare2-r2pipe diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md index 1494e06244..7e0dab2f4c 100644 --- a/Documentation/mainboard/index.md +++ b/Documentation/mainboard/index.md @@ -51,6 +51,11 @@ The boards in this section are not real mainboards, but emulators. - [Compaq 8200 Elite SFF](hp/compaq_8200_sff.md) +### EliteBook series + +- [EliteBook common](hp/elitebook_series.md) +- [EliteBook 8760w](hp/8760w.md) + ## Lenovo - [Mainboard codenames](lenovo/codenames.md) From 99e578e3c1697028957f25efc7c14d1cb4d405dc Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Tue, 15 Jan 2019 20:14:33 +0100 Subject: [PATCH 186/331] nb/intel/pineview: Move to C_ENVIRONMENT_BOOTBLOCK This adds a file i82801gx/bootblock_gcc.c since other targets that don't yet C_ENVIRONMENT_BOOTBLOCK still use the romcc compiled bootblock.c. Tested on Foxconn D41S. Change-Id: I7e74838b0d5e9c192082084cfd9821996f0e4c50 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/30939 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/cpu/intel/socket_FCBGA559/Kconfig | 7 +++ src/cpu/intel/socket_FCBGA559/Makefile.inc | 4 +- src/mainboard/foxconn/d41s/Makefile.inc | 2 + .../foxconn/d41s/{romstage.c => early_init.c} | 3 +- src/mainboard/intel/d510mo/Makefile.inc | 2 + .../intel/d510mo/{romstage.c => early_init.c} | 3 +- src/northbridge/intel/pineview/Kconfig | 1 + src/northbridge/intel/pineview/Makefile.inc | 2 + src/northbridge/intel/pineview/bootblock.c | 6 ++- src/northbridge/intel/pineview/pineview.h | 1 - src/northbridge/intel/pineview/romstage.c | 8 ---- src/southbridge/intel/i82801gx/Makefile.inc | 2 + .../intel/i82801gx/bootblock_gcc.c | 44 +++++++++++++++++++ 13 files changed, 71 insertions(+), 14 deletions(-) rename src/mainboard/foxconn/d41s/{romstage.c => early_init.c} (95%) rename src/mainboard/intel/d510mo/{romstage.c => early_init.c} (95%) create mode 100644 src/southbridge/intel/i82801gx/bootblock_gcc.c diff --git a/src/cpu/intel/socket_FCBGA559/Kconfig b/src/cpu/intel/socket_FCBGA559/Kconfig index b1b310d3cc..d3af4ca3cc 100644 --- a/src/cpu/intel/socket_FCBGA559/Kconfig +++ b/src/cpu/intel/socket_FCBGA559/Kconfig @@ -21,4 +21,11 @@ config DCACHE_RAM_SIZE hex default 0x4000 +config DCACHE_BSP_STACK_SIZE + hex + default 0x2000 + help + The amount of anticipated stack usage in CAR by bootblock and + other stages. + endif diff --git a/src/cpu/intel/socket_FCBGA559/Makefile.inc b/src/cpu/intel/socket_FCBGA559/Makefile.inc index 868f6e5608..c95e135bb5 100644 --- a/src/cpu/intel/socket_FCBGA559/Makefile.inc +++ b/src/cpu/intel/socket_FCBGA559/Makefile.inc @@ -8,7 +8,9 @@ subdirs-y += ../microcode subdirs-y += ../hyperthreading subdirs-y += ../speedstep -cpu_incs-y += $(src)/cpu/intel/car/non-evict/cache_as_ram.S +bootblock-y += ../car/bootblock.c +bootblock-y += ../car/non-evict/cache_as_ram.S + postcar-y += ../car/non-evict/exit_car.S romstage-y += ../car/romstage.c diff --git a/src/mainboard/foxconn/d41s/Makefile.inc b/src/mainboard/foxconn/d41s/Makefile.inc index f3d7e76263..057b5bfcd3 100644 --- a/src/mainboard/foxconn/d41s/Makefile.inc +++ b/src/mainboard/foxconn/d41s/Makefile.inc @@ -1,2 +1,4 @@ +romstage-y += early_init.c +bootblock-y += early_init.c ramstage-y += cstates.c romstage-y += gpio.c diff --git a/src/mainboard/foxconn/d41s/romstage.c b/src/mainboard/foxconn/d41s/early_init.c similarity index 95% rename from src/mainboard/foxconn/d41s/romstage.c rename to src/mainboard/foxconn/d41s/early_init.c index cdd12dc3ac..6568d96139 100644 --- a/src/mainboard/foxconn/d41s/romstage.c +++ b/src/mainboard/foxconn/d41s/early_init.c @@ -15,6 +15,7 @@ * GNU General Public License for more details. */ +#include #include #include #include @@ -23,7 +24,7 @@ #define SERIAL_DEV PNP_DEV(0x2e, IT8721F_SP1) -void mb_enable_lpc(void) +void bootblock_mainboard_early_init(void) { /* Disable Serial IRQ */ pci_write_config8(PCI_DEV(0, 0x1f, 0), SERIRQ_CNTL, 0xd0); diff --git a/src/mainboard/intel/d510mo/Makefile.inc b/src/mainboard/intel/d510mo/Makefile.inc index f3d7e76263..f87689b8a1 100644 --- a/src/mainboard/intel/d510mo/Makefile.inc +++ b/src/mainboard/intel/d510mo/Makefile.inc @@ -1,2 +1,4 @@ +bootblock-y += early_init.c +romstage-y += early_init.c ramstage-y += cstates.c romstage-y += gpio.c diff --git a/src/mainboard/intel/d510mo/romstage.c b/src/mainboard/intel/d510mo/early_init.c similarity index 95% rename from src/mainboard/intel/d510mo/romstage.c rename to src/mainboard/intel/d510mo/early_init.c index 024c3e10fe..2719e87fe6 100644 --- a/src/mainboard/intel/d510mo/romstage.c +++ b/src/mainboard/intel/d510mo/early_init.c @@ -14,6 +14,7 @@ * GNU General Public License for more details. */ +#include #include #include #include @@ -23,7 +24,7 @@ #define SERIAL_DEV PNP_DEV(0x4e, W83627THG_SP1) #define SUPERIO_DEV PNP_DEV(0x4e, 0) -void mb_enable_lpc(void) +void bootblock_mainboard_early_init(void) { /* Disable Serial IRQ */ pci_write_config8(PCI_DEV(0, 0x1f, 0), SERIRQ_CNTL, 0x00); diff --git a/src/northbridge/intel/pineview/Kconfig b/src/northbridge/intel/pineview/Kconfig index 1878cc4f38..2b4f502c61 100644 --- a/src/northbridge/intel/pineview/Kconfig +++ b/src/northbridge/intel/pineview/Kconfig @@ -33,6 +33,7 @@ config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy select SMM_TSEG select PARALLEL_MP select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM + select C_ENVIRONMENT_BOOTBLOCK config BOOTBLOCK_NORTHBRIDGE_INIT string diff --git a/src/northbridge/intel/pineview/Makefile.inc b/src/northbridge/intel/pineview/Makefile.inc index 90a9f48373..c72fe3ee57 100644 --- a/src/northbridge/intel/pineview/Makefile.inc +++ b/src/northbridge/intel/pineview/Makefile.inc @@ -16,6 +16,8 @@ ifeq ($(CONFIG_NORTHBRIDGE_INTEL_PINEVIEW),y) +bootblock-y += bootblock.c + ramstage-y += ram_calc.c ramstage-y += northbridge.c ramstage-y += gma.c diff --git a/src/northbridge/intel/pineview/bootblock.c b/src/northbridge/intel/pineview/bootblock.c index bd76fb933c..bd510b00ee 100644 --- a/src/northbridge/intel/pineview/bootblock.c +++ b/src/northbridge/intel/pineview/bootblock.c @@ -12,11 +12,13 @@ */ #include -#define PCIEXBAR 0x60 +#include +#include "pineview.h" + #define MMCONF_256_BUSSES 16 #define ENABLE 1 -static void bootblock_northbridge_init(void) +void bootblock_early_northbridge_init(void) { pci_io_write_config32(PCI_DEV(0,0,0), PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS | MMCONF_256_BUSSES | ENABLE); diff --git a/src/northbridge/intel/pineview/pineview.h b/src/northbridge/intel/pineview/pineview.h index 65d21cfb8d..f53ff17aa3 100644 --- a/src/northbridge/intel/pineview/pineview.h +++ b/src/northbridge/intel/pineview/pineview.h @@ -236,7 +236,6 @@ u32 decode_igd_gtt_size(const u32 gsm); u8 decode_pciebar(u32 *const base, u32 *const len); /* Mainboard romstage callback functions */ -void mb_enable_lpc(void); void get_mb_spd_addrmap(u8 *spd_addr_map); void mb_pirq_setup(void); /* optional */ diff --git a/src/northbridge/intel/pineview/romstage.c b/src/northbridge/intel/pineview/romstage.c index 41fb0f6720..8d7de45149 100644 --- a/src/northbridge/intel/pineview/romstage.c +++ b/src/northbridge/intel/pineview/romstage.c @@ -57,20 +57,12 @@ void mainboard_romstage_entry(unsigned long bist) if (bist == 0) enable_lapic(); - /* Disable watchdog timer */ - RCBA32(GCS) = RCBA32(GCS) | 0x20; - /* Enable GPIOs */ pci_write_config32(LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE | 1); pci_write_config8(LPC_DEV, GPIO_CNTL, 0x10); setup_pch_gpios(&mainboard_gpio_map); - mb_enable_lpc(); // nm10_enable_lpc - - /* Initialize console device(s) */ - console_init(); - /* Halt if there was a built in self test failure */ report_bist_failure(bist); diff --git a/src/southbridge/intel/i82801gx/Makefile.inc b/src/southbridge/intel/i82801gx/Makefile.inc index 32a4bf5333..6e7f9bf945 100644 --- a/src/southbridge/intel/i82801gx/Makefile.inc +++ b/src/southbridge/intel/i82801gx/Makefile.inc @@ -15,6 +15,8 @@ ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_I82801GX),y) +bootblock-y += bootblock_gcc.c + ramstage-y += i82801gx.c ramstage-y += ac97.c ramstage-y += azalia.c diff --git a/src/southbridge/intel/i82801gx/bootblock_gcc.c b/src/southbridge/intel/i82801gx/bootblock_gcc.c new file mode 100644 index 0000000000..996788888a --- /dev/null +++ b/src/southbridge/intel/i82801gx/bootblock_gcc.c @@ -0,0 +1,44 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Sven Schnelle + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include "i82801gx.h" + +static void enable_spi_prefetch(void) +{ + u8 reg8; + pci_devfn_t dev = PCI_DEV(0, 0x1f, 0); + + reg8 = pci_read_config8(dev, BIOS_CNTL); + reg8 &= ~(3 << 2); + reg8 |= (2 << 2); /* Prefetching and Caching Enabled */ + pci_write_config8(dev, BIOS_CNTL, reg8); +} + +void bootblock_early_southbridge_init(void) +{ + enable_spi_prefetch(); + + /* Enable RCBA */ + pci_devfn_t lpc_dev = PCI_DEV(0, 0x1f, 0); + pci_write_config32(lpc_dev, RCBA, (uintptr_t)DEFAULT_RCBA | 1); + + /* Enable upper 128bytes of CMOS */ + RCBA32(0x3400) = (1 << 2); + + /* Disable watchdog timer */ + RCBA32(GCS) = RCBA32(GCS) | 0x20; +} From d3872fcad91a97a8c0582381d1cc9745ccee5494 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Fri, 24 May 2019 17:54:29 +0200 Subject: [PATCH 187/331] superio/fintek/f71863fg: Remove variable set but not used Change-Id: I993055d237b2bd607822485d34d5508c74a7744c Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/32990 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held --- src/superio/fintek/f71863fg/superio.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/src/superio/fintek/f71863fg/superio.c b/src/superio/fintek/f71863fg/superio.c index 634888b217..a5cd632e49 100644 --- a/src/superio/fintek/f71863fg/superio.c +++ b/src/superio/fintek/f71863fg/superio.c @@ -23,15 +23,13 @@ static void f71863fg_init(struct device *dev) { - struct resource *res0; - if (!dev->enabled) return; switch (dev->path.pnp.device) { /* TODO: Might potentially need code for HWM or FDC etc. */ case F71863FG_KBC: - res0 = find_resource(dev, PNP_IDX_IO0); + find_resource(dev, PNP_IDX_IO0); pc_keyboard_init(NO_AUX_DEVICE); break; } From 82882288c9732aae9ba4baf7ff2916a886499ba2 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Sat, 25 May 2019 19:06:43 +0200 Subject: [PATCH 188/331] nb/intel/pineview: Use MTRR as a proxy for proper reset On reset this platform can sometimes hang. This also fixes pineview mainboards not building due to the symbol 'check_mtrr' lacking. Change-Id: I61fe77113004ea664522bda549240a33e3742a98 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/33010 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: HAOUAS Elyes --- src/northbridge/intel/pineview/Makefile.inc | 1 + 1 file changed, 1 insertion(+) diff --git a/src/northbridge/intel/pineview/Makefile.inc b/src/northbridge/intel/pineview/Makefile.inc index c72fe3ee57..2d166138b6 100644 --- a/src/northbridge/intel/pineview/Makefile.inc +++ b/src/northbridge/intel/pineview/Makefile.inc @@ -16,6 +16,7 @@ ifeq ($(CONFIG_NORTHBRIDGE_INTEL_PINEVIEW),y) +bootblock-y += ../../../cpu/x86/early_reset.S bootblock-y += bootblock.c ramstage-y += ram_calc.c From 7ae606f57f0b3d450ae748141b0e2367041b27d3 Mon Sep 17 00:00:00 2001 From: Paul Menzel Date: Wed, 22 May 2019 19:19:15 +0200 Subject: [PATCH 189/331] libpayload: Reset PS/2 keyboard MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Loading a libpayload based payload like coreinfo or FILO from SeaBIOS or GRUB pressing keys does not give the expected results. For example, pressing F1 gives the character 24 translated to scan code 6a. ESC for example 43 (111) in coreinfo loaded from SeaBIOS on QEMU Q35. The problem is not reproducible using the payload directly, that means without SeaBIOS or GRUB. The problem seems to be, that those have already initialized the PS/2 controller and AT keyboard. Comparing it with coreboot’s PS/2 keyboard code, the keyboard needs to be reset. That seems to fix the issue, when the keyboard was initialized before. TEST=Build coreboot for QEMU Q35 with SeaBIOS, and coreinfo as secondary payload. Run qemu-system-i386 -M q35 -L /dev/shm -bios build/coreboot.rom -serial stdio press 3 to select the coreinfo payload, and verify that the keys F1 and F2 are working. Same with coreinfo loaded from GRUB on the ASRock E350M1. Change-Id: I2732292ac316d4bc0029ecb5c95fa7d1e7d68947 Signed-off-by: Paul Menzel Reviewed-on: https://review.coreboot.org/c/coreboot/+/32951 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- payloads/libpayload/drivers/i8042/i8042.h | 1 + payloads/libpayload/drivers/i8042/keyboard.c | 7 +++++++ 2 files changed, 8 insertions(+) diff --git a/payloads/libpayload/drivers/i8042/i8042.h b/payloads/libpayload/drivers/i8042/i8042.h index 643167ef40..e864ac9263 100644 --- a/payloads/libpayload/drivers/i8042/i8042.h +++ b/payloads/libpayload/drivers/i8042/i8042.h @@ -63,6 +63,7 @@ #define I8042_KBCMD_EN 0xf4 #define I8042_KBCMD_DEFAULT_DIS 0xf5 #define I8042_KBCMD_SET_DEFAULT 0xf6 +#define I8042_KBCMD_ACK 0xfa #define I8042_KBCMD_RESEND 0xfe #define I8042_KBCMD_RESET 0xff diff --git a/payloads/libpayload/drivers/i8042/keyboard.c b/payloads/libpayload/drivers/i8042/keyboard.c index cded638380..fea9e718dd 100644 --- a/payloads/libpayload/drivers/i8042/keyboard.c +++ b/payloads/libpayload/drivers/i8042/keyboard.c @@ -317,6 +317,13 @@ void keyboard_init(void) /* Enable first PS/2 port */ i8042_cmd(I8042_CMD_EN_KB); + /* Reset keyboard and self test (keyboard side) */ + ret = keyboard_cmd(I8042_KBCMD_RESET); + if (ret != I8042_KBCMD_ACK) { + printf("ERROR: Keyboard reset failed ACK: 0x%x\n", ret); + return; + } + /* Set scancode set 1 */ ret = keyboard_cmd(I8042_KBCMD_SET_SCANCODE); if (!ret && !CONFIG(LP_PC_KEYBOARD_IGNORE_INIT_FAILURE)) From 1f925b15ae65ae4789b2ae1dd2ef8b4bbdc4e9f1 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Thu, 23 May 2019 14:37:40 +0200 Subject: [PATCH 190/331] drivers/intel/fsp1.1: Remove stale comment on bootflow This list is incorrect and not up to date. The FSP1.1 romstage bootflow is unnecessarily clumsy and instead of trying to update this comment effort is better spend making the bootflow more streamlined. Change-Id: If1e4c462acd0748f072f33e6397a7b43f3bfc834 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/32959 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Frans Hendriks --- .../intel/fsp1_1/include/fsp/romstage.h | 35 ------------------- 1 file changed, 35 deletions(-) diff --git a/src/drivers/intel/fsp1_1/include/fsp/romstage.h b/src/drivers/intel/fsp1_1/include/fsp/romstage.h index de37950887..6ddafd858b 100644 --- a/src/drivers/intel/fsp1_1/include/fsp/romstage.h +++ b/src/drivers/intel/fsp1_1/include/fsp/romstage.h @@ -42,41 +42,6 @@ struct romstage_params { const void *data_to_save; }; -/* - * FSP Boot Flow: - * 1. src/cpu/x86/16bit/reset.inc - * 2. src/cpu/x86/16bit/entry.inc - * 3. other modules - * 4. src/drivers/intel/fsp1_1/cache_as_ram.inc - * 5. src/drivers/intel/fsp1_1/fsp_util.c/find_fsp - * 6. FSP binary/TempRamInit - * 7. src/drivers/intel/fsp1_1/cache_as_ram.inc - return - * 8. src/soc/intel/common/romstage.c/romstage_main - * 9 src/soc/.../romstage/.../soc_pre_console_init - * 10 src/console/console.c/console_init - * 11 src/soc/.../romstage/.../soc_romstage_init - * 12. src/mainboard/.../romstage.c/mainboard_romstage_entry - * 13. src/soc/intel/common/romstage.c/romstage_common - * 14 src/soc/.../romstage/.../soc_pre_raminit - * 15. FSP binary/MemoryInit - * 16. src/soc/intel/common/romstage.c/romstage_common - return - * 17. src/mainboard/.../romstage.c/mainboard_romstage_entry - return - * 18. src/soc/intel/common/romstage.c/romstage_main - return - * 19. src/soc/intel/common/stack.c/setup_stack_and_mtrrs - * 20. src/drivers/intel/fsp1_1/cache_as_ram.inc - return, cleanup - * after call to romstage_main - * 21. FSP binary/TempRamExit - * 22. src/soc/intel/common/romstage.c/romstage_after_car - * 23. FSP binary/SiliconInit - * 24. src/soc/intel/common/romstage.c/romstage_after_car - return - * 25. src/drivers/intel/fsp1_1/fsp_util.c/fsp_notify_boot_state_callback - * 26. src/drivers/intel/fsp1_1/fsp_util.c/fsp_notify - * 27. FSP binary/FspNotify - * 28. src/drivers/intel/fsp1_1/fsp_util.c/fsp_notify_boot_state_callback - * 29. src/drivers/intel/fsp1_1/fsp_util.c/fsp_notify - * 30. FSP binary/FspNotify - */ - void mainboard_memory_init_params(struct romstage_params *params, MEMORY_INIT_UPD *memory_params); void mainboard_romstage_entry(struct romstage_params *params); From 16d635c82c7de67c440ef17b3e5efdc36d17bb4a Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Thu, 23 May 2019 14:43:13 +0200 Subject: [PATCH 191/331] drivers/intel/fsp1.1: Remove unused function MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This function is unused since POSTCAR_STAGE is used. (be291e8 soc/intel/fsp1.1: Implement postcar stage) Change-Id: Ia9ff5236295a0e1c4f7634d27cf0ae1d87029678 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/32960 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Kyösti Mälkki Reviewed-by: Frans Hendriks --- src/drivers/intel/fsp1_1/include/fsp/romstage.h | 1 - src/drivers/intel/fsp1_1/romstage.c | 7 ------- 2 files changed, 8 deletions(-) diff --git a/src/drivers/intel/fsp1_1/include/fsp/romstage.h b/src/drivers/intel/fsp1_1/include/fsp/romstage.h index 6ddafd858b..7efbb1085c 100644 --- a/src/drivers/intel/fsp1_1/include/fsp/romstage.h +++ b/src/drivers/intel/fsp1_1/include/fsp/romstage.h @@ -55,7 +55,6 @@ void romstage_common(struct romstage_params *params); asmlinkage void romstage_main(FSP_INFO_HEADER *fih); /* Initialize memory margin analysis settings. */ void setup_mma(MEMORY_INIT_UPD *memory_upd); -void *setup_stack_and_mtrrs(void); void soc_after_ram_init(struct romstage_params *params); void soc_display_memory_init_params(const MEMORY_INIT_UPD *old, MEMORY_INIT_UPD *new); diff --git a/src/drivers/intel/fsp1_1/romstage.c b/src/drivers/intel/fsp1_1/romstage.c index 40c598877f..85badced89 100644 --- a/src/drivers/intel/fsp1_1/romstage.c +++ b/src/drivers/intel/fsp1_1/romstage.c @@ -326,13 +326,6 @@ __weak void report_memory_config(void) { } -/* Choose top of stack and setup MTRRs */ -__weak void *setup_stack_and_mtrrs(void) -{ - die("ERROR - Must specify top of stack!\n"); - return NULL; -} - /* SOC initialization after RAM is enabled */ __weak void soc_after_ram_init(struct romstage_params *params) { From 608d73e4c50334e00e7543572eeb356d7b3325f5 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Wed, 9 Jan 2019 21:19:48 +0100 Subject: [PATCH 192/331] src/drivers/intel/fsp1_0: Move PLATFORM_USES_FSP1_0 drivers/intel/fsp1_0/Kconfig is a better location than cpu/x86/Kconfig. Change-Id: Ic1c86c26a66c33760484bb6a86e9763c148a7c96 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/30791 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/cpu/x86/Kconfig | 7 ------- src/drivers/intel/fsp1_0/Kconfig | 7 +++++++ 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig index 232fe63f32..608afd7a28 100644 --- a/src/cpu/x86/Kconfig +++ b/src/cpu/x86/Kconfig @@ -151,13 +151,6 @@ config X86_AMD_FIXED_MTRRS This option informs the MTRR code to use the RdMem and WrMem fields in the fixed MTRR MSRs. -config PLATFORM_USES_FSP1_0 - bool - default n - help - Selected for Intel processors/platform combinations that use the - Intel Firmware Support Package (FSP) 1.0 for initialization. - config MIRROR_PAYLOAD_TO_RAM_BEFORE_LOADING def_bool n help diff --git a/src/drivers/intel/fsp1_0/Kconfig b/src/drivers/intel/fsp1_0/Kconfig index 4ce528fb77..361dd5ea85 100644 --- a/src/drivers/intel/fsp1_0/Kconfig +++ b/src/drivers/intel/fsp1_0/Kconfig @@ -13,6 +13,13 @@ ## GNU General Public License for more details. ## +config PLATFORM_USES_FSP1_0 + bool + default n + help + Selected for Intel processors/platform combinations that use the + Intel Firmware Support Package (FSP) 1.0 for initialization. + if PLATFORM_USES_FSP1_0 comment "Intel FSP" From 548f33a9f4a7675c42822516c285bdf2c8bb64de Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Tue, 15 May 2018 16:34:50 +0200 Subject: [PATCH 193/331] sb/intel/ibexpeak: Use common Intel SMM code TODO in followup patch: Some not mainboard specific things should be moved out of mainboard_smi_apmc. Change-Id: Ifc2d8f7755ace598e66b162d071d472093e4656e Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/26296 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph --- src/mainboard/lenovo/x201/smihandler.c | 2 +- src/mainboard/packardbell/ms2290/smihandler.c | 2 +- src/southbridge/intel/ibexpeak/Kconfig | 1 + src/southbridge/intel/ibexpeak/Makefile.inc | 1 - src/southbridge/intel/ibexpeak/pch.h | 1 - src/southbridge/intel/ibexpeak/smi.c | 347 --------- src/southbridge/intel/ibexpeak/smihandler.c | 698 +----------------- 7 files changed, 18 insertions(+), 1034 deletions(-) delete mode 100644 src/southbridge/intel/ibexpeak/smi.c diff --git a/src/mainboard/lenovo/x201/smihandler.c b/src/mainboard/lenovo/x201/smihandler.c index e733b3b5fe..fc6a0e9670 100644 --- a/src/mainboard/lenovo/x201/smihandler.c +++ b/src/mainboard/lenovo/x201/smihandler.c @@ -19,7 +19,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/src/mainboard/packardbell/ms2290/smihandler.c b/src/mainboard/packardbell/ms2290/smihandler.c index ff13543cde..83562be921 100644 --- a/src/mainboard/packardbell/ms2290/smihandler.c +++ b/src/mainboard/packardbell/ms2290/smihandler.c @@ -18,9 +18,9 @@ #include #include #include -#include #include #include +#include #include #include #include diff --git a/src/southbridge/intel/ibexpeak/Kconfig b/src/southbridge/intel/ibexpeak/Kconfig index 4763133b80..85c89799e0 100644 --- a/src/southbridge/intel/ibexpeak/Kconfig +++ b/src/southbridge/intel/ibexpeak/Kconfig @@ -32,6 +32,7 @@ config SOUTH_BRIDGE_OPTIONS # dummy select SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ select SOUTHBRIDGE_INTEL_COMMON_SMBUS select SOUTHBRIDGE_INTEL_COMMON_SPI + select SOUTHBRIDGE_INTEL_COMMON_SMM select HAVE_USBDEBUG_OPTIONS select COMMON_FADT select ACPI_SATA_GENERATOR diff --git a/src/southbridge/intel/ibexpeak/Makefile.inc b/src/southbridge/intel/ibexpeak/Makefile.inc index 2fb371841a..24eac22b9f 100644 --- a/src/southbridge/intel/ibexpeak/Makefile.inc +++ b/src/southbridge/intel/ibexpeak/Makefile.inc @@ -35,7 +35,6 @@ ramstage-y += ../bd82x6x/me_status.c ramstage-$(CONFIG_ELOG) += ../bd82x6x/elog.c ramstage-y += madt.c -ramstage-y += smi.c smm-y += smihandler.c me.c ../bd82x6x/me_8.x.c ../bd82x6x/pch.c romstage-y += ../bd82x6x/early_usb.c early_smbus.c ../bd82x6x/early_me.c ../bd82x6x/me_status.c ../common/gpio.c early_thermal.c diff --git a/src/southbridge/intel/ibexpeak/pch.h b/src/southbridge/intel/ibexpeak/pch.h index 9b2dd8ac8e..90e7102ed2 100644 --- a/src/southbridge/intel/ibexpeak/pch.h +++ b/src/southbridge/intel/ibexpeak/pch.h @@ -61,7 +61,6 @@ int pch_silicon_revision(void); int pch_silicon_type(void); int pch_silicon_supported(int type, int rev); void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue); -void gpi_route_interrupt(u8 gpi, u8 mode); #if CONFIG(ELOG) void pch_log_state(void); #endif diff --git a/src/southbridge/intel/ibexpeak/smi.c b/src/southbridge/intel/ibexpeak/smi.c deleted file mode 100644 index 4c9f2ac26d..0000000000 --- a/src/southbridge/intel/ibexpeak/smi.c +++ /dev/null @@ -1,347 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#define __SIMPLE_DEVICE__ - -#include -#include -#include -#include -#include -#include -#include -#include -#include "pch.h" - -/* While we read PMBASE dynamically in case it changed, let's - * initialize it with a sane value - */ -static u16 pmbase = DEFAULT_PMBASE; - -/** - * @brief read and clear PM1_STS - * @return PM1_STS register - */ -static u16 reset_pm1_status(void) -{ - u16 reg16; - - reg16 = inw(pmbase + PM1_STS); - /* set status bits are cleared by writing 1 to them */ - outw(reg16, pmbase + PM1_STS); - - return reg16; -} - -static void dump_pm1_status(u16 pm1_sts) -{ - printk(BIOS_DEBUG, "PM1_STS: "); - if (pm1_sts & (1 << 15)) printk(BIOS_DEBUG, "WAK "); - if (pm1_sts & (1 << 14)) printk(BIOS_DEBUG, "PCIEXPWAK "); - if (pm1_sts & (1 << 11)) printk(BIOS_DEBUG, "PRBTNOR "); - if (pm1_sts & (1 << 10)) printk(BIOS_DEBUG, "RTC "); - if (pm1_sts & (1 << 8)) printk(BIOS_DEBUG, "PWRBTN "); - if (pm1_sts & (1 << 5)) printk(BIOS_DEBUG, "GBL "); - if (pm1_sts & (1 << 4)) printk(BIOS_DEBUG, "BM "); - if (pm1_sts & (1 << 0)) printk(BIOS_DEBUG, "TMROF "); - printk(BIOS_DEBUG, "\n"); -} - -/** - * @brief read and clear SMI_STS - * @return SMI_STS register - */ -static u32 reset_smi_status(void) -{ - u32 reg32; - - reg32 = inl(pmbase + SMI_STS); - /* set status bits are cleared by writing 1 to them */ - outl(reg32, pmbase + SMI_STS); - - return reg32; -} - -static void dump_smi_status(u32 smi_sts) -{ - printk(BIOS_DEBUG, "SMI_STS: "); - if (smi_sts & (1 << 26)) printk(BIOS_DEBUG, "SPI "); - if (smi_sts & (1 << 25)) printk(BIOS_DEBUG, "EL_SMI "); - if (smi_sts & (1 << 21)) printk(BIOS_DEBUG, "MONITOR "); - if (smi_sts & (1 << 20)) printk(BIOS_DEBUG, "PCI_EXP_SMI "); - if (smi_sts & (1 << 18)) printk(BIOS_DEBUG, "INTEL_USB2 "); - if (smi_sts & (1 << 17)) printk(BIOS_DEBUG, "LEGACY_USB2 "); - if (smi_sts & (1 << 16)) printk(BIOS_DEBUG, "SMBUS_SMI "); - if (smi_sts & (1 << 15)) printk(BIOS_DEBUG, "SERIRQ_SMI "); - if (smi_sts & (1 << 14)) printk(BIOS_DEBUG, "PERIODIC "); - if (smi_sts & (1 << 13)) printk(BIOS_DEBUG, "TCO "); - if (smi_sts & (1 << 12)) printk(BIOS_DEBUG, "DEVMON "); - if (smi_sts & (1 << 11)) printk(BIOS_DEBUG, "MCSMI "); - if (smi_sts & (1 << 10)) printk(BIOS_DEBUG, "GPI "); - if (smi_sts & (1 << 9)) printk(BIOS_DEBUG, "GPE0 "); - if (smi_sts & (1 << 8)) printk(BIOS_DEBUG, "PM1 "); - if (smi_sts & (1 << 6)) printk(BIOS_DEBUG, "SWSMI_TMR "); - if (smi_sts & (1 << 5)) printk(BIOS_DEBUG, "APM "); - if (smi_sts & (1 << 4)) printk(BIOS_DEBUG, "SLP_SMI "); - if (smi_sts & (1 << 3)) printk(BIOS_DEBUG, "LEGACY_USB "); - if (smi_sts & (1 << 2)) printk(BIOS_DEBUG, "BIOS "); - printk(BIOS_DEBUG, "\n"); -} - - -/** - * @brief read and clear GPE0_STS - * @return GPE0_STS register - */ -static u32 reset_gpe0_status(void) -{ - u32 reg32; - - reg32 = inl(pmbase + GPE0_STS); - /* set status bits are cleared by writing 1 to them */ - outl(reg32, pmbase + GPE0_STS); - - return reg32; -} - -static void dump_gpe0_status(u32 gpe0_sts) -{ - int i; - printk(BIOS_DEBUG, "GPE0_STS: "); - for (i=31; i>= 16; i--) { - if (gpe0_sts & (1 << i)) printk(BIOS_DEBUG, "GPIO%d ", (i-16)); - } - if (gpe0_sts & (1 << 14)) printk(BIOS_DEBUG, "USB4 "); - if (gpe0_sts & (1 << 13)) printk(BIOS_DEBUG, "PME_B0 "); - if (gpe0_sts & (1 << 12)) printk(BIOS_DEBUG, "USB3 "); - if (gpe0_sts & (1 << 11)) printk(BIOS_DEBUG, "PME "); - if (gpe0_sts & (1 << 10)) printk(BIOS_DEBUG, "EL_SCI/BATLOW "); - if (gpe0_sts & (1 << 9)) printk(BIOS_DEBUG, "PCI_EXP "); - if (gpe0_sts & (1 << 8)) printk(BIOS_DEBUG, "RI "); - if (gpe0_sts & (1 << 7)) printk(BIOS_DEBUG, "SMB_WAK "); - if (gpe0_sts & (1 << 6)) printk(BIOS_DEBUG, "TCO_SCI "); - if (gpe0_sts & (1 << 5)) printk(BIOS_DEBUG, "AC97 "); - if (gpe0_sts & (1 << 4)) printk(BIOS_DEBUG, "USB2 "); - if (gpe0_sts & (1 << 3)) printk(BIOS_DEBUG, "USB1 "); - if (gpe0_sts & (1 << 2)) printk(BIOS_DEBUG, "HOT_PLUG "); - if (gpe0_sts & (1 << 0)) printk(BIOS_DEBUG, "THRM "); - printk(BIOS_DEBUG, "\n"); -} - - -/** - * @brief read and clear ALT_GP_SMI_STS - * @return ALT_GP_SMI_STS register - */ -static u16 reset_alt_gp_smi_status(void) -{ - u16 reg16; - - reg16 = inl(pmbase + ALT_GP_SMI_STS); - /* set status bits are cleared by writing 1 to them */ - outl(reg16, pmbase + ALT_GP_SMI_STS); - - return reg16; -} - -static void dump_alt_gp_smi_status(u16 alt_gp_smi_sts) -{ - int i; - printk(BIOS_DEBUG, "ALT_GP_SMI_STS: "); - for (i=15; i>= 0; i--) { - if (alt_gp_smi_sts & (1 << i)) printk(BIOS_DEBUG, "GPI%d ", i); - } - printk(BIOS_DEBUG, "\n"); -} - - - -/** - * @brief read and clear TCOx_STS - * @return TCOx_STS registers - */ -static u32 reset_tco_status(void) -{ - u32 tcobase = pmbase + 0x60; - u32 reg32; - - reg32 = inl(tcobase + 0x04); - /* set status bits are cleared by writing 1 to them */ - outl(reg32 & ~(1 << 18), tcobase + 0x04); // Don't clear BOOT_STS before SECOND_TO_STS - if (reg32 & (1 << 18)) - outl(reg32 & (1 << 18), tcobase + 0x04); // clear BOOT_STS - - return reg32; -} - - -static void dump_tco_status(u32 tco_sts) -{ - printk(BIOS_DEBUG, "TCO_STS: "); - if (tco_sts & (1 << 20)) printk(BIOS_DEBUG, "SMLINK_SLV "); - if (tco_sts & (1 << 18)) printk(BIOS_DEBUG, "BOOT "); - if (tco_sts & (1 << 17)) printk(BIOS_DEBUG, "SECOND_TO "); - if (tco_sts & (1 << 16)) printk(BIOS_DEBUG, "INTRD_DET "); - if (tco_sts & (1 << 12)) printk(BIOS_DEBUG, "DMISERR "); - if (tco_sts & (1 << 10)) printk(BIOS_DEBUG, "DMISMI "); - if (tco_sts & (1 << 9)) printk(BIOS_DEBUG, "DMISCI "); - if (tco_sts & (1 << 8)) printk(BIOS_DEBUG, "BIOSWR "); - if (tco_sts & (1 << 7)) printk(BIOS_DEBUG, "NEWCENTURY "); - if (tco_sts & (1 << 3)) printk(BIOS_DEBUG, "TIMEOUT "); - if (tco_sts & (1 << 2)) printk(BIOS_DEBUG, "TCO_INT "); - if (tco_sts & (1 << 1)) printk(BIOS_DEBUG, "SW_TCO "); - if (tco_sts & (1 << 0)) printk(BIOS_DEBUG, "NMI2SMI "); - printk(BIOS_DEBUG, "\n"); -} - - - -/** - * @brief Set the EOS bit - */ -static void smi_set_eos(void) -{ - u8 reg8; - - reg8 = inb(pmbase + SMI_EN); - reg8 |= EOS; - outb(reg8, pmbase + SMI_EN); -} - -void southbridge_smm_init(void) -{ - u32 smi_en; - u16 pm1_en; - u32 gpe0_en; - -#if CONFIG(ELOG) - /* Log events from chipset before clearing */ - pch_log_state(); -#endif - - printk(BIOS_DEBUG, "Initializing southbridge SMI..."); - - pmbase = pci_read_config32(PCI_DEV(0, 0x1f, 0), - PMBASE) & 0xff80; - - printk(BIOS_SPEW, " ... pmbase = 0x%04x\n", pmbase); - - smi_en = inl(pmbase + SMI_EN); - if (smi_en & APMC_EN) { - printk(BIOS_INFO, "SMI# handler already enabled?\n"); - return; - } - - printk(BIOS_DEBUG, "\n"); - dump_smi_status(reset_smi_status()); - dump_pm1_status(reset_pm1_status()); - dump_gpe0_status(reset_gpe0_status()); - dump_alt_gp_smi_status(reset_alt_gp_smi_status()); - dump_tco_status(reset_tco_status()); - - /* Disable GPE0 PME_B0 */ - gpe0_en = inl(pmbase + GPE0_EN); - gpe0_en &= ~PME_B0_EN; - outl(gpe0_en, pmbase + GPE0_EN); - - pm1_en = 0; - pm1_en |= PWRBTN_EN; - pm1_en |= GBL_EN; - outw(pm1_en, pmbase + PM1_EN); - - /* Enable SMI generation: - * - on TCO events - * - on APMC writes (io 0xb2) - * - on writes to SLP_EN (sleep states) - * - on writes to GBL_RLS (bios commands) - * No SMIs: - * - on microcontroller writes (io 0x62/0x66) - */ - - smi_en = 0; /* reset SMI enables */ - -#if 0 - smi_en |= LEGACY_USB2_EN | LEGACY_USB_EN; -#endif - smi_en |= TCO_EN; - smi_en |= APMC_EN; -#if DEBUG_PERIODIC_SMIS - /* Set DEBUG_PERIODIC_SMIS in pch.h to debug using - * periodic SMIs. - */ - smi_en |= PERIODIC_EN; -#endif - smi_en |= SLP_SMI_EN; -#if 0 - smi_en |= BIOS_EN; -#endif - - /* The following need to be on for SMIs to happen */ - smi_en |= EOS | GBL_SMI_EN; - - outl(smi_en, pmbase + SMI_EN); -} - -void southbridge_trigger_smi(void) -{ - /** - * There are several methods of raising a controlled SMI# via - * software, among them: - * - Writes to io 0xb2 (APMC) - * - Writes to the Local Apic ICR with Delivery mode SMI. - * - * Using the local apic is a bit more tricky. According to - * AMD Family 11 Processor BKDG no destination shorthand must be - * used. - * The whole SMM initialization is quite a bit hardware specific, so - * I'm not too worried about the better of the methods at the moment - */ - - /* raise an SMI interrupt */ - printk(BIOS_SPEW, " ... raise SMI#\n"); - outb(0x00, 0xb2); -} - -void southbridge_clear_smi_status(void) -{ - /* Clear SMI status */ - reset_smi_status(); - - /* Clear PM1 status */ - reset_pm1_status(); - - /* Set EOS bit so other SMIs can occur. */ - smi_set_eos(); -} - -void smm_setup_structures(void *gnvs, void *tcg, void *smi1) -{ - /* - * Issue SMI to set the gnvs pointer in SMM. - * tcg and smi1 are unused. - * - * EAX = APM_CNT_GNVS_UPDATE - * EBX = gnvs pointer - * EDX = APM_CNT - */ - asm volatile ( - "outb %%al, %%dx\n\t" - : /* ignore result */ - : "a" (APM_CNT_GNVS_UPDATE), - "b" ((u32)gnvs), - "d" (APM_CNT) - ); -} diff --git a/src/southbridge/intel/ibexpeak/smihandler.c b/src/southbridge/intel/ibexpeak/smihandler.c index fabe1c41ba..dbc412c072 100644 --- a/src/southbridge/intel/ibexpeak/smihandler.c +++ b/src/southbridge/intel/ibexpeak/smihandler.c @@ -35,13 +35,7 @@ */ #include #include - -/* While we read PMBASE dynamically in case it changed, let's - * initialize it with a sane value - */ -static u16 pmbase = DEFAULT_PMBASE; - -static u8 smm_initialized = 0; +#include /* GNVS needs to be updated by an 0xEA PM Trap (B2) after it has been located * by coreboot. @@ -52,193 +46,6 @@ global_nvs_t *smm_get_gnvs(void) return gnvs; } -static void alt_gpi_mask(u16 clr, u16 set) -{ - u16 alt_gp = inw(pmbase + ALT_GP_SMI_EN); - alt_gp &= ~clr; - alt_gp |= set; - outw(alt_gp, pmbase + ALT_GP_SMI_EN); -} - -static void gpe0_mask(u32 clr, u32 set) -{ - u32 gpe0 = inl(pmbase + GPE0_EN); - gpe0 &= ~clr; - gpe0 |= set; - outl(gpe0, pmbase + GPE0_EN); -} - -void gpi_route_interrupt(u8 gpi, u8 mode) -{ - u32 gpi_rout; - if (gpi >= 16) - return; - - alt_gpi_mask(1 << gpi, 0); - gpe0_mask(1 << (gpi+16), 0); - - gpi_rout = pci_read_config32(PCI_DEV(0, 0x1f, 0), GPIO_ROUT); - gpi_rout &= ~(3 << (2 * gpi)); - gpi_rout |= ((mode & 3) << (2 * gpi)); - pci_write_config32(PCI_DEV(0, 0x1f, 0), GPIO_ROUT, gpi_rout); - - if (mode == GPI_IS_SCI) - gpe0_mask(0, 1 << (gpi+16)); - else if (mode == GPI_IS_SMI) - alt_gpi_mask(0, 1 << gpi); -} - -/** - * @brief read and clear PM1_STS - * @return PM1_STS register - */ -static u16 reset_pm1_status(void) -{ - u16 reg16; - - reg16 = inw(pmbase + PM1_STS); - /* set status bits are cleared by writing 1 to them */ - outw(reg16, pmbase + PM1_STS); - - return reg16; -} - -static void dump_pm1_status(u16 pm1_sts) -{ - printk(BIOS_SPEW, "PM1_STS: "); - if (pm1_sts & (1 << 15)) printk(BIOS_SPEW, "WAK "); - if (pm1_sts & (1 << 14)) printk(BIOS_SPEW, "PCIEXPWAK "); - if (pm1_sts & (1 << 11)) printk(BIOS_SPEW, "PRBTNOR "); - if (pm1_sts & (1 << 10)) printk(BIOS_SPEW, "RTC "); - if (pm1_sts & (1 << 8)) printk(BIOS_SPEW, "PWRBTN "); - if (pm1_sts & (1 << 5)) printk(BIOS_SPEW, "GBL "); - if (pm1_sts & (1 << 4)) printk(BIOS_SPEW, "BM "); - if (pm1_sts & (1 << 0)) printk(BIOS_SPEW, "TMROF "); - printk(BIOS_SPEW, "\n"); - int reg16 = inw(pmbase + PM1_EN); - printk(BIOS_SPEW, "PM1_EN: %x\n", reg16); -} - -/** - * @brief read and clear SMI_STS - * @return SMI_STS register - */ -static u32 reset_smi_status(void) -{ - u32 reg32; - - reg32 = inl(pmbase + SMI_STS); - /* set status bits are cleared by writing 1 to them */ - outl(reg32, pmbase + SMI_STS); - - return reg32; -} - -static void dump_smi_status(u32 smi_sts) -{ - printk(BIOS_DEBUG, "SMI_STS: "); - if (smi_sts & (1 << 26)) printk(BIOS_DEBUG, "SPI "); - if (smi_sts & (1 << 21)) printk(BIOS_DEBUG, "MONITOR "); - if (smi_sts & (1 << 20)) printk(BIOS_DEBUG, "PCI_EXP_SMI "); - if (smi_sts & (1 << 18)) printk(BIOS_DEBUG, "INTEL_USB2 "); - if (smi_sts & (1 << 17)) printk(BIOS_DEBUG, "LEGACY_USB2 "); - if (smi_sts & (1 << 16)) printk(BIOS_DEBUG, "SMBUS_SMI "); - if (smi_sts & (1 << 15)) printk(BIOS_DEBUG, "SERIRQ_SMI "); - if (smi_sts & (1 << 14)) printk(BIOS_DEBUG, "PERIODIC "); - if (smi_sts & (1 << 13)) printk(BIOS_DEBUG, "TCO "); - if (smi_sts & (1 << 12)) printk(BIOS_DEBUG, "DEVMON "); - if (smi_sts & (1 << 11)) printk(BIOS_DEBUG, "MCSMI "); - if (smi_sts & (1 << 10)) printk(BIOS_DEBUG, "GPI "); - if (smi_sts & (1 << 9)) printk(BIOS_DEBUG, "GPE0 "); - if (smi_sts & (1 << 8)) printk(BIOS_DEBUG, "PM1 "); - if (smi_sts & (1 << 6)) printk(BIOS_DEBUG, "SWSMI_TMR "); - if (smi_sts & (1 << 5)) printk(BIOS_DEBUG, "APM "); - if (smi_sts & (1 << 4)) printk(BIOS_DEBUG, "SLP_SMI "); - if (smi_sts & (1 << 3)) printk(BIOS_DEBUG, "LEGACY_USB "); - if (smi_sts & (1 << 2)) printk(BIOS_DEBUG, "BIOS "); - printk(BIOS_DEBUG, "\n"); -} - - -/** - * @brief read and clear GPE0_STS - * @return GPE0_STS register - */ -static u32 reset_gpe0_status(void) -{ - u32 reg32; - - reg32 = inl(pmbase + GPE0_STS); - /* set status bits are cleared by writing 1 to them */ - outl(reg32, pmbase + GPE0_STS); - - return reg32; -} - -static void dump_gpe0_status(u32 gpe0_sts) -{ - int i; - printk(BIOS_DEBUG, "GPE0_STS: "); - for (i=31; i>= 16; i--) { - if (gpe0_sts & (1 << i)) printk(BIOS_DEBUG, "GPIO%d ", (i-16)); - } - if (gpe0_sts & (1 << 14)) printk(BIOS_DEBUG, "USB4 "); - if (gpe0_sts & (1 << 13)) printk(BIOS_DEBUG, "PME_B0 "); - if (gpe0_sts & (1 << 12)) printk(BIOS_DEBUG, "USB3 "); - if (gpe0_sts & (1 << 11)) printk(BIOS_DEBUG, "PME "); - if (gpe0_sts & (1 << 10)) printk(BIOS_DEBUG, "BATLOW "); - if (gpe0_sts & (1 << 9)) printk(BIOS_DEBUG, "PCI_EXP "); - if (gpe0_sts & (1 << 8)) printk(BIOS_DEBUG, "RI "); - if (gpe0_sts & (1 << 7)) printk(BIOS_DEBUG, "SMB_WAK "); - if (gpe0_sts & (1 << 6)) printk(BIOS_DEBUG, "TCO_SCI "); - if (gpe0_sts & (1 << 5)) printk(BIOS_DEBUG, "AC97 "); - if (gpe0_sts & (1 << 4)) printk(BIOS_DEBUG, "USB2 "); - if (gpe0_sts & (1 << 3)) printk(BIOS_DEBUG, "USB1 "); - if (gpe0_sts & (1 << 2)) printk(BIOS_DEBUG, "SWGPE "); - if (gpe0_sts & (1 << 1)) printk(BIOS_DEBUG, "HOTPLUG "); - if (gpe0_sts & (1 << 0)) printk(BIOS_DEBUG, "THRM "); - printk(BIOS_DEBUG, "\n"); -} - - -/** - * @brief read and clear TCOx_STS - * @return TCOx_STS registers - */ -static u32 reset_tco_status(void) -{ - u32 tcobase = pmbase + 0x60; - u32 reg32; - - reg32 = inl(tcobase + 0x04); - /* set status bits are cleared by writing 1 to them */ - outl(reg32 & ~(1 << 18), tcobase + 0x04); // Don't clear BOOT_STS before SECOND_TO_STS - if (reg32 & (1 << 18)) - outl(reg32 & (1 << 18), tcobase + 0x04); // clear BOOT_STS - - return reg32; -} - - -static void dump_tco_status(u32 tco_sts) -{ - printk(BIOS_DEBUG, "TCO_STS: "); - if (tco_sts & (1 << 20)) printk(BIOS_DEBUG, "SMLINK_SLV "); - if (tco_sts & (1 << 18)) printk(BIOS_DEBUG, "BOOT "); - if (tco_sts & (1 << 17)) printk(BIOS_DEBUG, "SECOND_TO "); - if (tco_sts & (1 << 16)) printk(BIOS_DEBUG, "INTRD_DET "); - if (tco_sts & (1 << 12)) printk(BIOS_DEBUG, "DMISERR "); - if (tco_sts & (1 << 10)) printk(BIOS_DEBUG, "DMISMI "); - if (tco_sts & (1 << 9)) printk(BIOS_DEBUG, "DMISCI "); - if (tco_sts & (1 << 8)) printk(BIOS_DEBUG, "BIOSWR "); - if (tco_sts & (1 << 7)) printk(BIOS_DEBUG, "NEWCENTURY "); - if (tco_sts & (1 << 3)) printk(BIOS_DEBUG, "TIMEOUT "); - if (tco_sts & (1 << 2)) printk(BIOS_DEBUG, "TCO_INT "); - if (tco_sts & (1 << 1)) printk(BIOS_DEBUG, "SW_TCO "); - if (tco_sts & (1 << 0)) printk(BIOS_DEBUG, "NMI2SMI "); - printk(BIOS_DEBUG, "\n"); -} - int southbridge_io_trap_handler(int smif) { switch (smif) { @@ -256,53 +63,6 @@ int southbridge_io_trap_handler(int smif) return 0; } -/** - * @brief Set the EOS bit - */ -void southbridge_smi_set_eos(void) -{ - u8 reg8; - - reg8 = inb(pmbase + SMI_EN); - reg8 |= EOS; - outb(reg8, pmbase + SMI_EN); -} - -static void busmaster_disable_on_bus(int bus) -{ - int slot, func; - unsigned int val; - unsigned char hdr; - - for (slot = 0; slot < 0x20; slot++) { - for (func = 0; func < 8; func++) { - u32 reg32; - pci_devfn_t dev = PCI_DEV(bus, slot, func); - - val = pci_read_config32(dev, PCI_VENDOR_ID); - - if (val == 0xffffffff || val == 0x00000000 || - val == 0x0000ffff || val == 0xffff0000) - continue; - - /* Disable Bus Mastering for this one device */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 &= ~PCI_COMMAND_MASTER; - pci_write_config32(dev, PCI_COMMAND, reg32); - - /* If this is a bridge, then follow it. */ - hdr = pci_read_config8(dev, PCI_HEADER_TYPE); - hdr &= 0x7f; - if (hdr == PCI_HEADER_TYPE_BRIDGE || - hdr == PCI_HEADER_TYPE_CARDBUS) { - unsigned int buses; - buses = pci_read_config32(dev, PCI_PRIMARY_BUS); - busmaster_disable_on_bus((buses >> 8) & 0xff); - } - } - } -} - static void southbridge_gate_memory_reset_real(int offset, u16 use, u16 io, u16 lvl) { @@ -334,7 +94,7 @@ static void southbridge_gate_memory_reset_real(int offset, * Intel reference designs all use GPIO 60 but it is * not a requirement and boards could use a different pin. */ -static void southbridge_gate_memory_reset(void) +void southbridge_gate_memory_reset(void) { u16 gpiobase; @@ -354,377 +114,7 @@ static void southbridge_gate_memory_reset(void) gpiobase + GP_LVL); } -static void xhci_sleep(u8 slp_typ) -{ - u32 reg32, xhci_bar; - u16 reg16; - - switch (slp_typ) { - case ACPI_S3: - case ACPI_S4: - reg16 = pci_read_config16(PCH_XHCI_DEV, 0x74); - reg16 &= ~0x03UL; - pci_write_config32(PCH_XHCI_DEV, 0x74, reg16); - - reg32 = pci_read_config32(PCH_XHCI_DEV, PCI_COMMAND); - reg32 |= (PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); - pci_write_config32(PCH_XHCI_DEV, PCI_COMMAND, reg32); - - xhci_bar = pci_read_config32(PCH_XHCI_DEV, - PCI_BASE_ADDRESS_0) & ~0xFUL; - - if ((xhci_bar + 0x4C0) & 1) - pch_iobp_update(0xEC000082, ~0UL, (3 << 2)); - if ((xhci_bar + 0x4D0) & 1) - pch_iobp_update(0xEC000182, ~0UL, (3 << 2)); - if ((xhci_bar + 0x4E0) & 1) - pch_iobp_update(0xEC000282, ~0UL, (3 << 2)); - if ((xhci_bar + 0x4F0) & 1) - pch_iobp_update(0xEC000382, ~0UL, (3 << 2)); - - reg32 = pci_read_config32(PCH_XHCI_DEV, PCI_COMMAND); - reg32 &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); - pci_write_config32(PCH_XHCI_DEV, PCI_COMMAND, reg32); - - reg16 = pci_read_config16(PCH_XHCI_DEV, 0x74); - reg16 |= 0x03; - pci_write_config16(PCH_XHCI_DEV, 0x74, reg16); - break; - - case ACPI_S5: - reg16 = pci_read_config16(PCH_XHCI_DEV, 0x74); - reg16 |= ((1 << 8) | 0x03); - pci_write_config16(PCH_XHCI_DEV, 0x74, reg16); - break; - } -} - -static void southbridge_smi_sleep(void) -{ - u8 reg8; - u32 reg32; - u8 slp_typ; - u8 s5pwr = CONFIG_MAINBOARD_POWER_FAILURE_STATE; - - // save and recover RTC port values - u8 tmp70, tmp72; - tmp70 = inb(0x70); - tmp72 = inb(0x72); - get_option(&s5pwr, "power_on_after_fail"); - outb(tmp70, 0x70); - outb(tmp72, 0x72); - - /* First, disable further SMIs */ - reg8 = inb(pmbase + SMI_EN); - reg8 &= ~SLP_SMI_EN; - outb(reg8, pmbase + SMI_EN); - - /* Figure out SLP_TYP */ - reg32 = inl(pmbase + PM1_CNT); - printk(BIOS_SPEW, "SMI#: SLP = 0x%08x\n", reg32); - slp_typ = acpi_sleep_from_pm1(reg32); - - if (smm_get_gnvs()->xhci) - xhci_sleep(slp_typ); - - /* Do any mainboard sleep handling */ - mainboard_smi_sleep(slp_typ); - -#if CONFIG(ELOG_GSMI) - /* Log S3, S4, and S5 entry */ - if (slp_typ >= ACPI_S3) - elog_add_event_byte(ELOG_TYPE_ACPI_ENTER, slp_typ); -#endif - - /* Next, do the deed. - */ - - switch (slp_typ) { - case ACPI_S0: printk(BIOS_DEBUG, "SMI#: Entering S0 (On)\n"); break; - case ACPI_S1: printk(BIOS_DEBUG, "SMI#: Entering S1 (Assert STPCLK#)\n"); break; - case ACPI_S3: - printk(BIOS_DEBUG, "SMI#: Entering S3 (Suspend-To-RAM)\n"); - - /* Gate memory reset */ - southbridge_gate_memory_reset(); - - /* Invalidate the cache before going to S3 */ - wbinvd(); - break; - case ACPI_S4: printk(BIOS_DEBUG, "SMI#: Entering S4 (Suspend-To-Disk)\n"); break; - case ACPI_S5: - printk(BIOS_DEBUG, "SMI#: Entering S5 (Soft Power off)\n"); - - outl(0, pmbase + GPE0_EN); - - /* Always set the flag in case CMOS was changed on runtime. For - * "KEEP", switch to "OFF" - KEEP is software emulated - */ - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3); - if (s5pwr == MAINBOARD_POWER_ON) { - reg8 &= ~1; - } else { - reg8 |= 1; - } - pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3, reg8); - - /* also iterates over all bridges on bus 0 */ - busmaster_disable_on_bus(0); - break; - default: printk(BIOS_DEBUG, "SMI#: ERROR: SLP_TYP reserved\n"); break; - } - - /* Write back to the SLP register to cause the originally intended - * event again. We need to set BIT13 (SLP_EN) though to make the - * sleep happen. - */ - outl(reg32 | SLP_EN, pmbase + PM1_CNT); - - /* Make sure to stop executing code here for S3/S4/S5 */ - if (slp_typ >= ACPI_S3) - halt(); - - /* In most sleep states, the code flow of this function ends at - * the line above. However, if we entered sleep state S1 and wake - * up again, we will continue to execute code in this function. - */ - reg32 = inl(pmbase + PM1_CNT); - if (reg32 & SCI_EN) { - /* The OS is not an ACPI OS, so we set the state to S0 */ - reg32 &= ~(SLP_EN | SLP_TYP); - outl(reg32, pmbase + PM1_CNT); - } -} - -/* - * Look for Synchronous IO SMI and use save state from that - * core in case we are not running on the same core that - * initiated the IO transaction. - */ -static em64t101_smm_state_save_area_t *smi_apmc_find_state_save(u8 cmd) -{ - em64t101_smm_state_save_area_t *state; - int node; - - /* Check all nodes looking for the one that issued the IO */ - for (node = 0; node < CONFIG_MAX_CPUS; node++) { - state = smm_get_save_state(node); - - /* Check for Synchronous IO (bit0 == 1) */ - if (!(state->io_misc_info & (1 << 0))) - continue; - - /* Make sure it was a write (bit4 == 0) */ - if (state->io_misc_info & (1 << 4)) - continue; - - /* Check for APMC IO port */ - if (((state->io_misc_info >> 16) & 0xff) != APM_CNT) - continue; - - /* Check AX against the requested command */ - if ((state->rax & 0xff) != cmd) - continue; - - return state; - } - - return NULL; -} - -#if CONFIG(ELOG_GSMI) -static void southbridge_smi_gsmi(void) -{ - u32 *ret, *param; - u8 sub_command; - em64t101_smm_state_save_area_t *io_smi = - smi_apmc_find_state_save(APM_CNT_ELOG_GSMI); - - if (!io_smi) - return; - - /* Command and return value in EAX */ - ret = (u32*)&io_smi->rax; - sub_command = (u8)(*ret >> 8); - - /* Parameter buffer in EBX */ - param = (u32*)&io_smi->rbx; - - /* drivers/elog/gsmi.c */ - *ret = gsmi_exec(sub_command, param); -} -#endif - -static void southbridge_smi_apmc(void) -{ - u32 pmctrl; - u8 reg8; - em64t101_smm_state_save_area_t *state; - - /* Emulate B2 register as the FADT / Linux expects it */ - - reg8 = inb(APM_CNT); - switch (reg8) { - case APM_CNT_CST_CONTROL: - /* Calling this function seems to cause - * some kind of race condition in Linux - * and causes a kernel oops - */ - printk(BIOS_DEBUG, "C-state control\n"); - break; - case APM_CNT_PST_CONTROL: - /* Calling this function seems to cause - * some kind of race condition in Linux - * and causes a kernel oops - */ - printk(BIOS_DEBUG, "P-state control\n"); - break; - case APM_CNT_ACPI_DISABLE: - pmctrl = inl(pmbase + PM1_CNT); - pmctrl &= ~SCI_EN; - outl(pmctrl, pmbase + PM1_CNT); - printk(BIOS_DEBUG, "SMI#: ACPI disabled.\n"); - break; - case APM_CNT_ACPI_ENABLE: - pmctrl = inl(pmbase + PM1_CNT); - pmctrl |= SCI_EN; - outl(pmctrl, pmbase + PM1_CNT); - printk(BIOS_DEBUG, "SMI#: ACPI enabled.\n"); - break; - case APM_CNT_GNVS_UPDATE: - if (smm_initialized) { - printk(BIOS_DEBUG, "SMI#: SMM structures already initialized!\n"); - return; - } - state = smi_apmc_find_state_save(reg8); - if (state) { - /* EBX in the state save contains the GNVS pointer */ - gnvs = (global_nvs_t *)((u32)state->rbx); - smm_initialized = 1; - printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs); - } - break; -#if CONFIG(ELOG_GSMI) - case APM_CNT_ELOG_GSMI: - southbridge_smi_gsmi(); - break; -#endif - } - - mainboard_smi_apmc(reg8); -} - -static void southbridge_smi_pm1(void) -{ - u16 pm1_sts; - - pm1_sts = reset_pm1_status(); - dump_pm1_status(pm1_sts); - - /* While OSPM is not active, poweroff immediately - * on a power button event. - */ - if (pm1_sts & PWRBTN_STS) { - // power button pressed - u32 reg32; - reg32 = (7 << 10) | (1 << 13); -#if CONFIG(ELOG_GSMI) - elog_add_event(ELOG_TYPE_POWER_BUTTON); -#endif - outl(reg32, pmbase + PM1_CNT); - } -} - -static void southbridge_smi_gpe0(void) -{ - u32 gpe0_sts; - - gpe0_sts = reset_gpe0_status(); - dump_gpe0_status(gpe0_sts); -} - -static void southbridge_smi_gpi(void) -{ - u16 reg16; - reg16 = inw(pmbase + ALT_GP_SMI_STS); - outw(reg16, pmbase + ALT_GP_SMI_STS); - - reg16 &= inw(pmbase + ALT_GP_SMI_EN); - - mainboard_smi_gpi(reg16); - - if (reg16) - printk(BIOS_DEBUG, "GPI (mask %04x)\n",reg16); - - outw(reg16, pmbase + ALT_GP_SMI_STS); -} - -static void southbridge_smi_mc(void) -{ - u32 reg32; - - reg32 = inl(pmbase + SMI_EN); - - /* Are periodic SMIs enabled? */ - if ((reg32 & MCSMI_EN) == 0) - return; - - printk(BIOS_DEBUG, "Microcontroller SMI.\n"); -} - - - -static void southbridge_smi_tco(void) -{ - u32 tco_sts; - - tco_sts = reset_tco_status(); - - /* Any TCO event? */ - if (!tco_sts) - return; - - if (tco_sts & (1 << 8)) { // BIOSWR - u8 bios_cntl; - - bios_cntl = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0xdc); - - if (bios_cntl & 1) { - /* BWE is RW, so the SMI was caused by a - * write to BWE, not by a write to the BIOS - */ - - /* This is the place where we notice someone - * is trying to tinker with the BIOS. We are - * trying to be nice and just ignore it. A more - * resolute answer would be to power down the - * box. - */ - printk(BIOS_DEBUG, "Switching back to RO\n"); - pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xdc, (bios_cntl & ~1)); - } /* No else for now? */ - } else if (tco_sts & (1 << 3)) { /* TIMEOUT */ - /* Handle TCO timeout */ - printk(BIOS_DEBUG, "TCO Timeout.\n"); - } else { - dump_tco_status(tco_sts); - } -} - -static void southbridge_smi_periodic(void) -{ - u32 reg32; - - reg32 = inl(pmbase + SMI_EN); - - /* Are periodic SMIs enabled? */ - if ((reg32 & PERIODIC_EN) == 0) - return; - - printk(BIOS_DEBUG, "Periodic SMI.\n"); -} - -static void southbridge_smi_monitor(void) +void southbridge_smi_monitor(void) { #define IOTRAP(x) (trap_sts & (1 << x)) u32 trap_sts, trap_cycle; @@ -778,76 +168,18 @@ static void southbridge_smi_monitor(void) #undef IOTRAP } -typedef void (*smi_handler_t)(void); - -static smi_handler_t southbridge_smi[32] = { - NULL, // [0] reserved - NULL, // [1] reserved - NULL, // [2] BIOS_STS - NULL, // [3] LEGACY_USB_STS - southbridge_smi_sleep, // [4] SLP_SMI_STS - southbridge_smi_apmc, // [5] APM_STS - NULL, // [6] SWSMI_TMR_STS - NULL, // [7] reserved - southbridge_smi_pm1, // [8] PM1_STS - southbridge_smi_gpe0, // [9] GPE0_STS - southbridge_smi_gpi, // [10] GPI_STS - southbridge_smi_mc, // [11] MCSMI_STS - NULL, // [12] DEVMON_STS - southbridge_smi_tco, // [13] TCO_STS - southbridge_smi_periodic, // [14] PERIODIC_STS - NULL, // [15] SERIRQ_SMI_STS - NULL, // [16] SMBUS_SMI_STS - NULL, // [17] LEGACY_USB2_STS - NULL, // [18] INTEL_USB2_STS - NULL, // [19] reserved - NULL, // [20] PCI_EXP_SMI_STS - southbridge_smi_monitor, // [21] MONITOR_STS - NULL, // [22] reserved - NULL, // [23] reserved - NULL, // [24] reserved - NULL, // [25] EL_SMI_STS - NULL, // [26] SPI_STS - NULL, // [27] reserved - NULL, // [28] reserved - NULL, // [29] reserved - NULL, // [30] reserved - NULL // [31] reserved -}; - -/** - * @brief Interrupt handler for SMI# - * @param node - * @param state_save - */ -void southbridge_smi_handler(void) +void southbridge_update_gnvs(u8 apm_cnt, int *smm_done) { - int i, dump = 0; - u32 smi_sts; - - /* Update global variable pmbase */ - pmbase = lpc_get_pmbase(); - - /* We need to clear the SMI status registers, or we won't see what's - * happening in the following calls. - */ - smi_sts = reset_smi_status(); - - /* Call SMI sub handler for each of the status bits */ - for (i = 0; i < 31; i++) { - if (smi_sts & (1 << i)) { - if (southbridge_smi[i]) { - southbridge_smi[i](); - } else { - printk(BIOS_DEBUG, "SMI_STS[%d] occurred, but no " - "handler available.\n", i); - dump = 1; - } - } + em64t101_smm_state_save_area_t *state = + smi_apmc_find_state_save(apm_cnt); + if (state) { + /* EBX in the state save contains the GNVS pointer */ + gnvs = (global_nvs_t *)((u32)state->rbx); + *smm_done = 1; + printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs); } - - if (dump) { - dump_smi_status(smi_sts); - } - +} + +void southbridge_finalize_all(void) +{ } From b66ee5507c4c2395868a5cd350dc8a7eb46542fd Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Tue, 15 May 2018 16:35:45 +0200 Subject: [PATCH 194/331] cpu/intel/model_2065x: Use parallel MP init TESTED on Thinkpad X201 with a i7 CPU M620 CPU (hyperthread dual core). Boots ~28ms faster. Change-Id: I56b352f9d76ee58f5c82cd431a4e0fa206f848a0 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/26297 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph --- src/cpu/intel/model_2065x/Kconfig | 1 + src/cpu/intel/model_2065x/model_2065x.h | 1 + src/cpu/intel/model_2065x/model_2065x_init.c | 153 +++++++++---------- src/northbridge/intel/nehalem/northbridge.c | 2 +- 4 files changed, 73 insertions(+), 84 deletions(-) diff --git a/src/cpu/intel/model_2065x/Kconfig b/src/cpu/intel/model_2065x/Kconfig index ba2b7de74d..707713c697 100644 --- a/src/cpu/intel/model_2065x/Kconfig +++ b/src/cpu/intel/model_2065x/Kconfig @@ -20,6 +20,7 @@ config CPU_SPECIFIC_OPTIONS select TSC_SYNC_MFENCE select CPU_INTEL_COMMON select NO_FIXED_XIP_ROM_SIZE + select PARALLEL_MP config BOOTBLOCK_CPU_INIT string diff --git a/src/cpu/intel/model_2065x/model_2065x.h b/src/cpu/intel/model_2065x/model_2065x.h index 1e6a311910..904e794219 100644 --- a/src/cpu/intel/model_2065x/model_2065x.h +++ b/src/cpu/intel/model_2065x/model_2065x.h @@ -20,6 +20,7 @@ /* Nehalem bus clock is fixed at 133MHz */ #define NEHALEM_BCLK 133 +#define CORE_THREAD_COUNT_MSR 0x35 #define MSR_FEATURE_CONFIG 0x13c #define MSR_FLEX_RATIO 0x194 #define FLEX_RATIO_LOCK (1 << 20) diff --git a/src/cpu/intel/model_2065x/model_2065x_init.c b/src/cpu/intel/model_2065x/model_2065x_init.c index f08a058a57..d8de7c055f 100644 --- a/src/cpu/intel/model_2065x/model_2065x_init.c +++ b/src/cpu/intel/model_2065x/model_2065x_init.c @@ -15,6 +15,7 @@ * GNU General Public License for more details. */ +#include #include #include #include @@ -22,6 +23,7 @@ #include #include #include +#include #include #include #include @@ -109,29 +111,6 @@ static acpi_cstate_t cstate_map[] = { { 0 } }; -int cpu_get_apic_id_map(int *apic_id_map) -{ - int i; - struct cpuid_result result; - unsigned int threads_per_package, threads_per_core; - - /* Logical processors (threads) per core */ - result = cpuid_ext(0xb, 0); - threads_per_core = result.ebx & 0xffff; - - /* Logical processors (threads) per package */ - result = cpuid_ext(0xb, 1); - threads_per_package = result.ebx & 0xffff; - - for (i = 0; i < threads_per_package && i < CONFIG_MAX_CPUS; ++i) { - apic_id_map[i] = (i % threads_per_core) - + ((i / threads_per_core) << 2); - } - - return threads_per_package; -} - - int cpu_config_tdp_levels(void) { msr_t platform_info; @@ -250,58 +229,6 @@ static void configure_mca(void) wrmsr(IA32_MC0_STATUS + (i * 4), msr); } -/* - * Initialize any extra cores/threads in this package. - */ -static void intel_cores_init(struct device *cpu) -{ - struct cpuid_result result; - unsigned int threads_per_package, threads_per_core, i; - - /* Logical processors (threads) per core */ - result = cpuid_ext(0xb, 0); - threads_per_core = result.ebx & 0xffff; - - /* Logical processors (threads) per package */ - result = cpuid_ext(0xb, 1); - threads_per_package = result.ebx & 0xffff; - - /* Only initialize extra cores from BSP */ - if (cpu->path.apic.apic_id) - return; - - printk(BIOS_DEBUG, "CPU: %u has %u cores, %u threads per core\n", - cpu->path.apic.apic_id, threads_per_package/threads_per_core, - threads_per_core); - - for (i = 1; i < threads_per_package; ++i) { - struct device_path cpu_path; - struct device *new; - - /* Build the CPU device path */ - cpu_path.type = DEVICE_PATH_APIC; - cpu_path.apic.apic_id = - cpu->path.apic.apic_id + (i % threads_per_core) - + ((i / threads_per_core) << 2); - - /* Allocate the new CPU device structure */ - new = alloc_dev(cpu->bus, &cpu_path); - if (!new) - continue; - - printk(BIOS_DEBUG, "CPU: %u has core %u\n", - cpu->path.apic.apic_id, - new->path.apic.apic_id); - - /* Start the new CPU */ - if (is_smp_boot() && !start_cpu(new)) { - /* Record the error in cpu? */ - printk(BIOS_ERR, "CPU %u would not start!\n", - new->path.apic.apic_id); - } - } -} - static void model_2065x_init(struct device *cpu) { char processor_name[49]; @@ -309,8 +236,6 @@ static void model_2065x_init(struct device *cpu) /* Turn on caching if we haven't already */ x86_enable_cache(); - intel_update_microcode_from_cbfs(); - /* Clear out pending MCEs */ configure_mca(); @@ -320,10 +245,6 @@ static void model_2065x_init(struct device *cpu) printk(BIOS_INFO, "CPU:lapic=%ld, boot_cpu=%d\n", lapicid(), boot_cpu()); - /* Setup MTRRs based on physical address size */ - x86_setup_mtrrs_with_detect(); - x86_mtrr_check(); - /* Setup Page Attribute Tables (PAT) */ // TODO set up PAT @@ -348,9 +269,75 @@ static void model_2065x_init(struct device *cpu) /* Enable Turbo */ enable_turbo(); +} - /* Start up extra cores */ - intel_cores_init(cpu); +/* MP initialization support. */ +static const void *microcode_patch; + +static void pre_mp_init(void) +{ + /* Setup MTRRs based on physical address size. */ + x86_setup_mtrrs_with_detect(); + x86_mtrr_check(); +} + +static int get_cpu_count(void) +{ + msr_t msr; + int num_threads; + int num_cores; + + msr = rdmsr(CORE_THREAD_COUNT_MSR); + num_threads = (msr.lo >> 0) & 0xffff; + num_cores = (msr.lo >> 16) & 0xffff; + printk(BIOS_DEBUG, "CPU has %u cores, %u threads enabled.\n", + num_cores, num_threads); + + return num_threads; +} + +static void get_microcode_info(const void **microcode, int *parallel) +{ + microcode_patch = intel_microcode_find(); + *microcode = microcode_patch; + *parallel = 1; +} + +static void per_cpu_smm_trigger(void) +{ + /* Relocate the SMM handler. */ + smm_relocate(); + + /* After SMM relocation a 2nd microcode load is required. */ + intel_microcode_load_unlocked(microcode_patch); +} + +static void post_mp_init(void) +{ + /* Now that all APs have been relocated as well as the BSP let SMIs + * start flowing. */ + southbridge_smm_init(); + + /* Lock down the SMRAM space. */ + smm_lock(); +} + + +static const struct mp_ops mp_ops = { + .pre_mp_init = pre_mp_init, + .get_cpu_count = get_cpu_count, + .get_smm_info = smm_info, + .get_microcode_info = get_microcode_info, + .pre_mp_smm_init = smm_initialize, + .per_cpu_smm_trigger = per_cpu_smm_trigger, + .relocation_handler = smm_relocation_handler, + .post_mp_init = post_mp_init, +}; + +void bsp_init_and_start_aps(struct bus *cpu_bus) +{ + if (mp_init_with_smm(cpu_bus, &mp_ops)) + printk(BIOS_ERR, "MP initialization failure.\n"); } static struct device_operations cpu_dev_ops = { diff --git a/src/northbridge/intel/nehalem/northbridge.c b/src/northbridge/intel/nehalem/northbridge.c index a9032bafea..233b0bbd00 100644 --- a/src/northbridge/intel/nehalem/northbridge.c +++ b/src/northbridge/intel/nehalem/northbridge.c @@ -311,7 +311,7 @@ static const struct pci_driver mc_driver_44 __pci_driver = { static void cpu_bus_init(struct device *dev) { - initialize_cpus(dev->link_list); + bsp_init_and_start_aps(dev->link_list); } static struct device_operations cpu_bus_ops = { From 97c7c6bbb6c9dd2ef4f917c3c4c16a8ff0de5d9f Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Tue, 15 May 2018 16:45:21 +0200 Subject: [PATCH 195/331] cpu/intel/model_2065x: Put stage cache in TSEG TSEG is not accessible in ring 0 after it is locked in ramstage, in contrast with cbmem which remains accessible. Assuming SMM does not touch the cache this is a good region to cache stages. Change-Id: I89cbfb6ece62f554ac676fe686115e841d2c1e40 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/26298 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph --- src/cpu/intel/model_2065x/Kconfig | 5 ++++ src/cpu/intel/model_2065x/Makefile.inc | 4 +++ src/cpu/intel/model_2065x/model_2065x.h | 18 +++++++++++++ src/cpu/intel/model_2065x/stage_cache.c | 30 +++++++++++++++++++++ src/northbridge/intel/nehalem/northbridge.c | 7 ----- src/northbridge/intel/nehalem/ram_calc.c | 6 +++++ 6 files changed, 63 insertions(+), 7 deletions(-) create mode 100644 src/cpu/intel/model_2065x/stage_cache.c diff --git a/src/cpu/intel/model_2065x/Kconfig b/src/cpu/intel/model_2065x/Kconfig index 707713c697..d8c016867c 100644 --- a/src/cpu/intel/model_2065x/Kconfig +++ b/src/cpu/intel/model_2065x/Kconfig @@ -21,6 +21,7 @@ config CPU_SPECIFIC_OPTIONS select CPU_INTEL_COMMON select NO_FIXED_XIP_ROM_SIZE select PARALLEL_MP + select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM config BOOTBLOCK_CPU_INIT string @@ -30,4 +31,8 @@ config SMM_TSEG_SIZE hex default 0x800000 +config SMM_RESERVED_SIZE + hex + default 0x100000 + endif diff --git a/src/cpu/intel/model_2065x/Makefile.inc b/src/cpu/intel/model_2065x/Makefile.inc index 043141ac18..39246c0708 100644 --- a/src/cpu/intel/model_2065x/Makefile.inc +++ b/src/cpu/intel/model_2065x/Makefile.inc @@ -19,6 +19,10 @@ ramstage-y += acpi.c smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c +romstage-y += stage_cache.c +ramstage-y += stage_cache.c +postcar-y += stage_cache.c + cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_2065x/microcode.bin cpu_incs-y += $(src)/cpu/intel/car/non-evict/cache_as_ram.S diff --git a/src/cpu/intel/model_2065x/model_2065x.h b/src/cpu/intel/model_2065x/model_2065x.h index 904e794219..e7ba2a771b 100644 --- a/src/cpu/intel/model_2065x/model_2065x.h +++ b/src/cpu/intel/model_2065x/model_2065x.h @@ -80,4 +80,22 @@ void set_power_limits(u8 power_limit_1_time); int cpu_config_tdp_levels(void); #endif +/* + * Region of SMM space is reserved for multipurpose use. It falls below + * the IED region and above the SMM handler. + */ +#define RESERVED_SMM_SIZE CONFIG_SMM_RESERVED_SIZE +#define RESERVED_SMM_OFFSET (CONFIG_SMM_TSEG_SIZE - RESERVED_SMM_SIZE) + +/* Sanity check config options. */ +#if (CONFIG_SMM_TSEG_SIZE <= RESERVED_SMM_SIZE) +# error "CONFIG_SMM_TSEG_SIZE <= RESERVED_SMM_SIZE" +#endif +#if (CONFIG_SMM_TSEG_SIZE < 0x800000) +# error "CONFIG_SMM_TSEG_SIZE must at least be 8MiB" +#endif +#if ((CONFIG_SMM_TSEG_SIZE & (CONFIG_SMM_TSEG_SIZE - 1)) != 0) +# error "CONFIG_SMM_TSEG_SIZE is not a power of 2" +#endif + #endif diff --git a/src/cpu/intel/model_2065x/stage_cache.c b/src/cpu/intel/model_2065x/stage_cache.c new file mode 100644 index 0000000000..ab8ac979c1 --- /dev/null +++ b/src/cpu/intel/model_2065x/stage_cache.c @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 Google, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include "model_2065x.h" + +void stage_cache_external_region(void **base, size_t *size) +{ + /* + * The ramstage cache lives in the TSEG region at RESERVED_SMM_OFFSET. + * The top of RAM is defined to be the TSEG base address. + */ + *size = RESERVED_SMM_SIZE; + *base = (void *)((uintptr_t)northbridge_get_tseg_base() + + RESERVED_SMM_OFFSET); +} diff --git a/src/northbridge/intel/nehalem/northbridge.c b/src/northbridge/intel/nehalem/northbridge.c index 233b0bbd00..485cb27f45 100644 --- a/src/northbridge/intel/nehalem/northbridge.c +++ b/src/northbridge/intel/nehalem/northbridge.c @@ -171,13 +171,6 @@ static void mc_read_resources(struct device *dev) add_fixed_resources(dev, 10); } -u32 northbridge_get_tseg_base(void) -{ - struct device *dev = pcidev_on_root(0, 0); - - return pci_read_config32(dev, TSEG) & ~1; -} - u32 northbridge_get_tseg_size(void) { return CONFIG_SMM_TSEG_SIZE; diff --git a/src/northbridge/intel/nehalem/ram_calc.c b/src/northbridge/intel/nehalem/ram_calc.c index 163f21ce3c..ca821da2dc 100644 --- a/src/northbridge/intel/nehalem/ram_calc.c +++ b/src/northbridge/intel/nehalem/ram_calc.c @@ -23,6 +23,7 @@ #include #include #include +#include #include "nehalem.h" static uintptr_t smm_region_start(void) @@ -32,6 +33,11 @@ static uintptr_t smm_region_start(void) return tom; } +u32 northbridge_get_tseg_base(void) +{ + return (u32)smm_region_start & ~1; +} + void *cbmem_top(void) { return (void *) smm_region_start(); From 81e9b8ee67fe4f395e999200333a5214d1bf3789 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Mon, 3 Dec 2018 11:51:17 +0100 Subject: [PATCH 196/331] sb/intel/common/smi.c: Remove unused functions Since all targets using sb/intel/common and cpu/intel/smm/gen1 are now using PARALLEL_MP, some code is not used anymore. Change-Id: Ibdc2bb0f1412366b945813efbc1b6451d27f376f Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/30019 Reviewed-by: Paul Menzel Reviewed-by: HAOUAS Elyes Tested-by: build bot (Jenkins) --- src/cpu/intel/smm/gen1/smi.h | 3 - src/cpu/intel/smm/gen1/smmrelocate.c | 169 --------------------------- src/southbridge/intel/common/smi.c | 32 ----- 3 files changed, 204 deletions(-) diff --git a/src/cpu/intel/smm/gen1/smi.h b/src/cpu/intel/smm/gen1/smi.h index 6d08bb3684..05c507c09c 100644 --- a/src/cpu/intel/smm/gen1/smi.h +++ b/src/cpu/intel/smm/gen1/smi.h @@ -17,11 +17,8 @@ void bsp_init_and_start_aps(struct bus *cpu_bus); /* These helpers are for performing SMM relocation. */ void southbridge_smm_init(void); -void southbridge_trigger_smi(void); -void southbridge_clear_smi_status(void); u32 northbridge_get_tseg_base(void); u32 northbridge_get_tseg_size(void); -int cpu_get_apic_id_map(int *apic_id_map); void northbridge_write_smram(u8 smram); bool cpu_has_alternative_smrr(void); diff --git a/src/cpu/intel/smm/gen1/smmrelocate.c b/src/cpu/intel/smm/gen1/smmrelocate.c index cc2a8952ca..f3192bcd55 100644 --- a/src/cpu/intel/smm/gen1/smmrelocate.c +++ b/src/cpu/intel/smm/gen1/smmrelocate.c @@ -100,60 +100,6 @@ static void write_smrr(struct smm_relocation_params *relo_params) } } -/* The relocation work is actually performed in SMM context, but the code - * resides in the ramstage module. This occurs by trampolining from the default - * SMRAM entry point to here. */ -static void asmlinkage cpu_smm_do_relocation(void *arg) -{ - em64t101_smm_state_save_area_t *save_state; - msr_t mtrr_cap; - struct smm_relocation_params *relo_params; - const struct smm_module_params *p; - const struct smm_runtime *runtime; - int cpu; - - p = arg; - runtime = p->runtime; - relo_params = p->arg; - cpu = p->cpu; - - if (cpu >= CONFIG_MAX_CPUS) { - printk(BIOS_CRIT, - "Invalid CPU number assigned in SMM stub: %d\n", cpu); - return; - } - - printk(BIOS_DEBUG, "In relocation handler: cpu %d\n", cpu); - - /* All threads need to set IEDBASE and SMBASE in the save state area. - * Since one thread runs at a time during the relocation the save state - * is the same for all cpus. */ - save_state = (void *)(runtime->smbase + SMM_DEFAULT_SIZE - - runtime->save_state_size); - - /* The relocated handler runs with all CPUs concurrently. Therefore - * stagger the entry points adjusting SMBASE downwards by save state - * size * CPU num. */ - save_state->smbase = relo_params->smram_base - - cpu * runtime->save_state_size; - if (CONFIG_IED_REGION_SIZE != 0) { - save_state->iedbase = relo_params->ied_base; - - printk(BIOS_DEBUG, "New SMBASE=0x%08x IEDBASE=0x%08x @ %p\n", - save_state->smbase, save_state->iedbase, save_state); - } else { - printk(BIOS_DEBUG, "New SMBASE=0x%08x @ %p\n", - save_state->smbase, save_state); - } - - /* Write SMRR MSRs based on indicated support. */ - mtrr_cap = rdmsr(MTRR_CAP_MSR); - if (mtrr_cap.lo & SMRR_SUPPORTED && relo_params->smrr_mask.lo != 0) - write_smrr(relo_params); - - southbridge_clear_smi_status(); -} - static void fill_in_relocation_params(struct smm_relocation_params *params) { /* All range registers are aligned to 4KiB */ @@ -202,33 +148,6 @@ static void fill_in_relocation_params(struct smm_relocation_params *params) } } -static int install_relocation_handler(int *apic_id_map, int num_cpus, - struct smm_relocation_params *relo_params) -{ - /* The default SMM entry happens serially at the default location. - * Therefore, there is only 1 concurrent save state area. Set the - * stack size to the save state size, and call into the - * do_relocation handler. */ - int save_state_size = sizeof(em64t101_smm_state_save_area_t); - struct smm_loader_params smm_params = { - .per_cpu_stack_size = save_state_size, - .num_concurrent_stacks = num_cpus, - .per_cpu_save_state_size = save_state_size, - .num_concurrent_save_states = 1, - .handler = &cpu_smm_do_relocation, - .handler_arg = (void *)relo_params, - }; - - default_smm_area = backup_default_smm_area(); - - if (smm_setup_relocation_handler(&smm_params)) - return -1; - int i; - for (i = 0; i < num_cpus; i++) - smm_params.runtime->apic_id_to_cpu[i] = apic_id_map[i]; - return 0; -} - static void setup_ied_area(struct smm_relocation_params *params) { char *ied_base; @@ -248,94 +167,6 @@ static void setup_ied_area(struct smm_relocation_params *params) memset(ied_base + (1 << 20), 0, (32 << 10)); } -static int install_permanent_handler(int *apic_id_map, int num_cpus, - struct smm_relocation_params *relo_params) -{ - /* There are num_cpus concurrent stacks and num_cpus concurrent save - * state areas. Lastly, set the stack size to the save state size. */ - int save_state_size = sizeof(em64t101_smm_state_save_area_t); - struct smm_loader_params smm_params = { - .per_cpu_stack_size = save_state_size, - .num_concurrent_stacks = num_cpus, - .per_cpu_save_state_size = save_state_size, - .num_concurrent_save_states = num_cpus, - }; - - printk(BIOS_DEBUG, "Installing SMM handler to 0x%08x\n", - relo_params->smram_base); - if (smm_load_module((void *)relo_params->smram_base, - relo_params->smram_size, &smm_params)) - return -1; - int i; - for (i = 0; i < num_cpus; i++) - smm_params.runtime->apic_id_to_cpu[i] = apic_id_map[i]; - return 0; -} - -static int cpu_smm_setup(void) -{ - int num_cpus; - int apic_id_map[CONFIG_MAX_CPUS]; - - printk(BIOS_DEBUG, "Setting up SMI for CPU\n"); - - fill_in_relocation_params(&smm_reloc_params); - - /* enable the SMM memory window */ - northbridge_write_smram(D_OPEN | G_SMRAME | C_BASE_SEG); - - if (CONFIG_IED_REGION_SIZE != 0) - setup_ied_area(&smm_reloc_params); - - num_cpus = cpu_get_apic_id_map(apic_id_map); - if (num_cpus > CONFIG_MAX_CPUS) { - printk(BIOS_CRIT, - "Error: Hardware CPUs (%d) > MAX_CPUS (%d)\n", - num_cpus, CONFIG_MAX_CPUS); - } - - if (install_relocation_handler(apic_id_map, num_cpus, - &smm_reloc_params)) { - printk(BIOS_CRIT, "SMM Relocation handler install failed.\n"); - return -1; - } - - if (install_permanent_handler(apic_id_map, num_cpus, - &smm_reloc_params)) { - printk(BIOS_CRIT, "SMM Permanent handler install failed.\n"); - return -1; - } - - /* Ensure the SMM handlers hit DRAM before performing first SMI. */ - /* TODO(adurbin): Is this really needed? */ - wbinvd(); - - /* close the SMM memory window and enable normal SMM */ - northbridge_write_smram(G_SMRAME | C_BASE_SEG); - - return 0; -} - -void smm_init(void) -{ - /* Return early if CPU SMM setup failed. */ - if (cpu_smm_setup()) - return; - - southbridge_smm_init(); - - /* Initiate first SMI to kick off SMM-context relocation. Note: this - * SMI being triggered here queues up an SMI in the APs which are in - * wait-for-SIPI state. Once an AP gets an SIPI it will service the SMI - * at the SMM_DEFAULT_BASE before jumping to startup vector. */ - southbridge_trigger_smi(); - - printk(BIOS_DEBUG, "Relocation complete.\n"); - - /* Lock down the SMRAM space. */ - smm_lock(); -} - void smm_init_completion(void) { restore_default_smm_area(default_smm_area); diff --git a/src/southbridge/intel/common/smi.c b/src/southbridge/intel/common/smi.c index 036ac22adc..398c6804e0 100644 --- a/src/southbridge/intel/common/smi.c +++ b/src/southbridge/intel/common/smi.c @@ -104,38 +104,6 @@ void southbridge_smm_init(void) write_pmbase32(SMI_EN, smi_en); } -void southbridge_trigger_smi(void) -{ - /** - * There are several methods of raising a controlled SMI# via - * software, among them: - * - Writes to io 0xb2 (APMC) - * - Writes to the Local Apic ICR with Delivery mode SMI. - * - * Using the local apic is a bit more tricky. According to - * AMD Family 11 Processor BKDG no destination shorthand must be - * used. - * The whole SMM initialization is quite a bit hardware specific, so - * I'm not too worried about the better of the methods at the moment - */ - - /* raise an SMI interrupt */ - printk(BIOS_SPEW, " ... raise SMI#\n"); - outb(0x00, 0xb2); -} - -void southbridge_clear_smi_status(void) -{ - /* Clear SMI status */ - reset_smi_status(); - - /* Clear PM1 status */ - reset_pm1_status(); - - /* Set EOS bit so other SMIs can occur. */ - smi_set_eos(); -} - void smm_setup_structures(void *gnvs, void *tcg, void *smi1) { /* From d8f56a9b2999a3216aea7e219566af8d62bd53e1 Mon Sep 17 00:00:00 2001 From: Casper Chang Date: Fri, 24 May 2019 22:03:35 +0800 Subject: [PATCH 197/331] mb/google/sarien: Modify arcada touchscreen reset delay Modify reset delay to 20ms of touchscreen to address i2c hid driver rebind failed issue after auto update of touchscreen firmware BUG=b:132211627 TEST=Touchscreen works after auto update and no re-bind driver failed issue Signed-off-by: Casper Chang Change-Id: If17afbd160a2c97beb69d0cb50e4a7dc654775f5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32988 Tested-by: build bot (Jenkins) Reviewed-by: Nick Crews Reviewed-by: Duncan Laurie --- src/mainboard/google/sarien/variants/arcada/devicetree.cb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb index d3848a24b0..767df1f795 100644 --- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb +++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb @@ -315,7 +315,7 @@ chip soc/intel/cannonlake register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C23_IRQ)" register "generic.probed" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E7)" - register "generic.reset_delay_ms" = "10" + register "generic.reset_delay_ms" = "20" register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B21)" register "generic.enable_delay_ms" = "55" register "generic.has_power_resource" = "1" From 07db5fcec10b825d7d3660c492abb66f2e802405 Mon Sep 17 00:00:00 2001 From: Christian Walter Date: Thu, 23 May 2019 15:42:34 +0200 Subject: [PATCH 198/331] src/include/device/pci_ids.h: Add Kabylake C236 Device Change-Id: Ib11981543575311a32896df385d44cf30aa9387f Signed-off-by: Christian Walter Reviewed-on: https://review.coreboot.org/c/coreboot/+/32964 Reviewed-by: Philipp Deppenwiese Reviewed-by: Patrick Rudolph Tested-by: build bot (Jenkins) --- src/include/device/pci_ids.h | 1 + src/soc/intel/common/block/lpc/lpc.c | 1 + 2 files changed, 2 insertions(+) diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 553deafc8b..3c48e685de 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -2694,6 +2694,7 @@ #define PCI_DEVICE_ID_INTEL_SPT_H_Q170 0xa146 #define PCI_DEVICE_ID_INTEL_SPT_H_Q150 0xa147 #define PCI_DEVICE_ID_INTEL_SPT_H_B150 0xa148 +#define PCI_DEVICE_ID_INTEL_KBP_H_C236 0xa149 #define PCI_DEVICE_ID_INTEL_SPT_H_C236 0xa150 #define PCI_DEVICE_ID_INTEL_SPT_H_PREMIUM 0xa14e #define PCI_DEVICE_ID_INTEL_SPT_H_H110 0xa143 diff --git a/src/soc/intel/common/block/lpc/lpc.c b/src/soc/intel/common/block/lpc/lpc.c index 43b3522431..86547a443f 100644 --- a/src/soc/intel/common/block/lpc/lpc.c +++ b/src/soc/intel/common/block/lpc/lpc.c @@ -125,6 +125,7 @@ static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_INTEL_SPT_LP_U_PREMIUM, PCI_DEVICE_ID_INTEL_SPT_LP_Y_PREMIUM, PCI_DEVICE_ID_INTEL_SPT_H_C236, + PCI_DEVICE_ID_INTEL_KBP_H_C236, PCI_DEVICE_ID_INTEL_SPT_H_PREMIUM, PCI_DEVICE_ID_INTEL_SPT_H_H110, PCI_DEVICE_ID_INTEL_SPT_H_H170, From 3b4d0e060cd4d3384cba18404c0c309cf94f508e Mon Sep 17 00:00:00 2001 From: Christian Walter Date: Fri, 24 May 2019 15:17:06 +0200 Subject: [PATCH 199/331] src/cpu/x86/lapic/lapic.c: Add missing newline Added missing new line to Info Output. Change-Id: Ic4cd63f231de918fad7cd34724651bf8eb1c8e62 Signed-off-by: Christian Walter Reviewed-on: https://review.coreboot.org/c/coreboot/+/32987 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans Reviewed-by: Angel Pons --- src/cpu/x86/lapic/lapic.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/cpu/x86/lapic/lapic.c b/src/cpu/x86/lapic/lapic.c index 8cd3092b24..755fbe220d 100644 --- a/src/cpu/x86/lapic/lapic.c +++ b/src/cpu/x86/lapic/lapic.c @@ -24,7 +24,7 @@ void do_lapic_init(void) * see the Intel mp1.4 spec, page A-3 */ - printk(BIOS_INFO, "Setting up local APIC..."); + printk(BIOS_INFO, "Setting up local APIC...\n"); /* Enable the local APIC */ enable_lapic(); From 9e5b06297d8f5d86d33ced80f371d52ef4c12334 Mon Sep 17 00:00:00 2001 From: Christian Walter Date: Tue, 21 May 2019 17:37:58 +0200 Subject: [PATCH 200/331] src/arch/x86: Add automatic type41 entry creation SMBIOS Type41 Entries will be automatically created. Type 41 entries define attributes of the onboard devices. Change-Id: Idcb3532a5c05666d6613af4f303df85f4f1f6e97 Signed-off-by: Christian Walter Reviewed-on: https://review.coreboot.org/c/coreboot/+/32910 Reviewed-by: Philipp Deppenwiese Reviewed-by: Patrick Rudolph Tested-by: build bot (Jenkins) --- src/arch/x86/smbios.c | 71 ++++++++++++++++++++++++++++++++++++ src/include/device/pci_ids.h | 2 + src/include/smbios.h | 2 + 3 files changed, 75 insertions(+) diff --git a/src/arch/x86/smbios.c b/src/arch/x86/smbios.c index 310a870da6..bf627f280f 100644 --- a/src/arch/x86/smbios.c +++ b/src/arch/x86/smbios.c @@ -30,6 +30,9 @@ #include #include #include +#include +#include +#include #if CONFIG(CHROMEOS) #include #endif @@ -50,6 +53,41 @@ static u8 smbios_checksum(u8 *p, u32 length) return -ret; } +/* Get the device type 41 from the dev struct */ +static u8 smbios_get_device_type_from_dev(struct device *dev) +{ + u16 pci_basesubclass = (dev->class >> 8) & 0xFFFF; + + switch (pci_basesubclass) { + case PCI_CLASS_NOT_DEFINED: + return SMBIOS_DEVICE_TYPE_OTHER; + case PCI_CLASS_DISPLAY_VGA: + case PCI_CLASS_DISPLAY_XGA: + case PCI_CLASS_DISPLAY_3D: + case PCI_CLASS_DISPLAY_OTHER: + return SMBIOS_DEVICE_TYPE_VIDEO; + case PCI_CLASS_STORAGE_SCSI: + return SMBIOS_DEVICE_TYPE_SCSI; + case PCI_CLASS_NETWORK_ETHERNET: + return SMBIOS_DEVICE_TYPE_ETHERNET; + case PCI_CLASS_NETWORK_TOKEN_RING: + return SMBIOS_DEVICE_TYPE_TOKEN_RING; + case PCI_CLASS_MULTIMEDIA_VIDEO: + case PCI_CLASS_MULTIMEDIA_AUDIO: + case PCI_CLASS_MULTIMEDIA_PHONE: + case PCI_CLASS_MULTIMEDIA_OTHER: + return SMBIOS_DEVICE_TYPE_SOUND; + case PCI_CLASS_STORAGE_ATA: + return SMBIOS_DEVICE_TYPE_PATA; + case PCI_CLASS_STORAGE_SATA: + return SMBIOS_DEVICE_TYPE_SATA; + case PCI_CLASS_STORAGE_SAS: + return SMBIOS_DEVICE_TYPE_SAS; + default: + return SMBIOS_DEVICE_TYPE_UNKNOWN; + } +} + int smbios_add_string(u8 *start, const char *str) { @@ -999,6 +1037,38 @@ static int smbios_write_type127(unsigned long *current, int handle) return len; } +/* Generate Type41 entries from devicetree */ +static int smbios_walk_device_tree_type41(struct device *dev, int *handle, + unsigned long *current) +{ + static u8 type41_inst_cnt[SMBIOS_DEVICE_TYPE_COUNT + 1] = {}; + + if (dev->path.type != DEVICE_PATH_PCI) + return 0; + if (!dev->on_mainboard) + return 0; + + u8 device_type = smbios_get_device_type_from_dev(dev); + + if (device_type == SMBIOS_DEVICE_TYPE_OTHER || + device_type == SMBIOS_DEVICE_TYPE_UNKNOWN) + return 0; + + if (device_type > SMBIOS_DEVICE_TYPE_COUNT) + return 0; + + const char *name = get_pci_subclass_name(dev); + + return smbios_write_type41(current, handle, + name, // name + type41_inst_cnt[device_type]++, // inst + 0, // segment + dev->bus->secondary, //bus + PCI_SLOT(dev->path.pci.devfn), // device + PCI_FUNC(dev->path.pci.devfn), // func + device_type); +} + /* Generate Type9 entries from devicetree */ static int smbios_walk_device_tree_type9(struct device *dev, int *handle, unsigned long *current) @@ -1062,6 +1132,7 @@ static int smbios_walk_device_tree(struct device *tree, int *handle, len += dev->ops->get_smbios_data(dev, handle, current); } len += smbios_walk_device_tree_type9(dev, handle, current); + len += smbios_walk_device_tree_type41(dev, handle, current); } return len; } diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 3c48e685de..a35e134dc9 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -18,7 +18,9 @@ #define PCI_CLASS_STORAGE_FLOPPY 0x0102 #define PCI_CLASS_STORAGE_IPI 0x0103 #define PCI_CLASS_STORAGE_RAID 0x0104 +#define PCI_CLASS_STORAGE_ATA 0x0105 #define PCI_CLASS_STORAGE_SATA 0x0106 +#define PCI_CLASS_STORAGE_SAS 0x0107 #define PCI_CLASS_STORAGE_OTHER 0x0180 #define PCI_BASE_CLASS_NETWORK 0x02 diff --git a/src/include/smbios.h b/src/include/smbios.h index 017e90e742..0bba0a7f9e 100644 --- a/src/include/smbios.h +++ b/src/include/smbios.h @@ -756,6 +756,8 @@ typedef enum { SMBIOS_DEVICE_TYPE_SAS, } smbios_onboard_device_type; +#define SMBIOS_DEVICE_TYPE_COUNT 10 + struct smbios_type41 { u8 type; u8 length; From 63cba976b19fb5bc3b52f8448240bece9bafb28e Mon Sep 17 00:00:00 2001 From: Eric Lai Date: Thu, 23 May 2019 15:31:40 +0800 Subject: [PATCH 201/331] mb/google/sarien: Fix SSD power leakage in S5 Turn off SSD power in S5. BUG=b:133389422 TEST=measure H13 is low in S5 Signed-off-by: Eric Lai Change-Id: I40b5381cac33b0eac962a7730ee5c57e60e6d375 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32952 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie --- .../variants/arcada/include/variant/acpi/mainboard.asl | 8 ++++++++ .../variants/sarien/include/variant/acpi/mainboard.asl | 8 ++++++++ 2 files changed, 16 insertions(+) diff --git a/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/mainboard.asl b/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/mainboard.asl index 41121d28fe..6eba2bcb21 100644 --- a/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/mainboard.asl +++ b/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/mainboard.asl @@ -15,6 +15,8 @@ #define CAM_EN GPP_B11 /* Active low */ #define TS_PD GPP_E7 +#define SSD_EN GPP_H13 +#define SSD_RST GPP_H12 /* Method called from LPIT prior to enter s0ix state */ Method (MS0X, 1) @@ -35,6 +37,12 @@ Method (MPTS, 1) /* Clear touch screen pd pin to avoid leakage */ \_SB.PCI0.CTXS (TS_PD) + + /* Clear SSD EN adn RST pin to avoid leakage */ + If (Arg0 == 5) { + \_SB.PCI0.CTXS (SSD_EN) + \_SB.PCI0.CTXS (SSD_RST) + } } /* Method called from _WAK prior to wakeup */ diff --git a/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/mainboard.asl b/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/mainboard.asl index 41121d28fe..6eba2bcb21 100644 --- a/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/mainboard.asl +++ b/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/mainboard.asl @@ -15,6 +15,8 @@ #define CAM_EN GPP_B11 /* Active low */ #define TS_PD GPP_E7 +#define SSD_EN GPP_H13 +#define SSD_RST GPP_H12 /* Method called from LPIT prior to enter s0ix state */ Method (MS0X, 1) @@ -35,6 +37,12 @@ Method (MPTS, 1) /* Clear touch screen pd pin to avoid leakage */ \_SB.PCI0.CTXS (TS_PD) + + /* Clear SSD EN adn RST pin to avoid leakage */ + If (Arg0 == 5) { + \_SB.PCI0.CTXS (SSD_EN) + \_SB.PCI0.CTXS (SSD_RST) + } } /* Method called from _WAK prior to wakeup */ From 48b2adae1c3ba0c23630f912fd7f7c87f0a7528c Mon Sep 17 00:00:00 2001 From: Eric Lai Date: Tue, 28 May 2019 13:49:44 +0800 Subject: [PATCH 202/331] mb/google/sarien: Modify SSD power sequence Due to we turn off SSD power in S5. CB:32952 Based on M2 spec we have to turn on SSD power before RST assert. BUG=b:133389422 TEST=verify warm boot and cold boot are boot successfully. Signed-off-by: Eric Lai Change-Id: I5b78bab4be675bbb8795361bcfa5af52cb54bb1e Reviewed-on: https://review.coreboot.org/c/coreboot/+/33029 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie --- src/mainboard/google/sarien/variants/arcada/gpio.c | 2 +- src/mainboard/google/sarien/variants/sarien/gpio.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mainboard/google/sarien/variants/arcada/gpio.c b/src/mainboard/google/sarien/variants/arcada/gpio.c index ea0601b55e..ff0240c991 100644 --- a/src/mainboard/google/sarien/variants/arcada/gpio.c +++ b/src/mainboard/google/sarien/variants/arcada/gpio.c @@ -211,7 +211,6 @@ static const struct pad_config gpio_table[] = { /* I2C4_SCL */ PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), /* I2C_SCL_H1 */ /* I2C5_SDA */ PAD_NC(GPP_H10, NONE), /* ISH_I2C2_SDA */ /* I2C5_SCL */ PAD_NC(GPP_H11, NONE), /* ISH_I2C2_SCL */ -/* M2_SKT2_CFG1 */ PAD_CFG_GPO(GPP_H13, 1, DEEP), /* M.2 SSD D3 cold */ /* M2_SKT2_CFG2 */ PAD_NC(GPP_H14, NONE), /* M2_SKT2_CFG3 */ PAD_CFG_GPO(GPP_H15, 1, DEEP), /* BT_RADIO_DIS# */ /* DDPF_CTRLCLK */ PAD_NC(GPP_H16, NONE), @@ -239,6 +238,7 @@ static const struct pad_config gpio_table[] = { /* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { +/* M2_SKT2_CFG1 */ PAD_CFG_GPO(GPP_H13, 1, DEEP), /* M.2 SSD D3 cold */ /* SSD RESET pin will stay low first */ /* M2_SKT2_CFG0 */ PAD_CFG_GPO(GPP_H12, 0, DEEP), /* D3 cold RST */ /* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVOTX_UART */ diff --git a/src/mainboard/google/sarien/variants/sarien/gpio.c b/src/mainboard/google/sarien/variants/sarien/gpio.c index ec3b44d4a3..78db12e8a1 100644 --- a/src/mainboard/google/sarien/variants/sarien/gpio.c +++ b/src/mainboard/google/sarien/variants/sarien/gpio.c @@ -197,7 +197,6 @@ static const struct pad_config gpio_table[] = { /* I2C4_SCL */ PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), /* I2C_SCL_H1 */ /* I2C5_SDA */ PAD_NC(GPP_H10, NONE), /* I2C5_SCL */ PAD_NC(GPP_H11, NONE), -/* M2_SKT2_CFG1 */ PAD_CFG_GPO(GPP_H13, 1, DEEP), /* M.2 SSD D3 cold */ /* M2_SKT2_CFG2 */ PAD_NC(GPP_H14, NONE), /* M2_SKT2_CFG3 */ PAD_CFG_GPO(GPP_H15, 1, DEEP), /* BT_RADIO_DIS# */ /* DDPF_CTRLCLK */ PAD_NC(GPP_H16, NONE), @@ -224,6 +223,7 @@ static const struct pad_config gpio_table[] = { /* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { +/* M2_SKT2_CFG1 */ PAD_CFG_GPO(GPP_H13, 1, DEEP), /* M.2 SSD D3 cold */ /* SUSWARN# */ PAD_CFG_GPO(GPP_A13, 0, DEEP), /* Card reader D3 cold */ /* SUSACK# */ PAD_CFG_GPO(GPP_A15, 0, DEEP), /* Card reader D3 cold */ /* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVOTX_UART */ From 9637856b533ee6eaa7cd3e1c1b2ec4d816f58dff Mon Sep 17 00:00:00 2001 From: Bora Guvendik Date: Fri, 24 May 2019 14:41:31 -0700 Subject: [PATCH 203/331] soc/intel/cannonlake: Dump ME status info before notify EndOfFirmware Dumping ME status displays wrong information if we disable Heci1 because it is called after fsp notifies EndOfFirmware and disables Heci1. This patch moves the ME status dump before fsp notify EndOfFirmware. TEST=Boot to OS, check ME dump information Change-Id: Ifd8b18a41c502c4ecfb84698a7669028394589fd Signed-off-by: Bora Guvendik Reviewed-on: https://review.coreboot.org/c/coreboot/+/32991 Tested-by: build bot (Jenkins) Reviewed-by: Subrata Banik Reviewed-by: Furquan Shaikh Reviewed-by: Tim Wawrzynczak --- src/soc/intel/cannonlake/finalize.c | 3 --- src/soc/intel/cannonlake/include/soc/me.h | 2 +- src/soc/intel/cannonlake/me.c | 5 ++++- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/src/soc/intel/cannonlake/finalize.c b/src/soc/intel/cannonlake/finalize.c index eb4c5c2c9d..4dfd15bc4a 100644 --- a/src/soc/intel/cannonlake/finalize.c +++ b/src/soc/intel/cannonlake/finalize.c @@ -26,7 +26,6 @@ #include #include #include -#include #include #include #include @@ -95,8 +94,6 @@ static void soc_finalize(void *unused) { printk(BIOS_DEBUG, "Finalizing chipset.\n"); - dump_me_status(); - pch_finalize(); printk(BIOS_DEBUG, "Finalizing SMM.\n"); diff --git a/src/soc/intel/cannonlake/include/soc/me.h b/src/soc/intel/cannonlake/include/soc/me.h index 1d782c153c..5b411d3621 100644 --- a/src/soc/intel/cannonlake/include/soc/me.h +++ b/src/soc/intel/cannonlake/include/soc/me.h @@ -16,6 +16,6 @@ #ifndef _CANNONLAKE_ME_H_ #define _CANNONLAKE_ME_H_ -void dump_me_status(void); +void dump_me_status(void *unused); #endif /* _CANNONLAKE_ME_H_ */ diff --git a/src/soc/intel/cannonlake/me.c b/src/soc/intel/cannonlake/me.c index 3fedc6374e..c9748b7343 100644 --- a/src/soc/intel/cannonlake/me.c +++ b/src/soc/intel/cannonlake/me.c @@ -235,7 +235,7 @@ fail: } BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_EXIT, print_me_version, NULL); -void dump_me_status(void) +void dump_me_status(void *unused) { union hfsts1 hfsts1; union hfsts2 hfsts2; @@ -297,3 +297,6 @@ void dump_me_status(void) printk(BIOS_DEBUG, "ME: TXT Support : %s\n", hfsts6.fields.txt_support ? "YES" : "NO"); } + +BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_ENTRY, dump_me_status, NULL); +BOOT_STATE_INIT_ENTRY(BS_OS_RESUME_CHECK, BS_ON_EXIT, dump_me_status, NULL); From 1470c7367b8fca24c86c8912aa65e969e63ff521 Mon Sep 17 00:00:00 2001 From: Alan Green Date: Wed, 22 May 2019 11:12:44 +1000 Subject: [PATCH 204/331] util/xcompile/xcompile: apply -march to clang as well as gcc MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit For x64 and x86_32 configurations, apply the -march flag to both GCC and Clang flags. This solves the problem of Clang-compiled coreboot failing due to Clang emitting SSE instructions for code that is executed while SSE is not enabled. This patch takes functionality targeted for GCC configurations and moves it down a few lines, modifying CFLAGS instead of GCC_CFLAGS in order that it applies to both GCC and Clang. This is an alternate patch to CB:32887. Signed-off-by: Alan Green Change-Id: I6a6a6136b01a64d46f730ed19ebbeaadaf2183df Reviewed-on: https://review.coreboot.org/c/coreboot/+/32923 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Patrick Georgi Reviewed-by: Kyösti Mälkki --- util/xcompile/xcompile | 55 +++++++++++++++++++++--------------------- 1 file changed, 28 insertions(+), 27 deletions(-) diff --git a/util/xcompile/xcompile b/util/xcompile/xcompile index 4a29cdd647..40356d93d9 100755 --- a/util/xcompile/xcompile +++ b/util/xcompile/xcompile @@ -227,33 +227,6 @@ GCC_CC_${TARCH}:=${GCC} GCC_CFLAGS_${TARCH}:=${CFLAGS_GCC} GCC_COMPILER_RT_${TARCH}:=${CC_RT_GCC} GCC_COMPILER_RT_FLAGS_${TARCH}:=${CC_RT_EXTRA_GCC} -EOF - -# Generally the x86 should build for i686 -- no sse/mmx -# instructions since SMM modules are compiled using these -# flags. Note that this doesn't prevent a project using -# xcompile to explicitly specify -mmsse, etc flags. -# The Quark processor doesn't support the instructions -# introduced with the Pentium 6 architecture, so allow it -# to use i586 instead. -if [ "${TARCH}" = "x86_64" ]; then -cat < Date: Wed, 29 May 2019 13:59:14 +0530 Subject: [PATCH 205/331] drivers/intel/fsp2_0: Fix typo mistake Change-Id: I90f595d7d789429c8717261c6edb6c756f6c0e1f Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/33056 Tested-by: build bot (Jenkins) Reviewed-by: HAOUAS Elyes Reviewed-by: Aamir Bohra --- src/drivers/intel/fsp2_0/silicon_init.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/drivers/intel/fsp2_0/silicon_init.c b/src/drivers/intel/fsp2_0/silicon_init.c index e9c29db40e..302bc0f3ad 100644 --- a/src/drivers/intel/fsp2_0/silicon_init.c +++ b/src/drivers/intel/fsp2_0/silicon_init.c @@ -72,7 +72,7 @@ static void do_silicon_init(struct fsp_header *hdr) } printk(BIOS_SPEW, "FspSiliconInit returned 0x%08x\n", status); die_with_post_code(postcode, - "FspSiliconINit returned an error!\n"); + "FspSiliconInit returned an error!\n"); } } From 23fbd052b90be2e9a6c3858bb9b314069e70ea6d Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Tue, 28 May 2019 17:38:17 +0200 Subject: [PATCH 206/331] nb/intel/nehalem: Call smm_region_start() function This also removes the unnecessary mask. TEST: X201 Boots again. Change-Id: Ia637bd01cd7dc1aecd1a87a739d5243c70419553 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/33046 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Nico Huber --- src/northbridge/intel/nehalem/ram_calc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/northbridge/intel/nehalem/ram_calc.c b/src/northbridge/intel/nehalem/ram_calc.c index ca821da2dc..e32190f519 100644 --- a/src/northbridge/intel/nehalem/ram_calc.c +++ b/src/northbridge/intel/nehalem/ram_calc.c @@ -35,7 +35,7 @@ static uintptr_t smm_region_start(void) u32 northbridge_get_tseg_base(void) { - return (u32)smm_region_start & ~1; + return (u32)smm_region_start(); } void *cbmem_top(void) From b80d1324d3e86c0b8c72fd7cd09df07794931059 Mon Sep 17 00:00:00 2001 From: Ivy Jian Date: Mon, 27 May 2019 11:19:44 +0800 Subject: [PATCH 207/331] mb/google/poppy/variants/nami: Disable FPMCU for non-fingerprint variants Even fingerprint device probe failed on non-fingerpint boards,the CRFP driver still register the device that cause the GPE#1 as wake source every time. Override devicetree for non-fingerpirnt variants to avoid unexpected wake event(GPE#1). BUG=b:129650040 BRANCH=firmware-nami-10775.108.B TEST=Boots to OS and check no GPE#1 wake event from eventlog when S0ix exit. Signed-off-by: Ivy Jian Change-Id: I6fa96e04a34e296889414b96a8c604fc61b8a236 Reviewed-on: https://review.coreboot.org/c/coreboot/+/33017 Reviewed-by: EricR Lai Reviewed-by: John Su Tested-by: build bot (Jenkins) --- src/mainboard/google/poppy/variants/nami/mainboard.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/mainboard/google/poppy/variants/nami/mainboard.c b/src/mainboard/google/poppy/variants/nami/mainboard.c index dff62c217c..cc87136520 100644 --- a/src/mainboard/google/poppy/variants/nami/mainboard.c +++ b/src/mainboard/google/poppy/variants/nami/mainboard.c @@ -238,6 +238,7 @@ void variant_devtree_update(void) struct device *root = SA_DEV_ROOT; config_t *cfg = root->chip_info; uint8_t pl2_id = PL2_ID_DEFAULT; + struct device *spi_fpmcu = PCH_DEV_GSPI1; switch (sku_id) { case SKU_0_SONA: @@ -260,6 +261,7 @@ void variant_devtree_update(void) case SKU_3_PANTHEON: case SKU_4_PANTHEON: cfg->usb2_ports[5].enable = 0; + spi_fpmcu->enabled = 0; break; case SKU_0_BARD: case SKU_1_BARD: From c30e59051fcbda4fba8a2c36c6b04110ee1caacd Mon Sep 17 00:00:00 2001 From: Jacob Garber Date: Thu, 23 May 2019 14:34:58 -0600 Subject: [PATCH 208/331] arch/x86: Do not add properties to null DP packages It doesn't make sense to add a property to a non-existent Device Property package. However, some of these functions will proceed anyway and allocate a new Device Property package, add the property to that, and then immediately leak the new package. This changes all the acpi_dp_add_* functions to ignore a null package. Change-Id: I664dcdbaa6b1b8a3aeb9a0126d622e2ffb736efd Signed-off-by: Jacob Garber Found-by: Coverity CID 135745{6,7}, 138029{2-6} Reviewed-on: https://review.coreboot.org/c/coreboot/+/32971 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/arch/x86/acpi_device.c | 21 ++++++++++++++++++--- 1 file changed, 18 insertions(+), 3 deletions(-) diff --git a/src/arch/x86/acpi_device.c b/src/arch/x86/acpi_device.c index 5d8777f37f..57fbc89064 100644 --- a/src/arch/x86/acpi_device.c +++ b/src/arch/x86/acpi_device.c @@ -740,6 +740,9 @@ size_t acpi_dp_add_property_list(struct acpi_dp *dp, const struct acpi_dp *prop; size_t i, properties_added = 0; + if (!dp || !property_list) + return 0; + for (i = 0; i < property_count; i++) { prop = &property_list[i]; @@ -775,6 +778,9 @@ size_t acpi_dp_add_property_list(struct acpi_dp *dp, struct acpi_dp *acpi_dp_add_integer(struct acpi_dp *dp, const char *name, uint64_t value) { + if (!dp) + return NULL; + struct acpi_dp *new = acpi_dp_new(dp, ACPI_DP_TYPE_INTEGER, name); if (new) @@ -786,6 +792,9 @@ struct acpi_dp *acpi_dp_add_integer(struct acpi_dp *dp, const char *name, struct acpi_dp *acpi_dp_add_string(struct acpi_dp *dp, const char *name, const char *string) { + if (!dp) + return NULL; + struct acpi_dp *new = acpi_dp_new(dp, ACPI_DP_TYPE_STRING, name); if (new) @@ -797,6 +806,9 @@ struct acpi_dp *acpi_dp_add_string(struct acpi_dp *dp, const char *name, struct acpi_dp *acpi_dp_add_reference(struct acpi_dp *dp, const char *name, const char *reference) { + if (!dp) + return NULL; + struct acpi_dp *new = acpi_dp_new(dp, ACPI_DP_TYPE_REFERENCE, name); if (new) @@ -810,7 +822,7 @@ struct acpi_dp *acpi_dp_add_child(struct acpi_dp *dp, const char *name, { struct acpi_dp *new; - if (!child || child->type != ACPI_DP_TYPE_TABLE) + if (!dp || !child || child->type != ACPI_DP_TYPE_TABLE) return NULL; new = acpi_dp_new(dp, ACPI_DP_TYPE_CHILD, name); @@ -826,7 +838,7 @@ struct acpi_dp *acpi_dp_add_array(struct acpi_dp *dp, struct acpi_dp *array) { struct acpi_dp *new; - if (!array || array->type != ACPI_DP_TYPE_TABLE) + if (!dp || !array || array->type != ACPI_DP_TYPE_TABLE) return NULL; new = acpi_dp_new(dp, ACPI_DP_TYPE_ARRAY, array->name); @@ -842,7 +854,7 @@ struct acpi_dp *acpi_dp_add_integer_array(struct acpi_dp *dp, const char *name, struct acpi_dp *dp_array; int i; - if (len <= 0) + if (!dp || len <= 0) return NULL; dp_array = acpi_dp_new_table(name); @@ -862,6 +874,9 @@ struct acpi_dp *acpi_dp_add_gpio(struct acpi_dp *dp, const char *name, const char *ref, int index, int pin, int active_low) { + if (!dp) + return NULL; + struct acpi_dp *gpio = acpi_dp_new_table(name); if (!gpio) From 702f83897730739af21d10649759589ae9a22203 Mon Sep 17 00:00:00 2001 From: Eric Lai Date: Tue, 28 May 2019 23:49:32 +0800 Subject: [PATCH 209/331] mb/google/sarien: Send post code to the EC Use the mainboard post code hook to inform the wilco EC driver of the every stage. BUG=b:124401932,b:133466714,b:133600566 BRANCH=sarien TEST=Remove DIMM module, confirm diagnostic LED pattern for memory failure (2 amber, 4 white). Signed-off-by: Eric Lai Signed-off-by: Duncan Laurie Change-Id: Ic71e4a6e62b63ca2fd189957c4d6f49b61b934de Reviewed-on: https://review.coreboot.org/c/coreboot/+/33047 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie Reviewed-by: Frank Wu Reviewed-by: Furquan Shaikh --- src/mainboard/google/sarien/Makefile.inc | 5 +++++ src/mainboard/google/sarien/ec.c | 23 +++++++++++++++++++++++ src/mainboard/google/sarien/ramstage.c | 6 ------ 3 files changed, 28 insertions(+), 6 deletions(-) create mode 100644 src/mainboard/google/sarien/ec.c diff --git a/src/mainboard/google/sarien/Makefile.inc b/src/mainboard/google/sarien/Makefile.inc index 6fd23cefcd..7c37bc9901 100644 --- a/src/mainboard/google/sarien/Makefile.inc +++ b/src/mainboard/google/sarien/Makefile.inc @@ -29,5 +29,10 @@ verstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_HDA_VERB) += hda_verb.c +bootblock-$(CONFIG_EC_GOOGLE_WILCO) += ec.c +ramstage-$(CONFIG_EC_GOOGLE_WILCO) += ec.c +romstage-$(CONFIG_EC_GOOGLE_WILCO) += ec.c +verstage-$(CONFIG_EC_GOOGLE_WILCO) += ec.c + subdirs-y += variants/$(VARIANT_DIR) CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include diff --git a/src/mainboard/google/sarien/ec.c b/src/mainboard/google/sarien/ec.c new file mode 100644 index 0000000000..fd8e84fbc8 --- /dev/null +++ b/src/mainboard/google/sarien/ec.c @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include + +void mainboard_post(uint8_t value) +{ + wilco_ec_save_post_code(value); +} diff --git a/src/mainboard/google/sarien/ramstage.c b/src/mainboard/google/sarien/ramstage.c index e246419373..1d220461cf 100644 --- a/src/mainboard/google/sarien/ramstage.c +++ b/src/mainboard/google/sarien/ramstage.c @@ -15,7 +15,6 @@ #include #include -#include #include #include #include @@ -70,11 +69,6 @@ void mainboard_silicon_init_params(FSP_S_CONFIG *params) cnl_configure_pads(gpio_table, num_gpios); } -void mainboard_post(uint8_t value) -{ - wilco_ec_save_post_code(value); -} - static void mainboard_enable(struct device *dev) { dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator; From edbcd057e6e8a991c8473a0da05081452db2f8f5 Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Mon, 20 May 2019 09:21:43 +0200 Subject: [PATCH 210/331] Documentation: Warn about ME cleaner on Sandy Bridge Document known issues with 'disabled' ME. Change-Id: I364f3ed49341523c781eb2f3b41e866f33632a7e Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/c/coreboot/+/32889 Reviewed-by: Felix Held Tested-by: build bot (Jenkins) --- .../northbridge/intel/sandybridge/index.md | 1 + .../intel/sandybridge/me_cleaner.md | 20 +++++++++++++++++++ 2 files changed, 21 insertions(+) create mode 100644 Documentation/northbridge/intel/sandybridge/me_cleaner.md diff --git a/Documentation/northbridge/intel/sandybridge/index.md b/Documentation/northbridge/intel/sandybridge/index.md index dcb090aad6..c1d4b9948d 100644 --- a/Documentation/northbridge/intel/sandybridge/index.md +++ b/Documentation/northbridge/intel/sandybridge/index.md @@ -6,3 +6,4 @@ This section contains documentation about coreboot on specific Intel "Sandy Brid - [Native Ram Initialization](nri.md) - [RAM initialization feature matrix](nri_features.md) +- [ME Cleaner](me_cleaner.md) diff --git a/Documentation/northbridge/intel/sandybridge/me_cleaner.md b/Documentation/northbridge/intel/sandybridge/me_cleaner.md new file mode 100644 index 0000000000..1086e7e091 --- /dev/null +++ b/Documentation/northbridge/intel/sandybridge/me_cleaner.md @@ -0,0 +1,20 @@ +# ME Cleaner +It's possible to 'clean' the ME partition within the flash medium as part +of the build process. While cleaning as much code as possible is removed +from the ME firmware partition. In this state the ME errors out and doesn't +operate any more. + +**Using a 'cleaned' ME partition may lead to issues and its use should be +carefully evaulated.** + +## Observations with 'cleaned' ME + +* Instable LPC bus + * SuperIO is malfunctioning + * TPM is malfunctioning + * Random system shutdowns on high bus activity + +## Filing bug reports + +Always test with unmodified IFD and ME section before reporting bugs to the +coreboot project. From 1bffc4bda3b66ba2c91163ec396c54e51d2f056b Mon Sep 17 00:00:00 2001 From: Alex James Date: Wed, 15 May 2019 20:42:27 -0500 Subject: [PATCH 211/331] mb/gigabyte/ga-b75m-d3{h,v}: Switch to variant setup The Gigabyte GA-B75M-D3H/D3V mainboard trees share a lot of duplicate code, and can serve as a base for porting other Gigabyte 7 series motherboards. Switch the Gigabyte GA-B75M-D3H/D3V mainboard trees to a variant setup, defining ga-b75m-d3v as a variant of ga-b75m-d3h. Signed-off-by: Alex James Change-Id: Ia175207a2568aefe1aa9bd8d4d990de6a26f1657 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32708 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/mainboard/gigabyte/ga-b75m-d3h/Kconfig | 17 ++- .../gigabyte/ga-b75m-d3h/Kconfig.name | 3 + .../gigabyte/ga-b75m-d3h/Makefile.inc | 9 +- src/mainboard/gigabyte/ga-b75m-d3h/hda_verb.c | 4 +- src/mainboard/gigabyte/ga-b75m-d3h/romstage.c | 1 + .../ga-b75m-d3h}/gma-mainboard.ads | 0 .../{ => variants/ga-b75m-d3h}/gpio.c | 0 .../ga-b75m-d3h/include/variant/hda_verb.h} | 15 +-- .../variants}/ga-b75m-d3v/board_info.txt | 0 .../variants}/ga-b75m-d3v/gma-mainboard.ads | 0 .../variants}/ga-b75m-d3v/gpio.c | 0 .../ga-b75m-d3v/include/variant/hda_verb.h} | 7 +- src/mainboard/gigabyte/ga-b75m-d3v/Kconfig | 41 ------ .../gigabyte/ga-b75m-d3v/Kconfig.name | 2 - .../gigabyte/ga-b75m-d3v/Makefile.inc | 17 --- .../gigabyte/ga-b75m-d3v/acpi/ec.asl | 0 .../gigabyte/ga-b75m-d3v/acpi/mainboard.asl | 23 ---- .../gigabyte/ga-b75m-d3v/acpi/platform.asl | 29 ---- .../gigabyte/ga-b75m-d3v/acpi/superio.asl | 0 .../gigabyte/ga-b75m-d3v/acpi/thermal.asl | 63 --------- .../gigabyte/ga-b75m-d3v/acpi_tables.c | 39 ------ .../gigabyte/ga-b75m-d3v/cmos.default | 6 - .../gigabyte/ga-b75m-d3v/cmos.layout | 107 --------------- src/mainboard/gigabyte/ga-b75m-d3v/data.vbt | Bin 3902 -> 0 bytes .../gigabyte/ga-b75m-d3v/devicetree.cb | 124 ------------------ src/mainboard/gigabyte/ga-b75m-d3v/dsdt.asl | 43 ------ .../gigabyte/ga-b75m-d3v/mainboard.c | 34 ----- src/mainboard/gigabyte/ga-b75m-d3v/romstage.c | 104 --------------- 28 files changed, 34 insertions(+), 654 deletions(-) rename src/mainboard/gigabyte/ga-b75m-d3h/{ => variants/ga-b75m-d3h}/gma-mainboard.ads (100%) rename src/mainboard/gigabyte/ga-b75m-d3h/{ => variants/ga-b75m-d3h}/gpio.c (100%) rename src/mainboard/gigabyte/{ga-b75m-d3v/thermal.h => ga-b75m-d3h/variants/ga-b75m-d3h/include/variant/hda_verb.h} (61%) rename src/mainboard/gigabyte/{ => ga-b75m-d3h/variants}/ga-b75m-d3v/board_info.txt (100%) rename src/mainboard/gigabyte/{ => ga-b75m-d3h/variants}/ga-b75m-d3v/gma-mainboard.ads (100%) rename src/mainboard/gigabyte/{ => ga-b75m-d3h/variants}/ga-b75m-d3v/gpio.c (100%) rename src/mainboard/gigabyte/{ga-b75m-d3v/hda_verb.c => ga-b75m-d3h/variants/ga-b75m-d3v/include/variant/hda_verb.h} (93%) delete mode 100644 src/mainboard/gigabyte/ga-b75m-d3v/Kconfig delete mode 100644 src/mainboard/gigabyte/ga-b75m-d3v/Kconfig.name delete mode 100644 src/mainboard/gigabyte/ga-b75m-d3v/Makefile.inc delete mode 100644 src/mainboard/gigabyte/ga-b75m-d3v/acpi/ec.asl delete mode 100644 src/mainboard/gigabyte/ga-b75m-d3v/acpi/mainboard.asl delete mode 100644 src/mainboard/gigabyte/ga-b75m-d3v/acpi/platform.asl delete mode 100644 src/mainboard/gigabyte/ga-b75m-d3v/acpi/superio.asl delete mode 100644 src/mainboard/gigabyte/ga-b75m-d3v/acpi/thermal.asl delete mode 100644 src/mainboard/gigabyte/ga-b75m-d3v/acpi_tables.c delete mode 100644 src/mainboard/gigabyte/ga-b75m-d3v/cmos.default delete mode 100644 src/mainboard/gigabyte/ga-b75m-d3v/cmos.layout delete mode 100644 src/mainboard/gigabyte/ga-b75m-d3v/data.vbt delete mode 100644 src/mainboard/gigabyte/ga-b75m-d3v/devicetree.cb delete mode 100644 src/mainboard/gigabyte/ga-b75m-d3v/dsdt.asl delete mode 100644 src/mainboard/gigabyte/ga-b75m-d3v/mainboard.c delete mode 100644 src/mainboard/gigabyte/ga-b75m-d3v/romstage.c diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/Kconfig b/src/mainboard/gigabyte/ga-b75m-d3h/Kconfig index af884f62fb..ceb2dbc85f 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/Kconfig +++ b/src/mainboard/gigabyte/ga-b75m-d3h/Kconfig @@ -1,4 +1,4 @@ -if BOARD_GIGABYTE_GA_B75M_D3H +if BOARD_GIGABYTE_GA_B75M_D3H || BOARD_GIGABYTE_GA_B75M_D3V config BOARD_SPECIFIC_OPTIONS def_bool y @@ -30,12 +30,23 @@ config MAINBOARD_DIR string default gigabyte/ga-b75m-d3h +config VARIANT_DIR + string + default "ga-b75m-d3h" if BOARD_GIGABYTE_GA_B75M_D3H + default "ga-b75m-d3v" if BOARD_GIGABYTE_GA_B75M_D3V + config MAINBOARD_PART_NUMBER string - default "GA-B75M-D3H" + default "GA-B75M-D3H" if BOARD_GIGABYTE_GA_B75M_D3H + default "GA-B75M-D3V" if BOARD_GIGABYTE_GA_B75M_D3V config MAX_CPUS int default 8 -endif # BOARD_GIGABYTE_GA_B75M_D3H +# Override the default variant behavior, since the data.vbt is the same +config INTEL_GMA_VBT_FILE + string + default "src/mainboard/$(MAINBOARDDIR)/data.vbt" + +endif # BOARD_GIGABYTE_GA_B75M* diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/Kconfig.name b/src/mainboard/gigabyte/ga-b75m-d3h/Kconfig.name index 571f6d1647..f8fbe54215 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/Kconfig.name +++ b/src/mainboard/gigabyte/ga-b75m-d3h/Kconfig.name @@ -1,2 +1,5 @@ config BOARD_GIGABYTE_GA_B75M_D3H bool "GA-B75M-D3H" + +config BOARD_GIGABYTE_GA_B75M_D3V + bool "GA-B75M-D3V" diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/Makefile.inc b/src/mainboard/gigabyte/ga-b75m-d3h/Makefile.inc index 63976c4b79..07fc277c28 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/Makefile.inc +++ b/src/mainboard/gigabyte/ga-b75m-d3h/Makefile.inc @@ -13,5 +13,10 @@ ## GNU General Public License for more details. ## -romstage-y += gpio.c -ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads +romstage-y += variants/$(VARIANT_DIR)/gpio.c + +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += variants/$(VARIANT_DIR)/gma-mainboard.ads + +subdirs-y += variants/$(VARIANT_DIR) + +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/hda_verb.c b/src/mainboard/gigabyte/ga-b75m-d3h/hda_verb.c index 23cd570fb2..34610f09ee 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/hda_verb.c +++ b/src/mainboard/gigabyte/ga-b75m-d3h/hda_verb.c @@ -13,9 +13,7 @@ #include -const u32 cim_verb_data[] = { - /* FIXME: Add configuration for sound */ -}; +#include const u32 pc_beep_verbs[] = {}; diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c b/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c index 49647850cd..67bcbcb8c9 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c +++ b/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c @@ -88,6 +88,7 @@ void mainboard_early_init(int s3resume) { } +/* FIXME: The GA-B75M-D3V only has two DIMM slots! */ void mainboard_get_spd(spd_raw_data *spd, bool id_only) { read_spd(&spd[0], 0x50, id_only); diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/gma-mainboard.ads b/src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75m-d3h/gma-mainboard.ads similarity index 100% rename from src/mainboard/gigabyte/ga-b75m-d3h/gma-mainboard.ads rename to src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75m-d3h/gma-mainboard.ads diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/gpio.c b/src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75m-d3h/gpio.c similarity index 100% rename from src/mainboard/gigabyte/ga-b75m-d3h/gpio.c rename to src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75m-d3h/gpio.c diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/thermal.h b/src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75m-d3h/include/variant/hda_verb.h similarity index 61% rename from src/mainboard/gigabyte/ga-b75m-d3v/thermal.h rename to src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75m-d3h/include/variant/hda_verb.h index 9db69104a0..53e7c65ddb 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3v/thermal.h +++ b/src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75m-d3h/include/variant/hda_verb.h @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. - * Copyright (C) 2014 Vladimir Serbinenko - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. @@ -14,13 +11,11 @@ * GNU General Public License for more details. */ -#ifndef GAB75MD3H_THERMAL_H -#define GAB75MD3H_THERMAL_H +#ifndef GA_B75M_D3H_HDA_VERB_H +#define GA_B75M_D3H_HDA_VERB_H - /* Temperature which OS will shutdown at */ - #define CRITICAL_TEMPERATURE 100 - - /* Temperature which OS will throttle CPU */ - #define PASSIVE_TEMPERATURE 90 +const u32 cim_verb_data[] = { + /* FIXME: Add configuration for sound */ +}; #endif diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/board_info.txt b/src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75m-d3v/board_info.txt similarity index 100% rename from src/mainboard/gigabyte/ga-b75m-d3v/board_info.txt rename to src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75m-d3v/board_info.txt diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/gma-mainboard.ads b/src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75m-d3v/gma-mainboard.ads similarity index 100% rename from src/mainboard/gigabyte/ga-b75m-d3v/gma-mainboard.ads rename to src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75m-d3v/gma-mainboard.ads diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/gpio.c b/src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75m-d3v/gpio.c similarity index 100% rename from src/mainboard/gigabyte/ga-b75m-d3v/gpio.c rename to src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75m-d3v/gpio.c diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/hda_verb.c b/src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75m-d3v/include/variant/hda_verb.h similarity index 93% rename from src/mainboard/gigabyte/ga-b75m-d3v/hda_verb.c rename to src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75m-d3v/include/variant/hda_verb.h index 3ae6b5d01e..c84c80df7b 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3v/hda_verb.c +++ b/src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75m-d3v/include/variant/hda_verb.h @@ -11,7 +11,8 @@ * GNU General Public License for more details. */ -#include +#ifndef GA_B75M_D3V_HDA_VERB_H +#define GA_B75M_D3V_HDA_VERB_H const u32 cim_verb_data[] = { /* coreboot specific header */ @@ -36,6 +37,4 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x1f, 0x411111f0) }; -const u32 pc_beep_verbs[] = {}; - -AZALIA_ARRAY_SIZES; +#endif diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/Kconfig b/src/mainboard/gigabyte/ga-b75m-d3v/Kconfig deleted file mode 100644 index d86c742b37..0000000000 --- a/src/mainboard/gigabyte/ga-b75m-d3v/Kconfig +++ /dev/null @@ -1,41 +0,0 @@ -if BOARD_GIGABYTE_GA_B75M_D3V - -config BOARD_SPECIFIC_OPTIONS - def_bool y - select ARCH_X86 - select NORTHBRIDGE_INTEL_SANDYBRIDGE - select USE_NATIVE_RAMINIT - select SOUTHBRIDGE_INTEL_C216 - select SUPERIO_ITE_IT8728F - select BOARD_ROMSIZE_KB_8192 - select HAVE_ACPI_TABLES - select HAVE_OPTION_TABLE - select HAVE_CMOS_DEFAULT - select HAVE_ACPI_RESUME - select INTEL_GMA_HAVE_VBT - select INTEL_INT15 - select SERIRQ_CONTINUOUS_MODE - select MAINBOARD_HAS_LIBGFXINIT - select MAINBOARD_HAS_LPC_TPM - -config DRAM_RESET_GATE_GPIO - int - default 25 - -config USBDEBUG_HCD_INDEX - int - default 2 - -config MAINBOARD_DIR - string - default gigabyte/ga-b75m-d3v - -config MAINBOARD_PART_NUMBER - string - default "GA-B75M-D3V" - -config MAX_CPUS - int - default 8 - -endif # BOARD_GIGABYTE_GA_B75M_D3V diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/Kconfig.name b/src/mainboard/gigabyte/ga-b75m-d3v/Kconfig.name deleted file mode 100644 index 92f5744f2d..0000000000 --- a/src/mainboard/gigabyte/ga-b75m-d3v/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config BOARD_GIGABYTE_GA_B75M_D3V - bool "GA-B75M-D3V" diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/Makefile.inc b/src/mainboard/gigabyte/ga-b75m-d3v/Makefile.inc deleted file mode 100644 index 63976c4b79..0000000000 --- a/src/mainboard/gigabyte/ga-b75m-d3v/Makefile.inc +++ /dev/null @@ -1,17 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -romstage-y += gpio.c -ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/acpi/ec.asl b/src/mainboard/gigabyte/ga-b75m-d3v/acpi/ec.asl deleted file mode 100644 index e69de29bb2..0000000000 diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/acpi/mainboard.asl b/src/mainboard/gigabyte/ga-b75m-d3v/acpi/mainboard.asl deleted file mode 100644 index a1c79896d7..0000000000 --- a/src/mainboard/gigabyte/ga-b75m-d3v/acpi/mainboard.asl +++ /dev/null @@ -1,23 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Google Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -Scope (\_SB) -{ - Device (PWRB) - { - Name (_HID, EisaId ("PNP0C0C")) - } -} diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/acpi/platform.asl b/src/mainboard/gigabyte/ga-b75m-d3v/acpi/platform.asl deleted file mode 100644 index 10856d3394..0000000000 --- a/src/mainboard/gigabyte/ga-b75m-d3v/acpi/platform.asl +++ /dev/null @@ -1,29 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 The Chromium OS Authors. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* The _PTS method (Prepare To Sleep) is called before the OS is - * entering a sleep state. The sleep state number is passed in Arg0 - */ - -Method (_PTS, 1) -{ -} - -/* The _WAK method is called on system wakeup */ - -Method(_WAK,1) -{ - Return (Package () {0, 0}) -} diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/acpi/superio.asl b/src/mainboard/gigabyte/ga-b75m-d3v/acpi/superio.asl deleted file mode 100644 index e69de29bb2..0000000000 diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/acpi/thermal.asl b/src/mainboard/gigabyte/ga-b75m-d3v/acpi/thermal.asl deleted file mode 100644 index ca561a5039..0000000000 --- a/src/mainboard/gigabyte/ga-b75m-d3v/acpi/thermal.asl +++ /dev/null @@ -1,63 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -// Thermal Zone - -External (\PPKG, MethodObj) - -Scope (\_TZ) -{ - ThermalZone (THRM) - { - Name (_TC1, 0x02) - Name (_TC2, 0x03) - - // Thermal zone polling frequency: 10 seconds - Name (_TZP, 100) - - // Thermal sampling period for passive cooling: 10 seconds - Name (_TSP, 100) - - // Convert from Degrees C to 1/10 Kelvin for ACPI - Method (CTOK, 1) - { - // 10th of Degrees C - Multiply (Arg0, 10, Local0) - - // Convert to Kelvin - Add (Local0, 2732, Local0) - - Return (Local0) - } - - // Threshold for OS to shutdown - Method (_CRT, 0, Serialized) - { - Return (CTOK (\TCRT)) - } - - // Threshold for passive cooling - Method (_PSV, 0, Serialized) - { - Return (CTOK (\TPSV)) - } - - // Processors used for passive cooling - Method (_PSL, 0, Serialized) - { - Return (\PPKG ()) - } - } -} diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/acpi_tables.c b/src/mainboard/gigabyte/ga-b75m-d3v/acpi_tables.c deleted file mode 100644 index 5c09059173..0000000000 --- a/src/mainboard/gigabyte/ga-b75m-d3v/acpi_tables.c +++ /dev/null @@ -1,39 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include "thermal.h" - -static void acpi_update_thermal_table(global_nvs_t *gnvs) -{ - gnvs->tcrt = CRITICAL_TEMPERATURE; - gnvs->tpsv = PASSIVE_TEMPERATURE; -} - -void acpi_create_gnvs(global_nvs_t *gnvs) -{ - memset((void *)gnvs, 0, sizeof(*gnvs)); - - /* Disable USB ports in S3 by default */ - gnvs->s3u0 = 0; - gnvs->s3u1 = 0; - - /* Disable USB ports in S5 by default */ - gnvs->s5u0 = 0; - gnvs->s5u1 = 0; - - acpi_update_thermal_table(gnvs); -} diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/cmos.default b/src/mainboard/gigabyte/ga-b75m-d3v/cmos.default deleted file mode 100644 index 6f3cec735e..0000000000 --- a/src/mainboard/gigabyte/ga-b75m-d3v/cmos.default +++ /dev/null @@ -1,6 +0,0 @@ -boot_option=Fallback -debug_level=Debug -power_on_after_fail=Enable -nmi=Enable -sata_mode=AHCI -gfx_uma_size=32M diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/cmos.layout b/src/mainboard/gigabyte/ga-b75m-d3v/cmos.layout deleted file mode 100644 index 095e3833e1..0000000000 --- a/src/mainboard/gigabyte/ga-b75m-d3v/cmos.layout +++ /dev/null @@ -1,107 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2007-2008 coresystems GmbH -## Copyright (C) 2014 Vladimir Serbinenko -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -# ----------------------------------------------------------------- -entries - -# ----------------------------------------------------------------- -# Status Register A -# ----------------------------------------------------------------- -# Status Register B -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 - -# ----------------------------------------------------------------- -0 120 r 0 reserved_memory -#120 264 r 0 unused - -# ----------------------------------------------------------------- -# RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter -#390 2 r 0 unused? - -# ----------------------------------------------------------------- -# coreboot config options: console -#392 3 r 0 unused -395 4 e 6 debug_level -#399 1 r 0 unused - -# coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 7 power_on_after_fail - -#411 10 r 0 unused -421 1 e 9 sata_mode -#422 2 r 0 unused - -# coreboot config options: cpu -#425 7 r 0 unused - -# coreboot config options: northbridge -432 3 e 11 gfx_uma_size -#435 549 r 0 unused - -# coreboot config options: check sums -984 16 h 0 check_sum - -# ----------------------------------------------------------------- - -enumerations - -#ID value text -1 0 Disable -1 1 Enable -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -7 0 Disable -7 1 Enable -7 2 Keep -9 0 AHCI -9 1 IDE -11 0 32M -11 1 64M -11 2 96M -11 3 128M -11 4 160M -11 5 192M -11 6 224M - -# ----------------------------------------------------------------- -checksums - -checksum 392 439 984 diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/data.vbt b/src/mainboard/gigabyte/ga-b75m-d3v/data.vbt deleted file mode 100644 index ccbf6eed7f940d3e2de666eed4af9c9184e63c4b..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 3902 zcmdT{Z){Ul6hE);_22D#tb3c#)v=r*fo|;2YngLdroMLFTu0fuwKSC&>7eCLGR7!> z0*Sbyi(pJhH3kvUG@2;x6XBDIe&CZ?j4=x_#27yi;s-;B;R7*|AoaXI9fT=+F%t2< z{O-B;^xWUO_uO;teO;T5q%b)W>5Qc#?a_hcrqpO62MRn_Ge`B(5{Zo_w?)IL@U}>N zw0{$R1}kAj&E4w&IpFG~Q1I!V*wn%NWMI4nlM_?9quUF6a=Y@KvBPEy6a6s^@7R%_ z%oipO=5v@#zYs=^R$`GudnR)@a%k`Ne4!ULF0#g8SI5RK#9**9w6Qa!1Vf0*Gre8G z-rz=wMF;vvHz#88a4I%Bf}`UYjU~g$PaY0=xV4Hwmut}Uv0BCl>8n5YH z)FkQn`}?H0oCU8}c&`q01A4LDFyN5d04iM34L&ywTsjH;fE?O112h@FG!2N~q3LM_ zSbdk?r3$N!zmt#3KxhOd)YaY7+owjNgG0md#CR&5+4@rP_-n7v`r%FqXt5ke)e265 z1RsE7ybVt9J+MJ2!>Xd`cxF&_oCjLWDlTAR$56O2`qW2#!N=r(!FDQ+HL7Gi9wI!7IS27AT%G_2*2z`zGx$ z6=q70DRrfVs#0+};cn$SA5B%D66hK4JD#BsIH?*{@XGS?Y%9 zd2}`V1SlRK_u}~!nu|0^GaFEwFK3@#t;xkwq}KfgHhbaW28$!BjRzU3`bD{{fmjE_ zbRzJszF8xTwg6O4tZ)POp?xd-Zf}R0x4>d{vnSpN|? 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See the - * GNU General Public License for more details. - */ - -#include -DefinitionBlock( - "dsdt.aml", - "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up - OEM_ID, - ACPI_TABLE_CREATOR, - 0x20141018 // OEM revision -) -{ - #include - - // Some generic macros - #include "acpi/mainboard.asl" - #include "acpi/platform.asl" - #include "acpi/thermal.asl" - #include - /* global NVS and variables. */ - #include - #include - - Scope (\_SB) { - Device (PCI0) - { - #include - #include - #include - } - } -} diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/mainboard.c b/src/mainboard/gigabyte/ga-b75m-d3v/mainboard.c deleted file mode 100644 index cc26757914..0000000000 --- a/src/mainboard/gigabyte/ga-b75m-d3v/mainboard.c +++ /dev/null @@ -1,34 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2011-2012 Google Inc. - * Copyright (C) 2014 Vladimir Serbinenko - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include - -// mainboard_enable is executed as first thing after -// enumerate_buses(). - -static void mainboard_enable(struct device *dev) -{ - install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_NONE, - GMA_INT15_PANEL_FIT_DEFAULT, - GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); -} - -struct chip_operations mainboard_ops = { - .enable_dev = mainboard_enable -}; diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/romstage.c b/src/mainboard/gigabyte/ga-b75m-d3v/romstage.c deleted file mode 100644 index eb88d366ae..0000000000 --- a/src/mainboard/gigabyte/ga-b75m-d3v/romstage.c +++ /dev/null @@ -1,104 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Damien Zammit - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include - -#define SUPERIO_BASE 0x2e -#define SUPERIO_DEV PNP_DEV(SUPERIO_BASE, 0) -#define SIO_GPIO PNP_DEV(SUPERIO_BASE, IT8728F_GPIO) -#define SERIAL_DEV PNP_DEV(SUPERIO_BASE, 0x01) - -void pch_enable_lpc(void) -{ - pci_write_config16(PCH_LPC_DEV, LPC_EN, KBC_LPC_EN | - CNF1_LPC_EN | CNF2_LPC_EN | COMA_LPC_EN); - - pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x3c0a01); - pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10); - - pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000); -} - -void mainboard_config_superio(void) -{ - /* Initialize SuperIO */ - ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - - ite_reg_write(SIO_GPIO, 0xEF, 0x7E); // magic SIO disable reboot - - /* FIXME: These values could be configured in ramstage */ - ite_reg_write(SIO_GPIO, 0x25, 0x40); // gpio pin function -> gp16 - ite_reg_write(SIO_GPIO, 0x27, 0x10); // gpio pin function -> gp34 - ite_reg_write(SIO_GPIO, 0x2c, 0x80); // smbus isolation on parallel port - ite_reg_write(SIO_GPIO, 0x62, 0x0a); // simple iobase 0xa00 - ite_reg_write(SIO_GPIO, 0x72, 0x20); // watchdog timeout clear! - ite_reg_write(SIO_GPIO, 0x73, 0x00); // watchdog timeout clear! - ite_reg_write(SIO_GPIO, 0xcb, 0x00); // simple io set4 direction -> in - ite_reg_write(SIO_GPIO, 0xe9, 0x27); // bus select disable - ite_reg_write(SIO_GPIO, 0xf0, 0x10); // ? - ite_reg_write(SIO_GPIO, 0xf1, 0x42); // ? - ite_reg_write(SIO_GPIO, 0xf6, 0x1c); // hwmon alert beep -> gp36(pin12) - - /* EC SIO settings */ - ite_reg_write(IT8728F_EC, 0xf1, 0xc0); - ite_reg_write(IT8728F_EC, 0xf6, 0xf0); - ite_reg_write(IT8728F_EC, 0xf9, 0x48); - ite_reg_write(IT8728F_EC, 0x60, 0x0a); - ite_reg_write(IT8728F_EC, 0x61, 0x30); - ite_reg_write(IT8728F_EC, 0x62, 0x0a); - ite_reg_write(IT8728F_EC, 0x63, 0x20); - ite_reg_write(IT8728F_EC, 0x30, 0x01); -} - -const struct southbridge_usb_port mainboard_usb_ports[] = { - { 1, 5, 0 }, - { 1, 5, 0 }, - { 1, 5, 1 }, - { 1, 5, 1 }, - { 1, 5, 2 }, - { 1, 5, 2 }, - { 1, 5, 3 }, - { 1, 5, 3 }, - { 1, 5, 4 }, - { 1, 5, 4 }, - { 1, 5, 6 }, - { 1, 5, 5 }, - { 1, 5, 5 }, - { 1, 5, 6 }, -}; - -void mainboard_early_init(int s3resume) -{ -} - -/* FIXME: This board only has two DIMM slots! */ -void mainboard_get_spd(spd_raw_data *spd, bool id_only) -{ - read_spd(&spd[0], 0x50, id_only); - read_spd(&spd[1], 0x51, id_only); - read_spd(&spd[2], 0x52, id_only); - read_spd(&spd[3], 0x53, id_only); -} - -void mainboard_rcba_config(void) -{ - /* Enable HECI */ - RCBA32(FD2) &= ~0x2; -} From 87c4f11c64713c8a90d7a6ffe997da891c9758d4 Mon Sep 17 00:00:00 2001 From: Tobias Diedrich Date: Thu, 7 Dec 2017 22:40:20 +0100 Subject: [PATCH 212/331] intel/sandybridge: Make timC training more robust. When using native raminit with https://review.coreboot.org/#/c/22683/ I've found that timC training usually fails unless the ram is overspecced (i.e. DDR3L-1600 rated for 1.35V works most of the time with native raminit as DDR3-1333 @1.5V). Looking at the training data I've found that during timC training it is reading register values in the 0-4000 range and checking for runs of 0, but with the failing training the values don't go all the way down to 0. The solution for me has been to do a thresholing pre-pass, after which both the DDR3-1333 @1.5V and the DDR3L-1600 @1.35V work fine for me. Tested: - Intel NUC DCP847SKE - RAM slots with 2x4GB Kingston KVR1333D3S9/4G (DDR3-1333 1.5V), boots fine with native raminit @1.5V - RAM slots with 2x4GB Kingston KVR16LS11/4G (DDR3L-1600 1.35V), boots fine with native raminit @1.35V - Casual use with these settings - Tested on Lenovo T520 with Crucial HyperX DDR3-1833. - Memtest86+ stable. Change-Id: I9986616e86560c4980ccd8e3e549af53caa15c71 Signed-off-by: Tobias Diedrich Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/c/coreboot/+/22776 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- .../intel/sandybridge/raminit_common.c | 39 ++++++++++++++++--- 1 file changed, 34 insertions(+), 5 deletions(-) diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 5347c5c493..53f28c6cd6 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -1524,6 +1524,24 @@ static void test_timC(ramctr_timing * ctrl, int channel, int slotrank) wait_428c(channel); } +static void timC_threshold_process(int *data, const int count) +{ + int min = data[0]; + int max = min; + int i; + for (i = 1; i < count; i++) { + if (min > data[i]) + min = data[i]; + if (max < data[i]) + max = data[i]; + } + int threshold = min/2 + max/2; + for (i = 0; i < count; i++) + data[i] = data[i] > threshold; + printram("threshold=%d min=%d max=%d\n", + threshold, min, max); +} + static int discover_timC(ramctr_timing *ctrl, int channel, int slotrank) { int timC; @@ -1554,14 +1572,25 @@ static int discover_timC(ramctr_timing *ctrl, int channel, int slotrank) } } FOR_ALL_LANES { - struct run rn = - get_longest_zero_run(statistics[lane], MAX_TIMC + 1); - ctrl->timings[channel][slotrank].lanes[lane].timC = rn.middle; - if (rn.all) { + struct run rn = get_longest_zero_run( + statistics[lane], ARRAY_SIZE(statistics[lane])); + if (rn.all || rn.length < 8) { printk(BIOS_EMERG, "timC discovery failed: %d, %d, %d\n", channel, slotrank, lane); - return MAKE_ERR; + /* With command training not happend yet, the lane can + * be erroneous. Take the avarage as reference and try + * again to find a run. + */ + timC_threshold_process(statistics[lane], + ARRAY_SIZE(statistics[lane])); + rn = get_longest_zero_run(statistics[lane], + ARRAY_SIZE(statistics[lane])); + if (rn.all || rn.length < 8) { + printk(BIOS_EMERG, "timC recovery failed\n"); + return MAKE_ERR; + } } + ctrl->timings[channel][slotrank].lanes[lane].timC = rn.middle; printram("timC: %d, %d, %d: 0x%02x-0x%02x-0x%02x\n", channel, slotrank, lane, rn.start, rn.middle, rn.end); } From 6d6945b807469675f872124f33250d2e5c0f14b8 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Sat, 29 Dec 2018 14:00:46 +0100 Subject: [PATCH 213/331] soc/intel/apollolake: Don't use CAR_GLOBAL MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit All platforms using this code have NO_CAR_GLOBAL_MIGRATION. Change-Id: I0f393385aa94f18c2e05af3b5a54999575323d18 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/30510 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki --- src/soc/intel/apollolake/meminit.c | 7 +++---- src/soc/intel/apollolake/mmap_boot.c | 29 +++++++++------------------- src/soc/intel/apollolake/romstage.c | 7 +++---- 3 files changed, 15 insertions(+), 28 deletions(-) diff --git a/src/soc/intel/apollolake/meminit.c b/src/soc/intel/apollolake/meminit.c index 038fa9fb2b..219b661042 100644 --- a/src/soc/intel/apollolake/meminit.c +++ b/src/soc/intel/apollolake/meminit.c @@ -12,7 +12,6 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ -#include #include #include #include @@ -21,11 +20,11 @@ #include #include -static size_t memory_size_mib CAR_GLOBAL; +static size_t memory_size_mib; size_t memory_in_system_in_mib(void) { - return car_get_var(memory_size_mib); + return memory_size_mib; } static void accumulate_channel_memory(int density, int dual_rank) @@ -61,7 +60,7 @@ static void accumulate_channel_memory(int density, int dual_rank) sz *= GiB / MiB; - car_set_var(memory_size_mib, car_get_var(memory_size_mib) + sz); + memory_size_mib += sz; } size_t iohole_in_mib(void) diff --git a/src/soc/intel/apollolake/mmap_boot.c b/src/soc/intel/apollolake/mmap_boot.c index 1c3077ed91..614b6031c4 100644 --- a/src/soc/intel/apollolake/mmap_boot.c +++ b/src/soc/intel/apollolake/mmap_boot.c @@ -16,7 +16,6 @@ * GNU General Public License for more details. */ -#include #include #include #include @@ -57,17 +56,17 @@ * */ -static size_t bios_size CAR_GLOBAL; +static size_t bios_size; -static struct mem_region_device shadow_dev CAR_GLOBAL; -static struct xlate_region_device real_dev CAR_GLOBAL; +static struct mem_region_device shadow_dev; +static struct xlate_region_device real_dev; static void bios_mmap_init(void) { size_t size, start, bios_mapped_size; uintptr_t base; - size = car_get_var(bios_size); + size = bios_size; /* If bios_size is initialized, then bail out. */ if (size != 0) @@ -83,34 +82,25 @@ static void bios_mmap_init(void) */ bios_mapped_size = size - 256 * KiB; - struct mem_region_device *shadow_dev_ptr; - struct xlate_region_device *real_dev_ptr; - shadow_dev_ptr = car_get_var_ptr(&shadow_dev); - real_dev_ptr = car_get_var_ptr(&real_dev); - - mem_region_device_ro_init(shadow_dev_ptr, (void *)base, + mem_region_device_ro_init(&shadow_dev, (void *)base, bios_mapped_size); - xlate_region_device_ro_init(real_dev_ptr, &shadow_dev_ptr->rdev, + xlate_region_device_ro_init(&real_dev, &shadow_dev.rdev, start, bios_mapped_size, CONFIG_ROM_SIZE); - car_set_var(bios_size, size); + bios_size = size; } const struct region_device *boot_device_ro(void) { bios_mmap_init(); - struct xlate_region_device *real_dev_ptr; - real_dev_ptr = car_get_var_ptr(&real_dev); - - return &real_dev_ptr->rdev; + return &real_dev.rdev; } static int iafw_boot_region_properties(struct cbfs_props *props) { - struct xlate_region_device *real_dev_ptr; struct region *real_dev_reg; struct region regn; @@ -123,8 +113,7 @@ static int iafw_boot_region_properties(struct cbfs_props *props) /* Check that we are within the memory mapped area. It's too easy to forget the SRAM mapping when crafting an FMAP file. */ - real_dev_ptr = car_get_var_ptr(&real_dev); - real_dev_reg = &real_dev_ptr->sub_region; + real_dev_reg = &real_dev.sub_region; if (region_is_subregion(real_dev_reg, ®n)) { printk(BIOS_DEBUG, "CBFS @ %zx size %zx\n", props->offset, props->size); diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index c976ac2d6f..5bf501dcfa 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -17,7 +17,6 @@ */ #include -#include #include #include #include @@ -57,7 +56,7 @@ static const uint8_t hob_variable_guid[16] = { 0x8d, 0xe6, 0xc0, 0x44, 0x64, 0x1d, 0xe9, 0x42, }; -static uint32_t fsp_version CAR_GLOBAL; +static uint32_t fsp_version; /* High Performance Event Timer Configuration */ #define P2SB_HPTC 0x60 @@ -236,7 +235,7 @@ asmlinkage void car_stage_entry(void) &var_size); if (new_var_data) mrc_cache_stash_data(MRC_VARIABLE_DATA, - car_get_var(fsp_version), new_var_data, + fsp_version, new_var_data, var_size); else printk(BIOS_ERR, "Failed to determine variable data\n"); @@ -410,7 +409,7 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) mupd->FspmConfig.VariableNvsBufferPtr = rdev_mmap_full(&rdev); } - car_set_var(fsp_version, version); + fsp_version = version; } From 8a1b94ccbeca88b8fba96329477e99ea8535c244 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Sat, 25 May 2019 09:47:01 +0200 Subject: [PATCH 214/331] Clean up unused arch/early_variables.h header MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: Ib863e23863ba6d7504b6c4d32de2f1fea4e57fec Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/32996 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki --- src/drivers/intel/fsp1_1/car.c | 2 +- src/drivers/intel/fsp1_1/hob.c | 1 - src/drivers/intel/fsp1_1/romstage.c | 1 - src/mainboard/packardbell/ms2290/romstage.c | 1 - src/soc/intel/broadwell/romstage/romstage.c | 1 - src/soc/intel/broadwell/romstage/uart.c | 1 - src/soc/intel/common/block/fast_spi/fast_spi_flash.c | 1 - src/soc/intel/common/block/scs/early_mmc.c | 1 - src/soc/intel/skylake/romstage/romstage.c | 1 - src/soc/intel/skylake/romstage/romstage_fsp20.c | 1 - 10 files changed, 1 insertion(+), 10 deletions(-) diff --git a/src/drivers/intel/fsp1_1/car.c b/src/drivers/intel/fsp1_1/car.c index 34b2518c38..a1ee7b141a 100644 --- a/src/drivers/intel/fsp1_1/car.c +++ b/src/drivers/intel/fsp1_1/car.c @@ -13,7 +13,7 @@ * GNU General Public License for more details. */ -#include +#include #include #include #include diff --git a/src/drivers/intel/fsp1_1/hob.c b/src/drivers/intel/fsp1_1/hob.c index ee1a6a328e..0a123cff78 100644 --- a/src/drivers/intel/fsp1_1/hob.c +++ b/src/drivers/intel/fsp1_1/hob.c @@ -14,7 +14,6 @@ * GNU General Public License for more details. */ -#include #include #include #include diff --git a/src/drivers/intel/fsp1_1/romstage.c b/src/drivers/intel/fsp1_1/romstage.c index 85badced89..45ca87aac8 100644 --- a/src/drivers/intel/fsp1_1/romstage.c +++ b/src/drivers/intel/fsp1_1/romstage.c @@ -18,7 +18,6 @@ #include #include #include -#include #include #include #include diff --git a/src/mainboard/packardbell/ms2290/romstage.c b/src/mainboard/packardbell/ms2290/romstage.c index efaa9e423d..0ab5544858 100644 --- a/src/mainboard/packardbell/ms2290/romstage.c +++ b/src/mainboard/packardbell/ms2290/romstage.c @@ -31,7 +31,6 @@ #include #include -#include "arch/early_variables.h" #include #include diff --git a/src/soc/intel/broadwell/romstage/romstage.c b/src/soc/intel/broadwell/romstage/romstage.c index f8571678d8..9bca716447 100644 --- a/src/soc/intel/broadwell/romstage/romstage.c +++ b/src/soc/intel/broadwell/romstage/romstage.c @@ -16,7 +16,6 @@ #include #include #include -#include #include #include #include diff --git a/src/soc/intel/broadwell/romstage/uart.c b/src/soc/intel/broadwell/romstage/uart.c index 58450dd834..a1a29b65fd 100644 --- a/src/soc/intel/broadwell/romstage/uart.c +++ b/src/soc/intel/broadwell/romstage/uart.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include #include #include #include diff --git a/src/soc/intel/common/block/fast_spi/fast_spi_flash.c b/src/soc/intel/common/block/fast_spi/fast_spi_flash.c index 97e231ca3f..0a4344272e 100644 --- a/src/soc/intel/common/block/fast_spi/fast_spi_flash.c +++ b/src/soc/intel/common/block/fast_spi/fast_spi_flash.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include #include #include #include diff --git a/src/soc/intel/common/block/scs/early_mmc.c b/src/soc/intel/common/block/scs/early_mmc.c index 4b15bb48bb..8f47ec7d9e 100644 --- a/src/soc/intel/common/block/scs/early_mmc.c +++ b/src/soc/intel/common/block/scs/early_mmc.c @@ -14,7 +14,6 @@ */ #include -#include #include #include #include diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c index 12239ae13e..29c4774dc1 100644 --- a/src/soc/intel/skylake/romstage/romstage.c +++ b/src/soc/intel/skylake/romstage/romstage.c @@ -15,7 +15,6 @@ */ #include -#include #include #include #include diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c index 96937d651d..04c369beb8 100644 --- a/src/soc/intel/skylake/romstage/romstage_fsp20.c +++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c @@ -14,7 +14,6 @@ */ #include -#include #include #include #include From 00295aa8a6824bc2a0a2f9ff7eb8f649287bd97b Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Sat, 25 May 2019 09:52:07 +0200 Subject: [PATCH 215/331] soc/intel/braswell: Don't use CAR_GLOBAL MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Now that this soc supports NO_CAR_GLOBAL_MIGRATION CAR_GLOBAL and car_get/set_x are not needed anymore. Change-Id: Ia7fa97135a4b376ac0bd8b30093a77614cc2cf55 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/32997 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki --- src/soc/intel/braswell/romstage/romstage.c | 39 ++++++++++------------ 1 file changed, 17 insertions(+), 22 deletions(-) diff --git a/src/soc/intel/braswell/romstage/romstage.c b/src/soc/intel/braswell/romstage/romstage.c index 22b0df2a8b..8dfc291d1e 100644 --- a/src/soc/intel/braswell/romstage/romstage.c +++ b/src/soc/intel/braswell/romstage/romstage.c @@ -17,7 +17,6 @@ #include #include -#include #include #include #include @@ -105,48 +104,44 @@ static void soc_rtc_init(void) cmos_init(rtc_failed); } -static struct chipset_power_state power_state CAR_GLOBAL; +static struct chipset_power_state power_state; static void migrate_power_state(int is_recovery) { struct chipset_power_state *ps_cbmem; - struct chipset_power_state *ps_car; - ps_car = car_get_var_ptr(&power_state); ps_cbmem = cbmem_add(CBMEM_ID_POWER_STATE, sizeof(*ps_cbmem)); if (ps_cbmem == NULL) { printk(BIOS_DEBUG, "Not adding power state to cbmem!\n"); return; } - memcpy(ps_cbmem, ps_car, sizeof(*ps_cbmem)); + memcpy(ps_cbmem, &power_state, sizeof(*ps_cbmem)); } ROMSTAGE_CBMEM_INIT_HOOK(migrate_power_state); struct chipset_power_state *fill_power_state(void) { - struct chipset_power_state *ps = car_get_var_ptr(&power_state); + power_state.pm1_sts = inw(ACPI_BASE_ADDRESS + PM1_STS); + power_state.pm1_en = inw(ACPI_BASE_ADDRESS + PM1_EN); + power_state.pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT); + power_state.gpe0_sts = inl(ACPI_BASE_ADDRESS + GPE0_STS); + power_state.gpe0_en = inl(ACPI_BASE_ADDRESS + GPE0_EN); + power_state.tco_sts = inl(ACPI_BASE_ADDRESS + TCO_STS); + power_state.prsts = read32((void *)(PMC_BASE_ADDRESS + PRSTS)); + power_state.gen_pmcon1 = read32((void *)(PMC_BASE_ADDRESS + GEN_PMCON1)); + power_state.gen_pmcon2 = read32((void *)(PMC_BASE_ADDRESS + GEN_PMCON2)); - ps->pm1_sts = inw(ACPI_BASE_ADDRESS + PM1_STS); - ps->pm1_en = inw(ACPI_BASE_ADDRESS + PM1_EN); - ps->pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT); - ps->gpe0_sts = inl(ACPI_BASE_ADDRESS + GPE0_STS); - ps->gpe0_en = inl(ACPI_BASE_ADDRESS + GPE0_EN); - ps->tco_sts = inl(ACPI_BASE_ADDRESS + TCO_STS); - ps->prsts = read32((void *)(PMC_BASE_ADDRESS + PRSTS)); - ps->gen_pmcon1 = read32((void *)(PMC_BASE_ADDRESS + GEN_PMCON1)); - ps->gen_pmcon2 = read32((void *)(PMC_BASE_ADDRESS + GEN_PMCON2)); - - ps->prev_sleep_state = chipset_prev_sleep_state(ps); + power_state.prev_sleep_state = chipset_prev_sleep_state(&power_state); printk(BIOS_DEBUG, "pm1_sts: %04x pm1_en: %04x pm1_cnt: %08x\n", - ps->pm1_sts, ps->pm1_en, ps->pm1_cnt); + power_state.pm1_sts, power_state.pm1_en, power_state.pm1_cnt); printk(BIOS_DEBUG, "gpe0_sts: %08x gpe0_en: %08x tco_sts: %08x\n", - ps->gpe0_sts, ps->gpe0_en, ps->tco_sts); + power_state.gpe0_sts, power_state.gpe0_en, power_state.tco_sts); printk(BIOS_DEBUG, "prsts: %08x gen_pmcon1: %08x gen_pmcon2: %08x\n", - ps->prsts, ps->gen_pmcon1, ps->gen_pmcon2); - printk(BIOS_DEBUG, "prev_sleep_state %d\n", ps->prev_sleep_state); - return ps; + power_state.prsts, power_state.gen_pmcon1, power_state.gen_pmcon2); + printk(BIOS_DEBUG, "prev_sleep_state %d\n", power_state.prev_sleep_state); + return &power_state; } /* Return 0, 3, or 5 to indicate the previous sleep state. */ From 6e11908128ec83c6237f3285bc7e2cfbc6f6d0f7 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Mon, 27 May 2019 17:21:54 +0200 Subject: [PATCH 216/331] intel/quark/storage_test.h: Drop external variable declaration These are only used where they are initially declared. Change-Id: I0a81a945b771b6c29a170c479b9e72c98e8f3c5a Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/33022 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/soc/intel/quark/include/soc/storage_test.h | 5 ----- 1 file changed, 5 deletions(-) diff --git a/src/soc/intel/quark/include/soc/storage_test.h b/src/soc/intel/quark/include/soc/storage_test.h index 62c9e79236..1c93f1cdf0 100644 --- a/src/soc/intel/quark/include/soc/storage_test.h +++ b/src/soc/intel/quark/include/soc/storage_test.h @@ -48,9 +48,4 @@ struct log_entry { #define LOG_ENTRIES 256 -extern struct log_entry log[LOG_ENTRIES]; -extern uint8_t log_index; -extern int log_full; -extern long log_start_time; - #endif /* __STORAGE_TEST_H__ */ From 84e22e37e89e3384782c40379cc7f2b18faa2099 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Sat, 25 May 2019 09:57:27 +0200 Subject: [PATCH 217/331] soc/intel/quark: Don't use CAR_GLOBAL This soc has NO_CAR_GLOBAL_MIGRATION and does not require CAR_GLOBAL and car_get/set_x. Change-Id: I4e2c1c5766e3bcdd4763b42fb925074f7ccd7002 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/32998 Reviewed-by: Patrick Georgi Tested-by: build bot (Jenkins) --- src/soc/intel/quark/romstage/fsp2_0.c | 15 +++++++-------- src/soc/intel/quark/romstage/romstage.c | 1 - src/soc/intel/quark/storage_test.c | 15 +++++++-------- 3 files changed, 14 insertions(+), 17 deletions(-) diff --git a/src/soc/intel/quark/romstage/fsp2_0.c b/src/soc/intel/quark/romstage/fsp2_0.c index e4abcc034a..5ebbacbd2a 100644 --- a/src/soc/intel/quark/romstage/fsp2_0.c +++ b/src/soc/intel/quark/romstage/fsp2_0.c @@ -13,7 +13,7 @@ * GNU General Public License for more details. */ -#include +#include #include #include #include "../chip.h" @@ -85,20 +85,19 @@ asmlinkage void car_stage_c_entry(void) run_postcar_phase(&pcf); } -static struct chipset_power_state power_state CAR_GLOBAL; +static struct chipset_power_state power_state; struct chipset_power_state *get_power_state(void) { - return (struct chipset_power_state *)car_get_var_ptr(&power_state); + return &power_state; } int fill_power_state(void) { - struct chipset_power_state *ps = get_power_state(); - - ps->prev_sleep_state = 0; - printk(BIOS_SPEW, "prev_sleep_state %d\n", ps->prev_sleep_state); - return ps->prev_sleep_state; + power_state.prev_sleep_state = 0; + printk(BIOS_SPEW, "prev_sleep_state %d\n", + power_state.prev_sleep_state); + return power_state.prev_sleep_state; } void platform_fsp_memory_init_params_cb(FSPM_UPD *fspm_upd, uint32_t version) diff --git a/src/soc/intel/quark/romstage/romstage.c b/src/soc/intel/quark/romstage/romstage.c index f2a280effb..4ac580eb28 100644 --- a/src/soc/intel/quark/romstage/romstage.c +++ b/src/soc/intel/quark/romstage/romstage.c @@ -14,7 +14,6 @@ * GNU General Public License for more details. */ -#include #include #include #include diff --git a/src/soc/intel/quark/storage_test.c b/src/soc/intel/quark/storage_test.c index bdf86b1f12..653466a6d9 100644 --- a/src/soc/intel/quark/storage_test.c +++ b/src/soc/intel/quark/storage_test.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include #include #include #include @@ -29,13 +28,13 @@ #include #if CONFIG(STORAGE_LOG) -struct log_entry log[LOG_ENTRIES] CAR_GLOBAL; -uint8_t log_index CAR_GLOBAL; -int log_full CAR_GLOBAL; -long log_start_time CAR_GLOBAL; +struct log_entry log[LOG_ENTRIES]; +uint8_t log_index; +int log_full; +long log_start_time; #endif -static uint8_t drivers_storage[256] CAR_GLOBAL; +static uint8_t drivers_storage[256]; #define STORAGE_DEBUG BIOS_DEBUG #define LOG_DEBUG (CONFIG(STORAGE_LOG) ? STORAGE_DEBUG : BIOS_NEVER) @@ -175,7 +174,7 @@ void storage_test(uint32_t bar, int full_initialization) /* Get the structure addresses */ media = NULL; if (ENV_ROMSTAGE) - media = car_get_var_ptr(drivers_storage); + media = (struct storage_media *)drivers_storage; else media = cbmem_find(CBMEM_ID_STORAGE_DATA); sdhci_ctrlr = (void *)(((uintptr_t)(media + 1) + 0x7) & ~7); @@ -255,7 +254,7 @@ static void copy_storage_structures(int is_recovery) sdhci_ctrlr = (void *)(((uintptr_t)(media + 1) + 0x7) & ~7); /* Migrate the data into CBMEM */ - memcpy(media, car_get_var_ptr(drivers_storage), size); + memcpy(media, drivers_storage, size); media->ctrlr = &sdhci_ctrlr->sd_mmc_ctrlr; } From 9456d60f6597cea314be09be7cd053a631a31948 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Sat, 25 May 2019 10:22:09 +0200 Subject: [PATCH 218/331] soc/intel/common/gspi: Don't use CAR_GLOBAL MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit All platforms using this code have NO_CAR_GLOBAL_MIGRATION. Change-Id: I5dfbc718fd82f0511b0049383e4e93c6f15ee932 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/32999 Reviewed-by: Kyösti Mälkki Tested-by: build bot (Jenkins) --- src/soc/intel/common/block/gspi/gspi.c | 11 ++++------- 1 file changed, 4 insertions(+), 7 deletions(-) diff --git a/src/soc/intel/common/block/gspi/gspi.c b/src/soc/intel/common/block/gspi/gspi.c index 81eb7eedec..7fd7d0f9ae 100644 --- a/src/soc/intel/common/block/gspi/gspi.c +++ b/src/soc/intel/common/block/gspi/gspi.c @@ -14,7 +14,6 @@ * GNU General Public License for more details. */ -#include #include #include #include @@ -262,15 +261,13 @@ static uint32_t gspi_get_bus_clk_mhz(unsigned int gspi_bus) return cfg[gspi_bus].speed_mhz; } -static uintptr_t gspi_base[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX] CAR_GLOBAL; +static uintptr_t gspi_base[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX]; static uintptr_t gspi_get_bus_base_addr(unsigned int gspi_bus) { - uintptr_t *base = car_get_var_ptr(gspi_base); + if (!gspi_base[gspi_bus]) + gspi_base[gspi_bus] = gspi_calc_base_addr(gspi_bus); - if (!base[gspi_bus]) - base[gspi_bus] = gspi_calc_base_addr(gspi_bus); - - return base[gspi_bus]; + return gspi_base[gspi_bus]; } /* Parameters for GSPI controller operation. */ From 4a402feebf6d8754a8ca8d2207607efd93ef8fe4 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Sat, 25 May 2019 10:24:16 +0200 Subject: [PATCH 219/331] drivers/emulation/qemu_debugcon: Don't use CAR_GLOBAL MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This platform uses NO_CAR_GLOBAL_MIGRATION. Change-Id: Idc9434e5a1a8bc5ed76a9f80c9a7cfba2fd474c0 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/33000 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki --- src/drivers/emulation/qemu/qemu_debugcon.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/src/drivers/emulation/qemu/qemu_debugcon.c b/src/drivers/emulation/qemu/qemu_debugcon.c index 3807524c5c..b040bd8388 100644 --- a/src/drivers/emulation/qemu/qemu_debugcon.c +++ b/src/drivers/emulation/qemu/qemu_debugcon.c @@ -17,14 +17,13 @@ #include #include #include -#include -static int qemu_debugcon_detected CAR_GLOBAL; +static int qemu_debugcon_detected; void qemu_debugcon_init(void) { int detected = (inb(CONFIG_CONSOLE_QEMU_DEBUGCON_PORT) == 0xe9); - car_set_var(qemu_debugcon_detected, detected); + qemu_debugcon_detected = detected; printk(BIOS_INFO, "QEMU debugcon %s [port 0x%x]\n", detected ? "detected" : "not found", CONFIG_CONSOLE_QEMU_DEBUGCON_PORT); @@ -32,6 +31,6 @@ void qemu_debugcon_init(void) void qemu_debugcon_tx_byte(unsigned char data) { - if (car_get_var(qemu_debugcon_detected) != 0) + if (qemu_debugcon_detected != 0) outb(data, CONFIG_CONSOLE_QEMU_DEBUGCON_PORT); } From 3d6ccd0489cfc973ba6a9a47b3e5567cd3a40acb Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Mon, 27 May 2019 17:25:23 +0200 Subject: [PATCH 220/331] soc/intel/common/cse: Declare g_cse statically Change-Id: I91b6ce3b52d987e2fc0f79e550fda2891502bfe8 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/33023 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/soc/intel/common/block/cse/cse.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index 302e6dec05..e4fc6e4ff1 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -69,7 +69,7 @@ #define MEI_HDR_CSE_ADDR (((1 << 8) - 1) << MEI_HDR_CSE_ADDR_START) -struct cse_device { +static struct cse_device { uintptr_t sec_bar; } g_cse CAR_GLOBAL; From a5eed800f3fa84ab100f7b612361c641515ee412 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Sat, 25 May 2019 10:28:11 +0200 Subject: [PATCH 221/331] soc/intel/common/cse: Don't use CAR_GLOBAL MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit All platforms using this code have NO_CAR_GLOBAL_MIGRATION. Change-Id: If952ad8129e1fa6e45858cb77ec99c9fec55c4a6 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/33001 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki --- src/soc/intel/common/block/cse/cse.c | 22 +++++++++------------- 1 file changed, 9 insertions(+), 13 deletions(-) diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index e4fc6e4ff1..7bd46ceba9 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include #include #include #include @@ -71,7 +70,7 @@ static struct cse_device { uintptr_t sec_bar; -} g_cse CAR_GLOBAL; +} g_cse; /* * Initialize the device with provided temporary BAR. If BAR is 0 use a @@ -80,7 +79,6 @@ static struct cse_device { */ void heci_init(uintptr_t tempbar) { - struct cse_device *cse = car_get_var_ptr(&g_cse); #if defined(__SIMPLE_DEVICE__) pci_devfn_t dev = PCH_DEV_CSE; #else @@ -89,7 +87,7 @@ void heci_init(uintptr_t tempbar) u8 pcireg; /* Assume it is already initialized, nothing else to do */ - if (cse->sec_bar) + if (g_cse.sec_bar) return; /* Use default pre-ram bar */ @@ -111,7 +109,7 @@ void heci_init(uintptr_t tempbar) pcireg |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; pci_write_config8(dev, PCI_COMMAND, pcireg); - cse->sec_bar = tempbar; + g_cse.sec_bar = tempbar; } /* Get HECI BAR 0 from PCI configuration space */ @@ -130,20 +128,18 @@ static uint32_t get_cse_bar(void) static uint32_t read_bar(uint32_t offset) { - struct cse_device *cse = car_get_var_ptr(&g_cse); /* Reach PCI config space to get BAR in case CAR global not available */ - if (!cse->sec_bar) - cse->sec_bar = get_cse_bar(); - return read32((void *)(cse->sec_bar + offset)); + if (!g_cse.sec_bar) + g_cse.sec_bar = get_cse_bar(); + return read32((void *)(g_cse.sec_bar + offset)); } static void write_bar(uint32_t offset, uint32_t val) { - struct cse_device *cse = car_get_var_ptr(&g_cse); /* Reach PCI config space to get BAR in case CAR global not available */ - if (!cse->sec_bar) - cse->sec_bar = get_cse_bar(); - return write32((void *)(cse->sec_bar + offset), val); + if (!g_cse.sec_bar) + g_cse.sec_bar = get_cse_bar(); + return write32((void *)(g_cse.sec_bar + offset), val); } static uint32_t read_cse_csr(void) From ea6dd747e8a49cfba8add8e59bc3900bc9b598df Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Sat, 25 May 2019 10:32:31 +0200 Subject: [PATCH 222/331] soc/intel/common/pmc: Don't use CAR_GLOBAL MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit All platforms using this code use NO_CAR_GLOBAL_MIGRATION. Change-Id: I426dee60521045db4711cd253432c65223a64b93 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/33002 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki --- src/soc/intel/common/block/pmc/pmclib.c | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/src/soc/intel/common/block/pmc/pmclib.c b/src/soc/intel/common/block/pmc/pmclib.c index f58d36246e..564aacb55e 100644 --- a/src/soc/intel/common/block/pmc/pmclib.c +++ b/src/soc/intel/common/block/pmc/pmclib.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include #include #include #include @@ -27,7 +26,7 @@ #include #include -static struct chipset_power_state power_state CAR_GLOBAL; +static struct chipset_power_state power_state; struct chipset_power_state *pmc_get_power_state(void) { @@ -38,7 +37,7 @@ struct chipset_power_state *pmc_get_power_state(void) /* cbmem is online but ptr is not populated yet */ if (ptr == NULL && !(ENV_RAMSTAGE || ENV_POSTCAR)) - return car_get_var_ptr(&power_state); + return &power_state; return ptr; } @@ -46,16 +45,14 @@ struct chipset_power_state *pmc_get_power_state(void) static void migrate_power_state(int is_recovery) { struct chipset_power_state *ps_cbmem; - struct chipset_power_state *ps_car; - ps_car = car_get_var_ptr(&power_state); ps_cbmem = cbmem_add(CBMEM_ID_POWER_STATE, sizeof(*ps_cbmem)); if (ps_cbmem == NULL) { printk(BIOS_DEBUG, "Not adding power state to cbmem!\n"); return; } - memcpy(ps_cbmem, ps_car, sizeof(*ps_cbmem)); + memcpy(ps_cbmem, &power_state, sizeof(*ps_cbmem)); } ROMSTAGE_CBMEM_INIT_HOOK(migrate_power_state) From 75c20157ab927aa1e453f710bab96618d556bb20 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Sat, 25 May 2019 10:37:26 +0200 Subject: [PATCH 223/331] drivers/intel/fsp2_0: Dont' use CAR_GLOBAL MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit All platforms using this code have NO_CAR_GLOBAL_MIGRATION. Change-Id: Ic50b16916261abb8c63b8fe571819af5c830ff8d Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/33003 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki --- src/drivers/intel/fsp2_0/hand_off_block.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/src/drivers/intel/fsp2_0/hand_off_block.c b/src/drivers/intel/fsp2_0/hand_off_block.c index c5c78cabf0..95b8020002 100644 --- a/src/drivers/intel/fsp2_0/hand_off_block.c +++ b/src/drivers/intel/fsp2_0/hand_off_block.c @@ -10,7 +10,6 @@ * (at your option) any later version. */ -#include #include #include #include @@ -100,7 +99,7 @@ struct hob_resource *fsp_hob_header_to_resource(const struct hob_header *hob) * Utilities for locating and identifying HOBs */ -static void *fsp_hob_list_ptr CAR_GLOBAL; +static void *fsp_hob_list_ptr; static void save_hob_list(int is_recovery) { @@ -122,14 +121,14 @@ const void *fsp_get_hob_list(void) uint32_t *list_loc; if (ENV_ROMSTAGE) - return (void *)car_get_var(fsp_hob_list_ptr); + return fsp_hob_list_ptr; list_loc = cbmem_find(CBMEM_ID_FSP_RUNTIME); return (list_loc) ? (void *)(uintptr_t)(*list_loc) : NULL; } void *fsp_get_hob_list_ptr(void) { - return car_get_var_ptr(&fsp_hob_list_ptr); + return &fsp_hob_list_ptr; } static const From 3d90d3bfce7b3e2a885bb4722ecb3a5c127e2882 Mon Sep 17 00:00:00 2001 From: Evgeny Zinoviev Date: Sat, 25 May 2019 17:38:53 +0300 Subject: [PATCH 224/331] util/autoport: Add info about rank 1 mirroring inteltool can't detect whether address mapping is normal or mirrored, which in turn may be cause RAM initialization to fail when using spd.bin generated by inteltool. Mention this in readme as it may help someone. Change-Id: I8d24e4d9332bdcf484987581dd6941e2bf9c4f87 Signed-off-by: Evgeny Zinoviev Reviewed-on: https://review.coreboot.org/c/coreboot/+/32683 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- util/autoport/readme.md | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/util/autoport/readme.md b/util/autoport/readme.md index cfa8c36a38..fa349b906f 100644 --- a/util/autoport/readme.md +++ b/util/autoport/readme.md @@ -268,6 +268,12 @@ If several slots are soldered there are two ways to handle them: not forget to copy the data on all the array elements that need it. * If they use different data, use several files. +If memory initialization is not working, in particular write training (timB) +on DIMM's second rank fails, try enbling rank 1 mirroring, which can't be +detected by inteltool. It is described by SPD field "Address Mapping from Edge +Connector to DRAM", byte `63` (`0x3f`). Bit 0 describes Rank 1 Mapping, +0 = standard, 1 = mirrored; set it to 1. Bits 1-7 are reserved. + ### `board_info.txt` `board_info.txt` is a text file used in the board status page to list all From 64fb5aa9c3e50a49d2ecc153ff8c597e203475bc Mon Sep 17 00:00:00 2001 From: John Zhao Date: Thu, 23 May 2019 16:22:21 -0700 Subject: [PATCH 225/331] soc/intel/common: Set GSPI clock value to prevent division by zero Clang Static Analyzer version 8.0.0 detects the division by zero if gspi_clk_mhz is initialized to 0. gspi_clk_mhz is referred to speed_mhz in devicetree. Set gspi_clk_mhz to 1 if it is detected as 0 in order to prevent the division by zero in DIV_ROUND_UP operation. Then the value of (ref_clk_mhz - 1) will be fed into GSPI's Serial Clock Rate value. TEST=Built and boot up to kernel. Change-Id: I6a09474bff114c57d7a9c4c232bb636ff287e4d5 Signed-off-by: John Zhao Reviewed-on: https://review.coreboot.org/c/coreboot/+/32974 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie --- src/soc/intel/common/block/gspi/gspi.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/src/soc/intel/common/block/gspi/gspi.c b/src/soc/intel/common/block/gspi/gspi.c index 7fd7d0f9ae..17532bf6db 100644 --- a/src/soc/intel/common/block/gspi/gspi.c +++ b/src/soc/intel/common/block/gspi/gspi.c @@ -434,9 +434,11 @@ static uint32_t gspi_get_clk_div(unsigned int gspi_bus) { const uint32_t ref_clk_mhz = CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ; - const uint32_t gspi_clk_mhz = gspi_get_bus_clk_mhz(gspi_bus); + uint32_t gspi_clk_mhz = gspi_get_bus_clk_mhz(gspi_bus); + + if (!gspi_clk_mhz) + gspi_clk_mhz = 1; - assert(gspi_clk_mhz != 0); assert(ref_clk_mhz != 0); return (DIV_ROUND_UP(ref_clk_mhz, gspi_clk_mhz) - 1) & SSCR0_SCR_MASK; } From 2bb432ece634af05aade44ea55755ae3e6637acf Mon Sep 17 00:00:00 2001 From: John Zhao Date: Tue, 21 May 2019 19:32:51 -0700 Subject: [PATCH 226/331] soc/intel/common: Check bios_size and window_size after MIN operation Clang Static Analyzer version 8.0.0 detects that log2_ceil(bios_size) and log2_ceil(window_size) are garbage or undefined if the value of bios_size and window_size is zero. Check bios_size and window_size after MIN operation to prevent error. TEST=Built and boot up to kernel. Change-Id: Ifc3f3da52d129ef5d6063a46b045603a236be759 Signed-off-by: John Zhao Reviewed-on: https://review.coreboot.org/c/coreboot/+/32924 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie --- src/soc/intel/common/block/fast_spi/fast_spi.c | 5 ++--- src/soc/intel/common/block/lpc/lpc_lib.c | 3 +++ 2 files changed, 5 insertions(+), 3 deletions(-) diff --git a/src/soc/intel/common/block/fast_spi/fast_spi.c b/src/soc/intel/common/block/fast_spi/fast_spi.c index 455b13ccb7..58e7db75a1 100644 --- a/src/soc/intel/common/block/fast_spi/fast_spi.c +++ b/src/soc/intel/common/block/fast_spi/fast_spi.c @@ -236,14 +236,13 @@ void fast_spi_cache_bios_region(void) /* Only the IFD BIOS region is memory mapped (at top of 4G) */ fast_spi_get_bios_region(&bios_size); - if (!bios_size) - return; - /* LOCAL APIC default address is 0xFEE0000, bios_size over 16MB will * cause memory type conflict when setting memory type to write * protection, so limit the cached bios region to be no more than 16MB. * */ bios_size = MIN(bios_size, 16 * MiB); + if (!bios_size) + return; /* Round to power of two */ alignment = 1UL << (log2_ceil(bios_size)); diff --git a/src/soc/intel/common/block/lpc/lpc_lib.c b/src/soc/intel/common/block/lpc/lpc_lib.c index b383637736..c67c43532c 100644 --- a/src/soc/intel/common/block/lpc/lpc_lib.c +++ b/src/soc/intel/common/block/lpc/lpc_lib.c @@ -80,6 +80,9 @@ void lpc_open_pmio_window(uint16_t base, uint16_t size) /* Each IO range register can only open a 256-byte window. */ window_size = MIN(size, LPC_LGIR_MAX_WINDOW_SIZE); + if (!window_size) + return; + /* Window size must be a power of two for the AMASK to work. */ alignment = 1UL << (log2_ceil(window_size)); window_size = ALIGN_UP(window_size, alignment); From 6336ee6df936e7e67a7e3cdc8185214ae9cb668a Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Wed, 8 May 2019 18:58:55 +0200 Subject: [PATCH 227/331] sb/intel/*: Delete early_spi The file and all of it's functions are unused. Drop the dead code. Change-Id: Iaddd7a688d431d40f38293939e084d19b286aed4 Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/c/coreboot/+/32688 Tested-by: build bot (Jenkins) Reviewed-by: HAOUAS Elyes Reviewed-by: David Guckian Reviewed-by: Arthur Heymans --- src/soc/intel/baytrail/include/soc/romstage.h | 1 - src/soc/intel/baytrail/romstage/Makefile.inc | 1 - src/soc/intel/baytrail/romstage/early_spi.c | 60 -------- src/soc/intel/braswell/include/soc/romstage.h | 1 - src/soc/intel/braswell/romstage/Makefile.inc | 1 - src/soc/intel/braswell/romstage/early_spi.c | 63 -------- .../intel/broadwell/include/soc/romstage.h | 3 - src/soc/intel/broadwell/romstage/Makefile.inc | 1 - src/soc/intel/broadwell/romstage/spi.c | 143 ------------------ src/southbridge/intel/bd82x6x/Makefile.inc | 1 - src/southbridge/intel/bd82x6x/early_spi.c | 108 ------------- src/southbridge/intel/bd82x6x/pch.h | 1 - .../intel/fsp_rangeley/Makefile.inc | 2 +- .../intel/fsp_rangeley/early_spi.c | 108 ------------- src/southbridge/intel/fsp_rangeley/soc.h | 1 - src/southbridge/intel/ibexpeak/Makefile.inc | 2 - src/southbridge/intel/ibexpeak/pch.h | 1 - src/southbridge/intel/lynxpoint/Makefile.inc | 2 +- src/southbridge/intel/lynxpoint/early_spi.c | 108 ------------- src/southbridge/intel/lynxpoint/pch.h | 1 - 20 files changed, 2 insertions(+), 607 deletions(-) delete mode 100644 src/soc/intel/baytrail/romstage/early_spi.c delete mode 100644 src/soc/intel/braswell/romstage/early_spi.c delete mode 100644 src/soc/intel/broadwell/romstage/spi.c delete mode 100644 src/southbridge/intel/bd82x6x/early_spi.c delete mode 100644 src/southbridge/intel/fsp_rangeley/early_spi.c delete mode 100644 src/southbridge/intel/lynxpoint/early_spi.c diff --git a/src/soc/intel/baytrail/include/soc/romstage.h b/src/soc/intel/baytrail/include/soc/romstage.h index 3e8b6a27ef..fffce7e317 100644 --- a/src/soc/intel/baytrail/include/soc/romstage.h +++ b/src/soc/intel/baytrail/include/soc/romstage.h @@ -37,7 +37,6 @@ void gfx_init(void); void tco_disable(void); void punit_init(void); void set_max_freq(void); -int early_spi_read_wpsr(u8 *sr); #if CONFIG(ENABLE_BUILTIN_COM1) void byt_config_com1_and_enable(void); diff --git a/src/soc/intel/baytrail/romstage/Makefile.inc b/src/soc/intel/baytrail/romstage/Makefile.inc index f1a3463d20..d43a6fb6e3 100644 --- a/src/soc/intel/baytrail/romstage/Makefile.inc +++ b/src/soc/intel/baytrail/romstage/Makefile.inc @@ -5,4 +5,3 @@ romstage-y += raminit.c romstage-$(CONFIG_ENABLE_BUILTIN_COM1) += uart.c romstage-y += gfx.c romstage-y += pmc.c -romstage-y += early_spi.c diff --git a/src/soc/intel/baytrail/romstage/early_spi.c b/src/soc/intel/baytrail/romstage/early_spi.c deleted file mode 100644 index 72e9b2cdae..0000000000 --- a/src/soc/intel/baytrail/romstage/early_spi.c +++ /dev/null @@ -1,60 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. All rights reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include - -#include -#include -#include - -#define SPI_CYCLE_DELAY 10 /* 10us */ -#define SPI_CYCLE_TIMEOUT 400000 / SPI_CYCLE_DELAY /* 400ms */ - -#define SPI8(x) *((volatile u8 *)(SPI_BASE_ADDRESS + x)) -#define SPI16(x) *((volatile u16 *)(SPI_BASE_ADDRESS + x)) -#define SPI32(x) *((volatile u32 *)(SPI_BASE_ADDRESS + x)) - -/* Minimal set of commands to read wpsr from SPI. Don't use this code outside - * romstage -- it trashes the opmenu table. - * Returns 0 on success, < 0 on failure. */ -int early_spi_read_wpsr(u8 *sr) -{ - int timeout = SPI_CYCLE_TIMEOUT; - - /* No address associated with rdsr */ - SPI8(OPTYPE) = 0x0; - /* Setup opcode[0] = read wpsr */ - SPI8(OPMENU0) = 0x5; - - /* Start transaction */ - SPI16(SSFC) = DATA_CYCLE | SPI_CYCLE_GO; - - /* Wait for error / complete status */ - while (timeout--) { - u16 status = SPI16(SSFS); - if (status & FLASH_CYCLE_ERROR) { - printk(BIOS_ERR, "SPI rdsr failed\n"); - return -1; - } else if (status & CYCLE_DONE_STATUS) - break; - - udelay(SPI_CYCLE_DELAY); - } - - *sr = SPI32(FDATA0) & 0xff; - return 0; -} diff --git a/src/soc/intel/braswell/include/soc/romstage.h b/src/soc/intel/braswell/include/soc/romstage.h index 633233e6c6..4ecbd2c1f9 100644 --- a/src/soc/intel/braswell/include/soc/romstage.h +++ b/src/soc/intel/braswell/include/soc/romstage.h @@ -25,7 +25,6 @@ void gfx_init(void); void tco_disable(void); void punit_init(void); -int early_spi_read_wpsr(u8 *sr); void set_max_freq(void); /* romstage_common.c functions */ diff --git a/src/soc/intel/braswell/romstage/Makefile.inc b/src/soc/intel/braswell/romstage/Makefile.inc index c3ed415dcc..15de822041 100644 --- a/src/soc/intel/braswell/romstage/Makefile.inc +++ b/src/soc/intel/braswell/romstage/Makefile.inc @@ -1,3 +1,2 @@ -romstage-y += early_spi.c romstage-y += pmc.c romstage-y += romstage.c diff --git a/src/soc/intel/braswell/romstage/early_spi.c b/src/soc/intel/braswell/romstage/early_spi.c deleted file mode 100644 index 0ca5ef521f..0000000000 --- a/src/soc/intel/braswell/romstage/early_spi.c +++ /dev/null @@ -1,63 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. All rights reserved. - * Copyright (C) 2015 Intel Corp. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include - -#include -#include -#include - -#define SPI_CYCLE_DELAY 10 /* 10us */ -#define SPI_CYCLE_TIMEOUT (400000 / SPI_CYCLE_DELAY) /* 400ms */ - -#define SPI8(x) (*((volatile u8 *)(SPI_BASE_ADDRESS + (x)))) -#define SPI16(x) (*((volatile u16 *)(SPI_BASE_ADDRESS + (x)))) -#define SPI32(x) (*((volatile u32 *)(SPI_BASE_ADDRESS + (x)))) - -/* - * Minimal set of commands to read wpsr from SPI. Don't use this code outside - * romstage -- it trashes the opmenu table. - * Returns 0 on success, < 0 on failure. - */ -int early_spi_read_wpsr(u8 *sr) -{ - int timeout = SPI_CYCLE_TIMEOUT; - - /* No address associated with rdsr */ - SPI8(OPTYPE) = 0x0; - /* Setup opcode[0] = read wpsr */ - SPI8(OPMENU0) = 0x5; - - /* Start transaction */ - SPI16(SSFC) = DATA_CYCLE | SPI_CYCLE_GO; - - /* Wait for error / complete status */ - while (timeout--) { - u16 status = SPI16(SSFS); - if (status & FLASH_CYCLE_ERROR) { - printk(BIOS_ERR, "SPI rdsr failed\n"); - return -1; - } else if (status & CYCLE_DONE_STATUS) - break; - - udelay(SPI_CYCLE_DELAY); - } - - *sr = SPI32(FDATA0) & 0xff; - return 0; -} diff --git a/src/soc/intel/broadwell/include/soc/romstage.h b/src/soc/intel/broadwell/include/soc/romstage.h index ac8265fb4c..cd37cf6316 100644 --- a/src/soc/intel/broadwell/include/soc/romstage.h +++ b/src/soc/intel/broadwell/include/soc/romstage.h @@ -46,7 +46,4 @@ void intel_early_me_status(void); void enable_smbus(void); int smbus_read_byte(unsigned int device, unsigned int address); -int early_spi_read(u32 offset, u32 size, u8 *buffer); -int early_spi_read_wpsr(u8 *sr); - #endif diff --git a/src/soc/intel/broadwell/romstage/Makefile.inc b/src/soc/intel/broadwell/romstage/Makefile.inc index ea17d67061..a53cd95cd5 100644 --- a/src/soc/intel/broadwell/romstage/Makefile.inc +++ b/src/soc/intel/broadwell/romstage/Makefile.inc @@ -6,6 +6,5 @@ romstage-y += raminit.c romstage-y += report_platform.c romstage-y += romstage.c romstage-y += smbus.c -romstage-y += spi.c romstage-y += systemagent.c romstage-$(CONFIG_DRIVERS_UART_8250MEM) += uart.c diff --git a/src/soc/intel/broadwell/romstage/spi.c b/src/soc/intel/broadwell/romstage/spi.c deleted file mode 100644 index cb0509d104..0000000000 --- a/src/soc/intel/broadwell/romstage/spi.c +++ /dev/null @@ -1,143 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include - -#define SPI_DELAY 10 /* 10us */ -#define SPI_RETRY 200000 /* 2s */ - -static int early_spi_read_block(u32 offset, u8 size, u8 *buffer) -{ - u32 *ptr32 = (u32 *)buffer; - u32 i; - - /* Clear status bits */ - SPIBAR16(SPIBAR_HSFS) |= SPIBAR_HSFS_AEL | SPIBAR_HSFS_FCERR | - SPIBAR_HSFS_FDONE; - - if (SPIBAR16(SPIBAR_HSFS) & SPIBAR_HSFS_SCIP) { - printk(BIOS_ERR, "SPI ERROR: transaction in progress\n"); - return -1; - } - - /* Set flash address */ - SPIBAR32(SPIBAR_FADDR) = offset; - - /* Setup read transaction */ - SPIBAR16(SPIBAR_HSFC) = SPIBAR_HSFC_BYTE_COUNT(size) | - SPIBAR_HSFC_CYCLE_READ; - - /* Start transaction */ - SPIBAR16(SPIBAR_HSFC) |= SPIBAR_HSFC_GO; - - /* Wait for completion */ - for (i = 0; i < SPI_RETRY; i++) { - if (SPIBAR16(SPIBAR_HSFS) & SPIBAR_HSFS_SCIP) { - /* Cycle in progress, wait 1ms */ - udelay(SPI_DELAY); - continue; - } - - if (SPIBAR16(SPIBAR_HSFS) & SPIBAR_HSFS_AEL) { - printk(BIOS_ERR, "SPI ERROR: Access Error\n"); - return -1; - - } - - if (SPIBAR16(SPIBAR_HSFS) & SPIBAR_HSFS_FCERR) { - printk(BIOS_ERR, "SPI ERROR: Flash Cycle Error\n"); - return -1; - } - break; - } - - if (i >= SPI_RETRY) { - printk(BIOS_ERR, "SPI ERROR: Timeout\n"); - return -1; - } - - /* Read the data */ - for (i = 0; i < size; i += sizeof(u32)) { - if (size-i >= 4) { - /* reading >= dword */ - *ptr32++ = SPIBAR32(SPIBAR_FDATA(i/sizeof(u32))); - } else { - /* reading < dword */ - u8 j, *ptr8 = (u8 *)ptr32; - u32 temp = SPIBAR32(SPIBAR_FDATA(i/sizeof(u32))); - for (j = 0; j < (size-i); j++) { - *ptr8++ = temp & 0xff; - temp >>= 8; - } - } - } - - return size; -} - -int early_spi_read(u32 offset, u32 size, u8 *buffer) -{ - u32 current = 0; - - while (size > 0) { - u8 count = (size < 64) ? size : 64; - if (early_spi_read_block(offset + current, count, - buffer + current) < 0) - return -1; - size -= count; - current += count; - } - - return 0; -} - -/* - * Minimal set of commands to read WPSR from SPI. - * Don't use this code outside romstage -- it trashes the opmenu table. - * Returns 0 on success, < 0 on failure. - */ -int early_spi_read_wpsr(u8 *sr) -{ - int retry; - - /* No address associated with rdsr */ - SPIBAR8(SPIBAR_OPTYPE) = 0x0; - /* Setup opcode[0] = read wpsr */ - SPIBAR8(SPIBAR_OPMENU_LOWER) = 0x5; - - /* Start transaction */ - SPIBAR16(SPIBAR_SSFC) = SPIBAR_SSFC_DATA | SPIBAR_SSFC_GO; - - /* Wait for error / complete status */ - for (retry = SPI_RETRY; retry; retry--) { - u16 status = SPIBAR16(SPIBAR_SSFS); - if (status & SPIBAR_SSFS_ERROR) { - printk(BIOS_ERR, "SPI rdsr failed\n"); - return -1; - } else if (status & SPIBAR_SSFS_DONE) { - break; - } - - udelay(SPI_DELAY); - } - - *sr = SPIBAR32(SPIBAR_FDATA(0)) & 0xff; - return 0; -} diff --git a/src/southbridge/intel/bd82x6x/Makefile.inc b/src/southbridge/intel/bd82x6x/Makefile.inc index 023f5d32c2..b6023b00b3 100644 --- a/src/southbridge/intel/bd82x6x/Makefile.inc +++ b/src/southbridge/intel/bd82x6x/Makefile.inc @@ -37,7 +37,6 @@ ramstage-$(CONFIG_ELOG) += elog.c smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c me.c me_8.x.c pch.c romstage-y += early_smbus.c me_status.c -romstage-y += early_spi.c romstage-y += early_rcba.c romstage-y += early_pch.c diff --git a/src/southbridge/intel/bd82x6x/early_spi.c b/src/southbridge/intel/bd82x6x/early_spi.c deleted file mode 100644 index 3034930a06..0000000000 --- a/src/southbridge/intel/bd82x6x/early_spi.c +++ /dev/null @@ -1,108 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Google Inc. All rights reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include "pch.h" - -#define SPI_DELAY 10 /* 10us */ -#define SPI_RETRY 200000 /* 2s */ - -static int early_spi_read_block(u32 offset, u8 size, u8 *buffer) -{ - u32 *ptr32 = (u32*)buffer; - u32 i; - - /* Clear status bits */ - RCBA16(SPIBAR_HSFS) |= SPIBAR_HSFS_AEL | SPIBAR_HSFS_FCERR | - SPIBAR_HSFS_FDONE; - - if (RCBA16(SPIBAR_HSFS) & SPIBAR_HSFS_SCIP) { - printk(BIOS_ERR, "SPI ERROR: transaction in progress\n"); - return -1; - } - - /* Set flash address */ - RCBA32(SPIBAR_FADDR) = offset; - - /* Setup read transaction */ - RCBA16(SPIBAR_HSFC) = SPIBAR_HSFC_BYTE_COUNT(size) | - SPIBAR_HSFC_CYCLE_READ; - - /* Start transactinon */ - RCBA16(SPIBAR_HSFC) |= SPIBAR_HSFC_GO; - - /* Wait for completion */ - for (i = 0; i < SPI_RETRY; i++) { - if (RCBA16(SPIBAR_HSFS) & SPIBAR_HSFS_SCIP) { - /* Cycle in progress, wait 1ms */ - udelay(SPI_DELAY); - continue; - } - - if (RCBA16(SPIBAR_HSFS) & SPIBAR_HSFS_AEL) { - printk(BIOS_ERR, "SPI ERROR: Access Error\n"); - return -1; - - } - - if (RCBA16(SPIBAR_HSFS) & SPIBAR_HSFS_FCERR) { - printk(BIOS_ERR, "SPI ERROR: Flash Cycle Error\n"); - return -1; - } - break; - } - - if (i >= SPI_RETRY) { - printk(BIOS_ERR, "SPI ERROR: Timeout\n"); - return -1; - } - - /* Read the data */ - for (i = 0; i < size; i+=sizeof(u32)) { - if (size-i >= 4) { - /* reading >= dword */ - *ptr32++ = RCBA32(SPIBAR_FDATA(i/sizeof(u32))); - } else { - /* reading < dword */ - u8 j, *ptr8 = (u8*)ptr32; - u32 temp = RCBA32(SPIBAR_FDATA(i/sizeof(u32))); - for (j = 0; j < (size-i); j++) { - *ptr8++ = temp & 0xff; - temp >>= 8; - } - } - } - - return size; -} - -int early_spi_read(u32 offset, u32 size, u8 *buffer) -{ - u32 current = 0; - - while (size > 0) { - u8 count = (size < 64) ? size : 64; - if (early_spi_read_block(offset + current, count, - buffer + current) < 0) - return -1; - size -= count; - current += count; - } - - return 0; -} diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index faa6822bf2..4369b5c162 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -70,7 +70,6 @@ void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue); void enable_smbus(void); void enable_usb_bar(void); int smbus_read_byte(unsigned device, unsigned address); -int early_spi_read(u32 offset, u32 size, u8 *buffer); void early_thermal_init(void); void southbridge_configure_default_intmap(void); void southbridge_rcba_config(void); diff --git a/src/southbridge/intel/fsp_rangeley/Makefile.inc b/src/southbridge/intel/fsp_rangeley/Makefile.inc index 7fc86012de..67a51af15a 100644 --- a/src/southbridge/intel/fsp_rangeley/Makefile.inc +++ b/src/southbridge/intel/fsp_rangeley/Makefile.inc @@ -23,7 +23,7 @@ ramstage-y += spi.c ramstage-y += smbus.c ramstage-y += acpi.c -romstage-y += early_usb.c early_smbus.c gpio.c early_spi.c early_init.c +romstage-y += early_usb.c early_smbus.c gpio.c early_init.c romstage-y += romstage.c bootblock-$(CONFIG_USBDEBUG) += usb_debug.c diff --git a/src/southbridge/intel/fsp_rangeley/early_spi.c b/src/southbridge/intel/fsp_rangeley/early_spi.c deleted file mode 100644 index 7b20cdb9a7..0000000000 --- a/src/southbridge/intel/fsp_rangeley/early_spi.c +++ /dev/null @@ -1,108 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Google Inc. All rights reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include "soc.h" - -#define SPI_DELAY 10 /* 10us */ -#define SPI_RETRY 200000 /* 2s */ - -static int early_spi_read_block(u32 offset, u8 size, u8 *buffer) -{ - u32 *ptr32 = (u32*)buffer; - u32 i; - - /* Clear status bits */ - RCBA16(SPIBAR_HSFS) |= SPIBAR_HSFS_AEL | SPIBAR_HSFS_FCERR | - SPIBAR_HSFS_FDONE; - - if (RCBA16(SPIBAR_HSFS) & SPIBAR_HSFS_SCIP) { - printk(BIOS_ERR, "SPI ERROR: transaction in progress\n"); - return -1; - } - - /* Set flash address */ - RCBA32(SPIBAR_FADDR) = offset; - - /* Setup read transaction */ - RCBA16(SPIBAR_HSFC) = SPIBAR_HSFC_BYTE_COUNT(size) | - SPIBAR_HSFC_CYCLE_READ; - - /* Start transaction */ - RCBA16(SPIBAR_HSFC) |= SPIBAR_HSFC_GO; - - /* Wait for completion */ - for (i = 0; i < SPI_RETRY; i++) { - if (RCBA16(SPIBAR_HSFS) & SPIBAR_HSFS_SCIP) { - /* Cycle in progress, wait 1ms */ - udelay(SPI_DELAY); - continue; - } - - if (RCBA16(SPIBAR_HSFS) & SPIBAR_HSFS_AEL) { - printk(BIOS_ERR, "SPI ERROR: Access Error\n"); - return -1; - - } - - if (RCBA16(SPIBAR_HSFS) & SPIBAR_HSFS_FCERR) { - printk(BIOS_ERR, "SPI ERROR: Flash Cycle Error\n"); - return -1; - } - break; - } - - if (i >= SPI_RETRY) { - printk(BIOS_ERR, "SPI ERROR: Timeout\n"); - return -1; - } - - /* Read the data */ - for (i = 0; i < size; i+=sizeof(u32)) { - if (size-i >= 4) { - /* reading >= dword */ - *ptr32++ = RCBA32(SPIBAR_FDATA(i/sizeof(u32))); - } else { - /* reading < dword */ - u8 j, *ptr8 = (u8*)ptr32; - u32 temp = RCBA32(SPIBAR_FDATA(i/sizeof(u32))); - for (j = 0; j < (size-i); j++) { - *ptr8++ = temp & 0xff; - temp >>= 8; - } - } - } - - return size; -} - -int early_spi_read(u32 offset, u32 size, u8 *buffer) -{ - u32 current = 0; - - while (size > 0) { - u8 count = (size < 64) ? size : 64; - if (early_spi_read_block(offset + current, count, - buffer + current) < 0) - return -1; - size -= count; - current += count; - } - - return 0; -} diff --git a/src/southbridge/intel/fsp_rangeley/soc.h b/src/southbridge/intel/fsp_rangeley/soc.h index 4c5e835c7f..aceb425ab7 100644 --- a/src/southbridge/intel/fsp_rangeley/soc.h +++ b/src/southbridge/intel/fsp_rangeley/soc.h @@ -68,7 +68,6 @@ void soc_log_state(void); void enable_smbus(void); void enable_usb_bar(void); int smbus_read_byte(unsigned device, unsigned address); -int early_spi_read(u32 offset, u32 size, u8 *buffer); void rangeley_sb_early_initialization(void); #endif #endif diff --git a/src/southbridge/intel/ibexpeak/Makefile.inc b/src/southbridge/intel/ibexpeak/Makefile.inc index 24eac22b9f..fccb3a8656 100644 --- a/src/southbridge/intel/ibexpeak/Makefile.inc +++ b/src/southbridge/intel/ibexpeak/Makefile.inc @@ -39,7 +39,5 @@ smm-y += smihandler.c me.c ../bd82x6x/me_8.x.c ../bd82x6x/pch.c romstage-y += ../bd82x6x/early_usb.c early_smbus.c ../bd82x6x/early_me.c ../bd82x6x/me_status.c ../common/gpio.c early_thermal.c romstage-y += ../bd82x6x/early_rcba.c -romstage-$(CONFIG_SOUTHBRIDGE_INTEL_BD82X6X) += ../bd82x6x/early_spi.c -romstage-$(CONFIG_SOUTHBRIDGE_INTEL_C216) += ../bd82x6x/early_spi.c endif diff --git a/src/southbridge/intel/ibexpeak/pch.h b/src/southbridge/intel/ibexpeak/pch.h index 90e7102ed2..04cc21d475 100644 --- a/src/southbridge/intel/ibexpeak/pch.h +++ b/src/southbridge/intel/ibexpeak/pch.h @@ -71,7 +71,6 @@ int smbus_read_byte(unsigned device, unsigned address); int smbus_write_byte(unsigned device, unsigned address, u8 data); int smbus_block_read(unsigned device, unsigned cmd, u8 bytes, u8 *buf); int smbus_block_write(unsigned device, unsigned cmd, u8 bytes, const u8 *buf); -int early_spi_read(u32 offset, u32 size, u8 *buffer); void early_thermal_init(void); void southbridge_configure_default_intmap(void); #endif diff --git a/src/southbridge/intel/lynxpoint/Makefile.inc b/src/southbridge/intel/lynxpoint/Makefile.inc index f0bfa5bcc3..3e3ef35e2d 100644 --- a/src/southbridge/intel/lynxpoint/Makefile.inc +++ b/src/southbridge/intel/lynxpoint/Makefile.inc @@ -47,7 +47,7 @@ smm-$(CONFIG_HAVE_SMI_HANDLER) += pmutil.c usb_ehci.c usb_xhci.c bootblock-y += early_pch.c romstage-y += early_usb.c early_smbus.c early_me.c me_status.c early_pch.c -romstage-y += early_spi.c rcba.c pmutil.c +romstage-y += rcba.c pmutil.c ifeq ($(CONFIG_INTEL_LYNXPOINT_LP),y) romstage-y += lp_gpio.c diff --git a/src/southbridge/intel/lynxpoint/early_spi.c b/src/southbridge/intel/lynxpoint/early_spi.c deleted file mode 100644 index 3034930a06..0000000000 --- a/src/southbridge/intel/lynxpoint/early_spi.c +++ /dev/null @@ -1,108 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Google Inc. All rights reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include "pch.h" - -#define SPI_DELAY 10 /* 10us */ -#define SPI_RETRY 200000 /* 2s */ - -static int early_spi_read_block(u32 offset, u8 size, u8 *buffer) -{ - u32 *ptr32 = (u32*)buffer; - u32 i; - - /* Clear status bits */ - RCBA16(SPIBAR_HSFS) |= SPIBAR_HSFS_AEL | SPIBAR_HSFS_FCERR | - SPIBAR_HSFS_FDONE; - - if (RCBA16(SPIBAR_HSFS) & SPIBAR_HSFS_SCIP) { - printk(BIOS_ERR, "SPI ERROR: transaction in progress\n"); - return -1; - } - - /* Set flash address */ - RCBA32(SPIBAR_FADDR) = offset; - - /* Setup read transaction */ - RCBA16(SPIBAR_HSFC) = SPIBAR_HSFC_BYTE_COUNT(size) | - SPIBAR_HSFC_CYCLE_READ; - - /* Start transactinon */ - RCBA16(SPIBAR_HSFC) |= SPIBAR_HSFC_GO; - - /* Wait for completion */ - for (i = 0; i < SPI_RETRY; i++) { - if (RCBA16(SPIBAR_HSFS) & SPIBAR_HSFS_SCIP) { - /* Cycle in progress, wait 1ms */ - udelay(SPI_DELAY); - continue; - } - - if (RCBA16(SPIBAR_HSFS) & SPIBAR_HSFS_AEL) { - printk(BIOS_ERR, "SPI ERROR: Access Error\n"); - return -1; - - } - - if (RCBA16(SPIBAR_HSFS) & SPIBAR_HSFS_FCERR) { - printk(BIOS_ERR, "SPI ERROR: Flash Cycle Error\n"); - return -1; - } - break; - } - - if (i >= SPI_RETRY) { - printk(BIOS_ERR, "SPI ERROR: Timeout\n"); - return -1; - } - - /* Read the data */ - for (i = 0; i < size; i+=sizeof(u32)) { - if (size-i >= 4) { - /* reading >= dword */ - *ptr32++ = RCBA32(SPIBAR_FDATA(i/sizeof(u32))); - } else { - /* reading < dword */ - u8 j, *ptr8 = (u8*)ptr32; - u32 temp = RCBA32(SPIBAR_FDATA(i/sizeof(u32))); - for (j = 0; j < (size-i); j++) { - *ptr8++ = temp & 0xff; - temp >>= 8; - } - } - } - - return size; -} - -int early_spi_read(u32 offset, u32 size, u8 *buffer) -{ - u32 current = 0; - - while (size > 0) { - u8 count = (size < 64) ? size : 64; - if (early_spi_read_block(offset + current, count, - buffer + current) < 0) - return -1; - size -= count; - current += count; - } - - return 0; -} diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index 97d0aa33b3..93c2bc5703 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -195,7 +195,6 @@ void southbridge_smm_enable_smi(void); void enable_smbus(void); void enable_usb_bar(void); int smbus_read_byte(unsigned device, unsigned address); -int early_spi_read(u32 offset, u32 size, u8 *buffer); int early_pch_init(const void *gpio_map, const struct rcba_config_instruction *rcba_config); void pch_enable_lpc(void); From 57448845ff549f9aa75c3d49c9b292accb5dbc99 Mon Sep 17 00:00:00 2001 From: John Zhao Date: Mon, 20 May 2019 16:10:16 -0700 Subject: [PATCH 228/331] soc/intel/apollolake: Fix value stored to gnvs is never read Clang Static Analyzer found version 8.0.0 gnvs is allocated, but it is never used. Change sizeof(*gnvs) to sizeof(global_nvs_t) while adding ACPI GNVS to CBMEM. TEST=Built and boot up to kernel. Change-Id: Ie9421af4a556d1d88183aa938ee2a124a10ab727 Signed-off-by: John Zhao Reviewed-on: https://review.coreboot.org/c/coreboot/+/32903 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- src/soc/intel/apollolake/chip.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index f6880a7f3f..e9030dc2df 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -389,8 +389,6 @@ static void set_sci_irq(void) static void soc_init(void *data) { - struct global_nvs_t *gnvs; - /* Snapshot the current GPIO IRQ polarities. FSP is setting a * default policy that doesn't honor boards' requirements. */ itss_snapshot_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END); @@ -418,7 +416,7 @@ static void soc_init(void *data) p2sb_unhide(); /* Allocate ACPI NVS in CBMEM */ - gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(*gnvs)); + cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(struct global_nvs_t)); /* Set RAPL MSR for Package power limits*/ set_power_limits(); From 342d3180d7134be92db03190205849d514ac33a8 Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Fri, 24 May 2019 13:03:43 +0200 Subject: [PATCH 229/331] Makefile.inc: Extend version string for timeless builds MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit With the version string "TIMELESS", binaries are slightly smaller than for a regular build. This may lead to false positive build tests if the space is limited (e.g. bootblock). So let's make the string a little longer. Change-Id: I3bbf6f71d5bcd74728a3fe39734312690901d0ec Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/c/coreboot/+/32986 Reviewed-by: Patrick Georgi Reviewed-by: Kyösti Mälkki Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- Makefile.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile.inc b/Makefile.inc index 9860da1b68..d4f7597e82 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -31,7 +31,7 @@ CONFIG_OVERRIDE_DEVICETREE:=$(call strip_quotes, $(CONFIG_OVERRIDE_DEVICETREE)) # misleadingly named, this is the coreboot version ifeq ($(KERNELVERSION),) ifeq ($(BUILD_TIMELESS),1) -KERNELVERSION := TIMELESS +KERNELVERSION := -TIMELESS--LESSTIME- else KERNELVERSION := $(strip $(if $(GIT),\ $(shell git describe --dirty --always || git describe),\ From 348a44ecae1eb67e9b4e062926e7028012b21ca2 Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Mon, 27 May 2019 02:19:17 -0500 Subject: [PATCH 230/331] mb/google/{misc}: set default SMBIOS manufacturer Legacy Google mainboards (pre-Skylake) shipped with the SMBIOS manufacturer set to GOOGLE, which many Linux drivers rely on for application of DMI quirks. Set it as the default to avoid having to do so for each board's config Change-Id: I61b0217f3535852d7d6e24a1ac78075c20c0825a Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/33027 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/mainboard/google/auron/Kconfig | 4 ++++ src/mainboard/google/beltino/Kconfig | 4 ++++ src/mainboard/google/butterfly/Kconfig | 4 ++++ src/mainboard/google/cyan/Kconfig | 4 ++++ src/mainboard/google/jecht/Kconfig | 4 ++++ src/mainboard/google/link/Kconfig | 5 +++++ src/mainboard/google/parrot/Kconfig | 4 ++++ src/mainboard/google/rambi/Kconfig | 4 ++++ src/mainboard/google/slippy/Kconfig | 3 +++ src/mainboard/google/stout/Kconfig | 4 ++++ 10 files changed, 40 insertions(+) diff --git a/src/mainboard/google/auron/Kconfig b/src/mainboard/google/auron/Kconfig index 3f350e8dd2..69b086fefe 100644 --- a/src/mainboard/google/auron/Kconfig +++ b/src/mainboard/google/auron/Kconfig @@ -72,4 +72,8 @@ config VGA_BIOS_FILE string default "pci8086,0406.rom" +config MAINBOARD_SMBIOS_MANUFACTURER + string + default "GOOGLE" + endif diff --git a/src/mainboard/google/beltino/Kconfig b/src/mainboard/google/beltino/Kconfig index 872d49ddee..df5da9df20 100644 --- a/src/mainboard/google/beltino/Kconfig +++ b/src/mainboard/google/beltino/Kconfig @@ -59,4 +59,8 @@ config VGA_BIOS_FILE string default "pci8086,0406.rom" +config MAINBOARD_SMBIOS_MANUFACTURER + string + default "GOOGLE" + endif # BOARD_GOOGLE_BASEBOARD_BELTINO diff --git a/src/mainboard/google/butterfly/Kconfig b/src/mainboard/google/butterfly/Kconfig index 24797be46c..76bcc3d3b0 100644 --- a/src/mainboard/google/butterfly/Kconfig +++ b/src/mainboard/google/butterfly/Kconfig @@ -44,4 +44,8 @@ config MAINBOARD_VENDOR string default "Hewlett-Packard" +config MAINBOARD_SMBIOS_MANUFACTURER + string + default "GOOGLE" + endif # BOARD_GOOGLE_BUTTERFLY diff --git a/src/mainboard/google/cyan/Kconfig b/src/mainboard/google/cyan/Kconfig index aac14c06c3..bf0cd095f7 100644 --- a/src/mainboard/google/cyan/Kconfig +++ b/src/mainboard/google/cyan/Kconfig @@ -112,4 +112,8 @@ config CBFS_SIZE hex default 0x200000 +config MAINBOARD_SMBIOS_MANUFACTURER + string + default "GOOGLE" + endif # BOARD_GOOGLE_BASEBOARD_CYAN diff --git a/src/mainboard/google/jecht/Kconfig b/src/mainboard/google/jecht/Kconfig index 15ed05b04b..5ffc1bc435 100644 --- a/src/mainboard/google/jecht/Kconfig +++ b/src/mainboard/google/jecht/Kconfig @@ -53,4 +53,8 @@ config VGA_BIOS_FILE string default "pci8086,0406.rom" +config MAINBOARD_SMBIOS_MANUFACTURER + string + default "GOOGLE" + endif diff --git a/src/mainboard/google/link/Kconfig b/src/mainboard/google/link/Kconfig index 612a1b5987..3628f1d8a5 100644 --- a/src/mainboard/google/link/Kconfig +++ b/src/mainboard/google/link/Kconfig @@ -45,4 +45,9 @@ config GBB_HWID string depends on CHROMEOS default "X86 LINK TEST 6638" + +config MAINBOARD_SMBIOS_MANUFACTURER + string + default "GOOGLE" + endif # BOARD_GOOGLE_LINK diff --git a/src/mainboard/google/parrot/Kconfig b/src/mainboard/google/parrot/Kconfig index 4403d792f7..daf605d436 100644 --- a/src/mainboard/google/parrot/Kconfig +++ b/src/mainboard/google/parrot/Kconfig @@ -41,4 +41,8 @@ config VGA_BIOS_FILE string default "pci8086,0106.rom" +config MAINBOARD_SMBIOS_MANUFACTURER + string + default "GOOGLE" + endif # BOARD_GOOGLE_PARROT diff --git a/src/mainboard/google/rambi/Kconfig b/src/mainboard/google/rambi/Kconfig index 6d0c0dfce0..c47b3d7909 100644 --- a/src/mainboard/google/rambi/Kconfig +++ b/src/mainboard/google/rambi/Kconfig @@ -94,4 +94,8 @@ config VGA_BIOS_FILE string default "pci8086,0f31.rom" +config MAINBOARD_SMBIOS_MANUFACTURER + string + default "GOOGLE" + endif # BOARD_GOOGLE_BASEBOARD_RAMBI diff --git a/src/mainboard/google/slippy/Kconfig b/src/mainboard/google/slippy/Kconfig index ecc8aff5ba..242876da86 100644 --- a/src/mainboard/google/slippy/Kconfig +++ b/src/mainboard/google/slippy/Kconfig @@ -71,5 +71,8 @@ config VGA_BIOS_FILE config INTEL_GMA_VBT_FILE default "src/mainboard/$(MAINBOARDDIR)/data.vbt" +config MAINBOARD_SMBIOS_MANUFACTURER + string + default "GOOGLE" endif # BOARD_GOOGLE_BASEBOARD_SLIPPY diff --git a/src/mainboard/google/stout/Kconfig b/src/mainboard/google/stout/Kconfig index 7096d937c7..dfe687b0ff 100644 --- a/src/mainboard/google/stout/Kconfig +++ b/src/mainboard/google/stout/Kconfig @@ -43,4 +43,8 @@ config VGA_BIOS_ID string default "8086,0156" +config MAINBOARD_SMBIOS_MANUFACTURER + string + default "GOOGLE" + endif # BOARD_GOOGLE_STOUT From 924463d1a58075c208b008e13d8b0ec2f2b8731a Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Sun, 26 May 2019 16:25:24 -0500 Subject: [PATCH 231/331] google/clapper: fix up devicetree When clapper was upstreamed, the devicetree was pulled from the wrong firmware branch, leading to some incorrect settings and touchpad, touchscreen, and audio not working. Correct devicetree settings using Chromium branch firmware-clapper-5216.199.B Test: build/boot google/clapper, verify touchpad/touchscreen/audio functional under Linux (GalliumOS 3.0/kernel 4.16.18). Change-Id: Iacfce575a054b1f484149f36d0aa83d20d034d8a Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/33025 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- .../rambi/variants/clapper/devicetree.cb | 19 ++++++++++++++----- 1 file changed, 14 insertions(+), 5 deletions(-) diff --git a/src/mainboard/google/rambi/variants/clapper/devicetree.cb b/src/mainboard/google/rambi/variants/clapper/devicetree.cb index 1e50e53c77..c010af1e73 100644 --- a/src/mainboard/google/rambi/variants/clapper/devicetree.cb +++ b/src/mainboard/google/rambi/variants/clapper/devicetree.cb @@ -32,16 +32,25 @@ chip soc/intel/baytrail register "sdcard_cap_high" = "0x0" # Enable devices in ACPI mode + register "lpe_acpi_mode" = "1" + register "lpss_acpi_mode" = "1" register "scc_acpi_mode" = "1" # Enable PIPEA as DP_C register "gpu_pipea_port_select" = "2" # DP_C - register "gpu_pipea_power_cycle_delay" = "5" # 400ms - register "gpu_pipea_power_on_delay" = "2000" # 200ms - register "gpu_pipea_light_on_delay" = "10" # 1ms + register "gpu_pipea_power_cycle_delay" = "6" # 600ms + register "gpu_pipea_power_on_delay" = "5000" # 500ms + register "gpu_pipea_light_on_delay" = "70" # 7ms register "gpu_pipea_power_off_delay" = "500" # 50ms register "gpu_pipea_light_off_delay" = "2000" # 200ms + # VR PS2 control + register "vnn_ps2_enable" = "1" + register "vcc_ps2_enable" = "1" + + # Disable SLP_X stretching after SUS power well fail. + register "disable_slp_x_stretch_sus_fail" = "1" + device cpu_cluster 0 on device lapic 0 on end end @@ -59,11 +68,11 @@ chip soc/intel/baytrail device pci 18.2 on end # I2C2 device pci 18.3 off end # I2C3 device pci 18.4 off end # I2C4 - device pci 18.5 off end # I2C5 + device pci 18.5 on end # I2C5 device pci 18.6 on end # I2C6 device pci 18.7 off end # I2C7 device pci 1a.0 off end # TXE - device pci 1b.0 off end # HDA + device pci 1b.0 on end # HDA device pci 1c.0 on end # PCIE_PORT1 device pci 1c.1 on end # PCIE_PORT2 device pci 1c.2 off end # PCIE_PORT3 From bdcb4d37506f04e205f11ff45fd0925cf2a5cbc1 Mon Sep 17 00:00:00 2001 From: Jacob Garber Date: Mon, 27 May 2019 17:10:24 -0600 Subject: [PATCH 232/331] drivers/generic/max98357a: Add extra error handling It is possible that acpi_device_scope() and acpi_device_name() can return NULL to indicate an error, so add error handling to check their return values. Change-Id: I4c7ab0c592845d9d5f142e078fc2b505a99ecd12 Signed-off-by: Jacob Garber Found-by: Coverity CID 1362592 Reviewed-on: https://review.coreboot.org/c/coreboot/+/33028 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/drivers/generic/max98357a/max98357a.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/src/drivers/generic/max98357a/max98357a.c b/src/drivers/generic/max98357a/max98357a.c index 1408dacca6..838491dc84 100644 --- a/src/drivers/generic/max98357a/max98357a.c +++ b/src/drivers/generic/max98357a/max98357a.c @@ -36,9 +36,14 @@ static void max98357a_fill_ssdt(struct device *dev) if (!dev->enabled || !config) return; + const char *scope = acpi_device_scope(dev); + const char *name = acpi_device_name(dev); + if (!scope || !name) + return; + /* Device */ - acpigen_write_scope(acpi_device_scope(dev)); - acpigen_write_device(acpi_device_name(dev)); + acpigen_write_scope(scope); + acpigen_write_device(name); acpigen_write_name_string("_HID", MAX98357A_ACPI_HID); acpigen_write_name_integer("_UID", 0); acpigen_write_name_string("_DDN", dev->chip_ops->name); From 5b922726e1220585cbae4e0392817dcca3a2b11f Mon Sep 17 00:00:00 2001 From: Jacob Garber Date: Tue, 28 May 2019 11:47:49 -0600 Subject: [PATCH 233/331] cpu/x86/mtrr: Assert that MSR arrays are fully initialized The initialization logic for the fixed_msrs and msr_index arrays depends on the contents of the fixed MTRR descriptor. However, Coverity is unable to check these values and believes (incorrectly) that the arrays may not be entirely initialized. An assert was added in commit b28025a434 to ensure that one of the loops is entered, but it is simplest to just check that msr_num has iterated over the entire array after the loops are over. This also acts as a sanity check that the values in the MTRR descriptor were hardcoded correctly. Change-Id: Ia573792f74aa6ea5e659c1e2253f112184fbb0a5 Signed-off-by: Jacob Garber Found-by: Coverity CID 1370582 Reviewed-on: https://review.coreboot.org/c/coreboot/+/33048 Tested-by: build bot (Jenkins) Reviewed-by: Lance Zhao --- src/cpu/x86/mtrr/mtrr.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c index d87c3d43d3..60eee319ce 100644 --- a/src/cpu/x86/mtrr/mtrr.c +++ b/src/cpu/x86/mtrr/mtrr.c @@ -331,7 +331,6 @@ static void commit_fixed_mtrrs(void) desc = &fixed_mtrr_desc[i]; num_ranges = (desc->end - desc->begin) / desc->step; - ASSERT(num_ranges > 0); for (j = 0; j < num_ranges; j += RANGES_PER_FIXED_MTRR) { msr_index[msr_num] = desc->msr_index_base + (j / RANGES_PER_FIXED_MTRR); @@ -355,6 +354,9 @@ static void commit_fixed_mtrrs(void) } } + /* Ensure that both arrays were fully initialized */ + ASSERT(msr_num == NUM_FIXED_MTRRS) + for (i = 0; i < ARRAY_SIZE(fixed_msrs); i++) printk(BIOS_DEBUG, "MTRR: Fixed MSR 0x%lx 0x%08x%08x\n", msr_index[i], fixed_msrs[i].hi, fixed_msrs[i].lo); From 3f4a987beefc8cb66ba3f9fff5405cdad8933fd6 Mon Sep 17 00:00:00 2001 From: Patrick Georgi Date: Thu, 23 May 2019 12:31:24 +0200 Subject: [PATCH 234/331] commonlib: renumber CB_TAG_TCPA_LOG It conflicts with VBOOT_WORKBUF but unlike VBOOT_WORKBUF no user can be identified in the coreboot tree for TCPA_LOG, so renumber this. Change-Id: Ib8a850c0ccbcacdf7d288316b54eb82fce874a82 Signed-off-by: Patrick Georgi Reviewed-on: https://review.coreboot.org/c/coreboot/+/32955 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph --- src/commonlib/include/commonlib/coreboot_tables.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/commonlib/include/commonlib/coreboot_tables.h b/src/commonlib/include/commonlib/coreboot_tables.h index bbc8608266..0873dcc2eb 100644 --- a/src/commonlib/include/commonlib/coreboot_tables.h +++ b/src/commonlib/include/commonlib/coreboot_tables.h @@ -310,7 +310,7 @@ void lb_ramoops(struct lb_header *header); #define LB_TAG_CBMEM_CONSOLE 0x0017 #define LB_TAG_MRC_CACHE 0x0018 #define LB_TAG_ACPI_GNVS 0x0024 -#define LB_TAG_TCPA_LOG 0x0034 +#define LB_TAG_TCPA_LOG 0x0036 #define LB_TAG_WIFI_CALIBRATION 0x0027 #define LB_TAG_VPD 0x002c struct lb_cbmem_ref { From 68999a8b869be132f1c8c242d9a6167896920be3 Mon Sep 17 00:00:00 2001 From: Patrick Georgi Date: Thu, 23 May 2019 12:44:00 +0200 Subject: [PATCH 235/331] commonlib: fix typo LB_TAB_* (instead of LB_TAG_*) Also adapt all users of these symbols Change-Id: Ibf924a283d438de49a93ce661b0d9ca1a81cd6d1 Signed-off-by: Patrick Georgi Reviewed-on: https://review.coreboot.org/c/coreboot/+/32956 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph --- src/commonlib/include/commonlib/coreboot_tables.h | 6 +++--- src/lib/coreboot_table.c | 4 ++-- src/mainboard/google/daisy/mainboard.c | 2 +- src/mainboard/google/gale/mainboard.c | 2 +- src/mainboard/google/nyan/mainboard.c | 2 +- src/mainboard/google/nyan_big/mainboard.c | 2 +- src/mainboard/google/nyan_blaze/mainboard.c | 2 +- src/mainboard/google/peach_pit/mainboard.c | 2 +- src/mainboard/google/storm/mainboard.c | 2 +- src/mainboard/google/urara/mainboard.c | 2 +- src/mainboard/google/veyron/mainboard.c | 2 +- src/mainboard/google/veyron_mickey/mainboard.c | 2 +- src/mainboard/google/veyron_rialto/mainboard.c | 2 +- 13 files changed, 16 insertions(+), 16 deletions(-) diff --git a/src/commonlib/include/commonlib/coreboot_tables.h b/src/commonlib/include/commonlib/coreboot_tables.h index 0873dcc2eb..277b7467fb 100644 --- a/src/commonlib/include/commonlib/coreboot_tables.h +++ b/src/commonlib/include/commonlib/coreboot_tables.h @@ -291,9 +291,9 @@ struct lb_gpios { }; #define LB_TAG_VBNV 0x0019 -#define LB_TAB_VBOOT_HANDOFF 0x0020 -#define LB_TAB_VBOOT_WORKBUF 0x0034 -#define LB_TAB_DMA 0x0022 +#define LB_TAG_VBOOT_HANDOFF 0x0020 +#define LB_TAG_VBOOT_WORKBUF 0x0034 +#define LB_TAG_DMA 0x0022 #define LB_TAG_RAM_OOPS 0x0023 #define LB_TAG_MTC 0x002b struct lb_range { diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index 14cd030202..df756983d0 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -219,7 +219,7 @@ static void lb_vboot_handoff(struct lb_header *header) return; vbho = (struct lb_range *)lb_new_record(header); - vbho->tag = LB_TAB_VBOOT_HANDOFF; + vbho->tag = LB_TAG_VBOOT_HANDOFF; vbho->size = sizeof(*vbho); vbho->range_start = (intptr_t)addr; vbho->range_size = size; @@ -231,7 +231,7 @@ static void lb_vboot_workbuf(struct lb_header *header) struct vboot_working_data *wd = vboot_get_working_data(); vbwb = (struct lb_range *)lb_new_record(header); - vbwb->tag = LB_TAB_VBOOT_WORKBUF; + vbwb->tag = LB_TAG_VBOOT_WORKBUF; vbwb->size = sizeof(*vbwb); vbwb->range_start = (uintptr_t)wd + wd->buffer_offset; vbwb->range_size = wd->buffer_size; diff --git a/src/mainboard/google/daisy/mainboard.c b/src/mainboard/google/daisy/mainboard.c index e812189923..46939b70e9 100644 --- a/src/mainboard/google/daisy/mainboard.c +++ b/src/mainboard/google/daisy/mainboard.c @@ -350,7 +350,7 @@ void lb_board(struct lb_header *header) struct lb_range *dma; dma = (struct lb_range *)lb_new_record(header); - dma->tag = LB_TAB_DMA; + dma->tag = LB_TAG_DMA; dma->size = sizeof(*dma); dma->range_start = (uintptr_t)_dma_coherent; dma->range_size = REGION_SIZE(dma_coherent); diff --git a/src/mainboard/google/gale/mainboard.c b/src/mainboard/google/gale/mainboard.c index c8ab88a7fa..8025374efa 100644 --- a/src/mainboard/google/gale/mainboard.c +++ b/src/mainboard/google/gale/mainboard.c @@ -74,7 +74,7 @@ void lb_board(struct lb_header *header) struct lb_range *dma; dma = (struct lb_range *)lb_new_record(header); - dma->tag = LB_TAB_DMA; + dma->tag = LB_TAG_DMA; dma->size = sizeof(*dma); dma->range_start = (uintptr_t)_dma_coherent; dma->range_size = REGION_SIZE(dma_coherent); diff --git a/src/mainboard/google/nyan/mainboard.c b/src/mainboard/google/nyan/mainboard.c index b1cf19e258..807cec3f3f 100644 --- a/src/mainboard/google/nyan/mainboard.c +++ b/src/mainboard/google/nyan/mainboard.c @@ -259,7 +259,7 @@ void lb_board(struct lb_header *header) struct lb_range *dma; dma = (struct lb_range *)lb_new_record(header); - dma->tag = LB_TAB_DMA; + dma->tag = LB_TAG_DMA; dma->size = sizeof(*dma); dma->range_start = (uintptr_t)_dma_coherent; dma->range_size = REGION_SIZE(dma_coherent); diff --git a/src/mainboard/google/nyan_big/mainboard.c b/src/mainboard/google/nyan_big/mainboard.c index c0769f1b00..c8bb8136d4 100644 --- a/src/mainboard/google/nyan_big/mainboard.c +++ b/src/mainboard/google/nyan_big/mainboard.c @@ -257,7 +257,7 @@ void lb_board(struct lb_header *header) struct lb_range *dma; dma = (struct lb_range *)lb_new_record(header); - dma->tag = LB_TAB_DMA; + dma->tag = LB_TAG_DMA; dma->size = sizeof(*dma); dma->range_start = (uintptr_t)_dma_coherent; dma->range_size = REGION_SIZE(dma_coherent); diff --git a/src/mainboard/google/nyan_blaze/mainboard.c b/src/mainboard/google/nyan_blaze/mainboard.c index a296092a19..97d0576278 100644 --- a/src/mainboard/google/nyan_blaze/mainboard.c +++ b/src/mainboard/google/nyan_blaze/mainboard.c @@ -257,7 +257,7 @@ void lb_board(struct lb_header *header) struct lb_range *dma; dma = (struct lb_range *)lb_new_record(header); - dma->tag = LB_TAB_DMA; + dma->tag = LB_TAG_DMA; dma->size = sizeof(*dma); dma->range_start = (uintptr_t)_dma_coherent; dma->range_size = REGION_SIZE(dma_coherent); diff --git a/src/mainboard/google/peach_pit/mainboard.c b/src/mainboard/google/peach_pit/mainboard.c index 0441e52989..ecd2260511 100644 --- a/src/mainboard/google/peach_pit/mainboard.c +++ b/src/mainboard/google/peach_pit/mainboard.c @@ -485,7 +485,7 @@ void lb_board(struct lb_header *header) struct lb_range *dma; dma = (struct lb_range *)lb_new_record(header); - dma->tag = LB_TAB_DMA; + dma->tag = LB_TAG_DMA; dma->size = sizeof(*dma); dma->range_start = (uintptr_t)_dma_coherent; dma->range_size = REGION_SIZE(dma_coherent); diff --git a/src/mainboard/google/storm/mainboard.c b/src/mainboard/google/storm/mainboard.c index fdff5ab0f4..783e6ad7a1 100644 --- a/src/mainboard/google/storm/mainboard.c +++ b/src/mainboard/google/storm/mainboard.c @@ -119,7 +119,7 @@ void lb_board(struct lb_header *header) struct lb_range *dma; dma = (struct lb_range *)lb_new_record(header); - dma->tag = LB_TAB_DMA; + dma->tag = LB_TAG_DMA; dma->size = sizeof(*dma); dma->range_start = (uintptr_t)_dma_coherent; dma->range_size = REGION_SIZE(dma_coherent); diff --git a/src/mainboard/google/urara/mainboard.c b/src/mainboard/google/urara/mainboard.c index 3eaad3451e..7bf8b908a3 100644 --- a/src/mainboard/google/urara/mainboard.c +++ b/src/mainboard/google/urara/mainboard.c @@ -43,7 +43,7 @@ void lb_board(struct lb_header *header) struct lb_range *dma; dma = (struct lb_range *)lb_new_record(header); - dma->tag = LB_TAB_DMA; + dma->tag = LB_TAG_DMA; dma->size = sizeof(*dma); dma->range_start = (uintptr_t)_dma_coherent; dma->range_size = REGION_SIZE(dma_coherent); diff --git a/src/mainboard/google/veyron/mainboard.c b/src/mainboard/google/veyron/mainboard.c index d8ac310643..5243dc9290 100644 --- a/src/mainboard/google/veyron/mainboard.c +++ b/src/mainboard/google/veyron/mainboard.c @@ -123,7 +123,7 @@ void lb_board(struct lb_header *header) struct lb_range *dma; dma = (struct lb_range *)lb_new_record(header); - dma->tag = LB_TAB_DMA; + dma->tag = LB_TAG_DMA; dma->size = sizeof(*dma); dma->range_start = (uintptr_t)_dma_coherent; dma->range_size = REGION_SIZE(dma_coherent); diff --git a/src/mainboard/google/veyron_mickey/mainboard.c b/src/mainboard/google/veyron_mickey/mainboard.c index bb239732b5..9024b6c66a 100644 --- a/src/mainboard/google/veyron_mickey/mainboard.c +++ b/src/mainboard/google/veyron_mickey/mainboard.c @@ -101,7 +101,7 @@ void lb_board(struct lb_header *header) struct lb_range *dma; dma = (struct lb_range *)lb_new_record(header); - dma->tag = LB_TAB_DMA; + dma->tag = LB_TAG_DMA; dma->size = sizeof(*dma); dma->range_start = (uintptr_t)_dma_coherent; dma->range_size = REGION_SIZE(dma_coherent); diff --git a/src/mainboard/google/veyron_rialto/mainboard.c b/src/mainboard/google/veyron_rialto/mainboard.c index 074e6a4e99..6259955669 100644 --- a/src/mainboard/google/veyron_rialto/mainboard.c +++ b/src/mainboard/google/veyron_rialto/mainboard.c @@ -107,7 +107,7 @@ void lb_board(struct lb_header *header) struct lb_range *dma; dma = (struct lb_range *)lb_new_record(header); - dma->tag = LB_TAB_DMA; + dma->tag = LB_TAG_DMA; dma->size = sizeof(*dma); dma->range_start = (uintptr_t)_dma_coherent; dma->range_size = REGION_SIZE(dma_coherent); From e955fa33f6f994158a8bb2454505354ffed9ec9d Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Tue, 14 May 2019 12:52:54 +0200 Subject: [PATCH 236/331] src/drivers/xgi: Move coreboot related includes to xgi_coreboot.h MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: Ia18c77876121594a272a07d56acfaa863d0ccb25 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/29307 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Kyösti Mälkki --- src/drivers/xgi/common/vb_init.c | 2 +- src/drivers/xgi/common/vb_setmode.c | 2 +- src/drivers/xgi/common/vb_util.c | 3 ++- src/drivers/xgi/common/xgi_coreboot.h | 1 + 4 files changed, 5 insertions(+), 3 deletions(-) diff --git a/src/drivers/xgi/common/vb_init.c b/src/drivers/xgi/common/vb_init.c index a20c0683d4..b9191abe3d 100644 --- a/src/drivers/xgi/common/vb_init.c +++ b/src/drivers/xgi/common/vb_init.c @@ -17,7 +17,7 @@ * GNU General Public License for more details. */ -#include +/* coreboot related includes come indirectly from xgi_coreboot.h */ #include "xgi_coreboot.h" #include "vstruct.h" diff --git a/src/drivers/xgi/common/vb_setmode.c b/src/drivers/xgi/common/vb_setmode.c index 162d00cfcf..64412566a1 100644 --- a/src/drivers/xgi/common/vb_setmode.c +++ b/src/drivers/xgi/common/vb_setmode.c @@ -14,7 +14,7 @@ * GNU General Public License for more details. */ -#include +/* coreboot related includes come indirectly from xgi_coreboot.h */ #include "xgi_coreboot.h" #include "vstruct.h" diff --git a/src/drivers/xgi/common/vb_util.c b/src/drivers/xgi/common/vb_util.c index f71ad5680a..248b8af5f8 100644 --- a/src/drivers/xgi/common/vb_util.c +++ b/src/drivers/xgi/common/vb_util.c @@ -14,8 +14,9 @@ * GNU General Public License for more details. */ -#include "xgi_coreboot.h" +/* coreboot related includes come indirectly from xgi_coreboot.h */ +#include "xgi_coreboot.h" #include "vgatypes.h" #include "vb_util.h" diff --git a/src/drivers/xgi/common/xgi_coreboot.h b/src/drivers/xgi/common/xgi_coreboot.h index 41952d6925..5e593eb1c2 100644 --- a/src/drivers/xgi/common/xgi_coreboot.h +++ b/src/drivers/xgi/common/xgi_coreboot.h @@ -22,6 +22,7 @@ #include #include #include +#include #include #include #include From 1ac5ecbfd1acf79f3bea288ef644c28ba54cc685 Mon Sep 17 00:00:00 2001 From: Frans Hendriks Date: Thu, 23 May 2019 09:38:21 +0200 Subject: [PATCH 237/331] soc/intel/braswell/acpi/globalnvs.asl: Remove redundant use of Offset ASL compiler reports twice warning 'unnecessary/redundant use of Offfset operator'. Remove redundant offsets. BUG=N/A TEST=Facebook FBG-1701 booting Embedded Linux Change-Id: I16705b9392b17c50d3988012406e03de393cbcd2 Signed-off-by: Frans Hendriks Reviewed-on: https://review.coreboot.org/c/coreboot/+/32953 Tested-by: build bot (Jenkins) Reviewed-by: HAOUAS Elyes --- src/soc/intel/braswell/acpi/globalnvs.asl | 2 -- 1 file changed, 2 deletions(-) diff --git a/src/soc/intel/braswell/acpi/globalnvs.asl b/src/soc/intel/braswell/acpi/globalnvs.asl index c0b0b8d3d8..9bd9afc924 100644 --- a/src/soc/intel/braswell/acpi/globalnvs.asl +++ b/src/soc/intel/braswell/acpi/globalnvs.asl @@ -31,7 +31,6 @@ OperationRegion (GNVS, SystemMemory, NVSA, 0x2000) Field (GNVS, ByteAcc, NoLock, Preserve) { /* Miscellaneous */ - Offset (0x00), OSYS, 16, /* 0x00 - Operating System */ SMIF, 8, /* 0x02 - SMI function */ PRM0, 8, /* 0x03 - SMI function parameter */ @@ -55,7 +54,6 @@ Field (GNVS, ByteAcc, NoLock, Preserve) CID1, 16, /* 0x1e - Wifi Domain Type */ /* Device Config */ - Offset (0x20), S5U0, 8, /* 0x20 - Enable USB0 in S5 */ S5U1, 8, /* 0x21 - Enable USB1 in S5 */ S3U0, 8, /* 0x22 - Enable USB0 in S3 */ From 73ac12196c61c8d0c21a54dfa87b858662d6859a Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Thu, 23 May 2019 14:41:19 +0200 Subject: [PATCH 238/331] drivers/intel/fsp1.1: Simplify bootflow and clean up MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This gets rid of the boilerplate back and forward calls between the SOC/FSP-driver code and mainboard code. Change-Id: I5d4a10d1da6b3ac5e65efd7f82607b56b80e08d4 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/32961 Reviewed-by: Patrick Georgi Reviewed-by: Frans Hendriks Reviewed-by: Kyösti Mälkki Tested-by: build bot (Jenkins) --- .../intel/fsp1_1/include/fsp/romstage.h | 4 +- src/drivers/intel/fsp1_1/romstage.c | 91 +++++++++---------- src/mainboard/google/cyan/romstage.c | 7 -- src/mainboard/google/glados/romstage.c | 4 +- src/mainboard/intel/kunimitsu/romstage.c | 6 -- src/mainboard/intel/saddlebrook/romstage.c | 6 -- src/mainboard/intel/strago/romstage.c | 2 - 7 files changed, 45 insertions(+), 75 deletions(-) diff --git a/src/drivers/intel/fsp1_1/include/fsp/romstage.h b/src/drivers/intel/fsp1_1/include/fsp/romstage.h index 7efbb1085c..2caceebfa0 100644 --- a/src/drivers/intel/fsp1_1/include/fsp/romstage.h +++ b/src/drivers/intel/fsp1_1/include/fsp/romstage.h @@ -44,15 +44,13 @@ struct romstage_params { void mainboard_memory_init_params(struct romstage_params *params, MEMORY_INIT_UPD *memory_params); -void mainboard_romstage_entry(struct romstage_params *params); +void mainboard_pre_raminit(struct romstage_params *params); void mainboard_save_dimm_info(struct romstage_params *params); void mainboard_add_dimm_info(struct romstage_params *params, struct memory_info *mem_info, int channel, int dimm, int index); void raminit(struct romstage_params *params); void report_memory_config(void); -void romstage_common(struct romstage_params *params); -asmlinkage void romstage_main(FSP_INFO_HEADER *fih); /* Initialize memory margin analysis settings. */ void setup_mma(MEMORY_INIT_UPD *memory_upd); void soc_after_ram_init(struct romstage_params *params); diff --git a/src/drivers/intel/fsp1_1/romstage.c b/src/drivers/intel/fsp1_1/romstage.c index 45ca87aac8..d86d3ab484 100644 --- a/src/drivers/intel/fsp1_1/romstage.c +++ b/src/drivers/intel/fsp1_1/romstage.c @@ -37,48 +37,7 @@ #include #include -asmlinkage void romstage_main(FSP_INFO_HEADER *fih) -{ - struct romstage_params params = { - .chipset_context = fih, - }; - - post_code(0x30); - - timestamp_add_now(TS_START_ROMSTAGE); - - /* Load microcode before RAM init */ - if (CONFIG(SUPPORT_CPU_UCODE_IN_CBFS)) - intel_update_microcode_from_cbfs(); - - /* Display parameters */ - if (!CONFIG(NO_MMCONF_SUPPORT)) - printk(BIOS_SPEW, "CONFIG_MMCONF_BASE_ADDRESS: 0x%08x\n", - CONFIG_MMCONF_BASE_ADDRESS); - printk(BIOS_INFO, "Using FSP 1.1\n"); - - /* Display FSP banner */ - print_fsp_info(fih); - - /* Stash FSP version. */ - params.fsp_version = fsp_version(fih); - - /* Get power state */ - params.power_state = fill_power_state(); - - /* Call into mainboard. */ - mainboard_romstage_entry(¶ms); - soc_after_ram_init(¶ms); - post_code(0x38); -} - -void cache_as_ram_stage_main(FSP_INFO_HEADER *fih) -{ - romstage_main(fih); -} - -/* Entry from the mainboard. */ -void romstage_common(struct romstage_params *params) +static void raminit_common(struct romstage_params *params) { bool s3wake; struct region_device rdev; @@ -153,6 +112,47 @@ void romstage_common(struct romstage_params *params) full_reset(); } +void cache_as_ram_stage_main(FSP_INFO_HEADER *fih) +{ + struct romstage_params params = { + .chipset_context = fih, + }; + + post_code(0x30); + + timestamp_add_now(TS_START_ROMSTAGE); + + /* Load microcode before RAM init */ + if (CONFIG(SUPPORT_CPU_UCODE_IN_CBFS)) + intel_update_microcode_from_cbfs(); + + /* Display parameters */ + if (!CONFIG(NO_MMCONF_SUPPORT)) + printk(BIOS_SPEW, "CONFIG_MMCONF_BASE_ADDRESS: 0x%08x\n", + CONFIG_MMCONF_BASE_ADDRESS); + printk(BIOS_INFO, "Using FSP 1.1\n"); + + /* Display FSP banner */ + print_fsp_info(fih); + + /* Stash FSP version. */ + params.fsp_version = fsp_version(fih); + + /* Get power state */ + params.power_state = fill_power_state(); + + /* Board initialization before and after RAM is enabled */ + mainboard_pre_raminit(¶ms); + + post_code(0x31); + + /* Initialize memory */ + raminit_common(¶ms); + + soc_after_ram_init(¶ms); + post_code(0x38); +} + /* Initialize the power state */ __weak struct chipset_power_state *fill_power_state(void) { @@ -160,13 +160,8 @@ __weak struct chipset_power_state *fill_power_state(void) } /* Board initialization before and after RAM is enabled */ -__weak void mainboard_romstage_entry( - struct romstage_params *params) +__weak void mainboard_pre_raminit(struct romstage_params *params) { - post_code(0x31); - - /* Initialize memory */ - romstage_common(params); } /* Save the DIMM information for SMBIOS table 17 */ diff --git a/src/mainboard/google/cyan/romstage.c b/src/mainboard/google/cyan/romstage.c index c877e42055..dea73e9eee 100644 --- a/src/mainboard/google/cyan/romstage.c +++ b/src/mainboard/google/cyan/romstage.c @@ -19,13 +19,6 @@ #include "spd/spd_util.h" -/* All FSP specific code goes in this block */ -void mainboard_romstage_entry(struct romstage_params *rp) -{ - /* Call back into chipset code with platform values updated. */ - romstage_common(rp); -} - void mainboard_memory_init_params(struct romstage_params *params, MEMORY_INIT_UPD *memory_params) { diff --git a/src/mainboard/google/glados/romstage.c b/src/mainboard/google/glados/romstage.c index 47524c28ba..f2daa38d00 100644 --- a/src/mainboard/google/glados/romstage.c +++ b/src/mainboard/google/glados/romstage.c @@ -25,15 +25,13 @@ #include "spd/spd_util.h" #include "spd/spd.h" -void mainboard_romstage_entry(struct romstage_params *params) +void mainboard_pre_raminit(struct romstage_params *params) { #ifdef EC_ENABLE_KEYBOARD_BACKLIGHT /* Turn on keyboard backlight to indicate we are booting */ if (params->power_state->prev_sleep_state != ACPI_S3) google_chromeec_kbbacklight(25); #endif - /* Initialize memory */ - romstage_common(params); } void mainboard_memory_init_params(struct romstage_params *params, diff --git a/src/mainboard/intel/kunimitsu/romstage.c b/src/mainboard/intel/kunimitsu/romstage.c index f25f88b4dd..f900ca319b 100644 --- a/src/mainboard/intel/kunimitsu/romstage.c +++ b/src/mainboard/intel/kunimitsu/romstage.c @@ -20,12 +20,6 @@ #include "gpio.h" #include "spd/spd.h" -void mainboard_romstage_entry(struct romstage_params *params) -{ - /* Initialize memory */ - romstage_common(params); -} - void mainboard_memory_init_params(struct romstage_params *params, MEMORY_INIT_UPD *memory_params) { diff --git a/src/mainboard/intel/saddlebrook/romstage.c b/src/mainboard/intel/saddlebrook/romstage.c index 48d39db309..82b85fd700 100644 --- a/src/mainboard/intel/saddlebrook/romstage.c +++ b/src/mainboard/intel/saddlebrook/romstage.c @@ -33,12 +33,6 @@ void car_mainboard_pre_console_init(void) nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); } -void mainboard_romstage_entry(struct romstage_params *params) -{ - post_code(0x31); - romstage_common(params); -} - void mainboard_memory_init_params( struct romstage_params *params, MEMORY_INIT_UPD *memory_params) diff --git a/src/mainboard/intel/strago/romstage.c b/src/mainboard/intel/strago/romstage.c index ba0ff7b85e..1dc7ba32fc 100644 --- a/src/mainboard/intel/strago/romstage.c +++ b/src/mainboard/intel/strago/romstage.c @@ -14,8 +14,6 @@ * GNU General Public License for more details. */ -#include -#include #include #include "onboard.h" #include From 56e2d7d21aeffb75af34606bc034ee4fed560775 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Thu, 23 May 2019 15:07:49 +0200 Subject: [PATCH 239/331] soc/intel/skylake: Use common cpu/intel/car romstage code MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Setting up the console and entering postcar can be done in a common place. Change-Id: I8a8db0fcb4f0fbbb121a8195a8a8b6644c28db07 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/32962 Reviewed-by: Patrick Georgi Reviewed-by: Kyösti Mälkki Tested-by: build bot (Jenkins) --- src/drivers/intel/fsp1_1/car.c | 14 +++---- src/drivers/intel/fsp1_1/include/fsp/car.h | 1 - src/soc/intel/skylake/romstage/Makefile.inc | 2 +- src/soc/intel/skylake/romstage/car_stage.S | 41 --------------------- 4 files changed, 6 insertions(+), 52 deletions(-) delete mode 100644 src/soc/intel/skylake/romstage/car_stage.S diff --git a/src/drivers/intel/fsp1_1/car.c b/src/drivers/intel/fsp1_1/car.c index a1ee7b141a..82dc320e0e 100644 --- a/src/drivers/intel/fsp1_1/car.c +++ b/src/drivers/intel/fsp1_1/car.c @@ -15,6 +15,7 @@ #include #include +#include #include #include #include @@ -27,7 +28,7 @@ /* platform_enter_postcar() determines the stack to use after * cache-as-ram is torn down as well as the MTRR settings to use, * and continues execution in postcar stage. */ -static void platform_enter_postcar(void) +void platform_enter_postcar(void) { struct postcar_frame pcf; size_t alignment; @@ -153,17 +154,15 @@ asmlinkage void cache_as_ram_main(struct cache_as_ram_params *car_params) platform_enter_postcar(); } -/* This is the romstage C entry for platforms with - CONFIG_C_ENVIRONMENT_BOOTBLOCK */ -asmlinkage void romstage_c_entry(void) +/* This is the entry for platforms with CONFIG_C_ENVIRONMENT_BOOTBLOCK + called from cpu/intel/car/romstage.c */ +void mainboard_romstage_entry(unsigned long bist) { /* Need to locate the current FSP_INFO_HEADER. The cache-as-ram * is still enabled. We can directly access work buffer here. */ FSP_INFO_HEADER *fih; struct prog fsp = PROG_INIT(PROG_REFCODE, "fsp.bin"); - console_init(); - if (prog_locate(&fsp)) { fih = NULL; printk(BIOS_ERR, "Unable to locate %s\n", prog_name(&fsp)); @@ -174,9 +173,6 @@ asmlinkage void romstage_c_entry(void) } cache_as_ram_stage_main(fih); - - /* we don't return here */ - platform_enter_postcar(); } void __weak car_mainboard_pre_console_init(void) diff --git a/src/drivers/intel/fsp1_1/include/fsp/car.h b/src/drivers/intel/fsp1_1/include/fsp/car.h index 0ae687a9d7..c05139231c 100644 --- a/src/drivers/intel/fsp1_1/include/fsp/car.h +++ b/src/drivers/intel/fsp1_1/include/fsp/car.h @@ -31,7 +31,6 @@ struct cache_as_ram_params { /* Entry points from the cache-as-ram assembly code. */ asmlinkage void cache_as_ram_main(struct cache_as_ram_params *car_params); -asmlinkage void romstage_c_entry(void); /* Per stage calls from the above two functions. The void * return from * cache_as_ram_stage_main() is the stack pointer to use in RAM after * exiting cache-as-ram mode. */ diff --git a/src/soc/intel/skylake/romstage/Makefile.inc b/src/soc/intel/skylake/romstage/Makefile.inc index 8bfbfea66a..e929ebaf17 100644 --- a/src/soc/intel/skylake/romstage/Makefile.inc +++ b/src/soc/intel/skylake/romstage/Makefile.inc @@ -1,4 +1,4 @@ -romstage-$(CONFIG_PLATFORM_USES_FSP1_1) += car_stage.S +romstage-$(CONFIG_PLATFORM_USES_FSP1_1) += ../../../../cpu/intel/car/romstage.c romstage-$(CONFIG_PLATFORM_USES_FSP1_1) += romstage.c romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += romstage_fsp20.c romstage-y += systemagent.c diff --git a/src/soc/intel/skylake/romstage/car_stage.S b/src/soc/intel/skylake/romstage/car_stage.S deleted file mode 100644 index d8b45cb258..0000000000 --- a/src/soc/intel/skylake/romstage/car_stage.S +++ /dev/null @@ -1,41 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2015 Google Inc - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include - -/* I/O delay between post codes on failure */ -#define LHLT_DELAY 0x50000 - -.text -.global car_stage_entry -car_stage_entry: - call romstage_c_entry - - /* we don't return here */ - movb $0x69, %ah - jmp .Lhlt - -.Lhlt: - xchg %al, %ah -#if CONFIG(POST_IO) - outb %al, $CONFIG_POST_IO_PORT -#else - post_code(POST_DEAD_CODE) -#endif - movl $LHLT_DELAY, %ecx -.Lhlt_Delay: - outb %al, $0xED - loop .Lhlt_Delay - jmp .Lhlt From 23cb12b0404bbcb451140592b9502751a0ff719f Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Tue, 25 Jul 2017 19:36:25 +0200 Subject: [PATCH 240/331] payloads/external/iPXE: Add more Kconfig options MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add two new options: * Disable the prompt "Press Ctrl+B for the iPXE command line..." Add a boolean that disables the initial 2 second timeout. * Include a script that is executed instead of showing a shell. Allows to add a script that will be included into the iPXE ROM. Tested on Lenovo T500 and PC Engines apu2. Change-Id: Ie1083d8571d9d1f1c7c71659fb6ff0de2eecad0e Signed-off-by: Patrick Rudolph Signed-off-by: Michał Żygowski Reviewed-on: https://review.coreboot.org/c/coreboot/+/20782 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- payloads/external/Makefile.inc | 9 +++++++-- payloads/external/iPXE/Kconfig | 26 ++++++++++++++++++++++++++ payloads/external/iPXE/Makefile | 21 ++++++++++++++++++++- 3 files changed, 53 insertions(+), 3 deletions(-) diff --git a/payloads/external/Makefile.inc b/payloads/external/Makefile.inc index 5edbb81b18..9c34efabeb 100644 --- a/payloads/external/Makefile.inc +++ b/payloads/external/Makefile.inc @@ -229,7 +229,9 @@ endif ifeq ($(CONFIG_BUILD_IPXE),y) PXE_ROM_FILE:=payloads/external/iPXE/ipxe/ipxe.rom endif - +ifeq ($(CONFIG_PXE_ADD_SCRIPT),y) +PXE_CONFIG_SCRIPT:=$(abspath $(patsubst "%",%,$(CONFIG_PXE_SCRIPT))) +endif ifeq ($(CONFIG_CONSOLE_SERIAL)$(CONFIG_DRIVERS_UART_8250IO),yy) IPXE_UART=COM$(call int-add,$(CONFIG_UART_FOR_CONSOLE) 1) endif @@ -244,7 +246,7 @@ cbfs-files-$(CONFIG_PXE_ROM)$(CONFIG_BUILD_IPXE) += pci$(CONFIG_PXE_ROM_ID).rom pci$(CONFIG_PXE_ROM_ID).rom-file := $(PXE_ROM_FILE) pci$(CONFIG_PXE_ROM_ID).rom-type := raw -payloads/external/iPXE/ipxe/ipxe.rom ipxe: $(DOTCONFIG) +payloads/external/iPXE/ipxe/ipxe.rom ipxe: $(DOTCONFIG) $(PXE_CONFIG_SCRIPT) $(MAKE) -C payloads/external/iPXE all \ CROSS_COMPILE="$(CROSS_COMPILE_$(ARCH-ramstage-y))" \ PXE_ROM_PCI_ID=$(PXE_ROM_PCI_ID) \ @@ -253,6 +255,9 @@ payloads/external/iPXE/ipxe/ipxe.rom ipxe: $(DOTCONFIG) CONSOLE_SERIAL=$(IPXE_SERIAL_CONSOLE) \ IPXE_UART=$(IPXE_UART) \ CONFIG_TTYS0_BAUD=$(CONFIG_TTYS0_BAUD) \ + CONFIG_SCRIPT=$(PXE_CONFIG_SCRIPT) \ + CONFIG_HAS_SCRIPT=$(CONFIG_PXE_ADD_SCRIPT) \ + CONFIG_PXE_NO_PROMT=$(CONFIG_PXE_NO_PROMT) \ MFLAGS= MAKEFLAGS= # LinuxBoot diff --git a/payloads/external/iPXE/Kconfig b/payloads/external/iPXE/Kconfig index f99182c908..7cb0d1e249 100644 --- a/payloads/external/iPXE/Kconfig +++ b/payloads/external/iPXE/Kconfig @@ -87,5 +87,31 @@ config PXE_SERIAL_CONSOLE Unselect to let only SeaBIOS handle printing output. +config PXE_NO_PROMT + bool "Do not show prompt to boot from PXE" + default n + depends on BUILD_IPXE + help + Don't wait for the user to press Ctrl-B. + The PXE still can be run as it shows up in SeaBIOS's payload list. + +config PXE_ADD_SCRIPT + bool "Embed an iPXE script for automated provisioning" + depends on BUILD_IPXE + default n + help + Enable to embed a script that is run instead of an iPXE shell. + +config PXE_SCRIPT + string "Embedded iPXE script path and filename" + depends on PXE_ADD_SCRIPT + default "" + help + Path to a script that is embedded into the iPXE binary. + Example: startup.ipxe + + Uses the ipxe script instead showing the prompt: + "Press Ctrl-B to start iPXE..." + endmenu endif diff --git a/payloads/external/iPXE/Makefile b/payloads/external/iPXE/Makefile index 3a0585fc78..0c071fa13b 100644 --- a/payloads/external/iPXE/Makefile +++ b/payloads/external/iPXE/Makefile @@ -54,15 +54,34 @@ ifeq ($(CONSOLE_SERIAL),yy) sed 's|#define\s*COMCONSOLE.*|#define COMCONSOLE $(IPXE_UART)|' "$(project_dir)/src/config/serial.h" > "$(project_dir)/src/config/serial.h.tmp" sed 's|#define\s*COMSPEED.*|#define COMSPEED $(CONFIG_TTYS0_BAUD)|' "$(project_dir)/src/config/serial.h.tmp" > "$(project_dir)/src/config/serial.h" endif +ifneq ($(filter y,$(CONFIG_HAS_SCRIPT) $(CONFIG_PXE_NO_PROMT)),) + cp "$(project_dir)/src/config/general.h" "$(project_dir)/src/config/general.h.cb" +endif +ifeq ($(CONFIG_HAS_SCRIPT),y) + sed 's|//#define\s*IMAGE_SCRIPT.*|#define IMAGE_SCRIPT|' "$(project_dir)/src/config/general.h" > "$(project_dir)/src/config/general.h.tmp" + mv "$(project_dir)/src/config/general.h.tmp" "$(project_dir)/src/config/general.h" +endif +ifeq ($(CONFIG_PXE_NO_PROMT),y) + sed 's|#define\s*BANNER_TIMEOUT.*|#define BANNER_TIMEOUT 0|' "$(project_dir)/src/config/general.h" > "$(project_dir)/src/config/general.h.tmp" + mv "$(project_dir)/src/config/general.h.tmp" "$(project_dir)/src/config/general.h" +endif -build: config +build: config $(CONFIG_SCRIPT) +ifeq ($(CONFIG_HAS_SCRIPT),y) + echo " MAKE $(project_name) $(TAG-y) EMBED=$(CONFIG_SCRIPT)" + $(MAKE) -C $(project_dir)/src bin/$(PXE_ROM_PCI_ID).rom EMBED=$(CONFIG_SCRIPT) +else echo " MAKE $(project_name) $(TAG-y)" $(MAKE) -C $(project_dir)/src bin/$(PXE_ROM_PCI_ID).rom +endif cp $(project_dir)/src/bin/$(PXE_ROM_PCI_ID).rom $(project_dir)/ipxe.rom ifeq ($(CONSOLE_SERIAL),yy) cp "$(project_dir)/src/config/console.h.cb" "$(project_dir)/src/config/console.h" cp "$(project_dir)/src/config/serial.h.cb" "$(project_dir)/src/config/serial.h" endif +ifneq ($(filter y,$(CONFIG_HAS_SCRIPT) $(CONFIG_PXE_NO_PROMT)),) + cp "$(project_dir)/src/config/general.h.cb" "$(project_dir)/src/config/general.h" +endif clean: test -d $(project_dir) && $(MAKE) -C $(project_dir)/src veryclean || exit 0 From a998e280163b84c0786cb8d4b7f216a36b262d6a Mon Sep 17 00:00:00 2001 From: Christian Walter Date: Thu, 23 May 2019 16:14:59 +0200 Subject: [PATCH 241/331] src/soc/intel/skylake/chip.h: Add smbios.h for Type9 Entries In order to add the smbios_slot_desc for the SMBIOS Type9 entries into the devicetree, and not use numbers but strings like "SlotTypePciExpressGen3X4", smbios.h needs to be included in the static.c. Change-Id: Iace547868b4ce8eb7d3624baf1abd1187c1e5f51 Signed-off-by: Christian Walter Reviewed-on: https://review.coreboot.org/c/coreboot/+/32965 Reviewed-by: Philipp Deppenwiese Tested-by: build bot (Jenkins) --- src/soc/intel/skylake/chip.h | 1 + 1 file changed, 1 insertion(+) diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index 57d51e76b2..a537165dd9 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -34,6 +34,7 @@ #include #include #include +#include #define MAX_PEG_PORTS 3 From 543be8d367468253096311fe9198bb8cc66ad5b4 Mon Sep 17 00:00:00 2001 From: Christian Walter Date: Sun, 26 May 2019 01:14:13 +0200 Subject: [PATCH 242/331] payloads/external/Linuxboot: Fix Makefile when not using bash Adding "SHELL := /bin/bash" to the Makefile makes sure, that we use the bash shell which is needed here. Tested with oh-my-zsh. Change-Id: I71495e15b8f1a495af7d8ab21cc5235feb595e01 Signed-off-by: Christian Walter Reviewed-on: https://review.coreboot.org/c/coreboot/+/33014 Reviewed-by: Patrick Georgi Tested-by: build bot (Jenkins) --- payloads/external/LinuxBoot/targets/linux.mk | 1 + 1 file changed, 1 insertion(+) diff --git a/payloads/external/LinuxBoot/targets/linux.mk b/payloads/external/LinuxBoot/targets/linux.mk index 5632a0b923..e32ad1e21b 100644 --- a/payloads/external/LinuxBoot/targets/linux.mk +++ b/payloads/external/LinuxBoot/targets/linux.mk @@ -12,6 +12,7 @@ ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ## GNU General Public License for more details. ## +SHELL := /bin/bash ARCH-$(CONFIG_LINUXBOOT_X86_64)=x86_64 ARCH-$(CONFIG_LINUXBOOT_X86)=x86 From 62c0b61bed96df60967d2980d9ee4e4b3f0461b0 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Tue, 5 Feb 2019 21:10:01 +0100 Subject: [PATCH 243/331] soc/intel/denverton_ns: Don't use CONFIG_CBFS_SIZE CONFIG_CBFS_SIZE is only meaningful to generate the default fmap layout and ought not to be used in the code directly. Change-Id: Iae72a9fb02d62d7548d34689f5eb371f34cd3d81 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/31249 Reviewed-by: Angel Pons Reviewed-by: David Guckian Reviewed-by: Paul Menzel Reviewed-by: Nico Huber Tested-by: build bot (Jenkins) --- src/soc/intel/denverton_ns/bootblock/bootblock.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/soc/intel/denverton_ns/bootblock/bootblock.c b/src/soc/intel/denverton_ns/bootblock/bootblock.c index f16ee20620..57e3a2e49b 100644 --- a/src/soc/intel/denverton_ns/bootblock/bootblock.c +++ b/src/soc/intel/denverton_ns/bootblock/bootblock.c @@ -37,8 +37,8 @@ const FSPT_UPD temp_ram_init_params = { .MicrocodeRegionLength = (UINT32)CONFIG_CPU_MICROCODE_CBFS_LEN, .CodeRegionBase = - (UINT32)(0x100000000ULL - CONFIG_CBFS_SIZE), - .CodeRegionLength = (UINT32)CONFIG_CBFS_SIZE, + (UINT32)(0x100000000ULL - CONFIG_ROM_SIZE), + .CodeRegionLength = (UINT32)CONFIG_ROM_SIZE, .Reserved1 = {0}, }, .FsptConfig = { From b12ece98b09dd88634d93bcb41ca5c4cb9d86364 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Wed, 15 May 2019 21:01:02 +0200 Subject: [PATCH 244/331] src/{include,arch,cpu,lib}: Add missing 'include ' is supposed to provide and . So when is included, and/or is removed. Change-Id: I57aead27806e307b9827fc7ee2cd663f12ee6e5e Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/31892 Tested-by: build bot (Jenkins) Reviewed-by: Lijian Zhao --- src/arch/x86/include/arch/acpi.h | 2 +- src/cpu/allwinner/a10/twi.c | 7 ++++--- src/cpu/amd/family_10h-family_15h/init_cpus.c | 2 ++ src/cpu/amd/family_10h-family_15h/powernow_acpi.c | 2 +- src/include/types.h | 2 ++ src/lib/lzmadecode.c | 2 +- 6 files changed, 11 insertions(+), 6 deletions(-) diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h index 60efdd0d7a..dbf46a9b1b 100644 --- a/src/arch/x86/include/arch/acpi.h +++ b/src/arch/x86/include/arch/acpi.h @@ -56,11 +56,11 @@ #define OEM_ID "COREv4" /* Must be exactly 6 bytes long! */ #if !defined(__ASSEMBLER__) && !defined(__ACPI__) && !defined(__ROMCC__) -#include #include #include #include #include +#include #define RSDP_SIG "RSD PTR " /* RSDT pointer signature */ #define ASLC "CORE" /* Must be exactly 4 bytes long! */ diff --git a/src/cpu/allwinner/a10/twi.c b/src/cpu/allwinner/a10/twi.c index 6e7f9e214a..01ee5a5c6f 100644 --- a/src/cpu/allwinner/a10/twi.c +++ b/src/cpu/allwinner/a10/twi.c @@ -20,12 +20,13 @@ * Largely based on the uboot-sunxi code. */ -#include "memmap.h" -#include "twi.h" - #include #include #include +#include + +#include "memmap.h" +#include "twi.h" #define TWI_BASE(n) (A1X_TWI0_BASE + 0x400 * (n)) diff --git a/src/cpu/amd/family_10h-family_15h/init_cpus.c b/src/cpu/amd/family_10h-family_15h/init_cpus.c index 719d62fbcc..310706ba95 100644 --- a/src/cpu/amd/family_10h-family_15h/init_cpus.c +++ b/src/cpu/amd/family_10h-family_15h/init_cpus.c @@ -17,6 +17,8 @@ #include #include #include +#include + #include "init_cpus.h" #if CONFIG(HAVE_OPTION_TABLE) diff --git a/src/cpu/amd/family_10h-family_15h/powernow_acpi.c b/src/cpu/amd/family_10h-family_15h/powernow_acpi.c index d024069e30..e648b71750 100644 --- a/src/cpu/amd/family_10h-family_15h/powernow_acpi.c +++ b/src/cpu/amd/family_10h-family_15h/powernow_acpi.c @@ -16,7 +16,6 @@ */ #include -#include #include #include #include @@ -30,6 +29,7 @@ #include #include #include +#include static inline uint8_t is_fam15h(void) { diff --git a/src/include/types.h b/src/include/types.h index b76c95b5bb..d6fdc08588 100644 --- a/src/include/types.h +++ b/src/include/types.h @@ -15,6 +15,8 @@ #ifndef __TYPES_H #define __TYPES_H + +/* types.h is supposed to provide stdint and stddef defined in here: */ #include #include diff --git a/src/lib/lzmadecode.c b/src/lib/lzmadecode.c index 0a5d038638..c45e131708 100644 --- a/src/lib/lzmadecode.c +++ b/src/lib/lzmadecode.c @@ -20,7 +20,7 @@ */ #include "lzmadecode.h" -#include +#include #define kNumTopBits 24 #define kTopValue ((UInt32)1 << kNumTopBits) From bd1683da29d5688f97fcc43bef3e0df74e4196f9 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Wed, 15 May 2019 21:05:37 +0200 Subject: [PATCH 245/331] src/{device,drivers}: Add missing 'include ' is supposed to provide and . So when is included, and/or is removed. Change-Id: I3395715f9e2b03175089186ab2e57d9e508fc87c Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/32806 Tested-by: build bot (Jenkins) Reviewed-by: Lijian Zhao --- src/device/dram/ddr2.c | 1 + src/device/dram/ddr3.c | 1 + src/drivers/generic/bayhub/bh720.h | 2 ++ src/drivers/intel/fsp2_0/graphics.c | 1 + src/drivers/intel/fsp2_0/include/fsp/util.h | 1 + src/drivers/intel/fsp2_0/memory_init.c | 1 + src/drivers/intel/fsp2_0/silicon_init.c | 1 + src/drivers/intel/fsp2_0/temp_ram_exit.c | 1 + src/drivers/intel/fsp2_0/util.c | 1 + src/drivers/net/atl1e.c | 1 + src/drivers/net/r8168.c | 2 ++ src/drivers/pc80/rtc/mc146818rtc.c | 2 +- src/drivers/xpowers/axp209/axp209.c | 7 ++++--- 13 files changed, 18 insertions(+), 4 deletions(-) diff --git a/src/device/dram/ddr2.c b/src/device/dram/ddr2.c index 53106f23f9..60588b880b 100644 --- a/src/device/dram/ddr2.c +++ b/src/device/dram/ddr2.c @@ -26,6 +26,7 @@ #include #include #include +#include /*============================================================================== * = DDR2 SPD decoding helpers diff --git a/src/device/dram/ddr3.c b/src/device/dram/ddr3.c index e545b4d036..3272dac6d7 100644 --- a/src/device/dram/ddr3.c +++ b/src/device/dram/ddr3.c @@ -27,6 +27,7 @@ #include #include #include +#include /*============================================================================== * = DDR3 SPD decoding helpers diff --git a/src/drivers/generic/bayhub/bh720.h b/src/drivers/generic/bayhub/bh720.h index 3183bf1a84..ecea513bfb 100644 --- a/src/drivers/generic/bayhub/bh720.h +++ b/src/drivers/generic/bayhub/bh720.h @@ -15,6 +15,8 @@ * GNU General Public License for more details. */ +#include + enum { BH720_PROTECT = 0xd0, BH720_PROTECT_LOCK_OFF = 0, diff --git a/src/drivers/intel/fsp2_0/graphics.c b/src/drivers/intel/fsp2_0/graphics.c index e0c63d2570..55dc6dfddc 100644 --- a/src/drivers/intel/fsp2_0/graphics.c +++ b/src/drivers/intel/fsp2_0/graphics.c @@ -13,6 +13,7 @@ #include #include #include +#include enum pixel_format { pixel_rgbx_8bpc = 0, diff --git a/src/drivers/intel/fsp2_0/include/fsp/util.h b/src/drivers/intel/fsp2_0/include/fsp/util.h index 231162ed17..ef7ecd163f 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/util.h +++ b/src/drivers/intel/fsp2_0/include/fsp/util.h @@ -19,6 +19,7 @@ #include #include #include +#include struct hob_header { uint16_t type; diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c index 60e3310a4d..f248a58c77 100644 --- a/src/drivers/intel/fsp2_0/memory_init.c +++ b/src/drivers/intel/fsp2_0/memory_init.c @@ -32,6 +32,7 @@ #include #include #include +#include /* TPM MRC hash functionality depends on vboot starting before memory init. */ _Static_assert(!CONFIG(FSP2_0_USES_TPM_MRC_HASH) || diff --git a/src/drivers/intel/fsp2_0/silicon_init.c b/src/drivers/intel/fsp2_0/silicon_init.c index 302bc0f3ad..e72e4ac163 100644 --- a/src/drivers/intel/fsp2_0/silicon_init.c +++ b/src/drivers/intel/fsp2_0/silicon_init.c @@ -22,6 +22,7 @@ #include #include #include +#include struct fsp_header fsps_hdr; diff --git a/src/drivers/intel/fsp2_0/temp_ram_exit.c b/src/drivers/intel/fsp2_0/temp_ram_exit.c index ced3584fd0..075e923f84 100644 --- a/src/drivers/intel/fsp2_0/temp_ram_exit.c +++ b/src/drivers/intel/fsp2_0/temp_ram_exit.c @@ -15,6 +15,7 @@ #include #include #include +#include void fsp_temp_ram_exit(void) { diff --git a/src/drivers/intel/fsp2_0/util.c b/src/drivers/intel/fsp2_0/util.c index 19b8127ac5..f670e6facd 100644 --- a/src/drivers/intel/fsp2_0/util.c +++ b/src/drivers/intel/fsp2_0/util.c @@ -16,6 +16,7 @@ #include #include #include +#include static bool looks_like_fsp_header(const uint8_t *raw_hdr) { diff --git a/src/drivers/net/atl1e.c b/src/drivers/net/atl1e.c index f6f04a1035..097b768b12 100644 --- a/src/drivers/net/atl1e.c +++ b/src/drivers/net/atl1e.c @@ -26,6 +26,7 @@ #include #include #include +#include #define REG_SPI_FLASH_CTRL 0x200 #define SPI_FLASH_CTRL_EN_VPD 0x2000 diff --git a/src/drivers/net/r8168.c b/src/drivers/net/r8168.c index 3200163ab3..3188778900 100644 --- a/src/drivers/net/r8168.c +++ b/src/drivers/net/r8168.c @@ -33,6 +33,8 @@ #include #include #include +#include + #include "chip.h" #define NIC_TIMEOUT 1000 diff --git a/src/drivers/pc80/rtc/mc146818rtc.c b/src/drivers/pc80/rtc/mc146818rtc.c index 6e37cd2f78..e0869a9337 100644 --- a/src/drivers/pc80/rtc/mc146818rtc.c +++ b/src/drivers/pc80/rtc/mc146818rtc.c @@ -19,7 +19,6 @@ #include #include #include -#include #include #include #include @@ -29,6 +28,7 @@ #include #include #include +#include /* There's no way around this include guard. option_table.h is autogenerated */ #if CONFIG(USE_OPTION_TABLE) diff --git a/src/drivers/xpowers/axp209/axp209.c b/src/drivers/xpowers/axp209/axp209.c index da575ccffd..93e864dff7 100644 --- a/src/drivers/xpowers/axp209/axp209.c +++ b/src/drivers/xpowers/axp209/axp209.c @@ -8,12 +8,13 @@ * Subject to the GNU GPL v2, or (at your option) any later version. */ -#include "axp209.h" -#include "chip.h" - #include #include #include +#include + +#include "axp209.h" +#include "chip.h" /* Hide these definitions from the rest of the source, so keep them here */ enum registers { From 5fd93e05820d742fac5dbc1b371b464a88bb9043 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Wed, 15 May 2019 21:07:30 +0200 Subject: [PATCH 246/331] src/{ec,vendorcode}: Add missing 'include is supposed to provide and . So when is included, and/or is removed. Change-Id: I1eb4163fb36a47b584f1fc9dd3c012e2930e9866 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/32807 Tested-by: build bot (Jenkins) Reviewed-by: Lijian Zhao --- src/ec/lenovo/h8/h8.c | 1 + src/ec/lenovo/h8/wwan.c | 1 + src/ec/lenovo/pmh7/pmh7.c | 1 + src/vendorcode/siemens/hwilib/hwilib.c | 3 ++- 4 files changed, 5 insertions(+), 1 deletion(-) diff --git a/src/ec/lenovo/h8/h8.c b/src/ec/lenovo/h8/h8.c index de4f2c29b2..f707014c31 100644 --- a/src/ec/lenovo/h8/h8.c +++ b/src/ec/lenovo/h8/h8.c @@ -23,6 +23,7 @@ #include #include #include +#include #include "h8.h" #include "chip.h" diff --git a/src/ec/lenovo/h8/wwan.c b/src/ec/lenovo/h8/wwan.c index cf3c8f7cf0..e79cb61332 100644 --- a/src/ec/lenovo/h8/wwan.c +++ b/src/ec/lenovo/h8/wwan.c @@ -18,6 +18,7 @@ #include #include #include +#include #include "h8.h" #include "chip.h" diff --git a/src/ec/lenovo/pmh7/pmh7.c b/src/ec/lenovo/pmh7/pmh7.c index 986abb5d81..ef505cd164 100644 --- a/src/ec/lenovo/pmh7/pmh7.c +++ b/src/ec/lenovo/pmh7/pmh7.c @@ -20,6 +20,7 @@ #include #include #include +#include #include "pmh7.h" #include "chip.h" diff --git a/src/vendorcode/siemens/hwilib/hwilib.c b/src/vendorcode/siemens/hwilib/hwilib.c index 1213dce4ed..a4d87addff 100644 --- a/src/vendorcode/siemens/hwilib/hwilib.c +++ b/src/vendorcode/siemens/hwilib/hwilib.c @@ -18,8 +18,9 @@ #include #include #include -#include "hwilib.h" +#include +#include "hwilib.h" #define MAX_BLOCK_NUM 4 #define LEN_HIB 0x1fd From 51401c30509d189d07a8a94958bdecdfd8b7667d Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Wed, 15 May 2019 21:09:30 +0200 Subject: [PATCH 247/331] src/northbridge: Add missing 'include ' is supposed to provide and . When is included, and/or is removed. Change-Id: Iad5367bed844b866b2ad87639eee29a16d9a99ed Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/32808 Tested-by: build bot (Jenkins) Reviewed-by: Lijian Zhao --- src/northbridge/amd/amdfam10/link_control.c | 1 + src/northbridge/amd/amdfam10/misc_control.c | 1 + src/northbridge/amd/amdfam10/northbridge.c | 1 + src/northbridge/amd/amdht/h3finit.c | 1 + src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 2 ++ src/northbridge/amd/amdmct/mct_ddr3/s3utils.c | 2 ++ src/northbridge/amd/amdmct/wrappers/mcti_d.c | 1 + src/northbridge/intel/gm45/gma.c | 1 + src/northbridge/intel/haswell/gma.c | 1 + src/northbridge/intel/i945/early_init.c | 5 +++-- src/northbridge/intel/i945/gma.c | 1 + src/northbridge/intel/nehalem/gma.c | 1 + src/northbridge/intel/nehalem/raminit.c | 10 +++++----- src/northbridge/intel/pineview/early_init.c | 2 +- src/northbridge/intel/pineview/gma.c | 7 ++++--- src/northbridge/intel/sandybridge/early_init.c | 3 ++- src/northbridge/intel/sandybridge/gma.c | 1 + src/northbridge/intel/sandybridge/raminit.c | 1 + src/northbridge/intel/x4x/gma.c | 1 + src/northbridge/intel/x4x/raminit.c | 1 + 20 files changed, 32 insertions(+), 12 deletions(-) diff --git a/src/northbridge/amd/amdfam10/link_control.c b/src/northbridge/amd/amdfam10/link_control.c index 871a4366c2..384772374b 100644 --- a/src/northbridge/amd/amdfam10/link_control.c +++ b/src/northbridge/amd/amdfam10/link_control.c @@ -25,6 +25,7 @@ #include #include #include +#include #include "amdfam10.h" diff --git a/src/northbridge/amd/amdfam10/misc_control.c b/src/northbridge/amd/amdfam10/misc_control.c index bbaec53887..b0a1ab679a 100644 --- a/src/northbridge/amd/amdfam10/misc_control.c +++ b/src/northbridge/amd/amdfam10/misc_control.c @@ -32,6 +32,7 @@ #include #include #include +#include #include "amdfam10.h" diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index 1d071c1877..a681961be2 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -34,6 +34,7 @@ #include #include #include +#include #if CONFIG(LOGICAL_CPUS) #include diff --git a/src/northbridge/amd/amdht/h3finit.c b/src/northbridge/amd/amdht/h3finit.c index 8c33ad8156..cda0a28cef 100644 --- a/src/northbridge/amd/amdht/h3finit.c +++ b/src/northbridge/amd/amdht/h3finit.c @@ -36,6 +36,7 @@ #include #include #include +#include /*---------------------------------------------------------------------------- * DEFINITIONS AND MACROS diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c index 74e5234535..42e91b6130 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c @@ -43,7 +43,9 @@ #include #include #include +#include #include + #include "s3utils.h" #include "mct_d_gcc.h" #include "mct_d.h" diff --git a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c index a78a752052..d991002f5b 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c @@ -30,6 +30,8 @@ #include #include #include +#include + #include "mct_d.h" #include "mct_d_gcc.h" diff --git a/src/northbridge/amd/amdmct/wrappers/mcti_d.c b/src/northbridge/amd/amdmct/wrappers/mcti_d.c index 7aaf016d29..b8042fe46d 100644 --- a/src/northbridge/amd/amdmct/wrappers/mcti_d.c +++ b/src/northbridge/amd/amdmct/wrappers/mcti_d.c @@ -19,6 +19,7 @@ #include #include #include +#include #include "mcti.h" diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c index 3549b49234..a2de7f0fb0 100644 --- a/src/northbridge/intel/gm45/gma.c +++ b/src/northbridge/intel/gm45/gma.c @@ -27,6 +27,7 @@ #include #include #include +#include #include "drivers/intel/gma/i915_reg.h" #include "chip.h" diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c index 1b2430f849..607fab7602 100644 --- a/src/northbridge/intel/haswell/gma.c +++ b/src/northbridge/intel/haswell/gma.c @@ -31,6 +31,7 @@ #include #include #include +#include #include "chip.h" #include "haswell.h" diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index 84d9c105d6..f9167dfc97 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include #include #include #include @@ -22,9 +21,11 @@ #include #include #include -#include "i945.h" #include #include +#include + +#include "i945.h" int i945_silicon_revision(void) { diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c index 1d20533a48..54ff47cc64 100644 --- a/src/northbridge/intel/i945/gma.c +++ b/src/northbridge/intel/i945/gma.c @@ -33,6 +33,7 @@ #include #include #include +#include #include "i945.h" #include "chip.h" diff --git a/src/northbridge/intel/nehalem/gma.c b/src/northbridge/intel/nehalem/gma.c index 8c0117f531..087d37e5aa 100644 --- a/src/northbridge/intel/nehalem/gma.c +++ b/src/northbridge/intel/nehalem/gma.c @@ -31,6 +31,7 @@ #include #include #include +#include #include "chip.h" #include "nehalem.h" diff --git a/src/northbridge/intel/nehalem/raminit.c b/src/northbridge/intel/nehalem/raminit.c index 5b6077f5ea..15d6abb67b 100644 --- a/src/northbridge/intel/nehalem/raminit.c +++ b/src/northbridge/intel/nehalem/raminit.c @@ -30,18 +30,18 @@ #include #include #include -#include "raminit.h" -#include "chip.h" #include #include #include #include #include - -#include "nehalem.h" - #include #include +#include + +#include "chip.h" +#include "nehalem.h" +#include "raminit.h" #define NORTHBRIDGE PCI_DEV(0, 0, 0) #define SOUTHBRIDGE PCI_DEV(0, 0x1f, 0) diff --git a/src/northbridge/intel/pineview/early_init.c b/src/northbridge/intel/pineview/early_init.c index 509ab4ee0c..be6a5e27d6 100644 --- a/src/northbridge/intel/pineview/early_init.c +++ b/src/northbridge/intel/pineview/early_init.c @@ -14,7 +14,6 @@ * GNU General Public License for more details. */ -#include #include #include #include @@ -24,6 +23,7 @@ #include #include #include +#include #define LPC PCI_DEV(0, 0x1f, 0) #define D0F0 PCI_DEV(0, 0, 0) diff --git a/src/northbridge/intel/pineview/gma.c b/src/northbridge/intel/pineview/gma.c index 019f7648f0..dd6cb32596 100644 --- a/src/northbridge/intel/pineview/gma.c +++ b/src/northbridge/intel/pineview/gma.c @@ -23,10 +23,7 @@ #include #include #include - #include -#include "chip.h" -#include "pineview.h" #include #include #include @@ -34,6 +31,10 @@ #include #include #include +#include + +#include "chip.h" +#include "pineview.h" #define GTTSIZE (512*1024) diff --git a/src/northbridge/intel/sandybridge/early_init.c b/src/northbridge/intel/sandybridge/early_init.c index 34aec3851b..fd3d34f2de 100644 --- a/src/northbridge/intel/sandybridge/early_init.c +++ b/src/northbridge/intel/sandybridge/early_init.c @@ -14,7 +14,6 @@ * GNU General Public License for more details. */ -#include #include #include #include @@ -22,6 +21,8 @@ #include #include #include +#include + #include "sandybridge.h" static void sandybridge_setup_bars(void) diff --git a/src/northbridge/intel/sandybridge/gma.c b/src/northbridge/intel/sandybridge/gma.c index cb6782e9b7..1005288fee 100644 --- a/src/northbridge/intel/sandybridge/gma.c +++ b/src/northbridge/intel/sandybridge/gma.c @@ -27,6 +27,7 @@ #include #include #include +#include #include "chip.h" #include "sandybridge.h" diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index f67d61f973..c13ae37fbc 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -30,6 +30,7 @@ #include #include #include +#include #include "raminit_native.h" #include "raminit_common.h" diff --git a/src/northbridge/intel/x4x/gma.c b/src/northbridge/intel/x4x/gma.c index c4e8bf1cdd..61731fee3e 100644 --- a/src/northbridge/intel/x4x/gma.c +++ b/src/northbridge/intel/x4x/gma.c @@ -29,6 +29,7 @@ #include #include #include +#include #include "chip.h" #include "drivers/intel/gma/i915_reg.h" diff --git a/src/northbridge/intel/x4x/raminit.c b/src/northbridge/intel/x4x/raminit.c index 7fed1efe26..bd6536ab6f 100644 --- a/src/northbridge/intel/x4x/raminit.c +++ b/src/northbridge/intel/x4x/raminit.c @@ -32,6 +32,7 @@ #include #include #include +#include #include "iomap.h" #include "x4x.h" From ab89edbccf6e614213bbd88f5dbd5c8bf9a5d4c6 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Wed, 15 May 2019 21:10:44 +0200 Subject: [PATCH 248/331] src/southbridge: Add missing 'include ' is supposed to provide and . When is included, and/or is removed. Change-Id: I4d8628e4ce3c7f80da2590b4cad618b290e0d513 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/32809 Tested-by: build bot (Jenkins) Reviewed-by: Lijian Zhao --- src/southbridge/amd/pi/hudson/hudson.c | 4 ++-- src/southbridge/amd/pi/hudson/lpc.c | 2 ++ src/southbridge/amd/sb700/ide.c | 2 ++ src/southbridge/amd/sb700/sata.c | 2 ++ src/southbridge/amd/sb700/usb.c | 2 ++ src/southbridge/intel/bd82x6x/sata.c | 4 +++- src/southbridge/intel/common/smbus.c | 2 ++ src/southbridge/intel/i82801ix/sata.c | 4 +++- src/southbridge/intel/i82801jx/sata.c | 4 +++- src/southbridge/intel/ibexpeak/sata.c | 4 +++- 10 files changed, 24 insertions(+), 6 deletions(-) diff --git a/src/southbridge/amd/pi/hudson/hudson.c b/src/southbridge/amd/pi/hudson/hudson.c index e1ea2ce4b3..a331c57262 100644 --- a/src/southbridge/amd/pi/hudson/hudson.c +++ b/src/southbridge/amd/pi/hudson/hudson.c @@ -14,16 +14,16 @@ */ #include - #include #include #include - #include #include #include #include #include +#include + #include "hudson.h" #include "smbus.h" #include "smi.h" diff --git a/src/southbridge/amd/pi/hudson/lpc.c b/src/southbridge/amd/pi/hudson/lpc.c index abb92f29d2..5354a27822 100644 --- a/src/southbridge/amd/pi/hudson/lpc.c +++ b/src/southbridge/amd/pi/hudson/lpc.c @@ -27,6 +27,8 @@ #include #include #include +#include + #include "hudson.h" #include "pci_devs.h" diff --git a/src/southbridge/amd/sb700/ide.c b/src/southbridge/amd/sb700/ide.c index 673464318c..0b11db3c86 100644 --- a/src/southbridge/amd/sb700/ide.c +++ b/src/southbridge/amd/sb700/ide.c @@ -19,6 +19,8 @@ #include #include #include +#include + #include "sb700.h" static void ide_init(struct device *dev) diff --git a/src/southbridge/amd/sb700/sata.c b/src/southbridge/amd/sb700/sata.c index 39aef639d2..292a7f2c9e 100644 --- a/src/southbridge/amd/sb700/sata.c +++ b/src/southbridge/amd/sb700/sata.c @@ -23,6 +23,8 @@ #include #include #include +#include + #include "sb700.h" static int sata_drive_detect(int portnum, uint16_t iobar) diff --git a/src/southbridge/amd/sb700/usb.c b/src/southbridge/amd/sb700/usb.c index da653112d7..4109e88cc3 100644 --- a/src/southbridge/amd/sb700/usb.c +++ b/src/southbridge/amd/sb700/usb.c @@ -21,6 +21,8 @@ #include #include #include +#include + #include "sb700.h" static struct pci_operations lops_pci = { diff --git a/src/southbridge/intel/bd82x6x/sata.c b/src/southbridge/intel/bd82x6x/sata.c index 91c87bf26e..6a39873e7b 100644 --- a/src/southbridge/intel/bd82x6x/sata.c +++ b/src/southbridge/intel/bd82x6x/sata.c @@ -20,9 +20,11 @@ #include #include #include -#include "pch.h" #include #include +#include + +#include "pch.h" typedef struct southbridge_intel_bd82x6x_config config_t; diff --git a/src/southbridge/intel/common/smbus.c b/src/southbridge/intel/common/smbus.c index 4b08c48f27..af1eb602a0 100644 --- a/src/southbridge/intel/common/smbus.c +++ b/src/southbridge/intel/common/smbus.c @@ -19,6 +19,8 @@ #include #include #include +#include + #include "smbus.h" diff --git a/src/southbridge/intel/i82801ix/sata.c b/src/southbridge/intel/i82801ix/sata.c index 6155c15006..49d2d36b85 100644 --- a/src/southbridge/intel/i82801ix/sata.c +++ b/src/southbridge/intel/i82801ix/sata.c @@ -22,8 +22,10 @@ #include #include #include -#include "i82801ix.h" #include +#include + +#include "i82801ix.h" typedef struct southbridge_intel_i82801ix_config config_t; diff --git a/src/southbridge/intel/i82801jx/sata.c b/src/southbridge/intel/i82801jx/sata.c index 8de2d7427d..ddaa783868 100644 --- a/src/southbridge/intel/i82801jx/sata.c +++ b/src/southbridge/intel/i82801jx/sata.c @@ -22,8 +22,10 @@ #include #include #include -#include "i82801jx.h" #include +#include + +#include "i82801jx.h" typedef struct southbridge_intel_i82801jx_config config_t; diff --git a/src/southbridge/intel/ibexpeak/sata.c b/src/southbridge/intel/ibexpeak/sata.c index 112445bb65..e03f8b5884 100644 --- a/src/southbridge/intel/ibexpeak/sata.c +++ b/src/southbridge/intel/ibexpeak/sata.c @@ -21,9 +21,11 @@ #include #include #include -#include "pch.h" #include #include +#include + +#include "pch.h" typedef struct southbridge_intel_ibexpeak_config config_t; From 27d02d8286aff64115ae593a189c38fdaf3ce769 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Wed, 15 May 2019 21:11:39 +0200 Subject: [PATCH 249/331] src/soc: Add missing 'include ' is supposed to provide and . When is included, and/or is removed. Change-Id: I2db0a647bc657a3626cb5e78f23e9198e290261a Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/32810 Tested-by: build bot (Jenkins) Reviewed-by: Lijian Zhao --- src/soc/amd/common/block/include/amdblocks/psp.h | 2 +- src/soc/amd/stoneyridge/include/soc/northbridge.h | 1 + src/soc/amd/stoneyridge/southbridge.c | 2 +- src/soc/intel/apollolake/graphics.c | 1 + src/soc/intel/baytrail/gfx.c | 1 + src/soc/intel/broadwell/igd.c | 1 + src/soc/intel/cannonlake/graphics.c | 1 + src/soc/intel/icelake/graphics.c | 1 + src/soc/intel/skylake/graphics.c | 1 + src/soc/mediatek/common/pll.c | 1 + src/soc/mediatek/mt8173/ddp.c | 1 + src/soc/mediatek/mt8173/pll.c | 3 +-- src/soc/mediatek/mt8173/rtc.c | 1 + src/soc/nvidia/tegra210/dsi.c | 8 +++++--- src/soc/nvidia/tegra210/include/soc/dma.h | 1 + src/soc/nvidia/tegra210/mipi-phy.c | 3 +-- src/soc/nvidia/tegra210/spi.c | 3 +-- src/soc/qualcomm/ipq806x/include/soc/clock.h | 1 + src/soc/rockchip/common/gpio.c | 1 + src/soc/rockchip/rk3399/include/soc/mipi.h | 1 + src/soc/rockchip/rk3399/mipi.c | 2 +- 21 files changed, 25 insertions(+), 12 deletions(-) diff --git a/src/soc/amd/common/block/include/amdblocks/psp.h b/src/soc/amd/common/block/include/amdblocks/psp.h index 25a564b457..512b0b8c04 100644 --- a/src/soc/amd/common/block/include/amdblocks/psp.h +++ b/src/soc/amd/common/block/include/amdblocks/psp.h @@ -18,7 +18,7 @@ #include #include -#include +#include /* Extra, Special Purpose Registers in the PSP PCI Config Space */ diff --git a/src/soc/amd/stoneyridge/include/soc/northbridge.h b/src/soc/amd/stoneyridge/include/soc/northbridge.h index 563dae09e1..60a6ea22bb 100644 --- a/src/soc/amd/stoneyridge/include/soc/northbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/northbridge.h @@ -18,6 +18,7 @@ #define __PI_STONEYRIDGE_NORTHBRIDGE_H__ #include +#include /* D0F0 - Root Complex */ diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c index bf8787c1fc..84db3dd76c 100644 --- a/src/soc/amd/stoneyridge/southbridge.c +++ b/src/soc/amd/stoneyridge/southbridge.c @@ -14,7 +14,6 @@ */ #include - #include #include #include @@ -36,6 +35,7 @@ #include #include #include +#include /* * Table of devices that need their AOAC registers enabled and waited diff --git a/src/soc/intel/apollolake/graphics.c b/src/soc/intel/apollolake/graphics.c index 51661d0cfc..f5136ec103 100644 --- a/src/soc/intel/apollolake/graphics.c +++ b/src/soc/intel/apollolake/graphics.c @@ -26,6 +26,7 @@ #include #include #include +#include uintptr_t fsp_soc_get_igd_bar(void) { diff --git a/src/soc/intel/baytrail/gfx.c b/src/soc/intel/baytrail/gfx.c index d2cb589db8..2048c13824 100644 --- a/src/soc/intel/baytrail/gfx.c +++ b/src/soc/intel/baytrail/gfx.c @@ -28,6 +28,7 @@ #include #include #include +#include #include "chip.h" diff --git a/src/soc/intel/broadwell/igd.c b/src/soc/intel/broadwell/igd.c index b9b42810fc..9107b23eb9 100644 --- a/src/soc/intel/broadwell/igd.c +++ b/src/soc/intel/broadwell/igd.c @@ -36,6 +36,7 @@ #include #include #include +#include #define GT_RETRY 1000 enum { diff --git a/src/soc/intel/cannonlake/graphics.c b/src/soc/intel/cannonlake/graphics.c index a89dcb31fb..2acfecc5b0 100644 --- a/src/soc/intel/cannonlake/graphics.c +++ b/src/soc/intel/cannonlake/graphics.c @@ -23,6 +23,7 @@ #include #include #include +#include uintptr_t fsp_soc_get_igd_bar(void) { diff --git a/src/soc/intel/icelake/graphics.c b/src/soc/intel/icelake/graphics.c index 35fe8b6236..0fbddf06e9 100644 --- a/src/soc/intel/icelake/graphics.c +++ b/src/soc/intel/icelake/graphics.c @@ -23,6 +23,7 @@ #include #include #include +#include uintptr_t fsp_soc_get_igd_bar(void) { diff --git a/src/soc/intel/skylake/graphics.c b/src/soc/intel/skylake/graphics.c index 07ee67ab88..f563c11302 100644 --- a/src/soc/intel/skylake/graphics.c +++ b/src/soc/intel/skylake/graphics.c @@ -25,6 +25,7 @@ #include #include #include +#include uintptr_t fsp_soc_get_igd_bar(void) { diff --git a/src/soc/mediatek/common/pll.c b/src/soc/mediatek/common/pll.c index 0968d2f59f..a63fe8927b 100644 --- a/src/soc/mediatek/common/pll.c +++ b/src/soc/mediatek/common/pll.c @@ -16,6 +16,7 @@ #include #include #include +#include #define GENMASK(h, l) (BIT(h + 1) - BIT(l)) diff --git a/src/soc/mediatek/mt8173/ddp.c b/src/soc/mediatek/mt8173/ddp.c index 0b78c3ea64..f8896d391a 100644 --- a/src/soc/mediatek/mt8173/ddp.c +++ b/src/soc/mediatek/mt8173/ddp.c @@ -19,6 +19,7 @@ #include #include #include +#include #define RDMA_FIFO_PSEUDO_SIZE(bytes) (((bytes) / 16) << 16) #define RDMA_OUTPUT_VALID_FIFO_THRESHOLD(bytes) ((bytes) / 16) diff --git a/src/soc/mediatek/mt8173/pll.c b/src/soc/mediatek/mt8173/pll.c index 7eb12b1282..e1c1bff6d5 100644 --- a/src/soc/mediatek/mt8173/pll.c +++ b/src/soc/mediatek/mt8173/pll.c @@ -16,11 +16,10 @@ #include #include #include -#include - #include #include #include +#include enum mux_id { TOP_AXI_SEL, diff --git a/src/soc/mediatek/mt8173/rtc.c b/src/soc/mediatek/mt8173/rtc.c index 79e5732c2f..9ad4caa89c 100644 --- a/src/soc/mediatek/mt8173/rtc.c +++ b/src/soc/mediatek/mt8173/rtc.c @@ -18,6 +18,7 @@ #include #include #include +#include #define RTC_GPIO_USER_MASK ((1 << 13) - (1 << 8)) diff --git a/src/soc/nvidia/tegra210/dsi.c b/src/soc/nvidia/tegra210/dsi.c index 76054f0156..ae20d44d16 100644 --- a/src/soc/nvidia/tegra210/dsi.c +++ b/src/soc/nvidia/tegra210/dsi.c @@ -12,9 +12,10 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ + +#include #include #include -#include #include #include #include @@ -24,14 +25,15 @@ #include #include #include -#include "chip.h" #include #include #include #include #include +#include + +#include "chip.h" #include "jdi_25x18_display/panel-jdi-lpm102a188a.h" -#include struct tegra_mipi_device mipi_device_data[NUM_DSI]; diff --git a/src/soc/nvidia/tegra210/include/soc/dma.h b/src/soc/nvidia/tegra210/include/soc/dma.h index 1093479d5f..3cb94ce8d3 100644 --- a/src/soc/nvidia/tegra210/include/soc/dma.h +++ b/src/soc/nvidia/tegra210/include/soc/dma.h @@ -19,6 +19,7 @@ #include #include +#include /* * The DMA engine operates on 4 bytes at a time, so make sure any data diff --git a/src/soc/nvidia/tegra210/mipi-phy.c b/src/soc/nvidia/tegra210/mipi-phy.c index 4e6bdf0242..4e56730d3b 100644 --- a/src/soc/nvidia/tegra210/mipi-phy.c +++ b/src/soc/nvidia/tegra210/mipi-phy.c @@ -13,9 +13,7 @@ * GNU General Public License for more details. */ -#include #include - #include #include #include @@ -25,6 +23,7 @@ #include #include #include +#include int mipi_dphy_set_timing(struct tegra_dsi *dsi) { diff --git a/src/soc/nvidia/tegra210/spi.c b/src/soc/nvidia/tegra210/spi.c index edb052df6b..9310e0cc09 100644 --- a/src/soc/nvidia/tegra210/spi.c +++ b/src/soc/nvidia/tegra210/spi.c @@ -26,9 +26,8 @@ #include #include #include -#include -#include #include +#include #if defined(CONFIG_DEBUG_SPI) && CONFIG_DEBUG_SPI # define DEBUG_SPI(x,...) printk(BIOS_DEBUG, "TEGRA_SPI: " x) diff --git a/src/soc/qualcomm/ipq806x/include/soc/clock.h b/src/soc/qualcomm/ipq806x/include/soc/clock.h index 482deadfe7..7ecc1eee16 100644 --- a/src/soc/qualcomm/ipq806x/include/soc/clock.h +++ b/src/soc/qualcomm/ipq806x/include/soc/clock.h @@ -34,6 +34,7 @@ #define __IPQ860X_CLOCK_H_ #include +#include /* UART clock @ 7.3728 MHz */ #define UART_DM_CLK_RX_TX_BIT_RATE 0xCC diff --git a/src/soc/rockchip/common/gpio.c b/src/soc/rockchip/common/gpio.c index fa0990b10b..3d7e1614e0 100644 --- a/src/soc/rockchip/common/gpio.c +++ b/src/soc/rockchip/common/gpio.c @@ -20,6 +20,7 @@ #include #include #include +#include static void gpio_set_dir(gpio_t gpio, enum gpio_dir dir) { diff --git a/src/soc/rockchip/rk3399/include/soc/mipi.h b/src/soc/rockchip/rk3399/include/soc/mipi.h index f304d8fcd0..43ab7b914f 100644 --- a/src/soc/rockchip/rk3399/include/soc/mipi.h +++ b/src/soc/rockchip/rk3399/include/soc/mipi.h @@ -17,6 +17,7 @@ #define __RK_MIPI_H #include +#include struct rk_mipi_regs { u32 dsi_version; diff --git a/src/soc/rockchip/rk3399/mipi.c b/src/soc/rockchip/rk3399/mipi.c index cc16563c43..1f3f02cbee 100644 --- a/src/soc/rockchip/rk3399/mipi.c +++ b/src/soc/rockchip/rk3399/mipi.c @@ -20,13 +20,13 @@ #include #include #include -#include #include #include #include #include #include #include +#include #include static struct rk_mipi_dsi rk_mipi[2] = { From e39db681dfd7c4127f1ac0e360e0930e72ef3ee3 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Wed, 15 May 2019 21:12:31 +0200 Subject: [PATCH 250/331] src/mainboard: Add missing 'include ' is supposed to provide and . So when is included, and/or is removed. Change-Id: I3b1a395cfe8b710fb6b468e68f4c92e063794568 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/32811 Tested-by: build bot (Jenkins) Reviewed-by: Lijian Zhao --- src/mainboard/asus/kcma-d8/romstage.c | 2 +- src/mainboard/asus/kgpe-d16/romstage.c | 2 +- src/mainboard/cubietech/cubieboard/romstage.c | 2 +- src/mainboard/lenovo/t430s/variants/t430s/romstage.c | 1 + src/mainboard/siemens/mc_apl1/mainboard.c | 1 + src/mainboard/siemens/mc_apl1/variants/mc_apl1/mainboard.c | 1 + src/mainboard/siemens/mc_apl1/variants/mc_apl1/ptn3460.c | 1 + src/mainboard/siemens/mc_apl1/variants/mc_apl2/mainboard.c | 1 + src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c | 1 + src/mainboard/siemens/mc_apl1/variants/mc_apl4/ptn3460.c | 1 + src/mainboard/siemens/mc_apl1/variants/mc_apl5/mainboard.c | 1 + src/mainboard/siemens/mc_apl1/variants/mc_apl5/ptn3460.c | 1 + src/mainboard/siemens/mc_tcu3/ptn3460.c | 1 + 13 files changed, 13 insertions(+), 3 deletions(-) diff --git a/src/mainboard/asus/kcma-d8/romstage.c b/src/mainboard/asus/kcma-d8/romstage.c index 5d43a54272..6c40627823 100644 --- a/src/mainboard/asus/kcma-d8/romstage.c +++ b/src/mainboard/asus/kcma-d8/romstage.c @@ -17,7 +17,6 @@ * GNU General Public License for more details. */ -#include #include #include #include @@ -44,6 +43,7 @@ #include #include #include +#include #include "cpu/amd/quadcore/quadcore.c" diff --git a/src/mainboard/asus/kgpe-d16/romstage.c b/src/mainboard/asus/kgpe-d16/romstage.c index f7d30bda98..d017b0616a 100644 --- a/src/mainboard/asus/kgpe-d16/romstage.c +++ b/src/mainboard/asus/kgpe-d16/romstage.c @@ -17,7 +17,6 @@ * GNU General Public License for more details. */ -#include #include #include #include @@ -45,6 +44,7 @@ #include #include #include +#include #include "cpu/amd/quadcore/quadcore.c" diff --git a/src/mainboard/cubietech/cubieboard/romstage.c b/src/mainboard/cubietech/cubieboard/romstage.c index 21fa9b535f..bfb5e029d6 100644 --- a/src/mainboard/cubietech/cubieboard/romstage.c +++ b/src/mainboard/cubietech/cubieboard/romstage.c @@ -31,7 +31,7 @@ #include #include #include - +#include #define GPB_TWI0_FUNC 2 #define GPB_TWI0_PINS ((1 << 0) | (1 << 1)) diff --git a/src/mainboard/lenovo/t430s/variants/t430s/romstage.c b/src/mainboard/lenovo/t430s/variants/t430s/romstage.c index e461681f19..5bc7b80961 100644 --- a/src/mainboard/lenovo/t430s/variants/t430s/romstage.c +++ b/src/mainboard/lenovo/t430s/variants/t430s/romstage.c @@ -22,6 +22,7 @@ #include #include #include +#include const struct southbridge_usb_port mainboard_usb_ports[] = { { 1, 0, 0 }, /* P0:, OC 0 */ diff --git a/src/mainboard/siemens/mc_apl1/mainboard.c b/src/mainboard/siemens/mc_apl1/mainboard.c index b39b6817f6..c931e1008a 100644 --- a/src/mainboard/siemens/mc_apl1/mainboard.c +++ b/src/mainboard/siemens/mc_apl1/mainboard.c @@ -28,6 +28,7 @@ #include #include #include +#include #define MAX_PATH_DEPTH 12 #define MAX_NUM_MAPPINGS 10 diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl1/mainboard.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl1/mainboard.c index 6d22fd9826..df6fc21bde 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl1/mainboard.c +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl1/mainboard.c @@ -25,6 +25,7 @@ #include #include #include +#include #include #define TX_DWORD3 0xa8c diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl1/ptn3460.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl1/ptn3460.c index 060a35c0a8..c0770f3124 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl1/ptn3460.c +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl1/ptn3460.c @@ -16,6 +16,7 @@ #include #include #include +#include #include /** diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/mainboard.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/mainboard.c index f52091bced..7890ee0211 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/mainboard.c +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/mainboard.c @@ -24,6 +24,7 @@ #include #include #include +#include #define SD_CAP_BYP 0x810 #define SD_CAP_BYP_EN 0x5A diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c index 3e2e7f0910..6a883c6a26 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c @@ -28,6 +28,7 @@ #include #include #include +#include #define TX_DWORD3 0xa8c diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/ptn3460.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/ptn3460.c index 73d901935a..47763ae5d8 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/ptn3460.c +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/ptn3460.c @@ -16,6 +16,7 @@ #include #include #include +#include #include /* diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/mainboard.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/mainboard.c index 9462497aa6..e1b56bda13 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/mainboard.c +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/mainboard.c @@ -26,6 +26,7 @@ #include #include #include +#include #include #define TX_DWORD3 0xa8c diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/ptn3460.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/ptn3460.c index 060a35c0a8..c0770f3124 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/ptn3460.c +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/ptn3460.c @@ -16,6 +16,7 @@ #include #include #include +#include #include /** diff --git a/src/mainboard/siemens/mc_tcu3/ptn3460.c b/src/mainboard/siemens/mc_tcu3/ptn3460.c index 9acc60a345..414baeb089 100644 --- a/src/mainboard/siemens/mc_tcu3/ptn3460.c +++ b/src/mainboard/siemens/mc_tcu3/ptn3460.c @@ -17,6 +17,7 @@ #include #include #include +#include #include "soc/i2c.h" #include "ptn3460.h" From a95a6bf646aee936d841f458812f2ced3a29e6f7 Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Tue, 16 Jan 2018 18:59:54 +0100 Subject: [PATCH 251/331] libpayload/drivers/i8402/kbd: Fix qemu Reset keyboard controller to fix qemu make scan codes. Change-Id: I5f8ad2d4be4b9e89d9af3a62726259e77f0403c1 Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/c/coreboot/+/23584 Reviewed-by: Patrick Georgi Tested-by: build bot (Jenkins) --- payloads/libpayload/drivers/i8042/keyboard.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/payloads/libpayload/drivers/i8042/keyboard.c b/payloads/libpayload/drivers/i8042/keyboard.c index fea9e718dd..12255fb7f8 100644 --- a/payloads/libpayload/drivers/i8042/keyboard.c +++ b/payloads/libpayload/drivers/i8042/keyboard.c @@ -333,6 +333,14 @@ void keyboard_init(void) if (!ret && !CONFIG(LP_PC_KEYBOARD_IGNORE_INIT_FAILURE)) return; + /* + * Set default parameters. + * Fix for broken QEMU ps/2 make scancodes. + */ + ret = keyboard_cmd(0xf6); + if (!ret) + return; + /* Enable scanning */ ret = keyboard_cmd(I8042_KBCMD_EN); if (!ret && !CONFIG(LP_PC_KEYBOARD_IGNORE_INIT_FAILURE)) From 9b5e8c171868f3c559eb0f51a5b6f20cf5d0b7f9 Mon Sep 17 00:00:00 2001 From: Damien Zammit Date: Sat, 2 Sep 2017 18:28:29 +1000 Subject: [PATCH 252/331] xcompile: Remove --rtlib switch from clang CFLAGS Fix the following error from clang invoking gcc linker with wrong arg: i386-elf-gcc: error: unrecognized command line option '--rtlib=libgcc'; did you mean '-static-libgcc'? clang-4.0: error: linker (via gcc) command failed with exit code 1 Just remove --rtlib switch from CFLAGS relating to clang Change-Id: Ife7ef6b6b47a04598fc67b40751bc59eed93b4af Signed-off-by: Damien Zammit Reviewed-on: https://review.coreboot.org/c/coreboot/+/21354 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth --- util/xcompile/xcompile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/util/xcompile/xcompile b/util/xcompile/xcompile index 40356d93d9..7ab1cb7af8 100755 --- a/util/xcompile/xcompile +++ b/util/xcompile/xcompile @@ -453,7 +453,7 @@ test_architecture() { # but that's more of a clang limitation. Let's be optimistic # that this will change in the future. CLANG="${clang_prefix}clang" - CFLAGS_CLANG="-target ${clang_arch}-${TABI} --rtlib=${CLANG_RUNTIME} $CFLAGS_CLANG -ccc-gcc-name ${GCC}" + CFLAGS_CLANG="-target ${clang_arch}-${TABI} $CFLAGS_CLANG -ccc-gcc-name ${GCC}" fi } From 2b99a01e0d28ae3c755480e12beb130e8b1550ac Mon Sep 17 00:00:00 2001 From: Patrick Georgi Date: Wed, 29 May 2019 22:52:23 +0200 Subject: [PATCH 253/331] soc/rockchip/rk3288: Disable bootblock console Bootblock space is tight on this SoC and recent changes increased it ever so slightly to make this a problem. Since the bootblock is well-tested, we can get by without console. Change-Id: I7496a3e313b2c6ee6fb3c4671eac64376d84e0dc Signed-off-by: Patrick Georgi Reviewed-on: https://review.coreboot.org/c/coreboot/+/33068 Reviewed-by: Angel Pons Reviewed-by: Nico Huber Tested-by: build bot (Jenkins) --- src/soc/rockchip/rk3288/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/src/soc/rockchip/rk3288/Kconfig b/src/soc/rockchip/rk3288/Kconfig index 38d87524b7..f845f07514 100644 --- a/src/soc/rockchip/rk3288/Kconfig +++ b/src/soc/rockchip/rk3288/Kconfig @@ -30,6 +30,7 @@ config SOC_ROCKCHIP_RK3288 select MAINBOARD_HAS_NATIVE_VGA_INIT select MAINBOARD_FORCE_NATIVE_VGA_INIT select HAVE_LINEAR_FRAMEBUFFER + select NO_BOOTBLOCK_CONSOLE if SOC_ROCKCHIP_RK3288 From 10490b98e2c8b7b0c6c275b6b809d48697f6ee2f Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Thu, 21 Mar 2019 23:17:06 +0100 Subject: [PATCH 254/331] mb/roda/rk9: Document flash header Change-Id: I5bd131635340ffa0c6b8979fc8e263fc5f09fdc5 Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/c/coreboot/+/32025 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph --- Documentation/mainboard/index.md | 4 ++++ .../mainboard/roda/rk9/flash_header.md | 23 +++++++++++++++++++ 2 files changed, 27 insertions(+) create mode 100644 Documentation/mainboard/roda/rk9/flash_header.md diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md index 7e0dab2f4c..fb4f5022aa 100644 --- a/Documentation/mainboard/index.md +++ b/Documentation/mainboard/index.md @@ -81,6 +81,10 @@ The boards in this section are not real mainboards, but emulators. - [MS-7707](msi/ms7707/ms7707.md) +## Roda + +- [RK9 Flash Header](roda/rk9/flash_header.md) + ## SiFive - [SiFive HiFive Unleashed](sifive/hifive-unleashed.md) diff --git a/Documentation/mainboard/roda/rk9/flash_header.md b/Documentation/mainboard/roda/rk9/flash_header.md new file mode 100644 index 0000000000..c2978cbe68 --- /dev/null +++ b/Documentation/mainboard/roda/rk9/flash_header.md @@ -0,0 +1,23 @@ +Roda RK9 Flash Header +===================== + +There is a 5x2 pin, 1.27mm pitch header *J1* south of the BIOS flash. It +follows the pinout of the Dediprog adaptor board: + + +------+ + | 1 2 | 1: HOLD 2 2: CS 2 + | 3 4 | 3: CS 1 4: VCC + | 5 6 | 5: MISO 6: HOLD 1 + | 7 8 | 7: 8: CLK + | 9 10 | 9: GND 10: MOSI + +------+ + +Pins 3 to 10 directly map to the regular SPI flash pinout. + +There is also a *JP17* around. Ideally, it should be closed during +programming (isolates the SPI bus from the southbridge): + + +---+ + | 1 | 1: SF100-I/O3 + | 2 | 2: GND + +---+ From d64f8899728edfb645dde10a1f6f1fb46df13a15 Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Thu, 30 May 2019 11:48:02 +0200 Subject: [PATCH 255/331] mb/lenovo/*20*: Remove default FMAP These boards don't need a default FMAP. Moreover, having a default FMAP disables automatic integration of optional regions like `CONSOLE`. Also, these files contain an error: `COREBOOT` isn't placed at the top of the image. Resulting in default builds without a reset vector ;) Change-Id: If6331e19955034c02828e88902a5934c34d3e784 Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/c/coreboot/+/33110 Reviewed-by: Patrick Rudolph Reviewed-by: Arthur Heymans Tested-by: build bot (Jenkins) --- src/mainboard/lenovo/t420/Kconfig | 1 - src/mainboard/lenovo/t420/board.fmd | 16 ---------------- src/mainboard/lenovo/t420s/Kconfig | 1 - src/mainboard/lenovo/t420s/board.fmd | 16 ---------------- src/mainboard/lenovo/t520/Kconfig | 1 - src/mainboard/lenovo/t520/board.fmd | 16 ---------------- src/mainboard/lenovo/x220/Kconfig | 1 - src/mainboard/lenovo/x220/board.fmd | 16 ---------------- 8 files changed, 68 deletions(-) delete mode 100644 src/mainboard/lenovo/t420/board.fmd delete mode 100644 src/mainboard/lenovo/t420s/board.fmd delete mode 100644 src/mainboard/lenovo/t520/board.fmd delete mode 100644 src/mainboard/lenovo/x220/board.fmd diff --git a/src/mainboard/lenovo/t420/Kconfig b/src/mainboard/lenovo/t420/Kconfig index 3d3b56ae22..02bcc4f4a4 100644 --- a/src/mainboard/lenovo/t420/Kconfig +++ b/src/mainboard/lenovo/t420/Kconfig @@ -46,7 +46,6 @@ config VBOOT_VBNV_OFFSET config FMDFILE string default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/vboot-rwa.fmd" if VBOOT - default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/board.fmd" config MAINBOARD_DIR string diff --git a/src/mainboard/lenovo/t420/board.fmd b/src/mainboard/lenovo/t420/board.fmd deleted file mode 100644 index 04cf827a87..0000000000 --- a/src/mainboard/lenovo/t420/board.fmd +++ /dev/null @@ -1,16 +0,0 @@ -FLASH@0xff800000 0x800000 { - SI_ALL@0x0 0x500000 { - SI_DESC@0x0 0x1000 - SI_GBE@0x1000 0x2000 - SI_ME@0x3000 0x4ed000 - } - SI_BIOS@0x500000 0x300000 { - RW_MRC_CACHE@0 0x10000 - SMMSTORE(PRESERVE)@0x10000 0x40000 - - WP_RO@0x50000 0x2a0000 { - FMAP@0x0 0x800 - COREBOOT(CBFS)@0x1000 0x29f000 - } - } -} diff --git a/src/mainboard/lenovo/t420s/Kconfig b/src/mainboard/lenovo/t420s/Kconfig index 1383d4166c..60735b049d 100644 --- a/src/mainboard/lenovo/t420s/Kconfig +++ b/src/mainboard/lenovo/t420s/Kconfig @@ -45,7 +45,6 @@ config VBOOT_VBNV_OFFSET config FMDFILE string default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/vboot-rwa.fmd" if VBOOT - default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/board.fmd" config MAINBOARD_DIR string diff --git a/src/mainboard/lenovo/t420s/board.fmd b/src/mainboard/lenovo/t420s/board.fmd deleted file mode 100644 index 04cf827a87..0000000000 --- a/src/mainboard/lenovo/t420s/board.fmd +++ /dev/null @@ -1,16 +0,0 @@ -FLASH@0xff800000 0x800000 { - SI_ALL@0x0 0x500000 { - SI_DESC@0x0 0x1000 - SI_GBE@0x1000 0x2000 - SI_ME@0x3000 0x4ed000 - } - SI_BIOS@0x500000 0x300000 { - RW_MRC_CACHE@0 0x10000 - SMMSTORE(PRESERVE)@0x10000 0x40000 - - WP_RO@0x50000 0x2a0000 { - FMAP@0x0 0x800 - COREBOOT(CBFS)@0x1000 0x29f000 - } - } -} diff --git a/src/mainboard/lenovo/t520/Kconfig b/src/mainboard/lenovo/t520/Kconfig index ba17e8092b..e847f8e39d 100644 --- a/src/mainboard/lenovo/t520/Kconfig +++ b/src/mainboard/lenovo/t520/Kconfig @@ -58,7 +58,6 @@ config DEVICETREE config FMDFILE string default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/vboot-rwa.fmd" if VBOOT - default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/board.fmd" config MAINBOARD_PART_NUMBER string diff --git a/src/mainboard/lenovo/t520/board.fmd b/src/mainboard/lenovo/t520/board.fmd deleted file mode 100644 index 04cf827a87..0000000000 --- a/src/mainboard/lenovo/t520/board.fmd +++ /dev/null @@ -1,16 +0,0 @@ -FLASH@0xff800000 0x800000 { - SI_ALL@0x0 0x500000 { - SI_DESC@0x0 0x1000 - SI_GBE@0x1000 0x2000 - SI_ME@0x3000 0x4ed000 - } - SI_BIOS@0x500000 0x300000 { - RW_MRC_CACHE@0 0x10000 - SMMSTORE(PRESERVE)@0x10000 0x40000 - - WP_RO@0x50000 0x2a0000 { - FMAP@0x0 0x800 - COREBOOT(CBFS)@0x1000 0x29f000 - } - } -} diff --git a/src/mainboard/lenovo/x220/Kconfig b/src/mainboard/lenovo/x220/Kconfig index 358cf8ec39..c80c2520b2 100644 --- a/src/mainboard/lenovo/x220/Kconfig +++ b/src/mainboard/lenovo/x220/Kconfig @@ -53,7 +53,6 @@ config VARIANT_DIR config FMDFILE string default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/vboot-rwa.fmd" if VBOOT - default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/board.fmd" config MAINBOARD_PART_NUMBER string diff --git a/src/mainboard/lenovo/x220/board.fmd b/src/mainboard/lenovo/x220/board.fmd deleted file mode 100644 index 04cf827a87..0000000000 --- a/src/mainboard/lenovo/x220/board.fmd +++ /dev/null @@ -1,16 +0,0 @@ -FLASH@0xff800000 0x800000 { - SI_ALL@0x0 0x500000 { - SI_DESC@0x0 0x1000 - SI_GBE@0x1000 0x2000 - SI_ME@0x3000 0x4ed000 - } - SI_BIOS@0x500000 0x300000 { - RW_MRC_CACHE@0 0x10000 - SMMSTORE(PRESERVE)@0x10000 0x40000 - - WP_RO@0x50000 0x2a0000 { - FMAP@0x0 0x800 - COREBOOT(CBFS)@0x1000 0x29f000 - } - } -} From 695da71e615e9c946df64b79795a8d73228fb629 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Thu, 30 May 2019 09:56:35 +0530 Subject: [PATCH 256/331] src/vendorcode/amd/pi: Fix CONFIG() check issue in rules.h MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This patch fixes problem of adding CONFIG() check inside rules.h. Change-Id: Ifb6842d0efef3521642c5c399fdf2876f71b167a Signed-off-by: Subrata Banik Signed-off-by: Ronald G. Minnich Reviewed-on: https://review.coreboot.org/c/coreboot/+/33105 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi Reviewed-by: Kyösti Mälkki --- src/vendorcode/amd/pi/00670F00/Makefile.inc | 2 +- src/vendorcode/amd/pi/Makefile.inc | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/vendorcode/amd/pi/00670F00/Makefile.inc b/src/vendorcode/amd/pi/00670F00/Makefile.inc index 0e6f2afd1c..790955a1d0 100644 --- a/src/vendorcode/amd/pi/00670F00/Makefile.inc +++ b/src/vendorcode/amd/pi/00670F00/Makefile.inc @@ -77,8 +77,8 @@ $(call src-to-obj,libagesa,$1): $(agesa_src_path)/$(notdir $1) $(obj)/config.h $ @printf " CC $$(subst $(obj)/,,$$(@))\n" $(CC_libagesa) -c -MMD $(CFLAGS_libagesa) $(AGESA_CFLAGS) \ $(AGESA_INC) \ - -include $(src)/include/rules.h \ -include $(src)/include/kconfig.h \ + -include $(src)/include/rules.h \ -include $(src)/commonlib/include/commonlib/compiler.h \ -o $$@ \ $(agesa_src_path)/$(notdir $1) diff --git a/src/vendorcode/amd/pi/Makefile.inc b/src/vendorcode/amd/pi/Makefile.inc index 4c8db6ab50..4e8787bed2 100644 --- a/src/vendorcode/amd/pi/Makefile.inc +++ b/src/vendorcode/amd/pi/Makefile.inc @@ -100,8 +100,8 @@ $(call src-to-obj,libagesa,$1): $(agesa_src_path)/$(notdir $1) $(obj)/config.h $ @printf " CC $$(subst $(obj)/,,$$(@))\n" $(CC_libagesa) -c -MMD $(CFLAGS_libagesa) $(AGESA_CFLAGS) \ $(AGESA_INC) \ - -include $(src)/include/rules.h \ -include $(src)/include/kconfig.h \ + -include $(src)/include/rules.h \ -include $(src)/commonlib/include/commonlib/compiler.h \ -o $$@ \ $(agesa_src_path)/$(notdir $1) From a1d0928b0014def7481bd5ed4ede739a3aac42ba Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Wed, 29 May 2019 15:48:10 -0700 Subject: [PATCH 257/331] soc/intel/common/block/gpio: Fix the mask for gpio_pm_configure gpio_pm_configure clears out all the bits related to PM configuration in MISCCFG register and sets only the bits requested by mainboard. The mask as it is set currently results in preserving all PM bits instead of clearing them. This change updates the mask to ensure that the PM bits are cleared before setting the ones requested by mainboard. Change-Id: I5b8c04952775dc1e94fa229328be2f3c1102a468 Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/c/coreboot/+/33099 Tested-by: build bot (Jenkins) Reviewed-by: Subrata Banik Reviewed-by: Paul Fagerburg Reviewed-by: Tim Wawrzynczak --- src/soc/intel/common/block/gpio/gpio.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/intel/common/block/gpio/gpio.c b/src/soc/intel/common/block/gpio/gpio.c index d37601ce3b..7ebf05a220 100644 --- a/src/soc/intel/common/block/gpio/gpio.c +++ b/src/soc/intel/common/block/gpio/gpio.c @@ -615,7 +615,7 @@ void gpio_pm_configure(const uint8_t *misccfg_pm_values, size_t num) { int i; size_t gpio_communities; - uint8_t misccfg_pm_mask = MISCCFG_ENABLE_GPIO_PM_CONFIG; + const uint8_t misccfg_pm_mask = ~MISCCFG_ENABLE_GPIO_PM_CONFIG; const struct pad_community *comm; comm = soc_gpio_get_community(&gpio_communities); From 7fa3d5673c5d9837d55b6de69419a6871eee8438 Mon Sep 17 00:00:00 2001 From: Paul Fagerburg Date: Tue, 21 May 2019 14:54:26 -0600 Subject: [PATCH 258/331] mb/google/hatch: Create kindred variant Create the Kindred variant of Hatch by taking a copy of the Hatch files as placeholders. Kindred-specific changes will happen in future CLs. BUG=b:133181366 BRANCH=NONE TEST=util/abuild/abuild -p none -t google/hatch -x -a make sure the build includes GOOGLE_KINDRED Change-Id: I09ad3da0505d599fc3797d7fa24b4dc170dcd18b Signed-off-by: Paul Fagerburg Reviewed-on: https://review.coreboot.org/c/coreboot/+/32936 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/mainboard/google/hatch/Kconfig | 3 + src/mainboard/google/hatch/Kconfig.name | 6 + .../hatch/variants/kindred/Makefile.inc | 20 +++ .../kindred/include/variant/acpi/dptf.asl | 16 ++ .../variants/kindred/include/variant/ec.h | 21 +++ .../variants/kindred/include/variant/gpio.h | 21 +++ .../hatch/variants/kindred/overridetree.cb | 158 ++++++++++++++++++ 7 files changed, 245 insertions(+) create mode 100644 src/mainboard/google/hatch/variants/kindred/Makefile.inc create mode 100644 src/mainboard/google/hatch/variants/kindred/include/variant/acpi/dptf.asl create mode 100644 src/mainboard/google/hatch/variants/kindred/include/variant/ec.h create mode 100644 src/mainboard/google/hatch/variants/kindred/include/variant/gpio.h create mode 100644 src/mainboard/google/hatch/variants/kindred/overridetree.cb diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig index 09f792128c..e3927c0c25 100644 --- a/src/mainboard/google/hatch/Kconfig +++ b/src/mainboard/google/hatch/Kconfig @@ -65,6 +65,7 @@ config GBB_HWID default "HATCH TEST 1823" if BOARD_GOOGLE_HATCH default "HATCH_WHL TEST 2374" if BOARD_GOOGLE_HATCH_WHL default "KOHAKU TEST 1953" if BOARD_GOOGLE_KOHAKU + default "KINDRED TEST 2636" if BOARD_GOOGLE_KINDRED config MAINBOARD_DIR string @@ -79,6 +80,7 @@ config MAINBOARD_PART_NUMBER default "Hatch" if BOARD_GOOGLE_HATCH default "Hatch_whl" if BOARD_GOOGLE_HATCH_WHL default "Kohaku" if BOARD_GOOGLE_KOHAKU + default "Kindred" if BOARD_GOOGLE_KINDRED config MAINBOARD_VENDOR string @@ -101,6 +103,7 @@ config VARIANT_DIR default "hatch" if BOARD_GOOGLE_HATCH default "hatch_whl" if BOARD_GOOGLE_HATCH_WHL default "kohaku" if BOARD_GOOGLE_KOHAKU + default "kindred" if BOARD_GOOGLE_KINDRED config VBOOT select HAS_RECOVERY_MRC_CACHE diff --git a/src/mainboard/google/hatch/Kconfig.name b/src/mainboard/google/hatch/Kconfig.name index eb8e61274a..43fd4bed9b 100644 --- a/src/mainboard/google/hatch/Kconfig.name +++ b/src/mainboard/google/hatch/Kconfig.name @@ -17,3 +17,9 @@ config BOARD_GOOGLE_KOHAKU select BOARD_GOOGLE_BASEBOARD_HATCH select BOARD_ROMSIZE_KB_16384 select SOC_INTEL_COMETLAKE + +config BOARD_GOOGLE_KINDRED + bool "-> Kindred" + select BOARD_GOOGLE_BASEBOARD_HATCH + select BOARD_ROMSIZE_KB_16384 + select SOC_INTEL_COMETLAKE diff --git a/src/mainboard/google/hatch/variants/kindred/Makefile.inc b/src/mainboard/google/hatch/variants/kindred/Makefile.inc new file mode 100644 index 0000000000..8173ca4389 --- /dev/null +++ b/src/mainboard/google/hatch/variants/kindred/Makefile.inc @@ -0,0 +1,20 @@ +## This file is part of the coreboot project. +## +## Copyright 2019 Google LLC +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +SPD_SOURCES = 4G_2400 # 0b000 +SPD_SOURCES += empty_ddr4 # 0b001 +SPD_SOURCES += 8G_2400 # 0b010 +SPD_SOURCES += 8G_2666 # 0b011 +SPD_SOURCES += 16G_2400 # 0b100 +SPD_SOURCES += 16G_2666 # 0b101 diff --git a/src/mainboard/google/hatch/variants/kindred/include/variant/acpi/dptf.asl b/src/mainboard/google/hatch/variants/kindred/include/variant/acpi/dptf.asl new file mode 100644 index 0000000000..f1f09438fa --- /dev/null +++ b/src/mainboard/google/hatch/variants/kindred/include/variant/acpi/dptf.asl @@ -0,0 +1,16 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include diff --git a/src/mainboard/google/hatch/variants/kindred/include/variant/ec.h b/src/mainboard/google/hatch/variants/kindred/include/variant/ec.h new file mode 100644 index 0000000000..768987d225 --- /dev/null +++ b/src/mainboard/google/hatch/variants/kindred/include/variant/ec.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef VARIANT_EC_H +#define VARIANT_EC_H + +#include + +#endif diff --git a/src/mainboard/google/hatch/variants/kindred/include/variant/gpio.h b/src/mainboard/google/hatch/variants/kindred/include/variant/gpio.h new file mode 100644 index 0000000000..d99e2bbd65 --- /dev/null +++ b/src/mainboard/google/hatch/variants/kindred/include/variant/gpio.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include + +#endif diff --git a/src/mainboard/google/hatch/variants/kindred/overridetree.cb b/src/mainboard/google/hatch/variants/kindred/overridetree.cb new file mode 100644 index 0000000000..562bb8b229 --- /dev/null +++ b/src/mainboard/google/hatch/variants/kindred/overridetree.cb @@ -0,0 +1,158 @@ +chip soc/intel/cannonlake + + register "SerialIoDevMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoPci, + [PchSerialIoIndexI2C2] = PchSerialIoPci, + [PchSerialIoIndexI2C3] = PchSerialIoPci, + [PchSerialIoIndexI2C4] = PchSerialIoPci, + [PchSerialIoIndexI2C5] = PchSerialIoPci, + [PchSerialIoIndexSPI0] = PchSerialIoPci, + [PchSerialIoIndexSPI1] = PchSerialIoPci, + [PchSerialIoIndexSPI2] = PchSerialIoDisabled, + [PchSerialIoIndexUART0] = PchSerialIoSkipInit, + [PchSerialIoIndexUART1] = PchSerialIoDisabled, + [PchSerialIoIndexUART2] = PchSerialIoDisabled, + }" + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| GSPI0 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| | before memory is up | + #| GSPI1 | FP MCU | + #| I2C0 | Touchpad | + #| I2C1 | Touch screen | + #| I2C4 | Audio | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .gspi[0] = { + .speed_mhz = 1, + .early_init = 1, + }, + .i2c[0] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[4] = { + .speed = I2C_SPEED_FAST, + }, + }" + + # GPIO for SD card detect + register "sdcard_cd_gpio" = "vSD3_CD_B" + + device domain 0 on + device pci 15.0 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_D21_IRQ)" + register "wake" = "GPE0_DW0_21" + device i2c 15 on end + end + end # I2C #0 + device pci 15.1 on + chip drivers/i2c/generic + register "hid" = ""ELAN0001"" + register "desc" = ""ELAN Touchscreen"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)" + register "probed" = "1" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" + register "reset_delay_ms" = "100" + register "reset_off_delay_ms" = "5" + register "has_power_resource" = "1" + register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C4)" + register "stop_off_delay_ms" = "5" + device i2c 49 on end + end + chip drivers/i2c/hid + register "generic.hid" = ""GDIX0000"" + register "generic.desc" = ""Goodix Touchscreen"" + register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" + register "generic.reset_delay_ms" = "10" + register "generic.reset_off_delay_ms" = "1" + register "generic.has_power_resource" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 5d on end + end + chip drivers/generic/gpio_keys + register "name" = ""PENH"" + register "gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A8)" + register "key.wake" = "GPE0_DW0_08" + register "key.wakeup_event_action" = "EV_ACT_ASSERTED" + register "key.dev_name" = ""EJCT"" + register "key.linux_code" = "SW_PEN_INSERTED" + register "key.linux_input_type" = "EV_SW" + register "key.label" = ""pen_eject"" + device generic 0 on end + end + end # I2C #1 + device pci 15.2 off end # I2C #2 + device pci 15.3 on + chip drivers/i2c/sx9310 + register "desc" = ""SAR Proximity Sensor"" + register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_A0)" + register "speed" = "I2C_SPEED_FAST" + register "uid" = "1" + register "reg_prox_ctrl0" = "0x10" + register "reg_prox_ctrl1" = "0x00" + register "reg_prox_ctrl2" = "0x84" + register "reg_prox_ctrl3" = "0x0e" + register "reg_prox_ctrl4" = "0x07" + register "reg_prox_ctrl5" = "0xc6" + register "reg_prox_ctrl6" = "0x20" + register "reg_prox_ctrl7" = "0x0d" + register "reg_prox_ctrl8" = "0x8d" + register "reg_prox_ctrl9" = "0x43" + register "reg_prox_ctrl10" = "0x1f" + register "reg_prox_ctrl11" = "0x00" + register "reg_prox_ctrl12" = "0x00" + register "reg_prox_ctrl13" = "0x00" + register "reg_prox_ctrl14" = "0x00" + register "reg_prox_ctrl15" = "0x00" + register "reg_prox_ctrl16" = "0x00" + register "reg_prox_ctrl17" = "0x00" + register "reg_prox_ctrl18" = "0x00" + register "reg_prox_ctrl19" = "0x00" + register "reg_sar_ctrl0" = "0x50" + register "reg_sar_ctrl1" = "0x8a" + register "reg_sar_ctrl2" = "0x3c" + device i2c 28 on end + end + end # I2C #3 + device pci 19.0 on + chip drivers/i2c/generic + register "hid" = ""10EC5682"" + register "name" = ""RT58"" + register "desc" = ""Realtek RT5682"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_H0)" + register "property_count" = "1" + # Set the jd_src to RT5668_JD1 for jack detection + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on end + end + end #I2C #4 + device pci 1e.3 on + chip drivers/spi/acpi + register "name" = ""CRFP"" + register "hid" = "ACPI_DT_NAMESPACE_HID" + register "uid" = "1" + register "compat_string" = ""google,cros-ec-spi"" + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_A23_IRQ)" + device spi 1 on end + end # FPMCU + end # GSPI #1 + end + +end From a66c9b8bf4e4db0a108f90c21084ecc25aa87e72 Mon Sep 17 00:00:00 2001 From: Julius Werner Date: Mon, 20 May 2019 14:53:47 -0700 Subject: [PATCH 259/331] string.h: Move common string functions into .c file There's no clear reason why most of coreboot's basic string functions are static inline. These functions don't particularly benefit from inlining (at least not notably more than other functions). This patch moves them to string.c to be more consistent with our usual coding practices. Leaving the ctype functions as static inline because they actually seem small and collapsible enough that inlining seems reasonable. Also clarified the situation of strdup() and strconcat() a bit more, optimized strrchr() to be single-pass, fixed a bug with using strchr() to find '\0' and got rid of unnecessary register keywords. Change-Id: I88166ba9876e94dfa3cfc06969c78a9e1bc6fc36 Signed-off-by: Julius Werner Reviewed-on: https://review.coreboot.org/c/coreboot/+/32901 Tested-by: build bot (Jenkins) Reviewed-by: Alex Thiessen --- src/include/string.h | 119 +++++-------------------------------------- src/lib/Makefile.inc | 9 +++- src/lib/string.c | 109 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 131 insertions(+), 106 deletions(-) diff --git a/src/include/string.h b/src/include/string.h index c56a760a04..d164f32b83 100644 --- a/src/include/string.h +++ b/src/include/string.h @@ -25,33 +25,13 @@ int vsnprintf(char *buf, size_t size, const char *fmt, va_list args); #endif char *strdup(const char *s); char *strconcat(const char *s1, const char *s2); - -// simple string functions - -static inline size_t strnlen(const char *src, size_t max) -{ - size_t i = 0; - while ((*src++) && (i < max)) - i++; - return i; -} - -static inline size_t strlen(const char *src) -{ - size_t i = 0; - while (*src++) - i++; - return i; -} - -static inline char *strchr(const char *s, int c) -{ - for (; *s; s++) { - if (*s == c) - return (char *) s; - } - return 0; -} +size_t strnlen(const char *src, size_t max); +size_t strlen(const char *src); +char *strchr(const char *s, int c); +char *strncpy(char *to, const char *from, int count); +char *strcpy(char *dst, const char *src); +int strcmp(const char *s1, const char *s2); +int strncmp(const char *s1, const char *s2, int maxlen); /** * Find a character in a string. @@ -61,71 +41,14 @@ static inline char *strchr(const char *s, int c) * @return A pointer to the last occurrence of the character in the * string, or NULL if the character was not encountered within the string. */ -static inline char *strrchr(const char *s, int c) -{ - char *p = (char *)s + strlen(s); +char *strrchr(const char *s, int c); - for (; p >= s; p--) { - if (*p == c) - return p; - } - - return NULL; -} - -static inline char *strncpy(char *to, const char *from, int count) -{ - register char *ret = to; - register char data; - - while (count > 0) { - count--; - data = *from++; - *to++ = data; - if (data == '\0') - break; - } - - while (count > 0) { - count--; - *to++ = '\0'; - } - return ret; -} - -static inline char *strcpy(char *dst, const char *src) -{ - char *ptr = dst; - - while (*src) - *dst++ = *src++; - *dst = '\0'; - - return ptr; -} - -static inline int strcmp(const char *s1, const char *s2) -{ - int r; - - while ((r = (*s1 - *s2)) == 0 && *s1) { - s1++; - s2++; - } - return r; -} - -static inline int strncmp(const char *s1, const char *s2, int maxlen) -{ - int i; - - for (i = 0; i < maxlen; i++) { - if ((s1[i] != s2[i]) || (s1[i] == '\0')) - return s1[i] - s2[i]; - } - - return 0; -} +/* + * Parses an unsigned integer and moves the input pointer forward to the first + * character that's not a valid digit. s and *s must not be NULL. Result + * undefined if it overruns the return type size. + */ +unsigned int skip_atoi(char **s); static inline int isspace(int c) { @@ -179,18 +102,4 @@ static inline int tolower(int c) return c; } -/* - * Parses an unsigned integer and moves the input pointer forward to the first - * character that's not a valid digit. s and *s must not be NULL. Result - * undefined if it overruns the return type size. - */ -static inline unsigned int skip_atoi(char **s) -{ - unsigned int i = 0; - - while (isdigit(**s)) - i = i*10 + *((*s)++) - '0'; - return i; -} - #endif /* STRING_H */ diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 1350152a40..913675bac8 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -118,7 +118,6 @@ ramstage-y += bootmem.c ramstage-y += fmap.c ramstage-y += memchr.c ramstage-y += memcmp.c -ramstage-y += string.c ramstage-y += malloc.c smm-$(CONFIG_SMM_TSEG) += malloc.c ramstage-y += dimm_info_util.c @@ -244,6 +243,14 @@ postcar-y += reset.c ramstage-y += reset.c smm-y += reset.c +decompressor-y += string.c +bootblock-y += string.c +verstage-y += string.c +romstage-y += string.c +postcar-y += string.c +ramstage-y += string.c +smm-y += string.c + postcar-y += bootmode.c postcar-y += boot_device.c postcar-y += cbfs.c diff --git a/src/lib/string.c b/src/lib/string.c index 2e71489ff6..a19f017852 100644 --- a/src/lib/string.c +++ b/src/lib/string.c @@ -1,9 +1,14 @@ +#include +#include #include #include #include char *strdup(const char *s) { + if (!ENV_RAMSTAGE) + dead_code(); /* This can't be used without malloc(). */ + size_t sz = strlen(s) + 1; char *d = malloc(sz); if (d) @@ -13,6 +18,9 @@ char *strdup(const char *s) char *strconcat(const char *s1, const char *s2) { + if (!ENV_RAMSTAGE) + dead_code(); /* This can't be used without malloc(). */ + size_t sz_1 = strlen(s1); size_t sz_2 = strlen(s2); char *d = malloc(sz_1 + sz_2 + 1); @@ -22,3 +30,104 @@ char *strconcat(const char *s1, const char *s2) } return d; } + +size_t strnlen(const char *src, size_t max) +{ + size_t i = 0; + while ((*src++) && (i < max)) + i++; + return i; +} + +size_t strlen(const char *src) +{ + size_t i = 0; + while (*src++) + i++; + return i; +} + +char *strchr(const char *s, int c) +{ + do { + if (*s == c) + return (char *)s; + } while (*s++); + + return NULL; +} + +char *strrchr(const char *s, int c) +{ + char *p = NULL; + + do { + if (*s == c) + p = (char *)s; + } while (*s++); + + return p; +} + +char *strncpy(char *to, const char *from, int count) +{ + char *ret = to; + char data; + + while (count > 0) { + count--; + data = *from++; + *to++ = data; + if (data == '\0') + break; + } + + while (count > 0) { + count--; + *to++ = '\0'; + } + return ret; +} + +char *strcpy(char *dst, const char *src) +{ + char *ptr = dst; + + while (*src) + *dst++ = *src++; + *dst = '\0'; + + return ptr; +} + +int strcmp(const char *s1, const char *s2) +{ + int r; + + while ((r = (*s1 - *s2)) == 0 && *s1) { + s1++; + s2++; + } + return r; +} + +int strncmp(const char *s1, const char *s2, int maxlen) +{ + int i; + + for (i = 0; i < maxlen; i++) { + if ((s1[i] != s2[i]) || (s1[i] == '\0')) + return s1[i] - s2[i]; + } + + return 0; +} + +unsigned int skip_atoi(char **s) +{ + unsigned int i = 0; + + while (isdigit(**s)) + i = i*10 + *((*s)++) - '0'; + return i; +} From cdc459e66a3c6b68bae2515120445a10483df7f4 Mon Sep 17 00:00:00 2001 From: Tim Wawrzynczak Date: Tue, 21 May 2019 14:00:53 -0600 Subject: [PATCH 260/331] mb/google/hatch: Create helios variant Created helios (hatch variant). Currenly copied from kohaku. Helios- specific changes will come later. BUG=b:133182138 BRANCH=none TEST=none Change-Id: I9d151621a1c42e6f3cadb288f7ea476828c059b5 Signed-off-by: Tim Wawrzynczak Reviewed-on: https://review.coreboot.org/c/coreboot/+/32919 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh Reviewed-by: Paul Fagerburg --- .../google/hatch/variants/helios/Makefile.inc | 20 ++++++++ .../helios/include/variant/acpi/dptf.asl | 16 +++++++ .../variants/helios/include/variant/ec.h | 21 +++++++++ .../variants/helios/include/variant/gpio.h | 21 +++++++++ .../hatch/variants/helios/overridetree.cb | 46 +++++++++++++++++++ 5 files changed, 124 insertions(+) create mode 100644 src/mainboard/google/hatch/variants/helios/Makefile.inc create mode 100644 src/mainboard/google/hatch/variants/helios/include/variant/acpi/dptf.asl create mode 100644 src/mainboard/google/hatch/variants/helios/include/variant/ec.h create mode 100644 src/mainboard/google/hatch/variants/helios/include/variant/gpio.h create mode 100644 src/mainboard/google/hatch/variants/helios/overridetree.cb diff --git a/src/mainboard/google/hatch/variants/helios/Makefile.inc b/src/mainboard/google/hatch/variants/helios/Makefile.inc new file mode 100644 index 0000000000..cf6ee5ac97 --- /dev/null +++ b/src/mainboard/google/hatch/variants/helios/Makefile.inc @@ -0,0 +1,20 @@ +## This file is part of the coreboot project. +## +## Copyright 2019 Google LLC +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +SPD_SOURCES = 4G_2400 # 0b000 +SPD_SOURCES += empty_ddr4 # 0b001 +SPD_SOURCES += 8G_2400 # 0b010 +SPD_SOURCES += 8G_2666 # 0b011 +SPD_SOURCES += 16G_2400 # 0b100 +SPD_SOURCES += 16G_2666 # 0b101 diff --git a/src/mainboard/google/hatch/variants/helios/include/variant/acpi/dptf.asl b/src/mainboard/google/hatch/variants/helios/include/variant/acpi/dptf.asl new file mode 100644 index 0000000000..f1f09438fa --- /dev/null +++ b/src/mainboard/google/hatch/variants/helios/include/variant/acpi/dptf.asl @@ -0,0 +1,16 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include diff --git a/src/mainboard/google/hatch/variants/helios/include/variant/ec.h b/src/mainboard/google/hatch/variants/helios/include/variant/ec.h new file mode 100644 index 0000000000..768987d225 --- /dev/null +++ b/src/mainboard/google/hatch/variants/helios/include/variant/ec.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef VARIANT_EC_H +#define VARIANT_EC_H + +#include + +#endif diff --git a/src/mainboard/google/hatch/variants/helios/include/variant/gpio.h b/src/mainboard/google/hatch/variants/helios/include/variant/gpio.h new file mode 100644 index 0000000000..d99e2bbd65 --- /dev/null +++ b/src/mainboard/google/hatch/variants/helios/include/variant/gpio.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include + +#endif diff --git a/src/mainboard/google/hatch/variants/helios/overridetree.cb b/src/mainboard/google/hatch/variants/helios/overridetree.cb new file mode 100644 index 0000000000..84f0e29afa --- /dev/null +++ b/src/mainboard/google/hatch/variants/helios/overridetree.cb @@ -0,0 +1,46 @@ +chip soc/intel/cannonlake + register "SerialIoDevMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoPci, + [PchSerialIoIndexI2C2] = PchSerialIoPci, + [PchSerialIoIndexI2C3] = PchSerialIoPci, + [PchSerialIoIndexI2C4] = PchSerialIoPci, + [PchSerialIoIndexI2C5] = PchSerialIoPci, + [PchSerialIoIndexSPI0] = PchSerialIoPci, + [PchSerialIoIndexSPI1] = PchSerialIoPci, + [PchSerialIoIndexSPI2] = PchSerialIoDisabled, + [PchSerialIoIndexUART0] = PchSerialIoSkipInit, + [PchSerialIoIndexUART1] = PchSerialIoDisabled, + [PchSerialIoIndexUART2] = PchSerialIoDisabled, + }" + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| I2C0 | Trackpad | + #| I2C1 | Touchscreen | + #| I2C2 | Digitizer | + #| I2C4 | Audio | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .i2c[0] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[2] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[4] = { + .speed = I2C_SPEED_FAST, + }, + .gspi[0] = { + .speed_mhz = 1, + .early_init = 1, + }, + }" + + device domain 0 on end +end From f3510cbe36717f217a7ccde2b1f5994694ddce99 Mon Sep 17 00:00:00 2001 From: Tim Wawrzynczak Date: Tue, 21 May 2019 11:03:01 -0600 Subject: [PATCH 261/331] mainboard/google/hatch: Add Helios support Add Helios as a variant of Hatch. BUG=b:133182138 BRANCH=None TEST=util/abuild/abuild -p none -t google/hatch -x -a attempts to build a Helios target. Change-Id: I64ba06932eb0ee32405f7b14a94971a64c8fce71 Signed-off-by: Tim Wawrzynczak Reviewed-on: https://review.coreboot.org/c/coreboot/+/32918 Reviewed-by: Shelley Chen Reviewed-by: Furquan Shaikh Reviewed-by: Paul Fagerburg Tested-by: build bot (Jenkins) --- src/mainboard/google/hatch/Kconfig | 9 ++++++--- src/mainboard/google/hatch/Kconfig.name | 6 ++++++ 2 files changed, 12 insertions(+), 3 deletions(-) diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig index e3927c0c25..80451299f6 100644 --- a/src/mainboard/google/hatch/Kconfig +++ b/src/mainboard/google/hatch/Kconfig @@ -64,8 +64,9 @@ config GBB_HWID depends on CHROMEOS default "HATCH TEST 1823" if BOARD_GOOGLE_HATCH default "HATCH_WHL TEST 2374" if BOARD_GOOGLE_HATCH_WHL - default "KOHAKU TEST 1953" if BOARD_GOOGLE_KOHAKU + default "HELIOS TEST 0878" if BOARD_GOOGLE_HELIOS default "KINDRED TEST 2636" if BOARD_GOOGLE_KINDRED + default "KOHAKU TEST 1953" if BOARD_GOOGLE_KOHAKU config MAINBOARD_DIR string @@ -79,8 +80,9 @@ config MAINBOARD_PART_NUMBER string default "Hatch" if BOARD_GOOGLE_HATCH default "Hatch_whl" if BOARD_GOOGLE_HATCH_WHL - default "Kohaku" if BOARD_GOOGLE_KOHAKU + default "Helios" if BOARD_GOOGLE_HELIOS default "Kindred" if BOARD_GOOGLE_KINDRED + default "Kohaku" if BOARD_GOOGLE_KOHAKU config MAINBOARD_VENDOR string @@ -102,8 +104,9 @@ config VARIANT_DIR string default "hatch" if BOARD_GOOGLE_HATCH default "hatch_whl" if BOARD_GOOGLE_HATCH_WHL - default "kohaku" if BOARD_GOOGLE_KOHAKU + default "helios" if BOARD_GOOGLE_HELIOS default "kindred" if BOARD_GOOGLE_KINDRED + default "kohaku" if BOARD_GOOGLE_KOHAKU config VBOOT select HAS_RECOVERY_MRC_CACHE diff --git a/src/mainboard/google/hatch/Kconfig.name b/src/mainboard/google/hatch/Kconfig.name index 43fd4bed9b..9a257259ad 100644 --- a/src/mainboard/google/hatch/Kconfig.name +++ b/src/mainboard/google/hatch/Kconfig.name @@ -23,3 +23,9 @@ config BOARD_GOOGLE_KINDRED select BOARD_GOOGLE_BASEBOARD_HATCH select BOARD_ROMSIZE_KB_16384 select SOC_INTEL_COMETLAKE + +config BOARD_GOOGLE_HELIOS + bool "-> Helios" + select BOARD_GOOGLE_BASEBOARD_HATCH + select BOARD_ROMSIZE_KB_16384 + select SOC_INTEL_COMETLAKE From 2761847f904ce695fc8e47929f65bf6da64bcb6d Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Thu, 30 May 2019 18:28:59 +0530 Subject: [PATCH 262/331] Makefile.inc: Remove unnecessary CONFIG dependency This patch removes unnecessary kconfig depencies as below 1. CONFIG_ARCH_RAMSTAGE_X86_32 2. CONFIG_RELOCATABLE_RAMSTAGE Include required files as is without specify kconfig option. Change-Id: Ic9d1a95e80178775dd78e756f97f6da13a24dc95 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/33113 Tested-by: build bot (Jenkins) Reviewed-by: ron minnich --- src/arch/x86/Makefile.inc | 4 ++-- src/lib/Makefile.inc | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 6e4ee76c55..7e518d8c93 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -193,7 +193,7 @@ verstage-$(CONFIG_VBOOT_SEPARATE_VERSTAGE) += gdt_init.S verstage-$(CONFIG_IDT_IN_EVERY_STAGE) += exception.c verstage-$(CONFIG_IDT_IN_EVERY_STAGE) += idt.S -verstage-$(CONFIG_ARCH_RAMSTAGE_X86_32) += cpu_common.c +verstage-y += cpu_common.c verstage-y += memset.c verstage-y += memcpy.c verstage-y += memmove.c @@ -230,7 +230,7 @@ romstage-y += boot.c romstage-$(CONFIG_C_ENVIRONMENT_BOOTBLOCK) += gdt_init.S romstage-y += cbmem.c romstage-y += cbfs_and_run.c -romstage-$(CONFIG_ARCH_RAMSTAGE_X86_32) += cpu_common.c +romstage-y += cpu_common.c romstage-$(CONFIG_EARLY_EBDA_INIT) += ebda.c romstage-$(CONFIG_IDT_IN_EVERY_STAGE) += exception.c romstage-$(CONFIG_IDT_IN_EVERY_STAGE) += idt.S diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 913675bac8..1b8ad19b67 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -104,7 +104,7 @@ bootblock-$(CONFIG_ARCH_BOOTBLOCK_X86_32) += gcc.c verstage-$(CONFIG_ARCH_VERSTAGE_X86_32) += gcc.c romstage-$(CONFIG_ARCH_ROMSTAGE_X86_32) += gcc.c ramstage-$(CONFIG_ARCH_RAMSTAGE_X86_32) += gcc.c -smm-$(CONFIG_ARCH_RAMSTAGE_X86_32) += gcc.c +smm-y += gcc.c endif romstage-$(CONFIG_GENERIC_UDELAY) += timer.c @@ -279,7 +279,7 @@ verstage-y += program.ld ifeq ($(CONFIG_RELOCATABLE_MODULES),y) ramstage-y += rmodule.c -romstage-$(CONFIG_RELOCATABLE_RAMSTAGE) += rmodule.c +romstage-y += rmodule.c RMODULE_LDFLAGS := -z defs -Bsymbolic From c82acf59311abbb7e27add8d452282d57ed988aa Mon Sep 17 00:00:00 2001 From: Patrick Georgi Date: Fri, 22 Mar 2019 15:19:05 +0530 Subject: [PATCH 263/331] qualcomm/qcs405: enable SPI bus 4 for TPM Change-Id: Ic282daf10dad42bc4513cc55f15ce80a4bd316a5 Signed-off-by: Patrick Georgi Signed-off-by: Prudhvi Yarlagadda Signed-off-by: Nitheesh Sekar Reviewed-on: https://review.coreboot.org/c/coreboot/+/30934 Tested-by: build bot (Jenkins) --- src/mainboard/google/mistral/Makefile.inc | 1 + src/mainboard/google/mistral/verstage.c | 31 +++++++++++++++++++++++ 2 files changed, 32 insertions(+) create mode 100644 src/mainboard/google/mistral/verstage.c diff --git a/src/mainboard/google/mistral/Makefile.inc b/src/mainboard/google/mistral/Makefile.inc index 2cb963123b..ca191d147e 100644 --- a/src/mainboard/google/mistral/Makefile.inc +++ b/src/mainboard/google/mistral/Makefile.inc @@ -7,6 +7,7 @@ bootblock-y += bootblock.c verstage-y += memlayout.ld verstage-y += chromeos.c verstage-y += reset.c +verstage-y += verstage.c romstage-y += memlayout.ld romstage-y += chromeos.c diff --git a/src/mainboard/google/mistral/verstage.c b/src/mainboard/google/mistral/verstage.c new file mode 100644 index 0000000000..a34e4fa361 --- /dev/null +++ b/src/mainboard/google/mistral/verstage.c @@ -0,0 +1,31 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include +#include +#include +#include + +void verstage_mainboard_init(void) +{ + struct spi_slave spi; + + printk(BIOS_ERR, "Trying to initialize TPM SPI bus\n"); + if (spi_setup_slave(CONFIG_DRIVER_TPM_SPI_BUS, + CONFIG_DRIVER_TPM_SPI_CHIP, &spi)) { + printk(BIOS_ERR, "Failed to setup TPM SPI slave\n"); + } +} From a2c219a91d41463bf8830b321ee461806f9698da Mon Sep 17 00:00:00 2001 From: Nitheesh Sekar Date: Fri, 22 Mar 2019 15:10:43 +0530 Subject: [PATCH 264/331] qcs405: Enable SPI-NOR Enable support for Gigadevice spi-nor flash. Change-Id: I340eb3bf77b25fe3502d4b29ef4bf7c06b282c02 Signed-off-by: Nitheesh Sekar Reviewed-on: https://review.coreboot.org/c/coreboot/+/29968 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- src/mainboard/google/mistral/Kconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/mainboard/google/mistral/Kconfig b/src/mainboard/google/mistral/Kconfig index d1ab9c4f11..a2ba7cc24a 100644 --- a/src/mainboard/google/mistral/Kconfig +++ b/src/mainboard/google/mistral/Kconfig @@ -10,6 +10,8 @@ config BOARD_SPECIFIC_OPTIONS select COMMON_CBFS_SPI_WRAPPER select SOC_QUALCOMM_QCS405 select SPI_FLASH + select SPI_FLASH_GIGADEVICE + select SPI_FLASH_WINBOND select MAINBOARD_HAS_CHROMEOS config VBOOT From a82f991122b199bcdaf51eb93dcdcd81825de2bf Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Sat, 29 Dec 2018 21:43:11 -0600 Subject: [PATCH 265/331] google/buddy: fix Windows ACPI error with WLAN Buddy's WLAN ACPI code was equivalent to, but formatted differently from the other auron variants. Since only differnce is root port used, have buddy use common WLAN ACPI and use preprocessor guards to set the root port correctly. Test: build/boot Buddy, verify Windows 10 boots without ACPI BIOS ERROR. Change-Id: I78d994f2bb3981d4d10cb534cd6e0ae673f73527 Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/30523 Reviewed-by: Arthur Heymans Tested-by: build bot (Jenkins) --- src/mainboard/google/auron/acpi/mainboard.asl | 9 +++++-- .../google/auron/variants/buddy/devicetree.cb | 4 ++-- .../buddy/include/variant/acpi/mainboard.asl | 24 ------------------- 3 files changed, 9 insertions(+), 28 deletions(-) diff --git a/src/mainboard/google/auron/acpi/mainboard.asl b/src/mainboard/google/auron/acpi/mainboard.asl index a07ce3e7be..cd6a830564 100644 --- a/src/mainboard/google/auron/acpi/mainboard.asl +++ b/src/mainboard/google/auron/acpi/mainboard.asl @@ -16,8 +16,14 @@ #include -#if !CONFIG(BOARD_GOOGLE_BUDDY) +/* + * WLAN on Buddy connected to RP4, becomes RP2 after coalesce + */ +#if CONFIG(BOARD_GOOGLE_BUDDY) +Scope (\_SB.PCI0.RP02) +#else Scope (\_SB.PCI0.RP01) +#endif { Device (WLAN) { @@ -35,7 +41,6 @@ Scope (\_SB.PCI0.RP01) } } } -#endif #include diff --git a/src/mainboard/google/auron/variants/buddy/devicetree.cb b/src/mainboard/google/auron/variants/buddy/devicetree.cb index e6627949b5..f75da84eee 100644 --- a/src/mainboard/google/auron/variants/buddy/devicetree.cb +++ b/src/mainboard/google/auron/variants/buddy/devicetree.cb @@ -90,8 +90,8 @@ chip soc/intel/broadwell device pci 1b.0 off end # High Definition Audio device pci 1c.0 off end # PCIe Port #1 device pci 1c.1 off end # PCIe Port #2 - device pci 1c.2 on end # PCIe Port #3 - device pci 1c.3 on end # PCIe Port #4 + device pci 1c.2 on end # PCIe Port #3 - LAN (becomes RP1) + device pci 1c.3 on end # PCIe Port #4 - WLAN (becomes RP2) device pci 1c.4 on end # PCIe Port #5 device pci 1c.5 off end # PCIe Port #6 device pci 1d.0 on end # USB2 EHCI diff --git a/src/mainboard/google/auron/variants/buddy/include/variant/acpi/mainboard.asl b/src/mainboard/google/auron/variants/buddy/include/variant/acpi/mainboard.asl index 788fbdc61e..e9fd212e8d 100644 --- a/src/mainboard/google/auron/variants/buddy/include/variant/acpi/mainboard.asl +++ b/src/mainboard/google/auron/variants/buddy/include/variant/acpi/mainboard.asl @@ -117,27 +117,3 @@ Scope (\_SB.PCI0.RP01) } } } - -/* - * WLAN connected to Root Port 4, becomes Root Port 2 after coalesce - */ -Scope (\_SB.PCI0.RP02) -{ - Device (WLAN) - { - Name (_ADR, 0x00000000) - - /* GPIO10 is WLAN_WAKE_L_Q */ - Name (GPIO, BOARD_WLAN_WAKE_GPIO) - - Name (_PRW, Package() { GPIO, 3 }) - - Method (_DSW, 3, NotSerialized) - { - If (LEqual (Arg0, 1)) { - // Enable GPIO as wake source - \_SB.PCI0.LPCB.GPIO.GWAK (^GPIO) - } - } - } -} From 0da3a8a91bdfa97f658286717c9e6af0fcd69fe6 Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Mon, 27 May 2019 02:09:24 -0500 Subject: [PATCH 266/331] soc/intel/baytrail: set default VBIOS filename and PCI ID All Baytrail boards have the same GPU PCI ID, so set it here to avoid having to set it in each board's config. Move the VGA_BIOS_FILE config from google/rambi into soc/baytrail since it likewise applies to all Baytrail boards. Change-Id: Id1e0580b55e3590d868cb839987f06c49bb07cf5 Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/33026 Reviewed-by: HAOUAS Elyes Tested-by: build bot (Jenkins) --- src/mainboard/google/rambi/Kconfig | 4 ---- src/soc/intel/baytrail/Kconfig | 10 ++++++++++ 2 files changed, 10 insertions(+), 4 deletions(-) diff --git a/src/mainboard/google/rambi/Kconfig b/src/mainboard/google/rambi/Kconfig index c47b3d7909..56d44bcea0 100644 --- a/src/mainboard/google/rambi/Kconfig +++ b/src/mainboard/google/rambi/Kconfig @@ -90,10 +90,6 @@ config EC_GOOGLE_CHROMEEC_BOARDNAME string default "" -config VGA_BIOS_FILE - string - default "pci8086,0f31.rom" - config MAINBOARD_SMBIOS_MANUFACTURER string default "GOOGLE" diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index 03ad31d41f..43c2906f15 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -168,4 +168,14 @@ config REFCODE_BLOB_FILE endif # HAVE_REFCODE_BLOB +config VGA_BIOS_ID + string + depends on VGA_BIOS + default "8086,0f31" + +config VGA_BIOS_FILE + string + depends on VGA_BIOS + default "pci8086,0f31.rom" + endif From bfd23ce87bddafe5a1ff17d016cd88f6e746385b Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Thu, 30 May 2019 14:00:29 +0200 Subject: [PATCH 267/331] soc/intel/common/mmc: Replace IS_ENABLED() with CONFIG() Change-Id: I99d51176f6d7d6a98a3a3c82aa8e8eee73344496 Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/c/coreboot/+/33111 Reviewed-by: Subrata Banik Tested-by: build bot (Jenkins) --- src/soc/intel/common/block/include/intelblocks/early_mmc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/intel/common/block/include/intelblocks/early_mmc.h b/src/soc/intel/common/block/include/intelblocks/early_mmc.h index 69be40cf27..39aaf58fcf 100644 --- a/src/soc/intel/common/block/include/intelblocks/early_mmc.h +++ b/src/soc/intel/common/block/include/intelblocks/early_mmc.h @@ -61,7 +61,7 @@ int soc_configure_mmc_gpios(void); */ int soc_get_mmc_dll(struct mmc_dll_params *params); -#if IS_ENABLED(CONFIG_SOC_INTEL_COMMON_EARLY_MMC_WAKE) +#if CONFIG(SOC_INTEL_COMMON_EARLY_MMC_WAKE) /* * Initializes sdhci / mmc controller and sends CMD0, CMD1 to emmc card. * In case of success: It returns 0 and adds cbmem entry CBMEM_ID_MMC_STATUS From d1b99d2bbf11ece1e724eb57dfe5a01a950715ca Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Thu, 30 May 2019 15:11:42 +0200 Subject: [PATCH 268/331] nb/intel/snb: Don't run VGA oprom when libgfxinit is enabled This was likely an oversight when libgfxinit got its own Kconfig symbols. Change-Id: I647551719b332b5b734720ae4ee0619bbfcbed8c Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/c/coreboot/+/33126 Reviewed-by: Arthur Heymans Tested-by: build bot (Jenkins) --- src/northbridge/intel/sandybridge/gma.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/northbridge/intel/sandybridge/gma.c b/src/northbridge/intel/sandybridge/gma.c index 1005288fee..19df8d4cc8 100644 --- a/src/northbridge/intel/sandybridge/gma.c +++ b/src/northbridge/intel/sandybridge/gma.c @@ -626,7 +626,7 @@ static void gma_func0_init(struct device *dev) /* Init graphics power management */ gma_pm_init_pre_vbios(dev); - if (!CONFIG(MAINBOARD_DO_NATIVE_VGA_INIT)) + if (!CONFIG(MAINBOARD_USE_LIBGFXINIT)) /* PCI Init, will run VBIOS */ pci_dev_init(dev); From ec93be5208e1bfece4165858d0d9e2b13e185ea3 Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Thu, 30 May 2019 15:13:31 +0200 Subject: [PATCH 269/331] nb/intel/haswell/gma: Drop NGI remnant The native graphics init option was replaced with libgfxinit. Change-Id: I62569b70186b7b068effdadc4b39b3c09ddb7188 Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/c/coreboot/+/33127 Reviewed-by: Arthur Heymans Tested-by: build bot (Jenkins) --- src/northbridge/intel/haswell/gma.c | 8 -------- 1 file changed, 8 deletions(-) diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c index 607fab7602..ca446e25a7 100644 --- a/src/northbridge/intel/haswell/gma.c +++ b/src/northbridge/intel/haswell/gma.c @@ -236,14 +236,6 @@ static void power_well_enable(void) { gtt_write(HSW_PWR_WELL_CTL1, HSW_PWR_WELL_ENABLE); gtt_poll(HSW_PWR_WELL_CTL1, HSW_PWR_WELL_STATE, HSW_PWR_WELL_STATE); - - /* In the native graphics case, we've got about 20 ms. - * after we power up the AUX channel until we can talk to it. - * So get that going right now. We can't turn on the panel, yet, just VDD. - */ - if (CONFIG(MAINBOARD_DO_NATIVE_VGA_INIT)) { - gtt_write(PCH_PP_CONTROL, PCH_PP_UNLOCK| EDP_FORCE_VDD | PANEL_POWER_RESET); - } } static void gma_pm_init_pre_vbios(struct device *dev) From 2e6c3c8936e4d5afcbd39226bc6b18a42119afee Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Thu, 30 May 2019 15:21:40 +0200 Subject: [PATCH 270/331] mb/google/link: Remove Link's own native graphics init The code was already orphaned since its hook-up was removed with a6be58fece (nb/intel/sandybridge: Remove the C native graphic init). Change-Id: Ia554c457e2f3a2dc42965ac5cded0be8e82311fb Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/c/coreboot/+/33128 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans Reviewed-by: Julius Werner --- src/mainboard/google/link/Kconfig | 2 - src/mainboard/google/link/Makefile.inc | 3 - src/mainboard/google/link/i915.c | 374 ------------------------- src/mainboard/google/link/i915io.c | 355 ----------------------- src/mainboard/google/link/i915io.h | 82 ------ src/mainboard/google/link/intel_dp.c | 166 ----------- 6 files changed, 982 deletions(-) delete mode 100644 src/mainboard/google/link/i915.c delete mode 100644 src/mainboard/google/link/i915io.c delete mode 100644 src/mainboard/google/link/i915io.h delete mode 100644 src/mainboard/google/link/intel_dp.c diff --git a/src/mainboard/google/link/Kconfig b/src/mainboard/google/link/Kconfig index 3628f1d8a5..6d62f64e3e 100644 --- a/src/mainboard/google/link/Kconfig +++ b/src/mainboard/google/link/Kconfig @@ -14,8 +14,6 @@ config BOARD_SPECIFIC_OPTIONS select MAINBOARD_HAS_LPC_TPM select MAINBOARD_HAS_TPM1 select SERIRQ_CONTINUOUS_MODE - select MAINBOARD_HAS_NATIVE_VGA_INIT - select HAVE_LINEAR_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT select MAINBOARD_HAS_LIBGFXINIT select HAVE_IFD_BIN select HAVE_ME_BIN diff --git a/src/mainboard/google/link/Makefile.inc b/src/mainboard/google/link/Makefile.inc index 281ce32442..89bb365023 100644 --- a/src/mainboard/google/link/Makefile.inc +++ b/src/mainboard/google/link/Makefile.inc @@ -17,9 +17,6 @@ ramstage-y += ec.c romstage-y += chromeos.c ramstage-y += chromeos.c -ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += i915.c -ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += i915io.c -ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += intel_dp.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads smm-$(CONFIG_HAVE_SMI_HANDLER) += mainboard_smi.c diff --git a/src/mainboard/google/link/i915.c b/src/mainboard/google/link/i915.c deleted file mode 100644 index 12d424cde0..0000000000 --- a/src/mainboard/google/link/i915.c +++ /dev/null @@ -1,374 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "ec.h" -#include "onboard.h" -#include "i915io.h" - -enum { - vmsg = 1, vio = 2, vspin = 4, -}; - -static int verbose = 0; - -static unsigned int *mmio; -static unsigned int graphics; -static unsigned short addrport; -static unsigned short dataport; -static unsigned int physbase; -static u32 htotal, hblank, hsync, vtotal, vblank, vsync; - -const u32 link_edid_data[] = { - 0xffffff00, 0x00ffffff, 0x0379e430, 0x00000000, - 0x04011500, 0x96121ba5, 0xa2d54f02, 0x26935259, - 0x00545017, 0x01010000, 0x01010101, 0x01010101, - 0x01010101, 0x6f6d0101, 0xa4a0a000, 0x20306031, - 0xb510003a, 0x19000010, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x4c00fe00, - 0x69442047, 0x616c7073, 0x20200a79, 0xfe000000, - 0x31504c00, 0x45513932, 0x50532d31, 0x24003141, -}; - -#define READ32(addr) io_i915_READ32(addr) -#define WRITE32(val, addr) io_i915_WRITE32(val, addr) - -static char *regname(unsigned long addr) -{ - static char name[16]; - snprintf(name, sizeof(name), "0x%lx", addr); - return name; -} - -unsigned long io_i915_READ32(unsigned long addr) -{ - unsigned long val; - outl(addr, addrport); - val = inl(dataport); - if (verbose & vio) - printk(BIOS_SPEW, "%s: Got %08lx\n", regname(addr), val); - return val; -} - -void io_i915_WRITE32(unsigned long val, unsigned long addr) -{ - if (verbose & vio) - printk(BIOS_SPEW, "%s: outl %08lx\n", regname(addr), val); - outl(addr, addrport); - outl(val, dataport); -} - - -/* - 2560 - 4 words per - 4 *p - 10240 - 4k bytes per page - 4096/p - 2.50 - 1700 lines - 1700 * p - 4250.00 - PTEs -*/ -static void -setgtt(int start, int end, unsigned long base, int inc) -{ - int i; - - for(i = start; i < end; i++){ - u32 word = base + i*inc; - WRITE32(word|1,(i*4)|1); - } -} - -static unsigned long tickspermicrosecond = 1795; -static unsigned long long globalstart; - -static unsigned long -microseconds(unsigned long long start, unsigned long long end) -{ - unsigned long ret; - ret = ((end - start)/tickspermicrosecond); - return ret; -} - -static unsigned long globalmicroseconds(void) -{ - return microseconds(globalstart, rdtscll()); -} - -extern struct iodef iodefs[]; -extern int niodefs; - -static int i915_init_done = 0; - -/* fill the palette. This runs when the P opcode is hit. */ -/* and, yes, it's needed for even 32 bits per pixel */ -static void palette(void) -{ - int i; - unsigned long color = 0; - - for(i = 0; i < 256; i++, color += 0x010101){ - io_i915_WRITE32(color, _LGC_PALETTE_A + (i << 2)); - } -} - -static unsigned long times[4096]; - -static int run(int index) -{ - int i, prev = 0; - struct iodef *id, *lastidread = NULL; - unsigned long u, t; - if (index >= niodefs) - return index; - /* state machine! */ - for(i = index, id = &iodefs[i]; id->op; i++, id++){ - switch (id->op) { - case M: - if (verbose & vmsg) printk(BIOS_SPEW, "%ld: %s\n", - globalmicroseconds(), id->msg); - break; - case P: - palette(); - break; - case R: - u = READ32(id->addr); - if (verbose & vio) - printk(BIOS_SPEW, "\texpect %08lx\n", id->data); - /* we're looking for something. */ - if (lastidread->addr == id->addr){ - /* they're going to be polling. - * just do it 1000 times - */ - for (t = 0; t < 1000 && id->data != u; t++){ - u = READ32(id->addr); - } - if (verbose & vspin) printk(BIOS_SPEW, - "%s: # loops %ld got %08lx want %08lx\n", - regname(id->addr), - t, u, id->data); - } - lastidread = id; - break; - case W: - WRITE32(id->data, id->addr); - if (id->addr == PCH_PP_CONTROL){ - if (verbose & vio) - printk(BIOS_SPEW, "PCH_PP_CONTROL\n"); - switch (id->data & 0xf) { - case 8: break; - case 7: break; - default: udelay(100000); - if (verbose & vio) - printk(BIOS_SPEW, "U %d\n", 100000); - } - } - break; - case V: - if (id->count < 8){ - prev = verbose; - verbose = id->count; - } else { - verbose = prev; - } - printk(BIOS_SPEW, "Change verbosity to %d\n", verbose); - break; - case I: - printk(BIOS_SPEW, "run: return %d\n", i+1); - return i+1; - break; - default: - printk(BIOS_SPEW, "BAD TABLE, opcode %d @ %d\n", id->op, i); - return -1; - } - if (id->udelay) - udelay(id->udelay); - if (i < ARRAY_SIZE(times)) - times[i] = globalmicroseconds(); - } - printk(BIOS_SPEW, "run: return %d\n", i); - return i+1; -} - -int i915lightup_sandy(const struct i915_gpu_controller_info *info, - u32 pphysbase, u16 piobase, u8 *pmmio, u32 pgfx) -{ - static struct edid edid; - const struct edid_mode *mode; - int edid_ok; - - int index; - u32 auxin[16], auxout[16]; - mmio = (void *)pmmio; - addrport = piobase; - dataport = addrport + 4; - physbase = pphysbase; - graphics = pgfx; - printk(BIOS_SPEW, "i915lightup: graphics %p mmio %p" - "addrport %04x physbase %08x\n", - (void *)graphics, mmio, addrport, physbase); - globalstart = rdtscll(); - - - edid_ok = decode_edid((unsigned char *)&link_edid_data, - sizeof(link_edid_data), &edid); - mode = &edid.mode; - printk(BIOS_SPEW, "decode edid returns %d\n", edid_ok); - edid.framebuffer_bits_per_pixel = 32; - - htotal = (mode->ha - 1) | ((mode->ha + mode->hbl - 1) << 16); - printk(BIOS_SPEW, "I915_WRITE(HTOTAL(pipe), %08x)\n", htotal); - - hblank = (mode->ha - 1) | ((mode->ha + mode->hbl - 1) << 16); - printk(BIOS_SPEW, "I915_WRITE(HBLANK(pipe),0x%08x)\n", hblank); - - hsync = (mode->ha + mode->hso - 1) | - ((mode->ha + mode->hso + mode->hspw - 1) << 16); - printk(BIOS_SPEW, "I915_WRITE(HSYNC(pipe),0x%08x)\n", hsync); - - vtotal = (mode->va - 1) | ((mode->va + mode->vbl - 1) << 16); - printk(BIOS_SPEW, "I915_WRITE(VTOTAL(pipe), %08x)\n", vtotal); - - vblank = (mode->va - 1) | ((mode->va + mode->vbl - 1) << 16); - printk(BIOS_SPEW, "I915_WRITE(VBLANK(pipe),0x%08x)\n", vblank); - - vsync = (mode->va + mode->vso - 1) | - ((mode->va + mode->vso + mode->vspw - 1) << 16); - printk(BIOS_SPEW, "I915_WRITE(VSYNC(pipe),0x%08x)\n", vsync); - - printk(BIOS_SPEW, "Table has %d elements\n", niodefs); - - index = run(0); - printk(BIOS_SPEW, "Run returns %d\n", index); - auxout[0] = 1 << 31 /* dp */|0x1 << 28/*R*/|DP_DPCD_REV << 8|0xe; - intel_dp_aux_ch(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, auxout, 4, auxin, 14); - auxout[0] = 0 << 31 /* i2c */|1 << 30|0x0 << 28/*W*/|0x0 << 8|0x0; - intel_dp_aux_ch(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, auxout, 3, auxin, 0); - index = run(index); - printk(BIOS_SPEW, "Run returns %d\n", index); - auxout[0] = 0 << 31 /* i2c */|0 << 30|0x0 << 28/*W*/|0x0 << 8|0x0; - intel_dp_aux_ch(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, auxout, 3, auxin, 0); - index = run(index); - printk(BIOS_SPEW, "Run returns %d\n", index); - auxout[0] = 1 << 31 /* dp */|0x0 << 28/*W*/|DP_SET_POWER << 8|0x0; - auxout[1] = 0x01000000; - /* DP_SET_POWER_D0 | DP_PSR_SINK_INACTIVE */ - intel_dp_aux_ch(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, auxout, 5, auxin, 0); - index = run(index); - auxout[0] = 1 << 31 /* dp */|0x0 << 28/*W*/|DP_LINK_BW_SET << 8|0x8; - auxout[1] = 0x0a840000; - /*(DP_LINK_BW_2_7 &0xa)|0x0000840a*/ - auxout[2] = 0x00000000; - auxout[3] = 0x01000000; - intel_dp_aux_ch(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, auxout, 13, auxin, 0); - index = run(index); - auxout[0] = 1 << 31 /* dp */|0x0 << 28/*W*/|DP_TRAINING_PATTERN_SET << 8|0x0; - auxout[1] = 0x21000000; - /* DP_TRAINING_PATTERN_1 | DP_LINK_SCRAMBLING_DISABLE | - * DP_SYMBOL_ERROR_COUNT_BOTH |0x00000021*/ - intel_dp_aux_ch(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, auxout, 5, auxin, 0); - index = run(index); - auxout[0] = 1 << 31 /* dp */|0x0 << 28/*W*/|DP_TRAINING_LANE0_SET << 8|0x3; - auxout[1] = 0x00000000; - /* DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0 |0x00000000*/ - intel_dp_aux_ch(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, auxout, 8, auxin, 0); - index = run(index); - auxout[0] = 1 << 31 /* dp */|0x1 << 28/*R*/|DP_LANE0_1_STATUS << 8|0x5; - intel_dp_aux_ch(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, auxout, 4, auxin, 5); - index = run(index); - auxout[0] = 1 << 31 /* dp */|0x0 << 28/*W*/|DP_TRAINING_PATTERN_SET << 8|0x0; - auxout[1] = 0x22000000; - /* DP_TRAINING_PATTERN_2 | DP_LINK_SCRAMBLING_DISABLE | - * DP_SYMBOL_ERROR_COUNT_BOTH |0x00000022*/ - intel_dp_aux_ch(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, auxout, 5, auxin, 0); - index = run(index); - auxout[0] = 1 << 31 /* dp */|0x0 << 28/*W*/|DP_TRAINING_LANE0_SET << 8|0x3; - auxout[1] = 0x00000000; - /* DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0 |0x00000000*/ - intel_dp_aux_ch(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, auxout, 8, auxin, 0); - index = run(index); - auxout[0] = 1 << 31 /* dp */|0x1 << 28/*R*/|DP_LANE0_1_STATUS << 8|0x5; - intel_dp_aux_ch(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, auxout, 4, auxin, 5); - index = run(index); - auxout[0] = 1 << 31 /* dp */|0x0 << 28/*W*/|DP_TRAINING_PATTERN_SET << 8|0x0; - auxout[1] = 0x00000000; - /* DP_TRAINING_PATTERN_DISABLE | DP_LINK_QUAL_PATTERN_DISABLE | - * DP_SYMBOL_ERROR_COUNT_BOTH |0x00000000*/ - intel_dp_aux_ch(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, auxout, 5, auxin, 0); - index = run(index); - - if (index != niodefs) - printk(BIOS_ERR, "Left over IO work in i915_lightup" - " -- this is likely a table error. " - "Only %d of %d were done.\n", index, niodefs); - printk(BIOS_SPEW, "DONE startup\n"); - verbose = 0; - /* GTT is the Global Translation Table for the graphics pipeline. - * It is used to translate graphics addresses to physical - * memory addresses. As in the CPU, GTTs map 4K pages. - * There are 32 bits per pixel, or 4 bytes, - * which means 1024 pixels per page. - * There are 4250 GTTs on Link: - * 2650 (X) * 1700 (Y) pixels / 1024 pixels per page. - * The setgtt function adds a further bit of flexibility: - * it allows you to set a range (the first two parameters) to point - * to a physical address (third parameter);the physical address is - * incremented by a count (fourth parameter) for each GTT in the - * range. - * Why do it this way? For ultrafast startup, - * we can point all the GTT entries to point to one page, - * and set that page to 0s: - * memset(physbase, 0, 4096); - * setgtt(0, 4250, physbase, 0); - * this takes about 2 ms, and is a win because zeroing - * the page takes a up to 200 ms. We will be exploiting this - * trick in a later rev of this code. - * This call sets the GTT to point to a linear range of pages - * starting at physbase. - */ - setgtt(0, FRAME_BUFFER_PAGES, physbase, 4096); - printk(BIOS_SPEW, "memset %p to 0 for %d bytes\n", - (void *)graphics, FRAME_BUFFER_BYTES); - memset((void *)graphics, 0, FRAME_BUFFER_BYTES); - printk(BIOS_SPEW, "%ld microseconds\n", globalmicroseconds()); - set_vbe_mode_info_valid(&edid, (uintptr_t)graphics); - i915_init_done = 1; - return i915_init_done; -} diff --git a/src/mainboard/google/link/i915io.c b/src/mainboard/google/link/i915io.c deleted file mode 100644 index 5ebb42d4e7..0000000000 --- a/src/mainboard/google/link/i915io.c +++ /dev/null @@ -1,355 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include "i915io.h" - -struct iodef iodefs[] = { - {V, 0}, - {W, 1, "", PCH_GMBUS0, 0x00000000, 0}, - {R, 1, "", PP_ON_DELAYS, ( /* T2 */ 0x0 << 16) | ( /* T5 */ 0x0 << 0) | 0x00000000, 0}, - {R, 1, "", PP_OFF_DELAYS, ( /* T3 */ 0x0 << 16) | ( /* Tx */ 0x0 << 0) | 0x00000000, 0}, - {W, 1, "", PP_ON_DELAYS, ( /* T2 */ 0x190 << 16) | ( /* T5 */ 0x7d0 << 0) | 0x019007d0, 0}, - {W, 1, "", PP_OFF_DELAYS, ( /* T3 */ 0x15e << 16) | ( /* Tx */ 0x7d0 << 0) | 0x015e07d0, 0}, - {M, 1, "[drm:intel_detect_pch], Found PatherPoint PCH", 0x0, 0xcf8e64, 0}, - {M, 1, "[drm:i915_load_modeset_init], failed to find VBIOS tables", 0x0, 0xcf8e64, 0}, - {R, 50, "", FORCEWAKE_MT_ACK, 0x00000001, 10}, - {W, 1, "", FORCEWAKE_MT, 0x00010001, 0}, - {R, 1, "", FORCEWAKE_MT, 0x00010001, 0}, - {R, 1, "", FORCEWAKE_MT_ACK, 0x00000001, 0}, - {R, 1, "", 0x13805c, 0x40000000, 0}, - {R, 1, "", 0xa180, 0x84100020, 0}, - {W, 1, "", FORCEWAKE_MT, 0x00010000, 0}, - {R, 1, "", 0x120000, 0x00000000, 0}, - {M, 1, "[drm:intel_init_display], Using MT version of forcewake", 0x0, 0xcf8e64, 0}, - {R, 1, "", 0x145d10, 0x2010040c, 0}, - {M, 1, "[drm:intel_modeset_init], 3 display pipes available.", 0x0, 0xcf8e64, 0}, - {R, 1, "", _PIPEACONF, ( /* PIPECONF_FRAME_START_DELAY_MASK */ 0x0 << 27) | PIPECONF_BPP_8 | PIPECONF_DITHER_TYPE_SP | 0x00000000, 0}, - {W, 1, "", _PIPEACONF, ( /* PIPECONF_FRAME_START_DELAY_MASK */ 0x0 << 27) | PIPECONF_BPP_8 | PIPECONF_DITHER_TYPE_SP | 0x00000000, 0}, - {R, 1, "", _PIPEBCONF, 0x00000000, 0}, - {W, 1, "", _PIPEBCONF, 0x00000000, 0}, - {R, 1, "", 0x72008, 0x00000000, 0}, - {W, 1, "", 0x72008, 0x00000000, 0}, - {R, 1, "", _PIPEACONF, ( /* PIPECONF_FRAME_START_DELAY_MASK */ 0x0 << 27) | PIPECONF_BPP_8 | PIPECONF_DITHER_TYPE_SP | 0x00000000, 0}, - {W, 1, "", _PIPEACONF, ( /* PIPECONF_FRAME_START_DELAY_MASK */ 0x0 << 27) | PIPECONF_BPP_8 | PIPECONF_DITHER_TYPE_SP | 0x00000000, 0}, - {R, 1, "", _PIPEBCONF, 0x00000000, 0}, - {W, 1, "", _PIPEBCONF, 0x00000000, 0}, - {R, 1, "", 0x72008, 0x00000000, 0}, - {W, 1, "", 0x72008, 0x00000000, 0}, - {R, 1, "", _PIPEACONF, ( /* PIPECONF_FRAME_START_DELAY_MASK */ 0x0 << 27) | PIPECONF_BPP_8 | PIPECONF_DITHER_TYPE_SP | 0x00000000, 0}, - {W, 1, "", _PIPEACONF, ( /* PIPECONF_FRAME_START_DELAY_MASK */ 0x0 << 27) | PIPECONF_BPP_8 | PIPECONF_DITHER_TYPE_SP | 0x00000000, 0}, - {R, 1, "", _PIPEBCONF, 0x00000000, 0}, - {W, 1, "", _PIPEBCONF, 0x00000000, 0}, - {R, 1, "", 0x72008, 0x00000000, 0}, - {W, 1, "", 0x72008, 0x00000000, 300}, - {W, 1, "", CPU_VGACNTRL, 0x80000000, 0}, - {R, 1, "", CPU_VGACNTRL, 0x80000000, 0}, - {R, 1, "", DP_A, DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0 | DP_PORT_WIDTH_1 | DP_PLL_FREQ_270MHZ | DP_SYNC_VS_HIGH | DP_SYNC_HS_HIGH | DP_DETECTED | 0x0000001c, 0}, - {R, 1, "", PCH_PP_ON_DELAYS, PANEL_PORT_SELECT_DPA | ( /* PANEL_POWER_UP_DELAY */ 0x7d0 << 16) | ( /* PANEL_LIGHT_ON_DELAY */ 0x7d0 << 0) | 0x47d007d0, 0}, - {R, 1, "", PCH_PP_OFF_DELAYS, ( /* PANEL_POWER_DOWN_DELAY */ 0x1f4 << 16) | ( /* PANEL_LIGHT_OFF_DELAY */ 0x7d0 << 0) | 0x01f407d0, 0}, - {R, 1, "", PCH_PP_DIVISOR, 0x00186906, 0}, - {M, 1, "[drm:intel_dp_init], cur t1_t3 2000 t8 2000 t9 2000 t10 500t11_t12 6000", 0x0, 0xcf8e64, 0}, - {M, 1, "[drm:intel_dp_init], vbt t1_t3 0 t8 0 t9 0 t10 0 t11_t12 0", 0x0, 0xcf8e64, 0}, - {M, 1, "[drm:intel_dp_init], panel power up delay 200,power down" "delay 50, power cycle delay 600", 0x0, 0xcf8e64, 0}, - {M, 1, "[drm:intel_dp_init], backlight on delay 200, off delay 200", 0x0, 0xcf8e64, 0}, - {M, 1, "[drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on", 0x0, 0xcf8e64, 0}, - {R, 1, "", PCH_PP_CONTROL, 0x00000000, 0}, - {R, 1, "", PCH_PP_STATUS, 0x00000000, 0}, - {M, 1, "[drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle", 0x0, 0xcf8e64, 0}, - {M, 1, "[drm:ironlake_wait_panel_status], R PCH_PP_CONTROL:00000000", 0x0, 0xcf8e64, 0}, - {R, 2, "", PCH_PP_STATUS, 0x00000000, 0}, - {R, 1, "", PCH_PP_CONTROL, 0x00000000, 0}, - {W, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | EDP_FORCE_VDD | 0xabcd0008, 0}, - {R, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | EDP_FORCE_VDD | 0xabcd0008, 0}, - {M, 1, "[drm:ironlake_edp_panel_vdd_on], R PCH_PP_CONTROL:abcd0008", 0x0, 0xcf8e64, 0}, - {R, 2, "", PCH_PP_STATUS, 0x00000000, 0}, - {M, 1, "[drm:ironlake_edp_panel_vdd_on], eDP was not running", 0x0, 0xcf8e64, 0}, - {R, 1, "", PCH_PP_STATUS, 0x00000000, 0}, - {R, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | EDP_FORCE_VDD | 0xabcd0008, 0}, - {R, 1, "", PCH_PP_STATUS, 0x00000000, 0}, - {R, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | EDP_FORCE_VDD | 0xabcd0008, 0}, - {M, 1, "[drm:intel_dp_i2c_init], i2c_init DPDDC-A", 0x0, 0x00000000, 0}, - {R, 1, "", PCH_PP_STATUS, 0x00000000, 0}, - {R, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | EDP_FORCE_VDD | 0xabcd0008, 0}, - {R, 1, "", PCH_PP_STATUS, 0x00000000, 0}, - {R, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | EDP_FORCE_VDD | 0xabcd0008, 0}, - {R, 1, "", PCH_PP_STATUS, 0x00000000, 0}, - {R, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | EDP_FORCE_VDD | 0xabcd0008, 0}, - {R, 1, "", PCH_PP_STATUS, 0x00000000, 0}, - {R, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | EDP_FORCE_VDD | 0xabcd0008, 0}, - {I,}, - {M, 1, "[drm:ironlake_edp_panel_vdd_off], Turn eDP VDD off 1", 0x0, 0x00000000, 0}, - {R, 1, "", BLC_PWM_CPU_CTL, 0x000010ce, 0}, - {M, 1, "[drm:intel_panel_get_backlight], get backlight PWM = 4302", 0x0, 0xcf8e64, 0}, - {M, 1, "[drm:intel_dp_aux_ch], dp_aux_ch timeout status 0x5145003f", 0x0, 0xcf8e64, 0}, - {M, 1, "[drm:intel_dp_i2c_aux_ch], aux_ch failed -110", 0x0, 0xcf8e64, 0}, - {M, 1, "[drm:ironlake_init_pch_refclk], has_panel 1 has_lvds 0 " "has_pch_edp 0has_cpu_edp 1 has_ck505 0", 0x0, 0xcf8e64, 0}, - {R, 1, "", PCH_DREF_CONTROL, 0x00000000, 0}, - {M, 1, "[drm:ironlake_init_pch_refclk], Using SSC on panel", 0x0, 0xcf8e64, 0}, - {W, 1, "", PCH_DREF_CONTROL, DREF_SSC_SOURCE_ENABLE | DREF_NONSPREAD_SOURCE_ENABLE | DREF_SSC1_ENABLE | 0x00001402, 0}, - {R, 1, "", PCH_DREF_CONTROL, DREF_SSC_SOURCE_ENABLE | DREF_NONSPREAD_SOURCE_ENABLE | DREF_SSC1_ENABLE | 0x00001402, 200}, - {M, 1, "[drm:ironlake_init_pch_refclk], Using SSC on eDP", 0x0, 0xcf8e64, 0}, - {W, 1, "", PCH_DREF_CONTROL, DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD | DREF_SSC_SOURCE_ENABLE | DREF_NONSPREAD_SOURCE_ENABLE | DREF_SSC1_ENABLE | 0x00005402, 0}, - {R, 1, "", PCH_DREF_CONTROL, DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD | DREF_SSC_SOURCE_ENABLE | DREF_NONSPREAD_SOURCE_ENABLE | DREF_SSC1_ENABLE | 0x00005402, 200}, - {W, 1, "", ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE | 0x10000000, 0}, - {W, 1, "", WM3_LP_ILK, ( /* WMx_LP_LATENCY */ 0x0 << 24) | ( /* WMx_LP_FBC */ 0x0 << 20) | ( /* WMx_LP_SR */ 0x0 << 8) | ( /* WMx_LP_CURSOR */ 0x0 << 0) | 0x00000000, 0}, - {W, 1, "", WM2_LP_ILK, ( /* WMx_LP_LATENCY */ 0x0 << 24) | ( /* WMx_LP_FBC */ 0x0 << 20) | ( /* WMx_LP_SR */ 0x0 << 8) | ( /* WMx_LP_CURSOR */ 0x0 << 0) | 0x00000000, 0}, - {W, 1, "", WM1_LP_ILK, ( /* WMx_LP_LATENCY */ 0x0 << 24) | ( /* WMx_LP_FBC */ 0x0 << 20) | ( /* WMx_LP_SR */ 0x0 << 8) | ( /* WMx_LP_CURSOR */ 0x0 << 0) | 0x00000000, 0}, - {W, 1, "", 0x9404, 0x00002000, 0}, - {W, 1, "", ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE | 0x10000000, 0}, - {W, 1, "", IVB_CHICKEN3, 0x00000024, 0}, - {W, 1, "", GEN7_COMMON_SLICE_CHICKEN1, 0x04000400, 0}, - {W, 1, "", 0xb01c, 0x3c4fff8c, 0}, - {W, 1, "", GEN7_L3_CHICKEN_MODE_REGISTER, 0x20000000, 0}, - {R, 1, "", GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, 0x00000000, 0}, - {W, 1, "", GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, 0x00000800, 0}, - {R, 1, "", _DSPACNTR, ( /* DISPPLANE_SEL_PIPE(0=A,1=B) */ 0x0 << 24) | 0x00000000, 0}, - {W, 1, "", _DSPACNTR, ( /* DISPPLANE_SEL_PIPE(0=A,1=B) */ 0x0 << 24) | DISPPLANE_TRICKLE_FEED_DISABLE /* Ironlake */ | 0x00004000, 0}, - {R, 1, "", _DSPAADDR, 0x00000000, 0}, - {W, 1, "", _DSPAADDR, 0x00000000, 0}, - {R, 1, "", _DSPASIZE + 0xc, 0x00000000, 0}, - {W, 1, "", _DSPASIZE + 0xc, 0x00000000, 0}, - {R, 1, "", _DSPBCNTR, 0x00000000, 0}, - {W, 1, "", _DSPBCNTR, 0x00004000, 0}, - {R, 1, "", _DSPBADDR, 0x00000000, 0}, - {W, 1, "", _DSPBADDR, 0x00000000, 0}, - {R, 1, "", _DSPBSURF, 0x00000000, 0}, - {W, 1, "", _DSPBSURF, 0x00000000, 0}, - {R, 1, "", _DVSACNTR, 0x00000000, 0}, - {W, 1, "", _DVSACNTR, DVS_TRICKLE_FEED_DISABLE | 0x00004000, 0}, - {R, 1, "", _DVSALINOFF, 0x00000000, 0}, - {W, 1, "", _DVSALINOFF, 0x00000000, 0}, - {R, 1, "", _DVSASURF, 0x00000000, 0}, - {W, 1, "", _DVSASURF, 0x00000000, 0}, - {W, 1, "", SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE | 0x20000000, 0}, - {R, 1, "", SOUTH_CHICKEN2, 0x00000000, 0}, - {W, 1, "", SOUTH_CHICKEN2, DPLS_EDP_PPS_FIX_DIS | 0x00000001, 0}, - {W, 1, "", _TRANSA_CHICKEN2, 0x80000000, 0}, - {W, 1, "", _TRANSB_CHICKEN2, TRANS_CHICKEN2_TIMING_OVERRIDE | 0x80000000, 0}, - {M, 1, "[drm:drm_edid_to_eld], ELD:no CEA Extension found", 0x0, 0xcf8e64, 0}, - {M, 1, "[drm:drm_helper_probe_single_connector_modes], " "[CONNECTOR:6:eDP-1]probed modes :", 0x0, 0xcf8e64, 0}, - {M, 1, "[drm:drm_mode_debug_printmodeline],Modeline 0:\"2560x1700\" " "60 285250 2560 2608 2640 2720 1700 1703 1713 17490x48 0xa", 0x0, 0xcf8e64, 0}, - {M, 1, "[drm:drm_setup_crtcs], ", 0x0, 0xcf8e64, 0}, - {M, 1, "[drm:drm_enable_connectors], connector 6 enabled? yes", 0x0, 0xcf8e64, 0}, - {M, 1, "[drm:drm_setup_crtcs], picking CRTCs for 8192x8192 config", 0x0, 0xcf8e64, 0}, - {M, 1, "[drm:drm_setup_crtcs], desired mode 2560x1700 set on crtc 3", 0x0, 0xcf8e64, 0}, - {M, 1, "[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:6:eDP-1]", 0x0, 0xcf8e64, 0}, - {M, 1, "[drm:intel_dp_detect], DPCD:110a8441000001c0", 0x0, 0xcf8e64, 0}, - {M, 1, "[drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on", 0x0, 0xcf8e64, 0}, - {M, 1, "[drm:intel_dp_detect], DPCD:110a8441000001c0", 0x0, 0xcf8e64, 0}, - {M, 1, "[drm:drm_enable_connectors], connector 6 enabled? yes", 0x0, 0xcf8e64, 0}, - {M, 1, "[drm:intel_get_load_detect_pipe], [CONNECTOR:6:eDP-1],[ENCODER:7:TMDS-7]", 0x0, 0xcf8e64, 0}, - {M, 1, "[drm:intel_dp_mode_fixup], Display port link bw 0a lane count 4clock 270000", 0x0, 0xcf8e64, 0}, - {M, 1, "[drm:drm_crtc_helper_set_mode], [CRTC:3]", 0x0, 0xcf8e64, 0}, - {R, 1, "", PCH_PP_STATUS, 0x00000000, 0}, - {R, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | EDP_FORCE_VDD | 0xabcd0008, 0}, - {R, 1, "", PCH_PP_STATUS, 0x00000000, 0}, - {R, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | EDP_FORCE_VDD | 0xabcd0008, 0}, - {I,}, - {R, 1, "", DP_A, DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0 | DP_PORT_WIDTH_1 | DP_PLL_FREQ_270MHZ | DP_SYNC_VS_HIGH | DP_SYNC_HS_HIGH | DP_DETECTED | 0x0000001c, 0}, - {M, 1, "[drm:ironlake_edp_panel_vdd_off], Turn eDP VDD off 1", 0x0, 0xcf8e64, 0}, - {R, 2, "", PCH_DP_D, 0x00000004, 0}, - {R, 1, "", _PIPEACONF, ( /* PIPECONF_FRAME_START_DELAY_MASK */ 0x0 << 27) | PIPECONF_BPP_8 | PIPECONF_DITHER_TYPE_SP | 0x00000000, 0}, - {W, 1, "", _PIPEACONF, ( /* PIPECONF_FRAME_START_DELAY_MASK */ 0x0 << 27) | PIPECONF_BPP_6 | PIPECONF_DITHER_TYPE_SP | 0x00000040, 0}, - {R, 1, "", _PIPEACONF, ( /* PIPECONF_FRAME_START_DELAY_MASK */ 0x0 << 27) | PIPECONF_BPP_6 | PIPECONF_DITHER_TYPE_SP | 0x00000040, 0}, - {M, 1, "[drm:ironlake_crtc_mode_set], Mode for pipe 0:", 0x0, 0xcf8e64, 0}, - {M, 1, "[drm:drm_mode_debug_printmodeline],Modeline 0:\"2560x1700\" " "60 285250 2560 2608 2640 2720 1700 1703 1713 1749 0x48 0xa", 0x0, 0xcf8e64, 0}, - {W, 1, "", _TRANSA_DATA_M1, 0x00000000, 0}, - {W, 1, "", _TRANSA_DATA_N1, 0x00000000, 0}, - {W, 1, "", _TRANSA_DP_LINK_M1, 0x00000000, 0}, - {W, 1, "", _TRANSA_DP_LINK_N1, 0x00000000, 0}, - {W, 1, "", _PCH_FPA1, 0x00020e08, 0}, - {W, 1, "", _VSYNCSHIFT_A, 0x00000000, 0}, - {W, 1, "", _HTOTAL_A, 0x0a9f09ff, 0}, - {W, 1, "", _HBLANK_A, 0x0a9f09ff, 0}, - {W, 1, "", _HSYNC_A, 0x0a4f0a2f, 0}, - {W, 1, "", _VTOTAL_A, 0x06d406a3, 0}, - {W, 1, "", _VBLANK_A, 0x06d406a3, 0}, - {W, 1, "", _VSYNC_A, 0x06b006a6, 0}, - {W, 1, "", _PIPEASRC, 0x09ff06a3, 0}, - {W, 1, "", _PIPEA_DATA_M1, 0x7e4e58a4, 0}, - {W, 1, "", _PIPEA_DATA_N1, 0x0083d600, 0}, - {W, 1, "", _PIPEA_LINK_M1, 0x00045a42, 0}, - {W, 1, "", _PIPEA_LINK_N1, 0x00041eb0, 0}, - {M, 1, "[drm:ironlake_set_pll_edp], eDP PLL enable for clock 270000", 0x0, 0xcf8e64, 0}, - {R, 1, "", DP_A, DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0 | DP_PORT_WIDTH_1 | DP_PLL_FREQ_270MHZ | DP_SYNC_VS_HIGH | DP_SYNC_HS_HIGH | DP_DETECTED | 0x0000001c, 0}, - {W, 1, "", DP_A, DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0 | DP_PORT_WIDTH_1 | DP_PLL_FREQ_270MHZ | DP_SYNC_VS_HIGH | DP_SYNC_HS_HIGH | DP_DETECTED | 0x0000001c, 0}, - {R, 1, "", DP_A, DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0 | DP_PORT_WIDTH_1 | DP_PLL_FREQ_270MHZ | DP_SYNC_VS_HIGH | DP_SYNC_HS_HIGH | DP_DETECTED | 0x0000001c, 500}, - {W, 1, "", _PIPEACONF, ( /* PIPECONF_FRAME_START_DELAY_MASK */ 0x0 << 27) | PIPECONF_BPP_6 | PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP | 0x00000050, 0}, - {R, 1, "", _PIPEACONF, ( /* PIPECONF_FRAME_START_DELAY_MASK */ 0x0 << 27) | PIPECONF_BPP_6 | PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP | 0x00000050, 0}, - {R, 1, "", _PIPEASTAT, 0x00000000, 0}, - {W, 1, "", _PIPEASTAT, PIPE_VBLANK_INTERRUPT_STATUS | 0x00000002, 0}, - {R, 4562, "", _PIPEASTAT, 0x00000000, 0}, - {M, 1, "[drm:intel_wait_for_vblank], vblank wait timed out", 0x0, 0xcf8e64, 0}, - {W, 1, "", _DSPACNTR, DISPPLANE_GAMMA_ENABLE | ( /* DISPPLANE_SEL_PIPE(0=A,1=B) */ 0x0 << 24) | 0x40000000, 0}, - {R, 2, "", _DSPACNTR, DISPPLANE_GAMMA_ENABLE | ( /* DISPPLANE_SEL_PIPE(0=A,1=B) */ 0x0 << 24) | 0x40000000, 0}, - {W, 1, "", _DSPACNTR, DISPPLANE_GAMMA_ENABLE | (DISPPLANE_BGRX888 & 0x18000000) | ( /* DISPPLANE_SEL_PIPE(0=A,1=B) */ 0x0 << 24) | DISPPLANE_TRICKLE_FEED_DISABLE /* Ironlake */ | 0x58004000, 0}, - {M, 1, "[drm:ironlake_update_plane], Writing base 00000000 00000000 0 0 10240", 0x0, 0xcf8e64, 0}, - {W, 1, "", _DSPASTRIDE, 0x00002800, 0}, - {W, 1, "", _DSPASIZE + 0xc, 0x00000000, 0}, - {W, 1, "", _DSPACNTR + 0x24, 0x00000000, 0}, - {W, 1, "", _DSPAADDR, 0x00000000, 0}, - {R, 1, "", _DSPACNTR, DISPPLANE_GAMMA_ENABLE | (DISPPLANE_BGRX888 & 0x18000000) | ( /* DISPPLANE_SEL_PIPE(0=A,1=B) */ 0x0 << 24) | DISPPLANE_TRICKLE_FEED_DISABLE /* Ironlake */ | 0x58004000, 0}, - {R, 1, "", 0x145d10, 0x2010040c, 0}, - {R, 1, "", WM0_PIPEA_ILK, 0x00783818, 0}, - {W, 1, "", WM0_PIPEA_ILK, 0x00183806, 0}, - {M, 1, "[drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 24,cursor:6", 0x0, 0xcf8e64, 0}, - {W, 1, "", WM3_LP_ILK, ( /* WMx_LP_LATENCY */ 0x0 << 24) | ( /* WMx_LP_FBC */ 0x0 << 20) | ( /* WMx_LP_SR */ 0x0 << 8) | ( /* WMx_LP_CURSOR */ 0x0 << 0) | 0x00000000, 0}, - {W, 1, "", WM2_LP_ILK, ( /* WMx_LP_LATENCY */ 0x0 << 24) | ( /* WMx_LP_FBC */ 0x0 << 20) | ( /* WMx_LP_SR */ 0x0 << 8) | ( /* WMx_LP_CURSOR */ 0x0 << 0) | 0x00000000, 0}, - {W, 1, "", WM1_LP_ILK, ( /* WMx_LP_LATENCY */ 0x0 << 24) | ( /* WMx_LP_FBC */ 0x0 << 20) | ( /* WMx_LP_SR */ 0x0 << 8) | ( /* WMx_LP_CURSOR */ 0x0 << 0) | 0x00000000, 0}, - {R, 1, "", 0x145d10, 0x2010040c, 0}, - {M, 1, "[drm:ironlake_check_srwm], watermark 1:display plane 38, fbc lines 3,cursor 6", 0x0, 0xcf8e64, 0}, - {R, 1, "", 0x145d10, 0x2010040c, 0}, - {W, 1, "", WM1_LP_ILK, WMx_LP_SR_EN | ( /* WMx_LP_LATENCY */ 0x4 << 24) | ( /* WMx_LP_FBC */ 0x3 << 20) | ( /* WMx_LP_SR */ 0x26 << 8) | ( /* WMx_LP_CURSOR */ 0x6 << 0) | 0x84302606, 0}, - {R, 1, "", 0x145d10, 0x2010040c, 0}, - {M, 1, "[drm:ironlake_check_srwm], watermark 2:display plane 145, " "fbc lines 3,cursor 6", 0x0, 0xcf8e64, 0}, - {R, 1, "", 0x145d10, 0x2010040c, 0}, - {W, 1, "", WM2_LP_ILK, WMx_LP_SR_EN | ( /* WMx_LP_LATENCY */ 0x10 << 24) | ( /* WMx_LP_FBC */ 0x3 << 20) | ( /* WMx_LP_SR */ 0x91 << 8) | ( /* WMx_LP_CURSOR */ 0x6 << 0) | 0x90309106, 0}, - {R, 1, "", 0x145d10, 0x2010040c, 0}, - {M, 1, "[drm:ironlake_check_srwm], watermark 3:display plane " "288, fbc lines 4,cursor 10", 0x0, 0xcf8e64, 0}, - {R, 1, "", 0x145d10, 0x2010040c, 0}, - {W, 1, "", WM3_LP_ILK, WMx_LP_SR_EN | ( /* WMx_LP_LATENCY */ 0x20 << 24) | ( /* WMx_LP_FBC */ 0x4 << 20) | ( /* WMx_LP_SR */ 0x120 << 8) | ( /* WMx_LP_CURSOR */ 0xa << 0) | 0xa041200a, 0}, - {M, 1, "[drm:drm_crtc_helper_set_mode], [ENCODER:7:TMDS-7]set [MODE:0:2560x1700]", 0x0, 0xcf8e64, 0}, - {M, 1, "[drm:ironlake_edp_pll_on], ", 0x0, 0xcf8e64, 0}, - {R, 1, "", DP_A, DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0 | DP_PORT_WIDTH_1 | DP_PLL_FREQ_270MHZ | DP_SYNC_VS_HIGH | DP_SYNC_HS_HIGH | DP_DETECTED | 0x0000001c, 0}, - {W, 1, "", DP_A, DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0 | DP_PORT_WIDTH_1 | DP_PLL_FREQ_270MHZ | DP_PLL_ENABLE | DP_SYNC_VS_HIGH | DP_SYNC_HS_HIGH | DP_DETECTED | 0x0000401c, 0}, - {R, 1, "", DP_A, DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0 | DP_PORT_WIDTH_1 | DP_PLL_FREQ_270MHZ | DP_PLL_ENABLE | DP_SYNC_VS_HIGH | DP_SYNC_HS_HIGH | DP_DETECTED | 0x0000401c, 200}, - {R, 1, "", DP_A, DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0 | DP_PORT_WIDTH_1 | DP_PLL_FREQ_270MHZ | DP_PLL_ENABLE | DP_SYNC_VS_HIGH | DP_SYNC_HS_HIGH | DP_DETECTED | 0x0000401c, 0}, - {R, 1, "", 0x145d10, 0x2010040c, 0}, - {R, 1, "", WM0_PIPEA_ILK, 0x00183806, 0}, - {W, 1, "", WM0_PIPEA_ILK, 0x00183806, 0}, - {M, 1, "[drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 24,cursor:6", 0x0, 0xcf8e64, 0}, - {W, 1, "", WM3_LP_ILK, ( /* WMx_LP_LATENCY */ 0x0 << 24) | ( /* WMx_LP_FBC */ 0x0 << 20) | ( /* WMx_LP_SR */ 0x0 << 8) | ( /* WMx_LP_CURSOR */ 0x0 << 0) | 0x00000000, 0}, - {W, 1, "", WM2_LP_ILK, ( /* WMx_LP_LATENCY */ 0x0 << 24) | ( /* WMx_LP_FBC */ 0x0 << 20) | ( /* WMx_LP_SR */ 0x0 << 8) | ( /* WMx_LP_CURSOR */ 0x0 << 0) | 0x00000000, 0}, - {W, 1, "", WM1_LP_ILK, ( /* WMx_LP_LATENCY */ 0x0 << 24) | ( /* WMx_LP_FBC */ 0x0 << 20) | ( /* WMx_LP_SR */ 0x0 << 8) | ( /* WMx_LP_CURSOR */ 0x0 << 0) | 0x00000000, 0}, - {R, 1, "", 0x145d10, 0x2010040c, 0}, - {M, 1, "[drm:ironlake_check_srwm], watermark 1:display plane 38, fbc lines 3,cursor 6", 0x0, 0xcf8e64, 0}, - {R, 1, "", 0x145d10, 0x2010040c, 0}, - {W, 1, "", WM1_LP_ILK, WMx_LP_SR_EN | ( /* WMx_LP_LATENCY */ 0x4 << 24) | ( /* WMx_LP_FBC */ 0x3 << 20) |( /* WMx_LP_SR */ 0x26 << 8) | ( /* WMx_LP_CURSOR */ 0x6 << 0) | 0x84302606, 0}, - {R, 1, "", 0x145d10, 0x2010040c, 0}, - {M, 1, "[drm:ironlake_check_srwm], watermark 2:display plane 145, " "fbc lines 3,cursor 6", 0x0, 0xcf8e64, 0}, - {R, 1, "", 0x145d10, 0x2010040c, 0}, - {W, 1, "", WM2_LP_ILK, WMx_LP_SR_EN | ( /* WMx_LP_LATENCY */ 0x10 << 24) | ( /* WMx_LP_FBC */ 0x3 << 20) |( /* WMx_LP_SR */ 0x91 << 8) | ( /* WMx_LP_CURSOR */ 0x6 << 0) | 0x90309106, 0}, - {R, 1, "", 0x145d10, 0x2010040c, 0}, - {M, 1, "[drm:ironlake_check_srwm], watermark 3:display plane 288, " "fbc lines 4,cursor 10", 0x0, 0xcf8e64, 0}, - {R, 1, "", 0x145d10, 0x2010040c, 0}, - {W, 1, "", WM3_LP_ILK, WMx_LP_SR_EN | ( /* WMx_LP_LATENCY */ 0x20 << 24) | ( /* WMx_LP_FBC */ 0x4 << 20) |( /* WMx_LP_SR */ 0x120 << 8) | ( /* WMx_LP_CURSOR */ 0xa << 0) | 0xa041200a, 0}, - {R, 1, "", _FDI_TXA_CTL, 0x00040000, 0}, - {W, 1, "", _FDI_TXA_CTL, 0x00040000, 0}, - {R, 1, "", _FDI_TXA_CTL, 0x00040000, 0}, - {R, 1, "", _FDI_RXA_CTL, 0x00000040, 0}, - {R, 1, "", _PIPEACONF, ( /* PIPECONF_FRAME_START_DELAY_MASK */ 0x0 << 27) | PIPECONF_BPP_6 | PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP | 0x00000050, 0}, - {W, 1, "", _FDI_RXA_CTL, 0x00020040, 0}, - {R, 1, "", _FDI_RXA_CTL, 0x00020040, 100}, - {R, 1, "", SOUTH_CHICKEN1, 0x00000000, 0}, - {W, 2, "", SOUTH_CHICKEN1, 0x00000000, 0}, - {R, 1, "", SOUTH_CHICKEN1, 0x00000000, 0}, - {R, 1, "", _FDI_TXA_CTL, 0x00040000, 0}, - {W, 1, "", _FDI_TXA_CTL, 0x00040000, 0}, - {R, 1, "", _FDI_RXA_CTL, 0x00020040, 0}, - {R, 1, "", _PIPEACONF, ( /* PIPECONF_FRAME_START_DELAY_MASK */ 0x0 << 27) | PIPECONF_BPP_6 | PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP | 0x00000050, 0}, - {W, 1, "", _FDI_RXA_CTL, 0x00020040, 0}, - {R, 1, "", _FDI_RXA_CTL, 0x00020040, 100}, - {P, 1, "Set Palette"}, - {R, 1, "", _PIPEACONF, ( /* PIPECONF_FRAME_START_DELAY_MASK */ 0x0 << 27) | PIPECONF_BPP_6 | PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP | 0x00000050, 0}, - {W, 1, "", _PIPEACONF, PIPECONF_ENABLE | ( /* PIPECONF_FRAME_START_DELAY_MASK */ 0x0 << 27) | PIPECONF_BPP_6 | PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP | 0x80000050, 0}, - {R, 1, "", _PIPEASTAT, 0x00000000, 0}, - {W, 1, "", _PIPEASTAT, PIPE_VBLANK_INTERRUPT_STATUS | 0x00000002, 0}, - {R, 4533, "", _PIPEASTAT, 0x00000000, 0}, - {M, 1, "[drm:intel_wait_for_vblank], vblank wait timed out", 0x0, 0xcf8e64, 0}, - {R, 1, "", _PIPEACONF, PIPECONF_ENABLE | PIPECONF_DOUBLE_WIDE | ( /* PIPECONF_FRAME_START_DELAY_MASK */ 0x0 << 27) | PIPECONF_BPP_6 | PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP |0xc0000050, 0}, - {R, 1, "", _DSPACNTR, DISPPLANE_GAMMA_ENABLE | (DISPPLANE_BGRX888 & 0x18000000) | ( /* DISPPLANE_SEL_PIPE(0=A,1=B) */ 0x0 << 24) | DISPPLANE_TRICKLE_FEED_DISABLE /* Ironlake */ | 0x58004000, 0}, - {W, 1, "", _DSPACNTR, DISPLAY_PLANE_ENABLE | DISPPLANE_GAMMA_ENABLE | (DISPPLANE_BGRX888 & 0x18000000) | ( /* DISPPLANE_SEL_PIPE(0=A,1=B) */ 0x0 << 24) | DISPPLANE_TRICKLE_FEED_DISABLE /* Ironlake */ | 0xd8004000, 0}, - {R, 1, "", _DSPAADDR, 0x00000000, 0}, - {W, 1, "", _DSPAADDR, 0x00000000, 0}, - {R, 1, "", _DSPASIZE + 0xc, 0x00000000, 0}, - {W, 1, "", _DSPASIZE + 0xc, 0x00000000, 0}, - {R, 1, "", _PIPEASTAT, 0x00000000, 0}, - {W, 1, "", _PIPEASTAT, PIPE_VBLANK_INTERRUPT_STATUS | 0x00000002, 0}, - {R, 4392, "", _PIPEASTAT, 0x00000000, 0}, - {M, 1, "[drm:intel_wait_for_vblank], vblank wait timed out", 0x0, 0xcf8e64, 0}, - {M, 1, "[drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on", 0x0, 0xcf8e64, 0}, - {R, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | EDP_FORCE_VDD | 0xabcd0008, 0}, - {M, 1, "[drm:ironlake_edp_panel_on], Turn eDP power on", 0x0, 0xcf8e64, 0}, - {R, 1, "", PCH_PP_STATUS, 0x00000000, 0}, - {M, 1, "[drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle", 0x0, 0xcf8e64, 0}, - {M, 1, "[drm:ironlake_wait_panel_status], R PCH_PP_CONTROL:abcd0008", 0x0, 0xcf8e64, 0}, - {R, 2, "", PCH_PP_STATUS, 0x00000000, 0}, - {R, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | EDP_FORCE_VDD | 0xabcd0008, 0}, - {W, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | EDP_FORCE_VDD | PANEL_POWER_RESET | PANEL_POWER_ON | 0xabcd000b, 0}, - {R, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | EDP_FORCE_VDD | PANEL_POWER_RESET | PANEL_POWER_ON | 0xabcd000b, 0}, - {M, 1, "[drm:ironlake_wait_panel_on], Wait for panel power on", 0x0, 0xcf8e64, 0}, - {M, 1, "[drm:ironlake_wait_panel_status], R PCH_PP_CONTROL:abcd000b", 0x0, 0xcf8e64, 0}, - {R, 4, "", PCH_PP_STATUS, /*undocbit3 | undocbit1 | */ 0x0000000a, 0}, - {R, 16983, "", PCH_PP_STATUS, PP_ON | PP_SEQUENCE_POWER_UP | /*undocbit3 | undocbit1 | */ 0x9000000a, 0}, - {R, 17839, "", PCH_PP_STATUS, PP_ON | PP_SEQUENCE_POWER_UP | /*undocbit3 | undocbit0 | */ 0x90000009, 0}, - {R, 1, "", PCH_PP_STATUS, PP_ON | /*undocbit3 | */ 0x80000008, 0}, - {M, 1, "[drm:ironlake_edp_panel_vdd_off], Turn eDP VDD off 1", 0x0, 0xcf8e64, 0}, - {R, 2, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | EDP_FORCE_VDD | PANEL_POWER_RESET | PANEL_POWER_ON | 0xabcd000b, 0}, - {W, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | PANEL_POWER_RESET | PANEL_POWER_ON | 0xabcd0003, 0}, - {R, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | PANEL_POWER_RESET | PANEL_POWER_ON | 0xabcd0003, 0}, - {M, 1, "[drm:ironlake_panel_vdd_off_sync], R PCH_PP_CONTROL:abcd0003", 0x0, 0xcf8e64, 0}, - {R, 1, "", PCH_PP_STATUS, PP_ON | /*undocbit3 | */ 0x80000008, 0}, - {W, 1, "", DP_A, DP_PORT_EN | DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_2_CPT | DP_PRE_EMPHASIS_0 | (DP_PORT_WIDTH_4 & 0x180000) | DP_ENHANCED_FRAMING | DP_PLL_FREQ_270MHZ | DP_PLL_ENABLE | DP_DETECTED | 0x8e1c4104, 0}, - {R, 1, "", DP_A, DP_PORT_EN | DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_2_CPT | DP_PRE_EMPHASIS_0 | (DP_PORT_WIDTH_4 & 0x180000) | DP_ENHANCED_FRAMING | DP_PLL_FREQ_270MHZ | DP_PLL_ENABLE | DP_DETECTED | 0x8e1c4104, 0}, - {R, 2, "", PCH_PP_STATUS, PP_ON | /*undocbit3 | */ 0x80000008, 0}, - {R, 1, "", DP_A, DP_PORT_EN | DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_2_CPT | (DP_PRE_EMPHASIS_9_5 & 0xc00000) | (DP_PORT_WIDTH_4 & 0x180000) | DP_ENHANCED_FRAMING | DP_PLL_FREQ_270MHZ | DP_PLL_ENABLE | DP_DETECTED | 0x8cdc4104, 0}, - {M, 1, "[drm:intel_dp_link_down], ", 0x0, 0xcf8e64, 0}, - {W, 1, "", DP_A, DP_PORT_EN | DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | DP_PRE_EMPHASIS_0 | (DP_PORT_WIDTH_4 & 0x180000) | DP_ENHANCED_FRAMING | DP_PLL_FREQ_270MHZ | DP_DETECTED | 0x8e1c0004, 0}, - {R, 1, "", DP_A, DP_PORT_EN | DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | DP_PRE_EMPHASIS_0 | (DP_PORT_WIDTH_4 & 0x180000) | DP_ENHANCED_FRAMING | DP_PLL_FREQ_270MHZ | DP_DETECTED | 0x8e1c0004, 100}, - {W, 1, "", DP_A, DP_PORT_EN | DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_IDLE_CPT | DP_PRE_EMPHASIS_0 | (DP_PORT_WIDTH_4 & 0x180000) | DP_ENHANCED_FRAMING | DP_PLL_FREQ_270MHZ | DP_DETECTED | 0x8e1c0204, 0}, - {R, 1, "", DP_A, DP_PORT_EN | DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_IDLE_CPT | DP_PRE_EMPHASIS_0 | (DP_PORT_WIDTH_4 & 0x180000) | DP_ENHANCED_FRAMING | DP_PLL_FREQ_270MHZ | DP_DETECTED | 0x8e1c0204, 0}, - {W, 1, "", DP_A, DP_LINK_TRAIN_PAT_1 | (DP_LINK_TRAIN_OFF_CPT & 0x300) | DP_PRE_EMPHASIS_0 | (DP_PORT_WIDTH_4 & 0x180000) | DP_ENHANCED_FRAMING | DP_PLL_FREQ_270MHZ | DP_DETECTED | 0x0e1c0304, 0}, - {R, 2, "", DP_A, DP_LINK_TRAIN_PAT_1 | (DP_LINK_TRAIN_OFF_CPT & 0x300) | DP_PRE_EMPHASIS_0 | (DP_PORT_WIDTH_4 & 0x180000) | DP_ENHANCED_FRAMING | DP_PLL_FREQ_270MHZ | DP_DETECTED | 0x0e1c0304, 0}, - {R, 2, "", PCH_PP_STATUS, PP_ON | /*undocbit3 | */ 0x80000008, 0}, - {I,}, - {W, 1, "", DP_A, DP_PORT_EN | DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | (DP_PORT_WIDTH_4 & 0x180000) | DP_ENHANCED_FRAMING | DP_PLL_FREQ_270MHZ | DP_PLL_ENABLE | DP_DETECTED | 0x891c4004, 0}, - {R, 1, "", DP_A, DP_PORT_EN | DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | (DP_PORT_WIDTH_4 & 0x180000) | DP_ENHANCED_FRAMING | DP_PLL_FREQ_270MHZ | DP_PLL_ENABLE | DP_DETECTED | 0x891c4004, 0}, - {R, 2, "", PCH_PP_STATUS, PP_ON | /*undocbit3 | */ 0x80000008, 0}, - {I,}, - {R, 2, "", PCH_PP_STATUS, PP_ON | /*undocbit3 | */ 0x80000008, 0}, - {I,}, - {R, 2, "", PCH_PP_STATUS, PP_ON | /*undocbit3 | */ 0x80000008, 0}, - {I,}, - {M, 1, "[drm:intel_dp_start_link_train], clock recovery OK", 0x0, 0x00000000, 0}, - {W, 1, "", DP_A, DP_PORT_EN | DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_2_CPT | (DP_PORT_WIDTH_4 & 0x180000) | DP_ENHANCED_FRAMING | DP_PLL_FREQ_270MHZ | DP_PLL_ENABLE | DP_DETECTED | 0x891c4104, 0}, - {R, 1, "", DP_A, DP_PORT_EN | DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_2_CPT | (DP_PORT_WIDTH_4 & 0x180000) | DP_ENHANCED_FRAMING | DP_PLL_FREQ_270MHZ | DP_PLL_ENABLE | DP_DETECTED | 0x891c4104, 0}, - {R, 2, "", PCH_PP_STATUS, PP_ON | /* undocbit3 | */ 0x80000008, 0}, - {I,}, - {R, 2, "", PCH_PP_STATUS, PP_ON | /* undocbit3 | */ 0x80000008, 0}, - {I,}, - {R, 2, "", PCH_PP_STATUS, PP_ON | /* undocbit3 | */ 0x80000008, 0}, - {I,}, - {W, 1, "", DP_A, DP_PORT_EN | DP_LINK_TRAIN_PAT_1 | (DP_LINK_TRAIN_OFF_CPT & 0x300) | (DP_PORT_WIDTH_4 & 0x180000) | DP_ENHANCED_FRAMING | DP_PLL_FREQ_270MHZ | DP_PLL_ENABLE | DP_DETECTED | 0x891c4304, 0}, - {R, 1, "", DP_A, DP_PORT_EN | DP_LINK_TRAIN_PAT_1 | (DP_LINK_TRAIN_OFF_CPT & 0x300) | (DP_PORT_WIDTH_4 & 0x180000) | DP_ENHANCED_FRAMING | DP_PLL_FREQ_270MHZ | DP_PLL_ENABLE | DP_DETECTED | 0x891c4304, 0}, - {R, 2, "", PCH_PP_STATUS, PP_ON | /* undocbit3 | */ 0x80000008, 0}, - {I,}, - {M, 1, "[drm:ironlake_edp_backlight_on], ", 0x0, 0x00000000, 0}, - {R, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | PANEL_POWER_RESET | PANEL_POWER_ON | 0xabcd0003, 0}, - {W, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | EDP_BLC_ENABLE | PANEL_POWER_RESET | PANEL_POWER_ON | 0xabcd0007, 0}, - {R, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | EDP_BLC_ENABLE | PANEL_POWER_RESET | PANEL_POWER_ON | 0xabcd0007, 0}, - {R, 1, "", _PIPEADSL, 0x00000633, 500}, - {R, 1, "", _PIPEADSL, 0x00000652, 0}, - {R, 1, "", _PIPEASTAT, 0x00000000, 0}, - {W, 1, "", _PIPEASTAT, PIPE_VBLANK_INTERRUPT_STATUS | 0x00000002, 0}, - {R, 5085, "", _PIPEASTAT, 0x00000000, 0}, - {M, 1, "[drm:intel_wait_for_vblank], vblank wait timed out", 0x0, 0xcf8e64, 0}, - {M, 1, "[drm:intel_dp_mode_fixup], Display port link bw 0a lane count 4clock 270000", 0x0, 0xcf8e64, 0}, - {M, 1, "[drm:drm_crtc_helper_set_mode], [CRTC:3]", 0x0, 0xcf8e64, 0}, - {I,}, -}; - -int niodefs = ARRAY_SIZE(iodefs); diff --git a/src/mainboard/google/link/i915io.h b/src/mainboard/google/link/i915io.h deleted file mode 100644 index c7663d4db0..0000000000 --- a/src/mainboard/google/link/i915io.h +++ /dev/null @@ -1,82 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include - -/* things that are, strangely, not defined anywhere? */ -#define PCH_PP_UNLOCK 0xabcd0000 -#define WMx_LP_SR_EN (1 << 31) - -/* Google Link-specific defines */ -/* how many 4096-byte pages do we need for the framebuffer? - * There are 32 bits per pixel, or 4 bytes, - * which means 1024 pixels per page. - * HencetThere are 4250 GTTs on Link: - * 2650 (X) * 1700 (Y) pixels / 1024 pixels per page. - */ -#define FRAME_BUFFER_PAGES ((2560*1700)/1024) -#define FRAME_BUFFER_BYTES (FRAME_BUFFER_PAGES*4096) - -/* One-letter commands for code not meant to be ready for humans. - * The code was generated by a set of programs/scripts. - * M print out a kernel message - * R read a register. We do these mainly to ensure that if hardware wanted - * the register read, it was read; also, in debug, we can see what was expected - * and what was found. This has proven *very* useful to get this debugged. - * The udelay, if non-zero, will make sure there is a - * udelay() call with the value. - * The count is from the kernel and tells us how many times this read was done. - * Also useful for debugging and the state - * machine uses the info to drive a poll. - * W Write a register - * V set verbosity. It's a bit mask. - * 0 -> nothing - * 1 -> print kernel messages - * 2 -> print IO ops - * 4 -> print the number of times we spin on a register in a poll - * 8 -> restore whatever the previous verbosity level was - * (only one deep stack) - * - * Again, this is not really meant for human consumption. There is not a poll - * operator as such because, sometimes, there is a read/write/read where the - * second read is a poll, and this chipset is so touchy I'm reluctant to move - * things around and/or delete too many reads. - */ -#define M 1 -#define R 2 -#define W 4 -#define V 8 -#define I 16 -#define P 32 - -struct iodef { - unsigned char op; - unsigned int count; - const char *msg; - unsigned long addr; - unsigned long data; - unsigned long udelay; -}; - -/* i915.c */ -unsigned long io_i915_READ32(unsigned long addr); -void io_i915_WRITE32(unsigned long val, unsigned long addr); - -/* intel_dp.c */ -u32 pack_aux(u32 *src, int src_bytes); -void unpack_aux(u32 src, u32 *dst, int dst_bytes); -int intel_dp_aux_ch(u32 ch_ctl, u32 ch_data, u32 *send, int send_bytes, - u32 *recv, int recv_size); diff --git a/src/mainboard/google/link/intel_dp.c b/src/mainboard/google/link/intel_dp.c deleted file mode 100644 index f74743aab1..0000000000 --- a/src/mainboard/google/link/intel_dp.c +++ /dev/null @@ -1,166 +0,0 @@ -/* - * Copyright 2013 Google Inc. - * Copyright © 2008 Intel Corporation - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS - * IN THE SOFTWARE. - * - * Authors: - * Keith Packard - * - */ - -#include -#include -#include -#include "i915io.h" - -u32 -pack_aux(u32 *src32, int src_bytes) -{ - u8 *src = (u8 *)src32; - int i; - u32 v = 0; - - if (src_bytes > 4) - src_bytes = 4; - for (i = 0; i < src_bytes; i++) - v |= ((u32) src[i]) << ((3-i) * 8); - return v; -} - -void -unpack_aux(u32 src, u32 *dst32, int dst_bytes) -{ - u8 *dst = (u8 *)dst32; - - int i; - if (dst_bytes > 4) - dst_bytes = 4; - for (i = 0; i < dst_bytes; i++) - dst[i] = src >> ((3-i) * 8); -} - -int -intel_dp_aux_ch(u32 ch_ctl, u32 ch_data, u32 *send, int send_bytes, - u32 *recv, int recv_size) -{ - int i; - int recv_bytes; - u32 status; - u32 aux_clock_divider; - int try, precharge = 5; - - /* The clock divider is based off the hrawclk, - * and would like to run at 2MHz. So, take the - * hrawclk value and divide by 2 and use that - * - * Note that PCH attached eDP panels should use a 125MHz input - * clock divider. - */ - /* 200 on link */ - aux_clock_divider = 200; /* SNB & IVB eDP input clock at 400Mhz */ - - /* Try to wait for any previous AUX channel activity */ - for (try = 0; try < 3; try++) { - status = io_i915_READ32(ch_ctl); - if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0) - break; - udelay(1000); - } - - if (try == 3) { - printk(BIOS_SPEW, "[000000.0] [drm:%s], ", __func__); - printk(BIOS_SPEW, "dp_aux_ch not started status 0x%08lx\n", - io_i915_READ32(ch_ctl)); - return -1; - } - - /* Must try at least 3 times according to DP spec */ - for (try = 0; try < 5; try++) { - /* Load the send data into the aux channel data registers */ - for (i = 0; i < send_bytes; i += 4) - io_i915_WRITE32(send[i], ch_data + i); - - /* Send the command and wait for it to complete */ - io_i915_WRITE32( - DP_AUX_CH_CTL_SEND_BUSY | - DP_AUX_CH_CTL_TIME_OUT_400us | - (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | - (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) | - (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) | - DP_AUX_CH_CTL_DONE | - DP_AUX_CH_CTL_TIME_OUT_ERROR | - DP_AUX_CH_CTL_RECEIVE_ERROR, ch_ctl); - for (;;) { - status = io_i915_READ32(ch_ctl); - if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0) - break; - udelay(100); - } - - /* Clear done status and any errors */ - io_i915_WRITE32( - status | - DP_AUX_CH_CTL_DONE | - DP_AUX_CH_CTL_TIME_OUT_ERROR | - DP_AUX_CH_CTL_RECEIVE_ERROR, ch_ctl); - - if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR | - DP_AUX_CH_CTL_RECEIVE_ERROR)) - continue; - if (status & DP_AUX_CH_CTL_DONE) - break; - } - - if ((status & DP_AUX_CH_CTL_DONE) == 0) { - printk(BIOS_SPEW, "[000000.0] [drm:%s], ", __func__); - printk(BIOS_SPEW, "dp_aux_ch not done status 0x%08x\n", status); - return -1; - } - - /* Check for timeout or receive error. - * Timeouts occur when the sink is not connected - */ - if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) { - printk(BIOS_SPEW, "[000000.0] [drm:%s], ", __func__); - printk(BIOS_SPEW, "dp_aux_ch receive error status 0x%08x\n", status); - return -1; - } - - /* Timeouts occur when the device isn't connected, so they're - * "normal" -- don't fill the kernel log with these */ - if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) { - printk(BIOS_SPEW, "[000000.0] [drm:%s], ", __func__); - printk(BIOS_SPEW, "dp_aux_ch timeout status 0x%08x\n", status); - return -1; - } - - /* Unload any bytes sent back from the other side */ - recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >> - DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT); - if (recv_bytes > recv_size) - recv_bytes = recv_size; - - for (i = 0; i < recv_bytes; i += 4) - unpack_aux(io_i915_READ32(ch_data + i), - recv + i, recv_bytes - i); - - return recv_bytes; -} From 60a0a3d629d91f8909e5209753baf8f4b6bcc1f5 Mon Sep 17 00:00:00 2001 From: Evgeny Zinoviev Date: Thu, 30 May 2019 04:16:18 +0300 Subject: [PATCH 271/331] ec/lenovo/h8: Fix method name in ACPI code Fix a typo. Change-Id: I2ab624eccd9bad36908df7fd739828e9ed8a4f62 Signed-off-by: Evgeny Zinoviev Reviewed-on: https://review.coreboot.org/c/coreboot/+/33100 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph --- src/ec/lenovo/h8/acpi/lid.asl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/ec/lenovo/h8/acpi/lid.asl b/src/ec/lenovo/h8/acpi/lid.asl index a8e17cb785..c9142f5ff9 100644 --- a/src/ec/lenovo/h8/acpi/lid.asl +++ b/src/ec/lenovo/h8/acpi/lid.asl @@ -28,7 +28,7 @@ Device(LID) { Name(_HID, "PNP0C0D") - Method(_LId, 0, NotSerialized) + Method(_LID, 0, NotSerialized) { return (LIDS) } From d44d4f0f4eca026f81a3b2a21518d7524235f144 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Tue, 28 May 2019 09:47:38 +0200 Subject: [PATCH 272/331] mb/lenovo/*: Remove useless smihandler code This code to handle the brightness from SMM is copied from the Lenovo Thinkpad X60 code, but does not work on later generation. The PCI device it tries to address does not even exist on those devices. Change-Id: Ia959eb5b747846048396e66d4c926c96c27f3878 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/33138 Reviewed-by: Patrick Rudolph Reviewed-by: Nico Huber Tested-by: build bot (Jenkins) --- src/mainboard/lenovo/t420s/smihandler.c | 30 ------------------------- src/mainboard/lenovo/t430s/smihandler.c | 30 ------------------------- src/mainboard/lenovo/t520/smihandler.c | 30 ------------------------- src/mainboard/lenovo/t530/smihandler.c | 30 ------------------------- src/mainboard/lenovo/x220/smihandler.c | 30 ------------------------- 5 files changed, 150 deletions(-) diff --git a/src/mainboard/lenovo/t420s/smihandler.c b/src/mainboard/lenovo/t420s/smihandler.c index be4228dc90..2713725b36 100644 --- a/src/mainboard/lenovo/t420s/smihandler.c +++ b/src/mainboard/lenovo/t420s/smihandler.c @@ -27,23 +27,6 @@ #define GPE_EC_SCI 1 #define GPE_EC_WAKE 13 -static void mainboard_smi_brightness_up(void) -{ - u8 value; - - if ((value = pci_read_config8(PCI_DEV(0, 2, 1), 0xf4)) < 0xf0) - pci_write_config8(PCI_DEV(0, 2, 1), 0xf4, (value + 0x10) | 0xf); -} - -static void mainboard_smi_brightness_down(void) -{ - u8 value; - - if ((value = pci_read_config8(PCI_DEV(0, 2, 1), 0xf4)) > 0x10) - pci_write_config8(PCI_DEV(0, 2, 1), 0xf4, - (value - 0x10) & 0xf0); -} - static void mainboard_smi_handle_ec_sci(void) { u8 status = inb(EC_SC); @@ -54,19 +37,6 @@ static void mainboard_smi_handle_ec_sci(void) event = ec_query(); printk(BIOS_DEBUG, "EC event %02x\n", event); - - switch (event) { - case 0x14: - /* brightness up */ - mainboard_smi_brightness_up(); - break; - case 0x15: - /* brightness down */ - mainboard_smi_brightness_down(); - break; - default: - break; - } } void mainboard_smi_gpi(u32 gpi_sts) diff --git a/src/mainboard/lenovo/t430s/smihandler.c b/src/mainboard/lenovo/t430s/smihandler.c index 876d81c0d7..2810e5ae91 100644 --- a/src/mainboard/lenovo/t430s/smihandler.c +++ b/src/mainboard/lenovo/t430s/smihandler.c @@ -27,23 +27,6 @@ #define GPE_EC_SCI 1 #define GPE_EC_WAKE 13 -static void mainboard_smi_brightness_up(void) -{ - u8 value = pci_read_config8(PCI_DEV(0, 2, 1), 0xf4); - - if (value < 0xf0) - pci_write_config8(PCI_DEV(0, 2, 1), 0xf4, (value + 0x10) | 0xf); -} - -static void mainboard_smi_brightness_down(void) -{ - u8 value = pci_read_config8(PCI_DEV(0, 2, 1), 0xf4); - - if (value > 0x10) - pci_write_config8(PCI_DEV(0, 2, 1), 0xf4, - (value - 0x10) & 0xf0); -} - static void mainboard_smi_handle_ec_sci(void) { u8 status = inb(EC_SC); @@ -54,19 +37,6 @@ static void mainboard_smi_handle_ec_sci(void) event = ec_query(); printk(BIOS_DEBUG, "EC event %02x\n", event); - - switch (event) { - case 0x14: - /* brightness up */ - mainboard_smi_brightness_up(); - break; - case 0x15: - /* brightness down */ - mainboard_smi_brightness_down(); - break; - default: - break; - } } void mainboard_smi_gpi(u32 gpi_sts) diff --git a/src/mainboard/lenovo/t520/smihandler.c b/src/mainboard/lenovo/t520/smihandler.c index 88ce5046fc..46ad664c3c 100644 --- a/src/mainboard/lenovo/t520/smihandler.c +++ b/src/mainboard/lenovo/t520/smihandler.c @@ -27,23 +27,6 @@ #define GPE_EC_SCI 1 #define GPE_EC_WAKE 13 -static void mainboard_smi_brightness_up(void) -{ - u8 value; - - if ((value = pci_read_config8(PCI_DEV(0, 2, 1), 0xf4)) < 0xf0) - pci_write_config8(PCI_DEV(0, 2, 1), 0xf4, (value + 0x10) | 0xf); -} - -static void mainboard_smi_brightness_down(void) -{ - u8 value; - - if ((value = pci_read_config8(PCI_DEV(0, 2, 1), 0xf4)) > 0x10) - pci_write_config8(PCI_DEV(0, 2, 1), 0xf4, - (value - 0x10) & 0xf0); -} - static void mainboard_smi_handle_ec_sci(void) { u8 status = inb(EC_SC); @@ -54,19 +37,6 @@ static void mainboard_smi_handle_ec_sci(void) event = ec_query(); printk(BIOS_DEBUG, "EC event %02x\n", event); - - switch (event) { - case 0x14: - /* brightness up */ - mainboard_smi_brightness_up(); - break; - case 0x15: - /* brightness down */ - mainboard_smi_brightness_down(); - break; - default: - break; - } } void mainboard_smi_gpi(u32 gpi_sts) diff --git a/src/mainboard/lenovo/t530/smihandler.c b/src/mainboard/lenovo/t530/smihandler.c index bf0f81fc57..46ad664c3c 100644 --- a/src/mainboard/lenovo/t530/smihandler.c +++ b/src/mainboard/lenovo/t530/smihandler.c @@ -27,23 +27,6 @@ #define GPE_EC_SCI 1 #define GPE_EC_WAKE 13 -static void mainboard_smi_brightness_up(void) -{ - u8 value; - - if ((value = pci_read_config8(PCI_DEV(0, 2, 1), 0xf4)) < 0xf0) - pci_write_config8(PCI_DEV(0, 2, 1), 0xf4, (value + 0x10) | 0xf); -} - -static void mainboard_smi_brightness_down(void) -{ - u8 value; - - if ((value = pci_read_config8(PCI_DEV(0, 2, 1), 0xf4)) > 0x10) - pci_write_config8(PCI_DEV(0, 2, 1), 0xf4, - (value - 0x10) & 0xf0); -} - static void mainboard_smi_handle_ec_sci(void) { u8 status = inb(EC_SC); @@ -54,19 +37,6 @@ static void mainboard_smi_handle_ec_sci(void) event = ec_query(); printk(BIOS_DEBUG, "EC event %02x\n", event); - - switch (event) { - case 0x14: - /* brightness up */ - mainboard_smi_brightness_up(); - break; - case 0x15: - /* brightness down */ - mainboard_smi_brightness_down(); - break; - default: - break; - } } void mainboard_smi_gpi(u32 gpi_sts) diff --git a/src/mainboard/lenovo/x220/smihandler.c b/src/mainboard/lenovo/x220/smihandler.c index bf0f81fc57..46ad664c3c 100644 --- a/src/mainboard/lenovo/x220/smihandler.c +++ b/src/mainboard/lenovo/x220/smihandler.c @@ -27,23 +27,6 @@ #define GPE_EC_SCI 1 #define GPE_EC_WAKE 13 -static void mainboard_smi_brightness_up(void) -{ - u8 value; - - if ((value = pci_read_config8(PCI_DEV(0, 2, 1), 0xf4)) < 0xf0) - pci_write_config8(PCI_DEV(0, 2, 1), 0xf4, (value + 0x10) | 0xf); -} - -static void mainboard_smi_brightness_down(void) -{ - u8 value; - - if ((value = pci_read_config8(PCI_DEV(0, 2, 1), 0xf4)) > 0x10) - pci_write_config8(PCI_DEV(0, 2, 1), 0xf4, - (value - 0x10) & 0xf0); -} - static void mainboard_smi_handle_ec_sci(void) { u8 status = inb(EC_SC); @@ -54,19 +37,6 @@ static void mainboard_smi_handle_ec_sci(void) event = ec_query(); printk(BIOS_DEBUG, "EC event %02x\n", event); - - switch (event) { - case 0x14: - /* brightness up */ - mainboard_smi_brightness_up(); - break; - case 0x15: - /* brightness down */ - mainboard_smi_brightness_down(); - break; - default: - break; - } } void mainboard_smi_gpi(u32 gpi_sts) From 38b7445ad240f7504b95e3e0c63122418e3ff159 Mon Sep 17 00:00:00 2001 From: Jacob Garber Date: Fri, 31 May 2019 14:43:19 -0600 Subject: [PATCH 273/331] mb/google/poppy/variants/nami: Add fallthrough comment This fallthrough is intentional (see commit 2257a35862 - Perform PL2 setting for syndra), so add a comment to make that explicit. Change-Id: I57fe1e08f59aed12544cd2a71f1e0464f432f03b Signed-off-by: Jacob Garber Found-by: Coverity CID 1397063 Reviewed-on: https://review.coreboot.org/c/coreboot/+/33156 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/mainboard/google/poppy/variants/nami/mainboard.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mainboard/google/poppy/variants/nami/mainboard.c b/src/mainboard/google/poppy/variants/nami/mainboard.c index cc87136520..23870175b7 100644 --- a/src/mainboard/google/poppy/variants/nami/mainboard.c +++ b/src/mainboard/google/poppy/variants/nami/mainboard.c @@ -252,6 +252,7 @@ void variant_devtree_update(void) case SKU_6_SYNDRA: case SKU_7_SYNDRA: pl2_id = PL2_ID_SONA_SYNDRA; + /* fallthrough */ case SKU_0_VAYNE: case SKU_1_VAYNE: case SKU_2_VAYNE: From 7da638c20e4c56bc103be23216862e265b3ca8b1 Mon Sep 17 00:00:00 2001 From: Jacob Garber Date: Thu, 30 May 2019 16:11:41 -0600 Subject: [PATCH 274/331] mb/sifive/hifive-unleashed: Check for errors in fixup_fdt It is possible that cbfs_boot_map_with_leak() and malloc() could fail, so detect those conditions and print error messages if they do. Change-Id: I34951da0b73028c4c89446cb1779a72422997325 Signed-off-by: Jacob Garber Found-by: Coverity CID 1399147 Reviewed-on: https://review.coreboot.org/c/coreboot/+/33134 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph Reviewed-by: Xiang Wang --- src/mainboard/sifive/hifive-unleashed/fixup_fdt.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/src/mainboard/sifive/hifive-unleashed/fixup_fdt.c b/src/mainboard/sifive/hifive-unleashed/fixup_fdt.c index ea58e02b2e..8ac6ff1208 100644 --- a/src/mainboard/sifive/hifive-unleashed/fixup_fdt.c +++ b/src/mainboard/sifive/hifive-unleashed/fixup_fdt.c @@ -15,6 +15,7 @@ #include #include +#include #include #include #include @@ -86,6 +87,11 @@ static void fixup_fdt(void *unused) /* load flat dt from cbfs */ fdt_rom = cbfs_boot_map_with_leak("fallback/DTB", CBFS_TYPE_RAW, NULL); + if (fdt_rom == NULL) { + printk(BIOS_ERR, "Unable to load fallback/DTB from CBFS\n"); + return; + } + /* Expand DT into a tree */ tree = fdt_unflatten(fdt_rom); @@ -95,6 +101,12 @@ static void fixup_fdt(void *unused) /* convert the tree to a flat dt */ void *dt = malloc(dt_flat_size(tree)); + + if (dt == NULL) { + printk(BIOS_ERR, "Unable to allocate memory for flat device tree\n"); + return; + } + dt_flatten(tree, dt); /* update HLS */ From f7f90f7c3f35f03efe037c4e079420e88a317610 Mon Sep 17 00:00:00 2001 From: Jacob Garber Date: Tue, 28 May 2019 15:37:37 -0600 Subject: [PATCH 275/331] drivers/intel/fsp1_1: Exit cleanly if FSP not found Instead of dereferencing a null pointer, print a nice message and exit cleanly if the FSP isn't found in the CBFS. Change-Id: I761e7febc7cec5bd2ef3af214bc51777ee5c313d Signed-off-by: Jacob Garber Found-by: Coverity CID 1401467, 1401717 Reviewed-on: https://review.coreboot.org/c/coreboot/+/33049 Reviewed-by: Furquan Shaikh Tested-by: build bot (Jenkins) --- src/drivers/intel/fsp1_1/car.c | 15 ++++++--------- 1 file changed, 6 insertions(+), 9 deletions(-) diff --git a/src/drivers/intel/fsp1_1/car.c b/src/drivers/intel/fsp1_1/car.c index 82dc320e0e..41a02f33b9 100644 --- a/src/drivers/intel/fsp1_1/car.c +++ b/src/drivers/intel/fsp1_1/car.c @@ -160,17 +160,14 @@ void mainboard_romstage_entry(unsigned long bist) { /* Need to locate the current FSP_INFO_HEADER. The cache-as-ram * is still enabled. We can directly access work buffer here. */ - FSP_INFO_HEADER *fih; struct prog fsp = PROG_INIT(PROG_REFCODE, "fsp.bin"); - if (prog_locate(&fsp)) { - fih = NULL; - printk(BIOS_ERR, "Unable to locate %s\n", prog_name(&fsp)); - } else { - /* This leaks a mapping which this code assumes is benign as - * the flash is memory mapped CPU's address space. */ - fih = find_fsp((uintptr_t)rdev_mmap_full(prog_rdev(&fsp))); - } + if (prog_locate(&fsp)) + die_with_post_code(POST_INVALID_CBFS, "Unable to locate fsp.bin"); + + /* This leaks a mapping which this code assumes is benign as + * the flash is memory mapped CPU's address space. */ + FSP_INFO_HEADER *fih = find_fsp((uintptr_t)rdev_mmap_full(prog_rdev(&fsp))); cache_as_ram_stage_main(fih); } From 6681f05373c2ec07168e279026962d7a63539e93 Mon Sep 17 00:00:00 2001 From: Nitheesh Sekar Date: Fri, 14 Sep 2018 19:07:36 +0530 Subject: [PATCH 276/331] qcs405: util/qualcomm: Add T32 debug scripts Add T32 scripts that allow debug of any coreboot stage on qcs405. Change-Id: I4e792a2806e5ebd3b4075c7bb69c43587920deae Signed-off-by: Sricharan R Signed-off-by: Nitheesh Sekar Reviewed-on: https://review.coreboot.org/c/coreboot/+/29951 Reviewed-by: Patrick Georgi Tested-by: build bot (Jenkins) --- util/qualcomm/scripts/cmm/clear_bss.cmm | 16 ++ util/qualcomm/scripts/cmm/debug_cb_405.cmm | 165 ++++++++++++++++++ util/qualcomm/scripts/cmm/debug_cb_common.cmm | 18 +- .../scripts/cmm/pbl32_to_bootblock64_jump.cmm | 15 ++ 4 files changed, 211 insertions(+), 3 deletions(-) create mode 100755 util/qualcomm/scripts/cmm/clear_bss.cmm create mode 100644 util/qualcomm/scripts/cmm/debug_cb_405.cmm create mode 100644 util/qualcomm/scripts/cmm/pbl32_to_bootblock64_jump.cmm diff --git a/util/qualcomm/scripts/cmm/clear_bss.cmm b/util/qualcomm/scripts/cmm/clear_bss.cmm new file mode 100755 index 0000000000..16eaac71d8 --- /dev/null +++ b/util/qualcomm/scripts/cmm/clear_bss.cmm @@ -0,0 +1,16 @@ +d.a 0x80000000 mov x0,#0x8c +d.a 0x80000004 lsl x0, x0, #0x14 +d.a 0x80000008 mov x1,#0x18 +d.a 0x8000000c lsl x1,x1, #0x10 +d.a 0x80000010 mov x2,#0x0 +d.a 0x80000014 mov x3,#0x80 +d.a 0x80000018 lsl x3, x3, #0x18 +d.a 0x8000001c add x3, x3, #0x14 +d.a 0x80000020 str x2,[x0] +d.a 0x80000024 sub x1, x1, #0x8 +d.a 0x80000028 add x0, x0, #0x8 +d.a 0x8000002c cmp x1,0x0 +d.a 0x80000030 b.ne 0x20 +d.a 0x80000034 b 0x34 +r.s pc 0x80000000 +go diff --git a/util/qualcomm/scripts/cmm/debug_cb_405.cmm b/util/qualcomm/scripts/cmm/debug_cb_405.cmm new file mode 100644 index 0000000000..166d2aa308 --- /dev/null +++ b/util/qualcomm/scripts/cmm/debug_cb_405.cmm @@ -0,0 +1,165 @@ +;============================================================================ +;## +;## This file is part of the coreboot project. +;## +;## Copyright (C) 2018, The Linux Foundation. All rights reserved. +;## +;## This program is free software; you can redistribute it and/or modify +;## it under the terms of the GNU General Public License version 2 and +;## only version 2 as published by the Free Software Foundation. +;## +;## This program is distributed in the hope that it will be useful, +;## but WITHOUT ANY WARRANTY; without even the implied warranty of +;## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +;## GNU General Public License for more details. +;## +;============================================================================ +; Name: +; debug_cb_405.cmm +; +; Description: +; Debug coreboot 405 front-end +;============================================================================ + +;============================================================================ +; CMM script variables +;============================================================================ + +LOCAL &TargetPkg + +GLOBAL &BBEntryAddr // Bootblock Entry +GLOBAL &BBExitAddr // Bootblock Exit to Xbl-Sec +GLOBAL &VEREntryAddr // Verstage Entry +GLOBAL &ROMEntryAddr // Romstage Entry +GLOBAL &QCLEntryAddr // QCLstage Entry +GLOBAL &RAMEntryAddr // Ramstage Entry +GLOBAL &BL31EntryAddr // BL31 Entry +GLOBAL &DCEntryAddr // Depthcharge Entry +GLOBAL &KernelEntryAddr // Kernel Entry + +GLOBAL &PreRamConsoleAddr +GLOBAL &RamConsoleAddr +GLOBAL &PreRamCbfsCache +GLOBAL &VBoot2Work +GLOBAL &Stack +GLOBAL &Ttb +GLOBAL &Timestamp +GLOBAL &CbmemTop +GLOBAL &PostRamCbfsCache + +GLOBAL &CBTablePtr + +GLOBAL &debug + +;============================================================================ + +;--------------------------------------------------- +; Entry point +;--------------------------------------------------- +ENTRY &ImageName + + // Later these can be parameterized + &TargetPkg="Qcs405Pkg" + + // These settings come from .../src/soc/qualcomm/qcs405/include/soc/memlayout.ld + &BBEntryAddr=0x8c2f000 + &VEREntryAddr=0x8C00000 + &ROMEntryAddr=0x8C00000 + &QCLEntryAddr=0x1485AC00 + &RAMEntryAddr=0x9F860000 + &BL31EntryAddr=0x06820000 + &DCEntryAddr=0xf1104800 + &KernelEntryAddr=0x90080000 + + &PreRamConsoleAddr=0x8C4F400 + &VBoot2Work=0x8C47000 + &Stack=0x8C4B000 + &Ttb=0x8C39000 + &Timestamp=0x8C4F000 + &PreRamCbfsCache=0x8C57400 + &CbmemTop=0x280000000 + &PostRamCbfsCache=0x9F800000 + // End of memlayout.ld settings + + // Common commands irrespective of &Mode + PATH + &CwDir=os.pwd() + PATH + &CwDir + + // position at top of coreboot tree + // find depth count for source loading + cd ..\..\..\.. + &srcpath=os.pwd() + + b.sel PROGRAM onchip + ;sys.u + + b.d /all + + ;go &BBEntryAddr + ;wait !run() + +;--------------------------------------------------- +; Setup area and log +;--------------------------------------------------- + area.clear + area.reset + area.create CB_Logs 1000. 8192. + area.select CB_Logs + + ;winclear + ;b.d /all + + if FILE.EXIST("C:\TEMP\WIN.CMM") + do C:\TEMP\WIN.CMM + + area.view CB_Logs + + PRINT %String "Source Path: &srcpath" + + symbol.sourcepath.setbasedir &srcpath\src + + PRINT "pbl32_to_bootblock64 jump" + do pbl32_to_bootblock64_jump.cmm + do clear_bss.cmm + WAIT 5s + b + + // Make parsing simple, upper-case parameters + &Imagename=STRING.UPR("&Imagename") + IF (STR.CP("&ImageName","DEBUG,*")) + ( + &debug="DEBUG" + ) + ELSE + ( + &debug="" + ) + &Imagename=STR.CUT("&ImageName",6) + IF "&debug"=="" + ( + PRINT "SPI_RAM LOAD" + &ImageName=STRING.UPR("&ImageName") + IF "&ImageName"=="" + ( + &ImageName="RAM,BB" //for RAM load Bootblock only and jump till DC + ) + PRINT "&ImageName" + ) + ELSE + ( + if (STR.CP("&debug","DEBUG")) + ( + PRINT "DEBUG" + &ImageName=STRING.UPR("&ImageName") + IF "&ImageName"=="" + ( + &ImageName="RAM,ALL" //for RAM loading all the images + ) + PRINT "&ImageName" + ) + ) + + DO debug_cb_common.cmm &TargetPkg &srcpath &xblsrcpath &ImageName + + enddo diff --git a/util/qualcomm/scripts/cmm/debug_cb_common.cmm b/util/qualcomm/scripts/cmm/debug_cb_common.cmm index bdb0097cd3..5959ee11e6 100644 --- a/util/qualcomm/scripts/cmm/debug_cb_common.cmm +++ b/util/qualcomm/scripts/cmm/debug_cb_common.cmm @@ -104,6 +104,10 @@ ENTRY &TargetPkg &srcpath &xblsrcpath &ImageName if &BBStage ( + IF "&debug"=="" + ( + d.load.binary build/coreboot.rom 0xA0000000 + ) &imgpath="build\cbfs\fallback\bootblock.elf" if (&RAMLoad) d.load.elf &imgpath /strippart "coreboot" /sourcepath &srcpath @@ -114,9 +118,17 @@ ENTRY &TargetPkg &srcpath &xblsrcpath &ImageName ;b.s run_romstage /o ;d.set &PreRamConsoleAddr++0x8000 0 d.dump &PreRamConsoleAddr /spotlight - print %String "Now the control is in BootBlock, press enter after debugging to go to next stage" - print %String "Press enter to go to next stage" - enter + IF (STR.CP("&debug","DEBUG")) + ( + print %String "Now the control is in BootBlock, press enter after debugging to go to next stage" + print %String "Press enter to go to next stage" + enter + ) + ELSE + ( + go + enddo + ) ) go &VEREntryAddr diff --git a/util/qualcomm/scripts/cmm/pbl32_to_bootblock64_jump.cmm b/util/qualcomm/scripts/cmm/pbl32_to_bootblock64_jump.cmm new file mode 100644 index 0000000000..bebf85d1c4 --- /dev/null +++ b/util/qualcomm/scripts/cmm/pbl32_to_bootblock64_jump.cmm @@ -0,0 +1,15 @@ +PER.Set.simple SPR:0x36100 %Long 00c5183C +D.S AZSD:0x8600034 %LE %Long 0x8600000 +D.S AZSD:0x8600000 %LE %Long 0x1400000 +d.a 0x8600004 ldr r0,0x8600034 +d.a 0x8600008 mcr p15,0x0,r0,c12,c0,1 +d.a 0x860000c dsb +d.a 0x8600010 isb +d.a 0x8600014 mrc p15,0x0,r1,c12,c0,2 +d.a 0x8600018 orr r1,r1,0x3 +d.a 0x860001c mcr p15,0x0,r1,c12,c0,2 +d.a 0x8600020 isb +d.a 0x8600024 wfi +r.s pc 0x8600004 +go +b From c345570acce55a2cb13a65bf06c4e1d8069f7b36 Mon Sep 17 00:00:00 2001 From: Hung-Te Lin Date: Mon, 27 May 2019 11:02:00 +0800 Subject: [PATCH 277/331] src/driver/vpd: Update lib_vpd from upstream Update lib_vpd.c (only containing vpd_decode.c) to latest version from https://chromium.googlesource.com/chromiumos/platform/vpd The called module (vpd.c) has been also corrected for new lib_vpd types and constants. BUG=chromium:967209 TEST=select VPD config on kukui; make; boots on at least kukui boards. Change-Id: I3928e9c43cb87caf93fb44ee10434ce80f0a188a Signed-off-by: Hung-Te Lin Reviewed-on: https://review.coreboot.org/c/coreboot/+/33016 Tested-by: build bot (Jenkins) Reviewed-by: Joel Kitching --- src/drivers/vpd/Makefile.inc | 4 +- src/drivers/vpd/lib_vpd.c | 113 ------------------ src/drivers/vpd/lib_vpd.h | 226 ----------------------------------- src/drivers/vpd/vpd.c | 41 ++++--- src/drivers/vpd/vpd_decode.c | 92 ++++++++++++++ src/drivers/vpd/vpd_decode.h | 68 +++++++++++ 6 files changed, 184 insertions(+), 360 deletions(-) delete mode 100644 src/drivers/vpd/lib_vpd.c delete mode 100644 src/drivers/vpd/lib_vpd.h create mode 100644 src/drivers/vpd/vpd_decode.c create mode 100644 src/drivers/vpd/vpd_decode.h diff --git a/src/drivers/vpd/Makefile.inc b/src/drivers/vpd/Makefile.inc index 91c069d6c8..17019b599b 100644 --- a/src/drivers/vpd/Makefile.inc +++ b/src/drivers/vpd/Makefile.inc @@ -1,2 +1,2 @@ -romstage-$(CONFIG_VPD) += lib_vpd.c -ramstage-$(CONFIG_VPD) += vpd.c lib_vpd.c +romstage-$(CONFIG_VPD) += vpd_decode.c +ramstage-$(CONFIG_VPD) += vpd.c vpd_decode.c diff --git a/src/drivers/vpd/lib_vpd.c b/src/drivers/vpd/lib_vpd.c deleted file mode 100644 index 0744a712ab..0000000000 --- a/src/drivers/vpd/lib_vpd.c +++ /dev/null @@ -1,113 +0,0 @@ -/* - * Copyright (c) 2014 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - * - */ -#include -#include "lib_vpd.h" - -/* Given an encoded string, this functions decodes the length field which varies - * from 1 byte to many bytes. - * - * The in points the actual byte going to be decoded. The *length returns - * the decoded length field. The number of consumed bytes will be stroed in - * decoded_len. - * - * Returns VPD_FAIL if more bit is 1, but actually reaches the end of string. - */ -int decodeLen(const int32_t max_len, - const uint8_t *in, - int32_t *length, - int32_t *decoded_len) -{ - uint8_t more; - int i = 0; - - assert(length); - assert(decoded_len); - - *length = 0; - do { - if (i >= max_len) - return VPD_FAIL; - - more = in[i] & 0x80; - *length <<= 7; - *length |= in[i] & 0x7f; - ++i; - } while (more); - - *decoded_len = i; - - return VPD_OK; -} - -/* Given the encoded string, this function invokes callback with extracted - * (key, value). The *consumed will be plused the number of bytes consumed in - * this function. - * - * The input_buf points to the first byte of the input buffer. - * - * The *consumed starts from 0, which is actually the next byte to be decoded. - * It can be non-zero to be used in multiple calls. - * - * If one entry is successfully decoded, sends it to callback and returns the - * result. - */ -int decodeVpdString(const int32_t max_len, - const uint8_t *input_buf, - int32_t *consumed, - VpdDecodeCallback callback, - void *callback_arg) -{ - int type; - int32_t key_len, value_len; - int32_t decoded_len; - const uint8_t *key, *value; - - /* type */ - if (*consumed >= max_len) - return VPD_FAIL; - - type = input_buf[*consumed]; - switch (type) { - case VPD_TYPE_INFO: - case VPD_TYPE_STRING: - (*consumed)++; - /* key */ - if (VPD_OK != decodeLen(max_len - *consumed, - &input_buf[*consumed], &key_len, - &decoded_len) || - *consumed + decoded_len >= max_len) { - return VPD_FAIL; - } - - *consumed += decoded_len; - key = &input_buf[*consumed]; - *consumed += key_len; - - /* value */ - if (VPD_OK != decodeLen(max_len - *consumed, - &input_buf[*consumed], - &value_len, &decoded_len) || - *consumed + decoded_len > max_len) { - return VPD_FAIL; - } - *consumed += decoded_len; - value = &input_buf[*consumed]; - *consumed += value_len; - - if (type == VPD_TYPE_STRING) - return callback(key, key_len, value, value_len, - callback_arg); - - return VPD_OK; - - default: - return VPD_FAIL; - break; - } - - return VPD_OK; -} diff --git a/src/drivers/vpd/lib_vpd.h b/src/drivers/vpd/lib_vpd.h deleted file mode 100644 index 156d27939f..0000000000 --- a/src/drivers/vpd/lib_vpd.h +++ /dev/null @@ -1,226 +0,0 @@ -/* - * Copyright (c) 2013 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - * - */ - -#ifndef __LIB_VPD__ -#define __LIB_VPD__ - -#include - -enum { - VPD_OK = 0, - VPD_FAIL, -}; - -enum { - VPD_TYPE_TERMINATOR = 0, - VPD_TYPE_STRING, - VPD_TYPE_INFO = 0xfe, - VPD_TYPE_IMPLICIT_TERMINATOR = 0xff, -}; - -enum { - VPD_AS_LONG_AS = -1, -}; - -enum { /* export_type */ - VPD_EXPORT_KEY_VALUE = 1, - VPD_EXPORT_VALUE, - VPD_EXPORT_AS_PARAMETER, -}; - -/* Callback for decodeVpdString to invoke. */ -typedef int VpdDecodeCallback(const uint8_t *key, int32_t key_len, - const uint8_t *value, int32_t value_len, - void *arg); - -/* Container data types */ -struct StringPair { - uint8_t *key; - uint8_t *value; - int pad_len; - int filter_out; /* TRUE means not exported. */ - struct StringPair *next; -}; - -struct PairContainer { - struct StringPair *first; -}; - - -/*********************************************************************** - * Encode and decode VPD entries - ***********************************************************************/ - -/* Encodes the len into multiple bytes with the following format. - * - * 7 6 ............ 0 - * +----+------------------+ - * |More| Length | ... - * +----+------------------+ - * - * The encode_buf points to the actual position we are going to store. - * encoded_len will return the exact bytes we encoded in this function. - * Returns fail if the buffer is not long enough. - */ -int encodeLen( - const int32_t len, - uint8_t *encode_buf, - const int32_t max_len, - int32_t *encoded_len); - -/* Given an encoded string, this functions decodes the length field which varies - * from 1 byte to many bytes. - * - * The in points the actual byte going to be decoded. The *length returns - * the decoded length field. The number of consumed bytes will be stroed in - * decoded_len. - * - * Returns VPD_FAIL if more bit is 1, but actually reaches the end of string. - */ -int decodeLen( - const int32_t max_len, - const uint8_t *in, - int32_t *length, - int32_t *decoded_len); - - -/* Encodes the terminator. - * When calling, the output_buf should point to the start of buffer while - * *generated_len should contain how many bytes exist in buffer now. - * After return, *generated_len would be plused the number of bytes generated - * in this function. - */ -int encodeVpdTerminator( - const int max_buffer_len, - uint8_t *output_buf, - int *generated_len); - -/* Encodes the given type/key/value pair into buffer. - * - * The pad_value_len is used to control the output value length. - * When pad_value_len > 0, the value is outputted into fixed length (pad \0 - * if the value is shorter). Truncated if too long. - * pad_value_len == VPD_NO_LIMIT, output the value as long as possible. - * This is useful when we want to fix the structure layout at beginning. - * - * The encoded string will be stored in output_buf. If it is longer than - * max_buffer_len, this function returns fail. If the buffer is long enough, - * the generated_len will be updated. - * - * When calling, the output_buf should point to the start of buffer while - * *generated_len should contain how many bytes exist in buffer now. - * After return, *generated_len would be plused the number of bytes generated - * in this function. - * - * The initial value of *generated_len can be non-zero, so that this value - * can be used between multiple calls to encodeVpd2Pair(). - */ -int encodeVpdString( - const uint8_t *key, - const uint8_t *value, - const int pad_value_len, - const int max_buffer_len, - uint8_t *output_buf, - int *generated_len); - - -/* Given the encoded string, this function invokes callback with extracted - * (key, value). The *consumed will be plused the number of bytes consumed in - * this function. - * - * The input_buf points to the first byte of the input buffer. - * - * The *consumed starts from 0, which is actually the next byte to be decoded. - * It can be non-zero to be used in multiple calls. - * - * If one entry is successfully decoded, sends it to callback and returns the - * result. - */ -int decodeVpdString( - const int32_t max_len, - const uint8_t *input_buf, - int32_t *consumed, - VpdDecodeCallback callback, - void *callback_arg); - -/*********************************************************************** - * Container helpers - ***********************************************************************/ -void initContainer(struct PairContainer *container); - -struct StringPair *findString(struct PairContainer *container, - const uint8_t *key, - struct StringPair ***prev_next); - -/* If key is already existed in container, its value will be replaced. - * If not existed, creates new entry in container. - */ -void setString(struct PairContainer *container, - const uint8_t *key, - const uint8_t *value, - const int pad_len); - -/* merge all entries in src into dst. If key is duplicate, overwrite it. - */ -void mergeContainer(struct PairContainer *dst, - const struct PairContainer *src); - -/* subtract src from dst. -*/ -int subtractContainer(struct PairContainer *dst, - const struct PairContainer *src); - -/* Given a container, encode its all entries into the buffer. - */ -int encodeContainer(const struct PairContainer *container, - const int max_buf_len, - uint8_t *buf, - int *generated); - -/* Given a VPD blob, decode its entries and push into container. - */ -int decodeToContainer(struct PairContainer *container, - const int32_t max_len, - const uint8_t *input_buf, - int32_t *consumed); - -/* Set filter for exporting functions. - * If filter is NULL, resets the filter so that everything can be exported. - */ -int setContainerFilter(struct PairContainer *container, - const uint8_t *filter); - -/* - * Remove a key. - * Returns VPD_OK if deleted successfully. Otherwise, VPD_FAIL. - */ -int deleteKey(struct PairContainer *container, - const uint8_t *key); - -/* - * Returns number of pairs in container. - */ -int lenOfContainer(const struct PairContainer *container); - -/* - * Export the container content with human-readable text. - * - * The buf points to the first byte of buffer and *generated contains the number - * of bytes already existed in buffer. - * - * Afterward, the *generated will be plused on exact bytes this function has - * generated. - */ -int exportContainer(const int export_type, - const struct PairContainer *container, - const int max_buf_len, - uint8_t *buf, - int *generated); - -void destroyContainer(struct PairContainer *container); - -#endif /* __LIB_VPD__ */ diff --git a/src/drivers/vpd/vpd.c b/src/drivers/vpd/vpd.c index e620b58b31..c6dd339f61 100644 --- a/src/drivers/vpd/vpd.c +++ b/src/drivers/vpd/vpd.c @@ -12,7 +12,7 @@ #include #include "vpd.h" -#include "lib_vpd.h" +#include "vpd_decode.h" #include "vpd_tables.h" /* Currently we only support Google VPD 2.0, which has a fixed offset. */ @@ -160,27 +160,27 @@ static void cbmem_add_cros_vpd(int is_recovery) } } -static int vpd_gets_callback(const uint8_t *key, int32_t key_len, - const uint8_t *value, int32_t value_len, - void *arg) +static int vpd_gets_callback(const uint8_t *key, uint32_t key_len, + const uint8_t *value, uint32_t value_len, + void *arg) { struct vpd_gets_arg *result = (struct vpd_gets_arg *)arg; if (key_len != result->key_len || memcmp(key, result->key, key_len) != 0) - /* Returns VPD_OK to continue parsing. */ - return VPD_OK; + /* Returns VPD_DECODE_OK to continue parsing. */ + return VPD_DECODE_OK; result->matched = 1; result->value = value; result->value_len = value_len; - /* Returns VPD_FAIL to stop parsing. */ - return VPD_FAIL; + /* Returns VPD_DECODE_FAIL to stop parsing. */ + return VPD_DECODE_FAIL; } const void *vpd_find(const char *key, int *size, enum vpd_region region) { struct vpd_gets_arg arg = {0}; - int consumed = 0; + uint32_t consumed = 0; const struct vpd_cbmem *vpd; vpd = cbmem_find(CBMEM_ID_VPD); @@ -190,18 +190,21 @@ const void *vpd_find(const char *key, int *size, enum vpd_region region) arg.key = (const uint8_t *)key; arg.key_len = strlen(key); - if (region == VPD_ANY || region == VPD_RO) - while (VPD_OK == decodeVpdString(vpd->ro_size, vpd->blob, - &consumed, vpd_gets_callback, &arg)) { - /* Iterate until found or no more entries. */ + if (region == VPD_ANY || region == VPD_RO) { + while (vpd_decode_string( + vpd->ro_size, vpd->blob, &consumed, + vpd_gets_callback, &arg) == VPD_DECODE_OK) { + /* Iterate until found or no more entries. */ } - - if (!arg.matched && region != VPD_RO) - while (VPD_OK == decodeVpdString(vpd->rw_size, - vpd->blob + vpd->ro_size, &consumed, - vpd_gets_callback, &arg)) { - /* Iterate until found or no more entries. */ + } + if (!arg.matched && region != VPD_RO) { + while (vpd_decode_string( + vpd->rw_size, vpd->blob + vpd->ro_size, + &consumed, vpd_gets_callback, + &arg) == VPD_DECODE_OK) { + /* Iterate until found or no more entries. */ } + } if (!arg.matched) return NULL; diff --git a/src/drivers/vpd/vpd_decode.c b/src/drivers/vpd/vpd_decode.c new file mode 100644 index 0000000000..0eab704ca8 --- /dev/null +++ b/src/drivers/vpd/vpd_decode.c @@ -0,0 +1,92 @@ +/* + * Copyright 2014 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + * + * This is a copy from upstream: + * https://chromium.googlesource.com/chromiumos/platform/vpd/+/master/lib/vpd_decode.c + */ +#include "vpd_decode.h" + +int vpd_decode_len( + const u32 max_len, const u8 *in, u32 *length, u32 *decoded_len) +{ + u8 more; + int i = 0; + + if (!length || !decoded_len) + return VPD_DECODE_FAIL; + + *length = 0; + do { + if (i >= max_len) + return VPD_DECODE_FAIL; + + more = in[i] & 0x80; + *length <<= 7; + *length |= in[i] & 0x7f; + ++i; + } while (more); + + *decoded_len = i; + return VPD_DECODE_OK; +} + +int vpd_decode_string( + const u32 max_len, const u8 *input_buf, u32 *consumed, + vpd_decode_callback callback, void *callback_arg) +{ + int type; + int res; + u32 key_len; + u32 value_len; + u32 decoded_len; + const u8 *key; + const u8 *value; + + /* type */ + if (*consumed >= max_len) + return VPD_DECODE_FAIL; + + type = input_buf[*consumed]; + + switch (type) { + case VPD_TYPE_INFO: + case VPD_TYPE_STRING: + (*consumed)++; + + /* key */ + res = vpd_decode_len(max_len - *consumed, &input_buf[*consumed], + &key_len, &decoded_len); + /* key name cannot be empty, and must be followed by value. */ + if (res != VPD_DECODE_OK || key_len < 1 || + *consumed + decoded_len + key_len >= max_len) + return VPD_DECODE_FAIL; + + *consumed += decoded_len; + key = &input_buf[*consumed]; + *consumed += key_len; + + /* value */ + res = vpd_decode_len(max_len - *consumed, &input_buf[*consumed], + &value_len, &decoded_len); + /* value can be empty (value_len = 0). */ + if (res != VPD_DECODE_OK || + *consumed + decoded_len + value_len > max_len) + return VPD_DECODE_FAIL; + + *consumed += decoded_len; + value = &input_buf[*consumed]; + *consumed += value_len; + + if (type == VPD_TYPE_STRING) + return callback(key, key_len, value, value_len, + callback_arg); + break; + + default: + return VPD_DECODE_FAIL; + } + + return VPD_DECODE_OK; +} diff --git a/src/drivers/vpd/vpd_decode.h b/src/drivers/vpd/vpd_decode.h new file mode 100644 index 0000000000..99ca7efa81 --- /dev/null +++ b/src/drivers/vpd/vpd_decode.h @@ -0,0 +1,68 @@ +/* + * Copyright 2019 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + * + * This is a copy from upstream: + * https://chromium.googlesource.com/chromiumos/platform/vpd/+/master/include/lib/vpd_decode.h + */ + +#ifndef __VPD_DECODE_H +#define __VPD_DECODE_H + +#include + +enum { + VPD_DECODE_OK = 0, + VPD_DECODE_FAIL = 1, +}; + +enum { + VPD_TYPE_TERMINATOR = 0, + VPD_TYPE_STRING, + VPD_TYPE_INFO = 0xfe, + VPD_TYPE_IMPLICIT_TERMINATOR = 0xff, +}; + +/* Callback for vpd_decode_string to invoke. */ +typedef int vpd_decode_callback( + const u8 *key, u32 key_len, const u8 *value, u32 value_len, + void *arg); + +/* + * vpd_decode_len + * + * Given an encoded string, this function extracts the length of content + * (either key or value). The *consumed will contain the number of bytes + * consumed. + * + * The input_buf points to the first byte of the input buffer. + * + * The *consumed starts from 0, which is actually the next byte to be decoded. + * It can be non-zero to be used in multiple calls. + * + * Returns VPD_DECODE_OK on success, otherwise VPD_DECODE_FAIL. + */ +int vpd_decode_len( + const u32 max_len, const u8 *in, u32 *length, u32 *decoded_len); + +/* + * vpd_decode_string + * + * Given the encoded string, this function invokes callback with extracted + * (key, value). The *consumed will be plused the number of bytes consumed in + * this function. + * + * The input_buf points to the first byte of the input buffer. + * + * The *consumed starts from 0, which is actually the next byte to be decoded. + * It can be non-zero to be used in multiple calls. + * + * If one entry is successfully decoded, sends it to callback and returns the + * result. + */ +int vpd_decode_string( + const u32 max_len, const u8 *input_buf, u32 *consumed, + vpd_decode_callback callback, void *callback_arg); + +#endif /* __VPD_DECODE_H */ From 51dc5ea735cd175a6d38d59d8b3b3eadee027e6c Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Wed, 29 May 2019 23:26:07 +0200 Subject: [PATCH 278/331] soc/intel/common/lpss: Drop now unused lpss_clk_read() Change-Id: I7def72e820ee1a4fa47c34b26dab9e0886ba74e6 Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/c/coreboot/+/33094 Tested-by: build bot (Jenkins) Reviewed-by: Lance Zhao --- src/soc/intel/common/block/include/intelblocks/lpss.h | 3 --- src/soc/intel/common/block/lpss/lpss.c | 9 --------- 2 files changed, 12 deletions(-) diff --git a/src/soc/intel/common/block/include/intelblocks/lpss.h b/src/soc/intel/common/block/include/intelblocks/lpss.h index ca5568996f..eb38f13a71 100644 --- a/src/soc/intel/common/block/include/intelblocks/lpss.h +++ b/src/soc/intel/common/block/include/intelblocks/lpss.h @@ -30,7 +30,4 @@ void lpss_clk_update(uintptr_t base, uint32_t clk_m_val, uint32_t clk_n_val); /* Check if controller is in reset. */ bool lpss_is_controller_in_reset(uintptr_t base); -/* Read LPSS CLK register */ -uint32_t lpss_clk_read(uintptr_t base); - #endif /* SOC_INTEL_COMMON_BLOCK_LPSS_H */ diff --git a/src/soc/intel/common/block/lpss/lpss.c b/src/soc/intel/common/block/lpss/lpss.c index 1168871d09..6b6d17b106 100644 --- a/src/soc/intel/common/block/lpss/lpss.c +++ b/src/soc/intel/common/block/lpss/lpss.c @@ -69,12 +69,3 @@ void lpss_clk_update(uintptr_t base, uint32_t clk_m_val, uint32_t clk_n_val) write32(addr, clk_sel); } - -uint32_t lpss_clk_read(uintptr_t base) -{ - uint8_t *addr = (void *)base; - - addr += LPSS_CLOCK_CTL_REG; - - return read32(addr); -} From 8bbad6c8186037e67da9f1465078b5952c0c0899 Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Wed, 29 May 2019 23:18:26 +0200 Subject: [PATCH 279/331] soc/intel/common/uart: Drop dead call to soc_uart_set_legacy_mode() The only path that leads here is guarded by both !DRIVERS_UART_ 8250MEM_32 and INTEL_LPSS_UART_FOR_CONSOLE but the latter selects the former. Change-Id: I6e0765b028572950991c45b45b2051f4f176a94a Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/c/coreboot/+/33095 Tested-by: build bot (Jenkins) Reviewed-by: Lance Zhao --- src/soc/intel/common/block/include/intelblocks/uart.h | 6 ------ src/soc/intel/common/block/uart/uart.c | 4 ---- 2 files changed, 10 deletions(-) diff --git a/src/soc/intel/common/block/include/intelblocks/uart.h b/src/soc/intel/common/block/include/intelblocks/uart.h index ad2ddf4b28..55f259db7c 100644 --- a/src/soc/intel/common/block/include/intelblocks/uart.h +++ b/src/soc/intel/common/block/include/intelblocks/uart.h @@ -91,10 +91,4 @@ struct device *uart_get_device(void); */ struct device *soc_uart_console_to_device(int uart_console); -/* - * Set UART to legacy mode - * Put UART in byte access mode for 16550 compatibility - */ -void soc_uart_set_legacy_mode(void); - #endif /* SOC_INTEL_COMMON_BLOCK_UART_H */ diff --git a/src/soc/intel/common/block/uart/uart.c b/src/soc/intel/common/block/uart/uart.c index a8e5792a86..35c2c6cafb 100644 --- a/src/soc/intel/common/block/uart/uart.c +++ b/src/soc/intel/common/block/uart/uart.c @@ -139,10 +139,6 @@ void uart_bootblock_init(void) uart_common_init(uart_get_device(), UART_BASE(CONFIG_UART_FOR_CONSOLE)); - if (!CONFIG(DRIVERS_UART_8250MEM_32)) - /* Put UART in byte access mode for 16550 compatibility */ - soc_uart_set_legacy_mode(); - /* Configure the 2 pads per UART. */ uart_configure_gpio_pads(); } From ce8eebd3b7642e3d675616fb8d3d068cb58d66ef Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Wed, 29 May 2019 18:33:35 +0200 Subject: [PATCH 280/331] soc/intel/common/uart: Only return valid UART base We only configure the base address for the console UART, the other addresses are never assigned to the hardware. It seems better to return 0 for them instead of a spurious value. Change-Id: I3fa5c99958b56ca5b0b603917c086bdddb677fa2 Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/c/coreboot/+/33096 Tested-by: build bot (Jenkins) Reviewed-by: Lance Zhao --- src/soc/intel/common/block/uart/uart.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/src/soc/intel/common/block/uart/uart.c b/src/soc/intel/common/block/uart/uart.c index 35c2c6cafb..47774b6e96 100644 --- a/src/soc/intel/common/block/uart/uart.c +++ b/src/soc/intel/common/block/uart/uart.c @@ -46,8 +46,9 @@ static void uart_lpss_init(uintptr_t baseaddr) #if CONFIG(DRIVERS_UART_8250MEM) uintptr_t uart_platform_base(int idx) { - /* return Base address for UART console index */ - return UART_BASE_0_ADDR(idx); + if (idx == CONFIG_UART_FOR_CONSOLE) + return UART_BASE_0_ADDR(CONFIG_UART_FOR_CONSOLE); + return 0; } #endif From 62ddc491cf8c8c6412177d2866bec89c6f4906dc Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Wed, 29 May 2019 18:39:31 +0200 Subject: [PATCH 281/331] soc/intel/common/uart: Correctly guard uart_platform_base() We should only provide this implementation when the Intel LPSS UART is used. Otherwise, no other UART could be used for the console with these SoCs. Change-Id: Iebd89edb3f21d4a68587fd02659b4d529f3f4bbe Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/c/coreboot/+/33097 Tested-by: build bot (Jenkins) Reviewed-by: Lance Zhao --- src/soc/intel/common/block/uart/uart.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/intel/common/block/uart/uart.c b/src/soc/intel/common/block/uart/uart.c index 47774b6e96..84ba1ee0f2 100644 --- a/src/soc/intel/common/block/uart/uart.c +++ b/src/soc/intel/common/block/uart/uart.c @@ -43,7 +43,7 @@ static void uart_lpss_init(uintptr_t baseaddr) CONFIG_SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL); } -#if CONFIG(DRIVERS_UART_8250MEM) +#if CONFIG(INTEL_LPSS_UART_FOR_CONSOLE) uintptr_t uart_platform_base(int idx) { if (idx == CONFIG_UART_FOR_CONSOLE) From 2deb5fb3b07e07ee3d0d142723e2a25f5982d417 Mon Sep 17 00:00:00 2001 From: John Zhao Date: Wed, 29 May 2019 18:12:01 -0700 Subject: [PATCH 282/331] src/device: Prevent attack on null pointer dereference Clang Static Analyzer version 8.0.0 detects access to field dev results in a dereference of a null pointer which is loaded from variable bus. Add sanity check for pointer bus to prevent null pointer dereference. TEST=Built and boot up to kernel. Change-Id: I084906c33065eaa834f50c545efcfab620658ec9 Signed-off-by: John Zhao Reviewed-on: https://review.coreboot.org/c/coreboot/+/33101 Tested-by: build bot (Jenkins) Reviewed-by: Lijian Zhao --- src/device/device.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/src/device/device.c b/src/device/device.c index 1b4255bffe..17cd8f4ab8 100644 --- a/src/device/device.c +++ b/src/device/device.c @@ -340,6 +340,9 @@ static void compute_resources(struct bus *bus, struct resource *bridge, resource_t base; base = round(bridge->base, bridge->align); + if (!bus) + return; + printk(BIOS_SPEW, "%s %s: base: %llx size: %llx align: %d gran: %d" " limit: %llx\n", dev_path(bus->dev), resource2str(bridge), base, bridge->size, bridge->align, @@ -484,6 +487,9 @@ static void allocate_resources(struct bus *bus, struct resource *bridge, resource_t base; base = bridge->base; + if (!bus) + return; + printk(BIOS_SPEW, "%s %s: base:%llx size:%llx align:%d gran:%d " "limit:%llx\n", dev_path(bus->dev), resource2str(bridge), From 10ed868d1999e4bd69efd8b86093bd953b8f8827 Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Wed, 29 May 2019 23:13:47 +0200 Subject: [PATCH 283/331] soc/intel/{skl,cnl,icl}: Drop soc_uart_set_legacy_mode() This is never called: The only calling path is guarded by both !DRIVERS_UART_8250MEM_32 and INTEL_LPSS_UART_FOR_CONSOLE but the latter selects the former. If somebody figures out how this is supposed to be used, we can easily revive the implementation. Change-Id: I96e304bdee4eadb52725027d0d662ef75f3d4307 Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/c/coreboot/+/33093 Reviewed-by: Lance Zhao Tested-by: build bot (Jenkins) --- src/soc/intel/cannonlake/uart.c | 15 --------------- src/soc/intel/icelake/uart.c | 15 --------------- src/soc/intel/skylake/uart.c | 15 --------------- 3 files changed, 45 deletions(-) diff --git a/src/soc/intel/cannonlake/uart.c b/src/soc/intel/cannonlake/uart.c index 2bd906adf8..7174a9a58f 100644 --- a/src/soc/intel/cannonlake/uart.c +++ b/src/soc/intel/cannonlake/uart.c @@ -24,10 +24,6 @@ #include #include -/* Serial IO UART controller legacy mode */ -#define PCR_SERIAL_IO_GPPRVRW7 0x618 -#define PCR_SIO_PCH_LEGACY_UART(idx) (1 << (idx)) - const struct uart_gpio_pad_config uart_gpio_pads[] = { { .console_index = 0, @@ -54,17 +50,6 @@ const struct uart_gpio_pad_config uart_gpio_pads[] = { const int uart_max_index = ARRAY_SIZE(uart_gpio_pads); -void soc_uart_set_legacy_mode(void) -{ - pcr_write32(PID_SERIALIO, PCR_SERIAL_IO_GPPRVRW7, - PCR_SIO_PCH_LEGACY_UART(CONFIG_UART_FOR_CONSOLE)); - /* - * Dummy read after setting any of GPPRVRW7. - * Required for UART 16550 8-bit Legacy mode to become active - */ - lpss_clk_read(UART_BASE(CONFIG_UART_FOR_CONSOLE)); -} - struct device *soc_uart_console_to_device(int uart_console) { /* diff --git a/src/soc/intel/icelake/uart.c b/src/soc/intel/icelake/uart.c index 2bd906adf8..7174a9a58f 100644 --- a/src/soc/intel/icelake/uart.c +++ b/src/soc/intel/icelake/uart.c @@ -24,10 +24,6 @@ #include #include -/* Serial IO UART controller legacy mode */ -#define PCR_SERIAL_IO_GPPRVRW7 0x618 -#define PCR_SIO_PCH_LEGACY_UART(idx) (1 << (idx)) - const struct uart_gpio_pad_config uart_gpio_pads[] = { { .console_index = 0, @@ -54,17 +50,6 @@ const struct uart_gpio_pad_config uart_gpio_pads[] = { const int uart_max_index = ARRAY_SIZE(uart_gpio_pads); -void soc_uart_set_legacy_mode(void) -{ - pcr_write32(PID_SERIALIO, PCR_SERIAL_IO_GPPRVRW7, - PCR_SIO_PCH_LEGACY_UART(CONFIG_UART_FOR_CONSOLE)); - /* - * Dummy read after setting any of GPPRVRW7. - * Required for UART 16550 8-bit Legacy mode to become active - */ - lpss_clk_read(UART_BASE(CONFIG_UART_FOR_CONSOLE)); -} - struct device *soc_uart_console_to_device(int uart_console) { /* diff --git a/src/soc/intel/skylake/uart.c b/src/soc/intel/skylake/uart.c index 1b2a7428df..8b7c99eae5 100644 --- a/src/soc/intel/skylake/uart.c +++ b/src/soc/intel/skylake/uart.c @@ -24,10 +24,6 @@ #include #include -/* Serial IO UART controller legacy mode */ -#define PCR_SERIAL_IO_GPPRVRW7 0x618 -#define PCR_SIO_PCH_LEGACY_UART(idx) (1 << (idx)) - /* UART pad configuration. Support RXD and TXD for now. */ const struct uart_gpio_pad_config uart_gpio_pads[] = { { @@ -55,17 +51,6 @@ const struct uart_gpio_pad_config uart_gpio_pads[] = { const int uart_max_index = ARRAY_SIZE(uart_gpio_pads); -void soc_uart_set_legacy_mode(void) -{ - pcr_write32(PID_SERIALIO, PCR_SERIAL_IO_GPPRVRW7, - PCR_SIO_PCH_LEGACY_UART(CONFIG_UART_FOR_CONSOLE)); - /* - * Dummy read after setting any of GPPRVRW7. - * Required for UART 16550 8-bit Legacy mode to become active - */ - lpss_clk_read(UART_BASE(CONFIG_UART_FOR_CONSOLE)); -} - struct device *soc_uart_console_to_device(int uart_console) { /* From fa1f7216ce2105aab79ee91cb3f8c8e879ded341 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Wed, 22 May 2019 15:40:54 +0200 Subject: [PATCH 284/331] nb/intel/sandybridge: Remove variable set but not used MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: Iaac05f73d2ba892d3ec7ee2ac0c16a98f2fce5bc Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/32926 Reviewed-by: Patrick Georgi Reviewed-by: Kyösti Mälkki Tested-by: build bot (Jenkins) --- src/northbridge/intel/sandybridge/early_dmi.c | 129 +++++++++--------- 1 file changed, 64 insertions(+), 65 deletions(-) diff --git a/src/northbridge/intel/sandybridge/early_dmi.c b/src/northbridge/intel/sandybridge/early_dmi.c index db49040dc1..6d41a2da96 100644 --- a/src/northbridge/intel/sandybridge/early_dmi.c +++ b/src/northbridge/intel/sandybridge/early_dmi.c @@ -19,7 +19,6 @@ void early_init_dmi(void) { - volatile u32 tmp; int i; DMIBAR32(0x0914) |= 0x80000000; @@ -39,133 +38,133 @@ void early_init_dmi(void) DMIBAR32(0x090c) &= 0xfe1fffff; DMIBAR32(0x092c) &= 0xfe1fffff; - tmp = DMIBAR32(0x0904); // !!! = 0x7a1842ec + DMIBAR32(0x0904); // !!! = 0x7a1842ec DMIBAR32(0x0904) = 0x7a1842ec; - tmp = DMIBAR32(0x090c); // !!! = 0x00000208 + DMIBAR32(0x090c); // !!! = 0x00000208 DMIBAR32(0x090c) = 0x00000128; - tmp = DMIBAR32(0x0924); // !!! = 0x7a1842ec + DMIBAR32(0x0924); // !!! = 0x7a1842ec DMIBAR32(0x0924) = 0x7a1842ec; - tmp = DMIBAR32(0x092c); // !!! = 0x00000208 + DMIBAR32(0x092c); // !!! = 0x00000208 DMIBAR32(0x092c) = 0x00000128; - tmp = DMIBAR32(0x0700); // !!! = 0x46139008 + DMIBAR32(0x0700); // !!! = 0x46139008 DMIBAR32(0x0700) = 0x46139008; - tmp = DMIBAR32(0x0720); // !!! = 0x46139008 + DMIBAR32(0x0720); // !!! = 0x46139008 DMIBAR32(0x0720) = 0x46139008; - tmp = DMIBAR32(0x0c04); // !!! = 0x2e680008 + DMIBAR32(0x0c04); // !!! = 0x2e680008 DMIBAR32(0x0c04) = 0x2e680008; - tmp = DMIBAR32(0x0904); // !!! = 0x7a1842ec + DMIBAR32(0x0904); // !!! = 0x7a1842ec DMIBAR32(0x0904) = 0x3a1842ec; - tmp = DMIBAR32(0x0924); // !!! = 0x7a1842ec + DMIBAR32(0x0924); // !!! = 0x7a1842ec DMIBAR32(0x0924) = 0x3a1842ec; - tmp = DMIBAR32(0x0910); // !!! = 0x00006300 + DMIBAR32(0x0910); // !!! = 0x00006300 DMIBAR32(0x0910) = 0x00004300; - tmp = DMIBAR32(0x0930); // !!! = 0x00006300 + DMIBAR32(0x0930); // !!! = 0x00006300 DMIBAR32(0x0930) = 0x00004300; - tmp = DMIBAR32(0x0a00); // !!! = 0x03042010 + DMIBAR32(0x0a00); // !!! = 0x03042010 DMIBAR32(0x0a00) = 0x03042018; - tmp = DMIBAR32(0x0a10); // !!! = 0x03042010 + DMIBAR32(0x0a10); // !!! = 0x03042010 DMIBAR32(0x0a10) = 0x03042018; - tmp = DMIBAR32(0x0a20); // !!! = 0x03042010 + DMIBAR32(0x0a20); // !!! = 0x03042010 DMIBAR32(0x0a20) = 0x03042018; - tmp = DMIBAR32(0x0a30); // !!! = 0x03042010 + DMIBAR32(0x0a30); // !!! = 0x03042010 DMIBAR32(0x0a30) = 0x03042018; - tmp = DMIBAR32(0x0c00); // !!! = 0x29700c08 + DMIBAR32(0x0c00); // !!! = 0x29700c08 DMIBAR32(0x0c00) = 0x29700c08; - tmp = DMIBAR32(0x0a04); // !!! = 0x0c0708f0 + DMIBAR32(0x0a04); // !!! = 0x0c0708f0 DMIBAR32(0x0a04) = 0x0c0718f0; - tmp = DMIBAR32(0x0a14); // !!! = 0x0c0708f0 + DMIBAR32(0x0a14); // !!! = 0x0c0708f0 DMIBAR32(0x0a14) = 0x0c0718f0; - tmp = DMIBAR32(0x0a24); // !!! = 0x0c0708f0 + DMIBAR32(0x0a24); // !!! = 0x0c0708f0 DMIBAR32(0x0a24) = 0x0c0718f0; - tmp = DMIBAR32(0x0a34); // !!! = 0x0c0708f0 + DMIBAR32(0x0a34); // !!! = 0x0c0708f0 DMIBAR32(0x0a34) = 0x0c0718f0; - tmp = DMIBAR32(0x0900); // !!! = 0x50000000 + DMIBAR32(0x0900); // !!! = 0x50000000 DMIBAR32(0x0900) = 0x50000000; - tmp = DMIBAR32(0x0920); // !!! = 0x50000000 + DMIBAR32(0x0920); // !!! = 0x50000000 DMIBAR32(0x0920) = 0x50000000; - tmp = DMIBAR32(0x0908); // !!! = 0x51ffffff + DMIBAR32(0x0908); // !!! = 0x51ffffff DMIBAR32(0x0908) = 0x51ffffff; - tmp = DMIBAR32(0x0928); // !!! = 0x51ffffff + DMIBAR32(0x0928); // !!! = 0x51ffffff DMIBAR32(0x0928) = 0x51ffffff; - tmp = DMIBAR32(0x0a00); // !!! = 0x03042018 + DMIBAR32(0x0a00); // !!! = 0x03042018 DMIBAR32(0x0a00) = 0x03042018; - tmp = DMIBAR32(0x0a10); // !!! = 0x03042018 + DMIBAR32(0x0a10); // !!! = 0x03042018 DMIBAR32(0x0a10) = 0x03042018; - tmp = DMIBAR32(0x0a20); // !!! = 0x03042018 + DMIBAR32(0x0a20); // !!! = 0x03042018 DMIBAR32(0x0a20) = 0x03042018; - tmp = DMIBAR32(0x0a30); // !!! = 0x03042018 + DMIBAR32(0x0a30); // !!! = 0x03042018 DMIBAR32(0x0a30) = 0x03042018; - tmp = DMIBAR32(0x0700); // !!! = 0x46139008 + DMIBAR32(0x0700); // !!! = 0x46139008 DMIBAR32(0x0700) = 0x46139008; - tmp = DMIBAR32(0x0720); // !!! = 0x46139008 + DMIBAR32(0x0720); // !!! = 0x46139008 DMIBAR32(0x0720) = 0x46139008; - tmp = DMIBAR32(0x0904); // !!! = 0x3a1842ec + DMIBAR32(0x0904); // !!! = 0x3a1842ec DMIBAR32(0x0904) = 0x3a1846ec; - tmp = DMIBAR32(0x0924); // !!! = 0x3a1842ec + DMIBAR32(0x0924); // !!! = 0x3a1842ec DMIBAR32(0x0924) = 0x3a1846ec; - tmp = DMIBAR32(0x0a00); // !!! = 0x03042018 + DMIBAR32(0x0a00); // !!! = 0x03042018 DMIBAR32(0x0a00) = 0x03042018; - tmp = DMIBAR32(0x0a10); // !!! = 0x03042018 + DMIBAR32(0x0a10); // !!! = 0x03042018 DMIBAR32(0x0a10) = 0x03042018; - tmp = DMIBAR32(0x0a20); // !!! = 0x03042018 + DMIBAR32(0x0a20); // !!! = 0x03042018 DMIBAR32(0x0a20) = 0x03042018; - tmp = DMIBAR32(0x0a30); // !!! = 0x03042018 + DMIBAR32(0x0a30); // !!! = 0x03042018 DMIBAR32(0x0a30) = 0x03042018; - tmp = DMIBAR32(0x0908); // !!! = 0x51ffffff + DMIBAR32(0x0908); // !!! = 0x51ffffff DMIBAR32(0x0908) = 0x51ffffff; - tmp = DMIBAR32(0x0928); // !!! = 0x51ffffff + DMIBAR32(0x0928); // !!! = 0x51ffffff DMIBAR32(0x0928) = 0x51ffffff; - tmp = DMIBAR32(0x0c00); // !!! = 0x29700c08 + DMIBAR32(0x0c00); // !!! = 0x29700c08 DMIBAR32(0x0c00) = 0x29700c08; - tmp = DMIBAR32(0x0c0c); // !!! = 0x16063400 + DMIBAR32(0x0c0c); // !!! = 0x16063400 DMIBAR32(0x0c0c) = 0x00063400; - tmp = DMIBAR32(0x0700); // !!! = 0x46139008 + DMIBAR32(0x0700); // !!! = 0x46139008 DMIBAR32(0x0700) = 0x46339008; - tmp = DMIBAR32(0x0720); // !!! = 0x46139008 + DMIBAR32(0x0720); // !!! = 0x46139008 DMIBAR32(0x0720) = 0x46339008; - tmp = DMIBAR32(0x0700); // !!! = 0x46339008 + DMIBAR32(0x0700); // !!! = 0x46339008 DMIBAR32(0x0700) = 0x45339008; - tmp = DMIBAR32(0x0720); // !!! = 0x46339008 + DMIBAR32(0x0720); // !!! = 0x46339008 DMIBAR32(0x0720) = 0x45339008; - tmp = DMIBAR32(0x0700); // !!! = 0x45339008 + DMIBAR32(0x0700); // !!! = 0x45339008 DMIBAR32(0x0700) = 0x453b9008; - tmp = DMIBAR32(0x0720); // !!! = 0x45339008 + DMIBAR32(0x0720); // !!! = 0x45339008 DMIBAR32(0x0720) = 0x453b9008; - tmp = DMIBAR32(0x0700); // !!! = 0x453b9008 + DMIBAR32(0x0700); // !!! = 0x453b9008 DMIBAR32(0x0700) = 0x45bb9008; - tmp = DMIBAR32(0x0720); // !!! = 0x453b9008 + DMIBAR32(0x0720); // !!! = 0x453b9008 DMIBAR32(0x0720) = 0x45bb9008; - tmp = DMIBAR32(0x0700); // !!! = 0x45bb9008 + DMIBAR32(0x0700); // !!! = 0x45bb9008 DMIBAR32(0x0700) = 0x45fb9008; - tmp = DMIBAR32(0x0720); // !!! = 0x45bb9008 + DMIBAR32(0x0720); // !!! = 0x45bb9008 DMIBAR32(0x0720) = 0x45fb9008; - tmp = DMIBAR32(0x0914); // !!! = 0x9021a080 + DMIBAR32(0x0914); // !!! = 0x9021a080 DMIBAR32(0x0914) = 0x9021a280; - tmp = DMIBAR32(0x0934); // !!! = 0x9021a080 + DMIBAR32(0x0934); // !!! = 0x9021a080 DMIBAR32(0x0934) = 0x9021a280; - tmp = DMIBAR32(0x0914); // !!! = 0x9021a280 + DMIBAR32(0x0914); // !!! = 0x9021a280 DMIBAR32(0x0914) = 0x9821a280; - tmp = DMIBAR32(0x0934); // !!! = 0x9021a280 + DMIBAR32(0x0934); // !!! = 0x9021a280 DMIBAR32(0x0934) = 0x9821a280; - tmp = DMIBAR32(0x0a00); // !!! = 0x03042018 + DMIBAR32(0x0a00); // !!! = 0x03042018 DMIBAR32(0x0a00) = 0x03242018; - tmp = DMIBAR32(0x0a10); // !!! = 0x03042018 + DMIBAR32(0x0a10); // !!! = 0x03042018 DMIBAR32(0x0a10) = 0x03242018; - tmp = DMIBAR32(0x0a20); // !!! = 0x03042018 + DMIBAR32(0x0a20); // !!! = 0x03042018 DMIBAR32(0x0a20) = 0x03242018; - tmp = DMIBAR32(0x0a30); // !!! = 0x03042018 + DMIBAR32(0x0a30); // !!! = 0x03042018 DMIBAR32(0x0a30) = 0x03242018; - tmp = DMIBAR32(0x0258); // !!! = 0x40000600 + DMIBAR32(0x0258); // !!! = 0x40000600 DMIBAR32(0x0258) = 0x60000600; - tmp = DMIBAR32(0x0904); // !!! = 0x3a1846ec + DMIBAR32(0x0904); // !!! = 0x3a1846ec DMIBAR32(0x0904) = 0x2a1846ec; - tmp = DMIBAR32(0x0914); // !!! = 0x9821a280 + DMIBAR32(0x0914); // !!! = 0x9821a280 DMIBAR32(0x0914) = 0x98200280; - tmp = DMIBAR32(0x0924); // !!! = 0x3a1846ec + DMIBAR32(0x0924); // !!! = 0x3a1846ec DMIBAR32(0x0924) = 0x2a1846ec; - tmp = DMIBAR32(0x0934); // !!! = 0x9821a280 + DMIBAR32(0x0934); // !!! = 0x9821a280 DMIBAR32(0x0934) = 0x98200280; - tmp = DMIBAR32(0x022c); // !!! = 0x00c26460 + DMIBAR32(0x022c); // !!! = 0x00c26460 DMIBAR32(0x022c) = 0x00c2403c; early_pch_init_native_dmi_pre(); From 9c8895fd889b01fe71bb296e2566b96a9542b303 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Wed, 22 May 2019 19:57:43 +0200 Subject: [PATCH 285/331] nb/intel/sandybridge: Remove variable set but not used MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I75f5d821e018932d3f10d84b7ebed362777fb17d Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/32938 Reviewed-by: Patrick Georgi Reviewed-by: Kyösti Mälkki Tested-by: build bot (Jenkins) --- .../intel/sandybridge/raminit_common.c | 18 ++++++------------ 1 file changed, 6 insertions(+), 12 deletions(-) diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 53f28c6cd6..4974173ef1 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -1452,9 +1452,8 @@ static void test_timC(ramctr_timing * ctrl, int channel, int slotrank) int lane; FOR_ALL_LANES { - volatile u32 tmp; MCHBAR32(0x4340 + 0x400 * channel + 4 * lane) = 0; - tmp = MCHBAR32(0x4140 + 0x400 * channel + 4 * lane); + MCHBAR32(0x4140 + 0x400 * channel + 4 * lane); } wait_428c(channel); @@ -2026,9 +2025,8 @@ int write_training(ramctr_timing * ctrl) MCHBAR32_OR(0x5030, 8); FOR_ALL_POPULATED_CHANNELS { - volatile u32 tmp; MCHBAR32_AND(0x4020 + 0x400 * channel, ~0x00200000); - tmp = MCHBAR32(0x428c + 0x400 * channel); + MCHBAR32(0x428c + 0x400 * channel); wait_428c(channel); /* DRAM command ZQCS */ @@ -2373,9 +2371,8 @@ static int discover_edges_real(ramctr_timing *ctrl, int channel, int slotrank, program_timings(ctrl, channel); FOR_ALL_LANES { - volatile u32 tmp; MCHBAR32(0x4340 + 0x400 * channel + 4 * lane) = 0; - tmp = MCHBAR32(0x400 * channel + 4 * lane + 0x4140); + MCHBAR32(0x400 * channel + 4 * lane + 0x4140); } wait_428c(channel); @@ -2454,8 +2451,7 @@ int discover_edges(ramctr_timing *ctrl) fill_pattern0(ctrl, channel, 0, 0); MCHBAR32(0x4288 + (channel << 10)) = 0; FOR_ALL_LANES { - volatile u32 tmp; - tmp = MCHBAR32(0x400 * channel + lane * 4 + 0x4140); + MCHBAR32(0x400 * channel + lane * 4 + 0x4140); } FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { @@ -2655,10 +2651,9 @@ static int discover_edges_write_real(ramctr_timing *ctrl, int channel, program_timings(ctrl, channel); FOR_ALL_LANES { - volatile u32 tmp; MCHBAR32(0x4340 + 0x400 * channel + 4 * lane) = 0; - tmp = MCHBAR32(0x400 * channel + + MCHBAR32(0x400 * channel + 4 * lane + 0x4140); } wait_428c(channel); @@ -2703,8 +2698,7 @@ static int discover_edges_write_real(ramctr_timing *ctrl, int channel, wait_428c(channel); FOR_ALL_LANES { - volatile u32 tmp; - tmp = MCHBAR32(0x4340 + + MCHBAR32(0x4340 + 0x400 * channel + lane * 4); } From 19cb6c9980f86bb602c988f48dbf20413f2c27bf Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Wed, 22 May 2019 20:26:02 +0200 Subject: [PATCH 286/331] sb/intel/fsp_rangeley: Remove variable set but not used MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: Ia2bc9bb0f0ece5ae3a57662b54f3e7e78ce00b19 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/32942 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Kyösti Mälkki --- src/southbridge/intel/fsp_rangeley/romstage.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/src/southbridge/intel/fsp_rangeley/romstage.c b/src/southbridge/intel/fsp_rangeley/romstage.c index 19e470e309..2c2427eed1 100644 --- a/src/southbridge/intel/fsp_rangeley/romstage.c +++ b/src/southbridge/intel/fsp_rangeley/romstage.c @@ -90,7 +90,6 @@ void main(FSP_INFO_HEADER *fsp_info_header) * Memory is setup and the stack is set by the FSP. */ void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr) { - int cbmem_was_initted; void *cbmem_hob_ptr; timestamp_add_now(TS_AFTER_INITRAM); @@ -113,7 +112,7 @@ void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr) { /* Decode E0000 and F0000 segment to DRAM */ sideband_write(B_UNIT, BMISC, sideband_read(B_UNIT, BMISC) | (1 << 1) | (1 << 0)); - cbmem_was_initted = !cbmem_recovery(0); + cbmem_recovery(0); /* Save the HOB pointer in CBMEM to be used in ramstage*/ cbmem_hob_ptr = cbmem_add(CBMEM_ID_HOB_POINTER, sizeof(*hob_list_ptr)); From 1a7623bc1a76126c90c77ca27f27f2cba5ccae05 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Wed, 22 May 2019 21:05:24 +0200 Subject: [PATCH 287/331] drivers/aspeed/ast2050: Remove variable set but not used MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: Iedda92edf8c4eb7be037dcc0faa6fe8aa0c0754c Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/32945 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Kyösti Mälkki --- src/drivers/aspeed/ast2050/ast2050.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/src/drivers/aspeed/ast2050/ast2050.c b/src/drivers/aspeed/ast2050/ast2050.c index 631372d428..21af5c7c80 100644 --- a/src/drivers/aspeed/ast2050/ast2050.c +++ b/src/drivers/aspeed/ast2050/ast2050.c @@ -37,13 +37,12 @@ static void aspeed_ast2050_set_resources(struct device *dev) static void aspeed_ast2050_init(struct device *dev) { - u8 ret; struct drm_device drm_dev; drm_dev.pdev = dev; printk(BIOS_INFO, "ASpeed AST2050: initializing video device\n"); - ret = ast_driver_load(&drm_dev, 0); + ast_driver_load(&drm_dev, 0); /* Unlock extended configuration registers */ outb(0x80, 0x3d4); outb(0xa8, 0x3d5); From 156936b7711457157078ced41ea87529cb65aa2e Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Thu, 23 May 2019 23:16:11 +0200 Subject: [PATCH 288/331] nb/amd/amdmct/mct_ddr3/mct_d.c: Remove variable set but not used Change-Id: Icd9c0541d9006f4ebddcefff9d2355056af0c5c4 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/32972 Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c index 42e91b6130..5be456695e 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c @@ -3810,7 +3810,7 @@ static void HTMemMapInit_D(struct MCTStatStruc *pMCTstat, { u8 Node; u32 NextBase, BottomIO; - u8 _MemHoleRemap, DramHoleBase, DramHoleOffset; + u8 _MemHoleRemap, DramHoleBase; u32 HoleSize, DramSelBaseAddr; u32 val; @@ -3869,7 +3869,6 @@ static void HTMemMapInit_D(struct MCTStatStruc *pMCTstat, if ((DramSelBaseAddr > 0) && (DramSelBaseAddr < BottomIO)) base = DramSelBaseAddr; val = ((base + HoleSize) >> (24-8)) & 0xFF; - DramHoleOffset = val; val <<= 8; /* shl 16, rol 24 */ val |= DramHoleBase << 24; val |= 1 << DramHoleValid; From 4be1f8a2f6be29e7a9983d068c2356b7728f91d5 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Sat, 25 May 2019 19:38:03 +0200 Subject: [PATCH 289/331] sb/nvidia/mcp55: Remove variable set but not used Change-Id: Ic8f6c264aedbdab0eacb6a99a32cc90336e08d84 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/33011 Reviewed-by: Arthur Heymans Tested-by: build bot (Jenkins) --- src/southbridge/nvidia/mcp55/lpc.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/src/southbridge/nvidia/mcp55/lpc.c b/src/southbridge/nvidia/mcp55/lpc.c index 1aef631ee6..6416dd37b0 100644 --- a/src/southbridge/nvidia/mcp55/lpc.c +++ b/src/southbridge/nvidia/mcp55/lpc.c @@ -100,10 +100,9 @@ static void lpc_init(struct device *dev) get_option(&on, "slow_cpu"); if (on) { u16 pm10_bar; - u32 dword; pm10_bar = (pci_read_config16(dev, 0x60) & 0xff00); outl(((on << 1) + 0x10), (pm10_bar + 0x10)); - dword = inl(pm10_bar + 0x10); + inl(pm10_bar + 0x10); on = 8 - on; printk(BIOS_DEBUG, "Throttling CPU %2d.%1.1d percent.\n", (on * 12) + (on >> 1), (on & 1) * 5); From 99f1d5033591a28bf6b6a142adc24b285abc7870 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Sat, 25 May 2019 11:47:56 +0200 Subject: [PATCH 290/331] cpu/amd/family_10h-family_15h: Remove variable set but not used Change-Id: Ifc63ec5b588f8edcec5eda343ec9694332845045 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/33006 Reviewed-by: Angel Pons Reviewed-by: Marshall Dawson Tested-by: build bot (Jenkins) --- src/cpu/amd/family_10h-family_15h/init_cpus.c | 22 +++++++------------ 1 file changed, 8 insertions(+), 14 deletions(-) diff --git a/src/cpu/amd/family_10h-family_15h/init_cpus.c b/src/cpu/amd/family_10h-family_15h/init_cpus.c index 310706ba95..d6a4725e2e 100644 --- a/src/cpu/amd/family_10h-family_15h/init_cpus.c +++ b/src/cpu/amd/family_10h-family_15h/init_cpus.c @@ -986,7 +986,6 @@ void cpuSetAMDMSR(uint8_t node_id) uint8_t nvram; u32 platform; uint64_t revision; - uint8_t enable_c_states; uint8_t enable_cpb; printk(BIOS_DEBUG, "cpuSetAMDMSR "); @@ -1062,21 +1061,16 @@ void cpuSetAMDMSR(uint8_t node_id) } if (revision & (AMD_DR_Ex | AMD_FAM15_ALL)) { - enable_c_states = 0; if (CONFIG(HAVE_ACPI_TABLES)) - if (get_option(&nvram, "cpu_c_states") == CB_SUCCESS) - enable_c_states = !!nvram; - - if (enable_c_states) { - /* Set up the C-state base address */ - msr_t c_state_addr_msr; - c_state_addr_msr = rdmsr(MSR_CSTATE_ADDRESS); - c_state_addr_msr.lo = ACPI_CPU_P_LVL2; /* CstateAddr = ACPI_CPU_P_LVL2 */ - wrmsr(MSR_CSTATE_ADDRESS, c_state_addr_msr); - } + if ((get_option(&nvram, "cpu_c_states") == CB_SUCCESS) && + (nvram)) { + /* Set up the C-state base address */ + msr_t c_state_addr_msr; + c_state_addr_msr = rdmsr(MSR_CSTATE_ADDRESS); + c_state_addr_msr.lo = ACPI_CPU_P_LVL2; + wrmsr(MSR_CSTATE_ADDRESS, c_state_addr_msr); + } } -#else - enable_c_states = 0; #endif if (revision & AMD_FAM15_ALL) { From 95794693cb0270b63b9f209567313c2e052cce02 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Sat, 25 May 2019 13:34:51 +0200 Subject: [PATCH 291/331] sb/nvidia/ck804: Remove variable set but not used Change-Id: Ia8586e229e04fa11696a846653a3a54909ca7c1a Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/33007 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/southbridge/nvidia/ck804/ck804.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/src/southbridge/nvidia/ck804/ck804.c b/src/southbridge/nvidia/ck804/ck804.c index 59796e1add..02d70a694d 100644 --- a/src/southbridge/nvidia/ck804/ck804.c +++ b/src/southbridge/nvidia/ck804/ck804.c @@ -58,9 +58,6 @@ static void ck804_enable(struct device *dev) u32 reg_old, reg; u8 byte; - struct southbridge_nvidia_ck804_config *conf; - conf = dev->chip_info; - if (dev->device == 0x0000) { vendorid = pci_read_config32(dev, PCI_VENDOR_ID); deviceid = (vendorid >> 16) & 0xffff; From 6b7171b32c59fd8aa4aea79f88e59a376ef00064 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Sat, 25 May 2019 20:21:18 +0200 Subject: [PATCH 292/331] nb/amd/pi/00630F01/northbridge.c: Remove variable set but not used Change-Id: Id5e762880ddfcb65872a50e8ffe10d86b3719b5d Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/33012 Tested-by: build bot (Jenkins) Reviewed-by: Marshall Dawson --- src/northbridge/amd/pi/00630F01/northbridge.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/src/northbridge/amd/pi/00630F01/northbridge.c b/src/northbridge/amd/pi/00630F01/northbridge.c index eca2f0c73d..309a762840 100644 --- a/src/northbridge/amd/pi/00630F01/northbridge.c +++ b/src/northbridge/amd/pi/00630F01/northbridge.c @@ -463,11 +463,9 @@ static unsigned long agesa_write_acpi_tables(struct device *device, acpi_header_t *ssdt; acpi_header_t *alib; acpi_header_t *ivrs; - acpi_hest_t *hest; /* HEST */ current = ALIGN(current, 8); - hest = (acpi_hest_t *)current; acpi_write_hest((void *)current, acpi_fill_hest); acpi_add_table(rsdp, (void *)current); current += ((acpi_header_t *)current)->length; @@ -680,7 +678,6 @@ static void domain_set_resources(struct device *dev) struct bus *link; #if CONFIG_HW_MEM_HOLE_SIZEK != 0 struct hw_mem_hole_info mem_hole; - u32 reset_memhole = 1; #endif pci_tolm = 0xffffffffUL; @@ -711,7 +708,6 @@ static void domain_set_resources(struct device *dev) // Use hole_basek as mmio_basek, and we don't need to reset hole anymore if ((mem_hole.node_id != -1) && (mmio_basek > mem_hole.hole_startk)) { mmio_basek = mem_hole.hole_startk; - reset_memhole = 0; } #endif From c6d503fb8198c4e2df3cabfa9a1c3fa142e7d7e4 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Wed, 29 May 2019 12:44:04 +0200 Subject: [PATCH 293/331] sb//nvidia/mcp55/mcp55.c: Remove variable set but not used Change-Id: I40cae58a7a7c9c3c20367541853001510a59e42b Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/33061 Reviewed-by: Patrick Georgi Tested-by: build bot (Jenkins) --- src/southbridge/nvidia/mcp55/mcp55.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/src/southbridge/nvidia/mcp55/mcp55.c b/src/southbridge/nvidia/mcp55/mcp55.c index f93ec92a70..bd49d9be5f 100644 --- a/src/southbridge/nvidia/mcp55/mcp55.c +++ b/src/southbridge/nvidia/mcp55/mcp55.c @@ -59,8 +59,6 @@ void mcp55_enable(struct device *dev) u32 reg_old, reg; u8 byte; unsigned deviceid, vendorid, devfn; - struct southbridge_nvidia_mcp55_config *conf; - conf = dev->chip_info; int i; if (dev->device == 0x0000) { From 920bab553ef51ae33d2a87a1e1ff951149624d2c Mon Sep 17 00:00:00 2001 From: Marshall Dawson Date: Tue, 21 May 2019 17:56:34 -0600 Subject: [PATCH 294/331] soc/amd/stoneyridge: Fix alignment in iomap.h Change-Id: I79e8bc425d5db45abaeb655f86773f3bb1b2f8c4 Signed-off-by: Marshall Dawson Reviewed-on: https://review.coreboot.org/c/coreboot/+/32933 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/soc/amd/stoneyridge/include/soc/iomap.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/soc/amd/stoneyridge/include/soc/iomap.h b/src/soc/amd/stoneyridge/include/soc/iomap.h index 7762043119..1caef3362f 100644 --- a/src/soc/amd/stoneyridge/include/soc/iomap.h +++ b/src/soc/amd/stoneyridge/include/soc/iomap.h @@ -26,9 +26,9 @@ #include /* I2C fixed address */ -#define I2C_BASE_ADDRESS 0xfedc2000 -#define I2C_DEVICE_SIZE 0x00001000 -#define I2C_DEVICE_COUNT 4 +#define I2C_BASE_ADDRESS 0xfedc2000 +#define I2C_DEVICE_SIZE 0x00001000 +#define I2C_DEVICE_COUNT 4 #if CONFIG(HPET_ADDRESS_OVERRIDE) #error HPET address override is not allowed and must be fixed at 0xfed00000 From 4b55935173d2267635486d13016c7148f1e2955d Mon Sep 17 00:00:00 2001 From: Christian Walter Date: Tue, 28 May 2019 13:36:07 +0200 Subject: [PATCH 295/331] src/soc/intel/common/block/sgx: Add missing new lines Added missing new lines to Debug Output. Change-Id: I30f208a60661451bc0794c705113e8d19a68b0eb Signed-off-by: Christian Walter Reviewed-on: https://review.coreboot.org/c/coreboot/+/33035 Reviewed-by: Philipp Deppenwiese Tested-by: build bot (Jenkins) --- src/soc/intel/common/block/sgx/sgx.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/soc/intel/common/block/sgx/sgx.c b/src/soc/intel/common/block/sgx/sgx.c index 2d4cc53aa7..60714d9ce2 100644 --- a/src/soc/intel/common/block/sgx/sgx.c +++ b/src/soc/intel/common/block/sgx/sgx.c @@ -100,8 +100,8 @@ void prmrr_core_configure(void) return; } - printk(BIOS_INFO, "SGX: prmrr_base = 0x%llx", prmrr_base.data64); - printk(BIOS_INFO, "SGX: prmrr_mask = 0x%llx", prmrr_mask.data64); + printk(BIOS_INFO, "SGX: prmrr_base = 0x%llx\n", prmrr_base.data64); + printk(BIOS_INFO, "SGX: prmrr_mask = 0x%llx\n", prmrr_mask.data64); /* Program core PRMRR MSRs. * - Set cache writeback mem attrib in PRMRR base MSR From 10ed374d7d6555992a7434370130d813bfa3ad89 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Wed, 29 May 2019 14:57:06 +0200 Subject: [PATCH 296/331] sb/intel/i82801ix: Select SOUTHBRIDGE_INTEL_COMMON_SPI This allows to use the CONFIG_CONSOLE_SPI_FLASH. Change-Id: I563c69ce6337d46380f889f42633e858ac207916 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/33064 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph --- src/southbridge/intel/i82801ix/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/src/southbridge/intel/i82801ix/Kconfig b/src/southbridge/intel/i82801ix/Kconfig index a2697739a8..5edb8a1426 100644 --- a/src/southbridge/intel/i82801ix/Kconfig +++ b/src/southbridge/intel/i82801ix/Kconfig @@ -18,6 +18,7 @@ config SOUTHBRIDGE_INTEL_I82801IX bool select SOUTHBRIDGE_INTEL_COMMON select SOUTHBRIDGE_INTEL_COMMON_SMBUS + select SOUTHBRIDGE_INTEL_COMMON_SPI if !BOARD_EMULATION_QEMU_X86_Q35 select SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ select IOAPIC select HAVE_USBDEBUG From 9995418166bc4074de2a99aa50e74f8a88196c39 Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Wed, 29 May 2019 23:33:06 +0200 Subject: [PATCH 297/331] soc/intel: Replace UART_BASE() and friends with a Kconfig Re-add the Kconfig CONSOLE_UART_BASE_ADDRESS. It was lost by accident on APL at least. It is used outside of soc/intel/ scope, e.g. to con- figure SeaBIOS. As we only ever configure a single UART for the coreboot console, we don't need different addresses for each possible UART. Which saves us a lot of code. Change-Id: I28e1d98aa37a6acb57b98b8882fc4fa131d5d309 Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/c/coreboot/+/33098 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph --- src/soc/intel/apollolake/Kconfig | 5 +++++ src/soc/intel/apollolake/include/soc/iomap.h | 8 -------- src/soc/intel/cannonlake/Kconfig | 5 +++++ src/soc/intel/cannonlake/include/soc/iomap.h | 8 -------- src/soc/intel/common/acpi/acpi_debug.asl | 2 +- src/soc/intel/common/block/uart/uart.c | 9 ++++----- src/soc/intel/icelake/Kconfig | 5 +++++ src/soc/intel/icelake/include/soc/iomap.h | 8 -------- src/soc/intel/skylake/Kconfig | 5 +++++ src/soc/intel/skylake/include/soc/iomap.h | 7 ------- 10 files changed, 25 insertions(+), 37 deletions(-) diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 217d1eab24..1f819eab06 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -361,6 +361,11 @@ config CPU_BCLK_MHZ int default 100 +config CONSOLE_UART_BASE_ADDRESS + hex + default 0xddffc000 + depends on INTEL_LPSS_UART_FOR_CONSOLE + config APL_SKIP_SET_POWER_LIMITS bool default n diff --git a/src/soc/intel/apollolake/include/soc/iomap.h b/src/soc/intel/apollolake/include/soc/iomap.h index 8e2986d8b7..4b82365284 100644 --- a/src/soc/intel/apollolake/include/soc/iomap.h +++ b/src/soc/intel/apollolake/include/soc/iomap.h @@ -58,12 +58,4 @@ #define EARLY_I2C_BASE_ADDRESS 0xfe020000 #define EARLY_I2C_BASE(x) (EARLY_I2C_BASE_ADDRESS + (0x1000 * (x))) -#define UART_BASE_SIZE 0x1000 - -#define UART_BASE_0_ADDRESS 0xddffc000 -/* UART BARs are 4KB in size */ -#define UART_BASE_0_ADDR(x) (UART_BASE_0_ADDRESS + (2 * \ - UART_BASE_SIZE * (x))) -#define UART_BASE(x) UART_BASE_0_ADDR(x) - #endif /* _SOC_APOLLOLAKE_IOMAP_H_ */ diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index e524275b8f..76906b2548 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -223,6 +223,11 @@ config SOC_INTEL_I2C_DEV_MAX default 4 if SOC_INTEL_CANNONLAKE_PCH_H default 6 +config CONSOLE_UART_BASE_ADDRESS + hex + default 0xfe032000 + depends on INTEL_LPSS_UART_FOR_CONSOLE + # Clock divider parameters for 115200 baud rate config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL hex diff --git a/src/soc/intel/cannonlake/include/soc/iomap.h b/src/soc/intel/cannonlake/include/soc/iomap.h index 100bd11356..1ebaf3f7b6 100644 --- a/src/soc/intel/cannonlake/include/soc/iomap.h +++ b/src/soc/intel/cannonlake/include/soc/iomap.h @@ -29,14 +29,6 @@ #define PCH_TRACE_HUB_BASE_ADDRESS 0xfc800000 #define PCH_TRACE_HUB_BASE_SIZE 0x00800000 -#define UART_BASE_SIZE 0x1000 - -#define UART_BASE_0_ADDRESS 0xfe032000 -/* Both UART BAR 0 and 1 are 4KB in size */ -#define UART_BASE_0_ADDR(x) (UART_BASE_0_ADDRESS + (2 * \ - UART_BASE_SIZE * (x))) -#define UART_BASE(x) UART_BASE_0_ADDR(x) - #define EARLY_I2C_BASE_ADDRESS 0xfe040000 #define EARLY_I2C_BASE(x) (EARLY_I2C_BASE_ADDRESS + (0x1000 * (x))) diff --git a/src/soc/intel/common/acpi/acpi_debug.asl b/src/soc/intel/common/acpi/acpi_debug.asl index 6c52bbfd77..0c0be154e6 100644 --- a/src/soc/intel/common/acpi/acpi_debug.asl +++ b/src/soc/intel/common/acpi/acpi_debug.asl @@ -59,7 +59,7 @@ Method (APRT, 1, Serialized) #if CONFIG(DRIVERS_UART_8250MEM_32) OperationRegion (UBAR, SystemMemory, - UART_BASE_0_ADDR(CONFIG_UART_FOR_CONSOLE), 24) + CONFIG_CONSOLE_UART_BASE_ADDRESS, 24) Field (UBAR, AnyAcc, NoLock, Preserve) { TDR, 8, /* Transmit Data Register BAR + 0x000 */ diff --git a/src/soc/intel/common/block/uart/uart.c b/src/soc/intel/common/block/uart/uart.c index 84ba1ee0f2..9d820ffd7e 100644 --- a/src/soc/intel/common/block/uart/uart.c +++ b/src/soc/intel/common/block/uart/uart.c @@ -47,7 +47,7 @@ static void uart_lpss_init(uintptr_t baseaddr) uintptr_t uart_platform_base(int idx) { if (idx == CONFIG_UART_FOR_CONSOLE) - return UART_BASE_0_ADDR(CONFIG_UART_FOR_CONSOLE); + return CONFIG_CONSOLE_UART_BASE_ADDRESS; return 0; } #endif @@ -137,8 +137,7 @@ static void uart_configure_gpio_pads(void) void uart_bootblock_init(void) { /* Program UART BAR0, command, reset and clock register */ - uart_common_init(uart_get_device(), - UART_BASE(CONFIG_UART_FOR_CONSOLE)); + uart_common_init(uart_get_device(), CONFIG_CONSOLE_UART_BASE_ADDRESS); /* Configure the 2 pads per UART. */ uart_configure_gpio_pads(); @@ -155,8 +154,8 @@ static void uart_read_resources(struct device *dev) uart_is_debug_controller(dev)) { struct resource *res = find_resource(dev, PCI_BASE_ADDRESS_0); /* Need to set the base and size for the resource allocator. */ - res->base = UART_BASE(CONFIG_UART_FOR_CONSOLE); - res->size = UART_BASE_SIZE; + res->base = CONFIG_CONSOLE_UART_BASE_ADDRESS; + res->size = 0x1000; res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig index a4b46baab5..052e37dadb 100644 --- a/src/soc/intel/icelake/Kconfig +++ b/src/soc/intel/icelake/Kconfig @@ -138,6 +138,11 @@ config SOC_INTEL_UART_DEV_MAX int default 3 +config CONSOLE_UART_BASE_ADDRESS + hex + default 0xfe032000 + depends on INTEL_LPSS_UART_FOR_CONSOLE + # Clock divider parameters for 115200 baud rate config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL hex diff --git a/src/soc/intel/icelake/include/soc/iomap.h b/src/soc/intel/icelake/include/soc/iomap.h index 7c42b57730..218b8bfa60 100644 --- a/src/soc/intel/icelake/include/soc/iomap.h +++ b/src/soc/intel/icelake/include/soc/iomap.h @@ -28,14 +28,6 @@ #define PCH_TRACE_HUB_BASE_ADDRESS 0xfc800000 #define PCH_TRACE_HUB_BASE_SIZE 0x00800000 -#define UART_BASE_SIZE 0x1000 - -#define UART_BASE_0_ADDRESS 0xfe032000 -/* Both UART BAR 0 and 1 are 4KB in size */ -#define UART_BASE_0_ADDR(x) (UART_BASE_0_ADDRESS + (2 * \ - UART_BASE_SIZE * (x))) -#define UART_BASE(x) UART_BASE_0_ADDR(x) - #define EARLY_I2C_BASE_ADDRESS 0xfe040000 #define EARLY_I2C_BASE(x) (EARLY_I2C_BASE_ADDRESS + (0x1000 * (x))) diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index fcfe2b6591..626b5f80f0 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -289,6 +289,11 @@ config CPU_BCLK_MHZ int default 100 +config CONSOLE_UART_BASE_ADDRESS + hex + default 0xfe030000 + depends on INTEL_LPSS_UART_FOR_CONSOLE + # Clock divider parameters for 115200 baud rate config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL hex diff --git a/src/soc/intel/skylake/include/soc/iomap.h b/src/soc/intel/skylake/include/soc/iomap.h index 628a272a54..c73d766953 100644 --- a/src/soc/intel/skylake/include/soc/iomap.h +++ b/src/soc/intel/skylake/include/soc/iomap.h @@ -25,13 +25,6 @@ #define PCH_PRESERVED_BASE_ADDRESS 0xfc800000 #define PCH_PRESERVED_BASE_SIZE 0x02000000 -#define UART_BASE_SIZE 0x1000 -#define UART_BASE_0_ADDRESS 0xfe030000 -/* Both UART BAR 0 and 1 are 4KB in size */ -#define UART_BASE_0_ADDR(x) (UART_BASE_0_ADDRESS + (2 * \ - UART_BASE_SIZE * (x))) -#define UART_BASE(x) UART_BASE_0_ADDR(x) - #define EARLY_I2C_BASE_ADDRESS 0xfe040000 #define EARLY_I2C_BASE(x) (EARLY_I2C_BASE_ADDRESS + (0x1000 * (x))) From 317cbd6f02e5f49bbc64dd0de0082c313c77c6b1 Mon Sep 17 00:00:00 2001 From: John Zhao Date: Fri, 31 May 2019 10:44:46 -0700 Subject: [PATCH 298/331] src/soc/intel: Avoid NULL pointer dereference Coverity detects pointer mem_info as NULL_RETURNS. Add sanity check for mem_info to prevent NULL pointer dereference. BUG=CID 1401394 TEST=Built and boot up to kernel. Change-Id: I9d78ab38b8b2dd3734e0143acfd88d9093f16ce6 Signed-off-by: John Zhao Reviewed-on: https://review.coreboot.org/c/coreboot/+/33152 Reviewed-by: Martin Roth Tested-by: build bot (Jenkins) --- src/soc/intel/broadwell/romstage/raminit.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/src/soc/intel/broadwell/romstage/raminit.c b/src/soc/intel/broadwell/romstage/raminit.c index fc8b7c6984..c13761df3a 100644 --- a/src/soc/intel/broadwell/romstage/raminit.c +++ b/src/soc/intel/broadwell/romstage/raminit.c @@ -122,6 +122,12 @@ void raminit(struct pei_data *pei_data) printk(BIOS_DEBUG, "create cbmem for dimm information\n"); mem_info = cbmem_add(CBMEM_ID_MEMINFO, sizeof(struct memory_info)); + + if (!mem_info) { + printk(BIOS_ERR, "Error! Failed to add mem_info to cbmem\n"); + return; + } + memset(mem_info, 0, sizeof(*mem_info)); /* Translate pei_memory_info struct data into memory_info struct */ mem_info->dimm_cnt = pei_data->meminfo.dimm_cnt; From 8a2056cac4995dbb69b7e2f2b2a0ca0c5657d5ad Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Fri, 24 May 2019 12:14:52 +0200 Subject: [PATCH 299/331] mainboard/intel/saddlebrook: Remove unused functions MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Setting up the SIO serial console is done in the bootblock. Change-Id: Ideaf8f3dc0ee067e96d3fb5046071551c6d45329 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/32985 Reviewed-by: Christian Walter Reviewed-by: Kyösti Mälkki Tested-by: build bot (Jenkins) --- src/mainboard/intel/saddlebrook/romstage.c | 8 -------- 1 file changed, 8 deletions(-) diff --git a/src/mainboard/intel/saddlebrook/romstage.c b/src/mainboard/intel/saddlebrook/romstage.c index 82b85fd700..45f39d46e2 100644 --- a/src/mainboard/intel/saddlebrook/romstage.c +++ b/src/mainboard/intel/saddlebrook/romstage.c @@ -23,15 +23,7 @@ #include #include "spd/spd.h" #include -#include -#include -#define SERIAL_DEV PNP_DEV(0x2e, NCT6776_SP1) - -void car_mainboard_pre_console_init(void) -{ - nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); -} void mainboard_memory_init_params( struct romstage_params *params, From ef1ab4d6d47c87d976c8186d5d8651853e3c92a9 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Fri, 31 May 2019 16:09:56 +0530 Subject: [PATCH 300/331] arch/riscv/Kconfig: Make correct default value for CONFIG_ARCH_RISCV_M Change-Id: Ib9329904060cab48d527de1b1ccdab5b6fe71b99 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/33144 Reviewed-by: Martin Roth Tested-by: build bot (Jenkins) --- src/arch/riscv/Kconfig | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/arch/riscv/Kconfig b/src/arch/riscv/Kconfig index 9d325af759..25a398068a 100644 --- a/src/arch/riscv/Kconfig +++ b/src/arch/riscv/Kconfig @@ -24,8 +24,8 @@ config ARCH_RISCV_M # one implementation that will not have it due # to security concerns. bool - default n if ARCH_RISCV_M_DISABLED - default y + default y if ARCH_RISCV && !ARCH_RISCV_M_DISABLED + default n config ARCH_RISCV_S # S (supervisor) mode is for kernels. It is optional. From b2709ae0aed724278dfaa3d0af1d68e8fe18cbb1 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Thu, 30 May 2019 17:24:12 -0700 Subject: [PATCH 301/331] soc/intel/cannonlake: Do not read SPD again if index hasn't changed With the recent refactoring of memory configuration in CB:32513 ("soc/intel/cannonlake: Support different SPD read type for each slot"), meminit_cbfs_spd_index ends up reading SPD from CBFS for each slot. However, for mainboards that use the same SPD index for each slot this is unneccessary. This change adds a check to see if spd_data_ptr is not NULL and current spd index is the same as the last call to decide if SPD read from CBFS should be skipped. TEST=Verified that SPD gets read only once on hatch. Change-Id: I91963b55cea534c92207b2cd9f0caa96df8f222b Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/c/coreboot/+/33137 Reviewed-by: Paul Menzel Reviewed-by: Aaron Durbin Reviewed-by: Tim Wawrzynczak Reviewed-by: Philip Chen Tested-by: build bot (Jenkins) --- src/soc/intel/cannonlake/cnl_memcfg_init.c | 31 +++++++++++++++------- 1 file changed, 21 insertions(+), 10 deletions(-) diff --git a/src/soc/intel/cannonlake/cnl_memcfg_init.c b/src/soc/intel/cannonlake/cnl_memcfg_init.c index 4ebd9978ae..d3e5e837fd 100644 --- a/src/soc/intel/cannonlake/cnl_memcfg_init.c +++ b/src/soc/intel/cannonlake/cnl_memcfg_init.c @@ -91,18 +91,29 @@ static void meminit_spd_data(FSP_M_CONFIG *mem_cfg, uint8_t mem_slot, static void meminit_cbfs_spd_index(FSP_M_CONFIG *mem_cfg, int spd_index, uint8_t mem_slot) { - size_t spd_data_len; - uintptr_t spd_data_ptr; - struct region_device spd_rdev; + static size_t spd_data_len; + static uintptr_t spd_data_ptr; + static int last_spd_index; assert(mem_slot < NUM_DIMM_SLOT); - printk(BIOS_DEBUG, "SPD INDEX = %d\n", spd_index); - if (get_spd_cbfs_rdev(&spd_rdev, spd_index) < 0) - die("spd.bin not found or incorrect index\n"); - spd_data_len = region_device_sz(&spd_rdev); - /* Memory leak is ok since we have memory mapped boot media */ - assert(CONFIG(BOOT_DEVICE_MEMORY_MAPPED)); - spd_data_ptr = (uintptr_t)rdev_mmap_full(&spd_rdev); + + if ((spd_data_ptr == 0) || (last_spd_index != spd_index)) { + struct region_device spd_rdev; + + printk(BIOS_DEBUG, "SPD INDEX = %d\n", spd_index); + + if (get_spd_cbfs_rdev(&spd_rdev, spd_index) < 0) + die("spd.bin not found or incorrect index\n"); + + spd_data_len = region_device_sz(&spd_rdev); + + /* Memory leak is ok since we have memory mapped boot media */ + assert(CONFIG(BOOT_DEVICE_MEMORY_MAPPED)); + + spd_data_ptr = (uintptr_t)rdev_mmap_full(&spd_rdev); + last_spd_index = spd_index; + } + meminit_spd_data(mem_cfg, mem_slot, spd_data_len, spd_data_ptr); } From 3cae9afbf91d7b164a033968350f8f60b84301b9 Mon Sep 17 00:00:00 2001 From: Frans Hendriks Date: Fri, 5 Apr 2019 10:00:18 +0200 Subject: [PATCH 302/331] vendorcode/eltan: Add vendor code for measured and verified boot This patch contains the general files for the vendorcode/eltan that has been uploaded recently: - Add eltan directory to vendorcode. - Add documentation about the support in the vendorcode directories. - Add the Makefile.inc and Kconfig for the vendorcode/eltan and vendorcode/eltan/security. BUG=N/A TEST=Created verified binary and verify logging on Portwell PQ-M107 Change-Id: Ic1d5a21d40b6a31886777e8e9fe7b28c860f1a80 Signed-off-by: Frans Hendriks Reviewed-on: https://review.coreboot.org/c/coreboot/+/30218 Tested-by: build bot (Jenkins) Reviewed-by: Philipp Deppenwiese --- Documentation/vendorcode/eltan/index.md | 8 +++++ Documentation/vendorcode/eltan/security.md | 39 ++++++++++++++++++++++ src/vendorcode/Makefile.inc | 1 + src/vendorcode/eltan/Kconfig | 17 ++++++++++ src/vendorcode/eltan/Makefile.inc | 16 +++++++++ src/vendorcode/eltan/security/Kconfig | 16 +++++++++ src/vendorcode/eltan/security/Makefile.inc | 30 +++++++++++++++++ 7 files changed, 127 insertions(+) create mode 100644 Documentation/vendorcode/eltan/index.md create mode 100644 Documentation/vendorcode/eltan/security.md create mode 100644 src/vendorcode/eltan/Kconfig create mode 100644 src/vendorcode/eltan/Makefile.inc create mode 100644 src/vendorcode/eltan/security/Kconfig create mode 100644 src/vendorcode/eltan/security/Makefile.inc diff --git a/Documentation/vendorcode/eltan/index.md b/Documentation/vendorcode/eltan/index.md new file mode 100644 index 0000000000..4484798a23 --- /dev/null +++ b/Documentation/vendorcode/eltan/index.md @@ -0,0 +1,8 @@ +# Eltan vendorcode-specific documentation + +This section contains documentation about coreboot on Eltan specific +vendorcode. + +## Sections + +- [Security](security.md) diff --git a/Documentation/vendorcode/eltan/security.md b/Documentation/vendorcode/eltan/security.md new file mode 100644 index 0000000000..04537df23c --- /dev/null +++ b/Documentation/vendorcode/eltan/security.md @@ -0,0 +1,39 @@ +# Eltan Security + +## Security +This code enables measured boot and verified boot support. +Verified boot is available in coreboot, but based on ChromeOS. This vendorcode +uses a small encryption library and leave much more space in flash for the +payload. + +## Hashing Library +The library suppports SHA-1, SHA-256 and SHA-512. The required routines of +`3rdparty/vboot/firmware/2lib` are used. + +## Measured boot +measured boot support will use TPM2 device if available. The items specified +in `mb_log_list[]` will be measured. + +## Verified boot +verified boot support will use TPM2 device if available. The items specified +in the next table will be verified: +* `bootblock_verify_list[]` +* `verify_item_t romstage_verify_list[]` +* `ram_stage_additional_list[]` +* `ramstage_verify_list[]` +* `payload_verify_list[]` +* `oprom_verify_list[]` + +## Enabling support + +* Measured boot can be enabled using **CONFIG_MBOOT** +* Create mb_log_list table with list of item to measure +* Create tables bootblock_verify_list[], verify_item_t romstage_verify_list[], + ram_stage_additional_list[], ramstage_verify_list[], payload_verify_list[], + oprom_verify_list[] +* Verified boot can be enabled using **CONFIG_VERIFIED_BOOT** +* Added Kconfig values for verbose console output + +## Debugging + +You can enable verbose console output in *menuconfig*. diff --git a/src/vendorcode/Makefile.inc b/src/vendorcode/Makefile.inc index 522d4150e4..8ccb0d0ee7 100644 --- a/src/vendorcode/Makefile.inc +++ b/src/vendorcode/Makefile.inc @@ -3,3 +3,4 @@ subdirs-y += google subdirs-y += intel subdirs-y += siemens subdirs-y += cavium +subdirs-y += eltan diff --git a/src/vendorcode/eltan/Kconfig b/src/vendorcode/eltan/Kconfig new file mode 100644 index 0000000000..731dd2cea3 --- /dev/null +++ b/src/vendorcode/eltan/Kconfig @@ -0,0 +1,17 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2014-2018 Eltan B.V. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +source src/vendorcode/eltan/security/mboot/Kconfig +source src/vendorcode/eltan/security/verified_boot/Kconfig diff --git a/src/vendorcode/eltan/Makefile.inc b/src/vendorcode/eltan/Makefile.inc new file mode 100644 index 0000000000..1f6a4065cf --- /dev/null +++ b/src/vendorcode/eltan/Makefile.inc @@ -0,0 +1,16 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2018 Eltan B.V. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +subdirs-y += security diff --git a/src/vendorcode/eltan/security/Kconfig b/src/vendorcode/eltan/security/Kconfig new file mode 100644 index 0000000000..2af58080da --- /dev/null +++ b/src/vendorcode/eltan/security/Kconfig @@ -0,0 +1,16 @@ +## This file is part of the coreboot project. +## +## Copyright (C) 2018 Eltan B.V. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +source src/vendorcode/eltan/security/mboot/Kconfig +source src/vendorcode/eltan/security/verified_boot/Kconfig diff --git a/src/vendorcode/eltan/security/Makefile.inc b/src/vendorcode/eltan/security/Makefile.inc new file mode 100644 index 0000000000..26b324ba58 --- /dev/null +++ b/src/vendorcode/eltan/security/Makefile.inc @@ -0,0 +1,30 @@ +## This file is part of the coreboot project. +## +## Copyright (C) 2018 Eltan B.V. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +subdirs-y += lib +subdirs-y += verified_boot +subdirs-y += mboot + +ifeq ($(CONFIG_MBOOT), y) +CPPFLAGS_common += -I$(src)/vendorcode/eltan/security/mboot +CPPFLAGS_common += -I$(src)/vendorcode/eltan/security/include +endif + +ifeq ($(CONFIG_VERIFIED_BOOT), y) +CPPFLAGS_common += -I$(src)/vendorcode/eltan/security/verified_boot +endif + +ifeq ($(CONFIG_TPM2),y) +CPPFLAGS_common += -I$(src)/security/include +endif From a99ed13e3397bc536012120aab8cadb827913863 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Mon, 3 Jun 2019 19:02:31 -0700 Subject: [PATCH 303/331] libpayload/i8042/keyboard: Fix return value check for keyboard_cmd CB:32951 ("libpayload: Reset PS/2 keyboard") added a call to reset keyboard and check the return value of keyboard_cmd() to compare against I8042_KBCMD_ACK. However, keyboard_cmd() already checks for ACK and returns 1 or 0 based on whether ACK is received. This change fixes the check introduced by CB:32951 to compare against 0 just like the other checks for keyboard_cmd(). Additionally, it adds error messages for all failed commands in keyboard_init() to make the prints consistent in case of failure. BUG=b:134366527 TEST=Verified that logs do not contain "ERROR: Keyboard reset failed" anymore. Change-Id: Idcadaae12e0a44e404a1d98c6deb633d97058203 Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/c/coreboot/+/33185 Tested-by: build bot (Jenkins) Reviewed-by: Frank Wu Reviewed-by: Paul Menzel --- payloads/libpayload/drivers/i8042/keyboard.c | 22 +++++++++++++------- 1 file changed, 15 insertions(+), 7 deletions(-) diff --git a/payloads/libpayload/drivers/i8042/keyboard.c b/payloads/libpayload/drivers/i8042/keyboard.c index 12255fb7f8..240385ce6d 100644 --- a/payloads/libpayload/drivers/i8042/keyboard.c +++ b/payloads/libpayload/drivers/i8042/keyboard.c @@ -172,7 +172,7 @@ static unsigned char keyboard_cmd(unsigned char cmd) { i8042_write_data(cmd); - return i8042_wait_read_ps2() == 0xfa; + return i8042_wait_read_ps2() == I8042_KBCMD_ACK; } int keyboard_havechar(void) @@ -319,32 +319,40 @@ void keyboard_init(void) /* Reset keyboard and self test (keyboard side) */ ret = keyboard_cmd(I8042_KBCMD_RESET); - if (ret != I8042_KBCMD_ACK) { - printf("ERROR: Keyboard reset failed ACK: 0x%x\n", ret); + if (!ret) { + printf("ERROR: Keyboard reset failed!\n"); return; } /* Set scancode set 1 */ ret = keyboard_cmd(I8042_KBCMD_SET_SCANCODE); - if (!ret && !CONFIG(LP_PC_KEYBOARD_IGNORE_INIT_FAILURE)) + if (!ret && !CONFIG(LP_PC_KEYBOARD_IGNORE_INIT_FAILURE)) { + printf("ERROR: Keyboard set scancode failed!\n"); return; + } ret = keyboard_cmd(I8042_SCANCODE_SET_1); - if (!ret && !CONFIG(LP_PC_KEYBOARD_IGNORE_INIT_FAILURE)) + if (!ret && !CONFIG(LP_PC_KEYBOARD_IGNORE_INIT_FAILURE)) { + printf("ERROR: Keyboard scancode set#1 failed!\n"); return; + } /* * Set default parameters. * Fix for broken QEMU ps/2 make scancodes. */ ret = keyboard_cmd(0xf6); - if (!ret) + if (!ret) { + printf("ERROR: Keyboard set default params failed!\n"); return; + } /* Enable scanning */ ret = keyboard_cmd(I8042_KBCMD_EN); - if (!ret && !CONFIG(LP_PC_KEYBOARD_IGNORE_INIT_FAILURE)) + if (!ret && !CONFIG(LP_PC_KEYBOARD_IGNORE_INIT_FAILURE)) { + printf("ERROR: Keyboard enable scanning failed!\n"); return; + } console_add_input_driver(&cons); } From fca7c4d614eeee1b040cfeba37599b32d0ad55f1 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Sat, 1 Jun 2019 14:44:56 -0700 Subject: [PATCH 304/331] mb/google/hatch: Enable LTR for PCIe ports Enable LTR for NVMe and WiFi PCIe ports so that they can use ASPM L1.2 BUG=b:134195632 TEST=Verified L1 substate with lspci on hatch: Before: L1SubCtl1: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2- ASPM_L1.1+ After: L1SubCtl1: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1+ Change-Id: I7fce60897b78dde12747ac7fb857c988d16118ab Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/c/coreboot/+/33161 Reviewed-by: Patrick Georgi Reviewed-by: Paul Menzel Reviewed-by: Paul Fagerburg Tested-by: build bot (Jenkins) --- src/mainboard/google/hatch/variants/baseboard/devicetree.cb | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index 9d10cac41b..1123d53734 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -72,6 +72,7 @@ chip soc/intel/cannonlake # Enable Root port 9(x4) for NVMe. register "PcieRpEnable[8]" = "1" + register "PcieRpLtrEnable[8]" = "1" # RP 9 uses CLK SRC 1 register "PcieClkSrcUsage[1]" = "8" # ClkReq-to-ClkSrc mapping for CLK SRC 1 @@ -79,6 +80,7 @@ chip soc/intel/cannonlake # PCIe port 14 for M.2 E-key WLAN register "PcieRpEnable[13]" = "1" + register "PcieRpLtrEnable[13]" = "1" # RP 14 uses CLK SRC 3 register "PcieClkSrcUsage[3]" = "13" register "PcieClkSrcClkReq[3]" = "3" From 9636a106d43453976addb39253cf70bc65ea1224 Mon Sep 17 00:00:00 2001 From: Julius Werner Date: Fri, 3 May 2019 17:36:43 -0700 Subject: [PATCH 305/331] device_tree: Switch allocations to xzalloc() The FIT code is already using xzalloc() everywhere, and that's the only real consumer of device tree code right now. Chances are if you're trying to unflatten an FDT and it doesn't fit into the heap you're pretty much screwed anyway, so all the OOM handling feels a bit unnecessary (and some functions will just silently fail because they don't have a return value, which is bad). Let's just switch this all to die on failed allocations. Change-Id: I738f24d550a776653b2becd3d4f7d4d2cb3cc048 Signed-off-by: Julius Werner Reviewed-on: https://review.coreboot.org/c/coreboot/+/32861 Reviewed-by: Hung-Te Lin Tested-by: build bot (Jenkins) --- src/lib/device_tree.c | 55 ++++++++----------------------------------- src/lib/fit.c | 2 +- 2 files changed, 11 insertions(+), 46 deletions(-) diff --git a/src/lib/device_tree.c b/src/lib/device_tree.c index 8dbc510c10..bb40eee231 100644 --- a/src/lib/device_tree.c +++ b/src/lib/device_tree.c @@ -16,6 +16,7 @@ */ #include +#include #include #include #include @@ -153,24 +154,6 @@ int fdt_skip_node(const void *blob, uint32_t start_offset) /* * Functions to turn a flattened tree into an unflattened one. */ -static struct device_tree_node *alloc_node(void) -{ - struct device_tree_node *buf = malloc(sizeof(struct device_tree_node)); - if (!buf) - return NULL; - memset(buf, 0, sizeof(*buf)); - return buf; -} - -static struct device_tree_property *alloc_prop(void) -{ - struct device_tree_property *buf = - malloc(sizeof(struct device_tree_property)); - if (!buf) - return NULL; - memset(buf, 0, sizeof(*buf)); - return buf; -} static int fdt_unflatten_node(const void *blob, uint32_t start_offset, struct device_tree_node **new_node) @@ -185,18 +168,14 @@ static int fdt_unflatten_node(const void *blob, uint32_t start_offset, return 0; offset += size; - struct device_tree_node *node = alloc_node(); + struct device_tree_node *node = xzalloc(sizeof(*node)); *new_node = node; - if (!node) - return 0; node->name = name; struct fdt_property fprop; last = &node->properties; while ((size = fdt_next_property(blob, offset, &fprop))) { - struct device_tree_property *prop = alloc_prop(); - if (!prop) - return 0; + struct device_tree_property *prop = xzalloc(sizeof(*prop)); prop->prop = fprop; list_insert_after(&prop->list_node, last); @@ -227,10 +206,7 @@ static int fdt_unflatten_map_entry(const void *blob, uint32_t offset, if (!size) return 0; - struct device_tree_reserve_map_entry *entry = malloc(sizeof(*entry)); - if (!entry) - return 0; - memset(entry, 0, sizeof(*entry)); + struct device_tree_reserve_map_entry *entry = xzalloc(sizeof(*entry)); *new = entry; entry->start = start; entry->size = size; @@ -240,11 +216,8 @@ static int fdt_unflatten_map_entry(const void *blob, uint32_t offset, struct device_tree *fdt_unflatten(const void *blob) { - struct device_tree *tree = malloc(sizeof(*tree)); + struct device_tree *tree = xzalloc(sizeof(*tree)); const struct fdt_header *header = (const struct fdt_header *)blob; - if (!tree) - return NULL; - memset(tree, 0, sizeof(*tree)); tree->header = header; uint32_t struct_offset = be32toh(header->structure_offset); @@ -534,7 +507,7 @@ struct device_tree_node *dt_find_node(struct device_tree_node *parent, if (!create) return NULL; - found = alloc_node(); + found = malloc(sizeof(*found)); if (!found) return NULL; found->name = strdup(*path); @@ -804,9 +777,7 @@ void dt_add_bin_prop(struct device_tree_node *node, const char *name, } } - prop = alloc_prop(); - if (!prop) - return; + prop = xzalloc(sizeof(*prop)); list_insert_after(&prop->list_node, &node->properties); prop->prop.name = name; prop->prop.data = data; @@ -878,9 +849,7 @@ void dt_add_string_prop(struct device_tree_node *node, const char *name, */ void dt_add_u32_prop(struct device_tree_node *node, const char *name, u32 val) { - u32 *val_ptr = malloc(sizeof(val)); - if (!val_ptr) - return; + u32 *val_ptr = xmalloc(sizeof(val)); *val_ptr = htobe32(val); dt_add_bin_prop(node, name, val_ptr, sizeof(*val_ptr)); } @@ -894,9 +863,7 @@ void dt_add_u32_prop(struct device_tree_node *node, const char *name, u32 val) */ void dt_add_u64_prop(struct device_tree_node *node, const char *name, u64 val) { - u64 *val_ptr = malloc(sizeof(val)); - if (!val_ptr) - return; + u64 *val_ptr = xmalloc(sizeof(val)); *val_ptr = htobe64(val); dt_add_bin_prop(node, name, val_ptr, sizeof(*val_ptr)); } @@ -916,9 +883,7 @@ void dt_add_reg_prop(struct device_tree_node *node, u64 *addrs, u64 *sizes, { int i; size_t length = (addr_cells + size_cells) * sizeof(u32) * count; - u8 *data = malloc(length); - if (!data) - return; + u8 *data = xmalloc(length); u8 *cur = data; for (i = 0; i < count; i++) { diff --git a/src/lib/fit.c b/src/lib/fit.c index 3aad806f2e..d15641db9a 100644 --- a/src/lib/fit.c +++ b/src/lib/fit.c @@ -27,7 +27,7 @@ #include #include #include -#include +#include static struct list_node image_nodes; static struct list_node config_nodes; From 73eaec81689662cf5c1cd6ac5de1152e19b0c14d Mon Sep 17 00:00:00 2001 From: Julius Werner Date: Fri, 3 May 2019 17:58:07 -0700 Subject: [PATCH 306/331] device_tree: Add version checks This patch adds a few more sanity checks to the FDT header parsing to make sure that our code can support the version that is passed in. This patch was adapted from depthcharge's http://crosreview.com/1536384 Change-Id: I06c112f540213c8db7c2455c2e8a4e8e4f337b78 Signed-off-by: Julius Werner Reviewed-on: https://review.coreboot.org/c/coreboot/+/32862 Reviewed-by: Hung-Te Lin Reviewed-by: Paul Menzel Tested-by: build bot (Jenkins) --- src/include/device_tree.h | 3 ++- src/lib/device_tree.c | 18 ++++++++++++++++++ src/lib/fit.c | 8 +++----- 3 files changed, 23 insertions(+), 6 deletions(-) diff --git a/src/include/device_tree.h b/src/include/device_tree.h index 14be8322c6..96902b893b 100644 --- a/src/include/device_tree.h +++ b/src/include/device_tree.h @@ -33,7 +33,7 @@ struct fdt_header { uint32_t reserve_map_offset; uint32_t version; - uint32_t last_compatible_version; + uint32_t last_comp_version; uint32_t boot_cpuid_phys; @@ -42,6 +42,7 @@ struct fdt_header { }; #define FDT_HEADER_MAGIC 0xd00dfeed +#define FDT_SUPPORTED_VERSION 17 #define FDT_TOKEN_BEGIN_NODE 1 #define FDT_TOKEN_END_NODE 2 #define FDT_TOKEN_PROPERTY 3 diff --git a/src/lib/device_tree.c b/src/lib/device_tree.c index bb40eee231..7a3128efcf 100644 --- a/src/lib/device_tree.c +++ b/src/lib/device_tree.c @@ -220,6 +220,24 @@ struct device_tree *fdt_unflatten(const void *blob) const struct fdt_header *header = (const struct fdt_header *)blob; tree->header = header; + uint32_t magic = be32toh(header->magic); + uint32_t version = be32toh(header->version); + uint32_t last_comp_version = be32toh(header->last_comp_version); + + if (magic != FDT_HEADER_MAGIC) { + printk(BIOS_DEBUG, "Invalid device tree magic %#.8x!\n", magic); + return NULL; + } + if (last_comp_version > FDT_SUPPORTED_VERSION) { + printk(BIOS_DEBUG, "Unsupported device tree version %u(>=%u)\n", + version, last_comp_version); + return NULL; + } + if (version > FDT_SUPPORTED_VERSION) + printk(BIOS_DEBUG, + "NOTE: FDT version %u too new, should add support!\n", + version); + uint32_t struct_offset = be32toh(header->structure_offset); uint32_t strings_offset = be32toh(header->strings_offset); uint32_t reserve_offset = be32toh(header->reserve_map_offset); diff --git a/src/lib/fit.c b/src/lib/fit.c index d15641db9a..c98ba2f802 100644 --- a/src/lib/fit.c +++ b/src/lib/fit.c @@ -423,19 +423,17 @@ static void fit_update_compat(const void *fdt_blob, struct fit_config_node *fit_load(void *fit) { - struct fdt_header *header = (struct fdt_header *)fit; struct fit_image_node *image; struct fit_config_node *config; struct compat_string_entry *compat_node; printk(BIOS_DEBUG, "FIT: Loading FIT from %p\n", fit); - if (be32toh(header->magic) != FDT_HEADER_MAGIC) { - printk(BIOS_ERR, "FIT: Bad header magic value 0x%08x.\n", - be32toh(header->magic)); + struct device_tree *tree = fdt_unflatten(fit); + if (!tree) { + printk(BIOS_ERR, "ERROR: Failed to unflatten FIT image!\n"); return NULL; } - struct device_tree *tree = fdt_unflatten(fit); const char *default_config_name = NULL; struct fit_config_node *default_config = NULL; From 6702b68a7966d584e310bf7a99f4a1dc57f2f56f Mon Sep 17 00:00:00 2001 From: Julius Werner Date: Fri, 3 May 2019 18:13:53 -0700 Subject: [PATCH 307/331] device_tree: Add phandle caching and lookups This patch caches phandles when unflattening the device tree, so we don't have to look up the phandle property again every time we're trying to find the phandle of a node. This is especially important when supporting phandle lookups, which are also added. In addition we keep track of the highest phandle in the whole tree, which will be important for applying overlays later. With this, dt_get_phandle(node) becomes obsolete because the phandle is already available as a member variable in the node. This patch was adapted from depthcharge's http://crosreview.com/1536385 Change-Id: I9cbd67d1d13e57c25d068b3db18bb75c709d7ebe Signed-off-by: Julius Werner Reviewed-on: https://review.coreboot.org/c/coreboot/+/32863 Reviewed-by: Hung-Te Lin Tested-by: build bot (Jenkins) --- src/include/device_tree.h | 8 +++-- src/lib/device_tree.c | 59 ++++++++++++++++++++++--------------- src/soc/cavium/cn81xx/soc.c | 2 +- 3 files changed, 42 insertions(+), 27 deletions(-) diff --git a/src/include/device_tree.h b/src/include/device_tree.h index 96902b893b..8280dad077 100644 --- a/src/include/device_tree.h +++ b/src/include/device_tree.h @@ -47,6 +47,7 @@ struct fdt_header { #define FDT_TOKEN_END_NODE 2 #define FDT_TOKEN_PROPERTY 3 #define FDT_TOKEN_END 9 +#define FDT_PHANDLE_ILLEGAL 0xdeadbeef struct fdt_property { @@ -71,6 +72,8 @@ struct device_tree_property struct device_tree_node { const char *name; + uint32_t phandle; + // List of struct device_tree_property-s. struct list_node properties; // List of struct device_tree_nodes. @@ -91,6 +94,7 @@ struct device_tree { const void *header; uint32_t header_size; + uint32_t max_phandle; struct list_node reserve_map; @@ -136,6 +140,8 @@ void dt_read_cell_props(const struct device_tree_node *node, u32 *addrcp, // represented as an array of strings. struct device_tree_node *dt_find_node(struct device_tree_node *parent, const char **path, u32 *addrcp, u32 *sizecp, int create); +struct device_tree_node *dt_find_node_by_phandle(struct device_tree_node *root, + uint32_t phandle); // Look up or create a node relative to a parent node, through its path // represented as a string of '/' separated node names. struct device_tree_node *dt_find_node_by_path(struct device_tree_node *parent, const char *path, @@ -150,8 +156,6 @@ struct device_tree_node *dt_find_next_compat_child(struct device_tree_node *pare // Look up a node relative to a parent node, through its property value. struct device_tree_node *dt_find_prop_value(struct device_tree_node *parent, const char *name, void *data, size_t size); -// Return the phandle -uint32_t dt_get_phandle(const struct device_tree_node *node); // Write src into *dest as a 'length'-byte big-endian integer. void dt_write_int(u8 *dest, u64 src, size_t length); // Delete a property diff --git a/src/lib/device_tree.c b/src/lib/device_tree.c index 7a3128efcf..44eca4e2a8 100644 --- a/src/lib/device_tree.c +++ b/src/lib/device_tree.c @@ -66,6 +66,12 @@ int fdt_node_name(const void *blob, uint32_t offset, const char **name) return ALIGN_UP(strlen((char *)ptr) + 1, sizeof(uint32_t)) + 4; } +static int dt_prop_is_phandle(struct device_tree_property *prop) +{ + return !(strcmp("phandle", prop->prop.name) && + strcmp("linux,phandle", prop->prop.name)); +} + /* @@ -156,6 +162,7 @@ int fdt_skip_node(const void *blob, uint32_t start_offset) */ static int fdt_unflatten_node(const void *blob, uint32_t start_offset, + struct device_tree *tree, struct device_tree_node **new_node) { struct list_node *last; @@ -178,6 +185,12 @@ static int fdt_unflatten_node(const void *blob, uint32_t start_offset, struct device_tree_property *prop = xzalloc(sizeof(*prop)); prop->prop = fprop; + if (dt_prop_is_phandle(prop)) { + node->phandle = be32dec(prop->prop.data); + if (node->phandle > tree->max_phandle) + tree->max_phandle = node->phandle; + } + list_insert_after(&prop->list_node, last); last = &prop->list_node; @@ -186,7 +199,7 @@ static int fdt_unflatten_node(const void *blob, uint32_t start_offset, struct device_tree_node *child; last = &node->children; - while ((size = fdt_unflatten_node(blob, offset, &child))) { + while ((size = fdt_unflatten_node(blob, offset, tree, &child))) { list_insert_after(&child->list_node, last); last = &child->list_node; @@ -260,7 +273,7 @@ struct device_tree *fdt_unflatten(const void *blob) offset += size; } - fdt_unflatten_node(blob, struct_offset, &tree->root); + fdt_unflatten_node(blob, struct_offset, tree, &tree->root); return tree; } @@ -590,6 +603,26 @@ struct device_tree_node *dt_find_node_by_path(struct device_tree_node *parent, return node; } +struct device_tree_node *dt_find_node_by_phandle(struct device_tree_node *root, + uint32_t phandle) +{ + if (!root) + return NULL; + + if (root->phandle == phandle) + return root; + + struct device_tree_node *node; + struct device_tree_node *result; + list_for_each(node, root->children, list_node) { + result = dt_find_node_by_phandle(node, phandle); + if (result) + return result; + } + + return NULL; +} + /* * Check if given node is compatible. * @@ -719,28 +752,6 @@ struct device_tree_node *dt_find_prop_value(struct device_tree_node *parent, return NULL; } -/** - * Find the phandle of a node. - * - * @param node Pointer to node containing the phandle - * @return Zero on error, the phandle on success - */ -uint32_t dt_get_phandle(const struct device_tree_node *node) -{ - const uint32_t *phandle; - size_t len; - - dt_find_bin_prop(node, "phandle", (const void **)&phandle, &len); - if (phandle != NULL && len == sizeof(*phandle)) - return be32_to_cpu(*phandle); - - dt_find_bin_prop(node, "linux,phandle", (const void **)&phandle, &len); - if (phandle != NULL && len == sizeof(*phandle)) - return be32_to_cpu(*phandle); - - return 0; -} - /* * Write an arbitrary sized big-endian integer into a pointer. * diff --git a/src/soc/cavium/cn81xx/soc.c b/src/soc/cavium/cn81xx/soc.c index 98166b056f..05007493df 100644 --- a/src/soc/cavium/cn81xx/soc.c +++ b/src/soc/cavium/cn81xx/soc.c @@ -234,7 +234,7 @@ static int dt_platform_fixup(struct device_tree_fixup *fixup, continue; } /* Store the phandle */ - phandle = dt_get_phandle(dt_node); + phandle = dt_node->phandle; printk(BIOS_INFO, "%s: Removing node %s\n", __func__, path); list_remove(&dt_node->list_node); From f36d53c6539ec9e221a5005f00a56960f791a81f Mon Sep 17 00:00:00 2001 From: Julius Werner Date: Fri, 3 May 2019 18:23:34 -0700 Subject: [PATCH 308/331] device_tree: Drop sub-node path lookup from dt_find_node_by_path() Besides looking up a node with an absolute path dt_find_node_by_path() currently also supports finding a sub-node of a non-root node. All callers of the function pass the root node though, so it seems there is no real need for this functionality. Also it is planned to support DT path names with aliases, which would become messy in combination with the lookup from a sub-node. Change the interface of dt_find_node_by_path() to receive the DT tree object instead of a parent node and adapt all callers accordingly. This patch was adapted from depthcharge's http://crosreview.com/1252769 Change-Id: Iff56be4da2461ae73a7301dcaa315758d2a8c999 Signed-off-by: Julius Werner Reviewed-on: https://review.coreboot.org/c/coreboot/+/32864 Reviewed-by: Hung-Te Lin Tested-by: build bot (Jenkins) --- src/include/device_tree.h | 6 +++--- src/lib/device_tree.c | 12 ++++++------ src/soc/cavium/cn81xx/soc.c | 10 +++++----- 3 files changed, 14 insertions(+), 14 deletions(-) diff --git a/src/include/device_tree.h b/src/include/device_tree.h index 8280dad077..6eaeacd6f0 100644 --- a/src/include/device_tree.h +++ b/src/include/device_tree.h @@ -142,10 +142,10 @@ struct device_tree_node *dt_find_node(struct device_tree_node *parent, const cha u32 *addrcp, u32 *sizecp, int create); struct device_tree_node *dt_find_node_by_phandle(struct device_tree_node *root, uint32_t phandle); -// Look up or create a node relative to a parent node, through its path +// Look up or create a node in the tree, through its path // represented as a string of '/' separated node names. -struct device_tree_node *dt_find_node_by_path(struct device_tree_node *parent, const char *path, - u32 *addrcp, u32 *sizecp, int create); +struct device_tree_node *dt_find_node_by_path(struct device_tree *tree, + const char *path, u32 *addrcp, u32 *sizecp, int create); // Look up a node relative to a parent node, through its compatible string. struct device_tree_node *dt_find_compat(struct device_tree_node *parent, const char *compatible); // Look up the next child of a parent node, through its compatible string. It diff --git a/src/lib/device_tree.c b/src/lib/device_tree.c index 44eca4e2a8..3e1dd3580c 100644 --- a/src/lib/device_tree.c +++ b/src/lib/device_tree.c @@ -552,9 +552,9 @@ struct device_tree_node *dt_find_node(struct device_tree_node *parent, } /* - * Find a node from a string device tree path, relative to a parent node. + * Find a node in the tree from a string device tree path. * - * @param parent The node from which to start the relative path lookup. + * @param tree The device tree to search. * @param path A string representing a path in the device tree, with * nodes separated by '/'. Example: "soc/firmware/coreboot" * @param addrcp Pointer that will be updated with any #address-cells @@ -567,7 +567,7 @@ struct device_tree_node *dt_find_node(struct device_tree_node *parent, * It is the caller responsibility to provide the correct path string, namely * not starting or ending with a '/', and not having "//" anywhere in it. */ -struct device_tree_node *dt_find_node_by_path(struct device_tree_node *parent, +struct device_tree_node *dt_find_node_by_path(struct device_tree *tree, const char *path, u32 *addrcp, u32 *sizecp, int create) { @@ -595,7 +595,7 @@ struct device_tree_node *dt_find_node_by_path(struct device_tree_node *parent, if (!next_slash) { path_array[i] = NULL; - node = dt_find_node(parent, path_array, + node = dt_find_node(tree->root, path_array, addrcp, sizecp, create); } @@ -965,7 +965,7 @@ int dt_set_bin_prop_by_path(struct device_tree *tree, const char *path, *prop_name++ = '\0'; /* Separate path from the property name. */ - dt_node = dt_find_node_by_path(tree->root, path_copy, NULL, + dt_node = dt_find_node_by_path(tree, path_copy, NULL, NULL, create); if (!dt_node) { @@ -995,7 +995,7 @@ struct device_tree_node *dt_init_reserved_memory_node(struct device_tree *tree) struct device_tree_node *reserved; u32 addr = 0, size = 0; - reserved = dt_find_node_by_path(tree->root, "reserved-memory", &addr, + reserved = dt_find_node_by_path(tree, "reserved-memory", &addr, &size, 1); if (!reserved) return NULL; diff --git a/src/soc/cavium/cn81xx/soc.c b/src/soc/cavium/cn81xx/soc.c index 05007493df..20542e5fa2 100644 --- a/src/soc/cavium/cn81xx/soc.c +++ b/src/soc/cavium/cn81xx/soc.c @@ -185,7 +185,7 @@ static int dt_platform_fixup(struct device_tree_fixup *fixup, size_t i; /* Set the sclk clock rate. */ - dt_node = dt_find_node_by_path(tree->root, "soc@0/sclk", NULL, NULL, 0); + dt_node = dt_find_node_by_path(tree, "soc@0/sclk", NULL, NULL, 0); if (dt_node) { const u32 freq = thunderx_get_io_clock(); printk(BIOS_INFO, "%s: Set SCLK to %u Hz\n", __func__, freq); @@ -195,7 +195,7 @@ static int dt_platform_fixup(struct device_tree_fixup *fixup, __func__); /* Set refclkuaa clock rate. */ - dt_node = dt_find_node_by_path(tree->root, "soc@0/refclkuaa", NULL, + dt_node = dt_find_node_by_path(tree, "soc@0/refclkuaa", NULL, NULL, 0); if (dt_node) { const u32 freq = uart_platform_refclk(); @@ -212,7 +212,7 @@ static int dt_platform_fixup(struct device_tree_fixup *fixup, const uint64_t addr = UAAx_PF_BAR0(i); /* Remove the node */ snprintf(path, sizeof(path), "soc@0/serial@%llx", addr); - dt_node = dt_find_node_by_path(tree->root, path, NULL, NULL, 0); + dt_node = dt_find_node_by_path(tree, path, NULL, NULL, 0); if (!dt_node || uart_is_enabled(i)) { printk(BIOS_INFO, "%s: ignoring %s\n", __func__, path); continue; @@ -228,7 +228,7 @@ static int dt_platform_fixup(struct device_tree_fixup *fixup, const uint64_t addr = PEM_PEMX_PF_BAR0(i); /* Remove the node */ snprintf(path, sizeof(path), "soc@0/pci@%llx", addr); - dt_node = dt_find_node_by_path(tree->root, path, NULL, NULL, 0); + dt_node = dt_find_node_by_path(tree, path, NULL, NULL, 0); if (!dt_node || bdk_pcie_is_running(0, i)) { printk(BIOS_INFO, "%s: ignoring %s\n", __func__, path); continue; @@ -240,7 +240,7 @@ static int dt_platform_fixup(struct device_tree_fixup *fixup, /* Remove phandle to non existing nodes */ snprintf(path, sizeof(path), "soc@0/smmu0@%llx", SMMU_PF_BAR0); - dt_node = dt_find_node_by_path(tree->root, path, NULL, NULL, 0); + dt_node = dt_find_node_by_path(tree, path, NULL, NULL, 0); if (!dt_node) { printk(BIOS_ERR, "%s: SMMU entry not found\n", __func__); From fbec63d15f761e01c934078570acbef779e707ba Mon Sep 17 00:00:00 2001 From: Julius Werner Date: Fri, 3 May 2019 18:29:28 -0700 Subject: [PATCH 309/331] device_tree: Have absolute paths start with '/' Currently DT paths are *not* expected to start with '/'. This is not what the spec says (see Devicetree Specification v0.2, 2.2.3 Path Names) and also not what is done by Linux. Change dt_find_node_by_path() to expect paths to start with '/' and add a leading '/' to all DT path strings. Besides the compatibility with the spec this change is also needed to support aliases in the future. This patch was adapted from depthcharge's http://crosreview.com/1252770 Change-Id: Ibdf59ccbb4ead38c6193b630642fd1f1e847dd89 Signed-off-by: Julius Werner Reviewed-on: https://review.coreboot.org/c/coreboot/+/32865 Reviewed-by: Hung-Te Lin Tested-by: build bot (Jenkins) --- src/lib/device_tree.c | 8 ++++---- src/soc/cavium/cn81xx/soc.c | 10 +++++----- 2 files changed, 9 insertions(+), 9 deletions(-) diff --git a/src/lib/device_tree.c b/src/lib/device_tree.c index 3e1dd3580c..e26021e9ee 100644 --- a/src/lib/device_tree.c +++ b/src/lib/device_tree.c @@ -556,7 +556,7 @@ struct device_tree_node *dt_find_node(struct device_tree_node *parent, * * @param tree The device tree to search. * @param path A string representing a path in the device tree, with - * nodes separated by '/'. Example: "soc/firmware/coreboot" + * nodes separated by '/'. Example: "/firmware/coreboot" * @param addrcp Pointer that will be updated with any #address-cells * value found in the path. May be NULL to ignore. * @param sizecp Pointer that will be updated with any #size-cells @@ -565,13 +565,13 @@ struct device_tree_node *dt_find_node(struct device_tree_node *parent, * @return The found/created node, or NULL. * * It is the caller responsibility to provide the correct path string, namely - * not starting or ending with a '/', and not having "//" anywhere in it. + * starting with a '/', not ending in a '/' and not having "//" anywhere in it. */ struct device_tree_node *dt_find_node_by_path(struct device_tree *tree, const char *path, u32 *addrcp, u32 *sizecp, int create) { - char *dup_path = strdup(path); + char *dup_path = strdup(&path[1]); /* remove leading '/' */ /* Hopefully enough depth for any node. */ const char *path_array[15]; int i; @@ -995,7 +995,7 @@ struct device_tree_node *dt_init_reserved_memory_node(struct device_tree *tree) struct device_tree_node *reserved; u32 addr = 0, size = 0; - reserved = dt_find_node_by_path(tree, "reserved-memory", &addr, + reserved = dt_find_node_by_path(tree, "/reserved-memory", &addr, &size, 1); if (!reserved) return NULL; diff --git a/src/soc/cavium/cn81xx/soc.c b/src/soc/cavium/cn81xx/soc.c index 20542e5fa2..efe7d6d204 100644 --- a/src/soc/cavium/cn81xx/soc.c +++ b/src/soc/cavium/cn81xx/soc.c @@ -185,7 +185,7 @@ static int dt_platform_fixup(struct device_tree_fixup *fixup, size_t i; /* Set the sclk clock rate. */ - dt_node = dt_find_node_by_path(tree, "soc@0/sclk", NULL, NULL, 0); + dt_node = dt_find_node_by_path(tree, "/soc@0/sclk", NULL, NULL, 0); if (dt_node) { const u32 freq = thunderx_get_io_clock(); printk(BIOS_INFO, "%s: Set SCLK to %u Hz\n", __func__, freq); @@ -195,7 +195,7 @@ static int dt_platform_fixup(struct device_tree_fixup *fixup, __func__); /* Set refclkuaa clock rate. */ - dt_node = dt_find_node_by_path(tree, "soc@0/refclkuaa", NULL, + dt_node = dt_find_node_by_path(tree, "/soc@0/refclkuaa", NULL, NULL, 0); if (dt_node) { const u32 freq = uart_platform_refclk(); @@ -211,7 +211,7 @@ static int dt_platform_fixup(struct device_tree_fixup *fixup, char path[32]; const uint64_t addr = UAAx_PF_BAR0(i); /* Remove the node */ - snprintf(path, sizeof(path), "soc@0/serial@%llx", addr); + snprintf(path, sizeof(path), "/soc@0/serial@%llx", addr); dt_node = dt_find_node_by_path(tree, path, NULL, NULL, 0); if (!dt_node || uart_is_enabled(i)) { printk(BIOS_INFO, "%s: ignoring %s\n", __func__, path); @@ -227,7 +227,7 @@ static int dt_platform_fixup(struct device_tree_fixup *fixup, u32 phandle = 0; const uint64_t addr = PEM_PEMX_PF_BAR0(i); /* Remove the node */ - snprintf(path, sizeof(path), "soc@0/pci@%llx", addr); + snprintf(path, sizeof(path), "/soc@0/pci@%llx", addr); dt_node = dt_find_node_by_path(tree, path, NULL, NULL, 0); if (!dt_node || bdk_pcie_is_running(0, i)) { printk(BIOS_INFO, "%s: ignoring %s\n", __func__, path); @@ -239,7 +239,7 @@ static int dt_platform_fixup(struct device_tree_fixup *fixup, list_remove(&dt_node->list_node); /* Remove phandle to non existing nodes */ - snprintf(path, sizeof(path), "soc@0/smmu0@%llx", SMMU_PF_BAR0); + snprintf(path, sizeof(path), "/soc@0/smmu0@%llx", SMMU_PF_BAR0); dt_node = dt_find_node_by_path(tree, path, NULL, NULL, 0); if (!dt_node) { printk(BIOS_ERR, "%s: SMMU entry not found\n", From 6d5695fac53f52e1f389f420b5428e92de5b8c9c Mon Sep 17 00:00:00 2001 From: Julius Werner Date: Mon, 6 May 2019 19:23:28 -0700 Subject: [PATCH 310/331] device_tree: Add support for aliases This patch adds support to lookup nodes via the "/aliases" mechanism in device trees. This may be required for overlay support (don't quite remember tbh) and is also just a generally useful feature. It was adapted from depthcharge's http://crosreview.com/1249703 and http://crosreview.com/1542702. Change-Id: I1289ab2f02c4877a2d0111040384827e2b48a34a Signed-off-by: Julius Werner Reviewed-on: https://review.coreboot.org/c/coreboot/+/32866 Reviewed-by: Hung-Te Lin Tested-by: build bot (Jenkins) --- src/include/device_tree.h | 3 ++ src/lib/device_tree.c | 86 +++++++++++++++++++++++++++++++++------ 2 files changed, 77 insertions(+), 12 deletions(-) diff --git a/src/include/device_tree.h b/src/include/device_tree.h index 6eaeacd6f0..e3723c86ac 100644 --- a/src/include/device_tree.h +++ b/src/include/device_tree.h @@ -146,6 +146,9 @@ struct device_tree_node *dt_find_node_by_phandle(struct device_tree_node *root, // represented as a string of '/' separated node names. struct device_tree_node *dt_find_node_by_path(struct device_tree *tree, const char *path, u32 *addrcp, u32 *sizecp, int create); +// Look up a node through an alias. +struct device_tree_node *dt_find_node_by_alias(struct device_tree *tree, + const char *alias); // Look up a node relative to a parent node, through its compatible string. struct device_tree_node *dt_find_compat(struct device_tree_node *parent, const char *compatible); // Look up the next child of a parent node, through its compatible string. It diff --git a/src/lib/device_tree.c b/src/lib/device_tree.c index e26021e9ee..bbcd7c06f6 100644 --- a/src/lib/device_tree.c +++ b/src/lib/device_tree.c @@ -564,27 +564,65 @@ struct device_tree_node *dt_find_node(struct device_tree_node *parent, * @param create 1: Create node(s) if not found. 0: Return NULL instead. * @return The found/created node, or NULL. * - * It is the caller responsibility to provide the correct path string, namely - * starting with a '/', not ending in a '/' and not having "//" anywhere in it. - */ + * It is the caller responsibility to provide a path string that doesn't end + * with a '/' and doesn't contain any "//". If the path does not start with a + * '/', the first segment is interpreted as an alias. */ struct device_tree_node *dt_find_node_by_path(struct device_tree *tree, const char *path, u32 *addrcp, u32 *sizecp, int create) { - char *dup_path = strdup(&path[1]); /* remove leading '/' */ + char *sub_path; + char *duped_str; + struct device_tree_node *parent; + char *next_slash; /* Hopefully enough depth for any node. */ const char *path_array[15]; int i; - char *next_slash; struct device_tree_node *node = NULL; - if (!dup_path) - return NULL; + if (path[0] == '/') { // regular path + if (path[1] == '\0') { // special case: "/" is root node + dt_read_cell_props(tree->root, addrcp, sizecp); + return tree->root; + } - next_slash = dup_path; - path_array[0] = dup_path; + sub_path = duped_str = strdup(&path[1]); + if (!sub_path) + return NULL; + + parent = tree->root; + } else { // alias + char *alias; + + alias = duped_str = strdup(path); + if (!alias) + return NULL; + + sub_path = strchr(alias, '/'); + if (sub_path) + *sub_path = '\0'; + + parent = dt_find_node_by_alias(tree, alias); + if (!parent) { + printk(BIOS_DEBUG, + "Could not find node '%s', alias '%s' does not exist\n", + path, alias); + free(duped_str); + return NULL; + } + + if (!sub_path) { + // it's just the alias, no sub-path + free(duped_str); + return parent; + } + + sub_path++; + } + + next_slash = sub_path; + path_array[0] = sub_path; for (i = 1; i < (ARRAY_SIZE(path_array) - 1); i++) { - next_slash = strchr(next_slash, '/'); if (!next_slash) break; @@ -595,14 +633,38 @@ struct device_tree_node *dt_find_node_by_path(struct device_tree *tree, if (!next_slash) { path_array[i] = NULL; - node = dt_find_node(tree->root, path_array, + node = dt_find_node(parent, path_array, addrcp, sizecp, create); } - free(dup_path); + free(duped_str); return node; } +/* + * Find a node from an alias + * + * @param tree The device tree. + * @param alias The alias name. + * @return The found node, or NULL. + */ +struct device_tree_node *dt_find_node_by_alias(struct device_tree *tree, + const char *alias) +{ + struct device_tree_node *node; + const char *alias_path; + + node = dt_find_node_by_path(tree, "/aliases", NULL, NULL, 0); + if (!node) + return NULL; + + alias_path = dt_find_string_prop(node, alias); + if (!alias_path) + return NULL; + + return dt_find_node_by_path(tree, alias_path, NULL, NULL, 0); +} + struct device_tree_node *dt_find_node_by_phandle(struct device_tree_node *root, uint32_t phandle) { From 0d74653bd46a360466cf5050ea0c102fc11cdc2d Mon Sep 17 00:00:00 2001 From: Julius Werner Date: Mon, 6 May 2019 19:35:56 -0700 Subject: [PATCH 311/331] device_tree: Match debug output format to dtc -O dts output This patch updates the device tree dumping functions (not compiled by default but available for debugging) to output properties and nodes in a format similar to .dts files that is very close to what dtc outputs when you decompile a .dtb with it. This makes it easier to match device tree dumps from coreboot with device tree dumps generated by other device tree tooling. This patch was adapted from depthcharge's http://crosreview.com/1536386 Change-Id: Ib40e50d906aff05473a70c4fc9b124d63232558c Signed-off-by: Julius Werner Reviewed-on: https://review.coreboot.org/c/coreboot/+/32867 Reviewed-by: Hung-Te Lin Tested-by: build bot (Jenkins) --- src/lib/device_tree.c | 49 +++++++++++++++++++++++++++++++++---------- 1 file changed, 38 insertions(+), 11 deletions(-) diff --git a/src/lib/device_tree.c b/src/lib/device_tree.c index bbcd7c06f6..3c4bd24462 100644 --- a/src/lib/device_tree.c +++ b/src/lib/device_tree.c @@ -80,21 +80,36 @@ static int dt_prop_is_phandle(struct device_tree_property *prop) static void print_indent(int depth) { - while (depth--) - printk(BIOS_DEBUG, " "); + printk(BIOS_DEBUG, "%*s", depth * 8, ""); } static void print_property(const struct fdt_property *prop, int depth) { + int is_string = prop->size > 0 && + ((char *)prop->data)[prop->size - 1] == '\0'; + + if (is_string) + for (const char *c = prop->data; *c != '\0'; c++) + if (!isprint(*c)) + is_string = 0; + print_indent(depth); - printk(BIOS_DEBUG, "prop \"%s\" (%d bytes).\n", prop->name, prop->size); - print_indent(depth + 1); - for (int i = 0; i < MIN(25, prop->size); i++) { - printk(BIOS_DEBUG, "%02x ", ((uint8_t *)prop->data)[i]); + if (is_string) { + printk(BIOS_DEBUG, "%s = \"%s\";\n", + prop->name, (const char *)prop->data); + } else { + printk(BIOS_DEBUG, "%s = < ", prop->name); + for (int i = 0; i < MIN(128, prop->size); i += 4) { + uint32_t val = 0; + for (int j = 0; j < MIN(4, prop->size - i); j++) + val |= ((uint8_t *)prop->data)[i + j] << + (24 - j * 8); + printk(BIOS_DEBUG, "%#.2x ", val); + } + if (prop->size > 128) + printk(BIOS_DEBUG, "..."); + printk(BIOS_DEBUG, ">;\n"); } - if (prop->size > 25) - printk(BIOS_DEBUG, "..."); - printk(BIOS_DEBUG, "\n"); } static int print_flat_node(const void *blob, uint32_t start_offset, int depth) @@ -109,7 +124,7 @@ static int print_flat_node(const void *blob, uint32_t start_offset, int depth) offset += size; print_indent(depth); - printk(BIOS_DEBUG, "name = %s\n", name); + printk(BIOS_DEBUG, "%s {\n", name); struct fdt_property prop; while ((size = fdt_next_property(blob, offset, &prop))) { @@ -118,9 +133,14 @@ static int print_flat_node(const void *blob, uint32_t start_offset, int depth) offset += size; } + printk(BIOS_DEBUG, "\n"); // empty line between props and nodes + while ((size = print_flat_node(blob, offset, depth + 1))) offset += size; + print_indent(depth); + printk(BIOS_DEBUG, "}\n"); + return offset - start_offset + sizeof(uint32_t); } @@ -458,15 +478,22 @@ void dt_flatten(const struct device_tree *tree, void *start_dest) static void print_node(const struct device_tree_node *node, int depth) { print_indent(depth); - printk(BIOS_DEBUG, "name = %s\n", node->name); + if (depth == 0) // root node has no name, print a starting slash + printk(BIOS_DEBUG, "/"); + printk(BIOS_DEBUG, "%s {\n", node->name); struct device_tree_property *prop; list_for_each(prop, node->properties, list_node) print_property(&prop->prop, depth + 1); + printk(BIOS_DEBUG, "\n"); // empty line between props and nodes + struct device_tree_node *child; list_for_each(child, node->children, list_node) print_node(child, depth + 1); + + print_indent(depth); + printk(BIOS_DEBUG, "};\n"); } void dt_print_node(const struct device_tree_node *node) From 0e9116f0a12c0a2a8142978458d3266e5e9aacdc Mon Sep 17 00:00:00 2001 From: Julius Werner Date: Mon, 13 May 2019 17:30:31 -0700 Subject: [PATCH 312/331] device_tree: Make FDT property data non-const FDT property data should not be const -- sometimes we need to update it, for example when fixing up phandles in an overlay. On the other hand it's occasionally desirable to put a string constant in there without having to strdup() it all the time... let's just live with the tiny implicit assumption that the data we'd want to modify (phandle references, mostly) will never be added from string constants, and put a cast in dt_add_string_prop(). Change-Id: Ifac103fcff0520cc427ab9a2aa141c65e12507ac Signed-off-by: Julius Werner Reviewed-on: https://review.coreboot.org/c/coreboot/+/32868 Reviewed-by: Hung-Te Lin Tested-by: build bot (Jenkins) --- src/include/device_tree.h | 4 ++-- src/lib/device_tree.c | 4 ++-- src/soc/cavium/cn81xx/soc.c | 2 +- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/src/include/device_tree.h b/src/include/device_tree.h index e3723c86ac..d9d9613f96 100644 --- a/src/include/device_tree.h +++ b/src/include/device_tree.h @@ -52,7 +52,7 @@ struct fdt_header { struct fdt_property { const char *name; - const void *data; + void *data; uint32_t size; }; @@ -165,7 +165,7 @@ void dt_write_int(u8 *dest, u64 src, size_t length); void dt_delete_prop(struct device_tree_node *node, const char *name); // Add different kinds of properties to a node, or update existing ones. void dt_add_bin_prop(struct device_tree_node *node, const char *name, - const void *data, size_t size); + void *data, size_t size); void dt_add_string_prop(struct device_tree_node *node, const char *name, const char *str); void dt_add_u32_prop(struct device_tree_node *node, const char *name, u32 val); diff --git a/src/lib/device_tree.c b/src/lib/device_tree.c index 3c4bd24462..a5021ca8fd 100644 --- a/src/lib/device_tree.c +++ b/src/lib/device_tree.c @@ -883,7 +883,7 @@ void dt_delete_prop(struct device_tree_node *node, const char *name) * @param size The size of data in bytes. */ void dt_add_bin_prop(struct device_tree_node *node, const char *name, - const void *data, size_t size) + void *data, size_t size) { struct device_tree_property *prop; @@ -955,7 +955,7 @@ void dt_find_bin_prop(const struct device_tree_node *node, const char *name, void dt_add_string_prop(struct device_tree_node *node, const char *name, const char *str) { - dt_add_bin_prop(node, name, str, strlen(str) + 1); + dt_add_bin_prop(node, name, (char *)str, strlen(str) + 1); } /* diff --git a/src/soc/cavium/cn81xx/soc.c b/src/soc/cavium/cn81xx/soc.c index efe7d6d204..f1e11d335b 100644 --- a/src/soc/cavium/cn81xx/soc.c +++ b/src/soc/cavium/cn81xx/soc.c @@ -149,7 +149,7 @@ static void dt_platform_fixup_mac(struct device_tree_node *node) if (*localmac) return; if (used_mac < num_free_mac_addresses) { - const u64 genmac = next_free_mac_address + used_mac; + u64 genmac = next_free_mac_address + used_mac; dt_add_bin_prop(node, name, &genmac, 6); used_mac++; return; From 59b6542bbc5aa7215aa68eca098c047924e5e118 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Thu, 23 May 2019 15:24:30 +0200 Subject: [PATCH 313/331] soc/intel/braswell: Use common cpu/intel/car code MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The code in cpu/intel/car/romstage.c Does most of the things like setting up timestamps, stack guards, entering postcar. A functional difference is that the FSP header is searched for twice instead of passed from the CAR entry to the C code. When using C_ENVIRONMENT_BOOTBLOCK this needs to be done anyway (or a special linker symbol kept across multiple stages is needed, which is likely not worth the speedup). Change-Id: I0f03e5a808f00157fdd807b104417a54e4bde7b2 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/32963 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki --- src/drivers/intel/fsp1_1/cache_as_ram.inc | 46 ++++++------ src/drivers/intel/fsp1_1/car.c | 75 ++++---------------- src/drivers/intel/fsp1_1/include/fsp/car.h | 11 --- src/soc/intel/braswell/romstage/Makefile.inc | 1 + 4 files changed, 36 insertions(+), 97 deletions(-) diff --git a/src/drivers/intel/fsp1_1/cache_as_ram.inc b/src/drivers/intel/fsp1_1/cache_as_ram.inc index f50641e3ae..493dbc8d04 100644 --- a/src/drivers/intel/fsp1_1/cache_as_ram.inc +++ b/src/drivers/intel/fsp1_1/cache_as_ram.inc @@ -31,11 +31,11 @@ * EBX, EDI, ESI, EBP, MM0, MM1 * * Shift values to release MM2. - * mm0 -> edi: BIST value + * mm0 -> ebx: BIST value * mm1 -> mm0: low 32-bits of TSC value * mm2 -> mm1: high 32-bits of TSC value */ - movd %mm0, %edi + movd %mm0, %ebx movd %mm1, %eax movd %eax, %mm0 movd %mm2, %eax @@ -79,8 +79,8 @@ find_fsp_ret: /* * BIST value is zero * eax: TempRamInitApi address + * ebx: BIST value * ebp: FSP_INFO_HEADER address - * edi: BIST value * esi: Not used * mm0: low 32-bits of TSC value * mm1: high 32-bits of TSC value @@ -90,13 +90,12 @@ find_fsp_ret: jmp *%eax CAR_init_done: - addl $4, %esp /* * ebp: FSP_INFO_HEADER address + * ebx: BIST value * ecx: Temp RAM base * edx: Temp RAM top - * edi: BIST value * mm0: low 32-bits of TSC value * mm1: high 32-bits of TSC value */ @@ -109,43 +108,42 @@ CAR_init_done: /* * ebp: FSP_INFO_HEADER address + * ebx: BIST value * ecx: Temp RAM base * edx: Temp RAM top - * edi: BIST value * esp: Top of stack in temp RAM * mm0: low 32-bits of TSC value * mm1: high 32-bits of TSC value */ - /* Create cache_as_ram_params on stack */ - pushl %edx /* bootloader CAR end */ - pushl %ecx /* bootloader CAR begin */ - pushl %ebp /* FSP_INFO_HEADER */ - pushl %edi /* bist */ - movd %mm1, %eax - pushl %eax /* tsc[63:32] */ - movd %mm0, %eax - pushl %eax /* tsc[31:0] */ - pushl %esp /* pointer to cache_as_ram_params */ - - /* Save FSP_INFO_HEADER location in ebx */ - mov %ebp, %ebx - /* coreboot assumes stack/heap region will be zero */ cld movl %ecx, %edi neg %ecx - /* Only clear up to current stack value. */ - add %esp, %ecx + /* Clear up to Temp Ram top. */ + add %edx, %ecx shrl $2, %ecx xorl %eax, %eax rep stosl + /* Need to align stack to 16 bytes at call instruction. Account for + the pushes below. */ + andl $0xfffffff0, %esp + subl $4, %esp + + /* Push BIST and initial timestamp on the stack */ + pushl %ebx /* bist */ + movd %mm1, %eax + pushl %eax /* tsc[63:32] */ + movd %mm0, %eax + pushl %eax /* tsc[31:0] */ + before_romstage: post_code(0x2A) - /* Call cache_as_ram_main(struct cache_as_ram_params *) */ - call cache_as_ram_main + /* Call bootblock_c_entry_bist(uint64_t base_timestamp, uint32_t bist) + in cpu/intel/car/romstage.c */ + call bootblock_c_entry_bist movb $0x69, %ah jmp .Lhlt diff --git a/src/drivers/intel/fsp1_1/car.c b/src/drivers/intel/fsp1_1/car.c index 41a02f33b9..10f9524650 100644 --- a/src/drivers/intel/fsp1_1/car.c +++ b/src/drivers/intel/fsp1_1/car.c @@ -94,74 +94,25 @@ void platform_enter_postcar(void) run_postcar_phase(&pcf); } -/* This is the romstage C entry for platforms without - CONFIG_C_ENVIRONMENT_BOOTBLOCK */ -asmlinkage void cache_as_ram_main(struct cache_as_ram_params *car_params) -{ - int i; - const int num_guards = 4; - const u32 stack_guard = 0xdeadbeef; - u32 *stack_base; - u32 size; - - /* Size of unallocated CAR. */ - size = _car_region_end - _car_relocatable_data_end; - size = ALIGN_DOWN(size, 16); - - stack_base = (u32 *)(_car_region_end - size); - - for (i = 0; i < num_guards; i++) - stack_base[i] = stack_guard; - - /* Initialize timestamp book keeping only once. */ - timestamp_init(car_params->tsc); - - /* Call into pre-console init code then initialize console. */ - car_soc_pre_console_init(); - car_mainboard_pre_console_init(); - console_init(); - - printk(BIOS_DEBUG, "FSP TempRamInit successful\n"); - - printk(BIOS_SPEW, "bist: 0x%08x\n", car_params->bist); - printk(BIOS_SPEW, "tsc: 0x%016llx\n", car_params->tsc); - - display_mtrrs(); - - if (car_params->bootloader_car_start != CONFIG_DCACHE_RAM_BASE - || car_params->bootloader_car_end != (CONFIG_DCACHE_RAM_BASE - + CONFIG_DCACHE_RAM_SIZE)) { - printk(BIOS_INFO, "CAR mismatch: %08x--%08x vs %08lx--%08lx\n", - CONFIG_DCACHE_RAM_BASE, - CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE, - (long)car_params->bootloader_car_start, - (long)car_params->bootloader_car_end); - } - - car_soc_post_console_init(); - car_mainboard_post_console_init(); - - cache_as_ram_stage_main(car_params->fih); - - /* Check the stack. */ - for (i = 0; i < num_guards; i++) { - if (stack_base[i] == stack_guard) - continue; - printk(BIOS_DEBUG, "Smashed stack detected in romstage!\n"); - } - - /* we don't return here */ - platform_enter_postcar(); -} - -/* This is the entry for platforms with CONFIG_C_ENVIRONMENT_BOOTBLOCK - called from cpu/intel/car/romstage.c */ +/* This is the romstage entry called from cpu/intel/car/romstage.c */ void mainboard_romstage_entry(unsigned long bist) { /* Need to locate the current FSP_INFO_HEADER. The cache-as-ram * is still enabled. We can directly access work buffer here. */ struct prog fsp = PROG_INIT(PROG_REFCODE, "fsp.bin"); + if (!CONFIG(C_ENVIRONMENT_BOOTBLOCK)) { + /* Call into pre-console init code then initialize console. */ + car_soc_pre_console_init(); + car_mainboard_pre_console_init(); + console_init(); + + display_mtrrs(); + + car_soc_post_console_init(); + car_mainboard_post_console_init(); + } + if (prog_locate(&fsp)) die_with_post_code(POST_INVALID_CBFS, "Unable to locate fsp.bin"); diff --git a/src/drivers/intel/fsp1_1/include/fsp/car.h b/src/drivers/intel/fsp1_1/include/fsp/car.h index c05139231c..8d7a683672 100644 --- a/src/drivers/intel/fsp1_1/include/fsp/car.h +++ b/src/drivers/intel/fsp1_1/include/fsp/car.h @@ -20,17 +20,6 @@ #include #include -/* cache-as-ram support for FSP 1.1. */ -struct cache_as_ram_params { - uint64_t tsc; - uint32_t bist; - FSP_INFO_HEADER *fih; - uintptr_t bootloader_car_start; - uintptr_t bootloader_car_end; -}; - -/* Entry points from the cache-as-ram assembly code. */ -asmlinkage void cache_as_ram_main(struct cache_as_ram_params *car_params); /* Per stage calls from the above two functions. The void * return from * cache_as_ram_stage_main() is the stack pointer to use in RAM after * exiting cache-as-ram mode. */ diff --git a/src/soc/intel/braswell/romstage/Makefile.inc b/src/soc/intel/braswell/romstage/Makefile.inc index 15de822041..3d3e407a29 100644 --- a/src/soc/intel/braswell/romstage/Makefile.inc +++ b/src/soc/intel/braswell/romstage/Makefile.inc @@ -1,2 +1,3 @@ +romstage-y += ../../../../cpu/intel/car/romstage.c romstage-y += pmc.c romstage-y += romstage.c From ad5467d202408cafadd12aef6eea48b92b792a18 Mon Sep 17 00:00:00 2001 From: Felix Singer Date: Thu, 2 May 2019 14:40:48 +0200 Subject: [PATCH 314/331] drivers/fsp20: Fix spelling in help text Change-Id: Iab8d20a385bde31b29fa7766a87753fcc2d759b8 Signed-off-by: Felix Singer Reviewed-on: https://review.coreboot.org/c/coreboot/+/32544 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held --- src/drivers/intel/fsp2_0/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig index 7fe81e51a0..3fb39d5076 100644 --- a/src/drivers/intel/fsp2_0/Kconfig +++ b/src/drivers/intel/fsp2_0/Kconfig @@ -27,7 +27,7 @@ config PLATFORM_USES_FSP2_1 select FSP_PEIM_TO_PEIM_INTERFACE help Include FSP 2.1 wrappers and functionality. - Features added into FSP 2.1 specification that impacts corerboot are: + Features added into FSP 2.1 specification that impacts coreboot are: 1. Remove FSP stack switch and use the same stack with boot firmware 2. FSP should support external PPI interface pulled in via FSP_PEIM_TO_PEIM_INTERFACE From 086149eb32808f2003e2951ce679b3c7728c3846 Mon Sep 17 00:00:00 2001 From: Evgeny Zinoviev Date: Fri, 31 May 2019 16:25:04 +0300 Subject: [PATCH 315/331] mb/apple/macbookair4_2: Fix DRAM_RESET_GATE_GPIO It's GPIO28 according to schematics. Change-Id: I55be1ed178c818a17766e22cb2fd010412b8fe02 Signed-off-by: Evgeny Zinoviev Reviewed-on: https://review.coreboot.org/c/coreboot/+/33149 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber Reviewed-by: Felix Held --- src/mainboard/apple/macbookair4_2/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/apple/macbookair4_2/Kconfig b/src/mainboard/apple/macbookair4_2/Kconfig index 4b2ee8fdc8..df8ecfd79d 100644 --- a/src/mainboard/apple/macbookair4_2/Kconfig +++ b/src/mainboard/apple/macbookair4_2/Kconfig @@ -33,7 +33,7 @@ config VGA_BIOS_ID config DRAM_RESET_GATE_GPIO int - default 60 + default 28 config MAX_CPUS int From ec017590e54f5941f53cf33d8ebce6d311313a46 Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Sat, 6 Apr 2019 16:09:46 +0200 Subject: [PATCH 316/331] util/lint: Make usage of IS_ENABLED() an error As long as we keep the IS_ENABLED() definition in libpayload for compatibility, we should check that IS_ENABLED() usage doesn't sneak back in. Also remove all other IS_ENABLED() checks. Change-Id: Id30ffa0089cec6c24fc3dbbb10a1be35f63b3d89 Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/c/coreboot/+/32229 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner Reviewed-by: Patrick Georgi --- util/lint/checkpatch.pl | 10 ------- util/lint/kconfig_lint | 55 +++++++++-------------------------- util/lint/kconfig_lint_README | 8 ++--- 3 files changed, 16 insertions(+), 57 deletions(-) diff --git a/util/lint/checkpatch.pl b/util/lint/checkpatch.pl index 265b04cef2..1affdb7b33 100755 --- a/util/lint/checkpatch.pl +++ b/util/lint/checkpatch.pl @@ -6184,16 +6184,6 @@ sub process { } } -# check for #if defined CONFIG_ || defined CONFIG__MODULE - if ($line =~ /^\+\s*#\s*if\s+defined(?:\s*\(?\s*|\s+)(CONFIG_[A-Z_]+)\s*\)?\s*\|\|\s*defined(?:\s*\(?\s*|\s+)\1_MODULE\s*\)?\s*$/) { - my $config = $1; - if (WARN("PREFER_IS_ENABLED", - "Prefer IS_ENABLED() to CONFIG_ || CONFIG__MODULE\n" . $herecurr) && - $fix) { - $fixed[$fixlinenr] = "\+#if IS_ENABLED($config)"; - } - } - # check for case / default statements not preceded by break/fallthrough/switch if ($line =~ /^.\s*(?:case\s+(?:$Ident|$Constant)\s*|default):/) { my $has_break = 0; diff --git a/util/lint/kconfig_lint b/util/lint/kconfig_lint index 502a61878b..47f04941f2 100755 --- a/util/lint/kconfig_lint +++ b/util/lint/kconfig_lint @@ -93,7 +93,7 @@ sub Main { check_used_symbols(); check_for_ifdef(); check_for_def(); - check_is_enabled(); + check_config_macro(); check_selected_symbols(); # Run checks based on the data that was found @@ -213,27 +213,6 @@ sub check_for_ifdef { } } } - - my @collected_is_enabled; - if ($dont_use_git_grep) { - @collected_is_enabled = - `grep -Irn -- "\\ Date: Wed, 22 May 2019 21:44:48 +0200 Subject: [PATCH 317/331] nb/intel/x4x/rcven.c: Remove variable set but not used MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I13d6593e283f0a9e6603e19ccfda116f3b145e52 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/32948 Reviewed-by: Felix Held Reviewed-by: Kyösti Mälkki Tested-by: build bot (Jenkins) --- src/northbridge/intel/x4x/rcven.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/northbridge/intel/x4x/rcven.c b/src/northbridge/intel/x4x/rcven.c index 7c49838d13..36a6ebd259 100644 --- a/src/northbridge/intel/x4x/rcven.c +++ b/src/northbridge/intel/x4x/rcven.c @@ -41,7 +41,6 @@ static inline void barrier(void) static u8 sampledqs(u32 addr, u8 lane, u8 channel) { - volatile u32 strobe; u32 sample_offset = 0x400 * channel + 0x561 + lane * 4; /* Reset the DQS probe */ @@ -50,7 +49,8 @@ static u8 sampledqs(u32 addr, u8 lane, u8 channel) MCHBAR8(RESET_CNTL(channel)) |= 0x2; udelay(2); barrier(); - strobe = read32((u32 *)addr); + /* Read strobe */ + read32((u32 *)addr); barrier(); return (MCHBAR8(sample_offset) >> 6) & 1; } From 12f0e42cb4e66f0ebe198b051be31b68d876d2e5 Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Sat, 6 Apr 2019 16:16:36 +0200 Subject: [PATCH 318/331] kconfig: Drop IS_ENABLED() macro We keep its definition in libpayload, though, to maintain compatibility with existing payload code. For now. Change-Id: I8fc0d0136ba2316ef393c5c17f2b3ac3a9c6328d Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/c/coreboot/+/32230 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner --- Documentation/getting_started/kconfig.md | 2 -- src/include/kconfig.h | 1 - 2 files changed, 3 deletions(-) diff --git a/Documentation/getting_started/kconfig.md b/Documentation/getting_started/kconfig.md index 249fd4600e..852ca08bf9 100644 --- a/Documentation/getting_started/kconfig.md +++ b/Documentation/getting_started/kconfig.md @@ -1165,8 +1165,6 @@ saved .config file. As always, a 'select' statement overrides any specified - coreboot has added the glob operator '*' for the 'source' keyword. - coreboot’s Kconfig always defines variables except for strings. In other Kconfig implementations, bools set to false/0/no are not defined. -- IS_ENABLED() is ‘false’ for undefined variables and ‘0’ variables. In Linux - (where the macro comes from) it’s ‘true’ as soon as the variable is defined. - coreboot’s version of Kconfig adds the KCONFIG_STRICT environment variable to error out if there are any issues in the Kconfig files. In the Linux kernel, Kconfig will generate a warning, but will still output an updated .config or diff --git a/src/include/kconfig.h b/src/include/kconfig.h index 0478548d59..50ef302293 100644 --- a/src/include/kconfig.h +++ b/src/include/kconfig.h @@ -17,7 +17,6 @@ #define __config_enabled(arg1_or_junk) ___config_enabled(arg1_or_junk 1, 0, 0) #define ___config_enabled(__ignored, val, ...) val -#define IS_ENABLED(option) config_enabled(option) /* deprecated */ #define CONFIG(option) config_enabled(CONFIG_##option) #endif From 1b05479a7fc1605e1d9735575300bd09b55e6a5d Mon Sep 17 00:00:00 2001 From: Prudhvi Yarlagadda Date: Fri, 22 Mar 2019 12:38:20 +0530 Subject: [PATCH 319/331] libpayload: Add UART for qcs405 TEST=build Change-Id: I43164cf9eacc844af1d048f7b6ebbda96fc9d202 Signed-off-by: Prudhvi Yarlagadda Signed-off-by: Sricharan R Signed-off-by: Nitheesh Sekar Reviewed-on: https://review.coreboot.org/c/coreboot/+/29957 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- payloads/libpayload/Kconfig | 5 + payloads/libpayload/configs/config.mistral | 2 + payloads/libpayload/drivers/Makefile.inc | 1 + payloads/libpayload/drivers/serial/qcs405.c | 555 ++++++++++++++++++++ 4 files changed, 563 insertions(+) create mode 100644 payloads/libpayload/drivers/serial/qcs405.c diff --git a/payloads/libpayload/Kconfig b/payloads/libpayload/Kconfig index 5dce89ae6f..97b970b0f1 100644 --- a/payloads/libpayload/Kconfig +++ b/payloads/libpayload/Kconfig @@ -258,6 +258,11 @@ config IPQ40XX_SERIAL_CONSOLE depends on SERIAL_CONSOLE default n +config QCS405_SERIAL_CONSOLE + bool "QCS405 SOC compatible serial port driver" + depends on SERIAL_CONSOLE + default n + config PL011_SERIAL_CONSOLE bool "PL011 compatible serial port driver" depends on 8250_SERIAL_CONSOLE diff --git a/payloads/libpayload/configs/config.mistral b/payloads/libpayload/configs/config.mistral index 5f60392fdb..e305fb6700 100644 --- a/payloads/libpayload/configs/config.mistral +++ b/payloads/libpayload/configs/config.mistral @@ -1,3 +1,5 @@ CONFIG_LP_CHROMEOS=y CONFIG_LP_ARCH_ARM64=y CONFIG_LP_TIMER_ARM64_ARCH=y +CONFIG_LP_SERIAL_CONSOLE=y +CONFIG_LP_QCS405_SERIAL_CONSOLE=y diff --git a/payloads/libpayload/drivers/Makefile.inc b/payloads/libpayload/drivers/Makefile.inc index 40e587c223..b4e75943f3 100644 --- a/payloads/libpayload/drivers/Makefile.inc +++ b/payloads/libpayload/drivers/Makefile.inc @@ -37,6 +37,7 @@ libc-$(CONFIG_LP_8250_SERIAL_CONSOLE) += serial/8250.c serial/serial.c libc-$(CONFIG_LP_S5P_SERIAL_CONSOLE) += serial/s5p.c serial/serial.c libc-$(CONFIG_LP_IPQ806X_SERIAL_CONSOLE) += serial/ipq806x.c serial/serial.c libc-$(CONFIG_LP_IPQ40XX_SERIAL_CONSOLE) += serial/ipq40xx.c serial/serial.c +libc-$(CONFIG_LP_QCS405_SERIAL_CONSOLE) += serial/qcs405.c serial/serial.c libc-$(CONFIG_LP_PC_KEYBOARD) += i8042/keyboard.c libc-$(CONFIG_LP_PC_MOUSE) += i8042/mouse.c libc-$(CONFIG_LP_PC_I8042) += i8042/i8042.c diff --git a/payloads/libpayload/drivers/serial/qcs405.c b/payloads/libpayload/drivers/serial/qcs405.c new file mode 100644 index 0000000000..9f02e17263 --- /dev/null +++ b/payloads/libpayload/drivers/serial/qcs405.c @@ -0,0 +1,555 @@ +/* + * Copyright (c) 2010-2012, 2014, 2016, 2019, The Linux Foundation. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of The Linux Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include + +#define UART_DM_CLK_RX_TX_BIT_RATE 0xFF + +enum MSM_BOOT_UART_DM_PARITY_MODE { + MSM_BOOT_UART_DM_NO_PARITY, + MSM_BOOT_UART_DM_ODD_PARITY, + MSM_BOOT_UART_DM_EVEN_PARITY, + MSM_BOOT_UART_DM_SPACE_PARITY +}; + +/* UART Stop Bit Length */ +enum MSM_BOOT_UART_DM_STOP_BIT_LEN { + MSM_BOOT_UART_DM_SBL_9_16, + MSM_BOOT_UART_DM_SBL_1, + MSM_BOOT_UART_DM_SBL_1_9_16, + MSM_BOOT_UART_DM_SBL_2 +}; + +/* UART Bits per Char */ +enum MSM_BOOT_UART_DM_BITS_PER_CHAR { + MSM_BOOT_UART_DM_5_BPS, + MSM_BOOT_UART_DM_6_BPS, + MSM_BOOT_UART_DM_7_BPS, + MSM_BOOT_UART_DM_8_BPS +}; + +/* 8-N-1 Configuration */ +#define MSM_BOOT_UART_DM_8_N_1_MODE (MSM_BOOT_UART_DM_NO_PARITY | \ + (MSM_BOOT_UART_DM_SBL_1 << 2) | \ + (MSM_BOOT_UART_DM_8_BPS << 4)) + +/* UART_DM Registers */ + +/* UART Operational Mode Register */ +#define MSM_BOOT_UART_DM_MR1(base) ((base) + 0x00) +#define MSM_BOOT_UART_DM_MR2(base) ((base) + 0x04) +#define MSM_BOOT_UART_DM_RXBRK_ZERO_CHAR_OFF (1 << 8) +#define MSM_BOOT_UART_DM_LOOPBACK (1 << 7) + +#define PERIPH_BLK_BLSP 1 + +/* UART Clock Selection Register */ +#if PERIPH_BLK_BLSP +#define MSM_BOOT_UART_DM_CSR(base) ((base) + 0xA0) +#else +#define MSM_BOOT_UART_DM_CSR(base) ((base) + 0x08) +#endif + +/* UART DM TX FIFO Registers - 4 */ +#if PERIPH_BLK_BLSP +#define MSM_BOOT_UART_DM_TF(base, x) ((base) + 0x100+(4*(x))) +#else +#define MSM_BOOT_UART_DM_TF(base, x) ((base) + 0x70+(4*(x))) +#endif + +/* UART Command Register */ +#if PERIPH_BLK_BLSP +#define MSM_BOOT_UART_DM_CR(base) ((base) + 0xA8) +#else +#define MSM_BOOT_UART_DM_CR(base) ((base) + 0x10) +#endif +#define MSM_BOOT_UART_DM_CR_RX_ENABLE (1 << 0) +#define MSM_BOOT_UART_DM_CR_RX_DISABLE (1 << 1) +#define MSM_BOOT_UART_DM_CR_TX_ENABLE (1 << 2) +#define MSM_BOOT_UART_DM_CR_TX_DISABLE (1 << 3) + +/* UART Channel Command */ +#define MSM_BOOT_UART_DM_CR_CH_CMD_LSB(x) ((x & 0x0f) << 4) +#define MSM_BOOT_UART_DM_CR_CH_CMD_MSB(x) ((x >> 4) << 11) +#define MSM_BOOT_UART_DM_CR_CH_CMD(x) \ + (MSM_BOOT_UART_DM_CR_CH_CMD_LSB(x) | MSM_BOOT_UART_DM_CR_CH_CMD_MSB(x)) +#define MSM_BOOT_UART_DM_CMD_NULL MSM_BOOT_UART_DM_CR_CH_CMD(0) +#define MSM_BOOT_UART_DM_CMD_RESET_RX MSM_BOOT_UART_DM_CR_CH_CMD(1) +#define MSM_BOOT_UART_DM_CMD_RESET_TX MSM_BOOT_UART_DM_CR_CH_CMD(2) +#define MSM_BOOT_UART_DM_CMD_RESET_ERR_STAT MSM_BOOT_UART_DM_CR_CH_CMD(3) +#define MSM_BOOT_UART_DM_CMD_RES_BRK_CHG_INT MSM_BOOT_UART_DM_CR_CH_CMD(4) +#define MSM_BOOT_UART_DM_CMD_START_BRK MSM_BOOT_UART_DM_CR_CH_CMD(5) +#define MSM_BOOT_UART_DM_CMD_STOP_BRK MSM_BOOT_UART_DM_CR_CH_CMD(6) +#define MSM_BOOT_UART_DM_CMD_RES_CTS_N MSM_BOOT_UART_DM_CR_CH_CMD(7) +#define MSM_BOOT_UART_DM_CMD_RES_STALE_INT MSM_BOOT_UART_DM_CR_CH_CMD(8) +#define MSM_BOOT_UART_DM_CMD_PACKET_MODE MSM_BOOT_UART_DM_CR_CH_CMD(9) +#define MSM_BOOT_UART_DM_CMD_MODE_RESET MSM_BOOT_UART_DM_CR_CH_CMD(C) +#define MSM_BOOT_UART_DM_CMD_SET_RFR_N MSM_BOOT_UART_DM_CR_CH_CMD(D) +#define MSM_BOOT_UART_DM_CMD_RES_RFR_N MSM_BOOT_UART_DM_CR_CH_CMD(E) +#define MSM_BOOT_UART_DM_CMD_RES_TX_ERR MSM_BOOT_UART_DM_CR_CH_CMD(10) +#define MSM_BOOT_UART_DM_CMD_CLR_TX_DONE MSM_BOOT_UART_DM_CR_CH_CMD(11) +#define MSM_BOOT_UART_DM_CMD_RES_BRKSTRT_INT MSM_BOOT_UART_DM_CR_CH_CMD(12) +#define MSM_BOOT_UART_DM_CMD_RES_BRKEND_INT MSM_BOOT_UART_DM_CR_CH_CMD(13) +#define MSM_BOOT_UART_DM_CMD_RES_PER_FRM_INT MSM_BOOT_UART_DM_CR_CH_CMD(14) + +/*UART General Command */ +#define MSM_UART_DM_CR_GENERAL_CMD(x) ((x) << 8) + +#define MSM_BOOT_UART_DM_GCMD_NULL MSM_UART_DM_CR_GENERAL_CMD(0) +#define MSM_BOOT_UART_DM_GCMD_CR_PROT_EN MSM_UART_DM_CR_GENERAL_CMD(1) +#define MSM_BOOT_UART_DM_GCMD_CR_PROT_DIS MSM_UART_DM_CR_GENERAL_CMD(2) +#define MSM_BOOT_UART_DM_GCMD_RES_TX_RDY_INT MSM_UART_DM_CR_GENERAL_CMD(3) +#define MSM_BOOT_UART_DM_GCMD_SW_FORCE_STALE MSM_UART_DM_CR_GENERAL_CMD(4) +#define MSM_BOOT_UART_DM_GCMD_ENA_STALE_EVT MSM_UART_DM_CR_GENERAL_CMD(5) +#define MSM_BOOT_UART_DM_GCMD_DIS_STALE_EVT MSM_UART_DM_CR_GENERAL_CMD(6) + +/* UART Interrupt Mask Register */ +#if PERIPH_BLK_BLSP +#define MSM_BOOT_UART_DM_IMR(base) ((base) + 0xB0) +#else +#define MSM_BOOT_UART_DM_IMR(base) ((base) + 0x14) +#endif + +#define MSM_BOOT_UART_DM_TXLEV (1 << 0) +#define MSM_BOOT_UART_DM_RXHUNT (1 << 1) +#define MSM_BOOT_UART_DM_RXBRK_CHNG (1 << 2) +#define MSM_BOOT_UART_DM_RXSTALE (1 << 3) +#define MSM_BOOT_UART_DM_RXLEV (1 << 4) +#define MSM_BOOT_UART_DM_DELTA_CTS (1 << 5) +#define MSM_BOOT_UART_DM_CURRENT_CTS (1 << 6) +#define MSM_BOOT_UART_DM_TX_READY (1 << 7) +#define MSM_BOOT_UART_DM_TX_ERROR (1 << 8) +#define MSM_BOOT_UART_DM_TX_DONE (1 << 9) +#define MSM_BOOT_UART_DM_RXBREAK_START (1 << 10) +#define MSM_BOOT_UART_DM_RXBREAK_END (1 << 11) +#define MSM_BOOT_UART_DM_PAR_FRAME_ERR_IRQ (1 << 12) + +#define MSM_BOOT_UART_DM_IMR_ENABLED (MSM_BOOT_UART_DM_TX_READY | \ + MSM_BOOT_UART_DM_TXLEV | \ + MSM_BOOT_UART_DM_RXSTALE) + +/* UART Interrupt Programming Register */ +#define MSM_BOOT_UART_DM_IPR(base) ((base) + 0x18) +#define MSM_BOOT_UART_DM_STALE_TIMEOUT_LSB 0x0f +#define MSM_BOOT_UART_DM_STALE_TIMEOUT_MSB 0 /* Not used currently */ + +/* UART Transmit/Receive FIFO Watermark Register */ +#define MSM_BOOT_UART_DM_TFWR(base) ((base) + 0x1C) +/* Interrupt is generated when FIFO level is less than or equal to this value */ +#define MSM_BOOT_UART_DM_TFW_VALUE 0 + +#define MSM_BOOT_UART_DM_RFWR(base) ((base) + 0x20) +/*Interrupt generated when no of words in RX FIFO is greater than this value */ +#define MSM_BOOT_UART_DM_RFW_VALUE 0 + +/* UART Hunt Character Register */ +#define MSM_BOOT_UART_DM_HCR(base) ((base) + 0x24) + +/* Used for RX transfer initialization */ +#define MSM_BOOT_UART_DM_DMRX(base) ((base) + 0x34) + +/* Default DMRX value - any value bigger than FIFO size would be fine */ +#define MSM_BOOT_UART_DM_DMRX_DEF_VALUE 0x220 + +/* Register to enable IRDA function */ +#if PERIPH_BLK_BLSP +#define MSM_BOOT_UART_DM_IRDA(base) ((base) + 0xB8) +#else +#define MSM_BOOT_UART_DM_IRDA(base) ((base) + 0x38) +#endif + +/* UART Data Mover Enable Register */ +#define MSM_BOOT_UART_DM_DMEN(base) ((base) + 0x3C) + +/* Number of characters for Transmission */ +#define MSM_BOOT_UART_DM_NO_CHARS_FOR_TX(base) ((base) + 0x040) + +/* UART RX FIFO Base Address */ +#define MSM_BOOT_UART_DM_BADR(base) ((base) + 0x44) + +/* UART Status Register */ +#if PERIPH_BLK_BLSP +#define MSM_BOOT_UART_DM_SR(base) ((base) + 0x0A4) +#else +#define MSM_BOOT_UART_DM_SR(base) ((base) + 0x008) +#endif +#define MSM_BOOT_UART_DM_SR_RXRDY (1 << 0) +#define MSM_BOOT_UART_DM_SR_RXFULL (1 << 1) +#define MSM_BOOT_UART_DM_SR_TXRDY (1 << 2) +#define MSM_BOOT_UART_DM_SR_TXEMT (1 << 3) +#define MSM_BOOT_UART_DM_SR_UART_OVERRUN (1 << 4) +#define MSM_BOOT_UART_DM_SR_PAR_FRAME_ERR (1 << 5) +#define MSM_BOOT_UART_DM_RX_BREAK (1 << 6) +#define MSM_BOOT_UART_DM_HUNT_CHAR (1 << 7) +#define MSM_BOOT_UART_DM_RX_BRK_START_LAST (1 << 8) + +/* UART Receive FIFO Registers - 4 in numbers */ +#if PERIPH_BLK_BLSP +#define MSM_BOOT_UART_DM_RF(base, x) ((base) + 0x140 + (4*(x))) +#else +#define MSM_BOOT_UART_DM_RF(base, x) ((base) + 0x70 + (4*(x))) +#endif + +/* UART Masked Interrupt Status Register */ +#if PERIPH_BLK_BLSP +#define MSM_BOOT_UART_DM_MISR(base) ((base) + 0xAC) +#else +#define MSM_BOOT_UART_DM_MISR(base) ((base) + 0x10) +#endif + +/* UART Interrupt Status Register */ +#if PERIPH_BLK_BLSP +#define MSM_BOOT_UART_DM_ISR(base) ((base) + 0xB4) +#else +#define MSM_BOOT_UART_DM_ISR(base) ((base) + 0x14) +#endif + +/* Number of characters received since the end of last RX transfer */ +#if PERIPH_BLK_BLSP +#define MSM_BOOT_UART_DM_RX_TOTAL_SNAP(base) ((base) + 0xBC) +#else +#define MSM_BOOT_UART_DM_RX_TOTAL_SNAP(base) ((base) + 0x38) +#endif + +/* UART TX FIFO Status Register */ +#define MSM_BOOT_UART_DM_TXFS(base) ((base) + 0x4C) +#define MSM_BOOT_UART_DM_TXFS_STATE_LSB(x) \ + MSM_BOOT_UART_DM_EXTR_BITS(x, 0, 6) +#define MSM_BOOT_UART_DM_TXFS_STATE_MSB(x) \ + MSM_BOOT_UART_DM_EXTR_BITS(x, 14, 31) +#define MSM_BOOT_UART_DM_TXFS_BUF_STATE(x) \ + MSM_BOOT_UART_DM_EXTR_BITS(x, 7, 9) +#define MSM_BOOT_UART_DM_TXFS_ASYNC_STATE(x) \ + MSM_BOOT_UART_DM_EXTR_BITS(x, 10, 13) + +/* UART RX FIFO Status Register */ +#define MSM_BOOT_UART_DM_RXFS(base) ((base) + 0x50) +#define MSM_BOOT_UART_DM_RXFS_STATE_LSB(x) \ + MSM_BOOT_UART_DM_EXTR_BITS(x, 0, 6) +#define MSM_BOOT_UART_DM_RXFS_STATE_MSB(x) \ + MSM_BOOT_UART_DM_EXTR_BITS(x, 14, 31) +#define MSM_BOOT_UART_DM_RXFS_BUF_STATE(x) \ + MSM_BOOT_UART_DM_EXTR_BITS(x, 7, 9) +#define MSM_BOOT_UART_DM_RXFS_ASYNC_STATE(x) \ + MSM_BOOT_UART_DM_EXTR_BITS(x, 10, 13) + +/* Macros for Common Errors */ +#define MSM_BOOT_UART_DM_E_FAILURE 1 +#define MSM_BOOT_UART_DM_E_TIMEOUT 2 +#define MSM_BOOT_UART_DM_E_INVAL 3 +#define MSM_BOOT_UART_DM_E_MALLOC_FAIL 4 +#define MSM_BOOT_UART_DM_E_RX_NOT_READY 5 + +#define UART1_DM_BASE ((void *)0x078af000) +#define UART2_DM_BASE ((void *)0x078b1000) + +enum { + BLSP1_UART1, + BLSP1_UART2, +}; + +#define FIFO_DATA_SIZE 4 + +struct uart_params_t { + void *uart_dm_base; + unsigned int blsp_uart; +}; + +static struct console_input_driver consin = { + .havekey = serial_havechar, + .getchar = serial_getchar, +}; + +static struct console_output_driver consout = { + .putchar = serial_putchar, +}; + +static struct uart_params_t uart_board_param = {}; + +/** + * msm_boot_uart_dm_init_rx_transfer - Init Rx transfer + * @uart_dm_base: UART controller base address + */ +static unsigned int msm_boot_uart_dm_init_rx_transfer(void *uart_dm_base) +{ + /* Reset receiver */ + write32(MSM_BOOT_UART_DM_CR(uart_dm_base), + MSM_BOOT_UART_DM_CMD_RESET_RX); + + /* Enable receiver */ + write32(MSM_BOOT_UART_DM_CR(uart_dm_base), + MSM_BOOT_UART_DM_CR_RX_ENABLE); + write32(MSM_BOOT_UART_DM_DMRX(uart_dm_base), + MSM_BOOT_UART_DM_DMRX_DEF_VALUE); + + /* Clear stale event */ + write32(MSM_BOOT_UART_DM_CR(uart_dm_base), + MSM_BOOT_UART_DM_CMD_RES_STALE_INT); + + /* Enable stale event */ + write32(MSM_BOOT_UART_DM_CR(uart_dm_base), + MSM_BOOT_UART_DM_GCMD_ENA_STALE_EVT); + + return 0; +} + +static unsigned int msm_boot_uart_dm_init(void *uart_dm_base); + +static int valid_data = 0; + +static unsigned int word = 0; + +/** + * msm_boot_uart_dm_read - reads a word from the RX FIFO. + * @data: location where the read data is stored + * @count: no of valid data in the FIFO + * + * Reads a word from the RX FIFO. If no data is available + * returns %MSM_BOOT_UART_DM_E_RX_NOT_READY. + */ +static unsigned int +msm_boot_uart_dm_read(unsigned int *data, int *count) +{ + static int total_rx_data = 0; + static int rx_data_read = 0; + void *base; + uint32_t status_reg; + + base = uart_board_param.uart_dm_base; + + if (data == NULL) + return MSM_BOOT_UART_DM_E_INVAL; + + status_reg = read32(MSM_BOOT_UART_DM_MISR(base)); + + /* Check for DM_RXSTALE for RX transfer to finish */ + while (!(status_reg & MSM_BOOT_UART_DM_RXSTALE)) { + status_reg = read32(MSM_BOOT_UART_DM_MISR(base)); + return MSM_BOOT_UART_DM_E_RX_NOT_READY; + } + + /* Check for Overrun error. We'll just reset Error Status */ + if (read32(MSM_BOOT_UART_DM_SR(base)) & + MSM_BOOT_UART_DM_SR_UART_OVERRUN) { + write32(MSM_BOOT_UART_DM_CR(base), + MSM_BOOT_UART_DM_CMD_RESET_ERR_STAT); + total_rx_data = rx_data_read = 0; + msm_boot_uart_dm_init(base); + return MSM_BOOT_UART_DM_E_RX_NOT_READY; + } + + /* Read UART_DM_RX_TOTAL_SNAP for actual number of bytes received */ + if (total_rx_data == 0) + total_rx_data = read32(MSM_BOOT_UART_DM_RX_TOTAL_SNAP(base)); + + /* Data available in FIFO; read a word. */ + *data = read32(MSM_BOOT_UART_DM_RF(base, 0)); + + /* increment the total count of chars we've read so far */ + rx_data_read += FIFO_DATA_SIZE; + + /* actual count of valid data in word */ + *count = ((total_rx_data < rx_data_read) ? + (FIFO_DATA_SIZE - (rx_data_read - total_rx_data)) : + FIFO_DATA_SIZE); + + /* If there are still data left in FIFO we'll read them before + * initializing RX Transfer again + */ + if (rx_data_read < total_rx_data) + return 0; + + msm_boot_uart_dm_init_rx_transfer(base); + total_rx_data = rx_data_read = 0; + + return 0; +} + +void serial_putchar(unsigned int data) +{ + int num_of_chars = 1; + void *base = uart_board_param.uart_dm_base; + + if (data == '\n') { + num_of_chars++; + data = (data << 8) | '\r'; + } + + /* Wait until transmit FIFO is empty. */ + while (!(read32(MSM_BOOT_UART_DM_SR(base)) & + MSM_BOOT_UART_DM_SR_TXEMT)) + udelay(1); + /* + * TX FIFO is ready to accept new character(s). First write number of + * characters to be transmitted. + */ + write32(MSM_BOOT_UART_DM_NO_CHARS_FOR_TX(base), num_of_chars); + + /* And now write the character(s) */ + write32(MSM_BOOT_UART_DM_TF(base, 0), data); +} + +/* + * msm_boot_uart_dm_reset - resets UART controller + * @base: UART controller base address + */ +static unsigned int msm_boot_uart_dm_reset(void *base) +{ + write32(MSM_BOOT_UART_DM_CR(base), MSM_BOOT_UART_DM_CMD_RESET_RX); + write32(MSM_BOOT_UART_DM_CR(base), MSM_BOOT_UART_DM_CMD_RESET_TX); + write32(MSM_BOOT_UART_DM_CR(base), + MSM_BOOT_UART_DM_CMD_RESET_ERR_STAT); + write32(MSM_BOOT_UART_DM_CR(base), MSM_BOOT_UART_DM_CMD_RES_TX_ERR); + write32(MSM_BOOT_UART_DM_CR(base), MSM_BOOT_UART_DM_CMD_RES_STALE_INT); + + return 0; +} + +/* + * msm_boot_uart_dm_init - initilaizes UART controller + * @uart_dm_base: UART controller base address + */ +unsigned int msm_boot_uart_dm_init(void *uart_dm_base) +{ + /* Configure UART mode registers MR1 and MR2 */ + /* Hardware flow control isn't supported */ + write32(MSM_BOOT_UART_DM_MR1(uart_dm_base), 0x0); + + /* 8-N-1 configuration: 8 data bits - No parity - 1 stop bit */ + write32(MSM_BOOT_UART_DM_MR2(uart_dm_base), + MSM_BOOT_UART_DM_8_N_1_MODE); + + /* Configure Interrupt Mask register IMR */ + write32(MSM_BOOT_UART_DM_IMR(uart_dm_base), + MSM_BOOT_UART_DM_IMR_ENABLED); + + /* + * Configure Tx and Rx watermarks configuration registers + * TX watermark value is set to 0 - interrupt is generated when + * FIFO level is less than or equal to 0 + */ + write32(MSM_BOOT_UART_DM_TFWR(uart_dm_base), + MSM_BOOT_UART_DM_TFW_VALUE); + + /* RX watermark value */ + write32(MSM_BOOT_UART_DM_RFWR(uart_dm_base), + MSM_BOOT_UART_DM_RFW_VALUE); + + /* Configure Interrupt Programming Register */ + /* Set initial Stale timeout value */ + write32(MSM_BOOT_UART_DM_IPR(uart_dm_base), + MSM_BOOT_UART_DM_STALE_TIMEOUT_LSB); + + /* Configure IRDA if required */ + /* Disabling IRDA mode */ + write32(MSM_BOOT_UART_DM_IRDA(uart_dm_base), 0x0); + + /* Configure hunt character value in HCR register */ + /* Keep it in reset state */ + write32(MSM_BOOT_UART_DM_HCR(uart_dm_base), 0x0); + + /* + * Configure Rx FIFO base address + * Both TX/RX shares same SRAM and default is half-n-half. + * Sticking with default value now. + * As such RAM size is (2^RAM_ADDR_WIDTH, 32-bit entries). + * We have found RAM_ADDR_WIDTH = 0x7f + */ + + /* Issue soft reset command */ + msm_boot_uart_dm_reset(uart_dm_base); + + /* Enable/Disable Rx/Tx DM interfaces */ + /* Data Mover not currently utilized. */ + write32(MSM_BOOT_UART_DM_DMEN(uart_dm_base), 0x0); + + /* Enable transmitter */ + write32(MSM_BOOT_UART_DM_CR(uart_dm_base), + MSM_BOOT_UART_DM_CR_TX_ENABLE); + + /* Initialize Receive Path */ + msm_boot_uart_dm_init_rx_transfer(uart_dm_base); + + return 0; +} + +/** + * serial_havechar - checks if data available for reading + * + * Returns 1 if data available, 0 otherwise + */ +int serial_havechar(void) +{ + /* Return if data is already read */ + if (valid_data) + return 1; + + /* Read data from the FIFO */ + if (msm_boot_uart_dm_read(&word, &valid_data) != 0) + return 0; + + return 1; +} + +/** + * qcs405_serial_getc - reads a character + * + * Returns the character read from serial port. + */ +int serial_getchar(void) +{ + uint8_t byte; + + while (!serial_havechar()) + ; /* wait for incoming data */ + + byte = (uint8_t)(word & 0xff); + word = word >> 8; + valid_data--; + + return byte; +} + +/* For simplicity sake let's rely on coreboot initalizing the UART. */ +void serial_console_init(void) +{ + struct cb_serial *sc_ptr = lib_sysinfo.serial; + + if (!sc_ptr) + return; + + uart_board_param.uart_dm_base = (void *)(uintptr_t)sc_ptr->baseaddr; + + /* TODO: We should rely on coreboot init. */ + msm_boot_uart_dm_init(uart_board_param.uart_dm_base); + + console_add_output_driver(&consout); + console_add_input_driver(&consin); +} From 37e957f3349c461371e15cd3d6f754514506ce47 Mon Sep 17 00:00:00 2001 From: Prudhvi Yarlagadda Date: Fri, 22 Mar 2019 15:26:02 +0530 Subject: [PATCH 320/331] qcs405: Add UART support Add support for UART driver in coreboot. TEST=build & run Change-Id: Id9626c68eadead8b8ec5ffbc08cab7b0ec36478f Signed-off-by: Prudhvi Yarlagadda Signed-off-by: Sricharan R Signed-off-by: Nitheesh Sekar Reviewed-on: https://review.coreboot.org/c/coreboot/+/29964 Reviewed-by: Stefan Reinauer Tested-by: build bot (Jenkins) --- src/soc/qualcomm/qcs405/Kconfig | 1 + src/soc/qualcomm/qcs405/Makefile.inc | 4 + src/soc/qualcomm/qcs405/include/soc/blsp.h | 60 ++++ src/soc/qualcomm/qcs405/include/soc/cdp.h | 144 ++++++++++ src/soc/qualcomm/qcs405/include/soc/iomap.h | 156 ++++++++++ src/soc/qualcomm/qcs405/include/soc/uart.h | 273 ++++++++++++++++++ src/soc/qualcomm/qcs405/uart.c | 303 ++++++++++++++++++++ 7 files changed, 941 insertions(+) create mode 100644 src/soc/qualcomm/qcs405/include/soc/blsp.h create mode 100644 src/soc/qualcomm/qcs405/include/soc/cdp.h create mode 100644 src/soc/qualcomm/qcs405/include/soc/iomap.h create mode 100644 src/soc/qualcomm/qcs405/include/soc/uart.h create mode 100644 src/soc/qualcomm/qcs405/uart.c diff --git a/src/soc/qualcomm/qcs405/Kconfig b/src/soc/qualcomm/qcs405/Kconfig index 3e8c1ba5be..6bbdd3bf34 100644 --- a/src/soc/qualcomm/qcs405/Kconfig +++ b/src/soc/qualcomm/qcs405/Kconfig @@ -11,6 +11,7 @@ config SOC_QUALCOMM_QCS405 select GENERIC_UDELAY select HAVE_MONOTONIC_TIMER select ARM64_USE_ARCH_TIMER + select HAVE_UART_SPECIAL if SOC_QUALCOMM_QCS405 diff --git a/src/soc/qualcomm/qcs405/Makefile.inc b/src/soc/qualcomm/qcs405/Makefile.inc index 4df5246e3c..c64e5bcf58 100644 --- a/src/soc/qualcomm/qcs405/Makefile.inc +++ b/src/soc/qualcomm/qcs405/Makefile.inc @@ -8,12 +8,14 @@ bootblock-y += spi.c bootblock-y += mmu.c bootblock-y += gpio.c bootblock-y += clock.c +bootblock-$(CONFIG_DRIVERS_UART) += uart.c ################################################################################ verstage-y += timer.c verstage-y += spi.c verstage-y += gpio.c verstage-y += clock.c +verstage-$(CONFIG_DRIVERS_UART) += uart.c ################################################################################ romstage-y += timer.c @@ -22,6 +24,7 @@ romstage-y += cbmem.c romstage-y += gpio.c romstage-y += clock.c romstage-y += usb.c +romstage-$(CONFIG_DRIVERS_UART) += uart.c ################################################################################ ramstage-y += soc.c @@ -31,6 +34,7 @@ ramstage-y += cbmem.c ramstage-y += gpio.c ramstage-y += clock.c ramstage-y += usb.c +ramstage-$(CONFIG_DRIVERS_UART) += uart.c ################################################################################ diff --git a/src/soc/qualcomm/qcs405/include/soc/blsp.h b/src/soc/qualcomm/qcs405/include/soc/blsp.h new file mode 100644 index 0000000000..6e55d7dd37 --- /dev/null +++ b/src/soc/qualcomm/qcs405/include/soc/blsp.h @@ -0,0 +1,60 @@ +/* + * Copyright (c) 2011-2019 The Linux Foundation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of The Linux Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + +#ifndef __BLSP_H_ +#define __BLSP_H_ + +typedef enum { + BLSP_QUP_ID_0, + BLSP_QUP_ID_1, + BLSP_QUP_ID_2, + BLSP_QUP_ID_3, +} blsp_qup_id_t; + +typedef enum { + BLSP_SUCCESS = 0, + BLSP_ID_ERROR, + BLSP_ERROR, + BLSP_UNSUPPORTED +} blsp_return_t; + +typedef enum { + BLSP_PROTO_I2C_UIM = 1, + BLSP_PROTO_I2C_ONLY, + BLSP_PROTO_SPI_ONLY, + BLSP_PROTO_UART_FLOW_CTL, + BLSP_PROTO_UIM, + BLSP_PROTO_I2C_UART, +} blsp_protocol_t; + +blsp_return_t blsp_i2c_init(blsp_qup_id_t id); +int blsp_i2c_init_board(blsp_qup_id_t id); + +#endif diff --git a/src/soc/qualcomm/qcs405/include/soc/cdp.h b/src/soc/qualcomm/qcs405/include/soc/cdp.h new file mode 100644 index 0000000000..8e33f4b960 --- /dev/null +++ b/src/soc/qualcomm/qcs405/include/soc/cdp.h @@ -0,0 +1,144 @@ +/* + * Copyright (c) 2012-2019 The Linux Foundation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of The Linux Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + +#ifndef _QCS405_CDP_H_ +#define _QCS405_CDP_H_ + +#include + +unsigned int smem_get_board_machtype(void); + +typedef enum { + PHY_INTERFACE_MODE_MII, + PHY_INTERFACE_MODE_GMII, + PHY_INTERFACE_MODE_SGMII, + PHY_INTERFACE_MODE_QSGMII, + PHY_INTERFACE_MODE_TBI, + PHY_INTERFACE_MODE_RMII, + PHY_INTERFACE_MODE_RGMII, + PHY_INTERFACE_MODE_RGMII_ID, + PHY_INTERFACE_MODE_RGMII_RXID, + PHY_INTERFACE_MODE_RGMII_TXID, + PHY_INTERFACE_MODE_RTBI, + PHY_INTERFACE_MODE_XGMII, + PHY_INTERFACE_MODE_NONE /* Must be last */ +} phy_interface_t; + +typedef struct { + gpio_t gpio; + unsigned int func; + unsigned int dir; + unsigned int pull; + unsigned int drvstr; + unsigned int enable; +} gpio_func_data_t; + +typedef struct { + unsigned int m_value; + unsigned int n_value; + unsigned int d_value; +} uart_clk_mnd_t; + +/* SPI Mode */ + +typedef enum { + NOR_SPI_MODE_0, + NOR_SPI_MODE_1, + NOR_SPI_MODE_2, + NOR_SPI_MODE_3, +} spi_mode; + +/* SPI Chip selects */ + +typedef enum { + SPI_CS_0, + SPI_CS_1, + SPI_CS_2, + SPI_CS_3, +} spi_cs; + +/* Flash Types */ + +typedef enum { + ONLY_NAND, + ONLY_NOR, + NAND_NOR, + NOR_MMC, +} flash_desc; + +#define NO_OF_DBG_UART_GPIOS 2 + +#define SPI_NOR_FLASH_VENDOR_MICRON 0x1 +#define SPI_NOR_FLASH_VENDOR_SPANSION 0x2 + +/* SPI parameters */ + +typedef struct { + spi_mode mode; + spi_cs chip_select; + int vendor; +} spinorflash_params_t; + +typedef struct { + unsigned int count; + uint8_t addr[7]; +} ipq_gmac_phy_addr_t; + +typedef struct { + unsigned int base; + int unit; + unsigned int is_macsec; + unsigned int mac_pwr0; + unsigned int mac_pwr1; + unsigned int mac_conn_to_phy; + phy_interface_t phy; + ipq_gmac_phy_addr_t phy_addr; +} ipq_gmac_board_cfg_t; + +#define IPQ_GMAC_NMACS 4 + +enum gale_board_id { + BOARD_ID_GALE_PROTO = 0, + BOARD_ID_GALE_EVT = 1, + BOARD_ID_GALE_EVT2_0 = 2, + BOARD_ID_GALE_EVT2_1 = 6, + BOARD_ID_GALE_EVT3 = 5, +}; + +/* Board specific parameters */ +typedef struct { +} __packed board_ipq40xx_params_t; + +extern board_ipq40xx_params_t *gboard_param; + +unsigned int get_board_index(unsigned int machid); +void ipq_configure_gpio(const gpio_func_data_t *gpio, unsigned int count); + +#endif diff --git a/src/soc/qualcomm/qcs405/include/soc/iomap.h b/src/soc/qualcomm/qcs405/include/soc/iomap.h new file mode 100644 index 0000000000..2ed3e10f76 --- /dev/null +++ b/src/soc/qualcomm/qcs405/include/soc/iomap.h @@ -0,0 +1,156 @@ +/* + * Copyright (c) 2012 - 2013, 2015, 2019 The Linux Foundation. + * All rights reserved. + * + * Copyright (c) 2008, Google Inc. + * All rights reserved. + * + * Copyright (c) 2009-2012, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Google, Inc. nor the names of its contributors + * may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#ifndef __SOC_QUALCOMM_QCS405_IOMAP_H_ +#define __SOC_QUALCOMM_QCS405_IOMAP_H_ + +#include +#include +#include + +/* Typecast to allow integers being passed as address + This needs to be included because vendor code is not compliant with our + macros for read/write. Hence, special macros for readl_i and writel_i are + included to do this in one place for all occurrences in vendor code + */ +#define readl_i(a) read32((const void *)(a)) +#define writel_i(v, a) write32((void *)a, v) +#define clrsetbits_le32_i(addr, clear, set) \ + clrsetbits_le32(((void *)(addr)), (clear), (set)) + +#define GCC_CLK_CTL_REG ((void *)0x01800000u) +#define MSM_CLK_CTL_BASE GCC_CLK_CTL_REG +#define GCC_CLK_BRANCH_ENA (GCC_CLK_CTL_REG + 0x6000) +#define IMEM_AXI (1 << 17) +#define SYS_NOC_APSS_AHB (1 << 16) +#define BIMC_AXI_M0 (1 << 15) +#define APSS_AHB (1 << 14) +#define APSS_AXI (1 << 13) +#define MPM_AHB (1 << 12) +#define GMEM_SYS_NOC_AXI (1 << 11) +#define BLSP1_AHB (1 << 10) +#define BLSP1_SLEEP (1 << 9) +#define PRNG_AHB (1 << 8) +#define BOOT_ROM_AHB (1 << 7) +#define MSG_RAM_AHB (1 << 6) +#define TLMM_AHB (1 << 5) +#define TLMM (1 << 4) +#define SPMI_PCNOC_AHB (1 << 3) +#define CRYPTO (1 << 2) +#define CRYPTO_AXI (1 << 1) +#define CRYPTO_AHB (1 << 0) + +#define GCC_BLSP1_QUP1_I2C_APPS_CBCR (MSM_CLK_CTL_BASE + 0x2008) +#define GCC_BLSP1_QUP1_I2C_APPS_CMD_RCGR (MSM_CLK_CTL_BASE + 0x200c) +#define GCC_BLSP1_QUP1_I2C_APPS_CFG_RCGR (MSM_CLK_CTL_BASE + 0x2010) +#define GCC_BLSP1_QUP2_I2C_APPS_CBCR (MSM_CLK_CTL_BASE + 0x3010) +#define GCC_BLSP1_QUP2_I2C_APPS_CMD_RCGR (MSM_CLK_CTL_BASE + 0x3000) +#define GCC_BLSP1_QUP2_I2C_APPS_CFG_RCGR (MSM_CLK_CTL_BASE + 0x3004) + +#define GCNT_GLOBAL_CTRL_BASE ((void *)0x004a0000u) +#define GCNT_CNTCR (GCNT_GLOBAL_CTRL_BASE + 0x1000) +#define GCNT_GLB_CNTCV_LO (GCNT_GLOBAL_CTRL_BASE + 0x1008) +#define GCNT_GLB_CNTCV_HI (GCNT_GLOBAL_CTRL_BASE + 0x100c) +#define GCNT_CNTCV_LO (GCNT_GLOBAL_CTRL_BASE + 0x2000) +#define GCNT_CNTCV_HI (GCNT_GLOBAL_CTRL_BASE + 0x2004) + +#define GCNT_PSHOLD ((void *)0x004AB000u) + +/* RPM interface constants */ +#define RPM_INT ((void *)0x63020) +#define RPM_INT_ACK ((void *)0x63060) +#define RPM_SIGNAL_COOKIE ((void *)0x47C20) +#define RPM_SIGNAL_ENTRY ((void *)0x47C24) +#define RPM_FW_MAGIC_NUM 0x4D505242 + +#define TLMM_BASE_ADDR ((void *)0x01000000) +#define GPIO_CONFIG_ADDR(x) (TLMM_BASE_ADDR + 0x1000 * (x)) +#define GPIO_IN_OUT_ADDR(x) (GPIO_CONFIG_ADDR(x) + 4) + +/* Yes, this is not a typo... host2 is actually mapped before host1. */ +#define USB_HOST2_XHCI_BASE 0x10000000 +#define USB_HOST2_DWC3_BASE 0x1000C100 +#define USB_HOST2_PHY_BASE 0x100F8800 +#define USB_HOST1_XHCI_BASE 0x11000000 +#define USB_HOST1_DWC3_BASE 0x1100C100 +#define USB_HOST1_PHY_BASE 0x110F8800 + +#define UART1_DM_BASE ((void *)0x078af000) +#define UART2_DM_BASE ((void *)0x078B1000) + +enum { + BLSP1_UART1, + BLSP1_UART2, +}; + +#define GCC_BLSP1_UART_BCR_BASE (GCC_CLK_CTL_REG + 0x2038) +#define GCC_BLSP1_UART_BCR(x) (GCC_BLSP1_UART_BCR_BASE + (x) * 0xff0) +#define GCC_BLSP1_UART_APPS_CBCR(x) (GCC_BLSP1_UART_BCR(x) + 4) +#define GCC_BLSP1_UART_APPS_CMD_RCGR(x) (GCC_BLSP1_UART_APPS_CBCR(x) + 8) +#define GCC_BLSP1_UART_APPS_CFG_RCGR(x) (GCC_BLSP1_UART_APPS_CMD_RCGR(x) + 4) +#define GCC_BLSP1_UART_APPS_M(x) (GCC_BLSP1_UART_APPS_CFG_RCGR(x) + 4) +#define GCC_BLSP1_UART_APPS_N(x) (GCC_BLSP1_UART_APPS_M(x) + 4) +#define GCC_BLSP1_UART_APPS_D(x) (GCC_BLSP1_UART_APPS_N(x) + 4) +#define GCC_BLSP1_UART_MISC(x) (GCC_BLSP1_UART_APPS_D(x) + 4) + +#define BLSP1_QUP0_BASE ((void *)0x078B5000) +#define BLSP1_QUP1_BASE ((void *)0x078B6000) +#define BLSP1_QUP2_BASE ((void *)0x078B7000) +#define BLSP1_QUP3_BASE ((void *)0x078B8000) + +#define TCSR_BOOT_MISC_DETECT ((void *)0x0193D100) +#define TCSR_RESET_DEBUG_SW_ENTRY ((void *)0x01940000) + +static inline void *blsp_qup_base(blsp_qup_id_t id) +{ + switch (id) { + case BLSP_QUP_ID_0: return BLSP1_QUP0_BASE; + case BLSP_QUP_ID_1: return BLSP1_QUP1_BASE; + case BLSP_QUP_ID_2: return BLSP1_QUP2_BASE; + case BLSP_QUP_ID_3: return BLSP1_QUP3_BASE; + } + return NULL; +} + +#define BLSP_MINI_CORE_SHIFT 8 +#define BLSP_MINI_CORE_I2C (0x2u << BLSP_MINI_CORE_SHIFT) +#define BLSP_MINI_CORE_MASK (0xfu << BLSP_MINI_CORE_SHIFT) + +#define ETIMEDOUT -10 +#define EINVAL -11 +#define EIO -12 + +#endif diff --git a/src/soc/qualcomm/qcs405/include/soc/uart.h b/src/soc/qualcomm/qcs405/include/soc/uart.h new file mode 100644 index 0000000000..5c8a361c7b --- /dev/null +++ b/src/soc/qualcomm/qcs405/include/soc/uart.h @@ -0,0 +1,273 @@ +/* + * Copyright (c) 2012-2019 The Linux Foundation. All rights reserved.* + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of The Linux Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __UART_DM_H__ +#define __UART_DM_H__ + +#define PERIPH_BLK_BLSP 1 + +#define MSM_BOOT_UART_DM_EXTR_BITS(value, start_pos, end_pos) \ + ((value << (32 - end_pos)) >> (32 - (end_pos - start_pos))) + +extern void __udelay(unsigned long usec); + + +enum MSM_BOOT_UART_DM_PARITY_MODE { + MSM_BOOT_UART_DM_NO_PARITY, + MSM_BOOT_UART_DM_ODD_PARITY, + MSM_BOOT_UART_DM_EVEN_PARITY, + MSM_BOOT_UART_DM_SPACE_PARITY +}; + +/* UART Stop Bit Length */ +enum MSM_BOOT_UART_DM_STOP_BIT_LEN { + MSM_BOOT_UART_DM_SBL_9_16, + MSM_BOOT_UART_DM_SBL_1, + MSM_BOOT_UART_DM_SBL_1_9_16, + MSM_BOOT_UART_DM_SBL_2 +}; + +/* UART Bits per Char */ +enum MSM_BOOT_UART_DM_BITS_PER_CHAR { + MSM_BOOT_UART_DM_5_BPS, + MSM_BOOT_UART_DM_6_BPS, + MSM_BOOT_UART_DM_7_BPS, + MSM_BOOT_UART_DM_8_BPS +}; + +/* 8-N-1 Configuration */ +#define MSM_BOOT_UART_DM_8_N_1_MODE (MSM_BOOT_UART_DM_NO_PARITY | \ + (MSM_BOOT_UART_DM_SBL_1 << 2) | \ + (MSM_BOOT_UART_DM_8_BPS << 4)) + +/* UART_DM Registers */ + +/* UART Operational Mode Register */ +#define MSM_BOOT_UART_DM_MR1(base) ((base) + 0x00) +#define MSM_BOOT_UART_DM_MR2(base) ((base) + 0x04) +#define MSM_BOOT_UART_DM_RXBRK_ZERO_CHAR_OFF (1 << 8) +#define MSM_BOOT_UART_DM_LOOPBACK (1 << 7) + +/* UART Clock Selection Register */ +#if PERIPH_BLK_BLSP +#define MSM_BOOT_UART_DM_CSR(base) ((base) + 0xA0) +#else +#define MSM_BOOT_UART_DM_CSR(base) ((base) + 0x08) +#endif + +/* UART DM TX FIFO Registers - 4 */ +#if PERIPH_BLK_BLSP +#define MSM_BOOT_UART_DM_TF(base, x) ((base) + 0x100+(4*(x))) +#else +#define MSM_BOOT_UART_DM_TF(base, x) ((base) + 0x70+(4*(x))) +#endif + +/* UART Command Register */ +#if PERIPH_BLK_BLSP +#define MSM_BOOT_UART_DM_CR(base) ((base) + 0xA8) +#else +#define MSM_BOOT_UART_DM_CR(base) ((base) + 0x10) +#endif +#define MSM_BOOT_UART_DM_CR_RX_ENABLE (1 << 0) +#define MSM_BOOT_UART_DM_CR_RX_DISABLE (1 << 1) +#define MSM_BOOT_UART_DM_CR_TX_ENABLE (1 << 2) +#define MSM_BOOT_UART_DM_CR_TX_DISABLE (1 << 3) + +/* UART Channel Command */ +#define MSM_BOOT_UART_DM_CR_CH_CMD_LSB(x) ((x & 0x0f) << 4) +#define MSM_BOOT_UART_DM_CR_CH_CMD_MSB(x) ((x >> 4) << 11) +#define MSM_BOOT_UART_DM_CR_CH_CMD(x) \ + (MSM_BOOT_UART_DM_CR_CH_CMD_LSB(x) | MSM_BOOT_UART_DM_CR_CH_CMD_MSB(x)) +#define MSM_BOOT_UART_DM_CMD_NULL MSM_BOOT_UART_DM_CR_CH_CMD(0) +#define MSM_BOOT_UART_DM_CMD_RESET_RX MSM_BOOT_UART_DM_CR_CH_CMD(1) +#define MSM_BOOT_UART_DM_CMD_RESET_TX MSM_BOOT_UART_DM_CR_CH_CMD(2) +#define MSM_BOOT_UART_DM_CMD_RESET_ERR_STAT MSM_BOOT_UART_DM_CR_CH_CMD(3) +#define MSM_BOOT_UART_DM_CMD_RES_BRK_CHG_INT MSM_BOOT_UART_DM_CR_CH_CMD(4) +#define MSM_BOOT_UART_DM_CMD_START_BRK MSM_BOOT_UART_DM_CR_CH_CMD(5) +#define MSM_BOOT_UART_DM_CMD_STOP_BRK MSM_BOOT_UART_DM_CR_CH_CMD(6) +#define MSM_BOOT_UART_DM_CMD_RES_CTS_N MSM_BOOT_UART_DM_CR_CH_CMD(7) +#define MSM_BOOT_UART_DM_CMD_RES_STALE_INT MSM_BOOT_UART_DM_CR_CH_CMD(8) +#define MSM_BOOT_UART_DM_CMD_PACKET_MODE MSM_BOOT_UART_DM_CR_CH_CMD(9) +#define MSM_BOOT_UART_DM_CMD_MODE_RESET MSM_BOOT_UART_DM_CR_CH_CMD(C) +#define MSM_BOOT_UART_DM_CMD_SET_RFR_N MSM_BOOT_UART_DM_CR_CH_CMD(D) +#define MSM_BOOT_UART_DM_CMD_RES_RFR_N MSM_BOOT_UART_DM_CR_CH_CMD(E) +#define MSM_BOOT_UART_DM_CMD_RES_TX_ERR MSM_BOOT_UART_DM_CR_CH_CMD(10) +#define MSM_BOOT_UART_DM_CMD_CLR_TX_DONE MSM_BOOT_UART_DM_CR_CH_CMD(11) +#define MSM_BOOT_UART_DM_CMD_RES_BRKSTRT_INT MSM_BOOT_UART_DM_CR_CH_CMD(12) +#define MSM_BOOT_UART_DM_CMD_RES_BRKEND_INT MSM_BOOT_UART_DM_CR_CH_CMD(13) +#define MSM_BOOT_UART_DM_CMD_RES_PER_FRM_INT MSM_BOOT_UART_DM_CR_CH_CMD(14) + +/*UART General Command */ +#define MSM_BOOT_UART_DM_CR_GENERAL_CMD(x) ((x) << 8) + +#define MSM_BOOT_UART_DM_GCMD_NULL MSM_BOOT_UART_DM_CR_GENERAL_CMD(0) +#define MSM_BOOT_UART_DM_GCMD_CR_PROT_EN MSM_BOOT_UART_DM_CR_GENERAL_CMD(1) +#define MSM_BOOT_UART_DM_GCMD_CR_PROT_DIS MSM_BOOT_UART_DM_CR_GENERAL_CMD(2) +#define MSM_BOOT_UART_DM_GCMD_RES_TX_RDY_INT MSM_BOOT_UART_DM_CR_GENERAL_CMD(3) +#define MSM_BOOT_UART_DM_GCMD_SW_FORCE_STALE MSM_BOOT_UART_DM_CR_GENERAL_CMD(4) +#define MSM_BOOT_UART_DM_GCMD_ENA_STALE_EVT MSM_BOOT_UART_DM_CR_GENERAL_CMD(5) +#define MSM_BOOT_UART_DM_GCMD_DIS_STALE_EVT MSM_BOOT_UART_DM_CR_GENERAL_CMD(6) + +/* UART Interrupt Mask Register */ +#if PERIPH_BLK_BLSP +#define MSM_BOOT_UART_DM_IMR(base) ((base) + 0xB0) +#else +#define MSM_BOOT_UART_DM_IMR(base) ((base) + 0x14) +#endif + +#define MSM_BOOT_UART_DM_TXLEV (1 << 0) +#define MSM_BOOT_UART_DM_RXHUNT (1 << 1) +#define MSM_BOOT_UART_DM_RXBRK_CHNG (1 << 2) +#define MSM_BOOT_UART_DM_RXSTALE (1 << 3) +#define MSM_BOOT_UART_DM_RXLEV (1 << 4) +#define MSM_BOOT_UART_DM_DELTA_CTS (1 << 5) +#define MSM_BOOT_UART_DM_CURRENT_CTS (1 << 6) +#define MSM_BOOT_UART_DM_TX_READY (1 << 7) +#define MSM_BOOT_UART_DM_TX_ERROR (1 << 8) +#define MSM_BOOT_UART_DM_TX_DONE (1 << 9) +#define MSM_BOOT_UART_DM_RXBREAK_START (1 << 10) +#define MSM_BOOT_UART_DM_RXBREAK_END (1 << 11) +#define MSM_BOOT_UART_DM_PAR_FRAME_ERR_IRQ (1 << 12) + +#define MSM_BOOT_UART_DM_IMR_ENABLED (MSM_BOOT_UART_DM_TX_READY | \ + MSM_BOOT_UART_DM_TXLEV | \ + MSM_BOOT_UART_DM_RXSTALE) + +/* UART Interrupt Programming Register */ +#define MSM_BOOT_UART_DM_IPR(base) ((base) + 0x18) +#define MSM_BOOT_UART_DM_STALE_TIMEOUT_LSB 0x0f +#define MSM_BOOT_UART_DM_STALE_TIMEOUT_MSB 0 /* Not used currently */ + +/* UART Transmit/Receive FIFO Watermark Register */ +#define MSM_BOOT_UART_DM_TFWR(base) ((base) + 0x1C) +/* Interrupt is generated when FIFO level is less than or equal to this value */ +#define MSM_BOOT_UART_DM_TFW_VALUE 0 + +#define MSM_BOOT_UART_DM_RFWR(base) ((base) + 0x20) +/*Interrupt generated when no of words in RX FIFO is greater than this value */ +#define MSM_BOOT_UART_DM_RFW_VALUE 0 + +/* UART Hunt Character Register */ +#define MSM_BOOT_UART_DM_HCR(base) ((base) + 0x24) + +/* Used for RX transfer initialization */ +#define MSM_BOOT_UART_DM_DMRX(base) ((base) + 0x34) + +/* Default DMRX value - any value bigger than FIFO size would be fine */ +#define MSM_BOOT_UART_DM_DMRX_DEF_VALUE 0x220 + +/* Register to enable IRDA function */ +#if PERIPH_BLK_BLSP +#define MSM_BOOT_UART_DM_IRDA(base) ((base) + 0xB8) +#else +#define MSM_BOOT_UART_DM_IRDA(base) ((base) + 0x38) +#endif + +/* UART Data Mover Enable Register */ +#define MSM_BOOT_UART_DM_DMEN(base) ((base) + 0x3C) + +/* Number of characters for Transmission */ +#define MSM_BOOT_UART_DM_NO_CHARS_FOR_TX(base) ((base) + 0x040) + +/* UART RX FIFO Base Address */ +#define MSM_BOOT_UART_DM_BADR(base) ((base) + 0x44) + +/* UART Status Register */ +#if PERIPH_BLK_BLSP +#define MSM_BOOT_UART_DM_SR(base) ((base) + 0x0A4) +#else +#define MSM_BOOT_UART_DM_SR(base) ((base) + 0x008) +#endif +#define MSM_BOOT_UART_DM_SR_RXRDY (1 << 0) +#define MSM_BOOT_UART_DM_SR_RXFULL (1 << 1) +#define MSM_BOOT_UART_DM_SR_TXRDY (1 << 2) +#define MSM_BOOT_UART_DM_SR_TXEMT (1 << 3) +#define MSM_BOOT_UART_DM_SR_UART_OVERRUN (1 << 4) +#define MSM_BOOT_UART_DM_SR_PAR_FRAME_ERR (1 << 5) +#define MSM_BOOT_UART_DM_RX_BREAK (1 << 6) +#define MSM_BOOT_UART_DM_HUNT_CHAR (1 << 7) +#define MSM_BOOT_UART_DM_RX_BRK_START_LAST (1 << 8) + +/* UART Receive FIFO Registers - 4 in numbers */ +#if PERIPH_BLK_BLSP +#define MSM_BOOT_UART_DM_RF(base, x) ((base) + 0x140 + (4*(x))) +#else +#define MSM_BOOT_UART_DM_RF(base, x) ((base) + 0x70 + (4*(x))) +#endif + +/* UART Masked Interrupt Status Register */ +#if PERIPH_BLK_BLSP +#define MSM_BOOT_UART_DM_MISR(base) ((base) + 0xAC) +#else +#define MSM_BOOT_UART_DM_MISR(base) ((base) + 0x10) +#endif + +/* UART Interrupt Status Register */ +#if PERIPH_BLK_BLSP +#define MSM_BOOT_UART_DM_ISR(base) ((base) + 0xB4) +#else +#define MSM_BOOT_UART_DM_ISR(base) ((base) + 0x14) +#endif + +/* Number of characters received since the end of last RX transfer */ +#if PERIPH_BLK_BLSP +#define MSM_BOOT_UART_DM_RX_TOTAL_SNAP(base) ((base) + 0xBC) +#else +#define MSM_BOOT_UART_DM_RX_TOTAL_SNAP(base) ((base) + 0x38) +#endif + +/* UART TX FIFO Status Register */ +#define MSM_BOOT_UART_DM_TXFS(base) ((base) + 0x4C) +#define MSM_BOOT_UART_DM_TXFS_STATE_LSB(x) MSM_BOOT_UART_DM_EXTR_BITS(x, 0, 6) +#define MSM_BOOT_UART_DM_TXFS_STATE_MSB(x) \ + MSM_BOOT_UART_DM_EXTR_BITS(x, 14, 31) +#define MSM_BOOT_UART_DM_TXFS_BUF_STATE(x) MSM_BOOT_UART_DM_EXTR_BITS(x, 7, 9) +#define MSM_BOOT_UART_DM_TXFS_ASYNC_STATE(x) \ + MSM_BOOT_UART_DM_EXTR_BITS(x, 10, 13) + +/* UART RX FIFO Status Register */ +#define MSM_BOOT_UART_DM_RXFS(base) ((base) + 0x50) +#define MSM_BOOT_UART_DM_RXFS_STATE_LSB(x) MSM_BOOT_UART_DM_EXTR_BITS(x, 0, 6) +#define MSM_BOOT_UART_DM_RXFS_STATE_MSB(x) \ + MSM_BOOT_UART_DM_EXTR_BITS(x, 14, 31) +#define MSM_BOOT_UART_DM_RXFS_BUF_STATE(x) MSM_BOOT_UART_DM_EXTR_BITS(x, 7, 9) +#define MSM_BOOT_UART_DM_RXFS_ASYNC_STATE(x) \ + MSM_BOOT_UART_DM_EXTR_BITS(x, 10, 13) + +/* Macros for Common Errors */ +#define MSM_BOOT_UART_DM_E_SUCCESS 0 +#define MSM_BOOT_UART_DM_E_FAILURE 1 +#define MSM_BOOT_UART_DM_E_TIMEOUT 2 +#define MSM_BOOT_UART_DM_E_INVAL 3 +#define MSM_BOOT_UART_DM_E_MALLOC_FAIL 4 +#define MSM_BOOT_UART_DM_E_RX_NOT_READY 5 + +void qcs405_uart_init(void); + +#endif /* __UART_DM_H__ */ diff --git a/src/soc/qualcomm/qcs405/uart.c b/src/soc/qualcomm/qcs405/uart.c new file mode 100644 index 0000000000..4a4331220a --- /dev/null +++ b/src/soc/qualcomm/qcs405/uart.c @@ -0,0 +1,303 @@ +/* + * Copyright (c) 2012-2019 The Linux Foundation. All rights reserved. + * Source : APQ8064 LK boot + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of The Linux Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define FIFO_DATA_SIZE 4 + +typedef struct { + void *uart_dm_base; + unsigned int blsp_uart; + gpio_func_data_t dbg_uart_gpio[NO_OF_DBG_UART_GPIOS]; +} uart_params_t; + +void ipq_configure_gpio(const gpio_func_data_t *gpio, unsigned int count) +{ + int i; + + for (i = 0; i < count; i++) { + gpio_configure(gpio->gpio, gpio->func, + gpio->pull, gpio->drvstr, gpio->enable); + gpio++; + } +} + +static const uart_params_t uart_board_param = { + .uart_dm_base = UART2_DM_BASE, + .blsp_uart = BLSP1_UART2, + .dbg_uart_gpio = { + { + .gpio = GPIO(17), + .func = 1, + .dir = GPIO_OUTPUT, + .pull = GPIO_PULL_UP, + .enable = GPIO_OUTPUT + }, + { + .gpio = GPIO(18), + .func = 1, + .dir = GPIO_INPUT, + .pull = GPIO_NO_PULL, + .enable = GPIO_INPUT + }, + }, +}; + +/** + * @brief msm_boot_uart_dm_init_rx_transfer - Init Rx transfer + * @param uart_dm_base: UART controller base address + */ +static unsigned int msm_boot_uart_dm_init_rx_transfer(void *uart_dm_base) +{ + /* Reset receiver */ + write32(MSM_BOOT_UART_DM_CR(uart_dm_base), + MSM_BOOT_UART_DM_CMD_RESET_RX); + + /* Enable receiver */ + write32(MSM_BOOT_UART_DM_CR(uart_dm_base), + MSM_BOOT_UART_DM_CR_RX_ENABLE); + write32(MSM_BOOT_UART_DM_DMRX(uart_dm_base), + MSM_BOOT_UART_DM_DMRX_DEF_VALUE); + + /* Clear stale event */ + write32(MSM_BOOT_UART_DM_CR(uart_dm_base), + MSM_BOOT_UART_DM_CMD_RES_STALE_INT); + + /* Enable stale event */ + write32(MSM_BOOT_UART_DM_CR(uart_dm_base), + MSM_BOOT_UART_DM_GCMD_ENA_STALE_EVT); + + return MSM_BOOT_UART_DM_E_SUCCESS; +} + +#if CONFIG(DRIVERS_UART) +static unsigned int msm_boot_uart_dm_init(void *uart_dm_base); + +/* Received data is valid or not */ +static int valid_data = 0; + +/* Received data */ +static unsigned int word = 0; + + +void uart_tx_byte(int idx, unsigned char data) +{ + int num_of_chars = 1; + void *base = uart_board_param.uart_dm_base; + + /* Wait until transmit FIFO is empty. */ + while (!(read32(MSM_BOOT_UART_DM_SR(base)) & + MSM_BOOT_UART_DM_SR_TXEMT)) + udelay(1); + /* + * TX FIFO is ready to accept new character(s). First write number of + * characters to be transmitted. + */ + write32(MSM_BOOT_UART_DM_NO_CHARS_FOR_TX(base), num_of_chars); + + /* And now write the character(s) */ + write32(MSM_BOOT_UART_DM_TF(base, 0), data); +} +#endif /* CONFIG_SERIAL_UART */ + +/** + * @brief msm_boot_uart_dm_reset - resets UART controller + * @param base: UART controller base address + */ +static unsigned int msm_boot_uart_dm_reset(void *base) +{ + write32(MSM_BOOT_UART_DM_CR(base), MSM_BOOT_UART_DM_CMD_RESET_RX); + write32(MSM_BOOT_UART_DM_CR(base), MSM_BOOT_UART_DM_CMD_RESET_TX); + write32(MSM_BOOT_UART_DM_CR(base), + MSM_BOOT_UART_DM_CMD_RESET_ERR_STAT); + write32(MSM_BOOT_UART_DM_CR(base), MSM_BOOT_UART_DM_CMD_RES_TX_ERR); + write32(MSM_BOOT_UART_DM_CR(base), MSM_BOOT_UART_DM_CMD_RES_STALE_INT); + + return MSM_BOOT_UART_DM_E_SUCCESS; +} + +/** + * @brief msm_boot_uart_dm_init - initilaizes UART controller + * @param uart_dm_base: UART controller base address + */ +unsigned int msm_boot_uart_dm_init(void *uart_dm_base) +{ + /* Configure UART mode registers MR1 and MR2 */ + /* Hardware flow control isn't supported */ + write32(MSM_BOOT_UART_DM_MR1(uart_dm_base), 0x0); + + /* 8-N-1 configuration: 8 data bits - No parity - 1 stop bit */ + write32(MSM_BOOT_UART_DM_MR2(uart_dm_base), + MSM_BOOT_UART_DM_8_N_1_MODE); + + /* Configure Interrupt Mask register IMR */ + write32(MSM_BOOT_UART_DM_IMR(uart_dm_base), + MSM_BOOT_UART_DM_IMR_ENABLED); + + /* + * Configure Tx and Rx watermarks configuration registers + * TX watermark value is set to 0 - interrupt is generated when + * FIFO level is less than or equal to 0 + */ + write32(MSM_BOOT_UART_DM_TFWR(uart_dm_base), + MSM_BOOT_UART_DM_TFW_VALUE); + + /* RX watermark value */ + write32(MSM_BOOT_UART_DM_RFWR(uart_dm_base), + MSM_BOOT_UART_DM_RFW_VALUE); + + /* Configure Interrupt Programming Register */ + /* Set initial Stale timeout value */ + write32(MSM_BOOT_UART_DM_IPR(uart_dm_base), + MSM_BOOT_UART_DM_STALE_TIMEOUT_LSB); + + /* Configure IRDA if required */ + /* Disabling IRDA mode */ + write32(MSM_BOOT_UART_DM_IRDA(uart_dm_base), 0x0); + + /* Configure hunt character value in HCR register */ + /* Keep it in reset state */ + write32(MSM_BOOT_UART_DM_HCR(uart_dm_base), 0x0); + + /* + * Configure Rx FIFO base address + * Both TX/RX shares same SRAM and default is half-n-half. + * Sticking with default value now. + * As such RAM size is (2^RAM_ADDR_WIDTH, 32-bit entries). + * We have found RAM_ADDR_WIDTH = 0x7f + */ + + /* Issue soft reset command */ + msm_boot_uart_dm_reset(uart_dm_base); + + /* Enable/Disable Rx/Tx DM interfaces */ + /* Data Mover not currently utilized. */ + write32(MSM_BOOT_UART_DM_DMEN(uart_dm_base), 0x0); + + /* Enable transmitter */ + write32(MSM_BOOT_UART_DM_CR(uart_dm_base), + MSM_BOOT_UART_DM_CR_TX_ENABLE); + + /* Initialize Receive Path */ + msm_boot_uart_dm_init_rx_transfer(uart_dm_base); + + return 0; +} + +/** + * @brief qcs405_uart_init - initializes UART + * + * Initializes clocks, GPIO and UART controller. + */ +void uart_init(int idx) +{ + /* Note int idx isn't used in this driver. */ + void *dm_base; + + dm_base = uart_board_param.uart_dm_base; + + if (read32(MSM_BOOT_UART_DM_CSR(dm_base)) == 0xFF) + return; /* UART must have been already initialized. */ + + clock_configure_uart(1843200); + clock_enable_uart(); + + ipq_configure_gpio(uart_board_param.dbg_uart_gpio, + NO_OF_DBG_UART_GPIOS); + + write32(MSM_BOOT_UART_DM_CSR(dm_base), 0xFF); + + /* Initialize UART_DM */ + msm_boot_uart_dm_init(dm_base); +} + +/* for the benefit of non-console uart init */ +void qcs405_uart_init(void) +{ + uart_init(0); +} + +/** + * @brief uart_tx_flush - transmits a string of data + * @param idx: string to transmit + */ +void uart_tx_flush(int idx) +{ + void *base = uart_board_param.uart_dm_base; + + while (!(read32(MSM_BOOT_UART_DM_SR(base)) & + MSM_BOOT_UART_DM_SR_TXEMT)) + ; +} + +#if CONFIG(DRIVERS_UART) +/** + * qcs405_serial_getc - reads a character + * + * Returns the character read from serial port. + */ +uint8_t uart_rx_byte(int idx) +{ + uint8_t byte; + + byte = (uint8_t)(word & 0xff); + word = word >> 8; + valid_data--; + + return byte; +} +#endif + +#ifndef __PRE_RAM__ +void uart_fill_lb(void *data) +{ + struct lb_serial serial; + + serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED; + serial.baseaddr = (uint64_t)UART2_DM_BASE; + serial.baud = get_uart_baudrate(); + serial.regwidth = 1; + + lb_add_serial(&serial, data); + lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data); +} +#endif From 13539d2f9d671099764f12e45b8e6d4e41c8e4af Mon Sep 17 00:00:00 2001 From: Prudhvi Yarlagadda Date: Thu, 14 Mar 2019 11:01:12 +0530 Subject: [PATCH 321/331] qcs405: Add SPI driver support Add SPI driver support in coreboot. Change-Id: I813ba0b5cc8344c463c3e41ff6db80bc0d8ebd96 Signed-off-by: Prudhvi Yarlagadda Signed-off-by: Nitheesh Sekar Reviewed-on: https://review.coreboot.org/c/coreboot/+/32058 Reviewed-by: Patrick Georgi Tested-by: build bot (Jenkins) --- src/soc/qualcomm/qcs405/Kconfig | 9 + src/soc/qualcomm/qcs405/include/soc/qup.h | 232 +++++++ src/soc/qualcomm/qcs405/include/soc/spi.h | 210 ++++++ src/soc/qualcomm/qcs405/spi.c | 768 +++++++++++++++++++++- 4 files changed, 1202 insertions(+), 17 deletions(-) create mode 100644 src/soc/qualcomm/qcs405/include/soc/qup.h create mode 100644 src/soc/qualcomm/qcs405/include/soc/spi.h diff --git a/src/soc/qualcomm/qcs405/Kconfig b/src/soc/qualcomm/qcs405/Kconfig index 6bbdd3bf34..aa867c2f25 100644 --- a/src/soc/qualcomm/qcs405/Kconfig +++ b/src/soc/qualcomm/qcs405/Kconfig @@ -19,4 +19,13 @@ config VBOOT select VBOOT_SEPARATE_VERSTAGE select VBOOT_RETURN_FROM_VERSTAGE select VBOOT_STARTS_IN_BOOTBLOCK + +config QCS405_BLSP_SPI + bool + default y + prompt "Build Flash Using SPI-NOR" + +config BOOT_DEVICE_SPI_FLASH_BUS + int + default 5 endif diff --git a/src/soc/qualcomm/qcs405/include/soc/qup.h b/src/soc/qualcomm/qcs405/include/soc/qup.h new file mode 100644 index 0000000000..f8f9c75972 --- /dev/null +++ b/src/soc/qualcomm/qcs405/include/soc/qup.h @@ -0,0 +1,232 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 - 2019 The Linux Foundation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of The Linux Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __QUP_H__ +#define __QUP_H__ + + +/* QUP block registers */ +#define QUP_CONFIG 0x000 +#define QUP_STATE 0x004 +#define QUP_IO_MODES 0x008 +#define QUP_SW_RESET 0x00C +#define QUP_TRANSFER_CANCEL 0x014 +#define QUP_OPERATIONAL 0x018 +#define QUP_ERROR_FLAGS 0x01C +#define QUP_ERROR_FLAGS_EN 0x020 +#define QUP_TEST_CTRL 0x024 +#define QUP_OPERATIONAL_MASK 0x028 +#define QUP_HW_VERSION 0x030 +#define QUP_MX_OUTPUT_COUNT 0x100 +#define QUP_MX_OUTPUT_CNT_CURRENT 0x104 +#define QUP_OUTPUT_DEBUG 0x108 +#define QUP_OUTPUT_FIFO_WORD_CNT 0x10C +#define QUP_OUTPUT_FIFO 0x110 +#define QUP_OUTPUT_FIFO_SIZE 64 /* bytes */ +#define QUP_MX_WRITE_COUNT 0x150 +#define QUP_MX_WRITE_CNT_CURRENT 0x154 +#define QUP_MX_INPUT_COUNT 0x200 +#define QUP_MX_INPUT_CNT_CURRENT 0x204 +#define QUP_MX_READ_COUNT 0x208 +#define QUP_MX_READ_CNT_CURRENT 0x20C +#define QUP_INPUT_DEBUG 0x210 +#define QUP_INPUT_FIFO_WORD_CNT 0x214 +#define QUP_INPUT_FIFO 0x218 +#define QUP_INPUT_FIFO_SIZE 64 /* bytes */ +#define QUP_I2C_MASTER_CLK_CTL 0x400 +#define QUP_I2C_MASTER_STATUS 0x404 +#define QUP_I2C_MASTER_CONFIG 0x408 +#define QUP_I2C_MASTER_BUS_CLEAR 0x40C +#define QUP_I2C_MASTER_LOCAL_ID 0x410 +#define QUP_I2C_MASTER_COMMAND 0x414 + +#define OUTPUT_FIFO_FULL (1<<6) +#define INPUT_FIFO_NOT_EMPTY (1<<5) +#define OUTPUT_FIFO_NOT_EMPTY (1<<4) +#define MAX_OUTPUT_DONE_FLAG (1<<10) +#define MAX_INPUT_DONE_FLAG (1<<11) +#define INPUT_SERVICE_FLAG (1<<9) +#define OUTPUT_SERVICE_FLAG (1<<8) +#define QUP_UNPACK_EN (1<<14) +#define QUP_PACK_EN (1<<15) +#define QUP_OUTPUT_BIT_SHIFT_EN (1<<16) + +#define QUP_MODE_MASK (0x03) +#define QUP_OUTPUT_MODE_SHFT (10) +#define QUP_INPUT_MODE_SHFT (12) + +#define QUP_FS_DIVIDER_MASK (0xFF) + +#define QUP_APP_CLK_ON_EN (1 << 12) +#define QUP_CORE_CLK_ON_EN (1 << 13) +#define QUP_MINI_CORE_PROTO_SHFT (8) +#define QUP_MINI_CORE_PROTO_MASK (0x0F) + +/* Mini-core states */ +#define QUP_STATE_RESET 0x0 +#define QUP_STATE_RUN 0x1 +#define QUP_STATE_PAUSE 0x3 +#define QUP_STATE_VALID (1<<2) +#define QUP_STATE_MASK 0x3 +#define QUP_STATE_VALID_MASK (1<<2) + +/* Tags for output FIFO */ +#define QUP_I2C_1CLK_NOOP_SEQ 0x1 /*MSB 8-bit NOP, LSB 8-bits 1 clk.*/ +#define QUP_I2C_START_SEQ (0x1 << 8) +#define QUP_I2C_DATA_SEQ (0x2 << 8) +#define QUP_I2C_STOP_SEQ (0x3 << 8) +#define QUP_I2C_RECV_SEQ (0x4 << 8) + +/* Tags for input FIFO */ +#define QUP_I2C_MIDATA_SEQ (0x5 << 8) +#define QUP_I2C_MISTOP_SEQ (0x6 << 8) +#define QUP_I2C_MINACK_SEQ (0x7 << 8) + +#define QUP_I2C_ADDR(x) ((x & 0xFF) << 1) +#define QUP_I2C_DATA(x) (x & 0xFF) +#define QUP_I2C_MI_TAG(x) (x & 0xFF00) +#define QUP_I2C_SLAVE_READ (0x1) + +/*Bit vals for I2C_MASTER_CLK_CTL register */ +#define QUP_HS_DIVIDER_SHFT (8) +#define QUP_DIVIDER_MIN_VAL (0x3) + +/* Bit masks for I2C_MASTER_STATUS register */ +#define QUP_I2C_INVALID_READ_SEQ (1 << 25) +#define QUP_I2C_INVALID_READ_ADDR (1 << 24) +#define QUP_I2C_INVALID_TAG (1 << 23) +#define QUP_I2C_FAILED_MASK (0x3 << 6) +#define QUP_I2C_INVALID_WRITE (1 << 5) +#define QUP_I2C_ARB_LOST (1 << 4) +#define QUP_I2C_PACKET_NACK (1 << 3) +#define QUP_I2C_BUS_ERROR (1 << 2) + +typedef enum { + QUP_SUCCESS = 0, + QUP_ERR_BAD_PARAM, + QUP_ERR_STATE_SET, + QUP_ERR_TIMEOUT, + QUP_ERR_UNSUPPORTED, + QUP_ERR_I2C_FAILED, + QUP_ERR_I2C_ARB_LOST, + QUP_ERR_I2C_BUS_ERROR, + QUP_ERR_I2C_INVALID_SLAVE_ADDR, + QUP_ERR_XFER_FAIL, + QUP_ERR_I2C_NACK, + QUP_ERR_I2C_INVALID_WRITE, + QUP_ERR_I2C_INVALID_TAG, + QUP_ERR_UNDEFINED, +} qup_return_t; + +typedef enum { + QUP_MINICORE_SPI = 1, + QUP_MINICORE_I2C_MASTER, + QUP_MINICORE_I2C_SLAVE +} qup_protocol_t; + +typedef enum { + QUP_MODE_FIFO = 0, + QUP_MODE_BLOCK, + QUP_MODE_DATAMOVER, +} qup_mode_t; + +typedef struct { + qup_protocol_t protocol; + unsigned int clk_frequency; + unsigned int src_frequency; + qup_mode_t mode; + unsigned int initialized; +} qup_config_t; + +typedef struct { + qup_protocol_t protocol; + union { + struct { + uint8_t addr; + uint8_t *data; + unsigned int data_len; + } iic; + struct { + void *in; + void *out; + unsigned int size; + } spi; + } p; +} qup_data_t; + +/* + * Initialize BLSP QUP block for FIFO I2C transfers. + * id[IN]: BLSP for which QUP is to be initialized. + * config_ptr[IN]: configurations parameters for the QUP. + * + * return: QUP_SUCCESS, if initialization succeeds. + */ +qup_return_t qup_init(blsp_qup_id_t id, const qup_config_t *config_ptr); + +/* + * Set QUP state to run, pause, reset. + * id[IN]: BLSP block for which QUP state is to be set. + * state[IN]: New state to transition to. + * + * return: QUP_SUCCESS, if state transition succeeds. + */ +qup_return_t qup_set_state(blsp_qup_id_t id, uint32_t state); + +/* + * Reset the status bits set during an i2c transfer. + * id[IN]: BLSP block for which i2c status bits are to be cleared. + * + * return: QUP_SUCCESS, if status bits are cleared successfully. + */ +qup_return_t qup_reset_i2c_master_status(blsp_qup_id_t id); + +/* + * Send data to the peripheral on the bus. + * id[IN]: BLSP block for which data is to be sent. + * p_tx_obj[IN]: Data to be sent to the slave on the bus. + * stop_seq[IN]: When set to non-zero QUP engine sends i2c stop sequnce. + * + * return: QUP_SUCCESS, when data is sent successfully to the peripheral. + */ +qup_return_t qup_send_data(blsp_qup_id_t id, qup_data_t *p_tx_obj, + uint8_t stop_seq); + +/* + * Receive data from peripheral on the bus. + * id[IN]: BLSP block from which data is to be received. + * p_tx_obj[IN]: length of data to be received, slave address. + * [OUT]: buffer filled with data from slave. + * + * return: QUP_SUCCESS, when data is received successfully. + */ +qup_return_t qup_recv_data(blsp_qup_id_t id, qup_data_t *p_tx_obj); + +#endif //__QUP_H__ diff --git a/src/soc/qualcomm/qcs405/include/soc/spi.h b/src/soc/qualcomm/qcs405/include/soc/spi.h new file mode 100644 index 0000000000..12f7fd97c7 --- /dev/null +++ b/src/soc/qualcomm/qcs405/include/soc/spi.h @@ -0,0 +1,210 @@ +/* + * Register definitions for the IPQ BLSP SPI Controller + * + * Copyright (c) 2012-2019 The Linux Foundation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of The Linux Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _QCS405_SPI_H_ +#define _QCS405_SPI_H_ + +#include +#include +#include + +#define BLSP0_QUP_REG_BASE ((void *)0x78b5000u) +#define BLSP4_QUP_REG_BASE ((void *)0x78b9000u) +#define BLSP5_QUP_REG_BASE ((void *)0x7af5000u) + +#define BLSP0_SPI_CONFIG_REG (BLSP0_QUP_REG_BASE + 0x00000300) +#define BLSP4_SPI_CONFIG_REG (BLSP4_QUP_REG_BASE + 0x00000300) +#define BLSP5_SPI_CONFIG_REG (BLSP5_QUP_REG_BASE + 0x00000300) + +#define BLSP0_SPI_IO_CONTROL_REG (BLSP0_QUP_REG_BASE + 0x00000304) +#define BLSP4_SPI_IO_CONTROL_REG (BLSP4_QUP_REG_BASE + 0x00000304) +#define BLSP5_SPI_IO_CONTROL_REG (BLSP5_QUP_REG_BASE + 0x00000304) + +#define BLSP0_SPI_ERROR_FLAGS_REG (BLSP0_QUP_REG_BASE + 0x00000308) +#define BLSP4_SPI_ERROR_FLAGS_REG (BLSP4_QUP_REG_BASE + 0x00000308) +#define BLSP5_SPI_ERROR_FLAGS_REG (BLSP5_QUP_REG_BASE + 0x00000308) + +#define BLSP0_SPI_DEASSERT_WAIT_REG (BLSP0_QUP_REG_BASE + 0x00000310) +#define BLSP4_SPI_DEASSERT_WAIT_REG (BLSP4_QUP_REG_BASE + 0x00000310) +#define BLSP5_SPI_DEASSERT_WAIT_REG (BLSP5_QUP_REG_BASE + 0x00000310) +#define BLSP0_SPI_ERROR_FLAGS_EN_REG (BLSP0_QUP_REG_BASE + 0x0000030c) +#define BLSP4_SPI_ERROR_FLAGS_EN_REG (BLSP4_QUP_REG_BASE + 0x0000030c) +#define BLSP5_SPI_ERROR_FLAGS_EN_REG (BLSP5_QUP_REG_BASE + 0x0000030c) + +#define BLSP0_QUP_CONFIG_REG (BLSP0_QUP_REG_BASE + 0x00000000) +#define BLSP4_QUP_CONFIG_REG (BLSP4_QUP_REG_BASE + 0x00000000) +#define BLSP5_QUP_CONFIG_REG (BLSP5_QUP_REG_BASE + 0x00000000) + +#define BLSP0_QUP_ERROR_FLAGS_REG (BLSP0_QUP_REG_BASE + 0x0000001c) +#define BLSP4_QUP_ERROR_FLAGS_REG (BLSP4_QUP_REG_BASE + 0x0000001c) +#define BLSP5_QUP_ERROR_FLAGS_REG (BLSP5_QUP_REG_BASE + 0x0000001c) + +#define BLSP0_QUP_ERROR_FLAGS_EN_REG (BLSP0_QUP_REG_BASE + 0x00000020) +#define BLSP4_QUP_ERROR_FLAGS_EN_REG (BLSP4_QUP_REG_BASE + 0x00000020) +#define BLSP5_QUP_ERROR_FLAGS_EN_REG (BLSP5_QUP_REG_BASE + 0x00000020) + +#define BLSP0_QUP_OPERATIONAL_MASK (BLSP0_QUP_REG_BASE + 0x00000028) +#define BLSP4_QUP_OPERATIONAL_MASK (BLSP4_QUP_REG_BASE + 0x00000028) +#define BLSP5_QUP_OPERATIONAL_MASK (BLSP5_QUP_REG_BASE + 0x00000028) + +#define BLSP0_QUP_OPERATIONAL_REG (BLSP0_QUP_REG_BASE + 0x00000018) +#define BLSP4_QUP_OPERATIONAL_REG (BLSP4_QUP_REG_BASE + 0x00000018) +#define BLSP5_QUP_OPERATIONAL_REG (BLSP5_QUP_REG_BASE + 0x00000018) + +#define BLSP0_QUP_IO_MODES_REG (BLSP0_QUP_REG_BASE + 0x00000008) +#define BLSP4_QUP_IO_MODES_REG (BLSP4_QUP_REG_BASE + 0x00000008) +#define BLSP5_QUP_IO_MODES_REG (BLSP5_QUP_REG_BASE + 0x00000008) + +#define BLSP0_QUP_STATE_REG (BLSP0_QUP_REG_BASE + 0x00000004) +#define BLSP4_QUP_STATE_REG (BLSP4_QUP_REG_BASE + 0x00000004) +#define BLSP5_QUP_STATE_REG (BLSP5_QUP_REG_BASE + 0x00000004) + +#define BLSP0_QUP_INPUT_FIFOc_REG(c) \ + (BLSP0_QUP_REG_BASE + 0x00000218 + 4 * (c)) +#define BLSP4_QUP_INPUT_FIFOc_REG(c) \ + (BLSP4_QUP_REG_BASE + 0x00000218 + 4 * (c)) +#define BLSP5_QUP_INPUT_FIFOc_REG(c) \ + (BLSP5_QUP_REG_BASE + 0x00000218 + 4 * (c)) + +#define BLSP0_QUP_OUTPUT_FIFOc_REG(c) \ + (BLSP0_QUP_REG_BASE + 0x00000110 + 4 * (c)) +#define BLSP4_QUP_OUTPUT_FIFOc_REG(c) \ + (BLSP4_QUP_REG_BASE + 0x00000110 + 4 * (c)) +#define BLSP5_QUP_OUTPUT_FIFOc_REG(c) \ + (BLSP5_QUP_REG_BASE + 0x00000110 + 4 * (c)) + +#define BLSP0_QUP_MX_INPUT_COUNT_REG (BLSP0_QUP_REG_BASE + 0x00000200) +#define BLSP4_QUP_MX_INPUT_COUNT_REG (BLSP4_QUP_REG_BASE + 0x00000200) +#define BLSP5_QUP_MX_INPUT_COUNT_REG (BLSP5_QUP_REG_BASE + 0x00000200) + +#define BLSP0_QUP_MX_OUTPUT_COUNT_REG (BLSP0_QUP_REG_BASE + 0x00000100) +#define BLSP4_QUP_MX_OUTPUT_COUNT_REG (BLSP4_QUP_REG_BASE + 0x00000100) +#define BLSP5_QUP_MX_OUTPUT_COUNT_REG (BLSP5_QUP_REG_BASE + 0x00000100) + +#define BLSP0_QUP_SW_RESET_REG (BLSP0_QUP_REG_BASE + 0x0000000c) +#define BLSP4_QUP_SW_RESET_REG (BLSP4_QUP_REG_BASE + 0x0000000c) +#define BLSP5_QUP_SW_RESET_REG (BLSP5_QUP_REG_BASE + 0x0000000c) + +#define QUP_CONFIG_MINI_CORE_MSK (0x0F << 8) +#define QUP_CONFIG_MINI_CORE_SPI (1 << 8) +#define QUP_CONF_INPUT_MSK (1 << 7) +#define QUP_CONF_INPUT_ENA (0 << 7) +#define QUP_CONF_NO_INPUT (1 << 7) +#define QUP_CONF_OUTPUT_MSK (1 << 6) +#define QUP_CONF_OUTPUT_ENA (0 << 6) +#define QUP_CONF_NO_OUTPUT (1 << 6) +#define QUP_CONF_N_MASK 0x1F +#define QUP_CONF_N_SPI_8_BIT_WORD 0x07 + +#define SPI_CONFIG_INPUT_FIRST (1 << 9) +#define SPI_CONFIG_INPUT_FIRST_BACK (0 << 9) +#define SPI_CONFIG_LOOP_BACK_MSK (1 << 8) +#define SPI_CONFIG_NO_LOOP_BACK (0 << 8) +#define SPI_CONFIG_NO_SLAVE_OPER_MSK (1 << 5) +#define SPI_CONFIG_NO_SLAVE_OPER (0 << 5) + +#define SPI_IO_CTRL_CLK_ALWAYS_ON (0 << 9) +#define SPI_IO_CTRL_MX_CS_MODE (1 << 8) +#define SPI_IO_CTRL_NO_TRI_STATE (1 << 0) +#define SPI_IO_CTRL_FORCE_CS_MSK (1 << 11) +#define SPI_IO_CTRL_FORCE_CS_EN (1 << 11) +#define SPI_IO_CTRL_FORCE_CS_DIS (0 << 11) +#define SPI_IO_CTRL_CLOCK_IDLE_HIGH (1 << 10) + +#define QUP_IO_MODES_OUTPUT_BIT_SHIFT_MSK (1 << 16) +#define QUP_IO_MODES_OUTPUT_BIT_SHIFT_EN (1 << 16) +#define QUP_IO_MODES_INPUT_MODE_MSK (0x03 << 12) +#define QUP_IO_MODES_INPUT_BLOCK_MODE (0x01 << 12) +#define QUP_IO_MODES_OUTPUT_MODE_MSK (0x03 << 10) +#define QUP_IO_MODES_OUTPUT_BLOCK_MODE (0x01 << 10) + +#define SPI_INPUT_BLOCK_SIZE 4 +#define SPI_OUTPUT_BLOCK_SIZE 4 + +#define MAX_COUNT_SIZE 0xffff + +#define SPI_CORE_RESET 0 +#define SPI_CORE_RUNNING 1 +#define SPI_MODE0 0 +#define SPI_MODE1 1 +#define SPI_MODE2 2 +#define SPI_MODE3 3 +#define BLSP0_SPI 0 +#define BLSP4_SPI 4 +#define BLSP5_SPI 5 + +struct blsp_spi { + void *spi_config; + void *io_control; + void *error_flags; + void *error_flags_en; + void *qup_config; + void *qup_error_flags; + void *qup_error_flags_en; + void *qup_operational; + void *qup_io_modes; + void *qup_state; + void *qup_input_fifo; + void *qup_output_fifo; + void *qup_mx_input_count; + void *qup_mx_output_count; + void *qup_sw_reset; + void *qup_ns_reg; + void *qup_md_reg; + void *qup_op_mask; + void *qup_deassert_wait; +}; + + +#define SUCCESS 0 + +#define DUMMY_DATA_VAL 0 +#define TIMEOUT_CNT 100 + +#define ETIMEDOUT -10 +#define EINVAL -11 +#define EIO -12 + +/* MX_INPUT_COUNT and MX_OUTPUT_COUNT are 16-bits. Zero has a special meaning + * (count function disabled) and does not hold significance in the count. */ +#define MAX_PACKET_COUNT ((64 * KiB) - 1) + + +struct qcs_spi_slave { + struct spi_slave slave; + const struct blsp_spi *regs; + unsigned int mode; + unsigned int initialized; + unsigned long freq; + int allocated; +}; + +#endif diff --git a/src/soc/qualcomm/qcs405/spi.c b/src/soc/qualcomm/qcs405/spi.c index c04b15d3c8..13b9daef9d 100644 --- a/src/soc/qualcomm/qcs405/spi.c +++ b/src/soc/qualcomm/qcs405/spi.c @@ -1,49 +1,783 @@ /* - * This file is part of the coreboot project. + * Copyright (c) 2012-2019 The Linux Foundation. All rights reserved. * - * Copyright (C) 2018, The Linux Foundation. All rights reserved. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of The Linux Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -#include +#include +#include +#include +#include +#include +#include +#include +#include +#include #include +#include + +static const struct blsp_spi spi_reg[] = { + /* BLSP0 registers for SPI interface */ + { + BLSP0_SPI_CONFIG_REG, + BLSP0_SPI_IO_CONTROL_REG, + BLSP0_SPI_ERROR_FLAGS_REG, + BLSP0_SPI_ERROR_FLAGS_EN_REG, + BLSP0_QUP_CONFIG_REG, + BLSP0_QUP_ERROR_FLAGS_REG, + BLSP0_QUP_ERROR_FLAGS_EN_REG, + BLSP0_QUP_OPERATIONAL_REG, + BLSP0_QUP_IO_MODES_REG, + BLSP0_QUP_STATE_REG, + BLSP0_QUP_INPUT_FIFOc_REG(0), + BLSP0_QUP_OUTPUT_FIFOc_REG(0), + BLSP0_QUP_MX_INPUT_COUNT_REG, + BLSP0_QUP_MX_OUTPUT_COUNT_REG, + BLSP0_QUP_SW_RESET_REG, + 0, + 0, + BLSP0_QUP_OPERATIONAL_MASK, + BLSP0_SPI_DEASSERT_WAIT_REG, + }, + {0}, {0}, {0}, + /* BLSP4 registers for SPI interface */ + { + BLSP4_SPI_CONFIG_REG, + BLSP4_SPI_IO_CONTROL_REG, + BLSP4_SPI_ERROR_FLAGS_REG, + BLSP4_SPI_ERROR_FLAGS_EN_REG, + BLSP4_QUP_CONFIG_REG, + BLSP4_QUP_ERROR_FLAGS_REG, + BLSP4_QUP_ERROR_FLAGS_EN_REG, + BLSP4_QUP_OPERATIONAL_REG, + BLSP4_QUP_IO_MODES_REG, + BLSP4_QUP_STATE_REG, + BLSP4_QUP_INPUT_FIFOc_REG(0), + BLSP4_QUP_OUTPUT_FIFOc_REG(0), + BLSP4_QUP_MX_INPUT_COUNT_REG, + BLSP4_QUP_MX_OUTPUT_COUNT_REG, + BLSP4_QUP_SW_RESET_REG, + 0, + 0, + BLSP4_QUP_OPERATIONAL_MASK, + BLSP4_SPI_DEASSERT_WAIT_REG, + }, + /* BLSP5 registers for SPI interface */ + { + BLSP5_SPI_CONFIG_REG, + BLSP5_SPI_IO_CONTROL_REG, + BLSP5_SPI_ERROR_FLAGS_REG, + BLSP5_SPI_ERROR_FLAGS_EN_REG, + BLSP5_QUP_CONFIG_REG, + BLSP5_QUP_ERROR_FLAGS_REG, + BLSP5_QUP_ERROR_FLAGS_EN_REG, + BLSP5_QUP_OPERATIONAL_REG, + BLSP5_QUP_IO_MODES_REG, + BLSP5_QUP_STATE_REG, + BLSP5_QUP_INPUT_FIFOc_REG(0), + BLSP5_QUP_OUTPUT_FIFOc_REG(0), + BLSP5_QUP_MX_INPUT_COUNT_REG, + BLSP5_QUP_MX_OUTPUT_COUNT_REG, + BLSP5_QUP_SW_RESET_REG, + 0, + 0, + BLSP5_QUP_OPERATIONAL_MASK, + BLSP5_SPI_DEASSERT_WAIT_REG, + }, +}; + +static int check_bit_state(void *reg_addr, int mask, + int val, int us_delay) +{ + unsigned int count = TIMEOUT_CNT; + + while ((read32(reg_addr) & mask) != val) { + count--; + if (count == 0) + return -ETIMEDOUT; + udelay(us_delay); + } + + return SUCCESS; +} + +/* + * Check whether QUPn State is valid + */ +static int check_qup_state_valid(struct qcs_spi_slave *ds) +{ + return check_bit_state(ds->regs->qup_state, QUP_STATE_VALID_MASK, + QUP_STATE_VALID, 1); +} + +/* + * Configure QUPn Core state + */ +static int config_spi_state(struct qcs_spi_slave *ds, unsigned int state) +{ + uint32_t val; + int ret = SUCCESS; + + ret = check_qup_state_valid(ds); + if (ret != SUCCESS) + return ret; + + switch (state) { + case QUP_STATE_RUN: + /* Set the state to RUN */ + val = ((read32(ds->regs->qup_state) & ~QUP_STATE_MASK) + | QUP_STATE_RUN); + write32(ds->regs->qup_state, val); + ret = check_qup_state_valid(ds); + break; + case QUP_STATE_RESET: + /* Set the state to RESET */ + val = ((read32(ds->regs->qup_state) & ~QUP_STATE_MASK) + | QUP_STATE_RESET); + write32(ds->regs->qup_state, val); + ret = check_qup_state_valid(ds); + break; + default: + printk(BIOS_ERR, "unsupported QUP SPI state : %d\n", state); + ret = -EINVAL; + break; + } + + return ret; +} + +/* + * Set QUPn SPI Mode + */ +static void spi_set_mode(struct qcs_spi_slave *ds, unsigned int mode) +{ + unsigned int clk_idle_state; + unsigned int input_first_mode; + uint32_t val; + + switch (mode) { + case SPI_MODE0: + clk_idle_state = 0; + input_first_mode = SPI_CONFIG_INPUT_FIRST; + break; + case SPI_MODE1: + clk_idle_state = 0; + input_first_mode = 0; + break; + case SPI_MODE2: + clk_idle_state = 1; + input_first_mode = SPI_CONFIG_INPUT_FIRST; + break; + case SPI_MODE3: + clk_idle_state = 1; + input_first_mode = 0; + break; + default: + printk(BIOS_ERR, "unsupported spi mode : %d\n", mode); + return; + } + + val = read32(ds->regs->spi_config); + val |= input_first_mode; + write32(ds->regs->spi_config, val); + val = read32(ds->regs->io_control); + + if (clk_idle_state) + val |= SPI_IO_CTRL_CLOCK_IDLE_HIGH; + else + val &= ~SPI_IO_CTRL_CLOCK_IDLE_HIGH; + + write32(ds->regs->io_control, val); +} + +/* + * Reset entire QUP and all mini cores + */ +static void spi_reset(struct qcs_spi_slave *ds) +{ + write32(ds->regs->qup_sw_reset, 0x1); + udelay(5); + check_qup_state_valid(ds); +} + +static struct qcs_spi_slave spi_slave_pool[3]; + +static struct qcs_spi_slave *to_qcs_spi(const struct spi_slave *slave) +{ + struct qcs_spi_slave *ds; + size_t i; + + for (i = 0; i < ARRAY_SIZE(spi_slave_pool); i++) { + ds = spi_slave_pool + i; + + if (!ds->allocated) + continue; + + if ((ds->slave.bus == slave->bus) && + (ds->slave.cs == slave->cs)) + return ds; + } + + return NULL; +} + +static void write_force_cs(const struct spi_slave *slave, int assert) +{ + struct qcs_spi_slave *ds = to_qcs_spi(slave); + if (assert) + clrsetbits_le32(ds->regs->io_control, + SPI_IO_CTRL_FORCE_CS_MSK, SPI_IO_CTRL_FORCE_CS_EN); + else + clrsetbits_le32(ds->regs->io_control, + SPI_IO_CTRL_FORCE_CS_MSK, SPI_IO_CTRL_FORCE_CS_DIS); +} + +/* + * BLSP QUPn SPI Hardware Initialisation + */ +static int spi_hw_init(struct qcs_spi_slave *ds) +{ + int ret; + + ds->initialized = 0; + + /* QUPn module configuration */ + spi_reset(ds); + + /* Set the QUPn state */ + ret = config_spi_state(ds, QUP_STATE_RESET); + if (ret) + return ret; + + /* + * Configure Mini core to SPI core with Input Output enabled, + * SPI master, N = 8 bits + */ + clrsetbits_le32(ds->regs->qup_config, QUP_CONFIG_MINI_CORE_MSK | + QUP_CONF_INPUT_MSK | + QUP_CONF_OUTPUT_MSK | + QUP_CONF_N_MASK, + QUP_CONFIG_MINI_CORE_SPI | + QUP_CONF_INPUT_ENA | + QUP_CONF_OUTPUT_ENA | + QUP_CONF_N_SPI_8_BIT_WORD); + + /* + * Configure Input first SPI protocol, + * SPI master mode and no loopback + */ + clrsetbits_le32(ds->regs->spi_config, SPI_CONFIG_LOOP_BACK_MSK | + SPI_CONFIG_NO_SLAVE_OPER_MSK, + SPI_CONFIG_NO_LOOP_BACK | + SPI_CONFIG_NO_SLAVE_OPER); + + /* + * Configure SPI IO Control Register + * CLK_ALWAYS_ON = 0 + * MX_CS_MODE = 0 + * NO_TRI_STATE = 1 + */ + write32(ds->regs->io_control, SPI_IO_CTRL_CLK_ALWAYS_ON | + SPI_IO_CTRL_NO_TRI_STATE | SPI_IO_CTRL_MX_CS_MODE); + + /* + * Configure SPI IO Modes. + * OUTPUT_BIT_SHIFT_EN = 1 + * INPUT_MODE = Block Mode + * OUTPUT MODE = Block Mode + */ + clrsetbits_le32(ds->regs->qup_io_modes, + QUP_IO_MODES_OUTPUT_BIT_SHIFT_MSK | + QUP_IO_MODES_INPUT_MODE_MSK | + QUP_IO_MODES_OUTPUT_MODE_MSK, + QUP_IO_MODES_OUTPUT_BIT_SHIFT_EN | + QUP_IO_MODES_INPUT_BLOCK_MODE | + QUP_IO_MODES_OUTPUT_BLOCK_MODE); + + spi_set_mode(ds, ds->mode); + + /* Disable Error mask */ + write32(ds->regs->error_flags_en, 0); + write32(ds->regs->qup_error_flags_en, 0); + write32(ds->regs->qup_deassert_wait, 0); + + ds->initialized = 1; + + return SUCCESS; +} static int spi_ctrlr_claim_bus(const struct spi_slave *slave) { - return 0; + struct qcs_spi_slave *ds = to_qcs_spi(slave); + unsigned int ret; + + ret = spi_hw_init(ds); + if (ret) + return -EIO; + switch (slave->bus) { + case 4: + gpio_configure + (GPIO(37), 2, GPIO_PULL_DOWN, GPIO_6MA, GPIO_INPUT); // MOSI + gpio_configure + (GPIO(38), 2, GPIO_PULL_DOWN, GPIO_6MA, GPIO_OUTPUT); // MISO + gpio_configure + (GPIO(117), 2, GPIO_NO_PULL, GPIO_6MA, GPIO_OUTPUT); // CS + gpio_configure + (GPIO(118), 2, GPIO_PULL_DOWN, GPIO_6MA, GPIO_OUTPUT);// CLK + break; + case 5: + gpio_configure + (GPIO(26), 3, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); // MOSI + gpio_configure + (GPIO(27), 3, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); // MISO + gpio_configure + (GPIO(28), 4, GPIO_PULL_UP, GPIO_16MA, GPIO_INPUT); // CS + gpio_configure + (GPIO(29), 4, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); // CLK + break; + default: + printk(BIOS_ERR, "SPI error: unsupported bus %d " + "(Supported buses 0, 1, 2, 3, 4, 5)\n", slave->bus); + break; + } + write_force_cs(slave, 1); + + return SUCCESS; } static void spi_ctrlr_release_bus(const struct spi_slave *slave) { + struct qcs_spi_slave *ds = to_qcs_spi(slave); + /* Reset the SPI hardware */ + write_force_cs(slave, 0); + spi_reset(ds); + ds->initialized = 0; } -static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, - size_t bytes_out, void *din, size_t bytes_in) +/* + * Function to write data to OUTPUT FIFO + */ +static void spi_write_byte(struct qcs_spi_slave *ds, unsigned char data) { + /* Wait for space in the FIFO */ + while ((read32(ds->regs->qup_operational) & OUTPUT_FIFO_FULL)) + udelay(1); + + /* Write the byte of data */ + write32(ds->regs->qup_output_fifo, data); +} + +/* + * Function to read data from Input FIFO + */ +static unsigned char spi_read_byte(struct qcs_spi_slave *ds) +{ + /* Wait for Data in FIFO */ + while (!(read32(ds->regs->qup_operational) & INPUT_FIFO_NOT_EMPTY)) + udelay(1); + + /* Read a byte of data */ + return read32(ds->regs->qup_input_fifo) & 0xff; +} + +/* + * Function to check wheather Input or Output FIFO + * has data to be serviced + */ +static int check_fifo_status(void *reg_addr) +{ + unsigned int count = TIMEOUT_CNT; + unsigned int status_flag; + unsigned int val; + + do { + val = read32(reg_addr); + count--; + if (count == 0) + return -ETIMEDOUT; + status_flag = ((val & OUTPUT_SERVICE_FLAG) | + (val & INPUT_SERVICE_FLAG)); + } while (!status_flag); + + return SUCCESS; +} + +/* + * Function to configure Input and Output enable/disable + */ +static void enable_io_config(struct qcs_spi_slave *ds, + uint32_t write_cnt, uint32_t read_cnt) +{ + + if (write_cnt) { + clrsetbits_le32(ds->regs->qup_config, + QUP_CONF_OUTPUT_MSK, QUP_CONF_OUTPUT_ENA); + } else { + clrsetbits_le32(ds->regs->qup_config, + QUP_CONF_OUTPUT_MSK, QUP_CONF_NO_OUTPUT); + } + + if (read_cnt) { + clrsetbits_le32(ds->regs->qup_config, + QUP_CONF_INPUT_MSK, QUP_CONF_INPUT_ENA); + } else { + clrsetbits_le32(ds->regs->qup_config, + QUP_CONF_INPUT_MSK, QUP_CONF_NO_INPUT); + } +} + +/* + * Function to read bytes number of data from the Input FIFO + */ +static int __blsp_spi_read(struct qcs_spi_slave *ds, u8 *data_buffer, + unsigned int bytes) +{ + uint32_t val; + unsigned int i; + unsigned int fifo_count; + int ret = SUCCESS; + int state_config; + struct stopwatch sw; + + /* Configure no of bytes to read */ + state_config = config_spi_state(ds, QUP_STATE_RESET); + if (state_config) + return state_config; + + /* Configure input and output enable */ + enable_io_config(ds, 0, bytes); + + write32(ds->regs->qup_mx_input_count, bytes); + + state_config = config_spi_state(ds, QUP_STATE_RUN); + if (state_config) + return state_config; + + while (bytes) { + ret = check_fifo_status(ds->regs->qup_operational); + if (ret != SUCCESS) + goto out; + + val = read32(ds->regs->qup_operational); + if (val & INPUT_SERVICE_FLAG) { + /* + * acknowledge to hw that software will + * read input data + */ + val &= INPUT_SERVICE_FLAG; + write32(ds->regs->qup_operational, val); + + fifo_count = ((bytes > SPI_INPUT_BLOCK_SIZE) ? + SPI_INPUT_BLOCK_SIZE : bytes); + + for (i = 0; i < fifo_count; i++) { + *data_buffer = spi_read_byte(ds); + data_buffer++; + bytes--; + } + } + } + + stopwatch_init_msecs_expire(&sw, 10); + + do { + val = read32(ds->regs->qup_operational); + if (stopwatch_expired(&sw)) { + printk(BIOS_ERR, "SPI FIFO read timeout\n"); + ret = -ETIMEDOUT; + goto out; + } + } while (!(val & MAX_INPUT_DONE_FLAG)); + +out: + /* + * Put the SPI Core back in the Reset State + * to end the transfer + */ + (void)config_spi_state(ds, QUP_STATE_RESET); + return ret; +} + +static int blsp_spi_read(struct qcs_spi_slave *ds, u8 *data_buffer, + unsigned int bytes) +{ + int length, ret; + + while (bytes) { + length = (bytes < MAX_COUNT_SIZE) ? bytes : MAX_COUNT_SIZE; + + ret = __blsp_spi_read(ds, data_buffer, length); + if (ret != SUCCESS) + return ret; + + data_buffer += length; + bytes -= length; + } + return 0; } +/* + * Function to write data to the Output FIFO + */ +static int __blsp_spi_write(struct qcs_spi_slave *ds, const u8 *cmd_buffer, + unsigned int bytes) +{ + uint32_t val; + unsigned int i; + unsigned int write_len = bytes; + unsigned int read_len = bytes; + unsigned int fifo_count; + int ret = SUCCESS; + int state_config; + struct stopwatch sw; + + state_config = config_spi_state(ds, QUP_STATE_RESET); + if (state_config) + return state_config; + + /* Configure input and output enable */ + enable_io_config(ds, write_len, read_len); + /* No of bytes to be written in Output FIFO */ + write32(ds->regs->qup_mx_output_count, bytes); + write32(ds->regs->qup_mx_input_count, bytes); + state_config = config_spi_state(ds, QUP_STATE_RUN); + + if (state_config) + return state_config; + + /* + * read_len considered to ensure that we read the dummy data for the + * write we performed. This is needed to ensure with WR-RD transaction + * to get the actual data on the subsequent read cycle that happens + */ + while (write_len || read_len) { + ret = check_fifo_status(ds->regs->qup_operational); + if (ret != SUCCESS) + goto out; + + val = read32(ds->regs->qup_operational); + if (val & OUTPUT_SERVICE_FLAG) { + /* + * acknowledge to hw that software will write + * expected output data + */ + val &= OUTPUT_SERVICE_FLAG; + write32(ds->regs->qup_operational, val); + + if (write_len > SPI_OUTPUT_BLOCK_SIZE) + fifo_count = SPI_OUTPUT_BLOCK_SIZE; + else + fifo_count = write_len; + + for (i = 0; i < fifo_count; i++) { + /* Write actual data to output FIFO */ + spi_write_byte(ds, *cmd_buffer); + cmd_buffer++; + write_len--; + } + } + + if (val & INPUT_SERVICE_FLAG) { + /* + * acknowledge to hw that software + * will read input data + */ + val &= INPUT_SERVICE_FLAG; + write32(ds->regs->qup_operational, val); + + if (read_len > SPI_INPUT_BLOCK_SIZE) + fifo_count = SPI_INPUT_BLOCK_SIZE; + else + fifo_count = read_len; + + for (i = 0; i < fifo_count; i++) { + /* Read dummy data for the data written */ + (void)spi_read_byte(ds); + + /* Decrement the read count after reading the + * dummy data from the device. This is to make + * sure we read dummy data before we write the + * data to fifo + */ + read_len--; + } + } + } + + stopwatch_init_msecs_expire(&sw, 10); + + do { + val = read32(ds->regs->qup_operational); + if (stopwatch_expired(&sw)) { + printk(BIOS_ERR, "SPI FIFO write timeout\n"); + ret = -ETIMEDOUT; + goto out; + } + + } while (!(val & MAX_OUTPUT_DONE_FLAG)); + +out: + /* + * Put the SPI Core back in the Reset State + * to end the transfer + */ + (void)config_spi_state(ds, QUP_STATE_RESET); + + return ret; +} + +static int blsp_spi_write(struct qcs_spi_slave *ds, u8 *cmd_buffer, + unsigned int bytes) +{ + int length, ret; + + while (bytes) { + length = (bytes < MAX_COUNT_SIZE) ? bytes : MAX_COUNT_SIZE; + + ret = __blsp_spi_write(ds, cmd_buffer, length); + if (ret != SUCCESS) { + printk(BIOS_ERR, "SPI:DBG write not success\n"); + return ret; + } + + cmd_buffer += length; + bytes -= length; + } + + return 0; +} + +/* + * This function is invoked with either tx_buf or rx_buf. + * Calling this function with both null does a chip select change. + */ +static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, + size_t out_bytes, void *din, size_t in_bytes) +{ + struct qcs_spi_slave *ds = to_qcs_spi(slave); + u8 *txp = (u8 *)dout; + u8 *rxp = (u8 *)din; + int ret; + + ret = config_spi_state(ds, QUP_STATE_RESET); + if (ret != SUCCESS) + return ret; + + if (dout != NULL) { + ret = blsp_spi_write(ds, txp, (unsigned int) out_bytes); + if (ret != SUCCESS) + goto out; + } + + if (din != NULL) { + ret = blsp_spi_read(ds, rxp, in_bytes); + if (ret != SUCCESS) + goto out; + } + +out: + /* + * Put the SPI Core back in the Reset State + * to end the transfer + */ + (void)config_spi_state(ds, QUP_STATE_RESET); + + return ret; +} + +static int spi_ctrlr_setup(const struct spi_slave *slave) +{ + struct qcs_spi_slave *ds = NULL; + int i; + unsigned int bus = slave->bus; + unsigned int cs = slave->cs; + int qup = 0; + int blsp = 2; + + if (((bus != BLSP4_SPI) && (bus != BLSP5_SPI)) || cs != 0) { + printk(BIOS_ERR, + "SPI error: unsupported bus %d or cs %d\n", bus, cs); + return -1; + } + + for (i = 0; i < ARRAY_SIZE(spi_slave_pool); i++) { + if (spi_slave_pool[i].allocated) + continue; + ds = spi_slave_pool + i; + ds->slave.bus = bus; + ds->slave.cs = cs; + ds->regs = &spi_reg[bus]; + ds->mode = SPI_MODE0; + ds->freq = 50000000; + + if (bus == BLSP4_SPI) { + ds->freq = 1000000; + qup = 4; + blsp = 1; + } + + clock_configure_spi(blsp, qup, ds->freq); + clock_enable_spi(blsp, qup); + + ds->allocated = 1; + + return 0; + } + + printk(BIOS_ERR, "SPI error: all %d pools busy\n", i); + return -1; +} + +static int xfer_vectors(const struct spi_slave *slave, + struct spi_op vectors[], size_t count) +{ + return spi_flash_vector_helper(slave, vectors, count, spi_ctrlr_xfer); +} + static const struct spi_ctrlr spi_ctrlr = { + .setup = spi_ctrlr_setup, .claim_bus = spi_ctrlr_claim_bus, .release_bus = spi_ctrlr_release_bus, .xfer = spi_ctrlr_xfer, - .max_xfer_size = 65535, + .xfer_vector = xfer_vectors, + .max_xfer_size = MAX_PACKET_COUNT, }; const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = { { .ctrlr = &spi_ctrlr, - .bus_start = 0, - .bus_end = 0, + .bus_start = BLSP5_SPI, + .bus_end = BLSP5_SPI, + }, + { + .ctrlr = &spi_ctrlr, + .bus_start = BLSP4_SPI, + .bus_end = BLSP4_SPI, }, }; From 06cfb21e243ec74660e4886cef2f2e9c6c755d9e Mon Sep 17 00:00:00 2001 From: Roy Mingi Park Date: Mon, 3 Jun 2019 16:11:25 -0700 Subject: [PATCH 322/331] mb/google/sarien: Fix SSD's power off sequence before going to S5 BUG=b:133389422 TEST=check SSD's power off sequence to meet PCIE requirement. SSD's reset should be cleared before clearing SSD's power EN Pin. Change-Id: Ia106b805deafb8a442b56bcce91b51135cb32988 Signed-off-by: Roy Mingi Park Reviewed-on: https://review.coreboot.org/c/coreboot/+/33182 Reviewed-by: EricR Lai Reviewed-by: Duncan Laurie Tested-by: build bot (Jenkins) --- .../sarien/variants/arcada/include/variant/acpi/mainboard.asl | 3 ++- .../sarien/variants/sarien/include/variant/acpi/mainboard.asl | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/mainboard.asl b/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/mainboard.asl index 6eba2bcb21..4b05ba8e90 100644 --- a/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/mainboard.asl +++ b/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/mainboard.asl @@ -40,8 +40,9 @@ Method (MPTS, 1) /* Clear SSD EN adn RST pin to avoid leakage */ If (Arg0 == 5) { - \_SB.PCI0.CTXS (SSD_EN) \_SB.PCI0.CTXS (SSD_RST) + Sleep(1) + \_SB.PCI0.CTXS (SSD_EN) } } diff --git a/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/mainboard.asl b/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/mainboard.asl index 6eba2bcb21..4b05ba8e90 100644 --- a/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/mainboard.asl +++ b/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/mainboard.asl @@ -40,8 +40,9 @@ Method (MPTS, 1) /* Clear SSD EN adn RST pin to avoid leakage */ If (Arg0 == 5) { - \_SB.PCI0.CTXS (SSD_EN) \_SB.PCI0.CTXS (SSD_RST) + Sleep(1) + \_SB.PCI0.CTXS (SSD_EN) } } From fbf380abac431b3b93ea180ee928b6b8f8dd8182 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Thu, 10 Jan 2019 22:56:15 +0100 Subject: [PATCH 323/331] mb/*/devicetree.cb: Remove unavailable PCIe ports Some variants only support 4 PCIe ports so there is no need to have those unavailable ports in the devicetree. Change-Id: I154cae358fb7f862fc0c8eaa620474b37b5e6484 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/30821 Reviewed-by: Felix Held Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2/devicetree.cb | 2 -- src/mainboard/asrock/g41c-gs/variants/g41m-gs/devicetree.cb | 2 -- src/mainboard/asrock/g41c-gs/variants/g41m-s3/devicetree.cb | 2 -- src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/devicetree.cb | 2 -- src/mainboard/asus/p5gc-mx/devicetree.cb | 2 -- src/mainboard/foxconn/g41s-k/devicetree.cb | 2 -- src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb | 2 -- src/mainboard/intel/d945gclf/devicetree.cb | 2 -- src/mainboard/intel/dg41wv/devicetree.cb | 2 -- src/mainboard/lenovo/thinkcentre_a58/devicetree.cb | 2 -- 10 files changed, 20 deletions(-) diff --git a/src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2/devicetree.cb b/src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2/devicetree.cb index 833ea00ad7..156fe3fd64 100644 --- a/src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2/devicetree.cb +++ b/src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2/devicetree.cb @@ -62,8 +62,6 @@ chip northbridge/intel/x4x # Northbridge device pci 1c.1 on end # PCIe 2 device pci 1c.2 off end # PCIe 3 device pci 1c.3 off end # PCIe 4 - device pci 1c.4 off end # PCIe 5 - device pci 1c.5 off end # PCIe 6 device pci 1d.0 on # USB subsystemid 0x1849 0x27c8 end diff --git a/src/mainboard/asrock/g41c-gs/variants/g41m-gs/devicetree.cb b/src/mainboard/asrock/g41c-gs/variants/g41m-gs/devicetree.cb index 63bcbc8d39..ba2f00d1ec 100644 --- a/src/mainboard/asrock/g41c-gs/variants/g41m-gs/devicetree.cb +++ b/src/mainboard/asrock/g41c-gs/variants/g41m-gs/devicetree.cb @@ -57,8 +57,6 @@ chip northbridge/intel/x4x # Northbridge device pci 1c.1 on end # PCIe 2 device pci 1c.2 off end # PCIe 3 device pci 1c.3 off end # PCIe 4 - device pci 1c.4 off end # PCIe 5 - device pci 1c.5 off end # PCIe 6 device pci 1d.0 on # USB subsystemid 0x1849 0x27c8 end diff --git a/src/mainboard/asrock/g41c-gs/variants/g41m-s3/devicetree.cb b/src/mainboard/asrock/g41c-gs/variants/g41m-s3/devicetree.cb index 971eebd7c0..45a20142f4 100644 --- a/src/mainboard/asrock/g41c-gs/variants/g41m-s3/devicetree.cb +++ b/src/mainboard/asrock/g41c-gs/variants/g41m-s3/devicetree.cb @@ -59,8 +59,6 @@ chip northbridge/intel/x4x # Northbridge end device pci 1c.2 off end # PCIe 3 device pci 1c.3 off end # PCIe 4 - device pci 1c.4 off end # PCIe 5 - device pci 1c.5 off end # PCIe 6 device pci 1d.0 on # USB subsystemid 0x1849 0x27c8 end diff --git a/src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/devicetree.cb b/src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/devicetree.cb index 4c910c5f76..b458115134 100644 --- a/src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/devicetree.cb +++ b/src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/devicetree.cb @@ -56,8 +56,6 @@ chip northbridge/intel/x4x # Northbridge device pci 1c.1 on end # PCIe 2 (ethernet) device pci 1c.2 off end # PCIe 3 device pci 1c.3 off end # PCIe 4 - device pci 1c.4 off end # PCIe 5 - device pci 1c.5 off end # PCIe 6 device pci 1d.0 on # USB subsystemid 0x1849 0x27c8 end diff --git a/src/mainboard/asus/p5gc-mx/devicetree.cb b/src/mainboard/asus/p5gc-mx/devicetree.cb index 642f1ee009..2f7d2781d7 100644 --- a/src/mainboard/asus/p5gc-mx/devicetree.cb +++ b/src/mainboard/asus/p5gc-mx/devicetree.cb @@ -64,8 +64,6 @@ chip northbridge/intel/i945 device pci 1c.1 on end # PCIe device pci 1c.2 off end # PCIe port 3 device pci 1c.3 off end # PCIe port 4 - device pci 1c.4 off end # PCIe port 5 - device pci 1c.5 off end # PCIe port 6 device pci 1d.0 on # USB UHCI ioapic_irq 2 INTA 0x10 end diff --git a/src/mainboard/foxconn/g41s-k/devicetree.cb b/src/mainboard/foxconn/g41s-k/devicetree.cb index bf940b46aa..ca952ba7c6 100644 --- a/src/mainboard/foxconn/g41s-k/devicetree.cb +++ b/src/mainboard/foxconn/g41s-k/devicetree.cb @@ -57,8 +57,6 @@ chip northbridge/intel/x4x # Northbridge end device pci 1c.2 off end # PCIe 3 device pci 1c.3 off end # PCIe 4 - device pci 1c.4 off end # PCIe 5 - device pci 1c.5 off end # PCIe 6 device pci 1d.0 on end # USB device pci 1d.1 on end # USB device pci 1d.2 on end # USB diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb b/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb index 05edb278d9..8b47c4f21f 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb +++ b/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb @@ -63,8 +63,6 @@ chip northbridge/intel/x4x # Northbridge end device pci 1c.2 off end # PCIe 3 device pci 1c.3 off end # PCIe 4 - device pci 1c.4 off end # PCIe 5 - device pci 1c.5 off end # PCIe 6 device pci 1d.0 on # USB subsystemid 0x1458 0x5004 end diff --git a/src/mainboard/intel/d945gclf/devicetree.cb b/src/mainboard/intel/d945gclf/devicetree.cb index 90c517fb90..716654c6eb 100644 --- a/src/mainboard/intel/d945gclf/devicetree.cb +++ b/src/mainboard/intel/d945gclf/devicetree.cb @@ -59,8 +59,6 @@ chip northbridge/intel/i945 device pci 1c.1 off end # PCIe port 2 device pci 1c.2 on end # PCIe port 3 device pci 1c.3 on end # PCIe port 4 - device pci 1c.4 off end # PCIe port 5 - device pci 1c.5 off end # PCIe port 6 device pci 1d.0 on end # USB UHCI device pci 1d.1 on end # USB UHCI device pci 1d.2 on end # USB UHCI diff --git a/src/mainboard/intel/dg41wv/devicetree.cb b/src/mainboard/intel/dg41wv/devicetree.cb index d96ad9541c..be28763a00 100644 --- a/src/mainboard/intel/dg41wv/devicetree.cb +++ b/src/mainboard/intel/dg41wv/devicetree.cb @@ -77,8 +77,6 @@ chip northbridge/intel/x4x # Northbridge end device pci 1c.2 off end # PCIe 3 device pci 1c.3 off end # PCIe 4 - device pci 1c.4 off end # PCIe 5 - device pci 1c.5 off end # PCIe 6 device pci 1d.0 on # USB subsystemid 0x8086 0x5756 end diff --git a/src/mainboard/lenovo/thinkcentre_a58/devicetree.cb b/src/mainboard/lenovo/thinkcentre_a58/devicetree.cb index f3f56cec1f..cc3ef49f25 100644 --- a/src/mainboard/lenovo/thinkcentre_a58/devicetree.cb +++ b/src/mainboard/lenovo/thinkcentre_a58/devicetree.cb @@ -55,8 +55,6 @@ chip northbridge/intel/x4x # Northbridge end device pci 1c.2 off end # PCIe 3 device pci 1c.3 off end # PCIe 4 - device pci 1c.4 off end # PCIe 5 - device pci 1c.5 off end # PCIe 6 device pci 1d.0 on end # USB device pci 1d.1 on end # USB device pci 1d.2 on end # USB From 742df5ad34c0ad4d2bae2373ace6440c4cb6b792 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Mon, 3 Jun 2019 16:24:41 +0200 Subject: [PATCH 324/331] sb/intel/i82801gx: Include chip.h directly Change-Id: I3d743e90444292be687999ab4f50aa89d514fbad Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/33171 Reviewed-by: Felix Held Reviewed-by: Angel Pons Reviewed-by: HAOUAS Elyes Tested-by: build bot (Jenkins) --- src/mainboard/lenovo/t60/mainboard.c | 1 + src/mainboard/lenovo/x60/mainboard.c | 1 + src/mainboard/lenovo/z61t/mainboard.c | 1 + src/southbridge/intel/i82801gx/i82801gx.h | 1 - src/southbridge/intel/i82801gx/ide.c | 1 + src/southbridge/intel/i82801gx/lpc.c | 1 + src/southbridge/intel/i82801gx/pcie.c | 1 + src/southbridge/intel/i82801gx/sata.c | 1 + 8 files changed, 7 insertions(+), 1 deletion(-) diff --git a/src/mainboard/lenovo/t60/mainboard.c b/src/mainboard/lenovo/t60/mainboard.c index 2d998fbaa2..b78d862d41 100644 --- a/src/mainboard/lenovo/t60/mainboard.c +++ b/src/mainboard/lenovo/t60/mainboard.c @@ -22,6 +22,7 @@ #include #include #include +#include #include #include diff --git a/src/mainboard/lenovo/x60/mainboard.c b/src/mainboard/lenovo/x60/mainboard.c index 274a15113a..964e9c0b52 100644 --- a/src/mainboard/lenovo/x60/mainboard.c +++ b/src/mainboard/lenovo/x60/mainboard.c @@ -22,6 +22,7 @@ #include #include #include +#include #include "dock.h" #include #include diff --git a/src/mainboard/lenovo/z61t/mainboard.c b/src/mainboard/lenovo/z61t/mainboard.c index 886b4fb403..5f599465a1 100644 --- a/src/mainboard/lenovo/z61t/mainboard.c +++ b/src/mainboard/lenovo/z61t/mainboard.c @@ -22,6 +22,7 @@ #include #include #include +#include #include #include diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h index a91ffc500b..e44fcf5123 100644 --- a/src/southbridge/intel/i82801gx/i82801gx.h +++ b/src/southbridge/intel/i82801gx/i82801gx.h @@ -36,7 +36,6 @@ #if !defined(__ASSEMBLER__) #if !defined(__PRE_RAM__) -#include "chip.h" #if !defined(__SIMPLE_DEVICE__) void i82801gx_enable(struct device *dev); #endif diff --git a/src/southbridge/intel/i82801gx/ide.c b/src/southbridge/intel/i82801gx/ide.c index a36237228c..672ee432fd 100644 --- a/src/southbridge/intel/i82801gx/ide.c +++ b/src/southbridge/intel/i82801gx/ide.c @@ -19,6 +19,7 @@ #include #include #include +#include "chip.h" #include "i82801gx.h" typedef struct southbridge_intel_i82801gx_config config_t; diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index 948b6aa7f7..846a70997b 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -34,6 +34,7 @@ #include #include +#include "chip.h" #include "i82801gx.h" #include "nvs.h" diff --git a/src/southbridge/intel/i82801gx/pcie.c b/src/southbridge/intel/i82801gx/pcie.c index 3e5dbc3e87..0946a9aadf 100644 --- a/src/southbridge/intel/i82801gx/pcie.c +++ b/src/southbridge/intel/i82801gx/pcie.c @@ -19,6 +19,7 @@ #include #include #include +#include "chip.h" #include "i82801gx.h" /* Low Power variant has 6 root ports. */ diff --git a/src/southbridge/intel/i82801gx/sata.c b/src/southbridge/intel/i82801gx/sata.c index 8514b6d3bf..b657513dcf 100644 --- a/src/southbridge/intel/i82801gx/sata.c +++ b/src/southbridge/intel/i82801gx/sata.c @@ -20,6 +20,7 @@ #include #include #include +#include "chip.h" #include "i82801gx.h" #include "sata.h" From 2ba303e49d03b3e0a77a6b2adde07e38a3aa5c1a Mon Sep 17 00:00:00 2001 From: John Zhao Date: Tue, 28 May 2019 16:48:14 -0700 Subject: [PATCH 325/331] src/arch/x86: Prevent attack on null pointer dereference Clang Static Analyzer version 8.0.0 detects null pointer argument in call to memory copy function. Add sanity check for pointer header to prevent null pointer dereference. TEST=Built and boot up to kernel. Change-Id: I7027b7cae3009a5481048bfa0536a6cbd9bef683 Signed-off-by: John Zhao Reviewed-on: https://review.coreboot.org/c/coreboot/+/33051 Tested-by: build bot (Jenkins) Reviewed-by: Lance Zhao Reviewed-by: Felix Held --- src/arch/x86/acpi.c | 53 ++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 52 insertions(+), 1 deletion(-) diff --git a/src/arch/x86/acpi.c b/src/arch/x86/acpi.c index d1dcd03652..bf9813cbfe 100644 --- a/src/arch/x86/acpi.c +++ b/src/arch/x86/acpi.c @@ -218,6 +218,9 @@ void acpi_create_madt(acpi_madt_t *madt) memset((void *)madt, 0, sizeof(acpi_madt_t)); + if (!header) + return; + /* Fill out header fields. */ memcpy(header->signature, "APIC", 4); memcpy(header->oem_id, OEM_ID, 6); @@ -248,6 +251,9 @@ void acpi_create_mcfg(acpi_mcfg_t *mcfg) memset((void *)mcfg, 0, sizeof(acpi_mcfg_t)); + if (!header) + return; + /* Fill out header fields. */ memcpy(header->signature, "MCFG", 4); memcpy(header->oem_id, OEM_ID, 6); @@ -302,6 +308,9 @@ static void acpi_create_tcpa(acpi_tcpa_t *tcpa) if (!lasa) return; + if (!header) + return; + /* Fill out header fields. */ memcpy(header->signature, "TCPA", 4); memcpy(header->oem_id, OEM_ID, 6); @@ -361,6 +370,9 @@ static void acpi_create_tpm2(acpi_tpm2_t *tpm2) if (!lasa) tpm2_log_len = 0; + if (!header) + return; + /* Fill out header fields. */ memcpy(header->signature, "TPM2", 4); memcpy(header->oem_id, OEM_ID, 6); @@ -481,6 +493,9 @@ void acpi_create_srat(acpi_srat_t *srat, memset((void *)srat, 0, sizeof(acpi_srat_t)); + if (!header) + return; + /* Fill out header fields. */ memcpy(header->signature, "SRAT", 4); memcpy(header->oem_id, OEM_ID, 6); @@ -508,6 +523,9 @@ void acpi_create_dmar(acpi_dmar_t *dmar, enum dmar_flags flags, memset((void *)dmar, 0, sizeof(acpi_dmar_t)); + if (!header) + return; + /* Fill out header fields. */ memcpy(header->signature, "DMAR", 4); memcpy(header->oem_id, OEM_ID, 6); @@ -669,6 +687,9 @@ void acpi_create_slit(acpi_slit_t *slit, memset((void *)slit, 0, sizeof(acpi_slit_t)); + if (!header) + return; + /* Fill out header fields. */ memcpy(header->signature, "SLIT", 4); memcpy(header->oem_id, OEM_ID, 6); @@ -694,6 +715,9 @@ void acpi_create_hpet(acpi_hpet_t *hpet) memset((void *)hpet, 0, sizeof(acpi_hpet_t)); + if (!header) + return; + /* Fill out header fields. */ memcpy(header->signature, "HPET", 4); memcpy(header->oem_id, OEM_ID, 6); @@ -728,6 +752,9 @@ void acpi_create_vfct(struct device *device, memset((void *)vfct, 0, sizeof(struct acpi_vfct)); + if (!header) + return; + /* Fill out header fields. */ memcpy(header->signature, "VFCT", 4); memcpy(header->oem_id, OEM_ID, 6); @@ -754,6 +781,9 @@ void acpi_create_ivrs(acpi_ivrs_t *ivrs, memset((void *)ivrs, 0, sizeof(acpi_ivrs_t)); + if (!header) + return; + /* Fill out header fields. */ memcpy(header->signature, "IVRS", 4); memcpy(header->oem_id, OEM_ID, 6); @@ -807,6 +837,10 @@ void acpi_create_dbg2(acpi_dbg2_header_t *dbg2, current = (uintptr_t)dbg2; memset(dbg2, 0, sizeof(acpi_dbg2_header_t)); header = &(dbg2->header); + + if (!header) + return; + header->revision = get_acpi_table_revision(DBG2); memcpy(header->signature, "DBG2", 4); memcpy(header->oem_id, OEM_ID, 6); @@ -926,6 +960,9 @@ static void acpi_write_rsdt(acpi_rsdt_t *rsdt, char *oem_id, char *oem_table_id) { acpi_header_t *header = &(rsdt->header); + if (!header) + return; + /* Fill out header fields. */ memcpy(header->signature, "RSDT", 4); memcpy(header->oem_id, oem_id, 6); @@ -946,6 +983,9 @@ static void acpi_write_xsdt(acpi_xsdt_t *xsdt, char *oem_id, char *oem_table_id) { acpi_header_t *header = &(xsdt->header); + if (!header) + return; + /* Fill out header fields. */ memcpy(header->signature, "XSDT", 4); memcpy(header->oem_id, oem_id, 6); @@ -1046,7 +1086,8 @@ unsigned long acpi_create_hest_error_source(acpi_hest_t *hest, memcpy(pos, data, data_len); len += data_len; - header->length += len; + if (header) + header->length += len; return len; } @@ -1059,6 +1100,9 @@ void acpi_write_hest(acpi_hest_t *hest, memset(hest, 0, sizeof(acpi_hest_t)); + if (!header) + return; + memcpy(header->signature, "HEST", 4); memcpy(header->oem_id, OEM_ID, 6); memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); @@ -1080,6 +1124,9 @@ void acpi_write_bert(acpi_bert_t *bert, uintptr_t region, size_t length) memset(bert, 0, sizeof(acpi_bert_t)); + if (!header) + return; + memcpy(header->signature, "BERT", 4); memcpy(header->oem_id, OEM_ID, 6); memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); @@ -1101,6 +1148,10 @@ void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) acpi_header_t *header = &(fadt->header); memset((void *) fadt, 0, sizeof(acpi_fadt_t)); + + if (!header) + return; + memcpy(header->signature, "FACP", 4); header->length = sizeof(acpi_fadt_t); header->revision = get_acpi_table_revision(FADT); From c53665ce55ba4f5a670caf382213d984a2991900 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Wed, 22 May 2019 20:06:30 +0200 Subject: [PATCH 326/331] nb/intel/x4x: Remove variable set but not used MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I142ae6f7806b3f57b98a158e8f26592aed8fa452 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/32939 Reviewed-by: Felix Held Reviewed-by: Kyösti Mälkki Tested-by: build bot (Jenkins) --- src/northbridge/intel/x4x/raminit_ddr23.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/src/northbridge/intel/x4x/raminit_ddr23.c b/src/northbridge/intel/x4x/raminit_ddr23.c index f172623108..422b0ffa16 100644 --- a/src/northbridge/intel/x4x/raminit_ddr23.c +++ b/src/northbridge/intel/x4x/raminit_ddr23.c @@ -1317,7 +1317,6 @@ static u32 mirror_shift_bit(const u32 data, u8 bit) void send_jedec_cmd(const struct sysinfo *s, u8 r, u8 ch, u8 cmd, u32 val) { u32 addr = test_address(ch, r); - volatile u32 rubbish; u8 data8 = cmd; u32 data32; @@ -1337,7 +1336,7 @@ void send_jedec_cmd(const struct sysinfo *s, u8 r, u8 ch, u8 cmd, u32 val) } data32 <<= 3; - rubbish = read32((void *)((data32 | addr))); + read32((void *)((data32 | addr))); udelay(10); MCHBAR8_AND_OR(0x271, ~0x3e, NORMALOP_CMD); MCHBAR8_AND_OR(0x671, ~0x3e, NORMALOP_CMD); From d3a73280cc8e01a28cbdb1a4d086e4dda7b35f0c Mon Sep 17 00:00:00 2001 From: John Zhao Date: Fri, 31 May 2019 09:58:49 -0700 Subject: [PATCH 327/331] src/drivers/intel: Avoid NULL pointer dereference Coverity detects pointer fih as FORWARD_NULL. Add sanity check for fih to prevent NULL pointer dereference. BUG=CID 1401717 TEST=Built and boot up to kernel. Change-Id: Ia6853e5302c87d9ffe52b942f067be56f6e77406 Signed-off-by: John Zhao Reviewed-on: https://review.coreboot.org/c/coreboot/+/33150 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held Reviewed-by: Christian Walter --- src/drivers/intel/fsp1_1/car.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/drivers/intel/fsp1_1/car.c b/src/drivers/intel/fsp1_1/car.c index 10f9524650..dd17664036 100644 --- a/src/drivers/intel/fsp1_1/car.c +++ b/src/drivers/intel/fsp1_1/car.c @@ -120,6 +120,9 @@ void mainboard_romstage_entry(unsigned long bist) * the flash is memory mapped CPU's address space. */ FSP_INFO_HEADER *fih = find_fsp((uintptr_t)rdev_mmap_full(prog_rdev(&fsp))); + if (!fih) + die("Invalid FSP header\n"); + cache_as_ram_stage_main(fih); } From d622507450464db5ee6cff7de03f9649a299018b Mon Sep 17 00:00:00 2001 From: Frans Hendriks Date: Tue, 21 May 2019 11:04:50 +0200 Subject: [PATCH 328/331] lib/Makefile.inc: Add hexdump.c to postcar stage hexdump() is not available in postcar stage. Add hexdump() functionality to postcar stage. BUG=NA TEST=Booting Embedded Linux on Facebook FBG-1701 Change-Id: Ibdce911065c01b0a1aa81dc248557257d0e420b0 Signed-off-by: Frans Hendriks Reviewed-on: https://review.coreboot.org/c/coreboot/+/32908 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks --- src/lib/Makefile.inc | 1 + 1 file changed, 1 insertion(+) diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 1b8ad19b67..16d5c649b2 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -166,6 +166,7 @@ postcar-y += imd.c postcar-y += romstage_handoff.c bootblock-y += hexdump.c +postcar-y += hexdump.c ramstage-y += hexdump.c romstage-y += hexdump.c verstage-y += hexdump.c From 43b6e2ed7108859297512a6d4194335fb8237d1b Mon Sep 17 00:00:00 2001 From: Frans Hendriks Date: Tue, 4 Jun 2019 13:53:05 +0200 Subject: [PATCH 329/331] mainboard/facebook/fbg1701: Do initial mainboard commit Initial support for Facebook FBG-1701 system. coreboot implementation based on Intel Strago mainboard. Configure 'Onboard memory manufacturer' which must match HW. BUG=N/A TEST=booting SeaBIOS and Linux 4.15+ kernel on Facebook FBG-1701 Change-Id: I28ac78a630ee705b1e546031f024bfe7f952ab39 Signed-off-by: Frans Hendriks Reviewed-on: https://review.coreboot.org/c/coreboot/+/30414 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks Reviewed-by: Patrick Rudolph --- Documentation/mainboard/facebook/fbg1701.md | 83 ++++++ Documentation/mainboard/index.md | 4 + src/mainboard/facebook/fbg1701/Kconfig | 105 +++++++ src/mainboard/facebook/fbg1701/Kconfig.name | 2 + src/mainboard/facebook/fbg1701/Makefile.inc | 34 +++ src/mainboard/facebook/fbg1701/acpi/ec.asl | 14 + .../facebook/fbg1701/acpi/mainboard.asl | 45 +++ .../facebook/fbg1701/acpi/sleepstates.asl | 20 ++ .../facebook/fbg1701/acpi/superio.asl | 47 ++++ src/mainboard/facebook/fbg1701/acpi_tables.c | 54 ++++ src/mainboard/facebook/fbg1701/board_info.txt | 6 + src/mainboard/facebook/fbg1701/cmos.layout | 121 +++++++++ src/mainboard/facebook/fbg1701/com_init.c | 29 ++ src/mainboard/facebook/fbg1701/devicetree.cb | 131 +++++++++ src/mainboard/facebook/fbg1701/dsdt.asl | 48 ++++ src/mainboard/facebook/fbg1701/fadt.c | 48 ++++ src/mainboard/facebook/fbg1701/gpio.c | 253 +++++++++++++++++ src/mainboard/facebook/fbg1701/hda_verb.c | 78 ++++++ src/mainboard/facebook/fbg1701/irqroute.c | 18 ++ src/mainboard/facebook/fbg1701/irqroute.h | 70 +++++ src/mainboard/facebook/fbg1701/logo.c | 47 ++++ src/mainboard/facebook/fbg1701/mainboard.c | 52 ++++ src/mainboard/facebook/fbg1701/mainboard.h | 21 ++ src/mainboard/facebook/fbg1701/onboard.h | 36 +++ src/mainboard/facebook/fbg1701/ramstage.c | 32 +++ src/mainboard/facebook/fbg1701/romstage.c | 51 ++++ .../spd/MICRON_MT41K512M16HA-125A.spd.hex | 257 ++++++++++++++++++ .../spd/SAMSUNG_K4B8G1646D-MYKO.spd.hex | 254 +++++++++++++++++ src/mainboard/facebook/fbg1701/w25q64.c | 78 ++++++ 29 files changed, 2038 insertions(+) create mode 100644 Documentation/mainboard/facebook/fbg1701.md create mode 100644 src/mainboard/facebook/fbg1701/Kconfig create mode 100644 src/mainboard/facebook/fbg1701/Kconfig.name create mode 100644 src/mainboard/facebook/fbg1701/Makefile.inc create mode 100644 src/mainboard/facebook/fbg1701/acpi/ec.asl create mode 100644 src/mainboard/facebook/fbg1701/acpi/mainboard.asl create mode 100644 src/mainboard/facebook/fbg1701/acpi/sleepstates.asl create mode 100644 src/mainboard/facebook/fbg1701/acpi/superio.asl create mode 100644 src/mainboard/facebook/fbg1701/acpi_tables.c create mode 100644 src/mainboard/facebook/fbg1701/board_info.txt create mode 100644 src/mainboard/facebook/fbg1701/cmos.layout create mode 100644 src/mainboard/facebook/fbg1701/com_init.c create mode 100644 src/mainboard/facebook/fbg1701/devicetree.cb create mode 100644 src/mainboard/facebook/fbg1701/dsdt.asl create mode 100644 src/mainboard/facebook/fbg1701/fadt.c create mode 100644 src/mainboard/facebook/fbg1701/gpio.c create mode 100644 src/mainboard/facebook/fbg1701/hda_verb.c create mode 100644 src/mainboard/facebook/fbg1701/irqroute.c create mode 100644 src/mainboard/facebook/fbg1701/irqroute.h create mode 100644 src/mainboard/facebook/fbg1701/logo.c create mode 100644 src/mainboard/facebook/fbg1701/mainboard.c create mode 100644 src/mainboard/facebook/fbg1701/mainboard.h create mode 100644 src/mainboard/facebook/fbg1701/onboard.h create mode 100644 src/mainboard/facebook/fbg1701/ramstage.c create mode 100644 src/mainboard/facebook/fbg1701/romstage.c create mode 100644 src/mainboard/facebook/fbg1701/spd/MICRON_MT41K512M16HA-125A.spd.hex create mode 100644 src/mainboard/facebook/fbg1701/spd/SAMSUNG_K4B8G1646D-MYKO.spd.hex create mode 100644 src/mainboard/facebook/fbg1701/w25q64.c diff --git a/Documentation/mainboard/facebook/fbg1701.md b/Documentation/mainboard/facebook/fbg1701.md new file mode 100644 index 0000000000..89e8a6abbc --- /dev/null +++ b/Documentation/mainboard/facebook/fbg1701.md @@ -0,0 +1,83 @@ +# Facebook FBG-1701 + +This page describes how to run coreboot on the Facebook FBG1701. + +FBG1701 are assembled with different onboard memory modules: + Rev 1.0 Onboard Samsung K4B8G1646D-MYKO memory + Rev 1.1 and 1.2 Onboard Micron MT41K512M16HA-125A memory + +Use make menuconfig to configure `onboard memory manufacturer` in Mainboard +menu. + +## Required blobs + +This board currently requires: +fsp blob 3rdparty/fsp/BraswellFspBinPkg/FspBin/BSWFSP.fd +Microcode Intel Braswell cpuid 1046C4 version 410 + (Used pre-build binary retrieved from Intel site) + +## Flashing coreboot + +### Internal programming + +The main SPI flash can be accessed using [flashrom]. + +### External programming + +The system has an internal flash chip which is a 8 MiB soldered SOIC-8 chip. +This chip is located to the top middle side of the board. It's located +between SoC and Q7 connector. Use clip (or solder wires) to program +the chip. +Specifically, it's a Winbond W25Q64FW (1.8V), whose datasheet can be found +[here][W25Q64FW]. + +The system has an external flash chip which is a 8 MiB soldered SOIC-8 chip. +This chip is located in the middle of carrier board close to the flex cable +connection. +Specifically, it's a Winbond W25Q64FV (3.3V), whose datasheet can be found +[here][W25Q64FV]. + +## Known issues + +- None + +## Untested + +- hardware monitor +- SDIO +- Full Embedded Controller support + +## Working + +- USB +- Gigabit Ethernet +- integrated graphics +- flashrom +- external graphics +- PCIe +- eMMC +- SATA +- serial port +- SMBus +- HDA +- initialization with FSP MR2 +- SeaBIOS payload +- Embedded Linux (Ubuntu 4.15+) + +## Technology + +```eval_rst ++------------------+--------------------------------------------------+ +| SoC | Intel Atom Processor N3710 | ++------------------+--------------------------------------------------+ +| CPU | Intel Braswell (N3710) | ++------------------+--------------------------------------------------+ +| Super I/O, EC | ITE8256 | ++------------------+--------------------------------------------------+ +| Coprocessor | Intel Management Engine | ++------------------+--------------------------------------------------+ +``` + +[W25Q64FW]: https://www.winbond.com/resource-files/w25q64fw%20revn%2005182017%20sfdp.pdf +[W25Q64FV]: https://www.winbond.com/resource-files/w25q64fv%20revs%2007182017.pdf +[flashrom]: https://flashrom.org/Flashrom diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md index fb4f5022aa..f63ef763fb 100644 --- a/Documentation/mainboard/index.md +++ b/Documentation/mainboard/index.md @@ -30,6 +30,10 @@ The boards in this section are not real mainboards, but emulators. - [IceLake RVP](intel/icelake_rvp.md) - [KBLRVP11](intel/kblrvp11.md) +## Facebook + +- [FBG-1701](facebook/fbg1701.md) + ## Foxconn - [D41S](foxconn/d41s.md) diff --git a/src/mainboard/facebook/fbg1701/Kconfig b/src/mainboard/facebook/fbg1701/Kconfig new file mode 100644 index 0000000000..3f451945b4 --- /dev/null +++ b/src/mainboard/facebook/fbg1701/Kconfig @@ -0,0 +1,105 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2018-2019 Eltan B.V. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +if BOARD_FACEBOOK_FBG1701 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_8192 + select HAVE_ACPI_TABLES + select HAVE_OPTION_TABLE + select MAINBOARD_HAS_LPC_TPM + select MAINBOARD_HAS_TPM2 + select SOC_INTEL_BRASWELL + select PCIEXP_L1_SUB_STATE + select HAVE_FSP_BIN + select CACHE_MRC_SETTINGS + select DISABLE_HPET + select GENERIC_SPD_BIN + +choice + prompt "Onboard memory manufacturer" + default ONBOARD_MICRON_MEM + +config ONBOARD_SAMSUNG_MEM + bool "Samsung" + help + Samsung K4B8G1646D memory + +config ONBOARD_MICRON_MEM + bool "Micron" + help + Micron MT41K512M16HA memory +endchoice + +config MAINBOARD_DIR + string + default facebook/fbg1701 + +config MAINBOARD_PART_NUMBER + string + default "FBG-1701" + +config CBFS_SIZE + hex + default 0x00800000 + +config CPU_MICROCODE_CBFS_LEN + hex + default 0x10C00 + help + This should be updated when the microcode patch changes. + +config CPU_MICROCODE_CBFS_LOC + hex + default 0xFFFE9400 + +config MRC_SETTINGS_CACHE_SIZE + hex + default 0x08000 + +config FSP_LOC + hex + default 0xfff9c000 + +config FSP1_1_DISPLAY_LOGO + bool + default n + +config BOOTBLOCK_LOC + hex + default 0xFFFF0000 + +config BOOTBLOCK_SIZE + hex + default 0x10000 + +config SPI_FLASH_INCLUDE_ALL_DRIVERS + bool + default n + +config SPI_FLASH_WINBOND + bool + default y + +config TPM_INIT + bool "TPM Setup in RAMSTAGE" + default n + +config C_ENV_BOOTBLOCK_SIZE + hex "C Bootblock Size" + default 0x4000 + +endif # BOARD_FACEBOOK_FBG1701 diff --git a/src/mainboard/facebook/fbg1701/Kconfig.name b/src/mainboard/facebook/fbg1701/Kconfig.name new file mode 100644 index 0000000000..1ead7d587f --- /dev/null +++ b/src/mainboard/facebook/fbg1701/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_FACEBOOK_FBG1701 + bool "fbg1701" diff --git a/src/mainboard/facebook/fbg1701/Makefile.inc b/src/mainboard/facebook/fbg1701/Makefile.inc new file mode 100644 index 0000000000..07309c564c --- /dev/null +++ b/src/mainboard/facebook/fbg1701/Makefile.inc @@ -0,0 +1,34 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2013 Google Inc. +## Copyright (C) 2015 Intel Corp. +## Copyright (C) 2018-2019 Eltan B.V. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +bootblock-$(CONFIG_C_ENVIRONMENT_BOOTBLOCK) += com_init.c + +ramstage-y += gpio.c +ramstage-y += hda_verb.c +ramstage-y += irqroute.c +ramstage-$(CONFIG_FSP1_1_DISPLAY_LOGO) += logo.c +ramstage-y += ramstage.c +ramstage-y += w25q64.c + +cbfs-files-$(CONFIG_FSP1_1_DISPLAY_LOGO) += logo.bmp +logo.bmp-file := $(call strip_quotes,$(CONFIG_FSP1_1_LOGO_FILE_NAME)) +logo.bmp-type := raw +logo.bmp-compression := LZMA + +# Order of names in SPD_SOURCES is important! +SPD_SOURCES = SAMSUNG_K4B8G1646D-MYKO +SPD_SOURCES += MICRON_MT41K512M16HA-125A diff --git a/src/mainboard/facebook/fbg1701/acpi/ec.asl b/src/mainboard/facebook/fbg1701/acpi/ec.asl new file mode 100644 index 0000000000..3c9d818bae --- /dev/null +++ b/src/mainboard/facebook/fbg1701/acpi/ec.asl @@ -0,0 +1,14 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Eltan B.V. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ diff --git a/src/mainboard/facebook/fbg1701/acpi/mainboard.asl b/src/mainboard/facebook/fbg1701/acpi/mainboard.asl new file mode 100644 index 0000000000..9575748446 --- /dev/null +++ b/src/mainboard/facebook/fbg1701/acpi/mainboard.asl @@ -0,0 +1,45 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Google Inc. + * Copyright (C) 2015 Intel Corp. + * Copyright (C) 2018 Eltan B.V. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "onboard.h" + +Scope (\_SB) +{ + Device (PWRB) + { + Name (_HID, EisaId ("PNP0C0C")) + Name (_UID, 1) + } +} + +/* + * Onboard CPLD + */ +Scope (\_SB.PCI0.LPCB) +{ + Device (CPLD) /* Onboard CPLD */ + { + Name(_HID, EISAID("PNP0C01")) + Name(_CRS, ResourceTemplate() + { + /* Reserve 0x280 to 0x2BF for the CPLD */ + FixedIO (0x0280, 0x40) + IRQNoFlags () {7} + }) + } +} diff --git a/src/mainboard/facebook/fbg1701/acpi/sleepstates.asl b/src/mainboard/facebook/fbg1701/acpi/sleepstates.asl new file mode 100644 index 0000000000..428fda2a01 --- /dev/null +++ b/src/mainboard/facebook/fbg1701/acpi/sleepstates.asl @@ -0,0 +1,20 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2018 Eltan B.V. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Name(\_S0, Package(){0x0,0x0,0x0,0x0}) +Name(\_S4, Package(){0x6,0x6,0x0,0x0}) +Name(\_S5, Package(){0x7,0x7,0x0,0x0}) diff --git a/src/mainboard/facebook/fbg1701/acpi/superio.asl b/src/mainboard/facebook/fbg1701/acpi/superio.asl new file mode 100644 index 0000000000..468c95c531 --- /dev/null +++ b/src/mainboard/facebook/fbg1701/acpi/superio.asl @@ -0,0 +1,47 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Google Inc. + * Copyright (C) 2015 Intel Corp. + * Copyright (C) 2018-2019 Eltan B.V. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* mainboard configuration */ +#include "onboard.h" + +Device (COM1) { + Name (_HID, EISAID ("PNP0501")) + Name (_UID, 1) + Name (_ADR, 0) + + Method (_STA, 0, NotSerialized) + { + Return (0x0F) + } + + Name (_CRS, ResourceTemplate () + { + FixedIO (0x03F8, 0x08) + FixedIO (0x6E, 0x02) + IRQNoFlags () {4} + }) + + Name (_PRS, ResourceTemplate () + { + StartDependentFn (0, 0) { + FixedIO (0x03F8, 0x08) + FixedIO (0x6E, 0x02) + IRQNoFlags () {4} + } + EndDependentFn () + }) +} diff --git a/src/mainboard/facebook/fbg1701/acpi_tables.c b/src/mainboard/facebook/fbg1701/acpi_tables.c new file mode 100644 index 0000000000..15c955afc2 --- /dev/null +++ b/src/mainboard/facebook/fbg1701/acpi_tables.c @@ -0,0 +1,54 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Google Inc. + * Copyright (C) 2015 Intel Corp. + * Copyright (C) 2018 Eltan B.V. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include + +void acpi_create_gnvs(global_nvs_t *gnvs) +{ + acpi_init_gnvs(gnvs); + + /* Enable USB ports in S3 */ + gnvs->s3u0 = 1; + gnvs->s3u1 = 1; + + /* Disable USB ports in S5 */ + gnvs->s5u0 = 0; + gnvs->s5u1 = 0; + + /* Disable DPTF */ + gnvs->dpte = 0; + + /* PMIC is configured in I2C1, hide it for the OS */ + gnvs->dev.lpss_en[LPSS_NVS_I2C2] = 0; +} + +unsigned long acpi_fill_madt(unsigned long current) +{ + /* Local APICs */ + current = acpi_create_madt_lapics(current); + + /* IOAPIC */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, + 2, IO_APIC_ADDR, 0); + + current = acpi_madt_irq_overrides(current); + + return current; +} diff --git a/src/mainboard/facebook/fbg1701/board_info.txt b/src/mainboard/facebook/fbg1701/board_info.txt new file mode 100644 index 0000000000..41d91fd2be --- /dev/null +++ b/src/mainboard/facebook/fbg1701/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Facebook +Board name: FBG-1701 +Category: sbc +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/facebook/fbg1701/cmos.layout b/src/mainboard/facebook/fbg1701/cmos.layout new file mode 100644 index 0000000000..c293c5f989 --- /dev/null +++ b/src/mainboard/facebook/fbg1701/cmos.layout @@ -0,0 +1,121 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2008 coresystems GmbH +## Copyright (C) 2015 Intel Corp. +## Copyright (C) 2018 Eltan B.V. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +# ----------------------------------------------------------------- +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +# ----------------------------------------------------------------- +# Status Register A +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +# ----------------------------------------------------------------- +# Status Register B +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +# ----------------------------------------------------------------- +# Status Register C +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag +# ----------------------------------------------------------------- +# Status Register D +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram +# ----------------------------------------------------------------- +# Diagnostic Status Register +#112 8 r 0 diag_rsvd1 + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory +#120 264 r 0 unused + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +# reboot_counter reserved for core, not used by platform. +384 1 e 4 boot_option +388 4 h 0 reboot_counter +#390 2 r 0 unused + +# ----------------------------------------------------------------- +# coreboot config options: console +#392 3 r 0 unused +395 4 e 6 debug_level +#399 1 r 0 unused + +# coreboot config options: cpu +#400 1 e 2 unused +#401 7 r 0 unused + +# coreboot config options: southbridge +408 1 e 1 nmi +409 2 e 7 power_on_after_fail +#411 5 r 0 unused + +# coreboot config options: bootloader +#416 568 r 0 unused + +# coreboot config options: check sums +984 16 h 0 check_sum +#1000 24 r 0 amd_reserved + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +# ----------------------------------------------------------------- +checksums + +checksum 392 415 984 diff --git a/src/mainboard/facebook/fbg1701/com_init.c b/src/mainboard/facebook/fbg1701/com_init.c new file mode 100644 index 0000000000..f19aba311c --- /dev/null +++ b/src/mainboard/facebook/fbg1701/com_init.c @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. + * Copyright (C) 2018-2019 Eltan B.V. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include "onboard.h" + +#define SERIAL_DEV PNP_DEV(ITE8528_CMD_PORT, 1) /* ITE8528 UART1 */ + +void bootblock_mainboard_early_init(void) +{ + /* Enable the serial port inside the EC */ + pnp_set_logical_device(SERIAL_DEV); + pnp_set_enable(SERIAL_DEV, 1); +} diff --git a/src/mainboard/facebook/fbg1701/devicetree.cb b/src/mainboard/facebook/fbg1701/devicetree.cb new file mode 100644 index 0000000000..3c82a034b4 --- /dev/null +++ b/src/mainboard/facebook/fbg1701/devicetree.cb @@ -0,0 +1,131 @@ +chip soc/intel/braswell + + ############################################################ + # Set the parameters for MemoryInit + ############################################################ + + register "PcdMrcInitTsegSize" = "8" # SMM Region size in MiB + + register "PcdMrcInitMmioSize" = "0x0800" + register "PcdMrcInitSpdAddr1" = "0xa0" + register "PcdMrcInitSpdAddr2" = "0xa2" + register "PcdIgdDvmt50PreAlloc" = "1" + register "PcdApertureSize" = "2" + register "PcdGttSize" = "1" + register "PcdDvfsEnable" = "0" + register "PcdCaMirrorEn" = "1" + + ############################################################ + # Set the parameters for SiliconInit + ############################################################ + + register "PcdSdcardMode" = "PCH_DISABLED" + register "PcdEnableHsuart0" = "0" + register "PcdEnableHsuart1" = "0" + register "PcdEnableAzalia" = "1" + register "PcdEnableXhci" = "1" + register "PcdEnableLpe" = "0" + register "PcdEnableDma0" = "0" + register "PcdEnableDma1" = "0" + register "PcdEnableI2C0" = "0" + register "PcdEnableI2C1" = "0" + register "PcdEnableI2C2" = "0" + register "PcdEnableI2C3" = "0" + register "PcdEnableI2C4" = "0" + register "PcdEnableI2C5" = "0" + register "PcdEnableI2C6" = "0" + register "PunitPwrConfigDisable" = "0" # Enable SVID + register "ChvSvidConfig" = "1" + register "PcdEmmcMode" = "PCH_PCI_MODE" + register "PcdUsb3ClkSsc" = "1" + register "PcdDispClkSsc" = "1" + register "PcdSataClkSsc" = "1" + register "PcdEnableSata" = "0" # Disable SATA + register "Usb2Port0PerPortPeTxiSet" = "7" + register "Usb2Port0PerPortTxiSet" = "5" + register "Usb2Port0IUsbTxEmphasisEn" = "2" + register "Usb2Port0PerPortTxPeHalf" = "1" + register "Usb2Port1PerPortPeTxiSet" = "7" + register "Usb2Port1PerPortTxiSet" = "3" + register "Usb2Port1IUsbTxEmphasisEn" = "2" + register "Usb2Port1PerPortTxPeHalf" = "1" + register "Usb2Port2PerPortPeTxiSet" = "7" + register "Usb2Port2PerPortTxiSet" = "3" + register "Usb2Port2IUsbTxEmphasisEn" = "2" + register "Usb2Port2PerPortTxPeHalf" = "1" + register "Usb2Port3PerPortPeTxiSet" = "7" + register "Usb2Port3PerPortTxiSet" = "3" + register "Usb2Port3IUsbTxEmphasisEn" = "2" + register "Usb2Port3PerPortTxPeHalf" = "1" + register "Usb2Port4PerPortPeTxiSet" = "7" + register "Usb2Port4PerPortTxiSet" = "3" + register "Usb2Port4IUsbTxEmphasisEn" = "2" + register "Usb2Port4PerPortTxPeHalf" = "1" + register "Usb3Lane0Ow2tapgen2deemph3p5" = "0x3a" + register "Usb3Lane1Ow2tapgen2deemph3p5" = "0x64" + register "Usb3Lane2Ow2tapgen2deemph3p5" = "0x64" + register "Usb3Lane3Ow2tapgen2deemph3p5" = "0x3a" + register "PcdSataInterfaceSpeed" = "3" + register "PcdPchSsicEnable" = "1" + register "PcdRtcLock" = "0" # Disable RTC access locking to NVRAM + register "PMIC_I2CBus" = "0" + register "ISPEnable" = "0" # Disable IUNIT + register "ISPPciDevConfig" = "3" + register "PcdSdDetectChk" = "0" # Disable SD card detect + register "DptfDisable" = "1" + + # LPE audio codec settings + register "lpe_codec_clk_src" = "LPE_CLK_SRC_XTAL" # 19.2MHz clock + + # Enable devices in PCI mode + register "lpss_acpi_mode" = "0" + register "emmc_acpi_mode" = "0" + register "sd_acpi_mode" = "0" + register "lpe_acpi_mode" = "0" + + # Disable SLP_X stretching after SUS power well fail. + register "disable_slp_x_stretch_sus_fail" = "1" + + # Allow PCIe devices to wake system from suspend + register "pcie_wake_enable" = "1" + + # CPLD requires continuous mode + register "serirq_mode" = "SERIRQ_CONTINUOUS" + + device cpu_cluster 0 on + device lapic 0 on end + end + + device domain 0 on + device pci 00.0 on end # 8086 2280 - SoC router + device pci 02.0 on end # 8086 22B1 - GFX + device pci 0b.0 off end # 8086 22DC - PUNIT/DPTF + device pci 10.0 on end # 8086 2294 - MMC Port + device pci 12.0 on end # 8086 0F16 - SD Port + device pci 13.0 off end # 8086 22a3 - SATA Port + device pci 14.0 on end # 8086 22b5 - USB XHCI - Only 1 USB controller at a time + device pci 18.0 off end # 8086 22c0 - SIO - DMA + device pci 18.1 off end # 8086 22c1 - I2C Port 1 + device pci 18.2 off end # 8086 22c2 - I2C Port 2 + device pci 18.3 off end # 8086 22c3 - I2C Port 3 + device pci 18.4 off end # 8086 22c4 - I2C Port 4 + device pci 18.5 off end # 8086 22c5 - I2C Port 5 + device pci 18.6 off end # 8086 22c6 - I2C Port 6 + device pci 18.7 off end # 8086 22c7 - I2C Port 7 + device pci 1a.0 on end # 8086 2298 - Trusted Execution Engine + device pci 1b.0 on end # 8086 2284 - HD Audio + device pci 1c.0 on end # 8086 0000 - PCIe Root Port 1 + device pci 1c.1 off end # 8086 0000 - PCIe Root Port 2 + device pci 1c.2 off end # 8086 0000 - PCIe Root Port 3 + device pci 1c.3 on end # 8086 0000 - PCIe Root Port 4 + device pci 1e.0 off end # 8086 2286 - SIO - DMA + device pci 1e.3 off end # 8086 228a - HSUART 1 + device pci 1e.4 off end # 8086 228c - HSUART 2 + device pci 1f.0 on # 8086 229c - LPC bridge + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end + end # LPC Bridge + device pci 1f.3 on end # 8086 2292 - SMBus 0 + end +end diff --git a/src/mainboard/facebook/fbg1701/dsdt.asl b/src/mainboard/facebook/fbg1701/dsdt.asl new file mode 100644 index 0000000000..4eea7b93f4 --- /dev/null +++ b/src/mainboard/facebook/fbg1701/dsdt.asl @@ -0,0 +1,48 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2011 Google Inc. + * Copyright (C) 2015-2018 Intel Corp. + * Copyright (C) 2018 Eltan B.V. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, /* DSDT revision: ACPI v2.0 and up */ + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 /* OEM revision */ +) +{ + /* Some generic macros */ + #include + + /* global NVS and variables */ + #include + + #include + + Scope (\_SB) { + Device (PCI0) + { + #include + } + } + + /* Chipset specific sleep states */ + #include "acpi/sleepstates.asl" + #include "acpi/mainboard.asl" +} diff --git a/src/mainboard/facebook/fbg1701/fadt.c b/src/mainboard/facebook/fbg1701/fadt.c new file mode 100644 index 0000000000..73adfad94c --- /dev/null +++ b/src/mainboard/facebook/fbg1701/fadt.c @@ -0,0 +1,48 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2015 Intel Corp. + * Copyright (C) 2018-2019 Eltan B.V. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) +{ + acpi_header_t *header = &(fadt->header); + + memset((void *) fadt, 0, sizeof(acpi_fadt_t)); + memcpy(header->signature, "FACP", 4); + header->length = sizeof(acpi_fadt_t); + header->revision = 3; + memcpy(header->oem_id, OEM_ID, 6); + memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); + memcpy(header->asl_compiler_id, ASLC, 4); + header->asl_compiler_revision = 1; + + fadt->firmware_ctrl = (unsigned long) facs; + fadt->dsdt = (unsigned long) dsdt; + fadt->preferred_pm_profile = PM_MOBILE; + + fadt->x_firmware_ctl_l = (unsigned long)facs; + fadt->x_firmware_ctl_h = 0; + fadt->x_dsdt_l = (unsigned long)dsdt; + fadt->x_dsdt_h = 0; + + acpi_fill_in_fadt(fadt); + + fadt->iapc_boot_arch &= ~ACPI_FADT_8042; + + header->checksum = + acpi_checksum((void *) fadt, header->length); +} diff --git a/src/mainboard/facebook/fbg1701/gpio.c b/src/mainboard/facebook/fbg1701/gpio.c new file mode 100644 index 0000000000..5a73ca9148 --- /dev/null +++ b/src/mainboard/facebook/fbg1701/gpio.c @@ -0,0 +1,253 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. + * Copyright (C) 2018 Eltan B.V. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +/* South East Community */ +static const struct soc_gpio_map gpse_gpio_map[] = { + Native_M1,/* 00 MF_PLT_CLK0 */ + GPIO_NC, /* 01 PWM1 */ + GPIO_INPUT_NO_PULL, /* 02 MF_PLT_CLK1, RAMID2 */ + GPIO_NC, /* 03 MF_PLT_CLK4 */ + GPIO_NC, /* 04 MF_PLT_CLK3 */ + GPIO_NC, /* PWM0 05 */ + GPIO_NC, /* 06 MF_PLT_CLK5 */ + GPIO_NC, /* 07 MF_PLT_CLK2 */ + GPIO_NC, /* 15 SDMMC2_D3_CD_B */ + Native_M1, /* 16 SDMMC1_CLK */ + NATIVE_PU20K(1), /* 17 SDMMC1_D0 */ + GPIO_NC, /* 18 SDMMC2_D1 */ + GPIO_NC, /* 19 SDMMC2_CLK */ + NATIVE_PU20K(1),/* 20 SDMMC1_D2 */ + GPIO_NC, /* 21 SDMMC2_D2 */ + GPIO_NC, /* 22 SDMMC2_CMD */ + NATIVE_PU20K(1), /* 23 SDMMC1_CMD */ + NATIVE_PU20K(1), /* 24 SDMMC1_D1 */ + GPIO_NC, /* 25 SDMMC2_D0 */ + NATIVE_PU20K(1), /* 26 SDMMC1_D3_CD_B */ + NATIVE_PU20K(1), /* 30 SDMMC3_D1 */ + Native_M1, /* 31 SDMMC3_CLK */ + NATIVE_PU20K(1), /* 32 SDMMC3_D3 */ + NATIVE_PU20K(1), /* 33 SDMMC3_D2 */ + NATIVE_PU20K(1), /* 34 SDMMC3_CMD */ + NATIVE_PU20K(1), /* 35 SDMMC3_D0 */ + NATIVE_PU20K(1), /* 45 MF_LPC_AD2 */ + NATIVE_PU20K(1), /* 46 LPC_CLKRUNB */ + NATIVE_PU20K(1), /* 47 MF_LPC_AD0 */ + Native_M1, /* 48 LPC_FRAMEB */ + Native_M1, /* 49 MF_LPC_CLKOUT1 */ + NATIVE_PU20K(1), /* 50 MF_LPC_AD3 */ + Native_M1, /* 51 MF_LPC_CLKOUT0 */ + NATIVE_PU20K(1), /* 52 MF_LPC_AD1 */ + Native_M1,/* SPI1_MISO */ + Native_M1, /* 61 SPI1_CS0_B */ + Native_M1, /* SPI1_CLK */ + NATIVE_PU20K(1), /* 63 MMC1_D6 */ + Native_M1, /* 62 SPI1_MOSI */ + NATIVE_PU20K(1), /* 65 MMC1_D5 */ + GPIO_NC, /* 66 SPI1_CS1_B */ + NATIVE_PU20K(1), /* 67 MMC1_D4_SD_WE */ + NATIVE_PU20K(1), /* 68 MMC1_D7 */ + GPIO_NC, /* 69 MMC1_RCLK */ + Native_M1, /* 75 GPO USB_OC1_B */ + Native_M1, /* 76 PMU_RESETBUTTON_B */ + GPIO_NC, /* 77 GPIO_ALERT */ + Native_M1, /* 78 SDMMC3_PWR_EN_B */ + Native_M1, /* 79 GPI ILB_SERIRQ */ + Native_M1, /* 80 USB_OC0_B */ + NATIVE_INT_PU20K(1, L1), /* 81 SDMMC3_CD_B */ + Native_M1, /* 82 SPKR */ + Native_M1, /* 83 SUSPWRDNACK */ + SPARE_PIN, /* 84 spare pin */ + Native_M1, /* 85 SDMMC3_1P8_EN */ + GPIO_END +}; + +/* South West Community */ +static const struct soc_gpio_map gpsw_gpio_map[] = { + NATIVE_PU20K(1), /* 00 FST_SPI_D2 */ + NATIVE_PU20K(1), /* 01 FST_SPI_D0 */ + NATIVE_PU20K(1), /* 02 FST_SPI_CLK */ + NATIVE_PU20K(1), /* 03 FST_SPI_D3 */ + NATIVE_PU20K(1), /* 04 FST_SPI_CS1_B */ + NATIVE_PU20K(1), /* 05 FST_SPI_D1 */ + NATIVE_PU20K(1), /* 06 FST_SPI_CS0_B */ + GPIO_NC, /* 07 FST_SPI_CS2_B NC */ + GPIO_NC, /* 15 UART1_RTS_B */ + GPIO_NC, /* 16 UART1_RXD */ + GPIO_NC, /* 17 UART2_RXD */ + GPIO_NC, /* 18 UART1_CTS_B */ + GPIO_NC, /* 19 UART2_RTS_B */ + GPIO_NC, /* 20 UART1_TXD */ + GPIO_NC, /* 21 UART2_TXD */ + GPIO_NC, /* 22 UART2_CTS_B */ + Native_M2, /* 30 MF_HDA_CLK */ + Native_M2, /* 31 MF_HDA_RSTB */ + Native_M2, /* 32 MF_HDA_SDI0 */ + Native_M2, /* 33 MF_HDA_SDO */ + GPIO_NC, /* 34 MF_HDA_DOCKRSTB */ + Native_M2, /* 35 MF_HDA_SYNC */ + GPIO_NC, /* 36 MF_HDA_SDI1 */ + GPIO_NC, /* 37 MF_HDA_DOCKENB */ + GPIO_NC, /* 45 I2C5_SDA */ + GPIO_NC, /* 46 I2C4_SDA */ + GPIO_INPUT_NO_PULL, /* 47 I2C6_SDA SD_WP_1P8*/ + GPIO_NC, /* 48 I2C5_SCL */ + GPIO_NC, /* 49 I2C_NFC_SDA */ + GPIO_NC, /* 50 I2C4_SCL */ + GPIO_NC, /* 51 I2C6_SCL */ + GPIO_NC, /* 52 I2C_NFC_SCL */ + GPIO_NC, /* 60 I2C1_SDA */ + NATIVE_PU1K_CSEN_INVTX(1), /* 61 I2C0_SDA */ + GPIO_NC, /* 62 I2C2_SDA */ + GPIO_NC, /* 63 I2C1_SCL */ + GPIO_NC, /* 64 I2C3_SDA */ + NATIVE_PU1K_CSEN_INVTX(1), /* 65 I2C0_SCL */ + GPIO_NC, /* 66 I2C2_SCL */ + GPIO_NC, /* 67 I2C3_SCL */ + GPIO_NC, /* 75 SATA_GP0 */ + GPIO_NC, /* 76 GPI SATA_GP1 */ + Native_M1, /* 77 SATA_LEDN */ + GPIO_NC, /* 78 SATA_GP2 */ + Native_M1, /* 79 MF_SMB_ALERT_N */ + GPIO_INPUT_NO_PULL, /* 80 SATA_GP3, MMC1_RST */ + Native_M1, /* 81 MF_SMB_CLK */ + Native_M1, /* 82 MF_SMB_DATA */ + Native_M1, /* 90 PCIE_CLKREQ0B */ + Native_M1, /* 91 PCIE_CLKREQ1B */ + GPIO_NC, /* 92 GP_SSP_2_CLK */ + Native_M1, /* 93 PCIE_CLKREQ2B */ + GPIO_NC, /* 94 GP_SSP_2_RXD */ + Native_M1, /* 93 PCIE_CLKREQ3B */ + GPIO_NC, /* 96 GP_SSP_2_FS */ + GPIO_NC, /* 97 GP_SSP_2_TXD */ + GPIO_END +}; + +/* North Community */ +static const struct soc_gpio_map gpn_gpio_map[] = { + GPI(trig_edge_low, L8, NA, non_maskable, en_edge_rx_data, + UNMASK_WAKE, SCI), /* 00 GPIO_DFX0 SMC_EXTSMI_N */ + GPIO_NC, /* 01 GPIO_DFX3 */ + GPIO_NC, /* 02 GPIO_DFX7 */ + GPI(trig_edge_low, L8, NA, non_maskable, en_edge_rx_data, + UNMASK_WAKE, SCI), /* 03 GPIO_DFX1 PM_THRM_N */ + GPI(trig_edge_low, L8, NA, non_maskable, en_edge_rx_data, + UNMASK_WAKE, SCI), /* 04 GPIO_DFX5 LID_N */ + GPIO_NC, /* 05 GPIO_DFX4 */ + GPIO_NC, /* 06 GPIO_DFX8 */ + GPIO_NC, /* 07 GPIO_DFX2 */ + GPI(trig_edge_low, L8, NA, non_maskable, en_edge_rx_data, + UNMASK_WAKE, SCI), /* 08 GPIO_DFX6 WAKE1_N */ + GPI(trig_edge_low, L8, NA, non_maskable, en_edge_rx_data, + UNMASK_WAKE, SCI), /* 15 GPIO_SUS0 */ + GPIO_NC, /* 16 SEC_GPIO_SUS10 */ + GPI(trig_edge_low, L0, P_1K_H, non_maskable, NA, NA, NA), + /* 17 GPIO_SUS3 */ + GPI(trig_edge_low, L1, P_1K_H, non_maskable, NA, UNMASK_WAKE, NA), + /* 18 GPIO_SUS7 */ + GPI(trig_edge_low, L3, P_1K_H, non_maskable, NA, UNMASK_WAKE, NA), + /* 19 GPIO_SUS1 */ + GPIO_NC, /* 20 GPIO_SUS5 */ + GPIO_NC, /* 21 SEC_GPIO_SUS11 */ + GPIO_NC, /* 22 GPIO_SUS4 */ + GPIO_NC, /* 23 SEC_GPIO_SUS8 */ + Native_M6, /* 24 GPIO_SUS2 */ + GPIO_INPUT_PU_5K,/* 25 GPIO_SUS6 */ + Native_M1, /* 26 CX_PREQ_B */ + GPIO_NC, /* 27 SEC_GPIO_SUS9 */ + Native_M1, /* 30 TRST_B */ + Native_M1, /* 31 TCK */ + GPIO_SKIP, /* 32 PROCHOT_B */ + GPIO_SKIP, /* 33 SVID0_DATA */ + Native_M1, /* 34 TMS */ + GPIO_NC, /* 35 CX_PRDY_B_2 */ + GPIO_NC, /* 36 TDO_2 */ + Native_M1, /* 37 CX_PRDY_B */ + GPIO_SKIP, /* 38 SVID0_ALERT_B */ + Native_M1, /* 39 TDO */ + GPIO_SKIP, /* 40 SVID0_CLK */ + Native_M1, /* 41 TDI */ + GPIO_NC, /* 45 GP_CAMERASB05 */ + GPIO_NC, /* 46 GP_CAMERASB02 */ + Native_M2, /* 47 GP_CAMERASB08 */ + GPIO_NC, /* 48 GP_CAMERASB00 */ + GPIO_NC, /* 49 GP_CAMERASBO6 */ + Native_M2, /* 50 GP_CAMERASB10 */ + GPIO_NC, /* 51 GP_CAMERASB03 */ + Native_M2, /* 52 GP_CAMERASB09 */ + GPIO_NC, /* 53 GP_CAMERASB01 */ + GPIO_NC, /* 54 GP_CAMERASB07 */ + Native_M2, /* 55 GP_CAMERASB11 */ + GPIO_NC, /* 56 GP_CAMERASB04 */ + GPIO_NC, /* 60 PANEL0_BKLTEN */ + Native_M1, /* 61 HV_DDI0_HPD */ + GPIO_NC, /* 62 HV_DDI2_DDC_SDA */ + GPIO_NC, /* 63 PANEL1_BKLTCTL */ + Native_M1, /* 64 HV_DDI1_HPD */ + Native_M1, /* 65 PANEL0_BKLTCTL */ + NATIVE_PU20K(1), /* 66 HV_DDI0_DDC_SDA */ + GPIO_NC, /* 67 HV_DDI2_DDC_SCL */ + NATIVE_TX_RX_EN, /* 68 HV_DDI2_HPD */ + GPIO_NC, /* 69 PANEL1_VDDEN */ + GPIO_NC, /* 70 PANEL1_BKLTEN */ + NATIVE_PU20K(1), /* 71 HV_DDI0_DDC_SCL */ + GPIO_NC, /* 72 PANEL0_VDDEN */ + GPIO_END +}; + +/* East Community */ +static const struct soc_gpio_map gpe_gpio_map[] = { + Native_M1, /* 00 PMU_SLP_S3_B */ + GPIO_NC, /* 01 PMU_BATLOW_B */ + Native_M1, /* 02 SUS_STAT_B */ + Native_M1, /* 03 PMU_SLP_S0IX_B */ + Native_M1, /* 04 PMU_AC_PRESENT */ + Native_M1, /* 05 PMU_PLTRST_B */ + Native_M1, /* 06 PMU_SUSCLK */ + GPIO_NC, /* 07 PMU_SLP_LAN_B */ + Native_M1, /* 08 PMU_PWRBTN_B */ + Native_M1, /* 09 PMU_SLP_S4_B */ + NATIVE_FUNC(M1, P_1K_H, NA), /* 10 PMU_WAKE_B */ + GPIO_NC, /* 11 PMU_WAKE_LAN_B */ + GPIO_NC, /* 15 MF_GPIO_3 */ + GPIO_NC, /* 16 MF_GPIO_7 */ + GPIO_NC, /* 17 MF_I2C1_SCL */ + GPIO_NC, /* 18 MF_GPIO_1 */ + GPIO_NC, /* 19 MF_GPIO_5 */ + GPIO_NC, /* 20 MF_GPIO_9 */ + GPIO_NC, /* 21 MF_GPIO_0 */ + GPIO_INPUT_PU_20K, /* 22 MF_GPIO_4 */ + GPIO_NC, /* 23 MF_GPIO_8 */ + GPIO_NC, /* 24 MF_GPIO_2 */ + GPIO_NC, /* 25 MF_GPIO_6 */ + GPIO_NC, /* 26 MF_I2C1_SDA */ + GPIO_END +}; + +static struct soc_gpio_config gpio_config = { + /* BSW */ + .north = gpn_gpio_map, + .southeast = gpse_gpio_map, + .southwest = gpsw_gpio_map, + .east = gpe_gpio_map +}; + +struct soc_gpio_config *mainboard_get_gpios(void) +{ + return &gpio_config; +} diff --git a/src/mainboard/facebook/fbg1701/hda_verb.c b/src/mainboard/facebook/fbg1701/hda_verb.c new file mode 100644 index 0000000000..344443f09a --- /dev/null +++ b/src/mainboard/facebook/fbg1701/hda_verb.c @@ -0,0 +1,78 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Eltan B.V. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +const u32 cim_verb_data[] = { + /* coreboot specific header */ + 0x10EC0298, /* Codec Vendor - Device ID: Realtek ALC298 */ + 0x152D1165, /* Subsystem ID Quanta */ + 0x0000000C, /* Number of jacks */ + + /* HDA Codec Subsystem ID Verb Table */ + AZALIA_SUBVENDOR(0x0, 0x152D1165), + + /* Pin Widget Verb Table */ + + /* Widget node 1 (NID 0x01) */ + 0x0017FF00, + 0x0017FF00, + 0x0017FF00, + 0x0017FF00, + + /* Pin Complex (NID 0x12) DMIC */ + AZALIA_PIN_CFG(0x0, 0x12, 0x90A60130), + + /* Pin Complex (NID 0x13) DMIC */ + AZALIA_PIN_CFG(0x0, 0x13, 0x411111F0), + + /* Pin Complex (NID 0x14) SPEAKER-OUT (Port-D) */ + AZALIA_PIN_CFG(0x0, 0x14, 0x90180110), + + /* Pin Complex (NID 0x17) I2S-OUT */ + AZALIA_PIN_CFG(0x0, 0x17, 0x01011120), + + /* Pin Complex (NID 0x18) MIC1 (Port-B) */ + AZALIA_PIN_CFG(0x0, 0x18, 0x41111F0), + + /* Pin Complex (NID 0x19) I2S-IN */ + AZALIA_PIN_CFG(0x0, 0x19, 0x90870140), + + /* Pin Complex (NID 0x1A) LINE1 (Port-C) */ + AZALIA_PIN_CFG(0x0, 0x1A, 0x411111F0), + + /* Pin Complex (NID 0x1D) PC-BEEP */ + AZALIA_PIN_CFG(0x0, 0x1D, 0x40400001), + + /* Pin Complex (NID 0x1E) SPDIF-OUT */ + AZALIA_PIN_CFG(0x0, 0x1E, 0x411111F0), + + /* Pin Complex (NID 0x1F) SPDIF-IN */ + AZALIA_PIN_CFG(0x0, 0x1F, 0x411111F0), + + /* Pin Complex (NID 0x21) HP-OUT (Port-A) */ + AZALIA_PIN_CFG(0x0, 0x21, 0x411111F0), + + /* POST I2S bypass output SRC */ + 0x0205002D, + 0x0204C020, + 0x0205002D, + 0x0204C020, + +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/facebook/fbg1701/irqroute.c b/src/mainboard/facebook/fbg1701/irqroute.c new file mode 100644 index 0000000000..a4ff6bf2b2 --- /dev/null +++ b/src/mainboard/facebook/fbg1701/irqroute.c @@ -0,0 +1,18 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Eltan B.V. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "irqroute.h" + +DEFINE_IRQ_ROUTES; diff --git a/src/mainboard/facebook/fbg1701/irqroute.h b/src/mainboard/facebook/fbg1701/irqroute.h new file mode 100644 index 0000000000..6b7cb4169e --- /dev/null +++ b/src/mainboard/facebook/fbg1701/irqroute.h @@ -0,0 +1,70 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. + * Copyright (C) 2018 Eltan B.V. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include + +/* + * IR02h GFX INT(A) - PIRQ A + * IR0Bh PUNIT INT(A) - PIRQ F + * IR10h EMMC INT(ABCD) - PIRQ DEFG + * IR11h SDIO INT(A) - PIRQ B + * IR12h SD INT(A) - PIRQ C + * IR13h SATA INT(A) - PIRQ D + * IR14h XHCI INT(A) - PIRQ E + * IR15h LP Audio INT(A) - PIRQ F + * IR17h MMC INT(A) - PIRQ F + * IR18h SIO INT(ABCD) - PIRQ BADC + * IR1Ah TXE INT(A) - PIRQ F + * IR1Bh HD Audio INT(A) - PIRQ G + * IR1Ch PCIe INT(ABCD) - PIRQ EFGH + * IR1Dh EHCI INT(A) - PIRQ D + * IR1Eh SIO INT(ABCD) - PIRQ BDEF + * IR1Fh LPC INT(ABCD) - PIRQ HGBC +*/ +#define PCI_DEV_PIRQ_ROUTES \ + PCI_DEV_PIRQ_ROUTE(GFX_DEV, A, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(PUNIT_DEV, F, F, F, F), \ + PCI_DEV_PIRQ_ROUTE(MMC_DEV, D, E, F, G), \ + PCI_DEV_PIRQ_ROUTE(SD_DEV, C, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(SATA_DEV, D, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(XHCI_DEV, E, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(LPE_DEV, F, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(SIO1_DEV, B, A, D, C), \ + PCI_DEV_PIRQ_ROUTE(TXE_DEV, F, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(HDA_DEV, G, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(PCIE_DEV, E, F, G, H), \ + PCI_DEV_PIRQ_ROUTE(SIO2_DEV, B, D, E, F), \ + PCI_DEV_PIRQ_ROUTE(PCU_DEV, H, G, B, C) + +/* + * Route each PIRQ[A-H] to a PIC IRQ[0-15] + * Reserved: 0, 1, 2, 8, 13 + * PS2 keyboard: 12 + * ACPI/SCI: 9 + * Floppy: 6 + */ +#define PIRQ_PIC_ROUTES \ + PIRQ_PIC(A, 11), \ + PIRQ_PIC(B, 5), \ + PIRQ_PIC(C, 5), \ + PIRQ_PIC(D, 11), \ + PIRQ_PIC(E, 11), \ + PIRQ_PIC(F, 5), \ + PIRQ_PIC(G, 11), \ + PIRQ_PIC(H, 11) diff --git a/src/mainboard/facebook/fbg1701/logo.c b/src/mainboard/facebook/fbg1701/logo.c new file mode 100644 index 0000000000..678d2e2923 --- /dev/null +++ b/src/mainboard/facebook/fbg1701/logo.c @@ -0,0 +1,47 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Patrick Rudolph + * Copyright (C) 2018-2019 Eltan B.V. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include "mainboard.h" + +static char logo_data[1 * MiB]; +static size_t logo_data_sz = 0; + +void *load_logo(size_t *logo_size) +{ + const char *filename = "logo.bmp"; + + if (logo_data_sz != 0) { + if (logo_size) + *logo_size = logo_data_sz; + return (void *)logo_data; + } + + logo_data_sz = cbfs_boot_load_file(filename, logo_data, + sizeof(logo_data), CBFS_TYPE_RAW); + if (logo_data_sz == 0) + return NULL; + + if (logo_size) + *logo_size = logo_data_sz; + + printk(BIOS_DEBUG, "Found a Logo of %zu bytes after decompression\n", + logo_data_sz); + + return (void *)logo_data; +} diff --git a/src/mainboard/facebook/fbg1701/mainboard.c b/src/mainboard/facebook/fbg1701/mainboard.c new file mode 100644 index 0000000000..ff2564d67a --- /dev/null +++ b/src/mainboard/facebook/fbg1701/mainboard.c @@ -0,0 +1,52 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2011 Google Inc. + * Copyright (C) 2015 Intel Corp. + * Copyright (C) 2018-2019 Eltan B.V. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include "onboard.h" +#include "mainboard.h" + +/* + * Declare the resources we are using + */ +static void mainboard_reserve_resources(struct device *dev) +{ + unsigned int idx = 0; + struct resource *res; + + /* + * CPLD: Reserve the IRQ here all others are within the default LPC + * range 0 to 1000h + */ + res = new_resource(dev, idx++); + res->base = 0x7; + res->size = 0x1; + res->flags = IORESOURCE_IRQ | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; +} + +/* + * mainboard_enable is executed as first thing after + * enumerate_buses(). + */ +static void mainboard_enable(struct device *dev) +{ + mainboard_reserve_resources(dev); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/facebook/fbg1701/mainboard.h b/src/mainboard/facebook/fbg1701/mainboard.h new file mode 100644 index 0000000000..e161da0396 --- /dev/null +++ b/src/mainboard/facebook/fbg1701/mainboard.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Eltan B.V. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef MAINBOARD_H +#define MAINBOARD_H + +void *load_logo(size_t *logo_size); + +#endif diff --git a/src/mainboard/facebook/fbg1701/onboard.h b/src/mainboard/facebook/fbg1701/onboard.h new file mode 100644 index 0000000000..d1fd0509a6 --- /dev/null +++ b/src/mainboard/facebook/fbg1701/onboard.h @@ -0,0 +1,36 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. + * Copyright (C) 2018-2019 Eltan B.V. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef ONBOARD_H +#define ONBOARD_H + +/* SD CARD gpio */ +#define SDCARD_CD 81 /* Not used */ + +#define ITE8528_CMD_PORT 0x6E +#define ITE8528_DATA_PORT 0x6F + +/* CPLD definitions */ +#define CPLD_PCB_VERSION_PORT 0x283 +#define CPLD_PCB_VERSION_MASK 0xF0 +#define CPLD_PCB_VERSION_BIT 4 + +#define CPLD_RESET_PORT 0x287 +#define CPLD_CMD_RESET_DSI_BRIDGE_ACTIVE 0x20 +#define CPLD_CMD_RESET_DSI_BRIDGE_INACTIVE 0x00 + +#endif diff --git a/src/mainboard/facebook/fbg1701/ramstage.c b/src/mainboard/facebook/fbg1701/ramstage.c new file mode 100644 index 0000000000..91dfe3b2cf --- /dev/null +++ b/src/mainboard/facebook/fbg1701/ramstage.c @@ -0,0 +1,32 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018-2019 Eltan B.V. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include "mainboard.h" + +void mainboard_silicon_init_params(SILICON_INIT_UPD *params) +{ + if (CONFIG(FSP1_1_DISPLAY_LOGO)) { + size_t logo_len; + void *logo = NULL; + + logo = load_logo(&logo_len); + + if (logo) { + params->PcdLogoPtr = (u32)logo; + params->PcdLogoSize = logo_len; + } + } +} diff --git a/src/mainboard/facebook/fbg1701/romstage.c b/src/mainboard/facebook/fbg1701/romstage.c new file mode 100644 index 0000000000..e2e37d6387 --- /dev/null +++ b/src/mainboard/facebook/fbg1701/romstage.c @@ -0,0 +1,51 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. + * Copyright (C) 2018-2019 Eltan B.V. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +void mainboard_memory_init_params(struct romstage_params *params, + MEMORY_INIT_UPD *memory_params) +{ + struct region_device spd_rdev; + u8 spd_index = 0; + + if (CONFIG(ONBOARD_MICRON_MEM)) + spd_index = 1; + if (get_spd_cbfs_rdev(&spd_rdev, spd_index) < 0) + die("spd.bin not found\n"); + + memory_params->PcdMemoryTypeEnable = MEM_DDR3; + memory_params->PcdMemorySpdPtr = (uintptr_t)rdev_mmap_full(&spd_rdev); + memory_params->PcdMemChannel0Config = 1; /* Memory down */ + memory_params->PcdMemChannel1Config = 2; /* Disabled */ +} + +void mainboard_after_memory_init(void) +{ + printk(BIOS_DEBUG, "%s/%s called\n", __FILE__, __func__); + + /* Disable the Braswell UART hardware for COM1. */ + pci_write_config32(PCI_DEV(0, LPC_DEV, 0), UART_CONT, 0); +} diff --git a/src/mainboard/facebook/fbg1701/spd/MICRON_MT41K512M16HA-125A.spd.hex b/src/mainboard/facebook/fbg1701/spd/MICRON_MT41K512M16HA-125A.spd.hex new file mode 100644 index 0000000000..f18cbc2a87 --- /dev/null +++ b/src/mainboard/facebook/fbg1701/spd/MICRON_MT41K512M16HA-125A.spd.hex @@ -0,0 +1,257 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2019 Eltan B.V. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +# +# 8 Gb DDR3 (1600 MHz 11-11-11) Micron MT41K512M16HA-125:A +# +# SINGLE DIE +# + +# 512MBx16 64Mx16x8 ( 8 bank, 16 Rows, 10 Col, 2 KB page size ) +# 5-6-7-8-9-10-11 +# DDR3L-1600 +# tCk 1.25ns +# tRCD 13.75ns +# tRP 13.75ns +# tRAS 35ns +# tRC 48.75ns +# CL-tRCD-tRP 11-11-11 + +# 0 Number of SPD Bytes used / Total SPD Size / CRC Coverage +# bits[3:0]: 3 = 384 SPD Bytes Used +# bits[6:4]: 1 = 256 SPD Bytes Total +# bit7 : 0 = CRC covers bytes 0 ~ 128 +23 + +# 1 SPD Revision +# 0x10 = Revision 1.0 +10 + +# 2 Key Byte / DRAM Device Type +# bits[7:0]: 0x0c = DDR3 SDRAM +0B + +# 3 Key Byte / Module Type +# bits[3:0]: 3 = SODIMM +# bits[6:4]: 0 = Not hybrid +# bits[7]: 0 = Not hybrid +03 + +# 4 SDRAM CHIP Density and Banks +# bits[3:0]: 5 = 8 Gigabits Total SDRAM capacity per chip +# bits[6:4]: 0 = 3 (8 banks) +# bits[7]: reserverd +05 + +# 5 SDRAM Addressing +# bits[2:0]: 1 = 10 Column Address Bits +# bits[5:3]: 4 = 16 Row Address Bits +# bits[7:6]: 0 = reserved +21 + +# 6 Module Nominal Voltage +# bits[0]: 0 = 1.5V operable +# bits[1]: 1 = 1.35V operable +# bits[2]: 0 = NOT 1.25V operable +# bits[7:3]: reserved +02 + +# 7 Module Organization +# bits[2:0]: 010b = 16 bits SDRAM device +# bits[5:3]: 000b = 1 ranks +# bits[7:6]: reserved +02 + +# 8 Module Memory Bus width +# bits[2:0]: 3 = 64 bits pirmary bus width +# bits[4:3]: 0 = 0 bits bus witdth extension +# bits[7:5]: reserved +03 + +# 9 Fine Timebase (FTB) dividend / divisor +# bits[3:0]: 1 = Divisor +# bits[7:4]: 1 = Dividend +11 + +# 10 Medium Timebase (MTB) dividend +# bits[7:0]: 0 = 1 (timebase 0.125ns) +01 + +# 11 Medium Timebase (MTB) divisor +# bits[7:0]: 8 (timebase 0.125ns) +08 + +# 12 SDRAM Minimum cycle time (tCKmin) +# 0xA tCK = 1.25ns (DDR3-1600 (800 MHz clock)) +0A + +# 13 Reserved +00 + +# 14 CAS Latencies supported, Least Significate Byte +# Support 5,6,7,8,9,10,11 +FE + +# 15 CAS Latencies supported, Most Significate Byte +# No supporting CL 12-18 +00 + +# 16 Minimum CAS Latency Time (tAAmin) +# 0x69 tAA = 13.125ns (offset = 00) DDR3-1600K downbin +69 + +# 17 Minimum Write Recovery Time (tWRmin) +# 0x78 tWR = 15 ns +78 + +# 18 Minimum RAS to CAS Delay Time (tRCDmin) +# 0x69 tRCD = 13.125ns (offset 00) DDR3-1600K downbin +69 + +# 19 Minimum Row Active to Row Active Delay Time (tRRDmin) +# 0x3C tRRD = 7.5ns DDR3-1600, 2KB +3C + +# 20 Minimum Row Precharge Delay Time (tRPmin) +# 0x69 tRP = 13.125ns (offset 00) DDR3-1600K downbin +69 + +# 21 Upper Nibble for tRAS and tRC +# 3:0 : 1 higher tRAS = 35ns +# 7:0 : 1 higher tRC = 48.125ns +11 + +# 22 Minimum Active to Precharge Delay Time (tRASmin), Least Significant byte +# lower 0x118 : tRAS = 35ns DDR3-1600 +18 + +# 23 Minimum Active to Precharge Delay Time (tRCmin), Most Significant byte +# lower 0x181 : tRC = 48.125ns (offset 00) DDR3-1600K downbin +81 + +# 24 Minimum Refresh Recovery Delay time (tRFCmin), Least Significant byte +# lower 0xAF0 : tRFC = 350ns 8 Gb +F0 + +# 25 Minimum Refresh Recovery Delay time (tRFCmin), Most Significant byte +# higher 0xAF0 : tRFC = 350ns 8 Gb +0A + +# 26 tWTRmin +# 0x3C : tWTR = 7.5 ns (DDR3) +3C + +# 27 tRTPmin +# 0x3C : tRTP = 7.5 ns (DDR3) +3C + +# 28 Upper Nibble for tFAW +# Bit [3:0] : 1 = higher 0x140 tFAW = 40ns +01 + +# 29 tFAWmin Lower +# lower 0x140 : tFAW = 40ns +40 + +# 30 SDRAM Optional Features +# byte [0] : 1 = RZQ/6 is support +# byte [1] : 1 = RZQ/7 is supported +# byte [7] : 1 = DLL-Off Mode support +83 + +# 31 Thermal options +# byte [0] : 1 = 0 - 95C +# byte [2] : 1 = Auto Self Refresh (ASR) is supported +# byte [7] : 1 = Partial Array Self Refres (PASR) is supported +85 + +# 32 Module Thermal support +# byte [0] : 0 = Thermal sensor accuracy undefined +# byte [7] : 0 = No thermal sensor +00 + +# 33 SDRAM device type +# byte [1:0] : 00b = Signal Loading not specified +# byte [6:4] : 000b = Die count not specified +# byte [7] : 1 = Non-Standard Device +80 + +# 34 Fine tCKmin +# 0x00 tCK = 1.25ns (DDR3-1600 (800 MHz clock)) +00 + +# 35 Fine tAAmin +# 0x00 tAA = 13.125ns (tAAmin offset = 00) DDR3-1600K downbin +00 + +# 36 Fine tRCDmin +# 0x00 tRCD = 13.125ns DDR3-1600K downbin +00 + +# 37 Fine tRPmin +# 0x00 tRP = 13.125ns (offset 00) DDR3-1600K downbin +00 + +# 38 Fine tRCmin +# 0x00 tRC = 48.125ns (offset 00) DDR3-1600K downbin +00 + +# 39-59 reserved, general section +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 + +# 60-116 Module specific section +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 + +# 117-118 Module Manufacturer +80 2C + +# 119 Module Manufacturing Location +01 + +# 120-121 Module Manufacturing Date +13 0A + +# 122-125 Module Serial number +00 00 00 00 + +# 126-127 SPD CRC +00 00 + +# 128-145 Module Part number +4D 54 34 31 4B 35 31 32 4D 31 36 48 41 2D 31 32 +35 00 + +# 145-146 Module revision code +00 00 + +# 148-149 DRAM Manufacturer ID code +80 2C + +# 150-175 Manufacturer Specific Data +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 + +# 176-255 Open for Customer Use + +# 176 - 255 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/facebook/fbg1701/spd/SAMSUNG_K4B8G1646D-MYKO.spd.hex b/src/mainboard/facebook/fbg1701/spd/SAMSUNG_K4B8G1646D-MYKO.spd.hex new file mode 100644 index 0000000000..64faf1e163 --- /dev/null +++ b/src/mainboard/facebook/fbg1701/spd/SAMSUNG_K4B8G1646D-MYKO.spd.hex @@ -0,0 +1,254 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2018-2019 Eltan B.V. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +# +# 8 Gb DDR3 (1600 MHz 11-11-11) Samsung K4B8G1646D-MYK0 +# +# DUAL DIE +# +# 512Mb x16 ( 8 bank, 16 Rows, 10 Col, 2 KB page size ) +# 5-6-7-8-9-10-11 +# DDR3L-1600 +# tCk 1.25ns +# tRCD 13.75ns +# tRP 13.75ns +# tRAS 35ns +# tRC 48.75ns +# CL-tRCD-tRP 11-11-11 + +# 0 Number of SPD Bytes used / Total SPD Size / CRC Coverage +# bits[3:0]: 3 = 384 SPD Bytes Used +# bits[6:4]: 1 = 256 SPD Bytes Total +# bit7 : 0 = CRC covers bytes 0 ~ 128 +23 + +# 1 SPD Revision +# 0x10 = Revision 1.0 +10 + +# 2 Key Byte / DRAM Device Type +# bits[7:0]: 0x0c = DDR3 SDRAM +0B + +# 3 Key Byte / Module Type +# bits[3:0]: 3 = SODIMM +# bits[6:4]: 0 = Not hybrid +# bits[7]: 0 = Not hybrid +03 + +# 4 SDRAM CHIP Density and Banks +# bits[3:0]: 4 = 4 Gigabits Total SDRAM capacity per chip +# bits[6:4]: 0 = 3 (8 banks) +# bits[7]: reserverd +04 + +# 5 SDRAM Addressing +# bits[2:0]: 1 = 10 Column Address Bits +# bits[5:3]: 100b = 16 Row Address Bits +# bits[7:6]: 0 = reserved +21 + +# 6 Module Nominal Voltage +# bits[0]: 0 = 1.5V operable +# bits[1]: 1 = 1.35V operable +# bits[2]: 0 = NOT 1.25V operable +# bits[7:3]: reserved +02 + +# 7 Module Organization +# bits[2:0]: 010b = 16 bits SDRAM device +# bits[5:3]: 001b = 2 ranks +# bits[7:6]: reserved +0A + +# 8 Module Memory Bus width +# bits[2:0]: 3 = 64 bits pirmary bus width +# bits[4:3]: 0 = 0 bits bus witdth extension +# bits[7:5]: reserved +03 + +# 9 Fine Timebase (FTB) dividend / divisor +# bits[3:0]: 1 = Divisor +# bits[7:4]: 1 = Dividend +11 + +# 10 Medium Timebase (MTB) dividend +# bits[7:0]: 0 = 1 (timebase 0.125ns) +01 + +# 11 Medium Timebase (MTB) divisor +# bits[7:0]: 8 (timebase 0.125ns) +08 + +# 12 SDRAM Minimum cycle time (tCKmin) +# 0xA tCK = 1.25ns (DDR3-1600 (800 MHz clock)) +0A + +# 13 Reserved +00 + +# 14 CAS Latencies supported, Least Significate Byte +# Support 5,6,7,8,9,10,11 +FE + +# 15 CAS Latencies supported, Most Significate Byte +# Not supporting CL 12-18 +00 + +# 16 Minimum CAS Latency Time (tAAmin) +# 0x69 tAA = 13.125ns (offset = 00) DDR3-1600K downbin +69 + +# 17 Minimum Write Recovery Time (tWRmin) +# 0x78 tWR = 15 ns +78 + +# 18 Minimum RAS to CAS Delay Time (tRCDmin) +# 0x69 tRCD = 13.125ns (offset 00) DDR3-1600K downbin +69 + +# 19 Minimum Row Active to Row Active Delay Time (tRRDmin) +# 48 tRRD = 6.0ns DDR3-1600, 1KB +30 + +# 20 Minimum Row Precharge Delay Time (tRPmin) +# 0x69 tRP = 13.125ns (offset 00) DDR3-1600K downbin +69 + +# 21 Upper Nibble for tRAS and tRC +# 3:0 : 1 higher tRAS = 35ns +# 7:0 : 1 higher tRC = 48.125ns +11 + +# 22 Minimum Active to Precharge Delay Time (tRASmin), Least Significant byte +# lower 0x118 : tRAS = 35ns DDR3-1600 +18 + +# 23 Minimum Active to Precharge Delay Time (tRCmin), Most Significant byte +# lower 0x181 : tRC = 48.125ns (offset 00) DDR3-1600K downbin +81 + +# 24 Minimum Refresh Recovery Delay time (tRFCmin), Least Significant byte +# lower 0x680 : tRFC = 208ns 4 Gb +80 + +# 25 Minimum Refresh Recovery Delay time (tRFCmin), Most Significant byte +# higher 0x680 : tRFC = 208ns 4 Gb +06 + +# 26 tWTRmin +# 0x3C : tWTR = 7.5 ns (DDR3) +3C + +# 27 tRTPmin +# 0x3C : tRTP = 7.5 ns (DDR3) +3C + +# 28 Upper Nibble for tFAW +# Bit [3:0] : 1 = higher 0x140 tFAW = 40ns DDR3-1600K, 2 KB page size +01 + +# 29 tFAWmin Lower +# lower 0x140 : tFAW = 40ns DDR3-1600K, 2 KB page size +40 + +# 30 SDRAM Optional Features +# byte [0] : 1 = RZQ/6 is support +# byte [1] : 1 = RZQ/7 is supported +# byte [7] : 1 = DLL-Off Mode support +83 + +# 31 Thermal options +# byte [2]: 1 = Auto Self Refresh (ASR) is supported +04 + +# 32 Module Thermal support +# byte [0] : 0 = Thermal sensor accuracy undefined +# byte [7] : 0 = No thermal sensor +00 + +# 33 SDRAM device type +# byte [1:0] : 01b = multi load stack +# byte [6:4] : 100b = 8 die +# byte [7] : 0 = Standard Device +41 + +# 34 Fine tCKmin +# 0x00 tCK = 1.25ns (DDR3-1600 (800 MHz clock)) +00 + +# 35 Fine tAAmin +# 0x00 tAA = 13.125ns (tAAmin offset = 00) DDR3-1600K downbin +00 + +# 36 Fine tRCDmin +# 0x00 tRCD = 13.125ns DDR3-1600K downbin +00 + +# 37 Fine tRPmin +# 0x00 tRP = 13.125ns (offset 00) DDR3-1600K downbin +00 + +# 38 Fine tRCmin +# 0x00 tRC = 48.125ns (offset 00) DDR3-1600K downbin +00 + +# 39-59 reserved, general section +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 + +# 60-116 Module specific section +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 + +# 117-118 Module Manufacturer +80 CE + +# 119 Module Manufacturing Location +01 + +# 120-121 Module Manufacturing Date +12 1B + +# 122-125 Module Serial number +00 00 00 00 + +# 126-127 SPD CRC +00 00 + +# 128-145 Module Part number +4B 34 42 38 47 31 36 34 36 44 2D 4D 59 4B 30 20 +20 20 + +# 145-146 Module revision code +00 00 + +# 148-149 DRAM Manufacturer ID code +80 CE + +# 150-175 Manufacturer Specific Data +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 + +# 176-255 Open for Customer Use + +# 176 - 255 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/facebook/fbg1701/w25q64.c b/src/mainboard/facebook/fbg1701/w25q64.c new file mode 100644 index 0000000000..bc908f04b3 --- /dev/null +++ b/src/mainboard/facebook/fbg1701/w25q64.c @@ -0,0 +1,78 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015 Intel Corp. + * Copyright (C) 2018 Eltan B.V. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include + +/* + * SPI lockdown configuration + */ +#define SPI_OPMENU_0 CMD_W25_WRSR /* Write Status Register */ +#define SPI_OPTYPE_0 SPI_OPTYPE_WR_NOADDR /* Write, no address */ + +#define SPI_OPMENU_1 CMD_W25_PP /* BYPR: Byte Program */ +#define SPI_OPTYPE_1 SPI_OPTYPE_WR_ADDR /* Write, address required */ + +#define SPI_OPMENU_2 CMD_W25_READ /* Read Data */ +#define SPI_OPTYPE_2 SPI_OPTYPE_RD_ADDR /* Read, address required */ + +#define SPI_OPMENU_3 CMD_W25_RDSR /* Read Status Register */ +#define SPI_OPTYPE_3 SPI_OPTYPE_RD_NOADDR /* Read, no address */ + +#define SPI_OPMENU_4 CMD_W25_SE /* Sector Erase */ +#define SPI_OPTYPE_4 SPI_OPTYPE_WR_ADDR /* Write, address required */ + +#define SPI_OPMENU_5 CMD_W25_RDID /* Read ID */ +#define SPI_OPTYPE_5 SPI_OPTYPE_RD_NOADDR /* Read, no address */ + +#define SPI_OPMENU_6 CMD_W25_BE /* BE: Block Erase */ +#define SPI_OPTYPE_6 SPI_OPTYPE_WR_ADDR /* Write, address required */ + +#define SPI_OPMENU_7 CMD_W25_FAST_READ /* FAST: Fast Read */ +#define SPI_OPTYPE_7 SPI_OPTYPE_RD_ADDR /* Read, address required */ + +#define SPI_OPPREFIX CMD_W25_WREN /* WREN only to be inline */ + /* with flashrom */ + +#define SPI_OPTYPE ((SPI_OPTYPE_7 << 14) | (SPI_OPTYPE_6 << 12) | \ + (SPI_OPTYPE_5 << 10) | (SPI_OPTYPE_4 << 8) | \ + (SPI_OPTYPE_3 << 6) | (SPI_OPTYPE_2 << 4) | \ + (SPI_OPTYPE_1 << 2) | (SPI_OPTYPE_0 << 0)) + +#define SPI_OPMENU_UPPER ((SPI_OPMENU_7 << 24) | (SPI_OPMENU_6 << 16) | \ + (SPI_OPMENU_5 << 8) | (SPI_OPMENU_4 << 0)) + +#define SPI_OPMENU_LOWER ((SPI_OPMENU_3 << 24) | (SPI_OPMENU_2 << 16) | \ + (SPI_OPMENU_1 << 8) | (SPI_OPMENU_0 << 0)) + +#define SPI_VSCC (WG_64_BYTE | EO(0x20) | BES_4_KB) + +static const struct spi_config spi_config = { + .preop = CMD_W25_WREN, + .optype = SPI_OPTYPE, + .opmenu = { SPI_OPMENU_LOWER, SPI_OPMENU_UPPER }, + .lvscc = SPI_VSCC, + .uvscc = SPI_VSCC, +}; + +int mainboard_get_spi_config(struct spi_config *cfg) +{ + memcpy(cfg, &spi_config, sizeof(*cfg)); + + return 0; +} From 1583fcd13fe436e815977f96086412adabcb7dd7 Mon Sep 17 00:00:00 2001 From: Frans Hendriks Date: Wed, 5 Jun 2019 10:18:23 +0200 Subject: [PATCH 330/331] MAINTAINERS: Add maintainer to Facebook FBG1701 Add maintainers to the new mainboard port. Change-Id: I620ea424cc26fa0218a74052863ea30700789e1b Signed-off-by: Frans Hendriks Reviewed-on: https://review.coreboot.org/c/coreboot/+/33224 Tested-by: build bot (Jenkins) Reviewed-by: Philipp Deppenwiese --- MAINTAINERS | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 04f784f889..f1ae076937 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -382,6 +382,12 @@ M: Tristan Corrick S: Maintained F: src/mainboard/supermicro/x10slm-f/ +FACEBOOK FBG1701 MAINBOARD +M: Frans Hendriks +M: Wim Vervoorn +S: Maintained +F: src/mainboard/facebook/fbg1701/ + AMD FAMILY10H & FAMILY15H (NON-AGESA) CPUS & NORTHBRIDGE M: Timothy Pearson S: Supported From 1aac543a7af9e5353becc97853de8b4b1da7d4dd Mon Sep 17 00:00:00 2001 From: Hannah Williams Date: Thu, 16 May 2019 21:32:54 -0700 Subject: [PATCH 331/331] southbridge/intel/fsp_rangeley: Fix wrong parameters passed to outw outw takes (value, addr) not (addr, value) Change-Id: I6c00413ce9b9b6a3d5691d71ade2b12b08538622 Signed-off-by: Hannah Williams Reviewed-on: https://review.coreboot.org/c/coreboot/+/32842 Tested-by: build bot (Jenkins) Reviewed-by: HAOUAS Elyes Reviewed-by: Martin Roth --- src/southbridge/intel/fsp_rangeley/early_init.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/southbridge/intel/fsp_rangeley/early_init.c b/src/southbridge/intel/fsp_rangeley/early_init.c index 32e3bb5f4f..cec7a318bc 100644 --- a/src/southbridge/intel/fsp_rangeley/early_init.c +++ b/src/southbridge/intel/fsp_rangeley/early_init.c @@ -40,8 +40,8 @@ static void rangeley_setup_bars(void) /* Disable the watchdog reboot and turn off the watchdog timer */ write8((void *)(DEFAULT_PBASE + PMC_CFG), read8((void *)(DEFAULT_PBASE + PMC_CFG)) | NO_REBOOT); // disable reboot on timer trigger - outw(DEFAULT_ABASE + TCO1_CNT, inw(DEFAULT_ABASE + TCO1_CNT) | - TCO_TMR_HALT); // disable watchdog timer + outw(inw(DEFAULT_ABASE + TCO1_CNT) | TCO_TMR_HALT, + DEFAULT_ABASE + TCO1_CNT); // disable watchdog timer printk(BIOS_DEBUG, " done.\n");