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Intel Sandybridge: add reserved memory as resources

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Reserved memory resources will get removed from memory table at
the end of write_coreboot_table(),

Change-Id: I02711b4be4f25054bd3361295d8d4dc996b2eb3e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1372
Tested-by: build bot (Jenkins)
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
This commit is contained in:
Kyösti Mälkki
2012-07-26 23:51:20 +03:00
committed by Anton Kochkov
parent 51676b14e8
commit 1ec5e744c6
4 changed files with 28 additions and 17 deletions
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28
src/northbridge/intel/sandybridge/northbridge.c
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@@ -63,19 +63,6 @@ static const int legacy_hole_size_k = 384;
int add_northbridge_resources(struct lb_memory *mem)
{
lb_add_memory_range(mem, LB_MEM_RESERVED,
legacy_hole_base_k * 1024, legacy_hole_size_k * 1024);
#if CONFIG_CHROMEOS_RAMOOPS
lb_add_memory_range(mem, LB_MEM_RESERVED,
CONFIG_CHROMEOS_RAMOOPS_RAM_START,
CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE);
#endif
/* Required for SandyBridge sighting 3715511 */
lb_add_memory_range(mem, LB_MEM_RESERVED, 0x20000000, 0x00200000);
lb_add_memory_range(mem, LB_MEM_RESERVED, 0x40000000, 0x00200000);
return 0;
}
@@ -126,7 +113,7 @@ static void add_fixed_resources(struct device *dev, int index)
printk(BIOS_DEBUG, "Adding UMA memory area base=0x%llx "
"size=0x%llx\n", uma_memory_base, uma_memory_size);
resource = new_resource(dev, index);
resource = new_resource(dev, index++);
resource->base = (resource_t) uma_memory_base;
resource->size = (resource_t) uma_memory_size;
resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE |
@@ -139,12 +126,23 @@ static void add_fixed_resources(struct device *dev, int index)
if (get_pcie_bar(&pcie_config_base, &pcie_config_size)) {
printk(BIOS_DEBUG, "Adding PCIe config bar base=0x%08x "
"size=0x%x\n", pcie_config_base, pcie_config_size);
resource = new_resource(dev, index+1);
resource = new_resource(dev, index++);
resource->base = (resource_t) pcie_config_base;
resource->size = (resource_t) pcie_config_size;
resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE |
IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
}
mmio_resource(dev, index++, legacy_hole_base_k, legacy_hole_size_k);
#if CONFIG_CHROMEOS_RAMOOPS
mmio_resource(dev, index++, CONFIG_CHROMEOS_RAMOOPS_RAM_START >> 10,
CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE >> 10);
#endif
/* Required for SandyBridge sighting 3715511 */
bad_ram_resource(dev, index++, 0x20000000 >> 10, 0x00200000 >> 10);
bad_ram_resource(dev, index++, 0x40000000 >> 10, 0x00200000 >> 10);
}
static void pci_domain_set_resources(device_t dev)