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google/oak: elm: Do not control SPI_LEVEL_ENABLE after elm-rev1

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SPI level shifter is controlled by SRCLKENA0 after elm-rev1.
We don't need to configure it in the bootloader.

BUG=chrome-os-partner:51725
TEST=emerge-elm coreboot

Change-Id: I01ec00965b87ae370b72d3c0521fb37268714cf8
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 3234065e33c46bc2d67a96939422d318919d5e7a
Original-Change-Id: Iafed0cd7562eb5921af6b17f73a067d469143e02
Original-Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/337421
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/14694
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Yidi Lin
2016-04-06 16:28:06 +08:00
committed by Patrick Georgi
parent 374c50e876
commit 1efc72affa
1 changed files with 2 additions and 1 deletions
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3
src/mainboard/google/oak/bootblock.c
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@@ -81,7 +81,8 @@ void bootblock_mainboard_init(void)
nor_set_gpio_pinmux();
/* SPI_LEVEL_ENABLE: Enable 1.8V to 3.3V level shifter for EC SPI bus */
if (board_id() + CONFIG_BOARD_ID_ADJUSTMENT > 4)
if (board_id() + CONFIG_BOARD_ID_ADJUSTMENT > 4 &&
board_id() + CONFIG_BOARD_ID_ADJUSTMENT < 8)
gpio_output(PAD_SRCLKENAI2, 1);
/* Init i2c bus 2 Timing register for TPM */