From 1f0eb6b0dba9b72b0edd2b45c0db8f09d872fa43 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Tue, 11 Jan 2022 16:42:42 +0100 Subject: [PATCH] soc/amd/sabrina/include/iomap: update MMIO device mappings Compared to Cezanne there are 3 more UARTs with DMA controllers. Signed-off-by: Felix Held Change-Id: I3a3d255bb4976a55623f3a161e791e80f1d01c69 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61081 Tested-by: build bot (Jenkins) Reviewed-by: Marshall Dawson --- src/soc/amd/sabrina/include/soc/iomap.h | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/src/soc/amd/sabrina/include/soc/iomap.h b/src/soc/amd/sabrina/include/soc/iomap.h index 7b5f7849d9..0ea2a52fe9 100644 --- a/src/soc/amd/sabrina/include/soc/iomap.h +++ b/src/soc/amd/sabrina/include/soc/iomap.h @@ -1,7 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -/* TODO: Check if this is still correct */ - #ifndef AMD_SABRINA_IOMAP_H #define AMD_SABRINA_IOMAP_H @@ -34,6 +32,12 @@ #define APU_DMAC1_BASE 0xfedc8000 #define APU_UART0_BASE 0xfedc9000 #define APU_UART1_BASE 0xfedca000 +#define APU_DMAC2_BASE 0xfedcc000 +#define APU_DMAC3_BASE 0xfedcd000 +#define APU_UART2_BASE 0xfedce000 +#define APU_UART3_BASE 0xfedcf000 +#define APU_DMAC4_BASE 0xfedd0000 +#define APU_UART4_BASE 0xfedd1000 #define APU_EMMC_BASE 0xfedd5000 #define APU_EMMC_CONFIG_BASE 0xfedd5800