From 1f54599b9875e0de80c8636626bdfbe01646783c Mon Sep 17 00:00:00 2001
From: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com>
Date: Tue, 22 Mar 2022 11:22:02 +0800
Subject: [PATCH] mb/google/brya/var/taeko: Disable GL9763e PCIE port L0s
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GL9763e doesn’t support L0s state, so disable L0s at the root port.

BUG=b:220079865
TEST=Build FW and run stress exceed 2500 cycles.

Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com>
Change-Id: I6ed790c833d1c01a30aed0fd09cac260a3837ead
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62973
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Peichao Wang <pwang12@lenovo.corp-partner.google.com>
---
 src/mainboard/google/brya/variants/taeko/overridetree.cb | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/mainboard/google/brya/variants/taeko/overridetree.cb b/src/mainboard/google/brya/variants/taeko/overridetree.cb
index 75672ae362..b4cda82487 100644
--- a/src/mainboard/google/brya/variants/taeko/overridetree.cb
+++ b/src/mainboard/google/brya/variants/taeko/overridetree.cb
@@ -407,6 +407,7 @@ chip soc/intel/alderlake
 				.clk_src = 0,
 				.clk_req = 0,
 				.flags = PCIE_RP_LTR | PCIE_RP_AER,
+				.pcie_rp_aspm = ASPM_L1,
 			}"
 			chip soc/intel/common/block/pcie/rtd3
 				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D11)"