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libpayload: xhci: Make XHCI stack usable on ARM

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This patch updates the libpayload XHCI stack to run on ARM CPUs (tested
with the DWC3 controller on an Exynos5420). Firstly, it adds support for
64-byte Slot/Endpoint Context sizes. Since the existing context handling
code represented the whole device context as a C struct (whose size has
to be known at compile time), it was necessary to refactor the input and
device context structures to consist of pointers to the actual contexts
instead.

Secondly, it moves all data structures that the xHC accesses through DMA
to cache-coherent memory. With a similar rationale as in the ARM patches
for EHCI, using explicit cache maintenance functions to correctly handle
the actual transfer buffers in all cases is presumably impossible.
Instead this patch also chooses to create a DMA bounce buffer in the
XHCI stack where transfer buffers which are not already cache-coherent
will be copied to/from.

Change-Id: I14e82fffb43b4d52d687b65415f2e33920e088de
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/169453
Reviewed-by: Stefan Reinauer <reinauer@google.com>
(cherry picked from commit 1fa9964063cce6cbd87ba68334806dde8aa2354c)
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6643
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Julius Werner
2013-09-03 17:15:31 -07:00
committed by Isaac Christensen
parent d96541f3fc
commit 1f86434227
7 changed files with 216 additions and 158 deletions
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52
payloads/libpayload/drivers/usb/xhci_debug.c
View File

@@ -40,18 +40,18 @@ xhci_dump_slotctx(const slotctx_t *const sc)
usb_debug(" FIELD2\t0x%08"PRIx32"\n", sc->f2);
usb_debug(" FIELD3\t0x%08"PRIx32"\n", sc->f3);
usb_debug(" FIELD4\t0x%08"PRIx32"\n", sc->f4);
SC_DUMP(ROUTE, *sc);
SC_DUMP(SPEED, *sc);
SC_DUMP(MTT, *sc);
SC_DUMP(HUB, *sc);
SC_DUMP(CTXENT, *sc);
SC_DUMP(RHPORT, *sc);
SC_DUMP(NPORTS, *sc);
SC_DUMP(TTID, *sc);
SC_DUMP(TTPORT, *sc);
SC_DUMP(TTT, *sc);
SC_DUMP(UADDR, *sc);
SC_DUMP(STATE, *sc);
SC_DUMP(ROUTE, sc);
SC_DUMP(SPEED, sc);
SC_DUMP(MTT, sc);
SC_DUMP(HUB, sc);
SC_DUMP(CTXENT, sc);
SC_DUMP(RHPORT, sc);
SC_DUMP(NPORTS, sc);
SC_DUMP(TTID, sc);
SC_DUMP(TTPORT, sc);
SC_DUMP(TTT, sc);
SC_DUMP(UADDR, sc);
SC_DUMP(STATE, sc);
}
void
@@ -63,15 +63,15 @@ xhci_dump_epctx(const epctx_t *const ec)
usb_debug(" TRDQ_L\t0x%08"PRIx32"\n", ec->tr_dq_low);
usb_debug(" TRDQ_H\t0x%08"PRIx32"\n", ec->tr_dq_high);
usb_debug(" FIELD5\t0x%08"PRIx32"\n", ec->f5);
EC_DUMP(STATE, *ec);
EC_DUMP(INTVAL, *ec);
EC_DUMP(CERR, *ec);
EC_DUMP(TYPE, *ec);
EC_DUMP(MBS, *ec);
EC_DUMP(MPS, *ec);
EC_DUMP(DCS, *ec);
EC_DUMP(AVRTRB, *ec);
EC_DUMP(MXESIT, *ec);
EC_DUMP(STATE, ec);
EC_DUMP(INTVAL, ec);
EC_DUMP(CERR, ec);
EC_DUMP(TYPE, ec);
EC_DUMP(MBS, ec);
EC_DUMP(MPS, ec);
EC_DUMP(DCS, ec);
EC_DUMP(AVRTRB, ec);
EC_DUMP(MXESIT, ec);
}
void
@@ -79,19 +79,19 @@ xhci_dump_devctx(const devctx_t *const dc, const u32 ctx_mask)
{
int i;
if (ctx_mask & 1)
xhci_dump_slotctx(&dc->slot);
xhci_dump_slotctx(dc->slot);
for (i = 0; i < SC_GET(CTXENT, dc->slot); ++i) {
if (ctx_mask & (2 << i))
xhci_dump_epctx(&dc->all_eps[i]);
xhci_dump_epctx(dc->ep[i]);
}
}
void
xhci_dump_inputctx(const inputctx_t *const ic)
{
xhci_debug("Input Control add: 0x%08"PRIx32"\n", ic->control.add);
xhci_debug("Input Control drop: 0x%08"PRIx32"\n", ic->control.drop);
xhci_dump_devctx(&ic->dev, ic->control.add);
xhci_debug("Input Control add: 0x%08"PRIx32"\n", *ic->add);
xhci_debug("Input Control drop: 0x%08"PRIx32"\n", *ic->drop);
xhci_dump_devctx(&ic->dev, *ic->add);
}
void