src/superio/ite/it8772f: Separate mainboard from SIO at obj level
Remove #include early_serial.c and rename to early_init.c as no actual UART configuration is done here. Note that this SIO component still hard codes its base address to 0x2e. Change-Id: Ieef32ac7285246717f0519ffed4314ba28cd47dc Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6271 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
This commit is contained in:
Edward O'Callaghan
committed by
Patrick Georgi
Patrick Georgi
parent
d5339ae0b7
commit
1f9653a1bc
@@ -18,4 +18,5 @@
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## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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##
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romstage-$(CONFIG_SUPERIO_ITE_IT8772F) += early_init.c
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ramstage-$(CONFIG_SUPERIO_ITE_IT8772F) += superio.c
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87
src/superio/ite/it8772f/early_init.c
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87
src/superio/ite/it8772f/early_init.c
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@@ -0,0 +1,87 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <arch/io.h>
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#include <device/pnp_def.h>
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#include "it8772f.h"
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/* NOTICE: This file is deprecated, use ite/common instead */
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/* RAMstage equiv */
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/* u8 pnp_read_config(device_t dev, u8 reg) */
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u8 it8772f_sio_read(device_t dev, u8 reg)
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{
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u16 port = dev >> 8;
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outb(reg, port);
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return inb(port + 1);
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}
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/* RAMstage equiv */
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/* void pnp_write_config(device_t dev, u8 reg, u8 value) */
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void it8772f_sio_write(device_t dev, u8 reg, u8 value)
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{
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u16 port = dev >> 8;
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outb(reg, port);
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outb(value, port + 1);
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}
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void it8772f_enter_conf(device_t dev)
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{
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u16 port = dev >> 8;
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outb(0x87, port);
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outb(0x01, port);
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outb(0x55, port);
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outb((port == 0x4e) ? 0xaa : 0x55, port);
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}
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void it8772f_exit_conf(device_t dev)
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{
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it8772f_sio_write(dev, IT8772F_CONFIG_REG_CC, 0x02);
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}
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/* Set AC resume to be up to the Southbridge */
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void it8772f_ac_resume_southbridge(device_t dev)
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{
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it8772f_enter_conf(dev);
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it8772f_sio_write(dev, IT8772F_CONFIG_REG_LDN, IT8772F_EC);
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it8772f_sio_write(dev, 0xf4, 0x60);
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it8772f_exit_conf(dev);
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}
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/* Configure a set of GPIOs */
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void it8772f_gpio_setup(device_t dev, int set, u8 select, u8 polarity,
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u8 pullup, u8 output, u8 enable)
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{
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set--; /* Set 1 is offset 0 */
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it8772f_enter_conf(dev);
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it8772f_sio_write(dev, IT8772F_CONFIG_REG_LDN, IT8772F_GPIO);
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if (set < 5) {
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it8772f_sio_write(dev, GPIO_REG_SELECT(set), select);
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it8772f_sio_write(dev, GPIO_REG_ENABLE(set), enable);
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it8772f_sio_write(dev, GPIO_REG_POLARITY(set), polarity);
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}
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it8772f_sio_write(dev, GPIO_REG_OUTPUT(set), output);
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it8772f_sio_write(dev, GPIO_REG_PULLUP(set), pullup);
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it8772f_exit_conf(dev);
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}
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@@ -1,88 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <arch/io.h>
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#include <device/pnp_def.h>
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#include "it8772f.h"
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/* NOTICE: This file is deprecated, use ite/common instead */
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/* The base address is 0x2e or 0x4e, depending on config bytes. */
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/* FIXME: SUPERIO include.c */
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#define SIO_BASE 0x2e
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#define SIO_INDEX SIO_BASE
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#define SIO_DATA (SIO_BASE + 1)
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/* Global configuration registers. */
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#define IT8772F_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */
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#define IT8772F_CONFIG_REG_LDN 0x07 /* Logical Device Number. */
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u8 it8772f_sio_read(u8 index)
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{
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outb(index, SIO_BASE);
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return inb(SIO_DATA);
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}
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void it8772f_sio_write(u8 index, u8 value)
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{
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outb(index, SIO_BASE);
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outb(value, SIO_DATA);
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}
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static void it8772f_enter_conf(void)
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{
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u16 port = SIO_BASE;
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outb(0x87, port);
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outb(0x01, port);
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outb(0x55, port);
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outb((port == 0x4e) ? 0xaa : 0x55, port);
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}
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static void it8772f_exit_conf(void)
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{
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it8772f_sio_write(IT8772F_CONFIG_REG_CC, 0x02);
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}
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/* Set AC resume to be up to the Southbridge */
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void it8772f_ac_resume_southbridge(void)
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{
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it8772f_enter_conf();
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it8772f_sio_write(IT8772F_CONFIG_REG_LDN, IT8772F_EC);
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it8772f_sio_write(0xf4, 0x60);
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it8772f_exit_conf();
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}
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/* Configure a set of GPIOs */
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void it8772f_gpio_setup(int set, u8 select, u8 polarity, u8 pullup,
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u8 output, u8 enable)
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{
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set--; /* Set 1 is offset 0 */
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it8772f_enter_conf();
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it8772f_sio_write(IT8772F_CONFIG_REG_LDN, IT8772F_GPIO);
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if (set < 5) {
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it8772f_sio_write(GPIO_REG_SELECT(set), select);
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it8772f_sio_write(GPIO_REG_ENABLE(set), enable);
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it8772f_sio_write(GPIO_REG_POLARITY(set), polarity);
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}
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it8772f_sio_write(GPIO_REG_OUTPUT(set), output);
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it8772f_sio_write(GPIO_REG_PULLUP(set), pullup);
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it8772f_exit_conf();
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}
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@@ -103,10 +103,21 @@
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#define GPIO_REG_ENABLE(x) (0xc0 + (x))
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#define GPIO_REG_OUTPUT(x) (0xc8 + (x))
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u8 it8772f_sio_read(u8 index);
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void it8772f_sio_write(u8 index, u8 value);
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void it8772f_ac_resume_southbridge(void);
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void it8772f_gpio_setup(int set, u8 func_select, u8 polarity, u8 pullup,
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u8 output, u8 enable);
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#include <arch/io.h>
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#include <stdint.h>
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u8 it8772f_sio_read(device_t dev, u8 reg);
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void it8772f_sio_write(device_t dev, u8 reg, u8 value);
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void it8772f_ac_resume_southbridge(device_t dev);
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void it8772f_gpio_setup(device_t dev, int set, u8 select, u8 polarity,
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u8 pullup, u8 output, u8 enable);
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/* FIXME: should be static so will be removed later.. */
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/* Global configuration registers. */
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#define IT8772F_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */
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#define IT8772F_CONFIG_REG_LDN 0x07 /* Logical Device Number. */
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void it8772f_enter_conf(device_t dev);
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void it8772f_exit_conf(device_t dev);
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#endif /* SUPERIO_ITE_IT8772F_H */
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