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cpu/intel/slot_1: Move to C_ENVIRONMENT_BOOTBLOCK

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Console is not yet enabled in bootblock. This will be done in
a different CL.

Change-Id: Ic751d42a1969fb79fb50366f766d8796846a0bc4
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This commit is contained in:
Arthur Heymans
2019-11-12 12:05:38 +01:00
committed by Patrick Georgi
parent df0c731e68
commit 1fa240a3c5
7 changed files with 21 additions and 12 deletions
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4
src/cpu/intel/car/p3/cache_as_ram.S
View File

@@ -18,14 +18,10 @@
#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE
#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
#if !CONFIG(ROMCC_BOOTBLOCK)
#if ((CONFIG_C_ENV_BOOTBLOCK_SIZE & (CONFIG_C_ENV_BOOTBLOCK_SIZE - 1)) != 0)
#error "CONFIG_C_ENV_BOOTBLOCK_SIZE must be a power of 2!"
#endif
#define XIP_ROM_SIZE CONFIG_C_ENV_BOOTBLOCK_SIZE
#else
#define XIP_ROM_SIZE CONFIG_XIP_ROM_SIZE
#endif
.global bootblock_pre_c_entry

9
src/cpu/intel/slot_1/Kconfig
View File

@@ -27,7 +27,6 @@ config SLOT_SPECIFIC_OPTIONS # dummy
select UDELAY_TSC
select TSC_MONOTONIC_TIMER
select UNKNOWN_TSC_RATE
select ROMCC_BOOTBLOCK
config DCACHE_RAM_BASE
hex
@@ -37,4 +36,12 @@ config DCACHE_RAM_SIZE
hex
default 0x02000
config DCACHE_BSP_STACK_SIZE
hex
default 0x1000
config C_ENV_BOOTBLOCK_SIZE
hex
default 0x2000
endif

3
src/cpu/intel/slot_1/Makefile.inc
View File

@@ -26,6 +26,7 @@ subdirs-y += ../../x86/cache
subdirs-y += ../../x86/smm
subdirs-y += ../microcode
cpu_incs-y += $(src)/cpu/intel/car/p3/cache_as_ram.S
bootblock-y += ../car/p3/cache_as_ram.S
bootblock-y += ../car/bootblock.c
postcar-y += ../car/p4-netburst/exit_car.S
romstage-y += ../car/romstage.c