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northbridge/intel/fsp_sandybridge: Add space around operators

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Change-Id: I1b5cdfaf39be639a7ef71e66e91284fa186fbb86
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16630
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Elyes HAOUAS
2016-09-17 20:43:41 +02:00
committed by Martin Roth
parent 9a9c8dba8d
commit 2051448359
5 changed files with 6 additions and 6 deletions
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2
src/northbridge/intel/fsp_sandybridge/acpi.c
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@@ -41,7 +41,7 @@ unsigned long acpi_fill_mcfg(unsigned long current)
if (!dev) if (!dev)
return current; return current;
pciexbar_reg=pci_read_config32(dev, PCIEXBAR); pciexbar_reg = pci_read_config32(dev, PCIEXBAR);
// MMCFG not supported or not enabled. // MMCFG not supported or not enabled.
if (!(pciexbar_reg & (1 << 0))) if (!(pciexbar_reg & (1 << 0)))

2
src/northbridge/intel/fsp_sandybridge/acpi/hostbridge.asl
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@@ -134,7 +134,7 @@ Device (MCHC)
} }
/* /*
* Search CPU0 _PSS looking for control=arg0 and then * Search CPU0 _PSS looking for control = arg0 and then
* return previous P-state entry number for new _PPC * return previous P-state entry number for new _PPC
* *
* Format of _PSS: * Format of _PSS:

2
src/northbridge/intel/fsp_sandybridge/fsp/chipset_fsp_util.c
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@@ -95,7 +95,7 @@ void chipset_fsp_early_init(FSP_INIT_PARAMS *FspInitParams,
void ChipsetFspReturnPoint(EFI_STATUS Status, void ChipsetFspReturnPoint(EFI_STATUS Status,
VOID *HobListPtr) VOID *HobListPtr)
{ {
*(void **)CBMEM_FSP_HOB_PTR=HobListPtr; *(void **)CBMEM_FSP_HOB_PTR = HobListPtr;
if (Status == 0xFFFFFFFF) { if (Status == 0xFFFFFFFF) {
hard_reset(); hard_reset();
} }

4
src/northbridge/intel/fsp_sandybridge/gma.c
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@@ -31,7 +31,7 @@
u32 map_oprom_vendev(u32 vendev) u32 map_oprom_vendev(u32 vendev)
{ {
u32 new_vendev=vendev; u32 new_vendev = vendev;
switch (vendev) { switch (vendev) {
case 0x80860102: /* GT1 Desktop */ case 0x80860102: /* GT1 Desktop */
@@ -41,7 +41,7 @@ u32 map_oprom_vendev(u32 vendev)
case 0x80860122: /* GT2 Desktop >=1.3GHz */ case 0x80860122: /* GT2 Desktop >=1.3GHz */
case 0x80860126: /* GT2 Mobile >=1.3GHz */ case 0x80860126: /* GT2 Mobile >=1.3GHz */
case 0x80860166: /* IVB */ case 0x80860166: /* IVB */
new_vendev=0x80860106; /* GT1 Mobile */ new_vendev = 0x80860106; /* GT1 Mobile */
break; break;
} }

2
src/northbridge/intel/fsp_sandybridge/udelay.c
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@@ -19,7 +19,7 @@
#include <cpu/x86/msr.h> #include <cpu/x86/msr.h>
/** /**
* Intel SandyBridge/IvyBridge CPUs always run the TSC at BCLK=100MHz * Intel SandyBridge/IvyBridge CPUs always run the TSC at BCLK = 100MHz
*/ */
void udelay(u32 us) void udelay(u32 us)