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skylake: Add function to set PRR for protecting flash

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Add a function similar to broadwell to set the PRR for a region of
flash and protect it from writes.  This is used to secure the MRC
cache region if the SPI is write protected.

BUG=chrome-os-partner:54003
BRANCH=glados
TEST=boot on chell, verify PRR register is set and that the
MRC cache region cannot be written if the SPI is write protected.

Change-Id: I925ec9ce186f7adac327bca9c96255325b7f54ec
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Commit-Id: abb6f645f5ceef3f52bb7afd2632212ea916ff8d
Original-Change-Id: I2f90556a217b35b7c93645e41a1fcfe8070c53da
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/349274
Original-Reviewed-by: Shawn N <shawnn@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-on: https://review.coreboot.org/15102
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This commit is contained in:
Duncan Laurie
2016-06-02 15:23:42 -07:00
parent 8a14c39ac6
commit 205ed2d2b5
3 changed files with 51 additions and 1 deletions
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1
src/soc/intel/skylake/Kconfig
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@@ -25,6 +25,7 @@ config CPU_SPECIFIC_OPTIONS
select MMCONF_SUPPORT
select MMCONF_SUPPORT_DEFAULT
select NO_FIXED_XIP_ROM_SIZE
select MRC_SETTINGS_PROTECT
select PARALLEL_MP
select PCIEXP_ASPM
select PCIEXP_COMMON_CLOCK