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soc/intel/apollolake: Use common systemagent code

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This patch perform resource mapping for PCI,
fixed MMIO, DRAM and IMR's based on inputs given by SoC.

TEST=Ensure PCI root bridge 0:0:0 memory resource allocation
remains same between previous implementation and current
implementation.

Change-Id: I15a3b2fc46ec9063b54379d41996b9a1d612cfd2
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/19795
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Subrata Banik
2017-05-19 18:38:24 +05:30
committed by Martin Roth
parent 46a7178267
commit 208587e0f6
7 changed files with 66 additions and 204 deletions
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9
src/soc/intel/apollolake/chip.c
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@ -219,7 +219,6 @@ static void set_power_limits(void)
uint32_t power_unit;
uint32_t tdp, min_power, max_power;
uint32_t pl2_val;
uint32_t *rapl_mmio_reg;
if (!dev || !dev->chip_info) {
printk(BIOS_ERR, "BUG! Could not find SOC devicetree config\n");
@ -272,15 +271,11 @@ static void set_power_limits(void)
printk(BIOS_INFO, "RAPL PL2 %d.%dW\n", pl2_val / power_unit,
100 * (pl2_val % power_unit) / power_unit);
/* Get the MMIO address */
rapl_mmio_reg = (void *)(uintptr_t) (MCH_BASE_ADDRESS +
MCHBAR_RAPL_PPL);
/* Setting RAPL MMIO register for Power limits.
* RAPL driver is using MSR instead of MMIO.
* So, disabled LIMIT_EN bit for MMIO. */
write32(rapl_mmio_reg, limit.lo & ~(PKG_POWER_LIMIT_EN));
write32(rapl_mmio_reg + 1, limit.hi & ~(PKG_POWER_LIMIT_EN));
MCHBAR32(MCHBAR_RAPL_PPL) = limit.lo & ~PKG_POWER_LIMIT_EN;
MCHBAR32(MCHBAR_RAPL_PPL + 4) = limit.hi & ~PKG_POWER_LIMIT_EN;
}
static void soc_init(void *data)