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mb/amd/mayan: Enable MXM PCIe slot

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Follow the EC GPIO programming sequence to enable the MXM PCIe slot.

Change-Id: I75d7ac488bb005751e6f674ab9a2fd99baad571b
Signed-off-by: Anand Vaikar <a.vaikar2021@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74308
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
This commit is contained in:
Anand Vaikar 2023-04-12 12:09:37 +05:30 committed by Felix Held
parent 383c4e7530
commit 20d658e53c
2 changed files with 19 additions and 1 deletions
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1
src/mainboard/amd/mayan/devicetree_phoenix.cb
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@ -158,6 +158,7 @@ chip soc/amd/phoenix
device domain 0 on
device ref iommu on end
device ref gpp_bridge_1_1 on end # MXM
device ref gpp_bridge_2_1 on end # GBE
device ref gpp_bridge_2_2 on end # WIFI
device ref gpp_bridge_2_4 on end # NVMe SSD

19
src/mainboard/amd/mayan/ec.c
View File

@ -8,7 +8,14 @@
#define MAYAN_EC_CMD 0x666
#define MAYAN_EC_DATA 0x662
#define EC_GPIO_1_ADDR 0xA1
#define EC_GPIO_EVAL_PWREN BIT(1)
#define EC_GPIO_2_ADDR 0xA2
#define EC_GPIO_EVAL_SLOT_PWR BIT(5)
#define EC_GPIO_3_ADDR 0xA3
#define EC_GPIO_EVAL_RST_AUX BIT(0)
#define EC_GPIO_LOM_RESET_AUX BIT(1)
#define EC_GPIO_7_ADDR 0xA7
@ -35,8 +42,18 @@ static void configure_ec_gpio(void)
{
uint8_t tmp;
/* Enable MXM slot: set EC_GPIO_EVAL_PWREN, EC_GPIO_EVAL_SLOT_PWR
and EC_GPIO_EVAL_RST_AUX */
tmp = ec_read(EC_GPIO_1_ADDR);
tmp |= EC_GPIO_EVAL_PWREN;
ec_write(EC_GPIO_1_ADDR, tmp);
tmp = ec_read(EC_GPIO_2_ADDR);
tmp |= EC_GPIO_EVAL_SLOT_PWR;
ec_write(EC_GPIO_2_ADDR, tmp);
tmp = ec_read(EC_GPIO_3_ADDR);
tmp |= EC_GPIO_LOM_RESET_AUX;
tmp |= EC_GPIO_LOM_RESET_AUX | EC_GPIO_EVAL_RST_AUX;
ec_write(EC_GPIO_3_ADDR, tmp);
tmp = ec_read(EC_GPIO_7_ADDR);