Rename coreboot_ram stage to ramstage

Rename coreboot_ram stage to ramstage. This is done in order to provide
consistency with other stage names (bootblock, romstage) and to allow any
Makefile rule generalization, required for patches to be submitted later.

Change-Id: Ib66e43b7e17b9c48b2d099670ba7e7d857673386
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: http://review.coreboot.org/5567
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

src/cpu/intel/fsp_model_206ax/cache_as_ram.inc

@@ -162,7 +162,7 @@ _clear_mtrrs_:
 	post_code(0x38)
 
 	/* Enable Write Back and Speculative Reads for the first MB
-	 * and coreboot_ram.
+	 * and ramstage.
 	 */
 	movl	$MTRRphysBase_MSR(0), %ecx
 	movl	$(0x00000000 | MTRR_TYPE_WRBACK), %eax

src/cpu/intel/model_2065x/cache_as_ram.inc

@@ -227,7 +227,7 @@ before_romstage:
 	post_code(0x38)
 
 	/* Enable Write Back and Speculative Reads for the first MB
-	 * and coreboot_ram.
+	 * and ramstage.
 	 */
 	movl	$MTRRphysBase_MSR(0), %ecx
 	movl	$(0x00000000 | MTRR_TYPE_WRBACK), %eax

src/cpu/intel/model_206ax/cache_as_ram.inc

@@ -239,7 +239,7 @@ before_romstage:
 	post_code(0x38)
 
 	/* Enable Write Back and Speculative Reads for the first MB
-	 * and coreboot_ram.
+	 * and ramstage.
 	 */
 	movl	$MTRRphysBase_MSR(0), %ecx
 	movl	$(0x00000000 | MTRR_TYPE_WRBACK), %eax