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vendorcode/intel: Add edk2-stable202111 support

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This patch includes (edk2/edk2-stable202111) all required
headers for edk2-stable202111 EDK2 tag from EDK2 github
project using below command:

>> git clone -b edk2-stable202111 https://github.com/tianocore/edk2.git

commit hash: bb1bba3d776733c41dbfa2d1dc0fe234819a79f2

Only include necessary header files.

MdePkg/Include/Base.h was updated to avoid compilation errors
through safeguarding definitions for MIN, MAX, NULL, ABS, ARRAY_SIZE.

Note: edk2-stable202111 tag is required to adopt FSP 2.3 specification.
- Need to add ExtendedImageRevision in FSP_INFO_HEADER structure.
- Need to add FSP_NON_VOLATILE_STORAGE_HOB2 header.

Change-Id: I786cc05f9a638ac6226ebc8c0eaf1dc8189a4ca4
Signed-off-by: Subrata Banik <subi.banik@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59986
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
This commit is contained in:
Subrata Banik
2021-12-09 02:46:38 +05:30
committed by Subrata Banik
parent dd1ee27503
commit 20fe24b4f7
583 changed files with 237673 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

9
src/vendorcode/intel/Kconfig
View File

@@ -19,6 +19,10 @@ config UDK_202005_BINDING
def_bool n
select UDK_BASE
config UDK_202111_BINDING
def_bool n
select UDK_BASE
if UDK_BASE
config UDK_2013_VERSION
int
@@ -36,8 +40,13 @@ config UDK_202005_VERSION
int
default 202005
config UDK_202111_VERSION
int
default 202111
config UDK_VERSION
int
default UDK_202111_VERSION if UDK_202111_BINDING
default UDK_202005_VERSION if UDK_202005_BINDING
default UDK_2017_VERSION if UDK_2017_BINDING
default UDK_2015_VERSION if UDK_2015_BINDING

5
src/vendorcode/intel/Makefile.inc
View File

@@ -24,4 +24,9 @@ CPPFLAGS_x86_32 += -I$(src)/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Inclu
CPPFLAGS_x86_64 += -I$(src)/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/X64
CPPFLAGS_common += -I$(src)/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include
CPPFLAGS_common += -I$(src)/vendorcode/intel/edk2/edk2-stable202005/IntelFsp2Pkg/Include
else ifeq ($(CONFIG_UDK_202111_BINDING),y)
CPPFLAGS_x86_32 += -I$(src)/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Ia32
CPPFLAGS_x86_64 += -I$(src)/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/X64
CPPFLAGS_common += -I$(src)/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include
CPPFLAGS_common += -I$(src)/vendorcode/intel/edk2/edk2-stable202111/IntelFsp2Pkg/Include
endif

18
src/vendorcode/intel/edk2/edk2-stable202111/IntelFsp2Pkg/Include/FspEas.h Normal file
View File

@@ -0,0 +1,18 @@
/** @file
Intel FSP definition from Intel Firmware Support Package External
Architecture Specification v2.0.
Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef _FSP_EAS_H_
#define _FSP_EAS_H_
#include <Uefi/UefiBaseType.h>
#include <Guid/GuidHobFspEas.h>
#include <Guid/FspHeaderFile.h>
#include <FspEas/FspApi.h>
#endif

485
src/vendorcode/intel/edk2/edk2-stable202111/IntelFsp2Pkg/Include/FspEas/FspApi.h Normal file
View File

@@ -0,0 +1,485 @@
/** @file
Intel FSP API definition from Intel Firmware Support Package External
Architecture Specification v2.0 - v2.2
Copyright (c) 2014 - 2020, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef _FSP_API_H_
#define _FSP_API_H_
#include <Pi/PiStatusCode.h>
///
/// FSP Reset Status code
/// These are defined in FSP EAS v2.0 section 11.2.2 - OEM Status Code
/// @{
#define FSP_STATUS_RESET_REQUIRED_COLD 0x40000001
#define FSP_STATUS_RESET_REQUIRED_WARM 0x40000002
#define FSP_STATUS_RESET_REQUIRED_3 0x40000003
#define FSP_STATUS_RESET_REQUIRED_4 0x40000004
#define FSP_STATUS_RESET_REQUIRED_5 0x40000005
#define FSP_STATUS_RESET_REQUIRED_6 0x40000006
#define FSP_STATUS_RESET_REQUIRED_7 0x40000007
#define FSP_STATUS_RESET_REQUIRED_8 0x40000008
/// @}
///
/// FSP Event related definition.
///
#define FSP_EVENT_CODE 0xF5000000
#define FSP_POST_CODE (FSP_EVENT_CODE | 0x00F80000)
/*
FSP may optionally include the capability of generating events messages to aid in the debugging of firmware issues.
These events fall under three catagories: Error, Progress, and Debug. The event reporting mechanism follows the
status code services described in section 6 and 7 of the PI Specification v1.7 Volume 3.
@param[in] Type Indicates the type of event being reported.
See MdePkg/Include/Pi/PiStatusCode.h for the definition of EFI_STATUS_CODE_TYPE.
@param[in] Value Describes the current status of a hardware or software entity.
This includes information about the class and subclass that is used to classify the entity as well as an operation.
For progress events, the operation is the current activity. For error events, it is the exception.
For debug events, it is not defined at this time.
See MdePkg/Include/Pi/PiStatusCode.h for the definition of EFI_STATUS_CODE_VALUE.
@param[in] Instance The enumeration of a hardware or software entity within the system.
A system may contain multiple entities that match a class/subclass pairing. The instance differentiates between them.
An instance of 0 indicates that instance information is unavailable, not meaningful, or not relevant.
Valid instance numbers start with 1.
@param[in] *CallerId This parameter can be used to identify the sub-module within the FSP generating the event.
This parameter may be NULL.
@param[in] *Data This optional parameter may be used to pass additional data. The contents can have event-specific data.
For example, the FSP provides a EFI_STATUS_CODE_STRING_DATA instance to this parameter when sending debug messages.
This parameter is NULL when no additional data is provided.
@retval EFI_SUCCESS The event was handled successfully.
@retval EFI_INVALID_PARAMETER Input parameters are invalid.
@retval EFI_DEVICE_ERROR The event handler failed.
*/
typedef
EFI_STATUS
(EFIAPI *FSP_EVENT_HANDLER) (
IN EFI_STATUS_CODE_TYPE Type,
IN EFI_STATUS_CODE_VALUE Value,
IN UINT32 Instance,
IN OPTIONAL EFI_GUID *CallerId,
IN OPTIONAL EFI_STATUS_CODE_DATA *Data
);
/*
Handler for FSP-T debug log messages, provided by the bootloader.
@param[in] DebugMessage A pointer to the debug message to be written to the log.
@param[in] MessageLength Number of bytes to written to the debug log.
@retval UINT32 The return value indicates the number of bytes actually written to
the debug log. If the return value is less than MessageLength,
an error occurred.
*/
typedef
UINT32
(EFIAPI *FSP_DEBUG_HANDLER) (
IN CHAR8* DebugMessage,
IN UINT32 MessageLength
);
#pragma pack(1)
///
/// FSP_UPD_HEADER Configuration.
///
typedef struct {
///
/// UPD Region Signature. This signature will be
/// "XXXXXX_T" for FSP-T
/// "XXXXXX_M" for FSP-M
/// "XXXXXX_S" for FSP-S
/// Where XXXXXX is an unique signature
///
UINT64 Signature;
///
/// Revision of the Data structure.
/// For FSP spec 2.0/2.1 value is 1.
/// For FSP spec 2.2 value is 2.
///
UINT8 Revision;
UINT8 Reserved[23];
} FSP_UPD_HEADER;
///
/// FSPT_ARCH_UPD Configuration.
///
typedef struct {
///
/// Revision Revision of the structure is 1 for this version of the specification.
///
UINT8 Revision;
UINT8 Reserved[3];
///
/// Length Length of the structure in bytes. The current value for this field is 32.
///
UINT32 Length;
///
/// FspDebugHandler Optional debug handler for the bootloader to receive debug messages
/// occurring during FSP execution.
///
FSP_DEBUG_HANDLER FspDebugHandler;
UINT8 Reserved1[20];
} FSPT_ARCH_UPD;
///
/// FSPM_ARCH_UPD Configuration.
///
typedef struct {
///
/// Revision of the structure. For FSP v2.0 value is 1.
///
UINT8 Revision;
UINT8 Reserved[3];
///
/// Pointer to the non-volatile storage (NVS) data buffer.
/// If it is NULL it indicates the NVS data is not available.
///
VOID *NvsBufferPtr;
///
/// Pointer to the temporary stack base address to be
/// consumed inside FspMemoryInit() API.
///
VOID *StackBase;
///
/// Temporary stack size to be consumed inside
/// FspMemoryInit() API.
///
UINT32 StackSize;
///
/// Size of memory to be reserved by FSP below "top
/// of low usable memory" for bootloader usage.
///
UINT32 BootLoaderTolumSize;
///
/// Current boot mode.
///
UINT32 BootMode;
///
/// Optional event handler for the bootloader to be informed of events occurring during FSP execution.
/// This value is only valid if Revision is >= 2.
///
FSP_EVENT_HANDLER *FspEventHandler;
UINT8 Reserved1[4];
} FSPM_ARCH_UPD;
typedef struct {
///
/// Revision Revision of the structure is 1 for this version of the specification.
///
UINT8 Revision;
UINT8 Reserved[3];
///
/// Length Length of the structure in bytes. The current value for this field is 32.
///
UINT32 Length;
///
/// FspEventHandler Optional event handler for the bootloader to be informed of events
/// occurring during FSP execution.
///
FSP_EVENT_HANDLER FspEventHandler;
///
/// A FSP binary may optionally implement multi-phase silicon initialization,
/// This is only supported if the FspMultiPhaseSiInitEntryOffset field in FSP_INFO_HEADER
/// is non-zero.
/// To enable multi-phase silicon initialization, the bootloader must set
/// EnableMultiPhaseSiliconInit to a non-zero value.
///
UINT8 EnableMultiPhaseSiliconInit;
UINT8 Reserved1[19];
} FSPS_ARCH_UPD;
///
/// FSPT_UPD_COMMON Configuration.
///
typedef struct {
///
/// FSP_UPD_HEADER Configuration.
///
FSP_UPD_HEADER FspUpdHeader;
} FSPT_UPD_COMMON;
///
/// FSPT_UPD_COMMON Configuration for FSP spec. 2.2 and above.
///
typedef struct {
///
/// FSP_UPD_HEADER Configuration.
///
FSP_UPD_HEADER FspUpdHeader;
///
/// FSPT_ARCH_UPD Configuration.
///
FSPT_ARCH_UPD FsptArchUpd;
} FSPT_UPD_COMMON_FSP22;
///
/// FSPM_UPD_COMMON Configuration.
///
typedef struct {
///
/// FSP_UPD_HEADER Configuration.
///
FSP_UPD_HEADER FspUpdHeader;
///
/// FSPM_ARCH_UPD Configuration.
///
FSPM_ARCH_UPD FspmArchUpd;
} FSPM_UPD_COMMON;
///
/// FSPS_UPD_COMMON Configuration.
///
typedef struct {
///
/// FSP_UPD_HEADER Configuration.
///
FSP_UPD_HEADER FspUpdHeader;
} FSPS_UPD_COMMON;
///
/// FSPS_UPD_COMMON Configuration for FSP spec. 2.2 and above.
///
typedef struct {
///
/// FSP_UPD_HEADER Configuration.
///
FSP_UPD_HEADER FspUpdHeader;
///
/// FSPS_ARCH_UPD Configuration.
///
FSPS_ARCH_UPD FspsArchUpd;
} FSPS_UPD_COMMON_FSP22;
///
/// Enumeration of FSP_INIT_PHASE for NOTIFY_PHASE.
///
typedef enum {
///
/// This stage is notified when the bootloader completes the
/// PCI enumeration and the resource allocation for the
/// PCI devices is complete.
///
EnumInitPhaseAfterPciEnumeration = 0x20,
///
/// This stage is notified just before the bootloader hand-off
/// to the OS loader.
///
EnumInitPhaseReadyToBoot = 0x40,
///
/// This stage is notified just before the firmware/Preboot
/// environment transfers management of all system resources
/// to the OS or next level execution environment.
///
EnumInitPhaseEndOfFirmware = 0xF0
} FSP_INIT_PHASE;
///
/// Definition of NOTIFY_PHASE_PARAMS.
///
typedef struct {
///
/// Notification phase used for NotifyPhase API
///
FSP_INIT_PHASE Phase;
} NOTIFY_PHASE_PARAMS;
///
/// Action definition for FspMultiPhaseSiInit API
///
typedef enum {
EnumMultiPhaseGetNumberOfPhases = 0x0,
EnumMultiPhaseExecutePhase = 0x1
} FSP_MULTI_PHASE_ACTION;
///
/// Data structure returned by FSP when bootloader calling
/// FspMultiPhaseSiInit API with action 0 (EnumMultiPhaseGetNumberOfPhases)
///
typedef struct {
UINT32 NumberOfPhases;
UINT32 PhasesExecuted;
} FSP_MULTI_PHASE_GET_NUMBER_OF_PHASES_PARAMS;
///
/// FspMultiPhaseSiInit function parameter.
///
/// For action 0 (EnumMultiPhaseGetNumberOfPhases):
/// - PhaseIndex must be 0.
/// - MultiPhaseParamPtr should point to an instance of FSP_MULTI_PHASE_GET_NUMBER_OF_PHASES_PARAMS.
///
/// For action 1 (EnumMultiPhaseExecutePhase):
/// - PhaseIndex will be the phase that will be executed by FSP.
/// - MultiPhaseParamPtr shall be NULL.
///
typedef struct {
IN FSP_MULTI_PHASE_ACTION MultiPhaseAction;
IN UINT32 PhaseIndex;
IN OUT VOID *MultiPhaseParamPtr;
} FSP_MULTI_PHASE_PARAMS;
#pragma pack()
/**
This FSP API is called soon after coming out of reset and before memory and stack is
available. This FSP API will load the microcode update, enable code caching for the
region specified by the boot loader and also setup a temporary stack to be used until
main memory is initialized.
A hardcoded stack can be set up with the following values, and the "esp" register
initialized to point to this hardcoded stack.
1. The return address where the FSP will return control after setting up a temporary
stack.
2. A pointer to the input parameter structure
However, since the stack is in ROM and not writeable, this FSP API cannot be called
using the "call" instruction, but needs to be jumped to.
@param[in] FsptUpdDataPtr Pointer to the FSPT_UPD data structure.
@retval EFI_SUCCESS Temporary RAM was initialized successfully.
@retval EFI_INVALID_PARAMETER Input parameters are invalid.
@retval EFI_UNSUPPORTED The FSP calling conditions were not met.
@retval EFI_DEVICE_ERROR Temp RAM initialization failed.
If this function is successful, the FSP initializes the ECX and EDX registers to point to
a temporary but writeable memory range available to the boot loader and returns with
FSP_SUCCESS in register EAX. Register ECX points to the start of this temporary
memory range and EDX points to the end of the range. Boot loader is free to use the
whole range described. Typically the boot loader can reload the ESP register to point
to the end of this returned range so that it can be used as a standard stack.
**/
typedef
EFI_STATUS
(EFIAPI *FSP_TEMP_RAM_INIT) (
IN VOID *FsptUpdDataPtr
);
/**
This FSP API is used to notify the FSP about the different phases in the boot process.
This allows the FSP to take appropriate actions as needed during different initialization
phases. The phases will be platform dependent and will be documented with the FSP
release. The current FSP supports two notify phases:
Post PCI enumeration
Ready To Boot
@param[in] NotifyPhaseParamPtr Address pointer to the NOTIFY_PHASE_PRAMS
@retval EFI_SUCCESS The notification was handled successfully.
@retval EFI_UNSUPPORTED The notification was not called in the proper order.
@retval EFI_INVALID_PARAMETER The notification code is invalid.
**/
typedef
EFI_STATUS
(EFIAPI *FSP_NOTIFY_PHASE) (
IN NOTIFY_PHASE_PARAMS *NotifyPhaseParamPtr
);
/**
This FSP API is called after TempRamInit and initializes the memory.
This FSP API accepts a pointer to a data structure that will be platform dependent
and defined for each FSP binary. This will be documented in Integration guide with
each FSP release.
After FspMemInit completes its execution, it passes the pointer to the HobList and
returns to the boot loader from where it was called. BootLoader is responsible to
migrate its stack and data to Memory.
FspMemoryInit, TempRamExit and FspSiliconInit APIs provide an alternate method to
complete the silicon initialization and provides bootloader an opportunity to get
control after system memory is available and before the temporary RAM is torn down.
@param[in] FspmUpdDataPtr Pointer to the FSPM_UPD data structure.
@param[out] HobListPtr Pointer to receive the address of the HOB list.
@retval EFI_SUCCESS FSP execution environment was initialized successfully.
@retval EFI_INVALID_PARAMETER Input parameters are invalid.
@retval EFI_UNSUPPORTED The FSP calling conditions were not met.
@retval EFI_DEVICE_ERROR FSP initialization failed.
@retval EFI_OUT_OF_RESOURCES Stack range requested by FSP is not met.
@retval FSP_STATUS_RESET_REQUIREDx A reset is reuired. These status codes will not be returned during S3.
**/
typedef
EFI_STATUS
(EFIAPI *FSP_MEMORY_INIT) (
IN VOID *FspmUpdDataPtr,
OUT VOID **HobListPtr
);
/**
This FSP API is called after FspMemoryInit API. This FSP API tears down the temporary
memory setup by TempRamInit API. This FSP API accepts a pointer to a data structure
that will be platform dependent and defined for each FSP binary. This will be
documented in Integration Guide.
FspMemoryInit, TempRamExit and FspSiliconInit APIs provide an alternate method to
complete the silicon initialization and provides bootloader an opportunity to get
control after system memory is available and before the temporary RAM is torn down.
@param[in] TempRamExitParamPtr Pointer to the Temp Ram Exit parameters structure.
This structure is normally defined in the Integration Guide.
And if it is not defined in the Integration Guide, pass NULL.
@retval EFI_SUCCESS FSP execution environment was initialized successfully.
@retval EFI_INVALID_PARAMETER Input parameters are invalid.
@retval EFI_UNSUPPORTED The FSP calling conditions were not met.
@retval EFI_DEVICE_ERROR FSP initialization failed.
**/
typedef
EFI_STATUS
(EFIAPI *FSP_TEMP_RAM_EXIT) (
IN VOID *TempRamExitParamPtr
);
/**
This FSP API is called after TempRamExit API.
FspMemoryInit, TempRamExit and FspSiliconInit APIs provide an alternate method to complete the
silicon initialization.
@param[in] FspsUpdDataPtr Pointer to the FSPS_UPD data structure.
If NULL, FSP will use the default parameters.
@retval EFI_SUCCESS FSP execution environment was initialized successfully.
@retval EFI_INVALID_PARAMETER Input parameters are invalid.
@retval EFI_UNSUPPORTED The FSP calling conditions were not met.
@retval EFI_DEVICE_ERROR FSP initialization failed.
@retval FSP_STATUS_RESET_REQUIREDx A reset is required. These status codes will not be returned during S3.
**/
typedef
EFI_STATUS
(EFIAPI *FSP_SILICON_INIT) (
IN VOID *FspsUpdDataPtr
);
/**
This FSP API is expected to be called after FspSiliconInit but before FspNotifyPhase.
This FSP API provides multi-phase silicon initialization; which brings greater modularity
beyond the existing FspSiliconInit() API. Increased modularity is achieved by adding an
extra API to FSP-S. This allows the bootloader to add board specific initialization steps
throughout the SiliconInit flow as needed.
@param[in,out] FSP_MULTI_PHASE_PARAMS For action - EnumMultiPhaseGetNumberOfPhases:
FSP_MULTI_PHASE_PARAMS->MultiPhaseParamPtr will contain
how many phases supported by FSP.
For action - EnumMultiPhaseExecutePhase:
FSP_MULTI_PHASE_PARAMS->MultiPhaseParamPtr shall be NULL.
@retval EFI_SUCCESS FSP execution environment was initialized successfully.
@retval EFI_INVALID_PARAMETER Input parameters are invalid.
@retval EFI_UNSUPPORTED The FSP calling conditions were not met.
@retval EFI_DEVICE_ERROR FSP initialization failed.
@retval FSP_STATUS_RESET_REQUIREDx A reset is required. These status codes will not be returned during S3.
**/
typedef
EFI_STATUS
(EFIAPI *FSP_MULTI_PHASE_SI_INIT) (
IN FSP_MULTI_PHASE_PARAMS *MultiPhaseSiInitParamPtr
);
#endif

78
src/vendorcode/intel/edk2/edk2-stable202111/IntelFsp2Pkg/Include/FspGlobalData.h Normal file
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@@ -0,0 +1,78 @@
/** @file
Copyright (c) 2014 - 2020, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef _FSP_GLOBAL_DATA_H_
#define _FSP_GLOBAL_DATA_H_
#include <FspEas.h>
#define FSP_IN_API_MODE 0
#define FSP_IN_DISPATCH_MODE 1
#pragma pack(1)
typedef enum {
TempRamInitApiIndex,
FspInitApiIndex,
NotifyPhaseApiIndex,
FspMemoryInitApiIndex,
TempRamExitApiIndex,
FspSiliconInitApiIndex,
FspMultiPhaseSiInitApiIndex,
FspApiIndexMax
} FSP_API_INDEX;
typedef struct {
VOID *DataPtr;
UINT32 MicrocodeRegionBase;
UINT32 MicrocodeRegionSize;
UINT32 CodeRegionBase;
UINT32 CodeRegionSize;
} FSP_PLAT_DATA;
#define FSP_GLOBAL_DATA_SIGNATURE SIGNATURE_32 ('F', 'S', 'P', 'D')
#define FSP_PERFORMANCE_DATA_SIGNATURE SIGNATURE_32 ('P', 'E', 'R', 'F')
#define FSP_PERFORMANCE_DATA_TIMER_MASK 0xFFFFFFFFFFFFFF
typedef struct {
UINT32 Signature;
UINT8 Version;
UINT8 Reserved1[3];
UINT32 CoreStack;
UINT32 StatusCode;
UINT32 Reserved2[8];
FSP_PLAT_DATA PlatformData;
FSP_INFO_HEADER *FspInfoHeader;
VOID *UpdDataPtr;
VOID *TempRamInitUpdPtr;
VOID *MemoryInitUpdPtr;
VOID *SiliconInitUpdPtr;
UINT8 ApiIdx;
///
/// 0: FSP in API mode; 1: FSP in DISPATCH mode
///
UINT8 FspMode;
UINT8 OnSeparateStack;
UINT8 Reserved3;
UINT32 NumberOfPhases;
UINT32 PhasesExecuted;
///
/// To store function parameters pointer
/// so it can be retrieved after stack switched.
///
VOID *FunctionParameterPtr;
UINT8 Reserved4[16];
UINT32 PerfSig;
UINT16 PerfLen;
UINT16 Reserved5;
UINT32 PerfIdx;
UINT64 PerfData[32];
} FSP_GLOBAL_DATA;
#pragma pack()
#endif

56
src/vendorcode/intel/edk2/edk2-stable202111/IntelFsp2Pkg/Include/FspMeasurePointId.h Normal file
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@@ -0,0 +1,56 @@
/** @file
Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef _FSP_MEASURE_POINT_ID_H_
#define _FSP_MEASURE_POINT_ID_H_
//
// 0xD0 - 0xEF are reserved for FSP common measure point
//
#define FSP_PERF_ID_MRC_INIT_ENTRY 0xD0
#define FSP_PERF_ID_MRC_INIT_EXIT (FSP_PERF_ID_MRC_INIT_ENTRY + 1)
#define FSP_PERF_ID_SYSTEM_AGENT_INIT_ENTRY 0xD8
#define FSP_PERF_ID_SYSTEM_AGENT_INIT_EXIT (FSP_PERF_ID_SYSTEM_AGENT_INIT_ENTRY + 1)
#define FSP_PERF_ID_PCH_INIT_ENTRY 0xDA
#define FSP_PERF_ID_PCH_INIT_EXIT (FSP_PERF_ID_PCH_INIT_ENTRY + 1)
#define FSP_PERF_ID_CPU_INIT_ENTRY 0xE0
#define FSP_PERF_ID_CPU_INIT_EXIT (FSP_PERF_ID_CPU_INIT_ENTRY + 1)
#define FSP_PERF_ID_GFX_INIT_ENTRY 0xE8
#define FSP_PERF_ID_GFX_INIT_EXIT (FSP_PERF_ID_GFX_INIT_ENTRY + 1)
#define FSP_PERF_ID_ME_INIT_ENTRY 0xEA
#define FSP_PERF_ID_ME_INIT_EXIT (FSP_PERF_ID_ME_INIT_ENTRY + 1)
//
// 0xF0 - 0xFF are reserved for FSP API
//
#define FSP_PERF_ID_API_TEMP_RAM_INIT_ENTRY 0xF0
#define FSP_PERF_ID_API_TEMP_RAM_INIT_EXIT (FSP_PERF_ID_API_TEMP_RAM_INIT_ENTRY + 1)
#define FSP_PERF_ID_API_FSP_MEMORY_INIT_ENTRY 0xF2
#define FSP_PERF_ID_API_FSP_MEMORY_INIT_EXIT (FSP_PERF_ID_API_FSP_MEMORY_INIT_ENTRY + 1)
#define FSP_PERF_ID_API_TEMP_RAM_EXIT_ENTRY 0xF4
#define FSP_PERF_ID_API_TEMP_RAM_EXIT_EXIT (FSP_PERF_ID_API_TEMP_RAM_EXIT_ENTRY + 1)
#define FSP_PERF_ID_API_FSP_SILICON_INIT_ENTRY 0xF6
#define FSP_PERF_ID_API_FSP_SILICON_INIT_EXIT (FSP_PERF_ID_API_FSP_SILICON_INIT_ENTRY + 1)
#define FSP_PERF_ID_API_NOTIFY_POST_PCI_ENTRY 0xF8
#define FSP_PERF_ID_API_NOTIFY_POST_PCI_EXIT (FSP_PERF_ID_API_NOTIFY_POST_PCI_ENTRY + 1)
#define FSP_PERF_ID_API_NOTIFY_READY_TO_BOOT_ENTRY 0xFA
#define FSP_PERF_ID_API_NOTIFY_READY_TO_BOOT_EXIT (FSP_PERF_ID_API_NOTIFY_READY_TO_BOOT_ENTRY + 1)
#define FSP_PERF_ID_API_NOTIFY_END_OF_FIRMWARE_ENTRY 0xFC
#define FSP_PERF_ID_API_NOTIFY_END_OF_FIRMWARE_EXIT (FSP_PERF_ID_API_NOTIFY_END_OF_FIRMWARE_ENTRY + 1)
#endif

40
src/vendorcode/intel/edk2/edk2-stable202111/IntelFsp2Pkg/Include/FspStatusCode.h Normal file
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/** @file
Intel FSP status code definition
Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef _FSP_STATUS_CODE_H_
#define _FSP_STATUS_CODE_H_
//
// FSP API - 4 BITS
//
#define FSP_STATUS_CODE_TEMP_RAM_INIT 0xF000
#define FSP_STATUS_CODE_MEMORY_INIT 0xD000
#define FSP_STATUS_CODE_TEMP_RAM_EXIT 0xB000
#define FSP_STATUS_CODE_SILICON_INIT 0x9000
#define FSP_STATUS_CODE_POST_PCIE_ENUM_NOTIFICATION 0x6000
#define FSP_STATUS_CODE_READY_TO_BOOT_NOTIFICATION 0x4000
#define FSP_STATUS_CODE_END_OF_FIRMWARE_NOTIFICATION 0x2000
//
// MODULE - 4 BITS
//
#define FSP_STATUS_CODE_GFX_PEIM 0x0700
#define FSP_STATUS_CODE_COMMON_CODE 0x0800
#define FSP_STATUS_CODE_SILICON_COMMON_CODE 0x0900
#define FSP_STATUS_CODE_SYSTEM_AGENT 0x0A00
#define FSP_STATUS_CODE_PCH 0x0B00
#define FSP_STATUS_CODE_CPU 0x0C00
#define FSP_STATUS_CODE_MRC 0x0D00
#define FSP_STATUS_CODE_ME_BIOS 0x0E00
//
// Individual Codes - 1 BYTE
//
#define FSP_STATUS_CODE_API_ENTRY 0x0000
#define FSP_STATUS_CODE_API_EXIT 0x007F
#endif

235
src/vendorcode/intel/edk2/edk2-stable202111/IntelFsp2Pkg/Include/Guid/FspHeaderFile.h Normal file
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/** @file
Intel FSP Header File definition from Intel Firmware Support Package External
Architecture Specification v2.0 and above.
Copyright (c) 2014 - 2021, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef __FSP_HEADER_FILE_H__
#define __FSP_HEADER_FILE_H__
#define FSP_HEADER_REVISION_3 3
#define FSPE_HEADER_REVISION_1 1
#define FSPP_HEADER_REVISION_1 1
///
/// Fixed FSP header offset in the FSP image
///
#define FSP_INFO_HEADER_OFF 0x94
#define OFFSET_IN_FSP_INFO_HEADER(x) (UINT32)&((FSP_INFO_HEADER *)(UINTN)0)->x
#define FSP_INFO_HEADER_SIGNATURE SIGNATURE_32 ('F', 'S', 'P', 'H')
#pragma pack(1)
///
/// FSP Information Header as described in FSP v2.0 Spec section 5.1.1.
///
typedef struct {
///
/// Byte 0x00: Signature ('FSPH') for the FSP Information Header.
///
UINT32 Signature;
///
/// Byte 0x04: Length of the FSP Information Header.
///
UINT32 HeaderLength;
///
/// Byte 0x08: Reserved.
///
UINT8 Reserved1[2];
///
/// Byte 0x0A: Indicates compliance with a revision of this specification in the BCD format.
/// For revision v2.3 the value will be 0x23.
///
UINT8 SpecVersion;
///
/// Byte 0x0B: Revision of the FSP Information Header.
/// The Current value for this field is 0x6.
///
UINT8 HeaderRevision;
///
/// Byte 0x0C: Revision of the FSP binary.
/// Major.Minor.Revision.Build
/// If FSP HeaderRevision is <= 5, the ImageRevision can be decoded as follows:
/// 7 : 0 - Build Number
/// 15 : 8 - Revision
/// 23 : 16 - Minor Version
/// 31 : 24 - Major Version
/// If FSP HeaderRevision is >= 6, ImageRevision specifies the low-order bytes of the build number and revision
/// while ExtendedImageRevision specifies the high-order bytes of the build number and revision.
/// 7 : 0 - Low Byte of Build Number
/// 15 : 8 - Low Byte of Revision
/// 23 : 16 - Minor Version
/// 31 : 24 - Major Version
///
UINT32 ImageRevision;
///
/// Byte 0x10: Signature string that will help match the FSP Binary to a supported HW configuration.
///
CHAR8 ImageId[8];
///
/// Byte 0x18: Size of the entire FSP binary.
///
UINT32 ImageSize;
///
/// Byte 0x1C: FSP binary preferred base address.
///
UINT32 ImageBase;
///
/// Byte 0x20: Attribute for the FSP binary.
///
UINT16 ImageAttribute;
///
/// Byte 0x22: Attributes of the FSP Component.
///
UINT16 ComponentAttribute;
///
/// Byte 0x24: Offset of the FSP configuration region.
///
UINT32 CfgRegionOffset;
///
/// Byte 0x28: Size of the FSP configuration region.
///
UINT32 CfgRegionSize;
///
/// Byte 0x2C: Reserved2.
///
UINT32 Reserved2;
///
/// Byte 0x30: The offset for the API to setup a temporary stack till the memory is initialized.
///
UINT32 TempRamInitEntryOffset;
///
/// Byte 0x34: Reserved3.
///
UINT32 Reserved3;
///
/// Byte 0x38: The offset for the API to inform the FSP about the different stages in the boot process.
///
UINT32 NotifyPhaseEntryOffset;
///
/// Byte 0x3C: The offset for the API to initialize the memory.
///
UINT32 FspMemoryInitEntryOffset;
///
/// Byte 0x40: The offset for the API to tear down temporary RAM.
///
UINT32 TempRamExitEntryOffset;
///
/// Byte 0x44: The offset for the API to initialize the CPU and chipset.
///
UINT32 FspSiliconInitEntryOffset;
///
/// Byte 0x48: Offset for the API for the optional Multi-Phase processor and chipset initialization.
/// This value is only valid if FSP HeaderRevision is >= 5.
/// If the value is set to 0x00000000, then this API is not available in this component.
///
UINT32 FspMultiPhaseSiInitEntryOffset;
///
/// Byte 0x4C: Extended revision of the FSP binary.
/// This value is only valid if FSP HeaderRevision is >= 6.
/// ExtendedImageRevision specifies the high-order byte of the revision and build number in the FSP binary revision.
/// 7 : 0 - High Byte of Build Number
/// 15 : 8 - High Byte of Revision
/// The FSP binary build number can be decoded as follows:
/// Build Number = (ExtendedImageRevision[7:0] << 8) | ImageRevision[7:0]
/// Revision = (ExtendedImageRevision[15:8] << 8) | ImageRevision[15:8]
/// Minor Version = ImageRevision[23:16]
/// Major Version = ImageRevision[31:24]
///
UINT16 ExtendedImageRevision;
///
/// Byte 0x4E: Reserved4.
///
UINT16 Reserved4;
} FSP_INFO_HEADER;
///
/// Signature of the FSP Extended Header
///
#define FSP_INFO_EXTENDED_HEADER_SIGNATURE SIGNATURE_32 ('F', 'S', 'P', 'E')
///
/// FSP Information Extended Header as described in FSP v2.0 Spec section 5.1.2.
///
typedef struct {
///
/// Byte 0x00: Signature ('FSPE') for the FSP Extended Information Header.
///
UINT32 Signature;
///
/// Byte 0x04: Length of the table in bytes, including all additional FSP producer defined data.
///
UINT32 Length;
///
/// Byte 0x08: FSP producer defined revision of the table.
///
UINT8 Revision;
///
/// Byte 0x09: Reserved for future use.
///
UINT8 Reserved;
///
/// Byte 0x0A: FSP producer identification string
///
CHAR8 FspProducerId[6];
///
/// Byte 0x10: FSP producer implementation revision number. Larger numbers are assumed to be newer revisions.
///
UINT32 FspProducerRevision;
///
/// Byte 0x14: Size of the FSP producer defined data (n) in bytes.
///
UINT32 FspProducerDataSize;
///
/// Byte 0x18: FSP producer defined data of size (n) defined by FspProducerDataSize.
///
} FSP_INFO_EXTENDED_HEADER;
//
// A generic table search algorithm for additional tables can be implemented with a
// signature search algorithm until a terminator signature 'FSPP' is found.
//
#define FSP_FSPP_SIGNATURE SIGNATURE_32 ('F', 'S', 'P', 'P')
#define FSP_PATCH_TABLE_SIGNATURE FSP_FSPP_SIGNATURE
///
/// FSP Patch Table as described in FSP v2.0 Spec section 5.1.5.
///
typedef struct {
///
/// Byte 0x00: FSP Patch Table Signature "FSPP".
///
UINT32 Signature;
///
/// Byte 0x04: Size including the PatchData.
///
UINT16 HeaderLength;
///
/// Byte 0x06: Revision is set to 0x01.
///
UINT8 HeaderRevision;
///
/// Byte 0x07: Reserved for future use.
///
UINT8 Reserved;
///
/// Byte 0x08: Number of entries to Patch.
///
UINT32 PatchEntryNum;
///
/// Byte 0x0C: Patch Data.
///
//UINT32 PatchData[];
} FSP_PATCH_TABLE;
#pragma pack()
extern EFI_GUID gFspHeaderFileGuid;
#endif

24
src/vendorcode/intel/edk2/edk2-stable202111/IntelFsp2Pkg/Include/Guid/FspNonVolatileStorageHob2.h Normal file
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/** @file
Intel FSP Non-Volatile Storage (NVS) HOB version 2 definition from
Intel Firmware Support Package External Architecture Specification v2.3.
Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef __FSP_NON_VOLATILE_STORAGE_HOB2_H__
#define __FSP_NON_VOLATILE_STORAGE_HOB2_H__
///
/// The Non-Volatile Storage (NVS) HOB version 2 provides > 64KB buffer support.
///
typedef struct {
EFI_HOB_GUID_TYPE GuidHob;
EFI_PHYSICAL_ADDRESS NvsDataPtr;
UINT64 NvsDataLength;
} FSP_NON_VOLATILE_STORAGE_HOB2;
extern EFI_GUID gFspNonVolatileStorageHob2Guid;
#endif

17
src/vendorcode/intel/edk2/edk2-stable202111/IntelFsp2Pkg/Include/Guid/GuidHobFspEas.h Normal file
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/** @file
Intel FSP Hob Guid definition from Intel Firmware Support Package External
Architecture Specification v2.0.
Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef __GUID_HOB_FSP_EAS_GUID__
#define __GUID_HOB_FSP_EAS_GUID__
extern EFI_GUID gFspBootLoaderTolumHobGuid;
extern EFI_GUID gFspReservedMemoryResourceHobGuid;
extern EFI_GUID gFspNonVolatileStorageHobGuid;
#endif

24
src/vendorcode/intel/edk2/edk2-stable202111/IntelFsp2Pkg/Include/Library/CacheAsRamLib.h Normal file
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/** @file
Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef _CACHE_AS_RAM_LIB_H_
#define _CACHE_AS_RAM_LIB_H_
/**
This function disable CAR.
@param[in] DisableCar TRUE means use INVD, FALSE means use WBINVD
**/
VOID
EFIAPI
DisableCacheAsRam (
IN BOOLEAN DisableCar
);
#endif

56
src/vendorcode/intel/edk2/edk2-stable202111/IntelFsp2Pkg/Include/Library/CacheLib.h Normal file
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/** @file
Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef _CACHE_LIB_H_
#define _CACHE_LIB_H_
//
// EFI_MEMORY_CACHE_TYPE
//
typedef INT32 EFI_MEMORY_CACHE_TYPE;
#define EFI_CACHE_UNCACHEABLE 0
#define EFI_CACHE_WRITECOMBINING 1
#define EFI_CACHE_WRITETHROUGH 4
#define EFI_CACHE_WRITEPROTECTED 5
#define EFI_CACHE_WRITEBACK 6
/**
Reset all the MTRRs to a known state.
@retval EFI_SUCCESS All MTRRs have been reset successfully.
**/
EFI_STATUS
EFIAPI
ResetCacheAttributes (
VOID
);
/**
Given the memory range and cache type, programs the MTRRs.
@param[in] MemoryAddress Base Address of Memory to program MTRR.
@param[in] MemoryLength Length of Memory to program MTRR.
@param[in] MemoryCacheType Cache Type.
@retval EFI_SUCCESS Mtrr are set successfully.
@retval EFI_LOAD_ERROR No empty MTRRs to use.
@retval EFI_INVALID_PARAMETER The input parameter is not valid.
@retval others An error occurs when setting MTTR.
**/
EFI_STATUS
EFIAPI
SetCacheAttributes (
IN EFI_PHYSICAL_ADDRESS MemoryAddress,
IN UINT64 MemoryLength,
IN EFI_MEMORY_CACHE_TYPE MemoryCacheType
);
#endif

23
src/vendorcode/intel/edk2/edk2-stable202111/IntelFsp2Pkg/Include/Library/DebugDeviceLib.h Normal file
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/** @file
Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef __DEBUG_DEVICE_LIB_H__
#define __DEBUG_DEVICE_LIB_H__
/**
Returns the debug print device enable state.
@return Debug print device enable state.
**/
UINT8
EFIAPI
GetDebugPrintDeviceEnable (
VOID
);
#endif

308
src/vendorcode/intel/edk2/edk2-stable202111/IntelFsp2Pkg/Include/Library/FspCommonLib.h Normal file
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/** @file
Copyright (c) 2014 - 2019, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef _FSP_COMMON_LIB_H_
#define _FSP_COMMON_LIB_H_
#include <FspGlobalData.h>
#include <FspMeasurePointId.h>
/**
This function sets the FSP global data pointer.
@param[in] FspData Fsp global data pointer.
**/
VOID
EFIAPI
SetFspGlobalDataPointer (
IN FSP_GLOBAL_DATA *FspData
);
/**
This function gets the FSP global data pointer.
**/
FSP_GLOBAL_DATA *
EFIAPI
GetFspGlobalDataPointer (
VOID
);
/**
This function gets back the FSP API first parameter passed by the bootloader.
@retval ApiParameter FSP API first parameter passed by the bootloader.
**/
UINT32
EFIAPI
GetFspApiParameter (
VOID
);
/**
This function gets back the FSP API second parameter passed by the bootloader.
@retval ApiParameter FSP API second parameter passed by the bootloader.
**/
UINT32
EFIAPI
GetFspApiParameter2 (
VOID
);
/**
This function returns the FSP entry stack pointer from address of the first API parameter.
@retval FSP entry stack pointer.
**/
VOID*
EFIAPI
GetFspEntryStack (
VOID
);
/**
This function sets the FSP API parameter in the stack.
@param[in] Value New parameter value.
**/
VOID
EFIAPI
SetFspApiParameter (
IN UINT32 Value
);
/**
This function set the API status code returned to the BootLoader.
@param[in] ReturnStatus Status code to return.
**/
VOID
EFIAPI
SetFspApiReturnStatus (
IN UINT32 ReturnStatus
);
/**
This function sets the context switching stack to a new stack frame.
@param[in] NewStackTop New core stack to be set.
**/
VOID
EFIAPI
SetFspCoreStackPointer (
IN VOID *NewStackTop
);
/**
This function sets the platform specific data pointer.
@param[in] PlatformData Fsp platform specific data pointer.
**/
VOID
EFIAPI
SetFspPlatformDataPointer (
IN VOID *PlatformData
);
/**
This function gets the platform specific data pointer.
@param[in] PlatformData Fsp platform specific data pointer.
**/
VOID *
EFIAPI
GetFspPlatformDataPointer (
VOID
);
/**
This function sets the UPD data pointer.
@param[in] UpdDataPtr UPD data pointer.
**/
VOID
EFIAPI
SetFspUpdDataPointer (
IN VOID *UpdDataPtr
);
/**
This function gets the UPD data pointer.
@return UpdDataPtr UPD data pointer.
**/
VOID *
EFIAPI
GetFspUpdDataPointer (
VOID
);
/**
This function sets the memory init UPD data pointer.
@param[in] MemoryInitUpdPtr memory init UPD data pointer.
**/
VOID
EFIAPI
SetFspMemoryInitUpdDataPointer (
IN VOID *MemoryInitUpdPtr
);
/**
This function gets the memory init UPD data pointer.
@return memory init UPD data pointer.
**/
VOID *
EFIAPI
GetFspMemoryInitUpdDataPointer (
VOID
);
/**
This function sets the silicon init UPD data pointer.
@param[in] SiliconInitUpdPtr silicon init UPD data pointer.
**/
VOID
EFIAPI
SetFspSiliconInitUpdDataPointer (
IN VOID *SiliconInitUpdPtr
);
/**
This function gets the silicon init UPD data pointer.
@return silicon init UPD data pointer.
**/
VOID *
EFIAPI
GetFspSiliconInitUpdDataPointer (
VOID
);
/**
Set FSP measurement point timestamp.
@param[in] Id Measurement point ID.
@return performance timestamp.
**/
UINT64
EFIAPI
SetFspMeasurePoint (
IN UINT8 Id
);
/**
This function gets the FSP info header pointer.
@retval FspInfoHeader FSP info header pointer
**/
FSP_INFO_HEADER *
EFIAPI
GetFspInfoHeader (
VOID
);
/**
This function sets the FSP info header pointer.
@param[in] FspInfoHeader FSP info header pointer
**/
VOID
EFIAPI
SetFspInfoHeader (
FSP_INFO_HEADER *FspInfoHeader
);
/**
This function gets the FSP info header pointer from the API context.
@retval FspInfoHeader FSP info header pointer
**/
FSP_INFO_HEADER *
EFIAPI
GetFspInfoHeaderFromApiContext (
VOID
);
/**
This function gets the CfgRegion data pointer.
@return CfgRegion data pointer.
**/
VOID *
EFIAPI
GetFspCfgRegionDataPointer (
VOID
);
/**
This function gets FSP API calling mode.
@retval API calling mode
**/
UINT8
EFIAPI
GetFspApiCallingIndex (
VOID
);
/**
This function sets FSP API calling mode.
@param[in] Index API calling index
**/
VOID
EFIAPI
SetFspApiCallingIndex (
UINT8 Index
);
/**
This function gets FSP Phase StatusCode.
@retval StatusCode
**/
UINT32
EFIAPI
GetPhaseStatusCode (
VOID
);
/**
This function sets FSP Phase StatusCode.
@param[in] Mode Phase StatusCode
**/
VOID
EFIAPI
SetPhaseStatusCode (
UINT32 StatusCode
);
/**
This function updates the return status of the FSP API with requested reset type and returns to Boot Loader.
@param[in] FspResetType Reset type that needs to returned as API return status
**/
VOID
EFIAPI
FspApiReturnStatusReset (
IN UINT32 FspResetType
);
#endif

125
src/vendorcode/intel/edk2/edk2-stable202111/IntelFsp2Pkg/Include/Library/FspPlatformLib.h Normal file
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/** @file
Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef _FSP_PLATFORM_LIB_H_
#define _FSP_PLATFORM_LIB_H_
/**
Get system memory resource descriptor by owner.
@param[in] OwnerGuid resource owner guid
**/
EFI_HOB_RESOURCE_DESCRIPTOR *
EFIAPI
FspGetResourceDescriptorByOwner (
IN EFI_GUID *OwnerGuid
);
/**
Get system memory from HOB.
@param[in,out] LowMemoryLength less than 4G memory length
@param[in,out] HighMemoryLength greater than 4G memory length
**/
VOID
EFIAPI
FspGetSystemMemorySize (
IN OUT UINT64 *LowMemoryLength,
IN OUT UINT64 *HighMemoryLength
);
/**
Set a new stack frame for the continuation function.
**/
VOID
EFIAPI
FspSetNewStackFrame (
VOID
);
/**
This function transfer control back to BootLoader after FspSiliconInit.
**/
VOID
EFIAPI
FspSiliconInitDone (
VOID
);
/**
This function returns control to BootLoader after MemoryInitApi.
@param[in,out] HobListPtr The address of HobList pointer.
**/
VOID
EFIAPI
FspMemoryInitDone (
IN OUT VOID **HobListPtr
);
/**
This function returns control to BootLoader after TempRamExitApi.
**/
VOID
EFIAPI
FspTempRamExitDone (
VOID
);
/**
This function handle NotifyPhase API call from the BootLoader.
It gives control back to the BootLoader after it is handled. If the
Notification code is a ReadyToBoot event, this function will return
and FSP continues the remaining execution until it reaches the DxeIpl.
**/
VOID
EFIAPI
FspWaitForNotify (
VOID
);
/**
This function transfer control back to BootLoader after FspSiliconInit.
@param[in] Status return status for the FspSiliconInit.
**/
VOID
EFIAPI
FspSiliconInitDone2 (
IN EFI_STATUS Status
);
/**
This function returns control to BootLoader after MemoryInitApi.
@param[in] Status return status for the MemoryInitApi.
@param[in,out] HobListPtr The address of HobList pointer.
**/
VOID
EFIAPI
FspMemoryInitDone2 (
IN EFI_STATUS Status,
IN OUT VOID **HobListPtr
);
/**
This function returns control to BootLoader after TempRamExitApi.
@param[in] Status return status for the TempRamExitApi.
**/
VOID
EFIAPI
FspTempRamExitDone2 (
IN EFI_STATUS Status
);
#endif

96
src/vendorcode/intel/edk2/edk2-stable202111/IntelFsp2Pkg/Include/Library/FspSecPlatformLib.h Normal file
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/** @file
Copyright (c) 2015 - 2020, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef _FSP_SEC_PLATFORM_LIB_H_
#define _FSP_SEC_PLATFORM_LIB_H_
/**
This function performs platform level initialization.
This function must be in ASM file, because stack is not established yet.
This function is optional. If a library instance does not provide this function, the default empty one will be used.
The callee should not use XMM6/XMM7.
The return address is saved in MM7.
@retval in saved in EAX - 0 means platform initialization success.
other means platform initialization fail.
**/
UINT32
EFIAPI
SecPlatformInit (
VOID
);
/**
This function loads Microcode.
This function must be in ASM file, because stack is not established yet.
This function is optional. If a library instance does not provide this function, the default one will be used.
The callee should not use XMM6/XMM7.
The return address is saved in MM7.
@param[in] FsptUpdDataPtr Address pointer to the FSPT_UPD data structure. It is saved in ESP.
@retval in saved in EAX - 0 means Microcode is loaded successfully.
other means Microcode is not loaded successfully.
**/
UINT32
EFIAPI
LoadMicrocode (
IN VOID *FsptUpdDataPtr
);
/**
This function initializes the CAR.
This function must be in ASM file, because stack is not established yet.
The callee should not use XMM6/XMM7.
The return address is saved in MM7.
@param[in] FsptUpdDataPtr Address pointer to the FSPT_UPD data structure. It is saved in ESP.
@retval in saved in EAX - 0 means CAR initialization success.
other means CAR initialization fail.
**/
UINT32
EFIAPI
SecCarInit (
IN VOID *FsptUpdDataPtr
);
/**
This function check the signature of UPD.
@param[in] ApiIdx Internal index of the FSP API.
@param[in] ApiParam Parameter of the FSP API.
**/
EFI_STATUS
EFIAPI
FspUpdSignatureCheck (
IN UINT32 ApiIdx,
IN VOID *ApiParam
);
/**
This function handles FspMultiPhaseSiInitApi.
@param[in] ApiIdx Internal index of the FSP API.
@param[in] ApiParam Parameter of the FSP API.
**/
EFI_STATUS
EFIAPI
FspMultiPhaseSiInitApiHandler (
IN UINT32 ApiIdx,
IN VOID *ApiParam
);
#endif

55
src/vendorcode/intel/edk2/edk2-stable202111/IntelFsp2Pkg/Include/Library/FspSwitchStackLib.h Normal file
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/** @file
Copyright (c) 2014 - 2020, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef _FSP_SWITCH_STACK_LIB_H_
#define _FSP_SWITCH_STACK_LIB_H_
/**
This function will switch the current stack to the previous saved stack.
Before calling the previous stack has to be set in FSP_GLOBAL_DATA.CoreStack.
EIP
FLAGS 16 bit FLAGS 16 bit
EDI
ESI
EBP
ESP
EBX
EDX
ECX
EAX
DWORD IDT base1
StackPointer: DWORD IDT base2
@return ReturnKey After switching to the saved stack,
this value will be saved in eax before returning.
**/
UINT32
EFIAPI
Pei2LoaderSwitchStack (
VOID
);
/**
This function is equivalent to Pei2LoaderSwitchStack () but just indicates
the stack after switched is FSP stack.
@return ReturnKey After switching to the saved stack,
this value will be saved in eax before returning.
**/
UINT32
EFIAPI
Loader2PeiSwitchStack (
VOID
);
#endif

47
src/vendorcode/intel/edk2/edk2-stable202111/IntelFsp2Pkg/Include/Ppi/FspmArchConfigPpi.h Normal file
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/** @file
Header file for FSP-M Arch Config PPI for Dispatch mode
Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef _FSPM_ARCH_CONFIG_PPI_H_
#define _FSPM_ARCH_CONFIG_PPI_H_
#define FSPM_ARCH_CONFIG_PPI_REVISION 0x1
///
/// Global ID for the FSPM_ARCH_CONFIG_PPI.
///
#define FSPM_ARCH_CONFIG_GUID \
{ \
0x824d5a3a, 0xaf92, 0x4c0c, { 0x9f, 0x19, 0x19, 0x52, 0x6d, 0xca, 0x4a, 0xbb } \
}
///
/// This PPI provides FSP-M Arch Config PPI.
///
typedef struct {
///
/// Revision of the structure
///
UINT8 Revision;
UINT8 Reserved[3];
///
/// Pointer to the non-volatile storage (NVS) data buffer.
/// If it is NULL it indicates the NVS data is not available.
///
VOID *NvsBufferPtr;
///
/// Size of memory to be reserved by FSP below "top
/// of low usable memory" for bootloader usage.
///
UINT32 BootLoaderTolumSize;
UINT8 Reserved1[4];
} FSPM_ARCH_CONFIG_PPI;
extern EFI_GUID gFspmArchConfigPpiGuid;
#endif // _FSPM_ARCH_CONFIG_PPI_H_

52
src/vendorcode/intel/edk2/edk2-stable202111/IntelFsp2Pkg/Include/Ppi/TempRamExitPpi.h Normal file
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/** @file
This file defines the Silicon Temp Ram Exit PPI which implements the
required programming steps for disabling temporary memory.
Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef _FSP_TEMP_RAM_EXIT_PPI_H_
#define _FSP_TEMP_RAM_EXIT_PPI_H_
///
/// Global ID for the FSP_TEMP_RAM_EXIT_PPI.
///
#define FSP_TEMP_RAM_EXIT_GUID \
{ \
0xbc1cfbdb, 0x7e50, 0x42be, { 0xb4, 0x87, 0x22, 0xe0, 0xa9, 0x0c, 0xb0, 0x52 } \
}
//
// Forward declaration for the FSP_TEMP_RAM_EXIT_PPI.
//
typedef struct _FSP_TEMP_RAM_EXIT_PPI FSP_TEMP_RAM_EXIT_PPI;
/**
Silicon function for disabling temporary memory.
@param[in] TempRamExitParamPtr - Pointer to the TempRamExit parameters structure.
This structure is normally defined in the Integration
Guide. If it is not defined in the Integration Guide,
pass NULL.
@retval EFI_SUCCESS - FSP execution environment was initialized successfully.
@retval EFI_INVALID_PARAMETER - Input parameters are invalid.
@retval EFI_UNSUPPORTED - The FSP calling conditions were not met.
@retval EFI_DEVICE_ERROR - Temporary memory exit.
**/
typedef
EFI_STATUS
(EFIAPI *FSP_TEMP_RAM_EXIT) (
IN VOID *TempRamExitParamPtr
);
///
/// This PPI provides function to disable temporary memory.
///
struct _FSP_TEMP_RAM_EXIT_PPI {
FSP_TEMP_RAM_EXIT TempRamExit;
};
extern EFI_GUID gFspTempRamExitPpiGuid;
#endif // _FSP_TEMP_RAM_EXIT_PPI_H_

207
src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/AArch64/ProcessorBind.h Normal file
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/** @file
Processor or Compiler specific defines and types for AArch64.
Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef __PROCESSOR_BIND_H__
#define __PROCESSOR_BIND_H__
///
/// Define the processor type so other code can make processor based choices
///
#define MDE_CPU_AARCH64
//
// Make sure we are using the correct packing rules per EFI specification
//
#if !defined(__GNUC__) && !defined(__ASSEMBLER__)
#pragma pack()
#endif
#if defined(_MSC_EXTENSIONS)
//
// Disable some level 4 compilation warnings (same as IA32 and X64)
//
//
// Disabling bitfield type checking warnings.
//
#pragma warning ( disable : 4214 )
//
// Disabling the unreferenced formal parameter warnings.
//
#pragma warning ( disable : 4100 )
//
// Disable slightly different base types warning as CHAR8 * can not be set
// to a constant string.
//
#pragma warning ( disable : 4057 )
//
// ASSERT(FALSE) or while (TRUE) are legal constructs so suppress this warning
//
#pragma warning ( disable : 4127 )
//
// This warning is caused by functions defined but not used. For precompiled header only.
//
#pragma warning ( disable : 4505 )
//
// This warning is caused by empty (after preprocessing) source file. For precompiled header only.
//
#pragma warning ( disable : 4206 )
//
// Disable 'potentially uninitialized local variable X used' warnings
//
#pragma warning ( disable : 4701 )
//
// Disable 'potentially uninitialized local pointer variable X used' warnings
//
#pragma warning ( disable : 4703 )
//
// use Microsoft* C compiler dependent integer width types
//
typedef unsigned __int64 UINT64;
typedef __int64 INT64;
typedef unsigned __int32 UINT32;
typedef __int32 INT32;
typedef unsigned short UINT16;
typedef unsigned short CHAR16;
typedef short INT16;
typedef unsigned char BOOLEAN;
typedef unsigned char UINT8;
typedef char CHAR8;
typedef signed char INT8;
#else
//
// Assume standard AARCH64 alignment.
//
typedef unsigned long long UINT64;
typedef long long INT64;
typedef unsigned int UINT32;
typedef int INT32;
typedef unsigned short UINT16;
typedef unsigned short CHAR16;
typedef short INT16;
typedef unsigned char BOOLEAN;
typedef unsigned char UINT8;
typedef char CHAR8;
typedef signed char INT8;
#endif
///
/// Unsigned value of native width. (4 bytes on supported 32-bit processor instructions,
/// 8 bytes on supported 64-bit processor instructions)
///
typedef UINT64 UINTN;
///
/// Signed value of native width. (4 bytes on supported 32-bit processor instructions,
/// 8 bytes on supported 64-bit processor instructions)
///
typedef INT64 INTN;
//
// Processor specific defines
//
///
/// A value of native width with the highest bit set.
///
#define MAX_BIT 0x8000000000000000ULL
///
/// A value of native width with the two highest bits set.
///
#define MAX_2_BITS 0xC000000000000000ULL
///
/// Maximum legal AARCH64 address
///
#define MAX_ADDRESS 0xFFFFFFFFFFFFFFFFULL
///
/// Maximum usable address at boot time (48 bits using 4 KB pages)
///
#define MAX_ALLOC_ADDRESS 0xFFFFFFFFFFFFULL
///
/// Maximum legal AArch64 INTN and UINTN values.
///
#define MAX_INTN ((INTN)0x7FFFFFFFFFFFFFFFULL)
#define MAX_UINTN ((UINTN)0xFFFFFFFFFFFFFFFFULL)
///
/// Minimum legal AArch64 INTN value.
///
#define MIN_INTN (((INTN)-9223372036854775807LL) - 1)
///
/// The stack alignment required for AARCH64
///
#define CPU_STACK_ALIGNMENT 16
///
/// Page allocation granularity for AARCH64
///
#define DEFAULT_PAGE_ALLOCATION_GRANULARITY (0x1000)
#define RUNTIME_PAGE_ALLOCATION_GRANULARITY (0x10000)
//
// Modifier to ensure that all protocol member functions and EFI intrinsics
// use the correct C calling convention. All protocol member functions and
// EFI intrinsics are required to modify their member functions with EFIAPI.
//
#define EFIAPI
// When compiling with Clang, we still use GNU as for the assembler, so we still
// need to define the GCC_ASM* macros.
#if defined(__GNUC__) || defined(__clang__)
///
/// For GNU assembly code, .global or .globl can declare global symbols.
/// Define this macro to unify the usage.
///
#define ASM_GLOBAL .globl
#define GCC_ASM_EXPORT(func__) \
.global _CONCATENATE (__USER_LABEL_PREFIX__, func__) ;\
.type ASM_PFX(func__), %function
#define GCC_ASM_IMPORT(func__) \
.extern _CONCATENATE (__USER_LABEL_PREFIX__, func__)
#endif
/**
Return the pointer to the first instruction of a function given a function pointer.
On ARM CPU architectures, these two pointer values are the same,
so the implementation of this macro is very simple.
@param FunctionPointer A pointer to a function.
@return The pointer to the first instruction of a function given a function pointer.
**/
#define FUNCTION_ENTRY_POINT(FunctionPointer) (VOID *)(UINTN)(FunctionPointer)
#ifndef __USER_LABEL_PREFIX__
#define __USER_LABEL_PREFIX__
#endif
#endif

240
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/** @file
Processor or Compiler specific defines and types for ARM.
Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef __PROCESSOR_BIND_H__
#define __PROCESSOR_BIND_H__
///
/// Define the processor type so other code can make processor based choices
///
#define MDE_CPU_ARM
//
// Make sure we are using the correct packing rules per EFI specification
//
#if !defined(__GNUC__) && !defined(__ASSEMBLER__)
#pragma pack()
#endif
#if defined(_MSC_EXTENSIONS)
//
// Disable some level 4 compilation warnings (same as IA32 and X64)
//
//
// Disabling bitfield type checking warnings.
//
#pragma warning ( disable : 4214 )
//
// Disabling the unreferenced formal parameter warnings.
//
#pragma warning ( disable : 4100 )
//
// Disable slightly different base types warning as CHAR8 * can not be set
// to a constant string.
//
#pragma warning ( disable : 4057 )
//
// ASSERT(FALSE) or while (TRUE) are legal constructs so suppress this warning
//
#pragma warning ( disable : 4127 )
//
// This warning is caused by functions defined but not used. For precompiled header only.
//
#pragma warning ( disable : 4505 )
//
// This warning is caused by empty (after preprocessing) source file. For precompiled header only.
//
#pragma warning ( disable : 4206 )
//
// Disable 'potentially uninitialized local variable X used' warnings
//
#pragma warning ( disable : 4701 )
//
// Disable 'potentially uninitialized local pointer variable X used' warnings
//
#pragma warning ( disable : 4703 )
#endif
//
// RVCT and MSFT don't support the __builtin_unreachable() macro
//
#if defined(__ARMCC_VERSION) || defined(_MSC_EXTENSIONS)
#define UNREACHABLE()
#endif
#if defined(_MSC_EXTENSIONS)
//
// use Microsoft* C compiler dependent integer width types
//
typedef unsigned __int64 UINT64;
typedef __int64 INT64;
typedef unsigned __int32 UINT32;
typedef __int32 INT32;
typedef unsigned short UINT16;
typedef unsigned short CHAR16;
typedef short INT16;
typedef unsigned char BOOLEAN;
typedef unsigned char UINT8;
typedef char CHAR8;
typedef signed char INT8;
#else
//
// Assume standard ARM alignment.
// Need to check portability of long long
//
typedef unsigned long long UINT64;
typedef long long INT64;
typedef unsigned int UINT32;
typedef int INT32;
typedef unsigned short UINT16;
typedef unsigned short CHAR16;
typedef short INT16;
typedef unsigned char BOOLEAN;
typedef unsigned char UINT8;
typedef char CHAR8;
typedef signed char INT8;
#endif
///
/// Unsigned value of native width. (4 bytes on supported 32-bit processor instructions,
/// 8 bytes on supported 64-bit processor instructions)
///
typedef UINT32 UINTN;
///
/// Signed value of native width. (4 bytes on supported 32-bit processor instructions,
/// 8 bytes on supported 64-bit processor instructions)
///
typedef INT32 INTN;
//
// Processor specific defines
//
///
/// A value of native width with the highest bit set.
///
#define MAX_BIT 0x80000000
///
/// A value of native width with the two highest bits set.
///
#define MAX_2_BITS 0xC0000000
///
/// Maximum legal ARM address
///
#define MAX_ADDRESS 0xFFFFFFFF
///
/// Maximum usable address at boot time
///
#define MAX_ALLOC_ADDRESS MAX_ADDRESS
///
/// Maximum legal ARM INTN and UINTN values.
///
#define MAX_INTN ((INTN)0x7FFFFFFF)
#define MAX_UINTN ((UINTN)0xFFFFFFFF)
///
/// Minimum legal ARM INTN value.
///
#define MIN_INTN (((INTN)-2147483647) - 1)
///
/// The stack alignment required for ARM
///
#define CPU_STACK_ALIGNMENT sizeof(UINT64)
///
/// Page allocation granularity for ARM
///
#define DEFAULT_PAGE_ALLOCATION_GRANULARITY (0x1000)
#define RUNTIME_PAGE_ALLOCATION_GRANULARITY (0x1000)
//
// Modifier to ensure that all protocol member functions and EFI intrinsics
// use the correct C calling convention. All protocol member functions and
// EFI intrinsics are required to modify their member functions with EFIAPI.
//
#define EFIAPI
// When compiling with Clang, we still use GNU as for the assembler, so we still
// need to define the GCC_ASM* macros.
#if defined(__GNUC__) || defined(__clang__)
///
/// For GNU assembly code, .global or .globl can declare global symbols.
/// Define this macro to unify the usage.
///
#define ASM_GLOBAL .globl
#if !defined(__APPLE__)
///
/// ARM EABI defines that the linker should not manipulate call relocations
/// (do bl/blx conversion) unless the target symbol has function type.
/// CodeSourcery 2010.09 started requiring the .type to function properly
///
#define INTERWORK_FUNC(func__) .type ASM_PFX(func__), %function
#define GCC_ASM_EXPORT(func__) \
.global _CONCATENATE (__USER_LABEL_PREFIX__, func__) ;\
.type ASM_PFX(func__), %function
#define GCC_ASM_IMPORT(func__) \
.extern _CONCATENATE (__USER_LABEL_PREFIX__, func__)
#else
//
// .type not supported by Apple Xcode tools
//
#define INTERWORK_FUNC(func__)
#define GCC_ASM_EXPORT(func__) \
.globl _CONCATENATE (__USER_LABEL_PREFIX__, func__) \
#define GCC_ASM_IMPORT(name)
#endif
#elif defined(_MSC_EXTENSIONS)
//
// PRESERVE8 is not supported by the MSFT assembler.
//
#define PRESERVE8
#endif
/**
Return the pointer to the first instruction of a function given a function pointer.
On ARM CPU architectures, these two pointer values are the same,
so the implementation of this macro is very simple.
@param FunctionPointer A pointer to a function.
@return The pointer to the first instruction of a function given a function pointer.
**/
#define FUNCTION_ENTRY_POINT(FunctionPointer) (VOID *)(UINTN)(FunctionPointer)
#ifndef __USER_LABEL_PREFIX__
#define __USER_LABEL_PREFIX__
#endif
#endif

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156
src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Ebc/ProcessorBind.h Normal file
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/** @file
Processor or compiler specific defines and types for EBC.
We currently only have one EBC compiler so there may be some Intel compiler
specific functions in this file.
Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef __PROCESSOR_BIND_H__
#define __PROCESSOR_BIND_H__
///
/// Define the processor type so other code can make processor based choices
///
#define MDE_CPU_EBC
//
// Native integer types
//
///
/// 1-byte signed value
///
typedef signed char INT8;
///
/// Logical Boolean. 1-byte value containing 0 for FALSE or a 1 for TRUE. Other
/// values are undefined.
///
typedef unsigned char BOOLEAN;
///
/// 1-byte unsigned value.
///
typedef unsigned char UINT8;
///
/// 1-byte Character.
///
typedef char CHAR8;
///
/// 2-byte signed value.
///
typedef short INT16;
///
/// 2-byte unsigned value.
///
typedef unsigned short UINT16;
///
/// 2-byte Character. Unless otherwise specified all strings are stored in the
/// UTF-16 encoding format as defined by Unicode 2.1 and ISO/IEC 10646 standards.
///
typedef unsigned short CHAR16;
///
/// 4-byte signed value.
///
typedef int INT32;
///
/// 4-byte unsigned value.
///
typedef unsigned int UINT32;
///
/// 8-byte signed value.
///
typedef __int64 INT64;
///
/// 8-byte unsigned value.
///
typedef unsigned __int64 UINT64;
///
/// Signed value of native width. (4 bytes on supported 32-bit processor instructions,
/// 8 bytes on supported 64-bit processor instructions)
/// "long" type scales to the processor native size with EBC compiler
///
typedef long INTN;
///
/// The unsigned value of native width. (4 bytes on supported 32-bit processor instructions;
/// 8 bytes on supported 64-bit processor instructions)
/// "long" type scales to the processor native size with the EBC compiler.
///
typedef unsigned long UINTN;
///
/// A value of native width with the highest bit set.
/// Scalable macro to set the most significant bit in a natural number.
///
#define MAX_BIT ((UINTN)((1ULL << (sizeof (INTN) * 8 - 1))))
///
/// A value of native width with the two highest bits set.
/// Scalable macro to set the most 2 significant bits in a natural number.
///
#define MAX_2_BITS ((UINTN)(3ULL << (sizeof (INTN) * 8 - 2)))
///
/// Maximum legal EBC address
///
#define MAX_ADDRESS ((UINTN)(~0ULL >> (64 - sizeof (INTN) * 8)))
///
/// Maximum usable address at boot time (48 bits using 4 KB pages)
///
#define MAX_ALLOC_ADDRESS MAX_ADDRESS
///
/// Maximum legal EBC INTN and UINTN values.
///
#define MAX_UINTN ((UINTN)(~0ULL >> (64 - sizeof (INTN) * 8)))
#define MAX_INTN ((INTN)(~0ULL >> (65 - sizeof (INTN) * 8)))
///
/// Minimum legal EBC INTN value.
///
#define MIN_INTN (((INTN)-MAX_INTN) - 1)
///
/// The stack alignment required for EBC
///
#define CPU_STACK_ALIGNMENT sizeof(UINTN)
///
/// Page allocation granularity for EBC
///
#define DEFAULT_PAGE_ALLOCATION_GRANULARITY (0x1000)
#define RUNTIME_PAGE_ALLOCATION_GRANULARITY (0x1000)
///
/// Modifier to ensure that all protocol member functions and EFI intrinsics
/// use the correct C calling convention. All protocol member functions and
/// EFI intrinsics are required to modify their member functions with EFIAPI.
///
#ifdef EFIAPI
///
/// If EFIAPI is already defined, then we use that definition.
///
#else
#define EFIAPI
#endif
/**
Return the pointer to the first instruction of a function given a function pointer.
On EBC architectures, these two pointer values are the same,
so the implementation of this macro is very simple.
@param FunctionPointer A pointer to a function.
@return The pointer to the first instruction of a function given a function pointer.
**/
#define FUNCTION_ENTRY_POINT(FunctionPointer) (VOID *)(UINTN)(FunctionPointer)
#ifndef __USER_LABEL_PREFIX__
#define __USER_LABEL_PREFIX__
#endif
#endif

40
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/** @file
GUIDs used for ACPI entries in the EFI system table
These GUIDs point the ACPI tables as defined in the ACPI specifications.
ACPI 2.0 specification defines the ACPI 2.0 GUID. UEFI 2.0 defines the
ACPI 2.0 Table GUID and ACPI Table GUID.
Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@par Revision Reference:
GUIDs defined in UEFI 2.0 spec.
**/
#ifndef __ACPI_GUID_H__
#define __ACPI_GUID_H__
#define ACPI_TABLE_GUID \
{ \
0xeb9d2d30, 0x2d88, 0x11d3, {0x9a, 0x16, 0x0, 0x90, 0x27, 0x3f, 0xc1, 0x4d } \
}
#define EFI_ACPI_TABLE_GUID \
{ \
0x8868e871, 0xe4f1, 0x11d3, {0xbc, 0x22, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \
}
#define ACPI_10_TABLE_GUID ACPI_TABLE_GUID
//
// ACPI 2.0 or newer tables should use EFI_ACPI_TABLE_GUID.
//
#define EFI_ACPI_20_TABLE_GUID EFI_ACPI_TABLE_GUID
extern EFI_GUID gEfiAcpiTableGuid;
extern EFI_GUID gEfiAcpi10TableGuid;
extern EFI_GUID gEfiAcpi20TableGuid;
#endif

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src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Guid/Apriori.h Normal file
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/** @file
GUID used as an FV filename for A Priori file. The A Priori file contains a
list of FV filenames that the DXE dispatcher will schedule reguardless of
the dependency grammar.
Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@par Revision Reference:
GUID introduced in PI Version 1.0.
**/
#ifndef __APRIORI_GUID_H__
#define __APRIORI_GUID_H__
#define EFI_APRIORI_GUID \
{ \
0xfc510ee7, 0xffdc, 0x11d4, {0xbd, 0x41, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \
}
extern EFI_GUID gAprioriGuid;
#endif

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src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Guid/AprioriFileName.h Normal file
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/** @file
The GUID PEI_APRIORI_FILE_NAME_GUID definition is the file
name of the PEI a priori file that is stored in a firmware
volume.
Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@par Revision Reference:
GUID introduced in PI Version 1.0.
**/
#ifndef __PEI_APRIORI_FILE_NAME_H__
#define __PEI_APRIORI_FILE_NAME_H__
#define PEI_APRIORI_FILE_NAME_GUID \
{ 0x1b45cc0a, 0x156a, 0x428a, { 0x62, 0XAF, 0x49, 0x86, 0x4d, 0xa0, 0xe6, 0xe6 } }
///
/// This file must be of type EFI_FV_FILETYPE_FREEFORM and must
/// contain a single section of type EFI_SECTION_RAW. For details on
/// firmware volumes, firmware file types, and firmware file section
/// types.
///
typedef struct {
///
/// An array of zero or more EFI_GUID type entries that match the file names of PEIM
/// modules in the same Firmware Volume. The maximum number of entries.
///
EFI_GUID FileNamesWithinVolume[1];
} PEI_APRIORI_FILE_CONTENTS;
extern EFI_GUID gPeiAprioriFileNameGuid;
#endif

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/** @file
Block Translation Table (BTT) metadata layout definition.
BTT is a layout and set of rules for doing block I/O that provide powerfail
write atomicity of a single block.
Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@par Revision Reference:
This metadata layout definition was introduced in UEFI Specification 2.7.
**/
#ifndef _BTT_H_
#define _BTT_H_
///
/// The BTT layout and behavior is described by the GUID as below.
///
#define EFI_BTT_ABSTRACTION_GUID \
{ \
0x18633bfc, 0x1735, 0x4217, { 0x8a, 0xc9, 0x17, 0x23, 0x92, 0x82, 0xd3, 0xf8 } \
}
//
// Alignment of all BTT structures
//
#define EFI_BTT_ALIGNMENT 4096
#define EFI_BTT_INFO_UNUSED_LEN 3968
#define EFI_BTT_INFO_BLOCK_SIG_LEN 16
///
/// Indicate inconsistent metadata or lost metadata due to unrecoverable media errors.
///
#define EFI_BTT_INFO_BLOCK_FLAGS_ERROR 0x00000001
#define EFI_BTT_INFO_BLOCK_MAJOR_VERSION 2
#define EFI_BTT_INFO_BLOCK_MINOR_VERSION 0
///
/// Block Translation Table (BTT) Info Block
///
typedef struct _EFI_BTT_INFO_BLOCK {
///
/// Signature of the BTT Index Block data structure.
/// Shall be "BTT_ARENA_INFO\0\0".
///
CHAR8 Sig[EFI_BTT_INFO_BLOCK_SIG_LEN];
///
/// UUID identifying this BTT instance.
///
GUID Uuid;
///
/// UUID of containing namespace.
///
GUID ParentUuid;
///
/// Attributes of this BTT Info Block.
///
UINT32 Flags;
///
/// Major version number. Currently at version 2.
///
UINT16 Major;
///
/// Minor version number. Currently at version 0.
///
UINT16 Minor;
///
/// Advertised LBA size in bytes. I/O requests shall be in this size chunk.
///
UINT32 ExternalLbaSize;
///
/// Advertised number of LBAs in this arena.
///
UINT32 ExternalNLba;
///
/// Internal LBA size shall be greater than or equal to ExternalLbaSize and shall not be smaller than 512 bytes.
///
UINT32 InternalLbaSize;
///
/// Number of internal blocks in the arena data area.
///
UINT32 InternalNLba;
///
/// Number of free blocks maintained for writes to this arena.
///
UINT32 NFree;
///
/// The size of this info block in bytes.
///
UINT32 InfoSize;
///
/// Offset of next arena, relative to the beginning of this arena.
///
UINT64 NextOff;
///
/// Offset of the data area for this arena, relative to the beginning of this arena.
///
UINT64 DataOff;
///
/// Offset of the map for this arena, relative to the beginning of this arena.
///
UINT64 MapOff;
///
/// Offset of the flog for this arena, relative to the beginning of this arena.
///
UINT64 FlogOff;
///
/// Offset of the backup copy of this arena's info block, relative to the beginning of this arena.
///
UINT64 InfoOff;
///
/// Shall be zero.
///
CHAR8 Unused[EFI_BTT_INFO_UNUSED_LEN];
///
/// 64-bit Fletcher64 checksum of all fields.
///
UINT64 Checksum;
} EFI_BTT_INFO_BLOCK;
///
/// BTT Map entry maps an LBA that indexes into the arena, to its actual location.
///
typedef struct _EFI_BTT_MAP_ENTRY {
///
/// Post-map LBA number (block number in this arena's data area)
///
UINT32 PostMapLba : 30;
///
/// When set and Zero is not set, reads on this block return an error.
/// When set and Zero is set, indicate a map entry in its normal, non-error state.
///
UINT32 Error : 1;
///
/// When set and Error is not set, reads on this block return a full block of zeros.
/// When set and Error is set, indicate a map entry in its normal, non-error state.
///
UINT32 Zero : 1;
} EFI_BTT_MAP_ENTRY;
///
/// Alignment of each flog structure
///
#define EFI_BTT_FLOG_ENTRY_ALIGNMENT 64
///
/// The BTT Flog is both a free list and a log.
/// The Flog size is determined by the EFI_BTT_INFO_BLOCK.NFree which determines how many of these flog
/// entries there are.
/// The Flog location is the highest aligned address in the arena after space for the backup info block.
///
typedef struct _EFI_BTT_FLOG {
///
/// Last pre-map LBA written using this flog entry.
///
UINT32 Lba0;
///
/// Old post-map LBA.
///
UINT32 OldMap0;
///
/// New post-map LBA.
///
UINT32 NewMap0;
///
/// The Seq0 field in each flog entry is used to determine which set of fields is newer between the two sets
/// (Lba0, OldMap0, NewMpa0, Seq0 vs Lba1, Oldmap1, NewMap1, Seq1).
///
UINT32 Seq0;
///
/// Alternate lba entry.
///
UINT32 Lba1;
///
/// Alternate old entry.
///
UINT32 OldMap1;
///
/// Alternate new entry.
///
UINT32 NewMap1;
///
/// Alternate Seq entry.
///
UINT32 Seq1;
} EFI_BTT_FLOG;
extern GUID gEfiBttAbstractionGuid;
#endif //_BTT_H_

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/** @file
Guid & data structure used for Capsule process result variables
Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@par Revision Reference:
GUIDs defined in UEFI 2.4 spec.
**/
#ifndef _CAPSULE_REPORT_GUID_H__
#define _CAPSULE_REPORT_GUID_H__
//
// This is the GUID for capsule result variable.
//
#define EFI_CAPSULE_REPORT_GUID \
{ \
0x39b68c46, 0xf7fb, 0x441b, {0xb6, 0xec, 0x16, 0xb0, 0xf6, 0x98, 0x21, 0xf3 } \
}
typedef struct {
///
/// Size in bytes of the variable including any data beyond header as specified by CapsuleGuid
///
UINT32 VariableTotalSize;
///
/// For alignment
///
UINT32 Reserved;
///
/// Guid from EFI_CAPSULE_HEADER
///
EFI_GUID CapsuleGuid;
///
/// Timestamp using system time when processing completed
///
EFI_TIME CapsuleProcessed;
///
/// Result of the capsule processing. Exact interpretation of any error code may depend
/// upon type of capsule processed
///
EFI_STATUS CapsuleStatus;
} EFI_CAPSULE_RESULT_VARIABLE_HEADER;
typedef struct {
///
/// Version of this structure, currently 0x00000001
///
UINT16 Version;
///
/// The index of the payload within the FMP capsule which was processed to generate this report
/// Starting from zero
///
UINT8 PayloadIndex;
///
/// The UpdateImageIndex from EFI_FIRMWARE_MANAGEMENT_CAPSULE_IMAGE_HEADER
/// (after unsigned conversion from UINT8 to UINT16).
///
UINT8 UpdateImageIndex;
///
/// The UpdateImageTypeId Guid from EFI_FIRMWARE_MANAGEMENT_CAPSULE_IMAGE_HEADER.
///
EFI_GUID UpdateImageTypeId;
///
/// In case of capsule loaded from disk, the zero-terminated array containing file name of capsule that was processed.
/// In case of capsule submitted directly to UpdateCapsule() there is no file name, and this field is required to contain a single 16-bit zero character
/// which is included in VariableTotalSize.
///
/// CHAR16 CapsuleFileName[];
///
///
/// This field will contain a zero-terminated CHAR16 string containing the text representation of the device path of device publishing Firmware Management Protocol
/// (if present). In case where device path is not present and the target is not otherwise known to firmware, or when payload was blocked by policy, or skipped,
/// this field is required to contain a single 16-bit zero character which is included in VariableTotalSize.
///
/// CHAR16 CapsuleTarget[];
///
} EFI_CAPSULE_RESULT_VARIABLE_FMP;
typedef struct {
///
/// Version of this structure, currently 0x00000001
///
UINT32 Version;
///
/// The unique identifier of the capsule whose processing result is recorded in this variable.
/// 0x00000000 - 0xEFFFFFFF - Implementation Reserved
/// 0xF0000000 - 0xFFFFFFFF - Specification Reserved
/// #define REDFISH_DEFINED_JSON_SCHEMA 0xF000000
/// The JSON payload shall conform to a Redfish-defined JSON schema, see DMTF-Redfish
/// Specification.
///
UINT32 CapsuleId;
///
/// The length of Resp in bytes.
///
UINT32 RespLength;
///
/// Variable length buffer containing the replied JSON payload to the caller who delivered JSON
/// capsule to system. The definition of the JSON schema used in the replied payload is beyond
/// the scope of this specification.
///
UINT8 Resp[];
} EFI_CAPSULE_RESULT_VARIABLE_JSON;
extern EFI_GUID gEfiCapsuleReportGuid;
#endif

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/** @file
GUID and related data structures used with the Debug Image Info Table.
Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@par Revision Reference:
GUID defined in UEFI 2.0 spec.
**/
#ifndef __DEBUG_IMAGE_INFO_GUID_H__
#define __DEBUG_IMAGE_INFO_GUID_H__
#include <Protocol/LoadedImage.h>
///
/// EFI_DEBUG_IMAGE_INFO_TABLE configuration table GUID declaration.
///
#define EFI_DEBUG_IMAGE_INFO_TABLE_GUID \
{ \
0x49152e77, 0x1ada, 0x4764, {0xb7, 0xa2, 0x7a, 0xfe, 0xfe, 0xd9, 0x5e, 0x8b } \
}
#define EFI_DEBUG_IMAGE_INFO_UPDATE_IN_PROGRESS 0x01
#define EFI_DEBUG_IMAGE_INFO_TABLE_MODIFIED 0x02
#define EFI_DEBUG_IMAGE_INFO_TYPE_NORMAL 0x01
typedef struct {
UINT64 Signature; ///< A constant UINT64 that has the value EFI_SYSTEM_TABLE_SIGNATURE
EFI_PHYSICAL_ADDRESS EfiSystemTableBase; ///< The physical address of the EFI system table.
UINT32 Crc32; ///< A 32-bit CRC value that is used to verify the EFI_SYSTEM_TABLE_POINTER structure is valid.
} EFI_SYSTEM_TABLE_POINTER;
typedef struct {
///
/// Indicates the type of image info structure. For PE32 EFI images,
/// this is set to EFI_DEBUG_IMAGE_INFO_TYPE_NORMAL.
///
UINT32 ImageInfoType;
///
/// A pointer to an instance of the loaded image protocol for the associated image.
///
EFI_LOADED_IMAGE_PROTOCOL *LoadedImageProtocolInstance;
///
/// Indicates the image handle of the associated image.
///
EFI_HANDLE ImageHandle;
} EFI_DEBUG_IMAGE_INFO_NORMAL;
typedef union {
UINT32 *ImageInfoType;
EFI_DEBUG_IMAGE_INFO_NORMAL *NormalImage;
} EFI_DEBUG_IMAGE_INFO;
typedef struct {
///
/// UpdateStatus is used by the system to indicate the state of the debug image info table.
///
volatile UINT32 UpdateStatus;
///
/// The number of EFI_DEBUG_IMAGE_INFO elements in the array pointed to by EfiDebugImageInfoTable.
///
UINT32 TableSize;
///
/// A pointer to the first element of an array of EFI_DEBUG_IMAGE_INFO structures.
///
EFI_DEBUG_IMAGE_INFO *EfiDebugImageInfoTable;
} EFI_DEBUG_IMAGE_INFO_TABLE_HEADER;
extern EFI_GUID gEfiDebugImageInfoTableGuid;
#endif

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/** @file
GUID used to identify the DXE Services Table
Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@par Revision Reference:
GUID introduced in PI Version 1.0.
**/
#ifndef __DXE_SERVICES_GUID_H__
#define __DXE_SERVICES_GUID_H__
#define DXE_SERVICES_TABLE_GUID \
{ \
0x5ad34ba, 0x6f02, 0x4214, {0x95, 0x2e, 0x4d, 0xa0, 0x39, 0x8e, 0x2b, 0xb9 } \
}
extern EFI_GUID gEfiDxeServicesTableGuid;
#endif

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/** @file
GUIDs for gBS->CreateEventEx Event Groups. Defined in UEFI spec 2.0 and PI 1.2.1.
Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef __EVENT_GROUP_GUID__
#define __EVENT_GROUP_GUID__
#define EFI_EVENT_GROUP_EXIT_BOOT_SERVICES \
{ 0x27abf055, 0xb1b8, 0x4c26, { 0x80, 0x48, 0x74, 0x8f, 0x37, 0xba, 0xa2, 0xdf } }
extern EFI_GUID gEfiEventExitBootServicesGuid;
#define EFI_EVENT_GROUP_VIRTUAL_ADDRESS_CHANGE \
{ 0x13fa7698, 0xc831, 0x49c7, { 0x87, 0xea, 0x8f, 0x43, 0xfc, 0xc2, 0x51, 0x96 } }
extern EFI_GUID gEfiEventVirtualAddressChangeGuid;
#define EFI_EVENT_GROUP_MEMORY_MAP_CHANGE \
{ 0x78bee926, 0x692f, 0x48fd, { 0x9e, 0xdb, 0x1, 0x42, 0x2e, 0xf0, 0xd7, 0xab } }
extern EFI_GUID gEfiEventMemoryMapChangeGuid;
#define EFI_EVENT_GROUP_READY_TO_BOOT \
{ 0x7ce88fb3, 0x4bd7, 0x4679, { 0x87, 0xa8, 0xa8, 0xd8, 0xde, 0xe5, 0x0d, 0x2b } }
extern EFI_GUID gEfiEventReadyToBootGuid;
#define EFI_EVENT_GROUP_DXE_DISPATCH_GUID \
{ 0x7081e22f, 0xcac6, 0x4053, { 0x94, 0x68, 0x67, 0x57, 0x82, 0xcf, 0x88, 0xe5 }}
extern EFI_GUID gEfiEventDxeDispatchGuid;
#define EFI_END_OF_DXE_EVENT_GROUP_GUID \
{ 0x2ce967a, 0xdd7e, 0x4ffc, { 0x9e, 0xe7, 0x81, 0xc, 0xf0, 0x47, 0x8, 0x80 } }
extern EFI_GUID gEfiEndOfDxeEventGroupGuid;
#endif

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/** @file
GUID is the name of events used with CreateEventEx in order to be notified
when the EFI boot manager is about to boot a legacy boot option.
Events of this type are notificated just before Int19h is invoked.
Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@par Revision Reference:
GUID introduced in PI Version 1.0.
**/
#ifndef __EVENT_LEGACY_BIOS_GUID_H__
#define __EVENT_LEGACY_BIOS_GUID_H__
#define EFI_EVENT_LEGACY_BOOT_GUID \
{ 0x2a571201, 0x4966, 0x47f6, {0x8b, 0x86, 0xf3, 0x1e, 0x41, 0xf3, 0x2f, 0x10 } }
extern EFI_GUID gEfiEventLegacyBootGuid;
#endif

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/** @file
Provides a GUID and a data structure that can be used with EFI_FILE_PROTOCOL.SetInfo()
and EFI_FILE_PROTOCOL.GetInfo() to set or get generic file information.
This GUID is defined in UEFI specification.
Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef __FILE_INFO_H__
#define __FILE_INFO_H__
#define EFI_FILE_INFO_ID \
{ \
0x9576e92, 0x6d3f, 0x11d2, {0x8e, 0x39, 0x0, 0xa0, 0xc9, 0x69, 0x72, 0x3b } \
}
typedef struct {
///
/// The size of the EFI_FILE_INFO structure, including the Null-terminated FileName string.
///
UINT64 Size;
///
/// The size of the file in bytes.
///
UINT64 FileSize;
///
/// PhysicalSize The amount of physical space the file consumes on the file system volume.
///
UINT64 PhysicalSize;
///
/// The time the file was created.
///
EFI_TIME CreateTime;
///
/// The time when the file was last accessed.
///
EFI_TIME LastAccessTime;
///
/// The time when the file's contents were last modified.
///
EFI_TIME ModificationTime;
///
/// The attribute bits for the file.
///
UINT64 Attribute;
///
/// The Null-terminated name of the file.
///
CHAR16 FileName[1];
} EFI_FILE_INFO;
///
/// The FileName field of the EFI_FILE_INFO data structure is variable length.
/// Whenever code needs to know the size of the EFI_FILE_INFO data structure, it needs to
/// be the size of the data structure without the FileName field. The following macro
/// computes this size correctly no matter how big the FileName array is declared.
/// This is required to make the EFI_FILE_INFO data structure ANSI compilant.
///
#define SIZE_OF_EFI_FILE_INFO OFFSET_OF (EFI_FILE_INFO, FileName)
extern EFI_GUID gEfiFileInfoGuid;
#endif

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/** @file
Provides a GUID and a data structure that can be used with EFI_FILE_PROTOCOL.GetInfo()
or EFI_FILE_PROTOCOL.SetInfo() to get or set information about the system's volume.
This GUID is defined in UEFI specification.
Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef __FILE_SYSTEM_INFO_H__
#define __FILE_SYSTEM_INFO_H__
#define EFI_FILE_SYSTEM_INFO_ID \
{ \
0x9576e93, 0x6d3f, 0x11d2, {0x8e, 0x39, 0x0, 0xa0, 0xc9, 0x69, 0x72, 0x3b } \
}
typedef struct {
///
/// The size of the EFI_FILE_SYSTEM_INFO structure, including the Null-terminated VolumeLabel string.
///
UINT64 Size;
///
/// TRUE if the volume only supports read access.
///
BOOLEAN ReadOnly;
///
/// The number of bytes managed by the file system.
///
UINT64 VolumeSize;
///
/// The number of available bytes for use by the file system.
///
UINT64 FreeSpace;
///
/// The nominal block size by which files are typically grown.
///
UINT32 BlockSize;
///
/// The Null-terminated string that is the volume's label.
///
CHAR16 VolumeLabel[1];
} EFI_FILE_SYSTEM_INFO;
///
/// The VolumeLabel field of the EFI_FILE_SYSTEM_INFO data structure is variable length.
/// Whenever code needs to know the size of the EFI_FILE_SYSTEM_INFO data structure, it needs
/// to be the size of the data structure without the VolumeLable field. The following macro
/// computes this size correctly no matter how big the VolumeLable array is declared.
/// This is required to make the EFI_FILE_SYSTEM_INFO data structure ANSI compilant.
///
#define SIZE_OF_EFI_FILE_SYSTEM_INFO OFFSET_OF (EFI_FILE_SYSTEM_INFO, VolumeLabel)
extern EFI_GUID gEfiFileSystemInfoGuid;
#endif

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/** @file
Provides a GUID and a data structure that can be used with EFI_FILE_PROTOCOL.GetInfo()
or EFI_FILE_PROTOCOL.SetInfo() to get or set the system's volume label.
This GUID is defined in UEFI specification.
Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef __FILE_SYSTEM_VOLUME_LABEL_INFO_H__
#define __FILE_SYSTEM_VOLUME_LABEL_INFO_H__
#define EFI_FILE_SYSTEM_VOLUME_LABEL_ID \
{ \
0xDB47D7D3, 0xFE81, 0x11d3, {0x9A, 0x35, 0x00, 0x90, 0x27, 0x3F, 0xC1, 0x4D } \
}
typedef struct {
///
/// The Null-terminated string that is the volume's label.
///
CHAR16 VolumeLabel[1];
} EFI_FILE_SYSTEM_VOLUME_LABEL;
#define SIZE_OF_EFI_FILE_SYSTEM_VOLUME_LABEL \
OFFSET_OF (EFI_FILE_SYSTEM_VOLUME_LABEL, VolumeLabel)
extern EFI_GUID gEfiFileSystemVolumeLabelInfoIdGuid;
#endif

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/** @file
GUID is used to define the signed section.
Copyright (c) 2013 - 2018, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@par Revision Reference:
GUID introduced in PI Version 1.2.1.
**/
#ifndef __FIRMWARE_CONTENTS_SIGNED_GUID_H__
#define __FIRMWARE_CONTENTS_SIGNED_GUID_H__
#define EFI_FIRMWARE_CONTENTS_SIGNED_GUID \
{ 0xf9d89e8, 0x9259, 0x4f76, {0xa5, 0xaf, 0xc, 0x89, 0xe3, 0x40, 0x23, 0xdf } }
extern EFI_GUID gEfiFirmwareContentsSignedGuid;
#endif

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/** @file
Guid used to define the Firmware File System 2.
Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@par Revision Reference:
GUIDs introduced in PI Version 1.0.
**/
#ifndef __FIRMWARE_FILE_SYSTEM2_GUID_H__
#define __FIRMWARE_FILE_SYSTEM2_GUID_H__
///
/// The firmware volume header contains a data field for
/// the file system GUID
///
#define EFI_FIRMWARE_FILE_SYSTEM2_GUID \
{ 0x8c8ce578, 0x8a3d, 0x4f1c, { 0x99, 0x35, 0x89, 0x61, 0x85, 0xc3, 0x2d, 0xd3 } }
///
/// A Volume Top File (VTF) is a file that must be
/// located such that the last byte of the file is
/// also the last byte of the firmware volume
///
#define EFI_FFS_VOLUME_TOP_FILE_GUID \
{ 0x1BA0062E, 0xC779, 0x4582, { 0x85, 0x66, 0x33, 0x6A, 0xE8, 0xF7, 0x8F, 0x9 } }
extern EFI_GUID gEfiFirmwareFileSystem2Guid;
extern EFI_GUID gEfiFirmwareVolumeTopFileGuid;
#endif

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/** @file
Guid used to define the Firmware File System 3.
Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@par Revision Reference:
GUIDs introduced in PI Version 1.0.
**/
#ifndef __FIRMWARE_FILE_SYSTEM3_GUID_H__
#define __FIRMWARE_FILE_SYSTEM3_GUID_H__
///
/// The firmware volume header contains a data field for the file system GUID
/// {5473C07A-3DCB-4dca-BD6F-1E9689E7349A}
///
#define EFI_FIRMWARE_FILE_SYSTEM3_GUID \
{ 0x5473c07a, 0x3dcb, 0x4dca, { 0xbd, 0x6f, 0x1e, 0x96, 0x89, 0xe7, 0x34, 0x9a }}
extern EFI_GUID gEfiFirmwareFileSystem3Guid;
#endif // __FIRMWARE_FILE_SYSTEM3_GUID_H__

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/** @file
Guid & data structure used for Delivering Capsules Containing Updates to Firmware
Management Protocol
Copyright (c) 2013 - 2015, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@par Revision Reference:
GUIDs defined in UEFI 2.4 spec.
**/
#ifndef _FMP_CAPSULE_GUID_H__
#define _FMP_CAPSULE_GUID_H__
//
// This is the GUID of the capsule for Firmware Management Protocol.
//
#define EFI_FIRMWARE_MANAGEMENT_CAPSULE_ID_GUID \
{ \
0x6dcbd5ed, 0xe82d, 0x4c44, {0xbd, 0xa1, 0x71, 0x94, 0x19, 0x9a, 0xd9, 0x2a } \
}
#pragma pack(1)
typedef struct {
UINT32 Version;
///
/// The number of drivers included in the capsule and the number of corresponding
/// offsets stored in ItemOffsetList array.
///
UINT16 EmbeddedDriverCount;
///
/// The number of payload items included in the capsule and the number of
/// corresponding offsets stored in the ItemOffsetList array.
///
UINT16 PayloadItemCount;
///
/// Variable length array of dimension [EmbeddedDriverCount + PayloadItemCount]
/// containing offsets of each of the drivers and payload items contained within the capsule
///
// UINT64 ItemOffsetList[];
} EFI_FIRMWARE_MANAGEMENT_CAPSULE_HEADER;
typedef struct {
UINT32 Version;
///
/// Used to identify device firmware targeted by this update. This guid is matched by
/// system firmware against ImageTypeId field within a EFI_FIRMWARE_IMAGE_DESCRIPTOR
///
EFI_GUID UpdateImageTypeId;
///
/// Passed as ImageIndex in call to EFI_FIRMWARE_MANAGEMENT_PROTOCOL.SetImage()
///
UINT8 UpdateImageIndex;
UINT8 reserved_bytes[3];
///
/// Size of the binary update image which immediately follows this structure
///
UINT32 UpdateImageSize;
///
/// Size of the VendorCode bytes which optionally immediately follow binary update image in the capsule
///
UINT32 UpdateVendorCodeSize;
///
/// The HardwareInstance to target with this update. If value is zero it means match all
/// HardwareInstances. This field allows update software to target only a single device in
/// cases where there are more than one device with the same ImageTypeId GUID.
/// This header is outside the signed data of the Authentication Info structure and
/// therefore can be modified without changing the Auth data.
///
UINT64 UpdateHardwareInstance;
///
/// A 64-bit bitmask that determines what sections are added to the payload.
/// #define CAPSULE_SUPPORT_AUTHENTICATION 0x0000000000000001
/// #define CAPSULE_SUPPORT_DEPENDENCY 0x0000000000000002
///
UINT64 ImageCapsuleSupport;
} EFI_FIRMWARE_MANAGEMENT_CAPSULE_IMAGE_HEADER;
#pragma pack()
#define EFI_FIRMWARE_MANAGEMENT_CAPSULE_HEADER_INIT_VERSION 0x00000001
#define EFI_FIRMWARE_MANAGEMENT_CAPSULE_IMAGE_HEADER_INIT_VERSION 0x00000003
#define CAPSULE_SUPPORT_AUTHENTICATION 0x0000000000000001
#define CAPSULE_SUPPORT_DEPENDENCY 0x0000000000000002
extern EFI_GUID gEfiFmpCapsuleGuid;
#endif

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/** @file
GUID for EFI (NVRAM) Variables.
Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@par Revision Reference:
GUID defined in UEFI 2.1
**/
#ifndef __GLOBAL_VARIABLE_GUID_H__
#define __GLOBAL_VARIABLE_GUID_H__
#define EFI_GLOBAL_VARIABLE \
{ \
0x8BE4DF61, 0x93CA, 0x11d2, {0xAA, 0x0D, 0x00, 0xE0, 0x98, 0x03, 0x2B, 0x8C } \
}
extern EFI_GUID gEfiGlobalVariableGuid;
//
// Follow UEFI 2.4 spec:
// To prevent name collisions with possible future globally defined variables,
// other internal firmware data variables that are not defined here must be
// saved with a unique VendorGuid other than EFI_GLOBAL_VARIABLE or
// any other GUID defined by the UEFI Specification. Implementations must
// only permit the creation of variables with a UEFI Specification-defined
// VendorGuid when these variables are documented in the UEFI Specification.
//
// Note: except the globally defined variables defined below, the spec also defines
// L"Boot####" - A boot load option.
// L"Driver####" - A driver load option.
// L"SysPrep####" - A System Prep application load option.
// L"Key####" - Describes hot key relationship with a Boot#### load option.
// The attribute for them is NV+BS+RT, #### is a printed hex value, and no 0x or h
// is included in the hex value. They can not be expressed as a #define like other globally
// defined variables, it is because we can not list the Boot0000, Boot0001, etc one by one.
//
///
/// The language codes that the firmware supports. This value is deprecated.
/// Its attribute is BS+RT.
///
#define EFI_LANG_CODES_VARIABLE_NAME L"LangCodes"
///
/// The language code that the system is configured for. This value is deprecated.
/// Its attribute is NV+BS+RT.
///
#define EFI_LANG_VARIABLE_NAME L"Lang"
///
/// The firmware's boot managers timeout, in seconds, before initiating the default boot selection.
/// Its attribute is NV+BS+RT.
///
#define EFI_TIME_OUT_VARIABLE_NAME L"Timeout"
///
/// The language codes that the firmware supports.
/// Its attribute is BS+RT.
///
#define EFI_PLATFORM_LANG_CODES_VARIABLE_NAME L"PlatformLangCodes"
///
/// The language code that the system is configured for.
/// Its attribute is NV+BS+RT.
///
#define EFI_PLATFORM_LANG_VARIABLE_NAME L"PlatformLang"
///
/// The device path of the default input/output/error output console.
/// Its attribute is NV+BS+RT.
///
#define EFI_CON_IN_VARIABLE_NAME L"ConIn"
#define EFI_CON_OUT_VARIABLE_NAME L"ConOut"
#define EFI_ERR_OUT_VARIABLE_NAME L"ErrOut"
///
/// The device path of all possible input/output/error output devices.
/// Its attribute is BS+RT.
///
#define EFI_CON_IN_DEV_VARIABLE_NAME L"ConInDev"
#define EFI_CON_OUT_DEV_VARIABLE_NAME L"ConOutDev"
#define EFI_ERR_OUT_DEV_VARIABLE_NAME L"ErrOutDev"
///
/// The ordered boot option load list.
/// Its attribute is NV+BS+RT.
///
#define EFI_BOOT_ORDER_VARIABLE_NAME L"BootOrder"
///
/// The boot option for the next boot only.
/// Its attribute is NV+BS+RT.
///
#define EFI_BOOT_NEXT_VARIABLE_NAME L"BootNext"
///
/// The boot option that was selected for the current boot.
/// Its attribute is BS+RT.
///
#define EFI_BOOT_CURRENT_VARIABLE_NAME L"BootCurrent"
///
/// The types of boot options supported by the boot manager. Should be treated as read-only.
/// Its attribute is BS+RT.
///
#define EFI_BOOT_OPTION_SUPPORT_VARIABLE_NAME L"BootOptionSupport"
///
/// The ordered driver load option list.
/// Its attribute is NV+BS+RT.
///
#define EFI_DRIVER_ORDER_VARIABLE_NAME L"DriverOrder"
///
/// The ordered System Prep Application load option list.
/// Its attribute is NV+BS+RT.
///
#define EFI_SYS_PREP_ORDER_VARIABLE_NAME L"SysPrepOrder"
///
/// Identifies the level of hardware error record persistence
/// support implemented by the platform. This variable is
/// only modified by firmware and is read-only to the OS.
/// Its attribute is NV+BS+RT.
///
#define EFI_HW_ERR_REC_SUPPORT_VARIABLE_NAME L"HwErrRecSupport"
///
/// Whether the system is operating in setup mode (1) or not (0).
/// All other values are reserved. Should be treated as read-only.
/// Its attribute is BS+RT.
///
#define EFI_SETUP_MODE_NAME L"SetupMode"
///
/// The Key Exchange Key Signature Database.
/// Its attribute is NV+BS+RT+AT.
///
#define EFI_KEY_EXCHANGE_KEY_NAME L"KEK"
///
/// The public Platform Key.
/// Its attribute is NV+BS+RT+AT.
///
#define EFI_PLATFORM_KEY_NAME L"PK"
///
/// Array of GUIDs representing the type of signatures supported
/// by the platform firmware. Should be treated as read-only.
/// Its attribute is BS+RT.
///
#define EFI_SIGNATURE_SUPPORT_NAME L"SignatureSupport"
///
/// Whether the platform firmware is operating in Secure boot mode (1) or not (0).
/// All other values are reserved. Should be treated as read-only.
/// Its attribute is BS+RT.
///
#define EFI_SECURE_BOOT_MODE_NAME L"SecureBoot"
///
/// The OEM's default Key Exchange Key Signature Database. Should be treated as read-only.
/// Its attribute is BS+RT.
///
#define EFI_KEK_DEFAULT_VARIABLE_NAME L"KEKDefault"
///
/// The OEM's default public Platform Key. Should be treated as read-only.
/// Its attribute is BS+RT.
///
#define EFI_PK_DEFAULT_VARIABLE_NAME L"PKDefault"
///
/// The OEM's default secure boot signature store. Should be treated as read-only.
/// Its attribute is BS+RT.
///
#define EFI_DB_DEFAULT_VARIABLE_NAME L"dbDefault"
///
/// The OEM's default secure boot blacklist signature store. Should be treated as read-only.
/// Its attribute is BS+RT.
///
#define EFI_DBX_DEFAULT_VARIABLE_NAME L"dbxDefault"
///
/// The OEM's default secure boot timestamp signature store. Should be treated as read-only.
/// Its attribute is BS+RT.
///
#define EFI_DBT_DEFAULT_VARIABLE_NAME L"dbtDefault"
///
/// Allows the firmware to indicate supported features and actions to the OS.
/// Its attribute is BS+RT.
///
#define EFI_OS_INDICATIONS_SUPPORT_VARIABLE_NAME L"OsIndicationsSupported"
///
/// Allows the OS to request the firmware to enable certain features and to take certain actions.
/// Its attribute is NV+BS+RT.
///
#define EFI_OS_INDICATIONS_VARIABLE_NAME L"OsIndications"
///
/// Whether the system is configured to use only vendor provided
/// keys or not. Should be treated as read-only.
/// Its attribute is BS+RT.
///
#define EFI_VENDOR_KEYS_VARIABLE_NAME L"VendorKeys"
#endif

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/** @file
Guids used for the GPT (GUID Partition Table)
GPT defines a new disk partitioning scheme and also describes
usage of the legacy Master Boot Record (MBR) partitioning scheme.
Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@par Revision Reference:
GUIDs defined in UEFI 2.1 spec.
**/
#ifndef __GPT_GUID_H__
#define __GPT_GUID_H__
#define EFI_PART_TYPE_UNUSED_GUID \
{ \
0x00000000, 0x0000, 0x0000, {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 } \
}
#define EFI_PART_TYPE_EFI_SYSTEM_PART_GUID \
{ \
0xc12a7328, 0xf81f, 0x11d2, {0xba, 0x4b, 0x00, 0xa0, 0xc9, 0x3e, 0xc9, 0x3b } \
}
#define EFI_PART_TYPE_LEGACY_MBR_GUID \
{ \
0x024dee41, 0x33e7, 0x11d3, {0x9d, 0x69, 0x00, 0x08, 0xc7, 0x81, 0xf3, 0x9f } \
}
extern EFI_GUID gEfiPartTypeUnusedGuid;
extern EFI_GUID gEfiPartTypeSystemPartGuid;
extern EFI_GUID gEfiPartTypeLegacyMbrGuid;
#endif

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/** @file
Hob guid for Information about the graphics mode.
Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@par Revision Reference:
This HOB is introduced in in PI Version 1.4.
**/
#ifndef _GRAPHICS_INFO_HOB_GUID_H_
#define _GRAPHICS_INFO_HOB_GUID_H_
#include <Protocol/GraphicsOutput.h>
#define EFI_PEI_GRAPHICS_INFO_HOB_GUID \
{ \
0x39f62cce, 0x6825, 0x4669, { 0xbb, 0x56, 0x54, 0x1a, 0xba, 0x75, 0x3a, 0x07 } \
}
#define EFI_PEI_GRAPHICS_DEVICE_INFO_HOB_GUID \
{ \
0xe5cb2ac9, 0xd35d, 0x4430, { 0x93, 0x6e, 0x1d, 0xe3, 0x32, 0x47, 0x8d, 0xe7 } \
}
typedef struct {
EFI_PHYSICAL_ADDRESS FrameBufferBase;
UINT32 FrameBufferSize;
EFI_GRAPHICS_OUTPUT_MODE_INFORMATION GraphicsMode;
} EFI_PEI_GRAPHICS_INFO_HOB;
typedef struct {
UINT16 VendorId; ///< Ignore if the value is 0xFFFF.
UINT16 DeviceId; ///< Ignore if the value is 0xFFFF.
UINT16 SubsystemVendorId; ///< Ignore if the value is 0xFFFF.
UINT16 SubsystemId; ///< Ignore if the value is 0xFFFF.
UINT8 RevisionId; ///< Ignore if the value is 0xFF.
UINT8 BarIndex; ///< Ignore if the value is 0xFF.
} EFI_PEI_GRAPHICS_DEVICE_INFO_HOB;
extern EFI_GUID gEfiGraphicsInfoHobGuid;
extern EFI_GUID gEfiGraphicsDeviceInfoHobGuid;
#endif

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/** @file
GUID for hardware error record variables.
Copyright (c) 2007 - 2009, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@par Revision Reference:
GUID defined in UEFI 2.1.
**/
#ifndef _HARDWARE_ERROR_VARIABLE_GUID_H_
#define _HARDWARE_ERROR_VARIABLE_GUID_H_
#define EFI_HARDWARE_ERROR_VARIABLE \
{ \
0x414E6BDD, 0xE47B, 0x47cc, {0xB2, 0x44, 0xBB, 0x61, 0x02, 0x0C, 0xF5, 0x16} \
}
extern EFI_GUID gEfiHardwareErrorVariableGuid;
#endif

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src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Guid/HiiFormMapMethodGuid.h Normal file
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/** @file
Guid used to identify HII FormMap configuration method.
Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@par Revision Reference:
GUID defined in UEFI 2.2 spec.
**/
#ifndef __EFI_HII_FORMMAP_GUID_H__
#define __EFI_HII_FORMMAP_GUID_H__
#define EFI_HII_STANDARD_FORM_GUID \
{ 0x3bd2f4ec, 0xe524, 0x46e4, { 0xa9, 0xd8, 0x51, 0x1, 0x17, 0x42, 0x55, 0x62 } }
extern EFI_GUID gEfiHiiStandardFormGuid;
#endif

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src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Guid/HiiKeyBoardLayout.h Normal file
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/** @file
HII keyboard layout GUID as defined in UEFI2.1 specification
Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@par Revision Reference:
GUIDs defined in UEFI 2.1 spec.
**/
#ifndef __HII_KEYBOARD_LAYOUT_GUID_H__
#define __HII_KEYBOARD_LAYOUT_GUID_H__
#define EFI_HII_SET_KEYBOARD_LAYOUT_EVENT_GUID \
{ 0x14982a4f, 0xb0ed, 0x45b8, { 0xa8, 0x11, 0x5a, 0x7a, 0x9b, 0xc2, 0x32, 0xdf }}
extern EFI_GUID gEfiHiiKeyBoardLayoutGuid;
#endif

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src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Guid/HiiPlatformSetupFormset.h Normal file
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/** @file
GUID indicates that the form set contains forms designed to be used
for platform configuration and this form set will be displayed.
Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@par Revision Reference:
GUID defined in UEFI 2.1.
**/
#ifndef __HII_PLATFORM_SETUP_FORMSET_GUID_H__
#define __HII_PLATFORM_SETUP_FORMSET_GUID_H__
#define EFI_HII_PLATFORM_SETUP_FORMSET_GUID \
{ 0x93039971, 0x8545, 0x4b04, { 0xb4, 0x5e, 0x32, 0xeb, 0x83, 0x26, 0x4, 0xe } }
#define EFI_HII_DRIVER_HEALTH_FORMSET_GUID \
{ 0xf22fc20c, 0x8cf4, 0x45eb, { 0x8e, 0x6, 0xad, 0x4e, 0x50, 0xb9, 0x5d, 0xd3 } }
#define EFI_HII_USER_CREDENTIAL_FORMSET_GUID \
{ 0x337f4407, 0x5aee, 0x4b83, { 0xb2, 0xa7, 0x4e, 0xad, 0xca, 0x30, 0x88, 0xcd } }
#define EFI_HII_REST_STYLE_FORMSET_GUID \
{ 0x790217bd, 0xbecf, 0x485b, { 0x91, 0x70, 0x5f, 0xf7, 0x11, 0x31, 0x8b, 0x27 } }
extern EFI_GUID gEfiHiiPlatformSetupFormsetGuid;
extern EFI_GUID gEfiHiiDriverHealthFormsetGuid;
extern EFI_GUID gEfiHiiUserCredentialFormsetGuid;
extern EFI_GUID gEfiHiiRestStyleFormsetGuid;
#endif

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src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Guid/HobList.h Normal file
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/** @file
GUIDs used for HOB List entries
These GUIDs point the HOB List passed from PEI to DXE.
Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@par Revision Reference:
GUID introduced in PI Version 1.0.
**/
#ifndef __HOB_LIST_GUID_H__
#define __HOB_LIST_GUID_H__
#define HOB_LIST_GUID \
{ \
0x7739f24c, 0x93d7, 0x11d4, {0x9a, 0x3a, 0x0, 0x90, 0x27, 0x3f, 0xc1, 0x4d } \
}
extern EFI_GUID gEfiHobListGuid;
#endif

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/** @file
Image signature database are defined for the signed image validation.
Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@par Revision Reference:
GUIDs defined in UEFI 2.5 spec.
**/
#ifndef __IMAGE_AUTHTICATION_H__
#define __IMAGE_AUTHTICATION_H__
#include <Guid/GlobalVariable.h>
#include <Protocol/Hash.h>
#define EFI_IMAGE_SECURITY_DATABASE_GUID \
{ \
0xd719b2cb, 0x3d3a, 0x4596, { 0xa3, 0xbc, 0xda, 0xd0, 0xe, 0x67, 0x65, 0x6f } \
}
///
/// Varialbe name with guid EFI_IMAGE_SECURITY_DATABASE_GUID
/// for the authorized signature database.
///
#define EFI_IMAGE_SECURITY_DATABASE L"db"
///
/// Varialbe name with guid EFI_IMAGE_SECURITY_DATABASE_GUID
/// for the forbidden signature database.
///
#define EFI_IMAGE_SECURITY_DATABASE1 L"dbx"
///
/// Variable name with guid EFI_IMAGE_SECURITY_DATABASE_GUID
/// for the timestamp signature database.
///
#define EFI_IMAGE_SECURITY_DATABASE2 L"dbt"
#define SECURE_BOOT_MODE_ENABLE 1
#define SECURE_BOOT_MODE_DISABLE 0
#define SETUP_MODE 1
#define USER_MODE 0
//***********************************************************************
// Signature Database
//***********************************************************************
///
/// The format of a signature database.
///
#pragma pack(1)
typedef struct {
///
/// An identifier which identifies the agent which added the signature to the list.
///
EFI_GUID SignatureOwner;
///
/// The format of the signature is defined by the SignatureType.
///
UINT8 SignatureData[1];
} EFI_SIGNATURE_DATA;
typedef struct {
///
/// Type of the signature. GUID signature types are defined in below.
///
EFI_GUID SignatureType;
///
/// Total size of the signature list, including this header.
///
UINT32 SignatureListSize;
///
/// Size of the signature header which precedes the array of signatures.
///
UINT32 SignatureHeaderSize;
///
/// Size of each signature.
///
UINT32 SignatureSize;
///
/// Header before the array of signatures. The format of this header is specified
/// by the SignatureType.
/// UINT8 SignatureHeader[SignatureHeaderSize];
///
/// An array of signatures. Each signature is SignatureSize bytes in length.
/// EFI_SIGNATURE_DATA Signatures[][SignatureSize];
///
} EFI_SIGNATURE_LIST;
typedef struct {
///
/// The SHA256 hash of an X.509 certificate's To-Be-Signed contents.
///
EFI_SHA256_HASH ToBeSignedHash;
///
/// The time that the certificate shall be considered to be revoked.
///
EFI_TIME TimeOfRevocation;
} EFI_CERT_X509_SHA256;
typedef struct {
///
/// The SHA384 hash of an X.509 certificate's To-Be-Signed contents.
///
EFI_SHA384_HASH ToBeSignedHash;
///
/// The time that the certificate shall be considered to be revoked.
///
EFI_TIME TimeOfRevocation;
} EFI_CERT_X509_SHA384;
typedef struct {
///
/// The SHA512 hash of an X.509 certificate's To-Be-Signed contents.
///
EFI_SHA512_HASH ToBeSignedHash;
///
/// The time that the certificate shall be considered to be revoked.
///
EFI_TIME TimeOfRevocation;
} EFI_CERT_X509_SHA512;
#pragma pack()
///
/// This identifies a signature containing a SHA-256 hash. The SignatureHeader size shall
/// always be 0. The SignatureSize shall always be 16 (size of SignatureOwner component) +
/// 32 bytes.
///
#define EFI_CERT_SHA256_GUID \
{ \
0xc1c41626, 0x504c, 0x4092, {0xac, 0xa9, 0x41, 0xf9, 0x36, 0x93, 0x43, 0x28} \
}
///
/// This identifies a signature containing an RSA-2048 key. The key (only the modulus
/// since the public key exponent is known to be 0x10001) shall be stored in big-endian
/// order.
/// The SignatureHeader size shall always be 0. The SignatureSize shall always be 16 (size
/// of SignatureOwner component) + 256 bytes.
///
#define EFI_CERT_RSA2048_GUID \
{ \
0x3c5766e8, 0x269c, 0x4e34, {0xaa, 0x14, 0xed, 0x77, 0x6e, 0x85, 0xb3, 0xb6} \
}
///
/// This identifies a signature containing a RSA-2048 signature of a SHA-256 hash. The
/// SignatureHeader size shall always be 0. The SignatureSize shall always be 16 (size of
/// SignatureOwner component) + 256 bytes.
///
#define EFI_CERT_RSA2048_SHA256_GUID \
{ \
0xe2b36190, 0x879b, 0x4a3d, {0xad, 0x8d, 0xf2, 0xe7, 0xbb, 0xa3, 0x27, 0x84} \
}
///
/// This identifies a signature containing a SHA-1 hash. The SignatureSize shall always
/// be 16 (size of SignatureOwner component) + 20 bytes.
///
#define EFI_CERT_SHA1_GUID \
{ \
0x826ca512, 0xcf10, 0x4ac9, {0xb1, 0x87, 0xbe, 0x1, 0x49, 0x66, 0x31, 0xbd} \
}
///
/// TThis identifies a signature containing a RSA-2048 signature of a SHA-1 hash. The
/// SignatureHeader size shall always be 0. The SignatureSize shall always be 16 (size of
/// SignatureOwner component) + 256 bytes.
///
#define EFI_CERT_RSA2048_SHA1_GUID \
{ \
0x67f8444f, 0x8743, 0x48f1, {0xa3, 0x28, 0x1e, 0xaa, 0xb8, 0x73, 0x60, 0x80} \
}
///
/// This identifies a signature based on an X.509 certificate. If the signature is an X.509
/// certificate then verification of the signature of an image should validate the public
/// key certificate in the image using certificate path verification, up to this X.509
/// certificate as a trusted root. The SignatureHeader size shall always be 0. The
/// SignatureSize may vary but shall always be 16 (size of the SignatureOwner component) +
/// the size of the certificate itself.
/// Note: This means that each certificate will normally be in a separate EFI_SIGNATURE_LIST.
///
#define EFI_CERT_X509_GUID \
{ \
0xa5c059a1, 0x94e4, 0x4aa7, {0x87, 0xb5, 0xab, 0x15, 0x5c, 0x2b, 0xf0, 0x72} \
}
///
/// This identifies a signature containing a SHA-224 hash. The SignatureHeader size shall
/// always be 0. The SignatureSize shall always be 16 (size of SignatureOwner component) +
/// 28 bytes.
///
#define EFI_CERT_SHA224_GUID \
{ \
0xb6e5233, 0xa65c, 0x44c9, {0x94, 0x7, 0xd9, 0xab, 0x83, 0xbf, 0xc8, 0xbd} \
}
///
/// This identifies a signature containing a SHA-384 hash. The SignatureHeader size shall
/// always be 0. The SignatureSize shall always be 16 (size of SignatureOwner component) +
/// 48 bytes.
///
#define EFI_CERT_SHA384_GUID \
{ \
0xff3e5307, 0x9fd0, 0x48c9, {0x85, 0xf1, 0x8a, 0xd5, 0x6c, 0x70, 0x1e, 0x1} \
}
///
/// This identifies a signature containing a SHA-512 hash. The SignatureHeader size shall
/// always be 0. The SignatureSize shall always be 16 (size of SignatureOwner component) +
/// 64 bytes.
///
#define EFI_CERT_SHA512_GUID \
{ \
0x93e0fae, 0xa6c4, 0x4f50, {0x9f, 0x1b, 0xd4, 0x1e, 0x2b, 0x89, 0xc1, 0x9a} \
}
///
/// This identifies a signature containing the SHA256 hash of an X.509 certificate's
/// To-Be-Signed contents, and a time of revocation. The SignatureHeader size shall
/// always be 0. The SignatureSize shall always be 16 (size of the SignatureOwner component)
/// + 48 bytes for an EFI_CERT_X509_SHA256 structure. If the TimeOfRevocation is non-zero,
/// the certificate should be considered to be revoked from that time and onwards, and
/// otherwise the certificate shall be considered to always be revoked.
///
#define EFI_CERT_X509_SHA256_GUID \
{ \
0x3bd2a492, 0x96c0, 0x4079, {0xb4, 0x20, 0xfc, 0xf9, 0x8e, 0xf1, 0x03, 0xed } \
}
///
/// This identifies a signature containing the SHA384 hash of an X.509 certificate's
/// To-Be-Signed contents, and a time of revocation. The SignatureHeader size shall
/// always be 0. The SignatureSize shall always be 16 (size of the SignatureOwner component)
/// + 64 bytes for an EFI_CERT_X509_SHA384 structure. If the TimeOfRevocation is non-zero,
/// the certificate should be considered to be revoked from that time and onwards, and
/// otherwise the certificate shall be considered to always be revoked.
///
#define EFI_CERT_X509_SHA384_GUID \
{ \
0x7076876e, 0x80c2, 0x4ee6, {0xaa, 0xd2, 0x28, 0xb3, 0x49, 0xa6, 0x86, 0x5b } \
}
///
/// This identifies a signature containing the SHA512 hash of an X.509 certificate's
/// To-Be-Signed contents, and a time of revocation. The SignatureHeader size shall
/// always be 0. The SignatureSize shall always be 16 (size of the SignatureOwner component)
/// + 80 bytes for an EFI_CERT_X509_SHA512 structure. If the TimeOfRevocation is non-zero,
/// the certificate should be considered to be revoked from that time and onwards, and
/// otherwise the certificate shall be considered to always be revoked.
///
#define EFI_CERT_X509_SHA512_GUID \
{ \
0x446dbf63, 0x2502, 0x4cda, {0xbc, 0xfa, 0x24, 0x65, 0xd2, 0xb0, 0xfe, 0x9d } \
}
///
/// This identifies a signature containing a DER-encoded PKCS #7 version 1.5 [RFC2315]
/// SignedData value.
///
#define EFI_CERT_TYPE_PKCS7_GUID \
{ \
0x4aafd29d, 0x68df, 0x49ee, {0x8a, 0xa9, 0x34, 0x7d, 0x37, 0x56, 0x65, 0xa7} \
}
//***********************************************************************
// Image Execution Information Table Definition
//***********************************************************************
typedef UINT32 EFI_IMAGE_EXECUTION_ACTION;
#define EFI_IMAGE_EXECUTION_AUTHENTICATION 0x00000007
#define EFI_IMAGE_EXECUTION_AUTH_UNTESTED 0x00000000
#define EFI_IMAGE_EXECUTION_AUTH_SIG_FAILED 0x00000001
#define EFI_IMAGE_EXECUTION_AUTH_SIG_PASSED 0x00000002
#define EFI_IMAGE_EXECUTION_AUTH_SIG_NOT_FOUND 0x00000003
#define EFI_IMAGE_EXECUTION_AUTH_SIG_FOUND 0x00000004
#define EFI_IMAGE_EXECUTION_POLICY_FAILED 0x00000005
#define EFI_IMAGE_EXECUTION_INITIALIZED 0x00000008
//
// EFI_IMAGE_EXECUTION_INFO is added to EFI System Configuration Table
// and assigned the GUID EFI_IMAGE_SECURITY_DATABASE_GUID.
//
typedef struct {
///
/// Describes the action taken by the firmware regarding this image.
///
EFI_IMAGE_EXECUTION_ACTION Action;
///
/// Size of all of the entire structure.
///
UINT32 InfoSize;
///
/// If this image was a UEFI device driver (for option ROM, for example) this is the
/// null-terminated, user-friendly name for the device. If the image was for an application,
/// then this is the name of the application. If this cannot be determined, then a simple
/// NULL character should be put in this position.
/// CHAR16 Name[];
///
///
/// For device drivers, this is the device path of the device for which this device driver
/// was intended. In some cases, the driver itself may be stored as part of the system
/// firmware, but this field should record the device's path, not the firmware path. For
/// applications, this is the device path of the application. If this cannot be determined,
/// a simple end-of-path device node should be put in this position.
/// EFI_DEVICE_PATH_PROTOCOL DevicePath;
///
///
/// Zero or more image signatures. If the image contained no signatures,
/// then this field is empty.
/// EFI_SIGNATURE_LIST Signature;
///
} EFI_IMAGE_EXECUTION_INFO;
typedef struct {
///
/// Number of EFI_IMAGE_EXECUTION_INFO structures.
///
UINTN NumberOfImages;
///
/// Number of image instances of EFI_IMAGE_EXECUTION_INFO structures.
///
// EFI_IMAGE_EXECUTION_INFO InformationInfo[]
} EFI_IMAGE_EXECUTION_INFO_TABLE;
extern EFI_GUID gEfiImageSecurityDatabaseGuid;
extern EFI_GUID gEfiCertSha256Guid;
extern EFI_GUID gEfiCertRsa2048Guid;
extern EFI_GUID gEfiCertRsa2048Sha256Guid;
extern EFI_GUID gEfiCertSha1Guid;
extern EFI_GUID gEfiCertRsa2048Sha1Guid;
extern EFI_GUID gEfiCertX509Guid;
extern EFI_GUID gEfiCertSha224Guid;
extern EFI_GUID gEfiCertSha384Guid;
extern EFI_GUID gEfiCertSha512Guid;
extern EFI_GUID gEfiCertX509Sha256Guid;
extern EFI_GUID gEfiCertX509Sha384Guid;
extern EFI_GUID gEfiCertX509Sha512Guid;
extern EFI_GUID gEfiCertPkcs7Guid;
#endif

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/** @file
Guid & data structure for tables defined for reporting firmware configuration data to EFI
Configuration Tables and also for processing JSON payload capsule.
Copyright (c) 2020, American Megatrends International LLC. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef __JSON_CAPSULE_GUID_H__
#define __JSON_CAPSULE_GUID_H__
//
// The address reported in the table entry identified by EFI_JSON_CAPSULE_DATA_TABLE_GUID will be
// referenced as physical and will not be fixed up when transition from preboot to runtime phase. The
// addresses reported in these table entries identified by EFI_JSON_CONFIG_DATA_TABLE_GUID and
// EFI_JSON_CAPSULE_RESULT_TABLE_GUID will be referenced as virtual and will be fixed up when
// transition from preboot to runtime phase.
//
#define EFI_JSON_CONFIG_DATA_TABLE_GUID \
{0x87367f87, 0x1119, 0x41ce, \
{0xaa, 0xec, 0x8b, 0xe0, 0x11, 0x1f, 0x55, 0x8a }}
#define EFI_JSON_CAPSULE_DATA_TABLE_GUID \
{0x35e7a725, 0x8dd2, 0x4cac, \
{0x80, 0x11, 0x33, 0xcd, 0xa8, 0x10, 0x90, 0x56 }}
#define EFI_JSON_CAPSULE_RESULT_TABLE_GUID \
{0xdbc461c3, 0xb3de, 0x422a,\
{0xb9, 0xb4, 0x98, 0x86, 0xfd, 0x49, 0xa1, 0xe5 }}
#define EFI_JSON_CAPSULE_ID_GUID \
{0x67d6f4cd, 0xd6b8, 0x4573, \
{0xbf, 0x4a, 0xde, 0x5e, 0x25, 0x2d, 0x61, 0xae }}
#pragma pack(1)
typedef struct {
///
/// Version of the structure, initially 0x00000001.
///
UINT32 Version;
///
/// The unique identifier of this capsule.
///
UINT32 CapsuleId;
///
/// The length of the JSON payload immediately following this header, in bytes.
///
UINT32 PayloadLength;
///
/// Variable length buffer containing the JSON payload that should be parsed and applied to the system. The
/// definition of the JSON schema used in the payload is beyond the scope of this specification.
///
UINT8 Payload[];
} EFI_JSON_CAPSULE_HEADER;
typedef struct {
///
/// The length of the following ConfigData, in bytes.
///
UINT32 ConfigDataLength;
///
/// Variable length buffer containing the JSON payload that describes one group of configuration data within
/// current system. The definition of the JSON schema used in this payload is beyond the scope of this specification.
///
UINT8 ConfigData[];
} EFI_JSON_CONFIG_DATA_ITEM;
typedef struct {
///
/// Version of the structure, initially 0x00000001.
///
UINT32 Version;
///
////The total length of EFI_JSON_CAPSULE_CONFIG_DATA, in bytes.
///
UINT32 TotalLength;
///
/// Array of configuration data groups.
///
EFI_JSON_CONFIG_DATA_ITEM ConfigDataList[];
} EFI_JSON_CAPSULE_CONFIG_DATA;
#pragma pack()
extern EFI_GUID gEfiJsonConfigDataTableGuid;
extern EFI_GUID gEfiJsonCapsuleDataTableGuid;
extern EFI_GUID gEfiJsonCapsuleResultTableGuid;
extern EFI_GUID gEfiJsonCapsuleIdGuid;
#endif

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/** @file
GUID definition for the Linux Initrd media device path
Linux distro boot generally relies on an initial ramdisk (initrd) which is
provided by the loader, and which contains additional kernel modules (for
storage and network, for instance), and the initial user space startup code,
i.e., the code which brings up the user space side of the entire OS.
In order to provide a standard method to locate this initrd, the GUID defined
in this file is used to describe the device path for a LoadFile2 Protocol
instance that is responsible for loading the initrd file.
The kernel EFI Stub will locate and use this instance to load the initrd,
therefore the firmware/loader should install an instance of this to load the
relevant initrd.
Copyright (c) 2020, Arm, Ltd. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef LINUX_EFI_INITRD_MEDIA_GUID_H_
#define LINUX_EFI_INITRD_MEDIA_GUID_H_
#define LINUX_EFI_INITRD_MEDIA_GUID \
{0x5568e427, 0x68fc, 0x4f3d, {0xac, 0x74, 0xca, 0x55, 0x52, 0x31, 0xcc, 0x68}}
extern EFI_GUID gLinuxEfiInitrdMediaGuid;
#endif

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src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Guid/MdePkgTokenSpace.h Normal file
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/** @file
GUID for MdePkg PCD Token Space
Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef _MDEPKG_TOKEN_SPACE_GUID_H_
#define _MDEPKG_TOKEN_SPACE_GUID_H_
#define MDEPKG_TOKEN_SPACE_GUID \
{ \
0x914AEBE7, 0x4635, 0x459b, { 0xAA, 0x1C, 0x11, 0xE2, 0x19, 0xB0, 0x3A, 0x10 } \
}
extern EFI_GUID gEfiMdePkgTokenSpaceGuid;
#endif

28
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/** @file
GUIDs for HOBs used in memory allcation
Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@par Revision Reference:
GUIDs introduced in PI Version 1.0.
**/
#ifndef __MEMORY_ALLOCATION_GUID_H__
#define __MEMORY_ALLOCATION_GUID_H__
#define EFI_HOB_MEMORY_ALLOC_BSP_STORE_GUID \
{0x564b33cd, 0xc92a, 0x4593, {0x90, 0xbf, 0x24, 0x73, 0xe4, 0x3c, 0x63, 0x22} };
#define EFI_HOB_MEMORY_ALLOC_STACK_GUID \
{0x4ed4bf27, 0x4092, 0x42e9, {0x80, 0x7d, 0x52, 0x7b, 0x1d, 0x0, 0xc9, 0xbd} }
#define EFI_HOB_MEMORY_ALLOC_MODULE_GUID \
{0xf8e21975, 0x899, 0x4f58, {0xa4, 0xbe, 0x55, 0x25, 0xa9, 0xc6, 0xd7, 0x7a} }
extern EFI_GUID gEfiHobMemoryAllocBspStoreGuid;
extern EFI_GUID gEfiHobMemoryAllocStackGuid;
extern EFI_GUID gEfiHobMemoryAllocModuleGuid;
#endif

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/** @file
GUIDs used for UEFI Memory Attributes Table in the UEFI 2.6 specification.
Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef __UEFI_MEMORY_ATTRIBUTES_TABLE_H__
#define __UEFI_MEMORY_ATTRIBUTES_TABLE_H__
#define EFI_MEMORY_ATTRIBUTES_TABLE_GUID {\
0xdcfa911d, 0x26eb, 0x469f, {0xa2, 0x20, 0x38, 0xb7, 0xdc, 0x46, 0x12, 0x20} \
}
typedef struct {
UINT32 Version;
UINT32 NumberOfEntries;
UINT32 DescriptorSize;
UINT32 Reserved;
//EFI_MEMORY_DESCRIPTOR Entry[1];
} EFI_MEMORY_ATTRIBUTES_TABLE;
#define EFI_MEMORY_ATTRIBUTES_TABLE_VERSION 0x00000001
extern EFI_GUID gEfiMemoryAttributesTableGuid;
#endif

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/** @file
GUID used for MemoryOverwriteRequestControl UEFI variable defined in
TCG Platform Reset Attack Mitigation Specification 1.00.
See http://trustedcomputinggroup.org for the latest specification
The purpose of the MemoryOverwriteRequestControl UEFI variable is to give users (e.g., OS, loader) the ability to
indicate to the platform that secrets are present in memory and that the platform firmware must clear memory upon
a restart. The OS loader should not create the variable. Rather, the firmware is required to create it.
Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef _MEMORY_OVERWRITE_CONTROL_DATA_GUID_H_
#define _MEMORY_OVERWRITE_CONTROL_DATA_GUID_H_
#define MEMORY_ONLY_RESET_CONTROL_GUID \
{ \
0xe20939be, 0x32d4, 0x41be, {0xa1, 0x50, 0x89, 0x7f, 0x85, 0xd4, 0x98, 0x29} \
}
///
/// Variable name is "MemoryOverwriteRequestControl" and it is a 1 byte unsigned value.
/// The attributes should be:
/// EFI_VARIABLE_NON_VOLATILE |
/// EFI_VARIABLE_BOOTSERVICE_ACCESS |
/// EFI_VARIABLE_RUNTIME_ACCESS
///
#define MEMORY_OVERWRITE_REQUEST_VARIABLE_NAME L"MemoryOverwriteRequestControl"
///
/// 0 = Firmware MUST clear the MOR bit
/// 1 = Firmware MUST set the MOR bit
///
#define MOR_CLEAR_MEMORY_BIT_MASK 0x01
///
/// 0 = Firmware MAY autodetect a clean shutdown of the Static RTM OS.
/// 1 = Firmware MUST NOT autodetect a clean shutdown of the Static RTM OS.
///
#define MOR_DISABLEAUTODETECT_BIT_MASK 0x10
///
/// MOR field bit offset
///
#define MOR_CLEAR_MEMORY_BIT_OFFSET 0
#define MOR_DISABLEAUTODETECT_BIT_OFFSET 4
/**
Return the ClearMemory bit value 0 or 1.
@param mor 1 byte value that contains ClearMemory and DisableAutoDetect bit.
@return ClearMemory bit value
**/
#define MOR_CLEAR_MEMORY_VALUE(mor) (((UINT8)(mor) & MOR_CLEAR_MEMORY_BIT_MASK) >> MOR_CLEAR_MEMORY_BIT_OFFSET)
/**
Return the DisableAutoDetect bit value 0 or 1.
@param mor 1 byte value that contains ClearMemory and DisableAutoDetect bit.
@return DisableAutoDetect bit value
**/
#define MOR_DISABLE_AUTO_DETECT_VALUE(mor) (((UINT8)(mor) & MOR_DISABLEAUTODETECT_BIT_MASK) >> MOR_DISABLEAUTODETECT_BIT_OFFSET)
extern EFI_GUID gEfiMemoryOverwriteControlDataGuid;
#endif

29
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/** @file
GUIDs used for MPS entries in the UEFI 2.0 system table
ACPI is the primary means of exporting MPS information to the OS. MPS only was
included to support Itanium-based platform power on. So don't use it if you don't have too.
Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@par Revision Reference:
GUIDs defined in UEFI 2.0 spec.
**/
#ifndef __MPS_GUID_H__
#define __MPS_GUID_H__
#define EFI_MPS_TABLE_GUID \
{ \
0xeb9d2d2f, 0x2d88, 0x11d3, {0x9a, 0x16, 0x0, 0x90, 0x27, 0x3f, 0xc1, 0x4d } \
}
//
// GUID name defined in spec.
//
#define MPS_TABLE_GUID EFI_MPS_TABLE_GUID
extern EFI_GUID gEfiMpsTableGuid;
#endif

52
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/** @file
Terminal Device Path Vendor Guid.
Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@par Revision Reference:
GUIDs defined in UEFI 2.0 spec.
**/
#ifndef __PC_ANSI_H__
#define __PC_ANSI_H__
#define EFI_PC_ANSI_GUID \
{ \
0xe0c14753, 0xf9be, 0x11d2, {0x9a, 0x0c, 0x00, 0x90, 0x27, 0x3f, 0xc1, 0x4d } \
}
#define EFI_VT_100_GUID \
{ \
0xdfa66065, 0xb419, 0x11d3, {0x9a, 0x2d, 0x00, 0x90, 0x27, 0x3f, 0xc1, 0x4d } \
}
#define EFI_VT_100_PLUS_GUID \
{ \
0x7baec70b, 0x57e0, 0x4c76, {0x8e, 0x87, 0x2f, 0x9e, 0x28, 0x08, 0x83, 0x43 } \
}
#define EFI_VT_UTF8_GUID \
{ \
0xad15a0d6, 0x8bec, 0x4acf, {0xa0, 0x73, 0xd0, 0x1d, 0xe7, 0x7e, 0x2d, 0x88 } \
}
#define DEVICE_PATH_MESSAGING_UART_FLOW_CONTROL \
{ \
0x37499a9d, 0x542f, 0x4c89, {0xa0, 0x26, 0x35, 0xda, 0x14, 0x20, 0x94, 0xe4 } \
}
#define EFI_SAS_DEVICE_PATH_GUID \
{ \
0xd487ddb4, 0x008b, 0x11d9, {0xaf, 0xdc, 0x00, 0x10, 0x83, 0xff, 0xca, 0x4d } \
}
extern EFI_GUID gEfiPcAnsiGuid;
extern EFI_GUID gEfiVT100Guid;
extern EFI_GUID gEfiVT100PlusGuid;
extern EFI_GUID gEfiVTUTF8Guid;
extern EFI_GUID gEfiUartDevicePathGuid;
extern EFI_GUID gEfiSasDevicePathGuid;
#endif

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/** @file
Guid & data structure for EFI_RT _PROPERTIES_TABLE, designed to be published by a
platform if it no longer supports all EFI runtime services once ExitBootServices()
has been called by the OS. Introduced in UEFI 2.8a.
Copyright (c) 2020, American Megatrends International LLC. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef __RT_PROPERTIES_TABLE_GUID_H__
#define __RT_PROPERTIES_TABLE_GUID_H__
//
// Table, defined here, should be published by a platform if it no longer supports all EFI runtime
// services once ExitBootServices() has been called by the OS. Note that this is merely a hint
// to the OS, which it is free to ignore, and so the platform is still required to provide callable
// implementations of unsupported runtime services that simply return EFI_UNSUPPORTED.
//
#define EFI_RT_PROPERTIES_TABLE_GUID \
{ 0xeb66918a, 0x7eef, 0x402a, \
{ 0x84, 0x2e, 0x93, 0x1d, 0x21, 0xc3, 0x8a, 0xe9 }}
#pragma pack(1)
typedef struct {
///
/// Version of the structure, must be 0x1.
///
UINT16 Version;
///
/// Size in bytes of the entire EFI_RT_PROPERTIES_TABLE, must be 8.
///
UINT16 Length;
///
/// Bitmask of which calls are or are not supported, where a bit set to 1 indicates
/// that the call is supported, and 0 indicates that it is not.
///
UINT32 RuntimeServicesSupported;
} EFI_RT_PROPERTIES_TABLE;
#pragma pack()
#define EFI_RT_PROPERTIES_TABLE_VERSION 0x1
#define EFI_RT_SUPPORTED_GET_TIME 0x0001
#define EFI_RT_SUPPORTED_SET_TIME 0x0002
#define EFI_RT_SUPPORTED_GET_WAKEUP_TIME 0x0004
#define EFI_RT_SUPPORTED_SET_WAKEUP_TIME 0x0008
#define EFI_RT_SUPPORTED_GET_VARIABLE 0x0010
#define EFI_RT_SUPPORTED_GET_NEXT_VARIABLE_NAME 0x0020
#define EFI_RT_SUPPORTED_SET_VARIABLE 0x0040
#define EFI_RT_SUPPORTED_SET_VIRTUAL_ADDRESS_MAP 0x0080
#define EFI_RT_SUPPORTED_CONVERT_POINTER 0x0100
#define EFI_RT_SUPPORTED_GET_NEXT_HIGH_MONOTONIC_COUNT 0x0200
#define EFI_RT_SUPPORTED_RESET_SYSTEM 0x0400
#define EFI_RT_SUPPORTED_UPDATE_CAPSULE 0x0800
#define EFI_RT_SUPPORTED_QUERY_CAPSULE_CAPABILITIES 0x1000
#define EFI_RT_SUPPORTED_QUERY_VARIABLE_INFO 0x2000
extern EFI_GUID gEfiRtPropertiesTableGuid;
#endif

32
src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Guid/SmBios.h Normal file
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/** @file
GUIDs used to locate the SMBIOS tables in the UEFI 2.5 system table.
These GUIDs in the system table are the only legal ways to search for and
locate the SMBIOS tables. Do not search the 0xF0000 segment to find SMBIOS
tables.
Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@par Revision Reference:
GUIDs defined in UEFI 2.5 spec.
**/
#ifndef __SMBIOS_GUID_H__
#define __SMBIOS_GUID_H__
#define SMBIOS_TABLE_GUID \
{ \
0xeb9d2d31, 0x2d88, 0x11d3, {0x9a, 0x16, 0x0, 0x90, 0x27, 0x3f, 0xc1, 0x4d } \
}
#define SMBIOS3_TABLE_GUID \
{ \
0xf2fd1544, 0x9794, 0x4a2c, {0x99, 0x2e, 0xe5, 0xbb, 0xcf, 0x20, 0xe3, 0x94 } \
}
extern EFI_GUID gEfiSmbiosTableGuid;
extern EFI_GUID gEfiSmbios3TableGuid;
#endif

45
src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Guid/SmramMemoryReserve.h Normal file
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/** @file
This is a special GUID extension Hob to describe SMRAM memory regions.
This file defines:
* the GUID used to identify the GUID HOB for reserving SMRAM regions.
* the data structure of SMRAM descriptor to describe SMRAM candidate regions
* values of state of SMRAM candidate regions
* the GUID specific data structure of HOB for reserving SMRAM regions.
Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@par Revision Reference:
GUIDs defined in PI SPEC version 1.5.
**/
#ifndef _SMRAM_MEMORY_RESERVE_H_
#define _SMRAM_MEMORY_RESERVE_H_
#define EFI_SMM_SMRAM_MEMORY_GUID \
{ \
0x6dadf1d1, 0xd4cc, 0x4910, {0xbb, 0x6e, 0x82, 0xb1, 0xfd, 0x80, 0xff, 0x3d } \
}
/**
* The GUID extension hob is to describe SMRAM memory regions supported by the platform.
**/
typedef struct {
///
/// Designates the number of possible regions in the system
/// that can be usable for SMRAM.
///
UINT32 NumberOfSmmReservedRegions;
///
/// Used throughout this protocol to describe the candidate
/// regions for SMRAM that are supported by this platform.
///
EFI_SMRAM_DESCRIPTOR Descriptor[1];
} EFI_SMRAM_HOB_DESCRIPTOR_BLOCK;
extern EFI_GUID gEfiSmmSmramMemoryGuid;
#endif

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/** @file
GUID used to identify id for the caller who is initiating the Status Code.
Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@par Revision Reference:
These GUIDs and structures are defined in UEFI Platform Initialization Specification 1.2
Volume 3: Shared Architectural Elements
**/
#ifndef __PI_STATUS_CODE_DATA_TYPE_ID_GUID_H__
#define __PI_STATUS_CODE_DATA_TYPE_ID_GUID_H__
#include <PiDxe.h>
#include <Protocol/DebugSupport.h>
///
/// Global ID for the EFI_STATUS_CODE_STRING structure
///
#define EFI_STATUS_CODE_DATA_TYPE_STRING_GUID \
{ 0x92D11080, 0x496F, 0x4D95, { 0xBE, 0x7E, 0x03, 0x74, 0x88, 0x38, 0x2B, 0x0A } }
typedef enum {
///
/// A NULL-terminated ASCII string.
///
EfiStringAscii,
///
/// A double NULL-terminated Unicode string.
///
EfiStringUnicode,
///
/// An EFI_STATUS_CODE_STRING_TOKEN representing the string. The actual
/// string can be obtained by querying the HII Database
///
EfiStringToken
} EFI_STRING_TYPE;
///
/// Specifies the format of the data in EFI_STATUS_CODE_STRING_DATA.String.
///
typedef struct {
///
/// The HII package list which contains the string. Handle is a dynamic value that may
/// not be the same for different boots. Type EFI_HII_HANDLE is defined in
/// EFI_HII_DATABASE_PROTOCOL.NewPackageList() in the UEFI Specification.
///
EFI_HII_HANDLE Handle;
///
/// When combined with Handle, the string token can be used to retrieve the string.
/// Type EFI_STRING_ID is defined in EFI_IFR_OP_HEADER in the UEFI Specification.
///
EFI_STRING_ID Token;
} EFI_STATUS_CODE_STRING_TOKEN;
typedef union {
///
/// ASCII formatted string.
///
CHAR8 *Ascii;
///
/// Unicode formatted string.
///
CHAR16 *Unicode;
///
/// HII handle/token pair.
///
EFI_STATUS_CODE_STRING_TOKEN Hii;
} EFI_STATUS_CODE_STRING;
///
/// This data type defines a string type of extended data. A string can accompany
/// any status code. The string can provide additional information about the
/// status code. The string can be ASCII, Unicode, or a Human Interface Infrastructure
/// (HII) token/GUID pair.
///
typedef struct {
///
/// The data header identifying the data. DataHeader.HeaderSize should be
/// sizeof (EFI_STATUS_CODE_DATA), DataHeader.Size should be
/// sizeof (EFI_STATUS_CODE_STRING_DATA) - HeaderSize, and
/// DataHeader.Type should be
/// EFI_STATUS_CODE_DATA_TYPE_STRING_GUID.
///
EFI_STATUS_CODE_DATA DataHeader;
///
/// Specifies the format of the data in String.
///
EFI_STRING_TYPE StringType;
///
/// A pointer to the extended data. The data follows the format specified by
/// StringType.
///
EFI_STATUS_CODE_STRING String;
} EFI_STATUS_CODE_STRING_DATA;
extern EFI_GUID gEfiStatusCodeDataTypeStringGuid;
///
/// Global ID for the following structures:
/// - EFI_DEVICE_PATH_EXTENDED_DATA
/// - EFI_DEVICE_HANDLE_EXTENDED_DATA
/// - EFI_RESOURCE_ALLOC_FAILURE_ERROR_DATA
/// - EFI_COMPUTING_UNIT_VOLTAGE_ERROR_DATA
/// - EFI_COMPUTING_UNIT_MICROCODE_UPDATE_ERROR_DATA
/// - EFI_COMPUTING_UNIT_TIMER_EXPIRED_ERROR_DATA
/// - EFI_HOST_PROCESSOR_MISMATCH_ERROR_DATA
/// - EFI_MEMORY_RANGE_EXTENDED_DATA
/// - EFI_DEBUG_ASSERT_DATA
/// - EFI_STATUS_CODE_EXCEP_EXTENDED_DATA
/// - EFI_STATUS_CODE_START_EXTENDED_DATA
/// - EFI_LEGACY_OPROM_EXTENDED_DATA
/// - EFI_RETURN_STATUS_EXTENDED_DATA
///
#define EFI_STATUS_CODE_SPECIFIC_DATA_GUID \
{ 0x335984bd, 0xe805, 0x409a, { 0xb8, 0xf8, 0xd2, 0x7e, 0xce, 0x5f, 0xf7, 0xa6 } }
///
/// Extended data about the device path, which is used for many errors and
/// progress codes to point to the device.
///
/// The device path is used to point to the physical device in case there is more than one device
/// belonging to the same subclass. For example, the system may contain two USB keyboards and one
/// PS/2* keyboard. The driver that parses the status code can use the device path extended data to
/// differentiate between the three. The index field is not useful in this case because there is no standard
/// numbering convention. Device paths are preferred over using device handles because device handles
/// for a given device can change from one boot to another and do not mean anything beyond Boot
/// Services time. In certain cases, the bus driver may not create a device handle for a given device if it
/// detects a critical error. In these cases, the device path extended data can be used to refer to the
/// device, but there may not be any device handles with an instance of
/// EFI_DEVICE_PATH_PROTOCOL that matches DevicePath. The variable device path structure
/// is included in this structure to make it self sufficient.
///
typedef struct {
///
/// The data header identifying the data. DataHeader.HeaderSize should be
/// sizeof (EFI_STATUS_CODE_DATA). DataHeader.Size should be the size
/// of variable-length DevicePath, and DataHeader.Size is zero for a virtual
/// device that does not have a device path. DataHeader.Type should be
/// EFI_STATUS_CODE_SPECIFIC_DATA_GUID.
///
EFI_STATUS_CODE_DATA DataHeader;
///
/// The device path to the controller or the hardware device. Note that this parameter is a
/// variable-length device path structure and not a pointer to such a structure. This structure is
/// populated only if it is a physical device. For virtual devices, the Size field in DataHeader
/// is set to zero and this field is not populated.
///
// EFI_DEVICE_PATH_PROTOCOL DevicePath;
} EFI_DEVICE_PATH_EXTENDED_DATA;
///
/// Device handle Extended Data. Used for many
/// errors and progress codes to point to the device.
///
/// The handle of the device with which the progress or error code is associated. The handle is
/// guaranteed to be accurate only at the time the status code is reported. Handles are dynamic entities
/// between boots, so handles cannot be considered to be valid if the system has reset subsequent to the
/// status code being reported. Handles may be used to determine a wide variety of useful information
/// about the source of the status code.
///
typedef struct {
///
/// The data header identifying the data. DataHeader.HeaderSize should be
/// sizeof (EFI_STATUS_CODE_DATA), DataHeader.Size should be
/// sizeof (EFI_DEVICE_HANDLE_EXTENDED_DATA) - HeaderSize, and
/// DataHeader.Type should be EFI_STATUS_CODE_SPECIFIC_DATA_GUID.
///
EFI_STATUS_CODE_DATA DataHeader;
///
/// The device handle.
///
EFI_HANDLE Handle;
} EFI_DEVICE_HANDLE_EXTENDED_DATA;
///
/// This structure defines extended data describing a PCI resource allocation error.
///
/// @par Note:
/// The following structure contains variable-length fields and cannot be defined as a C-style
/// structure.
///
/// This extended data conveys details for a PCI resource allocation failure error. See the PCI
/// specification and the ACPI specification for details on PCI resource allocations and the format for
/// resource descriptors. This error does not detail why the resource allocation failed. It may be due to a
/// bad resource request or a lack of available resources to satisfy a valid request. The variable device
/// path structure and the resource structures are included in this structure to make it self sufficient.
///
typedef struct {
///
/// The data header identifying the data. DataHeader.HeaderSize should be sizeof
/// (EFI_STATUS_CODE_DATA), DataHeader.Size should be
/// (DevicePathSize + DevicePathSize + DevicePathSize +
/// sizeof(UINT32) + 3 * sizeof (UINT16) ), and DataHeader.Type
/// should be EFI_STATUS_CODE_SPECIFIC_DATA_GUID.
///
EFI_STATUS_CODE_DATA DataHeader;
///
/// The PCI BAR. Applicable only for PCI devices. Ignored for all other devices.
///
UINT32 Bar;
///
/// DevicePathSize should be zero if it is a virtual device that is not associated with
/// a device path. Otherwise, this parameter is the length of the variable-length
/// DevicePath.
///
UINT16 DevicePathSize;
///
/// Represents the size the ReqRes parameter. ReqResSize should be zero if the
/// requested resources are not provided as a part of extended data.
///
UINT16 ReqResSize;
///
/// Represents the size the AllocRes parameter. AllocResSize should be zero if the
/// allocated resources are not provided as a part of extended data.
///
UINT16 AllocResSize;
///
/// The device path to the controller or the hardware device that did not get the requested
/// resources. Note that this parameter is the variable-length device path structure and not
/// a pointer to this structure.
///
// EFI_DEVICE_PATH_PROTOCOL DevicePath;
///
/// The requested resources in the format of an ACPI 2.0 resource descriptor. This
/// parameter is not a pointer; it is the complete resource descriptor.
///
// UINT8 ReqRes[];
///
/// The allocated resources in the format of an ACPI 2.0 resource descriptor. This
/// parameter is not a pointer; it is the complete resource descriptor.
///
// UINT8 AllocRes[];
} EFI_RESOURCE_ALLOC_FAILURE_ERROR_DATA;
///
/// This structure provides a calculation for base-10 representations.
///
/// Not consistent with PI 1.2 Specification.
/// This data type is not defined in the PI 1.2 Specification, but is
/// required by several of the other data structures in this file.
///
typedef struct {
///
/// The INT16 number by which to multiply the base-2 representation.
///
INT16 Value;
///
/// The INT16 number by which to raise the base-2 calculation.
///
INT16 Exponent;
} EFI_EXP_BASE10_DATA;
///
/// This structure provides the voltage at the time of error. It also provides
/// the threshold value indicating the minimum or maximum voltage that is considered
/// an error. If the voltage is less then the threshold, the error indicates that the
/// voltage fell below the minimum acceptable value. If the voltage is greater then the threshold,
/// the error indicates that the voltage rose above the maximum acceptable value.
///
typedef struct {
///
/// The data header identifying the data. DataHeader.HeaderSize should be
/// sizeof (EFI_STATUS_CODE_DATA), DataHeader.Size should be
/// sizeof (EFI_COMPUTING_UNIT_VOLTAGE_ERROR_DATA) -
/// HeaderSize, and DataHeader.Type should be
/// EFI_STATUS_CODE_SPECIFIC_DATA_GUID.
///
EFI_STATUS_CODE_DATA DataHeader;
///
/// The voltage value at the time of the error.
///
EFI_EXP_BASE10_DATA Voltage;
///
/// The voltage threshold.
///
EFI_EXP_BASE10_DATA Threshold;
} EFI_COMPUTING_UNIT_VOLTAGE_ERROR_DATA;
///
/// Microcode Update Extended Error Data
///
typedef struct {
///
/// The data header identifying the data. DataHeader.HeaderSize should be
/// sizeof (EFI_STATUS_CODE_DATA), DataHeader.Size should be
/// sizeof (EFI_COMPUTING_UNIT_MICROCODE_UPDATE_ERROR_DATA) -
/// HeaderSize, and DataHeader.Type should be
/// EFI_STATUS_CODE_SPECIFIC_DATA_GUID.
///
EFI_STATUS_CODE_DATA DataHeader;
///
/// The version of the microcode update from the header.
///
UINT32 Version;
} EFI_COMPUTING_UNIT_MICROCODE_UPDATE_ERROR_DATA;
///
/// This structure provides details about the computing unit timer expiration error.
/// The timer limit provides the timeout value of the timer prior to expiration.
///
typedef struct {
///
/// The data header identifying the data. DataHeader.HeaderSize should be
/// sizeof (EFI_STATUS_CODE_DATA), DataHeader.Size should be
/// sizeof (EFI_COMPUTING_UNIT_TIMER_EXPIRED_ERROR_DATA) -
/// HeaderSize, and DataHeader.Type should be
/// EFI_STATUS_CODE_SPECIFIC_DATA_GUID.
///
EFI_STATUS_CODE_DATA DataHeader;
///
/// The number of seconds that the computing unit timer was configured to expire.
///
EFI_EXP_BASE10_DATA TimerLimit;
} EFI_COMPUTING_UNIT_TIMER_EXPIRED_ERROR_DATA;
///
/// Attribute bits for EFI_HOST_PROCESSOR_MISMATCH_ERROR_DATA.Attributes
/// All other attributes are reserved for future use and must be initialized to 0.
///
///@{
#define EFI_COMPUTING_UNIT_MISMATCH_SPEED 0x0001
#define EFI_COMPUTING_UNIT_MISMATCH_FSB_SPEED 0x0002
#define EFI_COMPUTING_UNIT_MISMATCH_FAMILY 0x0004
#define EFI_COMPUTING_UNIT_MISMATCH_MODEL 0x0008
#define EFI_COMPUTING_UNIT_MISMATCH_STEPPING 0x0010
#define EFI_COMPUTING_UNIT_MISMATCH_CACHE_SIZE 0x0020
#define EFI_COMPUTING_UNIT_MISMATCH_OEM1 0x1000
#define EFI_COMPUTING_UNIT_MISMATCH_OEM2 0x2000
#define EFI_COMPUTING_UNIT_MISMATCH_OEM3 0x4000
#define EFI_COMPUTING_UNIT_MISMATCH_OEM4 0x8000
///@}
///
/// This structure defines extended data for processor mismatch errors.
///
/// This provides information to indicate which processors mismatch, and how they mismatch. The
/// status code contains the instance number of the processor that is in error. This structure's
/// Instance indicates the second processor that does not match. This differentiation allows the
/// consumer to determine which two processors do not match. The Attributes indicate what
/// mismatch is being reported. Because Attributes is a bit field, more than one mismatch can be
/// reported with one error code.
///
typedef struct {
///
/// The data header identifying the data. DataHeader.HeaderSize should be
/// sizeof (EFI_STATUS_CODE_DATA), DataHeader.Size should be
/// sizeof (EFI_ HOST_PROCESSOR_MISMATCH_ERROR_DATA) -
/// HeaderSize , and DataHeader.Type should be
/// EFI_STATUS_CODE_SPECIFIC_DATA_GUID.
///
EFI_STATUS_CODE_DATA DataHeader;
///
/// The unit number of the computing unit that does not match.
///
UINT32 Instance;
///
/// The attributes describing the failure.
///
UINT16 Attributes;
} EFI_HOST_PROCESSOR_MISMATCH_ERROR_DATA;
///
/// This structure provides details about the computing unit thermal failure.
///
/// This structure provides the temperature at the time of error. It also provides the threshold value
/// indicating the minimum temperature that is considered an error.
///
typedef struct {
///
/// The data header identifying the data. DataHeader.HeaderSize should be
/// sizeof (EFI_STATUS_CODE_DATA), DataHeader.Size should be
/// sizeof (EFI_COMPUTING_UNIT_THERMAL_ERROR_DATA) -
/// HeaderSize , and DataHeader.Type should be
/// EFI_STATUS_CODE_SPECIFIC_DATA_GUID.
///
EFI_STATUS_CODE_DATA DataHeader;
///
/// The thermal value at the time of the error.
///
EFI_EXP_BASE10_DATA Temperature;
///
/// The thermal threshold.
///
EFI_EXP_BASE10_DATA Threshold;
} EFI_COMPUTING_UNIT_THERMAL_ERROR_DATA;
///
/// Enumeration of valid cache types
///
typedef enum {
EfiInitCacheDataOnly,
EfiInitCacheInstrOnly,
EfiInitCacheBoth,
EfiInitCacheUnspecified
} EFI_INIT_CACHE_TYPE;
///
/// Embedded cache init extended data
///
typedef struct {
///
/// The data header identifying the data. DataHeader.HeaderSize should be
/// sizeof (EFI_STATUS_CODE_DATA), DataHeader.Size should be
/// sizeof (EFI_CACHE_INIT_DATA) - HeaderSize , and
/// DataHeader.Type should be EFI_STATUS_CODE_SPECIFIC_DATA_GUID.
///
EFI_STATUS_CODE_DATA DataHeader;
///
/// The cache level. Starts with 1 for level 1 cache.
///
UINT32 Level;
///
/// The type of cache.
///
EFI_INIT_CACHE_TYPE Type;
} EFI_CACHE_INIT_DATA;
///
///
///
typedef UINT32 EFI_CPU_STATE_CHANGE_CAUSE;
///
/// The reasons that the processor is disabled.
/// Used to fill in EFI_COMPUTING_UNIT_CPU_DISABLED_ERROR_DATA.Cause.
///
///@{
#define EFI_CPU_CAUSE_INTERNAL_ERROR 0x0001
#define EFI_CPU_CAUSE_THERMAL_ERROR 0x0002
#define EFI_CPU_CAUSE_SELFTEST_FAILURE 0x0004
#define EFI_CPU_CAUSE_PREBOOT_TIMEOUT 0x0008
#define EFI_CPU_CAUSE_FAILED_TO_START 0x0010
#define EFI_CPU_CAUSE_CONFIG_ERROR 0x0020
#define EFI_CPU_CAUSE_USER_SELECTION 0x0080
#define EFI_CPU_CAUSE_BY_ASSOCIATION 0x0100
#define EFI_CPU_CAUSE_UNSPECIFIED 0x8000
///@}
///
/// This structure provides information about the disabled computing unit.
///
/// This structure provides details as to why and how the computing unit was disabled. The causes
/// should cover the typical reasons a processor would be disabled. How the processor was disabled is
/// important because there are distinct differences between hardware and software disabling.
///
typedef struct {
///
/// The data header identifying the data. DataHeader.HeaderSize should be
/// sizeof (EFI_STATUS_CODE_DATA), DataHeader.Size should be
/// sizeof (EFI_COMPUTING_UNIT_CPU_DISABLED_ERROR_DATA) -
/// HeaderSize, and DataHeader.Type should be
/// EFI_STATUS_CODE_SPECIFIC_DATA_GUID.
///
EFI_STATUS_CODE_DATA DataHeader;
///
/// The reason for disabling the processor.
///
UINT32 Cause;
///
/// TRUE if the processor is disabled via software means such as not listing it in the ACPI tables.
/// Such a processor will respond to Interprocessor Interrupts (IPIs). FALSE if the processor is hardware
/// disabled, which means it is invisible to software and will not respond to IPIs.
///
BOOLEAN SoftwareDisabled;
} EFI_COMPUTING_UNIT_CPU_DISABLED_ERROR_DATA;
///
/// Memory Error Granularity Definition
///
typedef UINT8 EFI_MEMORY_ERROR_GRANULARITY;
///
/// Memory Error Granularities. Used to fill in EFI_MEMORY_EXTENDED_ERROR_DATA.Granularity.
///
///@{
#define EFI_MEMORY_ERROR_OTHER 0x01
#define EFI_MEMORY_ERROR_UNKNOWN 0x02
#define EFI_MEMORY_ERROR_DEVICE 0x03
#define EFI_MEMORY_ERROR_PARTITION 0x04
///@}
///
/// Memory Error Operation Definition
///
typedef UINT8 EFI_MEMORY_ERROR_OPERATION;
///
/// Memory Error Operations. Used to fill in EFI_MEMORY_EXTENDED_ERROR_DATA.Operation.
///
///@{
#define EFI_MEMORY_OPERATION_OTHER 0x01
#define EFI_MEMORY_OPERATION_UNKNOWN 0x02
#define EFI_MEMORY_OPERATION_READ 0x03
#define EFI_MEMORY_OPERATION_WRITE 0x04
#define EFI_MEMORY_OPERATION_PARTIAL_WRITE 0x05
///@}
///
/// This structure provides specific details about the memory error that was detected. It provides
/// enough information so that consumers can identify the exact failure and provides enough
/// information to enable corrective action if necessary.
///
typedef struct {
///
/// The data header identifying the data. DataHeader.HeaderSize should be
/// sizeof (EFI_STATUS_CODE_DATA), DataHeader.Size should be
/// sizeof (EFI_MEMORY_EXTENDED_ERROR_DATA) - HeaderSize, and
/// DataHeader.Type should be EFI_STATUS_CODE_SPECIFIC_DATA_GUID.
///
EFI_STATUS_CODE_DATA DataHeader;
///
/// The error granularity type.
///
EFI_MEMORY_ERROR_GRANULARITY Granularity;
///
/// The operation that resulted in the error being detected.
///
EFI_MEMORY_ERROR_OPERATION Operation;
///
/// The error syndrome, vendor-specific ECC syndrome, or CRC data associated with
/// the error. If unknown, should be initialized to 0.
/// Inconsistent with specification here:
/// This field in StatusCodes spec0.9 is defined as UINT32, keep code unchanged.
///
UINTN Syndrome;
///
/// The physical address of the error.
///
EFI_PHYSICAL_ADDRESS Address;
///
/// The range, in bytes, within which the error address can be determined.
///
UINTN Resolution;
} EFI_MEMORY_EXTENDED_ERROR_DATA;
///
/// A definition to describe that the operation is performed on multiple devices within the array.
/// May be used for EFI_STATUS_CODE_DIMM_NUMBER.Array and EFI_STATUS_CODE_DIMM_NUMBER.Device.
///
#define EFI_MULTIPLE_MEMORY_DEVICE_OPERATION 0xfffe
///
/// A definition to describe that the operation is performed on all devices within the array.
/// May be used for EFI_STATUS_CODE_DIMM_NUMBER.Array and EFI_STATUS_CODE_DIMM_NUMBER.Device.
///
#define EFI_ALL_MEMORY_DEVICE_OPERATION 0xffff
///
/// A definition to describe that the operation is performed on multiple arrays.
/// May be used for EFI_STATUS_CODE_DIMM_NUMBER.Array and EFI_STATUS_CODE_DIMM_NUMBER.Device.
///
#define EFI_MULTIPLE_MEMORY_ARRAY_OPERATION 0xfffe
///
/// A definition to describe that the operation is performed on all the arrays.
/// May be used for EFI_STATUS_CODE_DIMM_NUMBER.Array and EFI_STATUS_CODE_DIMM_NUMBER.Device.
///
#define EFI_ALL_MEMORY_ARRAY_OPERATION 0xffff
///
/// This extended data provides some context that consumers can use to locate a DIMM within the
/// overall memory scheme.
///
/// This extended data provides some context that consumers can use to locate a DIMM within the
/// overall memory scheme. The Array and Device numbers may indicate a specific DIMM, or they
/// may be populated with the group definitions in "Related Definitions" below.
///
typedef struct {
///
/// The data header identifying the data. DataHeader.HeaderSize should be
/// sizeof (EFI_STATUS_CODE_DATA), DataHeader.Size should be
/// sizeof (EFI_STATUS_CODE_DIMM_NUMBER) - HeaderSize, and
/// DataHeader.Type should be EFI_STATUS_CODE_SPECIFIC_DATA_GUID.
///
EFI_STATUS_CODE_DATA DataHeader;
///
/// The memory array number.
///
UINT16 Array;
///
/// The device number within that Array.
///
UINT16 Device;
} EFI_STATUS_CODE_DIMM_NUMBER;
///
/// This structure defines extended data describing memory modules that do not match.
///
/// This extended data may be used to convey the specifics of memory modules that do not match.
///
typedef struct {
///
/// The data header identifying the data. DataHeader.HeaderSize should be
/// sizeof (EFI_STATUS_CODE_DATA), DataHeader.Size should be
/// sizeof (EFI_MEMORY_MODULE_MISMATCH_ERROR_DATA) -
/// HeaderSize, and DataHeader.Type should be
/// EFI_STATUS_CODE_SPECIFIC_DATA_GUID.
///
EFI_STATUS_CODE_DATA DataHeader;
///
/// The instance number of the memory module that does not match.
///
EFI_STATUS_CODE_DIMM_NUMBER Instance;
} EFI_MEMORY_MODULE_MISMATCH_ERROR_DATA;
///
/// This structure defines extended data describing a memory range.
///
/// This extended data may be used to convey the specifics of a memory range. Ranges are specified
/// with a start address and a length.
///
typedef struct {
///
/// The data header identifying the data. DataHeader.HeaderSize should be
/// sizeof (EFI_STATUS_CODE_DATA), DataHeader.Size should be
/// sizeof (EFI_MEMORY_RANGE_EXTENDED_DATA) - HeaderSize, and
/// DataHeader.Type should be EFI_STATUS_CODE_SPECIFIC_DATA_GUID.
///
EFI_STATUS_CODE_DATA DataHeader;
///
/// The starting address of the memory range.
///
EFI_PHYSICAL_ADDRESS Start;
///
/// The length in bytes of the memory range.
///
EFI_PHYSICAL_ADDRESS Length;
} EFI_MEMORY_RANGE_EXTENDED_DATA;
///
/// This structure provides the assert information that is typically associated with a debug assertion failing.
///
/// The data indicates the location of the assertion that failed in the source code. This information
/// includes the file name and line number that are necessary to find the failing assertion in source code.
///
typedef struct {
///
/// The data header identifying the data. DataHeader.HeaderSize should be
/// sizeof (EFI_STATUS_CODE_DATA), DataHeader.Size should be
/// sizeof (EFI_DEBUG_ASSERT_DATA) - HeaderSize , and
/// DataHeader.Type should be EFI_STATUS_CODE_SPECIFIC_DATA_GUID.
///
EFI_STATUS_CODE_DATA DataHeader;
///
/// The line number of the source file where the fault was generated.
///
UINT32 LineNumber;
///
/// The size in bytes of FileName.
///
UINT32 FileNameSize;
///
/// A pointer to a NULL-terminated ASCII or Unicode string that represents
/// the file name of the source file where the fault was generated.
///
EFI_STATUS_CODE_STRING_DATA *FileName;
} EFI_DEBUG_ASSERT_DATA;
///
/// System Context Data EBC/IA32/IPF
///
typedef union {
///
/// The context of the EBC virtual machine when the exception was generated. Type
/// EFI_SYSTEM_CONTEXT_EBC is defined in EFI_DEBUG_SUPPORT_PROTOCOL
/// in the UEFI Specification.
///
EFI_SYSTEM_CONTEXT_EBC SystemContextEbc;
///
/// The context of the IA-32 processor when the exception was generated. Type
/// EFI_SYSTEM_CONTEXT_IA32 is defined in the
/// EFI_DEBUG_SUPPORT_PROTOCOL in the UEFI Specification.
///
EFI_SYSTEM_CONTEXT_IA32 SystemContextIa32;
///
/// The context of the Itanium(R) processor when the exception was generated. Type
/// EFI_SYSTEM_CONTEXT_IPF is defined in the
/// EFI_DEBUG_SUPPORT_PROTOCOL in the UEFI Specification.
///
EFI_SYSTEM_CONTEXT_IPF SystemContextIpf;
///
/// The context of the X64 processor when the exception was generated. Type
/// EFI_SYSTEM_CONTEXT_X64 is defined in the
/// EFI_DEBUG_SUPPORT_PROTOCOL in the UEFI Specification.
///
EFI_SYSTEM_CONTEXT_X64 SystemContextX64;
///
/// The context of the ARM processor when the exception was generated. Type
/// EFI_SYSTEM_CONTEXT_ARM is defined in the
/// EFI_DEBUG_SUPPORT_PROTOCOL in the UEFI Specification.
///
EFI_SYSTEM_CONTEXT_ARM SystemContextArm;
} EFI_STATUS_CODE_EXCEP_SYSTEM_CONTEXT;
///
/// This structure defines extended data describing a processor exception error.
///
/// This extended data allows the processor context that is present at the time of the exception to be
/// reported with the exception. The format and contents of the context data varies depending on the
/// processor architecture.
///
typedef struct {
///
/// The data header identifying the data. DataHeader.HeaderSize should be
/// sizeof (EFI_STATUS_CODE_DATA), DataHeader.Size should be
/// sizeof (EFI_STATUS_CODE_EXCEP_EXTENDED_DATA) - HeaderSize,
/// and DataHeader.Type should be
/// EFI_STATUS_CODE_SPECIFIC_DATA_GUID.
///
EFI_STATUS_CODE_DATA DataHeader;
///
/// The system context.
///
EFI_STATUS_CODE_EXCEP_SYSTEM_CONTEXT Context;
} EFI_STATUS_CODE_EXCEP_EXTENDED_DATA;
///
/// This structure defines extended data describing a call to a driver binding protocol start function.
///
/// This extended data records information about a Start() function call. Start() is a member of
/// the UEFI Driver Binding Protocol.
///
typedef struct {
///
/// The data header identifying the data. DataHeader.HeaderSize should be
/// sizeof (EFI_STATUS_CODE_DATA), DataHeader.Size should be
/// sizeof (EFI_STATUS_CODE_START_EXTENDED_DATA) - HeaderSize,
/// and DataHeader.Type should be
/// EFI_STATUS_CODE_SPECIFIC_DATA_GUID.
///
EFI_STATUS_CODE_DATA DataHeader;
///
/// The controller handle.
///
EFI_HANDLE ControllerHandle;
///
/// The driver binding handle.
///
EFI_HANDLE DriverBindingHandle;
///
/// The size of the RemainingDevicePath. It is zero if the Start() function is
/// called with RemainingDevicePath = NULL. The UEFI Specification allows
/// that the Start() function of bus drivers can be called in this way.
///
UINT16 DevicePathSize;
///
/// Matches the RemainingDevicePath parameter being passed to the Start() function.
/// Note that this parameter is the variable-length device path and not a pointer
/// to the device path.
///
// EFI_DEVICE_PATH_PROTOCOL RemainingDevicePath;
} EFI_STATUS_CODE_START_EXTENDED_DATA;
///
/// This structure defines extended data describing a legacy option ROM (OpROM).
///
/// The device handle and ROM image base can be used by consumers to determine which option ROM
/// failed. Due to the black-box nature of legacy option ROMs, the amount of information that can be
/// obtained may be limited.
///
typedef struct {
///
/// The data header identifying the data. DataHeader.HeaderSize should be
/// sizeof (EFI_STATUS_CODE_DATA), DataHeader.Size should be
/// sizeof (EFI_LEGACY_OPROM_EXTENDED_DATA) - HeaderSize, and
/// DataHeader.Type should be EFI_STATUS_CODE_SPECIFIC_DATA_GUID.
///
EFI_STATUS_CODE_DATA DataHeader;
///
/// The handle corresponding to the device that this legacy option ROM is being invoked.
///
EFI_HANDLE DeviceHandle;
///
/// The base address of the shadowed legacy ROM image. May or may not point to the shadow RAM area.
///
EFI_PHYSICAL_ADDRESS RomImageBase;
} EFI_LEGACY_OPROM_EXTENDED_DATA;
///
/// This structure defines extended data describing an EFI_STATUS return value that stands for a
/// failed function call (such as a UEFI boot service).
///
typedef struct {
///
/// The data header identifying the data:
/// DataHeader.HeaderSize should be sizeof(EFI_STATUS_CODE_DATA),
/// DataHeader.Size should be sizeof(EFI_RETURN_STATUS_EXTENDED_DATA) - HeaderSize,
/// DataHeader.Type should be EFI_STATUS_CODE_SPECIFIC_DATA_GUID.
///
EFI_STATUS_CODE_DATA DataHeader;
///
/// The EFI_STATUS return value of the service or function whose failure triggered the
/// reporting of the status code (generally an error code or a debug code).
///
EFI_STATUS ReturnStatus;
} EFI_RETURN_STATUS_EXTENDED_DATA;
extern EFI_GUID gEfiStatusCodeSpecificDataGuid;
#endif

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/** @file
Guid & data structure used for EFI System Resource Table (ESRT)
Copyright (c) 2015 - 2020, Intel Corporation. All rights reserved.<BR>
Copyright (c) Microsoft Corporation.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@par Revision Reference:
GUIDs defined in UEFI 2.5 spec.
**/
#ifndef _SYSTEM_RESOURCE_TABLE_H__
#define _SYSTEM_RESOURCE_TABLE_H__
#define EFI_SYSTEM_RESOURCE_TABLE_GUID \
{ \
0xb122a263, 0x3661, 0x4f68, {0x99, 0x29, 0x78, 0xf8, 0xb0, 0xd6, 0x21, 0x80 } \
}
///
/// Current Entry Version
///
#define EFI_SYSTEM_RESOURCE_TABLE_FIRMWARE_RESOURCE_VERSION 1
///
/// Firmware Type Definitions
///
#define ESRT_FW_TYPE_UNKNOWN 0x00000000
#define ESRT_FW_TYPE_SYSTEMFIRMWARE 0x00000001
#define ESRT_FW_TYPE_DEVICEFIRMWARE 0x00000002
#define ESRT_FW_TYPE_UEFIDRIVER 0x00000003
///
/// Last Attempt Status Values
///
#define LAST_ATTEMPT_STATUS_SUCCESS 0x00000000
#define LAST_ATTEMPT_STATUS_ERROR_UNSUCCESSFUL 0x00000001
#define LAST_ATTEMPT_STATUS_ERROR_INSUFFICIENT_RESOURCES 0x00000002
#define LAST_ATTEMPT_STATUS_ERROR_INCORRECT_VERSION 0x00000003
#define LAST_ATTEMPT_STATUS_ERROR_INVALID_FORMAT 0x00000004
#define LAST_ATTEMPT_STATUS_ERROR_AUTH_ERROR 0x00000005
#define LAST_ATTEMPT_STATUS_ERROR_PWR_EVT_AC 0x00000006
#define LAST_ATTEMPT_STATUS_ERROR_PWR_EVT_BATT 0x00000007
#define LAST_ATTEMPT_STATUS_ERROR_UNSATISFIED_DEPENDENCIES 0x00000008
///
/// LAST_ATTEMPT_STATUS_ERROR_UNSUCCESSFUL_VENDOR_RANGE_MAX is defined as
/// 0x4000 as of UEFI Specification 2.8B. This will be modified in the
/// future to the correct value 0x3FFF. To ensure correct implementation,
/// this change is preemptively made in the value defined below.
///
/// When the UEFI Specification is updated, this comment block can be
/// removed.
///
#define LAST_ATTEMPT_STATUS_ERROR_UNSUCCESSFUL_VENDOR_RANGE_MIN 0x00001000
#define LAST_ATTEMPT_STATUS_ERROR_UNSUCCESSFUL_VENDOR_RANGE_MAX 0x00003FFF
typedef struct {
///
/// The firmware class field contains a GUID that identifies a firmware component
/// that can be updated via UpdateCapsule(). This GUID must be unique within all
/// entries of the ESRT.
///
EFI_GUID FwClass;
///
/// Identifies the type of firmware resource.
///
UINT32 FwType;
///
/// The firmware version field represents the current version of the firmware
/// resource, value must always increase as a larger number represents a newer
/// version.
///
UINT32 FwVersion;
///
/// The lowest firmware resource version to which a firmware resource can be
/// rolled back for the given system/device. Generally this is used to protect
/// against known and fixed security issues.
///
UINT32 LowestSupportedFwVersion;
///
/// The capsule flags field contains the CapsuleGuid flags (bits 0- 15) as defined
/// in the EFI_CAPSULE_HEADER that will be set in the capsule header.
///
UINT32 CapsuleFlags;
///
/// The last attempt version field describes the last firmware version for which
/// an update was attempted (uses the same format as Firmware Version).
/// Last Attempt Version is updated each time an UpdateCapsule() is attempted for
/// an ESRT entry and is preserved across reboots (non-volatile). However, in
/// cases where the attempt version is not recorded due to limitations in the
/// update process, the field shall set to zero after a failed update. Similarly,
/// in the case of a removable device, this value is set to 0 in cases where the
/// device has not been updated since being added to the system.
///
UINT32 LastAttemptVersion;
///
/// The last attempt status field describes the result of the last firmware update
/// attempt for the firmware resource entry.
/// LastAttemptStatus is updated each time an UpdateCapsule() is attempted for an
/// ESRT entry and is preserved across reboots (non-volatile).
/// If a firmware update has never been attempted or is unknown, for example after
/// fresh insertion of a removable device, LastAttemptStatus must be set to Success.
///
UINT32 LastAttemptStatus;
} EFI_SYSTEM_RESOURCE_ENTRY;
typedef struct {
///
/// The number of firmware resources in the table, must not be zero.
///
UINT32 FwResourceCount;
///
/// The maximum number of resource array entries that can be within the table
/// without reallocating the table, must not be zero.
///
UINT32 FwResourceCountMax;
///
/// The version of the EFI_SYSTEM_RESOURCE_ENTRY entities used in this table.
/// This field should be set to 1.
///
UINT64 FwResourceVersion;
///
/// Array of EFI_SYSTEM_RESOURCE_ENTRY
///
//EFI_SYSTEM_RESOURCE_ENTRY Entries[];
} EFI_SYSTEM_RESOURCE_TABLE;
extern EFI_GUID gEfiSystemResourceTableGuid;
#endif

27
src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Guid/VectorHandoffTable.h Normal file
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/** @file
GUID for system configuration table entry that points to the table
in case an entity in DXE wishes to update/change the vector table contents.
Copyright (c) 2013 - 2018, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@par Revision Reference:
GUID defined in PI 1.2.1 spec.
**/
#ifndef __EFI_VECTOR_HANDOFF_TABLE_H__
#define __EFI_VECTOR_HANDOFF_TABLE_H__
#include <Ppi/VectorHandoffInfo.h>
//
// System configuration table entry that points to the table
// in case an entity in DXE wishes to update/change the vector
// table contents.
//
#define EFI_VECTOR_HANDOF_TABLE_GUID \
{ 0x996ec11c, 0x5397, 0x4e73, { 0xb5, 0x8f, 0x82, 0x7e, 0x52, 0x90, 0x6d, 0xef }}
extern EFI_GUID gEfiVectorHandoffTableGuid;
#endif

122
src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Guid/WinCertificate.h Normal file
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/** @file
GUID for UEFI WIN_CERTIFICATE structure.
Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@par Revision Reference:
GUID defined in UEFI 2.0 spec.
**/
#ifndef __EFI_WIN_CERTIFICATE_H__
#define __EFI_WIN_CERTIFICATE_H__
//
// _WIN_CERTIFICATE.wCertificateType
//
#define WIN_CERT_TYPE_PKCS_SIGNED_DATA 0x0002
#define WIN_CERT_TYPE_EFI_PKCS115 0x0EF0
#define WIN_CERT_TYPE_EFI_GUID 0x0EF1
///
/// The WIN_CERTIFICATE structure is part of the PE/COFF specification.
///
typedef struct {
///
/// The length of the entire certificate,
/// including the length of the header, in bytes.
///
UINT32 dwLength;
///
/// The revision level of the WIN_CERTIFICATE
/// structure. The current revision level is 0x0200.
///
UINT16 wRevision;
///
/// The certificate type. See WIN_CERT_TYPE_xxx for the UEFI
/// certificate types. The UEFI specification reserves the range of
/// certificate type values from 0x0EF0 to 0x0EFF.
///
UINT16 wCertificateType;
///
/// The following is the actual certificate. The format of
/// the certificate depends on wCertificateType.
///
/// UINT8 bCertificate[ANYSIZE_ARRAY];
///
} WIN_CERTIFICATE;
///
/// WIN_CERTIFICATE_UEFI_GUID.CertType
///
#define EFI_CERT_TYPE_RSA2048_SHA256_GUID \
{0xa7717414, 0xc616, 0x4977, {0x94, 0x20, 0x84, 0x47, 0x12, 0xa7, 0x35, 0xbf } }
///
/// WIN_CERTIFICATE_UEFI_GUID.CertData
///
typedef struct {
EFI_GUID HashType;
UINT8 PublicKey[256];
UINT8 Signature[256];
} EFI_CERT_BLOCK_RSA_2048_SHA256;
///
/// Certificate which encapsulates a GUID-specific digital signature
///
typedef struct {
///
/// This is the standard WIN_CERTIFICATE header, where
/// wCertificateType is set to WIN_CERT_TYPE_EFI_GUID.
///
WIN_CERTIFICATE Hdr;
///
/// This is the unique id which determines the
/// format of the CertData. .
///
EFI_GUID CertType;
///
/// The following is the certificate data. The format of
/// the data is determined by the CertType.
/// If CertType is EFI_CERT_TYPE_RSA2048_SHA256_GUID,
/// the CertData will be EFI_CERT_BLOCK_RSA_2048_SHA256 structure.
///
UINT8 CertData[1];
} WIN_CERTIFICATE_UEFI_GUID;
///
/// Certificate which encapsulates the RSASSA_PKCS1-v1_5 digital signature.
///
/// The WIN_CERTIFICATE_UEFI_PKCS1_15 structure is derived from
/// WIN_CERTIFICATE and encapsulate the information needed to
/// implement the RSASSA-PKCS1-v1_5 digital signature algorithm as
/// specified in RFC2437.
///
typedef struct {
///
/// This is the standard WIN_CERTIFICATE header, where
/// wCertificateType is set to WIN_CERT_TYPE_UEFI_PKCS1_15.
///
WIN_CERTIFICATE Hdr;
///
/// This is the hashing algorithm which was performed on the
/// UEFI executable when creating the digital signature.
///
EFI_GUID HashAlgorithm;
///
/// The following is the actual digital signature. The
/// size of the signature is the same size as the key
/// (1024-bit key is 128 bytes) and can be determined by
/// subtracting the length of the other parts of this header
/// from the total length of the certificate as found in
/// Hdr.dwLength.
///
/// UINT8 Signature[];
///
} WIN_CERTIFICATE_EFI_PKCS1_15;
extern EFI_GUID gEfiCertTypeRsa2048Sha256Guid;
#endif

72
src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Ia32/Nasm.inc Normal file
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;------------------------------------------------------------------------------
;
; Copyright (c) 2019 - 2021, Intel Corporation. All rights reserved.<BR>
; SPDX-License-Identifier: BSD-2-Clause-Patent
;
; Abstract:
;
; This file provides macro definitions for NASM files.
;
;------------------------------------------------------------------------------
%macro SAVEPREVSSP 0
DB 0xF3, 0x0F, 0x01, 0xEA
%endmacro
%macro CLRSSBSY_EAX 0
DB 0x67, 0xF3, 0x0F, 0xAE, 0x30
%endmacro
%macro RSTORSSP_EAX 0
DB 0x67, 0xF3, 0x0F, 0x01, 0x28
%endmacro
%macro SETSSBSY 0
DB 0xF3, 0x0F, 0x01, 0xE8
%endmacro
%macro READSSP_EAX 0
DB 0xF3, 0x0F, 0x1E, 0xC8
%endmacro
%macro INCSSP_EAX 0
DB 0xF3, 0x0F, 0xAE, 0xE8
%endmacro
; NASM provides built-in macros STRUC and ENDSTRUC for structure definition.
; For example, to define a structure called mytype containing a longword,
; a word, a byte and a string of bytes, you might code
;
; struc mytype
;
; mt_long: resd 1
; mt_word: resw 1
; mt_byte: resb 1
; mt_str: resb 32
;
; endstruc
;
; Below macros are help to map the C types and the RESB family of pseudo-instructions.
; So that the above structure definition can be coded as
;
; struc mytype
;
; mt_long: CTYPE_UINT32 1
; mt_word: CTYPE_UINT16 1
; mt_byte: CTYPE_UINT8 1
; mt_str: CTYPE_CHAR8 32
;
; endstruc
%define CTYPE_UINT64 resq
%define CTYPE_INT64 resq
%define CTYPE_UINT32 resd
%define CTYPE_INT32 resd
%define CTYPE_UINT16 resw
%define CTYPE_INT16 resw
%define CTYPE_BOOLEAN resb
%define CTYPE_UINT8 resb
%define CTYPE_CHAR8 resb
%define CTYPE_INT8 resb
%define CTYPE_UINTN resd
%define CTYPE_INTN resd

322
src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Ia32/ProcessorBind.h Normal file
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/** @file
Processor or Compiler specific defines and types for IA-32 architecture.
Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef __PROCESSOR_BIND_H__
#define __PROCESSOR_BIND_H__
///
/// Define the processor type so other code can make processor based choices.
///
#define MDE_CPU_IA32
//
// Make sure we are using the correct packing rules per EFI specification
//
#if !defined(__GNUC__)
#pragma pack()
#endif
#if defined(__INTEL_COMPILER)
//
// Disable ICC's remark #869: "Parameter" was never referenced warning.
// This is legal ANSI C code so we disable the remark that is turned on with -Wall
//
#pragma warning ( disable : 869 )
//
// Disable ICC's remark #1418: external function definition with no prior declaration.
// This is legal ANSI C code so we disable the remark that is turned on with /W4
//
#pragma warning ( disable : 1418 )
//
// Disable ICC's remark #1419: external declaration in primary source file
// This is legal ANSI C code so we disable the remark that is turned on with /W4
//
#pragma warning ( disable : 1419 )
//
// Disable ICC's remark #593: "Variable" was set but never used.
// This is legal ANSI C code so we disable the remark that is turned on with /W4
//
#pragma warning ( disable : 593 )
#endif
#if defined(_MSC_EXTENSIONS)
//
// Disable warning that make it impossible to compile at /W4
// This only works for Microsoft* tools
//
//
// Disabling bitfield type checking warnings.
//
#pragma warning ( disable : 4214 )
//
// Disabling the unreferenced formal parameter warnings.
//
#pragma warning ( disable : 4100 )
//
// Disable slightly different base types warning as CHAR8 * can not be set
// to a constant string.
//
#pragma warning ( disable : 4057 )
//
// ASSERT(FALSE) or while (TRUE) are legal constructs so suppress this warning
//
#pragma warning ( disable : 4127 )
//
// This warning is caused by functions defined but not used. For precompiled header only.
//
#pragma warning ( disable : 4505 )
//
// This warning is caused by empty (after preprocessing) source file. For precompiled header only.
//
#pragma warning ( disable : 4206 )
#if defined(_MSC_VER) && _MSC_VER >= 1800
//
// Disable these warnings for VS2013.
//
//
// This warning is for potentially uninitialized local variable, and it may cause false
// positive issues in VS2013 and VS2015 build
//
#pragma warning ( disable : 4701 )
//
// This warning is for potentially uninitialized local pointer variable, and it may cause
// false positive issues in VS2013 and VS2015 build
//
#pragma warning ( disable : 4703 )
#endif
#endif
#if defined(_MSC_EXTENSIONS)
//
// use Microsoft C compiler dependent integer width types
//
///
/// 8-byte unsigned value.
///
typedef unsigned __int64 UINT64;
///
/// 8-byte signed value.
///
typedef __int64 INT64;
///
/// 4-byte unsigned value.
///
typedef unsigned __int32 UINT32;
///
/// 4-byte signed value.
///
typedef __int32 INT32;
///
/// 2-byte unsigned value.
///
typedef unsigned short UINT16;
///
/// 2-byte Character. Unless otherwise specified all strings are stored in the
/// UTF-16 encoding format as defined by Unicode 2.1 and ISO/IEC 10646 standards.
///
typedef unsigned short CHAR16;
///
/// 2-byte signed value.
///
typedef short INT16;
///
/// Logical Boolean. 1-byte value containing 0 for FALSE or a 1 for TRUE. Other
/// values are undefined.
///
typedef unsigned char BOOLEAN;
///
/// 1-byte unsigned value.
///
typedef unsigned char UINT8;
///
/// 1-byte Character.
///
typedef char CHAR8;
///
/// 1-byte signed value.
///
typedef signed char INT8;
#else
///
/// 8-byte unsigned value.
///
typedef unsigned long long UINT64;
///
/// 8-byte signed value.
///
typedef long long INT64;
///
/// 4-byte unsigned value.
///
typedef unsigned int UINT32;
///
/// 4-byte signed value.
///
typedef int INT32;
///
/// 2-byte unsigned value.
///
typedef unsigned short UINT16;
///
/// 2-byte Character. Unless otherwise specified all strings are stored in the
/// UTF-16 encoding format as defined by Unicode 2.1 and ISO/IEC 10646 standards.
///
typedef unsigned short CHAR16;
///
/// 2-byte signed value.
///
typedef short INT16;
///
/// Logical Boolean. 1-byte value containing 0 for FALSE or a 1 for TRUE. Other
/// values are undefined.
///
typedef unsigned char BOOLEAN;
///
/// 1-byte unsigned value.
///
typedef unsigned char UINT8;
///
/// 1-byte Character
///
typedef char CHAR8;
///
/// 1-byte signed value
///
typedef signed char INT8;
#endif
///
/// Unsigned value of native width. (4 bytes on supported 32-bit processor instructions;
/// 8 bytes on supported 64-bit processor instructions.)
///
typedef UINT32 UINTN;
///
/// Signed value of native width. (4 bytes on supported 32-bit processor instructions;
/// 8 bytes on supported 64-bit processor instructions.)
///
typedef INT32 INTN;
//
// Processor specific defines
//
///
/// A value of native width with the highest bit set.
///
#define MAX_BIT 0x80000000
///
/// A value of native width with the two highest bits set.
///
#define MAX_2_BITS 0xC0000000
///
/// Maximum legal IA-32 address.
///
#define MAX_ADDRESS 0xFFFFFFFF
///
/// Maximum usable address at boot time
///
#define MAX_ALLOC_ADDRESS MAX_ADDRESS
///
/// Maximum legal IA-32 INTN and UINTN values.
///
#define MAX_INTN ((INTN)0x7FFFFFFF)
#define MAX_UINTN ((UINTN)0xFFFFFFFF)
///
/// Minimum legal IA-32 INTN value.
///
#define MIN_INTN (((INTN)-2147483647) - 1)
///
/// The stack alignment required for IA-32.
///
#define CPU_STACK_ALIGNMENT sizeof(UINTN)
///
/// Page allocation granularity for IA-32.
///
#define DEFAULT_PAGE_ALLOCATION_GRANULARITY (0x1000)
#define RUNTIME_PAGE_ALLOCATION_GRANULARITY (0x1000)
//
// Modifier to ensure that all protocol member functions and EFI intrinsics
// use the correct C calling convention. All protocol member functions and
// EFI intrinsics are required to modify their member functions with EFIAPI.
//
#ifdef EFIAPI
///
/// If EFIAPI is already defined, then we use that definition.
///
#elif defined(_MSC_EXTENSIONS)
///
/// Microsoft* compiler specific method for EFIAPI calling convention.
///
#define EFIAPI __cdecl
#elif defined(__GNUC__) || defined(__clang__)
///
/// GCC specific method for EFIAPI calling convention.
///
#define EFIAPI __attribute__((cdecl))
#else
///
/// The default for a non Microsoft* or GCC compiler is to assume the EFI ABI
/// is the standard.
///
#define EFIAPI
#endif
#if defined(__GNUC__) || defined(__clang__)
///
/// For GNU assembly code, .global or .globl can declare global symbols.
/// Define this macro to unify the usage.
///
#define ASM_GLOBAL .globl
#endif
/**
Return the pointer to the first instruction of a function given a function pointer.
On IA-32 CPU architectures, these two pointer values are the same,
so the implementation of this macro is very simple.
@param FunctionPointer A pointer to a function.
@return The pointer to the first instruction of a function given a function pointer.
**/
#define FUNCTION_ENTRY_POINT(FunctionPointer) (VOID *)(UINTN)(FunctionPointer)
#ifndef __USER_LABEL_PREFIX__
#define __USER_LABEL_PREFIX__ _
#endif
#endif

16
src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/Acpi.h Normal file
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/** @file
This file contains the latest ACPI definitions that are
consumed by drivers that do not care about ACPI versions.
Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2019 - 2021, ARM Ltd. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef _ACPI_H_
#define _ACPI_H_
#include <IndustryStandard/Acpi64.h>
#endif

666
src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/Acpi10.h Normal file
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/** @file
ACPI 1.0b definitions from the ACPI Specification, revision 1.0b
Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2020, Arm Limited. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef _ACPI_1_0_H_
#define _ACPI_1_0_H_
#include <IndustryStandard/AcpiAml.h>
///
/// Common table header, this prefaces all ACPI tables, including FACS, but
/// excluding the RSD PTR structure.
///
typedef struct {
UINT32 Signature;
UINT32 Length;
} EFI_ACPI_COMMON_HEADER;
#pragma pack(1)
///
/// The common ACPI description table header. This structure prefaces most ACPI tables.
///
typedef struct {
UINT32 Signature;
UINT32 Length;
UINT8 Revision;
UINT8 Checksum;
UINT8 OemId[6];
UINT64 OemTableId;
UINT32 OemRevision;
UINT32 CreatorId;
UINT32 CreatorRevision;
} EFI_ACPI_DESCRIPTION_HEADER;
#pragma pack()
//
// Define for Descriptor
//
#define ACPI_SMALL_ITEM_FLAG 0x00
#define ACPI_LARGE_ITEM_FLAG 0x01
//
// Small Item Descriptor Name
//
#define ACPI_SMALL_IRQ_DESCRIPTOR_NAME 0x04
#define ACPI_SMALL_DMA_DESCRIPTOR_NAME 0x05
#define ACPI_SMALL_START_DEPENDENT_DESCRIPTOR_NAME 0x06
#define ACPI_SMALL_END_DEPENDENT_DESCRIPTOR_NAME 0x07
#define ACPI_SMALL_IO_PORT_DESCRIPTOR_NAME 0x08
#define ACPI_SMALL_FIXED_IO_PORT_DESCRIPTOR_NAME 0x09
#define ACPI_SMALL_VENDOR_DEFINED_DESCRIPTOR_NAME 0x0E
#define ACPI_SMALL_END_TAG_DESCRIPTOR_NAME 0x0F
//
// Large Item Descriptor Name
//
#define ACPI_LARGE_24_BIT_MEMORY_RANGE_DESCRIPTOR_NAME 0x01
#define ACPI_LARGE_VENDOR_DEFINED_DESCRIPTOR_NAME 0x04
#define ACPI_LARGE_32_BIT_MEMORY_RANGE_DESCRIPTOR_NAME 0x05
#define ACPI_LARGE_32_BIT_FIXED_MEMORY_RANGE_DESCRIPTOR_NAME 0x06
#define ACPI_LARGE_DWORD_ADDRESS_SPACE_DESCRIPTOR_NAME 0x07
#define ACPI_LARGE_WORD_ADDRESS_SPACE_DESCRIPTOR_NAME 0x08
#define ACPI_LARGE_EXTENDED_IRQ_DESCRIPTOR_NAME 0x09
#define ACPI_LARGE_QWORD_ADDRESS_SPACE_DESCRIPTOR_NAME 0x0A
//
// Small Item Descriptor Value
//
#define ACPI_IRQ_NOFLAG_DESCRIPTOR 0x22
#define ACPI_IRQ_DESCRIPTOR 0x23
#define ACPI_DMA_DESCRIPTOR 0x2A
#define ACPI_START_DEPENDENT_DESCRIPTOR 0x30
#define ACPI_START_DEPENDENT_EX_DESCRIPTOR 0x31
#define ACPI_END_DEPENDENT_DESCRIPTOR 0x38
#define ACPI_IO_PORT_DESCRIPTOR 0x47
#define ACPI_FIXED_LOCATION_IO_PORT_DESCRIPTOR 0x4B
#define ACPI_END_TAG_DESCRIPTOR 0x79
//
// Large Item Descriptor Value
//
#define ACPI_24_BIT_MEMORY_RANGE_DESCRIPTOR 0x81
#define ACPI_32_BIT_MEMORY_RANGE_DESCRIPTOR 0x85
#define ACPI_32_BIT_FIXED_MEMORY_RANGE_DESCRIPTOR 0x86
#define ACPI_DWORD_ADDRESS_SPACE_DESCRIPTOR 0x87
#define ACPI_WORD_ADDRESS_SPACE_DESCRIPTOR 0x88
#define ACPI_EXTENDED_INTERRUPT_DESCRIPTOR 0x89
#define ACPI_QWORD_ADDRESS_SPACE_DESCRIPTOR 0x8A
#define ACPI_ADDRESS_SPACE_DESCRIPTOR 0x8A
//
// Resource Type
//
#define ACPI_ADDRESS_SPACE_TYPE_MEM 0x00
#define ACPI_ADDRESS_SPACE_TYPE_IO 0x01
#define ACPI_ADDRESS_SPACE_TYPE_BUS 0x02
///
/// Power Management Timer frequency is fixed at 3.579545MHz.
///
#define ACPI_TIMER_FREQUENCY 3579545
//
// Ensure proper structure formats
//
#pragma pack(1)
///
/// The common definition of QWORD, DWORD, and WORD
/// Address Space Descriptors.
///
typedef PACKED struct {
UINT8 Desc;
UINT16 Len;
UINT8 ResType;
UINT8 GenFlag;
UINT8 SpecificFlag;
UINT64 AddrSpaceGranularity;
UINT64 AddrRangeMin;
UINT64 AddrRangeMax;
UINT64 AddrTranslationOffset;
UINT64 AddrLen;
} EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR;
typedef PACKED union {
UINT8 Byte;
PACKED struct {
UINT8 Length : 3;
UINT8 Name : 4;
UINT8 Type : 1;
} Bits;
} ACPI_SMALL_RESOURCE_HEADER;
typedef PACKED struct {
PACKED union {
UINT8 Byte;
PACKED struct {
UINT8 Name : 7;
UINT8 Type : 1;
}Bits;
} Header;
UINT16 Length;
} ACPI_LARGE_RESOURCE_HEADER;
///
/// IRQ Descriptor.
///
typedef PACKED struct {
ACPI_SMALL_RESOURCE_HEADER Header;
UINT16 Mask;
} EFI_ACPI_IRQ_NOFLAG_DESCRIPTOR;
///
/// IRQ Descriptor.
///
typedef PACKED struct {
ACPI_SMALL_RESOURCE_HEADER Header;
UINT16 Mask;
UINT8 Information;
} EFI_ACPI_IRQ_DESCRIPTOR;
///
/// DMA Descriptor.
///
typedef PACKED struct {
ACPI_SMALL_RESOURCE_HEADER Header;
UINT8 ChannelMask;
UINT8 Information;
} EFI_ACPI_DMA_DESCRIPTOR;
///
/// I/O Port Descriptor
///
typedef PACKED struct {
ACPI_SMALL_RESOURCE_HEADER Header;
UINT8 Information;
UINT16 BaseAddressMin;
UINT16 BaseAddressMax;
UINT8 Alignment;
UINT8 Length;
} EFI_ACPI_IO_PORT_DESCRIPTOR;
///
/// Fixed Location I/O Port Descriptor.
///
typedef PACKED struct {
ACPI_SMALL_RESOURCE_HEADER Header;
UINT16 BaseAddress;
UINT8 Length;
} EFI_ACPI_FIXED_LOCATION_IO_PORT_DESCRIPTOR;
///
/// 24-Bit Memory Range Descriptor
///
typedef PACKED struct {
ACPI_LARGE_RESOURCE_HEADER Header;
UINT8 Information;
UINT16 BaseAddressMin;
UINT16 BaseAddressMax;
UINT16 Alignment;
UINT16 Length;
} EFI_ACPI_24_BIT_MEMORY_RANGE_DESCRIPTOR;
///
/// 32-Bit Memory Range Descriptor
///
typedef PACKED struct {
ACPI_LARGE_RESOURCE_HEADER Header;
UINT8 Information;
UINT32 BaseAddressMin;
UINT32 BaseAddressMax;
UINT32 Alignment;
UINT32 Length;
} EFI_ACPI_32_BIT_MEMORY_RANGE_DESCRIPTOR;
///
/// Fixed 32-Bit Fixed Memory Range Descriptor
///
typedef PACKED struct {
ACPI_LARGE_RESOURCE_HEADER Header;
UINT8 Information;
UINT32 BaseAddress;
UINT32 Length;
} EFI_ACPI_32_BIT_FIXED_MEMORY_RANGE_DESCRIPTOR;
///
/// QWORD Address Space Descriptor
///
typedef PACKED struct {
ACPI_LARGE_RESOURCE_HEADER Header;
UINT8 ResType;
UINT8 GenFlag;
UINT8 SpecificFlag;
UINT64 AddrSpaceGranularity;
UINT64 AddrRangeMin;
UINT64 AddrRangeMax;
UINT64 AddrTranslationOffset;
UINT64 AddrLen;
} EFI_ACPI_QWORD_ADDRESS_SPACE_DESCRIPTOR;
///
/// DWORD Address Space Descriptor
///
typedef PACKED struct {
ACPI_LARGE_RESOURCE_HEADER Header;
UINT8 ResType;
UINT8 GenFlag;
UINT8 SpecificFlag;
UINT32 AddrSpaceGranularity;
UINT32 AddrRangeMin;
UINT32 AddrRangeMax;
UINT32 AddrTranslationOffset;
UINT32 AddrLen;
} EFI_ACPI_DWORD_ADDRESS_SPACE_DESCRIPTOR;
///
/// WORD Address Space Descriptor
///
typedef PACKED struct {
ACPI_LARGE_RESOURCE_HEADER Header;
UINT8 ResType;
UINT8 GenFlag;
UINT8 SpecificFlag;
UINT16 AddrSpaceGranularity;
UINT16 AddrRangeMin;
UINT16 AddrRangeMax;
UINT16 AddrTranslationOffset;
UINT16 AddrLen;
} EFI_ACPI_WORD_ADDRESS_SPACE_DESCRIPTOR;
///
/// Extended Interrupt Descriptor
///
typedef PACKED struct {
ACPI_LARGE_RESOURCE_HEADER Header;
UINT8 InterruptVectorFlags;
UINT8 InterruptTableLength;
UINT32 InterruptNumber[1];
} EFI_ACPI_EXTENDED_INTERRUPT_DESCRIPTOR;
#pragma pack()
///
/// The End tag identifies an end of resource data.
///
typedef struct {
UINT8 Desc;
UINT8 Checksum;
} EFI_ACPI_END_TAG_DESCRIPTOR;
//
// General use definitions
//
#define EFI_ACPI_RESERVED_BYTE 0x00
#define EFI_ACPI_RESERVED_WORD 0x0000
#define EFI_ACPI_RESERVED_DWORD 0x00000000
#define EFI_ACPI_RESERVED_QWORD 0x0000000000000000
//
// Resource Type Specific Flags
// Ref ACPI specification 6.4.3.5.5
//
// Bit [0] : Write Status, _RW
//
#define EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_READ_WRITE (1 << 0)
#define EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_READ_ONLY (0 << 0)
//
// Bit [2:1] : Memory Attributes, _MEM
//
#define EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_NON_CACHEABLE (0 << 1)
#define EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE (1 << 1)
#define EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_WRITE_COMBINING (2 << 1)
#define EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE (3 << 1)
//
// Bit [4:3] : Memory Attributes, _MTP
//
#define EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_ADDRESS_RANGE_MEMORY (0 << 3)
#define EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_ADDRESS_RANGE_RESERVED (1 << 3)
#define EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_ADDRESS_RANGE_ACPI (2 << 3)
#define EFI_APCI_MEMORY_RESOURCE_SPECIFIC_FLAG_ADDRESS_RANGE_NVS (3 << 3)
//
// Bit [5] : Memory to I/O Translation, _TTP
//
#define EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_TYPE_TRANSLATION (1 << 5)
#define EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_TYPE_STATIC (0 << 5)
//
// IRQ Information
// Ref ACPI specification 6.4.2.1
//
#define EFI_ACPI_IRQ_SHARABLE_MASK 0x10
#define EFI_ACPI_IRQ_SHARABLE 0x10
#define EFI_ACPI_IRQ_POLARITY_MASK 0x08
#define EFI_ACPI_IRQ_HIGH_TRUE 0x00
#define EFI_ACPI_IRQ_LOW_FALSE 0x08
#define EFI_ACPI_IRQ_MODE 0x01
#define EFI_ACPI_IRQ_LEVEL_TRIGGERED 0x00
#define EFI_ACPI_IRQ_EDGE_TRIGGERED 0x01
//
// DMA Information
// Ref ACPI specification 6.4.2.2
//
#define EFI_ACPI_DMA_SPEED_TYPE_MASK 0x60
#define EFI_ACPI_DMA_SPEED_TYPE_COMPATIBILITY 0x00
#define EFI_ACPI_DMA_SPEED_TYPE_A 0x20
#define EFI_ACPI_DMA_SPEED_TYPE_B 0x40
#define EFI_ACPI_DMA_SPEED_TYPE_F 0x60
#define EFI_ACPI_DMA_BUS_MASTER_MASK 0x04
#define EFI_ACPI_DMA_BUS_MASTER 0x04
#define EFI_ACPI_DMA_TRANSFER_TYPE_MASK 0x03
#define EFI_ACPI_DMA_TRANSFER_TYPE_8_BIT 0x00
#define EFI_ACPI_DMA_TRANSFER_TYPE_8_BIT_AND_16_BIT 0x01
#define EFI_ACPI_DMA_TRANSFER_TYPE_16_BIT 0x02
//
// IO Information
// Ref ACPI specification 6.4.2.5
//
#define EFI_ACPI_IO_DECODE_MASK 0x01
#define EFI_ACPI_IO_DECODE_16_BIT 0x01
#define EFI_ACPI_IO_DECODE_10_BIT 0x00
//
// Memory Information
// Ref ACPI specification 6.4.3.4
//
#define EFI_ACPI_MEMORY_WRITE_STATUS_MASK 0x01
#define EFI_ACPI_MEMORY_WRITABLE 0x01
#define EFI_ACPI_MEMORY_NON_WRITABLE 0x00
//
// Interrupt Vector Flags definitions for Extended Interrupt Descriptor
// Ref ACPI specification 6.4.3.6
//
#define EFI_ACPI_EXTENDED_INTERRUPT_FLAG_PRODUCER_CONSUMER_MASK BIT0
#define EFI_ACPI_EXTENDED_INTERRUPT_FLAG_MODE_MASK BIT1
#define EFI_ACPI_EXTENDED_INTERRUPT_FLAG_POLARITY_MASK BIT2
#define EFI_ACPI_EXTENDED_INTERRUPT_FLAG_SHARABLE_MASK BIT3
#define EFI_ACPI_EXTENDED_INTERRUPT_FLAG_WAKE_CAPABLITY_MASK BIT4
//
// Ensure proper structure formats
//
#pragma pack(1)
//
// ACPI 1.0b table structures
//
///
/// Root System Description Pointer Structure.
///
typedef struct {
UINT64 Signature;
UINT8 Checksum;
UINT8 OemId[6];
UINT8 Reserved;
UINT32 RsdtAddress;
} EFI_ACPI_1_0_ROOT_SYSTEM_DESCRIPTION_POINTER;
//
// Root System Description Table
// No definition needed as it is a common description table header, the same with
// EFI_ACPI_DESCRIPTION_HEADER, followed by a variable number of UINT32 table pointers.
//
///
/// RSDT Revision (as defined in ACPI 1.0b specification).
///
#define EFI_ACPI_1_0_ROOT_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01
///
/// Fixed ACPI Description Table Structure (FADT).
///
typedef struct {
EFI_ACPI_DESCRIPTION_HEADER Header;
UINT32 FirmwareCtrl;
UINT32 Dsdt;
UINT8 IntModel;
UINT8 Reserved1;
UINT16 SciInt;
UINT32 SmiCmd;
UINT8 AcpiEnable;
UINT8 AcpiDisable;
UINT8 S4BiosReq;
UINT8 Reserved2;
UINT32 Pm1aEvtBlk;
UINT32 Pm1bEvtBlk;
UINT32 Pm1aCntBlk;
UINT32 Pm1bCntBlk;
UINT32 Pm2CntBlk;
UINT32 PmTmrBlk;
UINT32 Gpe0Blk;
UINT32 Gpe1Blk;
UINT8 Pm1EvtLen;
UINT8 Pm1CntLen;
UINT8 Pm2CntLen;
UINT8 PmTmLen;
UINT8 Gpe0BlkLen;
UINT8 Gpe1BlkLen;
UINT8 Gpe1Base;
UINT8 Reserved3;
UINT16 PLvl2Lat;
UINT16 PLvl3Lat;
UINT16 FlushSize;
UINT16 FlushStride;
UINT8 DutyOffset;
UINT8 DutyWidth;
UINT8 DayAlrm;
UINT8 MonAlrm;
UINT8 Century;
UINT8 Reserved4;
UINT8 Reserved5;
UINT8 Reserved6;
UINT32 Flags;
} EFI_ACPI_1_0_FIXED_ACPI_DESCRIPTION_TABLE;
///
/// FADT Version (as defined in ACPI 1.0b specification).
///
#define EFI_ACPI_1_0_FIXED_ACPI_DESCRIPTION_TABLE_REVISION 0x01
#define EFI_ACPI_1_0_INT_MODE_DUAL_PIC 0
#define EFI_ACPI_1_0_INT_MODE_MULTIPLE_APIC 1
//
// Fixed ACPI Description Table Fixed Feature Flags
// All other bits are reserved and must be set to 0.
//
#define EFI_ACPI_1_0_WBINVD BIT0
#define EFI_ACPI_1_0_WBINVD_FLUSH BIT1
#define EFI_ACPI_1_0_PROC_C1 BIT2
#define EFI_ACPI_1_0_P_LVL2_UP BIT3
#define EFI_ACPI_1_0_PWR_BUTTON BIT4
#define EFI_ACPI_1_0_SLP_BUTTON BIT5
#define EFI_ACPI_1_0_FIX_RTC BIT6
#define EFI_ACPI_1_0_RTC_S4 BIT7
#define EFI_ACPI_1_0_TMR_VAL_EXT BIT8
#define EFI_ACPI_1_0_DCK_CAP BIT9
///
/// Firmware ACPI Control Structure.
///
typedef struct {
UINT32 Signature;
UINT32 Length;
UINT32 HardwareSignature;
UINT32 FirmwareWakingVector;
UINT32 GlobalLock;
UINT32 Flags;
UINT8 Reserved[40];
} EFI_ACPI_1_0_FIRMWARE_ACPI_CONTROL_STRUCTURE;
///
/// Firmware Control Structure Feature Flags.
/// All other bits are reserved and must be set to 0.
///
#define EFI_ACPI_1_0_S4BIOS_F BIT0
///
/// Multiple APIC Description Table header definition. The rest of the table
/// must be defined in a platform-specific manner.
///
typedef struct {
EFI_ACPI_DESCRIPTION_HEADER Header;
UINT32 LocalApicAddress;
UINT32 Flags;
} EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER;
///
/// MADT Revision (as defined in ACPI 1.0b specification).
///
#define EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION 0x01
///
/// Multiple APIC Flags
/// All other bits are reserved and must be set to 0.
///
#define EFI_ACPI_1_0_PCAT_COMPAT BIT0
//
// Multiple APIC Description Table APIC structure types
// All other values between 0x05 an 0xFF are reserved and
// will be ignored by OSPM.
//
#define EFI_ACPI_1_0_PROCESSOR_LOCAL_APIC 0x00
#define EFI_ACPI_1_0_IO_APIC 0x01
#define EFI_ACPI_1_0_INTERRUPT_SOURCE_OVERRIDE 0x02
#define EFI_ACPI_1_0_NON_MASKABLE_INTERRUPT_SOURCE 0x03
#define EFI_ACPI_1_0_LOCAL_APIC_NMI 0x04
//
// APIC Structure Definitions
//
///
/// Processor Local APIC Structure Definition.
///
typedef struct {
UINT8 Type;
UINT8 Length;
UINT8 AcpiProcessorId;
UINT8 ApicId;
UINT32 Flags;
} EFI_ACPI_1_0_PROCESSOR_LOCAL_APIC_STRUCTURE;
///
/// Local APIC Flags. All other bits are reserved and must be 0.
///
#define EFI_ACPI_1_0_LOCAL_APIC_ENABLED BIT0
///
/// IO APIC Structure.
///
typedef struct {
UINT8 Type;
UINT8 Length;
UINT8 IoApicId;
UINT8 Reserved;
UINT32 IoApicAddress;
UINT32 SystemVectorBase;
} EFI_ACPI_1_0_IO_APIC_STRUCTURE;
///
/// Interrupt Source Override Structure.
///
typedef struct {
UINT8 Type;
UINT8 Length;
UINT8 Bus;
UINT8 Source;
UINT32 GlobalSystemInterruptVector;
UINT16 Flags;
} EFI_ACPI_1_0_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE;
///
/// Non-Maskable Interrupt Source Structure.
///
typedef struct {
UINT8 Type;
UINT8 Length;
UINT16 Flags;
UINT32 GlobalSystemInterruptVector;
} EFI_ACPI_1_0_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE;
///
/// Local APIC NMI Structure.
///
typedef struct {
UINT8 Type;
UINT8 Length;
UINT8 AcpiProcessorId;
UINT16 Flags;
UINT8 LocalApicInti;
} EFI_ACPI_1_0_LOCAL_APIC_NMI_STRUCTURE;
///
/// Smart Battery Description Table (SBST)
///
typedef struct {
EFI_ACPI_DESCRIPTION_HEADER Header;
UINT32 WarningEnergyLevel;
UINT32 LowEnergyLevel;
UINT32 CriticalEnergyLevel;
} EFI_ACPI_1_0_SMART_BATTERY_DESCRIPTION_TABLE;
//
// Known table signatures
//
///
/// "RSD PTR " Root System Description Pointer.
///
#define EFI_ACPI_1_0_ROOT_SYSTEM_DESCRIPTION_POINTER_SIGNATURE SIGNATURE_64('R', 'S', 'D', ' ', 'P', 'T', 'R', ' ')
///
/// "APIC" Multiple APIC Description Table.
///
#define EFI_ACPI_1_0_APIC_SIGNATURE SIGNATURE_32('A', 'P', 'I', 'C')
///
/// "DSDT" Differentiated System Description Table.
///
#define EFI_ACPI_1_0_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('D', 'S', 'D', 'T')
///
/// "FACS" Firmware ACPI Control Structure.
///
#define EFI_ACPI_1_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_SIGNATURE SIGNATURE_32('F', 'A', 'C', 'S')
///
/// "FACP" Fixed ACPI Description Table.
///
#define EFI_ACPI_1_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('F', 'A', 'C', 'P')
///
/// "PSDT" Persistent System Description Table.
///
#define EFI_ACPI_1_0_PERSISTENT_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('P', 'S', 'D', 'T')
///
/// "RSDT" Root System Description Table.
///
#define EFI_ACPI_1_0_ROOT_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('R', 'S', 'D', 'T')
///
/// "SBST" Smart Battery Specification Table.
///
#define EFI_ACPI_1_0_SMART_BATTERY_SPECIFICATION_TABLE_SIGNATURE SIGNATURE_32('S', 'B', 'S', 'T')
///
/// "SSDT" Secondary System Description Table.
///
#define EFI_ACPI_1_0_SECONDARY_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('S', 'S', 'D', 'T')
#pragma pack()
#endif

539
src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/Acpi20.h Normal file
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@@ -0,0 +1,539 @@
/** @file
ACPI 2.0 definitions from the ACPI Specification, revision 2.0
Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef _ACPI_2_0_H_
#define _ACPI_2_0_H_
#include <IndustryStandard/Acpi10.h>
//
// Define for Descriptor
//
#define ACPI_LARGE_GENERIC_REGISTER_DESCRIPTOR_NAME 0x02
#define ACPI_GENERIC_REGISTER_DESCRIPTOR 0x82
//
// Ensure proper structure formats
//
#pragma pack(1)
///
/// Generic Register Descriptor
///
typedef PACKED struct {
ACPI_LARGE_RESOURCE_HEADER Header;
UINT8 AddressSpaceId;
UINT8 RegisterBitWidth;
UINT8 RegisterBitOffset;
UINT8 AddressSize;
UINT64 RegisterAddress;
} EFI_ACPI_GENERIC_REGISTER_DESCRIPTOR;
#pragma pack()
//
// Ensure proper structure formats
//
#pragma pack(1)
///
/// ACPI 2.0 Generic Address Space definition
///
typedef struct {
UINT8 AddressSpaceId;
UINT8 RegisterBitWidth;
UINT8 RegisterBitOffset;
UINT8 Reserved;
UINT64 Address;
} EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE;
//
// Generic Address Space Address IDs
//
#define EFI_ACPI_2_0_SYSTEM_MEMORY 0
#define EFI_ACPI_2_0_SYSTEM_IO 1
#define EFI_ACPI_2_0_PCI_CONFIGURATION_SPACE 2
#define EFI_ACPI_2_0_EMBEDDED_CONTROLLER 3
#define EFI_ACPI_2_0_SMBUS 4
#define EFI_ACPI_2_0_FUNCTIONAL_FIXED_HARDWARE 0x7F
//
// ACPI 2.0 table structures
//
///
/// Root System Description Pointer Structure
///
typedef struct {
UINT64 Signature;
UINT8 Checksum;
UINT8 OemId[6];
UINT8 Revision;
UINT32 RsdtAddress;
UINT32 Length;
UINT64 XsdtAddress;
UINT8 ExtendedChecksum;
UINT8 Reserved[3];
} EFI_ACPI_2_0_ROOT_SYSTEM_DESCRIPTION_POINTER;
///
/// RSD_PTR Revision (as defined in ACPI 2.0 spec.)
///
#define EFI_ACPI_2_0_ROOT_SYSTEM_DESCRIPTION_POINTER_REVISION 0x02
///
/// Common table header, this prefaces all ACPI tables, including FACS, but
/// excluding the RSD PTR structure
///
typedef struct {
UINT32 Signature;
UINT32 Length;
} EFI_ACPI_2_0_COMMON_HEADER;
//
// Root System Description Table
// No definition needed as it is a common description table header, the same with
// EFI_ACPI_DESCRIPTION_HEADER, followed by a variable number of UINT32 table pointers.
//
///
/// RSDT Revision (as defined in ACPI 2.0 spec.)
///
#define EFI_ACPI_2_0_ROOT_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01
//
// Extended System Description Table
// No definition needed as it is a common description table header, the same with
// EFI_ACPI_DESCRIPTION_HEADER, followed by a variable number of UINT64 table pointers.
//
///
/// XSDT Revision (as defined in ACPI 2.0 spec.)
///
#define EFI_ACPI_2_0_EXTENDED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01
///
/// Fixed ACPI Description Table Structure (FADT)
///
typedef struct {
EFI_ACPI_DESCRIPTION_HEADER Header;
UINT32 FirmwareCtrl;
UINT32 Dsdt;
UINT8 Reserved0;
UINT8 PreferredPmProfile;
UINT16 SciInt;
UINT32 SmiCmd;
UINT8 AcpiEnable;
UINT8 AcpiDisable;
UINT8 S4BiosReq;
UINT8 PstateCnt;
UINT32 Pm1aEvtBlk;
UINT32 Pm1bEvtBlk;
UINT32 Pm1aCntBlk;
UINT32 Pm1bCntBlk;
UINT32 Pm2CntBlk;
UINT32 PmTmrBlk;
UINT32 Gpe0Blk;
UINT32 Gpe1Blk;
UINT8 Pm1EvtLen;
UINT8 Pm1CntLen;
UINT8 Pm2CntLen;
UINT8 PmTmrLen;
UINT8 Gpe0BlkLen;
UINT8 Gpe1BlkLen;
UINT8 Gpe1Base;
UINT8 CstCnt;
UINT16 PLvl2Lat;
UINT16 PLvl3Lat;
UINT16 FlushSize;
UINT16 FlushStride;
UINT8 DutyOffset;
UINT8 DutyWidth;
UINT8 DayAlrm;
UINT8 MonAlrm;
UINT8 Century;
UINT16 IaPcBootArch;
UINT8 Reserved1;
UINT32 Flags;
EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE ResetReg;
UINT8 ResetValue;
UINT8 Reserved2[3];
UINT64 XFirmwareCtrl;
UINT64 XDsdt;
EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE XPm1aEvtBlk;
EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE XPm1bEvtBlk;
EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE XPm1aCntBlk;
EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE XPm1bCntBlk;
EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE XPm2CntBlk;
EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE XPmTmrBlk;
EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE XGpe0Blk;
EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE XGpe1Blk;
} EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE;
///
/// FADT Version (as defined in ACPI 2.0 spec.)
///
#define EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE_REVISION 0x03
//
// Fixed ACPI Description Table Preferred Power Management Profile
//
#define EFI_ACPI_2_0_PM_PROFILE_UNSPECIFIED 0
#define EFI_ACPI_2_0_PM_PROFILE_DESKTOP 1
#define EFI_ACPI_2_0_PM_PROFILE_MOBILE 2
#define EFI_ACPI_2_0_PM_PROFILE_WORKSTATION 3
#define EFI_ACPI_2_0_PM_PROFILE_ENTERPRISE_SERVER 4
#define EFI_ACPI_2_0_PM_PROFILE_SOHO_SERVER 5
#define EFI_ACPI_2_0_PM_PROFILE_APPLIANCE_PC 6
//
// Fixed ACPI Description Table Boot Architecture Flags
// All other bits are reserved and must be set to 0.
//
#define EFI_ACPI_2_0_LEGACY_DEVICES BIT0
#define EFI_ACPI_2_0_8042 BIT1
//
// Fixed ACPI Description Table Fixed Feature Flags
// All other bits are reserved and must be set to 0.
//
#define EFI_ACPI_2_0_WBINVD BIT0
#define EFI_ACPI_2_0_WBINVD_FLUSH BIT1
#define EFI_ACPI_2_0_PROC_C1 BIT2
#define EFI_ACPI_2_0_P_LVL2_UP BIT3
#define EFI_ACPI_2_0_PWR_BUTTON BIT4
#define EFI_ACPI_2_0_SLP_BUTTON BIT5
#define EFI_ACPI_2_0_FIX_RTC BIT6
#define EFI_ACPI_2_0_RTC_S4 BIT7
#define EFI_ACPI_2_0_TMR_VAL_EXT BIT8
#define EFI_ACPI_2_0_DCK_CAP BIT9
#define EFI_ACPI_2_0_RESET_REG_SUP BIT10
#define EFI_ACPI_2_0_SEALED_CASE BIT11
#define EFI_ACPI_2_0_HEADLESS BIT12
#define EFI_ACPI_2_0_CPU_SW_SLP BIT13
///
/// Firmware ACPI Control Structure
///
typedef struct {
UINT32 Signature;
UINT32 Length;
UINT32 HardwareSignature;
UINT32 FirmwareWakingVector;
UINT32 GlobalLock;
UINT32 Flags;
UINT64 XFirmwareWakingVector;
UINT8 Version;
UINT8 Reserved[31];
} EFI_ACPI_2_0_FIRMWARE_ACPI_CONTROL_STRUCTURE;
///
/// FACS Version (as defined in ACPI 2.0 spec.)
///
#define EFI_ACPI_2_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_VERSION 0x01
///
/// Firmware Control Structure Feature Flags
/// All other bits are reserved and must be set to 0.
///
#define EFI_ACPI_2_0_S4BIOS_F BIT0
///
/// Multiple APIC Description Table header definition. The rest of the table
/// must be defined in a platform specific manner.
///
typedef struct {
EFI_ACPI_DESCRIPTION_HEADER Header;
UINT32 LocalApicAddress;
UINT32 Flags;
} EFI_ACPI_2_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER;
///
/// MADT Revision (as defined in ACPI 2.0 spec.)
///
#define EFI_ACPI_2_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION 0x01
///
/// Multiple APIC Flags
/// All other bits are reserved and must be set to 0.
///
#define EFI_ACPI_2_0_PCAT_COMPAT BIT0
//
// Multiple APIC Description Table APIC structure types
// All other values between 0x09 an 0xFF are reserved and
// will be ignored by OSPM.
//
#define EFI_ACPI_2_0_PROCESSOR_LOCAL_APIC 0x00
#define EFI_ACPI_2_0_IO_APIC 0x01
#define EFI_ACPI_2_0_INTERRUPT_SOURCE_OVERRIDE 0x02
#define EFI_ACPI_2_0_NON_MASKABLE_INTERRUPT_SOURCE 0x03
#define EFI_ACPI_2_0_LOCAL_APIC_NMI 0x04
#define EFI_ACPI_2_0_LOCAL_APIC_ADDRESS_OVERRIDE 0x05
#define EFI_ACPI_2_0_IO_SAPIC 0x06
#define EFI_ACPI_2_0_PROCESSOR_LOCAL_SAPIC 0x07
#define EFI_ACPI_2_0_PLATFORM_INTERRUPT_SOURCES 0x08
//
// APIC Structure Definitions
//
///
/// Processor Local APIC Structure Definition
///
typedef struct {
UINT8 Type;
UINT8 Length;
UINT8 AcpiProcessorId;
UINT8 ApicId;
UINT32 Flags;
} EFI_ACPI_2_0_PROCESSOR_LOCAL_APIC_STRUCTURE;
///
/// Local APIC Flags. All other bits are reserved and must be 0.
///
#define EFI_ACPI_2_0_LOCAL_APIC_ENABLED BIT0
///
/// IO APIC Structure
///
typedef struct {
UINT8 Type;
UINT8 Length;
UINT8 IoApicId;
UINT8 Reserved;
UINT32 IoApicAddress;
UINT32 GlobalSystemInterruptBase;
} EFI_ACPI_2_0_IO_APIC_STRUCTURE;
///
/// Interrupt Source Override Structure
///
typedef struct {
UINT8 Type;
UINT8 Length;
UINT8 Bus;
UINT8 Source;
UINT32 GlobalSystemInterrupt;
UINT16 Flags;
} EFI_ACPI_2_0_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE;
///
/// Non-Maskable Interrupt Source Structure
///
typedef struct {
UINT8 Type;
UINT8 Length;
UINT16 Flags;
UINT32 GlobalSystemInterrupt;
} EFI_ACPI_2_0_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE;
///
/// Local APIC NMI Structure
///
typedef struct {
UINT8 Type;
UINT8 Length;
UINT8 AcpiProcessorId;
UINT16 Flags;
UINT8 LocalApicLint;
} EFI_ACPI_2_0_LOCAL_APIC_NMI_STRUCTURE;
///
/// Local APIC Address Override Structure
///
typedef struct {
UINT8 Type;
UINT8 Length;
UINT16 Reserved;
UINT64 LocalApicAddress;
} EFI_ACPI_2_0_LOCAL_APIC_ADDRESS_OVERRIDE_STRUCTURE;
///
/// IO SAPIC Structure
///
typedef struct {
UINT8 Type;
UINT8 Length;
UINT8 IoApicId;
UINT8 Reserved;
UINT32 GlobalSystemInterruptBase;
UINT64 IoSapicAddress;
} EFI_ACPI_2_0_IO_SAPIC_STRUCTURE;
///
/// Local SAPIC Structure
///
typedef struct {
UINT8 Type;
UINT8 Length;
UINT8 AcpiProcessorId;
UINT8 LocalSapicId;
UINT8 LocalSapicEid;
UINT8 Reserved[3];
UINT32 Flags;
} EFI_ACPI_2_0_PROCESSOR_LOCAL_SAPIC_STRUCTURE;
///
/// Platform Interrupt Sources Structure
///
typedef struct {
UINT8 Type;
UINT8 Length;
UINT16 Flags;
UINT8 InterruptType;
UINT8 ProcessorId;
UINT8 ProcessorEid;
UINT8 IoSapicVector;
UINT32 GlobalSystemInterrupt;
UINT32 Reserved;
} EFI_ACPI_2_0_PLATFORM_INTERRUPT_SOURCES_STRUCTURE;
///
/// Smart Battery Description Table (SBST)
///
typedef struct {
EFI_ACPI_DESCRIPTION_HEADER Header;
UINT32 WarningEnergyLevel;
UINT32 LowEnergyLevel;
UINT32 CriticalEnergyLevel;
} EFI_ACPI_2_0_SMART_BATTERY_DESCRIPTION_TABLE;
///
/// SBST Version (as defined in ACPI 2.0 spec.)
///
#define EFI_ACPI_2_0_SMART_BATTERY_DESCRIPTION_TABLE_REVISION 0x01
///
/// Embedded Controller Boot Resources Table (ECDT)
/// The table is followed by a null terminated ASCII string that contains
/// a fully qualified reference to the name space object.
///
typedef struct {
EFI_ACPI_DESCRIPTION_HEADER Header;
EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE EcControl;
EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE EcData;
UINT32 Uid;
UINT8 GpeBit;
} EFI_ACPI_2_0_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE;
///
/// ECDT Version (as defined in ACPI 2.0 spec.)
///
#define EFI_ACPI_2_0_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE_REVISION 0x01
//
// Known table signatures
//
///
/// "RSD PTR " Root System Description Pointer
///
#define EFI_ACPI_2_0_ROOT_SYSTEM_DESCRIPTION_POINTER_SIGNATURE SIGNATURE_64('R', 'S', 'D', ' ', 'P', 'T', 'R', ' ')
///
/// "SPIC" Multiple SAPIC Description Table
///
/// BUGBUG: Don't know where this came from except SR870BN4 uses it.
/// #define EFI_ACPI_2_0_MULTIPLE_SAPIC_DESCRIPTION_TABLE_SIGNATURE 0x43495053
///
#define EFI_ACPI_2_0_MULTIPLE_SAPIC_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('A', 'P', 'I', 'C')
///
/// "BOOT" MS Simple Boot Spec
///
#define EFI_ACPI_2_0_SIMPLE_BOOT_FLAG_TABLE_SIGNATURE SIGNATURE_32('B', 'O', 'O', 'T')
///
/// "DBGP" MS Bebug Port Spec
///
#define EFI_ACPI_2_0_DEBUG_PORT_TABLE_SIGNATURE SIGNATURE_32('D', 'B', 'G', 'P')
///
/// "DSDT" Differentiated System Description Table
///
#define EFI_ACPI_2_0_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('D', 'S', 'D', 'T')
///
/// "ECDT" Embedded Controller Boot Resources Table
///
#define EFI_ACPI_2_0_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE_SIGNATURE SIGNATURE_32('E', 'C', 'D', 'T')
///
/// "ETDT" Event Timer Description Table
///
#define EFI_ACPI_2_0_EVENT_TIMER_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('E', 'T', 'D', 'T')
///
/// "FACS" Firmware ACPI Control Structure
///
#define EFI_ACPI_2_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_SIGNATURE SIGNATURE_32('F', 'A', 'C', 'S')
///
/// "FACP" Fixed ACPI Description Table
///
#define EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('F', 'A', 'C', 'P')
///
/// "APIC" Multiple APIC Description Table
///
#define EFI_ACPI_2_0_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('A', 'P', 'I', 'C')
///
/// "PSDT" Persistent System Description Table
///
#define EFI_ACPI_2_0_PERSISTENT_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('P', 'S', 'D', 'T')
///
/// "RSDT" Root System Description Table
///
#define EFI_ACPI_2_0_ROOT_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('R', 'S', 'D', 'T')
///
/// "SBST" Smart Battery Specification Table
///
#define EFI_ACPI_2_0_SMART_BATTERY_SPECIFICATION_TABLE_SIGNATURE SIGNATURE_32('S', 'B', 'S', 'T')
///
/// "SLIT" System Locality Information Table
///
#define EFI_ACPI_2_0_SYSTEM_LOCALITY_INFORMATION_TABLE_SIGNATURE SIGNATURE_32('S', 'L', 'I', 'T')
///
/// "SPCR" Serial Port Console Redirection Table
///
#define EFI_ACPI_2_0_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE SIGNATURE_32('S', 'P', 'C', 'R')
///
/// "SRAT" Static Resource Affinity Table
///
#define EFI_ACPI_2_0_STATIC_RESOURCE_AFFINITY_TABLE_SIGNATURE SIGNATURE_32('S', 'R', 'A', 'T')
///
/// "SSDT" Secondary System Description Table
///
#define EFI_ACPI_2_0_SECONDARY_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('S', 'S', 'D', 'T')
///
/// "SPMI" Server Platform Management Interface Table
///
#define EFI_ACPI_2_0_SERVER_PLATFORM_MANAGEMENT_INTERFACE_SIGNATURE SIGNATURE_32('S', 'P', 'M', 'I')
///
/// "XSDT" Extended System Description Table
///
#define EFI_ACPI_2_0_EXTENDED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('X', 'S', 'D', 'T')
///
/// "MCFG" PCI Express Memory Mapped Configuration Space Base Address Description Table
///
#define EFI_ACPI_2_0_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE_SIGNATURE SIGNATURE_32('M', 'C', 'F', 'G')
#pragma pack()
#endif

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src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/Acpi30.h Normal file
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/** @file
ACPI 3.0 definitions from the ACPI Specification Revision 3.0b October 10, 2006
Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef _ACPI_3_0_H_
#define _ACPI_3_0_H_
#include <IndustryStandard/Acpi20.h>
//
// Define for Descriptor
//
#define ACPI_LARGE_EXTENDED_ADDRESS_SPACE_DESCRIPTOR_NAME 0x0B
#define ACPI_EXTENDED_ADDRESS_SPACE_DESCRIPTOR 0x8B
//
// Ensure proper structure formats
//
#pragma pack(1)
///
/// Extended Address Space Descriptor
///
typedef PACKED struct {
ACPI_LARGE_RESOURCE_HEADER Header;
UINT8 ResType;
UINT8 GenFlag;
UINT8 SpecificFlag;
UINT8 RevisionId;
UINT8 Reserved;
UINT64 AddrSpaceGranularity;
UINT64 AddrRangeMin;
UINT64 AddrRangeMax;
UINT64 AddrTranslationOffset;
UINT64 AddrLen;
UINT64 TypeSpecificAttribute;
} EFI_ACPI_EXTENDED_ADDRESS_SPACE_DESCRIPTOR;
#pragma pack()
//
// Memory Type Specific Flags
//
#define EFI_ACPI_MEMORY_TYPE_SPECIFIC_ATTRIBUTES_UC 0x0000000000000001
#define EFI_ACPI_MEMORY_TYPE_SPECIFIC_ATTRIBUTES_WC 0x0000000000000002
#define EFI_ACPI_MEMORY_TYPE_SPECIFIC_ATTRIBUTES_WT 0x0000000000000004
#define EFI_ACPI_MEMORY_TYPE_SPECIFIC_ATTRIBUTES_WB 0x0000000000000008
#define EFI_ACPI_MEMORY_TYPE_SPECIFIC_ATTRIBUTES_UCE 0x0000000000000010
#define EFI_ACPI_MEMORY_TYPE_SPECIFIC_ATTRIBUTES_NV 0x0000000000008000
//
// Ensure proper structure formats
//
#pragma pack(1)
///
/// ACPI 3.0 Generic Address Space definition
///
typedef struct {
UINT8 AddressSpaceId;
UINT8 RegisterBitWidth;
UINT8 RegisterBitOffset;
UINT8 AccessSize;
UINT64 Address;
} EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE;
//
// Generic Address Space Address IDs
//
#define EFI_ACPI_3_0_SYSTEM_MEMORY 0
#define EFI_ACPI_3_0_SYSTEM_IO 1
#define EFI_ACPI_3_0_PCI_CONFIGURATION_SPACE 2
#define EFI_ACPI_3_0_EMBEDDED_CONTROLLER 3
#define EFI_ACPI_3_0_SMBUS 4
#define EFI_ACPI_3_0_FUNCTIONAL_FIXED_HARDWARE 0x7F
//
// Generic Address Space Access Sizes
//
#define EFI_ACPI_3_0_UNDEFINED 0
#define EFI_ACPI_3_0_BYTE 1
#define EFI_ACPI_3_0_WORD 2
#define EFI_ACPI_3_0_DWORD 3
#define EFI_ACPI_3_0_QWORD 4
//
// ACPI 3.0 table structures
//
///
/// Root System Description Pointer Structure
///
typedef struct {
UINT64 Signature;
UINT8 Checksum;
UINT8 OemId[6];
UINT8 Revision;
UINT32 RsdtAddress;
UINT32 Length;
UINT64 XsdtAddress;
UINT8 ExtendedChecksum;
UINT8 Reserved[3];
} EFI_ACPI_3_0_ROOT_SYSTEM_DESCRIPTION_POINTER;
///
/// RSD_PTR Revision (as defined in ACPI 3.0b spec.)
///
#define EFI_ACPI_3_0_ROOT_SYSTEM_DESCRIPTION_POINTER_REVISION 0x02 ///< ACPISpec (Revision 3.0b) says current value is 2
///
/// Common table header, this prefaces all ACPI tables, including FACS, but
/// excluding the RSD PTR structure
///
typedef struct {
UINT32 Signature;
UINT32 Length;
} EFI_ACPI_3_0_COMMON_HEADER;
//
// Root System Description Table
// No definition needed as it is a common description table header, the same with
// EFI_ACPI_DESCRIPTION_HEADER, followed by a variable number of UINT32 table pointers.
//
///
/// RSDT Revision (as defined in ACPI 3.0 spec.)
///
#define EFI_ACPI_3_0_ROOT_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01
//
// Extended System Description Table
// No definition needed as it is a common description table header, the same with
// EFI_ACPI_DESCRIPTION_HEADER, followed by a variable number of UINT64 table pointers.
//
///
/// XSDT Revision (as defined in ACPI 3.0 spec.)
///
#define EFI_ACPI_3_0_EXTENDED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01
///
/// Fixed ACPI Description Table Structure (FADT)
///
typedef struct {
EFI_ACPI_DESCRIPTION_HEADER Header;
UINT32 FirmwareCtrl;
UINT32 Dsdt;
UINT8 Reserved0;
UINT8 PreferredPmProfile;
UINT16 SciInt;
UINT32 SmiCmd;
UINT8 AcpiEnable;
UINT8 AcpiDisable;
UINT8 S4BiosReq;
UINT8 PstateCnt;
UINT32 Pm1aEvtBlk;
UINT32 Pm1bEvtBlk;
UINT32 Pm1aCntBlk;
UINT32 Pm1bCntBlk;
UINT32 Pm2CntBlk;
UINT32 PmTmrBlk;
UINT32 Gpe0Blk;
UINT32 Gpe1Blk;
UINT8 Pm1EvtLen;
UINT8 Pm1CntLen;
UINT8 Pm2CntLen;
UINT8 PmTmrLen;
UINT8 Gpe0BlkLen;
UINT8 Gpe1BlkLen;
UINT8 Gpe1Base;
UINT8 CstCnt;
UINT16 PLvl2Lat;
UINT16 PLvl3Lat;
UINT16 FlushSize;
UINT16 FlushStride;
UINT8 DutyOffset;
UINT8 DutyWidth;
UINT8 DayAlrm;
UINT8 MonAlrm;
UINT8 Century;
UINT16 IaPcBootArch;
UINT8 Reserved1;
UINT32 Flags;
EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE ResetReg;
UINT8 ResetValue;
UINT8 Reserved2[3];
UINT64 XFirmwareCtrl;
UINT64 XDsdt;
EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE XPm1aEvtBlk;
EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE XPm1bEvtBlk;
EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE XPm1aCntBlk;
EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE XPm1bCntBlk;
EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE XPm2CntBlk;
EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE XPmTmrBlk;
EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE XGpe0Blk;
EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE XGpe1Blk;
} EFI_ACPI_3_0_FIXED_ACPI_DESCRIPTION_TABLE;
///
/// FADT Version (as defined in ACPI 3.0 spec.)
///
#define EFI_ACPI_3_0_FIXED_ACPI_DESCRIPTION_TABLE_REVISION 0x04
//
// Fixed ACPI Description Table Preferred Power Management Profile
//
#define EFI_ACPI_3_0_PM_PROFILE_UNSPECIFIED 0
#define EFI_ACPI_3_0_PM_PROFILE_DESKTOP 1
#define EFI_ACPI_3_0_PM_PROFILE_MOBILE 2
#define EFI_ACPI_3_0_PM_PROFILE_WORKSTATION 3
#define EFI_ACPI_3_0_PM_PROFILE_ENTERPRISE_SERVER 4
#define EFI_ACPI_3_0_PM_PROFILE_SOHO_SERVER 5
#define EFI_ACPI_3_0_PM_PROFILE_APPLIANCE_PC 6
#define EFI_ACPI_3_0_PM_PROFILE_PERFORMANCE_SERVER 7
//
// Fixed ACPI Description Table Boot Architecture Flags
// All other bits are reserved and must be set to 0.
//
#define EFI_ACPI_3_0_LEGACY_DEVICES BIT0
#define EFI_ACPI_3_0_8042 BIT1
#define EFI_ACPI_3_0_VGA_NOT_PRESENT BIT2
#define EFI_ACPI_3_0_MSI_NOT_SUPPORTED BIT3
#define EFI_ACPI_3_0_PCIE_ASPM_CONTROLS BIT4
//
// Fixed ACPI Description Table Fixed Feature Flags
// All other bits are reserved and must be set to 0.
//
#define EFI_ACPI_3_0_WBINVD BIT0
#define EFI_ACPI_3_0_WBINVD_FLUSH BIT1
#define EFI_ACPI_3_0_PROC_C1 BIT2
#define EFI_ACPI_3_0_P_LVL2_UP BIT3
#define EFI_ACPI_3_0_PWR_BUTTON BIT4
#define EFI_ACPI_3_0_SLP_BUTTON BIT5
#define EFI_ACPI_3_0_FIX_RTC BIT6
#define EFI_ACPI_3_0_RTC_S4 BIT7
#define EFI_ACPI_3_0_TMR_VAL_EXT BIT8
#define EFI_ACPI_3_0_DCK_CAP BIT9
#define EFI_ACPI_3_0_RESET_REG_SUP BIT10
#define EFI_ACPI_3_0_SEALED_CASE BIT11
#define EFI_ACPI_3_0_HEADLESS BIT12
#define EFI_ACPI_3_0_CPU_SW_SLP BIT13
#define EFI_ACPI_3_0_PCI_EXP_WAK BIT14
#define EFI_ACPI_3_0_USE_PLATFORM_CLOCK BIT15
#define EFI_ACPI_3_0_S4_RTC_STS_VALID BIT16
#define EFI_ACPI_3_0_REMOTE_POWER_ON_CAPABLE BIT17
#define EFI_ACPI_3_0_FORCE_APIC_CLUSTER_MODEL BIT18
#define EFI_ACPI_3_0_FORCE_APIC_PHYSICAL_DESTINATION_MODE BIT19
///
/// Firmware ACPI Control Structure
///
typedef struct {
UINT32 Signature;
UINT32 Length;
UINT32 HardwareSignature;
UINT32 FirmwareWakingVector;
UINT32 GlobalLock;
UINT32 Flags;
UINT64 XFirmwareWakingVector;
UINT8 Version;
UINT8 Reserved[31];
} EFI_ACPI_3_0_FIRMWARE_ACPI_CONTROL_STRUCTURE;
///
/// FACS Version (as defined in ACPI 3.0 spec.)
///
#define EFI_ACPI_3_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_VERSION 0x01
///
/// Firmware Control Structure Feature Flags
/// All other bits are reserved and must be set to 0.
///
#define EFI_ACPI_3_0_S4BIOS_F BIT0
//
// Differentiated System Description Table,
// Secondary System Description Table
// and Persistent System Description Table,
// no definition needed as they are common description table header, the same with
// EFI_ACPI_DESCRIPTION_HEADER, followed by a definition block.
//
#define EFI_ACPI_3_0_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x02
#define EFI_ACPI_3_0_SECONDARY_SYSTEM_DESCRIPTION_TABLE_REVISION 0x02
///
/// Multiple APIC Description Table header definition. The rest of the table
/// must be defined in a platform specific manner.
///
typedef struct {
EFI_ACPI_DESCRIPTION_HEADER Header;
UINT32 LocalApicAddress;
UINT32 Flags;
} EFI_ACPI_3_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER;
///
/// MADT Revision (as defined in ACPI 3.0 spec.)
///
#define EFI_ACPI_3_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION 0x02
///
/// Multiple APIC Flags
/// All other bits are reserved and must be set to 0.
///
#define EFI_ACPI_3_0_PCAT_COMPAT BIT0
//
// Multiple APIC Description Table APIC structure types
// All other values between 0x09 an 0xFF are reserved and
// will be ignored by OSPM.
//
#define EFI_ACPI_3_0_PROCESSOR_LOCAL_APIC 0x00
#define EFI_ACPI_3_0_IO_APIC 0x01
#define EFI_ACPI_3_0_INTERRUPT_SOURCE_OVERRIDE 0x02
#define EFI_ACPI_3_0_NON_MASKABLE_INTERRUPT_SOURCE 0x03
#define EFI_ACPI_3_0_LOCAL_APIC_NMI 0x04
#define EFI_ACPI_3_0_LOCAL_APIC_ADDRESS_OVERRIDE 0x05
#define EFI_ACPI_3_0_IO_SAPIC 0x06
#define EFI_ACPI_3_0_LOCAL_SAPIC 0x07
#define EFI_ACPI_3_0_PLATFORM_INTERRUPT_SOURCES 0x08
//
// APIC Structure Definitions
//
///
/// Processor Local APIC Structure Definition
///
typedef struct {
UINT8 Type;
UINT8 Length;
UINT8 AcpiProcessorId;
UINT8 ApicId;
UINT32 Flags;
} EFI_ACPI_3_0_PROCESSOR_LOCAL_APIC_STRUCTURE;
///
/// Local APIC Flags. All other bits are reserved and must be 0.
///
#define EFI_ACPI_3_0_LOCAL_APIC_ENABLED BIT0
///
/// IO APIC Structure
///
typedef struct {
UINT8 Type;
UINT8 Length;
UINT8 IoApicId;
UINT8 Reserved;
UINT32 IoApicAddress;
UINT32 GlobalSystemInterruptBase;
} EFI_ACPI_3_0_IO_APIC_STRUCTURE;
///
/// Interrupt Source Override Structure
///
typedef struct {
UINT8 Type;
UINT8 Length;
UINT8 Bus;
UINT8 Source;
UINT32 GlobalSystemInterrupt;
UINT16 Flags;
} EFI_ACPI_3_0_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE;
///
/// Platform Interrupt Sources Structure Definition
///
typedef struct {
UINT8 Type;
UINT8 Length;
UINT16 Flags;
UINT8 InterruptType;
UINT8 ProcessorId;
UINT8 ProcessorEid;
UINT8 IoSapicVector;
UINT32 GlobalSystemInterrupt;
UINT32 PlatformInterruptSourceFlags;
UINT8 CpeiProcessorOverride;
UINT8 Reserved[31];
} EFI_ACPI_3_0_PLATFORM_INTERRUPT_APIC_STRUCTURE;
//
// MPS INTI flags.
// All other bits are reserved and must be set to 0.
//
#define EFI_ACPI_3_0_POLARITY (3 << 0)
#define EFI_ACPI_3_0_TRIGGER_MODE (3 << 2)
///
/// Non-Maskable Interrupt Source Structure
///
typedef struct {
UINT8 Type;
UINT8 Length;
UINT16 Flags;
UINT32 GlobalSystemInterrupt;
} EFI_ACPI_3_0_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE;
///
/// Local APIC NMI Structure
///
typedef struct {
UINT8 Type;
UINT8 Length;
UINT8 AcpiProcessorId;
UINT16 Flags;
UINT8 LocalApicLint;
} EFI_ACPI_3_0_LOCAL_APIC_NMI_STRUCTURE;
///
/// Local APIC Address Override Structure
///
typedef struct {
UINT8 Type;
UINT8 Length;
UINT16 Reserved;
UINT64 LocalApicAddress;
} EFI_ACPI_3_0_LOCAL_APIC_ADDRESS_OVERRIDE_STRUCTURE;
///
/// IO SAPIC Structure
///
typedef struct {
UINT8 Type;
UINT8 Length;
UINT8 IoApicId;
UINT8 Reserved;
UINT32 GlobalSystemInterruptBase;
UINT64 IoSapicAddress;
} EFI_ACPI_3_0_IO_SAPIC_STRUCTURE;
///
/// Local SAPIC Structure
/// This struct followed by a null-terminated ASCII string - ACPI Processor UID String
///
typedef struct {
UINT8 Type;
UINT8 Length;
UINT8 AcpiProcessorId;
UINT8 LocalSapicId;
UINT8 LocalSapicEid;
UINT8 Reserved[3];
UINT32 Flags;
UINT32 ACPIProcessorUIDValue;
} EFI_ACPI_3_0_PROCESSOR_LOCAL_SAPIC_STRUCTURE;
///
/// Platform Interrupt Sources Structure
///
typedef struct {
UINT8 Type;
UINT8 Length;
UINT16 Flags;
UINT8 InterruptType;
UINT8 ProcessorId;
UINT8 ProcessorEid;
UINT8 IoSapicVector;
UINT32 GlobalSystemInterrupt;
UINT32 PlatformInterruptSourceFlags;
} EFI_ACPI_3_0_PLATFORM_INTERRUPT_SOURCES_STRUCTURE;
///
/// Platform Interrupt Source Flags.
/// All other bits are reserved and must be set to 0.
///
#define EFI_ACPI_3_0_CPEI_PROCESSOR_OVERRIDE BIT0
///
/// Smart Battery Description Table (SBST)
///
typedef struct {
EFI_ACPI_DESCRIPTION_HEADER Header;
UINT32 WarningEnergyLevel;
UINT32 LowEnergyLevel;
UINT32 CriticalEnergyLevel;
} EFI_ACPI_3_0_SMART_BATTERY_DESCRIPTION_TABLE;
///
/// SBST Version (as defined in ACPI 3.0 spec.)
///
#define EFI_ACPI_3_0_SMART_BATTERY_DESCRIPTION_TABLE_REVISION 0x01
///
/// Embedded Controller Boot Resources Table (ECDT)
/// The table is followed by a null terminated ASCII string that contains
/// a fully qualified reference to the name space object.
///
typedef struct {
EFI_ACPI_DESCRIPTION_HEADER Header;
EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE EcControl;
EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE EcData;
UINT32 Uid;
UINT8 GpeBit;
} EFI_ACPI_3_0_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE;
///
/// ECDT Version (as defined in ACPI 3.0 spec.)
///
#define EFI_ACPI_3_0_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE_REVISION 0x01
///
/// System Resource Affinity Table (SRAT. The rest of the table
/// must be defined in a platform specific manner.
///
typedef struct {
EFI_ACPI_DESCRIPTION_HEADER Header;
UINT32 Reserved1; ///< Must be set to 1
UINT64 Reserved2;
} EFI_ACPI_3_0_SYSTEM_RESOURCE_AFFINITY_TABLE_HEADER;
///
/// SRAT Version (as defined in ACPI 3.0 spec.)
///
#define EFI_ACPI_3_0_SYSTEM_RESOURCE_AFFINITY_TABLE_REVISION 0x02
//
// SRAT structure types.
// All other values between 0x02 an 0xFF are reserved and
// will be ignored by OSPM.
//
#define EFI_ACPI_3_0_PROCESSOR_LOCAL_APIC_SAPIC_AFFINITY 0x00
#define EFI_ACPI_3_0_MEMORY_AFFINITY 0x01
///
/// Processor Local APIC/SAPIC Affinity Structure Definition
///
typedef struct {
UINT8 Type;
UINT8 Length;
UINT8 ProximityDomain7To0;
UINT8 ApicId;
UINT32 Flags;
UINT8 LocalSapicEid;
UINT8 ProximityDomain31To8[3];
UINT8 Reserved[4];
} EFI_ACPI_3_0_PROCESSOR_LOCAL_APIC_SAPIC_AFFINITY_STRUCTURE;
///
/// Local APIC/SAPIC Flags. All other bits are reserved and must be 0.
///
#define EFI_ACPI_3_0_PROCESSOR_LOCAL_APIC_SAPIC_ENABLED (1 << 0)
///
/// Memory Affinity Structure Definition
///
typedef struct {
UINT8 Type;
UINT8 Length;
UINT32 ProximityDomain;
UINT16 Reserved1;
UINT32 AddressBaseLow;
UINT32 AddressBaseHigh;
UINT32 LengthLow;
UINT32 LengthHigh;
UINT32 Reserved2;
UINT32 Flags;
UINT64 Reserved3;
} EFI_ACPI_3_0_MEMORY_AFFINITY_STRUCTURE;
//
// Memory Flags. All other bits are reserved and must be 0.
//
#define EFI_ACPI_3_0_MEMORY_ENABLED (1 << 0)
#define EFI_ACPI_3_0_MEMORY_HOT_PLUGGABLE (1 << 1)
#define EFI_ACPI_3_0_MEMORY_NONVOLATILE (1 << 2)
///
/// System Locality Distance Information Table (SLIT).
/// The rest of the table is a matrix.
///
typedef struct {
EFI_ACPI_DESCRIPTION_HEADER Header;
UINT64 NumberOfSystemLocalities;
} EFI_ACPI_3_0_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_HEADER;
///
/// SLIT Version (as defined in ACPI 3.0 spec.)
///
#define EFI_ACPI_3_0_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_REVISION 0x01
//
// Known table signatures
//
///
/// "RSD PTR " Root System Description Pointer
///
#define EFI_ACPI_3_0_ROOT_SYSTEM_DESCRIPTION_POINTER_SIGNATURE SIGNATURE_64('R', 'S', 'D', ' ', 'P', 'T', 'R', ' ')
///
/// "APIC" Multiple APIC Description Table
///
#define EFI_ACPI_3_0_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('A', 'P', 'I', 'C')
///
/// "DSDT" Differentiated System Description Table
///
#define EFI_ACPI_3_0_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('D', 'S', 'D', 'T')
///
/// "ECDT" Embedded Controller Boot Resources Table
///
#define EFI_ACPI_3_0_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE_SIGNATURE SIGNATURE_32('E', 'C', 'D', 'T')
///
/// "FACP" Fixed ACPI Description Table
///
#define EFI_ACPI_3_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('F', 'A', 'C', 'P')
///
/// "FACS" Firmware ACPI Control Structure
///
#define EFI_ACPI_3_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_SIGNATURE SIGNATURE_32('F', 'A', 'C', 'S')
///
/// "PSDT" Persistent System Description Table
///
#define EFI_ACPI_3_0_PERSISTENT_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('P', 'S', 'D', 'T')
///
/// "RSDT" Root System Description Table
///
#define EFI_ACPI_3_0_ROOT_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('R', 'S', 'D', 'T')
///
/// "SBST" Smart Battery Specification Table
///
#define EFI_ACPI_3_0_SMART_BATTERY_SPECIFICATION_TABLE_SIGNATURE SIGNATURE_32('S', 'B', 'S', 'T')
///
/// "SLIT" System Locality Information Table
///
#define EFI_ACPI_3_0_SYSTEM_LOCALITY_INFORMATION_TABLE_SIGNATURE SIGNATURE_32('S', 'L', 'I', 'T')
///
/// "SRAT" System Resource Affinity Table
///
#define EFI_ACPI_3_0_SYSTEM_RESOURCE_AFFINITY_TABLE_SIGNATURE SIGNATURE_32('S', 'R', 'A', 'T')
///
/// "SSDT" Secondary System Description Table
///
#define EFI_ACPI_3_0_SECONDARY_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('S', 'S', 'D', 'T')
///
/// "XSDT" Extended System Description Table
///
#define EFI_ACPI_3_0_EXTENDED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('X', 'S', 'D', 'T')
///
/// "BOOT" MS Simple Boot Spec
///
#define EFI_ACPI_3_0_SIMPLE_BOOT_FLAG_TABLE_SIGNATURE SIGNATURE_32('B', 'O', 'O', 'T')
///
/// "CPEP" Corrected Platform Error Polling Table
///
#define EFI_ACPI_3_0_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_SIGNATURE SIGNATURE_32('C', 'P', 'E', 'P')
///
/// "DBGP" MS Debug Port Spec
///
#define EFI_ACPI_3_0_DEBUG_PORT_TABLE_SIGNATURE SIGNATURE_32('D', 'B', 'G', 'P')
///
/// "ETDT" Event Timer Description Table
///
#define EFI_ACPI_3_0_EVENT_TIMER_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('E', 'T', 'D', 'T')
///
/// "HPET" IA-PC High Precision Event Timer Table
///
#define EFI_ACPI_3_0_HIGH_PRECISION_EVENT_TIMER_TABLE_SIGNATURE SIGNATURE_32('H', 'P', 'E', 'T')
///
/// "MCFG" PCI Express Memory Mapped Configuration Space Base Address Description Table
///
#define EFI_ACPI_3_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('M', 'C', 'F', 'G')
///
/// "SPCR" Serial Port Console Redirection Table
///
#define EFI_ACPI_3_0_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE SIGNATURE_32('S', 'P', 'C', 'R')
///
/// "SPMI" Server Platform Management Interface Table
///
#define EFI_ACPI_3_0_SERVER_PLATFORM_MANAGEMENT_INTERFACE_TABLE_SIGNATURE SIGNATURE_32('S', 'P', 'M', 'I')
///
/// "TCPA" Trusted Computing Platform Alliance Capabilities Table
///
#define EFI_ACPI_3_0_TRUSTED_COMPUTING_PLATFORM_ALLIANCE_CAPABILITIES_TABLE_SIGNATURE SIGNATURE_32('T', 'C', 'P', 'A')
///
/// "WDRT" Watchdog Resource Table
///
#define EFI_ACPI_3_0_WATCHDOG_RESOURCE_TABLE_SIGNATURE SIGNATURE_32('W', 'D', 'R', 'T')
///
/// "WDAT" Watchdog Action Table
///
#define EFI_ACPI_3_0_WATCHDOG_ACTION_TABLE_SIGNATURE SIGNATURE_32('W', 'D', 'A', 'T')
///
/// "WSPT" Windows Specific Properties Table
///
#define EFI_ACPI_3_0_WINDOWS_SPECIFIC_PROPERTIES_TABLE_SIGNATURE SIGNATURE_32('W', 'S', 'P', 'T')
///
/// "iBFT" iSCSI Boot Firmware Table
///
#define EFI_ACPI_3_0_ISCSI_BOOT_FIRMWARE_TABLE_SIGNATURE SIGNATURE_32('i', 'B', 'F', 'T')
#pragma pack()
#endif

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/** @file
This file contains AML code definition in the latest ACPI spec.
Copyright (c) 2011, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2019 - 2021, Arm Limited. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef _ACPI_AML_H_
#define _ACPI_AML_H_
//
// ACPI AML definition
//
//
// Primary OpCode
//
#define AML_ZERO_OP 0x00
#define AML_ONE_OP 0x01
#define AML_ALIAS_OP 0x06
#define AML_NAME_OP 0x08
#define AML_BYTE_PREFIX 0x0a
#define AML_WORD_PREFIX 0x0b
#define AML_DWORD_PREFIX 0x0c
#define AML_STRING_PREFIX 0x0d
#define AML_QWORD_PREFIX 0x0e
#define AML_SCOPE_OP 0x10
#define AML_BUFFER_OP 0x11
#define AML_PACKAGE_OP 0x12
#define AML_VAR_PACKAGE_OP 0x13
#define AML_METHOD_OP 0x14
#define AML_EXTERNAL_OP 0x15
#define AML_DUAL_NAME_PREFIX 0x2e
#define AML_MULTI_NAME_PREFIX 0x2f
#define AML_NAME_CHAR_A 0x41
#define AML_NAME_CHAR_B 0x42
#define AML_NAME_CHAR_C 0x43
#define AML_NAME_CHAR_D 0x44
#define AML_NAME_CHAR_E 0x45
#define AML_NAME_CHAR_F 0x46
#define AML_NAME_CHAR_G 0x47
#define AML_NAME_CHAR_H 0x48
#define AML_NAME_CHAR_I 0x49
#define AML_NAME_CHAR_J 0x4a
#define AML_NAME_CHAR_K 0x4b
#define AML_NAME_CHAR_L 0x4c
#define AML_NAME_CHAR_M 0x4d
#define AML_NAME_CHAR_N 0x4e
#define AML_NAME_CHAR_O 0x4f
#define AML_NAME_CHAR_P 0x50
#define AML_NAME_CHAR_Q 0x51
#define AML_NAME_CHAR_R 0x52
#define AML_NAME_CHAR_S 0x53
#define AML_NAME_CHAR_T 0x54
#define AML_NAME_CHAR_U 0x55
#define AML_NAME_CHAR_V 0x56
#define AML_NAME_CHAR_W 0x57
#define AML_NAME_CHAR_X 0x58
#define AML_NAME_CHAR_Y 0x59
#define AML_NAME_CHAR_Z 0x5a
#define AML_ROOT_CHAR 0x5c
#define AML_PARENT_PREFIX_CHAR 0x5e
#define AML_NAME_CHAR__ 0x5f
#define AML_LOCAL0 0x60
#define AML_LOCAL1 0x61
#define AML_LOCAL2 0x62
#define AML_LOCAL3 0x63
#define AML_LOCAL4 0x64
#define AML_LOCAL5 0x65
#define AML_LOCAL6 0x66
#define AML_LOCAL7 0x67
#define AML_ARG0 0x68
#define AML_ARG1 0x69
#define AML_ARG2 0x6a
#define AML_ARG3 0x6b
#define AML_ARG4 0x6c
#define AML_ARG5 0x6d
#define AML_ARG6 0x6e
#define AML_STORE_OP 0x70
#define AML_REF_OF_OP 0x71
#define AML_ADD_OP 0x72
#define AML_CONCAT_OP 0x73
#define AML_SUBTRACT_OP 0x74
#define AML_INCREMENT_OP 0x75
#define AML_DECREMENT_OP 0x76
#define AML_MULTIPLY_OP 0x77
#define AML_DIVIDE_OP 0x78
#define AML_SHIFT_LEFT_OP 0x79
#define AML_SHIFT_RIGHT_OP 0x7a
#define AML_AND_OP 0x7b
#define AML_NAND_OP 0x7c
#define AML_OR_OP 0x7d
#define AML_NOR_OP 0x7e
#define AML_XOR_OP 0x7f
#define AML_NOT_OP 0x80
#define AML_FIND_SET_LEFT_BIT_OP 0x81
#define AML_FIND_SET_RIGHT_BIT_OP 0x82
#define AML_DEREF_OF_OP 0x83
#define AML_CONCAT_RES_OP 0x84
#define AML_MOD_OP 0x85
#define AML_NOTIFY_OP 0x86
#define AML_SIZE_OF_OP 0x87
#define AML_INDEX_OP 0x88
#define AML_MATCH_OP 0x89
#define AML_CREATE_DWORD_FIELD_OP 0x8a
#define AML_CREATE_WORD_FIELD_OP 0x8b
#define AML_CREATE_BYTE_FIELD_OP 0x8c
#define AML_CREATE_BIT_FIELD_OP 0x8d
#define AML_OBJECT_TYPE_OP 0x8e
#define AML_CREATE_QWORD_FIELD_OP 0x8f
#define AML_LAND_OP 0x90
#define AML_LOR_OP 0x91
#define AML_LNOT_OP 0x92
#define AML_LEQUAL_OP 0x93
#define AML_LGREATER_OP 0x94
#define AML_LLESS_OP 0x95
#define AML_TO_BUFFER_OP 0x96
#define AML_TO_DEC_STRING_OP 0x97
#define AML_TO_HEX_STRING_OP 0x98
#define AML_TO_INTEGER_OP 0x99
#define AML_TO_STRING_OP 0x9c
#define AML_COPY_OBJECT_OP 0x9d
#define AML_MID_OP 0x9e
#define AML_CONTINUE_OP 0x9f
#define AML_IF_OP 0xa0
#define AML_ELSE_OP 0xa1
#define AML_WHILE_OP 0xa2
#define AML_NOOP_OP 0xa3
#define AML_RETURN_OP 0xa4
#define AML_BREAK_OP 0xa5
#define AML_BREAK_POINT_OP 0xcc
#define AML_ONES_OP 0xff
//
// Extended OpCode
//
#define AML_EXT_OP 0x5b
#define AML_EXT_MUTEX_OP 0x01
#define AML_EXT_EVENT_OP 0x02
#define AML_EXT_COND_REF_OF_OP 0x12
#define AML_EXT_CREATE_FIELD_OP 0x13
#define AML_EXT_LOAD_TABLE_OP 0x1f
#define AML_EXT_LOAD_OP 0x20
#define AML_EXT_STALL_OP 0x21
#define AML_EXT_SLEEP_OP 0x22
#define AML_EXT_ACQUIRE_OP 0x23
#define AML_EXT_SIGNAL_OP 0x24
#define AML_EXT_WAIT_OP 0x25
#define AML_EXT_RESET_OP 0x26
#define AML_EXT_RELEASE_OP 0x27
#define AML_EXT_FROM_BCD_OP 0x28
#define AML_EXT_TO_BCD_OP 0x29
#define AML_EXT_UNLOAD_OP 0x2a
#define AML_EXT_REVISION_OP 0x30
#define AML_EXT_DEBUG_OP 0x31
#define AML_EXT_FATAL_OP 0x32
#define AML_EXT_TIMER_OP 0x33
#define AML_EXT_REGION_OP 0x80
#define AML_EXT_FIELD_OP 0x81
#define AML_EXT_DEVICE_OP 0x82
#define AML_EXT_PROCESSOR_OP 0x83
#define AML_EXT_POWER_RES_OP 0x84
#define AML_EXT_THERMAL_ZONE_OP 0x85
#define AML_EXT_INDEX_FIELD_OP 0x86
#define AML_EXT_BANK_FIELD_OP 0x87
#define AML_EXT_DATA_REGION_OP 0x88
//
// FieldElement OpCode
//
#define AML_FIELD_RESERVED_OP 0x00
#define AML_FIELD_ACCESS_OP 0x01
#define AML_FIELD_CONNECTION_OP 0x02
#define AML_FIELD_EXT_ACCESS_OP 0x03
//
// AML Name segment definitions
//
#define AML_NAME_SEG_SIZE 4
#endif

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/** @file
ACPI Alert Standard Format Description Table ASF! as described in the ASF2.0 Specification
Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef _ALERT_STANDARD_FORMAT_TABLE_H_
#define _ALERT_STANDARD_FORMAT_TABLE_H_
#include <IndustryStandard/Acpi.h>
//
// Ensure proper structure formats
//
#pragma pack (1)
///
/// Information Record header that appears at the beginning of each record
///
typedef struct {
UINT8 Type;
UINT8 Reserved;
UINT16 RecordLength;
} EFI_ACPI_ASF_RECORD_HEADER;
///
/// This structure contains information that identifies the system's type
/// and configuration
///
typedef struct {
EFI_ACPI_ASF_RECORD_HEADER RecordHeader;
UINT8 MinWatchDogResetValue;
UINT8 MinPollingInterval;
UINT16 SystemID;
UINT32 IANAManufactureID;
UINT8 FeatureFlags;
UINT8 Reserved[3];
} EFI_ACPI_ASF_INFO;
///
/// ASF Alert Data
///
typedef struct {
UINT8 DeviceAddress;
UINT8 Command;
UINT8 DataMask;
UINT8 CompareValue;
UINT8 EventSenseType;
UINT8 EventType;
UINT8 EventOffset;
UINT8 EventSourceType;
UINT8 EventSeverity;
UINT8 SensorNumber;
UINT8 Entity;
UINT8 EntityInstance;
} EFI_ACPI_ASF_ALERTDATA;
///
/// Alert sensors definition
///
typedef struct {
EFI_ACPI_ASF_RECORD_HEADER RecordHeader;
UINT8 AssertionEventBitMask;
UINT8 DeassertionEventBitMask;
UINT8 NumberOfAlerts;
UINT8 ArrayElementLength; ///< For ASF version 1.0 and later, this filed is set to 0x0C
///
/// EFI_ACPI_ASF_ALERTDATA DeviceArray[ANYSIZE_ARRAY];
///
} EFI_ACPI_ASF_ALRT;
///
/// Alert Control Data
///
typedef struct {
UINT8 Function;
UINT8 DeviceAddress;
UINT8 Command;
UINT8 DataValue;
} EFI_ACPI_ASF_CONTROLDATA;
///
/// Alert Remote Control System Actions
///
typedef struct {
EFI_ACPI_ASF_RECORD_HEADER RecordHeader;
UINT8 NumberOfControls;
UINT8 ArrayElementLength; ///< For ASF version 1.0 and later, this filed is set to 0x4
UINT16 RctlReserved;
///
/// EFI_ACPI_ASF_CONTROLDATA; DeviceArray[ANYSIZE_ARRAY];
///
} EFI_ACPI_ASF_RCTL;
///
/// Remote Control Capabilities
///
typedef struct {
EFI_ACPI_ASF_RECORD_HEADER RecordHeader;
UINT8 RemoteControlCapabilities[7];
UINT8 RMCPCompletionCode;
UINT32 RMCPIANA;
UINT8 RMCPSpecialCommand;
UINT8 RMCPSpecialCommandParameter[2];
UINT8 RMCPBootOptions[2];
UINT8 RMCPOEMParameters[2];
} EFI_ACPI_ASF_RMCP;
///
/// SMBus Devices with fixed addresses
///
typedef struct {
EFI_ACPI_ASF_RECORD_HEADER RecordHeader;
UINT8 SEEPROMAddress;
UINT8 NumberOfDevices;
///
/// UINT8 FixedSmbusAddresses[ANYSIZE_ARRAY];
///
} EFI_ACPI_ASF_ADDR;
///
/// ASF! Description Table Header
///
typedef EFI_ACPI_DESCRIPTION_HEADER EFI_ACPI_ASF_DESCRIPTION_HEADER;
///
/// The revision stored in ASF! DESCRIPTION TABLE as BCD value
///
#define EFI_ACPI_2_0_ASF_DESCRIPTION_TABLE_REVISION 0x20
///
/// "ASF!" ASF Description Table Signature
///
#define EFI_ACPI_ASF_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32 ('A', 'S', 'F', '!')
#pragma pack ()
#endif // _ALERT_STANDARD_FORMAT_TABLE_H

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/** @file
Arm Error Source Table as described in the
'ACPI for the Armv8 RAS Extensions 1.1' Specification.
Copyright (c) 2020 Arm Limited.
SPDX-License-Identifier: BSD-2-Clause-Patent
@par Reference(s):
- ACPI for the Armv8 RAS Extensions 1.1 Platform Design Document,
dated 28 September 2020.
(https://developer.arm.com/documentation/den0085/0101/)
@par Glossary
- Ref : Reference
- Id : Identifier
**/
#ifndef ARM_ERROR_SOURCE_TABLE_H_
#define ARM_ERROR_SOURCE_TABLE_H_
///
/// "AEST" Arm Error Source Table
///
#define EFI_ACPI_6_3_ARM_ERROR_SOURCE_TABLE_SIGNATURE SIGNATURE_32('A', 'E', 'S', 'T')
#define EFI_ACPI_ARM_ERROR_SOURCE_TABLE_REVISION 1
#pragma pack(1)
///
/// Arm Error Source Table definition.
///
typedef struct {
EFI_ACPI_DESCRIPTION_HEADER Header;
} EFI_ACPI_ARM_ERROR_SOURCE_TABLE;
///
/// AEST Node structure.
///
typedef struct {
/// Node type:
/// 0x00 - Processor error node
/// 0x01 - Memory error node
/// 0x02 - SMMU error node
/// 0x03 - Vendor-defined error node
/// 0x04 - GIC error node
UINT8 Type;
/// Length of structure in bytes.
UINT16 Length;
/// Reserved - Must be zero.
UINT8 Reserved;
/// Offset from the start of the node to node-specific data.
UINT32 DataOffset;
/// Offset from the start of the node to the node interface structure.
UINT32 InterfaceOffset;
/// Offset from the start of the node to node interrupt array.
UINT32 InterruptArrayOffset;
/// Number of entries in the interrupt array.
UINT32 InterruptArrayCount;
// Generic node data
/// The timestamp frequency of the counter in Hz.
UINT64 TimestampRate;
/// Reserved - Must be zero.
UINT64 Reserved1;
/// The rate in Hz at which the Error Generation Counter decrements.
UINT64 ErrorInjectionCountdownRate;
} EFI_ACPI_AEST_NODE_STRUCT;
// AEST Node type definitions
#define EFI_ACPI_AEST_NODE_TYPE_PROCESSOR 0x0
#define EFI_ACPI_AEST_NODE_TYPE_MEMORY 0x1
#define EFI_ACPI_AEST_NODE_TYPE_SMMU 0x2
#define EFI_ACPI_AEST_NODE_TYPE_VENDOR_DEFINED 0x3
#define EFI_ACPI_AEST_NODE_TYPE_GIC 0x4
///
/// AEST Node Interface structure.
///
typedef struct {
/// Interface type:
/// 0x0 - System register (SR)
/// 0x1 - Memory mapped (MMIO)
UINT8 Type;
/// Reserved - Must be zero.
UINT8 Reserved[3];
/// AEST node interface flags.
UINT32 Flags;
/// Base address of error group that contains the error node.
UINT64 BaseAddress;
/// Zero-based index of the first standard error record that
/// belongs to this node.
UINT32 StartErrorRecordIndex;
/// Number of error records in this node including both
/// implemented and unimplemented records.
UINT32 NumberErrorRecords;
/// A bitmap indicating the error records within this
/// node that are implemented in the current system.
UINT64 ErrorRecordImplemented;
/// A bitmap indicating the error records within this node that
/// support error status reporting through the ERRGSR register.
UINT64 ErrorRecordStatusReportingSupported;
/// A bitmap indicating the addressing mode used by each error
/// record within this node to populate the ERR<n>_ADDR register.
UINT64 AddressingMode;
} EFI_ACPI_AEST_INTERFACE_STRUCT;
// AEST Interface node type definitions.
#define EFI_ACPI_AEST_INTERFACE_TYPE_SR 0x0
#define EFI_ACPI_AEST_INTERFACE_TYPE_MMIO 0x1
// AEST node interface flag definitions.
#define EFI_ACPI_AEST_INTERFACE_FLAG_PRIVATE 0
#define EFI_ACPI_AEST_INTERFACE_FLAG_SHARED BIT0
#define EFI_ACPI_AEST_INTERFACE_FLAG_CLEAR_MISCX BIT1
///
/// AEST Node Interrupt structure.
///
typedef struct {
/// Interrupt type:
/// 0x0 - Fault Handling Interrupt
/// 0x1 - Error Recovery Interrupt
UINT8 InterruptType;
/// Reserved - Must be zero.
UINT8 Reserved[2];
/// Interrupt flags
/// Bits [31:1]: Must be zero.
/// Bit 0:
/// 0b - Interrupt is edge-triggered
/// 1b - Interrupt is level-triggered
UINT8 InterruptFlags;
/// GSIV of interrupt, if interrupt is an SPI or a PPI.
UINT32 InterruptGsiv;
/// If MSI is supported, then this field must be set to the
/// Identifier field of the IORT ITS Group node.
UINT8 ItsGroupRefId;
/// Reserved - must be zero.
UINT8 Reserved1[3];
} EFI_ACPI_AEST_INTERRUPT_STRUCT;
// AEST Interrupt node - interrupt type defintions.
#define EFI_ACPI_AEST_INTERRUPT_TYPE_FAULT_HANDLING 0x0
#define EFI_ACPI_AEST_INTERRUPT_TYPE_ERROR_RECOVERY 0x1
// AEST Interrupt node - interrupt flag defintions.
#define EFI_ACPI_AEST_INTERRUPT_FLAG_TRIGGER_TYPE_EDGE 0
#define EFI_ACPI_AEST_INTERRUPT_FLAG_TRIGGER_TYPE_LEVEL BIT0
///
/// Cache Processor Resource structure.
///
typedef struct {
/// Reference to the cache structure in the PPTT table.
UINT32 CacheRefId;
/// Reserved
UINT32 Reserved;
} EFI_ACPI_AEST_PROCESSOR_CACHE_RESOURCE_STRUCT;
///
/// TLB Processor Resource structure.
///
typedef struct {
/// TLB level from perspective of current processor.
UINT32 TlbRefId;
/// Reserved
UINT32 Reserved;
} EFI_ACPI_AEST_PROCESSOR_TLB_RESOURCE_STRUCT;
///
/// Processor Generic Resource structure.
///
typedef struct {
/// Vendor-defined supplementary data.
UINT32 Data;
} EFI_ACPI_AEST_PROCESSOR_GENERIC_RESOURCE_STRUCT;
///
/// AEST Processor Resource union.
///
typedef union {
/// Processor Cache resource.
EFI_ACPI_AEST_PROCESSOR_CACHE_RESOURCE_STRUCT Cache;
/// Processor TLB resource.
EFI_ACPI_AEST_PROCESSOR_TLB_RESOURCE_STRUCT Tlb;
/// Processor Generic resource.
EFI_ACPI_AEST_PROCESSOR_GENERIC_RESOURCE_STRUCT Generic;
} EFI_ACPI_AEST_PROCESSOR_RESOURCE;
///
/// AEST Processor structure.
///
typedef struct {
/// AEST Node header
EFI_ACPI_AEST_NODE_STRUCT NodeHeader;
/// Processor ID of node.
UINT32 AcpiProcessorId;
/// Resource type of the processor node.
/// 0x0 - Cache
/// 0x1 - TLB
/// 0x2 - Generic
UINT8 ResourceType;
/// Reserved - must be zero.
UINT8 Reserved;
/// Processor structure flags.
UINT8 Flags;
/// Processor structure revision.
UINT8 Revision;
/// Processor affinity descriptor for the resource that this
/// error node pertains to.
UINT64 ProcessorAffinityLevelIndicator;
/// Processor resource
EFI_ACPI_AEST_PROCESSOR_RESOURCE Resource;
// Node Interface
// EFI_ACPI_AEST_INTERFACE_STRUCT NodeInterface;
// Node Interrupt Array
// EFI_ACPI_AEST_INTERRUPT_STRUCT NodeInterruptArray[n];
} EFI_ACPI_AEST_PROCESSOR_STRUCT;
// AEST Processor resource type definitions.
#define EFI_ACPI_AEST_PROCESSOR_RESOURCE_TYPE_CACHE 0x0
#define EFI_ACPI_AEST_PROCESSOR_RESOURCE_TYPE_TLB 0x1
#define EFI_ACPI_AEST_PROCESSOR_RESOURCE_TYPE_GENERIC 0x2
// AEST Processor flag definitions.
#define EFI_ACPI_AEST_PROCESSOR_FLAG_GLOBAL BIT0
#define EFI_ACPI_AEST_PROCESSOR_FLAG_SHARED BIT1
///
/// Memory Controller structure.
///
typedef struct {
/// AEST Node header
EFI_ACPI_AEST_NODE_STRUCT NodeHeader;
/// SRAT proximity domain.
UINT32 ProximityDomain;
// Node Interface
// EFI_ACPI_AEST_INTERFACE_STRUCT NodeInterface;
// Node Interrupt Array
// EFI_ACPI_AEST_INTERRUPT_STRUCT NodeInterruptArray[n];
} EFI_ACPI_AEST_MEMORY_CONTROLLER_STRUCT;
///
/// SMMU structure.
///
typedef struct {
/// AEST Node header
EFI_ACPI_AEST_NODE_STRUCT NodeHeader;
/// Reference to the IORT table node that describes this SMMU.
UINT32 SmmuRefId;
/// Reference to the IORT table node that is associated with the
/// sub-component within this SMMU.
UINT32 SubComponentRefId;
// Node Interface
// EFI_ACPI_AEST_INTERFACE_STRUCT NodeInterface;
// Node Interrupt Array
// EFI_ACPI_AEST_INTERRUPT_STRUCT NodeInterruptArray[n];
} EFI_ACPI_AEST_SMMU_STRUCT;
///
/// Vendor-Defined structure.
///
typedef struct {
/// AEST Node header
EFI_ACPI_AEST_NODE_STRUCT NodeHeader;
/// ACPI HID of the component.
UINT32 HardwareId;
/// The ACPI Unique identifier of the component.
UINT32 UniqueId;
/// Vendor-specific data, for example to identify this error source.
UINT8 VendorData[16];
// Node Interface
// EFI_ACPI_AEST_INTERFACE_STRUCT NodeInterface;
// Node Interrupt Array
// EFI_ACPI_AEST_INTERRUPT_STRUCT NodeInterruptArray[n];
} EFI_ACPI_AEST_VENDOR_DEFINED_STRUCT;
///
/// GIC structure.
///
typedef struct {
/// AEST Node header
EFI_ACPI_AEST_NODE_STRUCT NodeHeader;
/// Type of GIC interface that is associated with this error node.
/// 0x0 - GIC CPU (GICC)
/// 0x1 - GIC Distributor (GICD)
/// 0x2 - GIC Resistributor (GICR)
/// 0x3 - GIC ITS (GITS)
UINT32 InterfaceType;
/// Identifier for the interface instance.
UINT32 GicInterfaceRefId;
// Node Interface
// EFI_ACPI_AEST_INTERFACE_STRUCT NodeInterface;
// Node Interrupt Array
// EFI_ACPI_AEST_INTERRUPT_STRUCT NodeInterruptArray[n];
} EFI_ACPI_AEST_GIC_STRUCT;
// AEST GIC interface type definitions.
#define EFI_ACPI_AEST_GIC_INTERFACE_TYPE_GICC 0x0
#define EFI_ACPI_AEST_GIC_INTERFACE_TYPE_GICD 0x1
#define EFI_ACPI_AEST_GIC_INTERFACE_TYPE_GICR 0x2
#define EFI_ACPI_AEST_GIC_INTERFACE_TYPE_GITS 0x3
#pragma pack()
#endif // ARM_ERROR_SOURCE_TABLE_H_

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src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/Atapi.h Normal file
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/** @file
This file contains just some basic definitions that are needed by drivers
that dealing with ATA/ATAPI interface.
Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef _ATAPI_H_
#define _ATAPI_H_
#pragma pack(1)
///
/// ATA5_IDENTIFY_DATA is defined in ATA-5.
/// (This structure is provided mainly for backward-compatibility support.
/// Old drivers may reference fields that are marked "obsolete" in
/// ATA_IDENTIFY_DATA, which currently conforms to ATA-8.)
///
typedef struct {
UINT16 config; ///< General Configuration.
UINT16 cylinders; ///< Number of Cylinders.
UINT16 reserved_2;
UINT16 heads; ///< Number of logical heads.
UINT16 vendor_data1;
UINT16 vendor_data2;
UINT16 sectors_per_track;
UINT16 vendor_specific_7_9[3];
CHAR8 SerialNo[20]; ///< ASCII
UINT16 vendor_specific_20_21[2];
UINT16 ecc_bytes_available;
CHAR8 FirmwareVer[8]; ///< ASCII
CHAR8 ModelName[40]; ///< ASCII
UINT16 multi_sector_cmd_max_sct_cnt;
UINT16 reserved_48;
UINT16 capabilities;
UINT16 reserved_50;
UINT16 pio_cycle_timing;
UINT16 reserved_52;
UINT16 field_validity;
UINT16 current_cylinders;
UINT16 current_heads;
UINT16 current_sectors;
UINT16 CurrentCapacityLsb;
UINT16 CurrentCapacityMsb;
UINT16 reserved_59;
UINT16 user_addressable_sectors_lo;
UINT16 user_addressable_sectors_hi;
UINT16 reserved_62;
UINT16 multi_word_dma_mode;
UINT16 advanced_pio_modes;
UINT16 min_multi_word_dma_cycle_time;
UINT16 rec_multi_word_dma_cycle_time;
UINT16 min_pio_cycle_time_without_flow_control;
UINT16 min_pio_cycle_time_with_flow_control;
UINT16 reserved_69_79[11];
UINT16 major_version_no;
UINT16 minor_version_no;
UINT16 command_set_supported_82; ///< word 82
UINT16 command_set_supported_83; ///< word 83
UINT16 command_set_feature_extn; ///< word 84
UINT16 command_set_feature_enb_85; ///< word 85
UINT16 command_set_feature_enb_86; ///< word 86
UINT16 command_set_feature_default; ///< word 87
UINT16 ultra_dma_mode; ///< word 88
UINT16 reserved_89_127[39];
UINT16 security_status;
UINT16 vendor_data_129_159[31];
UINT16 reserved_160_255[96];
} ATA5_IDENTIFY_DATA;
///
/// ATA_IDENTIFY_DATA strictly complies with ATA/ATAPI-8 Spec
/// to define the data returned by an ATA device upon successful
/// completion of the ATA IDENTIFY_DEVICE command.
///
typedef struct {
UINT16 config; ///< General Configuration.
UINT16 obsolete_1;
UINT16 specific_config; ///< Specific Configuration.
UINT16 obsolete_3;
UINT16 retired_4_5[2];
UINT16 obsolete_6;
UINT16 cfa_reserved_7_8[2];
UINT16 retired_9;
CHAR8 SerialNo[20]; ///< word 10~19
UINT16 retired_20_21[2];
UINT16 obsolete_22;
CHAR8 FirmwareVer[8]; ///< word 23~26
CHAR8 ModelName[40]; ///< word 27~46
UINT16 multi_sector_cmd_max_sct_cnt;
UINT16 trusted_computing_support;
UINT16 capabilities_49;
UINT16 capabilities_50;
UINT16 obsolete_51_52[2];
UINT16 field_validity;
UINT16 obsolete_54_58[5];
UINT16 multi_sector_setting;
UINT16 user_addressable_sectors_lo;
UINT16 user_addressable_sectors_hi;
UINT16 obsolete_62;
UINT16 multi_word_dma_mode;
UINT16 advanced_pio_modes;
UINT16 min_multi_word_dma_cycle_time;
UINT16 rec_multi_word_dma_cycle_time;
UINT16 min_pio_cycle_time_without_flow_control;
UINT16 min_pio_cycle_time_with_flow_control;
UINT16 additional_supported; ///< word 69
UINT16 reserved_70;
UINT16 reserved_71_74[4]; ///< Reserved for IDENTIFY PACKET DEVICE cmd.
UINT16 queue_depth;
UINT16 serial_ata_capabilities;
UINT16 reserved_77; ///< Reserved for Serial ATA
UINT16 serial_ata_features_supported;
UINT16 serial_ata_features_enabled;
UINT16 major_version_no;
UINT16 minor_version_no;
UINT16 command_set_supported_82; ///< word 82
UINT16 command_set_supported_83; ///< word 83
UINT16 command_set_feature_extn; ///< word 84
UINT16 command_set_feature_enb_85; ///< word 85
UINT16 command_set_feature_enb_86; ///< word 86
UINT16 command_set_feature_default; ///< word 87
UINT16 ultra_dma_mode; ///< word 88
UINT16 time_for_security_erase_unit;
UINT16 time_for_enhanced_security_erase_unit;
UINT16 advanced_power_management_level;
UINT16 master_password_identifier;
UINT16 hardware_configuration_test_result;
UINT16 obsolete_94;
UINT16 stream_minimum_request_size;
UINT16 streaming_transfer_time_for_dma;
UINT16 streaming_access_latency_for_dma_and_pio;
UINT16 streaming_performance_granularity[2]; ///< word 98~99
UINT16 maximum_lba_for_48bit_addressing[4]; ///< word 100~103
UINT16 streaming_transfer_time_for_pio;
UINT16 max_no_of_512byte_blocks_per_data_set_cmd;
UINT16 phy_logic_sector_support; ///< word 106
UINT16 interseek_delay_for_iso7779;
UINT16 world_wide_name[4]; ///< word 108~111
UINT16 reserved_for_128bit_wwn_112_115[4];
UINT16 reserved_for_technical_report;
UINT16 logic_sector_size_lo; ///< word 117
UINT16 logic_sector_size_hi; ///< word 118
UINT16 features_and_command_sets_supported_ext; ///< word 119
UINT16 features_and_command_sets_enabled_ext; ///< word 120
UINT16 reserved_121_126[6];
UINT16 obsolete_127;
UINT16 security_status; ///< word 128
UINT16 vendor_specific_129_159[31];
UINT16 cfa_power_mode; ///< word 160
UINT16 reserved_for_compactflash_161_167[7];
UINT16 device_nominal_form_factor;
UINT16 is_data_set_cmd_supported;
CHAR8 additional_product_identifier[8];
UINT16 reserved_174_175[2];
CHAR8 media_serial_number[60]; ///< word 176~205
UINT16 sct_command_transport; ///< word 206
UINT16 reserved_207_208[2];
UINT16 alignment_logic_in_phy_blocks; ///< word 209
UINT16 write_read_verify_sector_count_mode3[2]; ///< word 210~211
UINT16 verify_sector_count_mode2[2];
UINT16 nv_cache_capabilities;
UINT16 nv_cache_size_in_logical_block_lsw; ///< word 215
UINT16 nv_cache_size_in_logical_block_msw; ///< word 216
UINT16 nominal_media_rotation_rate;
UINT16 reserved_218;
UINT16 nv_cache_options; ///< word 219
UINT16 write_read_verify_mode; ///< word 220
UINT16 reserved_221;
UINT16 transport_major_revision_number;
UINT16 transport_minor_revision_number;
UINT16 reserved_224_229[6];
UINT64 extended_no_of_addressable_sectors;
UINT16 min_number_per_download_microcode_mode3; ///< word 234
UINT16 max_number_per_download_microcode_mode3; ///< word 235
UINT16 reserved_236_254[19];
UINT16 integrity_word;
} ATA_IDENTIFY_DATA;
///
/// ATAPI_IDENTIFY_DATA strictly complies with ATA/ATAPI-8 Spec
/// to define the data returned by an ATAPI device upon successful
/// completion of the ATA IDENTIFY_PACKET_DEVICE command.
///
typedef struct {
UINT16 config; ///< General Configuration.
UINT16 reserved_1;
UINT16 specific_config; ///< Specific Configuration.
UINT16 reserved_3_9[7];
CHAR8 SerialNo[20]; ///< word 10~19
UINT16 reserved_20_22[3];
CHAR8 FirmwareVer[8]; ///< word 23~26
CHAR8 ModelName[40]; ///< word 27~46
UINT16 reserved_47_48[2];
UINT16 capabilities_49;
UINT16 capabilities_50;
UINT16 obsolete_51;
UINT16 reserved_52;
UINT16 field_validity; ///< word 53
UINT16 reserved_54_61[8];
UINT16 dma_dir;
UINT16 multi_word_dma_mode; ///< word 63
UINT16 advanced_pio_modes; ///< word 64
UINT16 min_multi_word_dma_cycle_time;
UINT16 rec_multi_word_dma_cycle_time;
UINT16 min_pio_cycle_time_without_flow_control;
UINT16 min_pio_cycle_time_with_flow_control;
UINT16 reserved_69_70[2];
UINT16 obsolete_71_72[2];
UINT16 reserved_73_74[2];
UINT16 obsolete_75;
UINT16 serial_ata_capabilities;
UINT16 reserved_77; ///< Reserved for Serial ATA
UINT16 serial_ata_features_supported;
UINT16 serial_ata_features_enabled;
UINT16 major_version_no; ///< word 80
UINT16 minor_version_no; ///< word 81
UINT16 cmd_set_support_82;
UINT16 cmd_set_support_83;
UINT16 cmd_feature_support;
UINT16 cmd_feature_enable_85;
UINT16 cmd_feature_enable_86;
UINT16 cmd_feature_default;
UINT16 ultra_dma_select;
UINT16 time_required_for_sec_erase; ///< word 89
UINT16 time_required_for_enhanced_sec_erase; ///< word 90
UINT16 advanced_power_management_level;
UINT16 master_pwd_revison_code;
UINT16 hardware_reset_result; ///< word 93
UINT16 obsolete_94;
UINT16 reserved_95_107[13];
UINT16 world_wide_name[4]; ///< word 108~111
UINT16 reserved_for_128bit_wwn_112_115[4];
UINT16 reserved_116_118[3];
UINT16 command_and_feature_sets_supported; ///< word 119
UINT16 command_and_feature_sets_supported_enabled;
UINT16 reserved_121_124[4];
UINT16 atapi_byte_count_0_behavior; ///< word 125
UINT16 obsolete_126_127[2];
UINT16 security_status;
UINT16 reserved_129_159[31];
UINT16 cfa_reserved_160_175[16];
UINT16 reserved_176_221[46];
UINT16 transport_major_version;
UINT16 transport_minor_version;
UINT16 reserved_224_254[31];
UINT16 integrity_word;
} ATAPI_IDENTIFY_DATA;
///
/// Standard Quiry Data format, defined in SFF-8070i(ATAPI Removable Rewritable Specification).
///
typedef struct {
UINT8 peripheral_type;
UINT8 RMB;
UINT8 version;
UINT8 response_data_format;
UINT8 addnl_length; ///< n - 4, Numbers of bytes following this one.
UINT8 reserved_5;
UINT8 reserved_6;
UINT8 reserved_7;
UINT8 vendor_info[8];
UINT8 product_id[16];
UINT8 product_revision_level[4];
UINT8 vendor_specific_36_55[55 - 36 + 1];
UINT8 reserved_56_95[95 - 56 + 1];
///
/// Vendor-specific parameters fields. The sizeof (ATAPI_INQUIRY_DATA) is 254
/// since allocation_length is one byte in ATAPI_INQUIRY_CMD.
///
UINT8 vendor_specific_96_253[253 - 96 + 1];
} ATAPI_INQUIRY_DATA;
///
/// Request Sense Standard Data, defined in SFF-8070i(ATAPI Removable Rewritable Specification).
///
typedef struct {
UINT8 error_code : 7;
UINT8 valid : 1;
UINT8 reserved_1;
UINT8 sense_key : 4;
UINT8 reserved_2 : 1;
UINT8 Vendor_specifc_1 : 3;
UINT8 vendor_specific_3;
UINT8 vendor_specific_4;
UINT8 vendor_specific_5;
UINT8 vendor_specific_6;
UINT8 addnl_sense_length; ///< n - 7
UINT8 vendor_specific_8;
UINT8 vendor_specific_9;
UINT8 vendor_specific_10;
UINT8 vendor_specific_11;
UINT8 addnl_sense_code; ///< mandatory
UINT8 addnl_sense_code_qualifier; ///< mandatory
UINT8 field_replaceable_unit_code; ///< optional
UINT8 sense_key_specific_15 : 7;
UINT8 SKSV : 1;
UINT8 sense_key_specific_16;
UINT8 sense_key_specific_17;
} ATAPI_REQUEST_SENSE_DATA;
///
/// READ CAPACITY Data, defined in SFF-8070i(ATAPI Removable Rewritable Specification).
///
typedef struct {
UINT8 LastLba3;
UINT8 LastLba2;
UINT8 LastLba1;
UINT8 LastLba0;
UINT8 BlockSize3;
UINT8 BlockSize2;
UINT8 BlockSize1;
UINT8 BlockSize0;
} ATAPI_READ_CAPACITY_DATA;
///
/// Capacity List Header + Current/Maximum Capacity Descriptor,
/// defined in SFF-8070i(ATAPI Removable Rewritable Specification).
///
typedef struct {
UINT8 reserved_0;
UINT8 reserved_1;
UINT8 reserved_2;
UINT8 Capacity_Length;
UINT8 LastLba3;
UINT8 LastLba2;
UINT8 LastLba1;
UINT8 LastLba0;
UINT8 DesCode : 2;
UINT8 reserved_9 : 6;
UINT8 BlockSize2;
UINT8 BlockSize1;
UINT8 BlockSize0;
} ATAPI_READ_FORMAT_CAPACITY_DATA;
///
/// Test Unit Ready Command, defined in SFF-8070i(ATAPI Removable Rewritable Specification).
///
typedef struct {
UINT8 opcode;
UINT8 reserved_1;
UINT8 reserved_2;
UINT8 reserved_3;
UINT8 reserved_4;
UINT8 reserved_5;
UINT8 reserved_6;
UINT8 reserved_7;
UINT8 reserved_8;
UINT8 reserved_9;
UINT8 reserved_10;
UINT8 reserved_11;
} ATAPI_TEST_UNIT_READY_CMD;
///
/// INQUIRY Command, defined in SFF-8070i(ATAPI Removable Rewritable Specification).
///
typedef struct {
UINT8 opcode;
UINT8 reserved_1 : 5;
UINT8 lun : 3;
UINT8 page_code; ///< defined in SFF8090i, V6
UINT8 reserved_3;
UINT8 allocation_length;
UINT8 reserved_5;
UINT8 reserved_6;
UINT8 reserved_7;
UINT8 reserved_8;
UINT8 reserved_9;
UINT8 reserved_10;
UINT8 reserved_11;
} ATAPI_INQUIRY_CMD;
///
/// REQUEST SENSE Command, defined in SFF-8070i(ATAPI Removable Rewritable Specification).
///
typedef struct {
UINT8 opcode;
UINT8 reserved_1 : 5;
UINT8 lun : 3;
UINT8 reserved_2;
UINT8 reserved_3;
UINT8 allocation_length;
UINT8 reserved_5;
UINT8 reserved_6;
UINT8 reserved_7;
UINT8 reserved_8;
UINT8 reserved_9;
UINT8 reserved_10;
UINT8 reserved_11;
} ATAPI_REQUEST_SENSE_CMD;
///
/// READ (10) Command, defined in SFF-8070i(ATAPI Removable Rewritable Specification).
///
typedef struct {
UINT8 opcode;
UINT8 reserved_1 : 5;
UINT8 lun : 3;
UINT8 Lba0;
UINT8 Lba1;
UINT8 Lba2;
UINT8 Lba3;
UINT8 reserved_6;
UINT8 TranLen0;
UINT8 TranLen1;
UINT8 reserved_9;
UINT8 reserved_10;
UINT8 reserved_11;
} ATAPI_READ10_CMD;
///
/// READ Format Capacity Command, defined in SFF-8070i(ATAPI Removable Rewritable Specification).
///
typedef struct {
UINT8 opcode;
UINT8 reserved_1 : 5;
UINT8 lun : 3;
UINT8 reserved_2;
UINT8 reserved_3;
UINT8 reserved_4;
UINT8 reserved_5;
UINT8 reserved_6;
UINT8 allocation_length_hi;
UINT8 allocation_length_lo;
UINT8 reserved_9;
UINT8 reserved_10;
UINT8 reserved_11;
} ATAPI_READ_FORMAT_CAP_CMD;
///
/// MODE SENSE Command, defined in SFF-8070i(ATAPI Removable Rewritable Specification).
///
typedef struct {
UINT8 opcode;
UINT8 reserved_1 : 5;
UINT8 lun : 3;
UINT8 page_code : 6;
UINT8 page_control : 2;
UINT8 reserved_3;
UINT8 reserved_4;
UINT8 reserved_5;
UINT8 reserved_6;
UINT8 parameter_list_length_hi;
UINT8 parameter_list_length_lo;
UINT8 reserved_9;
UINT8 reserved_10;
UINT8 reserved_11;
} ATAPI_MODE_SENSE_CMD;
///
/// ATAPI_PACKET_COMMAND is not defined in the ATA specification.
/// We add it here for the convenience of ATA/ATAPI module writers.
///
typedef union {
UINT16 Data16[6];
ATAPI_TEST_UNIT_READY_CMD TestUnitReady;
ATAPI_READ10_CMD Read10;
ATAPI_REQUEST_SENSE_CMD RequestSence;
ATAPI_INQUIRY_CMD Inquiry;
ATAPI_MODE_SENSE_CMD ModeSense;
ATAPI_READ_FORMAT_CAP_CMD ReadFormatCapacity;
} ATAPI_PACKET_COMMAND;
#pragma pack()
#define ATAPI_MAX_DMA_EXT_CMD_SECTORS 0x10000
#define ATAPI_MAX_DMA_CMD_SECTORS 0x100
// ATA/ATAPI Signature equates
#define ATA_SIGNATURE 0x0101 ///< defined in ACS-3
#define ATAPI_SIGNATURE 0xeb14 ///< defined in ACS-3
#define ATAPI_SIGNATURE_32 0xeb140101 ///< defined in ACS-3
// Spin Up Configuration definitions
#define ATA_SPINUP_CFG_REQUIRED_IDD_INCOMPLETE 0x37c8 ///< defined in ACS-3
#define ATA_SPINUP_CFG_REQUIRED_IDD_COMPLETE 0x738c ///< defined in ACS-3
#define ATA_SPINUP_CFG_NOT_REQUIRED_IDD_INCOMPLETE 0x8c73 ///< defined in ACS-3
#define ATA_SPINUP_CFG_NOT_REQUIRED_IDD_COMPLETE 0xc837 ///< defined in ACS-3
//
// ATA Packet Command Code
//
#define ATA_CMD_FORMAT_UNIT 0x04 ///< defined in ATAPI Removable Rewritable Media Devices
#define ATA_CMD_SOFT_RESET 0x08 ///< defined from ATA-3
#define ATA_CMD_PACKET 0xA0 ///< defined from ATA-3
#define ATA_CMD_IDENTIFY_DEVICE 0xA1 ///< defined from ATA-3
#define ATA_CMD_SERVICE 0xA2 ///< defined from ATA-3
#define ATA_CMD_TEST_UNIT_READY 0x00 ///< defined from ATA-1
#define ATA_CMD_REQUEST_SENSE 0x03 ///< defined from ATA-4
#define ATA_CMD_INQUIRY 0x12 ///< defined in ATAPI Removable Rewritable Media Devices
#define ATA_CMD_READ_FORMAT_CAPACITY 0x23 ///< defined in ATAPI Removable Rewritable Media Devices
#define ATA_CMD_READ_CAPACITY 0x25 ///< defined in ATAPI Removable Rewritable Media Devices
#define ATA_CMD_READ_10 0x28 ///< defined in ATAPI Removable Rewritable Media Devices
#define ATA_CMD_WRITE_10 0x2A ///< defined in ATAPI Removable Rewritable Media Devices
#define ATA_CMD_ATAPI_SEEK 0x2B ///< defined in ATAPI Removable Rewritable Media Devices
#define ATA_CMD_WRITE_AND_VERIFY 0x2E ///< defined in ATAPI Removable Rewritable Media Devices
#define ATA_CMD_VERIFY 0x2F ///< defined in ATAPI Removable Rewritable Media Devices
#define ATA_CMD_READ_12 0xA8 ///< defined in ATAPI Removable Rewritable Media Devices
#define ATA_CMD_WRITE_12 0xAA ///< defined in ATAPI Removable Rewritable Media Devices
#define ATA_CMD_START_STOP_UNIT 0x1B ///< defined in ATAPI Removable Rewritable Media Devices
#define ATA_CMD_PREVENT_ALLOW_MEDIA_REMOVAL 0x1E ///< defined in ATAPI Removable Rewritable Media Devices
#define ATA_CMD_MODE_SELECT 0x55 ///< defined in ATAPI Removable Rewritable Media Devices
#define ATA_CMD_MODE_SENSE 0x5A ///< defined in ATAPI Removable Rewritable Media Devices
#define ATA_PAGE_CODE_READ_WRITE_ERROR 0x01 ///< defined in ATAPI Removable Rewritable Media Devices
#define ATA_PAGE_CODE_CACHING_PAGE 0x08 ///< defined in ATAPI Removable Rewritable Media Devices
#define ATA_PAGE_CODE_REMOVABLE_BLOCK_CAPABILITIES 0x1B ///< defined in ATAPI Removable Rewritable Media Devices
#define ATA_PAGE_CODE_TIMER_PROTECT_PAGE 0x1C ///< defined in ATAPI Removable Rewritable Media Devices
#define ATA_PAGE_CODE_RETURN_ALL_PAGES 0x3F ///< defined in ATAPI Removable Rewritable Media Devices
#define ATA_CMD_GET_CONFIGURATION 0x46 ///< defined in ATAPI Multimedia Devices
#define ATA_GCCD_RT_FIELD_VALUE_ALL 0x00 ///< defined in ATAPI Multimedia Devices
#define ATA_GCCD_RT_FIELD_VALUE_CURRENT 0x01 ///< defined in ATAPI Multimedia Devices
#define ATA_GCCD_RT_FIELD_VALUE_SINGLE 0x02 ///< defined in ATAPI Multimedia Devices
#define ATA_GCCD_RT_FIELD_VALUE_RESERVED 0x03 ///< defined in ATAPI Multimedia Devices
#define ATA_FEATURE_LIST_PROFILE_LIST 0x0000 ///< defined in ATAPI Multimedia Devices
#define ATA_FEATURE_LIST_CORE 0x0001 ///< defined in ATAPI Multimedia Devices
#define ATA_FEATURE_LIST_MORPHING 0x0002 ///< defined in ATAPI Multimedia Devices
#define ATA_FEATURE_LIST_REMOVEABLE_MEDIUM 0x0003 ///< defined in ATAPI Multimedia Devices
#define ATA_FEATURE_LIST_WRITE_PROTECT 0x0004 ///< defined in ATAPI Multimedia Devices
///
/// Start/Stop and Eject Operations
///
///@{
#define ATA_CMD_SUBOP_STOP_DISC 0x00 ///< Stop the Disc
#define ATA_CMD_SUBOP_START_DISC 0x01 ///< Start the Disc and acquire the format type
#define ATA_CMD_SUBOP_EJECT_DISC 0x02 ///< Eject the Disc if possible
#define ATA_CMD_SUBOP_CLOSE_TRAY 0x03 ///< Load the Disc (Close Tray)
///@}
//
// ATA Commands Code
//
//
// Class 1: PIO Data-In Commands
//
#define ATA_CMD_IDENTIFY_DRIVE 0xec ///< defined from ATA-3
#define ATA_CMD_READ_BUFFER 0xe4 ///< defined from ATA-1
#define ATA_CMD_READ_SECTORS 0x20 ///< defined from ATA-1
#define ATA_CMD_READ_SECTORS_WITH_RETRY 0x21 ///< defined from ATA-1, obsoleted from ATA-5
#define ATA_CMD_READ_LONG 0x22 ///< defined from ATA-1, obsoleted from ATA-5
#define ATA_CMD_READ_LONG_WITH_RETRY 0x23 ///< defined from ATA-1, obsoleted from ATA-5
#define ATA_CMD_READ_SECTORS_EXT 0x24 ///< defined from ATA-6
#define ATA_CMD_READ_MULTIPLE 0xc4 ///< defined in ACS-3
#define ATA_CMD_READ_MULTIPLE_EXT 0x29 ///< defined in ACS-3
#define ATA_CMD_READ_LOG_EXT 0x2f ///< defined in ACS-3
//
// Class 2: PIO Data-Out Commands
//
#define ATA_CMD_FORMAT_TRACK 0x50 ///< defined from ATA-1, obsoleted from ATA-4
#define ATA_CMD_WRITE_BUFFER 0xe8 ///< defined from ATA-1
#define ATA_CMD_WRITE_SECTORS 0x30 ///< defined from ATA-1
#define ATA_CMD_WRITE_SECTORS_WITH_RETRY 0x31 ///< defined from ATA-1, obsoleted from ATA-5
#define ATA_CMD_WRITE_LONG 0x32 ///< defined from ATA-1, obsoleted from ATA-5
#define ATA_CMD_WRITE_LONG_WITH_RETRY 0x33 ///< defined from ATA-1, obsoleted from ATA-5
#define ATA_CMD_WRITE_VERIFY 0x3c ///< defined from ATA-1, obsoleted from ATA-5
#define ATA_CMD_WRITE_SECTORS_EXT 0x34 ///< defined from ATA-6
#define ATA_CMD_WRITE_MULTIPLE 0xc5 ///< defined in ACS-3
#define ATA_CMD_WRITE_MULTIPLE_EXT 0x39 ///< defined in ACS-3
//
// Class 3 No Data Command
//
#define ATA_CMD_ACK_MEDIA_CHANGE 0xdb ///< defined from ATA-1, obsoleted from ATA-5
#define ATA_CMD_BOOT_POST_BOOT 0xdc ///< defined from ATA-1, obsoleted from ATA-3
#define ATA_CMD_BOOT_PRE_BOOT 0xdd ///< defined from ATA-1, obsoleted from ATA-3
#define ATA_CMD_CHECK_POWER_MODE 0x98 ///< defined from ATA-1, obsoleted from ATA-4
#define ATA_CMD_CHECK_POWER_MODE_ALIAS 0xe5 ///< defined from ATA-1
#define ATA_CMD_DOOR_LOCK 0xde ///< defined from ATA-1
#define ATA_CMD_DOOR_UNLOCK 0xdf ///< defined from ATA-1
#define ATA_CMD_EXEC_DRIVE_DIAG 0x90 ///< defined from ATA-1
#define ATA_CMD_IDLE_ALIAS 0x97 ///< defined from ATA-1, obsoleted from ATA-4
#define ATA_CMD_IDLE 0xe3 ///< defined from ATA-1
#define ATA_CMD_IDLE_IMMEDIATE 0x95 ///< defined from ATA-1, obsoleted from ATA-4
#define ATA_CMD_IDLE_IMMEDIATE_ALIAS 0xe1 ///< defined from ATA-1
#define ATA_CMD_INIT_DRIVE_PARAM 0x91 ///< defined from ATA-1, obsoleted from ATA-6
#define ATA_CMD_RECALIBRATE 0x10 ///< defined from ATA-1, obsoleted from ATA-4
#define ATA_CMD_READ_DRIVE_STATE 0xe9 ///< defined from ATA-1, obsoleted from ATA-3
#define ATA_CMD_SET_MULTIPLE_MODE 0xC6 ///< defined from ATA-2
#define ATA_CMD_READ_VERIFY 0x40 ///< defined from ATA-1
#define ATA_CMD_READ_VERIFY_WITH_RETRY 0x41 ///< defined from ATA-1, obsoleted from ATA-5
#define ATA_CMD_SEEK 0x70 ///< defined from ATA-1
#define ATA_CMD_SET_FEATURES 0xef ///< defined from ATA-1
#define ATA_CMD_STANDBY 0x96 ///< defined from ATA-1, obsoleted from ATA-4
#define ATA_CMD_STANDBY_ALIAS 0xe2 ///< defined from ATA-1
#define ATA_CMD_STANDBY_IMMEDIATE 0x94 ///< defined from ATA-1, obsoleted from ATA-4
#define ATA_CMD_STANDBY_IMMEDIATE_ALIAS 0xe0 ///< defined from ATA-1
#define ATA_CMD_SLEEP 0xe6 ///< defined in ACS-3
#define ATA_CMD_READ_NATIVE_MAX_ADDRESS 0xf8 ///< defined in ATA-6
#define ATA_CMD_READ_NATIVE_MAX_ADDRESS_EXT 0x27 ///< defined in ATA-6
//
// Set Features Sub Command
//
#define ATA_SUB_CMD_ENABLE_VOLATILE_WRITE_CACHE 0x02 ///< defined in ACS-3
#define ATA_SUB_CMD_SET_TRANSFER_MODE 0x03 ///< defined in ACS-3
#define ATA_SUB_CMD_ENABLE_APM 0x05 ///< defined in ACS-3
#define ATA_SUB_CMD_ENABLE_PUIS 0x06 ///< defined in ACS-3
#define ATA_SUB_CMD_PUIS_SET_DEVICE_SPINUP 0x07 ///< defined in ACS-3
#define ATA_SUB_CMD_ENABLE_WRITE_READ_VERIFY 0x0b ///< defined in ACS-3
#define ATA_SUB_CMD_ENABLE_SATA_FEATURE 0x10 ///< defined in ACS-3
#define ATA_SUB_CMD_DISABLE_MEDIA_STATUS_NOTIFICATION 0x31 ///< defined in ACS-3
#define ATA_SUB_CMD_ENABLE_FREE_FALL_CONTROL 0x41 ///< defined in ACS-3
#define ATA_SUB_CMD_ACOUSTIC_MANAGEMENT_ENABLE 0x42 ///< defined in ACS-3
#define ATA_SUB_CMD_SET_MAX_HOST_INTERFACE_SECTOR_TIMES 0x43 ///< defined in ACS-3
#define ATA_SUB_CMD_EXTENDED_POWER_CONDITIONS 0x4a ///< defined in ACS-3
#define ATA_SUB_CMD_DISABLE_READ_LOOK_AHEAD 0x55 ///< defined in ACS-3
#define ATA_SUB_CMD_EN_DIS_DSN_FEATURE 0x63 ///< defined in ACS-3
#define ATA_SUB_CMD_DISABLE_REVERT_TO_POWER_ON_DEFAULTS 0x66 ///< defined in ACS-3
#define ATA_SUB_CMD_DISABLE_VOLATILE_WRITE_CACHE 0x82 ///< defined in ACS-3
#define ATA_SUB_CMD_DISABLE_APM 0x85 ///< defined in ACS-3
#define ATA_SUB_CMD_DISABLE_PUIS 0x86 ///< defined in ACS-3
#define ATA_SUB_CMD_DISABLE_WRITE_READ_VERIFY 0x8b ///< defined in ACS-3
#define ATA_SUB_CMD_DISABLE_SATA_FEATURE 0x90 ///< defined in ACS-3
#define ATA_SUB_CMD_ENABLE_MEDIA_STATUS_NOTIFICATION 0x95 ///< defined in ACS-3
#define ATA_SUB_CMD_ENABLE_READ_LOOK_AHEAD 0xaa ///< defined in ACS-3
#define ATA_SUB_CMD_DISABLE_FREE_FALL_CONTROL 0xc1 ///< defined in ACS-3
#define ATA_SUB_CMD_ACOUSTIC_MANAGEMENT_DISABLE 0xc2 ///< defined in ACS-3
#define ATA_SUB_CMD_EN_DIS_SENSE_DATA_REPORTING 0xc3 ///< defined in ACS-3
#define ATA_SUB_CMD_ENABLE_REVERT_TO_POWER_ON_DEFAULTS 0xcc ///< defined in ACS-3
//
// S.M.A.R.T
//
#define ATA_CMD_SMART 0xb0 ///< defined from ATA-3
#define ATA_CONSTANT_C2 0xc2 ///< reserved
#define ATA_CONSTANT_4F 0x4f ///< reserved
#define ATA_SMART_READ_DATA 0xd0 ///< defined in ACS-3
#define ATA_SMART_AUTOSAVE 0xd2 ///< defined in ACS-3
#define ATA_AUTOSAVE_DISABLE_ATTR 0x00
#define ATA_AUTOSAVE_ENABLE_ATTR 0xf1
#define ATA_SMART_EXECUTE_OFFLINE_IMMEDIATE 0xd4 ///< defined in ACS-3
#define ATA_EXECUTE_SMART_OFFLINE_ROUTINE 0x00 ///< defined in ACS-3
#define ATA_EXECUTE_SMART_OFFLINE_SHORT_SELFTEST 0x01 ///< defined in ACS-3
#define ATA_EXECUTE_SMART_OFFLINE_EXTENDED_SELFTEST 0x02 ///< defined in ACS-3
#define ATA_EXECUTE_SMART_OFFLINE_CONVEYANCE_SELFTEST 0x03 ///< defined in ACS-3
#define ATA_EXECUTE_SMART_OFFLINE_SELECTIVE_SELFTEST 0x04 ///< defined in ACS-3
#define ATA_SMART_ABORT_SELF_TEST_SUBROUTINE 0x7f ///< defined in ACS-3
#define ATA_EXECUTE_SMART_CAPTIVE_SHORT_SELFTEST 0x81 ///< defined in ACS-3
#define ATA_EXECUTE_SMART_CAPTIVE_EXTENDED_SELFTEST 0x82 ///< defined in ACS-3
#define ATA_EXECUTE_SMART_CAPTIVE_CONVEYANCE_SELFTEST 0x83 ///< defined in ACS-3
#define ATA_EXECUTE_SMART_CAPTIVE_SELECTIVE_SELFTEST 0x84 ///< defined in ACS-3
#define ATA_SMART_READLOG 0xd5 ///< defined in ACS-3
#define ATA_SMART_WRITELOG 0xd6 ///< defined in ACS-3
#define ATA_SMART_ENABLE_OPERATION 0xd8 ///< reserved
#define ATA_SMART_DISABLE_OPERATION 0xd9 ///< defined in ACS-3
#define ATA_SMART_RETURN_STATUS 0xda ///< defined from ATA-3
#define ATA_SMART_THRESHOLD_NOT_EXCEEDED_VALUE 0xc24f ///< defined in ACS-3
#define ATA_SMART_THRESHOLD_EXCEEDED_VALUE 0x2cf4 ///< defined in ACS-3
// SMART Log Definitions
#define ATA_SMART_LOG_DIRECTORY 0x00 ///< defined in ACS-3
#define ATA_SMART_SUM_SMART_ERROR_LOG 0x01 ///< defined in ACS-3
#define ATA_SMART_COMP_SMART_ERROR_LOG 0x02 ///< defined in ACS-3
#define ATA_SMART_EXT_COMP_SMART_ERROR_LOG 0x03 ///< defined in ACS-3
#define ATA_SMART_SMART_SELFTEST_LOG 0x06 ///< defined in ACS-3
#define ATA_SMART_EXT_SMART_SELFTEST_LOG 0x07 ///< defined in ACS-3
#define ATA_SMART_SELECTIVE_SELFTEST_LOG 0x09 ///< defined in ACS-3
#define ATA_SMART_HOST_VENDOR_SPECIFIC 0x80 ///< defined in ACS-3
#define ATA_SMART_DEVICE_VENDOR_SPECIFIC 0xa0 ///< defined in ACS-3
//
// Class 4: DMA Command
//
#define ATA_CMD_READ_DMA 0xc8 ///< defined from ATA-1
#define ATA_CMD_READ_DMA_WITH_RETRY 0xc9 ///< defined from ATA-1, obsoleted from ATA-5
#define ATA_CMD_READ_DMA_EXT 0x25 ///< defined from ATA-6
#define ATA_CMD_WRITE_DMA 0xca ///< defined from ATA-1
#define ATA_CMD_WRITE_DMA_WITH_RETRY 0xcb ///< defined from ATA-1, obsoleted from ATA-
#define ATA_CMD_WRITE_DMA_EXT 0x35 ///< defined from ATA-6
//
// ATA Security commands
//
#define ATA_CMD_SECURITY_SET_PASSWORD 0xf1 ///< defined in ACS-3
#define ATA_CMD_SECURITY_UNLOCK 0xf2 ///< defined in ACS-3
#define ATA_CMD_SECURITY_ERASE_PREPARE 0xf3 ///< defined in ACS-3
#define ATA_CMD_SECURITY_ERASE_UNIT 0xf4 ///< defined in ACS-3
#define ATA_CMD_SECURITY_FREEZE_LOCK 0xf5 ///< defined in ACS-3
#define ATA_CMD_SECURITY_DISABLE_PASSWORD 0xf6 ///< defined in ACS-3
#define ATA_SECURITY_BUFFER_LENGTH 512 ///< defined in ACS-3
//
// ATA Device Config Overlay
//
#define ATA_CMD_DEV_CONFIG_OVERLAY 0xb1 ///< defined from ATA-6
#define ATA_CMD_DEV_CONFIG_RESTORE_FEATURE 0xc0 ///< defined from ATA-6
#define ATA_CMD_DEV_CONFIG_FREEZELOCK_FEATURE 0xc1 ///< defined from ATA-6
#define ATA_CMD_DEV_CONFIG_IDENTIFY_FEATURE 0xc2 ///< defined from ATA-6
#define ATA_CMD_DEV_CONFIG_SET_FEATURE 0xc3 ///< defined from ATA-6
//
// ATA Trusted Computing Feature Set Commands
//
#define ATA_CMD_TRUSTED_NON_DATA 0x5b ///< defined in ACS-3
#define ATA_CMD_TRUSTED_RECEIVE 0x5c ///< defined in ACS-3
#define ATA_CMD_TRUSTED_RECEIVE_DMA 0x5d ///< defined in ACS-3
#define ATA_CMD_TRUSTED_SEND 0x5e ///< defined in ACS-3
#define ATA_CMD_TRUSTED_SEND_DMA 0x5f ///< defined in ACS-3
//
// ATA Trusted Receive Fields
//
#define ATA_TR_RETURN_SECURITY_PROTOCOL_INFORMATION 0x00 ///< defined in ACS-3
#define ATA_TR_SECURITY_PROTOCOL_JEDEC_RESERVED 0xec ///< defined in ACS-3
#define ATA_TR_SECURITY_PROTOCOL_SDCARD_RESERVED 0xed ///< defined in ACS-3
#define ATA_TR_SECURITY_PROTOCOL_IEEE1667_RESERVED 0xee ///< defined in ACS-3
//
// Equates used for Acoustic Flags
//
#define ATA_ACOUSTIC_LEVEL_BYPASS 0xff ///< defined from ATA-6
#define ATA_ACOUSTIC_LEVEL_MAXIMUM_PERFORMANCE 0xfe ///< defined from ATA-6
#define ATA_ACOUSTIC_LEVEL_QUIET 0x80 ///< defined from ATA-6
//
// Equates used for DiPM Support
//
#define ATA_CMD_DIPM_SUB 0x03 // defined in ACS-3 : Count value in SetFeature identification : 03h Device-initiated interface power state transitions
#define ATA_DIPM_ENABLE 0x10 // defined in ACS-3
#define ATA_DIPM_DISABLE 0x90 // defined in ACS-3
//
// Equates used for DevSleep Support
//
#define ATA_CMD_DEVSLEEP_SUB 0x09 // defined in SATA 3.2 Gold Spec : Count value in SetFeature identification : 09h Device Sleep
#define ATA_DEVSLEEP_ENABLE 0x10 // defined in SATA 3.2 Gold Spec
#define ATA_DEVSLEEP_DISABLE 0x90 // defined in SATA 3.2 Gold Spec
#define ATA_DEVSLP_EXIT_TIMEOUT 20 // MDAT - 20 ms
#define ATA_DEVSLP_MINIMUM_DETECTION_TIME 10 // DMDT - 10 us
#define ATA_DEVSLP_MINIMUM_ASSERTION_TIME 10 // DETO - 10 ms
//
// Set MAX Commands
//
#define ATA_CMD_SET_MAX_ADDRESS_EXT 0x37 ///< defined from ATA-6
#define ATA_CMD_SET_MAX_ADDRESS 0xf9 ///< defined from ATA-6
#define ATA_SET_MAX_SET_PASSWORD 0x01 ///< defined from ATA-6
#define ATA_SET_MAX_LOCK 0x02 ///< defined from ATA-6
#define ATA_SET_MAX_UNLOCK 0x03 ///< defined from ATA-6
#define ATA_SET_MAX_FREEZE_LOCK 0x04 ///< defined from ATA-6
///
/// Default content of device control register, disable INT,
/// Bit3 is set to 1 according ATA-1
///
#define ATA_DEFAULT_CTL (0x0a)
///
/// Default context of Device/Head Register,
/// Bit7 and Bit5 are set to 1 for back-compatibilities.
///
#define ATA_DEFAULT_CMD (0xa0)
#define ATAPI_MAX_BYTE_COUNT (0xfffe)
#define ATA_REQUEST_SENSE_ERROR (0x70) ///< defined in SFF-8070i
//
// Sense Key, Additional Sense Codes and Additional Sense Code Qualifier
// defined in MultiMedia Commands (MMC, MMC-2)
//
// Sense Key
//
#define ATA_SK_NO_SENSE (0x0)
#define ATA_SK_RECOVERY_ERROR (0x1)
#define ATA_SK_NOT_READY (0x2)
#define ATA_SK_MEDIUM_ERROR (0x3)
#define ATA_SK_HARDWARE_ERROR (0x4)
#define ATA_SK_ILLEGAL_REQUEST (0x5)
#define ATA_SK_UNIT_ATTENTION (0x6)
#define ATA_SK_DATA_PROTECT (0x7)
#define ATA_SK_BLANK_CHECK (0x8)
#define ATA_SK_VENDOR_SPECIFIC (0x9)
#define ATA_SK_RESERVED_A (0xA)
#define ATA_SK_ABORT (0xB)
#define ATA_SK_RESERVED_C (0xC)
#define ATA_SK_OVERFLOW (0xD)
#define ATA_SK_MISCOMPARE (0xE)
#define ATA_SK_RESERVED_F (0xF)
//
// Additional Sense Codes
//
#define ATA_ASC_NOT_READY (0x04)
#define ATA_ASC_MEDIA_ERR1 (0x10)
#define ATA_ASC_MEDIA_ERR2 (0x11)
#define ATA_ASC_MEDIA_ERR3 (0x14)
#define ATA_ASC_MEDIA_ERR4 (0x30)
#define ATA_ASC_MEDIA_UPSIDE_DOWN (0x06)
#define ATA_ASC_INVALID_CMD (0x20)
#define ATA_ASC_LBA_OUT_OF_RANGE (0x21)
#define ATA_ASC_INVALID_FIELD (0x24)
#define ATA_ASC_WRITE_PROTECTED (0x27)
#define ATA_ASC_MEDIA_CHANGE (0x28)
#define ATA_ASC_RESET (0x29) ///< Power On Reset or Bus Reset occurred.
#define ATA_ASC_ILLEGAL_FIELD (0x26)
#define ATA_ASC_NO_MEDIA (0x3A)
#define ATA_ASC_ILLEGAL_MODE_FOR_THIS_TRACK (0x64)
//
// Additional Sense Code Qualifier
//
#define ATA_ASCQ_IN_PROGRESS (0x01)
//
// Error Register
//
#define ATA_ERRREG_BBK BIT7 ///< Bad block detected defined from ATA-1, obsoleted from ATA-2
#define ATA_ERRREG_UNC BIT6 ///< Uncorrectable Data defined from ATA-1, obsoleted from ATA-4
#define ATA_ERRREG_MC BIT5 ///< Media Change defined from ATA-1, obsoleted from ATA-4
#define ATA_ERRREG_IDNF BIT4 ///< ID Not Found defined from ATA-1, obsoleted from ATA-4
#define ATA_ERRREG_MCR BIT3 ///< Media Change Requested defined from ATA-1, obsoleted from ATA-4
#define ATA_ERRREG_ABRT BIT2 ///< Aborted Command defined from ATA-1
#define ATA_ERRREG_TK0NF BIT1 ///< Track 0 Not Found defined from ATA-1, obsoleted from ATA-4
#define ATA_ERRREG_AMNF BIT0 ///< Address Mark Not Found defined from ATA-1, obsoleted from ATA-4
//
// Status Register
//
#define ATA_STSREG_BSY BIT7 ///< Controller Busy defined from ATA-1
#define ATA_STSREG_DRDY BIT6 ///< Drive Ready defined from ATA-1
#define ATA_STSREG_DWF BIT5 ///< Drive Write Fault defined from ATA-1, obsoleted from ATA-4
#define ATA_STSREG_DF BIT5 ///< Drive Fault defined from ATA-6
#define ATA_STSREG_DSC BIT4 ///< Disk Seek Complete defined from ATA-1, obsoleted from ATA-4
#define ATA_STSREG_DRQ BIT3 ///< Data Request defined from ATA-1
#define ATA_STSREG_CORR BIT2 ///< Corrected Data defined from ATA-1, obsoleted from ATA-4
#define ATA_STSREG_IDX BIT1 ///< Index defined from ATA-1, obsoleted from ATA-4
#define ATA_STSREG_ERR BIT0 ///< Error defined from ATA-1
//
// Device Control Register
//
#define ATA_CTLREG_SRST BIT2 ///< Software Reset.
#define ATA_CTLREG_IEN_L BIT1 ///< Interrupt Enable #.
#endif

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/** @file
This file contains the Bluetooth definitions that are consumed by drivers.
These definitions are from Bluetooth Core Specification Version 4.0 June, 2010
Copyright (c) 2015 - 2017, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef _BLUETOOTH_H_
#define _BLUETOOTH_H_
#pragma pack(1)
///
/// BLUETOOTH_ADDRESS
///
typedef struct {
///
/// 48bit Bluetooth device address.
///
UINT8 Address[6];
} BLUETOOTH_ADDRESS;
///
/// BLUETOOTH_CLASS_OF_DEVICE. See Bluetooth specification for detail.
///
typedef struct {
UINT8 FormatType:2;
UINT8 MinorDeviceClass: 6;
UINT16 MajorDeviceClass: 5;
UINT16 MajorServiceClass:11;
} BLUETOOTH_CLASS_OF_DEVICE;
///
/// BLUETOOTH_LE_ADDRESS
///
typedef struct {
///
/// 48-bit Bluetooth device address
///
UINT8 Address[6];
///
/// 0x00 - Public Device Address
/// 0x01 - Random Device Address
///
UINT8 Type;
} BLUETOOTH_LE_ADDRESS;
#pragma pack()
#define BLUETOOTH_HCI_COMMAND_LOCAL_READABLE_NAME_MAX_SIZE 248
#define BLUETOOTH_HCI_LINK_KEY_SIZE 16
#endif

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/** @file
This file defines BMP file header data structures.
Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef _BMP_H_
#define _BMP_H_
#pragma pack(1)
typedef struct {
UINT8 Blue;
UINT8 Green;
UINT8 Red;
UINT8 Reserved;
} BMP_COLOR_MAP;
typedef struct {
CHAR8 CharB;
CHAR8 CharM;
UINT32 Size;
UINT16 Reserved[2];
UINT32 ImageOffset;
UINT32 HeaderSize;
UINT32 PixelWidth;
UINT32 PixelHeight;
UINT16 Planes; ///< Must be 1
UINT16 BitPerPixel; ///< 1, 4, 8, or 24
UINT32 CompressionType;
UINT32 ImageSize; ///< Compressed image size in bytes
UINT32 XPixelsPerMeter;
UINT32 YPixelsPerMeter;
UINT32 NumberOfColors;
UINT32 ImportantColors;
} BMP_IMAGE_HEADER;
#pragma pack()
#endif

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/** @file
Support for the latest CXL standard
The main header to reference all versions of CXL Base specification registers
from the MDE
Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef _CXL_MAIN_H_
#define _CXL_MAIN_H_
#include <IndustryStandard/Cxl11.h>
//
// CXL assigned new Vendor ID
//
#define CXL_DVSEC_VENDOR_ID 0x1E98
#endif

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/** @file
CXL 1.1 Register definitions
This file contains the register definitions based on the Compute Express Link
(CXL) Specification Revision 1.1.
Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef _CXL11_H_
#define _CXL11_H_
#include <IndustryStandard/Pci.h>
//
// DVSEC Vendor ID
// Compute Express Link Specification Revision: 1.1 - Chapter 7.1.1 - Table 58
// (subject to change as per CXL assigned Vendor ID)
//
#define INTEL_CXL_DVSEC_VENDOR_ID 0x8086
//
// CXL Flex Bus Device default device and function number
// Compute Express Link Specification Revision: 1.1 - Chapter 7.1.1
//
#define CXL_DEV_DEV 0
#define CXL_DEV_FUNC 0
//
// Ensure proper structure formats
//
#pragma pack(1)
/**
Macro used to verify the size of a data type at compile time and trigger a
STATIC_ASSERT() with an error message if the size of the data type does not
match the expected size.
@param TypeName Type name of data type to verify.
@param ExpectedSize The expected size, in bytes, of the data type specified
by TypeName.
**/
#define CXL_11_SIZE_ASSERT(TypeName, ExpectedSize) \
STATIC_ASSERT ( \
sizeof (TypeName) == ExpectedSize, \
"Size of " #TypeName \
" does not meet CXL 1.1 Specification requirements." \
)
/**
Macro used to verify the offset of a field in a data type at compile time and
trigger a STATIC_ASSERT() with an error message if the offset of the field in
the data type does not match the expected offset.
@param TypeName Type name of data type to verify.
@param FieldName Field name in the data type specified by TypeName to
verify.
@param ExpectedOffset The expected offset, in bytes, of the field specified
by TypeName and FieldName.
**/
#define CXL_11_OFFSET_ASSERT(TypeName, FieldName, ExpectedOffset) \
STATIC_ASSERT ( \
OFFSET_OF (TypeName, FieldName) == ExpectedOffset, \
"Offset of " #TypeName "." #FieldName \
" does not meet CXL 1.1 Specification requirements." \
)
///
/// The PCIe DVSEC for Flex Bus Device
///@{
typedef union {
struct {
UINT16 CacheCapable : 1; // bit 0
UINT16 IoCapable : 1; // bit 1
UINT16 MemCapable : 1; // bit 2
UINT16 MemHwInitMode : 1; // bit 3
UINT16 HdmCount : 2; // bit 4..5
UINT16 Reserved1 : 8; // bit 6..13
UINT16 ViralCapable : 1; // bit 14
UINT16 Reserved2 : 1; // bit 15
} Bits;
UINT16 Uint16;
} CXL_DVSEC_FLEX_BUS_DEVICE_CAPABILITY;
typedef union {
struct {
UINT16 CacheEnable : 1; // bit 0
UINT16 IoEnable : 1; // bit 1
UINT16 MemEnable : 1; // bit 2
UINT16 CacheSfCoverage : 5; // bit 3..7
UINT16 CacheSfGranularity : 3; // bit 8..10
UINT16 CacheCleanEviction : 1; // bit 11
UINT16 Reserved1 : 2; // bit 12..13
UINT16 ViralEnable : 1; // bit 14
UINT16 Reserved2 : 1; // bit 15
} Bits;
UINT16 Uint16;
} CXL_DVSEC_FLEX_BUS_DEVICE_CONTROL;
typedef union {
struct {
UINT16 Reserved1 : 14; // bit 0..13
UINT16 ViralStatus : 1; // bit 14
UINT16 Reserved2 : 1; // bit 15
} Bits;
UINT16 Uint16;
} CXL_DVSEC_FLEX_BUS_DEVICE_STATUS;
typedef union {
struct {
UINT16 Reserved1 : 1; // bit 0
UINT16 Reserved2 : 1; // bit 1
UINT16 Reserved3 : 1; // bit 2
UINT16 Reserved4 : 13; // bit 3..15
} Bits;
UINT16 Uint16;
} CXL_1_1_DVSEC_FLEX_BUS_DEVICE_CONTROL2;
typedef union {
struct {
UINT16 Reserved1 : 1; // bit 0
UINT16 Reserved2 : 1; // bit 1
UINT16 Reserved3 : 14; // bit 2..15
} Bits;
UINT16 Uint16;
} CXL_1_1_DVSEC_FLEX_BUS_DEVICE_STATUS2;
typedef union {
struct {
UINT16 ConfigLock : 1; // bit 0
UINT16 Reserved1 : 15; // bit 1..15
} Bits;
UINT16 Uint16;
} CXL_DVSEC_FLEX_BUS_DEVICE_LOCK;
typedef union {
struct {
UINT32 MemorySizeHigh : 32; // bit 0..31
} Bits;
UINT32 Uint32;
} CXL_DVSEC_FLEX_BUS_DEVICE_RANGE1_SIZE_HIGH;
typedef union {
struct {
UINT32 MemoryInfoValid : 1; // bit 0
UINT32 MemoryActive : 1; // bit 1
UINT32 MediaType : 3; // bit 2..4
UINT32 MemoryClass : 3; // bit 5..7
UINT32 DesiredInterleave : 3; // bit 8..10
UINT32 Reserved : 17; // bit 11..27
UINT32 MemorySizeLow : 4; // bit 28..31
} Bits;
UINT32 Uint32;
} CXL_DVSEC_FLEX_BUS_DEVICE_RANGE1_SIZE_LOW;
typedef union {
struct {
UINT32 MemoryBaseHigh : 32; // bit 0..31
} Bits;
UINT32 Uint32;
} CXL_DVSEC_FLEX_BUS_DEVICE_RANGE1_BASE_HIGH;
typedef union {
struct {
UINT32 Reserved : 28; // bit 0..27
UINT32 MemoryBaseLow : 4; // bit 28..31
} Bits;
UINT32 Uint32;
} CXL_DVSEC_FLEX_BUS_DEVICE_RANGE1_BASE_LOW;
typedef union {
struct {
UINT32 MemorySizeHigh : 32; // bit 0..31
} Bits;
UINT32 Uint32;
} CXL_DVSEC_FLEX_BUS_DEVICE_RANGE2_SIZE_HIGH;
typedef union {
struct {
UINT32 MemoryInfoValid : 1; // bit 0
UINT32 MemoryActive : 1; // bit 1
UINT32 MediaType : 3; // bit 2..4
UINT32 MemoryClass : 3; // bit 5..7
UINT32 DesiredInterleave : 3; // bit 8..10
UINT32 Reserved : 17; // bit 11..27
UINT32 MemorySizeLow : 4; // bit 28..31
} Bits;
UINT32 Uint32;
} CXL_DVSEC_FLEX_BUS_DEVICE_RANGE2_SIZE_LOW;
typedef union {
struct {
UINT32 MemoryBaseHigh : 32; // bit 0..31
} Bits;
UINT32 Uint32;
} CXL_DVSEC_FLEX_BUS_DEVICE_RANGE2_BASE_HIGH;
typedef union {
struct {
UINT32 Reserved : 28; // bit 0..27
UINT32 MemoryBaseLow : 4; // bit 28..31
} Bits;
UINT32 Uint32;
} CXL_DVSEC_FLEX_BUS_DEVICE_RANGE2_BASE_LOW;
//
// Flex Bus Device DVSEC ID
// Compute Express Link Specification Revision: 1.1 - Chapter 7.1.1, Table 58
//
#define FLEX_BUS_DEVICE_DVSEC_ID 0
//
// PCIe DVSEC for Flex Bus Device
// Compute Express Link Specification Revision: 1.1 - Chapter 7.1.1, Figure 95
//
typedef struct {
PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header; // offset 0
PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_1 DesignatedVendorSpecificHeader1; // offset 4
PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_2 DesignatedVendorSpecificHeader2; // offset 8
CXL_DVSEC_FLEX_BUS_DEVICE_CAPABILITY DeviceCapability; // offset 10
CXL_DVSEC_FLEX_BUS_DEVICE_CONTROL DeviceControl; // offset 12
CXL_DVSEC_FLEX_BUS_DEVICE_STATUS DeviceStatus; // offset 14
CXL_1_1_DVSEC_FLEX_BUS_DEVICE_CONTROL2 DeviceControl2; // offset 16
CXL_1_1_DVSEC_FLEX_BUS_DEVICE_STATUS2 DeviceStatus2; // offset 18
CXL_DVSEC_FLEX_BUS_DEVICE_LOCK DeviceLock; // offset 20
UINT16 Reserved; // offset 22
CXL_DVSEC_FLEX_BUS_DEVICE_RANGE1_SIZE_HIGH DeviceRange1SizeHigh; // offset 24
CXL_DVSEC_FLEX_BUS_DEVICE_RANGE1_SIZE_LOW DeviceRange1SizeLow; // offset 28
CXL_DVSEC_FLEX_BUS_DEVICE_RANGE1_BASE_HIGH DeviceRange1BaseHigh; // offset 32
CXL_DVSEC_FLEX_BUS_DEVICE_RANGE1_BASE_LOW DeviceRange1BaseLow; // offset 36
CXL_DVSEC_FLEX_BUS_DEVICE_RANGE2_SIZE_HIGH DeviceRange2SizeHigh; // offset 40
CXL_DVSEC_FLEX_BUS_DEVICE_RANGE2_SIZE_LOW DeviceRange2SizeLow; // offset 44
CXL_DVSEC_FLEX_BUS_DEVICE_RANGE2_BASE_HIGH DeviceRange2BaseHigh; // offset 48
CXL_DVSEC_FLEX_BUS_DEVICE_RANGE2_BASE_LOW DeviceRange2BaseLow; // offset 52
} CXL_1_1_DVSEC_FLEX_BUS_DEVICE;
CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, Header , 0x00);
CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DesignatedVendorSpecificHeader1, 0x04);
CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DesignatedVendorSpecificHeader2, 0x08);
CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceCapability , 0x0A);
CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceControl , 0x0C);
CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceStatus , 0x0E);
CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceControl2 , 0x10);
CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceStatus2 , 0x12);
CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceLock , 0x14);
CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceRange1SizeHigh , 0x18);
CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceRange1SizeLow , 0x1C);
CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceRange1BaseHigh , 0x20);
CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceRange1BaseLow , 0x24);
CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceRange2SizeHigh , 0x28);
CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceRange2SizeLow , 0x2C);
CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceRange2BaseHigh , 0x30);
CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceRange2BaseLow , 0x34);
CXL_11_SIZE_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE , 0x38);
///@}
///
/// PCIe DVSEC for FLex Bus Port
///@{
typedef union {
struct {
UINT16 CacheCapable : 1; // bit 0
UINT16 IoCapable : 1; // bit 1
UINT16 MemCapable : 1; // bit 2
UINT16 Reserved : 13; // bit 3..15
} Bits;
UINT16 Uint16;
} CXL_1_1_DVSEC_FLEX_BUS_PORT_CAPABILITY;
typedef union {
struct {
UINT16 CacheEnable : 1; // bit 0
UINT16 IoEnable : 1; // bit 1
UINT16 MemEnable : 1; // bit 2
UINT16 CxlSyncBypassEnable : 1; // bit 3
UINT16 DriftBufferEnable : 1; // bit 4
UINT16 Reserved : 3; // bit 5..7
UINT16 Retimer1Present : 1; // bit 8
UINT16 Retimer2Present : 1; // bit 9
UINT16 Reserved2 : 6; // bit 10..15
} Bits;
UINT16 Uint16;
} CXL_1_1_DVSEC_FLEX_BUS_PORT_CONTROL;
typedef union {
struct {
UINT16 CacheEnable : 1; // bit 0
UINT16 IoEnable : 1; // bit 1
UINT16 MemEnable : 1; // bit 2
UINT16 CxlSyncBypassEnable : 1; // bit 3
UINT16 DriftBufferEnable : 1; // bit 4
UINT16 Reserved : 3; // bit 5..7
UINT16 CxlCorrectableProtocolIdFramingError : 1; // bit 8
UINT16 CxlUncorrectableProtocolIdFramingError : 1; // bit 9
UINT16 CxlUnexpectedProtocolIdDropped : 1; // bit 10
UINT16 Reserved2 : 5; // bit 11..15
} Bits;
UINT16 Uint16;
} CXL_1_1_DVSEC_FLEX_BUS_PORT_STATUS;
//
// Flex Bus Port DVSEC ID
// Compute Express Link Specification Revision: 1.1 - Chapter 7.2.1.3, Table 62
//
#define FLEX_BUS_PORT_DVSEC_ID 7
//
// PCIe DVSEC for Flex Bus Port
// Compute Express Link Specification Revision: 1.1 - Chapter 7.2.1.3, Figure 99
//
typedef struct {
PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header; // offset 0
PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_1 DesignatedVendorSpecificHeader1; // offset 4
PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_2 DesignatedVendorSpecificHeader2; // offset 8
CXL_1_1_DVSEC_FLEX_BUS_PORT_CAPABILITY PortCapability; // offset 10
CXL_1_1_DVSEC_FLEX_BUS_PORT_CONTROL PortControl; // offset 12
CXL_1_1_DVSEC_FLEX_BUS_PORT_STATUS PortStatus; // offset 14
} CXL_1_1_DVSEC_FLEX_BUS_PORT;
CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_PORT, Header , 0x00);
CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_PORT, DesignatedVendorSpecificHeader1, 0x04);
CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_PORT, DesignatedVendorSpecificHeader2, 0x08);
CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_PORT, PortCapability , 0x0A);
CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_PORT, PortControl , 0x0C);
CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_PORT, PortStatus , 0x0E);
CXL_11_SIZE_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_PORT , 0x10);
///@}
///
/// CXL 1.1 Upstream and Downstream Port Subsystem Component registers
///
/// The CXL.Cache and CXL.Memory Architectural register definitions
/// Based on chapter 7.2.2 of Compute Express Link Specification Revision: 1.1
///@{
#define CXL_CAPABILITY_HEADER_OFFSET 0
typedef union {
struct {
UINT32 CxlCapabilityId : 16; // bit 0..15
UINT32 CxlCapabilityVersion : 4; // bit 16..19
UINT32 CxlCacheMemVersion : 4; // bit 20..23
UINT32 ArraySize : 8; // bit 24..31
} Bits;
UINT32 Uint32;
} CXL_CAPABILITY_HEADER;
#define CXL_RAS_CAPABILITY_HEADER_OFFSET 4
typedef union {
struct {
UINT32 CxlCapabilityId : 16; // bit 0..15
UINT32 CxlCapabilityVersion : 4; // bit 16..19
UINT32 CxlRasCapabilityPointer : 12; // bit 20..31
} Bits;
UINT32 Uint32;
} CXL_RAS_CAPABILITY_HEADER;
#define CXL_SECURITY_CAPABILITY_HEADER_OFFSET 8
typedef union {
struct {
UINT32 CxlCapabilityId : 16; // bit 0..15
UINT32 CxlCapabilityVersion : 4; // bit 16..19
UINT32 CxlSecurityCapabilityPointer : 12; // bit 20..31
} Bits;
UINT32 Uint32;
} CXL_SECURITY_CAPABILITY_HEADER;
#define CXL_LINK_CAPABILITY_HEADER_OFFSET 0xC
typedef union {
struct {
UINT32 CxlCapabilityId : 16; // bit 0..15
UINT32 CxlCapabilityVersion : 4; // bit 16..19
UINT32 CxlLinkCapabilityPointer : 12; // bit 20..31
} Bits;
UINT32 Uint32;
} CXL_LINK_CAPABILITY_HEADER;
typedef union {
struct {
UINT32 CacheDataParity : 1; // bit 0..0
UINT32 CacheAddressParity : 1; // bit 1..1
UINT32 CacheByteEnableParity : 1; // bit 2..2
UINT32 CacheDataEcc : 1; // bit 3..3
UINT32 MemDataParity : 1; // bit 4..4
UINT32 MemAddressParity : 1; // bit 5..5
UINT32 MemByteEnableParity : 1; // bit 6..6
UINT32 MemDataEcc : 1; // bit 7..7
UINT32 ReInitThreshold : 1; // bit 8..8
UINT32 RsvdEncodingViolation : 1; // bit 9..9
UINT32 PoisonReceived : 1; // bit 10..10
UINT32 ReceiverOverflow : 1; // bit 11..11
UINT32 Reserved : 20; // bit 12..31
} Bits;
UINT32 Uint32;
} CXL_1_1_UNCORRECTABLE_ERROR_STATUS;
typedef union {
struct {
UINT32 CacheDataParityMask : 1; // bit 0..0
UINT32 CacheAddressParityMask : 1; // bit 1..1
UINT32 CacheByteEnableParityMask : 1; // bit 2..2
UINT32 CacheDataEccMask : 1; // bit 3..3
UINT32 MemDataParityMask : 1; // bit 4..4
UINT32 MemAddressParityMask : 1; // bit 5..5
UINT32 MemByteEnableParityMask : 1; // bit 6..6
UINT32 MemDataEccMask : 1; // bit 7..7
UINT32 ReInitThresholdMask : 1; // bit 8..8
UINT32 RsvdEncodingViolationMask : 1; // bit 9..9
UINT32 PoisonReceivedMask : 1; // bit 10..10
UINT32 ReceiverOverflowMask : 1; // bit 11..11
UINT32 Reserved : 20; // bit 12..31
} Bits;
UINT32 Uint32;
} CXL_1_1_UNCORRECTABLE_ERROR_MASK;
typedef union {
struct {
UINT32 CacheDataParitySeverity : 1; // bit 0..0
UINT32 CacheAddressParitySeverity : 1; // bit 1..1
UINT32 CacheByteEnableParitySeverity : 1; // bit 2..2
UINT32 CacheDataEccSeverity : 1; // bit 3..3
UINT32 MemDataParitySeverity : 1; // bit 4..4
UINT32 MemAddressParitySeverity : 1; // bit 5..5
UINT32 MemByteEnableParitySeverity : 1; // bit 6..6
UINT32 MemDataEccSeverity : 1; // bit 7..7
UINT32 ReInitThresholdSeverity : 1; // bit 8..8
UINT32 RsvdEncodingViolationSeverity : 1; // bit 9..9
UINT32 PoisonReceivedSeverity : 1; // bit 10..10
UINT32 ReceiverOverflowSeverity : 1; // bit 11..11
UINT32 Reserved : 20; // bit 12..31
} Bits;
UINT32 Uint32;
} CXL_1_1_UNCORRECTABLE_ERROR_SEVERITY;
typedef union {
struct {
UINT32 CacheDataEcc : 1; // bit 0..0
UINT32 MemoryDataEcc : 1; // bit 1..1
UINT32 CrcThreshold : 1; // bit 2..2
UINT32 RetryThreshold : 1; // bit 3..3
UINT32 CachePoisonReceived : 1; // bit 4..4
UINT32 MemoryPoisonReceived : 1; // bit 5..5
UINT32 PhysicalLayerError : 1; // bit 6..6
UINT32 Reserved : 25; // bit 7..31
} Bits;
UINT32 Uint32;
} CXL_CORRECTABLE_ERROR_STATUS;
typedef union {
struct {
UINT32 CacheDataEccMask : 1; // bit 0..0
UINT32 MemoryDataEccMask : 1; // bit 1..1
UINT32 CrcThresholdMask : 1; // bit 2..2
UINT32 RetryThresholdMask : 1; // bit 3..3
UINT32 CachePoisonReceivedMask : 1; // bit 4..4
UINT32 MemoryPoisonReceivedMask : 1; // bit 5..5
UINT32 PhysicalLayerErrorMask : 1; // bit 6..6
UINT32 Reserved : 25; // bit 7..31
} Bits;
UINT32 Uint32;
} CXL_CORRECTABLE_ERROR_MASK;
typedef union {
struct {
UINT32 FirstErrorPointer : 4; // bit 0..3
UINT32 Reserved1 : 5; // bit 4..8
UINT32 MultipleHeaderRecordingCapability : 1; // bit 9..9
UINT32 Reserved2 : 3; // bit 10..12
UINT32 PoisonEnabled : 1; // bit 13..13
UINT32 Reserved3 : 18; // bit 14..31
} Bits;
UINT32 Uint32;
} CXL_ERROR_CAPABILITIES_AND_CONTROL;
typedef struct {
CXL_1_1_UNCORRECTABLE_ERROR_STATUS UncorrectableErrorStatus;
CXL_1_1_UNCORRECTABLE_ERROR_MASK UncorrectableErrorMask;
CXL_1_1_UNCORRECTABLE_ERROR_SEVERITY UncorrectableErrorSeverity;
CXL_CORRECTABLE_ERROR_STATUS CorrectableErrorStatus;
CXL_CORRECTABLE_ERROR_MASK CorrectableErrorMask;
CXL_ERROR_CAPABILITIES_AND_CONTROL ErrorCapabilitiesAndControl;
UINT32 HeaderLog[16];
} CXL_1_1_RAS_CAPABILITY_STRUCTURE;
CXL_11_OFFSET_ASSERT (CXL_1_1_RAS_CAPABILITY_STRUCTURE, UncorrectableErrorStatus , 0x00);
CXL_11_OFFSET_ASSERT (CXL_1_1_RAS_CAPABILITY_STRUCTURE, UncorrectableErrorMask , 0x04);
CXL_11_OFFSET_ASSERT (CXL_1_1_RAS_CAPABILITY_STRUCTURE, UncorrectableErrorSeverity , 0x08);
CXL_11_OFFSET_ASSERT (CXL_1_1_RAS_CAPABILITY_STRUCTURE, CorrectableErrorStatus , 0x0C);
CXL_11_OFFSET_ASSERT (CXL_1_1_RAS_CAPABILITY_STRUCTURE, CorrectableErrorMask , 0x10);
CXL_11_OFFSET_ASSERT (CXL_1_1_RAS_CAPABILITY_STRUCTURE, ErrorCapabilitiesAndControl, 0x14);
CXL_11_OFFSET_ASSERT (CXL_1_1_RAS_CAPABILITY_STRUCTURE, HeaderLog , 0x18);
CXL_11_SIZE_ASSERT (CXL_1_1_RAS_CAPABILITY_STRUCTURE , 0x58);
typedef union {
struct {
UINT32 DeviceTrustLevel : 2; // bit 0..1
UINT32 Reserved : 30; // bit 2..31
} Bits;
UINT32 Uint32;
} CXL_1_1_SECURITY_POLICY;
typedef struct {
CXL_1_1_SECURITY_POLICY SecurityPolicy;
} CXL_1_1_SECURITY_CAPABILITY_STRUCTURE;
CXL_11_OFFSET_ASSERT (CXL_1_1_SECURITY_CAPABILITY_STRUCTURE, SecurityPolicy, 0x0);
CXL_11_SIZE_ASSERT (CXL_1_1_SECURITY_CAPABILITY_STRUCTURE, 0x4);
typedef union {
struct {
UINT64 CxlLinkVersionSupported : 4; // bit 0..3
UINT64 CxlLinkVersionReceived : 4; // bit 4..7
UINT64 LlrWrapValueSupported : 8; // bit 8..15
UINT64 LlrWrapValueReceived : 8; // bit 16..23
UINT64 NumRetryReceived : 5; // bit 24..28
UINT64 NumPhyReinitReceived : 5; // bit 29..33
UINT64 WrPtrReceived : 8; // bit 34..41
UINT64 EchoEseqReceived : 8; // bit 42..49
UINT64 NumFreeBufReceived : 8; // bit 50..57
UINT64 Reserved : 6; // bit 58..63
} Bits;
UINT64 Uint64;
} CXL_LINK_LAYER_CAPABILITY;
typedef union {
struct {
UINT16 LlReset : 1; // bit 0..0
UINT16 LlInitStall : 1; // bit 1..1
UINT16 LlCrdStall : 1; // bit 2..2
UINT16 InitState : 2; // bit 3..4
UINT16 LlRetryBufferConsumed : 8; // bit 5..12
UINT16 Reserved : 3; // bit 13..15
} Bits;
UINT64 Uint64;
} CXL_LINK_LAYER_CONTROL_AND_STATUS;
typedef union {
struct {
UINT64 CacheReqCredits : 10; // bit 0..9
UINT64 CacheRspCredits : 10; // bit 10..19
UINT64 CacheDataCredits : 10; // bit 20..29
UINT64 MemReqRspCredits : 10; // bit 30..39
UINT64 MemDataCredits : 10; // bit 40..49
} Bits;
UINT64 Uint64;
} CXL_LINK_LAYER_RX_CREDIT_CONTROL;
typedef union {
struct {
UINT64 CacheReqCredits : 10; // bit 0..9
UINT64 CacheRspCredits : 10; // bit 10..19
UINT64 CacheDataCredits : 10; // bit 20..29
UINT64 MemReqRspCredits : 10; // bit 30..39
UINT64 MemDataCredits : 10; // bit 40..49
} Bits;
UINT64 Uint64;
} CXL_LINK_LAYER_RX_CREDIT_RETURN_STATUS;
typedef union {
struct {
UINT64 CacheReqCredits : 10; // bit 0..9
UINT64 CacheRspCredits : 10; // bit 10..19
UINT64 CacheDataCredits : 10; // bit 20..29
UINT64 MemReqRspCredits : 10; // bit 30..39
UINT64 MemDataCredits : 10; // bit 40..49
} Bits;
UINT64 Uint64;
} CXL_LINK_LAYER_TX_CREDIT_STATUS;
typedef union {
struct {
UINT32 AckForceThreshold : 8; // bit 0..7
UINT32 AckFLushRetimer : 10; // bit 8..17
} Bits;
UINT64 Uint64;
} CXL_LINK_LAYER_ACK_TIMER_CONTROL;
typedef union {
struct {
UINT32 MdhDisable : 1; // bit 0..0
UINT32 Reserved : 31; // bit 1..31
} Bits;
UINT64 Uint64;
} CXL_LINK_LAYER_DEFEATURE;
typedef struct {
CXL_LINK_LAYER_CAPABILITY LinkLayerCapability;
CXL_LINK_LAYER_CONTROL_AND_STATUS LinkLayerControlStatus;
CXL_LINK_LAYER_RX_CREDIT_CONTROL LinkLayerRxCreditControl;
CXL_LINK_LAYER_RX_CREDIT_RETURN_STATUS LinkLayerRxCreditReturnStatus;
CXL_LINK_LAYER_TX_CREDIT_STATUS LinkLayerTxCreditStatus;
CXL_LINK_LAYER_ACK_TIMER_CONTROL LinkLayerAckTimerControl;
CXL_LINK_LAYER_DEFEATURE LinkLayerDefeature;
} CXL_1_1_LINK_CAPABILITY_STRUCTURE;
CXL_11_OFFSET_ASSERT (CXL_1_1_LINK_CAPABILITY_STRUCTURE, LinkLayerCapability , 0x00);
CXL_11_OFFSET_ASSERT (CXL_1_1_LINK_CAPABILITY_STRUCTURE, LinkLayerControlStatus , 0x08);
CXL_11_OFFSET_ASSERT (CXL_1_1_LINK_CAPABILITY_STRUCTURE, LinkLayerRxCreditControl , 0x10);
CXL_11_OFFSET_ASSERT (CXL_1_1_LINK_CAPABILITY_STRUCTURE, LinkLayerRxCreditReturnStatus, 0x18);
CXL_11_OFFSET_ASSERT (CXL_1_1_LINK_CAPABILITY_STRUCTURE, LinkLayerTxCreditStatus , 0x20);
CXL_11_OFFSET_ASSERT (CXL_1_1_LINK_CAPABILITY_STRUCTURE, LinkLayerAckTimerControl , 0x28);
CXL_11_OFFSET_ASSERT (CXL_1_1_LINK_CAPABILITY_STRUCTURE, LinkLayerDefeature , 0x30);
CXL_11_SIZE_ASSERT (CXL_1_1_LINK_CAPABILITY_STRUCTURE , 0x38);
#define CXL_IO_ARBITRATION_CONTROL_OFFSET 0x180
typedef union {
struct {
UINT32 Reserved1 : 4; // bit 0..3
UINT32 WeightedRoundRobinArbitrationWeight : 4; // bit 4..7
UINT32 Reserved2 : 24; // bit 8..31
} Bits;
UINT32 Uint32;
} CXL_IO_ARBITRATION_CONTROL;
CXL_11_SIZE_ASSERT (CXL_IO_ARBITRATION_CONTROL, 0x4);
#define CXL_CACHE_MEMORY_ARBITRATION_CONTROL_OFFSET 0x1C0
typedef union {
struct {
UINT32 Reserved1 : 4; // bit 0..3
UINT32 WeightedRoundRobinArbitrationWeight : 4; // bit 4..7
UINT32 Reserved2 : 24; // bit 8..31
} Bits;
UINT32 Uint32;
} CXL_CACHE_MEMORY_ARBITRATION_CONTROL;
CXL_11_SIZE_ASSERT (CXL_CACHE_MEMORY_ARBITRATION_CONTROL, 0x4);
///@}
/// The CXL.RCRB base register definition
/// Based on chapter 7.3 of Compute Express Link Specification Revision: 1.1
///@{
typedef union {
struct {
UINT64 RcrbEnable : 1; // bit 0..0
UINT64 Reserved : 12; // bit 1..12
UINT64 RcrbBaseAddress : 51; // bit 13..63
} Bits;
UINT64 Uint64;
} CXL_RCRB_BASE;
CXL_11_SIZE_ASSERT (CXL_RCRB_BASE, 0x8);
///@}
#pragma pack()
//
// CXL Downstream / Upstream Port RCRB space register offsets
// Compute Express Link Specification Revision: 1.1 - Chapter 7.2.1.1 - Figure 97
//
#define CXL_PORT_RCRB_MEMBAR0_LOW_OFFSET 0x010
#define CXL_PORT_RCRB_MEMBAR0_HIGH_OFFSET 0x014
#define CXL_PORT_RCRB_EXTENDED_CAPABILITY_BASE_OFFSET 0x100
#endif

75
src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/DebugPort2Table.h Normal file
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/** @file
ACPI debug port 2 table definition, defined at
Microsoft DebugPort2Specification.
Copyright (c) 2012 - 2018, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2012 - 2016, ARM Limited. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef _DEBUG_PORT_2_TABLE_H_
#define _DEBUG_PORT_2_TABLE_H_
#include <IndustryStandard/Acpi.h>
//
// Ensure proper structure formats
//
#pragma pack(1)
//
// Debug Device Information structure.
//
typedef struct {
UINT8 Revision;
UINT16 Length;
UINT8 NumberofGenericAddressRegisters;
UINT16 NameSpaceStringLength;
UINT16 NameSpaceStringOffset;
UINT16 OemDataLength;
UINT16 OemDataOffset;
UINT16 PortType;
UINT16 PortSubtype;
UINT8 Reserved[2];
UINT16 BaseAddressRegisterOffset;
UINT16 AddressSizeOffset;
} EFI_ACPI_DBG2_DEBUG_DEVICE_INFORMATION_STRUCT;
#define EFI_ACPI_DBG2_DEBUG_DEVICE_INFORMATION_STRUCT_REVISION 0x00
#define EFI_ACPI_DBG2_PORT_TYPE_SERIAL 0x8000
#define EFI_ACPI_DBG2_PORT_SUBTYPE_SERIAL_FULL_16550 0x0000
#define EFI_ACPI_DBG2_PORT_SUBTYPE_SERIAL_16550_SUBSET_COMPATIBLE_WITH_MS_DBGP_SPEC 0x0001
#define EFI_ACPI_DBG2_PORT_SUBTYPE_SERIAL_ARM_PL011_UART 0x0003
#define EFI_ACPI_DBG2_PORT_SUBTYPE_SERIAL_NVIDIA_16550_UART 0x0005
#define EFI_ACPI_DBG2_PORT_SUBTYPE_SERIAL_ARM_SBSA_GENERIC_UART_2X 0x000d
#define EFI_ACPI_DBG2_PORT_SUBTYPE_SERIAL_ARM_SBSA_GENERIC_UART 0x000e
#define EFI_ACPI_DBG2_PORT_SUBTYPE_SERIAL_DCC 0x000f
#define EFI_ACPI_DBG2_PORT_SUBTYPE_SERIAL_BCM2835_UART 0x0010
#define EFI_ACPI_DBG2_PORT_SUBTYPE_SERIAL_16550_WITH_GAS 0x0012
#define EFI_ACPI_DBG2_PORT_TYPE_1394 0x8001
#define EFI_ACPI_DBG2_PORT_SUBTYPE_1394_STANDARD 0x0000
#define EFI_ACPI_DBG2_PORT_TYPE_USB 0x8002
#define EFI_ACPI_DBG2_PORT_SUBTYPE_USB_XHCI 0x0000
#define EFI_ACPI_DBG2_PORT_SUBTYPE_USB_EHCI 0x0001
#define EFI_ACPI_DBG2_PORT_TYPE_NET 0x8003
//
// Debug Port 2 Table definition.
//
typedef struct {
EFI_ACPI_DESCRIPTION_HEADER Header;
UINT32 OffsetDbgDeviceInfo;
UINT32 NumberDbgDeviceInfo;
} EFI_ACPI_DEBUG_PORT_2_DESCRIPTION_TABLE;
#pragma pack()
//
// DBG2 Revision (defined in spec)
//
#define EFI_ACPI_DEBUG_PORT_2_TABLE_REVISION 0x00
#endif

44
src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/DebugPortTable.h Normal file
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/** @file
ACPI debug port table definition, defined at
Microsoft DebugPortSpecification.
Copyright (c) 2012 - 2018, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef _DEBUG_PORT_TABLE_H_
#define _DEBUG_PORT_TABLE_H_
#include <IndustryStandard/Acpi.h>
//
// Ensure proper structure formats
//
#pragma pack(1)
//
// Debug Port Table definition.
//
typedef struct {
EFI_ACPI_DESCRIPTION_HEADER Header;
UINT8 InterfaceType;
UINT8 Reserved_37[3];
EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE BaseAddress;
} EFI_ACPI_DEBUG_PORT_DESCRIPTION_TABLE;
#pragma pack()
//
// DBGP Revision (defined in spec)
//
#define EFI_ACPI_DEBUG_PORT_TABLE_REVISION 0x01
//
// Interface Type
//
#define EFI_ACPI_DBGP_INTERFACE_TYPE_FULL_16550 0
#define EFI_ACPI_DBGP_INTERFACE_TYPE_16550_SUBSET_COMPATIBLE_WITH_MS_DBGP_SPEC 1
#endif

283
src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/Dhcp.h Normal file
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/** @file
This file contains the DHCPv4 and DHCPv6 option definitions and other configuration.
They are used to carry additional information and parameters in DHCP messages.
Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef _DHCP_H_
#define _DHCP_H_
///
/// Dynamic Host Configuration Protocol for IPv4 (DHCPv4)
///
/// Dhcpv4 Options, definitions from RFC 2132
///
#define DHCP4_TAG_PAD 0 /// Pad Option
#define DHCP4_TAG_EOP 255 /// End Option
#define DHCP4_TAG_NETMASK 1 /// Subnet Mask
#define DHCP4_TAG_TIME_OFFSET 2 /// Time Offset from UTC
#define DHCP4_TAG_ROUTER 3 /// Router option,
#define DHCP4_TAG_TIME_SERVER 4 /// Time Server
#define DHCP4_TAG_NAME_SERVER 5 /// Name Server
#define DHCP4_TAG_DNS_SERVER 6 /// Domain Name Server
#define DHCP4_TAG_LOG_SERVER 7 /// Log Server
#define DHCP4_TAG_COOKIE_SERVER 8 /// Cookie Server
#define DHCP4_TAG_LPR_SERVER 9 /// LPR Print Server
#define DHCP4_TAG_IMPRESS_SERVER 10 /// Impress Server
#define DHCP4_TAG_RL_SERVER 11 /// Resource Location Server
#define DHCP4_TAG_HOSTNAME 12 /// Host Name
#define DHCP4_TAG_BOOTFILE_LEN 13 /// Boot File Size
#define DHCP4_TAG_DUMP 14 /// Merit Dump File
#define DHCP4_TAG_DOMAINNAME 15 /// Domain Name
#define DHCP4_TAG_SWAP_SERVER 16 /// Swap Server
#define DHCP4_TAG_ROOTPATH 17 /// Root path
#define DHCP4_TAG_EXTEND_PATH 18 /// Extensions Path
#define DHCP4_TAG_IPFORWARD 19 /// IP Forwarding Enable/Disable
#define DHCP4_TAG_NONLOCAL_SRR 20 /// on-Local Source Routing Enable/Disable
#define DHCP4_TAG_POLICY_SRR 21 /// Policy Filter
#define DHCP4_TAG_EMTU 22 /// Maximum Datagram Reassembly Size
#define DHCP4_TAG_TTL 23 /// Default IP Time-to-live
#define DHCP4_TAG_PATHMTU_AGE 24 /// Path MTU Aging Timeout
#define DHCP4_TAG_PATHMTU_PLATEAU 25 /// Path MTU Plateau Table
#define DHCP4_TAG_IFMTU 26 /// Interface MTU
#define DHCP4_TAG_SUBNET_LOCAL 27 /// All Subnets are Local
#define DHCP4_TAG_BROADCAST 28 /// Broadcast Address
#define DHCP4_TAG_DISCOVER_MASK 29 /// Perform Mask Discovery
#define DHCP4_TAG_SUPPLY_MASK 30 /// Mask Supplier
#define DHCP4_TAG_DISCOVER_ROUTE 31 /// Perform Router Discovery
#define DHCP4_TAG_ROUTER_SOLICIT 32 /// Router Solicitation Address
#define DHCP4_TAG_STATIC_ROUTE 33 /// Static Route
#define DHCP4_TAG_TRAILER 34 /// Trailer Encapsulation
#define DHCP4_TAG_ARPAGE 35 /// ARP Cache Timeout
#define DHCP4_TAG_ETHER_ENCAP 36 /// Ethernet Encapsulation
#define DHCP4_TAG_TCP_TTL 37 /// TCP Default TTL
#define DHCP4_TAG_KEEP_INTERVAL 38 /// TCP Keepalive Interval
#define DHCP4_TAG_KEEP_GARBAGE 39 /// TCP Keepalive Garbage
#define DHCP4_TAG_NIS_DOMAIN 40 /// Network Information Service Domain
#define DHCP4_TAG_NIS_SERVER 41 /// Network Information Servers
#define DHCP4_TAG_NTP_SERVER 42 /// Network Time Protocol Servers
#define DHCP4_TAG_VENDOR 43 /// Vendor Specific Information
#define DHCP4_TAG_NBNS 44 /// NetBIOS over TCP/IP Name Server
#define DHCP4_TAG_NBDD 45 /// NetBIOS Datagram Distribution Server
#define DHCP4_TAG_NBTYPE 46 /// NetBIOS over TCP/IP Node Type
#define DHCP4_TAG_NBSCOPE 47 /// NetBIOS over TCP/IP Scope
#define DHCP4_TAG_XFONT 48 /// X Window System Font Server
#define DHCP4_TAG_XDM 49 /// X Window System Display Manager
#define DHCP4_TAG_REQUEST_IP 50 /// Requested IP Address
#define DHCP4_TAG_LEASE 51 /// IP Address Lease Time
#define DHCP4_TAG_OVERLOAD 52 /// Option Overload
#define DHCP4_TAG_MSG_TYPE 53 /// DHCP Message Type
#define DHCP4_TAG_SERVER_ID 54 /// Server Identifier
#define DHCP4_TAG_PARA_LIST 55 /// Parameter Request List
#define DHCP4_TAG_MESSAGE 56 /// Message
#define DHCP4_TAG_MAXMSG 57 /// Maximum DHCP Message Size
#define DHCP4_TAG_T1 58 /// Renewal (T1) Time Value
#define DHCP4_TAG_T2 59 /// Rebinding (T2) Time Value
#define DHCP4_TAG_VENDOR_CLASS_ID 60 /// Vendor class identifier
#define DHCP4_TAG_CLIENT_ID 61 /// Client-identifier
#define DHCP4_TAG_NISPLUS 64 /// Network Information Service+ Domain
#define DHCP4_TAG_NISPLUS_SERVER 65 /// Network Information Service+ Servers
#define DHCP4_TAG_TFTP 66 /// TFTP server name
#define DHCP4_TAG_BOOTFILE 67 /// Bootfile name
#define DHCP4_TAG_MOBILEIP 68 /// Mobile IP Home Agent
#define DHCP4_TAG_SMTP 69 /// Simple Mail Transport Protocol Server
#define DHCP4_TAG_POP3 70 /// Post Office Protocol (POP3) Server
#define DHCP4_TAG_NNTP 71 /// Network News Transport Protocol Server
#define DHCP4_TAG_WWW 72 /// Default World Wide Web (WWW) Server
#define DHCP4_TAG_FINGER 73 /// Default Finger Server
#define DHCP4_TAG_IRC 74 /// Default Internet Relay Chat (IRC) Server
#define DHCP4_TAG_STTALK 75 /// StreetTalk Server
#define DHCP4_TAG_STDA 76 /// StreetTalk Directory Assistance Server
#define DHCP4_TAG_USER_CLASS_ID 77 /// User class identifier
#define DHCP4_TAG_ARCH 93 /// Client System Architecture Type, RFC 4578
#define DHCP4_TAG_UNDI 94 /// Client Network Interface Identifier, RFC 4578
#define DHCP4_TAG_UUID 97 /// Client Machine Identifier, RFC 4578
#define DHCP4_TAG_CLASSLESS_ROUTE 121 /// Classless Route
///
/// Dynamic Host Configuration Protocol for IPv6 (DHCPv6)
///
/// Enumeration of Dhcp6 message type, refers to section-5.3 of rfc-3315.
///
typedef enum {
Dhcp6MsgSolicit = 1,
Dhcp6MsgAdvertise = 2,
Dhcp6MsgRequest = 3,
Dhcp6MsgConfirm = 4,
Dhcp6MsgRenew = 5,
Dhcp6MsgRebind = 6,
Dhcp6MsgReply = 7,
Dhcp6MsgRelease = 8,
Dhcp6MsgDecline = 9,
Dhcp6MsgReconfigure = 10,
Dhcp6MsgInfoRequest = 11
} DHCP6_MSG_TYPE;
///
/// Enumeration of option code in Dhcp6 packet, refers to section-24.3 of rfc-3315.
///
typedef enum {
Dhcp6OptClientId = 1,
Dhcp6OptServerId = 2,
Dhcp6OptIana = 3,
Dhcp6OptIata = 4,
Dhcp6OptIaAddr = 5,
Dhcp6OptRequestOption = 6,
Dhcp6OptPreference = 7,
Dhcp6OptElapsedTime = 8,
Dhcp6OptReplayMessage = 9,
Dhcp6OptAuthentication = 11,
Dhcp6OptServerUnicast = 12,
Dhcp6OptStatusCode = 13,
Dhcp6OptRapidCommit = 14,
Dhcp6OptUserClass = 15,
Dhcp6OptVendorClass = 16,
Dhcp6OptVendorInfo = 17,
Dhcp6OptInterfaceId = 18,
Dhcp6OptReconfigMessage = 19,
Dhcp6OptReconfigureAccept = 20
} DHCP6_OPT_CODE;
///
/// Enumeration of status code recorded by IANA, refers to section-24.4 of rfc-3315.
///
typedef enum {
Dhcp6StsSuccess = 0,
Dhcp6StsUnspecFail = 1,
Dhcp6StsNoAddrsAvail = 2,
Dhcp6StsNoBinding = 3,
Dhcp6StsNotOnLink = 4,
Dhcp6StsUseMulticast = 5
} DHCP6_STS_CODE;
///
/// Enumeration of Duid type recorded by IANA, refers to section-24.5 of rfc-3315.
///
typedef enum {
Dhcp6DuidTypeLlt = 1,
Dhcp6DuidTypeEn = 2,
Dhcp6DuidTypeLl = 3,
Dhcp6DuidTypeUuid = 4
} DHCP6_DUID_TYPE;
/// Transmission and Retransmission Parameters
/// This section presents a table of values used to describe the message
/// transmission behavior of clients and servers.
///
/// Transmit parameters of solicit message, refers to section-5.5 of rfc-3315.
///
#define DHCP6_SOL_MAX_DELAY 1
#define DHCP6_SOL_IRT 1
#define DHCP6_SOL_MRC 0
#define DHCP6_SOL_MRT 120
#define DHCP6_SOL_MRD 0
///
/// Transmit parameters of request message, refers to section-5.5 of rfc-3315.
///
#define DHCP6_REQ_IRT 1
#define DHCP6_REQ_MRC 10
#define DHCP6_REQ_MRT 30
#define DHCP6_REQ_MRD 0
///
/// Transmit parameters of confirm message, refers to section-5.5 of rfc-3315.
///
#define DHCP6_CNF_MAX_DELAY 1
#define DHCP6_CNF_IRT 1
#define DHCP6_CNF_MRC 0
#define DHCP6_CNF_MRT 4
#define DHCP6_CNF_MRD 10
///
/// Transmit parameters of renew message, refers to section-5.5 of rfc-3315.
///
#define DHCP6_REN_IRT 10
#define DHCP6_REN_MRC 0
#define DHCP6_REN_MRT 600
#define DHCP6_REN_MRD 0
///
/// Transmit parameters of rebind message, refers to section-5.5 of rfc-3315.
///
#define DHCP6_REB_IRT 10
#define DHCP6_REB_MRC 0
#define DHCP6_REB_MRT 600
#define DHCP6_REB_MRD 0
///
/// Transmit parameters of information request message, refers to section-5.5 of rfc-3315.
///
#define DHCP6_INF_MAX_DELAY 1
#define DHCP6_INF_IRT 1
#define DHCP6_INF_MRC 0
#define DHCP6_INF_MRT 120
#define DHCP6_INF_MRD 0
///
/// Transmit parameters of release message, refers to section-5.5 of rfc-3315.
///
#define DHCP6_REL_IRT 1
#define DHCP6_REL_MRC 5
#define DHCP6_REL_MRT 0
#define DHCP6_REL_MRD 0
///
/// Transmit parameters of decline message, refers to section-5.5 of rfc-3315.
///
#define DHCP6_DEC_IRT 1
#define DHCP6_DEC_MRC 5
#define DHCP6_DEC_MRT 0
#define DHCP6_DEC_MRD 0
////
//// DHCPv6 Options, definitions from RFC 3315,RFC 5970 and RFC 3646.
////
#define DHCP6_OPT_CLIENT_ID 1 /// Client Identifier Option
#define DHCP6_OPT_SERVER_ID 2 /// Server Identifier Option
#define DHCP6_OPT_IA_NA 3 /// The Identity Association for Non-temporary Addresses option
#define DHCP6_OPT_IA_TA 4 /// The Identity Association for the Temporary Addresses
#define DHCP6_OPT_IAADDR 5 /// IA Address option
#define DHCP6_OPT_ORO 6 /// Request option
#define DHCP6_OPT_PREFERENCE 7 /// Preference option
#define DHCP6_OPT_ELAPSED_TIME 8 /// Elapsed Time Option
#define DHCP6_OPT_REPLAY_MSG 9 /// Relay Message option
#define DHCP6_OPT_AUTH 11 /// Authentication option
#define DHCP6_OPT_UNICAST 12 /// Server Unicast Option
#define DHCP6_OPT_STATUS_CODE 13 /// Status Code Option
#define DHCP6_OPT_RAPID_COMMIT 14 /// Rapid Commit option
#define DHCP6_OPT_USER_CLASS 15 /// User Class option
#define DHCP6_OPT_VENDOR_CLASS 16 /// Vendor Class Option
#define DHCP6_OPT_VENDOR_OPTS 17 /// Vendor-specific Information Option
#define DHCP6_OPT_INTERFACE_ID 18 /// Interface-Id Option
#define DHCP6_OPT_RECONFIG_MSG 19 /// Reconfigure Message Option
#define DHCP6_OPT_RECONFIG_ACCEPT 20 /// Reconfigure Accept Option
#define DHCP6_OPT_DNS_SERVERS 23 /// DNS Configuration options, RFC 3646
#define DHCP6_OPT_BOOT_FILE_URL 59 /// Assigned by IANA, RFC 5970
#define DHCP6_OPT_BOOT_FILE_PARAM 60 /// Assigned by IANA, RFC 5970
#define DHCP6_OPT_ARCH 61 /// Assigned by IANA, RFC 5970
#define DHCP6_OPT_UNDI 62 /// Assigned by IANA, RFC 5970
///
/// Processor Architecture Types
/// These identifiers are defined by IETF:
/// http://www.ietf.org/assignments/dhcpv6-parameters/dhcpv6-parameters.xml
///
#define PXE_CLIENT_ARCH_X86_BIOS 0x0000 /// x86 BIOS for PXE
#define PXE_CLIENT_ARCH_IPF 0x0002 /// Itanium for PXE
#define PXE_CLIENT_ARCH_IA32 0x0006 /// x86 uefi for PXE
#define PXE_CLIENT_ARCH_X64 0x0007 /// x64 uefi for PXE
#define PXE_CLIENT_ARCH_EBC 0x0009 /// EBC for PXE
#define PXE_CLIENT_ARCH_ARM 0x000A /// Arm uefi 32 for PXE
#define PXE_CLIENT_ARCH_AARCH64 0x000B /// Arm uefi 64 for PXE
#define PXE_CLIENT_ARCH_RISCV32 0x0019 /// RISC-V uefi 32 for PXE
#define PXE_CLIENT_ARCH_RISCV64 0x001B /// RISC-V uefi 64 for PXE
#define PXE_CLIENT_ARCH_RISCV128 0x001D /// RISC-V uefi 128 for PXE
#define HTTP_CLIENT_ARCH_IA32 0x000F /// x86 uefi boot from http
#define HTTP_CLIENT_ARCH_X64 0x0010 /// x64 uefi boot from http
#define HTTP_CLIENT_ARCH_EBC 0x0011 /// EBC boot from http
#define HTTP_CLIENT_ARCH_ARM 0x0012 /// Arm uefi 32 boot from http
#define HTTP_CLIENT_ARCH_AARCH64 0x0013 /// Arm uefi 64 boot from http
#define HTTP_CLIENT_ARCH_RISCV32 0x001A /// RISC-V uefi 32 boot from http
#define HTTP_CLIENT_ARCH_RISCV64 0x001C /// RISC-V uefi 64 boot from http
#define HTTP_CLIENT_ARCH_RISCV128 0x001E /// RISC-V uefi 128 boot from http
#endif

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/** @file
DMA Remapping Reporting (DMAR) ACPI table definition from Intel(R)
Virtualization Technology for Directed I/O (VT-D) Architecture Specification.
Copyright (c) 2016 - 2020, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@par Revision Reference:
- Intel(R) Virtualization Technology for Directed I/O (VT-D) Architecture
Specification v3.2, Dated October 2020.
https://software.intel.com/content/dam/develop/external/us/en/documents/vt-directed-io-spec.pdf
@par Glossary:
- HPET - High Precision Event Timer
- NUMA - Non-uniform Memory Access
**/
#ifndef _DMA_REMAPPING_REPORTING_TABLE_H_
#define _DMA_REMAPPING_REPORTING_TABLE_H_
#include <IndustryStandard/Acpi.h>
#pragma pack(1)
///
/// DMA-Remapping Reporting Structure definitions from section 8.1
///@{
#define EFI_ACPI_DMAR_REVISION 0x01
#define EFI_ACPI_DMAR_FLAGS_INTR_REMAP BIT0
#define EFI_ACPI_DMAR_FLAGS_X2APIC_OPT_OUT BIT1
#define EFI_ACPI_DMAR_FLAGS_DMA_CTRL_PLATFORM_OPT_IN_FLAG BIT2
///@}
///
/// Remapping Structure Types definitions from section 8.2
///@{
#define EFI_ACPI_DMAR_TYPE_DRHD 0x00
#define EFI_ACPI_DMAR_TYPE_RMRR 0x01
#define EFI_ACPI_DMAR_TYPE_ATSR 0x02
#define EFI_ACPI_DMAR_TYPE_RHSA 0x03
#define EFI_ACPI_DMAR_TYPE_ANDD 0x04
#define EFI_ACPI_DMAR_TYPE_SATC 0x05
///@}
///
/// DMA-Remapping Hardware Unit definitions from section 8.3
///
#define EFI_ACPI_DMAR_DRHD_FLAGS_INCLUDE_PCI_ALL BIT0
///
/// DMA-Remapping Device Scope Entry Structure definitions from section 8.3.1
///@{
#define EFI_ACPI_DEVICE_SCOPE_ENTRY_TYPE_PCI_ENDPOINT 0x01
#define EFI_ACPI_DEVICE_SCOPE_ENTRY_TYPE_PCI_BRIDGE 0x02
#define EFI_ACPI_DEVICE_SCOPE_ENTRY_TYPE_IOAPIC 0x03
#define EFI_ACPI_DEVICE_SCOPE_ENTRY_TYPE_MSI_CAPABLE_HPET 0x04
#define EFI_ACPI_DEVICE_SCOPE_ENTRY_TYPE_ACPI_NAMESPACE_DEVICE 0x05
///@}
///
/// Root Port ATS Capability Reporting Structure definitions from section 8.5
///
#define EFI_ACPI_DMAR_ATSR_FLAGS_ALL_PORTS BIT0
///
/// Definition for DMA Remapping Structure Header
///
typedef struct {
UINT16 Type;
UINT16 Length;
} EFI_ACPI_DMAR_STRUCTURE_HEADER;
///
/// Definition for DMA-Remapping PCI Path
///
typedef struct {
UINT8 Device;
UINT8 Function;
} EFI_ACPI_DMAR_PCI_PATH;
///
/// Device Scope Structure is defined in section 8.3.1
///
typedef struct {
UINT8 Type;
UINT8 Length;
UINT16 Reserved2;
UINT8 EnumerationId;
UINT8 StartBusNumber;
} EFI_ACPI_DMAR_DEVICE_SCOPE_STRUCTURE_HEADER;
/**
DMA-remapping hardware unit definition (DRHD) structure is defined in
section 8.3. This uniquely represents a remapping hardware unit present
in the platform. There must be at least one instance of this structure
for each PCI segment in the platform.
**/
typedef struct {
EFI_ACPI_DMAR_STRUCTURE_HEADER Header;
/**
- Bit[0]: INCLUDE_PCI_ALL
- If Set, this remapping hardware unit has under its scope all
PCI compatible devices in the specified Segment, except devices
reported under the scope of other remapping hardware units for
the same Segment.
- If Clear, this remapping hardware unit has under its scope only
devices in the specified Segment that are explicitly identified
through the DeviceScope field.
- Bits[7:1] Reserved.
**/
UINT8 Flags;
UINT8 Reserved;
///
/// The PCI Segment associated with this unit.
///
UINT16 SegmentNumber;
///
/// Base address of remapping hardware register-set for this unit.
///
UINT64 RegisterBaseAddress;
} EFI_ACPI_DMAR_DRHD_HEADER;
/**
Reserved Memory Region Reporting Structure (RMRR) is described in section 8.4
Reserved memory ranges that may be DMA targets may be reported through the
RMRR structures, along with the devices that requires access to the specified
reserved memory region.
**/
typedef struct {
EFI_ACPI_DMAR_STRUCTURE_HEADER Header;
UINT8 Reserved[2];
///
/// PCI Segment Number associated with devices identified through
/// the Device Scope field.
///
UINT16 SegmentNumber;
///
/// Base address of 4KB-aligned reserved memory region
///
UINT64 ReservedMemoryRegionBaseAddress;
/**
Last address of the reserved memory region. Value in this field must be
greater than the value in Reserved Memory Region Base Address field.
The reserved memory region size (Limit - Base + 1) must be an integer
multiple of 4KB.
**/
UINT64 ReservedMemoryRegionLimitAddress;
} EFI_ACPI_DMAR_RMRR_HEADER;
/**
Root Port ATS Capability Reporting (ATSR) structure is defined in section 8.5.
This structure is applicable only for platforms supporting Device-TLBs as
reported through the Extended Capability Register. For each PCI Segment in
the platform that supports Device-TLBs, BIOS provides an ATSR structure. The
ATSR structures identifies PCI-Express Root-Ports supporting Address
Translation Services (ATS) transactions. Software must enable ATS on endpoint
devices behind a Root Port only if the Root Port is reported as supporting
ATS transactions.
**/
typedef struct {
EFI_ACPI_DMAR_STRUCTURE_HEADER Header;
/**
- Bit[0]: ALL_PORTS:
- If Set, indicates all PCI Express Root Ports in the specified
PCI Segment supports ATS transactions.
- If Clear, indicates ATS transactions are supported only on
Root Ports identified through the Device Scope field.
- Bits[7:1] Reserved.
**/
UINT8 Flags;
UINT8 Reserved;
///
/// The PCI Segment associated with this ATSR structure
///
UINT16 SegmentNumber;
} EFI_ACPI_DMAR_ATSR_HEADER;
/**
Remapping Hardware Static Affinity (RHSA) is an optional structure defined
in section 8.6. This is intended to be used only on NUMA platforms with
Remapping hardware units and memory spanned across multiple nodes.
When used, there must be a RHSA structure for each Remapping hardware unit
reported through DRHD structure.
**/
typedef struct {
EFI_ACPI_DMAR_STRUCTURE_HEADER Header;
UINT8 Reserved[4];
///
/// Register Base Address of this Remap hardware unit reported in the
/// corresponding DRHD structure.
///
UINT64 RegisterBaseAddress;
///
/// Proximity Domain to which the Remap hardware unit identified by the
/// Register Base Address field belongs.
///
UINT32 ProximityDomain;
} EFI_ACPI_DMAR_RHSA_HEADER;
/**
An ACPI Name-space Device Declaration (ANDD) structure is defined in section
8.7 and uniquely represents an ACPI name-space enumerated device capable of
issuing DMA requests in the platform. ANDD structures are used in conjunction
with Device-Scope entries of type ACPI_NAMESPACE_DEVICE.
**/
typedef struct {
EFI_ACPI_DMAR_STRUCTURE_HEADER Header;
UINT8 Reserved[3];
/**
Each ACPI device enumerated through an ANDD structure must have a unique
value for this field. To report an ACPI device with ACPI Device Number
value of X, under the scope of a DRHD unit, a Device-Scope entry of type
ACPI_NAMESPACE_DEVICE is used with value of X in the Enumeration ID field.
The Start Bus Number and Path fields in the Device-Scope together
provides the 16-bit source-id allocated by platform for the ACPI device.
**/
UINT8 AcpiDeviceNumber;
} EFI_ACPI_DMAR_ANDD_HEADER;
/**
An SoC Integrated Address Translation Cache (SATC) reporting structure is
defined in section 8.8.
**/
typedef struct {
EFI_ACPI_DMAR_STRUCTURE_HEADER Header;
/**
- Bit[0]: ATC_REQUIRED:
- If Set, indicates that every SoC integrated device enumerated
in this table has a functional requirement to enable its ATC
(via the ATS capability) for device operation.
- If Clear, any device enumerated in this table can operate when
its respective ATC is not enabled (albeit with reduced
performance or functionality).
- Bits[7:1] Reserved.
**/
UINT8 Flags;
UINT8 Reserved;
///
/// The PCI Segment associated with this SATC structure. All SoC integrated
/// devices within a PCI segment with same value for Flags field must be
/// enumerated in the same SATC structure.
///
UINT16 SegmentNumber;
} EFI_ACPI_DMAR_SATC_HEADER;
/**
DMA Remapping Reporting Structure Header as defined in section 8.1
This header will be followed by list of Remapping Structures listed below
- DMA Remapping Hardware Unit Definition (DRHD)
- Reserved Memory Region Reporting (RMRR)
- Root Port ATS Capability Reporting (ATSR)
- Remapping Hardware Static Affinity (RHSA)
- ACPI Name-space Device Declaration (ANDD)
- SoC Integrated Address Translation Cache reporting (SATC)
These structure types must by reported in numerical order.
i.e., All remapping structures of type 0 (DRHD) enumerated before remapping
structures of type 1 (RMRR), and so forth.
**/
typedef struct {
EFI_ACPI_DESCRIPTION_HEADER Header;
/**
This field indicates the maximum DMA physical addressability supported by
this platform. The system address map reported by the BIOS indicates what
portions of this addresses are populated. The Host Address Width (HAW) of
the platform is computed as (N+1), where N is the value reported in this
field.
For example, for a platform supporting 40 bits of physical addressability,
the value of 100111b is reported in this field.
**/
UINT8 HostAddressWidth;
/**
- Bit[0]: INTR_REMAP - If Clear, the platform does not support interrupt
remapping. If Set, the platform supports interrupt remapping.
- Bit[1]: X2APIC_OPT_OUT - For firmware compatibility reasons, platform
firmware may Set this field to request system software to opt
out of enabling Extended xAPIC (X2APIC) mode. This field is
valid only when the INTR_REMAP field (bit 0) is Set.
- Bit[2]: DMA_CTRL_PLATFORM_OPT_IN_FLAG - Platform firmware is
recommended to Set this field to report any platform initiated
DMA is restricted to only reserved memory regions (reported in
RMRR structures) when transferring control to system software
such as on ExitBootServices().
- Bits[7:3] Reserved.
**/
UINT8 Flags;
UINT8 Reserved[10];
} EFI_ACPI_DMAR_HEADER;
#pragma pack()
#endif

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/** @file
ElTorito Partitions Format Definition.
This file includes some definitions from
1. "El Torito" Bootable CD-ROM Format Specification, Version 1.0.
2. Volume and File Structure of CDROM for Information Interchange,
Standard ECMA-119. (IS0 9660)
Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef _ELTORITO_H_
#define _ELTORITO_H_
//
// CDROM_VOLUME_DESCRIPTOR.Types, defined in ISO 9660
//
#define CDVOL_TYPE_STANDARD 0x0
#define CDVOL_TYPE_CODED 0x1
#define CDVOL_TYPE_END 0xFF
///
/// CDROM_VOLUME_DESCRIPTOR.Id
///
#define CDVOL_ID "CD001"
///
/// CDROM_VOLUME_DESCRIPTOR.SystemId
///
#define CDVOL_ELTORITO_ID "EL TORITO SPECIFICATION"
//
// Indicator types
//
#define ELTORITO_ID_CATALOG 0x01
#define ELTORITO_ID_SECTION_BOOTABLE 0x88
#define ELTORITO_ID_SECTION_NOT_BOOTABLE 0x00
#define ELTORITO_ID_SECTION_HEADER 0x90
#define ELTORITO_ID_SECTION_HEADER_FINAL 0x91
//
// ELTORITO_CATALOG.Boot.MediaTypes
//
#define ELTORITO_NO_EMULATION 0x00
#define ELTORITO_12_DISKETTE 0x01
#define ELTORITO_14_DISKETTE 0x02
#define ELTORITO_28_DISKETTE 0x03
#define ELTORITO_HARD_DISK 0x04
#pragma pack(1)
///
/// CD-ROM Volume Descriptor
///
typedef union {
struct {
UINT8 Type;
CHAR8 Id[5]; ///< "CD001"
CHAR8 Reserved[82];
} Unknown;
///
/// Boot Record Volume Descriptor, defined in "El Torito" Specification.
///
struct {
UINT8 Type; ///< Must be 0
CHAR8 Id[5]; ///< "CD001"
UINT8 Version; ///< Must be 1
CHAR8 SystemId[32]; ///< "EL TORITO SPECIFICATION"
CHAR8 Unused[32]; ///< Must be 0
UINT8 EltCatalog[4]; ///< Absolute pointer to first sector of Boot Catalog
CHAR8 Unused2[13]; ///< Must be 0
} BootRecordVolume;
///
/// Primary Volume Descriptor, defined in ISO 9660.
///
struct {
UINT8 Type;
CHAR8 Id[5]; ///< "CD001"
UINT8 Version;
UINT8 Unused; ///< Must be 0
CHAR8 SystemId[32];
CHAR8 VolumeId[32];
UINT8 Unused2[8]; ///< Must be 0
UINT32 VolSpaceSize[2]; ///< the number of Logical Blocks
} PrimaryVolume;
} CDROM_VOLUME_DESCRIPTOR;
///
/// Catalog Entry
///
typedef union {
struct {
CHAR8 Reserved[0x20];
} Unknown;
///
/// Catalog validation entry (Catalog header)
///
struct {
UINT8 Indicator; ///< Must be 01
UINT8 PlatformId;
UINT16 Reserved;
CHAR8 ManufacId[24];
UINT16 Checksum;
UINT16 Id55AA;
} Catalog;
///
/// Initial/Default Entry or Section Entry
///
struct {
UINT8 Indicator; ///< 88 = Bootable, 00 = Not Bootable
UINT8 MediaType : 4;
UINT8 Reserved1 : 4; ///< Must be 0
UINT16 LoadSegment;
UINT8 SystemType;
UINT8 Reserved2; ///< Must be 0
UINT16 SectorCount;
UINT32 Lba;
} Boot;
///
/// Section Header Entry
///
struct {
UINT8 Indicator; ///< 90 - Header, more header follw, 91 - Final Header
UINT8 PlatformId;
UINT16 SectionEntries; ///< Number of section entries following this header
CHAR8 Id[28];
} Section;
} ELTORITO_CATALOG;
#pragma pack()
#endif

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/** @file
Header file for eMMC support.
This header file contains some definitions defined in EMMC4.5/EMMC5.0 spec.
Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef __EMMC_H__
#define __EMMC_H__
//
// EMMC command index
//
#define EMMC_GO_IDLE_STATE 0
#define EMMC_SEND_OP_COND 1
#define EMMC_ALL_SEND_CID 2
#define EMMC_SET_RELATIVE_ADDR 3
#define EMMC_SET_DSR 4
#define EMMC_SLEEP_AWAKE 5
#define EMMC_SWITCH 6
#define EMMC_SELECT_DESELECT_CARD 7
#define EMMC_SEND_EXT_CSD 8
#define EMMC_SEND_CSD 9
#define EMMC_SEND_CID 10
#define EMMC_STOP_TRANSMISSION 12
#define EMMC_SEND_STATUS 13
#define EMMC_BUSTEST_R 14
#define EMMC_GO_INACTIVE_STATE 15
#define EMMC_SET_BLOCKLEN 16
#define EMMC_READ_SINGLE_BLOCK 17
#define EMMC_READ_MULTIPLE_BLOCK 18
#define EMMC_BUSTEST_W 19
#define EMMC_SEND_TUNING_BLOCK 21
#define EMMC_SET_BLOCK_COUNT 23
#define EMMC_WRITE_BLOCK 24
#define EMMC_WRITE_MULTIPLE_BLOCK 25
#define EMMC_PROGRAM_CID 26
#define EMMC_PROGRAM_CSD 27
#define EMMC_SET_WRITE_PROT 28
#define EMMC_CLR_WRITE_PROT 29
#define EMMC_SEND_WRITE_PROT 30
#define EMMC_SEND_WRITE_PROT_TYPE 31
#define EMMC_ERASE_GROUP_START 35
#define EMMC_ERASE_GROUP_END 36
#define EMMC_ERASE 38
#define EMMC_FAST_IO 39
#define EMMC_GO_IRQ_STATE 40
#define EMMC_LOCK_UNLOCK 42
#define EMMC_SET_TIME 49
#define EMMC_PROTOCOL_RD 53
#define EMMC_PROTOCOL_WR 54
#define EMMC_APP_CMD 55
#define EMMC_GEN_CMD 56
typedef enum {
EmmcPartitionUserData = 0,
EmmcPartitionBoot1 = 1,
EmmcPartitionBoot2 = 2,
EmmcPartitionRPMB = 3,
EmmcPartitionGP1 = 4,
EmmcPartitionGP2 = 5,
EmmcPartitionGP3 = 6,
EmmcPartitionGP4 = 7,
EmmcPartitionUnknown
} EMMC_PARTITION_TYPE;
#pragma pack(1)
typedef struct {
UINT8 NotUsed:1; // Not used [0:0]
UINT8 Crc:7; // CRC [7:1]
UINT8 ManufacturingDate; // Manufacturing date [15:8]
UINT8 ProductSerialNumber[4]; // Product serial number [47:16]
UINT8 ProductRevision; // Product revision [55:48]
UINT8 ProductName[6]; // Product name [103:56]
UINT8 OemId; // OEM/Application ID [111:104]
UINT8 DeviceType:2; // Device/BGA [113:112]
UINT8 Reserved:6; // Reserved [119:114]
UINT8 ManufacturerId; // Manufacturer ID [127:120]
} EMMC_CID;
typedef struct {
UINT32 NotUsed:1; // Not used [0:0]
UINT32 Crc:7; // CRC [7:1]
UINT32 Ecc:2; // ECC code [9:8]
UINT32 FileFormat:2; // File format [11:10]
UINT32 TmpWriteProtect:1; // Temporary write protection [12:12]
UINT32 PermWriteProtect:1; // Permanent write protection [13:13]
UINT32 Copy:1; // Copy flag (OTP) [14:14]
UINT32 FileFormatGrp:1; // File format group [15:15]
UINT32 ContentProtApp:1; // Content protection application [16:16]
UINT32 Reserved:4; // Reserved [20:17]
UINT32 WriteBlPartial:1; // Partial blocks for write allowed [21:21]
UINT32 WriteBlLen:4; // Max. write data block length [25:22]
UINT32 R2WFactor:3; // Write speed factor [28:26]
UINT32 DefaultEcc:2; // Manufacturer default ECC [30:29]
UINT32 WpGrpEnable:1; // Write protect group enable [31:31]
UINT32 WpGrpSize:5; // Write protect group size [36:32]
UINT32 EraseGrpMult:5; // Erase group size multiplier [41:37]
UINT32 EraseGrpSize:5; // Erase group size [46:42]
UINT32 CSizeMult:3; // Device size multiplier [49:47]
UINT32 VddWCurrMax:3; // Max. write current @ VDD max [52:50]
UINT32 VddWCurrMin:3; // Max. write current @ VDD min [55:53]
UINT32 VddRCurrMax:3; // Max. read current @ VDD max [58:56]
UINT32 VddRCurrMin:3; // Max. read current @ VDD min [61:59]
UINT32 CSizeLow:2; // Device size low two bits [63:62]
UINT32 CSizeHigh:10; // Device size high eight bits [73:64]
UINT32 Reserved1:2; // Reserved [75:74]
UINT32 DsrImp:1; // DSR implemented [76:76]
UINT32 ReadBlkMisalign:1; // Read block misalignment [77:77]
UINT32 WriteBlkMisalign:1; // Write block misalignment [78:78]
UINT32 ReadBlPartial:1; // Partial blocks for read allowed [79:79]
UINT32 ReadBlLen:4; // Max. read data block length [83:80]
UINT32 Ccc:12; // Device command classes [95:84]
UINT32 TranSpeed:8; // Max. bus clock frequency [103:96]
UINT32 Nsac:8; // Data read access-time 2 in CLK cycles (NSAC*100) [111:104]
UINT32 Taac:8; // Data read access-time 1 [119:112]
UINT32 Reserved2:2; // Reserved [121:120]
UINT32 SpecVers:4; // System specification version [125:122]
UINT32 CsdStructure:2; // CSD structure [127:126]
} EMMC_CSD;
typedef struct {
//
// Modes Segment
//
UINT8 Reserved[16]; // Reserved [15:0]
UINT8 SecureRemovalType; // Secure Removal Type R/W & R [16]
UINT8 ProductStateAwarenessEnablement; // Product state awareness enablement R/W/E & R [17]
UINT8 MaxPreLoadingDataSize[4]; // Max pre loading data size R [21:18]
UINT8 PreLoadingDataSize[4]; // Pre loading data size R/W/EP [25:22]
UINT8 FfuStatus; // FFU status R [26]
UINT8 Reserved1[2]; // Reserved [28:27]
UINT8 ModeOperationCodes; // Mode operation codes W/EP [29]
UINT8 ModeConfig; // Mode config R/W/EP [30]
UINT8 Reserved2; // Reserved [31]
UINT8 FlushCache; // Flushing of the cache W/EP [32]
UINT8 CacheCtrl; // Control to turn the Cache ON/OFF R/W/EP [33]
UINT8 PowerOffNotification; // Power Off Notification R/W/EP [34]
UINT8 PackedFailureIndex; // Packed command failure index R [35]
UINT8 PackedCommandStatus; // Packed command status R [36]
UINT8 ContextConf[15]; // Context configuration R/W/EP [51:37]
UINT8 ExtPartitionsAttribute[2]; // Extended Partitions Attribute R/W [53:52]
UINT8 ExceptionEventsStatus[2]; // Exception events status R [55:54]
UINT8 ExceptionEventsCtrl[2]; // Exception events control R/W/EP [57:56]
UINT8 DyncapNeeded; // Number of addressed group to be Released R [58]
UINT8 Class6Ctrl; // Class 6 commands control R/W/EP [59]
UINT8 IniTimeoutEmu; // 1st initialization after disabling sector size emulation R [60]
UINT8 DataSectorSize; // Sector size R [61]
UINT8 UseNativeSector; // Sector size emulation R/W [62]
UINT8 NativeSectorSize; // Native sector size R [63]
UINT8 VendorSpecificField[64]; // Vendor Specific Fields <vendor specific> [127:64]
UINT8 Reserved3[2]; // Reserved [129:128]
UINT8 ProgramCidCsdDdrSupport; // Program CID/CSD in DDR mode support R [130]
UINT8 PeriodicWakeup; // Periodic Wake-up R/W/E [131]
UINT8 TcaseSupport; // Package Case Temperature is controlled W/EP [132]
UINT8 ProductionStateAwareness; // Production state awareness R/W/E [133]
UINT8 SecBadBlkMgmnt; // Bad Block Management mode R/W [134]
UINT8 Reserved4; // Reserved [135]
UINT8 EnhStartAddr[4]; // Enhanced User Data Start Address R/W [139:136]
UINT8 EnhSizeMult[3]; // Enhanced User Data Area Size R/W [142:140]
UINT8 GpSizeMult[12]; // General Purpose Partition Size R/W [154:143]
UINT8 PartitionSettingCompleted; // Partitioning Setting R/W [155]
UINT8 PartitionsAttribute; // Partitions attribute R/W [156]
UINT8 MaxEnhSizeMult[3]; // Max Enhanced Area Size R [159:157]
UINT8 PartitioningSupport; // Partitioning Support R [160]
UINT8 HpiMgmt; // HPI management R/W/EP [161]
UINT8 RstFunction; // H/W reset function R/W [162]
UINT8 BkopsEn; // Enable background operations handshake R/W [163]
UINT8 BkopsStart; // Manually start background operations W/EP [164]
UINT8 SanitizeStart; // Start Sanitize operation W/EP [165]
UINT8 WrRelParam; // Write reliability parameter register R [166]
UINT8 WrRelSet; // Write reliability setting register R/W [167]
UINT8 RpmbSizeMult; // RPMB Size R [168]
UINT8 FwConfig; // FW configuration R/W [169]
UINT8 Reserved5; // Reserved [170]
UINT8 UserWp; // User area write protection register R/W,R/W/CP&R/W/EP [171]
UINT8 Reserved6; // Reserved [172]
UINT8 BootWp; // Boot area write protection register R/W&R/W/CP[173]
UINT8 BootWpStatus; // Boot write protection status registers R [174]
UINT8 EraseGroupDef; // High-density erase group definition R/W/EP [175]
UINT8 Reserved7; // Reserved [176]
UINT8 BootBusConditions; // Boot bus Conditions R/W/E [177]
UINT8 BootConfigProt; // Boot config protection R/W&R/W/CP[178]
UINT8 PartitionConfig; // Partition configuration R/W/E&R/W/EP[179]
UINT8 Reserved8; // Reserved [180]
UINT8 ErasedMemCont; // Erased memory content R [181]
UINT8 Reserved9; // Reserved [182]
UINT8 BusWidth; // Bus width mode W/EP [183]
UINT8 Reserved10; // Reserved [184]
UINT8 HsTiming; // High-speed interface timing R/W/EP [185]
UINT8 Reserved11; // Reserved [186]
UINT8 PowerClass; // Power class R/W/EP [187]
UINT8 Reserved12; // Reserved [188]
UINT8 CmdSetRev; // Command set revision R [189]
UINT8 Reserved13; // Reserved [190]
UINT8 CmdSet; // Command set R/W/EP [191]
//
// Properties Segment
//
UINT8 ExtCsdRev; // Extended CSD revision [192]
UINT8 Reserved14; // Reserved [193]
UINT8 CsdStructure; // CSD STRUCTURE [194]
UINT8 Reserved15; // Reserved [195]
UINT8 DeviceType; // Device type [196]
UINT8 DriverStrength; // I/O Driver Strength [197]
UINT8 OutOfInterruptTime; // Out-of-interrupt busy timing[198]
UINT8 PartitionSwitchTime; // Partition switching timing [199]
UINT8 PwrCl52M195V; // Power class for 52MHz at 1.95V [200]
UINT8 PwrCl26M195V; // Power class for 26MHz at 1.95V [201]
UINT8 PwrCl52M360V; // Power class for 52MHz at 3.6V [202]
UINT8 PwrCl26M360V; // Power class for 26MHz at 3.6V [203]
UINT8 Reserved16; // Reserved [204]
UINT8 MinPerfR4B26M; // Minimum Read Performance for 4bit at 26MHz [205]
UINT8 MinPerfW4B26M; // Minimum Write Performance for 4bit at 26MHz [206]
UINT8 MinPerfR8B26M4B52M; // Minimum Read Performance for 8bit at 26MHz, for 4bit at 52MHz [207]
UINT8 MinPerfW8B26M4B52M; // Minimum Write Performance for 8bit at 26MHz, for 4bit at 52MHz [208]
UINT8 MinPerfR8B52M; // Minimum Read Performance for 8bit at 52MHz [209]
UINT8 MinPerfW8B52M; // Minimum Write Performance for 8bit at 52MHz [210]
UINT8 Reserved17; // Reserved [211]
UINT8 SecCount[4]; // Sector Count [215:212]
UINT8 SleepNotificationTime; // Sleep Notification Timeout [216]
UINT8 SATimeout; // Sleep/awake timeout [217]
UINT8 ProductionStateAwarenessTimeout; // Production state awareness timeout [218]
UINT8 SCVccq; // Sleep current (VCCQ) [219]
UINT8 SCVcc; // Sleep current (VCC) [220]
UINT8 HcWpGrpSize; // High-capacity write protect group size [221]
UINT8 RelWrSecC; // Reliable write sector count [222]
UINT8 EraseTimeoutMult; // High-capacity erase timeout [223]
UINT8 HcEraseGrpSize; // High-capacity erase unit size [224]
UINT8 AccSize; // Access size [225]
UINT8 BootSizeMult; // Boot partition size [226]
UINT8 Reserved18; // Reserved [227]
UINT8 BootInfo; // Boot information [228]
UINT8 SecTrimMult; // Secure TRIM Multiplier [229]
UINT8 SecEraseMult; // Secure Erase Multiplier [230]
UINT8 SecFeatureSupport; // Secure Feature support [231]
UINT8 TrimMult; // TRIM Multiplier [232]
UINT8 Reserved19; // Reserved [233]
UINT8 MinPerfDdrR8b52M; // Minimum Read Performance for 8bit at 52MHz in DDR mode [234]
UINT8 MinPerfDdrW8b52M; // Minimum Write Performance for 8bit at 52MHz in DDR mode [235]
UINT8 PwrCl200M130V; // Power class for 200MHz, at VCCQ=1.3V, VCC = 3.6V [236]
UINT8 PwrCl200M195V; // Power class for 200MHz at VCCQ=1.95V, VCC = 3.6V [237]
UINT8 PwrClDdr52M195V; // Power class for 52MHz, DDR at VCC= 1.95V [238]
UINT8 PwrClDdr52M360V; // Power class for 52MHz, DDR at VCC= 3.6V [239]
UINT8 Reserved20; // Reserved [240]
UINT8 IniTimeoutAp; // 1st initialization time after partitioning [241]
UINT8 CorrectlyPrgSectorsNum[4]; // Number of correctly programmed sectors [245:242]
UINT8 BkopsStatus; // Background operations status [246]
UINT8 PowerOffLongTime; // Power off notification(long) timeout [247]
UINT8 GenericCmd6Time; // Generic CMD6 timeout [248]
UINT8 CacheSize[4]; // Cache size [252:249]
UINT8 PwrClDdr200M360V; // Power class for 200MHz, DDR at VCC= 3.6V [253]
UINT8 FirmwareVersion[8]; // Firmware version [261:254]
UINT8 DeviceVersion[2]; // Device version [263:262]
UINT8 OptimalTrimUnitSize; // Optimal trim unit size[264]
UINT8 OptimalWriteSize; // Optimal write size [265]
UINT8 OptimalReadSize; // Optimal read size [266]
UINT8 PreEolInfo; // Pre EOL information [267]
UINT8 DeviceLifeTimeEstTypA; // Device life time estimation type A [268]
UINT8 DeviceLifeTimeEstTypB; // Device life time estimation type B [269]
UINT8 VendorProprietaryHealthReport[32]; // Vendor proprietary health report [301:270]
UINT8 NumOfFwSectorsProgrammed[4]; // Number of FW sectors correctly programmed [305:302]
UINT8 Reserved21[181]; // Reserved [486:306]
UINT8 FfuArg[4]; // FFU Argument [490:487]
UINT8 OperationCodeTimeout; // Operation codes timeout [491]
UINT8 FfuFeatures; // FFU features [492]
UINT8 SupportedModes; // Supported modes [493]
UINT8 ExtSupport; // Extended partitions attribute support [494]
UINT8 LargeUnitSizeM1; // Large Unit size [495]
UINT8 ContextCapabilities; // Context management capabilities [496]
UINT8 TagResSize; // Tag Resources Size [497]
UINT8 TagUnitSize; // Tag Unit Size [498]
UINT8 DataTagSupport; // Data Tag Support [499]
UINT8 MaxPackedWrites; // Max packed write commands [500]
UINT8 MaxPackedReads; // Max packed read commands[501]
UINT8 BkOpsSupport; // Background operations support [502]
UINT8 HpiFeatures; // HPI features [503]
UINT8 SupportedCmdSet; // Supported Command Sets [504]
UINT8 ExtSecurityErr; // Extended Security Commands Error [505]
UINT8 Reserved22[6]; // Reserved [511:506]
} EMMC_EXT_CSD;
#pragma pack()
#endif

62
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/** @file
ACPI high precision event timer table definition, at www.intel.com
Specification name is IA-PC HPET (High Precision Event Timers) Specification.
Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef _HIGH_PRECISION_EVENT_TIMER_TABLE_H_
#define _HIGH_PRECISION_EVENT_TIMER_TABLE_H_
#include <IndustryStandard/Acpi.h>
//
// Ensure proper structure formats
//
#pragma pack(1)
///
/// HPET Event Timer Block ID described in IA-PC HPET Specification, 3.2.4.
///
typedef union {
struct {
UINT32 Revision : 8;
UINT32 NumberOfTimers : 5;
UINT32 CounterSize : 1;
UINT32 Reserved : 1;
UINT32 LegacyRoute : 1;
UINT32 VendorId : 16;
} Bits;
UINT32 Uint32;
} EFI_ACPI_HIGH_PRECISION_EVENT_TIMER_BLOCK_ID;
///
/// High Precision Event Timer Table header definition.
///
typedef struct {
EFI_ACPI_DESCRIPTION_HEADER Header;
UINT32 EventTimerBlockId;
EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE BaseAddressLower32Bit;
UINT8 HpetNumber;
UINT16 MainCounterMinimumClockTickInPeriodicMode;
UINT8 PageProtectionAndOemAttribute;
} EFI_ACPI_HIGH_PRECISION_EVENT_TIMER_TABLE_HEADER;
///
/// HPET Revision (defined in spec)
///
#define EFI_ACPI_HIGH_PRECISION_EVENT_TIMER_TABLE_REVISION 0x01
//
// Page protection setting
// Values 3 through 15 are reserved for use by the specification
//
#define EFI_ACPI_NO_PAGE_PROTECTION 0
#define EFI_ACPI_4KB_PAGE_PROTECTION 1
#define EFI_ACPI_64KB_PAGE_PROTECTION 2
#pragma pack()
#endif

76
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/** @file
Support for HSTI 1.1a specification, defined at
Microsoft Hardware Security Testability Specification.
Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef __HSTI_H__
#define __HSTI_H__
#pragma pack(1)
#define ADAPTER_INFO_PLATFORM_SECURITY_GUID \
{0x6be272c7, 0x1320, 0x4ccd, { 0x90, 0x17, 0xd4, 0x61, 0x2c, 0x01, 0x2b, 0x25 }}
#define PLATFORM_SECURITY_VERSION_VNEXTCS 0x00000003
#define PLATFORM_SECURITY_ROLE_PLATFORM_REFERENCE 0x00000001 // IHV
#define PLATFORM_SECURITY_ROLE_PLATFORM_IBV 0x00000002
#define PLATFORM_SECURITY_ROLE_IMPLEMENTOR_OEM 0x00000003
#define PLATFORM_SECURITY_ROLE_IMPLEMENTOR_ODM 0x00000004
typedef struct {
//
// Return PLATFORM_SECURITY_VERSION_VNEXTCS
//
UINT32 Version;
//
// The role of the publisher of this interface. Reference platform designers
// such as IHVs and IBVs are expected to return PLATFORM_SECURITY_ROLE_PLATFORM_REFERENCE
// and PLATFORM_SECURITY_ROLE_PLATFORM_IBV respectively.
// If the test modules from the designers are unable to fully verify all
// security features, then the platform implementers, OEMs and ODMs, will
// need to publish this interface with a role of Implementer.
//
UINT32 Role;
//
// Human readable vendor, model, & version of this implementation.
//
CHAR16 ImplementationID[256];
//
// The size in bytes of the SecurityFeaturesRequired and SecurityFeaturesEnabled arrays.
// The arrays must be the same size.
//
UINT32 SecurityFeaturesSize;
//
// IHV-defined bitfield corresponding to all security features which must be
// implemented to meet the security requirements defined by PLATFORM_SECURITY_VERSION Version.
//
//UINT8 SecurityFeaturesRequired[]; //Ignored for non-IHV
//
// Publisher-defined bitfield corresponding to all security features which
// have implemented programmatic tests in this module.
//
//UINT8 SecurityFeaturesImplemented[];
//
// Publisher-defined bitfield corresponding to all security features which
// have been verified implemented by this implementation.
//
//UINT8 SecurityFeaturesVerified[];
//
// A Null-terminated string, one failure per line (CR/LF terminated), with a
// unique identifier that the OEM/ODM can use to locate the documentation
// which will describe the steps to remediate the failure - a URL to the
// documentation is recommended.
//
//CHAR16 ErrorString[];
} ADAPTER_INFO_PLATFORM_SECURITY;
#pragma pack()
extern EFI_GUID gAdapterInfoPlatformSecurityGuid;
#endif

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/** @file
Hypertext Transfer Protocol -- HTTP/1.1 Standard definitions, from RFC 2616
This file contains common HTTP 1.1 definitions from RFC 2616
(C) Copyright 2015-2016 Hewlett Packard Enterprise Development LP<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef __HTTP_11_H__
#define __HTTP_11_H__
#pragma pack(1)
///
/// HTTP Version (currently HTTP 1.1)
///
/// The version of an HTTP message is indicated by an HTTP-Version field
/// in the first line of the message.
///
#define HTTP_VERSION "HTTP/1.1"
///
/// HTTP Request Method definitions
///
/// The Method token indicates the method to be performed on the
/// resource identified by the Request-URI. The method is case-sensitive.
///
#define HTTP_METHOD_OPTIONS "OPTIONS"
#define HTTP_METHOD_GET "GET"
#define HTTP_METHOD_HEAD "HEAD"
#define HTTP_METHOD_POST "POST"
#define HTTP_METHOD_PUT "PUT"
#define HTTP_METHOD_DELETE "DELETE"
#define HTTP_METHOD_TRACE "TRACE"
#define HTTP_METHOD_CONNECT "CONNECT"
#define HTTP_METHOD_PATCH "PATCH"
///
/// Connect method has maximum length according to EFI_HTTP_METHOD defined in
/// UEFI2.5 spec so use this.
///
#define HTTP_METHOD_MAXIMUM_LEN sizeof (HTTP_METHOD_CONNECT)
///
/// Accept Request Header
/// The Accept request-header field can be used to specify certain media types which are
/// acceptable for the response. Accept headers can be used to indicate that the request
/// is specifically limited to a small set of desired types, as in the case of a request
/// for an in-line image.
///
#define HTTP_HEADER_ACCEPT "Accept"
///
/// Accept-Charset Request Header
/// The Accept-Charset request-header field can be used to indicate what character sets
/// are acceptable for the response. This field allows clients capable of understanding
/// more comprehensive or special-purpose character sets to signal that capability to a
/// server which is capable of representing documents in those character sets.
///
#define HTTP_HEADER_ACCEPT_CHARSET "Accept-Charset"
///
/// Accept-Language Request Header
/// The Accept-Language request-header field is similar to Accept,
/// but restricts the set of natural languages that are preferred
/// as a response to the request.
///
#define HTTP_HEADER_ACCEPT_LANGUAGE "Accept-Language"
///
/// Accept-Ranges Request Header
/// The Accept-Ranges response-header field allows the server to
/// indicate its acceptance of range requests for a resource:
///
#define HTTP_HEADER_ACCEPT_RANGES "Accept-Ranges"
///
/// Accept-Encoding Request Header
/// The Accept-Encoding request-header field is similar to Accept,
/// but restricts the content-codings that are acceptable in the response.
///
#define HTTP_HEADER_ACCEPT_ENCODING "Accept-Encoding"
///
/// Content-Encoding Header
/// The Content-Encoding entity-header field is used as a modifier to the media-type.
/// When present, its value indicates what additional content codings have been applied
/// to the entity-body, and thus what decoding mechanisms must be applied in order to
/// obtain the media-type referenced by the Content-Type header field. Content-Encoding
/// is primarily used to allow a document to be compressed without losing the identity
/// of its underlying media type.
///
#define HTTP_HEADER_CONTENT_ENCODING "Content-Encoding"
///
/// HTTP Content-Encoding Compression types
///
#define HTTP_CONTENT_ENCODING_IDENTITY "identity" /// No transformation is used. This is the default value for content coding.
#define HTTP_CONTENT_ENCODING_GZIP "gzip" /// Content-Encoding: GNU zip format (described in RFC 1952).
#define HTTP_CONTENT_ENCODING_COMPRESS "compress" /// encoding format produced by the common UNIX file compression program "compress".
#define HTTP_CONTENT_ENCODING_DEFLATE "deflate" /// The "zlib" format defined in RFC 1950 in combination with the "deflate"
/// compression mechanism described in RFC 1951.
///
/// Content-Type Header
/// The Content-Type entity-header field indicates the media type of the entity-body sent to
/// the recipient or, in the case of the HEAD method, the media type that would have been sent
/// had the request been a GET.
///
#define HTTP_HEADER_CONTENT_TYPE "Content-Type"
//
// Common Media Types defined in http://www.iana.org/assignments/media-types/media-types.xhtml
//
#define HTTP_CONTENT_TYPE_APP_JSON "application/json"
#define HTTP_CONTENT_TYPE_APP_OCTET_STREAM "application/octet-stream"
#define HTTP_CONTENT_TYPE_TEXT_HTML "text/html"
#define HTTP_CONTENT_TYPE_TEXT_PLAIN "text/plain"
#define HTTP_CONTENT_TYPE_TEXT_CSS "text/css"
#define HTTP_CONTENT_TYPE_TEXT_XML "text/xml"
#define HTTP_CONTENT_TYPE_IMAGE_GIF "image/gif"
#define HTTP_CONTENT_TYPE_IMAGE_JPEG "image/jpeg"
#define HTTP_CONTENT_TYPE_IMAGE_PNG "image/png"
#define HTTP_CONTENT_TYPE_IMAGE_SVG_XML "image/svg+xml"
///
/// Content-Length Header
/// The Content-Length entity-header field indicates the size of the entity-body,
/// in decimal number of OCTETs, sent to the recipient or, in the case of the HEAD
/// method, the size of the entity-body that would have been sent had the request been a GET.
///
#define HTTP_HEADER_CONTENT_LENGTH "Content-Length"
///
/// Transfer-Encoding Header
/// The Transfer-Encoding general-header field indicates what (if any) type of transformation
/// has been applied to the message body in order to safely transfer it between the sender
/// and the recipient. This differs from the content-coding in that the transfer-coding
/// is a property of the message, not of the entity.
///
#define HTTP_HEADER_TRANSFER_ENCODING "Transfer-Encoding"
#define HTTP_HEADER_TRANSFER_ENCODING_CHUNKED "chunked"
#define CHUNKED_TRANSFER_CODING_CR '\r'
#define CHUNKED_TRANSFER_CODING_LF '\n'
#define CHUNKED_TRANSFER_CODING_LAST_CHUNK '0'
#define CHUNKED_TRANSFER_CODING_EXTENSION_SEPARATOR ';'
///
/// User Agent Request Header
///
/// The User-Agent request-header field contains information about the user agent originating
/// the request. This is for statistical purposes, the tracing of protocol violations, and
/// automated recognition of user agents for the sake of tailoring responses to avoid
/// particular user agent limitations. User agents SHOULD include this field with requests.
/// The field can contain multiple product tokens and comments identifying the agent and any
/// subproducts which form a significant part of the user agent.
/// By convention, the product tokens are listed in order of their significance for
/// identifying the application.
///
#define HTTP_HEADER_USER_AGENT "User-Agent"
///
/// Host Request Header
///
/// The Host request-header field specifies the Internet host and port number of the resource
/// being requested, as obtained from the original URI given by the user or referring resource
///
#define HTTP_HEADER_HOST "Host"
///
/// Location Response Header
///
/// The Location response-header field is used to redirect the recipient to a location other than
/// the Request-URI for completion of the request or identification of a new resource.
/// For 201 (Created) responses, the Location is that of the new resource which was created by
/// the request. For 3xx responses, the location SHOULD indicate the server's preferred URI for
/// automatic redirection to the resource. The field value consists of a single absolute URI.
///
#define HTTP_HEADER_LOCATION "Location"
///
/// The If-Match request-header field is used with a method to make it conditional.
/// A client that has one or more entities previously obtained from the resource
/// can verify that one of those entities is current by including a list of their
/// associated entity tags in the If-Match header field.
/// The purpose of this feature is to allow efficient updates of cached information
/// with a minimum amount of transaction overhead. It is also used, on updating requests,
/// to prevent inadvertent modification of the wrong version of a resource.
/// As a special case, the value "*" matches any current entity of the resource.
///
#define HTTP_HEADER_IF_MATCH "If-Match"
///
/// The If-None-Match request-header field is used with a method to make it conditional.
/// A client that has one or more entities previously obtained from the resource can verify
/// that none of those entities is current by including a list of their associated entity
/// tags in the If-None-Match header field. The purpose of this feature is to allow efficient
/// updates of cached information with a minimum amount of transaction overhead. It is also used
/// to prevent a method (e.g. PUT) from inadvertently modifying an existing resource when the
/// client believes that the resource does not exist.
///
#define HTTP_HEADER_IF_NONE_MATCH "If-None-Match"
///
/// Authorization Request Header
/// The Authorization field value consists of credentials
/// containing the authentication information of the user agent for
/// the realm of the resource being requested.
///
#define HTTP_HEADER_AUTHORIZATION "Authorization"
///
/// ETAG Response Header
/// The ETag response-header field provides the current value of the entity tag
/// for the requested variant.
///
#define HTTP_HEADER_ETAG "ETag"
///
/// Custom header field checked by the iLO web server to
/// specify a client session key.
/// Example: X-Auth-Token: 24de6b1f8fa147ad59f6452def628798
///
#define HTTP_HEADER_X_AUTH_TOKEN "X-Auth-Token"
///
/// Expect Header
/// The "Expect" header field in a request indicates a certain set of
/// behaviors (expectations) that need to be supported by the server in
/// order to properly handle this request. The only such expectation
/// defined by this specification is 100-continue.
///
#define HTTP_HEADER_EXPECT "Expect"
///
/// Expect Header Value
///
#define HTTP_EXPECT_100_CONTINUE "100-continue"
#pragma pack()
#endif

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/** @file
The definition for iSCSI Boot Firmware Table, it's defined in Microsoft's
iSCSI Boot Firmware Table(iBFT) as Defined in ACPI 3.0b Specification.
Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef _ISCSI_BOOT_FIRMWARE_TABLE_H_
#define _ISCSI_BOOT_FIRMWARE_TABLE_H_
#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_REVISION 0x01
#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_STRUCTURE_ALIGNMENT 8
///
/// Structure Type/ID
///
#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_RESERVED_STRUCTURE_ID 0
#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_CONTROL_STRUCTURE_ID 1
#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_INITIATOR_STRUCTURE_ID 2
#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_NIC_STRUCTURE_ID 3
#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_TARGET_STRUCTURE_ID 4
#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_EXTERNSIONS_STRUCTURE_ID 5
///
/// from the definition of IP_PREFIX_ORIGIN Enumeration in MSDN,
/// not defined in Microsoft iBFT document.
///
typedef enum {
IpPrefixOriginOther = 0,
IpPrefixOriginManual,
IpPrefixOriginWellKnown,
IpPrefixOriginDhcp,
IpPrefixOriginRouterAdvertisement,
IpPrefixOriginUnchanged = 16
} IP_PREFIX_VALUE;
#pragma pack(1)
///
/// iBF Table Header
///
typedef struct {
UINT32 Signature;
UINT32 Length;
UINT8 Revision;
UINT8 Checksum;
UINT8 OemId[6];
UINT64 OemTableId;
UINT8 Reserved[24];
} EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_HEADER;
///
/// Common Header of Boot Firmware Table Structure
///
typedef struct {
UINT8 StructureId;
UINT8 Version;
UINT16 Length;
UINT8 Index;
UINT8 Flags;
} EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_STRUCTURE_HEADER;
///
/// Control Structure
///
typedef struct {
EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_STRUCTURE_HEADER Header;
UINT16 Extensions;
UINT16 InitiatorOffset;
UINT16 NIC0Offset;
UINT16 Target0Offset;
UINT16 NIC1Offset;
UINT16 Target1Offset;
} EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_CONTROL_STRUCTURE;
#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_CONTROL_STRUCTURE_VERSION 0x1
#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_CONTROL_STRUCTURE_FLAG_BOOT_FAILOVER BIT0
///
/// Initiator Structure
///
typedef struct {
EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_STRUCTURE_HEADER Header;
EFI_IPv6_ADDRESS ISnsServer;
EFI_IPv6_ADDRESS SlpServer;
EFI_IPv6_ADDRESS PrimaryRadiusServer;
EFI_IPv6_ADDRESS SecondaryRadiusServer;
UINT16 IScsiNameLength;
UINT16 IScsiNameOffset;
} EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_INITIATOR_STRUCTURE;
#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_INITIATOR_STRUCTURE_VERSION 0x1
#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_INITIATOR_STRUCTURE_FLAG_BLOCK_VALID BIT0
#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_INITIATOR_STRUCTURE_FLAG_BOOT_SELECTED BIT1
///
/// NIC Structure
///
typedef struct {
EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_STRUCTURE_HEADER Header;
EFI_IPv6_ADDRESS Ip;
UINT8 SubnetMaskPrefixLength;
UINT8 Origin;
EFI_IPv6_ADDRESS Gateway;
EFI_IPv6_ADDRESS PrimaryDns;
EFI_IPv6_ADDRESS SecondaryDns;
EFI_IPv6_ADDRESS DhcpServer;
UINT16 VLanTag;
UINT8 Mac[6];
UINT16 PciLocation;
UINT16 HostNameLength;
UINT16 HostNameOffset;
} EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_NIC_STRUCTURE;
#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_NIC_STRUCTURE_VERSION 0x1
#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_NIC_STRUCTURE_FLAG_BLOCK_VALID BIT0
#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_NIC_STRUCTURE_FLAG_BOOT_SELECTED BIT1
#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_NIC_STRUCTURE_FLAG_GLOBAL BIT2
///
/// Target Structure
///
typedef struct {
EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_STRUCTURE_HEADER Header;
EFI_IPv6_ADDRESS Ip;
UINT16 Port;
UINT8 BootLun[8];
UINT8 CHAPType;
UINT8 NicIndex;
UINT16 IScsiNameLength;
UINT16 IScsiNameOffset;
UINT16 CHAPNameLength;
UINT16 CHAPNameOffset;
UINT16 CHAPSecretLength;
UINT16 CHAPSecretOffset;
UINT16 ReverseCHAPNameLength;
UINT16 ReverseCHAPNameOffset;
UINT16 ReverseCHAPSecretLength;
UINT16 ReverseCHAPSecretOffset;
} EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_TARGET_STRUCTURE;
#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_TARGET_STRUCTURE_VERSION 0x1
#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_TARGET_STRUCTURE_FLAG_BLOCK_VALID BIT0
#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_TARGET_STRUCTURE_FLAG_BOOT_SELECTED BIT1
#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_TARGET_STRUCTURE_FLAG_RADIUS_CHAP BIT2
#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_TARGET_STRUCTURE_FLAG_RADIUS_RCHAP BIT3
#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_TARGET_STRUCTURE_CHAP_TYPE_NO_CHAP 0
#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_TARGET_STRUCTURE_CHAP_TYPE_CHAP 1
#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_TARGET_STRUCTURE_CHAP_TYPE_MUTUAL_CHAP 2
#pragma pack()
#endif

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/** @file
ACPI IO Remapping Table (IORT) as specified in ARM spec DEN0049D
http://infocenter.arm.com/help/topic/com.arm.doc.den0049d/DEN0049D_IO_Remapping_Table.pdf
Copyright (c) 2017, Linaro Limited. All rights reserved.<BR>
Copyright (c) 2018, ARM Limited. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef __IO_REMAPPING_TABLE_H__
#define __IO_REMAPPING_TABLE_H__
#include <IndustryStandard/Acpi.h>
#define EFI_ACPI_IO_REMAPPING_TABLE_REVISION 0x0
#define EFI_ACPI_IORT_TYPE_ITS_GROUP 0x0
#define EFI_ACPI_IORT_TYPE_NAMED_COMP 0x1
#define EFI_ACPI_IORT_TYPE_ROOT_COMPLEX 0x2
#define EFI_ACPI_IORT_TYPE_SMMUv1v2 0x3
#define EFI_ACPI_IORT_TYPE_SMMUv3 0x4
#define EFI_ACPI_IORT_TYPE_PMCG 0x5
#define EFI_ACPI_IORT_MEM_ACCESS_PROP_CCA BIT0
#define EFI_ACPI_IORT_MEM_ACCESS_PROP_AH_TR BIT0
#define EFI_ACPI_IORT_MEM_ACCESS_PROP_AH_WA BIT1
#define EFI_ACPI_IORT_MEM_ACCESS_PROP_AH_RA BIT2
#define EFI_ACPI_IORT_MEM_ACCESS_PROP_AH_AHO BIT3
#define EFI_ACPI_IORT_MEM_ACCESS_FLAGS_CPM BIT0
#define EFI_ACPI_IORT_MEM_ACCESS_FLAGS_DACS BIT1
#define EFI_ACPI_IORT_SMMUv1v2_MODEL_v1 0x0
#define EFI_ACPI_IORT_SMMUv1v2_MODEL_v2 0x1
#define EFI_ACPI_IORT_SMMUv1v2_MODEL_MMU400 0x2
#define EFI_ACPI_IORT_SMMUv1v2_MODEL_MMU500 0x3
#define EFI_ACPI_IORT_SMMUv1v2_MODEL_MMU401 0x4
#define EFI_ACPI_IORT_SMMUv1v2_MODEL_CAVIUM_THX_v2 0x5
#define EFI_ACPI_IORT_SMMUv1v2_FLAG_DVM BIT0
#define EFI_ACPI_IORT_SMMUv1v2_FLAG_COH_WALK BIT1
#define EFI_ACPI_IORT_SMMUv1v2_INT_FLAG_LEVEL 0x0
#define EFI_ACPI_IORT_SMMUv1v2_INT_FLAG_EDGE 0x1
#define EFI_ACPI_IORT_SMMUv3_FLAG_COHAC_OVERRIDE BIT0
#define EFI_ACPI_IORT_SMMUv3_FLAG_HTTU_OVERRIDE BIT1
#define EFI_ACPI_IORT_SMMUv3_FLAG_PROXIMITY_DOMAIN BIT3
#define EFI_ACPI_IORT_SMMUv3_MODEL_GENERIC 0x0
#define EFI_ACPI_IORT_SMMUv3_MODEL_HISILICON_HI161X 0x1
#define EFI_ACPI_IORT_SMMUv3_MODEL_CAVIUM_CN99XX 0x2
#define EFI_ACPI_IORT_ROOT_COMPLEX_ATS_UNSUPPORTED 0x0
#define EFI_ACPI_IORT_ROOT_COMPLEX_ATS_SUPPORTED 0x1
#define EFI_ACPI_IORT_ID_MAPPING_FLAGS_SINGLE BIT0
#pragma pack(1)
///
/// Table header
///
typedef struct {
EFI_ACPI_DESCRIPTION_HEADER Header;
UINT32 NumNodes;
UINT32 NodeOffset;
UINT32 Reserved;
} EFI_ACPI_6_0_IO_REMAPPING_TABLE;
///
/// Definition for ID mapping table shared by all node types
///
typedef struct {
UINT32 InputBase;
UINT32 NumIds;
UINT32 OutputBase;
UINT32 OutputReference;
UINT32 Flags;
} EFI_ACPI_6_0_IO_REMAPPING_ID_TABLE;
///
/// Node header definition shared by all node types
///
typedef struct {
UINT8 Type;
UINT16 Length;
UINT8 Revision;
UINT32 Reserved;
UINT32 NumIdMappings;
UINT32 IdReference;
} EFI_ACPI_6_0_IO_REMAPPING_NODE;
///
/// Node type 0: ITS node
///
typedef struct {
EFI_ACPI_6_0_IO_REMAPPING_NODE Node;
UINT32 NumItsIdentifiers;
//UINT32 ItsIdentifiers[NumItsIdentifiers];
} EFI_ACPI_6_0_IO_REMAPPING_ITS_NODE;
///
/// Node type 1: root complex node
///
typedef struct {
EFI_ACPI_6_0_IO_REMAPPING_NODE Node;
UINT32 CacheCoherent;
UINT8 AllocationHints;
UINT16 Reserved;
UINT8 MemoryAccessFlags;
UINT32 AtsAttribute;
UINT32 PciSegmentNumber;
UINT8 MemoryAddressSize;
UINT8 Reserved1[3];
} EFI_ACPI_6_0_IO_REMAPPING_RC_NODE;
///
/// Node type 2: named component node
///
typedef struct {
EFI_ACPI_6_0_IO_REMAPPING_NODE Node;
UINT32 Flags;
UINT32 CacheCoherent;
UINT8 AllocationHints;
UINT16 Reserved;
UINT8 MemoryAccessFlags;
UINT8 AddressSizeLimit;
//UINT8 ObjectName[];
} EFI_ACPI_6_0_IO_REMAPPING_NAMED_COMP_NODE;
///
/// Node type 3: SMMUv1 or SMMUv2 node
///
typedef struct {
UINT32 Interrupt;
UINT32 InterruptFlags;
} EFI_ACPI_6_0_IO_REMAPPING_SMMU_INT;
typedef struct {
EFI_ACPI_6_0_IO_REMAPPING_NODE Node;
UINT64 Base;
UINT64 Span;
UINT32 Model;
UINT32 Flags;
UINT32 GlobalInterruptArrayRef;
UINT32 NumContextInterrupts;
UINT32 ContextInterruptArrayRef;
UINT32 NumPmuInterrupts;
UINT32 PmuInterruptArrayRef;
UINT32 SMMU_NSgIrpt;
UINT32 SMMU_NSgIrptFlags;
UINT32 SMMU_NSgCfgIrpt;
UINT32 SMMU_NSgCfgIrptFlags;
//EFI_ACPI_6_0_IO_REMAPPING_SMMU_CTX_INT ContextInterrupt[NumContextInterrupts];
//EFI_ACPI_6_0_IO_REMAPPING_SMMU_CTX_INT PmuInterrupt[NumPmuInterrupts];
} EFI_ACPI_6_0_IO_REMAPPING_SMMU_NODE;
///
/// Node type 4: SMMUv3 node
///
typedef struct {
EFI_ACPI_6_0_IO_REMAPPING_NODE Node;
UINT64 Base;
UINT32 Flags;
UINT32 Reserved;
UINT64 VatosAddress;
UINT32 Model;
UINT32 Event;
UINT32 Pri;
UINT32 Gerr;
UINT32 Sync;
UINT32 ProximityDomain;
UINT32 DeviceIdMappingIndex;
} EFI_ACPI_6_0_IO_REMAPPING_SMMU3_NODE;
///
/// Node type 5: PMCG node
///
typedef struct {
EFI_ACPI_6_0_IO_REMAPPING_NODE Node;
UINT64 Base;
UINT32 OverflowInterruptGsiv;
UINT32 NodeReference;
UINT64 Page1Base;
//EFI_ACPI_6_0_IO_REMAPPING_ID_TABLE OverflowInterruptMsiMapping[1];
} EFI_ACPI_6_0_IO_REMAPPING_PMCG_NODE;
#pragma pack()
#endif

55
src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/Ipmi.h Normal file
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/** @file
IPMI 2.0 definitions from the IPMI Specification Version 2.0, Revision 1.1.
IPMI Platform Management FRU Information Storage Definition v1.0 Revision 1.3.
See IPMI specification, Appendix G, Command Assignments
and Appendix H, Sub-function Assignments.
Copyright (c) 1999 - 2018, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef _IPMI_H_
#define _IPMI_H_
#include <IndustryStandard/IpmiNetFnChassis.h>
#include <IndustryStandard/IpmiNetFnBridge.h>
#include <IndustryStandard/IpmiNetFnSensorEvent.h>
#include <IndustryStandard/IpmiNetFnApp.h>
#include <IndustryStandard/IpmiNetFnFirmware.h>
#include <IndustryStandard/IpmiNetFnStorage.h>
#include <IndustryStandard/IpmiNetFnTransport.h>
#include <IndustryStandard/IpmiNetFnGroupExtension.h>
#include <IndustryStandard/IpmiFruInformationStorage.h>
//
// Generic Completion Codes definitions
//
#define IPMI_COMP_CODE_NORMAL 0x00
#define IPMI_COMP_CODE_NODE_BUSY 0xC0
#define IPMI_COMP_CODE_INVALID_COMMAND 0xC1
#define IPMI_COMP_CODE_INVALID_FOR_GIVEN_LUN 0xC2
#define IPMI_COMP_CODE_TIMEOUT 0xC3
#define IPMI_COMP_CODE_OUT_OF_SPACE 0xC4
#define IPMI_COMP_CODE_RESERVATION_CANCELED_OR_INVALID 0xC5
#define IPMI_COMP_CODE_REQUEST_DATA_TRUNCATED 0xC6
#define IPMI_COMP_CODE_INVALID_REQUEST_DATA_LENGTH 0xC7
#define IPMI_COMP_CODE_REQUEST_EXCEED_LIMIT 0xC8
#define IPMI_COMP_CODE_OUT_OF_RANGE 0xC9
#define IPMI_COMP_CODE_CANNOT_RETURN 0xCA
#define IPMI_COMP_CODE_NOT_PRESENT 0xCB
#define IPMI_COMP_CODE_INVALID_DATA_FIELD 0xCC
#define IPMI_COMP_CODE_COMMAND_ILLEGAL 0xCD
#define IPMI_COMP_CODE_CMD_RESP_NOT_PROVIDED 0xCE
#define IPMI_COMP_CODE_FAIL_DUP_REQUEST 0xCF
#define IPMI_COMP_CODE_SDR_REP_IN_UPDATE_MODE 0xD0
#define IPMI_COMP_CODE_DEV_IN_FW_UPDATE_MODE 0xD1
#define IPMI_COMP_CODE_BMC_INIT_IN_PROGRESS 0xD2
#define IPMI_COMP_CODE_DEST_UNAVAILABLE 0xD3
#define IPMI_COMP_CODE_INSUFFICIENT_PRIVILEGE 0xD4
#define IPMI_COMP_CODE_UNSUPPORTED_IN_PRESENT_STATE 0xD5
#define IPMI_COMP_CODE_SUBFUNCTION_DISABLED 0xD6
#define IPMI_COMP_CODE_UNSPECIFIED 0xFF
#endif

86
src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/IpmiFruInformationStorage.h Normal file
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/** @file
IPMI Platform Management FRU Information Storage Definitions
This file contains the definitions for:
Common Header Format (Chapter 8)
MultiRecord Header (Section 16.1)
Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@par Revision Reference:
- IPMI Platform Management FRU Information Storage Definition v1.0 Revision
1.3, Dated March 24, 2015.
https://www.intel.com/content/dam/www/public/us/en/documents/specification-updates/ipmi-platform-mgt-fru-info-storage-def-v1-0-rev-1-3-spec-update.pdf
**/
#ifndef _IPMI_FRU_INFORMATION_STORAGE_H_
#define _IPMI_FRU_INFORMATION_STORAGE_H_
#pragma pack(1)
//
// Structure definitions for FRU Common Header
//
typedef union {
///
/// Individual bit fields
///
struct {
UINT8 FormatVersionNumber:4;
UINT8 Reserved:4;
} Bits;
///
/// All bit fields as a 8-bit value
///
UINT8 Uint8;
} IPMI_FRU_COMMON_HEADER_FORMAT_VERSION;
typedef struct {
IPMI_FRU_COMMON_HEADER_FORMAT_VERSION FormatVersion;
UINT8 InternalUseStartingOffset;
UINT8 ChassisInfoStartingOffset;
UINT8 BoardAreaStartingOffset;
UINT8 ProductInfoStartingOffset;
UINT8 MultiRecInfoStartingOffset;
UINT8 Pad;
UINT8 Checksum;
} IPMI_FRU_COMMON_HEADER;
//
// Structure definition for FRU MultiRecord Header
//
typedef union {
///
/// Individual bit fields
///
struct {
UINT8 RecordFormatVersion:4;
UINT8 Reserved:3;
UINT8 EndofList:1;
} Bits;
///
/// All bit fields as a 8-bit value
///
UINT8 Uint8;
} IPMI_FRU_MULTI_RECORD_HEADER_FORMAT_VERSION;
typedef struct {
UINT8 RecordTypeId;
IPMI_FRU_MULTI_RECORD_HEADER_FORMAT_VERSION FormatVersion;
UINT8 RecordLength;
UINT8 RecordChecksum;
UINT8 HeaderChecksum;
} IPMI_FRU_MULTI_RECORD_HEADER;
//
// Structure definition for System UUID Subrecord with checksum.
//
typedef struct {
UINT8 RecordCheckSum;
UINT8 SubRecordId;
EFI_GUID Uuid;
} IPMI_SYSTEM_UUID_SUB_RECORD_WITH_CHECKSUM;
#pragma pack()
#endif

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