Add gaze14 1660ti variant files

src/mainboard/system76/cfl-h/Makefile.inc

@@ -1,2 +1,3 @@
 bootblock-y += bootblock.c
 ramstage-y += ramstage.c variants/$(VARIANT_DIR)/hda_verb.c
+CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include

src/mainboard/system76/cfl-h/bootblock.c

@@ -16,7 +16,7 @@
 #include <bootblock_common.h>
 #include <gpio.h>
 #include <soc/gpio.h>
-#include "gpio.h"
+#include <variant/gpio.h>
 
 void bootblock_mainboard_init(void) {
 	gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));

src/mainboard/system76/cfl-h/devicetree.cb

@@ -145,17 +145,14 @@ chip soc/intel/cannonlake
 	# Thermal
 	register "tcc_offset" = "2"
 
-	# Unlock GPIO pads
-	register "PchUnlockGpioPads" = "1"
-
 	# Serial IRQ Continuous
 	register "SerialIrqConfigSirqMode" = "1"
 
 # LPC (soc/intel/cannonlake/lpc.c)
 	# LPC configuration from lspci -s 1f.0 -xxx
-	# Address 0x84: TODO
+	# Address 0x84: Decode 0x1640 - 0x164F
 	register "gen1_dec" = "0x000c1641"
-	# Address 0x88: TODO
+	# Address 0x88: Decode 0x680 - 0x68F
 	register "gen2_dec" = "0x000c0681"
 	# Address 0x8C: Decode 0x80 - 0x8F
 	register "gen3_dec" = "0x000c0081"

src/mainboard/system76/cfl-h/ramstage.c

@@ -17,7 +17,7 @@
 #include <device/device.h>
 #include <pc80/keyboard.h>
 #include <soc/ramstage.h>
-#include "gpio.h"
+#include <variant/gpio.h>
 
 void mainboard_silicon_init_params(FSP_S_CONFIG *params) {
 	/* Configure pads prior to SiliconInit() in case there's any

src/mainboard/system76/cfl-h/variants/gaze14_1650_15/include/variant/gpio.h

@@ -21,16 +21,29 @@
 
 #ifndef __ACPI__
 
+/* Early pad configuration in romstage. */
+static const struct pad_config early_gpio_table[] = {
+	// UART2
+		// UART2_RXD
+		PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),
+		// UART2_TXD
+		PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),
+		// NC
+		PAD_NC(GPP_C22, NONE),
+		// NC
+		PAD_NC(GPP_C23, NONE),
+};
+
 /* Pad configuration in ramstage. */
 static const struct pad_config gpio_table[] = {
 // GPD
 	// Power Management
 		// NC
-		PAD_NC(GPD0, NONE),
+		PAD_CFG_NF(GPD0, NONE, DEEP, NF1),
 		// AC_PRESENT
 		PAD_CFG_NF(GPD1, NATIVE, DEEP, NF1),
 		// NC
-		PAD_NC(GPD2, NONE),
+		PAD_CFG_GPI(GPD2, NATIVE, PWROK),
 		// PWR_BTN#
 		PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1),
 		// SUSB#_PCH
@@ -38,58 +51,58 @@ static const struct pad_config gpio_table[] = {
 		// SUSC#_PCH
 		PAD_CFG_NF(GPD5, NONE, DEEP, NF1),
 		// NC
-		PAD_NC(GPD6, NONE),
+		_PAD_CFG_STRUCT(GPD6, 0x44000601, 0x0000),
 
 	// GPIO
 		// NC
-		PAD_NC(GPD7, NONE),
+		_PAD_CFG_STRUCT(GPD7, 0x04000300, 0x0000),
 
 	// Power Management
 		// SUS_CLK_R
 		PAD_CFG_NF(GPD8, NONE, DEEP, NF1),
 		// NC
-		PAD_NC(GPD9, NONE),
+		PAD_CFG_GPI(GPD9, NONE, PWROK),
 		// NC
-		PAD_NC(GPD10, NONE),
+		PAD_CFG_NF(GPD10, NONE, PWROK, NF1),
 		// NC
-		PAD_NC(GPD11, NONE),
+		PAD_CFG_TERM_GPO(GPD11, 0, NONE, PWROK),
 
 // GPP_A
 	// LPC
 		// SB_KBCRST#
 		PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1),
 		// LPC_AD0
-		PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1),
+		PAD_CFG_NF(GPP_A1, NATIVE, DEEP, NF1),
 		// LPC_AD1
-		PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1),
+		PAD_CFG_NF(GPP_A2, NATIVE, DEEP, NF1),
 		// LPC_AD2
-		PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1),
+		PAD_CFG_NF(GPP_A3, NATIVE, DEEP, NF1),
 		// LPC_AD3
-		PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1),
+		PAD_CFG_NF(GPP_A4, NATIVE, DEEP, NF1),
 		// LPC_FRAME#
 		PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1),
 		// SERIRQ
 		PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1),
 		// NC
-		PAD_NC(GPP_A7, NONE),
+		PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1),
 		// PM_CLKRUN#
 		PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1),
 		// PCLK_KBC
 		PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1),
 		// NC
-		PAD_NC(GPP_A10, NONE),
+		PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1),
 
 	// Power Management
 		// TODO: LAN_WAKEUP#
 		PAD_CFG_GPI(GPP_A11, NONE, DEEP),
 		// NC
-		PAD_NC(GPP_A12, NONE),
+		PAD_CFG_GPI(GPP_A12, NONE, DEEP),
 		// SUSWARN#
 		PAD_CFG_NF(GPP_A13, DN_20K, DEEP, NF1),
 
 	// LPC
 		// NC
-		PAD_NC(GPP_A14, NONE),
+		PAD_CFG_TERM_GPO(GPP_A14, 0, DN_20K, DEEP),
 
 	// Power Management
 		// SUS_PWR_ACK
@@ -111,48 +124,48 @@ static const struct pad_config gpio_table[] = {
 		// NC
 		PAD_NC(GPP_A21, NONE),
 		// SATA_PWR_EN
-		PAD_CFG_TERM_GPO(GPP_A22, 1, NONE, DEEP),
+		PAD_CFG_TERM_GPO(GPP_A22, 0, NONE, DEEP),
 		// NC
 		PAD_NC(GPP_A23, NONE),
 
 // GPP_B
 	// GSPI
 		// TODO: TPM_PIRQ#
-		PAD_NC(GPP_B0, NONE),
+		_PAD_CFG_STRUCT(GPP_B0, 0x40000700, 0x0000),
 		// NC
-		PAD_NC(GPP_B1, NONE),
+		PAD_CFG_GPI(GPP_B1, NONE, DEEP),
 
 	// Power Management
 		// NC
-		PAD_NC(GPP_B2, NONE),
+		PAD_CFG_TERM_GPO(GPP_B2, 0, NONE, DEEP),
 
 	// CPU Misc
 		// NC
-		PAD_NC(GPP_B3, NONE),
+		PAD_CFG_GPI(GPP_B3, NONE, DEEP),
 		// TODO: EXTTS_SNI_DRV1
-		PAD_NC(GPP_B4, NONE),
+		PAD_CFG_GPI(GPP_B4, NONE, DEEP),
 
 	// Clock Signals
 		// NC
-		PAD_NC(GPP_B5, NONE),
+		PAD_CFG_TERM_GPO(GPP_B5, 1, NONE, DEEP),
 		// NC
-		PAD_NC(GPP_B6, NONE),
+		PAD_CFG_GPI(GPP_B6, NONE, PLTRST),
 		// NC
-		PAD_NC(GPP_B7, NONE),
+		PAD_CFG_GPI(GPP_B7, NONE, PLTRST),
 		// NC
-		PAD_NC(GPP_B8, NONE),
+		PAD_CFG_GPI(GPP_B8, NONE, PLTRST),
 		// NC
-		PAD_NC(GPP_B9, NONE),
+		PAD_CFG_GPI(GPP_B9, NONE, PLTRST),
 		// LAN_CLKREQ#
-		PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1),
+		PAD_CFG_GPI(GPP_B10, NONE, PLTRST),
 
 	// Audio
 		// TODO: GPP_B11: DDR Voltage select - 0 = 1.2V, 1 = 1.35V
-		PAD_CFG_GPO(GPP_B11, 0, DEEP),
+		PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1),
 
 	// Power Management
 		// SLP_S0#
-		PAD_CFG_NF(GPP_B12, UP_20K, DEEP, NF1),
+		PAD_CFG_GPI(GPP_B12, UP_20K, DEEP),
 		// PLT_RST#
 		PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
 
@@ -162,15 +175,15 @@ static const struct pad_config gpio_table[] = {
 
 	// GSPI
 		// NC
-		PAD_NC(GPP_B15, NONE),
+		PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1),
 		// NC
 		PAD_NC(GPP_B16, NONE),
 		// NC
-		PAD_NC(GPP_B17, NONE),
+		PAD_CFG_GPI(GPP_B17, NONE, DEEP),
 		// LPSS_GSPI0_MOSI - strap for no reboot mode
-		PAD_NC(GPP_B18, NONE),
+		PAD_CFG_GPI(GPP_B18, NONE, DEEP),
 		// NC
-		PAD_NC(GPP_B19, NONE),
+		PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1),
 		// NC
 		PAD_NC(GPP_B20, NONE),
 		// NC
@@ -180,7 +193,7 @@ static const struct pad_config gpio_table[] = {
 
 	// SMBUS
 		// PCH_HOT_GNSS_DISABLE - strap for DCI BSSB mode
-		PAD_NC(GPP_B23, NONE),
+		PAD_CFG_NF(GPP_B23, NONE, DEEP, NF1),
 
 // GPP_C
 	// SMBUS
@@ -189,23 +202,23 @@ static const struct pad_config gpio_table[] = {
 		// SMB_DATA
 		PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
 		// NC
-		PAD_NC(GPP_C2, NONE),
+		PAD_CFG_GPI(GPP_C2, NONE, DEEP),
 		// NC
 		PAD_NC(GPP_C3, NONE),
 		// NC
 		PAD_NC(GPP_C4, NONE),
 		// NC
-		PAD_NC(GPP_C5, NONE),
+		PAD_CFG_GPI(GPP_C5, NONE, DEEP),
 		// NC
-		PAD_NC(GPP_C6, NONE),
+		PAD_CFG_GPI(GPP_C6, NONE, DEEP),
 		// NC
-		PAD_NC(GPP_C7, NONE),
+		PAD_CFG_GPI(GPP_C7, NONE, DEEP),
 
 	// UART
 		// NC
 		PAD_NC(GPP_C8, NONE),
 		// TODO: CNVI_DET#
-		PAD_NC(GPP_C9, NONE),
+		PAD_CFG_TERM_GPO(GPP_C9, 1, NONE, DEEP),
 		// NC
 		PAD_NC(GPP_C10, NONE),
 		// NC
@@ -225,9 +238,9 @@ static const struct pad_config gpio_table[] = {
 		// I2C_SDA_TP
 		PAD_CFG_NF(GPP_C17, NONE, PLTRST, NF1),
 		// NC
-		PAD_NC(GPP_C18, NONE),
+		PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1),
 		// NC
-		PAD_NC(GPP_C19, NONE),
+		PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1),
 
 	// UART
 		// UART2_RXD
@@ -235,9 +248,9 @@ static const struct pad_config gpio_table[] = {
 		// UART2_TXD
 		PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),
 		// NC
-		PAD_NC(GPP_C22, NONE),
+		PAD_CFG_NF(GPP_C22, NONE, DEEP, NF1),
 		// NC
-		PAD_NC(GPP_C23, NONE),
+		PAD_CFG_NF(GPP_C23, NONE, DEEP, NF1),
 
 // GPP_D
 	// SPI
@@ -284,13 +297,13 @@ static const struct pad_config gpio_table[] = {
 
 	// DMIC
 		// NC
-		PAD_NC(GPP_D17, NONE),
+		PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1),
 		// NC
-		PAD_NC(GPP_D18, NONE),
+		PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1),
 		// NC
-		PAD_NC(GPP_D19, NONE),
+		PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1),
 		// NC
-		PAD_NC(GPP_D20, NONE),
+		PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1),
 
 	// SPI
 		// NC
@@ -305,27 +318,27 @@ static const struct pad_config gpio_table[] = {
 // GPP_E
 	// SATA
 		// NC
-		PAD_NC(GPP_E0, NONE),
+		PAD_CFG_GPI(GPP_E0, NONE, DEEP),
 		// SATAGP1
 		PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1),
 		// NC
-		PAD_NC(GPP_E2, NONE),
+		PAD_CFG_GPI(GPP_E2, NONE, DEEP),
 
 	// CPU Misc
 		// TODO: EXTTS_SNI_DRV0
-		PAD_NC(GPP_E3, NONE),
+		_PAD_CFG_STRUCT(GPP_E3, 0x44000101, 0x0000),
 
 	// SATA
 		// DEVSLP0
-		PAD_CFG_NF(GPP_E4, UP_20K, DEEP, NF1),
+		PAD_CFG_GPI(GPP_E4, UP_20K, DEEP),
 		// DEVSLP1
-		PAD_CFG_NF(GPP_E5, UP_20K, DEEP, NF1),
+		PAD_CFG_GPI(GPP_E5, UP_20K, DEEP),
 		// NC
 		PAD_NC(GPP_E6, NONE),
 
 	// CPU Misc
 		// TODO: TP_ATTN#
-		PAD_NC(GPP_E7, NONE),
+		_PAD_CFG_STRUCT(GPP_E7, 0x40800100, 0x3000),
 
 	// SATA
 		// SATA_LED#
@@ -422,129 +435,129 @@ static const struct pad_config gpio_table[] = {
 		// WLAN_CLKREQ#
 		PAD_CFG_NF(GPP_H0, NONE, DEEP, NF1),
 		// NC
-		PAD_NC(GPP_H1, NONE),
+		_PAD_CFG_STRUCT(GPP_H1, 0x84000300, 0x0000),
 		// PEG_CLKREQ#
 		PAD_CFG_NF(GPP_H2, NONE, DEEP, NF1),
 		// NC
-		PAD_NC(GPP_H3, NONE),
+		_PAD_CFG_STRUCT(GPP_H3, 0x84000300, 0x0000),
 		// SSD_CLKREQ#
 		PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
 		// SSD2_CLKREQ#
 		PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),
 		// NC
-		PAD_NC(GPP_H6, NONE),
+		_PAD_CFG_STRUCT(GPP_H6, 0x84000300, 0x0000),
 		// NC
-		PAD_NC(GPP_H7, NONE),
+		_PAD_CFG_STRUCT(GPP_H7, 0x84000300, 0x0000),
 		// NC
-		PAD_NC(GPP_H8, NONE),
+		_PAD_CFG_STRUCT(GPP_H8, 0x84000300, 0x0000),
 		// NC
-		PAD_NC(GPP_H9, NONE),
+		_PAD_CFG_STRUCT(GPP_H9, 0x84000300, 0x0000),
 
 	// SMBUS
 		// NC
-		PAD_NC(GPP_H10, NONE),
+		PAD_CFG_GPI(GPP_H10, NONE, DEEP),
 		// NC
-		PAD_NC(GPP_H11, NONE),
+		PAD_CFG_GPI(GPP_H11, NONE, DEEP),
 		// GPP_H_12 - strap for ESPI flash sharing mode
-		PAD_NC(GPP_H12, NONE),
+		PAD_CFG_GPI(GPP_H12, NONE, DEEP),
 		// NC
-		PAD_NC(GPP_H13, NONE),
+		PAD_CFG_GPI(GPP_H13, NONE, DEEP),
 		// NC
-		PAD_NC(GPP_H14, NONE),
+		PAD_CFG_GPI(GPP_H14, NONE, DEEP),
 		// NC
-		PAD_NC(GPP_H15, NONE),
+		PAD_CFG_GPI(GPP_H15, NONE, DEEP),
 		// NC
-		PAD_NC(GPP_H16, NONE),
+		PAD_CFG_GPI(GPP_H16, NONE, DEEP),
 		// NC
-		PAD_NC(GPP_H17, NONE),
+		PAD_CFG_GPI(GPP_H17, NONE, DEEP),
 		// NC
-		PAD_NC(GPP_H18, NONE),
+		PAD_CFG_GPI(GPP_H18, NONE, DEEP),
 
 	// ISH
 		// NC
-		PAD_NC(GPP_H19, NONE),
+		PAD_CFG_GPI(GPP_H19, NONE, DEEP),
 		// NC
-		PAD_NC(GPP_H20, NONE),
+		PAD_CFG_GPI(GPP_H20, NONE, DEEP),
 		// NC
-		PAD_NC(GPP_H21, NONE),
+		PAD_CFG_GPI(GPP_H21, NONE, DEEP),
 		// NC
-		PAD_NC(GPP_H22, NONE),
+		PAD_CFG_GPI(GPP_H22, NONE, DEEP),
 
 	// GPIO
 		// NC
-		PAD_NC(GPP_H23, NONE),
+		PAD_CFG_GPI(GPP_H23, NONE, DEEP),
 
 // GPP_I
 	// Display Signals
 		// NC
-		PAD_NC(GPP_I0, NONE),
+		_PAD_CFG_STRUCT(GPP_I0, 0x40000700, 0x3c00),
 		// HDMI_HPD
-		PAD_CFG_NF(GPP_I1, NATIVE, DEEP, NF1),
+		_PAD_CFG_STRUCT(GPP_I1, 0x40000700, 0x3c00),
 		// NC
-		PAD_NC(GPP_I2, NONE),
+		_PAD_CFG_STRUCT(GPP_I2, 0x40000700, 0x3c00),
 		// MDP_E_HPD
-		PAD_CFG_NF(GPP_I3, NONE, DEEP, NF1),
+		_PAD_CFG_STRUCT(GPP_I3, 0x40000700, 0x0000),
 		// EDP_HPD
-		PAD_CFG_NF(GPP_I4, NONE, DEEP, NF1),
+		_PAD_CFG_STRUCT(GPP_I4, 0x40000700, 0x0000),
 		// NC
-		PAD_NC(GPP_I5, NONE),
+		_PAD_CFG_STRUCT(GPP_I5, 0x40000700, 0x0000),
 		// NC
-		PAD_NC(GPP_I6, NONE),
+		_PAD_CFG_STRUCT(GPP_I6, 0x40000700, 0x0000),
 		// HDMI_CTRLCLK
-		PAD_CFG_NF(GPP_I7, NONE, DEEP, NF1),
+		_PAD_CFG_STRUCT(GPP_I7, 0x40000700, 0x0000),
 		// HDMI_CTRLDATA
-		PAD_CFG_NF(GPP_I8, NONE, DEEP, NF1),
+		_PAD_CFG_STRUCT(GPP_I8, 0x40000700, 0x0000),
 		// NC
-		PAD_NC(GPP_I9, NONE),
+		_PAD_CFG_STRUCT(GPP_I9, 0x40000700, 0x1000),
 		// NC
-		PAD_NC(GPP_I10, NONE),
+		_PAD_CFG_STRUCT(GPP_I10, 0x40000700, 0x1000),
 
 	// PCIE
 		// TODO: H_SKTOCC_N
-		PAD_NC(GPP_I11, NONE),
+		_PAD_CFG_STRUCT(GPP_I11, 0x40000700, 0x3c00),
 		// NC
-		PAD_NC(GPP_I12, NONE),
+		_PAD_CFG_STRUCT(GPP_I12, 0x40000700, 0x3c00),
 		// NC
-		PAD_NC(GPP_I13, NONE),
+		_PAD_CFG_STRUCT(GPP_I13, 0x40000700, 0x3c00),
 		// NC
-		PAD_NC(GPP_I14, NONE),
+		_PAD_CFG_STRUCT(GPP_I14, 0x40000700, 0x3c00),
 
 // GPP_J
 	// CNVI
 		// CNVI_GNSS_PA_BLANKING
-		PAD_CFG_NF(GPP_J0, NATIVE, DEEP, NF1),
+		_PAD_CFG_STRUCT(GPP_J0, 0x40000700, 0x3c00),
 
 	// Power Management
 		// NC
-		PAD_NC(GPP_J1, NONE),
+		_PAD_CFG_STRUCT(GPP_J1, 0x40000700, 0x3c00),
 
 	// GPIO
 		// NC
-		PAD_NC(GPP_J2, NONE),
+		_PAD_CFG_STRUCT(GPP_J2, 0x40000700, 0x3c00),
 		// NC
-		PAD_NC(GPP_J3, NONE),
+		_PAD_CFG_STRUCT(GPP_J3, 0x40000700, 0x3c00),
 
 	// CNVI
 		// CNVI_BRI_DT
-		PAD_CFG_NF(GPP_J4, NATIVE, DEEP, NF1),
+		_PAD_CFG_STRUCT(GPP_J4, 0x40000700, 0x3c00),
 		// CNVI_BRI_RSP
-		PAD_CFG_NF(GPP_J5, NONE, DEEP, NF1),
+		PAD_CFG_GPI(GPP_J5, NONE, DEEP),
 		// CNVI_RGI_DT
 		PAD_CFG_NF(GPP_J6, NONE, PLTRST, NF1),
 		// CNVI_RGI_RSP
 		PAD_CFG_NF(GPP_J7, NONE, DEEP, NF1),
 		// CNVI_MFUART2_RXD
-		PAD_CFG_NF(GPP_J8, NONE, DEEP, NF1),
+		_PAD_CFG_STRUCT(GPP_J8, 0x46880100, 0x0000),
 		// CNVI_MFUART2_TXD
 		PAD_CFG_NF(GPP_J9, NONE, DEEP, NF1),
 
 	// GPIO
 		// NC
-		PAD_NC(GPP_J10, NONE),
+		PAD_CFG_GPI(GPP_J10, NONE, DEEP),
 
 	// A4WP
 		// NC
-		PAD_NC(GPP_J11, NONE),
+		PAD_CFG_GPI(GPP_J11, NONE, DEEP),
 
 // GPP_K
 	// GPIO
@@ -555,23 +568,23 @@ static const struct pad_config gpio_table[] = {
 		// NC
 		PAD_NC(GPP_K2, NONE),
 		// SCI#
-		PAD_CFG_GPI_SCI_LOW(GPP_K3, UP_20K, DEEP, LEVEL),
+		_PAD_CFG_STRUCT(GPP_K3, 0x80880100, 0x3000),
 		// NC
 		PAD_NC(GPP_K4, NONE),
 		// NC
 		PAD_NC(GPP_K5, NONE),
 		// SWI#
-		PAD_CFG_GPI_SCI_LOW(GPP_K6, UP_20K, DEEP, LEVEL),
+		_PAD_CFG_STRUCT(GPP_K6, 0x40880100, 0x3000),
 		// NC
 		PAD_NC(GPP_K7, NONE),
 		// SATA_M2_PWR_EN1
-		PAD_CFG_TERM_GPO(GPP_K8, 1, NONE, DEEP),
+		PAD_CFG_GPI(GPP_K8, NONE, DEEP),
 		// SATA_M2_PWR_EN2
-		PAD_CFG_TERM_GPO(GPP_K9, 1, NONE, DEEP),
+		PAD_CFG_GPI(GPP_K9, NONE, DEEP),
 		// NC
-		PAD_NC(GPP_K10, NONE),
+		PAD_CFG_GPI(GPP_K10, NONE, DEEP),
 		// NC
-		PAD_NC(GPP_K11, NONE),
+		PAD_CFG_GPI(GPP_K11, NONE, DEEP),
 
 	// GSX
 		// NC
@@ -593,26 +606,13 @@ static const struct pad_config gpio_table[] = {
 		// SMI#
 		_PAD_CFG_STRUCT(GPP_K19, 0x42000100, 0x3000),
 		// TODO: GPU_EVENT#
-		PAD_CFG_GPI(GPP_K20, NONE, DEEP),
+		_PAD_CFG_STRUCT(GPP_K20, 0x44000101, 0x0000),
 		// TODO: GC6_FB_EN_PCH
 		PAD_CFG_GPI(GPP_K21, NONE, DEEP),
 		// TODO: DGPU_PWRGD_R
 		_PAD_CFG_STRUCT(GPP_K22, 0x80000100, 0x0000),
 		// NC
-		PAD_NC(GPP_K23, NONE),
+		PAD_CFG_NF(GPP_K23, NONE, DEEP, NF1),
-};
-
-/* Early pad configuration in romstage. */
-static const struct pad_config early_gpio_table[] = {
-	// UART2
-		// UART2_RXD
-		PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),
-		// UART2_TXD
-		PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),
-		// NC
-		PAD_NC(GPP_C22, NONE),
-		// NC
-		PAD_NC(GPP_C23, NONE),
 };
 
 #endif

src/mainboard/system76/cfl-h/variants/gaze14_1660ti_15/hda_verb.c

@@ -1 +1,52 @@
-//TODO
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 System76
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef HDA_VERB_H
+#define HDA_VERB_H
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+	/* Realtek, ALC293 */
+	0x10ec0293, /* Vendor ID */
+	0x15588550, /* Subsystem ID */
+	12, /* Number of entries */
+	AZALIA_SUBVENDOR(0, 0x15588550),
+	AZALIA_PIN_CFG(0, 0x12, 0x90a60130),
+	AZALIA_PIN_CFG(0, 0x13, 0x40000000),
+	AZALIA_PIN_CFG(0, 0x14, 0x90170110),
+	AZALIA_PIN_CFG(0, 0x15, 0x02211020),
+	AZALIA_PIN_CFG(0, 0x16, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x18, 0x02a11040),
+	AZALIA_PIN_CFG(0, 0x19, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1a, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1b, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1d, 0x40738205),
+	AZALIA_PIN_CFG(0, 0x1e, 0x411111f0),
+	/* Intel, KabylakeHDMI */
+	0x8086280b, /* Vendor ID */
+	0x80860101, /* Subsystem ID */
+	4, /* Number of entries */
+	AZALIA_SUBVENDOR(2, 0x80860101),
+	AZALIA_PIN_CFG(2, 0x05, 0x18560010),
+	AZALIA_PIN_CFG(2, 0x06, 0x18560010),
+	AZALIA_PIN_CFG(2, 0x07, 0x18560010),
+};
+
+const u32 pc_beep_verbs[] = {};
+
+AZALIA_ARRAY_SIZES;
+
+#endif

src/mainboard/system76/cfl-h/variants/gaze14_1660ti_15/include/variant/gpio.h

@@ -0,0 +1,271 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 System76
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef MAINBOARD_GPIO_H
+#define MAINBOARD_GPIO_H
+
+#include <soc/gpe.h>
+#include <soc/gpio.h>
+
+#ifndef __ACPI__
+
+/* Early pad configuration in romstage. */
+static const struct pad_config early_gpio_table[] = {
+	// UART2
+		// UART2_RXD
+		PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),
+		// UART2_TXD
+		PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),
+		// NC
+		PAD_NC(GPP_C22, NONE),
+		// NC
+		PAD_NC(GPP_C23, NONE),
+};
+
+/* Pad configuration in ramstage. */
+static const struct pad_config gpio_table[] = {
+		PAD_CFG_NF(GPD0, NONE, DEEP, NF1),
+		PAD_CFG_NF(GPD1, DN_20K, DEEP, NF1),
+		PAD_CFG_GPI(GPD2, DN_20K, PWROK),
+		PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1),
+		PAD_CFG_NF(GPD4, DN_20K, DEEP, NF1),
+		PAD_CFG_NF(GPD5, DN_20K, DEEP, NF1),
+		PAD_CFG_NF(GPD6, DN_20K, DEEP, NF1),
+		PAD_CFG_GPI(GPD7, NONE, PWROK),
+		PAD_CFG_NF(GPD8, DN_20K, DEEP, NF1),
+		PAD_CFG_GPI(GPD9, DN_20K, PWROK),
+		_PAD_CFG_STRUCT(GPD10, 0x04000601, 0x1000),
+		PAD_CFG_TERM_GPO(GPD11, 0, DN_20K, DEEP),
+		PAD_CFG_TERM_GPO(GPP_A0, 0, NONE, DEEP),
+		PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1),
+		PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1),
+		PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1),
+		PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1),
+		PAD_CFG_NF(GPP_A5, DN_20K, DEEP, NF1),
+		PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1),
+		_PAD_CFG_STRUCT(GPP_A7, 0x80100100, 0x0000),
+		PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1),
+		PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1),
+		PAD_CFG_NF(GPP_A10, DN_20K, DEEP, NF1),
+		PAD_CFG_GPI(GPP_A11, UP_20K, DEEP),
+		PAD_CFG_GPI(GPP_A12, NONE, DEEP),
+		PAD_CFG_NF(GPP_A13, DN_20K, DEEP, NF1),
+		PAD_CFG_NF(GPP_A14, DN_20K, DEEP, NF1),
+		PAD_CFG_NF(GPP_A15, UP_20K, DEEP, NF1),
+		_PAD_CFG_STRUCT(GPP_A16, 0x44000101, 0x1000),
+		_PAD_CFG_STRUCT(GPP_A17, 0x44000101, 0x0000),
+		PAD_CFG_TERM_GPO(GPP_A18, 1, NONE, DEEP),
+		PAD_CFG_GPI(GPP_A19, NONE, DEEP),
+		PAD_CFG_GPI(GPP_A20, NONE, DEEP),
+		_PAD_CFG_STRUCT(GPP_A21, 0x44000101, 0x0000),
+		PAD_CFG_TERM_GPO(GPP_A22, 1, NONE, DEEP),
+		PAD_CFG_GPI(GPP_A23, NONE, DEEP),
+		_PAD_CFG_STRUCT(GPP_B0, 0x40000700, 0x0000),
+		PAD_CFG_GPI(GPP_B1, NONE, DEEP),
+		PAD_CFG_TERM_GPO(GPP_B2, 0, NONE, DEEP),
+		PAD_CFG_TERM_GPO(GPP_B3, 0, NONE, DEEP),
+		PAD_CFG_TERM_GPO(GPP_B4, 0, NONE, DEEP),
+		PAD_CFG_TERM_GPO(GPP_B5, 0, UP_20K, DEEP),
+		PAD_CFG_TERM_GPO(GPP_B6, 0, NONE, DEEP),
+		PAD_CFG_TERM_GPO(GPP_B7, 0, NONE, DEEP),
+		PAD_CFG_TERM_GPO(GPP_B8, 0, NONE, DEEP),
+		PAD_CFG_TERM_GPO(GPP_B9, 0, NONE, DEEP),
+		PAD_CFG_TERM_GPO(GPP_B10, 0, NONE, DEEP),
+		PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1),
+		PAD_CFG_TERM_GPO(GPP_B12, 0, NONE, DEEP),
+		_PAD_CFG_STRUCT(GPP_B13, 0x44000601, 0x0000),
+		_PAD_CFG_STRUCT(GPP_B14, 0x44000601, 0x1000),
+		PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1),
+		PAD_CFG_TERM_GPO(GPP_B16, 0, NONE, DEEP),
+		PAD_CFG_TERM_GPO(GPP_B17, 0, NONE, DEEP),
+		PAD_CFG_TERM_GPO(GPP_B18, 0, NONE, DEEP),
+		PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1),
+		PAD_CFG_TERM_GPO(GPP_B20, 0, NONE, DEEP),
+		PAD_CFG_TERM_GPO(GPP_B21, 0, NONE, DEEP),
+		PAD_CFG_TERM_GPO(GPP_B22, 0, NONE, DEEP),
+		PAD_CFG_NF(GPP_B23, NONE, DEEP, NF1),
+		PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
+		PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
+		PAD_CFG_GPI(GPP_C2, NONE, DEEP),
+		PAD_CFG_GPI(GPP_C3, NONE, DEEP),
+		PAD_CFG_GPI(GPP_C4, NONE, DEEP),
+		PAD_CFG_TERM_GPO(GPP_C5, 0, NONE, DEEP),
+		PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1),
+		PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1),
+		PAD_CFG_TERM_GPO(GPP_C8, 0, NONE, DEEP),
+		PAD_CFG_GPI(GPP_C9, NONE, DEEP),
+		PAD_CFG_TERM_GPO(GPP_C10, 0, NONE, DEEP),
+		PAD_CFG_TERM_GPO(GPP_C11, 0, NONE, DEEP),
+		PAD_CFG_TERM_GPO(GPP_C12, 0, NONE, DEEP),
+		PAD_CFG_TERM_GPO(GPP_C13, 0, NONE, DEEP),
+		PAD_CFG_TERM_GPO(GPP_C14, 0, NONE, DEEP),
+		PAD_CFG_TERM_GPO(GPP_C15, 0, NONE, DEEP),
+		PAD_CFG_NF(GPP_C16, NONE, PLTRST, NF1),
+		PAD_CFG_NF(GPP_C17, NONE, PLTRST, NF1),
+		PAD_CFG_NF(GPP_C18, NONE, PLTRST, NF1),
+		PAD_CFG_NF(GPP_C19, NONE, PLTRST, NF1),
+		PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),
+		PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),
+		PAD_CFG_NF(GPP_C22, NONE, DEEP, NF1),
+		PAD_CFG_NF(GPP_C23, NONE, DEEP, NF1),
+		PAD_CFG_TERM_GPO(GPP_D0, 0, NONE, DEEP),
+		PAD_CFG_TERM_GPO(GPP_D1, 0, NONE, DEEP),
+		PAD_CFG_TERM_GPO(GPP_D2, 0, NONE, DEEP),
+		PAD_CFG_TERM_GPO(GPP_D3, 0, NONE, DEEP),
+		PAD_CFG_TERM_GPO(GPP_D4, 0, NONE, DEEP),
+		PAD_CFG_NF(GPP_D5, NONE, DEEP, NF3),
+		PAD_CFG_NF(GPP_D6, NONE, DEEP, NF3),
+		PAD_CFG_TERM_GPO(GPP_D7, 0, NONE, DEEP),
+		PAD_CFG_TERM_GPO(GPP_D8, 0, NONE, DEEP),
+		PAD_CFG_TERM_GPO(GPP_D9, 0, NONE, DEEP),
+		PAD_CFG_TERM_GPO(GPP_D10, 0, NONE, DEEP),
+		PAD_CFG_TERM_GPO(GPP_D11, 0, NONE, DEEP),
+		PAD_CFG_TERM_GPO(GPP_D12, 0, NONE, DEEP),
+		PAD_CFG_TERM_GPO(GPP_D13, 0, NONE, DEEP),
+		PAD_CFG_TERM_GPO(GPP_D14, 0, NONE, DEEP),
+		PAD_CFG_TERM_GPO(GPP_D15, 0, NONE, DEEP),
+		PAD_CFG_TERM_GPO(GPP_D16, 0, NONE, DEEP),
+		PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1),
+		PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1),
+		PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1),
+		PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1),
+		PAD_CFG_TERM_GPO(GPP_D21, 0, NONE, DEEP),
+		PAD_CFG_TERM_GPO(GPP_D22, 0, NONE, DEEP),
+		PAD_CFG_TERM_GPO(GPP_D23, 0, NONE, DEEP),
+		PAD_CFG_GPI(GPP_E0, NONE, DEEP),
+		PAD_CFG_NF(GPP_E1, UP_20K, DEEP, NF1),
+		PAD_CFG_GPI(GPP_E2, NONE, DEEP),
+		PAD_CFG_TERM_GPO(GPP_E3, 0, UP_20K, DEEP),
+		PAD_CFG_TERM_GPO(GPP_E4, 1, NONE, DEEP),
+		PAD_CFG_TERM_GPO(GPP_E5, 0, NONE, DEEP),
+		PAD_CFG_TERM_GPO(GPP_E6, 0, NONE, DEEP),
+		_PAD_CFG_STRUCT(GPP_E7, 0x80800100, 0x0000),
+		PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1),
+		_PAD_CFG_STRUCT(GPP_E9, 0x44000101, 0x3000),
+		_PAD_CFG_STRUCT(GPP_E10, 0x44000501, 0x3000),
+		_PAD_CFG_STRUCT(GPP_E11, 0x44000501, 0x3000),
+		_PAD_CFG_STRUCT(GPP_E12, 0x44000501, 0x3000),
+		PAD_CFG_TERM_GPO(GPP_F0, 0, NONE, DEEP),
+		PAD_CFG_TERM_GPO(GPP_F1, 0, NONE, DEEP),
+		PAD_CFG_TERM_GPO(GPP_F2, 0, NONE, DEEP),
+		PAD_CFG_TERM_GPO(GPP_F3, 0, NONE, DEEP),
+		PAD_CFG_TERM_GPO(GPP_F4, 0, NONE, DEEP),
+		PAD_CFG_GPI(GPP_F5, NONE, DEEP),
+		_PAD_CFG_STRUCT(GPP_F6, 0x44000101, 0x0000),
+		PAD_CFG_TERM_GPO(GPP_F7, 0, NONE, DEEP),
+		PAD_CFG_TERM_GPO(GPP_F8, 1, NONE, DEEP),
+		PAD_CFG_TERM_GPO(GPP_F9, 0, NONE, DEEP),
+		PAD_CFG_GPI(GPP_F10, NONE, DEEP),
+		PAD_CFG_GPI(GPP_F11, NONE, DEEP),
+		PAD_CFG_GPI(GPP_F12, NONE, DEEP),
+		PAD_CFG_GPI(GPP_F13, NONE, DEEP),
+		PAD_CFG_GPI(GPP_F14, NONE, DEEP),
+		_PAD_CFG_STRUCT(GPP_F15, 0x44000501, 0x3000),
+		_PAD_CFG_STRUCT(GPP_F16, 0x44000501, 0x3000),
+		_PAD_CFG_STRUCT(GPP_F17, 0x44000501, 0x3000),
+		_PAD_CFG_STRUCT(GPP_F18, 0x44000501, 0x3000),
+		PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1),
+		PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1),
+		PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1),
+		PAD_CFG_TERM_GPO(GPP_F22, 1, NONE, DEEP),
+		PAD_CFG_TERM_GPO(GPP_F23, 1, NONE, DEEP),
+		PAD_CFG_GPI(GPP_G0, UP_20K, DEEP),
+		PAD_CFG_GPI(GPP_G1, UP_20K, DEEP),
+		PAD_CFG_GPI(GPP_G2, NONE, DEEP),
+		_PAD_CFG_STRUCT(GPP_G3, 0x44000101, 0x0000),
+		PAD_CFG_GPI(GPP_G4, NONE, DEEP),
+		PAD_CFG_TERM_GPO(GPP_G5, 0, NONE, DEEP),
+		PAD_CFG_TERM_GPO(GPP_G6, 0, NONE, DEEP),
+		PAD_CFG_TERM_GPO(GPP_G7, 0, NONE, DEEP),
+		PAD_CFG_NF(GPP_H0, NONE, DEEP, NF1),
+		PAD_CFG_TERM_GPO(GPP_H1, 0, NONE, DEEP),
+		PAD_CFG_NF(GPP_H2, NONE, DEEP, NF1),
+		PAD_CFG_TERM_GPO(GPP_H3, 0, NONE, DEEP),
+		PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
+		PAD_CFG_GPI(GPP_H5, DN_20K, DEEP),
+		PAD_CFG_TERM_GPO(GPP_H6, 0, NONE, DEEP),
+		PAD_CFG_TERM_GPO(GPP_H7, 0, NONE, DEEP),
+		PAD_CFG_TERM_GPO(GPP_H8, 0, NONE, DEEP),
+		PAD_CFG_TERM_GPO(GPP_H9, 0, NONE, DEEP),
+		PAD_CFG_TERM_GPO(GPP_H10, 0, NONE, DEEP),
+		PAD_CFG_TERM_GPO(GPP_H11, 0, NONE, DEEP),
+		PAD_CFG_TERM_GPO(GPP_H12, 0, NONE, DEEP),
+		PAD_CFG_GPI(GPP_H13, NONE, DEEP),
+		PAD_CFG_TERM_GPO(GPP_H14, 0, NONE, DEEP),
+		PAD_CFG_GPI(GPP_H15, NONE, DEEP),
+		PAD_CFG_TERM_GPO(GPP_H16, 0, NONE, DEEP),
+		PAD_CFG_TERM_GPO(GPP_H17, 0, NONE, DEEP),
+		PAD_CFG_TERM_GPO(GPP_H18, 0, NONE, DEEP),
+		PAD_CFG_TERM_GPO(GPP_H19, 0, NONE, DEEP),
+		PAD_CFG_TERM_GPO(GPP_H20, 0, NONE, DEEP),
+		PAD_CFG_TERM_GPO(GPP_H21, 0, NONE, DEEP),
+		PAD_CFG_TERM_GPO(GPP_H22, 0, NONE, DEEP),
+		PAD_CFG_GPI(GPP_H23, UP_20K, DEEP),
+		_PAD_CFG_STRUCT(GPP_I0, 0x40000700, 0x3c00),
+		_PAD_CFG_STRUCT(GPP_I1, 0x40000700, 0x3c00),
+		_PAD_CFG_STRUCT(GPP_I2, 0x40000700, 0x3c00),
+		_PAD_CFG_STRUCT(GPP_I3, 0x40000700, 0x0000),
+		_PAD_CFG_STRUCT(GPP_I4, 0x40000700, 0x0000),
+		_PAD_CFG_STRUCT(GPP_I5, 0x40000700, 0x0000),
+		_PAD_CFG_STRUCT(GPP_I6, 0x40000700, 0x0000),
+		_PAD_CFG_STRUCT(GPP_I7, 0x40000700, 0x0000),
+		_PAD_CFG_STRUCT(GPP_I8, 0x40000700, 0x0000),
+		_PAD_CFG_STRUCT(GPP_I9, 0x40000700, 0x1000),
+		_PAD_CFG_STRUCT(GPP_I10, 0x40000700, 0x1000),
+		_PAD_CFG_STRUCT(GPP_I11, 0x40000700, 0x3c00),
+		_PAD_CFG_STRUCT(GPP_I12, 0x40000700, 0x3c00),
+		_PAD_CFG_STRUCT(GPP_I13, 0x40000700, 0x3c00),
+		_PAD_CFG_STRUCT(GPP_I14, 0x40000700, 0x3c00),
+		_PAD_CFG_STRUCT(GPP_J0, 0x40000700, 0x3c00),
+		_PAD_CFG_STRUCT(GPP_J1, 0x40000700, 0x3c00),
+		_PAD_CFG_STRUCT(GPP_J2, 0x40000700, 0x3c00),
+		_PAD_CFG_STRUCT(GPP_J3, 0x40000700, 0x3c00),
+		_PAD_CFG_STRUCT(GPP_J4, 0x40000700, 0x3c00),
+		PAD_CFG_NF(GPP_J5, NONE, DEEP, NF1),
+		_PAD_CFG_STRUCT(GPP_J6, 0x46880100, 0x0000),
+		PAD_CFG_NF(GPP_J7, NONE, DEEP, NF1),
+		_PAD_CFG_STRUCT(GPP_J8, 0x46880100, 0x0000),
+		PAD_CFG_NF(GPP_J9, NONE, DEEP, NF1),
+		PAD_CFG_NF(GPP_J10, NONE, DEEP, NF1),
+		PAD_CFG_NF(GPP_J11, NONE, DEEP, NF1),
+		PAD_CFG_TERM_GPO(GPP_K0, 0, NONE, DEEP),
+		PAD_CFG_TERM_GPO(GPP_K1, 0, NONE, DEEP),
+		PAD_CFG_TERM_GPO(GPP_K2, 0, NONE, DEEP),
+		_PAD_CFG_STRUCT(GPP_K3, 0x40880100, 0x0000),
+		PAD_CFG_TERM_GPO(GPP_K4, 0, NONE, DEEP),
+		PAD_CFG_TERM_GPO(GPP_K5, 0, NONE, DEEP),
+		_PAD_CFG_STRUCT(GPP_K6, 0x40880100, 0x0000),
+		PAD_CFG_TERM_GPO(GPP_K7, 0, NONE, DEEP),
+		PAD_CFG_TERM_GPO(GPP_K8, 1, NONE, DEEP),
+		PAD_CFG_TERM_GPO(GPP_K9, 1, NONE, DEEP),
+		PAD_CFG_TERM_GPO(GPP_K10, 0, NONE, DEEP),
+		PAD_CFG_TERM_GPO(GPP_K11, 0, NONE, DEEP),
+		PAD_CFG_TERM_GPO(GPP_K12, 0, NONE, DEEP),
+		PAD_CFG_TERM_GPO(GPP_K13, 0, NONE, DEEP),
+		PAD_CFG_TERM_GPO(GPP_K14, 0, NONE, DEEP),
+		PAD_CFG_TERM_GPO(GPP_K15, 0, NONE, DEEP),
+		PAD_CFG_TERM_GPO(GPP_K16, 0, NONE, DEEP),
+		PAD_CFG_TERM_GPO(GPP_K17, 0, NONE, DEEP),
+		PAD_CFG_TERM_GPO(GPP_K18, 0, NONE, DEEP),
+		_PAD_CFG_STRUCT(GPP_K19, 0x42800101, 0x0000),
+		PAD_CFG_TERM_GPO(GPP_K20, 1, NONE, DEEP),
+		PAD_CFG_GPI(GPP_K21, NONE, DEEP),
+		_PAD_CFG_STRUCT(GPP_K22, 0x44000101, 0x0000),
+		PAD_CFG_TERM_GPO(GPP_K23, 1, NONE, DEEP),
+};
+
+#endif
+
+#endif

src/mainboard/system76/cfl-h/variants/gaze14_1660ti_17/hda_verb.c

@@ -1 +1,52 @@
-//TODO
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 System76
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef HDA_VERB_H
+#define HDA_VERB_H
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+	/* Realtek, ALC293 */
+	0x10ec0293, /* Vendor ID */
+	0x15588551, /* Subsystem ID */
+	12, /* Number of entries */
+	AZALIA_SUBVENDOR(0, 0x15588550),
+	AZALIA_PIN_CFG(0, 0x12, 0x90a60130),
+	AZALIA_PIN_CFG(0, 0x13, 0x40000000),
+	AZALIA_PIN_CFG(0, 0x14, 0x90170110),
+	AZALIA_PIN_CFG(0, 0x15, 0x02211020),
+	AZALIA_PIN_CFG(0, 0x16, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x18, 0x02a11040),
+	AZALIA_PIN_CFG(0, 0x19, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1a, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1b, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1d, 0x40738205),
+	AZALIA_PIN_CFG(0, 0x1e, 0x411111f0),
+	/* Intel, KabylakeHDMI */
+	0x8086280b, /* Vendor ID */
+	0x80860101, /* Subsystem ID */
+	4, /* Number of entries */
+	AZALIA_SUBVENDOR(2, 0x80860101),
+	AZALIA_PIN_CFG(2, 0x05, 0x18560010),
+	AZALIA_PIN_CFG(2, 0x06, 0x18560010),
+	AZALIA_PIN_CFG(2, 0x07, 0x18560010),
+};
+
+const u32 pc_beep_verbs[] = {};
+
+AZALIA_ARRAY_SIZES;
+
+#endif