- Fix config.g and the hdama config so everthing builds again.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1680 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Eric Biederman
@@ -67,7 +67,8 @@ struct device {
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unsigned long rom_address;
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struct device_operations *ops;
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struct chip *chip;
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struct chip_control *chip_control;
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void *chip_info;
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};
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extern struct device dev_root; /* root bus */
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@@ -9,11 +9,17 @@ enum device_path_type {
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DEVICE_PATH_PNP,
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DEVICE_PATH_I2C,
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DEVICE_PATH_APIC,
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DEVICE_PATH_PCI_DOMAIN,
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DEVICE_APIC_CLUSTER,
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};
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struct pci_domain_path
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{
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unsigned domain;
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};
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struct pci_path
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{
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unsigned bus;
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unsigned devfn;
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};
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@@ -33,13 +39,21 @@ struct apic_path
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unsigned apic_id;
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};
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struct apic_cluster_path
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{
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unsigned cluster;
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};
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struct device_path {
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enum device_path_type type;
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union {
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struct pci_path pci;
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struct pnp_path pnp;
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struct i2c_path i2c;
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struct apic_path apic;
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struct pci_path pci;
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struct pnp_path pnp;
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struct i2c_path i2c;
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struct apic_path apic;
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struct pci_domain_path pci_domain;
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struct apic_cluster_path apic_cluster;
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} u;
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};
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@@ -16,7 +16,6 @@ end
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##
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default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
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default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
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default CONFIG_ROM_STREAM = 1
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##
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## Compute where this copy of linuxBIOS will start in the boot rom
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@@ -33,72 +32,216 @@ default _ROMBASE = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE )
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default XIP_ROM_SIZE=65536
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default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
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arch i386 end
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##
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## Build the objects we have code for in this directory.
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##
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driver mainboard.o
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if HAVE_MP_TABLE object mptable.o end
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if HAVE_PIRQ_TABLE object irq_tables.o end
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#object reset.o
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##
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## Romcc output
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##
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makerule ./failover.E
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depends "$(MAINBOARD)/failover.c"
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action "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/failover.c > ./failover.E"
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end
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makerule ./failover.inc
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depends "./failover.E ./romcc"
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action "./romcc -O -o failover.inc --label-prefix=failover ./failover.E"
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end
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makerule ./auto.E
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depends "$(MAINBOARD)/auto.c option_table.h "
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action "$(CPP) -I$(TOP)/src -I. $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/auto.c > ./auto.E"
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end
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makerule ./auto.inc
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depends "./auto.E ./romcc"
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action "./romcc -mcpu=k8 -O2 ./auto.E > auto.inc"
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end
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##
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## Build our 16 bit and 32 bit linuxBIOS entry code
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##
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mainboardinit cpu/x86/16bit/entry16.inc
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mainboardinit cpu/x86/32bit/entry32.inc
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ldscript /cpu/x86/16bit/entry16.lds
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ldscript /cpu/x86/32bit/entry32.lds
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##
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## Build our reset vector (This is where linuxBIOS is entered)
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##
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if USE_FALLBACK_IMAGE
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mainboardinit cpu/x86/16bit/reset16.inc
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ldscript /cpu/x86/16bit/reset16.lds
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else
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mainboardinit cpu/x86/32bit/reset32.inc
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ldscript /cpu/x86/32bit/reset32.lds
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end
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### Should this be in the northbridge code?
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mainboardinit arch/i386/lib/cpu_reset.inc
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##
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## Include an id string (For safe flashing)
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##
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mainboardinit arch/i386/lib/id.inc
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ldscript /arch/i386/lib/id.lds
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###
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### This is the early phase of linuxBIOS startup
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### Things are delicate and we test to see if we should
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### failover to another image.
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###
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if USE_FALLBACK_IMAGE
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ldscript /arch/i386/lib/failover.lds
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mainboardinit ./failover.inc
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end
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###
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### O.k. We aren't just an intermediary anymore!
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###
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##
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## Setup RAM
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##
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mainboardinit cpu/x86/fpu/enable_fpu.inc
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mainboardinit cpu/x86/mmx/enable_mmx.inc
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mainboardinit cpu/x86/sse/enable_sse.inc
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mainboardinit ./auto.inc
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mainboardinit cpu/x86/sse/disable_sse.inc
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mainboardinit cpu/x86/mmx/disable_mmx.inc
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##
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## Include the secondary Configuration files
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##
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dir /pc80
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config chip.h
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# sample config for arima/hdama
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chip northbridge/amd/amdk8
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print "HI MOM!\n"
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device pnp cf8.0 on # cf8 config
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print "HI MOM!\n"
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device pci 18.0 on # northbridge
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print "HI MOM!\n"
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device pci_domain 0 on
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device pci 18.0 on # northbridge
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# devices on link 0, link 0 == LDT 0
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chip southbridge/amd/amd8131
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print "SOUTH\n"
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# the on/off keyword is mandatory
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device pci 0.0 on end
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print "SOUTH2\n"
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device pci 0.1 on end
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print "SOUTH3\n"
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device pci 1.0 on end
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print "SOUTH4\n"
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device pci 1.1 on end
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end
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chip southbridge/amd/amd8111
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print "NEXT SOUTH\n"
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# this "device pci 0.0" is the parent the next one
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# PCI bridge
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device pci 0.0 on
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# this "device pci 0.0" is a child of the
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# previous one
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# devices behind the bridge
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device pci 0.0 on end
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device pci 0.1 on end
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device pci 0.2 on end
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# the device statement can span across multiple
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# lines too
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device pci 1.0
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off
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end
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device pci 1.0 off end
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end
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device pci 1.0 on
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chip superio/NSC/pc87360
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device pnp 2e.3 on
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io 0x60 = 0x3f8
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device pnp 2e.0 off # Floppy
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io 0x60 = 0x3f0
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irq 0x70 = 6
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drq 0x74 = 2
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end
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device pnp 2e.1 off # Parallel Port
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io 0x60 = 0x378
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irq 0x70 = 7
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end
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device pnp 2e.2 off # Com 2
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io 0x60 = 0x2f8
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irq 0x70 = 3
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end
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device pnp 2e.3 on # Com 1
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io 0x60 = 0x3f8
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irq 0x70 = 4
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end
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end
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device pnp 2e.4 off end # SWC
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device pnp 2e.5 off end # Mouse
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device pnp 2e.6 on # Keyboard
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io 0x60 = 0x60
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io 0x62 = 0x64
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irq 0x70 = 1
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end
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device pnp 2e.7 off end # GPIO
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device pnp 2e.8 off end # ACB
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device pnp 2e.9 off end # FSCM
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device pnp 2e.a off end # WDT
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end
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end
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device pci 1.1 on end
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device pci 1.2 off end
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device pci 1.3 off end
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device pci 1.5 on end
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device pci 1.2 on end
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device pci 1.3 on
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chip drivers/generic/generic
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#phillips pca9545 smbus mux
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device i2c 70 on end
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# analog_devices adm1026
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chip drivers/generic/generic
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device i2c 2c on end
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end
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device i2c 70 on end
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device i2c 70 on end
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device i2c 70 on end
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end
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chip drivers/generic/generic link 4 #dimm 0-0-0
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device i2c 50 on end
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end
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chip drivers/generic/generic link 4 #dimm 0-0-1
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device i2c 51 on end
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end
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chip drivers/generic/generic link 4 #dimm 0-1-0
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device i2c 52 on end
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end
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chip drivers/generic/generic link 4 #dimm 0-1-1
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device i2c 53 on end
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end
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chip drivers/generic/generic link 4 #dimm 1-0-0
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device i2c 54 on end
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end
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chip drivers/generic/generic link 4 #dimm 1-0-1
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device i2c 55 on end
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end
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chip drivers/generic/generic link 4 #dimm 1-1-0
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device i2c 56 on end
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end
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chip drivers/generic/generic link 4 #dimm 1-1-1
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device i2c 57 on end
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end
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end
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device pci 1.5 off end
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device pci 1.6 on end
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end
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end # device pci 18.0
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device pci 18.0 on
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# some non-existence devices on link 1
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device pci 18.0 on end # LDT1
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device pci 18.0 on end # LDT2
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device pci 18.1 on end
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device pci 18.2 on end
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device pci 18.3 on end
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chip northbridge/amd/amdk8
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device pci 19.0 on end
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device pci 19.0 on end
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device pci 19.0 on end
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device pci 19.1 on end
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device pci 19.2 on end
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device pci 19.3 on end
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end
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device pci 18.0 on
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# some non-existence devices on link 2
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end
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device apic_cluster 0 on
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chip cpu/amd/socket_940
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device apic 0 on end
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end
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device pci 18.1
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# empty
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chip cpu/amd/socket_940
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device apic 1 on end
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end
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device pci 18.2
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# empty
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end
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device pci 18.3
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# empty
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end
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end # device pnp
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end
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end
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@@ -53,6 +53,9 @@ default HAVE_FALLBACK_BOOT=1
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##
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default HAVE_HARD_RESET=1
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##
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## Funky hard reset implementation
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##
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default HARD_RESET_BUS=1
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default HARD_RESET_DEVICE=4
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default HARD_RESET_FUNCTION=0
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@@ -121,4 +124,11 @@ default HEAP_SIZE=0x4000
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##
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default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
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default _RAMBASE=0x00004000
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##
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## Load the payload from the ROM
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##
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default CONFIG_ROM_STREAM = 1
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end
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